From KokHow.Teh@infineon.com Tue Jul 1 07:05:28 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jul 2008 07:05:35 +0100 (BST) Received: from smtp3.infineon.com ([203.126.106.229]:10290 "EHLO smtp3.infineon.com") by ftp.linux-mips.org with ESMTP id S29047646AbYGAGF2 convert rfc822-to-8bit (ORCPT ); Tue, 1 Jul 2008 07:05:28 +0100 X-SBRS: None Received: from unknown (HELO sinse301.ap.infineon.com) ([172.20.70.22]) by smtp3.infineon.com with ESMTP; 01 Jul 2008 14:05:19 +0800 Received: from sinse303.ap.infineon.com ([172.20.70.24]) by sinse301.ap.infineon.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.1830); Tue, 1 Jul 2008 14:05:18 +0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Kmem_cache handling in linux-2.6.2x kernel. Date: Tue, 1 Jul 2008 14:05:17 +0800 Message-ID: <31E09F73562D7A4D82119D7F6C172986045B6E80@sinse303.ap.infineon.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Kmem_cache handling in linux-2.6.2x kernel. Thread-Index: AcjbQCezWLXpXWxBSj2JrUNDAJRvkw== From: To: , Cc: X-OriginalArrivalTime: 01 Jul 2008 06:05:18.0988 (UTC) FILETIME=[706164C0:01C8DB40] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19677 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: KokHow.Teh@infineon.com Precedence: bulk X-list: linux-mips Content-Length: 1430 Lines: 26 Hi list; I have a question about kmem_cache implemented in Linux-2.6.2x kernel. I have an application that allocates and free 64KByte chunks of memory (32-byte aligned) quite often. Therefore, I create a lookaside cache for that purpose and use kmem_cache_alloc(), kmem_cache_free() to allocate and free the caches. The application works very well in this model. However, my concern here is if kmem_cache_free() does return the cache to the system-wide pool so that it could be used by other applications when need arises; when system is low in memory resources, for instance. This is a question about the internal workings of the memory management system of the Linux-2.6.2x kernel as to how efficient it manages this lookasie caches. The concern is valid because if this lookaside cache is not managed well, i.e, it is not returned to the system-wide pool of free memory pools to be used by other applications, this will penalize the performace and throughput of the whole system due to the dynamic behaviour of the utilization of system memory resources. For example, other applications might be swapping in and out of the harddisk and if the kmem_cache_free()'ed memory objects could be used by these applications, it will help in this case to reduce the number of swaps that happen, thereby freeing the CPU and/or DMA from doing the swapping to do other critical tasks. Any insight and advice is appreciated. Regards, KH From nschichan@freebox.fr Tue Jul 1 14:42:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jul 2008 14:42:44 +0100 (BST) Received: from bobafett.staff.proxad.net ([213.228.1.121]:20421 "EHLO bobafett.staff.proxad.net") by ftp.linux-mips.org with ESMTP id S30613934AbYGANmh (ORCPT ); Tue, 1 Jul 2008 14:42:37 +0100 Received: from localhost (localhost [127.0.0.1]) by bobafett.staff.proxad.net (Postfix) with ESMTP id CE5302AE93; Tue, 1 Jul 2008 15:42:30 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at staff.proxad.net Received: from bobafett.staff.proxad.net ([127.0.0.1]) by localhost (bobafett.staff.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with LMTP id wyuBsemcEl1S; Tue, 1 Jul 2008 15:42:29 +0200 (CEST) Received: from nschichan.priv.staff.proxad.net (nschichan.priv.staff.proxad.net [172.18.3.120]) by bobafett.staff.proxad.net (Postfix) with ESMTP id A42192AE47; Tue, 1 Jul 2008 15:42:29 +0200 (CEST) From: Nicolas Schichan Organization: Freebox To: Tomasz Chmielewski Subject: Re: kexec on mips - anyone has it working? Date: Tue, 1 Jul 2008 15:42:28 +0200 User-Agent: KMail/1.9.6 (enterprise 0.20070907.709405) Cc: linux-mips@linux-mips.org, Kexec Mailing List , openwrt-devel@lists.openwrt.org References: <483BCB75.4050901@wpkg.org> <200805301327.11925.nschichan@freebox.fr> <483FE764.1090901@wpkg.org> In-Reply-To: <483FE764.1090901@wpkg.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200807011542.29274.nschichan@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19678 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nschichan@freebox.fr Precedence: bulk X-list: linux-mips Content-Length: 1279 Lines: 47 On Friday 30 May 2008 13:39:16 Tomasz Chmielewski wrote: Hello, > Nicolas Schichan schrieb: > > On Thursday 29 May 2008 22:15:47 Tomasz Chmielewski wrote: > >> Will call new kernel at 00305000 > > > > The calling address of the kernel looks quite wrong, it should clearly > > be inside the KSEG0 zone. could you please indicate the output of the > > command "mips-linux-readelf -l vmlinux" ? > > # uname -m > mips > # readelf -l vmlinux > > Elf file type is EXEC (Executable file) > Entry point 0x80251b50 This is quite surprising. The jump address that kexec will use is cleary not what I expected. I would have expected it to be the Entry point address given by readelf. could you try the following patch to make sure that the kimage* structure is not corrupted by the code in machine_kexec() ? Index: linux/arch/mips/kernel/machine_kexec.c =================================================================== --- linux/arch/mips/kernel/machine_kexec.c (revision 8056) +++ linux/arch/mips/kernel/machine_kexec.c (working copy) @@ -49,6 +49,8 @@ unsigned long entry; unsigned long *ptr; + printk("image->start = %p", image->start); + reboot_code_buffer = (unsigned long)page_address(image->control_code_page); Regards, -- Nicolas Schichan From mangoo@wpkg.org Tue Jul 1 18:53:34 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jul 2008 18:53:41 +0100 (BST) Received: from mx03.syneticon.net ([87.79.32.166]:22534 "EHLO mx03.syneticon.net") by ftp.linux-mips.org with ESMTP id S32704464AbYGARxe (ORCPT ); Tue, 1 Jul 2008 18:53:34 +0100 Received: from localhost (filter1.syneticon.net [192.168.113.3]) by mx03.syneticon.net (Postfix) with ESMTP id 22DC29601; Tue, 1 Jul 2008 19:53:33 +0200 (CEST) X-Virus-Scanned: amavisd-new at mx03.syneticon.net Received: from mx03.syneticon.net ([192.168.113.4]) by localhost (mx03.syneticon.net [192.168.113.3]) (amavisd-new, port 10025) with ESMTP id py1CEgWu3J7t; Tue, 1 Jul 2008 19:53:19 +0200 (CEST) Received: from [192.168.10.145] (koln-4d0b69d5.pool.mediaWays.net [77.11.105.213]) by mx03.syneticon.net (Postfix) with ESMTP; Tue, 1 Jul 2008 19:53:19 +0200 (CEST) Message-ID: <486A6F0D.4070802@wpkg.org> Date: Tue, 01 Jul 2008 19:53:17 +0200 From: Tomasz Chmielewski User-Agent: Thunderbird 2.0.0.12 (X11/20080305) MIME-Version: 1.0 To: Nicolas Schichan CC: linux-mips@linux-mips.org, Kexec Mailing List , openwrt-devel@lists.openwrt.org Subject: Re: kexec on mips - anyone has it working? References: <483BCB75.4050901@wpkg.org> <200805301327.11925.nschichan@freebox.fr> <483FE764.1090901@wpkg.org> <200807011542.29274.nschichan@freebox.fr> In-Reply-To: <200807011542.29274.nschichan@freebox.fr> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19679 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mangoo@wpkg.org Precedence: bulk X-list: linux-mips Content-Length: 1832 Lines: 55 Nicolas Schichan schrieb: > On Friday 30 May 2008 13:39:16 Tomasz Chmielewski wrote: > > Hello, > >> Nicolas Schichan schrieb: >>> On Thursday 29 May 2008 22:15:47 Tomasz Chmielewski wrote: >>>> Will call new kernel at 00305000 >>> The calling address of the kernel looks quite wrong, it should clearly >>> be inside the KSEG0 zone. could you please indicate the output of the >>> command "mips-linux-readelf -l vmlinux" ? >> # uname -m >> mips >> # readelf -l vmlinux >> >> Elf file type is EXEC (Executable file) >> Entry point 0x80251b50 > > This is quite surprising. The jump address that kexec will use is > cleary not what I expected. I would have expected it to be the Entry > point address given by readelf. > > could you try the following patch to make sure that the kimage* > structure is not corrupted by the code in machine_kexec() ? > > Index: linux/arch/mips/kernel/machine_kexec.c > =================================================================== > --- linux/arch/mips/kernel/machine_kexec.c (revision 8056) > +++ linux/arch/mips/kernel/machine_kexec.c (working copy) > @@ -49,6 +49,8 @@ > unsigned long entry; > unsigned long *ptr; > > + printk("image->start = %p", image->start); > + > reboot_code_buffer = > (unsigned long)page_address(image->control_code_page); Umm? CC arch/mips/kernel/machine_kexec.o cc1: warnings being treated as errors arch/mips/kernel/machine_kexec.c: In function 'machine_kexec': arch/mips/kernel/machine_kexec.c:52: warning: format '%p' expects type 'void *', but argument 2 has type 'long unsigned int' make[6]: *** [arch/mips/kernel/machine_kexec.o] Error 1 make[5]: *** [arch/mips/kernel] Error 2 make[5]: Leaving directory `/home/tch-data/openwrt/11612/build_dir/linux-brcm47xx/linux-2.6.25.9' -- Tomasz Chmielewski http://wpkg.org From nschichan@freebox.fr Tue Jul 1 19:00:50 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jul 2008 19:00:56 +0100 (BST) Received: from bobafett.staff.proxad.net ([213.228.1.121]:28634 "EHLO bobafett.staff.proxad.net") by ftp.linux-mips.org with ESMTP id S32705264AbYGASAu (ORCPT ); Tue, 1 Jul 2008 19:00:50 +0100 Received: from localhost (localhost [127.0.0.1]) by bobafett.staff.proxad.net (Postfix) with ESMTP id A879F2780D; Tue, 1 Jul 2008 20:00:41 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at staff.proxad.net Received: from bobafett.staff.proxad.net ([127.0.0.1]) by localhost (bobafett.staff.proxad.net [127.0.0.1]) (amavisd-new, port 10024) with LMTP id RtqeFE0FbOl5; Tue, 1 Jul 2008 20:00:40 +0200 (CEST) Received: from nschichan.priv.staff.proxad.net (nschichan.priv.staff.proxad.net [172.18.3.120]) by bobafett.staff.proxad.net (Postfix) with ESMTP id 9BA7943BE; Tue, 1 Jul 2008 20:00:40 +0200 (CEST) From: Nicolas Schichan Organization: Freebox To: kexec@lists.infradead.org Subject: Re: kexec on mips - anyone has it working? Date: Tue, 1 Jul 2008 20:00:40 +0200 User-Agent: KMail/1.9.6 (enterprise 0.20070907.709405) Cc: Tomasz Chmielewski , linux-mips@linux-mips.org References: <483BCB75.4050901@wpkg.org> <200807011542.29274.nschichan@freebox.fr> <486A6F0D.4070802@wpkg.org> In-Reply-To: <486A6F0D.4070802@wpkg.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200807012000.40421.nschichan@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19680 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nschichan@freebox.fr Precedence: bulk X-list: linux-mips Content-Length: 1603 Lines: 50 On Tuesday 01 July 2008 19:53:17 Tomasz Chmielewski wrote: > > Index: linux/arch/mips/kernel/machine_kexec.c > > =================================================================== > > --- linux/arch/mips/kernel/machine_kexec.c (revision 8056) > > +++ linux/arch/mips/kernel/machine_kexec.c (working copy) > > @@ -49,6 +49,8 @@ > > unsigned long entry; > > unsigned long *ptr; > > > > + printk("image->start = %p", image->start); > > + > > reboot_code_buffer = > > (unsigned long)page_address(image->control_code_page); > > Umm? > > CC arch/mips/kernel/machine_kexec.o > cc1: warnings being treated as errors > arch/mips/kernel/machine_kexec.c: In function 'machine_kexec': > arch/mips/kernel/machine_kexec.c:52: warning: format '%p' expects type > 'void *', but argument 2 has type 'long unsigned int' > make[6]: *** [arch/mips/kernel/machine_kexec.o] Error 1 > make[5]: *** [arch/mips/kernel] Error 2 > make[5]: Leaving directory > `/home/tch-data/openwrt/11612/build_dir/linux-brcm47xx/linux-2.6.25.9' -Werror is missing from my kernel cflags. Try this one, %lx will accept unsigned long parameters without warnings: Index: linux/arch/mips/kernel/machine_kexec.c =================================================================== --- linux/arch/mips/kernel/machine_kexec.c (revision 8056) +++ linux/arch/mips/kernel/machine_kexec.c (working copy) @@ -49,6 +49,8 @@ unsigned long entry; unsigned long *ptr; + printk("image->start = %lx", image->start); + reboot_code_buffer = (unsigned long)page_address(image->control_code_page); Regards, -- Nicolas Schichan From mangoo@wpkg.org Tue Jul 1 19:21:35 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jul 2008 19:21:42 +0100 (BST) Received: from mx03.syneticon.net ([87.79.32.166]:56836 "EHLO mx03.syneticon.net") by ftp.linux-mips.org with ESMTP id S32706994AbYGASVf (ORCPT ); Tue, 1 Jul 2008 19:21:35 +0100 Received: from localhost (filter1.syneticon.net [192.168.113.3]) by mx03.syneticon.net (Postfix) with ESMTP id 5AEB29601; Tue, 1 Jul 2008 20:21:34 +0200 (CEST) X-Virus-Scanned: amavisd-new at mx03.syneticon.net Received: from mx03.syneticon.net ([192.168.113.4]) by localhost (mx03.syneticon.net [192.168.113.3]) (amavisd-new, port 10025) with ESMTP id BRg5Zo+0PuhB; Tue, 1 Jul 2008 20:21:19 +0200 (CEST) Received: from [192.168.10.145] (koln-4d0b69d5.pool.mediaWays.net [77.11.105.213]) by mx03.syneticon.net (Postfix) with ESMTP; Tue, 1 Jul 2008 20:21:19 +0200 (CEST) Message-ID: <486A759D.6080803@wpkg.org> Date: Tue, 01 Jul 2008 20:21:17 +0200 From: Tomasz Chmielewski User-Agent: Thunderbird 2.0.0.12 (X11/20080305) MIME-Version: 1.0 To: Nicolas Schichan CC: kexec@lists.infradead.org, linux-mips@linux-mips.org Subject: Re: kexec on mips - anyone has it working? References: <483BCB75.4050901@wpkg.org> <200807011542.29274.nschichan@freebox.fr> <486A6F0D.4070802@wpkg.org> <200807012000.40421.nschichan@freebox.fr> In-Reply-To: <200807012000.40421.nschichan@freebox.fr> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19681 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mangoo@wpkg.org Precedence: bulk X-list: linux-mips Content-Length: 330 Lines: 18 Nicolas Schichan schrieb: > + printk("image->start = %lx", image->start); > + > reboot_code_buffer = > (unsigned long)page_address(image->control_code_page); # kexec -e b44: eth0: powering down PHY Starting new kernel image->start = 304000Will call new kernel at 00304000 Bye ... -- Tomasz Chmielewski http://wpkg.org From mangoo@wpkg.org Tue Jul 1 19:25:56 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jul 2008 19:26:03 +0100 (BST) Received: from mx03.syneticon.net ([87.79.32.166]:31501 "EHLO mx03.syneticon.net") by ftp.linux-mips.org with ESMTP id S32707294AbYGASZ4 (ORCPT ); Tue, 1 Jul 2008 19:25:56 +0100 Received: from localhost (filter1.syneticon.net [192.168.113.3]) by mx03.syneticon.net (Postfix) with ESMTP id 3B98F9601; Tue, 1 Jul 2008 20:25:55 +0200 (CEST) X-Virus-Scanned: amavisd-new at mx03.syneticon.net Received: from mx03.syneticon.net ([192.168.113.4]) by localhost (mx03.syneticon.net [192.168.113.3]) (amavisd-new, port 10025) with ESMTP id IVzukLrygtvA; Tue, 1 Jul 2008 20:25:52 +0200 (CEST) Received: from [192.168.10.145] (koln-4d0b69d5.pool.mediaWays.net [77.11.105.213]) by mx03.syneticon.net (Postfix) with ESMTP; Tue, 1 Jul 2008 20:25:52 +0200 (CEST) Message-ID: <486A76AF.9080109@wpkg.org> Date: Tue, 01 Jul 2008 20:25:51 +0200 From: Tomasz Chmielewski User-Agent: Thunderbird 2.0.0.12 (X11/20080305) MIME-Version: 1.0 To: Nicolas Schichan CC: kexec@lists.infradead.org, linux-mips@linux-mips.org Subject: Re: kexec on mips - anyone has it working? References: <483BCB75.4050901@wpkg.org> <200807011542.29274.nschichan@freebox.fr> <486A6F0D.4070802@wpkg.org> <200807012000.40421.nschichan@freebox.fr> In-Reply-To: <200807012000.40421.nschichan@freebox.fr> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19682 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mangoo@wpkg.org Precedence: bulk X-list: linux-mips Content-Length: 350 Lines: 21 Nicolas Schichan schrieb: (...) > + printk("image->start = %lx", image->start); > + And this is what happens if I use your "util.c for kexec-userland" - why does it use a different address? # /root/kexec-test/kexec -r Starting new kernel image->start = 802520d0Will call new kernel at 802520d0 Bye ... -- Tomasz Chmielewski http://wpkg.org From drow@false.org Tue Jul 1 21:22:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jul 2008 21:22:56 +0100 (BST) Received: from NaN.false.org ([208.75.86.248]:48332 "EHLO nan.false.org") by ftp.linux-mips.org with ESMTP id S32713250AbYGAUWr (ORCPT ); Tue, 1 Jul 2008 21:22:47 +0100 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 1F02198243; Tue, 1 Jul 2008 20:22:43 +0000 (GMT) Received: from caradoc.them.org (22.svnf5.xdsl.nauticom.net [209.195.183.55]) by nan.false.org (Postfix) with ESMTP id 0D6CF9809F; Tue, 1 Jul 2008 20:22:41 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.69) (envelope-from ) id 1KDmN5-0006pV-UM; Tue, 01 Jul 2008 16:22:40 -0400 Date: Tue, 1 Jul 2008 16:22:37 -0400 From: Daniel Jacobowitz To: binutils@sourceware.org, gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Subject: Re: RFC: Adding non-PIC executable support to MIPS Message-ID: <20080701202236.GA1534@caradoc.them.org> Mail-Followup-To: binutils@sourceware.org, gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com References: <87y74pxwyl.fsf@firetop.home> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="vtzGhvizbBRQ85DL" Content-Disposition: inline In-Reply-To: <87y74pxwyl.fsf@firetop.home> User-Agent: Mutt/1.5.17 (2008-05-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19683 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@debian.org Precedence: bulk X-list: linux-mips Content-Length: 200044 Lines: 5591 --vtzGhvizbBRQ85DL Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sat, Jun 28, 2008 at 06:58:58PM +0100, Richard Sandiford wrote: > used on GNU/Linux. At the same time, CodeSourcery implemented it for > Sourcery G++. I only found out about CS's version recently, after > finishing the Specifix one, and I think the same is true in reverse. > Oh well! Yes, that's right - first I heard about this was last week :-( > I suppose the good news is that we can pick the best bits of each > implementation as the official one. I'll describe my implementation > below, then compare it to what I understand CS's version to be. > CS folks: please correct me if I'm wrong. Dan said that he'd be > submitting CS's version too. Indeed, and here it is. I have attached patches for gcc, binutils, gdb, glibc (EGLIBC trunk but likely to apply fine to FSF GLIBC also), and glibc-ports (ditto). There's also a build fix for EGLIBC after Richard's recent change to the "h" constraint (similar to the one in Richard's eglibc quilt). I have also included the ABI writeup we used. Changelogs are missing for the binutils/gcc patches. The patches were written by Mark Shinwell, Catherine Moore, and myself. The ABI document was originally written by Nigel Stephens of MIPS Technologies, Inc., who sponsored this project; I've updated it as we went along. Richard, Nigel, and I discussed a version of this document in 2007; it has changed slightly. I've had to do some last minute updates to it today to match the implementation, so I sincerely hope I got them right. Most descripions of Richard's implementation also apply to ours. It is compatible with both existing ET_REL objects and existing ET_EXEC/ET_DYN modules. Old binaries continue to work with a patched C library, existing static libraries can still be used by the new linker, et cetera. > Comparison with the CS implementation > ------------------------------------- Some similarities first: R_MIPS_COPY / R_MIPS_JUMP_SLOT, STO_MIPS_PLT, EF_MIPS_CPIC, use of .option pic0, the need for linker errors on non-PIC, the grotty glibc hack to make it check STO_MIPS_PLT (Richard's duplicates more code, but is considerably less grotty; had we realized we'd be stuck with a copy of dl-lookup.c I would likely not have written the awful preprocessor trick you'll see in the ports patch). > I think the main differences with CS's implemention are: > > - CS treat .got.plt is part of .got. See above for why I think it > should be separate. Note that the PLT header is the same size for > both implementations, so the extra parameters don't cost much. No, we don't - they're on opposite sides of .data. We reserve two words at the start of the PLT GOT in addition to the two at the beginning of the GOT. The PLT header loads the start of .got.plt and passes that to _dl_runtime_pltresolve in $gp. The return address is passed in $t9 and the index in $t8. > - CS PLT entries pass a PLT index rather than a .got.plt address. > This makes no difference for most objects, but a longer stub > is needed if there are more than 0x10000 PLT entries. Yes, this was chosen in order to support MIPS I while still fitting the PLT entries on a single cache line. > - I couldn't see any specific support for ld -r in the CS version. That's right, we do not support this. I've no complaint about gaining support :-) Given the requirement, STO_MIPS_PIC seems sensible. > - The CS version always uses separate "la $25" trampolines, > rather than adding instructions to the beginning of a function. > This is an implementation rather than an ABI detail though. Right. > - CS support MIPS I, at the cost of using the start of the next > PLT entry as a delay slot instruction. FWIW it also adds one instruction to the header; that's why the delay slot of the branch is empty. > - STO_MIPS_PLT is separate from STO_MIPS16. Right. > This comparison is based on 4.2-129 and I've probably got it wrong. > > I'm not sure if CS's version supports n32 and n64, but adding > it wouldn't be a big issue. Right - it's not there, but we figured we'd add it at some not-too-future date. Also: - We reserve two words at the start of the PLT GOT rather than pass another argument to the resolver. One of them points to the PLT resolver, and the other to the link map (from which the dynamic linker can look up whatever it needs). - One of the new dynamic tags, DT_MIPS_PLTGOT, exists solely to let the dynamic linker fill in those two reserved entries. So this tag is required. - The other dynamic tag, DT_MIPS_RWPLT, is for a specified but unimplmented optimization a la PowerPC-32 - rewriting resolved PLT entries to a direct jump. OK, that's the ABI comparison. These are what I'm concerned about for integrating the two versions; all implementation differences I know we can decide case-by-case. And because both Richard's and our versions apply this behavior by default based on a configure option, I'm not concerned with the command line options or spelling of configure options either. We've shipped our version. Richard's version has presumably also shipped. We did negotiate the ABI changes with MTI; this is not quite as good as doing it in full view, but it was the best we could manage and MTI is as close to a central authority for the MIPS psABI as exists today. Richard, what are your thoughts on reconciling the differences? You can surely guess that I want to avoid changing our ABI now, even for relatively significant technical reasons - I'm all ears if there's a major reason, but in the comparisons I do not see one. If necessary, one of us can end up with a compatibility layer at runtime thanks to DT_MIPS_RWPLT :-( Comments welcome from all. -- Daniel Jacobowitz CodeSourcery --vtzGhvizbBRQ85DL Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="nonpic.txt" ==== MIPS non-PIC ABI specification ==== Introduction ---- This document describes the specification of the new MIPS ABI to provide absolute (non-PIC) addressing as used for Linux applications on most architectures. MIPS currently uses the existing psABI that mandates compilation of applications as position-independent code. The intention is that this extension to the ABI will be a strict superset of the existing MIPS o32 psABI for non-PIC executables, and will not break compatibility with legacy PIC object files, allowing interlinking of new-model and legacy object files both statically and dynamically (apart from ld.so, of course). This document does not cover n32 and n64 ABIs; they are expected to be a straightforward extension of the same design. At this time we do not propose any change to the position-independent addressing conventions used by shared objects. Similarly, position-independent executables compiled with '-fpie' -- as required for address space randomisation in "hardened" Linux distributions -- shall continue to use the existing psABI addressing and calling mechanisms. Identification of Object Files ---- Object files which use this new ABI extension will need to be identifiable. They will have EF_MIPS_CPIC set and EF_MIPS_PIC clear in the ELF header's e_flags field. The dynamic linker can identify new-model executables which use the PLT mechanism by the existence of DT_JMPREL tag in the dynamic table. It is also suggested that the EI_ABIVERSION entry in the ELF header ident be incremented from 0 to 1 for such executables, so that existing dynamic linkers will refuse to link them, and display a "helpful" error message rather than linking them incorrectly and having the application crash. [Ed. note: this does not actually work with glibc's ld.so for executables; it does not check the ABI version of the executable, or checks it too late.] Procedure Linkage Table ---- The Procedure Linkage Table (PLT) consists of a set of stubs generated by the static linker to stand in for external functions that are in a shared object. They can be called using an absolute JAL instuction and then redirect the call from the executable to the actual function via a pointer in the PLT GOT (the .got.plt section which holds 32-bit function pointers only). The PLT is output to the .plt section, which section should be aligned to a 32 byte boundary so that all PLT entries occupy no more than one cache line. The PLT GOT holds function addresses used by the PLT stubs, and the PLT GOT entries shall be initialised by the static linker to point to the PLT header (i.e. the base of the .plt section). In this way the first call to an external function will invoke the dynamic linker to resolve the symbol and update the corresponding PLT GOT entry; the next call will then jump from the PLT straight to the function, avoiding the dynamic linker. In the existing version of the ABI, as implemented by glibc, the first two GOT entries are reserved: GOT[0] Pointer to dynamic linker's GOT resolver which takes a dynamic symbol index argument. GOT[1] Pointer to this object's link map In this ABI, the GOT layout will remain the same. The first two entries in the PLT GOT will be reserved as follows: PLTGOT[0] Pointer to dynamic linker's PLT resolver (which takes a PLT index argument instead of the dynamic symbol index used by the GOT resolver). PLTGOT[1] Pointer to this object's link map. Since PLT entries use absolute addresses to access the PLT GOT, the PLT GOT does not need to be located within 32K of the _gp symbol. Indeed it would be better to prevent the PLT GOT from occupying this scarce resource in the address map. There is no requirement for the PLT GOT and GOT to be consecutive. For each PLT entry a R_MIPS_JUMP_SLOT relocation entry shall be output to the dynamic .rel.plt section: the relocation entry's dynamic symbol index specifies the symbol to which the PLT entry refers, and the offset field holds the address of the PLT entry. An addend is never required (so we remain with REL relocs). The PLT index passed by the PLT to the dynamic linker is both an index into the array of jump slot relocations, and can be transformed into an index into the PLT GOT by adding two (corresponding to the reserved PLT resolver and link map slots at PLTGOT[0] and PLTGOT[1]). Dynamic symbol table entries referenced only by jump slot or copy relocations shall precede the "GOT mapped" symbols whose first index is specified by the DT_MIPS_GOTSYM dynamic table entry. PLT Header ---- The first entry in the PLT handles the first call to a PLT only, and is 32 bytes in size:: PLT0: lui gp, %hi(.got.plt) # linker needs address of addiu gp, %lo(.got.plt) # .got.plt to find link map lw t9, 0(gp) # PLTGOT[0] == &_dl_runtime_pltresolve() move t7,ra # linker needs caller's address jalr t9 # call _dl_runtime_pltresolve() nop # bdslot nop # spare nop # spare PLT Type A '''' If the maximum PLT index is less than or equal to 65535, then a minimum length PLT of 16 bytes can be generated:: PLT1: lui t7, %hi(%pltgot(name1)) # high PLT GOT pointer lw t9, %lo(%pltgot(name1))(t7) # load func pointer from PLT GOT ori t8, $0, index1 # load plt index (ldslot) jr t9 # jump to func PLT2: lui t7, %hi(%pltgot(name2) # (bdslot) lw t9, %lo(%pltgot(name2))(t7) ori t8, $0, index2 jr t9 PLT3: ... PLTn: nop; nop; nop; nop (Note that this is effectively pseudocode; the assembler does not need modifying to understand "%pltgot(...)" since these instructions will be directly written out by the linker.) PLT Type B '''' When the maximum PLT index is greater than 65535, a large PLT is required, rounded up to 32 bytes in length:: PLT1: lui t7, %hi(%pltgot(name1)) # high PLT GOT pointer lw t9, %lo(%pltgot(name1))(t7) # load func pointer from PLT GOT lui t8, index1>>16 # load hi plt index (ldslot) jr t9 # jump to func ori t8, t8, index1&0xffff # load lo plt index (bdslot) nop nop nop Writable PLT Fixup ---- PLT Type C '''' After resolving the symbol and updating the PLT GOT, then if the PLT is in a writable section, the dynamic linker shall patch the PLT to use the absolute address of the function, thereby avoiding the PLT GOT reference, as follows. The dynamic linker can detect a writable PLT by the existence of a non-null DT_MIPS_RWPLT entry in the dynamic table:: PLT1: lui t9, %hi(name1) addiu t9, %lo(name1) jr t9 nop PLT Type D '''' Furthermore if the address at which the function is loaded lies within the same 256MB segment as the PLT entry, then it can avoid the indirect jump also:: PLT1: lui t9, %hi(name1) j name1 addiu t9, %lo(name1) nop Note that the base MIPS32 and MIPS64 MMU does not provide a "no-execute" bit, and therefore cannot support the "least privilege" page protection model required by "Hardened" Linux features such as Exec Shield and PAX. [Actually the SmartMIPS ASE specifies the execute-inhibit (XI) bit, but that's only available in the 4KSd core.] However the static linker should be capable of generating a non-writable (secure) PLT and GOT to conform with SELinux restrictions, and on a SmartMIPS core this could be used to prevent writable data areas from becoming executable. This would be at the cost of some loss of performance for external function calls. Function addresses ---- To allow comparison of function addresses to work as expected, it is necessary for the executable and all shared objects to see the same function address. If the executable takes the address of an external function it will generate a PLT entry for that function, and that PLT entry must then be the canonical address for the function throughout the program. Taking the address of an external function in a non-PIC executable will result in a symbol table entry with type STT_FUNC and section index of SHN_UNDEF, but with a non-zero st_value field that holds the address of the function's PLT entry; furthermore the new STO_MIPS_PLT bit shall be set in the symbol's st_other field. If the function's address is not referenced (i.e. the function is only ever called by the executable), then the symbol's st_value field will be zero and the STO_MIPS_PLT bit clear. The dynamic linker will use an undefined function symbol table entry with STO_MIPS_PLT set to resolve all references to that symbol in preference to the actual definition of that symbol, except when resolving an R_MIPS_JUMP_SLOT relocation. Note that this is the opposite behaviour to the legacy MIPS psABI where an undefined function symbol table entry with a zero st_value field indicates that there is an address reference to the function and the dynamic linker must resolve the symbol immediately upon loading; and where undefined function entries are always ignored when searching for a symbol definition. Dynamic Section ---- Dynamic section entries give information to the dynamic linker. Some of the information is processor-specific, including the interpretation of some entries in the dynamic structure. The following new or changed dynamic table entries are required by the extended ABI: DT_JMPREL (23) Previously unused for MIPS, now points to the first jump-slot relocation in the dynamic relocation table (i.e. the base of .rel.plt). DT_PLTREL (20) Previously unused for MIPS, now with a value of DT_REL indicating that DT_JMPREL points to REL relocations. DT_PLTRELSZ (2) Previously unused for MIPS, now holding the size of .rel.plt in bytes. DT_MIPS_PLTGOT (0x70000032) (New) Points to the base of the PLT GOT (.got.plt section), since it may not be contiguous with the traditional GOT (.got section). The standard DT_PLTGOT entry points to the base of the GOT. DT_MIPS_RWPLT (0x70000034) (New) Points to the base of the PLT when the PLT is writable; for a non-writable PLT it is omitted or has a zero value. The dynamic symbol table may have undefined function entries with the following bit set in the st_other field: STO_MIPS_PLT (0x8) (New) Symbol value is the address of a PLT entry. The dynamic relocation table may now contain two new relocation types generated by the static linker: R_MIPS_COPY (126) A data copy relocation. R_MIPS_JUMP_SLOT (127) A PLT relocation. External Data ---- If a non-PIC executable contains a reference to a data symbol in a shared object, then the static linker shall allocate space for that symbol in the executable's writable .dynbss (or .dynsbss) section, and output an R_MIPS_COPY relocation entry to the dynamic relocation section. The offset field of the relocation entry gives the address of the data in the .dynbss section. During execution the dynamic linker will copy any initial data associated with the shared object's symbol to the location specified by the offset, and point all GOT entries that refer to that symbol to the executable's copy. Large Code Size ---- The 26-bit offset of a MIPS absolute JAL and J instruction would limit the executable's code (including the PLT) to fit in a single 256MB address segment. That's sufficient for most embedded applications, but could be exceeded by some larger "server" applications. This may be handled by explicitly compiling large applications with '-mlongcalls'. A more elegant solution would be for the linker to automatically insert trampolines when a call site and the function (or its PLT) are not within the same 256MB segment, similar to the mechanism used for the PPC32 architecture. This may be implemented at a later date and has no ABI implications. Small Data ---- An optimisation available to statically-linked "bare iron" applications is to place data with size no greater than some threshold (default 8 bytes) in a small data section, where it can be referenced using short offsets from the $gp register. In Dhrystone the lack of small data addressing accounts for approximately one eighth of the 30% performance differential between bare-iron and Linux. Enabling small data addressing for non-PIC executables will enable some but not all of this performance to be regained, particularly in functions which reference many small global variables. Because shared libraries use the $gp register to hold their GOT pointer, the register will not be constant throughout the application, so the compiler must reload the small data pointer whenever required by a function. Note that "small" external data must be allocated in the executable's .dynsbss section, instead of the .dynbss section. Since this is a local optimisation the compiler may use an arbitrary register to hold the small data pointer: it could be any call-clobbered register, or a call-saved register if its use crosses a function call. The compiler might choose not to use a small data pointer register if it can determine that there is only one reference to small data in a function, in which case it will be faster to use an absolute address. For non-PIC executables the compiler may now consider $gp to be a call-clobbered register that it is free to allocate for any purpose. Legacy psABI support ---- While new-model code will use the PLT to reference external functions, any legacy PIC code with which it is statically linked should continue to use the linker-generated call stubs in the .MIPS.stubs section, rather than referencing the new-model PLT. This is to avoid the penalty of a double indirection when calling the function: i.e. calling indirectly via the GOT to the PLT, and then the PLT calling the actual function via the PLT GOT. The exception to this is if the non-PIC code references the same function, in which case the PIC code must generate a local GOT entry which points to the associated PLT entry. [A possible optimisation, if we are willing to have both a PLT GOT and GOT entry referencing the same function, is to only point the GOT to the PLT only if there are relocations other than R_MIPS_26, R_MIPS_CALL16 or R_MIPS_GOT16 referencing the function, and otherwise use a global GOT entry pointing directly to the function.] Similarly for access to external data, if the non-PIC code generates an R_MIPS_COPY relocation for a symbol, then PIC code referencing the same symbol must allocate a local GOT entry pointing to the executable's copy of the data in .dynbss or .dynsbss. Otherwise a global GOT entry shall be allocated to point to the symbol. Finally, if the non-PIC executable references a function in the statically-linked PIC code, then it will be necessary for the linker to allocate a call stub which first loads the $t9 register with the function's address, for use by non-PIC caller. The call stub would look like PLT style C or D above, and could be allocated in the PLT or .MIPS.stubs section, or any other part of the text section. If the function is globally binding, and is referenced by a non-PIC, non-call relocation, then its symbol table entry must point to the call stub, so that the stub is the canonical address of the function. --vtzGhvizbBRQ85DL Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="gcc-nonpic.diff" Index: gcc/configure =================================================================== --- gcc/configure (revision 137143) +++ gcc/configure (working copy) @@ -1048,6 +1048,7 @@ Optional Features: arrange to use setjmp/longjmp exception handling --enable-secureplt enable -msecure-plt by default for PowerPC --enable-cld enable -mcld by default for 32bit x86 + --enable-mips-nonpic enable non-PIC ABI by default for MIPS GNU/Linux o32 --disable-win32-registry disable lookup of installation paths in the Registry on Windows hosts @@ -13779,6 +13780,12 @@ else enable_cld=no fi; +# Check whether --enable-mips-nonpic or --disable-mips-nonpic was given. +if test "${enable_mips_nonpic+set}" = set; then + enableval="$enable_mips_nonpic" + +fi; + # Windows32 Registry support for specifying GCC installation paths. # Check whether --enable-win32-registry or --disable-win32-registry was given. if test "${enable_win32_registry+set}" = set; then Index: gcc/testsuite/gcc.target/mips/lazy-binding-1.c =================================================================== --- gcc/testsuite/gcc.target/mips/lazy-binding-1.c (revision 137143) +++ gcc/testsuite/gcc.target/mips/lazy-binding-1.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do compile { target nomips16 } } */ -/* { dg-mips-options "-mabicalls -mshared -mexplicit-relocs -O2 -fno-delayed-branch" } */ +/* { dg-mips-options "-mabicalls -mshared -fpic -mexplicit-relocs -O2 -fno-delayed-branch" } */ void bar (void); Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c (revision 0) @@ -0,0 +1,9 @@ +extern void nonpic_nothing (void); +extern int hit_nonpic_addr; +void +nonpic_addr () +{ + nonpic_receive_fn_addr (&nonpic_nothing); + hit_nonpic_addr++; + return; +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c (revision 0) @@ -0,0 +1,10 @@ +extern void pic_nothing (void); +extern void pic_addr (void); +extern int hit_nonpic_call; +void +nonpic_call () +{ + pic_nothing (); + pic_addr (); + hit_nonpic_call++; +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c (revision 0) @@ -0,0 +1,9 @@ +extern void pic_nothing (void); +extern void abort (void); +void +pic_receive_fn_addr (void *x) +{ + if (x != &pic_nothing) + abort (); + return; +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-10.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-10.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-10.c (revision 0) @@ -0,0 +1,25 @@ +/* { dg-options "nonpic-call.o pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +extern void nonpic_call (); +extern void pic_addr(); +int hit_nonpic_call = 0; +int hit_pic_addr = 0; +int hit_pic_nothing = 0; +int hit_nonpic_nothing = 0; +extern void exit (int); +extern void abort (void); + +main () +{ + nonpic_call (); + pic_addr (); + + if (hit_nonpic_call != 1) + abort (); + + if (hit_pic_addr != 2) + abort (); + + exit (0); + +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-11.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-11.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-11.c (revision 0) @@ -0,0 +1,23 @@ +/* { dg-options "nonpic-addr.o pic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +extern void nonpic_addr (); +extern void pic_addr(); +extern void exit (int); +extern void abort (void); +int hit_nonpic_addr = 0; +int hit_pic_addr = 0; +int hit_pic_nothing = 0; +int hit_nonpic_nothing = 0; +main () +{ + nonpic_addr (); + pic_addr (); + + if (hit_nonpic_addr != 1) + abort (); + + if (hit_pic_addr != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-12.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-12.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-12.c (revision 0) @@ -0,0 +1,23 @@ +/* { dg-options "nonpic-addr-call.o pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +int hit_nonpic_addr_call = 0; +int hit_pic_addr = 0; +int hit_nonpic_nothing = 0; +int hit_pic_nothing = 0; +extern void nonpic_addr_call (); +extern void pic_addr(); +extern void abort (void); +extern void exit (int); +main () +{ + nonpic_addr_call (); + pic_addr (); + + if (hit_nonpic_addr_call != 1) + abort (); + + if (hit_pic_addr != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp (revision 0) @@ -0,0 +1,45 @@ +# Copyright (C) 2008 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a MIPS target. +if ![istarget mips*-*-*] { + return +} + +load_lib gcc-dg.exp + +dg-init + +set old-dg-do-what-default "${dg-do-what-default}" +set dg-do-what-default "assemble" + +foreach testcase [lsort [glob -nocomplain $srcdir/$subdir/pic-*.c]] { + verbose "Compiling [file tail [file dirname $testcase]]/[file tail $testcase]" + dg-test -keep-output $testcase "-fpic" "" +} + +foreach testcase [lsort [glob -nocomplain $srcdir/$subdir/nonpic-\[a-z\]*.c]] { + verbose "Compiling [file tail [file dirname $testcase]]/[file tail $testcase]" + dg-test -keep-output $testcase "-fno-pic" "" +} + +set dg-do-what-default "run" +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/nonpic-\[0-9\]*.c]] "-fno-pic" "" + +set dg-do-what-default "${old-dg-do-what-default}" +dg-finish Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c (revision 0) @@ -0,0 +1,10 @@ +extern int hit_nonpic_addr_call; +extern void pic_nothing (void); +extern void pic_receive_fn_addr (void *); +void +nonpic_addr_call (void) +{ + hit_nonpic_addr_call++; + pic_receive_fn_addr (&pic_nothing); + return; +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-13.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-13.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-13.c (revision 0) @@ -0,0 +1,21 @@ +/* { dg-options "pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o" } */ + +int hit_pic_addr_call = 0; +int hit_nonpic_nothing = 0; +extern void nonpic_nothing (); +extern void pic_addr_call(); +extern void exit (int); +extern void abort (void); +main () +{ + nonpic_nothing (); + pic_addr_call (); + + if (hit_nonpic_nothing != 1) + abort (); + + if (hit_pic_addr_call != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-14.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-14.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-14.c (revision 0) @@ -0,0 +1,24 @@ +/* { dg-options "nonpic-call.o pic-addr.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +int hit_pic_addr_call = 0; +int hit_nonpic_call = 0; +int hit_pic_addr = 0; +int hit_nonpic_nothing = 0; +int hit_pic_nothing = 0; +extern void nonpic_call (); +extern void pic_addr_call(); +extern void abort (void); +extern void exit (int); +main () +{ + nonpic_call (); + pic_addr_call (); + + if (hit_nonpic_call != 1) + abort (); + + if (hit_pic_addr_call != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-15.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-15.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-15.c (revision 0) @@ -0,0 +1,23 @@ +/* { dg-options "nonpic-addr.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +int hit_pic_addr_call = 0; +int hit_nonpic_addr = 0; +int hit_nonpic_nothing = 0; +int hit_pic_nothing = 0; +extern void nonpic_addr (); +extern void pic_addr_call(); +extern void abort (void); +extern void exit (int); +main () +{ + nonpic_addr (); + pic_addr_call (); + + if (hit_nonpic_addr != 1) + abort (); + + if (hit_pic_addr_call != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-16.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-16.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-16.c (revision 0) @@ -0,0 +1,21 @@ +/* { dg-options "nonpic-addr-call.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o pic-nothing.o nonpic-nothing.o" } */ + +extern void abort (void); +extern void exit (int); +extern void nonpic_addr_call (); +extern void pic_addr_call(); +int hit_nonpic_addr_call = 0; +int hit_pic_addr_call = 0; +int hit_nonpic_nothing = 0; +int hit_pic_nothing = 0; +main () +{ + nonpic_addr_call (); + pic_addr_call (); + + if (hit_nonpic_addr_call != 1) + abort (); + if (hit_pic_addr_call != 1) + abort (); + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c (revision 0) @@ -0,0 +1,8 @@ +extern void nonpic_nothing (void); +extern void abort (void); +void +nonpic_receive_fn_addr (void *x) +{ + if (x != &nonpic_nothing) + abort (); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c (revision 0) @@ -0,0 +1,7 @@ +extern int hit_pic_nothing; +void +pic_nothing () +{ + hit_pic_nothing++; + return; +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c (revision 0) @@ -0,0 +1,9 @@ +extern int hit_pic_addr; +extern void pic_nothing (void); +void +pic_addr () +{ + pic_receive_fn_addr (&pic_nothing); + hit_pic_addr++; + return; +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c (revision 0) @@ -0,0 +1,10 @@ +extern int hit_pic_call; +extern void nonpic_nothing (void); +extern void nonpic_addr (void); +void +pic_call () +{ + nonpic_nothing (); + nonpic_addr (); + hit_pic_call++; +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-1.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-1.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-1.c (revision 0) @@ -0,0 +1,21 @@ +/* { dg-options "pic-nothing.o nonpic-nothing.o" } */ + +extern void nonpic_nothing (); +extern void pic_nothing (); +int hit_pic_nothing = 0; +int hit_nonpic_nothing = 0; +extern void exit (int); +extern void abort (void); +main () +{ + nonpic_nothing (); + pic_nothing (); + + if (hit_nonpic_nothing != 1) + abort (); + + if (hit_pic_nothing != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-2.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-2.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-2.c (revision 0) @@ -0,0 +1,23 @@ +/* { dg-options "pic-addr.o nonpic-call.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +extern void nonpic_call (); +extern void pic_nothing (); +extern void abort (void); +extern void exit (int); +int hit_nonpic_call = 0; +int hit_pic_nothing = 0; +int hit_pic_addr = 0; +int hit_nonpic_nothing = 0; +main () +{ + nonpic_call (); + pic_nothing (); + + if (hit_nonpic_call != 1) + abort (); + + if (hit_pic_nothing != 2) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-3.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-3.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-3.c (revision 0) @@ -0,0 +1,22 @@ +/* { dg-options "nonpic-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +extern void nonpic_addr (); +extern void pic_nothing (); +extern void abort (void); +extern void exit (int); +int hit_nonpic_addr = 0; +int hit_pic_nothing = 0; +int hit_nonpic_nothing = 0; +main () +{ + nonpic_addr (); + pic_nothing (); + + if (hit_nonpic_addr != 1) + abort (); + + if (hit_pic_nothing != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-4.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-4.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-4.c (revision 0) @@ -0,0 +1,24 @@ +/* { dg-options "pic-addr.o pic-receive-fn-addr.o nonpic-addr-call.o nonpic-nothing.o pic-nothing.o" } */ + +int hit_nonpic_addr_call = 0; +int hit_pic_nothing = 0; +int hit_nonpic_nothing = 0; +int hit_pic_addr = 0; +int hit_nonpic_addr = 0; +extern void nonpic_addr_call (); +extern void pic_nothing (); +extern void exit (int); +extern void abort (void); +main () +{ + nonpic_addr_call (); + pic_nothing (); + + if (hit_nonpic_addr_call != 1) + abort (); + + if (hit_pic_nothing != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-5.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-5.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-5.c (revision 0) @@ -0,0 +1,24 @@ +/* { dg-options "pic-addr.o pic-call.o nonpic-addr.o pic-receive-fn-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +extern void nonpic_nothing (); +extern void pic_call (); +extern void exit (int); +extern void abort (void); +int hit_nonpic_nothing = 0; +int hit_pic_call = 0; +int hit_nonpic_addr = 0; +int hit_pic_nothing = 0; +int hit_pic_addr = 0; +main () +{ + nonpic_nothing (); + pic_call (); + + if (hit_nonpic_nothing != 2) + abort (); + + if (hit_pic_call != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-6.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-6.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-6.c (revision 0) @@ -0,0 +1,26 @@ +/* { dg-options "pic-call.o nonpic-call.o nonpic-addr.o pic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +extern void nonpic_call (); +extern void pic_call (); +extern void exit (int); +extern void abort (void); +int hit_pic_call = 0; +int hit_nonpic_call = 0; +int hit_pic_nothing = 0; +int hit_nonpic_nothing = 0; +int hit_nonpic_addr = 0; +int hit_pic_addr = 0; + +main () +{ + pic_call (); + nonpic_call (); + + if (hit_pic_call != 1) + abort (); + + if (hit_nonpic_call != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-7.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-7.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-7.c (revision 0) @@ -0,0 +1,23 @@ +/* { dg-options "pic-call.o nonpic-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +int hit_pic_call = 0; +int hit_nonpic_addr = 0; +int hit_nonpic_nothing = 0; +int hit_pic_nothing = 0; +extern void nonpic_addr (); +extern void pic_call (); +extern void exit (int); +extern void abort (void); +main () +{ + pic_call (); + nonpic_addr (); + + if (hit_pic_call != 1) + abort (); + + if (hit_nonpic_addr != 2) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c (revision 0) @@ -0,0 +1,7 @@ +extern int hit_nonpic_nothing; +void +nonpic_nothing () +{ + hit_nonpic_nothing++; + return; +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-8.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-8.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-8.c (revision 0) @@ -0,0 +1,24 @@ +/* { dg-options "pic-call.o nonpic-addr-call.o nonpic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +int hit_nonpic_addr_call = 0; +int hit_pic_call = 0; +int hit_pic_nothing = 0; +int hit_nonpic_nothing = 0; +int hit_nonpic_addr = 0; +extern void exit (int); +extern void abort (void); +extern void nonpic_addr_call (); +extern void pic_call (); +main () +{ + pic_call (); + nonpic_addr_call (); + + if (hit_pic_call != 1) + abort (); + + if (hit_nonpic_addr_call != 1) + abort (); + + exit (0); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-9.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-9.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-9.c (revision 0) @@ -0,0 +1,15 @@ +/* { dg-options "pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */ + +extern void nonpic_nothing (); +extern void pic_addr(); +extern void exit (int); +extern void abort (void); +int hit_pic_addr = 0; +int hit_nonpic_nothing = 0; +int hit_pic_nothing = 0; +int hit_pic_receive_fn_addr = 0; +main () +{ + pic_addr (); + nonpic_nothing (); +} Index: gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c (revision 0) +++ gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c (revision 0) @@ -0,0 +1,10 @@ +extern int hit_pic_addr_call; +extern void nonpic_nothing (void); +extern void nonpic_receive_fn_addr (void *); +void +pic_addr_call (void) +{ + hit_pic_addr_call++; + nonpic_receive_fn_addr (&nonpic_nothing); + return; +} Index: gcc/configure.ac =================================================================== --- gcc/configure.ac (revision 137143) +++ gcc/configure.ac (working copy) @@ -1537,6 +1537,10 @@ AC_ARG_ENABLE(cld, [ --enable-cld enable -mcld by default for 32bit x86], [], [enable_cld=no]) +AC_ARG_ENABLE(mips-nonpic, +[ --enable-mips-nonpic enable non-PIC ABI by default for MIPS GNU/Linux o32], +[], []) + # Windows32 Registry support for specifying GCC installation paths. AC_ARG_ENABLE(win32-registry, [ --disable-win32-registry Index: gcc/config.gcc =================================================================== --- gcc/config.gcc (revision 137143) +++ gcc/config.gcc (working copy) @@ -1489,7 +1489,7 @@ mcore-*-pe*) mips-sgi-irix[56]*) tm_file="elfos.h ${tm_file} mips/iris.h" tmake_file="mips/t-iris mips/t-slibgcc-irix" - target_cpu_default="MASK_ABICALLS" + tm_defines="${tm_defines} TARGET_ABICALLS_DEFAULT=1" case ${target} in *-*-irix5*) tm_file="${tm_file} mips/iris5.h" @@ -1515,12 +1515,16 @@ mips-sgi-irix[56]*) use_fixproto=yes ;; mips*-*-netbsd*) # NetBSD/mips, either endian. - target_cpu_default="MASK_ABICALLS" + tm_defines="${tm_defines} TARGET_ABICALLS_DEFAULT=1" tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h" ;; mips64*-*-linux*) tm_file="dbxelf.h elfos.h svr4.h linux.h ${tm_file} mips/linux.h mips/linux64.h" tmake_file="${tmake_file} mips/t-linux64" + tm_defines="${tm_defines} TARGET_ABICALLS_DEFAULT=1" + if test x${enable_mips_nonpic}; then + tm_defines="${tm_defines} TARGET_ABICALLS_NONPIC=1" + fi tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_N32" case ${target} in mips64el-st-linux-gnu) @@ -1533,7 +1537,11 @@ mips64*-*-linux*) test x$with_llsc != x || with_llsc=yes ;; mips*-*-linux*) # Linux MIPS, either endian. - tm_file="dbxelf.h elfos.h svr4.h linux.h ${tm_file} mips/linux.h" + tm_file="dbxelf.h elfos.h svr4.h linux.h ${tm_file} mips/linux.h" + tm_defines="${tm_defines} TARGET_ABICALLS_DEFAULT=1" + if test x${enable_mips_nonpic}; then + tm_defines="${tm_defines} TARGET_ABICALLS_NONPIC=1" + fi case ${target} in mipsisa32r2*) tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33" @@ -1545,7 +1553,7 @@ mips*-*-linux*) # Linux MIPS, either ;; mips*-*-openbsd*) tm_defines="${tm_defines} OBSD_HAS_DECLARE_FUNCTION_NAME OBSD_HAS_DECLARE_OBJECT OBSD_HAS_CORRECT_SPECS" - target_cpu_default="MASK_ABICALLS" + tm_defines="${tm_defines} TARGET_ABICALLS_DEFAULT=1" tm_file="mips/mips.h openbsd.h mips/openbsd.h mips/sdb.h" case ${target} in mips*el-*-openbsd*) Index: gcc/config/mips/linux.h =================================================================== --- gcc/config/mips/linux.h (revision 137143) +++ gcc/config/mips/linux.h (working copy) @@ -37,10 +37,6 @@ along with GCC; see the file COPYING3. #undef MD_EXEC_PREFIX #undef MD_STARTFILE_PREFIX -/* If we don't set MASK_ABICALLS, we can't default to PIC. */ -#undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_ABICALLS - #define TARGET_OS_CPP_BUILTINS() \ do { \ LINUX_TARGET_OS_CPP_BUILTINS(); \ @@ -79,7 +75,8 @@ along with GCC; see the file COPYING3. %{static:-static}}}" #undef SUBTARGET_ASM_SPEC -#define SUBTARGET_ASM_SPEC "%{mabi=64: -64} %{!mno-abicalls:-KPIC}" +#define SUBTARGET_ASM_SPEC \ + "%{mabi=64: -64} %{mabicalls:%{fpic|fPIC:-KPIC;:-mnon-pic-abicalls}}" /* The MIPS assembler has different syntax for .set. We set it to .dummy to trap any errors. */ @@ -163,7 +160,8 @@ extern const char *host_detect_local_cpu # define MARCH_MTUNE_NATIVE_SPECS "" #endif -#define BASE_DRIVER_SELF_SPECS \ +#define LINUX_DRIVER_SELF_SPECS \ NO_SHARED_SPECS \ MARCH_MTUNE_NATIVE_SPECS -#define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS +#undef SUBTARGET_SELF_SPECS +#define SUBTARGET_SELF_SPECS LINUX_DRIVER_SELF_SPECS Index: gcc/config/mips/elfoabi.h =================================================================== --- gcc/config/mips/elfoabi.h (revision 137143) +++ gcc/config/mips/elfoabi.h (working copy) @@ -19,7 +19,8 @@ You should have received a copy of the G along with GCC; see the file COPYING3. If not see . */ -#define DRIVER_SELF_SPECS \ +#undef SUBTARGET_SELF_SPECS +#define SUBTARGET_SELF_SPECS \ /* Make sure a -mips option is present. This helps us to pick \ the right multilib, and also makes the later specs easier \ to write. */ \ Index: gcc/config/mips/linux64.h =================================================================== --- gcc/config/mips/linux64.h (revision 137143) +++ gcc/config/mips/linux64.h (working copy) @@ -20,9 +20,9 @@ along with GCC; see the file COPYING3. /* Force the default endianness and ABI flags onto the command line in order to make the other specs easier to write. */ -#undef DRIVER_SELF_SPECS -#define DRIVER_SELF_SPECS \ -BASE_DRIVER_SELF_SPECS \ +#undef SUBTARGET_SELF_SPECS +#define SUBTARGET_SELF_SPECS \ +LINUX_DRIVER_SELF_SPECS \ " %{!EB:%{!EL:%(endian_spec)}}" \ " %{!mabi=*: -mabi=n32}" Index: gcc/config/mips/sde.h =================================================================== --- gcc/config/mips/sde.h (revision 137143) +++ gcc/config/mips/sde.h (working copy) @@ -19,7 +19,8 @@ You should have received a copy of the G along with GCC; see the file COPYING3. If not see . */ -#define DRIVER_SELF_SPECS \ +#undef SUBTARGET_SELF_SPECS +#define SUBTARGET_SELF_SPECS \ /* Make sure a -mips option is present. This helps us to pick \ the right multilib, and also makes the later specs easier \ to write. */ \ Index: gcc/config/mips/mips.md =================================================================== --- gcc/config/mips/mips.md (revision 137143) +++ gcc/config/mips/mips.md (working copy) @@ -4462,6 +4462,22 @@ [(set (match_operand:P 0 "register_operand" "=d") (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))]) +;; Move the constant value of __gnu_local_gp (operand 1) into +;; operand 0, for non-PIC abicalls code. All uses of the result +;; are explicit, so there's no need for unspec_volatile here. +(define_insn_and_split "loadgp_nonpic_" + [(set (match_operand:P 0 "register_operand" "=d") + (const:P (unspec:P [(match_operand 1 "" "")] UNSPEC_LOADGP)))] + "TARGET_NONPIC_ABICALLS" + "#" + "" + [(const_int 0)] +{ + mips_emit_move (operands[0], operands[1]); + DONE; +} + [(set_attr "length" "8")]) + ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset ;; of _gp from the start of this function. Operand 1 is the incoming ;; function address. @@ -5827,11 +5843,12 @@ ;; Restore the gp that we saved above. Despite the earlier comment, it seems ;; that older code did recalculate the gp from $25. Continue to jump through -;; $25 for compatibility (we lose nothing by doing so). +;; $25 for compatibility (we lose nothing by doing so). Similarly restore +;; $gp if we might be jumping to code which expects that. (define_expand "builtin_longjmp" [(use (match_operand 0 "register_operand"))] - "TARGET_USE_GOT" + "TARGET_USE_GOT || TARGET_ABICALLS" { /* The elements of the buffer are, in order: */ int W = GET_MODE_SIZE (Pmode); Index: gcc/config/mips/iris6.h =================================================================== --- gcc/config/mips/iris6.h (revision 137143) +++ gcc/config/mips/iris6.h (working copy) @@ -29,7 +29,8 @@ along with GCC; see the file COPYING3. /* Force the default ABI onto the command line in order to make the specs easier to write. Default to the mips2 ISA for the O32 ABI. */ -#define DRIVER_SELF_SPECS \ +#undef SUBTARGET_SELF_SPECS +#define SUBTARGET_SELF_SPECS \ "%{!mabi=*: -mabi=n32}", \ "%{mabi=32: %{!mips*: %{!march*: -mips2}}}" Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c (revision 137143) +++ gcc/config/mips/mips.c (working copy) @@ -1415,7 +1415,7 @@ mips_classify_symbol (const_rtx x, enum if (TARGET_MIPS16_SHORT_JUMP_TABLES) return SYMBOL_PC_RELATIVE; - if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) + if (TARGET_PIC_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) return SYMBOL_GOT_PAGE_OFST; return SYMBOL_ABSOLUTE; @@ -1438,14 +1438,15 @@ mips_classify_symbol (const_rtx x, enum return SYMBOL_GP_RELATIVE; } - /* Do not use small-data accesses for weak symbols; they may end up - being zero. */ + /* Use a small-data access if appropriate; but do not use small-data + accesses for weak symbols; they may end up being zero. */ if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x)) return SYMBOL_GP_RELATIVE; - /* Don't use GOT accesses for locally-binding symbols when -mno-shared - is in effect. */ - if (TARGET_ABICALLS + /* Use GOT accesses for PIC abicalls, except for locally-binding + symbols when -mno-shared is in effect - in that case the symbol + address is constant. */ + if (TARGET_PIC_ABICALLS && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))) { /* There are three cases to consider: @@ -2243,6 +2244,21 @@ mips_emit_call_insn (rtx pattern, bool l return insn; } +/* The __gnu_local_gp symbol. */ + +static GTY(()) rtx mips_gnu_local_gp_rtx; + +static rtx +mips_gnu_local_gp (void) +{ + if (mips_gnu_local_gp_rtx == NULL) + { + mips_gnu_local_gp_rtx = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp"); + SYMBOL_REF_FLAGS (mips_gnu_local_gp_rtx) |= SYMBOL_FLAG_LOCAL; + } + return mips_gnu_local_gp_rtx; +} + /* Return an instruction that copies $gp into register REG. We want GCC to treat the register's value as constant, so that its value can be rematerialized on demand. */ @@ -2255,9 +2271,22 @@ gen_load_const_gp (rtx reg) : gen_load_const_gp_di (reg)); } +/* Return an instruction that moves the constant value of + __gnu_local_gp into register REG. */ + +static rtx +gen_loadgp_nonpic (rtx reg) +{ + return (Pmode == SImode + ? gen_loadgp_nonpic_si (reg, mips_gnu_local_gp ()) + : gen_loadgp_nonpic_di (reg, mips_gnu_local_gp ())); +} + /* Return a pseudo register that contains the value of $gp throughout the current function. Such registers are needed by MIPS16 functions, - for which $gp itself is not a valid base register or addition operand. */ + for which $gp itself is not a valid base register or addition operand. + Also hold the GP in a non-PIC abicalls function which refers to TLS + data - such functions do not require $28 or even a hard register. */ static rtx mips16_gp_pseudo_reg (void) @@ -2273,7 +2302,10 @@ mips16_gp_pseudo_reg (void) { rtx insn, scan, after; - insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx); + if (TARGET_NONPIC_ABICALLS) + insn = gen_loadgp_nonpic (cfun->machine->mips16_gp_pseudo_rtx); + else + insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx); push_topmost_sequence (); /* We need to emit the initialization after the FUNCTION_BEG @@ -2415,6 +2447,19 @@ mips_add_offset (rtx temp, rtx reg, HOST return plus_constant (reg, offset); } +/* Return the RTX to use for explicit GOT accesses. Uses a pseudo if + possible. */ + +static rtx +mips_got_base (void) +{ + gcc_assert (can_create_pseudo_p ()); + if (TARGET_NONPIC_ABICALLS) + return mips16_gp_pseudo_reg (); + else + return pic_offset_table_rtx; +} + /* The __tls_get_attr symbol. */ static GTY(()) rtx mips_tls_symbol; @@ -2438,7 +2483,7 @@ mips_call_tls_get_addr (rtx sym, enum mi start_sequence (); emit_insn (gen_rtx_SET (Pmode, a0, - gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc))); + gen_rtx_LO_SUM (Pmode, mips_got_base (), loc))); insn = mips_expand_call (v0, mips_tls_symbol, const0_rtx, const0_rtx, false); RTL_CONST_CALL_P (insn) = 1; use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); @@ -2504,12 +2549,12 @@ mips_legitimize_tls_address (rtx loc) if (Pmode == DImode) { emit_insn (gen_tls_get_tp_di (v1)); - emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2)); + emit_insn (gen_load_gotdi (tmp1, mips_got_base (), tmp2)); } else { emit_insn (gen_tls_get_tp_si (v1)); - emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2)); + emit_insn (gen_load_gotsi (tmp1, mips_got_base (), tmp2)); } dest = gen_reg_rtx (Pmode); emit_insn (gen_add3_insn (dest, tmp1, v1)); @@ -6835,7 +6880,7 @@ mips_select_rtx_section (enum machine_mo /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION. - The complication here is that, with the combination TARGET_ABICALLS + The complication here is that, with the combination TARGET_PIC_ABICALLS && !TARGET_GPWORD, jump tables will use absolute addresses, and should therefore not be included in the read-only part of a DSO. Handle such cases by selecting a normal data section instead of a read-only one. @@ -6844,7 +6889,7 @@ mips_select_rtx_section (enum machine_mo static section * mips_function_rodata_section (tree decl) { - if (!TARGET_ABICALLS || TARGET_GPWORD) + if (!TARGET_PIC_ABICALLS || TARGET_GPWORD) return default_function_rodata_section (decl); if (decl && DECL_SECTION_NAME (decl)) @@ -7344,6 +7389,8 @@ mips_file_start (void) /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */ if (TARGET_ABICALLS) fprintf (asm_out_file, "\t.abicalls\n"); + if (TARGET_NONPIC_ABICALLS) + fprintf (asm_out_file, "\t.option\tpic0\n"); if (flag_verbose_asm) fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n", @@ -7937,7 +7984,7 @@ mips_save_reg_p (unsigned int regno) { /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then if we have not chosen a call-clobbered substitute. */ - if (regno == GLOBAL_POINTER_REGNUM) + if (regno == GLOBAL_POINTER_REGNUM && fixed_regs[regno]) return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno; /* Check call-saved registers. */ @@ -8161,7 +8208,7 @@ mips_current_loadgp_style (void) if (TARGET_RTP_PIC) return LOADGP_RTP; - if (TARGET_ABSOLUTE_ABICALLS) + if (TARGET_ABSOLUTE_ABICALLS || !flag_pic) return LOADGP_ABSOLUTE; return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI; @@ -8276,7 +8323,7 @@ mips_restore_gp (void) { rtx base, address; - gcc_assert (TARGET_ABICALLS && TARGET_OLDABI); + gcc_assert (TARGET_PIC_ABICALLS && TARGET_OLDABI); base = frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx; address = mips_add_offset (pic_offset_table_rtx, base, @@ -8527,10 +8574,6 @@ mips_save_reg (rtx reg, rtx mem) } } -/* The __gnu_local_gp symbol. */ - -static GTY(()) rtx mips_gnu_local_gp; - /* If we're generating n32 or n64 abicalls, emit instructions to set up the global pointer. */ @@ -8543,14 +8586,9 @@ mips_emit_loadgp (void) switch (mips_current_loadgp_style ()) { case LOADGP_ABSOLUTE: - if (mips_gnu_local_gp == NULL) - { - mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp"); - SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL; - } emit_insn (Pmode == SImode - ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp) - : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp)); + ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp ()) + : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp ())); break; case LOADGP_NEWABI: @@ -12702,6 +12740,10 @@ mips_override_options (void) /* End of code shared with GAS. */ + /* The non-PIC ABI may only be used in conjunction with the o32 ABI. */ + if (TARGET_NONPIC_ABICALLS && mips_abi != ABI_32) + sorry ("non-PIC abicalls may only be used with the o32 ABI"); + /* If no -mlong* option was given, infer it from the other options. */ if ((target_flags_explicit & MASK_LONG64) == 0) { @@ -12750,24 +12792,14 @@ mips_override_options (void) target_flags &= ~MASK_ABICALLS; } - /* MIPS16 cannot generate PIC yet. */ + /* MIPS16 cannot generate PIC or abicalls yet. */ if (TARGET_MIPS16 && (flag_pic || TARGET_ABICALLS)) { - sorry ("MIPS16 PIC"); + sorry ("MIPS16 PIC and abicalls are not yet implemented"); target_flags &= ~MASK_ABICALLS; flag_pic = flag_pie = flag_shlib = 0; } - if (TARGET_ABICALLS) - /* We need to set flag_pic for executables as well as DSOs - because we may reference symbols that are not defined in - the final executable. (MIPS does not use things like - copy relocs, for example.) - - Also, there is a body of code that uses __PIC__ to distinguish - between -mabicalls and -mno-abicalls code. */ - flag_pic = 1; - /* -mvr4130-align is a "speed over size" optimization: it usually produces faster code, but at the expense of more nops. Enable it at -O3 and above. */ @@ -12781,6 +12813,7 @@ mips_override_options (void) /* If we have a nonzero small-data limit, check that the -mgpopt setting is consistent with the other target flags. */ + if (mips_small_data_threshold > 0) { if (!TARGET_GPOPT) @@ -13001,6 +13034,14 @@ mips_conditional_register_usage (void) for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2) mips_swap_registers (regno); } + /* In non-PIC abicalls, $gp is completely ordinary; we can use a pseudo + for TLS GOT entries. */ + if (TARGET_NONPIC_ABICALLS) + { + call_used_regs[GLOBAL_POINTER_REGNUM] = TARGET_OLDABI; + call_really_used_regs[GLOBAL_POINTER_REGNUM] = TARGET_OLDABI; + fixed_regs[GLOBAL_POINTER_REGNUM] = 0; + } } /* Initialize vector TARGET to VALS. */ Index: gcc/config/mips/mips.h =================================================================== --- gcc/config/mips/mips.h (revision 137143) +++ gcc/config/mips/mips.h (working copy) @@ -163,7 +163,7 @@ enum mips_code_readable_setting { accesses are so much shorter. */ #define TARGET_ABSOLUTE_ABICALLS \ - (TARGET_ABICALLS \ + (TARGET_PIC_ABICALLS \ && !TARGET_SHARED \ && TARGET_EXPLICIT_RELOCS \ && !ABI_HAS_64BIT_SYMBOLS) @@ -182,11 +182,19 @@ enum mips_code_readable_setting { #define TARGET_SIBCALLS \ (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS)) -/* True if we need to use a global offset table to access some symbols. */ -#define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC) +/* True if using abicalls, and position-independent (even if + -mno-shared). */ +#define TARGET_PIC_ABICALLS (TARGET_ABICALLS && flag_pic) + +/* True if using abicalls, but not ourselves PIC. */ +#define TARGET_NONPIC_ABICALLS (TARGET_ABICALLS && !flag_pic) + +/* True if we need to use a global offset table to access some symbols. + Small data and TLS may use the GOT even without this. */ +#define TARGET_USE_GOT (TARGET_PIC_ABICALLS || TARGET_RTP_PIC) /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */ -#define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI) +#define TARGET_CALL_CLOBBERED_GP (TARGET_PIC_ABICALLS && TARGET_OLDABI) /* True if TARGET_USE_GOT and if $gp is a call-saved register. */ #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP) @@ -200,7 +208,8 @@ enum mips_code_readable_setting { Although GAS does understand .gpdword, the SGI linker mishandles the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64). We therefore disable GP-relative switch tables for n64 on IRIX targets. */ -#define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX)) +#define TARGET_GPWORD \ + (TARGET_PIC_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX)) /* Generate mips16 code */ #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) @@ -973,6 +982,47 @@ enum mips_code_readable_setting { #endif +/* Some targets (most of those with dynamic linking, e.g. Irix, + GNU/Linux, BSD) default to -mabicalls. They mostly default to PIC + also. Force the appropriate -mabicalls setting into the command + line for the benefit of the -fno-pic spec just below. */ +#ifdef TARGET_ABICALLS_DEFAULT +#define ABICALLS_SPEC "%{!mno-abicalls:%{!mabicalls:-mabicalls}}" +#else +#define ABICALLS_SPEC "%{!mno-abicalls:%{!mabicalls:-mno-abicalls}}" +#endif + +/* Make -mabicalls imply PIC unless the target supports non-PIC + abicalls. Targets which do not support non-PIC abicalls must set + flag_pic for executables as well as DSOs + because we may reference symbols that are not defined in + the final executable - these targets do not have copy relocs. + + All 64-bit targets are assumed to not support PIC abicalls. + CSL NOTE: It would be nice to remove this restriction before + contributing upstream; 64-bit support should be a small project. + + Also, there is a body of code that uses __PIC__ to distinguish + between -mabicalls and -mno-abicalls code. For targets with + non-PIC abicalls support any such code will have to be corrected. + All you need to do if !__PIC__ is use $t9 for indirect calls + and be careful about assuming $gp is set up in inline asm. */ +#ifdef TARGET_ABICALLS_NONPIC +#define ABICALLS_SELF_SPECS ABICALLS_SPEC, \ + "%{mabicalls:%{!fno-pic:%{mabi=o64|mabi=64|mabi=n32:-fpic}}}" +#else +#define ABICALLS_SELF_SPECS ABICALLS_SPEC, \ + "%{mabicalls:%{!fno-pic:-fpic}}" +#endif + +/* Any additional self specs defined by the subtarget. */ +#define SUBTARGET_SELF_SPECS "" + +#define DRIVER_SELF_SPECS \ + SUBTARGET_SELF_SPECS, \ + ABICALLS_SELF_SPECS + + #ifndef MIPS_ABI_DEFAULT #define MIPS_ABI_DEFAULT ABI_32 #endif @@ -1044,7 +1094,7 @@ enum mips_code_readable_setting { %{mfix-vr4120} %{mfix-vr4130} \ %(subtarget_asm_optimizing_spec) \ %(subtarget_asm_debugging_spec) \ -%{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \ +%{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \ %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ %{mfp32} %{mfp64} \ %{mshared} %{mno-shared} \ @@ -2484,7 +2534,7 @@ typedef struct mips_args { ? "%*" INSN "\t%" #OPNO "%/" \ : REG_P (OPERANDS[OPNO]) \ ? "%*" INSN "r\t%" #OPNO "%/" \ - : TARGET_ABICALLS \ + : TARGET_PIC_ABICALLS \ ? (".option\tpic0\n\t" \ "%*" INSN "\t%" #OPNO "%/\n\t" \ ".option\tpic2") \ Index: gcc/config/mips/vr.h =================================================================== --- gcc/config/mips/vr.h (revision 137143) +++ gcc/config/mips/vr.h (working copy) @@ -26,7 +26,8 @@ along with GCC; see the file COPYING3. MULTILIB_ABI_DEFAULT, \ DEFAULT_VR_ARCH } -#define DRIVER_SELF_SPECS \ +#undef SUBTARGET_SELF_SPECS +#define SUBTARGET_SELF_SPECS \ /* Enforce the default architecture. This is mostly for \ the assembler's benefit. */ \ "%{!march=*:%{!mfix-vr4120:%{!mfix-vr4130:" \ --vtzGhvizbBRQ85DL Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="gdb-nonpic.patch" 2008-03-07 Daniel Jacobowitz gdb/ * mips-tdep.c (mips32_scan_prologue): Stop scanning at branches. 2008-03-10 Daniel Jacobowitz gdb/ * mips-linux-tdep.c (mips_linux_in_dynsym_resolve_code): Update comments. (mips_linux_skip_resolver): Also use glibc_skip_solib_resolver. (mips_linux_init_abi): Do not override skip_trampoline_code. * configure.tgt (mips*-*-linux*): Add glibc-tdep.o. * mips-tdep.c (mips_stub_frame_sniffer): Use the stub frame sniffer for .MIPS.pic_stubs. (mips_skip_mips16_trampoline_code): Rename from mips_skip_trampoline_code. (mips_skip_pic_trampoline_code, mips_skip_trampoline_code): New. * infrun.c (handle_inferior_event): Do not check IN_SOLIB_DYNSYM_RESOLVE_CODE. Do not pass zero to in_solib_dynsym_resolve_code. * Makefile.in (mips-linux-tdep.o): Update. Index: gdb/Makefile.in =================================================================== RCS file: /scratch/gcc/repos/src/src/gdb/Makefile.in,v retrieving revision 1.1027 diff -u -p -r1.1027 Makefile.in --- gdb/Makefile.in 10 Jun 2008 10:23:53 -0000 1.1027 +++ gdb/Makefile.in 27 Jun 2008 14:28:26 -0000 @@ -2519,7 +2519,7 @@ mips-linux-tdep.o: mips-linux-tdep.c $(d $(gdb_assert_h) $(frame_h) $(regcache_h) $(trad_frame_h) \ $(tramp_frame_h) $(gdbtypes_h) $(solib_h) $(symtab_h) \ $(mips_linux_tdep_h) $(solist_h) $(solib_svr4_h) \ - $(target_descriptions_h) + $(target_descriptions_h) $(glibc_tdep_h) mipsnbsd-nat.o: mipsnbsd-nat.c $(defs_h) $(inferior_h) $(regcache_h) \ $(target_h) $(mips_tdep_h) $(mipsnbsd_tdep_h) $(inf_ptrace_h) mipsnbsd-tdep.o: mipsnbsd-tdep.c $(defs_h) $(gdbcore_h) $(regcache_h) \ Index: gdb/configure.tgt =================================================================== RCS file: /scratch/gcc/repos/src/src/gdb/configure.tgt,v retrieving revision 1.203 diff -u -p -r1.203 configure.tgt --- gdb/configure.tgt 1 May 2008 23:09:14 -0000 1.203 +++ gdb/configure.tgt 27 Jun 2008 14:28:26 -0000 @@ -297,7 +297,7 @@ mips*-sgi-irix6*) ;; mips*-*-linux*) # Target: Linux/MIPS - gdb_target_obs="mips-tdep.o mips-linux-tdep.o \ + gdb_target_obs="mips-tdep.o mips-linux-tdep.o glibc-tdep.o \ corelow.o solib.o solib-svr4.o symfile-mem.o" gdb_sim=../sim/mips/libsim.a build_gdbserver=yes Index: gdb/infrun.c =================================================================== RCS file: /scratch/gcc/repos/src/src/gdb/infrun.c,v retrieving revision 1.282 diff -u -p -r1.282 infrun.c --- gdb/infrun.c 24 Jun 2008 19:30:18 -0000 1.282 +++ gdb/infrun.c 27 Jun 2008 14:28:26 -0000 @@ -2863,12 +2863,7 @@ infrun: BPSTAT_WHAT_SET_LONGJMP_RESUME ( until we exit the run time loader code and reach the callee's address. */ if (step_over_calls == STEP_OVER_UNDEBUGGABLE -#ifdef IN_SOLIB_DYNSYM_RESOLVE_CODE - && IN_SOLIB_DYNSYM_RESOLVE_CODE (stop_pc) -#else - && in_solib_dynsym_resolve_code (stop_pc) -#endif - ) + && in_solib_dynsym_resolve_code (stop_pc)) { CORE_ADDR pc_after_resolver = gdbarch_skip_solib_resolver (current_gdbarch, stop_pc); @@ -2961,13 +2956,7 @@ infrun: BPSTAT_WHAT_SET_LONGJMP_RESUME ( if (real_stop_pc != 0) ecs->stop_func_start = real_stop_pc; - if ( -#ifdef IN_SOLIB_DYNSYM_RESOLVE_CODE - IN_SOLIB_DYNSYM_RESOLVE_CODE (ecs->stop_func_start) -#else - in_solib_dynsym_resolve_code (ecs->stop_func_start) -#endif -) + if (real_stop_pc != 0 && in_solib_dynsym_resolve_code (real_stop_pc)) { struct symtab_and_line sr_sal; init_sal (&sr_sal); Index: gdb/mips-linux-tdep.c =================================================================== RCS file: /scratch/gcc/repos/src/src/gdb/mips-linux-tdep.c,v retrieving revision 1.71 diff -u -p -r1.71 mips-linux-tdep.c --- gdb/mips-linux-tdep.c 30 Apr 2008 21:25:16 -0000 1.71 +++ gdb/mips-linux-tdep.c 27 Jun 2008 14:28:26 -0000 @@ -37,6 +37,7 @@ #include "symtab.h" #include "target-descriptions.h" #include "mips-linux-tdep.h" +#include "glibc-tdep.h" static struct target_so_ops mips_svr4_so_ops; @@ -666,13 +667,13 @@ mips_linux_in_dynsym_stub (CORE_ADDR pc, } /* Return non-zero iff PC belongs to the dynamic linker resolution - code or to a stub. */ + code, a PLT entry, or a lazy binding stub. */ static int mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) { /* Check whether PC is in the dynamic linker. This also checks - whether it is in the .plt section, which MIPS does not use. */ + whether it is in the .plt section, used by non-PIC executables. */ if (svr4_in_dynsym_resolve_code (pc)) return 1; @@ -688,8 +689,8 @@ mips_linux_in_dynsym_resolve_code (CORE_ and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc implementation of this triggers at "fixup" from the same objfile as "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at - "__dl_runtime_resolve" directly. An unresolved PLT entry will - point to _dl_runtime_resolve, which will first call + "__dl_runtime_resolve" directly. An unresolved lazy binding + stub will point to _dl_runtime_resolve, which will first call __dl_runtime_resolve, and then pass control to the resolved function. */ @@ -703,7 +704,7 @@ mips_linux_skip_resolver (struct gdbarch if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) return frame_pc_unwind (get_current_frame ()); - return 0; + return glibc_skip_solib_resolver (gdbarch, pc); } /* Signal trampoline support. There are four supported layouts for a @@ -1151,7 +1152,6 @@ mips_linux_init_abi (struct gdbarch_info break; } - set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); set_gdbarch_software_single_step (gdbarch, mips_software_single_step); Index: gdb/mips-tdep.c =================================================================== RCS file: /scratch/gcc/repos/src/src/gdb/mips-tdep.c,v retrieving revision 1.475 diff -u -p -r1.475 mips-tdep.c --- gdb/mips-tdep.c 3 Jun 2008 10:53:34 -0000 1.475 +++ gdb/mips-tdep.c 27 Jun 2008 14:29:07 -0000 @@ -1928,6 +1928,7 @@ mips32_scan_prologue (CORE_ADDR start_pc CORE_ADDR end_prologue_addr = 0; int seen_sp_adjust = 0; int load_immediate_bytes = 0; + int in_delay_slot = 0; struct gdbarch *gdbarch = get_frame_arch (this_frame); int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); @@ -2085,7 +2086,18 @@ restart: instructions? */ if (end_prologue_addr == 0) end_prologue_addr = cur_pc; + + /* Check for branches and jumps. For now, only jump to + register are caught (i.e. returns). */ + if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) + in_delay_slot = 1; } + + /* If the previous instruction was a jump, we must have reached + the end of the prologue by now. Stop scanning so that we do + not go past the function return. */ + if (in_delay_slot) + break; } if (this_cache != NULL) @@ -2303,6 +2315,13 @@ mips_stub_frame_sniffer (const struct fr ".MIPS.stubs") == 0) return 1; + /* Calling a PIC function from a non-PIC function passes through a stub + section; binutils calls it ".MIPS.pic_stubs". */ + if (s != NULL + && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), + ".MIPS.pic_stubs") == 0) + return 1; + return 0; } @@ -5020,7 +5039,7 @@ mips_breakpoint_from_pc (struct gdbarch gory details. */ static CORE_ADDR -mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) +mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) { char *name; CORE_ADDR start_addr; @@ -5099,6 +5118,67 @@ mips_skip_trampoline_code (struct frame_ return 0; /* not a stub */ } +/* If the current PC is the start of a non-PIC-to-PIC stub, return the + PC of the stub target. The stub just loads $t9 and jumps to it, + so that $t9 has the correct value at function entry. */ + +static CORE_ADDR +mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) +{ + struct obj_section *s; + int i; + gdb_byte stub_code[16]; + int32_t stub_words[4]; + + s = find_pc_section (pc); + if (s == NULL + || strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), + ".MIPS.pic_stubs") != 0) + return 0; + + if (target_read_memory (pc, stub_code, 16) != 0) + return 0; + for (i = 0; i < 4; i++) + stub_words[i] = extract_unsigned_integer (stub_code + i * 4, 4); + + /* A stub contains these instructions: + lui t9, %hi(target) + addiu t9, t9, %lo(target) + jr t9 + nop + + N64 stubs will require more instructions. */ + if ((stub_words[0] & 0xffff0000U) == 0x3c190000 + && (stub_words[1] & 0xffff0000U) == 0x27390000 + && stub_words[2] == 0x03200008 + && stub_words[3] == 0x00000000) + return (((stub_words[0] & 0x0000ffff) << 16) + + (stub_words[1] & 0x0000ffff)); + + /* Not a recognized stub. */ + return 0; +} + +static CORE_ADDR +mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) +{ + CORE_ADDR target_pc; + + target_pc = mips_skip_mips16_trampoline_code (frame, pc); + if (target_pc) + return target_pc; + + target_pc = find_solib_trampoline_target (frame, pc); + if (target_pc) + return target_pc; + + target_pc = mips_skip_pic_trampoline_code (frame, pc); + if (target_pc) + return target_pc; + + return 0; +} + /* Convert a dbx stab register number (from `r' declaration) to a GDB [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ --vtzGhvizbBRQ85DL Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="glibc-longlong.patch" 2008-06-27 Daniel Jacobowitz * longlong.h: Update from GCC. Index: stdlib/longlong.h =================================================================== RCS file: /cvs/glibc/libc/stdlib/longlong.h,v retrieving revision 1.31 diff -u -p -r1.31 longlong.h --- stdlib/longlong.h 15 May 2006 20:25:33 -0000 1.31 +++ stdlib/longlong.h 27 Jun 2008 13:05:23 -0000 @@ -229,6 +229,19 @@ UDItype __umulsidi3 (USItype, USItype); #define UDIV_TIME 100 #endif /* __arm__ */ +#if defined(__arm__) +/* Let gcc decide how best to implement count_leading_zeros. */ +#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X)) +#define COUNT_LEADING_ZEROS_0 32 +#endif + +#if defined (__CRIS__) && __CRIS_arch_version >= 3 +#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X)) +#if __CRIS_arch_version >= 8 +#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X)) +#endif +#endif /* __CRIS__ */ + #if defined (__hppa) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \ @@ -315,7 +328,7 @@ UDItype __umulsidi3 (USItype, USItype); #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ - __asm__ ("addl %5,%1\n\tadcl %3,%0" \ + __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \ : "=r" ((USItype) (sh)), \ "=&r" ((USItype) (sl)) \ : "%0" ((USItype) (ah)), \ @@ -323,7 +336,7 @@ UDItype __umulsidi3 (USItype, USItype); "%1" ((USItype) (al)), \ "g" ((USItype) (bl))) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ - __asm__ ("subl %5,%1\n\tsbbl %3,%0" \ + __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \ : "=r" ((USItype) (sh)), \ "=&r" ((USItype) (sl)) \ : "0" ((USItype) (ah)), \ @@ -331,31 +344,60 @@ UDItype __umulsidi3 (USItype, USItype); "1" ((USItype) (al)), \ "g" ((USItype) (bl))) #define umul_ppmm(w1, w0, u, v) \ - __asm__ ("mull %3" \ + __asm__ ("mul{l} %3" \ : "=a" ((USItype) (w0)), \ "=d" ((USItype) (w1)) \ : "%0" ((USItype) (u)), \ "rm" ((USItype) (v))) #define udiv_qrnnd(q, r, n1, n0, dv) \ - __asm__ ("divl %4" \ + __asm__ ("div{l} %4" \ : "=a" ((USItype) (q)), \ "=d" ((USItype) (r)) \ : "0" ((USItype) (n0)), \ "1" ((USItype) (n1)), \ "rm" ((USItype) (dv))) -#define count_leading_zeros(count, x) \ - do { \ - USItype __cbtmp; \ - __asm__ ("bsrl %1,%0" \ - : "=r" (__cbtmp) : "rm" ((USItype) (x))); \ - (count) = __cbtmp ^ 31; \ - } while (0) -#define count_trailing_zeros(count, x) \ - __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x))) +#define count_leading_zeros(count, x) ((count) = __builtin_clz (x)) +#define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x)) #define UMUL_TIME 40 #define UDIV_TIME 40 #endif /* 80x86 */ +#if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64 +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \ + : "=r" ((UDItype) (sh)), \ + "=&r" ((UDItype) (sl)) \ + : "%0" ((UDItype) (ah)), \ + "rme" ((UDItype) (bh)), \ + "%1" ((UDItype) (al)), \ + "rme" ((UDItype) (bl))) +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \ + : "=r" ((UDItype) (sh)), \ + "=&r" ((UDItype) (sl)) \ + : "0" ((UDItype) (ah)), \ + "rme" ((UDItype) (bh)), \ + "1" ((UDItype) (al)), \ + "rme" ((UDItype) (bl))) +#define umul_ppmm(w1, w0, u, v) \ + __asm__ ("mul{q} %3" \ + : "=a" ((UDItype) (w0)), \ + "=d" ((UDItype) (w1)) \ + : "%0" ((UDItype) (u)), \ + "rm" ((UDItype) (v))) +#define udiv_qrnnd(q, r, n1, n0, dv) \ + __asm__ ("div{q} %4" \ + : "=a" ((UDItype) (q)), \ + "=d" ((UDItype) (r)) \ + : "0" ((UDItype) (n0)), \ + "1" ((UDItype) (n1)), \ + "rm" ((UDItype) (dv))) +#define count_leading_zeros(count, x) ((count) = __builtin_clzl (x)) +#define count_trailing_zeros(count, x) ((count) = __builtin_ctzl (x)) +#define UMUL_TIME 40 +#define UDIV_TIME 40 +#endif /* x86_64 */ + #if defined (__i960__) && W_TYPE_SIZE == 32 #define umul_ppmm(w1, w0, u, v) \ ({union {UDItype __ll; \ @@ -523,6 +565,11 @@ UDItype __umulsidi3 (USItype, USItype); __asm__ ("bfffo %1{%b2:%b2},%0" \ : "=d" ((USItype) (count)) \ : "od" ((USItype) (x)), "n" (0)) +/* Some ColdFire architectures have a ff1 instruction supported via + __builtin_clz. */ +#elif defined (__mcfisaaplus__) || defined (__mcfisac__) +#define count_leading_zeros(count,x) ((count) = __builtin_clz (x)) +#define COUNT_LEADING_ZEROS_0 32 #endif #endif /* mc68000 */ @@ -585,14 +632,19 @@ UDItype __umulsidi3 (USItype, USItype); #endif /* __m88000__ */ #if defined (__mips__) && W_TYPE_SIZE == 32 -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("multu %2,%3" \ - : "=l" ((USItype) (w0)), \ - "=h" ((USItype) (w1)) \ - : "d" ((USItype) (u)), \ - "d" ((USItype) (v))) +#define umul_ppmm(w1, w0, u, v) \ + do { \ + UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \ + (w1) = (USItype) (__x >> 32); \ + (w0) = (USItype) (__x); \ + } while (0) #define UMUL_TIME 10 #define UDIV_TIME 100 + +#if (__mips == 32 || __mips == 64) && ! __mips16 +#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X)) +#define COUNT_LEADING_ZEROS_0 32 +#endif #endif /* __mips__ */ #if defined (__ns32000__) && W_TYPE_SIZE == 32 @@ -641,7 +693,9 @@ UDItype __umulsidi3 (USItype, USItype); || defined (__powerpc__) /* gcc */ \ || defined (__POWERPC__) /* BEOS */ \ || defined (__ppc__) /* Darwin */ \ - || defined (PPC) /* GNU/Linux, SysV */ \ + || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \ + || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \ + && CPU_FAMILY == PPC) \ ) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ do { \ @@ -679,7 +733,10 @@ UDItype __umulsidi3 (USItype, USItype); __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x)) #define COUNT_LEADING_ZEROS_0 32 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \ - || defined (__ppc__) || defined (PPC) + || defined (__ppc__) \ + || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \ + || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \ + && CPU_FAMILY == PPC) #define umul_ppmm(ph, pl, m0, m1) \ do { \ USItype __m0 = (m0), __m1 = (m1); \ @@ -828,18 +885,51 @@ UDItype __umulsidi3 (USItype, USItype); } while (0) #endif -#if defined (__sh2__) && W_TYPE_SIZE == 32 +#if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32 +#ifndef __sh1__ #define umul_ppmm(w1, w0, u, v) \ __asm__ ( \ - "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \ - : "=r" ((USItype)(w1)), \ - "=r" ((USItype)(w0)) \ + "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \ + : "=r<" ((USItype)(w1)), \ + "=r<" ((USItype)(w0)) \ : "r" ((USItype)(u)), \ "r" ((USItype)(v)) \ : "macl", "mach") #define UMUL_TIME 5 #endif +/* This is the same algorithm as __udiv_qrnnd_c. */ +#define UDIV_NEEDS_NORMALIZATION 1 + +#define udiv_qrnnd(q, r, n1, n0, d) \ + do { \ + extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \ + __attribute__ ((visibility ("hidden"))); \ + /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \ + __asm__ ( \ + "mov%M4 %4,r5\n" \ +" swap.w %3,r4\n" \ +" swap.w r5,r6\n" \ +" jsr @%5\n" \ +" shll16 r6\n" \ +" swap.w r4,r4\n" \ +" jsr @%5\n" \ +" swap.w r1,%0\n" \ +" or r1,%0" \ + : "=r" (q), "=&z" (r) \ + : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \ + : "r1", "r2", "r4", "r5", "r6", "pr"); \ + } while (0) + +#define UDIV_TIME 80 + +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("clrt;subc %5,%1; subc %4,%0" \ + : "=r" (sh), "=r" (sl) \ + : "0" (ah), "1" (al), "r" (bh), "r" (bl)) + +#endif /* __sh__ */ + #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v) #define count_leading_zeros(count, x) \ @@ -1153,6 +1243,23 @@ UDItype __umulsidi3 (USItype, USItype); } while (0) #endif /* __vax__ */ +#if defined (__xtensa__) && W_TYPE_SIZE == 32 +/* This code is not Xtensa-configuration-specific, so rely on the compiler + to expand builtin functions depending on what configuration features + are available. This avoids library calls when the operation can be + performed in-line. */ +#define umul_ppmm(w1, w0, u, v) \ + do { \ + DWunion __w; \ + __w.ll = __builtin_umulsidi3 (u, v); \ + w1 = __w.s.high; \ + w0 = __w.s.low; \ + } while (0) +#define __umulsidi3(u, v) __builtin_umulsidi3 (u, v) +#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X)) +#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X)) +#endif /* __xtensa__ */ + #if defined (__z8000__) && W_TYPE_SIZE == 16 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \ --vtzGhvizbBRQ85DL Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="glibc-ports-nonpic.patch" 2008-03-28 Mark Shinwell Daniel Jacobowitz * sysdeps/mips/dl-lookup.c: New. * sysdeps/mips/do-lookup.h: New. * sysdeps/mips/dl-machine.h (ELF_MACHINE_NO_PLT): Remove definition. (ELF_MACHINE_JMP_SLOT): Alter definition and update comment. (elf_machine_type_class): Likewise. (ELF_MACHINE_PLT_REL): Define. (elf_machine_fixup_plt): New. (elf_machine_plt_value): New. (elf_machine_reloc): Handle jump slot and copy relocations. (elf_machine_lazy_rel): Point relocation place at PLT if required. (elf_machine_runtime_setup): Fill in .got.plt header. * sysdeps/mips/dl-trampoline.c: New. * sysdeps/mips/bits/linkmap.h (link_map_machine): New. * sysdeps/mips/tls-macros.h: Load $gp as required. * sysdeps/unix/sysv/linux/mips/mips32/sysdep.h (SYSCALL_ERROR_LABEL): Delete definition. * sysdeps/unix/sysv/linux/mips/nptl/sysdep-cancel.h (PSEUDO_CPLOAD, PSEUDO_ERRJMP, PSEUDO_SAVEGP, PSEUDO_LOADGP): Define. (PSEUDO): Use them. Move outside __PIC__. (PSEUDO_JMP): New. (CENABLE, CDISABLE): Use it. Index: sysdeps/unix/sysv/linux/mips/mips32/sysdep.h =================================================================== --- sysdeps/unix/sysv/linux/mips/mips32/sysdep.h (revision 213009) +++ sysdeps/unix/sysv/linux/mips/mips32/sysdep.h (working copy) @@ -35,15 +35,7 @@ # define SYS_ify(syscall_name) __NR_/**/syscall_name #endif -#ifdef __ASSEMBLER__ - -/* We don't want the label for the error handler to be visible in the symbol - table when we define it here. */ -#ifdef __PIC__ -# define SYSCALL_ERROR_LABEL 99b -#endif - -#else /* ! __ASSEMBLER__ */ +#ifndef __ASSEMBLER__ /* Define a macro which expands into the inline wrapper code for a system call. */ Index: sysdeps/unix/sysv/linux/mips/nptl/sysdep-cancel.h =================================================================== --- sysdeps/unix/sysv/linux/mips/nptl/sysdep-cancel.h (revision 213009) +++ sysdeps/unix/sysv/linux/mips/nptl/sysdep-cancel.h (working copy) @@ -25,28 +25,38 @@ #if !defined NOT_IN_libc || defined IS_IN_libpthread || defined IS_IN_librt -#ifdef __PIC__ +# ifdef __PIC__ +# define PSEUDO_CPLOAD .cpload t9; +# define PSEUDO_ERRJMP la t9, __syscall_error; jr t9; +# define PSEUDO_SAVEGP sw gp, 32(sp); cfi_rel_offset (gp, 32); +# define PSEUDO_LOADGP lw gp, 32(sp); +# else +# define PSEUDO_CPLOAD +# define PSEUDO_ERRJMP j __syscall_error; +# define PSEUDO_SAVEGP +# define PSEUDO_LOADGP +# endif + # undef PSEUDO # define PSEUDO(name, syscall_name, args) \ .align 2; \ L(pseudo_start): \ cfi_startproc; \ - 99: la t9,__syscall_error; \ - jr t9; \ + 99: PSEUDO_ERRJMP \ .type __##syscall_name##_nocancel, @function; \ .globl __##syscall_name##_nocancel; \ __##syscall_name##_nocancel: \ .set noreorder; \ - .cpload t9; \ + PSEUDO_CPLOAD \ li v0, SYS_ify(syscall_name); \ syscall; \ .set reorder; \ - bne a3, zero, SYSCALL_ERROR_LABEL; \ + bne a3, zero, 99b; \ ret; \ .size __##syscall_name##_nocancel,.-__##syscall_name##_nocancel; \ ENTRY (name) \ .set noreorder; \ - .cpload t9; \ + PSEUDO_CPLOAD \ .set reorder; \ SINGLE_THREAD_P(v1); \ bne zero, v1, L(pseudo_cancel); \ @@ -54,17 +64,16 @@ li v0, SYS_ify(syscall_name); \ syscall; \ .set reorder; \ - bne a3, zero, SYSCALL_ERROR_LABEL; \ + bne a3, zero, 99b; \ ret; \ L(pseudo_cancel): \ SAVESTK_##args; \ sw ra, 28(sp); \ cfi_rel_offset (ra, 28); \ - sw gp, 32(sp); \ - cfi_rel_offset (gp, 32); \ + PSEUDO_SAVEGP \ PUSHARGS_##args; /* save syscall args */ \ CENABLE; \ - lw gp, 32(sp); \ + PSEUDO_LOADGP \ sw v0, 44(sp); /* save mask */ \ POPARGS_##args; /* restore syscall args */ \ .set noreorder; \ @@ -75,12 +84,12 @@ sw a3, 40(sp); /* save syscall error flag */ \ lw a0, 44(sp); /* pass mask as arg1 */ \ CDISABLE; \ - lw gp, 32(sp); \ + PSEUDO_LOADGP \ lw v0, 36(sp); /* restore syscall result */ \ lw a3, 40(sp); /* restore syscall error flag */ \ lw ra, 28(sp); /* restore return address */ \ .set noreorder; \ - bne a3, zero, SYSCALL_ERROR_LABEL; \ + bne a3, zero, 99b; \ RESTORESTK; \ L(pseudo_end): \ .set reorder; @@ -88,8 +97,6 @@ # undef PSEUDO_END # define PSEUDO_END(sym) cfi_endproc; .end sym; .size sym,.-sym -#endif - # define PUSHARGS_0 /* nothing to do */ # define PUSHARGS_1 PUSHARGS_0 sw a0, 0(sp); cfi_rel_offset (a0, 0); # define PUSHARGS_2 PUSHARGS_1 sw a1, 4(sp); cfi_rel_offset (a1, 4); @@ -136,19 +143,25 @@ # define RESTORESTK addu sp, STKSPACE; cfi_adjust_cfa_offset(-STKSPACE) +# ifdef __PIC__ /* We use jalr rather than jal. This means that the assembler will not automatically restore $gp (in case libc has multiple GOTs) so we must do it manually - which we have to do anyway since we don't use .cprestore. It also shuts up the assembler warning about not using .cprestore. */ +# define PSEUDO_JMP(sym) la t9, sym; jalr t9; +# else +# define PSEUDO_JMP(sym) jal sym; +# endif + # ifdef IS_IN_libpthread -# define CENABLE la t9, __pthread_enable_asynccancel; jalr t9; -# define CDISABLE la t9, __pthread_disable_asynccancel; jalr t9; +# define CENABLE PSEUDO_JMP (__pthread_enable_asynccancel) +# define CDISABLE PSEUDO_JMP (__pthread_disable_asynccancel) # elif defined IS_IN_librt -# define CENABLE la t9, __librt_enable_asynccancel; jalr t9; -# define CDISABLE la t9, __librt_disable_asynccancel; jalr t9; +# define CENABLE PSEUDO_JMP (__librt_enable_asynccancel) +# define CDISABLE PSEUDO_JMP (__librt_disable_asynccancel) # else -# define CENABLE la t9, __libc_enable_asynccancel; jalr t9; -# define CDISABLE la t9, __libc_disable_asynccancel; jalr t9; +# define CENABLE PSEUDO_JMP (__libc_enable_asynccancel) +# define CDISABLE PSEUDO_JMP (__libc_disable_asynccancel) # endif # ifndef __ASSEMBLER__ Index: sysdeps/mips/do-lookup.h =================================================================== --- sysdeps/mips/do-lookup.h (revision 0) +++ sysdeps/mips/do-lookup.h (revision 0) @@ -0,0 +1,37 @@ +/* MIPS-specific veneer to GLIBC's do-lookup.h. + Copyright (C) 2008 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +/* The semantics of zero/non-zero values of undefined symbols differs + depending on whether the non-PIC ABI is in use. Under the non-PIC ABI, + a non-zero value indicates that there is an address reference to the + symbol and thus it must always be resolved (except when resolving a jump + slot relocation) to the PLT entry whose address is provided as the + symbol's value; a zero value indicates that this canonical-address + behaviour is not required. Yet under the classic MIPS psABI, a zero value + indicates that there is an address reference to the function and the + dynamic linker must resolve the symbol immediately upon loading. To + avoid conflict, symbols for which the dynamic linker must assume the + non-PIC ABI semantics are marked with the STO_MIPS_PLT flag. The + following ugly hack causes the code in the platform-independent + do-lookup.h file to check this flag correctly. */ +#define st_value st_shndx == SHN_UNDEF && !(sym->st_other & STO_MIPS_PLT)) \ + || (sym->st_value +#include_next "do-lookup.h" +#undef st_value + Index: sysdeps/mips/tls-macros.h =================================================================== --- sysdeps/mips/tls-macros.h (revision 213009) +++ sysdeps/mips/tls-macros.h (working copy) @@ -4,27 +4,27 @@ /* These versions are for o32 and n32. */ -# define TLS_GD(x) \ - ({ void *__result; \ - extern void *__tls_get_addr (void *); \ - asm ("addiu %0, $28, %%tlsgd(" #x ")" \ - : "=r" (__result)); \ - (int *)__tls_get_addr (__result); }) +#ifndef __PIC__ +# define LOAD_GP "move %[tmp], $28\n\tla $28, __gnu_local_gp\n\t" +# define UNLOAD_GP "\n\tmove $28, %[tmp]" #else +# define LOAD_GP +# define UNLOAD_GP +#endif + # define TLS_GD(x) \ - ({ void *__result; \ + ({ void *__result, *__tmp; \ extern void *__tls_get_addr (void *); \ - asm ("daddiu %0, $28, %%tlsgd(" #x ")" \ - : "=r" (__result)); \ + asm (LOAD_GP "addiu %0, $28, %%tlsgd(" #x ")" \ + UNLOAD_GP \ + : "=r" (__result), [tmp] "=&r" (__tmp)); \ (int *)__tls_get_addr (__result); }) -#endif - -#if _MIPS_SIM != _ABI64 # define TLS_LD(x) \ - ({ void *__result; \ + ({ void *__result, *__tmp; \ extern void *__tls_get_addr (void *); \ - asm ("addiu %0, $28, %%tlsldm(" #x ")" \ - : "=r" (__result)); \ + asm (LOAD_GP "addiu %0, $28, %%tlsldm(" #x ")" \ + UNLOAD_GP \ + : "=r" (__result), [tmp] "=&r" (__tmp)); \ __result = __tls_get_addr (__result); \ asm ("lui $3,%%dtprel_hi(" #x ")\n\t" \ "addiu $3,$3,%%dtprel_lo(" #x ")\n\t" \ @@ -32,13 +32,15 @@ : "+r" (__result) : : "$3"); \ __result; }) # define TLS_IE(x) \ - ({ void *__result; \ + ({ void *__result, *__tmp; \ asm (".set push\n\t.set mips32r2\n\t" \ "rdhwr\t%0,$29\n\t.set pop" \ : "=v" (__result)); \ - asm ("lw $3,%%gottprel(" #x ")($28)\n\t" \ + asm (LOAD_GP "lw $3,%%gottprel(" #x ")($28)\n\t" \ "addu %0,%0,$3" \ - : "+r" (__result) : : "$3"); \ + UNLOAD_GP \ + : "+r" (__result), [tmp] "=&r" (__tmp) \ + : : "$3"); \ __result; }) # define TLS_LE(x) \ ({ void *__result; \ @@ -55,6 +57,12 @@ /* These versions are for n64. */ +# define TLS_GD(x) \ + ({ void *__result; \ + extern void *__tls_get_addr (void *); \ + asm ("daddiu %0, $28, %%tlsgd(" #x ")" \ + : "=r" (__result)); \ + (int *)__tls_get_addr (__result); }) # define TLS_LD(x) \ ({ void *__result; \ extern void *__tls_get_addr (void *); \ Index: sysdeps/mips/dl-machine.h =================================================================== --- sysdeps/mips/dl-machine.h (revision 213009) +++ sysdeps/mips/dl-machine.h (working copy) @@ -25,8 +25,6 @@ #define ELF_MACHINE_NAME "MIPS" -#define ELF_MACHINE_NO_PLT - #include #ifndef ENTRY_POINT @@ -56,10 +54,15 @@ #endif /* A reloc type used for ld.so cmdline arg lookups to reject PLT entries. - This makes no sense on MIPS but we have to define this to R_MIPS_REL32 - to avoid the asserts in dl-lookup.c from blowing. */ -#define ELF_MACHINE_JMP_SLOT R_MIPS_REL32 -#define elf_machine_type_class(type) ELF_RTYPE_CLASS_PLT + This makes no sense on MIPS unless using the non-PIC ABI but we have + to define this to avoid the asserts in dl-lookup.c from blowing. + We choose the value that makes sense for the non-PIC ABI. */ +#define ELF_MACHINE_JMP_SLOT R_MIPS_JUMP_SLOT +#define elf_machine_type_class(type) \ + ((((type) == ELF_MACHINE_JMP_SLOT) * ELF_RTYPE_CLASS_PLT) \ + | (((type) == R_MIPS_COPY) * ELF_RTYPE_CLASS_COPY)) + +#define ELF_MACHINE_PLT_REL 1 /* Translate a processor specific dynamic tag to the index in l_info array. */ @@ -73,6 +76,14 @@ do { if ((l)->l_info[DT_MIPS (RLD_MAP)]) (ElfW(Addr)) (r); \ } while (0) +/* Allow ABIVERSION == 1, meaning non-PIC abicalls. */ +#define VALID_ELF_ABIVERSION(ver) (ver == 0 || ver == 2) +#define VALID_ELF_OSABI(osabi) (osabi == ELFOSABI_SYSV) +#define VALID_ELF_HEADER(hdr,exp,size) \ + memcmp (hdr,exp,size-2) == 0 \ + && VALID_ELF_OSABI (hdr[EI_OSABI]) \ + && VALID_ELF_ABIVERSION (hdr[EI_ABIVERSION]) + /* Return nonzero iff ELF header is compatible with the running host. */ static inline int __attribute_used__ elf_machine_matches_host (const ElfW(Ehdr) *ehdr) @@ -294,6 +305,24 @@ do { \ # define ARCH_LA_PLTEXIT mips_n64_gnu_pltexit # endif +/* For a non-writable PLT, rewrite the .got.plt entry at RELOC_ADDR to + point at the symbol with address VALUE. For a writable PLT, rewrite + the corresponding PLT entry instead. */ +static inline Elf32_Addr +elf_machine_fixup_plt (struct link_map *map, lookup_t t, + const Elf32_Rel *reloc, + Elf32_Addr *reloc_addr, Elf32_Addr value) +{ + return *reloc_addr = value; +} + +static inline Elf32_Addr +elf_machine_plt_value (struct link_map *map, const Elf32_Rel *reloc, + Elf32_Addr value) +{ + return value; +} + #endif /* !dl_machine_h */ #ifdef RESOLVE_MAP @@ -461,6 +490,60 @@ elf_machine_reloc (struct link_map *map, #endif case R_MIPS_NONE: /* Alright, Wilbur. */ break; + + case R_MIPS_JUMP_SLOT: + { + /* Handle a jump slot relocation (only for the non-PIC ABI). */ + + struct link_map *sym_map; + Elf32_Addr value; + + /* The addend for a jump slot relocation must always be zero: + calls via the PLT always branch to the symbol's address and + not to the address plus a non-zero offset. */ + if (r_addend != 0) + _dl_signal_error (0, map->l_name, NULL, + "found jump slot relocation with non-zero addend"); + + sym_map = RESOLVE_MAP (&sym, version, r_type); + value = sym_map == NULL ? 0 : sym_map->l_addr + sym->st_value; + *addr_field = value; + + break; + } + + case R_MIPS_COPY: + { + /* Handle a copy relocation (only for the non-PIC ABI). */ + + const Elf32_Sym *const refsym = sym; + struct link_map *sym_map; + Elf32_Addr value; + + /* Calculate the address of the symbol. */ + sym_map = RESOLVE_MAP (&sym, version, r_type); + value = sym_map == NULL ? 0 : sym_map->l_addr + sym->st_value; + + if (sym == NULL) + /* This can happen in trace mode if an object could not be + found. */ + break; + if (sym->st_size > refsym->st_size + || (GLRO(dl_verbose) && sym->st_size < refsym->st_size)) + { + const char *strtab; + + strtab = (const void *) D_PTR (map, l_info[DT_STRTAB]); + _dl_error_printf ("\ + %s: Symbol `%s' has different size in shared object, consider re-linking\n", + rtld_progname ?: "", + strtab + refsym->st_name); + } + memcpy (reloc_addr, (void *) value, + MIN (sym->st_size, refsym->st_size)); + break; + } + #if _MIPS_SIM == _ABI64 case R_MIPS_64: /* For full compliance with the ELF64 ABI, one must precede the @@ -505,9 +588,23 @@ elf_machine_rel_relative (ElfW(Addr) l_a auto inline void __attribute__((always_inline)) elf_machine_lazy_rel (struct link_map *map, - ElfW(Addr) l_addr, const ElfW(Rela) *reloc) + ElfW(Addr) l_addr, const ElfW(Rel) *reloc) { - /* Do nothing. */ + Elf32_Addr *const reloc_addr = (void *) (l_addr + reloc->r_offset); + const unsigned int r_type = ELF32_R_TYPE (reloc->r_info); + /* Check for unexpected PLT reloc type. */ + if (__builtin_expect (r_type == R_MIPS_JUMP_SLOT, 1)) + { + if (__builtin_expect (map->l_mach.plt, 0) == 0) + { + /* Nothing is required here since we only support lazy + relocation in executables. */ + } + else + *reloc_addr = map->l_mach.plt; + } + else + _dl_reloc_bad_type (map, r_type, 1); } auto inline void @@ -650,6 +747,22 @@ elf_machine_runtime_setup (struct link_m /* Relocate global offset table. */ elf_machine_got_rel (l, lazy); + /* If using the non-PIC ABI, fill in the first two entries of + .got.plt. */ + if (l->l_info[DT_JMPREL] && lazy) + { + extern void _dl_runtime_pltresolve (void); + Elf32_Addr *gotplt; + gotplt = (Elf32_Addr *) D_PTR (l, l_info[DT_MIPS (PLTGOT)]); + /* If a library is prelinked but we have to relocate anyway, + we have to be able to undo the prelinking of .got.plt. + The prelinker saved the address of .plt for us here. */ + if (gotplt[1]) + l->l_mach.plt = gotplt[1] + l->l_addr; + gotplt[0] = (Elf32_Addr) &_dl_runtime_pltresolve; + gotplt[1] = (Elf32_Addr) l; + } + # endif return lazy; } Index: sysdeps/mips/dl-lookup.c =================================================================== --- sysdeps/mips/dl-lookup.c (revision 0) +++ sysdeps/mips/dl-lookup.c (revision 0) @@ -0,0 +1,581 @@ +/* Look up a symbol in the loaded objects. + MIPS/Linux version - this is identical to the common version, but + because it is in sysdeps/mips, it gets sysdeps/mips/do-lookup.h. + Using instead of "do-lookup.h" would work too. + + Copyright (C) 1995-2005, 2006, 2007 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define VERSTAG(tag) (DT_NUM + DT_THISPROCNUM + DT_VERSIONTAGIDX (tag)) + +/* We need this string more than once. */ +static const char undefined_msg[] = "undefined symbol: "; + + +struct sym_val + { + const ElfW(Sym) *s; + struct link_map *m; + }; + + +#define make_string(string, rest...) \ + ({ \ + const char *all[] = { string, ## rest }; \ + size_t len, cnt; \ + char *result, *cp; \ + \ + len = 1; \ + for (cnt = 0; cnt < sizeof (all) / sizeof (all[0]); ++cnt) \ + len += strlen (all[cnt]); \ + \ + cp = result = alloca (len); \ + for (cnt = 0; cnt < sizeof (all) / sizeof (all[0]); ++cnt) \ + cp = __stpcpy (cp, all[cnt]); \ + \ + result; \ + }) + +/* Statistics function. */ +#ifdef SHARED +# define bump_num_relocations() ++GL(dl_num_relocations) +#else +# define bump_num_relocations() ((void) 0) +#endif + + +/* The actual lookup code. */ +#include "do-lookup.h" + + +static uint_fast32_t +dl_new_hash (const char *s) +{ + uint_fast32_t h = 5381; + for (unsigned char c = *s; c != '\0'; c = *++s) + h = h * 33 + c; + return h & 0xffffffff; +} + + +/* Add extra dependency on MAP to UNDEF_MAP. */ +static int +internal_function +add_dependency (struct link_map *undef_map, struct link_map *map, int flags) +{ + struct link_map *runp; + unsigned int i; + int result = 0; + + /* Avoid self-references and references to objects which cannot be + unloaded anyway. */ + if (undef_map == map) + return 0; + + /* Avoid references to objects which cannot be unloaded anyway. */ + assert (map->l_type == lt_loaded); + if ((map->l_flags_1 & DF_1_NODELETE) != 0) + return 0; + + struct link_map_reldeps *l_reldeps + = atomic_forced_read (undef_map->l_reldeps); + + /* Make sure l_reldeps is read before l_initfini. */ + atomic_read_barrier (); + + /* Determine whether UNDEF_MAP already has a reference to MAP. First + look in the normal dependencies. */ + struct link_map **l_initfini = atomic_forced_read (undef_map->l_initfini); + if (l_initfini != NULL) + { + for (i = 0; l_initfini[i] != NULL; ++i) + if (l_initfini[i] == map) + return 0; + } + + /* No normal dependency. See whether we already had to add it + to the special list of dynamic dependencies. */ + unsigned int l_reldepsact = 0; + if (l_reldeps != NULL) + { + struct link_map **list = &l_reldeps->list[0]; + l_reldepsact = l_reldeps->act; + for (i = 0; i < l_reldepsact; ++i) + if (list[i] == map) + return 0; + } + + /* Save serial number of the target MAP. */ + unsigned long long serial = map->l_serial; + + /* Make sure nobody can unload the object while we are at it. */ + if (__builtin_expect (flags & DL_LOOKUP_GSCOPE_LOCK, 0)) + { + /* We can't just call __rtld_lock_lock_recursive (GL(dl_load_lock)) + here, that can result in ABBA deadlock. */ + THREAD_GSCOPE_RESET_FLAG (); + __rtld_lock_lock_recursive (GL(dl_load_lock)); + /* While MAP value won't change, after THREAD_GSCOPE_RESET_FLAG () + it can e.g. point to unallocated memory. So avoid the optimizer + treating the above read from MAP->l_serial as ensurance it + can safely dereference it. */ + map = atomic_forced_read (map); + + /* From this point on it is unsafe to dereference MAP, until it + has been found in one of the lists. */ + + /* Redo the l_initfini check in case undef_map's l_initfini + changed in the mean time. */ + if (undef_map->l_initfini != l_initfini + && undef_map->l_initfini != NULL) + { + l_initfini = undef_map->l_initfini; + for (i = 0; l_initfini[i] != NULL; ++i) + if (l_initfini[i] == map) + goto out_check; + } + + /* Redo the l_reldeps check if undef_map's l_reldeps changed in + the mean time. */ + if (undef_map->l_reldeps != NULL) + { + if (undef_map->l_reldeps != l_reldeps) + { + struct link_map **list = &undef_map->l_reldeps->list[0]; + l_reldepsact = undef_map->l_reldeps->act; + for (i = 0; i < l_reldepsact; ++i) + if (list[i] == map) + goto out_check; + } + else if (undef_map->l_reldeps->act > l_reldepsact) + { + struct link_map **list + = &undef_map->l_reldeps->list[0]; + i = l_reldepsact; + l_reldepsact = undef_map->l_reldeps->act; + for (; i < l_reldepsact; ++i) + if (list[i] == map) + goto out_check; + } + } + } + else + __rtld_lock_lock_recursive (GL(dl_load_lock)); + + /* The object is not yet in the dependency list. Before we add + it make sure just one more time the object we are about to + reference is still available. There is a brief period in + which the object could have been removed since we found the + definition. */ + runp = GL(dl_ns)[undef_map->l_ns]._ns_loaded; + while (runp != NULL && runp != map) + runp = runp->l_next; + + if (runp != NULL) + { + /* The object is still available. */ + + /* MAP could have been dlclosed, freed and then some other dlopened + library could have the same link_map pointer. */ + if (map->l_serial != serial) + goto out_check; + + /* Redo the NODELETE check, as when dl_load_lock wasn't held + yet this could have changed. */ + if ((map->l_flags_1 & DF_1_NODELETE) != 0) + goto out; + + /* If the object with the undefined reference cannot be removed ever + just make sure the same is true for the object which contains the + definition. */ + if (undef_map->l_type != lt_loaded + || (undef_map->l_flags_1 & DF_1_NODELETE) != 0) + { + map->l_flags_1 |= DF_1_NODELETE; + goto out; + } + + /* Add the reference now. */ + if (__builtin_expect (l_reldepsact >= undef_map->l_reldepsmax, 0)) + { + /* Allocate more memory for the dependency list. Since this + can never happen during the startup phase we can use + `realloc'. */ + struct link_map_reldeps *newp; + unsigned int max + = undef_map->l_reldepsmax ? undef_map->l_reldepsmax * 2 : 10; + + newp = malloc (sizeof (*newp) + max * sizeof (struct link_map *)); + if (newp == NULL) + { + /* If we didn't manage to allocate memory for the list this is + no fatal problem. We simply make sure the referenced object + cannot be unloaded. This is semantically the correct + behavior. */ + map->l_flags_1 |= DF_1_NODELETE; + goto out; + } + else + { + if (l_reldepsact) + memcpy (&newp->list[0], &undef_map->l_reldeps->list[0], + l_reldepsact * sizeof (struct link_map *)); + newp->list[l_reldepsact] = map; + newp->act = l_reldepsact + 1; + atomic_write_barrier (); + void *old = undef_map->l_reldeps; + undef_map->l_reldeps = newp; + undef_map->l_reldepsmax = max; + if (old) + _dl_scope_free (old); + } + } + else + { + undef_map->l_reldeps->list[l_reldepsact] = map; + atomic_write_barrier (); + undef_map->l_reldeps->act = l_reldepsact + 1; + } + + /* Display information if we are debugging. */ + if (__builtin_expect (GLRO(dl_debug_mask) & DL_DEBUG_FILES, 0)) + _dl_debug_printf ("\ +\nfile=%s [%lu]; needed by %s [%lu] (relocation dependency)\n\n", + map->l_name[0] ? map->l_name : rtld_progname, + map->l_ns, + undef_map->l_name[0] + ? undef_map->l_name : rtld_progname, + undef_map->l_ns); + } + else + /* Whoa, that was bad luck. We have to search again. */ + result = -1; + + out: + /* Release the lock. */ + __rtld_lock_unlock_recursive (GL(dl_load_lock)); + + if (__builtin_expect (flags & DL_LOOKUP_GSCOPE_LOCK, 0)) + THREAD_GSCOPE_SET_FLAG (); + + return result; + + out_check: + if (map->l_serial != serial) + result = -1; + goto out; +} + +static void +internal_function +_dl_debug_bindings (const char *undef_name, struct link_map *undef_map, + const ElfW(Sym) **ref, struct sym_val *value, + const struct r_found_version *version, int type_class, + int protected); + + +/* Search loaded objects' symbol tables for a definition of the symbol + UNDEF_NAME, perhaps with a requested version for the symbol. + + We must never have calls to the audit functions inside this function + or in any function which gets called. If this would happen the audit + code might create a thread which can throw off all the scope locking. */ +lookup_t +internal_function +_dl_lookup_symbol_x (const char *undef_name, struct link_map *undef_map, + const ElfW(Sym) **ref, + struct r_scope_elem *symbol_scope[], + const struct r_found_version *version, + int type_class, int flags, struct link_map *skip_map) +{ + const uint_fast32_t new_hash = dl_new_hash (undef_name); + unsigned long int old_hash = 0xffffffff; + struct sym_val current_value = { NULL, NULL }; + struct r_scope_elem **scope = symbol_scope; + + bump_num_relocations (); + + /* No other flag than DL_LOOKUP_ADD_DEPENDENCY or DL_LOOKUP_GSCOPE_LOCK + is allowed if we look up a versioned symbol. */ + assert (version == NULL + || (flags & ~(DL_LOOKUP_ADD_DEPENDENCY | DL_LOOKUP_GSCOPE_LOCK)) + == 0); + + size_t i = 0; + if (__builtin_expect (skip_map != NULL, 0)) + /* Search the relevant loaded objects for a definition. */ + while ((*scope)->r_list[i] != skip_map) + ++i; + + /* Search the relevant loaded objects for a definition. */ + for (size_t start = i; *scope != NULL; start = 0, ++scope) + { + int res = do_lookup_x (undef_name, new_hash, &old_hash, *ref, + ¤t_value, *scope, start, version, flags, + skip_map, type_class); + if (res > 0) + break; + + if (__builtin_expect (res, 0) < 0 && skip_map == NULL) + { + /* Oh, oh. The file named in the relocation entry does not + contain the needed symbol. This code is never reached + for unversioned lookups. */ + assert (version != NULL); + const char *reference_name = undef_map ? undef_map->l_name : NULL; + + /* XXX We cannot translate the message. */ + _dl_signal_cerror (0, (reference_name[0] + ? reference_name + : (rtld_progname ?: "
")), + N_("relocation error"), + make_string ("symbol ", undef_name, ", version ", + version->name, + " not defined in file ", + version->filename, + " with link time reference", + res == -2 + ? " (no version symbols)" : "")); + *ref = NULL; + return 0; + } + } + + if (__builtin_expect (current_value.s == NULL, 0)) + { + if ((*ref == NULL || ELFW(ST_BIND) ((*ref)->st_info) != STB_WEAK) + && skip_map == NULL) + { + /* We could find no value for a strong reference. */ + const char *reference_name = undef_map ? undef_map->l_name : ""; + const char *versionstr = version ? ", version " : ""; + const char *versionname = (version && version->name + ? version->name : ""); + + /* XXX We cannot translate the message. */ + _dl_signal_cerror (0, (reference_name[0] + ? reference_name + : (rtld_progname ?: "
")), + N_("symbol lookup error"), + make_string (undefined_msg, undef_name, + versionstr, versionname)); + } + *ref = NULL; + return 0; + } + + int protected = (*ref + && ELFW(ST_VISIBILITY) ((*ref)->st_other) == STV_PROTECTED); + if (__builtin_expect (protected != 0, 0)) + { + /* It is very tricky. We need to figure out what value to + return for the protected symbol. */ + if (type_class == ELF_RTYPE_CLASS_PLT) + { + if (current_value.s != NULL && current_value.m != undef_map) + { + current_value.s = *ref; + current_value.m = undef_map; + } + } + else + { + struct sym_val protected_value = { NULL, NULL }; + + for (scope = symbol_scope; *scope != NULL; i = 0, ++scope) + if (do_lookup_x (undef_name, new_hash, &old_hash, *ref, + &protected_value, *scope, i, version, flags, + skip_map, ELF_RTYPE_CLASS_PLT) != 0) + break; + + if (protected_value.s != NULL && protected_value.m != undef_map) + { + current_value.s = *ref; + current_value.m = undef_map; + } + } + } + + /* We have to check whether this would bind UNDEF_MAP to an object + in the global scope which was dynamically loaded. In this case + we have to prevent the latter from being unloaded unless the + UNDEF_MAP object is also unloaded. */ + if (__builtin_expect (current_value.m->l_type == lt_loaded, 0) + /* Don't do this for explicit lookups as opposed to implicit + runtime lookups. */ + && (flags & DL_LOOKUP_ADD_DEPENDENCY) != 0 + /* Add UNDEF_MAP to the dependencies. */ + && add_dependency (undef_map, current_value.m, flags) < 0) + /* Something went wrong. Perhaps the object we tried to reference + was just removed. Try finding another definition. */ + return _dl_lookup_symbol_x (undef_name, undef_map, ref, + (flags & DL_LOOKUP_GSCOPE_LOCK) + ? undef_map->l_scope : symbol_scope, + version, type_class, flags, skip_map); + + /* The object is used. */ + current_value.m->l_used = 1; + + if (__builtin_expect (GLRO(dl_debug_mask) + & (DL_DEBUG_BINDINGS|DL_DEBUG_PRELINK), 0)) + _dl_debug_bindings (undef_name, undef_map, ref, + ¤t_value, version, type_class, protected); + + *ref = current_value.s; + return LOOKUP_VALUE (current_value.m); +} + + +/* Cache the location of MAP's hash table. */ + +void +internal_function +_dl_setup_hash (struct link_map *map) +{ + Elf_Symndx *hash; + Elf_Symndx nchain; + + if (__builtin_expect (map->l_info[DT_ADDRTAGIDX (DT_GNU_HASH) + DT_NUM + + DT_THISPROCNUM + DT_VERSIONTAGNUM + + DT_EXTRANUM + DT_VALNUM] != NULL, 1)) + { + Elf32_Word *hash32 + = (void *) D_PTR (map, l_info[DT_ADDRTAGIDX (DT_GNU_HASH) + DT_NUM + + DT_THISPROCNUM + DT_VERSIONTAGNUM + + DT_EXTRANUM + DT_VALNUM]); + map->l_nbuckets = *hash32++; + Elf32_Word symbias = *hash32++; + Elf32_Word bitmask_nwords = *hash32++; + /* Must be a power of two. */ + assert ((bitmask_nwords & (bitmask_nwords - 1)) == 0); + map->l_gnu_bitmask_idxbits = bitmask_nwords - 1; + map->l_gnu_shift = *hash32++; + + map->l_gnu_bitmask = (ElfW(Addr) *) hash32; + hash32 += __ELF_NATIVE_CLASS / 32 * bitmask_nwords; + + map->l_gnu_buckets = hash32; + hash32 += map->l_nbuckets; + map->l_gnu_chain_zero = hash32 - symbias; + return; + } + + if (!map->l_info[DT_HASH]) + return; + hash = (void *) D_PTR (map, l_info[DT_HASH]); + + map->l_nbuckets = *hash++; + nchain = *hash++; + map->l_buckets = hash; + hash += map->l_nbuckets; + map->l_chain = hash; +} + + +static void +internal_function +_dl_debug_bindings (const char *undef_name, struct link_map *undef_map, + const ElfW(Sym) **ref, struct sym_val *value, + const struct r_found_version *version, int type_class, + int protected) +{ + const char *reference_name = undef_map->l_name; + + if (GLRO(dl_debug_mask) & DL_DEBUG_BINDINGS) + { + _dl_debug_printf ("binding file %s [%lu] to %s [%lu]: %s symbol `%s'", + (reference_name[0] + ? reference_name + : (rtld_progname ?: "
")), + undef_map->l_ns, + value->m->l_name[0] ? value->m->l_name : rtld_progname, + value->m->l_ns, + protected ? "protected" : "normal", undef_name); + if (version) + _dl_debug_printf_c (" [%s]\n", version->name); + else + _dl_debug_printf_c ("\n"); + } +#ifdef SHARED + if (GLRO(dl_debug_mask) & DL_DEBUG_PRELINK) + { + int conflict = 0; + struct sym_val val = { NULL, NULL }; + + if ((GLRO(dl_trace_prelink_map) == NULL + || GLRO(dl_trace_prelink_map) == GL(dl_ns)[LM_ID_BASE]._ns_loaded) + && undef_map != GL(dl_ns)[LM_ID_BASE]._ns_loaded) + { + const uint_fast32_t new_hash = dl_new_hash (undef_name); + unsigned long int old_hash = 0xffffffff; + + do_lookup_x (undef_name, new_hash, &old_hash, *ref, &val, + undef_map->l_local_scope[0], 0, version, 0, NULL, + type_class); + + if (val.s != value->s || val.m != value->m) + conflict = 1; + } + + if (value->s + && (__builtin_expect (ELFW(ST_TYPE) (value->s->st_info) + == STT_TLS, 0))) + type_class = 4; + + if (conflict + || GLRO(dl_trace_prelink_map) == undef_map + || GLRO(dl_trace_prelink_map) == NULL + || type_class == 4) + { + _dl_printf ("%s 0x%0*Zx 0x%0*Zx -> 0x%0*Zx 0x%0*Zx ", + conflict ? "conflict" : "lookup", + (int) sizeof (ElfW(Addr)) * 2, + (size_t) undef_map->l_map_start, + (int) sizeof (ElfW(Addr)) * 2, + (size_t) (((ElfW(Addr)) *ref) - undef_map->l_map_start), + (int) sizeof (ElfW(Addr)) * 2, + (size_t) (value->s ? value->m->l_map_start : 0), + (int) sizeof (ElfW(Addr)) * 2, + (size_t) (value->s ? value->s->st_value : 0)); + + if (conflict) + _dl_printf ("x 0x%0*Zx 0x%0*Zx ", + (int) sizeof (ElfW(Addr)) * 2, + (size_t) (val.s ? val.m->l_map_start : 0), + (int) sizeof (ElfW(Addr)) * 2, + (size_t) (val.s ? val.s->st_value : 0)); + + _dl_printf ("/%x %s\n", type_class, undef_name); + } + } +#endif +} Index: sysdeps/mips/dl-trampoline.c =================================================================== --- sysdeps/mips/dl-trampoline.c (revision 213009) +++ sysdeps/mips/dl-trampoline.c (working copy) @@ -270,3 +270,44 @@ _dl_runtime_resolve:\n\ .end _dl_runtime_resolve\n\ .previous\n\ "); + +/* Assembler veneer called from the PLT header code when using the + non-PIC ABI. + + Code in each PLT entry puts the caller's return address into t7 ($15), + the PLT entry index into t8 ($24), the address of _dl_runtime_pltresolve + into t9 ($25) and the address of .got.plt into gp ($28). _dl_fixup + needs a0 ($4) to hold the link map and a1 ($5) to hold the index into + .rel.plt (== PLT entry index * 4). */ + +asm ("\n\ + .text\n\ + .align 2\n\ + .globl _dl_runtime_pltresolve\n\ + .type _dl_runtime_pltresolve,@function\n\ + .ent _dl_runtime_pltresolve\n\ +_dl_runtime_pltresolve:\n\ + .frame $29, " STRINGXP(ELF_DL_FRAME_SIZE) ", $31\n\ + .set noreorder\n\ + # Save arguments and sp value in stack.\n\ + " STRINGXP(PTR_SUBIU) " $29, " STRINGXP(ELF_DL_FRAME_SIZE) "\n\ + lw $10, 4($28)\n\ + # Modify t9 ($25) so as to point .cpload instruction.\n\ + " IFABIO32(STRINGXP(PTR_ADDIU) " $25, 12\n") "\ + # Compute GP.\n\ + " STRINGXP(SETUP_GP) "\n\ + " STRINGXV(SETUP_GP64 (0, _dl_runtime_pltresolve)) "\n\ + .set reorder\n\ + " ELF_DL_SAVE_ARG_REGS "\ + move $4, $10\n\ + sll $5, $24, 3\n\ + jal _dl_fixup\n\ + " ELF_DL_RESTORE_ARG_REGS "\ + " STRINGXP(RESTORE_GP64) "\n\ + " STRINGXP(PTR_ADDIU) " $29, " STRINGXP(ELF_DL_FRAME_SIZE) "\n\ + move $25, $2\n\ + jr $25\n\ + .end _dl_runtime_pltresolve\n\ + .previous\n\ +"); + Index: sysdeps/mips/bits/linkmap.h =================================================================== --- sysdeps/mips/bits/linkmap.h (revision 0) +++ sysdeps/mips/bits/linkmap.h (revision 0) @@ -0,0 +1,4 @@ +struct link_map_machine + { + Elf32_Addr plt; /* Address of .plt */ + }; --vtzGhvizbBRQ85DL Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="glibc-relocs.patch" 2008-03-14 Mark Shinwell * elf/elf.h (STO_MIPS_PLT): New. (R_MIPS_COPY): New. (R_MIPS_JUMP_SLOT): New. (R_MIPS_NUM): Redefine to 128. (DT_MIPS_PLTGOT): New. (DT_MIPS_RWPLT): New. (DT_MIPS_NUM): Redefine to 0x35. Index: elf/elf.h =================================================================== --- elf/elf.h (revision 213009) +++ elf/elf.h (working copy) @@ -1395,6 +1395,7 @@ typedef struct #define STO_MIPS_INTERNAL 0x1 #define STO_MIPS_HIDDEN 0x2 #define STO_MIPS_PROTECTED 0x3 +#define STO_MIPS_PLT 0x8 #define STO_MIPS_SC_ALIGN_UNUSED 0xff /* MIPS specific values for `st_info'. */ @@ -1541,8 +1542,10 @@ typedef struct #define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ #define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ #define R_MIPS_GLOB_DAT 51 +#define R_MIPS_COPY 126 +#define R_MIPS_JUMP_SLOT 127 /* Keep this the last entry. */ -#define R_MIPS_NUM 52 +#define R_MIPS_NUM 128 /* Legal values for p_type field of Elf32_Phdr. */ @@ -1608,7 +1611,13 @@ typedef struct #define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ #define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ #define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ -#define DT_MIPS_NUM 0x32 +/* The address of .got.plt in an executable using the new non-PIC ABI. */ +#define DT_MIPS_PLTGOT 0x70000032 +/* The base of the PLT in an executable using the new non-PIC ABI if that + PLT is writable. For a non-writable PLT, this is omitted or has a zero + value. */ +#define DT_MIPS_RWPLT 0x70000034 +#define DT_MIPS_NUM 0x35 /* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ --vtzGhvizbBRQ85DL Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="binutils-nonpic.diff" ? changelog-diffs Index: bfd/bfd-in2.h =================================================================== RCS file: /cvs/src/src/bfd/bfd-in2.h,v retrieving revision 1.446 diff -u -p -r1.446 bfd-in2.h --- bfd/bfd-in2.h 21 May 2008 12:01:36 -0000 1.446 +++ bfd/bfd-in2.h 1 Jul 2008 16:08:49 -0000 @@ -2661,7 +2661,7 @@ to compensate for the borrow when the lo BFD_RELOC_MIPS_TLS_TPREL_LO16, -/* MIPS ELF relocations (VxWorks extensions). */ +/* MIPS ELF relocations (VxWorks and nonpic extensions). */ BFD_RELOC_MIPS_COPY, BFD_RELOC_MIPS_JUMP_SLOT, Index: bfd/elf32-mips.c =================================================================== RCS file: /cvs/src/src/bfd/elf32-mips.c,v retrieving revision 1.197 diff -u -p -r1.197 elf32-mips.c --- bfd/elf32-mips.c 27 Feb 2008 17:06:06 -0000 1.197 +++ bfd/elf32-mips.c 1 Jul 2008 16:08:49 -0000 @@ -875,6 +875,36 @@ static reloc_howto_type elf_mips_gnu_vte 0, /* dst_mask */ FALSE); /* pcrel_offset */ +static reloc_howto_type elf_mips_copy_howto = + HOWTO (R_MIPS_COPY, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_MIPS_COPY", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x0, /* dst_mask */ + FALSE); /* pcrel_offset */ + +static reloc_howto_type elf_mips_jump_slot_howto = + HOWTO (R_MIPS_JUMP_SLOT, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_MIPS_JUMP_SLOT", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x0, /* dst_mask */ + FALSE); /* pcrel_offset */ + /* Set the GP value for OUTPUT_BFD. Returns FALSE if this is a dangerous relocation. */ @@ -1273,6 +1303,10 @@ bfd_elf32_bfd_reloc_type_lookup (bfd *ab return &elf_mips_gnu_vtentry_howto; case BFD_RELOC_32_PCREL: return &elf_mips_gnu_pcrel32; + case BFD_RELOC_MIPS_COPY: + return &elf_mips_copy_howto; + case BFD_RELOC_MIPS_JUMP_SLOT: + return &elf_mips_jump_slot_howto; } } @@ -1306,6 +1340,10 @@ bfd_elf32_bfd_reloc_name_lookup (bfd *ab return &elf_mips_gnu_vtinherit_howto; if (strcasecmp (elf_mips_gnu_vtentry_howto.name, r_name) == 0) return &elf_mips_gnu_vtentry_howto; + if (strcasecmp (elf_mips_copy_howto.name, r_name) == 0) + return &elf_mips_copy_howto; + if (strcasecmp (elf_mips_jump_slot_howto.name, r_name) == 0) + return &elf_mips_jump_slot_howto; return NULL; } @@ -1326,6 +1364,10 @@ mips_elf32_rtype_to_howto (unsigned int return &elf_mips_gnu_rel16_s2; case R_MIPS_PC32: return &elf_mips_gnu_pcrel32; + case R_MIPS_COPY: + return &elf_mips_copy_howto; + case R_MIPS_JUMP_SLOT: + return &elf_mips_jump_slot_howto; default: if (r_type >= R_MIPS16_min && r_type < R_MIPS16_max) return &elf_mips16_howto_table_rel[r_type - R_MIPS16_min]; @@ -1591,9 +1633,19 @@ static const struct ecoff_debug_swap mip #define elf_backend_default_use_rela_p 0 #define elf_backend_sign_extend_vma TRUE +/* Most MIPS ELF files do not contain a traditional PLT; only VxWorks + and non-PIC dynamic executables do. These settings only affect + _bfd_elf_create_dynamic_sections, which is only called when we + do want a traditional PLT. */ +#undef elf_backend_want_plt_sym +#define elf_backend_want_plt_sym 1 +#undef elf_backend_plt_readonly +#define elf_backend_plt_readonly 1 + #define elf_backend_discard_info _bfd_mips_elf_discard_info #define elf_backend_ignore_discarded_relocs \ _bfd_mips_elf_ignore_discarded_relocs +#define elf_backend_write_section _bfd_mips_elf_write_section #define elf_backend_mips_irix_compat elf32_mips_irix_compat #define elf_backend_mips_rtype_to_howto mips_elf32_rtype_to_howto #define bfd_elf32_bfd_is_local_label_name \ @@ -1613,6 +1665,8 @@ static const struct ecoff_debug_swap mip #define bfd_elf32_bfd_print_private_bfd_data \ _bfd_mips_elf_print_private_bfd_data +#define elf_backend_plt_sym_val _bfd_mips_elf_plt_sym_val + /* Support for SGI-ish mips targets. */ #define TARGET_LITTLE_SYM bfd_elf32_littlemips_vec #define TARGET_LITTLE_NAME "elf32-littlemips" @@ -1652,82 +1706,6 @@ static const struct ecoff_debug_swap mip /* Include the target file again for this target. */ #include "elf32-target.h" - -/* Specific to VxWorks. */ -static reloc_howto_type mips_vxworks_copy_howto_rela = - HOWTO (R_MIPS_COPY, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_MIPS_COPY", /* name */ - FALSE, /* partial_inplace */ - 0x0, /* src_mask */ - 0x0, /* dst_mask */ - FALSE); /* pcrel_offset */ - -/* Specific to VxWorks. */ -static reloc_howto_type mips_vxworks_jump_slot_howto_rela = - HOWTO (R_MIPS_JUMP_SLOT, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_MIPS_JUMP_SLOT", /* name */ - FALSE, /* partial_inplace */ - 0x0, /* src_mask */ - 0x0, /* dst_mask */ - FALSE); /* pcrel_offset */ - -/* Implement elf_backend_bfd_reloc_type_lookup for VxWorks. */ - -static reloc_howto_type * -mips_vxworks_bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code) -{ - switch (code) - { - case BFD_RELOC_MIPS_COPY: - return &mips_vxworks_copy_howto_rela; - case BFD_RELOC_MIPS_JUMP_SLOT: - return &mips_vxworks_jump_slot_howto_rela; - default: - return bfd_elf32_bfd_reloc_type_lookup (abfd, code); - } -} - -static reloc_howto_type * -mips_vxworks_bfd_reloc_name_lookup (bfd *abfd, const char *r_name) -{ - if (strcasecmp (mips_vxworks_copy_howto_rela.name, r_name) == 0) - return &mips_vxworks_copy_howto_rela; - if (strcasecmp (mips_vxworks_jump_slot_howto_rela.name, r_name) == 0) - return &mips_vxworks_jump_slot_howto_rela; - - return bfd_elf32_bfd_reloc_name_lookup (abfd, r_name); -} - -/* Implement elf_backend_mips_rtype_to_lookup for VxWorks. */ - -static reloc_howto_type * -mips_vxworks_rtype_to_howto (unsigned int r_type, bfd_boolean rela_p) -{ - switch (r_type) - { - case R_MIPS_COPY: - return &mips_vxworks_copy_howto_rela; - case R_MIPS_JUMP_SLOT: - return &mips_vxworks_jump_slot_howto_rela; - default: - return mips_elf32_rtype_to_howto (r_type, rela_p); - } -} - /* Implement elf_backend_final_write_processing for VxWorks. */ static void @@ -1758,12 +1736,6 @@ mips_vxworks_final_write_processing (bfd #undef elf_backend_want_got_plt #define elf_backend_want_got_plt 1 -#undef elf_backend_want_plt_sym -#define elf_backend_want_plt_sym 1 -#undef elf_backend_got_symbol_offset -#define elf_backend_got_symbol_offset 0 -#undef elf_backend_want_dynbss -#define elf_backend_want_dynbss 1 #undef elf_backend_may_use_rel_p #define elf_backend_may_use_rel_p 0 #undef elf_backend_may_use_rela_p @@ -1772,21 +1744,10 @@ mips_vxworks_final_write_processing (bfd #define elf_backend_default_use_rela_p 1 #undef elf_backend_got_header_size #define elf_backend_got_header_size (4 * 3) -#undef elf_backend_plt_readonly -#define elf_backend_plt_readonly 1 -#undef bfd_elf32_bfd_reloc_type_lookup -#define bfd_elf32_bfd_reloc_type_lookup \ - mips_vxworks_bfd_reloc_type_lookup -#undef bfd_elf32_bfd_reloc_name_lookup -#define bfd_elf32_bfd_reloc_name_lookup \ - mips_vxworks_bfd_reloc_name_lookup -#undef elf_backend_mips_rtype_to_howto -#define elf_backend_mips_rtype_to_howto \ - mips_vxworks_rtype_to_howto #undef elf_backend_adjust_dynamic_symbol #define elf_backend_adjust_dynamic_symbol \ - _bfd_mips_vxworks_adjust_dynamic_symbol + _bfd_mips_plt_adjust_dynamic_symbol #undef elf_backend_finish_dynamic_symbol #define elf_backend_finish_dynamic_symbol \ _bfd_mips_vxworks_finish_dynamic_symbol @@ -1809,6 +1770,7 @@ mips_vxworks_final_write_processing (bfd #undef elf_backend_additional_program_headers #undef elf_backend_modify_segment_map #undef elf_backend_symbol_processing +#undef elf_backend_plt_sym_val /* NOTE: elf_backend_rela_normal is not defined for MIPS. */ #include "elf32-target.h" Index: bfd/elflink.c =================================================================== RCS file: /cvs/src/src/bfd/elflink.c,v retrieving revision 1.304 diff -u -p -r1.304 elflink.c --- bfd/elflink.c 29 Apr 2008 11:53:45 -0000 1.304 +++ bfd/elflink.c 1 Jul 2008 16:08:49 -0000 @@ -1178,7 +1178,7 @@ _bfd_elf_merge_symbol (bfd *abfd, if (olddef && newdyn) oldweak = FALSE; - /* Allow changes between different types of funciton symbol. */ + /* Allow changes between different types of function symbol. */ if (bed->is_function_type (ELF_ST_TYPE (sym->st_info)) && bed->is_function_type (h->type)) *type_change_ok = TRUE; Index: bfd/elfxx-mips.c =================================================================== RCS file: /cvs/src/src/bfd/elfxx-mips.c,v retrieving revision 1.230 diff -u -p -r1.230 elfxx-mips.c --- bfd/elfxx-mips.c 21 Apr 2008 17:54:24 -0000 1.230 +++ bfd/elfxx-mips.c 1 Jul 2008 16:08:50 -0000 @@ -306,9 +306,6 @@ struct mips_elf_link_hash_entry the initial global GOT entry to a local GOT entry. */ bfd_boolean forced_local; - /* Are we referenced by some kind of relocation? */ - bfd_boolean is_relocation_target; - /* Are we referenced by branch relocations? */ bfd_boolean is_branch_target; @@ -326,6 +323,18 @@ struct mips_elf_link_hash_entry possible to use root.got.offset instead, but that field is overloaded already. */ bfd_vma tls_got_offset; + + /* Offset of any corresponding PLT entry from the start of .plt + when using the non-PIC ABI, unless has_non_pic_to_pic_stub is + set, in which case it is the offset of the stub from the start + of the stubs section. */ + bfd_vma plt_entry_offset; + + /* Set if this symbol has a non-PIC -> PIC call stub associated + with it. If set, the PLT offset field specifies the offset into + the PLT section where the stub lies. All calls from non-PIC code + to the symbol must go via that stub. */ + bfd_boolean has_non_pic_to_pic_stub; }; /* MIPS ELF linker hash table. */ @@ -353,6 +362,10 @@ struct mips_elf_link_hash_table bfd_boolean computed_got_sizes; /* True if we're generating code for VxWorks. */ bfd_boolean is_vxworks; + /* True if we're generating code for the non-PIC ABI. */ + bfd_boolean is_non_pic; + /* A non-PIC input BFD with relocations, to attach stubs to. */ + bfd *non_pic_bfd; /* True if we already reported the small-data section overflow. */ bfd_boolean small_data_overflow_reported; /* Shortcuts to some dynamic sections, or NULL if they are not @@ -363,10 +376,13 @@ struct mips_elf_link_hash_table asection *srelplt2; asection *sgotplt; asection *splt; - /* The size of the PLT header in bytes (VxWorks only). */ + asection *snonpictopic; + /* The size of the PLT header in bytes (VxWorks and non-PIC ABI only). */ bfd_vma plt_header_size; - /* The size of a PLT entry in bytes (VxWorks only). */ + /* The size of a PLT entry in bytes (VxWorks and non-PIC ABI only). */ bfd_vma plt_entry_size; + /* The size of a large PLT entry in bytes (non-PIC ABI only). */ + bfd_vma large_plt_entry_size; /* The size of a function stub entry in bytes. */ bfd_vma function_stub_size; }; @@ -552,6 +568,11 @@ static bfd *reldyn_sorting_bfd; /* Nonzero if ABFD is using NewABI conventions. */ #define NEWABI_P(abfd) (ABI_N32_P (abfd) || ABI_64_P (abfd)) +/* Nonzero if ABFD is a non-PIC object. */ +#define NON_PIC_P(abfd) \ + (((elf_elfheader (abfd)->e_flags & EF_MIPS_PIC) == 0) \ + && ((elf_elfheader (abfd)->e_flags & EF_MIPS_CPIC) == EF_MIPS_CPIC)) + /* The IRIX compatibility level we are striving for. */ #define IRIX_COMPAT(abfd) \ (get_elf_backend_data (abfd)->elf_backend_mips_irix_compat (abfd)) @@ -564,6 +585,9 @@ static bfd *reldyn_sorting_bfd; #define MIPS_ELF_OPTIONS_SECTION_NAME(abfd) \ (NEWABI_P (abfd) ? ".MIPS.options" : ".options") +/* The name of the section holding non-PIC to PIC call stubs. */ +#define NON_PIC_TO_PIC_STUB_SECTION_NAME ".MIPS.pic_stubs" + /* True if NAME is the recognized name of any SHT_MIPS_OPTIONS section. Some IRIX system files do not use MIPS_ELF_OPTIONS_SECTION_NAME. */ #define MIPS_ELF_OPTIONS_SECTION_NAME_P(NAME) \ @@ -752,6 +776,56 @@ static bfd *reldyn_sorting_bfd; #define CALL_STUB_P(name) CONST_STRNEQ (name, CALL_STUB) #define CALL_FP_STUB_P(name) CONST_STRNEQ (name, CALL_FP_STUB) +#define MIPS_NONPIC_LARGE_PLT_THRESHOLD 65536 + +/* The format of the first PLT entry in a non-PIC ABI executable. + This branches to the dynamic linker to resolve a symbol. + This first PLT entry is called via one of the other PLT entries, + which will have initialised t8 to the PLT entry index. */ +static const bfd_vma mips_non_pic_exec_plt0_entry[] = { + 0x3c1c0000, /* lui $gp, */ + 0x279c0000, /* addiu $gp, */ + 0x8f990000, /* lw $t9, 0($gp) */ + 0x03e07821, /* move $t7, $ra */ + 0x0320f809, /* jalr $t9 */ + 0x00000000, /* nop */ + 0x00000000, /* nop */ + 0x00000000 /* nop */ +}; + +/* The format of subsequent PLT entries in a non-PIC ABI executable + whose (0-based) PLT indexes are less than + MIPS_NONPIC_LARGE_PLT_THRESHOLD. (One PLT may contain both entries + in this format and in the format of mips_non_pic_large_exec_plt_entry.) */ +static const bfd_vma mips_non_pic_exec_plt_entry[] = { + 0x3c0f0000, /* lui $t7, */ + 0x8df90000, /* lw $t9, ($t7) */ + 0x34180000, /* ori $t8, $0, */ + 0x03200008 /* jr $t9 */ +}; + +/* The format of subsequent PLT entries in a non-PIC ABI executable + whose (0-based) PLT indexes are greater than or equal to + MIPS_NONPIC_LARGE_PLT_THRESHOLD. */ +static const bfd_vma mips_non_pic_large_exec_plt_entry[] = { + 0x3c0f0000, /* lui $t7, */ + 0x8df90000, /* lw $t9, ($t7) */ + 0x3c180000, /* lui $t8, */ + 0x03200008, /* jr $t9 */ + 0x37180000, /* ori $t8, $t8, */ + 0x00000000, /* nop */ + 0x00000000, /* nop */ + 0x00000000 /* nop */ +}; + +/* The format of a stub used to call PIC code from non-PIC code. */ +static const bfd_vma mips_non_pic_to_pic_stub[] = { + 0x3c190000, /* lui $t9, */ + 0x27390000, /* addiu $t9, $t9, */ + 0x03200008, /* jr $t9 */ + 0x00000000 /* nop */ +}; + /* The format of the first PLT entry in a VxWorks executable. */ static const bfd_vma mips_vxworks_exec_plt0_entry[] = { 0x3c190000, /* lui t9, %hi(_GLOBAL_OFFSET_TABLE_) */ @@ -870,8 +944,9 @@ mips_elf_link_hash_newfunc (struct bfd_h ret->call_fp_stub = NULL; ret->forced_local = FALSE; ret->is_branch_target = FALSE; - ret->is_relocation_target = FALSE; ret->tls_type = GOT_NORMAL; + ret->has_non_pic_to_pic_stub = FALSE; + ret->plt_entry_offset = (bfd_vma) -1; } return (struct bfd_hash_entry *) ret; @@ -4041,17 +4116,6 @@ mips_elf_create_got_section (bfd *abfd, mips_elf_section_data (s)->elf.this_hdr.sh_flags |= SHF_ALLOC | SHF_WRITE | SHF_MIPS_GPREL; - /* VxWorks also needs a .got.plt section. */ - if (htab->is_vxworks) - { - s = bfd_make_section_with_flags (abfd, ".got.plt", - SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS - | SEC_IN_MEMORY | SEC_LINKER_CREATED); - if (s == NULL || !bfd_set_section_alignment (abfd, s, 4)) - return FALSE; - - htab->sgotplt = s; - } return TRUE; } @@ -4293,8 +4357,16 @@ mips_elf_calculate_relocation (bfd *abfd /* If this is a 32- or 64-bit call to a 16-bit function with a stub, we need to redirect the call to the stub, unless we're already *in* - a stub. */ - if (r_type != R_MIPS16_26 && !info->relocatable + a stub. Likewise for non-PIC to PIC call stubs. (Note that + these latter varieties of stubs never contain any relocations, so + we don't need to check if we're within a stub section here.) */ + if (h != NULL && htab->is_non_pic + && (r_type == R_MIPS_26 || r_type == R_MIPS_PC16) + && h->has_non_pic_to_pic_stub) + symbol = htab->snonpictopic->output_section->vma + + htab->snonpictopic->output_section->output_offset + + h->plt_entry_offset; + else if (r_type != R_MIPS16_26 && !info->relocatable && ((h != NULL && h->fn_stub != NULL) || (local_p && elf_tdata (input_bfd)->local_stubs != NULL @@ -4357,6 +4429,17 @@ mips_elf_calculate_relocation (bfd *abfd BFD_ASSERT (sec->size > 0); symbol = sec->output_section->vma + sec->output_offset; } + else if (htab->is_non_pic && h != NULL + && !h->has_non_pic_to_pic_stub + && h->plt_entry_offset != (bfd_vma) -1) + { + BFD_ASSERT (!local_p); + BFD_ASSERT (r_type == R_MIPS_PC16 || addend == 0); + sec = htab->splt; + BFD_ASSERT (sec != NULL); + symbol = sec->output_section->vma + sec->output_offset + + h->plt_entry_offset; + } /* Calls from 16-bit code to 32-bit code and vice versa require the special jalx instruction. */ @@ -4516,8 +4599,9 @@ mips_elf_calculate_relocation (bfd *abfd case R_MIPS_64: if ((info->shared || (!htab->is_vxworks - && htab->root.dynamic_sections_created + && !htab->is_non_pic && h != NULL + && htab->root.dynamic_sections_created && h->root.def_dynamic && !h->root.def_regular)) && r_symndx != 0 @@ -4531,7 +4615,8 @@ mips_elf_calculate_relocation (bfd *abfd In VxWorks executables, references to external symbols are handled using copy relocs or PLT stubs, so there's - no need to add a dynamic relocation here. */ + no need to add a dynamic relocation here. Likewise for + the non-PIC ABI. */ value = addend; if (!mips_elf_create_dynamic_relocation (abfd, info, @@ -6150,6 +6235,56 @@ _bfd_mips_elf_link_output_symbol_hook /* Functions for the dynamic linker. */ +static bfd_boolean +_bfd_mips_elf_create_nonpic_dynamic_sections (bfd *abfd, + struct bfd_link_info *info) +{ + flagword flags; + asection *s; + struct mips_elf_link_hash_table *htab; + + htab = mips_elf_hash_table (info); + flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_LINKER_CREATED | SEC_READONLY); + + BFD_ASSERT (!info->shared); + + s = bfd_make_section_with_flags (abfd, ".got.plt", + SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS + | SEC_IN_MEMORY | SEC_LINKER_CREATED); + if (s == NULL || !bfd_set_section_alignment (abfd, s, 4)) + return FALSE; + htab->sgotplt = s; + + /* Create the .plt, .rel.plt, .dynbss and .rel.bss sections. */ + if (!_bfd_elf_create_dynamic_sections (abfd, info)) + return FALSE; + + /* Cache the sections created above. */ + htab->sdynbss = bfd_get_section_by_name (abfd, ".dynbss"); + htab->srelbss = bfd_get_section_by_name (abfd, ".rel.bss"); + htab->srelplt = bfd_get_section_by_name (abfd, ".rel.plt"); + htab->splt = bfd_get_section_by_name (abfd, ".plt"); + if (!htab->sdynbss + || !htab->srelbss + || !htab->srelplt + || !htab->splt) + abort (); + + /* Align .plt to 32 bytes, so that no PLT entry crosses a + cache line. */ + if (! bfd_set_section_alignment (abfd, htab->splt, 5)) + return FALSE; + + /* Work out the PLT sizes. */ + htab->plt_header_size = 4 * ARRAY_SIZE (mips_non_pic_exec_plt0_entry); + htab->plt_entry_size = 4 * ARRAY_SIZE (mips_non_pic_exec_plt_entry); + htab->large_plt_entry_size = + 4 * ARRAY_SIZE (mips_non_pic_large_exec_plt_entry); + + return TRUE; +} + /* Create dynamic sections when linking against a dynamic object. */ bfd_boolean @@ -6182,6 +6317,18 @@ _bfd_mips_elf_create_dynamic_sections (b if (! mips_elf_create_got_section (abfd, info, FALSE)) return FALSE; + /* VxWorks and non-PIC ABI code also need a .got.plt section. */ + if (htab->is_vxworks) + { + s = bfd_make_section_with_flags (abfd, ".got.plt", + SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS + | SEC_IN_MEMORY | SEC_LINKER_CREATED); + if (s == NULL || !bfd_set_section_alignment (abfd, s, 4)) + return FALSE; + + htab->sgotplt = s; + } + if (! mips_elf_rel_dyn_section (info, TRUE)) return FALSE; @@ -6342,6 +6489,12 @@ _bfd_mips_elf_create_dynamic_sections (b } } + /* If creating a (non-shared) object using the non-PIC ABI, + we also need a PLT etc. */ + if (htab->is_non_pic + && !_bfd_mips_elf_create_nonpic_dynamic_sections (abfd, info)) + return FALSE; + return TRUE; } @@ -6498,6 +6651,24 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s sym_hashes = elf_sym_hashes (abfd); extsymoff = (elf_bad_symtab (abfd)) ? 0 : symtab_hdr->sh_info; + /* Check if this is the first non-PIC file encountered during an + executable link. We have to check the input file's flags, + since merge_private_data is not called until later. */ + if (!htab->is_non_pic && !info->shared) + { + flagword flags; + + flags = elf_elfheader (abfd)->e_flags; + if ((flags & (EF_MIPS_PIC | EF_MIPS_CPIC)) == EF_MIPS_CPIC) + { + htab->is_non_pic = TRUE; + htab->non_pic_bfd = abfd; + if (elf_hash_table (info)->dynamic_sections_created) + if (!_bfd_mips_elf_create_nonpic_dynamic_sections (dynobj, info)) + return FALSE; + } + } + /* Check for the mips16 stub sections. */ name = bfd_get_section_name (abfd, sec); @@ -6823,7 +6994,8 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s are handled using copy relocs or PLT stubs, so there's no need to add a dynamic relocation here. */ if (dynobj == NULL - && (info->shared || (h != NULL && !htab->is_vxworks)) + && (info->shared + || (h != NULL && !htab->is_vxworks && !htab->is_non_pic)) && (sec->flags & SEC_ALLOC) != 0) elf_hash_table (info)->dynobj = dynobj = abfd; break; @@ -6835,8 +7007,6 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s if (h) { - ((struct mips_elf_link_hash_entry *) h)->is_relocation_target = TRUE; - /* Relocations against the special VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols must be left to the loader. Allocate room for them in .rela.dyn. */ @@ -6890,7 +7060,7 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s case R_MIPS_CALL_LO16: if (h != NULL) { - /* VxWorks call relocations point the function's .got.plt + /* VxWorks call relocations point at the function's .got.plt entry, which will be allocated by adjust_dynamic_symbol. Otherwise, this symbol requires a global GOT entry. */ if ((!htab->is_vxworks || h->forced_local) @@ -6899,7 +7069,9 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s /* We need a stub, not a plt entry for the undefined function. But we record it as if it needs plt. See - _bfd_elf_adjust_dynamic_symbol. */ + _bfd_elf_adjust_dynamic_symbol. Note that these relocations + are always used for PIC calls, even when using the new + non-PIC ABI. */ h->needs_plt = 1; h->type = STT_FUNC; } @@ -7006,10 +7178,15 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s case R_MIPS_32: case R_MIPS_REL32: case R_MIPS_64: + if (h != NULL) + h->non_got_ref = TRUE; /* In VxWorks executables, references to external symbols are handled using copy relocs or PLT stubs, so there's - no need to add a .rela.dyn entry for this relocation. */ - if ((info->shared || (h != NULL && !htab->is_vxworks)) + no need to add a .rela.dyn entry for this relocation. + Likewise for the non-PIC ABI, if we already know that + we are using it. */ + if ((info->shared + || (h != NULL && !htab->is_vxworks && !htab->is_non_pic)) && (sec->flags & SEC_ALLOC) != 0) { if (sreloc == NULL) @@ -7034,7 +7211,9 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s struct mips_elf_link_hash_entry *hmips; /* We only need to copy this reloc if the symbol is - defined in a dynamic object. */ + defined in a dynamic object. We do not need to + do so at all if we find a non-PIC file later in + the link. */ hmips = (struct mips_elf_link_hash_entry *) h; ++hmips->possibly_dynamic_relocs; if (MIPS_ELF_READONLY_SECTION (sec)) @@ -7048,7 +7227,11 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s table index greater that DT_MIPS_GOTSYM if there are dynamic relocations against it. This does not apply to VxWorks, which does not have the usual coupling - between global GOT entries and .dynsym entries. */ + between global GOT entries and .dynsym entries. + If this link turns out to be a non-PIC one (i.e. we + have only seen PIC files so far, but find a non-PIC + one later), then this will not have been necessary; + but it is harmless in that case. */ if (h != NULL && !htab->is_vxworks) { if (dynobj == NULL) @@ -7079,11 +7262,21 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s case R_MIPS_GPREL16: case R_MIPS_LITERAL: case R_MIPS_GPREL32: + if (h != NULL + && (r_type == R_MIPS_GPREL16 || r_type == R_MIPS_GPREL32)) + h->non_got_ref = TRUE; + if (SGI_COMPAT (abfd)) mips_elf_hash_table (info)->compact_rel_size += sizeof (Elf32_External_crinfo); break; + case R_MIPS_HI16: + case R_MIPS_LO16: + if (h != NULL && strcmp (h->root.root.string, "_gp_disp") != 0) + h->non_got_ref = TRUE; + break; + /* This relocation describes the C++ object vtable hierarchy. Reconstruct it for later use during GC. */ case R_MIPS_GNU_VTINHERIT: @@ -7106,19 +7299,19 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s /* We must not create a stub for a symbol that has relocations related to taking the function's address. This doesn't apply to - VxWorks, where CALL relocs refer to a .got.plt entry instead of - a normal .got entry. */ + VxWorks or the non-PIC ABI, where CALL relocs refer to a + .got.plt entry instead of a normal .got entry. */ if (!htab->is_vxworks && h != NULL) switch (r_type) { - default: - ((struct mips_elf_link_hash_entry *) h)->no_fn_stub = TRUE; - break; case R_MIPS_CALL16: case R_MIPS_CALL_HI16: case R_MIPS_CALL_LO16: case R_MIPS_JALR: break; + default: + ((struct mips_elf_link_hash_entry *) h)->no_fn_stub = TRUE; + break; } /* If this reloc is not a 16 bit call, and it has a global @@ -7133,6 +7326,36 @@ _bfd_mips_elf_check_relocs (bfd *abfd, s mh = (struct mips_elf_link_hash_entry *) h; mh->need_fn_stub = TRUE; } + + /* Refuse invalid relocations when creating a shared library. Do + not refuse R_MIPS_32 / R_MIPS_64; they're not PIC, but we'll set + TEXTREL and the result will be fine. */ + if (info->shared + && (sec->flags & SEC_ALLOC) != 0 + && (sec->flags & SEC_READONLY) != 0) + { + switch (r_type) + { + case R_MIPS_HI16: + /* Don't refuse R_MIPS_HI16 relocation if it's a part of + compound relocation or against _gp_disp. */ + if (NEWABI_P (dynobj) + || (h != NULL + && strcmp (h->root.root.string, "_gp_disp") == 0)) + break; + /* FALLTHROUGH */ + case R_MIPS_26: + howto = MIPS_ELF_RTYPE_TO_HOWTO (abfd, r_type, FALSE); + (*_bfd_error_handler) + (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"), + abfd, howto->name, + (h) ? h->root.root.string : "a local symbol"); + bfd_set_error (bfd_error_bad_value); + return FALSE; + default: + break; + } + } } return TRUE; @@ -7299,6 +7522,61 @@ _bfd_mips_relax_section (bfd *abfd, asec return FALSE; } +/* Return the size in bytes that the next PLT entry to be added to + htab->splt will require. */ +static bfd_vma +mips_elf_next_plt_entry_size (struct mips_elf_link_hash_table *htab) +{ + /* If we have fewer than MIPS_NONPIC_LARGE_PLT_THRESHOLD entries + currently in the PLT, the next entry to be added will be a normal + "small" PLT entry; otherwise it must be a large PLT entry. */ + if (htab->splt->size - htab->plt_header_size + >= htab->plt_entry_size * MIPS_NONPIC_LARGE_PLT_THRESHOLD) + return htab->large_plt_entry_size; + else + return htab->plt_entry_size; +} + +/* Create an old-style .MIPS.stubs entry for a symbol not defined in a + regular file. The symbol's value is pointed at the .MIPS.stubs entry + to provide a canonical function address. */ + +static bfd_boolean +mips_elf_create_old_style_stub (struct bfd_link_info *info, + struct elf_link_hash_entry *h) +{ + bfd *dynobj = elf_hash_table (info)->dynobj; + struct mips_elf_link_hash_table *htab = mips_elf_hash_table (info); + asection *s; + + BFD_ASSERT (dynobj != NULL); + BFD_ASSERT (htab != NULL); + BFD_ASSERT (elf_hash_table (info) != NULL); + BFD_ASSERT (!((struct mips_elf_link_hash_entry *) h)->no_fn_stub + && h->needs_plt + && !h->def_regular); + + if (!elf_hash_table (info)->dynamic_sections_created) + return TRUE; + + /* Find the .stub section. */ + s = bfd_get_section_by_name (dynobj, + MIPS_ELF_STUB_SECTION_NAME (dynobj)); + BFD_ASSERT (s != NULL); + + h->root.u.def.section = s; + h->root.u.def.value = s->size; + + h->plt.offset = s->size; + + /* Make room for this stub code. */ + s->size += htab->function_stub_size; + + /* The last half word of the stub will be filled with the index + of this symbol in .dynsym section. */ + return TRUE; +} + /* Adjust a symbol defined by a dynamic object and referenced by a regular object. The current definition is in some section of the dynamic object, but we're not including those sections. We have to @@ -7311,11 +7589,15 @@ _bfd_mips_elf_adjust_dynamic_symbol (str { bfd *dynobj; struct mips_elf_link_hash_entry *hmips; - asection *s; struct mips_elf_link_hash_table *htab; htab = mips_elf_hash_table (info); dynobj = elf_hash_table (info)->dynobj; + hmips = (struct mips_elf_link_hash_entry *) h; + + /* VxWorks and the non-PIC ABI are handled elsewhere. */ + if (htab->is_vxworks || htab->is_non_pic) + return _bfd_mips_plt_adjust_dynamic_symbol (info, h); /* Make sure we know what is going on here. */ BFD_ASSERT (dynobj != NULL @@ -7328,7 +7610,6 @@ _bfd_mips_elf_adjust_dynamic_symbol (str /* If this symbol is defined in a dynamic object, we need to copy any R_MIPS_32 or R_MIPS_REL32 relocs against it into the output file. */ - hmips = (struct mips_elf_link_hash_entry *) h; if (! info->relocatable && hmips->possibly_dynamic_relocs != 0 && (h->root.type == bfd_link_hash_defweak @@ -7343,39 +7624,9 @@ _bfd_mips_elf_adjust_dynamic_symbol (str } /* For a function, create a stub, if allowed. */ - if (! hmips->no_fn_stub - && h->needs_plt) - { - if (! elf_hash_table (info)->dynamic_sections_created) - return TRUE; - - /* If this symbol is not defined in a regular file, then set - the symbol to the stub location. This is required to make - function pointers compare as equal between the normal - executable and the shared library. */ - if (!h->def_regular) - { - /* We need .stub section. */ - s = bfd_get_section_by_name (dynobj, - MIPS_ELF_STUB_SECTION_NAME (dynobj)); - BFD_ASSERT (s != NULL); - - h->root.u.def.section = s; - h->root.u.def.value = s->size; - - /* XXX Write this stub address somewhere. */ - h->plt.offset = s->size; - - /* Make room for this stub code. */ - s->size += htab->function_stub_size; - - /* The last half word of the stub will be filled with the index - of this symbol in .dynsym section. */ - return TRUE; - } - } - else if ((h->type == STT_FUNC) - && !h->needs_plt) + if (!hmips->no_fn_stub && h->needs_plt && !h->def_regular) + return mips_elf_create_old_style_stub (info, h); + else if (h->type == STT_FUNC && !h->needs_plt) { /* This will set the entry for this symbol in the GOT to 0, and the dynamic linker will take care of this. */ @@ -7401,94 +7652,188 @@ _bfd_mips_elf_adjust_dynamic_symbol (str return TRUE; } -/* Likewise, for VxWorks. */ +/* Likewise, for ABIs requiring procedure linkage tables (the non-PIC + ABI, and that of VxWorks). */ bfd_boolean -_bfd_mips_vxworks_adjust_dynamic_symbol (struct bfd_link_info *info, - struct elf_link_hash_entry *h) +_bfd_mips_plt_adjust_dynamic_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *h) { + bfd_boolean needs_plt_entry = FALSE; bfd *dynobj; struct mips_elf_link_hash_entry *hmips; struct mips_elf_link_hash_table *htab; + int reloc_size; htab = mips_elf_hash_table (info); dynobj = elf_hash_table (info)->dynobj; hmips = (struct mips_elf_link_hash_entry *) h; - /* Make sure we know what is going on here. */ + /* The code below is only for VxWorks or applications using the + non-PIC ABI. */ + BFD_ASSERT (htab->is_vxworks || htab->is_non_pic); BFD_ASSERT (dynobj != NULL && (h->needs_plt - || h->needs_copy || h->u.weakdef != NULL || (h->def_dynamic && h->ref_regular && !h->def_regular))); - /* If the symbol is defined by a dynamic object, we need a PLT stub if + /* Note applicable to the non-PIC ABI only. + On entry to this function, h->needs_plt is set just when there is + a call from PIC code to the symbol under consideration. Unless the + symbol now transpires to be local or have its address taken, this + means that an old-style .MIPS.stubs entry is required. We set + needs_plt_entry during this function if we are using the non-PIC ABI + and discover that the symbol requires a PLT entry. Both of these + flags may be set together. On exit from this function, h->needs_plt + details whether a .MIPS.stubs entry was created. */ + + /* If the symbol is defined by a dynamic object, we need a PLT entry if either (a) we want to branch to the symbol or (b) we're linking an executable that needs a canonical function address. In the latter - case, the canonical address will be the address of the executable's - load stub. */ + case, the canonical address will be that of the PLT entry. */ if ((hmips->is_branch_target || (!info->shared && h->type == STT_FUNC - && hmips->is_relocation_target)) + && h->non_got_ref)) && h->def_dynamic && h->ref_regular && !h->def_regular && !h->forced_local) - h->needs_plt = 1; + { + /* This is the only place where we mark a symbol as requiring a + PLT entry under the non-PIC ABI. */ + if (htab->is_non_pic) + needs_plt_entry = TRUE; - /* Locally-binding symbols do not need a PLT stub; we can refer to - the functions directly. */ + if (htab->is_vxworks) + h->needs_plt = TRUE; + } + /* Locally-binding symbols do not need a PLT or a .MIPS.stubs entry; + we can refer to the functions directly. */ else if (h->needs_plt && (SYMBOL_CALLS_LOCAL (info, h) || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT && h->root.type == bfd_link_hash_undefweak))) { - h->needs_plt = 0; + h->needs_plt = FALSE; return TRUE; } - if (h->needs_plt) + /* If using the non-PIC ABI, create a .MIPS.stubs entry for this + symbol if required. The symbol must not have had its address + taken; it must have been marked as requiring a stub previously; + and it must not be defined in a regular file. */ + if (htab->is_non_pic && h->needs_plt && !hmips->no_fn_stub) + { + if (!mips_elf_create_old_style_stub (info, h)) + return FALSE; + /* We continue if the stub was created successfully; as above, we + may need a PLT entry too. */ + } + + /* Under the non-PIC ABI, symbols marked as requiring non-PIC to PIC + call stubs (such symbols being defined in PIC code) should by definition + never be undefined in a regular file. It follows that such symbols + should never have PLT entries associated with them, nor copy relocs. */ + BFD_ASSERT (!htab->is_non_pic + || !hmips->has_non_pic_to_pic_stub + || !needs_plt_entry + || !h->non_got_ref); + + /* Calculate the number of bytes required for a relocation + in .rel[a].plt. */ + if (htab->is_vxworks) + reloc_size = sizeof (Elf32_External_Rela); + else + reloc_size = sizeof (Elf32_External_Rel); + + if ((htab->is_vxworks && h->needs_plt) + || (htab->is_non_pic && needs_plt_entry)) { + /* VxWorks can have PLT entries in shared libraries; but this never + happens with the non-PIC ABI. In the non-PIC case, every symbol + being dealt with here should be undefined in a regular file. */ + BFD_ASSERT (htab->is_vxworks || !h->def_regular); + /* If this is the first symbol to need a PLT entry, allocate room - for the header, and for the header's .rela.plt.unloaded entries. */ + for the first PLT (header) entry, and on VxWorks for the header's + .rela.plt.unloaded entries. For the non-PIC ABI, also allocate + room at the start of .got.plt for the PLT resolver and link + map pointers. */ if (htab->splt->size == 0) { - htab->splt->size += htab->plt_header_size; - if (!info->shared) - htab->srelplt2->size += 2 * sizeof (Elf32_External_Rela); + htab->splt->size = htab->plt_header_size; + if (!info->shared && htab->is_vxworks) + { + BFD_ASSERT (htab->srelplt2->size == 0); + htab->srelplt2->size = 2 * reloc_size; + } + if (htab->is_non_pic) + { + BFD_ASSERT (htab->sgotplt->size == 0); + /* Leave space for the PLT resolver and link map pointers. */ + htab->sgotplt->size = 8; + } + BFD_ASSERT (htab->srelplt->size == 0); } /* Assign the next .plt entry to this symbol. */ - h->plt.offset = htab->splt->size; - htab->splt->size += htab->plt_entry_size; + if (htab->is_vxworks) + h->plt.offset = htab->splt->size; + else + hmips->plt_entry_offset = htab->splt->size; + htab->splt->size += mips_elf_next_plt_entry_size (htab); /* If the output file has no definition of the symbol, set the - symbol's value to the address of the stub. Point at the PLT - load stub rather than the lazy resolution stub; this stub - will become the canonical function address. */ + symbol's value to the address of the stub. Note the + assertion above that h->def_regular will always be false + under the non-PIC ABI. */ if (!info->shared && !h->def_regular) { h->root.u.def.section = htab->splt; - h->root.u.def.value = h->plt.offset; - h->root.u.def.value += 8; + h->root.u.def.value = htab->is_vxworks ? + h->plt.offset : hmips->plt_entry_offset; + if (htab->is_non_pic) + { + /* Make sure the dynamic linker knows that the symbol's value + points at a PLT entry and not at a .MIPS.stubs entry. */ + h->other = STO_MIPS_PLT; + } + /* On VxWorks, point at the PLT load stub rather than the + lazy resolution stub; this stub will become the canonical + function address. */ + if (htab->is_vxworks) + h->root.u.def.value += 8; } - /* Make room for the .got.plt entry and the R_JUMP_SLOT relocation. */ + /* Make room for the .got.plt entry, and the R_JUMP_SLOT relocation + in .rel[a].plt. */ htab->sgotplt->size += 4; - htab->srelplt->size += sizeof (Elf32_External_Rela); + htab->srelplt->size += reloc_size; - /* Make room for the .rela.plt.unloaded relocations. */ - if (!info->shared) - htab->srelplt2->size += 3 * sizeof (Elf32_External_Rela); + /* Make room for the .rela.plt.unloaded relocations on VxWorks. */ + if (htab->is_vxworks && !info->shared) + htab->srelplt2->size += 3 * reloc_size; return TRUE; } + /* If we reach this point for non-PIC, then we have created a + .MIPS.stubs stub (unless no_fn_stub) but not a PLT entry since one was + not required. We're done. */ + BFD_ASSERT (!htab->is_non_pic || !needs_plt_entry); + if (htab->is_non_pic && h->needs_plt) + return TRUE; + + /* We should never reach this point on VxWorks or the non-PIC ABI if + we have created a PLT entry or a .MIPS.stubs-style stub + respectively. */ + BFD_ASSERT (!h->needs_plt); + /* If a function symbol is defined by a dynamic object, and we do not - need a PLT stub for it, the symbol's value should be zero. */ + need a PLT entry for it, the symbol's value should be zero. */ if (h->type == STT_FUNC && h->def_dynamic && h->ref_regular @@ -7510,11 +7855,19 @@ _bfd_mips_vxworks_adjust_dynamic_symbol return TRUE; } - /* This is a reference to a symbol defined by a dynamic object which + /* We have a reference to a symbol defined by a dynamic object which is not a function. */ + BFD_ASSERT (h->ref_regular && h->def_dynamic && !h->def_regular); + BFD_ASSERT (h->type != STT_FUNC); + + /* If creating a shared library, we are done. */ if (info->shared) return TRUE; + /* If this symbol does not require a copy reloc, we are done. */ + if (!h->non_got_ref) + return TRUE; + /* We must allocate the symbol in our .dynbss section, which will become part of the .bss section of the executable. There will be an entry for this symbol in the .dynsym section. The dynamic @@ -7524,10 +7877,14 @@ _bfd_mips_vxworks_adjust_dynamic_symbol determine the address it must put in the global offset table, so both the dynamic object and the regular object will refer to the same memory location for the variable. */ - + BFD_ASSERT (!h->needs_copy); if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) { - htab->srelbss->size += sizeof (Elf32_External_Rela); + if (htab->is_non_pic) + mips_elf_allocate_dynamic_relocations (dynobj, info, 1); + else + htab->srelbss->size += sizeof (Elf32_External_Rela); + /* Note that this symbol definitely needs a copy reloc. */ h->needs_copy = 1; } @@ -7560,6 +7917,35 @@ count_section_dynsyms (bfd *output_bfd, return count; } +/* Determine if a symbol requires a non-PIC to PIC call stub to be + created for it. If so, mark it as such and allocate space for the + stub code. */ + +static int +mips_elf_maybe_create_non_pic_to_pic_stub (void *h_ptr, void *htab_ptr) +{ + struct mips_elf_link_hash_entry *h = + (struct mips_elf_link_hash_entry *) h_ptr; + struct mips_elf_link_hash_table *htab = + (struct mips_elf_link_hash_table *) htab_ptr; + + if (h != NULL + && h->root.def_regular + && !h->root.def_dynamic + && !h->has_non_pic_to_pic_stub + && h->is_branch_target + && !NON_PIC_P (h->root.root.u.def.section->owner)) + { + BFD_ASSERT (htab->snonpictopic != NULL); + + h->plt_entry_offset = htab->snonpictopic->size; + htab->snonpictopic->size += 4 * ARRAY_SIZE (mips_non_pic_to_pic_stub); + h->has_non_pic_to_pic_stub = TRUE; + } + + return 1; +} + /* This function is called after all the input files have been read, and the input sections have been assigned to output sections. We check for any mips16 stub sections that we can discard. */ @@ -7702,6 +8088,25 @@ _bfd_mips_elf_always_size_sections (bfd } htab->computed_got_sizes = TRUE; + /* Identify symbols that require non-PIC to PIC call stubs. + Allocate space for any such stubs. */ + if (htab->is_non_pic) + { + BFD_ASSERT (htab->snonpictopic != NULL); + + elf_link_hash_traverse (elf_hash_table (info), + mips_elf_maybe_create_non_pic_to_pic_stub, htab); + if (htab->snonpictopic->size != 0) + { + htab->snonpictopic->contents = bfd_zalloc (output_bfd, + htab->snonpictopic->size); + if (htab->snonpictopic->contents == NULL) + return FALSE; + } + else + htab->snonpictopic->flags |= SEC_EXCLUDE; + } + return TRUE; } @@ -7887,11 +8292,19 @@ _bfd_mips_elf_size_dynamic_sections (bfd else if (SGI_COMPAT (output_bfd) && CONST_STRNEQ (name, ".compact_rel")) s->size += mips_elf_hash_table (info)->compact_rel_size; + else if (s == htab->splt) + { + /* If the last PLT entry has a branch delay slot, allocate + room for an extra nop to fill the delay slot. */ + if (s->size - htab->plt_header_size + <= htab->plt_entry_size * MIPS_NONPIC_LARGE_PLT_THRESHOLD) + s->size += 4; + } else if (! CONST_STRNEQ (name, ".init") - && s != htab->sgotplt - && s != htab->splt) + && s != htab->sgotplt) { - /* It's not one of our sections, so don't allocate space. */ + /* It's not one of our sections, or it's the non-PIC to PIC stubs + section that is allocated elsewhere, so don't allocate space. */ continue; } @@ -8034,6 +8447,24 @@ _bfd_mips_elf_size_dynamic_sections (bfd if (! MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_MIPS_GOTSYM, 0)) return FALSE; + if (htab->is_non_pic && htab->splt->size > 0) + { + if (! MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_PLTREL, 0)) + return FALSE; + + if (! MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_JMPREL, 0)) + return FALSE; + + if (! MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_PLTRELSZ, 0)) + return FALSE; + + if (! MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_MIPS_PLTGOT, 0)) + return FALSE; + + if (! MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_MIPS_RWPLT, 0)) + return FALSE; + } + if (IRIX_COMPAT (dynobj) == ict_irix5 && ! MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_MIPS_HIPAGENO, 0)) return FALSE; @@ -8505,11 +8936,14 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd const char *name; int idx; struct mips_elf_link_hash_table *htab; + struct mips_elf_link_hash_entry *hmips; + + hmips = (struct mips_elf_link_hash_entry *) h; htab = mips_elf_hash_table (info); dynobj = elf_hash_table (info)->dynobj; - if (h->plt.offset != MINUS_ONE) + if (h->plt.offset != MINUS_ONE && h->needs_plt) { asection *s; bfd_byte stub[MIPS_FUNCTION_STUB_BIG_SIZE]; @@ -8556,7 +8990,7 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd bfd_put_32 (output_bfd, STUB_LI16S (output_bfd, h->dynindx), stub + idx); - BFD_ASSERT (h->plt.offset <= s->size); + BFD_ASSERT (h->plt.offset <= s->size - htab->function_stub_size); memcpy (s->contents + h->plt.offset, stub, htab->function_stub_size); /* Mark the symbol as undefined. plt.offset != -1 occurs @@ -8569,6 +9003,107 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd sym->st_value = (s->output_section->vma + s->output_offset + h->plt.offset); } + else if (hmips->plt_entry_offset != (bfd_vma) -1 + && !hmips->has_non_pic_to_pic_stub) + { + /* Fill in the PLT, .got.plt and .rel.plt entries for this symbol. */ + + bfd_byte *loc; + bfd_vma plt_address, plt_index, gotplt_address; + Elf_Internal_Rela rel; + static const bfd_vma *plt_entry; + bfd_vma gotplt_address_high, gotplt_address_low; + + BFD_ASSERT (!info->shared); + BFD_ASSERT (h->dynindx != -1); + BFD_ASSERT (htab->splt != NULL); + BFD_ASSERT (hmips->plt_entry_offset < htab->splt->size); + + /* Calculate the address of the .plt entry. */ + plt_address = (htab->splt->output_section->vma + + htab->splt->output_offset + + hmips->plt_entry_offset); + + /* Calculate the (0-based) index, in words, of the .rel.plt entry, + taking into account whether this is a large PLT entry or not. + The index into .got.plt is this index plus two (to skip over + the PLT resolver and link map pointers at the start of the + PLT GOT.) */ + if (hmips->plt_entry_offset + >= htab->plt_header_size + + htab->plt_entry_size * MIPS_NONPIC_LARGE_PLT_THRESHOLD) + /* This entry is a large PLT entry. */ + plt_index = ((hmips->plt_entry_offset - htab->plt_header_size + - htab->plt_entry_size * MIPS_NONPIC_LARGE_PLT_THRESHOLD) + / htab->large_plt_entry_size + + MIPS_NONPIC_LARGE_PLT_THRESHOLD); + else + { + /* This entry is a normal PLT entry. */ + plt_index = ((hmips->plt_entry_offset - htab->plt_header_size) + / htab->plt_entry_size); + BFD_ASSERT (plt_index < MIPS_NONPIC_LARGE_PLT_THRESHOLD); + } + + /* Calculate the address of the .got.plt entry. The addition of 8 + is to allow for the PLT resolver and link map pointers at the + start of .got.plt. */ + gotplt_address = (htab->sgotplt->output_section->vma + + htab->sgotplt->output_offset + + 8 + plt_index * 4); + + /* Split the address of the .got.plt entry into high and low + parts. The 0x8000 bias is to compensate for the fact that the addiu + instruction into which the low part will be written accepts a + _signed_ immediate. */ + gotplt_address_high = ((gotplt_address + 0x8000) >> 16) & 0xffff; + gotplt_address_low = gotplt_address & 0xffff; + + /* Fill in the initial value (the address of the first PLT entry) + of the .got.plt entry. */ + bfd_put_32 (output_bfd, plt_address - hmips->plt_entry_offset, + htab->sgotplt->contents + 8 + plt_index * 4); + + /* Find out where the .plt entry should go. + Note the use of hmips->plt_entry_offset to save distinguishing between + large and small PLT entries. */ + loc = htab->splt->contents + hmips->plt_entry_offset; + + /* Choose the PLT entry template to use and write it, suitably + filled, to the output bfd. */ + if (plt_index >= MIPS_NONPIC_LARGE_PLT_THRESHOLD) + { + /* Large PLT entry. */ + plt_entry = mips_non_pic_large_exec_plt_entry; + bfd_put_32 (output_bfd, plt_entry[0] | gotplt_address_high, loc); + bfd_put_32 (output_bfd, plt_entry[1] | gotplt_address_low, loc + 4); + bfd_put_32 (output_bfd, plt_entry[2] | (plt_index >> 16), loc + 8); + bfd_put_32 (output_bfd, plt_entry[3], loc + 12); + bfd_put_32 (output_bfd, plt_entry[4] | (plt_index & 0xffff), + loc + 16); + bfd_put_32 (output_bfd, plt_entry[5], loc + 20); + bfd_put_32 (output_bfd, plt_entry[6], loc + 24); + bfd_put_32 (output_bfd, plt_entry[7], loc + 28); + } + else + { + /* Normal PLT entry. */ + plt_entry = mips_non_pic_exec_plt_entry; + bfd_put_32 (output_bfd, plt_entry[0] | gotplt_address_high, loc); + bfd_put_32 (output_bfd, plt_entry[1] | gotplt_address_low, loc + 4); + bfd_put_32 (output_bfd, plt_entry[2] | plt_index, loc + 8); + bfd_put_32 (output_bfd, plt_entry[3], loc + 12); + } + + /* Emit an R_MIPS_JUMP_SLOT relocation against the .got.plt entry. */ + loc = htab->srelplt->contents + plt_index * sizeof (Elf32_External_Rel); + rel.r_offset = gotplt_address; + rel.r_info = ELF32_R_INFO (h->dynindx, R_MIPS_JUMP_SLOT); + bfd_elf32_swap_reloc_out (output_bfd, &rel, loc); + + /* Mark the symbol as undefined. */ + sym->st_shndx = SHN_UNDEF; + } BFD_ASSERT (h->dynindx != -1 || h->forced_local); @@ -8718,6 +9253,29 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd } } + /* Emit a copy reloc, if needed. */ + if (htab->is_non_pic && h->needs_copy) + { + asection *relsec; + Elf_Internal_Rela rel; + bfd_byte *reloff; /* dyn.rel offset for this copy reloc */ + + relsec = mips_elf_rel_dyn_section (info, FALSE); + BFD_ASSERT (relsec != NULL); + BFD_ASSERT (h->dynindx != -1); + + reloff = relsec->contents + + (relsec->reloc_count * sizeof (Elf32_External_Rel)); + + rel.r_addend = 0; + rel.r_info = ELF_R_INFO (output_bfd, (unsigned long) h->dynindx, R_MIPS_COPY); + rel.r_offset = (h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset + + h->root.u.def.value); + bfd_elf32_swap_reloc_out (output_bfd, &rel, reloff); + ++relsec->reloc_count; + } + /* If this is a mips16 symbol, force the value to be even. */ if (sym->st_other == STO_MIPS16) sym->st_value &= ~1; @@ -8897,6 +9455,41 @@ _bfd_mips_vxworks_finish_dynamic_symbol return TRUE; } +/* Install the PLT header for a non-PIC executable. */ + +static void +mips_non_pic_finish_plt (bfd *output_bfd, struct bfd_link_info *info) +{ + bfd_byte *loc; + bfd_vma plt_address; + static const bfd_vma *plt_entry; + struct mips_elf_link_hash_table *htab; + bfd_vma got_plt, got_plt_high, got_plt_low; + + htab = mips_elf_hash_table (info); + plt_entry = mips_non_pic_exec_plt0_entry; + + /* Calculate the address of .got.plt and split it into high and low + parts. The 0x8000 bias is to compensate for the fact that the addiu + instruction into which the low part will be written accepts a + _signed_ immediate. */ + got_plt = htab->sgotplt->output_section->vma + htab->sgotplt->output_offset; + got_plt_high = ((got_plt + 0x8000) >> 16) & 0xffff; + got_plt_low = got_plt & 0xffff; + + /* Calculate the address of the PLT header. */ + plt_address = htab->splt->output_section->vma + htab->splt->output_offset; + + /* Install the PLT header. */ + loc = htab->splt->contents; + bfd_put_32 (output_bfd, plt_entry[0] | got_plt_high, loc); + bfd_put_32 (output_bfd, plt_entry[1] | got_plt_low, loc + 4); + bfd_put_32 (output_bfd, plt_entry[2], loc + 8); + bfd_put_32 (output_bfd, plt_entry[3], loc + 12); + bfd_put_32 (output_bfd, plt_entry[4], loc + 16); + bfd_put_32 (output_bfd, plt_entry[5], loc + 20); +} + /* Install the PLT header for a VxWorks executable and finalize the contents of .rela.plt.unloaded. */ @@ -9059,20 +9652,21 @@ _bfd_mips_elf_finish_dynamic_sections (b case DT_PLTGOT: name = ".got"; - if (htab->is_vxworks) - { - /* _GLOBAL_OFFSET_TABLE_ is defined to be the beginning - of the ".got" section in DYNOBJ. */ - s = bfd_get_section_by_name (dynobj, name); - BFD_ASSERT (s != NULL); - dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; - } - else - { - s = bfd_get_section_by_name (output_bfd, name); - BFD_ASSERT (s != NULL); - dyn.d_un.d_ptr = s->vma; - } + /* _GLOBAL_OFFSET_TABLE_ is defined to be the beginning + of the ".got" section in DYNOBJ. */ + s = bfd_get_section_by_name (dynobj, name); + BFD_ASSERT (s != NULL); + dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; + break; + + case DT_MIPS_PLTGOT: + BFD_ASSERT (htab->is_non_pic); + dyn.d_un.d_val = (htab->sgotplt->output_section->vma + + htab->sgotplt->output_offset); + break; + + case DT_MIPS_RWPLT: + BFD_ASSERT (htab->is_non_pic); break; case DT_MIPS_RLD_VERSION: @@ -9159,17 +9753,17 @@ _bfd_mips_elf_finish_dynamic_sections (b break; case DT_PLTREL: - BFD_ASSERT (htab->is_vxworks); - dyn.d_un.d_val = DT_RELA; + BFD_ASSERT (htab->is_vxworks || htab->is_non_pic); + dyn.d_un.d_val = htab->is_vxworks ? DT_RELA : DT_REL; break; case DT_PLTRELSZ: - BFD_ASSERT (htab->is_vxworks); + BFD_ASSERT (htab->is_vxworks || htab->is_non_pic); dyn.d_un.d_val = htab->srelplt->size; break; case DT_JMPREL: - BFD_ASSERT (htab->is_vxworks); + BFD_ASSERT (htab->is_vxworks || htab->is_non_pic); dyn.d_un.d_val = (htab->srelplt->output_section->vma + htab->srelplt->output_offset); break; @@ -9407,6 +10001,10 @@ _bfd_mips_elf_finish_dynamic_sections (b else mips_vxworks_finish_exec_plt (output_bfd, info); } + + if (htab->is_non_pic && htab->splt && htab->splt->size > 0) + mips_non_pic_finish_plt (output_bfd, info); + return TRUE; } @@ -9994,6 +10592,9 @@ _bfd_mips_elf_copy_indirect_symbol (stru dirmips->readonly_reloc = TRUE; if (indmips->no_fn_stub) dirmips->no_fn_stub = TRUE; + if (indmips->has_non_pic_to_pic_stub) + dirmips->has_non_pic_to_pic_stub = TRUE; + dirmips->is_branch_target |= indmips->is_branch_target; if (dirmips->tls_type == 0) dirmips->tls_type = indmips->tls_type; @@ -10540,6 +11141,7 @@ _bfd_mips_elf_link_hash_table_create (bf ret->mips16_stubs_seen = FALSE; ret->computed_got_sizes = FALSE; ret->is_vxworks = FALSE; + ret->is_non_pic = FALSE; ret->small_data_overflow_reported = FALSE; ret->srelbss = NULL; ret->sdynbss = NULL; @@ -10547,6 +11149,7 @@ _bfd_mips_elf_link_hash_table_create (bf ret->srelplt2 = NULL; ret->sgotplt = NULL; ret->splt = NULL; + ret->snonpictopic = NULL; ret->plt_header_size = 0; ret->plt_entry_size = 0; ret->function_stub_size = 0; @@ -10571,6 +11174,7 @@ _bfd_mips_vxworks_link_hash_table_create } return ret; } + /* We need to use a special link routine to handle the .reginfo and the .mdebug sections. We need to merge all instances of these @@ -11558,12 +12162,6 @@ _bfd_mips_elf_merge_private_bfd_data (bf new_flags &= ~EF_MIPS_UCODE; old_flags &= ~EF_MIPS_UCODE; - /* Don't care about the PIC flags from dynamic objects; they are - PIC by design. */ - if ((new_flags & (EF_MIPS_PIC | EF_MIPS_CPIC)) != 0 - && (ibfd->flags & DYNAMIC) != 0) - new_flags &= ~ (EF_MIPS_PIC | EF_MIPS_CPIC); - if (new_flags == old_flags) return TRUE; @@ -11585,19 +12183,18 @@ _bfd_mips_elf_merge_private_bfd_data (bf break; } } - if (null_input_bfd) + /* Dynamic objects normally have no sections, and do not reach + here - but they might if used as DYNOBJ. */ + if (null_input_bfd || (ibfd->flags & DYNAMIC) != 0) return TRUE; ok = TRUE; if (((new_flags & (EF_MIPS_PIC | EF_MIPS_CPIC)) != 0) != ((old_flags & (EF_MIPS_PIC | EF_MIPS_CPIC)) != 0)) - { - (*_bfd_error_handler) - (_("%B: warning: linking PIC files with non-PIC files"), - ibfd); - ok = TRUE; - } + (*_bfd_error_handler) + (_("%B: warning: linking PIC files with non-PIC files"), + ibfd); if (new_flags & (EF_MIPS_PIC | EF_MIPS_CPIC)) elf_elfheader (obfd)->e_flags |= EF_MIPS_CPIC; @@ -11805,6 +12402,10 @@ _bfd_mips_elf_get_target_dtag (bfd_vma d return "DT_MIPS_GP_VALUE"; case DT_MIPS_AUX_DYNAMIC: return "DT_MIPS_AUX_DYNAMIC"; + case DT_MIPS_PLTGOT: + return "DT_MIPS_PLTGOT"; + case DT_MIPS_RWPLT: + return "DT_MIPS_RWPLT"; } } @@ -11939,3 +12540,133 @@ _bfd_mips_elf_common_definition (Elf_Int || sym->st_shndx == SHN_MIPS_ACOMMON || sym->st_shndx == SHN_MIPS_SCOMMON); } + +/* Return address for Ith PLT stub in section PLT, for relocation REL + or (bfd_vma) -1 if it should not be included. */ + +bfd_vma +_bfd_mips_elf_plt_sym_val (bfd_vma i, const asection *plt, + const arelent *rel ATTRIBUTE_UNUSED) +{ + if (i > MIPS_NONPIC_LARGE_PLT_THRESHOLD) + return (plt->vma + 4 * ARRAY_SIZE (mips_non_pic_exec_plt0_entry) + + (MIPS_NONPIC_LARGE_PLT_THRESHOLD + * 4 * ARRAY_SIZE (mips_non_pic_exec_plt_entry)) + + ((i - MIPS_NONPIC_LARGE_PLT_THRESHOLD) + * 4 * ARRAY_SIZE (mips_non_pic_large_exec_plt_entry))); + else + return (plt->vma + 4 * ARRAY_SIZE (mips_non_pic_exec_plt0_entry) + + i * 4 * ARRAY_SIZE (mips_non_pic_exec_plt_entry)); +} + +/* Generate non-PIC to PIC call stubs for all symbols which need them. */ + +static bfd_boolean +mips_elf_nonpic_stub (struct elf_link_hash_entry *h, void *info) +{ + struct bfd_link_info *link_info = info; + struct mips_elf_link_hash_table *htab = mips_elf_hash_table (link_info); + struct bfd *abfd = htab->non_pic_bfd; + struct mips_elf_link_hash_entry *hmips; + bfd_vma target_address, target_high, target_low; + bfd_byte *loc; + asection *sec; + + hmips = (struct mips_elf_link_hash_entry *) h; + if (!hmips->has_non_pic_to_pic_stub) + return TRUE; + + BFD_ASSERT (!link_info->shared); + BFD_ASSERT (h->def_regular); + BFD_ASSERT (!h->def_dynamic); + BFD_ASSERT (htab->snonpictopic != NULL); + BFD_ASSERT (htab->snonpictopic->contents != NULL); + BFD_ASSERT (htab->snonpictopic->output_section != NULL); + BFD_ASSERT (hmips->plt_entry_offset < htab->snonpictopic->size); + + sec = h->root.u.def.section; + + /* Determine the address (to which the stub will branch) of the + symbol, split into two halves as required by the stub + instructions. */ + if (sec->output_section) + target_address = h->root.u.def.value + + sec->output_section->vma + + sec->output_offset; + else + target_address = h->root.u.def.value; + + target_high = ((target_address + 0x8000) >> 16) & 0xffff; + target_low = target_address & 0xffff; + + /* Fill the stub with instructions. */ + loc = htab->snonpictopic->contents + hmips->plt_entry_offset; + bfd_put_32 (abfd, mips_non_pic_to_pic_stub[0] | target_high, loc); + bfd_put_32 (abfd, mips_non_pic_to_pic_stub[1] | target_low, + loc + 4); + bfd_put_32 (abfd, mips_non_pic_to_pic_stub[2], loc + 8); + bfd_put_32 (abfd, mips_non_pic_to_pic_stub[3], loc + 12); + + return TRUE; +} + +void +_bfd_mips_elf_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED, + struct bfd_link_info *link_info) +{ + struct mips_elf_link_hash_table *htab; + + if (!link_info) + return; + + htab = mips_elf_hash_table (link_info); + if (htab->snonpictopic == NULL || !htab->is_non_pic) + return; + + elf_link_hash_traverse (&htab->root, mips_elf_nonpic_stub, link_info); +} + +/* If performing a non-PIC link, create the section to be used for + non-PIC to PIC call stubs. */ + +bfd_boolean +bfd_mips_elf_maybe_create_non_pic_to_pic_stubs_section + (struct bfd_link_info *info) +{ + struct mips_elf_link_hash_table *htab = mips_elf_hash_table (info); + bfd *abfd = htab->non_pic_bfd; + flagword flags; + + if (info->relocatable) + return TRUE; + if (!htab->is_non_pic) + return TRUE; + + flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_READONLY | SEC_LINKER_CREATED); + htab->snonpictopic = + bfd_make_section_with_flags (abfd, + NON_PIC_TO_PIC_STUB_SECTION_NAME, + flags | SEC_CODE); + if (htab->snonpictopic == NULL + || ! bfd_set_section_alignment (abfd, htab->snonpictopic, + MIPS_ELF_LOG_FILE_ALIGN (abfd))) + return FALSE; + + return TRUE; +} + +void +_bfd_mips_post_process_headers (bfd *abfd, struct bfd_link_info *link_info) +{ + struct mips_elf_link_hash_table *htab; + Elf_Internal_Ehdr *i_ehdrp; + + i_ehdrp = elf_elfheader (abfd); + if (link_info) + { + htab = mips_elf_hash_table (link_info); + if (htab->is_non_pic) + i_ehdrp->e_ident[EI_ABIVERSION] = 1; + } +} Index: bfd/elfxx-mips.h =================================================================== RCS file: /cvs/src/src/bfd/elfxx-mips.h,v retrieving revision 1.38 diff -u -p -r1.38 elfxx-mips.h --- bfd/elfxx-mips.h 27 Feb 2008 17:06:06 -0000 1.38 +++ bfd/elfxx-mips.h 1 Jul 2008 16:08:50 -0000 @@ -50,7 +50,7 @@ extern bfd_boolean _bfd_mips_elf_check_r (bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *); extern bfd_boolean _bfd_mips_elf_adjust_dynamic_symbol (struct bfd_link_info *, struct elf_link_hash_entry *); -extern bfd_boolean _bfd_mips_vxworks_adjust_dynamic_symbol +extern bfd_boolean _bfd_mips_plt_adjust_dynamic_symbol (struct bfd_link_info *, struct elf_link_hash_entry *); extern bfd_boolean _bfd_mips_elf_always_size_sections (bfd *, struct bfd_link_info *); @@ -65,6 +65,9 @@ extern bfd_boolean _bfd_mips_elf_finish_ extern bfd_boolean _bfd_mips_vxworks_finish_dynamic_symbol (bfd *, struct bfd_link_info *, struct elf_link_hash_entry *, Elf_Internal_Sym *); +extern bfd_boolean _bfd_mips_nonpic_finish_dynamic_symbol + (bfd *, struct bfd_link_info *, struct elf_link_hash_entry *, + Elf_Internal_Sym *); extern bfd_boolean _bfd_mips_elf_finish_dynamic_sections (bfd *, struct bfd_link_info *); extern void _bfd_mips_elf_final_write_processing @@ -146,6 +149,15 @@ extern const struct bfd_elf_special_sect extern bfd_boolean _bfd_mips_elf_common_definition (Elf_Internal_Sym *); +extern bfd_vma _bfd_mips_elf_plt_sym_val + (bfd_vma, const asection *, const arelent *); +extern void _bfd_mips_elf_begin_write_processing + (bfd *abfd, struct bfd_link_info *link_info); +extern bfd_boolean bfd_mips_elf_maybe_create_non_pic_to_pic_stubs_section + (struct bfd_link_info *); +extern void _bfd_mips_post_process_headers + (bfd *abfd, struct bfd_link_info *link_info); + #define elf_backend_common_definition _bfd_mips_elf_common_definition #define elf_backend_name_local_section_symbols \ _bfd_mips_elf_name_local_section_symbols @@ -153,3 +165,5 @@ extern bfd_boolean _bfd_mips_elf_common_ #define elf_backend_eh_frame_address_size _bfd_mips_elf_eh_frame_address_size #define elf_backend_merge_symbol_attribute _bfd_mips_elf_merge_symbol_attribute #define elf_backend_ignore_undef_symbol _bfd_mips_elf_ignore_undef_symbol +#define elf_backend_post_process_headers _bfd_mips_post_process_headers +#define elf_backend_begin_write_processing _bfd_mips_elf_begin_write_processing Index: bfd/reloc.c =================================================================== RCS file: /cvs/src/src/bfd/reloc.c,v retrieving revision 1.174 diff -u -p -r1.174 reloc.c --- bfd/reloc.c 16 Apr 2008 08:51:18 -0000 1.174 +++ bfd/reloc.c 1 Jul 2008 16:08:50 -0000 @@ -2251,7 +2251,7 @@ ENUM ENUMX BFD_RELOC_MIPS_JUMP_SLOT ENUMDOC - MIPS ELF relocations (VxWorks extensions). + MIPS ELF relocations (VxWorks and non-PIC extensions). COMMENT ENUM Index: binutils/readelf.c =================================================================== RCS file: /cvs/src/src/binutils/readelf.c,v retrieving revision 1.411 diff -u -p -r1.411 readelf.c --- binutils/readelf.c 18 Jun 2008 10:49:50 -0000 1.411 +++ binutils/readelf.c 1 Jul 2008 16:08:50 -0000 @@ -1495,6 +1495,9 @@ get_mips_dynamic_type (unsigned long typ case DT_MIPS_COMPACT_SIZE: return "MIPS_COMPACT_SIZE"; case DT_MIPS_GP_VALUE: return "MIPS_GP_VALUE"; case DT_MIPS_AUX_DYNAMIC: return "MIPS_AUX_DYNAMIC"; + case DT_MIPS_PLTGOT: return "MIPS_PLTGOT"; + case DT_MIPS_RWPLT: return "MIPS_RWPLT"; + default: return NULL; } @@ -7145,6 +7148,7 @@ get_mips_symbol_other (unsigned int othe { case STO_OPTIONAL: return "OPTIONAL"; case STO_MIPS16: return "MIPS16"; + case STO_MIPS_PLT: return "MIPS_PLT"; default: return NULL; } } Index: gas/config/tc-mips.c =================================================================== RCS file: /cvs/src/src/gas/config/tc-mips.c,v retrieving revision 1.388 diff -u -p -r1.388 tc-mips.c --- gas/config/tc-mips.c 12 Jun 2008 21:44:53 -0000 1.388 +++ gas/config/tc-mips.c 1 Jul 2008 16:08:51 -0000 @@ -1854,6 +1854,12 @@ md_begin (void) as_bad (_("-G may not be used in position-independent code")); g_switch_value = 0; } + else if (mips_abicalls) + { + if (g_switch_seen && g_switch_value != 0) + as_bad (_("-G may not be used with abicalls")); + g_switch_value = 0; + } if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) as_warn (_("Could not set architecture and machine")); @@ -11166,6 +11172,8 @@ struct option md_longopts[] = {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, +#define OPTION_NON_PIC_ABICALLS (OPTION_ELF_BASE + 12) + {"mnon-pic-abicalls", no_argument, NULL, OPTION_NON_PIC_ABICALLS}, #endif /* OBJ_ELF */ {NULL, no_argument, NULL, 0} @@ -11574,6 +11582,11 @@ md_parse_option (int c, char *arg) case OPTION_MVXWORKS_PIC: mips_pic = VXWORKS_PIC; break; + + case OPTION_NON_PIC_ABICALLS: + mips_pic = NO_PIC; + mips_abicalls = TRUE; + break; #endif /* OBJ_ELF */ default: Index: include/elf/mips.h =================================================================== RCS file: /cvs/src/src/include/elf/mips.h,v retrieving revision 1.37 diff -u -p -r1.37 mips.h --- include/elf/mips.h 11 Mar 2008 23:21:08 -0000 1.37 +++ include/elf/mips.h 1 Jul 2008 16:08:54 -0000 @@ -662,6 +662,13 @@ extern void bfd_mips_elf32_swap_reginfo_ /* Address of auxiliary .dynamic. */ #define DT_MIPS_AUX_DYNAMIC 0x70000031 + +/* Address of the base of the PLTGOT. */ +#define DT_MIPS_PLTGOT 0x70000032 + +/* Points to the base of a writable PLT. */ +#define DT_MIPS_RWPLT 0x70000034 + /* Flags which may appear in a DT_MIPS_FLAGS entry. */ @@ -723,6 +730,9 @@ extern void bfd_mips_elf32_swap_reginfo_ #define STO_HIDDEN STV_HIDDEN #define STO_PROTECTED STV_PROTECTED +/* Symbol value is the address of a PLT entry. */ +#define STO_MIPS_PLT 0x8 + /* This value is used for a mips16 .text symbol. */ #define STO_MIPS16 0xf0 Index: ld/emulparams/elf32bmip.sh =================================================================== RCS file: /cvs/src/src/ld/emulparams/elf32bmip.sh,v retrieving revision 1.16 diff -u -p -r1.16 elf32bmip.sh --- ld/emulparams/elf32bmip.sh 9 Aug 2007 11:02:24 -0000 1.16 +++ ld/emulparams/elf32bmip.sh 1 Jul 2008 16:08:54 -0000 @@ -35,6 +35,16 @@ OTHER_GOT_SYMBOLS=' . = .; _gp = ALIGN(16) + 0x7ff0; ' +# Only non-PIC abicalls binaries (and VxWorks, which overrides these) +# have .got.plt. It should not go between the definition of _gp and +# the start of .got. It can go in the relro area, because it does not +# need to be anywhere near _gp or small data. Do not set SEPARATE_GOTPLT +# because we might not have a .plt; don't make eight bytes of .data +# relro. +GOT=".got ${RELOCATING-0} : { *(.got) }" +GOTPLT=".got.plt ${RELOCATING-0} : { *(.got.plt) }" +DATA_GOTPLT= + OTHER_SDATA_SECTIONS=" .lit8 ${RELOCATING-0} : { *(.lit8) } .lit4 ${RELOCATING-0} : { *(.lit4) } Index: ld/emulparams/elf32ebmipvxworks.sh =================================================================== RCS file: /cvs/src/src/ld/emulparams/elf32ebmipvxworks.sh,v retrieving revision 1.2 diff -u -p -r1.2 elf32ebmipvxworks.sh --- ld/emulparams/elf32ebmipvxworks.sh 18 May 2007 09:18:18 -0000 1.2 +++ ld/emulparams/elf32ebmipvxworks.sh 1 Jul 2008 16:08:54 -0000 @@ -13,6 +13,9 @@ OTHER_READWRITE_SECTIONS=" .rdata ${RELOCATING-0} : ONLY_IF_RW { *(.rdata) } " unset OTHER_GOT_SYMBOLS +unset GOT +unset GOTPLT +unset DATA_GOTPLT SHLIB_TEXT_START_ADDR=0 unset TEXT_DYNAMIC unset DATA_ADDR Index: ld/emulparams/elf32elmipvxworks.sh =================================================================== RCS file: /cvs/src/src/ld/emulparams/elf32elmipvxworks.sh,v retrieving revision 1.1 diff -u -p -r1.1 elf32elmipvxworks.sh --- ld/emulparams/elf32elmipvxworks.sh 22 Mar 2006 09:28:13 -0000 1.1 +++ ld/emulparams/elf32elmipvxworks.sh 1 Jul 2008 16:08:54 -0000 @@ -4,6 +4,9 @@ OUTPUT_FORMAT="elf32-littlemips-vxworks" BIG_OUTPUT_FORMAT="elf32-bigmips-vxworks" LITTLE_OUTPUT_FORMAT="elf32-littlemips-vxworks" unset OTHER_GOT_SYMBOLS +unset GOT +unset GOTPLT +unset DATA_GOTPLT SHLIB_TEXT_START_ADDR=0 unset TEXT_DYNAMIC unset DATA_ADDR Index: ld/emultempl/mipself.em =================================================================== RCS file: /cvs/src/src/ld/emultempl/mipself.em,v retrieving revision 1.9 diff -u -p -r1.9 mipself.em --- ld/emultempl/mipself.em 19 Jul 2007 19:56:10 -0000 1.9 +++ ld/emultempl/mipself.em 1 Jul 2008 16:08:54 -0000 @@ -19,6 +19,9 @@ # MA 02110-1301, USA. fragment <); Tue, 1 Jul 2008 21:43:41 +0100 Received: by nf-out-0910.google.com with SMTP id h3so16194nfh.14 for ; Tue, 01 Jul 2008 13:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:mail-followup-to:cc :subject:references:date:in-reply-to:message-id:user-agent :mime-version:content-type; bh=RG0+zZm9lEcSl0UtOGVWsJNj10aIWS+uSrnoKNY+8UA=; b=u4Mcwx+zh+3EkHmBGYCew6ks7PbxPbcKertCRGcVVjwY7zJu8uo4a4ZT0Y9xRapEQc gX0e164IzhD/HRGw9efSe1POIhJFPTGmxkZZiwe+oTlOTGXsjNseOXLe+1Wuf26lSWmI 5maD/WvQaMJjskXTk22/XgBHg17muE26ck52Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:mail-followup-to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-type; b=W1H5yf66Qjyd/PixPUBs0qF9IMDJEvR2jPevANs/muU5KWkNjzusF+3Eh9TaqYh5Wu pWTy7o7TWbDkoZTuujnN1y7xraewv3K013o38+IJeSJGTCY8T/izEaEhX3/hSjSpT8dn IUxOk488mYlKHB/BHJVm3EUuVIrDF3D10ALxI= Received: by 10.210.21.13 with SMTP id 13mr5777669ebu.75.1214945020292; Tue, 01 Jul 2008 13:43:40 -0700 (PDT) Received: from localhost ( [79.75.55.39]) by mx.google.com with ESMTPS id u14sm13662329gvf.6.2008.07.01.13.43.37 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 01 Jul 2008 13:43:38 -0700 (PDT) From: Richard Sandiford To: binutils@sourceware.org Mail-Followup-To: binutils@sourceware.org,gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Cc: gcc@gcc.gnu.org, linux-mips@linux-mips.org Subject: Re: RFC: Adding non-PIC executable support to MIPS References: <87y74pxwyl.fsf@firetop.home> <20080701202236.GA1534@caradoc.them.org> Date: Tue, 01 Jul 2008 21:43:30 +0100 In-Reply-To: <20080701202236.GA1534@caradoc.them.org> (Daniel Jacobowitz's message of "Tue\, 1 Jul 2008 16\:22\:37 -0400") Message-ID: <87zlp149ot.fsf@firetop.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19684 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rdsandiford@googlemail.com Precedence: bulk X-list: linux-mips Content-Length: 1992 Lines: 44 Daniel Jacobowitz writes: > We've shipped our version. Richard's version has presumably also > shipped. Right. > We did negotiate the ABI changes with MTI; this is not quite > as good as doing it in full view, but it was the best we could manage > and MTI is as close to a central authority for the MIPS psABI as > exists today. > > Richard, what are your thoughts on reconciling the differences? You > can surely guess that I want to avoid changing our ABI now, even for > relatively significant technical reasons - I'm all ears if there's a > major reason, but in the comparisons I do not see one. I suppose I still support the trade-off between the 5-insn MIPS I stubs (with extra-long variation for large PLT indices) and the absolute .got.plt address I used. And I still think it's shame we're treating STO_MIPS_PLT and STO_MIPS16 as separate; we then only have 1 bit of st_other unclaimed. However, IMO, your argument about MTI being the central authority is a killer one. The purpose of the GNU tools should be to follow appropriate standards where applicable (and extend them where it seems wise). So from that point of view, I agree that the GNU tools should follow the ABI that Nigel and MTI set down. Consider my patch withdrawn. TBH, the close relationship between CodeSourcery and MTI make it difficult for a non-Sourcerer and non-MTI employee to continue to be a MIPS maintainer. I won't be in-the-know about this sort of thing. I've been thinking about that a lot recently, since I heard about your implementation. I kind-of guessed it had been agreed with MTI beforehand (although I hadn't realised MTI themselves had written the specification). Having thought it over, I think it would be best if I stand down as a MIPS maintainer and if someone with the appropriate commercial connections is appointed instead. I'd recommend any combination of yourself, Adam Nemet and David Daney (subject to said people being willing, of course). Richard From rdsandiford@googlemail.com Tue Jul 1 23:03:05 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 01 Jul 2008 23:03:11 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.186]:4231 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S32716728AbYGAWDF (ORCPT ); Tue, 1 Jul 2008 23:03:05 +0100 Received: by nf-out-0910.google.com with SMTP id h3so24648nfh.14 for ; Tue, 01 Jul 2008 15:03:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:mail-followup-to:cc :subject:references:date:in-reply-to:message-id:user-agent :mime-version:content-type; bh=QmXN6RhKS0/S1/XTXrOP6Zl+KiStHwWJlFhVEynpZ5w=; b=a5s8+RTGjm9dn1e4VxtQEJmGh/1dVKndynHMOrj8DVtPfPyfuikIZODnq64UzVF1as zL7zTqjbVjfmnl0XORGxoRMHnzwzDIYCI+BdKbcYfkVU/Us6f2d1G6wtkoWE/UbAS+T2 Xl8TfSQ3fN1xr3towMcXzyNIuvcwtBLe3Dt8Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:mail-followup-to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-type; b=YZbKp/A7koACVvpypMHopcBP0rV3g5B4iXX1nJV1IWed4Ss4A3Rte32Ob/1RP0Zupa DbpM+0UjAYw9BO6T3ZjUfFeEny9AYkpG8jLTSco1Ap9JrB0VntlshYNZZ7wZ3pst72rI kCTMQiM92ZmA+6pY3a23hk5DwzV6O4WlulvsY= Received: by 10.210.76.19 with SMTP id y19mr5777304eba.186.1214949783944; Tue, 01 Jul 2008 15:03:03 -0700 (PDT) Received: from localhost ( [79.75.55.39]) by mx.google.com with ESMTPS id i6sm2211941gve.4.2008.07.01.15.03.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 01 Jul 2008 15:03:02 -0700 (PDT) From: Richard Sandiford To: binutils@sourceware.org Mail-Followup-To: binutils@sourceware.org,gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Cc: gcc@gcc.gnu.org, linux-mips@linux-mips.org Subject: Re: RFC: Adding non-PIC executable support to MIPS References: <87y74pxwyl.fsf@firetop.home> <20080701202236.GA1534@caradoc.them.org> <87zlp149ot.fsf@firetop.home> Date: Tue, 01 Jul 2008 23:02:59 +0100 In-Reply-To: <87zlp149ot.fsf@firetop.home> (Richard Sandiford's message of "Tue\, 01 Jul 2008 21\:43\:30 +0100") Message-ID: <87r6ad460c.fsf@firetop.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19685 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rdsandiford@googlemail.com Precedence: bulk X-list: linux-mips Content-Length: 763 Lines: 15 Richard Sandiford writes: > I've been thinking about that a lot recently, since I heard about > your implementation. I kind-of guessed it had been agreed with MTI > beforehand (although I hadn't realised MTI themselves had written > the specification). Having thought it over, I think it would be best > if I stand down as a MIPS maintainer and if someone with the appropriate > commercial connections is appointed instead. I'd recommend any > combination of yourself, Adam Nemet and David Daney (subject to > said people being willing, of course). I realised afterwards that this might be offensive by who it left out. For the record, it wasn't supposed to be an exclusive list. Other people have strong claims too. ;) Richard From mlarsen@broadcom.com Wed Jul 2 01:12:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 01:12:43 +0100 (BST) Received: from mms2.broadcom.com ([216.31.210.18]:62724 "EHLO mms2.broadcom.com") by ftp.linux-mips.org with ESMTP id S32723985AbYGBAMd (ORCPT ); Wed, 2 Jul 2008 01:12:33 +0100 Received: from [10.11.16.99] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Tue, 01 Jul 2008 17:12:20 -0700 X-Server-Uuid: D3C04415-6FA8-4F2C-93C1-920E106A2031 Received: by mail-irva-10.broadcom.com (Postfix, from userid 47) id 9A20E2B1; Tue, 1 Jul 2008 17:12:20 -0700 (PDT) Received: from mail-irva-8.broadcom.com (mail-irva-8 [10.11.18.52]) by mail-irva-10.broadcom.com (Postfix) with ESMTP id 86C912B0 for ; Tue, 1 Jul 2008 17:12:20 -0700 (PDT) Received: from mail-sj1-12.sj.broadcom.com (mail-sj1-12.sj.broadcom.com [10.16.128.215]) by mail-irva-8.broadcom.com (MOS 3.7.5a-GA) with ESMTP id GZD36507; Tue, 1 Jul 2008 17:12:20 -0700 (PDT) Received: from NT-SJCA-0750.brcm.ad.broadcom.com (nt-sjca-0750 [10.16.192.220]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 1A7F920501 for ; Tue, 1 Jul 2008 17:12:20 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Subject: RE: Bug in atomic_sub_if_positive Date: Tue, 1 Jul 2008 17:12:19 -0700 Message-ID: Thread-Topic: RE: Bug in atomic_sub_if_positive Thread-Index: Acjb16gnajlQWCmATQa1bV7F7m0yoAAABL1g From: "Morten Larsen" To: linux-mips@linux-mips.org X-WSS-ID: 6474186E3D075132792-01-01 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: base64 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19686 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlarsen@broadcom.com Precedence: bulk X-list: linux-mips Content-Length: 1667 Lines: 23 DQo+IEFzIGZhciBhcyBJIGNhbiB0ZWxsIHRoZSBicmFuY2ggb3B0aW1pemF0aW9uIGZpeGVzIGlu IDIuNi4yMSBpbnRyb2R1Y2VkDQo+IGEgYnVnIGluIGF0b21pY19zdWJfaWZfcG9zaXRpdmUgdGhh dCBjYXVzZXMgaXQgdG8gcmV0dXJuIGV2ZW4gd2hlbiB0aGUNCj4gc2MgaW5zdHJ1Y3Rpb24gZmFp bHMuIFRoZSByZXN1bHQgaXMgdGhhdCBlLmcuIGRvd25fdHJ5bG9jayBiZWNvbWVzDQo+IHVucmVs aWFibGUgYXMgdGhlIHNlbWFwaG9yZSBjb3VudGVyIGlzIG5vdCBhbHdheXMgZGVjcmVtZW50ZWQu DQoNClByZXZpb3VzIHBhdGNoIHdhcyBnYXJibGVkIGJ5IE91dGxvb2sgLSB0aGlzIG9uZSBzaG91 bGQgYmUgY2xlYW46DQoNCi0tLSBhL2luY2x1ZGUvYXNtLW1pcHMvYXRvbWljLmgJMjAwOC0wNi0y NSAyMjozODo0My4xNTk3MzkwMDAgLTA3MDANCisrKyBiL2luY2x1ZGUvYXNtLW1pcHMvYXRvbWlj LmgJMjAwOC0wNi0yNSAyMjozOTowNy41NTIwNjUwMDAgLTA3MDANCkBAIC0yOTIsMTAgKzI5Miwx MCBAQCBzdGF0aWMgX19pbmxpbmVfXyBpbnQgYXRvbWljX3N1Yl9pZl9wb3NpDQogCQkiCWJlcXoJ JTAsIDJmCQkJCQlcbiINCiAJCSIJIHN1YnUJJTAsICUxLCAlMwkJCQlcbiINCiAJCSIJLnNldAly ZW9yZGVyCQkJCQlcbiINCi0JCSIxOgkJCQkJCQlcbiINCiAJCSIJLnN1YnNlY3Rpb24gMgkJCQkJ XG4iDQogCQkiMjoJYgkxYgkJCQkJXG4iDQogCQkiCS5wcmV2aW91cwkJCQkJXG4iDQorCQkiMToJ CQkJCQkJXG4iDQogCQkiCS5zZXQJbWlwczAJCQkJCVxuIg0KIAkJOiAiPSZyIiAocmVzdWx0KSwg Ij0mciIgKHRlbXApLCAiPW0iICh2LT5jb3VudGVyKQ0KIAkJOiAiSXIiIChpKSwgIm0iICh2LT5j b3VudGVyKQ0KQEAgLTY4MiwxMCArNjgyLDEwIEBAIHN0YXRpYyBfX2lubGluZV9fIGxvbmcgYXRv bWljNjRfc3ViX2lmX3ANCiAJCSIJYmVxegklMCwgMmYJCQkJCVxuIg0KIAkJIgkgZHN1YnUJJTAs ICUxLCAlMwkJCQlcbiINCiAJCSIJLnNldAlyZW9yZGVyCQkJCQlcbiINCi0JCSIxOgkJCQkJCQlc biINCiAJCSIJLnN1YnNlY3Rpb24gMgkJCQkJXG4iDQogCQkiMjoJYgkxYgkJCQkJXG4iDQogCQki CS5wcmV2aW91cwkJCQkJXG4iDQorCQkiMToJCQkJCQkJXG4iDQogCQkiCS5zZXQJbWlwczAJCQkJ CVxuIg0KIAkJOiAiPSZyIiAocmVzdWx0KSwgIj0mciIgKHRlbXApLCAiPW0iICh2LT5jb3VudGVy KQ0KIAkJOiAiSXIiIChpKSwgIm0iICh2LT5jb3VudGVyKQ0K From markus.gothe@27m.se Wed Jul 2 01:29:04 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 01:29:09 +0100 (BST) Received: from mail.lysator.liu.se ([130.236.254.3]:38100 "EHLO mail.lysator.liu.se") by ftp.linux-mips.org with ESMTP id S32724961AbYGBA3E (ORCPT ); Wed, 2 Jul 2008 01:29:04 +0100 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.lysator.liu.se (Postfix) with ESMTP id 83ECD200FCED; Wed, 2 Jul 2008 02:29:00 +0200 (CEST) Received: from mail.lysator.liu.se ([127.0.0.1]) by localhost (lenin.lysator.liu.se [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 05858-01-92; Wed, 2 Jul 2008 02:28:59 +0200 (CEST) Received: from [192.168.10.105] (h-60-134.A163.cust.bahnhof.se [79.136.60.134]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.lysator.liu.se (Postfix) with ESMTP id B5DCB200A240; Wed, 2 Jul 2008 02:28:59 +0200 (CEST) Cc: linux-mips@linux-mips.org Message-Id: <1CA160A5-AC66-4BBF-9C88-0C2B9FF40E6E@27m.se> From: Markus Gothe To: "Morten Larsen" In-Reply-To: Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg=pgp-sha1; boundary="Apple-Mail-24-428131126" Mime-Version: 1.0 (Apple Message framework v926) Subject: Re: [SPAM] RE: Bug in atomic_sub_if_positive Date: Wed, 2 Jul 2008 02:28:52 +0200 References: X-Pgp-Agent: GPGMail d53 (v53, Leopard) Content-Transfer-Encoding: 7bit X-Mailer: Apple Mail (2.926) X-Virus-Scanned: by amavisd-new-20030616-p10 (Debian) at lysator.liu.se Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19687 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markus.gothe@27m.se Precedence: bulk X-list: linux-mips Content-Length: 18425 Lines: 354 This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --Apple-Mail-24-428131126 Content-Type: multipart/alternative; boundary=Apple-Mail-23-428131087 --Apple-Mail-23-428131087 Content-Type: text/plain; charset=ISO-8859-1; format=flowed; delsp=yes Content-Transfer-Encoding: quoted-printable NACK. You must realize that 1b stands for 'label 1, backwards', so correctly =20= it would be '2: b 1f'... Which is a kind off inconsequent numbering in =20= this case. //Markus On 2 Jul 2008, at 02:12, Morten Larsen wrote: > >> As far as I can tell the branch optimization fixes in 2.6.21 =20 >> introduced >> a bug in atomic_sub_if_positive that causes it to return even when =20= >> the >> sc instruction fails. The result is that e.g. down_trylock becomes >> unreliable as the semaphore counter is not always decremented. > > Previous patch was garbled by Outlook - this one should be clean: > > --- a/include/asm-mips/atomic.h 2008-06-25 22:38:43.159739000 = -0700 > +++ b/include/asm-mips/atomic.h 2008-06-25 22:39:07.552065000 = -0700 > @@ -292,10 +292,10 @@ static __inline__ int atomic_sub_if_posi > " beqz %0, 2f = \n" > " subu %0, %1, %3 = \n" > " .set reorder = \n" > - "1: = \n" > " .subsection 2 = \n" > "2: b 1b = \n" > " .previous = \n" > + "1: = \n" > " .set mips0 = \n" > : "=3D&r" (result), "=3D&r" (temp), "=3Dm" (v->counter) > : "Ir" (i), "m" (v->counter) > @@ -682,10 +682,10 @@ static __inline__ long atomic64_sub_if_p > " beqz %0, 2f = \n" > " dsubu %0, %1, %3 = \n" > " .set reorder = \n" > - "1: = \n" > " .subsection 2 = \n" > "2: b 1b = \n" > " .previous = \n" > + "1: = \n" > " .set mips0 = \n" > : "=3D&r" (result), "=3D&r" (temp), "=3Dm" (v->counter) > : "Ir" (i), "m" (v->counter) _______________________________________ Mr Markus Gothe Software Engineer Phone: +46 (0)13 21 81 20 (ext. 1046) Fax: +46 (0)13 21 21 15 Mobile: +46 (0)70 348 44 35 Diskettgatan 11, SE-583 35 Link=F6ping, Sweden www.27m.com --Apple-Mail-23-428131087 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable NACK.

You = must realize that 1b stands for 'label 1, backwards', so correctly it = would be '2: b 1f'... Which is a kind off inconsequent numbering in this = case.

//Markus

On 2 Jul = 2008, at 02:12, Morten Larsen wrote:


As far as I can tell = the branch optimization fixes in 2.6.21 = introduced
a bug in = atomic_sub_if_positive that causes it to return even when = the
sc instruction fails. The = result is that e.g. down_trylock becomes
unreliable as the semaphore counter is not always = decremented.

Previous patch was garbled by Outlook - = this one should be clean:

--- a/include/asm-mips/atomic.h = 2008-06-25 22:38:43.159739000 -0700
+++ = b/include/asm-mips/atomic.h 2008-06-25 22:39:07.552065000 = -0700
@@ -292,10 +292,10 @@ static __inline__ int = atomic_sub_if_posi
" beqz %0, 2f \n"
= = = " = subu = %0, %1, %3= = = = \n"
= = " = .set = reorder = = = = = \n"
- = = "1: = = = = = = = \n"
= = " = .subsection 2 \n"
"2: b 1b \n"
= = = " = .previous = = = = = \n"
+ = = "1: = = = = = = = \n"
= = " = .set = mips0 = = = = = \n"
= = : "=3D&r" (result), "=3D&r" (temp), "=3Dm" = (v->counter)
= = : "Ir" (i), "m" (v->counter)
@@ -682,10 +682,10 @@ static = __inline__ long atomic64_sub_if_p
" beqz %0, 2f \n"
= = = " = dsubu = %0, %1, %3= = = = \n"
= = " = .set = reorder = = = = = \n"
- = = "1: = = = = = = = \n"
= = " = .subsection 2 \n"
"2: b 1b \n"
= = = " = .previous = = = = = \n"
+ = = "1: = = = = = = = \n"
= = " = .set = mips0 = = = = = \n"
= = : "=3D&r" (result), "=3D&r" (temp), "=3Dm" = (v->counter)
= = : "Ir" (i), "m" (v->counter)


Mr Markus = Gothe
Software Engineer

Phone: = +46 (0)13 21 81 20 (ext. 1046)
Fax: +46 = (0)13 21 21 15
Mobile: +46 (0)70 348 44 = 35
Diskettgatan 11, SE-583 35 Link=F6ping, = Sweden



= --Apple-Mail-23-428131087-- --Apple-Mail-24-428131126 content-type: application/pgp-signature; x-mac-type=70674453; name=PGP.sig content-description: This is a digitally signed message part content-disposition: inline; filename=PGP.sig content-transfer-encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.8 (Darwin) iEYEARECAAYFAkhqy8QACgkQ6I0XmJx2Nry2bACgxwjEQt5GQ3vtWzAHbSajQd6D 10oAn1VdcTxfdXQQIPqn9/szlSDDVHHD =WE4W -----END PGP SIGNATURE----- --Apple-Mail-24-428131126-- From mlarsen@broadcom.com Wed Jul 2 01:43:50 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 01:43:58 +0100 (BST) Received: from mms2.broadcom.com ([216.31.210.18]:11528 "EHLO mms2.broadcom.com") by ftp.linux-mips.org with ESMTP id S29054755AbYGBAnu convert rfc822-to-8bit (ORCPT ); Wed, 2 Jul 2008 01:43:50 +0100 Received: from [10.11.16.99] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Tue, 01 Jul 2008 17:43:26 -0700 X-Server-Uuid: D3C04415-6FA8-4F2C-93C1-920E106A2031 Received: by mail-irva-10.broadcom.com (Postfix, from userid 47) id D78E82B1; Tue, 1 Jul 2008 17:43:26 -0700 (PDT) Received: from mail-irva-8.broadcom.com (mail-irva-8 [10.11.18.52]) by mail-irva-10.broadcom.com (Postfix) with ESMTP id C37922B0; Tue, 1 Jul 2008 17:43:26 -0700 (PDT) Received: from mail-sj1-12.sj.broadcom.com (mail-sj1-12.sj.broadcom.com [10.16.128.215]) by mail-irva-8.broadcom.com (MOS 3.7.5a-GA) with ESMTP id GZD41167; Tue, 1 Jul 2008 17:43:15 -0700 (PDT) Received: from NT-SJCA-0750.brcm.ad.broadcom.com (nt-sjca-0750 [10.16.192.220]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id B3B6A20501; Tue, 1 Jul 2008 17:43:15 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Subject: RE: [SPAM] RE: Bug in atomic_sub_if_positive Date: Tue, 1 Jul 2008 17:43:14 -0700 Message-ID: In-Reply-To: <1CA160A5-AC66-4BBF-9C88-0C2B9FF40E6E@27m.se> Thread-Topic: [SPAM] RE: Bug in atomic_sub_if_positive Thread-Index: Acjb2qZnclxNhMgNQHeIqx5CltCbqAAALd2g From: "Morten Larsen" To: "Markus Gothe" cc: linux-mips@linux-mips.org X-WSS-ID: 647410A43D075149103-01-01 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19688 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlarsen@broadcom.com Precedence: bulk X-list: linux-mips Content-Length: 3240 Lines: 103 Thanks for the reply. My main point is that if the sc instruction fails (returns zero) then we need to start over (with another ll instruction.) It appears that the current code does not do this correctly. If you have a better suggestion for a patch, that's fine with me. Below is the code from the 2.6.20.21 kernel, which is (also) working for me. =:-) Morten __asm__ __volatile__( " .set mips3 \n" "1: ll %1, %2 # atomic_sub_if_positive\n" " subu %0, %1, %3 \n" " bltz %0, 1f \n" " sc %0, %2 \n" " .set noreorder \n" " beqz %0, 1b \n" " subu %0, %1, %3 \n" " .set reorder \n" "1: \n" " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); ________________________________ From: Markus Gothe [mailto:markus.gothe@27m.se] Sent: Tuesday, July 01, 2008 5:29 PM To: Morten Larsen Cc: linux-mips@linux-mips.org Subject: Re: [SPAM] RE: Bug in atomic_sub_if_positive NACK. You must realize that 1b stands for 'label 1, backwards', so correctly it would be '2: b 1f'... Which is a kind off inconsequent numbering in this case. //Markus On 2 Jul 2008, at 02:12, Morten Larsen wrote: As far as I can tell the branch optimization fixes in 2.6.21 introduced a bug in atomic_sub_if_positive that causes it to return even when the sc instruction fails. The result is that e.g. down_trylock becomes unreliable as the semaphore counter is not always decremented. Previous patch was garbled by Outlook - this one should be clean: --- a/include/asm-mips/atomic.h 2008-06-25 22:38:43.159739000 -0700 +++ b/include/asm-mips/atomic.h 2008-06-25 22:39:07.552065000 -0700 @@ -292,10 +292,10 @@ static __inline__ int atomic_sub_if_posi " beqz %0, 2f \n" " subu %0, %1, %3 \n" " .set reorder \n" - "1: \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" + "1: \n" " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) @@ -682,10 +682,10 @@ static __inline__ long atomic64_sub_if_p " beqz %0, 2f \n" " dsubu %0, %1, %3 \n" " .set reorder \n" - "1: \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" + "1: \n" " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) _______________________________________ Mr Markus Gothe Software Engineer Phone: +46 (0)13 21 81 20 (ext. 1046) Fax: +46 (0)13 21 21 15 Mobile: +46 (0)70 348 44 35 Diskettgatan 11, SE-583 35 Linköping, Sweden www.27m.com From Adam.Nemet@caviumnetworks.com Wed Jul 2 08:01:35 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 08:01:41 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11102 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S36907672AbYGBHBf (ORCPT ); Wed, 2 Jul 2008 08:01:35 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Wed, 02 Jul 2008 03:00:37 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 2 Jul 2008 00:00:36 -0700 Received: from localhost.localdomain ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 2 Jul 2008 00:00:36 -0700 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by localhost.localdomain (8.14.2/8.13.7/Debian-2) with ESMTP id m6270YFb016824; Wed, 2 Jul 2008 00:00:34 -0700 Received: (from anemet@localhost) by localhost.localdomain (8.14.2/8.13.7/Submit) id m6270Xlb016823; Wed, 2 Jul 2008 00:00:33 -0700 To: binutils@sourceware.org Cc: gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Subject: Re: RFC: Adding non-PIC executable support to MIPS References: <87y74pxwyl.fsf@firetop.home> <20080701202236.GA1534@caradoc.them.org> <87zlp149ot.fsf@firetop.home> From: Adam Nemet Date: Wed, 02 Jul 2008 00:00:33 -0700 In-Reply-To: <87zlp149ot.fsf@firetop.home> (Richard Sandiford's message of "Tue, 01 Jul 2008 21:43:30 +0100") Message-ID: <87myl093e6.fsf@localhost.localdomain.i-did-not-set--mail-host-address--so-tickle-me> User-Agent: Gnus/5.1007 (Gnus v5.10.7) XEmacs/21.4.20 (linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-OriginalArrivalTime: 02 Jul 2008 07:00:36.0414 (UTC) FILETIME=[54222DE0:01C8DC11] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19689 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemet@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1712 Lines: 34 Richard Sandiford writes: > However, IMO, your argument about MTI being the central authority > is a killer one. The purpose of the GNU tools should be to follow > appropriate standards where applicable (and extend them where it > seems wise). So from that point of view, I agree that the GNU tools > should follow the ABI that Nigel and MTI set down. Consider my > patch withdrawn. While I'm not entirely clear how this decision came about I'd like to point out that it is unfortunate that MTI had not sought wider consensus for this ABI extension among MIPS implementors and the community. We would not be in this situation with duplicated efforts and much frustration if this proposal had been circulated properly ahead of time. > I've been thinking about that a lot recently, since I heard about > your implementation. I kind-of guessed it had been agreed with MTI > beforehand (although I hadn't realised MTI themselves had written > the specification). Having thought it over, I think it would be best > if I stand down as a MIPS maintainer and if someone with the appropriate > commercial connections is appointed instead. I'd recommend any > combination of yourself, Adam Nemet and David Daney (subject to > said people being willing, of course). Richard, while I understand your frustration I really hope that you will reconsider your decision and remain the MIPS maintainer. I think there is a chance that if the community expresses that MTI should seek broader consensus for such proposals they will do so in the future. Your expertise as the GCC maintainer has improved the backend tremendously and and you should be given all the information necessary to continue your great work. Adam From ths@networkno.de Wed Jul 2 11:00:01 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 11:00:07 +0100 (BST) Received: from relay01.mx.bawue.net ([193.7.176.67]:33258 "EHLO relay01.mx.bawue.net") by ftp.linux-mips.org with ESMTP id S62065451AbYGBKAB (ORCPT ); Wed, 2 Jul 2008 11:00:01 +0100 Received: from lagash (88-106-136-149.dynamic.dsl.as9105.com [88.106.136.149]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by relay01.mx.bawue.net (Postfix) with ESMTP id B485B48916; Wed, 2 Jul 2008 11:59:57 +0200 (CEST) Received: from ths by lagash with local (Exim 4.69) (envelope-from ) id 1KDz80-0001q7-4o; Wed, 02 Jul 2008 10:59:56 +0100 Date: Wed, 2 Jul 2008 10:59:56 +0100 From: Thiemo Seufer To: Morten Larsen Cc: linux-mips@linux-mips.org Subject: Re: Bug in atomic_sub_if_positive Message-ID: <20080702095955.GA7007@networkno.de> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19690 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Content-Length: 1065 Lines: 28 Morten Larsen wrote: > > > As far as I can tell the branch optimization fixes in 2.6.21 introduced > > a bug in atomic_sub_if_positive that causes it to return even when the > > sc instruction fails. The result is that e.g. down_trylock becomes > > unreliable as the semaphore counter is not always decremented. > > Previous patch was garbled by Outlook - this one should be clean: > > --- a/include/asm-mips/atomic.h 2008-06-25 22:38:43.159739000 -0700 > +++ b/include/asm-mips/atomic.h 2008-06-25 22:39:07.552065000 -0700 > @@ -292,10 +292,10 @@ static __inline__ int atomic_sub_if_posi > " beqz %0, 2f \n" > " subu %0, %1, %3 \n" > " .set reorder \n" > - "1: \n" > " .subsection 2 \n" > "2: b 1b \n" > " .previous \n" > + "1: \n" AFAICS this change should make no difference to the generated code. I suspect you assembler handles .subsection incorrectly. Can you provide a disassembled exapmle which gets altered by this patch? Also, please tell us the exact version of the assembler you use. Thiemo From ths@networkno.de Wed Jul 2 11:13:58 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 11:14:05 +0100 (BST) Received: from relay01.mx.bawue.net ([193.7.176.67]:14793 "EHLO relay01.mx.bawue.net") by ftp.linux-mips.org with ESMTP id S62065707AbYGBKN6 (ORCPT ); Wed, 2 Jul 2008 11:13:58 +0100 Received: from lagash (88-106-136-149.dynamic.dsl.as9105.com [88.106.136.149]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by relay01.mx.bawue.net (Postfix) with ESMTP id AE71448916; Wed, 2 Jul 2008 12:13:57 +0200 (CEST) Received: from ths by lagash with local (Exim 4.69) (envelope-from ) id 1KDzLY-00026W-LX; Wed, 02 Jul 2008 11:13:56 +0100 Date: Wed, 2 Jul 2008 11:13:56 +0100 From: Thiemo Seufer To: binutils@sourceware.org, gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Subject: Re: RFC: Adding non-PIC executable support to MIPS Message-ID: <20080702101356.GB7007@networkno.de> References: <87y74pxwyl.fsf@firetop.home> <20080701202236.GA1534@caradoc.them.org> <87zlp149ot.fsf@firetop.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87zlp149ot.fsf@firetop.home> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19691 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Content-Length: 2438 Lines: 56 Richard Sandiford wrote: > Daniel Jacobowitz writes: > > We've shipped our version. Richard's version has presumably also > > shipped. > > Right. > > > We did negotiate the ABI changes with MTI; this is not quite > > as good as doing it in full view, but it was the best we could manage > > and MTI is as close to a central authority for the MIPS psABI as > > exists today. > > > > Richard, what are your thoughts on reconciling the differences? You > > can surely guess that I want to avoid changing our ABI now, even for > > relatively significant technical reasons - I'm all ears if there's a > > major reason, but in the comparisons I do not see one. > > I suppose I still support the trade-off between the 5-insn MIPS I stubs > (with extra-long variation for large PLT indices) and the absolute > .got.plt address I used. And I still think it's shame we're treating > STO_MIPS_PLT and STO_MIPS16 as separate; we then only have 1 bit of > st_other unclaimed. > > However, IMO, your argument about MTI being the central authority > is a killer one. The purpose of the GNU tools should be to follow > appropriate standards where applicable (and extend them where it > seems wise). So from that point of view, I agree that the GNU tools > should follow the ABI that Nigel and MTI set down. Consider my > patch withdrawn. > > TBH, the close relationship between CodeSourcery and MTI > make it difficult for a non-Sourcerer and non-MTI employee > to continue to be a MIPS maintainer. I won't be in-the-know > about this sort of thing. > > I've been thinking about that a lot recently, since I heard about > your implementation. I kind-of guessed it had been agreed with MTI > beforehand (although I hadn't realised MTI themselves had written > the specification). The specification is a co-production of MTI and CS. I believe the reason why it wasn't discussed in a wider audience is that it occured to nobody there could be a parallel effort going on after all those years! > Having thought it over, I think it would be best > if I stand down as a MIPS maintainer and if someone with the appropriate > commercial connections is appointed instead. I'd recommend any > combination of yourself, Adam Nemet and David Daney (subject to > said people being willing, of course). FWIW, I believe a person who is _not_ in the midst of the commercial pressures adds valuable perspective as a maintainer. Thiemo From anemo@mba.ocn.ne.jp Wed Jul 2 11:31:41 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 11:31:44 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:47559 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S62065862AbYGBKbl (ORCPT ); Wed, 2 Jul 2008 11:31:41 +0100 Received: from no.name.available by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [213.58.128.207]) with ESMTP; Wed, 2 Jul 2008 19:31:39 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 5C8C644FDF; Wed, 2 Jul 2008 19:31:34 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 51B9C18602; Wed, 2 Jul 2008 19:31:34 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id m62AVXfl091762; Wed, 2 Jul 2008 19:31:33 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Wed, 02 Jul 2008 19:31:33 +0900 (JST) Message-Id: <20080702.193133.211490377.nemoto@toshiba-tops.co.jp> To: ths@networkno.de Cc: mlarsen@broadcom.com, linux-mips@linux-mips.org Subject: Re: Bug in atomic_sub_if_positive From: Atsushi Nemoto In-Reply-To: <20080702095955.GA7007@networkno.de> References: <20080702095955.GA7007@networkno.de> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 6.1 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19692 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1926 Lines: 61 On Wed, 2 Jul 2008 10:59:56 +0100, Thiemo Seufer wrote: > > --- a/include/asm-mips/atomic.h 2008-06-25 22:38:43.159739000 -0700 > > +++ b/include/asm-mips/atomic.h 2008-06-25 22:39:07.552065000 -0700 > > @@ -292,10 +292,10 @@ static __inline__ int atomic_sub_if_posi > > " beqz %0, 2f \n" > > " subu %0, %1, %3 \n" > > " .set reorder \n" > > - "1: \n" > > " .subsection 2 \n" > > "2: b 1b \n" > > " .previous \n" > > + "1: \n" > > AFAICS this change should make no difference to the generated code. I > suspect you assembler handles .subsection incorrectly. Can you provide > a disassembled exapmle which gets altered by this patch? Also, please > tell us the exact version of the assembler you use. Why no defference? The '1b' in subsection refer backword '1' label on the source code (which is a label for LL insn in this case with the patch) ? Anyway I can provide them. I'm using vanilla 2.17 and 2.18. Without the patch: 801233bc : 801233bc: lui v0,0x8038 801233c0: ll a0,31976(v0) 801233c4: addiu v1,a0,-1 801233c8: bltz v1,801233dc 801233cc: nop 801233d0: sc v1,31976(v0) 801233d4: beqz v1,80124dac 801233d8: addiu v1,a0,-1 801233dc: bltz v1,801233fc 801233e0: li v0,-1 ... 80124dac: b 801233dc 80124db0: nop With the patch: 801233bc : 801233bc: lui v0,0x8038 801233c0: ll a0,31976(v0) 801233c4: addiu v1,a0,-1 801233c8: bltz v1,801233dc 801233cc: nop 801233d0: sc v1,31976(v0) 801233d4: beqz v1,80124dac 801233d8: addiu v1,a0,-1 801233dc: bltz v1,801233fc 801233e0: li v0,-1 ... 80124dac: b 801233c0 80124db0: nop The patch looks correct. --- Atsushi Nemoto From ths@networkno.de Wed Jul 2 11:52:01 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 11:52:10 +0100 (BST) Received: from relay01.mx.bawue.net ([193.7.176.67]:43964 "EHLO relay01.mx.bawue.net") by ftp.linux-mips.org with ESMTP id S62068190AbYGBKwB (ORCPT ); Wed, 2 Jul 2008 11:52:01 +0100 Received: from lagash (88-106-136-149.dynamic.dsl.as9105.com [88.106.136.149]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by relay01.mx.bawue.net (Postfix) with ESMTP id 5108548918; Wed, 2 Jul 2008 12:51:56 +0200 (CEST) Received: from ths by lagash with local (Exim 4.69) (envelope-from ) id 1KDzwJ-0002F6-Er; Wed, 02 Jul 2008 11:51:55 +0100 Date: Wed, 2 Jul 2008 11:51:55 +0100 From: Thiemo Seufer To: Atsushi Nemoto Cc: mlarsen@broadcom.com, linux-mips@linux-mips.org Subject: Re: Bug in atomic_sub_if_positive Message-ID: <20080702105155.GC7007@networkno.de> References: <20080702095955.GA7007@networkno.de> <20080702.193133.211490377.nemoto@toshiba-tops.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080702.193133.211490377.nemoto@toshiba-tops.co.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19693 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Content-Length: 2112 Lines: 66 Atsushi Nemoto wrote: > On Wed, 2 Jul 2008 10:59:56 +0100, Thiemo Seufer wrote: > > > --- a/include/asm-mips/atomic.h 2008-06-25 22:38:43.159739000 -0700 > > > +++ b/include/asm-mips/atomic.h 2008-06-25 22:39:07.552065000 -0700 > > > @@ -292,10 +292,10 @@ static __inline__ int atomic_sub_if_posi > > > " beqz %0, 2f \n" > > > " subu %0, %1, %3 \n" > > > " .set reorder \n" > > > - "1: \n" > > > " .subsection 2 \n" > > > "2: b 1b \n" > > > " .previous \n" > > > + "1: \n" > > > > AFAICS this change should make no difference to the generated code. I > > suspect you assembler handles .subsection incorrectly. Can you provide > > a disassembled exapmle which gets altered by this patch? Also, please > > tell us the exact version of the assembler you use. > > Why no defference? The '1b' in subsection refer backword '1' label on > the source code (which is a label for LL insn in this case with the > patch) ? Oh. Now that you spelled it out I see it, too. :-) > Anyway I can provide them. I'm using vanilla 2.17 and 2.18. > > Without the patch: > 801233bc : > 801233bc: lui v0,0x8038 > 801233c0: ll a0,31976(v0) > 801233c4: addiu v1,a0,-1 > 801233c8: bltz v1,801233dc > 801233cc: nop > 801233d0: sc v1,31976(v0) > 801233d4: beqz v1,80124dac > 801233d8: addiu v1,a0,-1 > 801233dc: bltz v1,801233fc > 801233e0: li v0,-1 > ... > 80124dac: b 801233dc > 80124db0: nop > > With the patch: > 801233bc : > 801233bc: lui v0,0x8038 > 801233c0: ll a0,31976(v0) > 801233c4: addiu v1,a0,-1 > 801233c8: bltz v1,801233dc > 801233cc: nop > 801233d0: sc v1,31976(v0) > 801233d4: beqz v1,80124dac > 801233d8: addiu v1,a0,-1 > 801233dc: bltz v1,801233fc > 801233e0: li v0,-1 > ... > 80124dac: b 801233c0 > 80124db0: nop > > > The patch looks correct. Agreed. Thiemo From saravanakumar.s@teclever.com Wed Jul 2 12:23:43 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 12:23:49 +0100 (BST) Received: from smtpauth23.prod.mesa1.secureserver.net ([64.202.165.47]:55680 "HELO smtpauth23.prod.mesa1.secureserver.net") by ftp.linux-mips.org with SMTP id S62070200AbYGBLXn (ORCPT ); Wed, 2 Jul 2008 12:23:43 +0100 Received: (qmail 25523 invoked from network); 2 Jul 2008 11:23:34 -0000 Received: from unknown (122.167.166.84) by smtpauth23.prod.mesa1.secureserver.net (64.202.165.47) with ESMTP; 02 Jul 2008 11:23:32 -0000 Subject: kernel configuration_ help From: saravanakumar To: "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" Content-Type: text/plain Date: Wed, 02 Jul 2008 16:52:52 +0530 Message-Id: <1214997772.16081.3.camel@teclever-desktop> Mime-Version: 1.0 X-Mailer: Evolution 2.22.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19694 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: saravanakumar.s@teclever.com Precedence: bulk X-list: linux-mips Content-Length: 264 Lines: 10 hai, i want my usb to access the root file system,for that what are the changes to be done in kernel code, and in the configuration, i think changes to be done in do_mount.c for root delay, if its correct where to give the delay. with regards saravana kumar.s From ralf@linux-mips.org Wed Jul 2 12:25:07 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 12:25:14 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:13533 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S62070260AbYGBLZH (ORCPT ); Wed, 2 Jul 2008 12:25:07 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m62BO6VO007845; Wed, 2 Jul 2008 13:24:31 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m62BO5tu007818; Wed, 2 Jul 2008 12:24:05 +0100 Date: Wed, 2 Jul 2008 12:24:05 +0100 From: Ralf Baechle To: Marian Jancar Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 5/7] gcov: add gcov profiling infrastructure Message-ID: <20080702112404.GB15896@linux-mips.org> References: <48313DE6.30802@de.ibm.com> <20080523001136.59ec8b34.akpm@linux-foundation.org> <20080523084506.GB719@linux-mips.org> <4843DEFD.9020303@satca.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4843DEFD.9020303@satca.net> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19695 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1866 Lines: 39 On Mon, Jun 02, 2008 at 01:52:29PM +0200, Marian Jancar wrote: > Ralf Baechle wrote: > >> {standard input}: Assembler messages: > >> {standard input}:2716: Error: Branch out of range > >> {standard input}:2819: Error: Branch out of range > >> {standard input}:2884: Error: Branch out of range > >> {standard input}:3032: Error: Branch out of range > >> {standard input}:3097: Error: Branch out of range > >> {standard input}:3151: Error: Branch out of range > >> {standard input}:3216: Error: Branch out of range > >> make[1]: *** [drivers/telephony/ixj.o] Error 1 > >> make: *** [drivers/telephony/ixj.o] Error 2 > > > > A known problem which I had decieded to ignore until it begins to actually > > bite. It's triggered by something like this > > > > __asm__ __volatile__( > > " .set mips3 \n" > > "1: ll %0, %1 # atomic_add \n" > > " addu %0, %2 \n" > > " sc %0, %1 \n" > > " beqz %0, 2f \n" > > " .subsection 2 \n" > > "2: b 1b \n" > > " .previous \n" > > " .set mips0 \n" > > : "=&r" (temp), "=m" (v->counter) > > : "Ir" (i), "m" (v->counter)); > > > > when compiled into a large compilation unit. > > Please unignore :) It bites when compiling madwifi (without profiling or > anything such). Can't reproduce this one - what is the cooking receipe based on a recent devel kernel? Ralf From drow@false.org Wed Jul 2 13:08:35 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 13:08:42 +0100 (BST) Received: from NaN.false.org ([208.75.86.248]:40081 "EHLO nan.false.org") by ftp.linux-mips.org with ESMTP id S62072498AbYGBMIf (ORCPT ); Wed, 2 Jul 2008 13:08:35 +0100 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id B5B83982C3; Wed, 2 Jul 2008 12:08:30 +0000 (GMT) Received: from caradoc.them.org (22.svnf5.xdsl.nauticom.net [209.195.183.55]) by nan.false.org (Postfix) with ESMTP id 765F598243; Wed, 2 Jul 2008 12:08:30 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.69) (envelope-from ) id 1KE18P-0003RW-97; Wed, 02 Jul 2008 08:08:29 -0400 Date: Wed, 2 Jul 2008 08:08:29 -0400 From: Daniel Jacobowitz To: binutils@sourceware.org, gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Subject: Re: RFC: Adding non-PIC executable support to MIPS Message-ID: <20080702120829.GA12595@caradoc.them.org> Mail-Followup-To: binutils@sourceware.org, gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com References: <87y74pxwyl.fsf@firetop.home> <20080701202236.GA1534@caradoc.them.org> <87zlp149ot.fsf@firetop.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87zlp149ot.fsf@firetop.home> User-Agent: Mutt/1.5.17 (2008-05-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19696 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@debian.org Precedence: bulk X-list: linux-mips Content-Length: 2579 Lines: 52 On Tue, Jul 01, 2008 at 09:43:30PM +0100, Richard Sandiford wrote: > I suppose I still support the trade-off between the 5-insn MIPS I stubs > (with extra-long variation for large PLT indices) and the absolute > .got.plt address I used. And I still think it's shame we're treating > STO_MIPS_PLT and STO_MIPS16 as separate; we then only have 1 bit of > st_other unclaimed. I'm undecided about the MIPS I issue, but I completely agree about STO_MIPS16/STO_MIPS_PLT. I wish we'd thought of that too. At least our implementation didn't have STO_MIPS_PIC; so there's one bit left, and assuming we add support for ld -r (likely) we can do it your way. For the final merged versions of these patches, even if they implement "our" version, I hope to draw heavily on your work. It's always high quality and the GOT cleanups in particular look very useful. > TBH, the close relationship between CodeSourcery and MTI > make it difficult for a non-Sourcerer and non-MTI employee > to continue to be a MIPS maintainer. I won't be in-the-know > about this sort of thing. > > I've been thinking about that a lot recently, since I heard about > your implementation. I kind-of guessed it had been agreed with MTI > beforehand (although I hadn't realised MTI themselves had written > the specification). Having thought it over, I think it would be best > if I stand down as a MIPS maintainer and if someone with the appropriate > commercial connections is appointed instead. I'd recommend any > combination of yourself, Adam Nemet and David Daney (subject to > said people being willing, of course). I'm sorry you feel this way. I believe strongly that corporate affiliation is not a useful indicator for maintainership; the system we have set up here relies more on individual knowledge and experience than affiliation. We could have done more to keep everyone informed of our progress; I could write an essay on why we didn't, but I'd rather not. We're talking internally about how to avoid this unfortunate coincidence in the future. Anyway, there's plenty of blame to go around. I think you're doing an excellent job as a GCC maintainer, and so does everyone I spoke to about this at CS. If you no longer have the time or incentive to do it, I won't argue with you about stepping down, but please don't because of this incident. [In any case, I'd decline; I'm trying to shed some of my existing maintenance responsibilities so that I can spend more time on the ones I care most about. Anyone else want to be binutils release manager?] -- Daniel Jacobowitz CodeSourcery From drow@false.org Wed Jul 2 13:47:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 13:47:31 +0100 (BST) Received: from NaN.false.org ([208.75.86.248]:32132 "EHLO nan.false.org") by ftp.linux-mips.org with ESMTP id S62074288AbYGBMrZ (ORCPT ); Wed, 2 Jul 2008 13:47:25 +0100 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 91CAB982C3; Wed, 2 Jul 2008 12:47:23 +0000 (GMT) Received: from caradoc.them.org (22.svnf5.xdsl.nauticom.net [209.195.183.55]) by nan.false.org (Postfix) with ESMTP id 3FD8398243; Wed, 2 Jul 2008 12:47:22 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.69) (envelope-from ) id 1KE1k2-00043n-6W; Wed, 02 Jul 2008 08:47:22 -0400 Date: Wed, 2 Jul 2008 08:47:22 -0400 From: Daniel Jacobowitz To: Yoriko Komatsuzaki , Chris Friesen Cc: libc-ports , linux-mips@linux-mips.org Subject: Re: do-lookup.h regarding to mips/dlsym and libstdc++ Message-ID: <20080702124722.GA15301@caradoc.them.org> References: <483AF8BC.7020603@nortel.com> <20080129132739.5D6B.YORIKO@sm.sony.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <483AF8BC.7020603@nortel.com> <20080129132739.5D6B.YORIKO@sm.sony.co.jp> User-Agent: Mutt/1.5.17 (2008-05-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19697 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@debian.org Precedence: bulk X-list: linux-mips Content-Length: 1360 Lines: 33 On Tue, Jan 29, 2008 at 01:32:20PM +0900, Yoriko Komatsuzaki wrote: > Because even though UNDEF symbol is found, > it can process as global symbol for the rare occasion. > > This phenomena is showed only in mips. When libstdc++ is linked in > proior libc, the malloc's entry in libstdc++ MIPS.stubs table seemed to > be recognized as the malloc global symbol ... > > How do you feel about it? On Mon, May 26, 2008 at 11:51:56AM -0600, Chris Friesen wrote: > On MIPS, the DEFAULT returns the address of this libraries undefined > symbol for the extern and NEXT returns our external procedure. Putting > in a second RTLD_NEXT call returned the real sigaction address. > > This worked for most procedures we are looking for. However, during > booting, we have an app that uses a specific library which has an extern > for sigaction as well and now in the preloaded code we need a fourth call > to dlsym to skip that one. Hi folks, This bug is fixed as a by-product of support for non-PIC MIPS executables. Either Richard's patch or CodeSourcery's, applied to glibc, should suffice. It'll be another week or two at least before they're applied to CVS, but in the mean time you can find them here: http://sourceware.org/ml/binutils/2008-06/msg00280.html http://sourceware.org/ml/binutils/2008-07/msg00008.html -- Daniel Jacobowitz CodeSourcery From ralf@linux-mips.org Wed Jul 2 14:18:07 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 14:18:15 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:10199 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S62076964AbYGBNSH (ORCPT ); Wed, 2 Jul 2008 14:18:07 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m62DHKom003359 for ; Wed, 2 Jul 2008 15:17:46 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m62DHKvJ003352 for linux-mips@linux-mips.org; Wed, 2 Jul 2008 14:17:20 +0100 Date: Wed, 2 Jul 2008 14:17:20 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: Branch out of range issues Message-ID: <20080702131720.GC15896@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19698 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 412 Lines: 10 Recently a few people have reported "branch out of range" problems building recent kernels. One way to fix those - at the risk of causing considerable collateral damage - is using -ffunction-sections. I'm hessitating to make a change like this so short before a kernel release since at this point I'm not convinved that this is actually needed. Anyway I'd appreciate feedback on the problem. Thanks, Ralf From tsbogend@alpha.franken.de Wed Jul 2 20:06:08 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 20:06:17 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:33459 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S23869175AbYGBTGH (ORCPT ); Wed, 2 Jul 2008 20:06:07 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KE7eW-0000rd-00; Wed, 02 Jul 2008 21:06:04 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 26B63C214C; Wed, 2 Jul 2008 21:06:03 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] Enable FAST-20 for onboard scsi To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20080702190603.26B63C214C@solo.franken.de> Date: Wed, 2 Jul 2008 21:06:03 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19699 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 1057 Lines: 29 Both onboard controller of the O2 support FAST-20 transfer speeds, but the bit, which signals that to the aic driver, isn't set. Instead of adding detection code to the scsi driver, we just fake the missing bit in the PCI config space of the scsi chips. Signed-off-by: Thomas Bogendoerfer --- arch/mips/pci/ops-mace.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c index e958818..1cfb558 100644 --- a/arch/mips/pci/ops-mace.c +++ b/arch/mips/pci/ops-mace.c @@ -61,6 +61,13 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, /* ack possible master abort */ mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT; mace->pci.control = control; + /* + * someone forgot to set the ultra bit for the onboard + * scsi chips; we fake it here + */ + if (bus->number == 0 && reg == 0x40 && size == 4 && + (devfn == (1 << 3) || devfn == (2 << 3))) + *val |= 0x1000; DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val); From rdsandiford@googlemail.com Wed Jul 2 20:56:09 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 20:56:16 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.184]:38185 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S23871867AbYGBT4J (ORCPT ); Wed, 2 Jul 2008 20:56:09 +0100 Received: by nf-out-0910.google.com with SMTP id h3so145727nfh.14 for ; Wed, 02 Jul 2008 12:56:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:mail-followup-to:cc :subject:references:date:in-reply-to:message-id:user-agent :mime-version:content-type; bh=Fcjc+mfdyY8AvqUKoZxxJr8gIq3fGDsnY3eUf3hJ+dk=; b=pUus5Fo1FqM9RCBiBSzLCTn9N6p2pHwZDJ/UlLhiSBkWUz4eQ4yeZjhiGrmOlELypE Zn9U6Esbvn92Kb6dpY6LtS/cSkkQRNaZGpVmGOYvEOO9xjq5rhTY9ShRmx+9RgCJ5QKw njNogLoLC9XIp6Qept96DpPADMnpl1ozVVn/Q= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:mail-followup-to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-type; b=YhGaB3yGhgrhIDeiTP2Y3IC0iNZW83Bgx+rzYj9tLX4iJyNIwRLJIVwc6qtxmol17g NxPpcd2+rUXeFRf070z3S3/LuNu4jvlOFbdU0BxE6zXCUQNQPXBL+/9uTgLHeqlyWbfV xFkjsyHWPD0PkCFcZlgOSREOpM96ufSYI07jg= Received: by 10.210.34.2 with SMTP id h2mr6958630ebh.122.1215028567483; Wed, 02 Jul 2008 12:56:07 -0700 (PDT) Received: from localhost ( [79.67.7.185]) by mx.google.com with ESMTPS id g11sm4839009gve.8.2008.07.02.12.56.03 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 02 Jul 2008 12:56:04 -0700 (PDT) From: Richard Sandiford To: binutils@sourceware.org Mail-Followup-To: binutils@sourceware.org,gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Cc: gcc@gcc.gnu.org, linux-mips@linux-mips.org Subject: Re: RFC: Adding non-PIC executable support to MIPS References: <87y74pxwyl.fsf@firetop.home> <20080701202236.GA1534@caradoc.them.org> <87zlp149ot.fsf@firetop.home> <20080702120829.GA12595@caradoc.them.org> Date: Wed, 02 Jul 2008 20:55:54 +0100 In-Reply-To: <20080702120829.GA12595@caradoc.them.org> (Daniel Jacobowitz's message of "Wed\, 2 Jul 2008 08\:08\:29 -0400") Message-ID: <87abh0m56d.fsf@firetop.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19700 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rdsandiford@googlemail.com Precedence: bulk X-list: linux-mips Content-Length: 2948 Lines: 76 Thanks to everyone for their kind messages. I won't drag this out for non-MIPS folk by replying publicly to each one. Daniel Jacobowitz writes: > the GOT cleanups in particular look very useful. Thanks. To be clear: the withdrawal was simply for the patches in this message. Although the original motivation for the GOT cleanups was to reduce the amount of wasted space in mostly-non-PIC executables, they're really a separate change in their own right. My hope was that, even without the non-PIC stuff, the new code might be more maintainable than what we have now. > We could have done more to keep everyone informed of our progress; I > could write an essay on why we didn't, but I'd rather not. We're > talking internally about how to avoid this unfortunate coincidence in > the future. Anyway, there's plenty of blame to go around. FWIW, I don't blame MTI or CS at all for this. Duplicated effort is part of the risk one runs with the model that both you (CS) and I were following. (And for the record, I say "I" because the fault was mine rather than Specifix's.) When I was doing the work, I was expecting to use the patches as the basis for a discussion on this list. And I honestly expected to have to change some of the details as a result. E.g. I wasn't sure what the reaction would be to requiring MIPS II or above. So it's no surprise that my version as posted is not going to be used. And when I learnt about your alternative implementation, I was expecting some of that implementation to be chosen instead. The difficulty was simply that, as you rightly said, MTI are the authority here. That made any discussion on this list moot. That was just an attempt to clarify things rather than force you into writing an essay ;) Anyway, enough of that. Back to technical stuff. Would it work if we had stubs like this: lui t7,%hi(.got.plt entry) lw t9,%lo(.got.plt entry)(t7) addiu t8,t7,%lo(.got.plt entry) jr t9 ... lui t7,%hi(.got.plt entry + 4) [next entry] and a header like this: lui gp,%hi(.got.plt) lw t9,%lo(.got.plt)(gp) addiu gp,gp,%lo(.got.plt) subu t8,t8,gp move t7,ra srl t8,t8,2 jalr t9 subu t8,t8,2 (Key for my benefit, 'cos I can only think in terms of numerical registers: t7 = $15 t8 = $24 t9 = $25) The size of the header and first 0x10000 stubs would be the same. I think it would also preserve the resolver interface while removing the need for the extra-large .plts. The only incompatibility I can see would be that objdump on older executables would not get the foo@plt symbols right for large indices. OTOH, perhaps you could argue that the extra complication of the two PLT entries doesn't count for much given that the code is already written. It's just an idea. Richard From drow@false.org Wed Jul 2 21:29:20 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 02 Jul 2008 21:29:26 +0100 (BST) Received: from NaN.false.org ([208.75.86.248]:52710 "EHLO nan.false.org") by ftp.linux-mips.org with ESMTP id S23872641AbYGBU3U (ORCPT ); Wed, 2 Jul 2008 21:29:20 +0100 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 634D0982C3; Wed, 2 Jul 2008 20:29:15 +0000 (GMT) Received: from caradoc.them.org (22.svnf5.xdsl.nauticom.net [209.195.183.55]) by nan.false.org (Postfix) with ESMTP id 41F6098243; Wed, 2 Jul 2008 20:29:15 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.69) (envelope-from ) id 1KE8x0-0006gN-5n; Wed, 02 Jul 2008 16:29:14 -0400 Date: Wed, 2 Jul 2008 16:29:14 -0400 From: Daniel Jacobowitz To: binutils@sourceware.org, gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Subject: Re: RFC: Adding non-PIC executable support to MIPS Message-ID: <20080702202914.GA17986@caradoc.them.org> Mail-Followup-To: binutils@sourceware.org, gcc@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com References: <87y74pxwyl.fsf@firetop.home> <20080701202236.GA1534@caradoc.them.org> <87zlp149ot.fsf@firetop.home> <20080702120829.GA12595@caradoc.them.org> <87abh0m56d.fsf@firetop.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87abh0m56d.fsf@firetop.home> User-Agent: Mutt/1.5.17 (2008-05-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19701 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@debian.org Precedence: bulk X-list: linux-mips Content-Length: 826 Lines: 20 On Wed, Jul 02, 2008 at 08:55:54PM +0100, Richard Sandiford wrote: > The size of the header and first 0x10000 stubs would be the same. > I think it would also preserve the resolver interface while removing > the need for the extra-large .plts. The only incompatibility I can > see would be that objdump on older executables would not get the > foo@plt symbols right for large indices. > > OTOH, perhaps you could argue that the extra complication of the > two PLT entries doesn't count for much given that the code is > already written. It's just an idea. Your version looks fine to me, it's ABI-preserving, the PLT entries still work for MIPS I and still have the same runtime cost when not resolving. I like it - thanks! I'm not worried about making people upgrade objdump, either. -- Daniel Jacobowitz CodeSourcery From tsbogend@alpha.franken.de Thu Jul 3 00:21:27 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 00:21:35 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:15295 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S23879013AbYGBXV1 (ORCPT ); Thu, 3 Jul 2008 00:21:27 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KEBdd-0002hA-01 for linux-mips@linux-mips.org; Thu, 03 Jul 2008 01:21:25 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 8570DFAB49; Thu, 3 Jul 2008 01:21:18 +0200 (CEST) Date: Thu, 3 Jul 2008 01:21:18 +0200 To: linux-mips@linux-mips.org Subject: Re: SGI O2 sound driver v4 Message-ID: <20080702232118.GB18226@alpha.franken.de> References: <20080628000916.GA22049@alpha.franken.de> <20080628141336.GA17727@alpha.franken.de> <20080628224553.GA2064@alpha.franken.de> <20080629223537.GA697@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20080629223537.GA697@alpha.franken.de> User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19703 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 55407 Lines: 1884 On Mon, Jun 30, 2008 at 12:35:37AM +0200, Thomas Bogendoerfer wrote: > > [...] > changes in v5: - fixed contols - got rid of wrong spinlocks - setup two pcm devices - moved button support to a new input driver - restructered interrupt setup TODO: - test capture - check inputs (mic/line/cd) - add dma error interrupt handling I'm planning to submit the different parts to the maintainers after I've checked that capturing is working. Thomas. arch/mips/sgi-ip32/ip32-platform.c | 36 ++ drivers/input/misc/Kconfig | 10 + drivers/input/misc/Makefile | 1 + drivers/input/misc/sgio2_btns.c | 154 ++++++ include/sound/ad1843.h | 46 ++ sound/mips/Kconfig | 6 + sound/mips/Makefile | 2 + sound/mips/ad1843.c | 530 +++++++++++++++++++ sound/mips/sgio2audio.c | 986 ++++++++++++++++++++++++++++++++++++ 9 files changed, 1771 insertions(+), 0 deletions(-) diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c index 89a71f4..2ee401b 100644 --- a/arch/mips/sgi-ip32/ip32-platform.c +++ b/arch/mips/sgi-ip32/ip32-platform.c @@ -65,6 +65,42 @@ static __init int meth_devinit(void) device_initcall(meth_devinit); +static __init int sgio2audio_devinit(void) +{ + struct platform_device *pd; + int ret; + + pd = platform_device_alloc("sgio2audio", -1); + if (!pd) + return -ENOMEM; + + ret = platform_device_add(pd); + if (ret) + platform_device_put(pd); + + return ret; +} + +device_initcall(sgio2audio_devinit); + +static __init int sgio2btns_devinit(void) +{ + struct platform_device *pd; + int ret; + + pd = platform_device_alloc("sgio2btns", -1); + if (!pd) + return -ENOMEM; + + ret = platform_device_add(pd); + if (ret) + platform_device_put(pd); + + return ret; +} + +device_initcall(sgio2btns_devinit); + MODULE_AUTHOR("Ralf Baechle "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("8250 UART probe driver for SGI IP32 aka O2"); diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 432699d..e33d7cb 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -189,6 +189,16 @@ config INPUT_UINPUT To compile this driver as a module, choose M here: the module will be called uinput. +config INPUT_SGIO2_BTNS + tristate "SGI O2 volume button interface" + depends on SGI_IP32 + select INPUT_POLLDEV + help + Say Y here if you want to support SGI O2 volume button interface. + + To compile this driver as a module, choose M here: the + module will be called sgio_btns. + config HP_SDC_RTC tristate "HP SDC Real Time Clock" depends on GSC || HP300 diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index ebd39f2..0e274f1 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -19,3 +19,4 @@ obj-$(CONFIG_INPUT_YEALINK) += yealink.o obj-$(CONFIG_HP_SDC_RTC) += hp_sdc_rtc.o obj-$(CONFIG_INPUT_UINPUT) += uinput.o obj-$(CONFIG_INPUT_APANEL) += apanel.o +obj-$(CONFIG_INPUT_SGIO2_BTNS) += sgio2_btns.o diff --git a/drivers/input/misc/sgio2_btns.c b/drivers/input/misc/sgio2_btns.c new file mode 100644 index 0000000..83c9501 --- /dev/null +++ b/drivers/input/misc/sgio2_btns.c @@ -0,0 +1,154 @@ +/* + * Cobalt button interface driver. + * + * Copyright (C) 2007-2008 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +#include + +#define BUTTONS_POLL_INTERVAL 30 /* msec */ +#define BUTTONS_COUNT_THRESHOLD 3 +#define BUTTONS_STATUS_MASK 0xfe000000 + +static const unsigned short sgio2_map[] = { + KEY_VOLUMEUP, + KEY_VOLUMEDOWN +}; + +struct buttons_dev { + struct input_polled_dev *poll_dev; + unsigned short keymap[ARRAY_SIZE(sgio2_map)]; + int count[ARRAY_SIZE(sgio2_map)]; + void __iomem *reg; +}; + +static void handle_buttons(struct input_polled_dev *dev) +{ + struct buttons_dev *bdev = dev->private; + struct input_dev *input = dev->input; + u64 status; + int i; + + status = (readq(&mace->perif.audio.control) >> 24) & 3; + + for (i = 0; i < ARRAY_SIZE(bdev->keymap); i++) { + if (status & (1U << i)) { + if (++bdev->count[i] == BUTTONS_COUNT_THRESHOLD) { + input_event(input, EV_MSC, MSC_SCAN, i); + input_report_key(input, bdev->keymap[i], 1); + input_sync(input); + } + } else { + if (bdev->count[i] >= BUTTONS_COUNT_THRESHOLD) { + input_event(input, EV_MSC, MSC_SCAN, i); + input_report_key(input, bdev->keymap[i], 0); + input_sync(input); + } + bdev->count[i] = 0; + } + } +} + +static int __devinit sgio2_buttons_probe(struct platform_device *pdev) +{ + struct buttons_dev *bdev; + struct input_polled_dev *poll_dev; + struct input_dev *input; + int error, i; + + bdev = kzalloc(sizeof(struct buttons_dev), GFP_KERNEL); + poll_dev = input_allocate_polled_device(); + if (!bdev || !poll_dev) { + error = -ENOMEM; + goto err_free_mem; + } + + memcpy(bdev->keymap, sgio2_map, sizeof(bdev->keymap)); + + poll_dev->private = bdev; + poll_dev->poll = handle_buttons; + poll_dev->poll_interval = BUTTONS_POLL_INTERVAL; + + input = poll_dev->input; + input->name = "SGI O2 buttons"; + input->phys = "sgio2/input0"; + input->id.bustype = BUS_HOST; + input->dev.parent = &pdev->dev; + + input->keycode = bdev->keymap; + input->keycodemax = ARRAY_SIZE(bdev->keymap); + input->keycodesize = sizeof(unsigned short); + + input_set_capability(input, EV_MSC, MSC_SCAN); + __set_bit(EV_KEY, input->evbit); + for (i = 0; i < ARRAY_SIZE(sgio2_map); i++) + __set_bit(bdev->keymap[i], input->keybit); + __clear_bit(KEY_RESERVED, input->keybit); + + bdev->poll_dev = poll_dev; + dev_set_drvdata(&pdev->dev, bdev); + + error = input_register_polled_device(poll_dev); + if (!error) + return 0; + + err_free_mem: + input_free_polled_device(poll_dev); + kfree(bdev); + dev_set_drvdata(&pdev->dev, NULL); + return error; +} + +static int __devexit sgio2_buttons_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct buttons_dev *bdev = dev_get_drvdata(dev); + + input_unregister_polled_device(bdev->poll_dev); + input_free_polled_device(bdev->poll_dev); + kfree(bdev); + dev_set_drvdata(dev, NULL); + + return 0; +} + +static struct platform_driver sgio2_buttons_driver = { + .probe = sgio2_buttons_probe, + .remove = __devexit_p(sgio2_buttons_remove), + .driver = { + .name = "sgio2btns", + .owner = THIS_MODULE, + }, +}; + +static int __init sgio2_buttons_init(void) +{ + return platform_driver_register(&sgio2_buttons_driver); +} + +static void __exit sgio2_buttons_exit(void) +{ + platform_driver_unregister(&sgio2_buttons_driver); +} + +module_init(sgio2_buttons_init); +module_exit(sgio2_buttons_exit); diff --git a/include/sound/ad1843.h b/include/sound/ad1843.h new file mode 100644 index 0000000..3892be9 --- /dev/null +++ b/include/sound/ad1843.h @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright 2003 Vivien Chappelier + * Copyright 2008 Thomas Bogendoerfer + */ + +#ifndef __SOUND_AD1843_H +#define __SOUND_AD1843_H + +struct snd_ad1843 { + void *chip; + int (*read)(void *chip, int reg); + int (*write)(void *chip, int reg, int val); +}; + +#define AD1843_GAIN_RECLEV 0 +#define AD1843_GAIN_LINE 1 +#define AD1843_GAIN_CD 2 +#define AD1843_GAIN_MIC 3 +#define AD1843_GAIN_PCM_0 4 +#define AD1843_GAIN_PCM_1 5 +#define AD1843_GAIN_SIZE (AD1843_GAIN_PCM_1+1) + +int ad1843_get_gain_max(struct snd_ad1843 *ad1843, int id); +int ad1843_get_gain(struct snd_ad1843 *ad1843, int id); +int ad1843_set_gain(struct snd_ad1843 *ad1843, int id, int newval); +int ad1843_get_recsrc(struct snd_ad1843 *ad1843); +int ad1843_set_recsrc(struct snd_ad1843 *ad1843, int newsrc); +void ad1843_setup_dac(struct snd_ad1843 *ad1843, + unsigned int id, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels); +void ad1843_shutdown_dac(struct snd_ad1843 *ad1843, + unsigned int id); +void ad1843_setup_adc(struct snd_ad1843 *ad1843, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels); +void ad1843_shutdown_adc(struct snd_ad1843 *ad1843); +int ad1843_init(struct snd_ad1843 *ad1843); + +#endif /* __SOUND_AD1843_H */ diff --git a/sound/mips/Kconfig b/sound/mips/Kconfig index 531f8ba..a3e202e 100644 --- a/sound/mips/Kconfig +++ b/sound/mips/Kconfig @@ -11,5 +11,11 @@ config SND_AU1X00 help ALSA Sound driver for the Au1x00's AC97 port. +config SND_SGI_O2 + tristate "SGI O2 Audio" + depends on SND && SGI_IP32 + help + Sound support for the SGI O2 Workstation. + endmenu diff --git a/sound/mips/Makefile b/sound/mips/Makefile index 47afed9..55624d8 100644 --- a/sound/mips/Makefile +++ b/sound/mips/Makefile @@ -2,7 +2,9 @@ # Makefile for ALSA # +snd-sgi-o2-objs := sgio2audio.o ad1843.o snd-au1x00-objs := au1x00.o # Toplevel Module Dependency obj-$(CONFIG_SND_AU1X00) += snd-au1x00.o +obj-$(CONFIG_SND_SGI_O2) += snd-sgi-o2.o diff --git a/sound/mips/ad1843.c b/sound/mips/ad1843.c new file mode 100644 index 0000000..f338390 --- /dev/null +++ b/sound/mips/ad1843.c @@ -0,0 +1,530 @@ +/* + * AD1843 low level driver + * + * Copyright 2003 Vivien Chappelier + * Copyright 2008 Thomas Bogendoerfer + * + * inspired from vwsnd.c (SGI VW audio driver) + * Copyright 1999 Silicon Graphics, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +/* + * AD1843 bitfield definitions. All are named as in the AD1843 data + * sheet, with ad1843_ prepended and individual bit numbers removed. + * + * E.g., bits LSS0 through LSS2 become ad1843_LSS. + * + * Only the bitfields we need are defined. + */ + +struct ad1843_bitfield { + char reg; + char lo_bit; + char nbits; +}; + +static const struct ad1843_bitfield + ad1843_PDNO = { 0, 14, 1 }, /* Converter Power-Down Flag */ + ad1843_INIT = { 0, 15, 1 }, /* Clock Initialization Flag */ + ad1843_RIG = { 2, 0, 4 }, /* Right ADC Input Gain */ + ad1843_RMGE = { 2, 4, 1 }, /* Right ADC Mic Gain Enable */ + ad1843_RSS = { 2, 5, 3 }, /* Right ADC Source Select */ + ad1843_LIG = { 2, 8, 4 }, /* Left ADC Input Gain */ + ad1843_LMGE = { 2, 12, 1 }, /* Left ADC Mic Gain Enable */ + ad1843_LSS = { 2, 13, 3 }, /* Left ADC Source Select */ + ad1843_RD2M = { 3, 0, 5 }, /* Right DAC 2 Mix Gain/Atten */ + ad1843_RD2MM = { 3, 7, 1 }, /* Right DAC 2 Mix Mute */ + ad1843_LD2M = { 3, 8, 5 }, /* Left DAC 2 Mix Gain/Atten */ + ad1843_LD2MM = { 3, 15, 1 }, /* Left DAC 2 Mix Mute */ + ad1843_RX1M = { 4, 0, 5 }, /* Right Aux 1 Mix Gain/Atten */ + ad1843_RX1MM = { 4, 7, 1 }, /* Right Aux 1 Mix Mute */ + ad1843_LX1M = { 4, 8, 5 }, /* Left Aux 1 Mix Gain/Atten */ + ad1843_LX1MM = { 4, 15, 1 }, /* Left Aux 1 Mix Mute */ + ad1843_RX2M = { 5, 0, 5 }, /* Right Aux 2 Mix Gain/Atten */ + ad1843_RX2MM = { 5, 7, 1 }, /* Right Aux 2 Mix Mute */ + ad1843_LX2M = { 5, 8, 5 }, /* Left Aux 2 Mix Gain/Atten */ + ad1843_LX2MM = { 5, 15, 1 }, /* Left Aux 2 Mix Mute */ + ad1843_RMCM = { 7, 0, 5 }, /* Right Mic Mix Gain/Atten */ + ad1843_RMCMM = { 7, 7, 1 }, /* Right Mic Mix Mute */ + ad1843_LMCM = { 7, 8, 5 }, /* Left Mic Mix Gain/Atten */ + ad1843_LMCMM = { 7, 15, 1 }, /* Left Mic Mix Mute */ + ad1843_HPOS = { 8, 4, 1 }, /* Headphone Output Voltage Swing */ + ad1843_HPOM = { 8, 5, 1 }, /* Headphone Output Mute */ + ad1843_MPOM = { 8, 6, 1 }, /* Mono Output Mute */ + ad1843_RDA1G = { 9, 0, 6 }, /* Right DAC1 Analog/Digital Gain */ + ad1843_RDA1GM = { 9, 7, 1 }, /* Right DAC1 Analog Mute */ + ad1843_LDA1G = { 9, 8, 6 }, /* Left DAC1 Analog/Digital Gain */ + ad1843_LDA1GM = { 9, 15, 1 }, /* Left DAC1 Analog Mute */ + ad1843_RDA2G = { 10, 0, 6 }, /* Right DAC2 Analog/Digital Gain */ + ad1843_RDA2GM = { 10, 7, 1 }, /* Right DAC2 Analog Mute */ + ad1843_LDA2G = { 10, 8, 6 }, /* Left DAC2 Analog/Digital Gain */ + ad1843_LDA2GM = { 10, 15, 1 }, /* Left DAC2 Analog Mute */ + ad1843_RDA1AM = { 11, 7, 1 }, /* Right DAC1 Digital Mute */ + ad1843_LDA1AM = { 11, 15, 1 }, /* Left DAC1 Digital Mute */ + ad1843_RDA2AM = { 12, 7, 1 }, /* Right DAC2 Digital Mute */ + ad1843_LDA2AM = { 12, 15, 1 }, /* Left DAC2 Digital Mute */ + ad1843_ADLC = { 15, 0, 2 }, /* ADC Left Sample Rate Source */ + ad1843_ADRC = { 15, 2, 2 }, /* ADC Right Sample Rate Source */ + ad1843_DA1C = { 15, 8, 2 }, /* DAC1 Sample Rate Source */ + ad1843_DA2C = { 15, 10, 2 }, /* DAC2 Sample Rate Source */ + ad1843_C1C = { 17, 0, 16 }, /* Clock 1 Sample Rate Select */ + ad1843_C2C = { 20, 0, 16 }, /* Clock 2 Sample Rate Select */ + ad1843_C3C = { 23, 0, 16 }, /* Clock 3 Sample Rate Select */ + ad1843_DAADL = { 25, 4, 2 }, /* Digital ADC Left Source Select */ + ad1843_DAADR = { 25, 6, 2 }, /* Digital ADC Right Source Select */ + ad1843_DAMIX = { 25, 14, 1 }, /* DAC Digital Mix Enable */ + ad1843_DRSFLT = { 25, 15, 1 }, /* Digital Reampler Filter Mode */ + ad1843_ADLF = { 26, 0, 2 }, /* ADC Left Channel Data Format */ + ad1843_ADRF = { 26, 2, 2 }, /* ADC Right Channel Data Format */ + ad1843_ADTLK = { 26, 4, 1 }, /* ADC Transmit Lock Mode Select */ + ad1843_SCF = { 26, 7, 1 }, /* SCLK Frequency Select */ + ad1843_DA1F = { 26, 8, 2 }, /* DAC1 Data Format Select */ + ad1843_DA2F = { 26, 10, 2 }, /* DAC2 Data Format Select */ + ad1843_DA1SM = { 26, 14, 1 }, /* DAC1 Stereo/Mono Mode Select */ + ad1843_DA2SM = { 26, 15, 1 }, /* DAC2 Stereo/Mono Mode Select */ + ad1843_ADLEN = { 27, 0, 1 }, /* ADC Left Channel Enable */ + ad1843_ADREN = { 27, 1, 1 }, /* ADC Right Channel Enable */ + ad1843_AAMEN = { 27, 4, 1 }, /* Analog to Analog Mix Enable */ + ad1843_ANAEN = { 27, 7, 1 }, /* Analog Channel Enable */ + ad1843_DA1EN = { 27, 8, 1 }, /* DAC1 Enable */ + ad1843_DA2EN = { 27, 9, 1 }, /* DAC2 Enable */ + ad1843_DDMEN = { 27, 12, 1 }, /* DAC2 to DAC1 Mix Enable */ + ad1843_C1EN = { 28, 11, 1 }, /* Clock Generator 1 Enable */ + ad1843_C2EN = { 28, 12, 1 }, /* Clock Generator 2 Enable */ + ad1843_C3EN = { 28, 13, 1 }, /* Clock Generator 3 Enable */ + ad1843_PDNI = { 28, 15, 1 }; /* Converter Power Down */ + +/* + * The various registers of the AD1843 use three different formats for + * specifying gain. The ad1843_gain structure parameterizes the + * formats. + */ + +struct ad1843_gain { + int negative; /* nonzero if gain is negative. */ + const struct ad1843_bitfield *lfield; + const struct ad1843_bitfield *rfield; +}; + +const struct ad1843_gain ad1843_gain_RECLEV = { + 0, &ad1843_LIG, &ad1843_RIG +}; +const struct ad1843_gain ad1843_gain_LINE = { + 1, &ad1843_LX1M, &ad1843_RX1M +}; +const struct ad1843_gain ad1843_gain_CD = { + 1, &ad1843_LX2M, &ad1843_RX2M +}; +const struct ad1843_gain ad1843_gain_MIC = { + 1, &ad1843_LMCM, &ad1843_RMCM +}; +const struct ad1843_gain ad1843_gain_PCM_0 = { + 1, &ad1843_LDA1G, &ad1843_RDA1G +}; +const struct ad1843_gain ad1843_gain_PCM_1 = { + 1, &ad1843_LD2M, &ad1843_RD2M +}; + +const struct ad1843_gain *ad1843_gain[AD1843_GAIN_SIZE] = +{ + &ad1843_gain_RECLEV, + &ad1843_gain_LINE, + &ad1843_gain_CD, + &ad1843_gain_MIC, + &ad1843_gain_PCM_0, + &ad1843_gain_PCM_1, +}; + +/* read the current value of an AD1843 bitfield. */ + +static int ad1843_read_bits(struct snd_ad1843 *ad1843, + const struct ad1843_bitfield *field) +{ + int w; + + w = ad1843->read(ad1843->chip, field->reg); + return w >> field->lo_bit & ((1 << field->nbits) - 1); +} + +/* + * write a new value to an AD1843 bitfield and return the old value. + */ + +static int ad1843_write_bits(struct snd_ad1843 *ad1843, + const struct ad1843_bitfield *field, + int newval) +{ + int w, mask, oldval, newbits; + + w = ad1843->read(ad1843->chip, field->reg); + mask = ((1 << field->nbits) - 1) << field->lo_bit; + oldval = (w & mask) >> field->lo_bit; + newbits = (newval << field->lo_bit) & mask; + w = (w & ~mask) | newbits; + ad1843->write(ad1843->chip, field->reg, w); + + return oldval; +} + +/* + * ad1843_read_multi reads multiple bitfields from the same AD1843 + * register. It uses a single read cycle to do it. (Reading the + * ad1843 requires 256 bit times at 12.288 MHz, or nearly 20 + * microseconds.) + * + * Called like this. + * + * ad1843_read_multi(ad1843, nfields, + * &ad1843_FIELD1, &val1, + * &ad1843_FIELD2, &val2, ...); + */ + +static void ad1843_read_multi(struct snd_ad1843 *ad1843, int argcount, ...) +{ + va_list ap; + const struct ad1843_bitfield *fp; + int w = 0, mask, *value, reg = -1; + + va_start(ap, argcount); + while (--argcount >= 0) { + fp = va_arg(ap, const struct ad1843_bitfield *); + value = va_arg(ap, int *); + if (reg == -1) { + reg = fp->reg; + w = ad1843->read(ad1843->chip, reg); + } + + mask = (1 << fp->nbits) - 1; + *value = w >> fp->lo_bit & mask; + } + va_end(ap); +} + +/* + * ad1843_write_multi stores multiple bitfields into the same AD1843 + * register. It uses one read and one write cycle to do it. + * + * Called like this. + * + * ad1843_write_multi(ad1843, nfields, + * &ad1843_FIELD1, val1, + * &ad1843_FIELF2, val2, ...); + */ + +static void ad1843_write_multi(struct snd_ad1843 *ad1843, int argcount, ...) +{ + va_list ap; + int reg; + const struct ad1843_bitfield *fp; + int value; + int w, m, mask, bits; + + mask = 0; + bits = 0; + reg = -1; + + va_start(ap, argcount); + while (--argcount >= 0) { + fp = va_arg(ap, const struct ad1843_bitfield *); + value = va_arg(ap, int); + if (reg == -1) + reg = fp->reg; + else + BUG_ON(reg != fp->reg); + m = ((1 << fp->nbits) - 1) << fp->lo_bit; + mask |= m; + bits |= (value << fp->lo_bit) & m; + } + va_end(ap); + + if (~mask & 0xFFFF) + w = ad1843->read(ad1843->chip, reg); + else + w = 0; + w = (w & ~mask) | bits; + ad1843->write(ad1843->chip, reg, w); +} + +int ad1843_get_gain_max(struct snd_ad1843 *ad1843, int id) +{ + const struct ad1843_gain *gp = ad1843_gain[id]; + + return (1 << gp->lfield->nbits) - 1; +} + +/* + * ad1843_get_gain reads the specified register and extracts the gain value + * using the supplied gain type. + */ + +int ad1843_get_gain(struct snd_ad1843 *ad1843, int id) +{ + int lg, rg; + const struct ad1843_gain *gp = ad1843_gain[id]; + unsigned short mask = (1 << gp->lfield->nbits) - 1; + + ad1843_read_multi(ad1843, 2, gp->lfield, &lg, gp->rfield, &rg); + if (gp->negative) { + lg = mask - lg; + rg = mask - rg; + } + return lg << 0 | rg << 8; +} + +/* + * Set an audio channel's gain. + * + * Returns the new gain, which may be lower than the old gain. + */ + +int ad1843_set_gain(struct snd_ad1843 *ad1843, int id, int newval) +{ + const struct ad1843_gain *gp = ad1843_gain[id]; + unsigned short mask = (1 << gp->lfield->nbits) - 1; + + int lg = (newval >> 0) & mask; + int rg = (newval >> 8) & mask; + + if (gp->negative) { + lg = mask - lg; + rg = mask - rg; + } + ad1843_write_multi(ad1843, 2, gp->lfield, lg, gp->rfield, rg); + return ad1843_get_gain(ad1843, id); +} + +/* Returns the current recording source */ + +int ad1843_get_recsrc(struct snd_ad1843 *ad1843) +{ + int val = ad1843_read_bits(ad1843, &ad1843_LSS); + + if (val < 1 || val > 3) { + val = 1; + ad1843_write_multi(ad1843, 2, + &ad1843_LSS, val, &ad1843_RSS, val); + } + return val - 1; +} + +/* + * Set recording source. + * + * Returns newsrc on success, -errno on failure. + */ + +int ad1843_set_recsrc(struct snd_ad1843 *ad1843, int newsrc) +{ + if (newsrc < 1 || newsrc > 3) + return -EINVAL; + + newsrc--; + ad1843_write_multi(ad1843, 2, &ad1843_LSS, newsrc, &ad1843_RSS, newsrc); + return newsrc; +} + +/* Setup ad1843 for D/A conversion. */ + +void ad1843_setup_dac(struct snd_ad1843 *ad1843, + unsigned int id, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels) +{ + int ad_fmt = 0, ad_mode = 0; + + switch (fmt) { + case SNDRV_PCM_FORMAT_S8: + ad_fmt = 0; + break; + case SNDRV_PCM_FORMAT_U8: + ad_fmt = 0; + break; + case SNDRV_PCM_FORMAT_S16_LE: + ad_fmt = 1; + break; + case SNDRV_PCM_FORMAT_MU_LAW: + ad_fmt = 2; + break; + case SNDRV_PCM_FORMAT_A_LAW: + ad_fmt = 3; + break; + default: + break; + } + + switch (channels) { + case 2: + ad_mode = 0; + break; + case 1: + ad_mode = 1; + break; + default: + break; + } + + if (id) { + ad1843_write_bits(ad1843, &ad1843_C2C, framerate); + ad1843_write_multi(ad1843, 2, + &ad1843_DA2SM, ad_mode, + &ad1843_DA2F, ad_fmt); + } else { + ad1843_write_bits(ad1843, &ad1843_C1C, framerate); + ad1843_write_multi(ad1843, 2, + &ad1843_DA1SM, ad_mode, + &ad1843_DA1F, ad_fmt); + } +} + +void ad1843_shutdown_dac(struct snd_ad1843 *ad1843, unsigned int id) +{ + if (id) + ad1843_write_bits(ad1843, &ad1843_DA2F, 1); + else + ad1843_write_bits(ad1843, &ad1843_DA1F, 1); +} + +void ad1843_setup_adc(struct snd_ad1843 *ad1843, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels) +{ + int da_fmt = 0; + + switch (fmt) { + case SNDRV_PCM_FORMAT_S8: da_fmt = 0; break; + case SNDRV_PCM_FORMAT_U8: da_fmt = 0; break; + case SNDRV_PCM_FORMAT_S16_LE: da_fmt = 1; break; + case SNDRV_PCM_FORMAT_MU_LAW: da_fmt = 2; break; + case SNDRV_PCM_FORMAT_A_LAW: da_fmt = 3; break; + default: break; + } + + ad1843_write_bits(ad1843, &ad1843_C3C, framerate); + ad1843_write_multi(ad1843, 2, + &ad1843_ADLF, da_fmt, &ad1843_ADRF, da_fmt); +} + +void ad1843_shutdown_adc(struct snd_ad1843 *ad1843) +{ + /* nothing to do */ +} + +/* + * Fully initialize the ad1843. As described in the AD1843 data + * sheet, section "START-UP SEQUENCE". The numbered comments are + * subsection headings from the data sheet. See the data sheet, pages + * 52-54, for more info. + * + * return 0 on success, -errno on failure. */ + +int ad1843_init(struct snd_ad1843 *ad1843) +{ + unsigned long later; + + if (ad1843_read_bits(ad1843, &ad1843_INIT) != 0) { + printk(KERN_ERR "ad1843: AD1843 won't initialize\n"); + return -EIO; + } + + ad1843_write_bits(ad1843, &ad1843_SCF, 1); + + /* 4. Put the conversion resources into standby. */ + ad1843_write_bits(ad1843, &ad1843_PDNI, 0); + later = jiffies + HZ / 2; /* roughly half a second */ + + while (ad1843_read_bits(ad1843, &ad1843_PDNO)) { + if (time_after(jiffies, later)) { + printk(KERN_ERR + "ad1843: AD1843 won't power up\n"); + return -EIO; + } + schedule(); + } + + /* 5. Power up the clock generators and enable clock output pins. */ + ad1843_write_multi(ad1843, 3, + &ad1843_C1EN, 1, + &ad1843_C2EN, 1, + &ad1843_C3EN, 1); + + /* 6. Configure conversion resources while they are in standby. */ + + /* DAC1/2 use clock 1/2 as source, ADC uses clock 3. Always. */ + ad1843_write_multi(ad1843, 4, + &ad1843_DA1C, 1, + &ad1843_DA2C, 2, + &ad1843_ADLC, 3, + &ad1843_ADRC, 3); + + /* 7. Enable conversion resources. */ + ad1843_write_bits(ad1843, &ad1843_ADTLK, 1); + ad1843_write_multi(ad1843, 7, + &ad1843_ANAEN, 1, + &ad1843_AAMEN, 1, + &ad1843_DA1EN, 1, + &ad1843_DA2EN, 1, + &ad1843_DDMEN, 1, + &ad1843_ADLEN, 1, + &ad1843_ADREN, 1); + + /* 8. Configure conversion resources while they are enabled. */ + + /* set gain to 0 for all channels */ + ad1843_set_gain(ad1843, AD1843_GAIN_RECLEV, 0); + ad1843_set_gain(ad1843, AD1843_GAIN_LINE, 0); + ad1843_set_gain(ad1843, AD1843_GAIN_CD, 0); + ad1843_set_gain(ad1843, AD1843_GAIN_MIC, 0); + ad1843_set_gain(ad1843, AD1843_GAIN_PCM_0, 0); + ad1843_set_gain(ad1843, AD1843_GAIN_PCM_1, 0); + + /* Unmute all channels. */ + /* DAC1 */ + ad1843_write_multi(ad1843, 2, &ad1843_LDA1GM, 0, &ad1843_RDA1GM, 0); + ad1843_write_multi(ad1843, 2, &ad1843_LDA1AM, 0, &ad1843_RDA1AM, 0); + /* Line In */ + ad1843_write_multi(ad1843, 2, &ad1843_LX1MM, 0, &ad1843_RX1MM, 0); + /* CD */ + ad1843_write_multi(ad1843, 2, &ad1843_LX2MM, 0, &ad1843_RX2MM, 0); + /* Mic */ + ad1843_write_multi(ad1843, 2, &ad1843_LMCMM, 0, &ad1843_RMCMM, 0); + /* DAC2 */ + ad1843_write_multi(ad1843, 2, &ad1843_LD2MM, 0, &ad1843_RD2MM, 0); + + /* Set default recording source to Line In and set + * mic gain to +20 dB. + */ + ad1843_set_recsrc(ad1843, 2); + ad1843_write_multi(ad1843, 2, &ad1843_LMGE, 1, &ad1843_RMGE, 1); + + /* Set Speaker Out level to +/- 4V and unmute it. */ + ad1843_write_multi(ad1843, 3, + &ad1843_HPOS, 1, + &ad1843_HPOM, 0, + &ad1843_MPOM, 0); + + return 0; +} diff --git a/sound/mips/sgio2audio.c b/sound/mips/sgio2audio.c new file mode 100644 index 0000000..6c1528e --- /dev/null +++ b/sound/mips/sgio2audio.c @@ -0,0 +1,986 @@ +/* + * Sound driver for Silicon Graphics O2 Workstations A/V board audio. + * + * Copyright 2003 Vivien Chappelier + * Copyright 2008 Thomas Bogendoerfer + * Mxier part taken from mace_audio.c: + * Copyright 2007 Thorben Jändling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#define SNDRV_GET_ID +#include +#include + + +MODULE_AUTHOR("Vivien Chappelier "); +MODULE_DESCRIPTION("SGI O2 Audio"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("{{Silicon Graphics, O2 Audio}}"); + +static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ +static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ + +module_param(index, int, 0444); +MODULE_PARM_DESC(index, "Index value for SGI O2 soundcard."); +module_param(id, charp, 0444); +MODULE_PARM_DESC(id, "ID string for SGI O2 soundcard."); + + +#define SGIO2AUDIO_MAX_VOLUME 31 + +#define AUDIO_CONTROL_RESET BIT(0) /* 1: reset audio interface */ +#define AUDIO_CONTROL_CODEC_PRESENT BIT(1) /* 1: codec detected */ + +#define CODEC_CONTROL_WORD_SHIFT 0 +#define CODEC_CONTROL_READ BIT(16) +#define CODEC_CONTROL_ADDRESS_SHIFT 17 + +#define CHANNEL_CONTROL_RESET BIT(10) /* 1: reset channel */ +#define CHANNEL_DMA_ENABLE BIT(9) /* 1: enable DMA transfer */ +#define CHANNEL_INT_THRESHOLD_DISABLED (0 << 5) /* interrupt disabled */ +#define CHANNEL_INT_THRESHOLD_25 (1 << 5) /* int on buffer >25% full */ +#define CHANNEL_INT_THRESHOLD_50 (2 << 5) /* int on buffer >50% full */ +#define CHANNEL_INT_THRESHOLD_75 (3 << 5) /* int on buffer >75% full */ +#define CHANNEL_INT_THRESHOLD_EMPTY (4 << 5) /* int on buffer empty */ +#define CHANNEL_INT_THRESHOLD_NOT_EMPTY (5 << 5) /* int on buffer !empty */ +#define CHANNEL_INT_THRESHOLD_FULL (6 << 5) /* int on buffer empty */ +#define CHANNEL_INT_THRESHOLD_NOT_FULL (7 << 5) /* int on buffer !empty */ + +#define CHANNEL_RING_SHIFT 12 +#define CHANNEL_RING_SIZE (1 << CHANNEL_RING_SHIFT) +#define CHANNEL_RING_MASK (CHANNEL_RING_SIZE - 1) + +#define CHANNEL_LEFT_SHIFT 40 +#define CHANNEL_RIGHT_SHIFT 8 + +struct snd_sgio2audio_chan { + int idx; + struct snd_pcm_substream *substream; + int pos; + snd_pcm_uframes_t size; + spinlock_t lock; +}; + +/* definition of the chip-specific record */ +struct snd_sgio2audio { + struct snd_card *card; + + /* codec */ + struct snd_ad1843 ad1843; + spinlock_t ad1843_lock; + + /* channels */ + struct snd_sgio2audio_chan channel[3]; + + /* properties */ + int volume; + + /* resources */ + void *ring_base; + dma_addr_t ring_base_dma; +}; + +/* AD1843 access */ + +/* + * read_ad1843_reg returns the current contents of a 16 bit AD1843 register. + * + * Returns unsigned register value on success, -errno on failure. + */ +static int read_ad1843_reg(void *priv, int reg) +{ + struct snd_sgio2audio *chip = priv; + int val; + unsigned long flags; + + spin_lock_irqsave(&chip->ad1843_lock, flags); + + writeq((reg << CODEC_CONTROL_ADDRESS_SHIFT) | + CODEC_CONTROL_READ, &mace->perif.audio.codec_control); + wmb(); + val = readq(&mace->perif.audio.codec_control); /* flush bus */ + udelay(200); + + val = readq(&mace->perif.audio.codec_read); + + spin_unlock_irqrestore(&chip->ad1843_lock, flags); + return val; +} + +/* + * write_ad1843_reg writes the specified value to a 16 bit AD1843 register. + */ +static int write_ad1843_reg(void *priv, int reg, int word) +{ + struct snd_sgio2audio *chip = priv; + int val; + unsigned long flags; + + spin_lock_irqsave(&chip->ad1843_lock, flags); + + writeq((reg << CODEC_CONTROL_ADDRESS_SHIFT) | + (word << CODEC_CONTROL_WORD_SHIFT), + &mace->perif.audio.codec_control); + wmb(); + val = readq(&mace->perif.audio.codec_control); /* flush bus */ + udelay(200); + + spin_unlock_irqrestore(&chip->ad1843_lock, flags); + return 0; +} + +static int sgio2audio_gain_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct snd_sgio2audio *chip = snd_kcontrol_chip(kcontrol); + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 2; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = ad1843_get_gain_max(&chip->ad1843, + (int)kcontrol->private_value); + return 0; +} + +static int sgio2audio_gain_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_sgio2audio *chip = snd_kcontrol_chip(kcontrol); + int vol; + + vol = ad1843_get_gain(&chip->ad1843, (int)kcontrol->private_value); + + ucontrol->value.integer.value[0] = (vol >> 8) & 0xFF; + ucontrol->value.integer.value[1] = vol & 0xFF; + + return 0; +} + +static int sgio2audio_gain_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_sgio2audio *chip = snd_kcontrol_chip(kcontrol); + int newvol, oldvol; + + oldvol = ad1843_get_gain(&chip->ad1843, kcontrol->private_value); + newvol = (ucontrol->value.integer.value[0] << 8) | + ucontrol->value.integer.value[1]; + + newvol = ad1843_set_gain(&chip->ad1843, kcontrol->private_value, + newvol); + + return newvol != oldvol; +} + +static int sgio2audio_source_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + static const char *texts[3] = { + "Line In", "Mic", "CD" + }; + uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; + uinfo->count = 1; + uinfo->value.enumerated.items = 3; + if (uinfo->value.enumerated.item >= 3) + uinfo->value.enumerated.item = 1; + strcpy(uinfo->value.enumerated.name, + texts[uinfo->value.enumerated.item]); + return 0; +} + +static int sgio2audio_source_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_sgio2audio *chip = snd_kcontrol_chip(kcontrol); + + ucontrol->value.enumerated.item[0] = ad1843_get_recsrc(&chip->ad1843); + return 0; +} + +static int sgio2audio_source_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_sgio2audio *chip = snd_kcontrol_chip(kcontrol); + int newsrc, oldsrc; + + oldsrc = ad1843_get_recsrc(&chip->ad1843); + newsrc = ad1843_set_recsrc(&chip->ad1843, + ucontrol->value.enumerated.item[0]); + + return newsrc != oldsrc; +} + +/* dac1/pcm0 mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_pcm0 __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Playback 0 Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_PCM_0, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + +/* dac2/pcm1 mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_pcm1 __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Playback 1 Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_PCM_1, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + +/* record level mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_reclevel __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Capture Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_RECLEV, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + +/* record level source control */ +static struct snd_kcontrol_new sgio2audio_ctrl_recsource __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Capture Source", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .info = sgio2audio_source_info, + .get = sgio2audio_source_get, + .put = sgio2audio_source_put, +}; + +/* line mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_line __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Line Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_LINE, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + +/* cd mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_cd __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "CD Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_CD, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + +/* mic mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_mic __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Mic Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_MIC, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + + +static int __devinit snd_sgio2audio_new_mixer(struct snd_sgio2audio *chip) +{ + int err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_pcm0, chip)); + if (err < 0) + return err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_pcm1, chip)); + if (err < 0) + return err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_reclevel, chip)); + if (err < 0) + return err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_recsource, chip)); + if (err < 0) + return err; + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_line, chip)); + if (err < 0) + return err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_cd, chip)); + if (err < 0) + return err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_mic, chip)); + if (err < 0) + return err; + + return 0; +} + +/* low-level audio interface DMA */ + +/* get data out of bounce buffer, count must be a multiple of 32 */ +/* returns 1 if a period has elapsed */ +static int snd_sgio2audio_dma_pull_frag(struct snd_sgio2audio *chip, + unsigned int ch, unsigned int count) +{ + int ret; + unsigned long src_base, src_pos, dst_mask; + unsigned char *dst_base; + int dst_pos; + u64 *src; + s16 *dst; + u64 x; + unsigned long flags; + struct snd_pcm_runtime *runtime = chip->channel[ch].substream->runtime; + + spin_lock_irqsave(&chip->channel[ch].lock, flags); + + src_base = (unsigned long) chip->ring_base | (ch << CHANNEL_RING_SHIFT); + src_pos = readq(&mace->perif.audio.chan[ch].read_ptr); + dst_base = runtime->dma_area; + dst_pos = chip->channel[ch].pos; + dst_mask = frames_to_bytes(runtime, runtime->buffer_size) - 1; + + /* check if a period has elapsed */ + chip->channel[ch].size += (count >> 3); /* in frames */ + ret = chip->channel[ch].size >= runtime->period_size; + chip->channel[ch].size %= runtime->period_size; + + while (count) { + src = (u64 *)(src_base + src_pos); + dst = (s16 *)(dst_base + dst_pos); + + x = *src; + dst[0] = (x >> CHANNEL_LEFT_SHIFT) & 0xffff; + dst[1] = (x >> CHANNEL_RIGHT_SHIFT) & 0xffff; + + src_pos = (src_pos + sizeof(u64)) & CHANNEL_RING_MASK; + dst_pos = (dst_pos + 2 * sizeof(s16)) & dst_mask; + count -= sizeof(u64); + } + + writeq(src_pos, &mace->perif.audio.chan[ch].read_ptr); /* in bytes */ + chip->channel[ch].pos = dst_pos; + + spin_unlock_irqrestore(&chip->channel[ch].lock, flags); + return ret; +} + +/* put some DMA data in bounce buffer, count must be a multiple of 32 */ +/* returns 1 if a period has elapsed */ +static int snd_sgio2audio_dma_push_frag(struct snd_sgio2audio *chip, + unsigned int ch, unsigned int count) +{ + int ret; + s64 l, r; + unsigned long dst_base, dst_pos, src_mask; + unsigned char *src_base; + int src_pos; + u64 *dst; + s16 *src; + unsigned long flags; + struct snd_pcm_runtime *runtime = chip->channel[ch].substream->runtime; + + spin_lock_irqsave(&chip->channel[ch].lock, flags); + + dst_base = (unsigned long)chip->ring_base | (ch << CHANNEL_RING_SHIFT); + dst_pos = readq(&mace->perif.audio.chan[ch].write_ptr); + src_base = runtime->dma_area; + src_pos = chip->channel[ch].pos; + src_mask = frames_to_bytes(runtime, runtime->buffer_size) - 1; + + /* check if a period has elapsed */ + chip->channel[ch].size += (count >> 3); /* in frames */ + ret = chip->channel[ch].size >= runtime->period_size; + chip->channel[ch].size %= runtime->period_size; + + while (count) { + src = (s16 *)(src_base + src_pos); + dst = (u64 *)(dst_base + dst_pos); + + l = src[0]; /* sign extend */ + r = src[1]; /* sign extend */ + + *dst = ((l & 0x00ffffff) << CHANNEL_LEFT_SHIFT) | + ((r & 0x00ffffff) << CHANNEL_RIGHT_SHIFT); + + dst_pos = (dst_pos + sizeof(u64)) & CHANNEL_RING_MASK; + src_pos = (src_pos + 2 * sizeof(s16)) & src_mask; + count -= sizeof(u64); + } + + writeq(dst_pos, &mace->perif.audio.chan[ch].write_ptr); /* in bytes */ + chip->channel[ch].pos = src_pos; + + spin_unlock_irqrestore(&chip->channel[ch].lock, flags); + return ret; +} + +static int snd_sgio2audio_dma_start(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_sgio2audio_chan *chan = substream->runtime->private_data; + int ch = chan->idx; + + /* reset DMA channel */ + writeq(CHANNEL_CONTROL_RESET, &mace->perif.audio.chan[ch].control); + udelay(10); + writeq(0, &mace->perif.audio.chan[ch].control); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* push a full buffer */ + snd_sgio2audio_dma_push_frag(chip, ch, CHANNEL_RING_SIZE - 32); + } + /* set DMA to wake on 50% empty and enable interrupt */ + writeq(CHANNEL_DMA_ENABLE | CHANNEL_INT_THRESHOLD_50, + &mace->perif.audio.chan[ch].control); + return 0; +} + +static int snd_sgio2audio_dma_stop(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio_chan *chan = substream->runtime->private_data; + + writeq(0, &mace->perif.audio.chan[chan->idx].control); + return 0; +} + +static irqreturn_t snd_sgio2audio_dma_in_isr(int irq, void *dev_id) +{ + struct snd_sgio2audio_chan *chan = dev_id; + struct snd_pcm_substream *substream; + struct snd_sgio2audio *chip; + int count, ch; + + substream = chan->substream; + chip = snd_pcm_substream_chip(substream); + ch = chan->idx; + + /* empty the ring */ + count = CHANNEL_RING_SIZE - + readq(&mace->perif.audio.chan[ch].depth) - 32; + if (snd_sgio2audio_dma_pull_frag(chip, ch, count)) + snd_pcm_period_elapsed(substream); + + return IRQ_HANDLED; +} + +static irqreturn_t snd_sgio2audio_dma_out_isr(int irq, void *dev_id) +{ + struct snd_sgio2audio_chan *chan = dev_id; + struct snd_pcm_substream *substream; + struct snd_sgio2audio *chip; + int count, ch; + + substream = chan->substream; + chip = snd_pcm_substream_chip(substream); + ch = chan->idx; + /* fill the ring */ + count = CHANNEL_RING_SIZE - + readq(&mace->perif.audio.chan[ch].depth) - 32; + if (snd_sgio2audio_dma_push_frag(chip, ch, count)) + snd_pcm_period_elapsed(substream); + + return IRQ_HANDLED; +} + +/* PCM part */ +/* PCM hardware definition */ +static struct snd_pcm_hardware snd_sgio2audio_playback_hw = { + .info = (SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER), + .formats = SNDRV_PCM_FMTBIT_S16_BE, + .rates = SNDRV_PCM_RATE_8000_48000, + .rate_min = 8000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + .buffer_bytes_max = 65536, + .period_bytes_min = 32768, + .period_bytes_max = 65536, + .periods_min = 1, + .periods_max = 1024, +}; + +/* PCM playback open callback */ +static int snd_sgio2audio_playback1_open(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + + runtime->hw = snd_sgio2audio_playback_hw; + runtime->private_data = &chip->channel[1]; + return 0; +} + +static int snd_sgio2audio_playback2_open(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + + runtime->hw = snd_sgio2audio_playback_hw; + runtime->private_data = &chip->channel[2]; + return 0; +} + +/* PCM playback close callback */ +static int snd_sgio2audio_playback_close(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + + runtime->private_data = NULL; + return 0; +} + +/* PCM capture open callback */ +static int snd_sgio2audio_capture_open(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + + runtime->hw = snd_sgio2audio_playback_hw; + runtime->private_data = &chip->channel[0]; + return 0; +} + +/* PCM capture close callback */ +static int snd_sgio2audio_capture_close(struct snd_pcm_substream *substream) +{ + return 0; +} + + +/* hw_params callback */ +static int snd_sgio2audio_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + /* alloc virtual 'dma' area */ + if (substream->runtime->dma_area) + vfree(substream->runtime->dma_area); + substream->runtime->dma_area = vmalloc(params_buffer_bytes(hw_params)); + if (substream->runtime->dma_area == NULL) + return -ENOMEM; + return 0; +} + +/* hw_free callback */ +static int snd_sgio2audio_pcm_hw_free(struct snd_pcm_substream *substream) +{ + if (substream->runtime->dma_area) + vfree(substream->runtime->dma_area); + substream->runtime->dma_area = NULL; + return 0; +} + +/* prepare callback */ +static int snd_sgio2audio_pcm_prepare(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_sgio2audio_chan *chan = substream->runtime->private_data; + int ch = chan->idx; + unsigned long flags; + + spin_lock_irqsave(&chip->channel[ch].lock, flags); + + /* Setup the pseudo-dma transfer pointers. */ + chip->channel[ch].pos = 0; + chip->channel[ch].size = 0; + chip->channel[ch].substream = substream; + + /* set AD1843 format */ + /* hardware format is always S16_LE */ + switch (substream->stream) { + case SNDRV_PCM_STREAM_PLAYBACK: + ad1843_setup_dac(&chip->ad1843, + ch - 1, + runtime->rate, + SNDRV_PCM_FORMAT_S16_LE, + runtime->channels); + break; + case SNDRV_PCM_STREAM_CAPTURE: + ad1843_setup_adc(&chip->ad1843, + runtime->rate, + SNDRV_PCM_FORMAT_S16_LE, + runtime->channels); + break; + } + spin_unlock_irqrestore(&chip->channel[ch].lock, flags); + return 0; +} + +/* trigger callback */ +static int snd_sgio2audio_pcm_trigger(struct snd_pcm_substream *substream, + int cmd) +{ + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + /* start the PCM engine */ + snd_sgio2audio_dma_start(substream); + break; + case SNDRV_PCM_TRIGGER_STOP: + /* stop the PCM engine */ + snd_sgio2audio_dma_stop(substream); + break; + default: + return -EINVAL; + } + return 0; +} + +/* pointer callback */ +static snd_pcm_uframes_t +snd_sgio2audio_pcm_pointer(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_sgio2audio_chan *chan = substream->runtime->private_data; + + /* get the current hardware pointer */ + return bytes_to_frames(substream->runtime, + chip->channel[chan->idx].pos); +} + +/* get the physical page pointer on the given offset */ +static struct page *snd_sgio2audio_page(struct snd_pcm_substream *substream, + unsigned long offset) +{ + return vmalloc_to_page(substream->runtime->dma_area + offset); +} + +/* operators */ +static struct snd_pcm_ops snd_sgio2audio_playback1_ops = { + .open = snd_sgio2audio_playback1_open, + .close = snd_sgio2audio_playback_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_sgio2audio_pcm_hw_params, + .hw_free = snd_sgio2audio_pcm_hw_free, + .prepare = snd_sgio2audio_pcm_prepare, + .trigger = snd_sgio2audio_pcm_trigger, + .pointer = snd_sgio2audio_pcm_pointer, + .page = snd_sgio2audio_page, +}; + +static struct snd_pcm_ops snd_sgio2audio_playback2_ops = { + .open = snd_sgio2audio_playback2_open, + .close = snd_sgio2audio_playback_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_sgio2audio_pcm_hw_params, + .hw_free = snd_sgio2audio_pcm_hw_free, + .prepare = snd_sgio2audio_pcm_prepare, + .trigger = snd_sgio2audio_pcm_trigger, + .pointer = snd_sgio2audio_pcm_pointer, + .page = snd_sgio2audio_page, +}; + +static struct snd_pcm_ops snd_sgio2audio_capture_ops = { + .open = snd_sgio2audio_capture_open, + .close = snd_sgio2audio_capture_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_sgio2audio_pcm_hw_params, + .hw_free = snd_sgio2audio_pcm_hw_free, + .prepare = snd_sgio2audio_pcm_prepare, + .trigger = snd_sgio2audio_pcm_trigger, + .pointer = snd_sgio2audio_pcm_pointer, + .page = snd_sgio2audio_page, +}; + +/* + * definitions of capture are omitted here... + */ + +/* create a pcm device */ +static int __devinit snd_sgio2audio_new_pcm(struct snd_sgio2audio *chip) +{ + struct snd_pcm *pcm; + int err; + + /* create first pcm device with one outputs and one input */ + err = snd_pcm_new(chip->card, "SGI O2 Audio", 0, 1, 1, &pcm); + if (err < 0) + return err; + + pcm->private_data = chip; + strcpy(pcm->name, "SGI O2 DAC1"); + + /* set operators */ + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, + &snd_sgio2audio_playback1_ops); + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, + &snd_sgio2audio_capture_ops); + + /* create second pcm device with one outputs and no input */ + err = snd_pcm_new(chip->card, "SGI O2 Audio", 1, 1, 0, &pcm); + if (err < 0) + return err; + + pcm->private_data = chip; + strcpy(pcm->name, "SGI O2 DAC2"); + + /* set operators */ + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, + &snd_sgio2audio_playback2_ops); + + return 0; +} + +static struct { + int idx; + int irq; + irqreturn_t (*isr)(int, void *); + const char *desc; +} snd_sgio2_isr_table[] = { + { + .idx = 0, + .irq = MACEISA_AUDIO1_DMAT_IRQ, + .isr = snd_sgio2audio_dma_in_isr, + .desc = "Capture DMA Channel 0" + }, { + .idx = 1, + .irq = MACEISA_AUDIO2_DMAT_IRQ, + .isr = snd_sgio2audio_dma_out_isr, + .desc = "Playback DMA Channel 1" + }, { + .idx = 2, + .irq = MACEISA_AUDIO3_DMAT_IRQ, + .isr = snd_sgio2audio_dma_out_isr, + .desc = "Playback DMA Channel 2" + } +}; + +/* ALSA driver */ + +static int snd_sgio2audio_free(struct snd_sgio2audio *chip) +{ + int i; + + /* reset interface */ + writeq(AUDIO_CONTROL_RESET, &mace->perif.audio.control); + udelay(1); + writeq(0, &mace->perif.audio.control); + + /* release IRQ's */ + for (i = 0; i < ARRAY_SIZE(snd_sgio2_isr_table); i++) + free_irq(snd_sgio2_isr_table[i].irq, + &chip->channel[snd_sgio2_isr_table[i].idx]); + + dma_free_coherent(NULL, MACEISA_RINGBUFFERS_SIZE, + chip->ring_base, chip->ring_base_dma); + + /* release card data */ + kfree(chip); + return 0; +} + +static int snd_sgio2audio_dev_free(struct snd_device *device) +{ + struct snd_sgio2audio *chip = device->device_data; + /* TODO: component destructor */ + return snd_sgio2audio_free(chip); +} + +static struct snd_device_ops ops = { + .dev_free = snd_sgio2audio_dev_free, +}; + +static int __devinit snd_sgio2audio_create(struct snd_card *card, + struct snd_sgio2audio **rchip) +{ + struct snd_sgio2audio *chip; + int i, err; + + *rchip = NULL; + + /* check if a codec is attached to the interface */ + /* (Audio or Audio/Video board present) */ + if (!(readq(&mace->perif.audio.control) & AUDIO_CONTROL_CODEC_PRESENT)) + return -ENOENT; + + chip = kzalloc(sizeof(struct snd_sgio2audio), GFP_KERNEL); + if (chip == NULL) + return -ENOMEM; + + chip->card = card; + + chip->ring_base = dma_alloc_coherent(NULL, MACEISA_RINGBUFFERS_SIZE, + &chip->ring_base_dma, GFP_USER); + if (chip->ring_base == NULL) { + printk(KERN_ERR + "sgio2audio: could not allocate ring buffers\n"); + kfree(chip); + return -ENOMEM; + } + + spin_lock_init(&chip->ad1843_lock); + + chip->volume = SGIO2AUDIO_MAX_VOLUME; + + /* initialize channels */ + for (i = 0; i < 3; i++) { + spin_lock_init(&chip->channel[i].lock); + chip->channel[i].idx = i; + } + + /* allocate IRQs */ + for (i = 0; i < ARRAY_SIZE(snd_sgio2_isr_table); i++) { + if (request_irq(snd_sgio2_isr_table[i].irq, + snd_sgio2_isr_table[i].isr, + IRQF_SHARED, + snd_sgio2_isr_table[i].desc, + &chip->channel[snd_sgio2_isr_table[i].idx])) { + snd_sgio2audio_free(chip); + printk(KERN_ERR "sgio2audio: cannot allocate irq %d\n", + snd_sgio2_isr_table[i].irq); + return -EBUSY; + } + } + + /* reset the interface */ + writeq(AUDIO_CONTROL_RESET, &mace->perif.audio.control); + udelay(1); + writeq(0, &mace->perif.audio.control); + udelay(100); /* give time to recover */ + + /* set ring base */ + writeq(chip->ring_base_dma, &mace->perif.ctrl.ringbase); + + /* attach the AD1843 codec */ + chip->ad1843.read = read_ad1843_reg; + chip->ad1843.write = write_ad1843_reg; + chip->ad1843.chip = chip; + + /* initialize the AD1843 codec */ + err = ad1843_init(&chip->ad1843); + if (err < 0) { + snd_sgio2audio_free(chip); + return err; + } + + err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); + if (err < 0) { + snd_sgio2audio_free(chip); + return err; + } + *rchip = chip; + return 0; +} + +static int __devinit snd_sgio2audio_probe(struct platform_device *pdev) +{ + struct snd_card *card; + struct snd_sgio2audio *chip; + int err; + + card = snd_card_new(index, id, THIS_MODULE, 0); + if (card == NULL) + return -ENOMEM; + + err = snd_sgio2audio_create(card, &chip); + if (err < 0) { + snd_card_free(card); + return err; + } + snd_card_set_dev(card, &pdev->dev); + + /* TODO : finish PCM, do mixer and /proc */ + err = snd_sgio2audio_new_pcm(chip); + if (err < 0) { + snd_card_free(card); + return err; + } + err = snd_sgio2audio_new_mixer(chip); + if (err < 0) { + snd_card_free(card); + return err; + } + + strcpy(card->driver, "SGI O2 Audio"); + strcpy(card->shortname, "SGI O2 Audio"); + sprintf(card->longname, "%s irq %i-%i", + card->shortname, + MACEISA_AUDIO1_DMAT_IRQ, + MACEISA_AUDIO3_MERR_IRQ); + + err = snd_card_register(card); + if (err < 0) { + snd_card_free(card); + return err; + } + platform_set_drvdata(pdev, card); + return 0; +} + +static int __exit snd_sgio2audio_remove(struct platform_device *pdev) +{ + struct snd_card *card = platform_get_drvdata(pdev); + + snd_card_free(card); + platform_set_drvdata(pdev, NULL); + return 0; +} + +static struct platform_driver sgio2audio_driver = { + .probe = snd_sgio2audio_probe, + .remove = __devexit_p(snd_sgio2audio_remove), + .driver = { + .name = "sgio2audio", + .owner = THIS_MODULE, + } +}; + +static int __init alsa_card_sgio2audio_init(void) +{ + return platform_driver_register(&sgio2audio_driver); +} + +static void __exit alsa_card_sgio2audio_exit(void) +{ + platform_driver_unregister(&sgio2audio_driver); +} + +module_init(alsa_card_sgio2audio_init) +module_exit(alsa_card_sgio2audio_exit) -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From yoriko@sm.sony.co.jp Thu Jul 3 06:06:16 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 06:06:24 +0100 (BST) Received: from ms5.Sony.CO.JP ([211.125.136.201]:59346 "EHLO ms5.sony.co.jp") by ftp.linux-mips.org with ESMTP id S20096375AbYGCFGQ (ORCPT ); Thu, 3 Jul 2008 06:06:16 +0100 Received: from mta5.sony.co.jp (mta5.Sony.CO.JP [137.153.71.6]) by ms5.sony.co.jp (R8/Sony) with ESMTP id m6355s59016330; Thu, 3 Jul 2008 14:05:54 +0900 (JST) Received: from mta5.sony.co.jp (localhost [127.0.0.1]) by mta5.sony.co.jp (R8/Sony) with ESMTP id m6355slJ029703; Thu, 3 Jul 2008 14:05:54 +0900 (JST) Received: from smail1.sm.sony.co.jp (smail1.sm.sony.co.jp [43.11.253.1]) by mta5.sony.co.jp (R8/Sony) with ESMTP id m6355sVc029691; Thu, 3 Jul 2008 14:05:54 +0900 (JST) Received: from imail.sm.sony.co.jp (imail.sm.sony.co.jp [43.4.141.32]) by smail1.sm.sony.co.jp (8.11.6p2/8.11.6) with ESMTP id m6355sP11050; Thu, 3 Jul 2008 14:05:54 +0900 (JST) Received: from [43.4.145.254] (gco-w12f-vlan145-254.sm.sony.co.jp [43.4.145.254]) by imail.sm.sony.co.jp (8.12.11/3.7W) with ESMTP id m6355oL8012013; Thu, 3 Jul 2008 14:05:50 +0900 (JST) Date: Thu, 03 Jul 2008 14:05:54 +0900 From: Yoriko Komatsuzaki To: Daniel Jacobowitz Subject: Re: do-lookup.h regarding to mips/dlsym and libstdc++ Cc: Chris Friesen , libc-ports , linux-mips@linux-mips.org In-Reply-To: <20080702124722.GA15301@caradoc.them.org> References: <20080129132739.5D6B.YORIKO@sm.sony.co.jp> <20080702124722.GA15301@caradoc.them.org> Message-Id: <20080703140301.D2B2.C06B4389@sm.sony.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Mailer: Becky! ver. 2.47 [ja] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19704 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoriko@sm.sony.co.jp Precedence: bulk X-list: linux-mips Content-Length: 1642 Lines: 47 Thank you for your reply. I will do the checking. --- Yoriko Komatsuzaki (yoriko@sm.sony.co.jp) System Software Development Department Common Technology Division Technology Development Group Sony Corporation > On Tue, Jan 29, 2008 at 01:32:20PM +0900, Yoriko Komatsuzaki wrote: > > Because even though UNDEF symbol is found, > > it can process as global symbol for the rare occasion. > > > > This phenomena is showed only in mips. When libstdc++ is linked in > > proior libc, the malloc's entry in libstdc++ MIPS.stubs table seemed to > > be recognized as the malloc global symbol ... > > > > How do you feel about it? > > On Mon, May 26, 2008 at 11:51:56AM -0600, Chris Friesen wrote: > > On MIPS, the DEFAULT returns the address of this libraries undefined > > symbol for the extern and NEXT returns our external procedure. Putting > > in a second RTLD_NEXT call returned the real sigaction address. > > > > This worked for most procedures we are looking for. However, during > > booting, we have an app that uses a specific library which has an extern > > for sigaction as well and now in the preloaded code we need a fourth call > > to dlsym to skip that one. > > Hi folks, > > This bug is fixed as a by-product of support for non-PIC MIPS > executables. Either Richard's patch or CodeSourcery's, applied to > glibc, should suffice. It'll be another week or two at least before > they're applied to CVS, but in the mean time you can find them here: > > http://sourceware.org/ml/binutils/2008-06/msg00280.html > http://sourceware.org/ml/binutils/2008-07/msg00008.html > > -- > Daniel Jacobowitz > CodeSourcery > From ralf@linux-mips.org Thu Jul 3 15:50:31 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 15:50:41 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:37775 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20130414AbYGCOub (ORCPT ); Thu, 3 Jul 2008 15:50:31 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m63EnD95009752; Thu, 3 Jul 2008 16:49:38 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m63EnBf3009738; Thu, 3 Jul 2008 15:49:11 +0100 Date: Thu, 3 Jul 2008 15:49:11 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Enable FAST-20 for onboard scsi Message-ID: <20080703144911.GA9630@linux-mips.org> References: <20080702190603.26B63C214C@solo.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080702190603.26B63C214C@solo.franken.de> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19705 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 436 Lines: 12 On Wed, Jul 02, 2008 at 09:06:03PM +0200, Thomas Bogendoerfer wrote: > Both onboard controller of the O2 support FAST-20 transfer speeds, > but the bit, which signals that to the aic driver, isn't set. Instead > of adding detection code to the scsi driver, we just fake the missing > bit in the PCI config space of the scsi chips. > > Signed-off-by: Thomas Bogendoerfer Thanks, queued for 2.6.27. Ralf From vegard.nossum@gmail.com Thu Jul 3 15:50:58 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 15:51:05 +0100 (BST) Received: from wf-out-1314.google.com ([209.85.200.174]:28023 "EHLO wf-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20130425AbYGCOun (ORCPT ); Thu, 3 Jul 2008 15:50:43 +0100 Received: by wf-out-1314.google.com with SMTP id 27so926140wfd.21 for ; Thu, 03 Jul 2008 07:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:cc:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:references; bh=ViDqCdSNz8P/ZSF6nlyJcQhxX3DrOPn2e/3PAJam2UE=; b=WHyWYo2Yw1i/93gvNqEbxSX2Ew9y6KRPVAr6E5vYRtzHcSkOzN9hm8/G0HrNA80uHh 4XzfHOEL4zzK0cmL0HO5wRnXIi+97fGAYQrDZkn1ZsCr/xz4znCCMAxMigHZV0mo91/0 pv4p1nU3Jtsr3fPLxGMoOnMQiyBE8jhyzlLWc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:cc:in-reply-to:mime-version :content-type:content-transfer-encoding:content-disposition :references; b=Ehu0ygmRhaUG83iYnqboql1eJVp1TFfD4UpvW7MhKxUupuXx0r7LJsDu21lC+85CtN YW07pMo0w1UOorbWGlgfNLNmpY2KKp1u2mdGxIeZvVLdUpVqkVxRdRiiYnq+4kYWWhqy VPyNOTouAl7+eJWBD3ogLbP6ZR1lDtEi5SCz0= Received: by 10.142.70.11 with SMTP id s11mr19021wfa.293.1215096640239; Thu, 03 Jul 2008 07:50:40 -0700 (PDT) Received: by 10.142.204.16 with HTTP; Thu, 3 Jul 2008 07:50:40 -0700 (PDT) Message-ID: <19f34abd0807030750n31a3bc3t8609f58c9c1f7c7@mail.gmail.com> Date: Thu, 3 Jul 2008 16:50:40 +0200 From: "Vegard Nossum" To: saravanakumar Subject: Re: kernel configuration_ help Cc: "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" In-Reply-To: <1214997772.16081.3.camel@teclever-desktop> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <1214997772.16081.3.camel@teclever-desktop> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19706 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vegard.nossum@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1312 Lines: 39 On Wed, Jul 2, 2008 at 1:22 PM, saravanakumar wrote: > hai, > i want my usb to access the root file system,for that what are the > changes to be done in kernel code, and in the configuration, i think > changes to be done in do_mount.c for root delay, if its correct where to > give the delay. Hi, If I understand correctly, you have your root filesystem on a USB device. It seems that you must pass the rootdelay= option on the kernel command line. No changes to the code should be necessary. From Documentation/kernel-parameters.txt: rootdelay= [KNL] Delay (in seconds) to pause before attempting to mount the root filesystem Try 10 seconds first, then go lower until it stops working. It seems that this unfortunate hack is necessary because USB devices can take an indefinite amount of time to register themselves once connected. You will of course also need the relevant config options. Make sure your filesystem is selected, Advanced partition selection, USB, and SCSI disk support. Good luck! Vegard -- "The animistic metaphor of the bug that maliciously sneaked in while the programmer was not looking is intellectually dishonest as it disguises that the error is the programmer's own creation." -- E. W. Dijkstra, EWD1036 From anemo@mba.ocn.ne.jp Thu Jul 3 16:02:52 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 16:03:00 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:42178 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20130896AbYGCPCw (ORCPT ); Thu, 3 Jul 2008 16:02:52 +0100 Received: from localhost (p7152-ipad201funabasi.chiba.ocn.ne.jp [222.146.70.152]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 3F765ADA1; Fri, 4 Jul 2008 00:02:45 +0900 (JST) Date: Fri, 04 Jul 2008 00:04:26 +0900 (JST) Message-Id: <20080704.000426.39153587.anemo@mba.ocn.ne.jp> To: ths@networkno.de Cc: mlarsen@broadcom.com, linux-mips@linux-mips.org Subject: Re: Bug in atomic_sub_if_positive From: Atsushi Nemoto In-Reply-To: <20080702105155.GC7007@networkno.de> References: <20080702095955.GA7007@networkno.de> <20080702.193133.211490377.nemoto@toshiba-tops.co.jp> <20080702105155.GC7007@networkno.de> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19707 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 216 Lines: 10 On Wed, 2 Jul 2008 11:51:55 +0100, Thiemo Seufer wrote: > > The patch looks correct. > > Agreed. Ralf, too late for 2.6.26? Anyway I think it should go into -stable tree too. --- Atsushi Nemoto From ralf@linux-mips.org Thu Jul 3 16:22:32 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 16:22:38 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:62886 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20132325AbYGCPWc (ORCPT ); Thu, 3 Jul 2008 16:22:32 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m63FLVlt024063; Thu, 3 Jul 2008 17:21:56 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m63FLU09024056; Thu, 3 Jul 2008 16:21:30 +0100 Date: Thu, 3 Jul 2008 16:21:30 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/5] [MIPS] 8253: make the pit_clockevent variable static Message-ID: <20080703152130.GA11434@linux-mips.org> References: <1213773503-23536-1-git-send-email-dmitri.vorobiev@movial.fi> <1213773503-23536-2-git-send-email-dmitri.vorobiev@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1213773503-23536-2-git-send-email-dmitri.vorobiev@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19708 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 551 Lines: 16 On Wed, Jun 18, 2008 at 10:18:19AM +0300, Dmitri Vorobiev wrote: > From: Dmitri Vorobiev > Date: Wed, 18 Jun 2008 10:18:19 +0300 > To: ralf@linux-mips.org, linux-mips@linux-mips.org > Subject: [PATCH 1/5] [MIPS] 8253: make the pit_clockevent variable static > > The pit_clockevent symbol is needlessly defined global. This patch makes > that variable static. > > Spotted by sparse. Compile-tested using Malta defconfig. > > Signed-off-by: Dmitri Vorobiev Queued for 2.6.27. Thanks, Ralf From ralf@linux-mips.org Thu Jul 3 16:23:18 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 16:23:23 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:423 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20132465AbYGCPXS (ORCPT ); Thu, 3 Jul 2008 16:23:18 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m63FMHF3024337; Thu, 3 Jul 2008 17:22:42 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m63FMHja024336; Thu, 3 Jul 2008 16:22:17 +0100 Date: Thu, 3 Jul 2008 16:22:17 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/5] [MIPS] Namespace clean-up in arch/mips/pci/pci.c Message-ID: <20080703152217.GA24232@linux-mips.org> References: <1213773503-23536-1-git-send-email-dmitri.vorobiev@movial.fi> <1213773503-23536-3-git-send-email-dmitri.vorobiev@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1213773503-23536-3-git-send-email-dmitri.vorobiev@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19709 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 485 Lines: 21 On Wed, Jun 18, 2008 at 10:18:20AM +0300, Dmitri Vorobiev wrote: > The following symbols > > hose_head > hose_tail > > are needlessly defined global in arch/mips/pci/pci.c, and > this patch makes them static. > > The variable pci_isa_hose is not used, and is removed by > this patch. > > Spotted by namespacecheck. Tested by booting a Malta 4Kc > board up to the shell prompt. > > Signed-off-by: Dmitri Vorobiev Queued for 2.6.27. Thanks, Ralf From ralf@linux-mips.org Thu Jul 3 16:23:46 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 16:23:52 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:1959 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20132516AbYGCPXq (ORCPT ); Thu, 3 Jul 2008 16:23:46 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m63FMjHR024510; Thu, 3 Jul 2008 17:23:10 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m63FMjG9024509; Thu, 3 Jul 2008 16:22:45 +0100 Date: Thu, 3 Jul 2008 16:22:45 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 3/5] [MIPS] A few cleanups in malta_int.c Message-ID: <20080703152245.GB11434@linux-mips.org> References: <1213773503-23536-1-git-send-email-dmitri.vorobiev@movial.fi> <1213773503-23536-4-git-send-email-dmitri.vorobiev@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1213773503-23536-4-git-send-email-dmitri.vorobiev@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19710 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 705 Lines: 19 On Wed, Jun 18, 2008 at 10:18:21AM +0300, Dmitri Vorobiev wrote: > Both the fill_ipi_map() routine and the gic_intr_map array defined > in arch/mips/mips-boards/malta/malta_int.c are not used outside of > the latter file. Thus, these objects can become static. Moreover, > these two objects are used by the MT code only, which is why this > patch adds the appropriate ifdef. > > While at it, this patch removes an unnecessary preprocessing macro > in favor of the commonly used ARRAY_SIZE. > > Successfully tested using a Qemu-emulated Malta board for both SMP > and UP kernels. > > Signed-off-by: Dmitri Vorobiev Queued for 2.6.27 after fixing a reject. Thanks, Ralf From ralf@linux-mips.org Thu Jul 3 16:24:13 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 16:24:17 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:3751 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20132595AbYGCPYN (ORCPT ); Thu, 3 Jul 2008 16:24:13 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m63FNC2u024667; Thu, 3 Jul 2008 17:23:37 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m63FN6gY024635; Thu, 3 Jul 2008 16:23:06 +0100 Date: Thu, 3 Jul 2008 16:23:06 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 4/5] [MIPS] Make gcmp_probe() static Message-ID: <20080703152306.GB24232@linux-mips.org> References: <1213773503-23536-1-git-send-email-dmitri.vorobiev@movial.fi> <1213773503-23536-5-git-send-email-dmitri.vorobiev@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1213773503-23536-5-git-send-email-dmitri.vorobiev@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19711 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 324 Lines: 12 On Wed, Jun 18, 2008 at 10:18:22AM +0300, Dmitri Vorobiev wrote: > The gcmp_probe() function is needlessly defined global, and > this patch makes it static. > > Tested by booting a Malta 4Kc board up to the shell prompt. > > Signed-off-by: Dmitri Vorobiev Queued for 2.6.27. Thanks, Ralf From ralf@linux-mips.org Thu Jul 3 16:24:39 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 16:24:42 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:5543 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20132635AbYGCPYj (ORCPT ); Thu, 3 Jul 2008 16:24:39 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m63FNc7j024829; Thu, 3 Jul 2008 17:24:03 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m63FNc3A024828; Thu, 3 Jul 2008 16:23:38 +0100 Date: Thu, 3 Jul 2008 16:23:38 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 5/5] [MIPS] Add an appropriate header into display.c Message-ID: <20080703152338.GC11434@linux-mips.org> References: <1213773503-23536-1-git-send-email-dmitri.vorobiev@movial.fi> <1213773503-23536-6-git-send-email-dmitri.vorobiev@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1213773503-23536-6-git-send-email-dmitri.vorobiev@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19712 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 859 Lines: 27 On Wed, Jun 18, 2008 at 10:18:23AM +0300, Dmitri Vorobiev wrote: > The following errors were caught by sparse: > > >>>>>>>>>>> > > arch/mips/mips-boards/generic/display.c:30:6: warning: symbol > 'mips_display_message' was not declared. Should it be static? > > arch/mips/mips-boards/generic/display.c:58:6: warning: symbol > 'mips_scroll_message' was not declared. Should it be static? > > >>>>>>>>>>> > > This patch includes the asm/mips-boards/prom.h header file into > arch/mips/mips-boards/generic/display.c. This adds the needed > function declarations, and the errors are gone. > > Compile-tested using defconfigs for Malta, Atlas and SEAD boards. > Runtime test was successfully performed by booting a Malta 4Kc > board up to the shell prompt. > > Signed-off-by: Dmitri Vorobiev Queued for 2.6.27. Thanks, Ralf From dmitri.vorobiev@movial.fi Thu Jul 3 16:25:53 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 16:25:55 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:51642 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S20132827AbYGCPZw (ORCPT ); Thu, 3 Jul 2008 16:25:52 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 88585C80EF; Thu, 3 Jul 2008 18:25:46 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id T-B8x4W0+2TB; Thu, 3 Jul 2008 18:25:46 +0300 (EEST) Received: from [172.17.49.48] (sd048.hel.movial.fi [172.17.49.48]) by smtp.movial.fi (Postfix) with ESMTP id 68BEBC80ED; Thu, 3 Jul 2008 18:25:46 +0300 (EEST) Message-ID: <486CF01F.9080808@movial.fi> Date: Thu, 03 Jul 2008 18:28:31 +0300 From: Dmitri Vorobiev Organization: Movial Creative Technologies User-Agent: Icedove 1.5.0.14eol (X11/20080509) MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: [PATCH 5/5] [MIPS] Add an appropriate header into display.c References: <1213773503-23536-1-git-send-email-dmitri.vorobiev@movial.fi> <1213773503-23536-6-git-send-email-dmitri.vorobiev@movial.fi> <20080703152338.GC11434@linux-mips.org> In-Reply-To: <20080703152338.GC11434@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19713 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips Content-Length: 906 Lines: 26 Ralf Baechle wrote: > On Wed, Jun 18, 2008 at 10:18:23AM +0300, Dmitri Vorobiev wrote: > >> The following errors were caught by sparse: >> >> arch/mips/mips-boards/generic/display.c:30:6: warning: symbol >> 'mips_display_message' was not declared. Should it be static? >> >> arch/mips/mips-boards/generic/display.c:58:6: warning: symbol >> 'mips_scroll_message' was not declared. Should it be static? >> >> This patch includes the asm/mips-boards/prom.h header file into >> arch/mips/mips-boards/generic/display.c. This adds the needed >> function declarations, and the errors are gone. >> >> Compile-tested using defconfigs for Malta, Atlas and SEAD boards. >> Runtime test was successfully performed by booting a Malta 4Kc >> board up to the shell prompt. >> >> Signed-off-by: Dmitri Vorobiev > > Queued for 2.6.27. Thanks, Ralf, thanks for picking up the series. Dmitri From ralf@linux-mips.org Thu Jul 3 16:44:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 16:44:53 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:24489 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20133768AbYGCPoq (ORCPT ); Thu, 3 Jul 2008 16:44:46 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m63FhTAL005721; Thu, 3 Jul 2008 17:43:54 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m63FhT4a005714; Thu, 3 Jul 2008 16:43:29 +0100 Date: Thu, 3 Jul 2008 16:43:29 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] IP28: switch to "normal" mode after PROM no longer needed Message-ID: <20080703154329.GA21642@linux-mips.org> References: <20080318214756.D7E77C2816@solo.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080318214756.D7E77C2816@solo.franken.de> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19714 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 451 Lines: 14 On Tue, Mar 18, 2008 at 10:47:56PM +0100, Thomas Bogendoerfer wrote: > SGI-IP28 is running in so called slow mode, when kernel is started > from the PROM. PROM calls must be done in slow mode otherwise the > PROM will issue an error. To get better memory performance we now > switch to normal mode, when the PROM is no longer needed. > > Signed-off-by: Thomas Bogendoerfer Ugly ... but applied anyway. Thanks, Ralf From anemo@mba.ocn.ne.jp Thu Jul 3 16:58:06 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 03 Jul 2008 16:58:12 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:44740 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20134230AbYGCP6G (ORCPT ); Thu, 3 Jul 2008 16:58:06 +0100 Received: from localhost (p7152-ipad201funabasi.chiba.ocn.ne.jp [222.146.70.152]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id B67E5AA0D; Fri, 4 Jul 2008 00:57:59 +0900 (JST) Date: Fri, 04 Jul 2008 00:59:40 +0900 (JST) Message-Id: <20080704.005940.108121109.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] Declare some pci variables in header file From: Atsushi Nemoto In-Reply-To: <20080419.005346.85684007.anemo@mba.ocn.ne.jp> References: <20080419.005346.85684007.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19715 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 2633 Lines: 82 On Sat, 19 Apr 2008 00:53:46 +0900 (JST), Atsushi Nemoto wrote: > Declare pci_probe_only, etc. in asm-mips/pci.h file. This will fix > some sparse warnings. Revesed against current linux-queue tree. ------------------------------------------------------ Subject: [PATCH] Declare some pci variables in header file From: Atsushi Nemoto Declare pci_probe_only, etc. in asm-mips/pci.h file. This will fix some sparse warnings. Signed-off-by: Atsushi Nemoto --- arch/mips/pci/fixup-vr4133.c | 1 - arch/mips/pci/pci-bcm1480.c | 1 - arch/mips/pci/pci-ip27.c | 1 - arch/mips/pci/pci-sb1250.c | 1 - include/asm-mips/pci.h | 3 +++ 5 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/mips/pci/fixup-vr4133.c b/arch/mips/pci/fixup-vr4133.c index de5e5f6..34e651b 100644 --- a/arch/mips/pci/fixup-vr4133.c +++ b/arch/mips/pci/fixup-vr4133.c @@ -171,7 +171,6 @@ void i8259_init(void) int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - extern int pci_probe_only; pci_probe_only = 1; #ifdef CONFIG_ROCKHOPPER diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index d19d262..a9060c7 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -202,7 +202,6 @@ static int __init bcm1480_pcibios_init(void) { uint32_t cmdreg; uint64_t reg; - extern int pci_probe_only; /* CFE will assign PCI resources */ pci_probe_only = 1; diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index a185169..ce92f82 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -47,7 +47,6 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) static int num_bridges = 0; bridge_t *bridge; int slot; - extern int pci_probe_only; pci_probe_only = 1; diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index 9bc102a..bf63959 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -210,7 +210,6 @@ static int __init sb1250_pcibios_init(void) void __iomem *io_map_base; uint32_t cmdreg; uint64_t reg; - extern int pci_probe_only; /* CFE will assign PCI resources */ pci_probe_only = 1; diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 301ff2f..d3be834 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -172,4 +172,7 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) return channel ? 15 : 14; } +extern int pci_probe_only; +extern unsigned int pcibios_max_latency; + #endif /* _ASM_PCI_H */ From ralf@linux-mips.org Fri Jul 4 12:56:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jul 2008 12:56:33 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:59308 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20177455AbYGDL4Z (ORCPT ); Fri, 4 Jul 2008 12:56:25 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m64BsZvR019412; Fri, 4 Jul 2008 13:55:00 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m64BsRO8019405; Fri, 4 Jul 2008 12:54:27 +0100 Date: Fri, 4 Jul 2008 12:54:27 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: ths@networkno.de, mlarsen@broadcom.com, linux-mips@linux-mips.org Subject: Re: Bug in atomic_sub_if_positive Message-ID: <20080704115427.GA992@linux-mips.org> References: <20080702095955.GA7007@networkno.de> <20080702.193133.211490377.nemoto@toshiba-tops.co.jp> <20080702105155.GC7007@networkno.de> <20080704.000426.39153587.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080704.000426.39153587.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19716 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 438 Lines: 17 On Fri, Jul 04, 2008 at 12:04:26AM +0900, Atsushi Nemoto wrote: > On Wed, 2 Jul 2008 11:51:55 +0100, Thiemo Seufer wrote: > > > The patch looks correct. > > > > Agreed. > > Ralf, too late for 2.6.26? Pull request to Linus is out. > Anyway I think it should go into -stable tree too. It is. This one is important. Heck, I don't get how a kernel can be as reliable as it was with an elefant like this :-) Ralf From mahendravarman15@gmail.com Fri Jul 4 15:28:41 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jul 2008 15:28:49 +0100 (BST) Received: from ug-out-1314.google.com ([66.249.92.172]:26306 "EHLO ug-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20187690AbYGDO2l (ORCPT ); Fri, 4 Jul 2008 15:28:41 +0100 Received: by ug-out-1314.google.com with SMTP id 30so802807ugs.39 for ; Fri, 04 Jul 2008 07:28:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:mime-version:content-type; bh=vnoxj2M3aERxE+9Vx5cee91J8rgOKu/w71znbcHLaak=; b=o5UCqdCHyUVEqD5F2aAGUhZTDh0GDoEnGs6PTa9rrv5mkMGkfnyG3ZoIDSBfD3hwj5 RwmAtUKPOO4XM3fK0iRqPkTAYpA8iYp7gW248dOUItvo9qr1Ti0AULFtUiRt5dllaDNx hiyxwJsGJKODRpXMXHmri8/SBRbeeZWnct+4w= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:mime-version:content-type; b=UOaK+dYLIpfUZauFGEZD/OVL2YJsuikc5KkKQnMfwZGIFAiMt2HN32UpDtKhyUPNzk Gozm+9J+jmReSBQJUtM13ozA5B2+ROlcFA8+rAXpFI3VglB1Hd2VDnFFa5XRU2s6VpQM P2ctfkTd4n3M6OptsdZtLTPpSKdTkxgfM4k0A= Received: by 10.67.32.7 with SMTP id k7mr2502097ugj.38.1215181717458; Fri, 04 Jul 2008 07:28:37 -0700 (PDT) Received: by 10.67.22.9 with HTTP; Fri, 4 Jul 2008 07:28:37 -0700 (PDT) Message-ID: <4ac2955e0807040728g54aeddccj684ea6a5ff6c6509@mail.gmail.com> Date: Fri, 4 Jul 2008 19:58:37 +0530 From: "mahendra varman" To: linuxppc-embedded@ozlabs.org., linux-kernel@vger.kernel.org, "linux-mips@linux-mips.org" Subject: cpc700-i2c driver in linux 2.6 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_10883_8576246.1215181717428" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19717 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mahendravarman15@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1009 Lines: 27 ------=_Part_10883_8576246.1215181717428 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi all Iam porting linux 2.6 in one of my board containing cpc700 system controller and ppc processor Iam using the spruce platform I could not find the cpc700-i2c file in linux 2.6 under drivers/i2c section If any of you already tried the above means plzz provide me the cpc700-i2c file in 2.6 Thanks in advance ------=_Part_10883_8576246.1215181717428 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi all

Iam porting linux 2.6 in one of my board containing cpc700 system controller and ppc processor
Iam using the spruce platform
I could not find the cpc700-i2c file in linux 2.6 under drivers/i2c section

If any of you already tried the above means plzz provide me the cpc700-i2c file in 2.6


Thanks in advance

------=_Part_10883_8576246.1215181717428-- From tsbogend@alpha.franken.de Fri Jul 4 23:51:18 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 04 Jul 2008 23:51:26 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:52696 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20212153AbYGDWvS (ORCPT ); Fri, 4 Jul 2008 23:51:18 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KEu7X-00017g-00 for linux-mips@linux-mips.org; Sat, 05 Jul 2008 00:51:15 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id CBCD51DA77A; Sat, 5 Jul 2008 00:51:06 +0200 (CEST) Date: Sat, 5 Jul 2008 00:51:06 +0200 To: linux-mips@linux-mips.org Subject: Re: SGI O2 sound driver v6 Message-ID: <20080704225106.GA7408@alpha.franken.de> References: <20080628000916.GA22049@alpha.franken.de> <20080628141336.GA17727@alpha.franken.de> <20080628224553.GA2064@alpha.franken.de> <20080629223537.GA697@alpha.franken.de> <20080702232118.GB18226@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20080702232118.GB18226@alpha.franken.de> User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19718 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 56199 Lines: 1914 On Thu, Jul 03, 2008 at 01:21:18AM +0200, Thomas Bogendoerfer wrote: > [...] changes in v6: - fixed mmap setup - capture is working now - reworked all mixer controls - added dma error interrupt - fixed button detection in input driver This is the final complete patch. I'm now going to split the patch into pieces for submission to the different maintainers. Thomas. arch/mips/sgi-ip32/ip32-platform.c | 36 ++ drivers/input/misc/Kconfig | 10 + drivers/input/misc/Makefile | 1 + drivers/input/misc/sgio2_btns.c | 154 ++++++ include/sound/ad1843.h | 46 ++ sound/mips/Kconfig | 6 + sound/mips/Makefile | 2 + sound/mips/ad1843.c | 539 +++++++++++++++++++ sound/mips/sgio2audio.c | 1013 ++++++++++++++++++++++++++++++++++++ 9 files changed, 1807 insertions(+), 0 deletions(-) diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c index 89a71f4..2ee401b 100644 --- a/arch/mips/sgi-ip32/ip32-platform.c +++ b/arch/mips/sgi-ip32/ip32-platform.c @@ -65,6 +65,42 @@ static __init int meth_devinit(void) device_initcall(meth_devinit); +static __init int sgio2audio_devinit(void) +{ + struct platform_device *pd; + int ret; + + pd = platform_device_alloc("sgio2audio", -1); + if (!pd) + return -ENOMEM; + + ret = platform_device_add(pd); + if (ret) + platform_device_put(pd); + + return ret; +} + +device_initcall(sgio2audio_devinit); + +static __init int sgio2btns_devinit(void) +{ + struct platform_device *pd; + int ret; + + pd = platform_device_alloc("sgio2btns", -1); + if (!pd) + return -ENOMEM; + + ret = platform_device_add(pd); + if (ret) + platform_device_put(pd); + + return ret; +} + +device_initcall(sgio2btns_devinit); + MODULE_AUTHOR("Ralf Baechle "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("8250 UART probe driver for SGI IP32 aka O2"); diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 432699d..e33d7cb 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -189,6 +189,16 @@ config INPUT_UINPUT To compile this driver as a module, choose M here: the module will be called uinput. +config INPUT_SGIO2_BTNS + tristate "SGI O2 volume button interface" + depends on SGI_IP32 + select INPUT_POLLDEV + help + Say Y here if you want to support SGI O2 volume button interface. + + To compile this driver as a module, choose M here: the + module will be called sgio_btns. + config HP_SDC_RTC tristate "HP SDC Real Time Clock" depends on GSC || HP300 diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index ebd39f2..0e274f1 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -19,3 +19,4 @@ obj-$(CONFIG_INPUT_YEALINK) += yealink.o obj-$(CONFIG_HP_SDC_RTC) += hp_sdc_rtc.o obj-$(CONFIG_INPUT_UINPUT) += uinput.o obj-$(CONFIG_INPUT_APANEL) += apanel.o +obj-$(CONFIG_INPUT_SGIO2_BTNS) += sgio2_btns.o diff --git a/drivers/input/misc/sgio2_btns.c b/drivers/input/misc/sgio2_btns.c new file mode 100644 index 0000000..5029873 --- /dev/null +++ b/drivers/input/misc/sgio2_btns.c @@ -0,0 +1,154 @@ +/* + * Cobalt button interface driver. + * + * Copyright (C) 2007-2008 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +#include + +#define BUTTONS_POLL_INTERVAL 30 /* msec */ +#define BUTTONS_COUNT_THRESHOLD 3 + +static const unsigned short sgio2_map[] = { + KEY_VOLUMEUP, + KEY_VOLUMEDOWN +}; + +struct buttons_dev { + struct input_polled_dev *poll_dev; + unsigned short keymap[ARRAY_SIZE(sgio2_map)]; + int count[ARRAY_SIZE(sgio2_map)]; + void __iomem *reg; +}; + +static void handle_buttons(struct input_polled_dev *dev) +{ + struct buttons_dev *bdev = dev->private; + struct input_dev *input = dev->input; + u64 status; + int i; + + status = (readq(&mace->perif.audio.control) >> 23) & 3; + + for (i = 0; i < ARRAY_SIZE(bdev->keymap); i++) { + if (status & (1U << i)) { + writeq(status & ~(1U << i), &mace->perif.audio.control); + if (++bdev->count[i] == BUTTONS_COUNT_THRESHOLD) { + input_event(input, EV_MSC, MSC_SCAN, i); + input_report_key(input, bdev->keymap[i], 1); + input_sync(input); + } + } else { + if (bdev->count[i] >= BUTTONS_COUNT_THRESHOLD) { + input_event(input, EV_MSC, MSC_SCAN, i); + input_report_key(input, bdev->keymap[i], 0); + input_sync(input); + } + bdev->count[i] = 0; + } + } +} + +static int __devinit sgio2_buttons_probe(struct platform_device *pdev) +{ + struct buttons_dev *bdev; + struct input_polled_dev *poll_dev; + struct input_dev *input; + int error, i; + + bdev = kzalloc(sizeof(struct buttons_dev), GFP_KERNEL); + poll_dev = input_allocate_polled_device(); + if (!bdev || !poll_dev) { + error = -ENOMEM; + goto err_free_mem; + } + + memcpy(bdev->keymap, sgio2_map, sizeof(bdev->keymap)); + + poll_dev->private = bdev; + poll_dev->poll = handle_buttons; + poll_dev->poll_interval = BUTTONS_POLL_INTERVAL; + + input = poll_dev->input; + input->name = "SGI O2 buttons"; + input->phys = "sgio2/input0"; + input->id.bustype = BUS_HOST; + input->dev.parent = &pdev->dev; + + input->keycode = bdev->keymap; + input->keycodemax = ARRAY_SIZE(bdev->keymap); + input->keycodesize = sizeof(unsigned short); + + input_set_capability(input, EV_MSC, MSC_SCAN); + __set_bit(EV_KEY, input->evbit); + for (i = 0; i < ARRAY_SIZE(sgio2_map); i++) + __set_bit(bdev->keymap[i], input->keybit); + __clear_bit(KEY_RESERVED, input->keybit); + + bdev->poll_dev = poll_dev; + dev_set_drvdata(&pdev->dev, bdev); + + error = input_register_polled_device(poll_dev); + if (!error) + return 0; + + err_free_mem: + input_free_polled_device(poll_dev); + kfree(bdev); + dev_set_drvdata(&pdev->dev, NULL); + return error; +} + +static int __devexit sgio2_buttons_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct buttons_dev *bdev = dev_get_drvdata(dev); + + input_unregister_polled_device(bdev->poll_dev); + input_free_polled_device(bdev->poll_dev); + kfree(bdev); + dev_set_drvdata(dev, NULL); + + return 0; +} + +static struct platform_driver sgio2_buttons_driver = { + .probe = sgio2_buttons_probe, + .remove = __devexit_p(sgio2_buttons_remove), + .driver = { + .name = "sgio2btns", + .owner = THIS_MODULE, + }, +}; + +static int __init sgio2_buttons_init(void) +{ + return platform_driver_register(&sgio2_buttons_driver); +} + +static void __exit sgio2_buttons_exit(void) +{ + platform_driver_unregister(&sgio2_buttons_driver); +} + +module_init(sgio2_buttons_init); +module_exit(sgio2_buttons_exit); diff --git a/include/sound/ad1843.h b/include/sound/ad1843.h new file mode 100644 index 0000000..b236a9d --- /dev/null +++ b/include/sound/ad1843.h @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright 2003 Vivien Chappelier + * Copyright 2008 Thomas Bogendoerfer + */ + +#ifndef __SOUND_AD1843_H +#define __SOUND_AD1843_H + +struct snd_ad1843 { + void *chip; + int (*read)(void *chip, int reg); + int (*write)(void *chip, int reg, int val); +}; + +#define AD1843_GAIN_RECLEV 0 +#define AD1843_GAIN_LINE 1 +#define AD1843_GAIN_LINE_2 2 +#define AD1843_GAIN_MIC 3 +#define AD1843_GAIN_PCM_0 4 +#define AD1843_GAIN_PCM_1 5 +#define AD1843_GAIN_SIZE (AD1843_GAIN_PCM_1+1) + +int ad1843_get_gain_max(struct snd_ad1843 *ad1843, int id); +int ad1843_get_gain(struct snd_ad1843 *ad1843, int id); +int ad1843_set_gain(struct snd_ad1843 *ad1843, int id, int newval); +int ad1843_get_recsrc(struct snd_ad1843 *ad1843); +int ad1843_set_recsrc(struct snd_ad1843 *ad1843, int newsrc); +void ad1843_setup_dac(struct snd_ad1843 *ad1843, + unsigned int id, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels); +void ad1843_shutdown_dac(struct snd_ad1843 *ad1843, + unsigned int id); +void ad1843_setup_adc(struct snd_ad1843 *ad1843, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels); +void ad1843_shutdown_adc(struct snd_ad1843 *ad1843); +int ad1843_init(struct snd_ad1843 *ad1843); + +#endif /* __SOUND_AD1843_H */ diff --git a/sound/mips/Kconfig b/sound/mips/Kconfig index 531f8ba..a3e202e 100644 --- a/sound/mips/Kconfig +++ b/sound/mips/Kconfig @@ -11,5 +11,11 @@ config SND_AU1X00 help ALSA Sound driver for the Au1x00's AC97 port. +config SND_SGI_O2 + tristate "SGI O2 Audio" + depends on SND && SGI_IP32 + help + Sound support for the SGI O2 Workstation. + endmenu diff --git a/sound/mips/Makefile b/sound/mips/Makefile index 47afed9..55624d8 100644 --- a/sound/mips/Makefile +++ b/sound/mips/Makefile @@ -2,7 +2,9 @@ # Makefile for ALSA # +snd-sgi-o2-objs := sgio2audio.o ad1843.o snd-au1x00-objs := au1x00.o # Toplevel Module Dependency obj-$(CONFIG_SND_AU1X00) += snd-au1x00.o +obj-$(CONFIG_SND_SGI_O2) += snd-sgi-o2.o diff --git a/sound/mips/ad1843.c b/sound/mips/ad1843.c new file mode 100644 index 0000000..76bdf68 --- /dev/null +++ b/sound/mips/ad1843.c @@ -0,0 +1,539 @@ +/* + * AD1843 low level driver + * + * Copyright 2003 Vivien Chappelier + * Copyright 2008 Thomas Bogendoerfer + * + * inspired from vwsnd.c (SGI VW audio driver) + * Copyright 1999 Silicon Graphics, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +/* + * AD1843 bitfield definitions. All are named as in the AD1843 data + * sheet, with ad1843_ prepended and individual bit numbers removed. + * + * E.g., bits LSS0 through LSS2 become ad1843_LSS. + * + * Only the bitfields we need are defined. + */ + +struct ad1843_bitfield { + char reg; + char lo_bit; + char nbits; +}; + +static const struct ad1843_bitfield + ad1843_PDNO = { 0, 14, 1 }, /* Converter Power-Down Flag */ + ad1843_INIT = { 0, 15, 1 }, /* Clock Initialization Flag */ + ad1843_RIG = { 2, 0, 4 }, /* Right ADC Input Gain */ + ad1843_RMGE = { 2, 4, 1 }, /* Right ADC Mic Gain Enable */ + ad1843_RSS = { 2, 5, 3 }, /* Right ADC Source Select */ + ad1843_LIG = { 2, 8, 4 }, /* Left ADC Input Gain */ + ad1843_LMGE = { 2, 12, 1 }, /* Left ADC Mic Gain Enable */ + ad1843_LSS = { 2, 13, 3 }, /* Left ADC Source Select */ + ad1843_RD2M = { 3, 0, 5 }, /* Right DAC 2 Mix Gain/Atten */ + ad1843_RD2MM = { 3, 7, 1 }, /* Right DAC 2 Mix Mute */ + ad1843_LD2M = { 3, 8, 5 }, /* Left DAC 2 Mix Gain/Atten */ + ad1843_LD2MM = { 3, 15, 1 }, /* Left DAC 2 Mix Mute */ + ad1843_RX1M = { 4, 0, 5 }, /* Right Aux 1 Mix Gain/Atten */ + ad1843_RX1MM = { 4, 7, 1 }, /* Right Aux 1 Mix Mute */ + ad1843_LX1M = { 4, 8, 5 }, /* Left Aux 1 Mix Gain/Atten */ + ad1843_LX1MM = { 4, 15, 1 }, /* Left Aux 1 Mix Mute */ + ad1843_RX2M = { 5, 0, 5 }, /* Right Aux 2 Mix Gain/Atten */ + ad1843_RX2MM = { 5, 7, 1 }, /* Right Aux 2 Mix Mute */ + ad1843_LX2M = { 5, 8, 5 }, /* Left Aux 2 Mix Gain/Atten */ + ad1843_LX2MM = { 5, 15, 1 }, /* Left Aux 2 Mix Mute */ + ad1843_RMCM = { 7, 0, 5 }, /* Right Mic Mix Gain/Atten */ + ad1843_RMCMM = { 7, 7, 1 }, /* Right Mic Mix Mute */ + ad1843_LMCM = { 7, 8, 5 }, /* Left Mic Mix Gain/Atten */ + ad1843_LMCMM = { 7, 15, 1 }, /* Left Mic Mix Mute */ + ad1843_HPOS = { 8, 4, 1 }, /* Headphone Output Voltage Swing */ + ad1843_HPOM = { 8, 5, 1 }, /* Headphone Output Mute */ + ad1843_MPOM = { 8, 6, 1 }, /* Mono Output Mute */ + ad1843_RDA1G = { 9, 0, 6 }, /* Right DAC1 Analog/Digital Gain */ + ad1843_RDA1GM = { 9, 7, 1 }, /* Right DAC1 Analog Mute */ + ad1843_LDA1G = { 9, 8, 6 }, /* Left DAC1 Analog/Digital Gain */ + ad1843_LDA1GM = { 9, 15, 1 }, /* Left DAC1 Analog Mute */ + ad1843_RDA2G = { 10, 0, 6 }, /* Right DAC2 Analog/Digital Gain */ + ad1843_RDA2GM = { 10, 7, 1 }, /* Right DAC2 Analog Mute */ + ad1843_LDA2G = { 10, 8, 6 }, /* Left DAC2 Analog/Digital Gain */ + ad1843_LDA2GM = { 10, 15, 1 }, /* Left DAC2 Analog Mute */ + ad1843_RDA1AM = { 11, 7, 1 }, /* Right DAC1 Digital Mute */ + ad1843_LDA1AM = { 11, 15, 1 }, /* Left DAC1 Digital Mute */ + ad1843_RDA2AM = { 12, 7, 1 }, /* Right DAC2 Digital Mute */ + ad1843_LDA2AM = { 12, 15, 1 }, /* Left DAC2 Digital Mute */ + ad1843_ADLC = { 15, 0, 2 }, /* ADC Left Sample Rate Source */ + ad1843_ADRC = { 15, 2, 2 }, /* ADC Right Sample Rate Source */ + ad1843_DA1C = { 15, 8, 2 }, /* DAC1 Sample Rate Source */ + ad1843_DA2C = { 15, 10, 2 }, /* DAC2 Sample Rate Source */ + ad1843_C1C = { 17, 0, 16 }, /* Clock 1 Sample Rate Select */ + ad1843_C2C = { 20, 0, 16 }, /* Clock 2 Sample Rate Select */ + ad1843_C3C = { 23, 0, 16 }, /* Clock 3 Sample Rate Select */ + ad1843_DAADL = { 25, 4, 2 }, /* Digital ADC Left Source Select */ + ad1843_DAADR = { 25, 6, 2 }, /* Digital ADC Right Source Select */ + ad1843_DAMIX = { 25, 14, 1 }, /* DAC Digital Mix Enable */ + ad1843_DRSFLT = { 25, 15, 1 }, /* Digital Reampler Filter Mode */ + ad1843_ADLF = { 26, 0, 2 }, /* ADC Left Channel Data Format */ + ad1843_ADRF = { 26, 2, 2 }, /* ADC Right Channel Data Format */ + ad1843_ADTLK = { 26, 4, 1 }, /* ADC Transmit Lock Mode Select */ + ad1843_SCF = { 26, 7, 1 }, /* SCLK Frequency Select */ + ad1843_DA1F = { 26, 8, 2 }, /* DAC1 Data Format Select */ + ad1843_DA2F = { 26, 10, 2 }, /* DAC2 Data Format Select */ + ad1843_DA1SM = { 26, 14, 1 }, /* DAC1 Stereo/Mono Mode Select */ + ad1843_DA2SM = { 26, 15, 1 }, /* DAC2 Stereo/Mono Mode Select */ + ad1843_ADLEN = { 27, 0, 1 }, /* ADC Left Channel Enable */ + ad1843_ADREN = { 27, 1, 1 }, /* ADC Right Channel Enable */ + ad1843_AAMEN = { 27, 4, 1 }, /* Analog to Analog Mix Enable */ + ad1843_ANAEN = { 27, 7, 1 }, /* Analog Channel Enable */ + ad1843_DA1EN = { 27, 8, 1 }, /* DAC1 Enable */ + ad1843_DA2EN = { 27, 9, 1 }, /* DAC2 Enable */ + ad1843_DDMEN = { 27, 12, 1 }, /* DAC2 to DAC1 Mix Enable */ + ad1843_C1EN = { 28, 11, 1 }, /* Clock Generator 1 Enable */ + ad1843_C2EN = { 28, 12, 1 }, /* Clock Generator 2 Enable */ + ad1843_C3EN = { 28, 13, 1 }, /* Clock Generator 3 Enable */ + ad1843_PDNI = { 28, 15, 1 }; /* Converter Power Down */ + +/* + * The various registers of the AD1843 use three different formats for + * specifying gain. The ad1843_gain structure parameterizes the + * formats. + */ + +struct ad1843_gain { + int negative; /* nonzero if gain is negative. */ + const struct ad1843_bitfield *lfield; + const struct ad1843_bitfield *rfield; + const struct ad1843_bitfield *lmute; + const struct ad1843_bitfield *rmute; +}; + +const struct ad1843_gain ad1843_gain_RECLEV = { + 0, &ad1843_LIG, &ad1843_RIG +}; +const struct ad1843_gain ad1843_gain_LINE = { + 1, &ad1843_LX1M, &ad1843_RX1M, &ad1843_LX1MM, &ad1843_RX1MM +}; +const struct ad1843_gain ad1843_gain_LINE_2 = { + 1, &ad1843_LDA2G, &ad1843_RDA2G, &ad1843_LDA2GM, &ad1843_RDA2GM +}; +const struct ad1843_gain ad1843_gain_MIC = { + 1, &ad1843_LMCM, &ad1843_RMCM, &ad1843_LMCMM, &ad1843_RMCMM +}; +const struct ad1843_gain ad1843_gain_PCM_0 = { + 1, &ad1843_LDA1G, &ad1843_RDA1G, &ad1843_LDA1GM, &ad1843_RDA1GM +}; +const struct ad1843_gain ad1843_gain_PCM_1 = { + 1, &ad1843_LD2M, &ad1843_RD2M, &ad1843_LD2MM, &ad1843_RD2MM +}; + +const struct ad1843_gain *ad1843_gain[AD1843_GAIN_SIZE] = +{ + &ad1843_gain_RECLEV, + &ad1843_gain_LINE, + &ad1843_gain_LINE_2, + &ad1843_gain_MIC, + &ad1843_gain_PCM_0, + &ad1843_gain_PCM_1, +}; + +/* read the current value of an AD1843 bitfield. */ + +static int ad1843_read_bits(struct snd_ad1843 *ad1843, + const struct ad1843_bitfield *field) +{ + int w; + + w = ad1843->read(ad1843->chip, field->reg); + return w >> field->lo_bit & ((1 << field->nbits) - 1); +} + +/* + * write a new value to an AD1843 bitfield and return the old value. + */ + +static int ad1843_write_bits(struct snd_ad1843 *ad1843, + const struct ad1843_bitfield *field, + int newval) +{ + int w, mask, oldval, newbits; + + w = ad1843->read(ad1843->chip, field->reg); + mask = ((1 << field->nbits) - 1) << field->lo_bit; + oldval = (w & mask) >> field->lo_bit; + newbits = (newval << field->lo_bit) & mask; + w = (w & ~mask) | newbits; + ad1843->write(ad1843->chip, field->reg, w); + + return oldval; +} + +/* + * ad1843_read_multi reads multiple bitfields from the same AD1843 + * register. It uses a single read cycle to do it. (Reading the + * ad1843 requires 256 bit times at 12.288 MHz, or nearly 20 + * microseconds.) + * + * Called like this. + * + * ad1843_read_multi(ad1843, nfields, + * &ad1843_FIELD1, &val1, + * &ad1843_FIELD2, &val2, ...); + */ + +static void ad1843_read_multi(struct snd_ad1843 *ad1843, int argcount, ...) +{ + va_list ap; + const struct ad1843_bitfield *fp; + int w = 0, mask, *value, reg = -1; + + va_start(ap, argcount); + while (--argcount >= 0) { + fp = va_arg(ap, const struct ad1843_bitfield *); + value = va_arg(ap, int *); + if (reg == -1) { + reg = fp->reg; + w = ad1843->read(ad1843->chip, reg); + } + + mask = (1 << fp->nbits) - 1; + *value = w >> fp->lo_bit & mask; + } + va_end(ap); +} + +/* + * ad1843_write_multi stores multiple bitfields into the same AD1843 + * register. It uses one read and one write cycle to do it. + * + * Called like this. + * + * ad1843_write_multi(ad1843, nfields, + * &ad1843_FIELD1, val1, + * &ad1843_FIELF2, val2, ...); + */ + +static void ad1843_write_multi(struct snd_ad1843 *ad1843, int argcount, ...) +{ + va_list ap; + int reg; + const struct ad1843_bitfield *fp; + int value; + int w, m, mask, bits; + + mask = 0; + bits = 0; + reg = -1; + + va_start(ap, argcount); + while (--argcount >= 0) { + fp = va_arg(ap, const struct ad1843_bitfield *); + value = va_arg(ap, int); + if (reg == -1) + reg = fp->reg; + else + BUG_ON(reg != fp->reg); + m = ((1 << fp->nbits) - 1) << fp->lo_bit; + mask |= m; + bits |= (value << fp->lo_bit) & m; + } + va_end(ap); + + if (~mask & 0xFFFF) + w = ad1843->read(ad1843->chip, reg); + else + w = 0; + w = (w & ~mask) | bits; + ad1843->write(ad1843->chip, reg, w); +} + +int ad1843_get_gain_max(struct snd_ad1843 *ad1843, int id) +{ + const struct ad1843_gain *gp = ad1843_gain[id]; + int ret; + + ret = (1 << gp->lfield->nbits); + if (!gp->lmute) + ret -= 1; + return ret; +} + +/* + * ad1843_get_gain reads the specified register and extracts the gain value + * using the supplied gain type. + */ + +int ad1843_get_gain(struct snd_ad1843 *ad1843, int id) +{ + int lg, rg, lm, rm; + const struct ad1843_gain *gp = ad1843_gain[id]; + unsigned short mask = (1 << gp->lfield->nbits) - 1; + + ad1843_read_multi(ad1843, 2, gp->lfield, &lg, gp->rfield, &rg); + if (gp->negative) { + lg = mask - lg; + rg = mask - rg; + } + if (gp->lmute) { + ad1843_read_multi(ad1843, 2, gp->lmute, &lm, gp->rmute, &rm); + if (lm) + lg = 0; + if (rm) + rg = 0; + } + return lg << 0 | rg << 8; +} + +/* + * Set an audio channel's gain. + * + * Returns the new gain, which may be lower than the old gain. + */ + +int ad1843_set_gain(struct snd_ad1843 *ad1843, int id, int newval) +{ + const struct ad1843_gain *gp = ad1843_gain[id]; + unsigned short mask = (1 << gp->lfield->nbits) - 1; + + int lg = (newval >> 0) & mask; + int rg = (newval >> 8) & mask; + int lm = (lg == 0) ? 1 : 0; + int rm = (rg == 0) ? 1 : 0; + + if (gp->negative) { + lg = mask - lg; + rg = mask - rg; + } + if (gp->lmute) + ad1843_write_multi(ad1843, 2, gp->lmute, lm, gp->rmute, rm); + ad1843_write_multi(ad1843, 2, gp->lfield, lg, gp->rfield, rg); + return ad1843_get_gain(ad1843, id); +} + +/* Returns the current recording source */ + +int ad1843_get_recsrc(struct snd_ad1843 *ad1843) +{ + int val = ad1843_read_bits(ad1843, &ad1843_LSS); + + if (val < 0 || val > 2) { + val = 2; + ad1843_write_multi(ad1843, 2, + &ad1843_LSS, val, &ad1843_RSS, val); + } + return val; +} + +/* + * Set recording source. + * + * Returns newsrc on success, -errno on failure. + */ + +int ad1843_set_recsrc(struct snd_ad1843 *ad1843, int newsrc) +{ + if (newsrc < 0 || newsrc > 2) + return -EINVAL; + + ad1843_write_multi(ad1843, 2, &ad1843_LSS, newsrc, &ad1843_RSS, newsrc); + return newsrc; +} + +/* Setup ad1843 for D/A conversion. */ + +void ad1843_setup_dac(struct snd_ad1843 *ad1843, + unsigned int id, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels) +{ + int ad_fmt = 0, ad_mode = 0; + + switch (fmt) { + case SNDRV_PCM_FORMAT_S8: + ad_fmt = 0; + break; + case SNDRV_PCM_FORMAT_U8: + ad_fmt = 0; + break; + case SNDRV_PCM_FORMAT_S16_LE: + ad_fmt = 1; + break; + case SNDRV_PCM_FORMAT_MU_LAW: + ad_fmt = 2; + break; + case SNDRV_PCM_FORMAT_A_LAW: + ad_fmt = 3; + break; + default: + break; + } + + switch (channels) { + case 2: + ad_mode = 0; + break; + case 1: + ad_mode = 1; + break; + default: + break; + } + + if (id) { + ad1843_write_bits(ad1843, &ad1843_C2C, framerate); + ad1843_write_multi(ad1843, 2, + &ad1843_DA2SM, ad_mode, + &ad1843_DA2F, ad_fmt); + } else { + ad1843_write_bits(ad1843, &ad1843_C1C, framerate); + ad1843_write_multi(ad1843, 2, + &ad1843_DA1SM, ad_mode, + &ad1843_DA1F, ad_fmt); + } +} + +void ad1843_shutdown_dac(struct snd_ad1843 *ad1843, unsigned int id) +{ + if (id) + ad1843_write_bits(ad1843, &ad1843_DA2F, 1); + else + ad1843_write_bits(ad1843, &ad1843_DA1F, 1); +} + +void ad1843_setup_adc(struct snd_ad1843 *ad1843, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels) +{ + int da_fmt = 0; + + switch (fmt) { + case SNDRV_PCM_FORMAT_S8: da_fmt = 0; break; + case SNDRV_PCM_FORMAT_U8: da_fmt = 0; break; + case SNDRV_PCM_FORMAT_S16_LE: da_fmt = 1; break; + case SNDRV_PCM_FORMAT_MU_LAW: da_fmt = 2; break; + case SNDRV_PCM_FORMAT_A_LAW: da_fmt = 3; break; + default: break; + } + + ad1843_write_bits(ad1843, &ad1843_C3C, framerate); + ad1843_write_multi(ad1843, 2, + &ad1843_ADLF, da_fmt, &ad1843_ADRF, da_fmt); +} + +void ad1843_shutdown_adc(struct snd_ad1843 *ad1843) +{ + /* nothing to do */ +} + +/* + * Fully initialize the ad1843. As described in the AD1843 data + * sheet, section "START-UP SEQUENCE". The numbered comments are + * subsection headings from the data sheet. See the data sheet, pages + * 52-54, for more info. + * + * return 0 on success, -errno on failure. */ + +int ad1843_init(struct snd_ad1843 *ad1843) +{ + unsigned long later; + + if (ad1843_read_bits(ad1843, &ad1843_INIT) != 0) { + printk(KERN_ERR "ad1843: AD1843 won't initialize\n"); + return -EIO; + } + + ad1843_write_bits(ad1843, &ad1843_SCF, 1); + + /* 4. Put the conversion resources into standby. */ + ad1843_write_bits(ad1843, &ad1843_PDNI, 0); + later = jiffies + HZ / 2; /* roughly half a second */ + + while (ad1843_read_bits(ad1843, &ad1843_PDNO)) { + if (time_after(jiffies, later)) { + printk(KERN_ERR + "ad1843: AD1843 won't power up\n"); + return -EIO; + } + schedule(); + } + + /* 5. Power up the clock generators and enable clock output pins. */ + ad1843_write_multi(ad1843, 3, + &ad1843_C1EN, 1, + &ad1843_C2EN, 1, + &ad1843_C3EN, 1); + + /* 6. Configure conversion resources while they are in standby. */ + + /* DAC1/2 use clock 1/2 as source, ADC uses clock 3. Always. */ + ad1843_write_multi(ad1843, 4, + &ad1843_DA1C, 1, + &ad1843_DA2C, 2, + &ad1843_ADLC, 3, + &ad1843_ADRC, 3); + + /* 7. Enable conversion resources. */ + ad1843_write_bits(ad1843, &ad1843_ADTLK, 1); + ad1843_write_multi(ad1843, 7, + &ad1843_ANAEN, 1, + &ad1843_AAMEN, 1, + &ad1843_DA1EN, 1, + &ad1843_DA2EN, 1, + &ad1843_DDMEN, 1, + &ad1843_ADLEN, 1, + &ad1843_ADREN, 1); + + /* 8. Configure conversion resources while they are enabled. */ + + /* set gain to 0 for all channels */ + ad1843_set_gain(ad1843, AD1843_GAIN_RECLEV, 0); + ad1843_set_gain(ad1843, AD1843_GAIN_LINE, 0); + ad1843_set_gain(ad1843, AD1843_GAIN_LINE_2, 0); + ad1843_set_gain(ad1843, AD1843_GAIN_MIC, 0); + ad1843_set_gain(ad1843, AD1843_GAIN_PCM_0, 0); + ad1843_set_gain(ad1843, AD1843_GAIN_PCM_1, 0); + + /* Unmute all channels. */ + /* DAC1 */ + ad1843_write_multi(ad1843, 2, &ad1843_LDA1GM, 0, &ad1843_RDA1GM, 0); + /* DAC2 */ + ad1843_write_multi(ad1843, 2, &ad1843_LDA2GM, 0, &ad1843_RDA2GM, 0); + + /* Set default recording source to Line In and set + * mic gain to +20 dB. + */ + ad1843_set_recsrc(ad1843, 2); + ad1843_write_multi(ad1843, 2, &ad1843_LMGE, 1, &ad1843_RMGE, 1); + + /* Set Speaker Out level to +/- 4V and unmute it. */ + ad1843_write_multi(ad1843, 3, + &ad1843_HPOS, 1, + &ad1843_HPOM, 0, + &ad1843_MPOM, 0); + + return 0; +} diff --git a/sound/mips/sgio2audio.c b/sound/mips/sgio2audio.c new file mode 100644 index 0000000..6630af3 --- /dev/null +++ b/sound/mips/sgio2audio.c @@ -0,0 +1,1013 @@ +/* + * Sound driver for Silicon Graphics O2 Workstations A/V board audio. + * + * Copyright 2003 Vivien Chappelier + * Copyright 2008 Thomas Bogendoerfer + * Mxier part taken from mace_audio.c: + * Copyright 2007 Thorben Jändling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#define SNDRV_GET_ID +#include +#include + + +MODULE_AUTHOR("Vivien Chappelier "); +MODULE_DESCRIPTION("SGI O2 Audio"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("{{Silicon Graphics, O2 Audio}}"); + +static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ +static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ + +module_param(index, int, 0444); +MODULE_PARM_DESC(index, "Index value for SGI O2 soundcard."); +module_param(id, charp, 0444); +MODULE_PARM_DESC(id, "ID string for SGI O2 soundcard."); + + +#define SGIO2AUDIO_MAX_VOLUME 31 + +#define AUDIO_CONTROL_RESET BIT(0) /* 1: reset audio interface */ +#define AUDIO_CONTROL_CODEC_PRESENT BIT(1) /* 1: codec detected */ + +#define CODEC_CONTROL_WORD_SHIFT 0 +#define CODEC_CONTROL_READ BIT(16) +#define CODEC_CONTROL_ADDRESS_SHIFT 17 + +#define CHANNEL_CONTROL_RESET BIT(10) /* 1: reset channel */ +#define CHANNEL_DMA_ENABLE BIT(9) /* 1: enable DMA transfer */ +#define CHANNEL_INT_THRESHOLD_DISABLED (0 << 5) /* interrupt disabled */ +#define CHANNEL_INT_THRESHOLD_25 (1 << 5) /* int on buffer >25% full */ +#define CHANNEL_INT_THRESHOLD_50 (2 << 5) /* int on buffer >50% full */ +#define CHANNEL_INT_THRESHOLD_75 (3 << 5) /* int on buffer >75% full */ +#define CHANNEL_INT_THRESHOLD_EMPTY (4 << 5) /* int on buffer empty */ +#define CHANNEL_INT_THRESHOLD_NOT_EMPTY (5 << 5) /* int on buffer !empty */ +#define CHANNEL_INT_THRESHOLD_FULL (6 << 5) /* int on buffer empty */ +#define CHANNEL_INT_THRESHOLD_NOT_FULL (7 << 5) /* int on buffer !empty */ + +#define CHANNEL_RING_SHIFT 12 +#define CHANNEL_RING_SIZE (1 << CHANNEL_RING_SHIFT) +#define CHANNEL_RING_MASK (CHANNEL_RING_SIZE - 1) + +#define CHANNEL_LEFT_SHIFT 40 +#define CHANNEL_RIGHT_SHIFT 8 + +struct snd_sgio2audio_chan { + int idx; + struct snd_pcm_substream *substream; + int pos; + snd_pcm_uframes_t size; + spinlock_t lock; +}; + +/* definition of the chip-specific record */ +struct snd_sgio2audio { + struct snd_card *card; + + /* codec */ + struct snd_ad1843 ad1843; + spinlock_t ad1843_lock; + + /* channels */ + struct snd_sgio2audio_chan channel[3]; + + /* properties */ + int volume; + + /* resources */ + void *ring_base; + dma_addr_t ring_base_dma; +}; + +/* AD1843 access */ + +/* + * read_ad1843_reg returns the current contents of a 16 bit AD1843 register. + * + * Returns unsigned register value on success, -errno on failure. + */ +static int read_ad1843_reg(void *priv, int reg) +{ + struct snd_sgio2audio *chip = priv; + int val; + unsigned long flags; + + spin_lock_irqsave(&chip->ad1843_lock, flags); + + writeq((reg << CODEC_CONTROL_ADDRESS_SHIFT) | + CODEC_CONTROL_READ, &mace->perif.audio.codec_control); + wmb(); + val = readq(&mace->perif.audio.codec_control); /* flush bus */ + udelay(200); + + val = readq(&mace->perif.audio.codec_read); + + spin_unlock_irqrestore(&chip->ad1843_lock, flags); + return val; +} + +/* + * write_ad1843_reg writes the specified value to a 16 bit AD1843 register. + */ +static int write_ad1843_reg(void *priv, int reg, int word) +{ + struct snd_sgio2audio *chip = priv; + int val; + unsigned long flags; + + spin_lock_irqsave(&chip->ad1843_lock, flags); + + writeq((reg << CODEC_CONTROL_ADDRESS_SHIFT) | + (word << CODEC_CONTROL_WORD_SHIFT), + &mace->perif.audio.codec_control); + wmb(); + val = readq(&mace->perif.audio.codec_control); /* flush bus */ + udelay(200); + + spin_unlock_irqrestore(&chip->ad1843_lock, flags); + return 0; +} + +static int sgio2audio_gain_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct snd_sgio2audio *chip = snd_kcontrol_chip(kcontrol); + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 2; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = ad1843_get_gain_max(&chip->ad1843, + (int)kcontrol->private_value); + return 0; +} + +static int sgio2audio_gain_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_sgio2audio *chip = snd_kcontrol_chip(kcontrol); + int vol; + + vol = ad1843_get_gain(&chip->ad1843, (int)kcontrol->private_value); + + ucontrol->value.integer.value[0] = (vol >> 8) & 0xFF; + ucontrol->value.integer.value[1] = vol & 0xFF; + + return 0; +} + +static int sgio2audio_gain_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_sgio2audio *chip = snd_kcontrol_chip(kcontrol); + int newvol, oldvol; + + oldvol = ad1843_get_gain(&chip->ad1843, kcontrol->private_value); + newvol = (ucontrol->value.integer.value[0] << 8) | + ucontrol->value.integer.value[1]; + + newvol = ad1843_set_gain(&chip->ad1843, kcontrol->private_value, + newvol); + + return newvol != oldvol; +} + +static int sgio2audio_source_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + static const char *texts[3] = { + "Cam Mic", "Mic", "Line" + }; + uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; + uinfo->count = 1; + uinfo->value.enumerated.items = 3; + if (uinfo->value.enumerated.item >= 3) + uinfo->value.enumerated.item = 1; + strcpy(uinfo->value.enumerated.name, + texts[uinfo->value.enumerated.item]); + return 0; +} + +static int sgio2audio_source_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_sgio2audio *chip = snd_kcontrol_chip(kcontrol); + + ucontrol->value.enumerated.item[0] = ad1843_get_recsrc(&chip->ad1843); + return 0; +} + +static int sgio2audio_source_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_sgio2audio *chip = snd_kcontrol_chip(kcontrol); + int newsrc, oldsrc; + + oldsrc = ad1843_get_recsrc(&chip->ad1843); + newsrc = ad1843_set_recsrc(&chip->ad1843, + ucontrol->value.enumerated.item[0]); + + return newsrc != oldsrc; +} + +/* dac1/pcm0 mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_pcm0 __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "PCM Playback Volume", + .index = 0, + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_PCM_0, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + +/* dac2/pcm1 mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_pcm1 __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "PCM Playback Volume", + .index = 1, + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_PCM_1, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + +/* record level mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_reclevel __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Capture Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_RECLEV, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + +/* record level source control */ +static struct snd_kcontrol_new sgio2audio_ctrl_recsource __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Capture Source", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .info = sgio2audio_source_info, + .get = sgio2audio_source_get, + .put = sgio2audio_source_put, +}; + +/* line mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_line __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Line Playback Volume", + .index = 0, + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_LINE, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + +/* cd mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_cd __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Line Playback Volume", + .index = 1, + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_LINE_2, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + +/* mic mixer control */ +static struct snd_kcontrol_new sgio2audio_ctrl_mic __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Mic Playback Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .private_value = AD1843_GAIN_MIC, + .info = sgio2audio_gain_info, + .get = sgio2audio_gain_get, + .put = sgio2audio_gain_put, +}; + + +static int __devinit snd_sgio2audio_new_mixer(struct snd_sgio2audio *chip) +{ + int err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_pcm0, chip)); + if (err < 0) + return err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_pcm1, chip)); + if (err < 0) + return err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_reclevel, chip)); + if (err < 0) + return err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_recsource, chip)); + if (err < 0) + return err; + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_line, chip)); + if (err < 0) + return err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_cd, chip)); + if (err < 0) + return err; + + err = snd_ctl_add(chip->card, + snd_ctl_new1(&sgio2audio_ctrl_mic, chip)); + if (err < 0) + return err; + + return 0; +} + +/* low-level audio interface DMA */ + +/* get data out of bounce buffer, count must be a multiple of 32 */ +/* returns 1 if a period has elapsed */ +static int snd_sgio2audio_dma_pull_frag(struct snd_sgio2audio *chip, + unsigned int ch, unsigned int count) +{ + int ret; + unsigned long src_base, src_pos, dst_mask; + unsigned char *dst_base; + int dst_pos; + u64 *src; + s16 *dst; + u64 x; + unsigned long flags; + struct snd_pcm_runtime *runtime = chip->channel[ch].substream->runtime; + + spin_lock_irqsave(&chip->channel[ch].lock, flags); + + src_base = (unsigned long) chip->ring_base | (ch << CHANNEL_RING_SHIFT); + src_pos = readq(&mace->perif.audio.chan[ch].read_ptr); + dst_base = runtime->dma_area; + dst_pos = chip->channel[ch].pos; + dst_mask = frames_to_bytes(runtime, runtime->buffer_size) - 1; + + /* check if a period has elapsed */ + chip->channel[ch].size += (count >> 3); /* in frames */ + ret = chip->channel[ch].size >= runtime->period_size; + chip->channel[ch].size %= runtime->period_size; + + while (count) { + src = (u64 *)(src_base + src_pos); + dst = (s16 *)(dst_base + dst_pos); + + x = *src; + dst[0] = (x >> CHANNEL_LEFT_SHIFT) & 0xffff; + dst[1] = (x >> CHANNEL_RIGHT_SHIFT) & 0xffff; + + src_pos = (src_pos + sizeof(u64)) & CHANNEL_RING_MASK; + dst_pos = (dst_pos + 2 * sizeof(s16)) & dst_mask; + count -= sizeof(u64); + } + + writeq(src_pos, &mace->perif.audio.chan[ch].read_ptr); /* in bytes */ + chip->channel[ch].pos = dst_pos; + + spin_unlock_irqrestore(&chip->channel[ch].lock, flags); + return ret; +} + +/* put some DMA data in bounce buffer, count must be a multiple of 32 */ +/* returns 1 if a period has elapsed */ +static int snd_sgio2audio_dma_push_frag(struct snd_sgio2audio *chip, + unsigned int ch, unsigned int count) +{ + int ret; + s64 l, r; + unsigned long dst_base, dst_pos, src_mask; + unsigned char *src_base; + int src_pos; + u64 *dst; + s16 *src; + unsigned long flags; + struct snd_pcm_runtime *runtime = chip->channel[ch].substream->runtime; + + spin_lock_irqsave(&chip->channel[ch].lock, flags); + + dst_base = (unsigned long)chip->ring_base | (ch << CHANNEL_RING_SHIFT); + dst_pos = readq(&mace->perif.audio.chan[ch].write_ptr); + src_base = runtime->dma_area; + src_pos = chip->channel[ch].pos; + src_mask = frames_to_bytes(runtime, runtime->buffer_size) - 1; + + /* check if a period has elapsed */ + chip->channel[ch].size += (count >> 3); /* in frames */ + ret = chip->channel[ch].size >= runtime->period_size; + chip->channel[ch].size %= runtime->period_size; + + while (count) { + src = (s16 *)(src_base + src_pos); + dst = (u64 *)(dst_base + dst_pos); + + l = src[0]; /* sign extend */ + r = src[1]; /* sign extend */ + + *dst = ((l & 0x00ffffff) << CHANNEL_LEFT_SHIFT) | + ((r & 0x00ffffff) << CHANNEL_RIGHT_SHIFT); + + dst_pos = (dst_pos + sizeof(u64)) & CHANNEL_RING_MASK; + src_pos = (src_pos + 2 * sizeof(s16)) & src_mask; + count -= sizeof(u64); + } + + writeq(dst_pos, &mace->perif.audio.chan[ch].write_ptr); /* in bytes */ + chip->channel[ch].pos = src_pos; + + spin_unlock_irqrestore(&chip->channel[ch].lock, flags); + return ret; +} + +static int snd_sgio2audio_dma_start(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_sgio2audio_chan *chan = substream->runtime->private_data; + int ch = chan->idx; + + /* reset DMA channel */ + writeq(CHANNEL_CONTROL_RESET, &mace->perif.audio.chan[ch].control); + udelay(10); + writeq(0, &mace->perif.audio.chan[ch].control); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* push a full buffer */ + snd_sgio2audio_dma_push_frag(chip, ch, CHANNEL_RING_SIZE - 32); + } + /* set DMA to wake on 50% empty and enable interrupt */ + writeq(CHANNEL_DMA_ENABLE | CHANNEL_INT_THRESHOLD_50, + &mace->perif.audio.chan[ch].control); + return 0; +} + +static int snd_sgio2audio_dma_stop(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio_chan *chan = substream->runtime->private_data; + + writeq(0, &mace->perif.audio.chan[chan->idx].control); + return 0; +} + +static irqreturn_t snd_sgio2audio_dma_in_isr(int irq, void *dev_id) +{ + struct snd_sgio2audio_chan *chan = dev_id; + struct snd_pcm_substream *substream; + struct snd_sgio2audio *chip; + int count, ch; + + substream = chan->substream; + chip = snd_pcm_substream_chip(substream); + ch = chan->idx; + + /* empty the ring */ + count = CHANNEL_RING_SIZE - + readq(&mace->perif.audio.chan[ch].depth) - 32; + if (snd_sgio2audio_dma_pull_frag(chip, ch, count)) + snd_pcm_period_elapsed(substream); + + return IRQ_HANDLED; +} + +static irqreturn_t snd_sgio2audio_dma_out_isr(int irq, void *dev_id) +{ + struct snd_sgio2audio_chan *chan = dev_id; + struct snd_pcm_substream *substream; + struct snd_sgio2audio *chip; + int count, ch; + + substream = chan->substream; + chip = snd_pcm_substream_chip(substream); + ch = chan->idx; + /* fill the ring */ + count = CHANNEL_RING_SIZE - + readq(&mace->perif.audio.chan[ch].depth) - 32; + if (snd_sgio2audio_dma_push_frag(chip, ch, count)) + snd_pcm_period_elapsed(substream); + + return IRQ_HANDLED; +} + +static irqreturn_t snd_sgio2audio_error_isr(int irq, void *dev_id) +{ + struct snd_sgio2audio_chan *chan = dev_id; + struct snd_pcm_substream *substream; + + substream = chan->substream; + snd_sgio2audio_dma_stop(substream); + snd_sgio2audio_dma_start(substream); + return IRQ_HANDLED; +} + +/* PCM part */ +/* PCM hardware definition */ +static struct snd_pcm_hardware snd_sgio2audio_pcm_hw = { + .info = (SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER), + .formats = SNDRV_PCM_FMTBIT_S16_BE, + .rates = SNDRV_PCM_RATE_8000_48000, + .rate_min = 8000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + .buffer_bytes_max = 65536, + .period_bytes_min = 32768, + .period_bytes_max = 65536, + .periods_min = 1, + .periods_max = 1024, +}; + +/* PCM playback open callback */ +static int snd_sgio2audio_playback1_open(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + + runtime->hw = snd_sgio2audio_pcm_hw; + runtime->private_data = &chip->channel[1]; + return 0; +} + +static int snd_sgio2audio_playback2_open(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + + runtime->hw = snd_sgio2audio_pcm_hw; + runtime->private_data = &chip->channel[2]; + return 0; +} + +/* PCM capture open callback */ +static int snd_sgio2audio_capture_open(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + + runtime->hw = snd_sgio2audio_pcm_hw; + runtime->private_data = &chip->channel[0]; + return 0; +} + +/* PCM close callback */ +static int snd_sgio2audio_pcm_close(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + + runtime->private_data = NULL; + return 0; +} + + +/* hw_params callback */ +static int snd_sgio2audio_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + int size = params_buffer_bytes(hw_params); + + /* alloc virtual 'dma' area */ + if (runtime->dma_area) + vfree(runtime->dma_area); + runtime->dma_area = vmalloc(size); + if (runtime->dma_area == NULL) + return -ENOMEM; + runtime->dma_bytes = size; + return 0; +} + +/* hw_free callback */ +static int snd_sgio2audio_pcm_hw_free(struct snd_pcm_substream *substream) +{ + if (substream->runtime->dma_area) + vfree(substream->runtime->dma_area); + substream->runtime->dma_area = NULL; + return 0; +} + +/* prepare callback */ +static int snd_sgio2audio_pcm_prepare(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_sgio2audio_chan *chan = substream->runtime->private_data; + int ch = chan->idx; + unsigned long flags; + + spin_lock_irqsave(&chip->channel[ch].lock, flags); + + /* Setup the pseudo-dma transfer pointers. */ + chip->channel[ch].pos = 0; + chip->channel[ch].size = 0; + chip->channel[ch].substream = substream; + + /* set AD1843 format */ + /* hardware format is always S16_LE */ + switch (substream->stream) { + case SNDRV_PCM_STREAM_PLAYBACK: + ad1843_setup_dac(&chip->ad1843, + ch - 1, + runtime->rate, + SNDRV_PCM_FORMAT_S16_LE, + runtime->channels); + break; + case SNDRV_PCM_STREAM_CAPTURE: + ad1843_setup_adc(&chip->ad1843, + runtime->rate, + SNDRV_PCM_FORMAT_S16_LE, + runtime->channels); + break; + } + spin_unlock_irqrestore(&chip->channel[ch].lock, flags); + return 0; +} + +/* trigger callback */ +static int snd_sgio2audio_pcm_trigger(struct snd_pcm_substream *substream, + int cmd) +{ + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + /* start the PCM engine */ + snd_sgio2audio_dma_start(substream); + break; + case SNDRV_PCM_TRIGGER_STOP: + /* stop the PCM engine */ + snd_sgio2audio_dma_stop(substream); + break; + default: + return -EINVAL; + } + return 0; +} + +/* pointer callback */ +static snd_pcm_uframes_t +snd_sgio2audio_pcm_pointer(struct snd_pcm_substream *substream) +{ + struct snd_sgio2audio *chip = snd_pcm_substream_chip(substream); + struct snd_sgio2audio_chan *chan = substream->runtime->private_data; + + /* get the current hardware pointer */ + return bytes_to_frames(substream->runtime, + chip->channel[chan->idx].pos); +} + +/* get the physical page pointer on the given offset */ +static struct page *snd_sgio2audio_page(struct snd_pcm_substream *substream, + unsigned long offset) +{ + return vmalloc_to_page(substream->runtime->dma_area + offset); +} + +/* operators */ +static struct snd_pcm_ops snd_sgio2audio_playback1_ops = { + .open = snd_sgio2audio_playback1_open, + .close = snd_sgio2audio_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_sgio2audio_pcm_hw_params, + .hw_free = snd_sgio2audio_pcm_hw_free, + .prepare = snd_sgio2audio_pcm_prepare, + .trigger = snd_sgio2audio_pcm_trigger, + .pointer = snd_sgio2audio_pcm_pointer, + .page = snd_sgio2audio_page, +}; + +static struct snd_pcm_ops snd_sgio2audio_playback2_ops = { + .open = snd_sgio2audio_playback2_open, + .close = snd_sgio2audio_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_sgio2audio_pcm_hw_params, + .hw_free = snd_sgio2audio_pcm_hw_free, + .prepare = snd_sgio2audio_pcm_prepare, + .trigger = snd_sgio2audio_pcm_trigger, + .pointer = snd_sgio2audio_pcm_pointer, + .page = snd_sgio2audio_page, +}; + +static struct snd_pcm_ops snd_sgio2audio_capture_ops = { + .open = snd_sgio2audio_capture_open, + .close = snd_sgio2audio_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_sgio2audio_pcm_hw_params, + .hw_free = snd_sgio2audio_pcm_hw_free, + .prepare = snd_sgio2audio_pcm_prepare, + .trigger = snd_sgio2audio_pcm_trigger, + .pointer = snd_sgio2audio_pcm_pointer, + .page = snd_sgio2audio_page, +}; + +/* + * definitions of capture are omitted here... + */ + +/* create a pcm device */ +static int __devinit snd_sgio2audio_new_pcm(struct snd_sgio2audio *chip) +{ + struct snd_pcm *pcm; + int err; + + /* create first pcm device with one outputs and one input */ + err = snd_pcm_new(chip->card, "SGI O2 Audio", 0, 1, 1, &pcm); + if (err < 0) + return err; + + pcm->private_data = chip; + strcpy(pcm->name, "SGI O2 DAC1"); + + /* set operators */ + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, + &snd_sgio2audio_playback1_ops); + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, + &snd_sgio2audio_capture_ops); + + /* create second pcm device with one outputs and no input */ + err = snd_pcm_new(chip->card, "SGI O2 Audio", 1, 1, 0, &pcm); + if (err < 0) + return err; + + pcm->private_data = chip; + strcpy(pcm->name, "SGI O2 DAC2"); + + /* set operators */ + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, + &snd_sgio2audio_playback2_ops); + + return 0; +} + +static struct { + int idx; + int irq; + irqreturn_t (*isr)(int, void *); + const char *desc; +} snd_sgio2_isr_table[] = { + { + .idx = 0, + .irq = MACEISA_AUDIO1_DMAT_IRQ, + .isr = snd_sgio2audio_dma_in_isr, + .desc = "Capture DMA Channel 0" + }, { + .idx = 0, + .irq = MACEISA_AUDIO1_OF_IRQ, + .isr = snd_sgio2audio_error_isr, + .desc = "Capture Overflow" + }, { + .idx = 1, + .irq = MACEISA_AUDIO2_DMAT_IRQ, + .isr = snd_sgio2audio_dma_out_isr, + .desc = "Playback DMA Channel 1" + }, { + .idx = 1, + .irq = MACEISA_AUDIO2_MERR_IRQ, + .isr = snd_sgio2audio_error_isr, + .desc = "Memory Error Channel 1" + }, { + .idx = 2, + .irq = MACEISA_AUDIO3_DMAT_IRQ, + .isr = snd_sgio2audio_dma_out_isr, + .desc = "Playback DMA Channel 2" + }, { + .idx = 2, + .irq = MACEISA_AUDIO3_MERR_IRQ, + .isr = snd_sgio2audio_error_isr, + .desc = "Memory Error Channel 2" + } +}; + +/* ALSA driver */ + +static int snd_sgio2audio_free(struct snd_sgio2audio *chip) +{ + int i; + + /* reset interface */ + writeq(AUDIO_CONTROL_RESET, &mace->perif.audio.control); + udelay(1); + writeq(0, &mace->perif.audio.control); + + /* release IRQ's */ + for (i = 0; i < ARRAY_SIZE(snd_sgio2_isr_table); i++) + free_irq(snd_sgio2_isr_table[i].irq, + &chip->channel[snd_sgio2_isr_table[i].idx]); + + dma_free_coherent(NULL, MACEISA_RINGBUFFERS_SIZE, + chip->ring_base, chip->ring_base_dma); + + /* release card data */ + kfree(chip); + return 0; +} + +static int snd_sgio2audio_dev_free(struct snd_device *device) +{ + struct snd_sgio2audio *chip = device->device_data; + + return snd_sgio2audio_free(chip); +} + +static struct snd_device_ops ops = { + .dev_free = snd_sgio2audio_dev_free, +}; + +static int __devinit snd_sgio2audio_create(struct snd_card *card, + struct snd_sgio2audio **rchip) +{ + struct snd_sgio2audio *chip; + int i, err; + + *rchip = NULL; + + /* check if a codec is attached to the interface */ + /* (Audio or Audio/Video board present) */ + if (!(readq(&mace->perif.audio.control) & AUDIO_CONTROL_CODEC_PRESENT)) + return -ENOENT; + + chip = kzalloc(sizeof(struct snd_sgio2audio), GFP_KERNEL); + if (chip == NULL) + return -ENOMEM; + + chip->card = card; + + chip->ring_base = dma_alloc_coherent(NULL, MACEISA_RINGBUFFERS_SIZE, + &chip->ring_base_dma, GFP_USER); + if (chip->ring_base == NULL) { + printk(KERN_ERR + "sgio2audio: could not allocate ring buffers\n"); + kfree(chip); + return -ENOMEM; + } + + spin_lock_init(&chip->ad1843_lock); + + chip->volume = SGIO2AUDIO_MAX_VOLUME; + + /* initialize channels */ + for (i = 0; i < 3; i++) { + spin_lock_init(&chip->channel[i].lock); + chip->channel[i].idx = i; + } + + /* allocate IRQs */ + for (i = 0; i < ARRAY_SIZE(snd_sgio2_isr_table); i++) { + if (request_irq(snd_sgio2_isr_table[i].irq, + snd_sgio2_isr_table[i].isr, + IRQF_SHARED, + snd_sgio2_isr_table[i].desc, + &chip->channel[snd_sgio2_isr_table[i].idx])) { + snd_sgio2audio_free(chip); + printk(KERN_ERR "sgio2audio: cannot allocate irq %d\n", + snd_sgio2_isr_table[i].irq); + return -EBUSY; + } + } + + /* reset the interface */ + writeq(AUDIO_CONTROL_RESET, &mace->perif.audio.control); + udelay(1); + writeq(0, &mace->perif.audio.control); + udelay(100); /* give time to recover */ + + /* set ring base */ + writeq(chip->ring_base_dma, &mace->perif.ctrl.ringbase); + + /* attach the AD1843 codec */ + chip->ad1843.read = read_ad1843_reg; + chip->ad1843.write = write_ad1843_reg; + chip->ad1843.chip = chip; + + /* initialize the AD1843 codec */ + err = ad1843_init(&chip->ad1843); + if (err < 0) { + snd_sgio2audio_free(chip); + return err; + } + + err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); + if (err < 0) { + snd_sgio2audio_free(chip); + return err; + } + *rchip = chip; + return 0; +} + +static int __devinit snd_sgio2audio_probe(struct platform_device *pdev) +{ + struct snd_card *card; + struct snd_sgio2audio *chip; + int err; + + card = snd_card_new(index, id, THIS_MODULE, 0); + if (card == NULL) + return -ENOMEM; + + err = snd_sgio2audio_create(card, &chip); + if (err < 0) { + snd_card_free(card); + return err; + } + snd_card_set_dev(card, &pdev->dev); + + err = snd_sgio2audio_new_pcm(chip); + if (err < 0) { + snd_card_free(card); + return err; + } + err = snd_sgio2audio_new_mixer(chip); + if (err < 0) { + snd_card_free(card); + return err; + } + + strcpy(card->driver, "SGI O2 Audio"); + strcpy(card->shortname, "SGI O2 Audio"); + sprintf(card->longname, "%s irq %i-%i", + card->shortname, + MACEISA_AUDIO1_DMAT_IRQ, + MACEISA_AUDIO3_MERR_IRQ); + + err = snd_card_register(card); + if (err < 0) { + snd_card_free(card); + return err; + } + platform_set_drvdata(pdev, card); + return 0; +} + +static int __exit snd_sgio2audio_remove(struct platform_device *pdev) +{ + struct snd_card *card = platform_get_drvdata(pdev); + + snd_card_free(card); + platform_set_drvdata(pdev, NULL); + return 0; +} + +static struct platform_driver sgio2audio_driver = { + .probe = snd_sgio2audio_probe, + .remove = __devexit_p(snd_sgio2audio_remove), + .driver = { + .name = "sgio2audio", + .owner = THIS_MODULE, + } +}; + +static int __init alsa_card_sgio2audio_init(void) +{ + return platform_driver_register(&sgio2audio_driver); +} + +static void __exit alsa_card_sgio2audio_exit(void) +{ + platform_driver_unregister(&sgio2audio_driver); +} + +module_init(alsa_card_sgio2audio_init) +module_exit(alsa_card_sgio2audio_exit) -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From tsbogend@alpha.franken.de Sat Jul 5 00:12:19 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Jul 2008 00:12:27 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:35289 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20212841AbYGDXMT (ORCPT ); Sat, 5 Jul 2008 00:12:19 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KEuRt-0004Kk-00; Sat, 05 Jul 2008 01:12:17 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 3C6121DA77A; Sat, 5 Jul 2008 01:12:13 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] IP32: Add platform devices for audio and volume button To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20080704231213.3C6121DA77A@solo.franken.de> Date: Sat, 5 Jul 2008 01:12:13 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19719 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 1298 Lines: 55 Create platform devices for audio and volume button driver. Signed-off-by: Thomas Bogendoerfer --- arch/mips/sgi-ip32/ip32-platform.c | 36 ++++++++++++++++++++++++++++++++++++ 1 files changed, 36 insertions(+), 0 deletions(-) diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c index 89a71f4..2ee401b 100644 --- a/arch/mips/sgi-ip32/ip32-platform.c +++ b/arch/mips/sgi-ip32/ip32-platform.c @@ -65,6 +65,42 @@ static __init int meth_devinit(void) device_initcall(meth_devinit); +static __init int sgio2audio_devinit(void) +{ + struct platform_device *pd; + int ret; + + pd = platform_device_alloc("sgio2audio", -1); + if (!pd) + return -ENOMEM; + + ret = platform_device_add(pd); + if (ret) + platform_device_put(pd); + + return ret; +} + +device_initcall(sgio2audio_devinit); + +static __init int sgio2btns_devinit(void) +{ + struct platform_device *pd; + int ret; + + pd = platform_device_alloc("sgio2btns", -1); + if (!pd) + return -ENOMEM; + + ret = platform_device_add(pd); + if (ret) + platform_device_put(pd); + + return ret; +} + +device_initcall(sgio2btns_devinit); + MODULE_AUTHOR("Ralf Baechle "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("8250 UART probe driver for SGI IP32 aka O2"); From ralf@linux-mips.org Sat Jul 5 00:26:26 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Jul 2008 00:26:33 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:33931 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20213587AbYGDX00 (ORCPT ); Sat, 5 Jul 2008 00:26:26 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m64NP9gC006237; Sat, 5 Jul 2008 01:25:34 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m64NP9Tb006236; Sat, 5 Jul 2008 00:25:09 +0100 Date: Sat, 5 Jul 2008 00:25:09 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] IP32: Add platform devices for audio and volume button Message-ID: <20080704232509.GA5788@linux-mips.org> References: <20080704231213.3C6121DA77A@solo.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080704231213.3C6121DA77A@solo.franken.de> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19720 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 168 Lines: 7 On Sat, Jul 05, 2008 at 01:12:13AM +0200, Thomas Bogendoerfer wrote: > Create platform devices for audio and volume button driver. Thanks, queued for 2.6.27, Ralf From tbm@cyrius.com Sat Jul 5 08:04:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Jul 2008 08:04:38 +0100 (BST) Received: from sorrow.cyrius.com ([65.19.161.204]:43536 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S20221205AbYGEHEd (ORCPT ); Sat, 5 Jul 2008 08:04:33 +0100 Received: by sorrow.cyrius.com (Postfix, from userid 10) id B51AAD8E7; Sat, 5 Jul 2008 07:04:29 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 0762A150F52; Sat, 5 Jul 2008 10:04:10 +0300 (IDT) Date: Sat, 5 Jul 2008 10:04:10 +0300 From: Martin Michlmayr To: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org Subject: Re: SGI O2 sound driver v6 Message-ID: <20080705070410.GA7384@deprecation.cyrius.com> References: <20080628000916.GA22049@alpha.franken.de> <20080628141336.GA17727@alpha.franken.de> <20080628224553.GA2064@alpha.franken.de> <20080629223537.GA697@alpha.franken.de> <20080702232118.GB18226@alpha.franken.de> <20080704225106.GA7408@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080704225106.GA7408@alpha.franken.de> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19721 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 265 Lines: 11 * Thomas Bogendoerfer [2008-07-05 00:51]: > --- /dev/null > +++ b/drivers/input/misc/sgio2_btns.c > @@ -0,0 +1,154 @@ > +/* > + * Cobalt button interface driver. You should update that text. -- Martin Michlmayr http://www.cyrius.com/ From geert@linux-m68k.org Sat Jul 5 09:24:12 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Jul 2008 09:24:17 +0100 (BST) Received: from winston.telenet-ops.be ([195.130.137.75]:2491 "EHLO winston.telenet-ops.be") by ftp.linux-mips.org with ESMTP id S28590565AbYGEIWc (ORCPT ); Sat, 5 Jul 2008 09:22:32 +0100 Received: from localhost (localhost.localdomain [127.0.0.1]) by winston.telenet-ops.be (Postfix) with SMTP id E584DA0046; Sat, 5 Jul 2008 10:22:30 +0200 (CEST) Received: from anakin.of.borg (78-21-204-88.access.telenet.be [78.21.204.88]) by winston.telenet-ops.be (Postfix) with ESMTP id CC5D6A002F; Sat, 5 Jul 2008 10:22:30 +0200 (CEST) Received: from anakin.of.borg (localhost [127.0.0.1]) by anakin.of.borg (8.14.3/8.14.3/Debian-4) with ESMTP id m658MUYi007236 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sat, 5 Jul 2008 10:22:30 +0200 Received: from localhost (geert@localhost) by anakin.of.borg (8.14.3/8.14.3/Submit) with ESMTP id m658MUar007233; Sat, 5 Jul 2008 10:22:30 +0200 X-Authentication-Warning: anakin.of.borg: geert owned process doing -bs Date: Sat, 5 Jul 2008 10:22:30 +0200 (CEST) From: Geert Uytterhoeven To: Thomas Bogendoerfer cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [SPAM] [PATCH] IP32: Add platform devices for audio and volume button In-Reply-To: <20080704231213.3C6121DA77A@solo.franken.de> Message-ID: References: <20080704231213.3C6121DA77A@solo.franken.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19722 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Content-Length: 829 Lines: 29 On Sat, 5 Jul 2008, Thomas Bogendoerfer wrote: > +static __init int sgio2audio_devinit(void) > +{ > + struct platform_device *pd; > + int ret; > + > + pd = platform_device_alloc("sgio2audio", -1); > + if (!pd) > + return -ENOMEM; > + > + ret = platform_device_add(pd); > + if (ret) > + platform_device_put(pd); This sequence is exactly what platform_device_register_simple() does, right? BTW, I'm also still wondering what's the most efficient way of creating platform devices. There's also platform_device_register()... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From tsbogend@alpha.franken.de Sat Jul 5 09:31:57 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 05 Jul 2008 09:32:03 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:62957 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S28589888AbYGEIb5 (ORCPT ); Sat, 5 Jul 2008 09:31:57 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KF3BT-0004Uh-00; Sat, 05 Jul 2008 10:31:55 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 6822AC2E7E; Sat, 5 Jul 2008 10:04:14 +0200 (CEST) Date: Sat, 5 Jul 2008 10:04:14 +0200 To: Martin Michlmayr Cc: linux-mips@linux-mips.org Subject: Re: SGI O2 sound driver v6 Message-ID: <20080705080414.GA4989@alpha.franken.de> References: <20080628000916.GA22049@alpha.franken.de> <20080628141336.GA17727@alpha.franken.de> <20080628224553.GA2064@alpha.franken.de> <20080629223537.GA697@alpha.franken.de> <20080702232118.GB18226@alpha.franken.de> <20080704225106.GA7408@alpha.franken.de> <20080705070410.GA7384@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080705070410.GA7384@deprecation.cyrius.com> User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19723 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 580 Lines: 18 On Sat, Jul 05, 2008 at 10:04:10AM +0300, Martin Michlmayr wrote: > * Thomas Bogendoerfer [2008-07-05 00:51]: > > --- /dev/null > > +++ b/drivers/input/misc/sgio2_btns.c > > @@ -0,0 +1,154 @@ > > +/* > > + * Cobalt button interface driver. > > You should update that text. of course. I noticed it, while preparing the patch for maintainer submission and fixed it. Thanks for noticing. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From mcdonald.shane@gmail.com Sun Jul 6 00:19:51 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 06 Jul 2008 00:19:57 +0100 (BST) Received: from rv-out-0708.google.com ([209.85.198.245]:8425 "EHLO rv-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S20042651AbYGEXTv (ORCPT ); Sun, 6 Jul 2008 00:19:51 +0100 Received: by rv-out-0708.google.com with SMTP id c5so1632272rvf.24 for ; Sat, 05 Jul 2008 16:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:to:subject :message-id:date:from; bh=Gfgj7q+mKExEZM1fpL4AKEb+sPPRDjJ2vBHGLK0E3Zg=; b=m1VMFR5BBjN/dcRSsnLamECafik/hQrvll+Xldw/oFvhuXcQbziK//qyCtcHDpEUCo zlf1xCVpKDkZrEo9xubCNlgC9EIf/4Ac/MjjwlOT6+ebksHzPHeeij6sltkgROxSSyhK FttMP+VoSDwc2MTnX+q8Zmi6ysr7dS18QQUTo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=to:subject:message-id:date:from; b=gfkpS62qo9zPPo9SQfCLVbb1tsj3KPMHRcgVjL1Y1mQE+faSFy+M2tFI5xBJ0V/1rX jDbMiWkNJD9R4b75I7OoTndg+w2KwBcEML+zEEU4WhtAp1TYXFV16V3DlPdR+YhAqtSf +TDMjXHx0SZpwQV+12cbYWrCR5jZDPrw88R9M= Received: by 10.140.133.9 with SMTP id g9mr1260760rvd.235.1215299987928; Sat, 05 Jul 2008 16:19:47 -0700 (PDT) Received: from localhost ( [207.47.250.104]) by mx.google.com with ESMTPS id c20sm3324620rvf.1.2008.07.05.16.19.45 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 05 Jul 2008 16:19:46 -0700 (PDT) Received: from shane by localhost with local (Exim 4.63) (envelope-from ) id 1KFH2c-0005iq-80; Sat, 05 Jul 2008 17:19:42 -0600 To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [MIPS] Fix section mismatches when compiling atlas and decstation defconfigs Message-Id: Date: Sat, 05 Jul 2008 17:19:42 -0600 From: Shane McDonald Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19725 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 2278 Lines: 64 From: Shane McDonald Section mismatches are reported when compiling the default Atlas configuration and the default Decstation configuration. This patch resolves those mismatches by defining affected functions with the __cpuinit attribute, rather than __init. Signed-off-by: Shane McDonald --- arch/mips/mm/c-r3k.c | 6 +++--- arch/mips/mm/sc-rm7k.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff -uprN -X orig/Documentation/dontdiff orig/arch/mips/mm/c-r3k.c patched/arch/mips/mm/c-r3k.c --- orig/arch/mips/mm/c-r3k.c 2008-07-04 17:22:25.000000000 -0600 +++ patched/arch/mips/mm/c-r3k.c 2008-07-05 11:56:01.000000000 -0600 @@ -26,7 +26,7 @@ static unsigned long icache_size, dcache_size; /* Size in bytes */ static unsigned long icache_lsize, dcache_lsize; /* Size in bytes */ -unsigned long __init r3k_cache_size(unsigned long ca_flags) +unsigned long __cpuinit r3k_cache_size(unsigned long ca_flags) { unsigned long flags, status, dummy, size; volatile unsigned long *p; @@ -61,7 +61,7 @@ unsigned long __init r3k_cache_size(unsi return size * sizeof(*p); } -unsigned long __init r3k_cache_lsize(unsigned long ca_flags) +unsigned long __cpuinit r3k_cache_lsize(unsigned long ca_flags) { unsigned long flags, status, lsize, i; volatile unsigned long *p; @@ -90,7 +90,7 @@ unsigned long __init r3k_cache_lsize(uns return lsize * sizeof(*p); } -static void __init r3k_probe_cache(void) +static void __cpuinit r3k_probe_cache(void) { dcache_size = r3k_cache_size(ST0_ISC); if (dcache_size) diff -uprN -X orig/Documentation/dontdiff orig/arch/mips/mm/sc-rm7k.c patched/arch/mips/mm/sc-rm7k.c --- orig/arch/mips/mm/sc-rm7k.c 2008-07-04 17:22:25.000000000 -0600 +++ patched/arch/mips/mm/sc-rm7k.c 2008-07-05 09:51:34.000000000 -0600 @@ -86,7 +86,7 @@ static void rm7k_sc_inv(unsigned long ad /* * This function is executed in uncached address space. */ -static __init void __rm7k_sc_enable(void) +static __cpuinit void __rm7k_sc_enable(void) { int i; @@ -107,7 +107,7 @@ static __init void __rm7k_sc_enable(void } } -static __init void rm7k_sc_enable(void) +static __cpuinit void rm7k_sc_enable(void) { if (read_c0_config() & RM7K_CONF_SE) return; From ralf@linux-mips.org Mon Jul 7 06:28:54 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jul 2008 06:28:59 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:30621 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20033740AbYGGF2y (ORCPT ); Mon, 7 Jul 2008 06:28:54 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m675Ra0h016482; Mon, 7 Jul 2008 07:28:02 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m675RZjj016481; Mon, 7 Jul 2008 06:27:35 +0100 Date: Mon, 7 Jul 2008 06:27:35 +0100 From: Ralf Baechle To: Shane McDonald Cc: linux-mips@linux-mips.org Subject: Re: [MIPS] Fix section mismatches when compiling atlas and decstation defconfigs Message-ID: <20080707052735.GB26850@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19726 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 682 Lines: 19 On Sat, Jul 05, 2008 at 05:19:42PM -0600, Shane McDonald wrote: > From: Shane McDonald Btw, while it doesn't harm there is no need to insert this From: line into the patch if it's identical to the sender's email address as in your case. Where it's missing git will just pick the From: address from the email headers. > Section mismatches are reported when compiling the default > Atlas configuration and the default Decstation configuration. > This patch resolves those mismatches by defining affected > functions with the __cpuinit attribute, rather than __init. > > Signed-off-by: Shane McDonald Thanks, applied. Ralf From ralf@linux-mips.org Mon Jul 7 12:58:01 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jul 2008 12:58:03 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:41376 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20045778AbYGGL55 (ORCPT ); Mon, 7 Jul 2008 12:57:57 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m67Busbf028148; Mon, 7 Jul 2008 12:57:20 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m67Burlc028147; Mon, 7 Jul 2008 12:56:53 +0100 Date: Mon, 7 Jul 2008 12:56:53 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Declare some pci variables in header file Message-ID: <20080707115653.GA28127@linux-mips.org> References: <20080419.005346.85684007.anemo@mba.ocn.ne.jp> <20080704.005940.108121109.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080704.005940.108121109.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19727 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 334 Lines: 11 On Fri, Jul 04, 2008 at 12:59:40AM +0900, Atsushi Nemoto wrote: > On Sat, 19 Apr 2008 00:53:46 +0900 (JST), Atsushi Nemoto wrote: > > Declare pci_probe_only, etc. in asm-mips/pci.h file. This will fix > > some sparse warnings. > > Revesed against current linux-queue tree. Thanks, queued for 2.6.27. Ralf From ralf@linux-mips.org Mon Jul 7 16:27:31 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jul 2008 16:27:33 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:34182 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28601028AbYGGP1b (ORCPT ); Mon, 7 Jul 2008 16:27:31 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m67FQU8M006020; Mon, 7 Jul 2008 16:26:55 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m67FQUI8006019; Mon, 7 Jul 2008 16:26:30 +0100 Date: Mon, 7 Jul 2008 16:26:29 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] rbtx4927: misc cleanups Message-ID: <20080707152629.GA1790@linux-mips.org> References: <20080416.020045.75183728.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080416.020045.75183728.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19728 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 350 Lines: 13 On Wed, Apr 16, 2008 at 02:00:45AM +0900, Atsushi Nemoto wrote: > * Merge tx4927_pci.h into tx4927.h > * Kill (broken) external PCI clock frequency reporting > * Kill unnecessary wbflush() > * Kill unnecessary includes > * Kill debug garbages > > Signed-off-by: Atsushi Nemoto Queued for 2.6.27. Thanks Atsushi-San! Ralf From anemo@mba.ocn.ne.jp Mon Jul 7 17:12:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jul 2008 17:12:41 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:59376 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S28584188AbYGGQMd (ORCPT ); Mon, 7 Jul 2008 17:12:33 +0100 Received: from localhost (p7140-ipad206funabasi.chiba.ocn.ne.jp [222.145.81.140]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id F3340AA82; Tue, 8 Jul 2008 01:12:25 +0900 (JST) Date: Tue, 08 Jul 2008 01:14:10 +0900 (JST) Message-Id: <20080708.011410.41198497.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] Make pcibios_plat_dev_init weak From: Atsushi Nemoto In-Reply-To: <20080418.235357.25909447.anemo@mba.ocn.ne.jp> References: <20080418.235357.25909447.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19729 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 14206 Lines: 440 Most platforms do not need special pcibios_plat_dev_init. Make it weak function and kill all empty instances. Signed-off-by: Atsushi Nemoto --- Revised against current linux-queue tree. arch/mips/pci/fixup-atlas.c | 6 ------ arch/mips/pci/fixup-au1000.c | 6 ------ arch/mips/pci/fixup-capcella.c | 6 ------ arch/mips/pci/fixup-cobalt.c | 6 ------ arch/mips/pci/fixup-emma2rh.c | 6 ------ arch/mips/pci/fixup-excite.c | 6 ------ arch/mips/pci/fixup-ip32.c | 6 ------ arch/mips/pci/fixup-jmr3927.c | 6 ------ arch/mips/pci/fixup-lm2e.c | 6 ------ arch/mips/pci/fixup-malta.c | 6 ------ arch/mips/pci/fixup-mpc30x.c | 6 ------ arch/mips/pci/fixup-pmcmsp.c | 21 --------------------- arch/mips/pci/fixup-pnx8550.c | 6 ------ arch/mips/pci/fixup-rbtx4927.c | 6 ------ arch/mips/pci/fixup-sni.c | 6 ------ arch/mips/pci/fixup-tb0219.c | 6 ------ arch/mips/pci/fixup-tb0226.c | 6 ------ arch/mips/pci/fixup-tb0287.c | 6 ------ arch/mips/pci/fixup-tx4938.c | 9 --------- arch/mips/pci/fixup-wrppmc.c | 6 ------ arch/mips/pci/fixup-yosemite.c | 6 ------ arch/mips/pci/pci-bcm1480.c | 6 ------ arch/mips/pci/pci-ip27.c | 6 ------ arch/mips/pci/pci-lasat.c | 6 ------ arch/mips/pci/pci-sb1250.c | 6 ------ arch/mips/pci/pci.c | 5 +++++ 26 files changed, 5 insertions(+), 168 deletions(-) diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c index 506e883..d41c8c6 100644 --- a/arch/mips/pci/fixup-atlas.c +++ b/arch/mips/pci/fixup-atlas.c @@ -63,12 +63,6 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq_tab[slot][pin]; } -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - #ifdef CONFIG_KGDB /* * The PCI scan may have moved the saa9730 I/O address, so reread diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c index e2ddfc4..d611d97 100644 --- a/arch/mips/pci/fixup-au1000.c +++ b/arch/mips/pci/fixup-au1000.c @@ -35,9 +35,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return irq_tab_alchemy[slot][pin]; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-capcella.c b/arch/mips/pci/fixup-capcella.c index 1416bca..834be10 100644 --- a/arch/mips/pci/fixup-capcella.c +++ b/arch/mips/pci/fixup-capcella.c @@ -42,9 +42,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return irq_tab_capcella[slot][pin]; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index 9553b14..eff9041 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -185,9 +185,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq_tab_cobalt[slot]; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c index a270589..cc26790 100644 --- a/arch/mips/pci/fixup-emma2rh.c +++ b/arch/mips/pci/fixup-emma2rh.c @@ -93,9 +93,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return irq_map[slot][pin]; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c index cd64d9f..106649d 100644 --- a/arch/mips/pci/fixup-excite.c +++ b/arch/mips/pci/fixup-excite.c @@ -28,9 +28,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return USB_IRQ; /* USB controller is the only PCI device */ } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-ip32.c b/arch/mips/pci/fixup-ip32.c index 190fffd..97e3a04 100644 --- a/arch/mips/pci/fixup-ip32.c +++ b/arch/mips/pci/fixup-ip32.c @@ -43,9 +43,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return irq_tab_mace[slot][pin]; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index e974394..a46196a 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -84,9 +84,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) irq = JMR3927_IRQ_ETHER0; return irq; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-lm2e.c b/arch/mips/pci/fixup-lm2e.c index e18ae4f..791cb8f 100644 --- a/arch/mips/pci/fixup-lm2e.c +++ b/arch/mips/pci/fixup-lm2e.c @@ -59,12 +59,6 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - static void __init loongson2e_nec_fixup(struct pci_dev *pdev) { unsigned int val; diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c index 0f48498..c3b2ba0 100644 --- a/arch/mips/pci/fixup-malta.c +++ b/arch/mips/pci/fixup-malta.c @@ -43,12 +43,6 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return pci_irq[virq]; } -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - static void __init malta_piix_func0_fixup(struct pci_dev *pdev) { unsigned char reg_val; diff --git a/arch/mips/pci/fixup-mpc30x.c b/arch/mips/pci/fixup-mpc30x.c index 5911596..092cc75 100644 --- a/arch/mips/pci/fixup-mpc30x.c +++ b/arch/mips/pci/fixup-mpc30x.c @@ -41,9 +41,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq_tab_mpc30x[slot]; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-pmcmsp.c b/arch/mips/pci/fixup-pmcmsp.c index 65735b1..087bf06 100644 --- a/arch/mips/pci/fixup-pmcmsp.c +++ b/arch/mips/pci/fixup-pmcmsp.c @@ -164,27 +164,6 @@ static char irq_tab[][5] __initdata = { /***************************************************************************** * - * FUNCTION: pcibios_plat_dev_init - * _________________________________________________________________________ - * - * DESCRIPTION: Perform platform specific device initialization at - * pci_enable_device() time. - * None are needed for the MSP7120 PCI Controller. - * - * INPUTS: dev - structure describing the PCI device - * - * OUTPUTS: none - * - * RETURNS: PCIBIOS_SUCCESSFUL - * - ****************************************************************************/ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return PCIBIOS_SUCCESSFUL; -} - -/***************************************************************************** - * * FUNCTION: pcibios_map_irq * _________________________________________________________________________ * diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c index 96857ac..1ef895a 100644 --- a/arch/mips/pci/fixup-pnx8550.c +++ b/arch/mips/pci/fixup-pnx8550.c @@ -49,9 +49,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return pnx8550_irq_tab[slot][pin]; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 2d234ca..bccf7be 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -131,9 +131,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c index 5c8a79b..bf6718c 100644 --- a/arch/mips/pci/fixup-sni.c +++ b/arch/mips/pci/fixup-sni.c @@ -162,9 +162,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return 0; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c index ed87733..d525c53 100644 --- a/arch/mips/pci/fixup-tb0219.c +++ b/arch/mips/pci/fixup-tb0219.c @@ -43,9 +43,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-tb0226.c b/arch/mips/pci/fixup-tb0226.c index e3eedf4..7e5e922 100644 --- a/arch/mips/pci/fixup-tb0226.c +++ b/arch/mips/pci/fixup-tb0226.c @@ -78,9 +78,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-tb0287.c b/arch/mips/pci/fixup-tb0287.c index 267ab3d..fd0f628 100644 --- a/arch/mips/pci/fixup-tb0287.c +++ b/arch/mips/pci/fixup-tb0287.c @@ -57,9 +57,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c index f2ba06e..6d33d06 100644 --- a/arch/mips/pci/fixup-tx4938.c +++ b/arch/mips/pci/fixup-tx4938.c @@ -81,12 +81,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } - -/* - * Do platform specific device initialization at pci_enable_device() time - */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c index 3d27754..f50b078 100644 --- a/arch/mips/pci/fixup-wrppmc.c +++ b/arch/mips/pci/fixup-wrppmc.c @@ -29,9 +29,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return pci_irq_tab[slot][pin]; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-yosemite.c b/arch/mips/pci/fixup-yosemite.c index fdafb13..0a75d30 100644 --- a/arch/mips/pci/fixup-yosemite.c +++ b/arch/mips/pci/fixup-yosemite.c @@ -33,9 +33,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return 3; /* Everything goes to one irq bit */ } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index a9060c7..0deac04 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -82,12 +82,6 @@ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return K_BCM1480_INT_PCI_INTA - 1 + pin; } -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - /* * Some checks before doing config cycles: * In PCI Device Mode, hide everything on bus 0 except the LDT host diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index ce92f82..9b39fd5 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -159,12 +159,6 @@ int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - /* * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses * to find the slot number in sense of the bridge device register. diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c index e70ae32..fce5e52 100644 --- a/arch/mips/pci/pci-lasat.c +++ b/arch/mips/pci/pci-lasat.c @@ -86,9 +86,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return -1; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index bf63959..a97a667 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -89,12 +89,6 @@ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return dev->irq; } -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - /* * Some checks before doing config cycles: * In PCI Device Mode, hide everything on bus 0 except the LDT host diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index d7d6cb0..9dd6e01 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -226,6 +226,11 @@ unsigned int pcibios_assign_all_busses(void) return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; } +int __weak pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + int pcibios_enable_device(struct pci_dev *dev, int mask) { int err; From anemo@mba.ocn.ne.jp Mon Jul 7 17:12:58 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jul 2008 17:13:04 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:22261 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S28588454AbYGGQMs (ORCPT ); Mon, 7 Jul 2008 17:12:48 +0100 Received: from localhost (p7140-ipad206funabasi.chiba.ocn.ne.jp [222.145.81.140]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id EB4F7A6F4; Tue, 8 Jul 2008 01:12:42 +0900 (JST) Date: Tue, 08 Jul 2008 01:14:26 +0900 (JST) Message-Id: <20080708.011426.08077033.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] Remove never used pci_probe variable From: Atsushi Nemoto In-Reply-To: <20080419.003435.26096353.anemo@mba.ocn.ne.jp> References: <20080419.003435.26096353.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19730 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 970 Lines: 37 Nobody overwrite pci_probe. Remove it. Also make pcibios_assign_all_busses weak so that platform code can overwrite it. Signed-off-by: Atsushi Nemoto --- Revised against current linux-queue tree. arch/mips/pci/pci.c | 8 ++------ 1 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 9dd6e01..a3dcfd4 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -21,10 +21,6 @@ */ int pci_probe_only; -#define PCI_ASSIGN_ALL_BUSSES 1 - -unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES; - /* * The PCI controller list. */ @@ -221,9 +217,9 @@ void pcibios_set_master(struct pci_dev *dev) pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); } -unsigned int pcibios_assign_all_busses(void) +unsigned int __weak pcibios_assign_all_busses(void) { - return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; + return 1; } int __weak pcibios_plat_dev_init(struct pci_dev *dev) From anemo@mba.ocn.ne.jp Mon Jul 7 17:13:21 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jul 2008 17:13:28 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:53753 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S28583630AbYGGQNI (ORCPT ); Mon, 7 Jul 2008 17:13:08 +0100 Received: from localhost (p7140-ipad206funabasi.chiba.ocn.ne.jp [222.145.81.140]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id A3E85A05C; Tue, 8 Jul 2008 01:13:03 +0900 (JST) Date: Tue, 08 Jul 2008 01:14:47 +0900 (JST) Message-Id: <20080708.011447.130240273.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] Make pcibios_setup weak From: Atsushi Nemoto In-Reply-To: <20080419.003733.48796522.anemo@mba.ocn.ne.jp> References: <20080419.003733.48796522.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19731 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 568 Lines: 22 Make pcibios_setup weak so that platform code can overwrite it. Signed-off-by: Atsushi Nemoto --- Revised against current linux-queue tree. arch/mips/pci/pci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index a3dcfd4..b8f382e 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -329,7 +329,7 @@ EXPORT_SYMBOL(PCIBIOS_MIN_IO); EXPORT_SYMBOL(PCIBIOS_MIN_MEM); #endif -char *pcibios_setup(char *str) +char *__weak pcibios_setup(char *str) { return str; } From tsbogend@alpha.franken.de Mon Jul 7 22:49:06 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jul 2008 22:49:13 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:62877 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S28593726AbYGGVtE (ORCPT ); Mon, 7 Jul 2008 22:49:04 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KFyZz-00019G-00; Mon, 07 Jul 2008 23:49:03 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id A32DCC340A; Mon, 7 Jul 2008 23:49:00 +0200 (CEST) Date: Mon, 7 Jul 2008 23:49:00 +0200 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, ths@networkno.de Subject: Current git broken for R4400 IP22 Message-ID: <20080707214900.GA16143@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19732 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 917 Lines: 35 and the bisect winner is: fb2a27e743cd565c25cd896911e494482a8b7251 is first bad commit commit fb2a27e743cd565c25cd896911e494482a8b7251 Author: Thiemo Seufer Date: Mon Feb 18 19:32:49 2008 +0000 [MIPS] Reimplement clear_page/copy_page .... booting stops after: EXT3-fs: mounted filesystem with ordered data mode. VFS: Mounted root (ext3 filesystem) readonly. Freeing unused kernel memory: 244k freed This is on a IP22 CPU with 200Mhz: CPU revision is: 00000460 (R4400SC) FPU revision is: 00000500 [..] Primary instruction cache 16kB, VIPT, direct mapped, linesize 16 bytes. Primary data cache 16kB, direct mapped, VIPT, cache aliases, linesize 16 bytes Unified secondary cache 1024kB direct mapped, linesize 128 bytes. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From tsbogend@alpha.franken.de Mon Jul 7 23:13:06 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 07 Jul 2008 23:13:08 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:50078 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S28591973AbYGGWNG (ORCPT ); Mon, 7 Jul 2008 23:13:06 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KFyxF-00060g-00; Tue, 08 Jul 2008 00:13:05 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id AE672DE6F3; Tue, 8 Jul 2008 00:13:03 +0200 (CEST) Date: Tue, 8 Jul 2008 00:13:03 +0200 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, ths@networkno.de Subject: Re: Current git broken for R4400 IP22 Message-ID: <20080707221303.GA25880@alpha.franken.de> References: <20080707214900.GA16143@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080707214900.GA16143@alpha.franken.de> User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19733 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 586 Lines: 17 On Mon, Jul 07, 2008 at 11:49:00PM +0200, Thomas Bogendoerfer wrote: > and the bisect winner is: > > fb2a27e743cd565c25cd896911e494482a8b7251 is first bad commit > commit fb2a27e743cd565c25cd896911e494482a8b7251 > Author: Thiemo Seufer > Date: Mon Feb 18 19:32:49 2008 +0000 > > [MIPS] Reimplement clear_page/copy_page reverting this patch brings current git head back to life on that machine. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From zhengyli@cisco.com Tue Jul 8 10:21:36 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 10:21:43 +0100 (BST) Received: from ind-iport-1.cisco.com ([64.104.129.195]:61750 "EHLO ind-iport-1.cisco.com") by ftp.linux-mips.org with ESMTP id S20045047AbYGHJVg (ORCPT ); Tue, 8 Jul 2008 10:21:36 +0100 X-IronPort-AV: E=Sophos;i="4.30,322,1212364800"; d="scan'208,217";a="22795488" Received: from hkg-dkim-2.cisco.com ([10.75.231.163]) by ind-iport-1.cisco.com with ESMTP; 08 Jul 2008 09:21:16 +0000 Received: from hkg-core-1.cisco.com (hkg-core-1.cisco.com [64.104.123.94]) by hkg-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id m689L9L5020364 for ; Tue, 8 Jul 2008 17:21:09 +0800 Received: from xbh-hkg-412.apac.cisco.com (xbh-hkg-412.cisco.com [64.104.123.69]) by hkg-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id m689L9p9003482 for ; Tue, 8 Jul 2008 09:21:09 GMT Received: from xmb-hkg-412.apac.cisco.com ([64.104.123.84]) by xbh-hkg-412.apac.cisco.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 8 Jul 2008 17:21:08 +0800 X-Mimeole: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C8E0DB.F49FC1B0" Subject: how to print stack trace in signal handler Date: Tue, 8 Jul 2008 17:21:27 +0800 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: how to print stack trace in signal handler Thread-Index: Acjg2//7N2WRMUCxTzmVrQyGKGOWCQ== From: "Rockson Li (zhengyli)" To: X-OriginalArrivalTime: 08 Jul 2008 09:21:08.0701 (UTC) FILETIME=[F4A590D0:01C8E0DB] DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=4826; t=1215508870; x=1216372870; c=relaxed/simple; s=hkgdkim2001; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=zhengyli@cisco.com; z=From:=20=22Rockson=20Li=20(zhengyli)=22=20 |Subject:=20how=20to=20print=20stack=20trace=20in=20signal= 20handler |Sender:=20; bh=nyaKDYidV/Ief5xiCacNELHbtmRbMy/Svb+xsF44p1o=; b=Barj1WOnUH9CcenPGEjyH4osWSEF9uxU4zVEuoxGrJOj/Gjyffm4lC/NE/ y5hakRqWvjKUAc14vQV4/vz0vodyXov8OlyJkh/C62pJWK1WzCGdPsL+FBeM ucx79o7z2Gkog4UEVn1FFvZCWVV2c30UeRdrztClcBMz27r7g2tTg=; Authentication-Results: hkg-dkim-2; header.From=zhengyli@cisco.com; dkim=pass ( sig from cisco.com/hkgdkim2001 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19734 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhengyli@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 4725 Lines: 162 This is a multi-part message in MIME format. ------_=_NextPart_001_01C8E0DB.F49FC1B0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Gurus, =20 I want to print the stack trace in exception signal handler, do you guys know any reliable way to do it? =20 My Dev Env, Gcc: MontaVista 3.3.1 Linux Kernel: 2.4.18 Glibc: 2.3.2 =20 I tired,=20 1) backtrace, it just print nothing. 2) try to use sa_sigaction, but when I get uc_mcontext.gregs from the third parameter (cast to ucontext_t*), there is no stack pointer register?? =20 do not know why. =20 Many thanks=20 =20 -Rockson =20 Registers dumped in signal handler: Reg 0: 0 Reg 1: 5f13 Reg 2: 0 Reg 3: 47269c Reg 4: 0 Reg 5: 0 Reg 6: 0 Reg 7: 7fff7918 Reg 8: 0 Reg 9: 0 Reg 10: 0 Reg 11: 8 Reg 12: 0 Reg 13: b Reg 14: 0 Reg 15: 7fff78f8 Reg 16: 0 Reg 17: 0 Reg 18: 0 Reg 19: 0 Reg 20: 0 Reg 21: 5f00 Reg 22: 0 Reg 23: b Reg 24: 0 Reg 25: 0 Reg 26: 0 Reg 27: 0 Reg 28: 0 Reg 29: 0 Reg 30: 0 Reg 31: 0 Reg 32: 0 Reg 33: b Reg 34: 0 Reg 35: 0 Reg 36: 0 =20 =20 ------_=_NextPart_001_01C8E0DB.F49FC1B0 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hi=20 Gurus,
 
I want = to print the=20 stack trace in exception signal handler, do you guys know any reliable = way to do=20 it?
 
My Dev = Env,
Gcc: = MontaVista=20 3.3.1
Linux = Kernel:=20 2.4.18
Glibc: = 2.3.2
 
I = tired,=20
1) = backtrace, it=20 just print nothing.
2) try = to use=20 sa_sigaction, but when I get uc_mcontext.gregs from the third parameter = (cast to=20 ucontext_t*),
   =20 there is no stack pointer register??
 
do not = know=20 why.
 
Many = thanks=20
 
-Rockson
 
Registers dumped in=20 signal handler:
Reg 0: = 0
Reg 1:=20 5f13
Reg 2: 0
Reg 3: 47269c
Reg 4: 0
Reg 5: 0
Reg 6: = 0
Reg 7:=20 7fff7918
Reg 8: 0
Reg 9: 0
Reg 10: 0
Reg 11: 8
Reg 12: = 0
Reg=20 13: b
Reg 14: 0
Reg 15: 7fff78f8
Reg 16: 0
Reg 17: 0
Reg = 18:=20 0
Reg 19: 0
Reg 20: 0
Reg 21: 5f00
Reg 22: 0
Reg 23: = b
Reg 24:=20 0
Reg 25: 0
Reg 26: 0
Reg 27: 0
Reg 28: 0
Reg 29: = 0
Reg 30:=20 0
Reg 31: 0
Reg 32: 0
Reg 33: b
Reg 34: 0
Reg 35: = 0
Reg 36:=20 0
 
 

 ------_=_NextPart_001_01C8E0DB.F49FC1B0-- From krapfenbauer@ict.tuwien.ac.at Tue Jul 8 10:34:42 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 10:34:48 +0100 (BST) Received: from mail2.ict.tuwien.ac.at ([128.131.81.21]:6590 "EHLO mail.ict.tuwien.ac.at") by ftp.linux-mips.org with ESMTP id S20044857AbYGHJej (ORCPT ); Tue, 8 Jul 2008 10:34:39 +0100 Received: from pc81-11.ict.tuwien.ac.at ([128.131.81.11]) by mail.ict.tuwien.ac.at with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1KG9an-0002f4-Il for linux-mips@linux-mips.org; Tue, 08 Jul 2008 11:34:37 +0200 Message-ID: <487334AD.70100@ict.tuwien.ac.at> Date: Tue, 08 Jul 2008 11:34:37 +0200 From: Harald Krapfenbauer Organization: Institute of Computer Technology, Vienna University of Technology User-Agent: Thunderbird 2.0.0.14 (X11/20080502) MIME-Version: 1.0 To: "linux-mips@linux-mips.org" Subject: 64-bit values on 32-bit machine Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 128.131.81.11 X-SA-Exim-Mail-From: krapfenbauer@ict.tuwien.ac.at X-SA-Exim-Scanned: No (on mail.ict.tuwien.ac.at); SAEximRunCond expanded to false Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19735 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: krapfenbauer@ict.tuwien.ac.at Precedence: bulk X-list: linux-mips Content-Length: 437 Lines: 15 Hello, I want to know how 64-bit values are passed on a little-endian 32-bit MIPS machine on function calls. If there is one 64-bit argument to a function, it is passed in registers a0-a1 I think, but does a0 contain the lower 4 bytes or the upper 4? Similarly, if there are several arguments so that a 64-bit argument is passed on the stack: Do the lower 4 bytes go to the lower address or to the higher? Thanks in advance! Harald From tsbogend@alpha.franken.de Tue Jul 8 13:46:41 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 13:46:50 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:40128 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20023015AbYGHMql (ORCPT ); Tue, 8 Jul 2008 13:46:41 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KGCad-0007gY-00; Tue, 08 Jul 2008 14:46:39 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 4EDFBC3562; Tue, 8 Jul 2008 14:46:34 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] Fix 32bit kernels on R4k with 128 byte cache line size To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20080708124634.4EDFBC3562@solo.franken.de> Date: Tue, 8 Jul 2008 14:46:34 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19736 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 3695 Lines: 106 The generated copy_page for R4k CPU with a 128 byte cache line size used Create Dirty Exclusive cache line operations even if only part of the cache line was filled. This change avoids generating cache operations, if only part of the cache line size is copied in one loop. It also increases the maxmimum loop size, because the generated code even fits into the available space for r4k CPUs with 128 byte cache line size. Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/page.c | 61 ++++++++++++++++++++++++++------------------------ 1 files changed, 32 insertions(+), 29 deletions(-) diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 1edf0cb..1417c64 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -235,13 +235,12 @@ static void __cpuinit set_prefetch_parameters(void) } /* * Too much unrolling will overflow the available space in - * clear_space_array / copy_page_array. 8 words sounds generous, - * but a R4000 with 128 byte L2 line length can exceed even that. + * clear_space_array / copy_page_array. */ - half_clear_loop_size = min(8 * clear_word_size, + half_clear_loop_size = min(16 * clear_word_size, max(cache_line_size >> 1, 4 * clear_word_size)); - half_copy_loop_size = min(8 * copy_word_size, + half_copy_loop_size = min(16 * copy_word_size, max(cache_line_size >> 1, 4 * copy_word_size)); } @@ -263,21 +262,23 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off) if (pref_bias_clear_store) { uasm_i_pref(buf, pref_dst_mode, pref_bias_clear_store + off, A0); - } else if (cpu_has_cache_cdex_s) { - uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); - } else if (cpu_has_cache_cdex_p) { - if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { - uasm_i_nop(buf); - uasm_i_nop(buf); - uasm_i_nop(buf); - uasm_i_nop(buf); - } + } else if (cache_line_size == (half_clear_loop_size << 1)) { + if (cpu_has_cache_cdex_s) { + uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); + } else if (cpu_has_cache_cdex_p) { + if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { + uasm_i_nop(buf); + uasm_i_nop(buf); + uasm_i_nop(buf); + uasm_i_nop(buf); + } - if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) - uasm_i_lw(buf, ZERO, ZERO, AT); + if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) + uasm_i_lw(buf, ZERO, ZERO, AT); - uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); - } + uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); + } + } } void __cpuinit build_clear_page(void) @@ -403,20 +404,22 @@ static inline void build_copy_store_pref(u32 **buf, int off) if (pref_bias_copy_store) { uasm_i_pref(buf, pref_dst_mode, pref_bias_copy_store + off, A0); - } else if (cpu_has_cache_cdex_s) { - uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); - } else if (cpu_has_cache_cdex_p) { - if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { - uasm_i_nop(buf); - uasm_i_nop(buf); - uasm_i_nop(buf); - uasm_i_nop(buf); - } + } else if (cache_line_size == (half_copy_loop_size << 1)) { + if (cpu_has_cache_cdex_s) { + uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); + } else if (cpu_has_cache_cdex_p) { + if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { + uasm_i_nop(buf); + uasm_i_nop(buf); + uasm_i_nop(buf); + uasm_i_nop(buf); + } - if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) - uasm_i_lw(buf, ZERO, ZERO, AT); + if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) + uasm_i_lw(buf, ZERO, ZERO, AT); - uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); + uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); + } } } From ralf@linux-mips.org Tue Jul 8 14:03:56 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 14:04:07 +0100 (BST) Received: from [217.169.26.28] ([217.169.26.28]:16010 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20022905AbYGHND4 (ORCPT ); Tue, 8 Jul 2008 14:03:56 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m68D2aai029514; Tue, 8 Jul 2008 14:03:02 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m68D2ZKr029513; Tue, 8 Jul 2008 14:02:35 +0100 Date: Tue, 8 Jul 2008 14:02:34 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Fix 32bit kernels on R4k with 128 byte cache line size Message-ID: <20080708130234.GA29470@linux-mips.org> References: <20080708124634.4EDFBC3562@solo.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080708124634.4EDFBC3562@solo.franken.de> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19737 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 673 Lines: 16 On Tue, Jul 08, 2008 at 02:46:34PM +0200, Thomas Bogendoerfer wrote: > The generated copy_page for R4k CPU with a 128 byte cache line size used > Create Dirty Exclusive cache line operations even if only part of the > cache line was filled. This change avoids generating cache operations, > if only part of the cache line size is copied in one loop. It also > increases the maxmimum loop size, because the generated code even fits > into the available space for r4k CPUs with 128 byte cache line size. > > Signed-off-by: Thomas Bogendoerfer Thanks - another important fix in the last minute ... Applied, will send to Linus tonight. Ralf From ralf@linux-mips.org Tue Jul 8 16:16:01 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 16:16:08 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:48774 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20036090AbYGHPQB (ORCPT ); Tue, 8 Jul 2008 16:16:01 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m68FEaPV031632; Tue, 8 Jul 2008 16:15:01 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m68FEU4Z031631; Tue, 8 Jul 2008 16:14:30 +0100 Date: Tue, 8 Jul 2008 16:14:30 +0100 From: Ralf Baechle To: Harald Krapfenbauer Cc: "linux-mips@linux-mips.org" Subject: Re: 64-bit values on 32-bit machine Message-ID: <20080708151429.GA31147@linux-mips.org> References: <487334AD.70100@ict.tuwien.ac.at> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <487334AD.70100@ict.tuwien.ac.at> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19738 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 2605 Lines: 120 On Tue, Jul 08, 2008 at 11:34:37AM +0200, Harald Krapfenbauer wrote: > I want to know how 64-bit values are passed on a little-endian 32-bit > MIPS machine on function calls. > > If there is one 64-bit argument to a function, it is passed in registers > a0-a1 I think, but does a0 contain the lower 4 bytes or the upper 4? > > Similarly, if there are several arguments so that a 64-bit argument is > passed on the stack: Do the lower 4 bytes go to the lower address or to > the higher? Give a man a fish and he's got to eat for one day. Teach a man how to fish and he's got food for a life ;-) I suggest to find out about such ABI details you write a small test program in C, compile that to assembler code using the -S option and check the generated .s file. For example: $ cat c.c extern foo(unsigned long long a1, unsigned long long a2, unsigned long long a3); void bar(void) { foo(1UL, 2UL, 3UL); } $ mips-linux-gcc -fno-pic -mno-abicalls -O2 -S c.c .file 1 "c.c" .section .mdebug.abi32 .previous .gnu_attribute 4, 1 .text .align 2 .globl bar .ent bar .type bar, @function bar: .set nomips16 .frame $sp,32,$31 # vars= 0, regs= 1/0, args= 24, gp= 0 .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro addiu $sp,$sp,-32 li $3,3 # 0x3 move $2,$0 li $5,1 # 0x1 move $4,$0 li $7,2 # 0x2 move $6,$0 sw $31,28($sp) sw $3,20($sp) jal foo sw $2,16($sp) lw $31,28($sp) nop j $31 addiu $sp,$sp,32 .set macro .set reorder .end bar .ident "GCC: (GNU) 4.3.0" $ mips-linux-gcc is the big endian compiler. Repeat for little endian: $ mipsel-linux-gcc -fno-pic -mno-abicalls -O2 -S c.c .file 1 "c.c" .section .mdebug.abi32 .previous .gnu_attribute 4, 1 .text .align 2 .globl bar .ent bar .type bar, @function bar: .set nomips16 .frame $sp,32,$31 # vars= 0, regs= 1/0, args= 24, gp= 0 .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro addiu $sp,$sp,-32 li $2,3 # 0x3 move $3,$0 li $4,1 # 0x1 move $5,$0 li $6,2 # 0x2 move $7,$0 sw $31,28($sp) sw $2,16($sp) jal foo sw $3,20($sp) lw $31,28($sp) nop j $31 addiu $sp,$sp,32 .set macro .set reorder .end bar .ident "GCC: (GNU) 4.3.0" $ Ignore the "-fno-pic -mno-abicalls" options; they disable the PIC code generation which on MIPS is default and is making the generated code well harder to read. You will notice that big endian compiler uses register pairs $4/$5 rsp. $6/$6 in the order high / low half and the little endian compiler does it in the reverse order; similar for the memory order for stack arguments. Ralf From anemo@mba.ocn.ne.jp Tue Jul 8 16:26:28 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 16:26:32 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:17613 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20036561AbYGHP02 (ORCPT ); Tue, 8 Jul 2008 16:26:28 +0100 Received: from localhost (p2206-ipad301funabasi.chiba.ocn.ne.jp [122.17.252.206]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id EB03CAE18; Wed, 9 Jul 2008 00:26:20 +0900 (JST) Date: Wed, 09 Jul 2008 00:28:05 +0900 (JST) Message-Id: <20080709.002805.128619748.anemo@mba.ocn.ne.jp> To: linux-sparse@vger.kernel.org Cc: linux-mips@linux-mips.org Subject: [PATCH] sparse: Increase pre_buffer[] and check overflow From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19739 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 996 Lines: 35 I got this error when running sparse on mips kernel with gcc 4.3: builtin:272:1: warning: Newline in string or character constant The linus-mips kernel uses '$(CC) -dM -E' to generates arguments for sparse. With gcc 4.3, it generates lot of '-D' options and causes pre_buffer overflow. This patch increase pre_buffer[] size and add extra checking for overflow instead of silently truncating. Signed-off-by: Atsushi Nemoto --- diff --git a/lib.c b/lib.c index 0abcc9a..b8b2d57 100644 --- a/lib.c +++ b/lib.c @@ -186,7 +186,7 @@ void die(const char *fmt, ...) } static unsigned int pre_buffer_size; -static char pre_buffer[8192]; +static char pre_buffer[16384]; int Waddress_space = 1; int Wbitwise = 0; @@ -238,6 +238,8 @@ void add_pre_buffer(const char *fmt, ...) fmt, args); pre_buffer_size = size; va_end(args); + if (pre_buffer_size >= sizeof(pre_buffer) - 1) + die("pre_buffer overflow"); } static char **handle_switch_D(char *arg, char **next) From anemo@mba.ocn.ne.jp Tue Jul 8 16:58:16 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 16:58:22 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:9949 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S28584674AbYGHP6Q (ORCPT ); Tue, 8 Jul 2008 16:58:16 +0100 Received: from localhost (p2206-ipad301funabasi.chiba.ocn.ne.jp [122.17.252.206]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 55D7BA8EF; Wed, 9 Jul 2008 00:58:09 +0900 (JST) Date: Wed, 09 Jul 2008 00:59:53 +0900 (JST) Message-Id: <20080709.005953.26097194.anemo@mba.ocn.ne.jp> To: linux-sparse@vger.kernel.org Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] sparse: Increase pre_buffer[] and check overflow From: Atsushi Nemoto In-Reply-To: <20080709.002805.128619748.anemo@mba.ocn.ne.jp> References: <20080709.002805.128619748.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19740 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 8744 Lines: 164 On Wed, 09 Jul 2008 00:28:05 +0900 (JST), Atsushi Nemoto wrote: > The linus-mips kernel uses '$(CC) -dM -E' to generates arguments for > sparse. With gcc 4.3, it generates lot of '-D' options and causes > pre_buffer overflow. Here is an example of sparse commandline: sparse -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ -Wbitwise -D__DBL_MIN_EXP__='(-1021)' -D__HQ_FBIT__='15' -D__SFRACT_IBIT__='0' -D__FLT_MIN__='1.17549435e-38F' -D__UFRACT_MAX__='0XFFFFP-16UR' -D__DEC64_DEN__='0.000000000000001E-383DD' -D__DQ_FBIT__='63' -D__ULFRACT_FBIT__='32' -D__SACCUM_EPSILON__='0x1P-7HK' -D__CHAR_BIT__='8' -D__USQ_IBIT__='0' -D__ACCUM_FBIT__='15' -DR3000='1' -D__USFRACT_FBIT__='8' -D__ULLFRACT_MAX__='0XFFFFFFFFFFFFFFFFP-64ULLR' -D__WCHAR_MAX__='2147483647' -D__LACCUM_IBIT__='32' -D__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4='1' -D__DBL_DENORM_MIN__='4.9406564584124654e-324' -D__FLT_EVAL_METHOD__='0' -D__unix__='1' -D__LLACCUM_MAX__='0X7FFFFFFFFFFFFFFFP-31LLK' -D__FRACT_FBIT__='15' -D_MIPS_ISA='_MIPS_ISA_MIPS32' -D__UACCUM_FBIT__='16' -D__LANGUAGE_C='1' -D__DBL_MIN_10_EXP__='(-307)' -D__FINITE_MATH_ONLY__='0' -D_MIPS_TUNE='"mips32r2"' -D__LFRACT_IBIT__='0' -D__LFRACT_MAX__='0X7FFFFFFFP-31LR' -D__DEC64_MAX_EXP__='384' -D_ABIO32='1' -D__SA_FBIT__='15' -D__SHRT_MAX__='32767' -D__LDBL_MAX__='1.7976931348623157e+308L' -D__FRACT_MAX__='0X7FFFP-15R' -D__UFRACT_FBIT__='16' -D__UFRACT_MIN__='0.0UR' -D__LANGUAGE_C__='1' -D__UINTMAX_TYPE__='long long unsigned int' -D__LLFRACT_EPSILON__='0x1P-63LLR' -D__linux='1' -D__DEC32_EPSILON__='1E-6DF' -D__OPTIMIZE__='1' -D__unix='1' -D__ULFRACT_MAX__='0XFFFFFFFFP-32ULR' -D__TA_IBIT__='64' -D__LDBL_MAX_EXP__='1024' -D__MIPSEL__='1' -D__linux__='1' -D__ULLFRACT_MIN__='0.0ULLR' -D__SCHAR_MAX__='127' -D__DBL_DIG__='15' -D__LLACCUM_MIN__='(-0X1P31LLK-0X1P31LLK)' -D__SQ_FBIT__='31' -D__SIZEOF_POINTER__='4' -D__USACCUM_IBIT__='8' -D__USER_LABEL_PREFIX__='' -D__STDC_HOSTED__='0' -D__LDBL_HAS_INFINITY__='1' -D__LFRACT_MIN__='(-0.5LR-0.5LR)' -D__mips_fpr='32' -D__HA_IBIT__='8' -D__TQ_IBIT__='0' -D__FLT_EPSILON__='1.19209290e-7F' -D__mips__='1' -D__USFRACT_IBIT__='0' -D__LDBL_MIN__='2.2250738585072014e-308L' -D__FRACT_MIN__='(-0.5R-0.5R)' -D__DEC32_MAX__='9.999999E96DF' -D__DA_IBIT__='32' -DMIPSEL='1' -D__UQQ_FBIT__='8' -D__SIZEOF_LONG__='4' -D__UACCUM_MAX__='0XFFFFFFFFP-16UK' -D__DECIMAL_DIG__='17' -D__LFRACT_EPSILON__='0x1P-31LR' -D__ULFRACT_MIN__='0.0ULR' -D__gnu_linux__='1' -D__LDBL_HAS_QUIET_NAN__='1' -D__ULACCUM_IBIT__='32' -D__UACCUM_EPSILON__='0x1P-16UK' -D__ULLACCUM_MAX__='0XFFFFFFFFFFFFFFFFP-32ULLK' -D__HQ_IBIT__='0' -D__FLT_HAS_DENORM__='1' -D__SIZEOF_LONG_DOUBLE__='8' -D_R3000='1' -D__DQ_IBIT__='0' -D__DBL_MAX__='1.7976931348623157e+308' -D__ULFRACT_IBIT__='0' -D__DBL_HAS_INFINITY__='1' -D__ACCUM_IBIT__='16' -D__DEC32_MIN_EXP__='(-95)' -D__LACCUM_MAX__='0X7FFFFFFFFFFFFFFFP-31LK' -D__LDBL_HAS_DENORM__='1' -D__DEC128_MAX__='9.999999999999999999999999999999999E6144DL' -D__DEC32_MIN__='1E-95DF' -D__ACCUM_MAX__='0X7FFFFFFFP-15K' -D__DBL_MAX_EXP__='1024' -D__USACCUM_EPSILON__='0x1P-8UHK' -D__R3000__='1' -D__DEC128_EPSILON__='1E-33DL' -D__SFRACT_MAX__='0X7FP-7HR' -D__FRACT_IBIT__='0' -D__UACCUM_MIN__='0.0UK' -Dmips='1' -D__UACCUM_IBIT__='16' -D__LONG_LONG_MAX__='9223372036854775807LL' -D__SIZEOF_SIZE_T__='4' -D__ULACCUM_MAX__='0XFFFFFFFFFFFFFFFFP-32ULK' -D__SIZEOF_WINT_T__='4' -D__SA_IBIT__='16' -D__ULLACCUM_MIN__='0.0ULLK' -D__GXX_ABI_VERSION='1002' -D__UTA_FBIT__='64' -D__FLT_MIN_EXP__='(-125)' -D__USFRACT_MAX__='0XFFP-8UHR' -D__UFRACT_IBIT__='0' -D_MIPSEL='1' -D__DBL_MIN__='2.2250738585072014e-308' -D_MIPS_ARCH='"mips32r2"' -D__LACCUM_MIN__='(-0X1P31LK-0X1P31LK)' -D__ULLACCUM_FBIT__='32' -D__ULLFRACT_EPSILON__='0x1P-64ULLR' -D__DEC128_MIN__='1E-6143DL' -D__REGISTER_PREFIX__='' -D__DBL_HAS_DENORM__='1' -D__ACCUM_MIN__='(-0X1P15K-0X1P15K)' -D__SQ_IBIT__='0' -D__UHA_FBIT__='8' -D__SFRACT_MIN__='(-0.5HR-0.5HR)' -D__R3000='1' -D__UTQ_FBIT__='128' -D__FLT_MANT_DIG__='24' -D__VERSION__='"4.3.1"' -D__ULLFRACT_FBIT__='64' -D__FRACT_EPSILON__='0x1P-15R' -D__ULACCUM_MIN__='0.0ULK' -D__UDA_FBIT__='32' -D__LLACCUM_EPSILON__='0x1P-31LLK' -D_MIPS_TUNE_MIPS32R2='1' -D__USFRACT_MIN__='0.0UHR' -D__UQQ_IBIT__='0' -D__DEC64_EPSILON__='1E-15DD' -D__DEC128_MIN_EXP__='(-6143)' -D__UHQ_FBIT__='16' -D__LLACCUM_FBIT__='31' -Dunix='1' -D__SIZE_TYPE__='unsigned int' -D__UDQ_FBIT__='64' -D__DEC32_DEN__='0.000001E-95DF' -D__ELF__='1' -D__mips_isa_rev='2' -D__ULFRACT_EPSILON__='0x1P-32ULR' -D__LLFRACT_FBIT__='63' -D__FLT_RADIX__='2' -D__LDBL_EPSILON__='2.2204460492503131e-16L' -D__SACCUM_MAX__='0X7FFFP-7HK' -D__SIZEOF_PTRDIFF_T__='4' -D__LACCUM_EPSILON__='0x1P-31LK' -D_MIPS_SZPTR='32' -D__USACCUM_MAX__='0XFFFFP-8UHK' -D__SFRACT_EPSILON__='0x1P-7HR' -D__FLT_HAS_QUIET_NAN__='1' -D__FLT_MAX_10_EXP__='38' -D__LONG_MAX__='2147483647L' -D__FLT_HAS_INFINITY__='1' -D__USA_FBIT__='16' -D__DEC64_MAX__='9.999999999999999E384DD' -D__DEC64_MANT_DIG__='16' -D__SACCUM_FBIT__='7' -D_mips='1' -D__SIZEOF_INT__='4' -D__DEC32_MAX_EXP__='96' -D__QQ_FBIT__='7' -Dlinux='1' -D__DEC128_DEN__='0.000000000000000000000000000000001E-6143DL' -D__UTA_IBIT__='64' -D_MIPS_SZINT='32' -D__LDBL_MANT_DIG__='53' -D__SFRACT_FBIT__='7' -D__SACCUM_MIN__='(-0X1P7HK-0X1P7HK)' -D__DBL_HAS_QUIET_NAN__='1' -D__MIPSEL='1' -D__WCHAR_TYPE__='int' -D__SIZEOF_FLOAT__='4' -D__USQ_FBIT__='32' -D__DEC64_MIN_EXP__='(-383)' -D__ULLACCUM_IBIT__='32' -D__FLT_DIG__='6' -D__INT_MAX__='2147483647' -D__LACCUM_FBIT__='31' -D__USACCUM_MIN__='0.0UHK' -D__UHA_IBIT__='8' -D__FLT_MAX_EXP__='128' -D__UTQ_IBIT__='0' -D_MIPS_SIM='_ABIO32' -D__DBL_MANT_DIG__='53' -D__DEC64_MIN__='1E-383DD' -D__WINT_TYPE__='unsigned int' -D__SIZEOF_SHORT__='2' -D__ULLFRACT_IBIT__='0' -D__LDBL_MIN_EXP__='(-1021)' -D_MIPS_FPSET='16' -D__UDA_IBIT__='32' -D__LFRACT_FBIT__='31' -D__LDBL_MAX_10_EXP__='308' -D__DBL_EPSILON__='2.2204460492503131e-16' -D__SIZEOF_WCHAR_T__='4' -D__LLFRACT_MAX__='0X7FFFFFFFFFFFFFFFP-63LLR' -D__TQ_FBIT__='127' -D__ULLACCUM_EPSILON__='0x1P-32ULLK' -D__UHQ_IBIT__='0' -D__LLACCUM_IBIT__='32' -D__DEC_EVAL_METHOD__='2' -D__TA_FBIT__='63' -D_MIPS_ARCH_MIPS32R2='1' -D__mips_soft_float='1' -D__UDQ_IBIT__='0' -D__ACCUM_EPSILON__='0x1P-15K' -D__INTMAX_MAX__='9223372036854775807LL' -D__FLT_DENORM_MIN__='1.40129846e-45F' -D__LLFRACT_IBIT__='0' -DVMLINUX_LOAD_ADDRESS='0xffffffff80100000' -D__FLT_MAX__='3.40282347e+38F' -DLANGUAGE_C='1' -D__USACCUM_FBIT__='8' -D__SIZEOF_DOUBLE__='8' -D__FLT_MIN_10_EXP__='(-37)' -D__UFRACT_EPSILON__='0x1P-16UR' -D__INTMAX_TYPE__='long long int' -D_LANGUAGE_C='1' -D__DEC128_MAX_EXP__='6144' -D__DEC32_MANT_DIG__='7' -D__HA_FBIT__='7' -D__DBL_MAX_10_EXP__='308' -D__LDBL_DENORM_MIN__='4.9406564584124654e-324L' -D__STDC__='1' -D__PTRDIFF_TYPE__='int' -D__LLFRACT_MIN__='(-0.5LLR-0.5LLR)' -D__mips='32' -D__DA_FBIT__='31' -D_MIPS_SZLONG='32' -D__USA_IBIT__='16' -D__DEC128_MANT_DIG__='34' -D__LDBL_MIN_10_EXP__='(-307)' -D__SIZEOF_LONG_LONG__='8' -D__ULACCUM_EPSILON__='0x1P-32ULK' -D__SACCUM_IBIT__='8' -D__LDBL_DIG__='15' -D__GNUC_GNU_INLINE__='1' -D__USFRACT_EPSILON__='0x1P-8UHR' -D__ULACCUM_FBIT__='32' -D__QQ_IBIT__='0' -nostdinc -isystem /usr/lib/gcc/mipsel-linux/4.3.1/include -Wp,-MD,init/.main.o.d -nostdinc -isystem /usr/lib/gcc/mipsel-linux/4.3.1/include -D__KERNEL__ -Iinclude -Iinclude2 -I/home/git/linux-mips/include -include include/linux/autoconf.h -I/home/git/linux-mips/init -Iinit -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Werror-implicit-function-declaration -O2 -fno-stack-protector -mabi=32 -G 0 -mno-abicalls -fno-pic -pipe -msoft-float -ffreestanding -march=mips32r2 -Wa,-mips32r2 -Wa,--trap -I/home/git/linux-mips/include/asm-mips/mach-mips -Iinclude/asm-mips/mach-mips -I/home/git/linux-mips/include/asm-mips/mach-generic -Iinclude/asm-mips/mach-generic -D"VMLINUX_LOAD_ADDRESS=0xffffffff80100000" -fomit-frame-pointer -Wdeclaration-after-statement -Wno-pointer-sign -D"KBUILD_STR(s)=#s" -D"KBUILD_BASENAME=KBUILD_STR(main)" -D"KBUILD_MODNAME=KBUILD_STR(main)" /home/git/linux-mips/init/main.c ; Many of them are not required for kernel build. So another workaround might be filtering some patterns out on kernel side. Something like this: diff --git a/arch/mips/Makefile b/arch/mips/Makefile index ad36c94..4ffa809 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -641,6 +641,9 @@ LDFLAGS += -m $(ld-emul) ifdef CONFIG_MIPS CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -xc /dev/null | \ egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \ + egrep -vw '__(FLT|DBL|LDBL)_[A-Z_0-9]+__' | \ + egrep -vw '__[A-Z]*(ACCUM|FRACT)_[A-Z_0-9]+__' | \ + egrep -vw '__DEC[0-9]+_[A-Z_0-9]+__' | \ sed -e 's/^\#define /-D/' -e "s/ /='/" -e "s/$$/'/") ifdef CONFIG_64BIT CHECKFLAGS += -m64 From sbrown@cortland.com Tue Jul 8 18:40:26 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 18:40:35 +0100 (BST) Received: from [66.209.47.173] ([66.209.47.173]:19123 "EHLO mythtv.ewol.com") by ftp.linux-mips.org with ESMTP id S20046635AbYGHRk0 (ORCPT ); Tue, 8 Jul 2008 18:40:26 +0100 Received: from [127.0.0.1] (localhost.localdomain [127.0.0.1]) by mythtv.ewol.com (8.14.2/8.14.2) with ESMTP id m68He6DZ023622; Tue, 8 Jul 2008 13:40:07 -0400 Message-ID: <4873A676.8050906@cortland.com> Date: Tue, 08 Jul 2008 13:40:06 -0400 From: Steve Brown Reply-To: sbrown@cortland.com User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: linux-mips@linux-mips.org CC: Michael Buesch Subject: Correct way to set coherent_dma_mask on a non-pci device? Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19741 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sbrown@cortland.com Precedence: bulk X-list: linux-mips Content-Length: 389 Lines: 13 There appears to be no function like pci_set_consistent_dma_mask to set the coherent mask for a non-pci device. What is the "proper" way to set it? The context for the question is a recent change to ssb_dma_set_mask() in drivers/ssb/main.c that removed the somewhat fragile, direct manipulation of dma_mask and coherent_dma_mask in favor of a call to dma_set_mask(). Thanks, Steve From mb@bu3sch.de Tue Jul 8 18:56:11 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 18:56:20 +0100 (BST) Received: from bu3sch.de ([62.75.166.246]:21228 "EHLO vs166246.vserver.de") by ftp.linux-mips.org with ESMTP id S20024248AbYGHR4L (ORCPT ); Tue, 8 Jul 2008 18:56:11 +0100 Received: from ycb20.y.pppool.de ([89.60.203.32] helo=powermac.local) by vs166246.vserver.de with esmtpa (Exim 4.63) (envelope-from ) id 1KGHQ8-000114-KS; Tue, 08 Jul 2008 17:56:08 +0000 From: Michael Buesch To: sbrown@cortland.com Subject: Re: Correct way to set coherent_dma_mask on a non-pci device? Date: Tue, 8 Jul 2008 19:55:47 +0200 User-Agent: KMail/1.9.6 (enterprise 0.20070907.709405) Cc: linux-mips@linux-mips.org References: <4873A676.8050906@cortland.com> In-Reply-To: <4873A676.8050906@cortland.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200807081955.47594.mb@bu3sch.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19742 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mb@bu3sch.de Precedence: bulk X-list: linux-mips Content-Length: 584 Lines: 16 On Tuesday 08 July 2008 19:40:06 Steve Brown wrote: > There appears to be no function like pci_set_consistent_dma_mask to set > the coherent mask for a non-pci device. > > What is the "proper" way to set it? > > The context for the question is a recent change to ssb_dma_set_mask() in > drivers/ssb/main.c that removed the somewhat fragile, direct > manipulation of dma_mask and coherent_dma_mask in favor of a call to > dma_set_mask(). Note that SSB devices use the dma_*** API for doing DMA remappings. So it uses dma_set_mask() for setting the mask. -- Greetings Michael. From ralf@linux-mips.org Tue Jul 8 19:51:22 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 19:51:31 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:47009 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28592576AbYGHSvW (ORCPT ); Tue, 8 Jul 2008 19:51:22 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m68IncZJ010235; Tue, 8 Jul 2008 19:49:42 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m68InVmR010192; Tue, 8 Jul 2008 19:49:31 +0100 Date: Tue, 8 Jul 2008 19:49:30 +0100 From: Ralf Baechle To: Shane McDonald Cc: linux-mips@linux-mips.org Subject: Re: [MIPS] Fix section mismatches when compiling atlas and decstation defconfigs Message-ID: <20080708184922.GA27245@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19743 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 570 Lines: 17 On Sat, Jul 05, 2008 at 05:19:42PM -0600, Shane McDonald wrote: > From: Shane McDonald > > Section mismatches are reported when compiling the default > Atlas configuration and the default Decstation configuration. > This patch resolves those mismatches by defining affected > functions with the __cpuinit attribute, rather than __init. > > Signed-off-by: Shane McDonald I already had an earlier version of your patch applied so I have only applied the c-r4k.c part now with an adjusted comment. Thanks, Ralf From sam@ravnborg.org Tue Jul 8 21:45:00 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 08 Jul 2008 21:45:07 +0100 (BST) Received: from pasmtpb.tele.dk ([80.160.77.98]:41156 "EHLO pasmtpB.tele.dk") by ftp.linux-mips.org with ESMTP id S20052894AbYGHUpA (ORCPT ); Tue, 8 Jul 2008 21:45:00 +0100 Received: from ravnborg.org (0x535d98d8.vgnxx8.dynamic.dsl.tele.dk [83.93.152.216]) by pasmtpB.tele.dk (Postfix) with ESMTP id 0B7EDE3039B; Tue, 8 Jul 2008 22:44:57 +0200 (CEST) Received: by ravnborg.org (Postfix, from userid 500) id 295C6580D9; Tue, 8 Jul 2008 22:45:47 +0200 (CEST) Date: Tue, 8 Jul 2008 22:45:47 +0200 From: Sam Ravnborg To: Atsushi Nemoto Cc: linux-sparse@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] sparse: Increase pre_buffer[] and check overflow Message-ID: <20080708204547.GA16742@uranus.ravnborg.org> References: <20080709.002805.128619748.anemo@mba.ocn.ne.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080709.002805.128619748.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19744 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips Content-Length: 613 Lines: 16 On Wed, Jul 09, 2008 at 12:28:05AM +0900, Atsushi Nemoto wrote: > I got this error when running sparse on mips kernel with gcc 4.3: > > builtin:272:1: warning: Newline in string or character constant > > The linus-mips kernel uses '$(CC) -dM -E' to generates arguments for > sparse. With gcc 4.3, it generates lot of '-D' options and causes > pre_buffer overflow. Why does mips have this need when all other archs does not? We should fix sparse so it is dynamically allocated - but that is not an excuse for mips to use odd stuff like this. So please someone from mips land explain why this is needed. Sam From dmitri.vorobiev@movial.fi Wed Jul 9 08:26:27 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Jul 2008 08:26:34 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:18658 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S20042504AbYGIH01 (ORCPT ); Wed, 9 Jul 2008 08:26:27 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id D7674C8103; Wed, 9 Jul 2008 10:26:20 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id md1cu9u6lp6V; Wed, 9 Jul 2008 10:26:20 +0300 (EEST) Received: from [172.17.49.48] (sd048.hel.movial.fi [172.17.49.48]) by smtp.movial.fi (Postfix) with ESMTP id B2F12C8100; Wed, 9 Jul 2008 10:26:20 +0300 (EEST) Message-ID: <487468E2.30402@movial.fi> Date: Wed, 09 Jul 2008 10:29:38 +0300 From: Dmitri Vorobiev Organization: Movial Creative Technologies User-Agent: Icedove 1.5.0.14eol (X11/20080509) MIME-Version: 1.0 To: Ralf Baechle CC: Shane McDonald , linux-mips@linux-mips.org Subject: Re: [MIPS] Fix section mismatches when compiling atlas and decstation defconfigs References: <20080708184922.GA27245@linux-mips.org> In-Reply-To: <20080708184922.GA27245@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19746 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips Content-Length: 665 Lines: 26 Ralf Baechle wrote: > On Sat, Jul 05, 2008 at 05:19:42PM -0600, Shane McDonald wrote: > >> From: Shane McDonald >> >> Section mismatches are reported when compiling the default >> Atlas configuration and the default Decstation configuration. >> This patch resolves those mismatches by defining affected >> functions with the __cpuinit attribute, rather than __init. >> >> Signed-off-by: Shane McDonald > > I already had an earlier version of your patch applied so I have only > applied the c-r4k.c part now with an adjusted comment. Isn't Atlas doomed to death? Thanks, Dmitri > > Thanks, > > Ralf > From ralf@linux-mips.org Wed Jul 9 13:37:22 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Jul 2008 13:37:29 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:25747 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20024945AbYGIMhW (ORCPT ); Wed, 9 Jul 2008 13:37:22 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m69COALd017723 for ; Wed, 9 Jul 2008 13:29:30 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m69COA0I017716 for linux-mips@linux-mips.org; Wed, 9 Jul 2008 13:24:10 +0100 Date: Wed, 9 Jul 2008 13:24:09 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: Re: Atlas and SEAD Message-ID: <20080709122409.GA13197@linux-mips.org> References: <20080612134027.GA19346@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080612134027.GA19346@linux-mips.org> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19747 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 326 Lines: 9 On Thu, Jun 12, 2008 at 02:40:27PM +0100, Ralf Baechle wrote: > It's time to ask the routine question again, who does still care about > the Atlas and SEAD boards? I don't even recall how long since the last > test report on actual hardware for these so my chainsaw is itching. So they're gone in -queue and -next. Ralf From ralf@linux-mips.org Wed Jul 9 13:37:46 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Jul 2008 13:37:56 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:26515 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20024964AbYGIMhg (ORCPT ); Wed, 9 Jul 2008 13:37:36 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m699rQjr030350; Wed, 9 Jul 2008 10:58:47 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m699rORd030331; Wed, 9 Jul 2008 10:53:24 +0100 Date: Wed, 9 Jul 2008 10:53:24 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: Shane McDonald , linux-mips@linux-mips.org Subject: Re: [MIPS] Fix section mismatches when compiling atlas and decstation defconfigs Message-ID: <20080709095324.GA29844@linux-mips.org> References: <20080708184922.GA27245@linux-mips.org> <487468E2.30402@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <487468E2.30402@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19748 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 868 Lines: 23 On Wed, Jul 09, 2008 at 10:29:38AM +0300, Dmitri Vorobiev wrote: > Ralf Baechle wrote: > > On Sat, Jul 05, 2008 at 05:19:42PM -0600, Shane McDonald wrote: > > > >> From: Shane McDonald > >> > >> Section mismatches are reported when compiling the default > >> Atlas configuration and the default Decstation configuration. > >> This patch resolves those mismatches by defining affected > >> functions with the __cpuinit attribute, rather than __init. > >> > >> Signed-off-by: Shane McDonald > > > > I already had an earlier version of your patch applied so I have only > > applied the c-r4k.c part now with an adjusted comment. > > Isn't Atlas doomed to death? Yes - but there is nothing in this patch that actually makes it Atlas or DECstation specific. It's simply fixing bugs in the CPU cache code. Ralf From anemo@mba.ocn.ne.jp Wed Jul 9 17:00:31 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Jul 2008 17:00:33 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:33499 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20022151AbYGIQAb (ORCPT ); Wed, 9 Jul 2008 17:00:31 +0100 Received: from localhost (p5236-ipad201funabasi.chiba.ocn.ne.jp [222.146.68.236]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 014D1AE89; Thu, 10 Jul 2008 01:00:23 +0900 (JST) Date: Thu, 10 Jul 2008 01:02:08 +0900 (JST) Message-Id: <20080710.010208.39154926.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Make gpio_txx9 entirely spinlock-safe From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19749 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1323 Lines: 40 TXx9 GPIO set/get routines are spinlock-safe. This patch make gpio_direction_{input,output} routines also spinlock-safe so that they can be used during early board setup. Signed-off-by: Atsushi Nemoto --- diff --git a/arch/mips/kernel/gpio_txx9.c b/arch/mips/kernel/gpio_txx9.c index b1436a8..c6854d9 100644 --- a/arch/mips/kernel/gpio_txx9.c +++ b/arch/mips/kernel/gpio_txx9.c @@ -47,23 +47,25 @@ static void txx9_gpio_set(struct gpio_chip *chip, unsigned int offset, static int txx9_gpio_dir_in(struct gpio_chip *chip, unsigned int offset) { - spin_lock_irq(&txx9_gpio_lock); + unsigned long flags; + spin_lock_irqsave(&txx9_gpio_lock, flags); __raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset), &txx9_pioptr->dir); mmiowb(); - spin_unlock_irq(&txx9_gpio_lock); + spin_unlock_irqrestore(&txx9_gpio_lock, flags); return 0; } static int txx9_gpio_dir_out(struct gpio_chip *chip, unsigned int offset, int value) { - spin_lock_irq(&txx9_gpio_lock); + unsigned long flags; + spin_lock_irqsave(&txx9_gpio_lock, flags); txx9_gpio_set_raw(offset, value); __raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset), &txx9_pioptr->dir); mmiowb(); - spin_unlock_irq(&txx9_gpio_lock); + spin_unlock_irqrestore(&txx9_gpio_lock, flags); return 0; } From anemo@mba.ocn.ne.jp Wed Jul 9 17:16:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Jul 2008 17:16:39 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:195 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20021828AbYGIQQh (ORCPT ); Wed, 9 Jul 2008 17:16:37 +0100 Received: from localhost (p5236-ipad201funabasi.chiba.ocn.ne.jp [222.146.68.236]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 11767A042; Thu, 10 Jul 2008 01:16:33 +0900 (JST) Date: Thu, 10 Jul 2008 01:18:18 +0900 (JST) Message-Id: <20080710.011818.26096759.anemo@mba.ocn.ne.jp> To: sam@ravnborg.org Cc: linux-sparse@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] sparse: Increase pre_buffer[] and check overflow From: Atsushi Nemoto In-Reply-To: <20080708204547.GA16742@uranus.ravnborg.org> References: <20080709.002805.128619748.anemo@mba.ocn.ne.jp> <20080708204547.GA16742@uranus.ravnborg.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19750 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 2726 Lines: 65 On Tue, 8 Jul 2008 22:45:47 +0200, Sam Ravnborg wrote: > > The linus-mips kernel uses '$(CC) -dM -E' to generates arguments for > > sparse. With gcc 4.3, it generates lot of '-D' options and causes > > pre_buffer overflow. > > Why does mips have this need when all other archs does not? > We should fix sparse so it is dynamically allocated - but > that is not an excuse for mips to use odd stuff like this. > > So please someone from mips land explain why this is needed. This was introduced by commit 59b3e8e9aac69d2d02853acac7e2affdfbabca50. ("[MIPS] Makefile crapectomy.") Before the commit, CHECKFLAGS was adjusted like this: CHECKFLAGS-y += -D__linux__ -D__mips__ \ -D_MIPS_SZINT=32 \ -D_ABIO32=1 \ -D_ABIN32=2 \ -D_ABI64=3 CHECKFLAGS-$(CONFIG_32BIT) += -D_MIPS_SIM=_ABIO32 \ -D_MIPS_SZLONG=32 \ -D_MIPS_SZPTR=32 \ -D__PTRDIFF_TYPE__=int CHECKFLAGS-$(CONFIG_64BIT) += -m64 -D_MIPS_SIM=_ABI64 \ -D_MIPS_SZLONG=64 \ -D_MIPS_SZPTR=64 \ -D__PTRDIFF_TYPE__="long int" CHECKFLAGS-$(CONFIG_CPU_BIG_ENDIAN) += -D__MIPSEB__ CHECKFLAGS-$(CONFIG_CPU_LITTLE_ENDIAN) += -D__MIPSEL__ CHECKFLAGS = $(CHECKFLAGS-y) CHECKFLAGS-$(CONFIG_CPU_R3000) += -D_MIPS_ISA=_MIPS_ISA_MIPS1 CHECKFLAGS-$(CONFIG_CPU_TX39XX) += -D_MIPS_ISA=_MIPS_ISA_MIPS1 CHECKFLAGS-$(CONFIG_CPU_R6000) += -D_MIPS_ISA=_MIPS_ISA_MIPS2 CHECKFLAGS-$(CONFIG_CPU_R4300) += -D_MIPS_ISA=_MIPS_ISA_MIPS3 CHECKFLAGS-$(CONFIG_CPU_VR41XX) += -D_MIPS_ISA=_MIPS_ISA_MIPS3 CHECKFLAGS-$(CONFIG_CPU_R4X00) += -D_MIPS_ISA=_MIPS_ISA_MIPS3 CHECKFLAGS-$(CONFIG_CPU_TX49XX) += -D_MIPS_ISA=_MIPS_ISA_MIPS3 CHECKFLAGS-$(CONFIG_CPU_MIPS32_R1) += -D_MIPS_ISA=_MIPS_ISA_MIPS32 CHECKFLAGS-$(CONFIG_CPU_MIPS32_R2) += -D_MIPS_ISA=_MIPS_ISA_MIPS32 CHECKFLAGS-$(CONFIG_CPU_MIPS64_R1) += -D_MIPS_ISA=_MIPS_ISA_MIPS64 CHECKFLAGS-$(CONFIG_CPU_MIPS64_R2) += -D_MIPS_ISA=_MIPS_ISA_MIPS64 CHECKFLAGS-$(CONFIG_CPU_R5000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 CHECKFLAGS-$(CONFIG_CPU_R5432) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 CHECKFLAGS-$(CONFIG_CPU_NEVADA) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 CHECKFLAGS-$(CONFIG_CPU_RM7000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 CHECKFLAGS-$(CONFIG_CPU_RM9000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 CHECKFLAGS-$(CONFIG_CPU_SB1) += -D_MIPS_ISA=_MIPS_ISA_MIPS64 CHECKFLAGS-$(CONFIG_CPU_R8000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 CHECKFLAGS-$(CONFIG_CPU_R10000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 And now: CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -xc /dev/null | \ egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \ sed -e 's/^\#define /-D/' -e "s/ /='/" -e "s/$$/'/") ifdef CONFIG_64BIT CHECKFLAGS += -m64 endif It looks fairly simple, unless you run make C=1 V=1 ... --- Atsushi Nemoto From sam@ravnborg.org Wed Jul 9 17:31:24 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Jul 2008 17:31:26 +0100 (BST) Received: from pasmtpb.tele.dk ([80.160.77.98]:56297 "EHLO pasmtpB.tele.dk") by ftp.linux-mips.org with ESMTP id S20023167AbYGIQbY (ORCPT ); Wed, 9 Jul 2008 17:31:24 +0100 Received: from ravnborg.org (0x535d98d8.vgnxx8.dynamic.dsl.tele.dk [83.93.152.216]) by pasmtpB.tele.dk (Postfix) with ESMTP id 0FEC8E30CAF; Wed, 9 Jul 2008 18:31:22 +0200 (CEST) Received: by ravnborg.org (Postfix, from userid 500) id 55D9D580D9; Wed, 9 Jul 2008 18:32:12 +0200 (CEST) Date: Wed, 9 Jul 2008 18:32:12 +0200 From: Sam Ravnborg To: Atsushi Nemoto Cc: linux-sparse@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] sparse: Increase pre_buffer[] and check overflow Message-ID: <20080709163212.GA1227@uranus.ravnborg.org> References: <20080709.002805.128619748.anemo@mba.ocn.ne.jp> <20080708204547.GA16742@uranus.ravnborg.org> <20080710.011818.26096759.anemo@mba.ocn.ne.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080710.011818.26096759.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19751 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips Content-Length: 1050 Lines: 31 On Thu, Jul 10, 2008 at 01:18:18AM +0900, Atsushi Nemoto wrote: > On Tue, 8 Jul 2008 22:45:47 +0200, Sam Ravnborg wrote: > > > The linus-mips kernel uses '$(CC) -dM -E' to generates arguments for > > > sparse. With gcc 4.3, it generates lot of '-D' options and causes > > > pre_buffer overflow. > > > > Why does mips have this need when all other archs does not? > > We should fix sparse so it is dynamically allocated - but > > that is not an excuse for mips to use odd stuff like this. > > > > So please someone from mips land explain why this is needed. > > This was introduced by commit 59b3e8e9aac69d2d02853acac7e2affdfbabca50. > ("[MIPS] Makefile crapectomy.") > > Before the commit, CHECKFLAGS was adjusted like this: > > CHECKFLAGS-y += -D__linux__ -D__mips__ \ > -D_MIPS_SZINT=32 \ > -D_ABIO32=1 \ ... So the expalnation seems that gcc for mips define much more than the usual gcc does. My gcc define 76 symbols for i386. And we use this stuff in the kernel. OK - thanks for the details. Sam From ralf@linux-mips.org Wed Jul 9 17:41:00 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 09 Jul 2008 17:41:02 +0100 (BST) Received: from ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk ([217.169.26.28]:63414 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20025262AbYGIQk7 (ORCPT ); Wed, 9 Jul 2008 17:40:59 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m69GesgW025421; Wed, 9 Jul 2008 17:40:55 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m69GerHL025414; Wed, 9 Jul 2008 17:40:53 +0100 Date: Wed, 9 Jul 2008 17:40:53 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Make gpio_txx9 entirely spinlock-safe Message-ID: <20080709164053.GA5672@linux-mips.org> References: <20080710.010208.39154926.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080710.010208.39154926.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19752 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 279 Lines: 9 On Thu, Jul 10, 2008 at 01:02:08AM +0900, Atsushi Nemoto wrote: > TXx9 GPIO set/get routines are spinlock-safe. This patch make > gpio_direction_{input,output} routines also spinlock-safe so that they > can be used during early board setup. Thanks, queued for 2.6.27. Ralf From anemo@mba.ocn.ne.jp Thu Jul 10 16:30:16 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Jul 2008 16:30:28 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:24319 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20026383AbYGJPaQ (ORCPT ); Thu, 10 Jul 2008 16:30:16 +0100 Received: from localhost (p7221-ipad210funabasi.chiba.ocn.ne.jp [58.88.126.221]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 27694AAB9; Fri, 11 Jul 2008 00:29:51 +0900 (JST) Date: Fri, 11 Jul 2008 00:31:36 +0900 (JST) Message-Id: <20080711.003136.106261691.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 1/3] reorganize txx9 code From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19761 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 397067 Lines: 12550 Move arch/mips/{jmr3927,tx4927,tx4938} into arch/mips/txx9/ tree. This will help more code sharing and maintainance. Signed-off-by: Atsushi Nemoto --- git-diff --stat -M output: arch/mips/Kconfig | 3 +- arch/mips/Makefile | 12 ++-- arch/mips/jmr3927/common/Makefile | 7 -- arch/mips/jmr3927/common/puts.c | 60 -------------------- arch/mips/pci/Makefile | 2 +- arch/mips/pci/fixup-jmr3927.c | 2 +- arch/mips/pci/fixup-rbtx4927.c | 2 +- arch/mips/pci/{fixup-tx4938.c => fixup-rbtx4938.c} | 2 +- arch/mips/pci/ops-tx3927.c | 2 +- arch/mips/pci/ops-tx4927.c | 2 +- arch/mips/pci/ops-tx4938.c | 2 +- arch/mips/pci/pci-jmr3927.c | 2 +- arch/mips/tx4927/Kconfig | 3 - arch/mips/tx4927/common/Makefile | 10 --- arch/mips/tx4927/common/tx4927_dbgio.c | 43 -------------- arch/mips/tx4927/toshiba_rbtx4927/Makefile | 5 -- arch/mips/tx4938/common/Makefile | 8 --- arch/mips/tx4938/toshiba_rbtx4938/Makefile | 7 -- arch/mips/{tx4938 => txx9}/Kconfig | 4 + arch/mips/txx9/generic/Makefile | 10 +++ arch/mips/{tx4938/common => txx9/generic}/dbgio.c | 0 .../tx4927_irq.c => txx9/generic/irq_tx4927.c} | 3 +- .../common/irq.c => txx9/generic/irq_tx4938.c} | 2 +- .../tx4927_prom.c => txx9/generic/mem_tx4927.c} | 1 - .../common/prom.c => txx9/generic/mem_tx4938.c} | 0 .../common => txx9/generic}/smsc_fdc37m81x.c | 2 +- .../{jmr3927/rbhma3100 => txx9/jmr3927}/Makefile | 4 +- .../{jmr3927/rbhma3100 => txx9/jmr3927}/init.c | 2 +- .../mips/{jmr3927/rbhma3100 => txx9/jmr3927}/irq.c | 2 +- .../{jmr3927/rbhma3100 => txx9/jmr3927}/kgdb_io.c | 2 +- arch/mips/{jmr3927/common => txx9/jmr3927}/prom.c | 26 +++++++++ .../{jmr3927/rbhma3100 => txx9/jmr3927}/setup.c | 2 +- arch/mips/txx9/rbtx4927/Makefile | 3 + .../toshiba_rbtx4927_irq.c => txx9/rbtx4927/irq.c} | 4 +- .../rbtx4927/prom.c} | 2 +- .../rbtx4927/setup.c} | 4 +- arch/mips/txx9/rbtx4938/Makefile | 3 + .../toshiba_rbtx4938 => txx9/rbtx4938}/irq.c | 4 +- .../toshiba_rbtx4938 => txx9/rbtx4938}/prom.c | 4 +- .../toshiba_rbtx4938 => txx9/rbtx4938}/setup.c | 6 +- .../rbtx4938}/spi_eeprom.c | 4 +- include/asm-mips/{jmr3927 => txx9}/jmr3927.h | 8 +- .../{tx4927/toshiba_rbtx4927.h => txx9/rbtx4927.h} | 8 +- include/asm-mips/{tx4938 => txx9}/rbtx4938.h | 9 +-- include/asm-mips/{tx4927 => txx9}/smsc_fdc37m81x.h | 2 - include/asm-mips/{tx4938 => txx9}/spi.h | 7 +- include/asm-mips/{jmr3927 => txx9}/tx3927.h | 8 +- include/asm-mips/{tx4927 => txx9}/tx4927.h | 6 +- include/asm-mips/{tx4938 => txx9}/tx4938.h | 5 +- include/asm-mips/{jmr3927 => txx9}/txx927.h | 6 +- 50 files changed, 107 insertions(+), 220 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a038142..3202960 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -642,8 +642,7 @@ source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" -source "arch/mips/tx4927/Kconfig" -source "arch/mips/tx4938/Kconfig" +source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" endmenu diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 36aa690..8e1e49c 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -553,8 +553,8 @@ all-$(CONFIG_SNI_RM) := vmlinux.ecoff # # Toshiba JMR-TX3927 board # -core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/jmr3927/rbhma3100/ \ - arch/mips/jmr3927/common/ +core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ \ + arch/mips/txx9/generic/ cflags-$(CONFIG_TOSHIBA_JMR3927) += -Iinclude/asm-mips/mach-jmr3927 load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000 @@ -562,16 +562,16 @@ load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000 # Toshiba RBTX4927 board or # Toshiba RBTX4937 board # -core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/ -core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ +core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/ +core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/generic/ cflags-$(CONFIG_TOSHIBA_RBTX4927) += -Iinclude/asm-mips/mach-tx49xx load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 # # Toshiba RBTX4938 board # -core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/ -core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/ +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/generic/ cflags-$(CONFIG_TOSHIBA_RBTX4938) += -Iinclude/asm-mips/mach-tx49xx load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000 diff --git a/arch/mips/jmr3927/common/Makefile b/arch/mips/jmr3927/common/Makefile deleted file mode 100644 index 8fd4fcc..0000000 --- a/arch/mips/jmr3927/common/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for the common code of TOSHIBA JMR-TX3927 board -# - -obj-y += prom.o puts.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/jmr3927/common/prom.c b/arch/mips/jmr3927/common/prom.c deleted file mode 100644 index 5398813..0000000 --- a/arch/mips/jmr3927/common/prom.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * PROM library initialisation code, assuming a version of - * pmon is the boot code. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * Based on arch/mips/au1000/common/prom.c - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/xx files. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include - -#include - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - int prom_argc = fw_arg0; - char **prom_argv = (char **) fw_arg1; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/jmr3927/common/puts.c b/arch/mips/jmr3927/common/puts.c deleted file mode 100644 index c611ab4..0000000 --- a/arch/mips/jmr3927/common/puts.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Low level uart routines to directly access a TX[34]927 SIO. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com or source@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * Based on arch/mips/au1000/common/puts.c - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include - -#define TIMEOUT 0xffffff - -void -prom_putchar(char c) -{ - int i = 0; - - do { - i++; - if (i>TIMEOUT) - break; - } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); - tx3927_sioptr(1)->tfifo = c; - return; -} - -void -puts(const char *cp) -{ - while (*cp) - prom_putchar(*cp++); - prom_putchar('\r'); - prom_putchar('\n'); -} diff --git a/arch/mips/jmr3927/rbhma3100/Makefile b/arch/mips/jmr3927/rbhma3100/Makefile deleted file mode 100644 index d86e30d..0000000 --- a/arch/mips/jmr3927/rbhma3100/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for TOSHIBA JMR-TX3927 board -# - -obj-y += init.o irq.o setup.o -obj-$(CONFIG_KGDB) += kgdb_io.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/jmr3927/rbhma3100/init.c b/arch/mips/jmr3927/rbhma3100/init.c deleted file mode 100644 index 700b9cf..0000000 --- a/arch/mips/jmr3927/rbhma3100/init.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * arch/mips/jmr3927/common/init.c - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include - -extern void __init prom_init_cmdline(void); - -const char *get_system_type(void) -{ - return "Toshiba" -#ifdef CONFIG_TOSHIBA_JMR3927 - " JMR_TX3927" -#endif - ; -} - -extern void puts(const char *cp); - -void __init prom_init(void) -{ -#ifdef CONFIG_TOSHIBA_JMR3927 - /* CCFG */ - if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) - puts("Warning: TX3927 TLB off\n"); -#endif - - prom_init_cmdline(); - add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); -} diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c deleted file mode 100644 index 3a47e8c..0000000 --- a/arch/mips/jmr3927/rbhma3100/irq.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#if JMR3927_IRQ_END > NR_IRQS -#error JMR3927_IRQ_END > NR_IRQS -#endif - -static unsigned char irc_level[TX3927_NUM_IR] = { - 5, 5, 5, 5, 5, 5, /* INT[5:0] */ - 7, 7, /* SIO */ - 5, 5, 5, 0, 0, /* DMA, PIO, PCI */ - 6, 6, 6 /* TMR */ -}; - -/* - * CP0_STATUS is a thread's resource (saved/restored on context switch). - * So disable_irq/enable_irq MUST handle IOC/IRC registers. - */ -static void mask_irq_ioc(unsigned int irq) -{ - /* 0: mask */ - unsigned int irq_nr = irq - JMR3927_IRQ_IOC; - unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); - unsigned int bit = 1 << irq_nr; - jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); - /* flush write buffer */ - (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); -} -static void unmask_irq_ioc(unsigned int irq) -{ - /* 0: mask */ - unsigned int irq_nr = irq - JMR3927_IRQ_IOC; - unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); - unsigned int bit = 1 << irq_nr; - jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); - /* flush write buffer */ - (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned long cp0_cause = read_c0_cause(); - int irq; - - if ((cp0_cause & CAUSEF_IP7) == 0) - return; - irq = (cp0_cause >> CAUSEB_IP2) & 0x0f; - - do_IRQ(irq + JMR3927_IRQ_IRC); -} - -static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id) -{ - unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); - int i; - - for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { - if (istat & (1 << i)) { - irq = JMR3927_IRQ_IOC + i; - do_IRQ(irq); - } - } - return IRQ_HANDLED; -} - -static struct irqaction ioc_action = { - .handler = jmr3927_ioc_interrupt, - .mask = CPU_MASK_NONE, - .name = "IOC", -}; - -static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) -{ - printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); - printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", - tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); - - return IRQ_HANDLED; -} -static struct irqaction pcierr_action = { - .handler = jmr3927_pcierr_interrupt, - .mask = CPU_MASK_NONE, - .name = "PCI error", -}; - -static void __init jmr3927_irq_init(void); - -void __init arch_init_irq(void) -{ - /* Now, interrupt control disabled, */ - /* all IRC interrupts are masked, */ - /* all IRC interrupt mode are Low Active. */ - - /* mask all IOC interrupts */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR); - /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */ - jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR); - - /* clear PCI Soft interrupts */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR); - /* clear PCI Reset interrupts */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - - jmr3927_irq_init(); - - /* setup IOC interrupt 1 (PCI, MODEM) */ - setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); - -#ifdef CONFIG_PCI - setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); -#endif - - /* enable all CPU interrupt bits. */ - set_c0_status(ST0_IM); /* IE bit is still 0. */ -} - -static struct irq_chip jmr3927_irq_ioc = { - .name = "jmr3927_ioc", - .ack = mask_irq_ioc, - .mask = mask_irq_ioc, - .mask_ack = mask_irq_ioc, - .unmask = unmask_irq_ioc, -}; - -static void __init jmr3927_irq_init(void) -{ - u32 i; - - txx9_irq_init(TX3927_IRC_REG); - for (i = 0; i < TXx9_MAX_IR; i++) - txx9_irq_set_pri(i, irc_level[i]); - for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) - set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); -} diff --git a/arch/mips/jmr3927/rbhma3100/kgdb_io.c b/arch/mips/jmr3927/rbhma3100/kgdb_io.c deleted file mode 100644 index 342579c..0000000 --- a/arch/mips/jmr3927/rbhma3100/kgdb_io.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Low level uart routines to directly access a TX[34]927 SIO. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com or source@mvista.com - * - * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include - -#define TIMEOUT 0xffffff - -static int remoteDebugInitialized = 0; -static void debugInit(int baud); - -int putDebugChar(unsigned char c) -{ - int i = 0; - - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(38400); - } - - do { - slow_down(); - i++; - if (i>TIMEOUT) { - break; - } - } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS)); - tx3927_sioptr(0)->tfifo = c; - - return 1; -} - -unsigned char getDebugChar(void) -{ - int i = 0; - int dicr; - char c; - - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(38400); - } - - /* diable RX int. */ - dicr = tx3927_sioptr(0)->dicr; - tx3927_sioptr(0)->dicr = 0; - - do { - slow_down(); - i++; - if (i>TIMEOUT) { - break; - } - } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID) - ; - c = tx3927_sioptr(0)->rfifo; - - /* clear RX int. status */ - tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS; - /* enable RX int. */ - tx3927_sioptr(0)->dicr = dicr; - - return c; -} - -static void debugInit(int baud) -{ - tx3927_sioptr(0)->lcr = 0x020; - tx3927_sioptr(0)->dicr = 0; - tx3927_sioptr(0)->disr = 0x4100; - tx3927_sioptr(0)->cisr = 0x014; - tx3927_sioptr(0)->fcr = 0; - tx3927_sioptr(0)->flcr = 0x02; - tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) | - TXx927_SIBGR_BCLK_T0; -} diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c deleted file mode 100644 index f39c444..0000000 --- a/arch/mips/jmr3927/rbhma3100/setup.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif - -#include -#include -#include -#include -#include - -extern void puts(const char *cp); - -/* don't enable - see errata */ -static int jmr3927_ccfg_toeon; - -static inline void do_reset(void) -{ -#if 1 /* Resetting PCI bus */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); - (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ - mdelay(1); - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); -#endif - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); -} - -static void jmr3927_machine_restart(char *command) -{ - local_irq_disable(); - puts("Rebooting..."); - do_reset(); -} - -static void jmr3927_machine_halt(void) -{ - puts("JMR-TX3927 halted.\n"); - while (1); -} - -static void jmr3927_machine_power_off(void) -{ - puts("JMR-TX3927 halted. Please turn off the power.\n"); - while (1); -} - -void __init plat_time_init(void) -{ - txx9_clockevent_init(TX3927_TMR_REG(0), - TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0), - JMR3927_IMCLK); - txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK); -} - -#define DO_WRITE_THROUGH -#define DO_ENABLE_CACHE - -extern char * __init prom_getcmdline(void); -static void jmr3927_board_init(void); -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; - -void __init plat_mem_setup(void) -{ - char *argptr; - - set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); - - _machine_restart = jmr3927_machine_restart; - _machine_halt = jmr3927_machine_halt; - pm_power_off = jmr3927_machine_power_off; - - /* - * IO/MEM resources. - */ - ioport_resource.start = pci_io_resource.start; - ioport_resource.end = pci_io_resource.end; - iomem_resource.start = 0; - iomem_resource.end = 0xffffffff; - - /* Reboot on panic */ - panic_timeout = 180; - - /* cache setup */ - { - unsigned int conf; -#ifdef DO_ENABLE_CACHE - int mips_ic_disable = 0, mips_dc_disable = 0; -#else - int mips_ic_disable = 1, mips_dc_disable = 1; -#endif -#ifdef DO_WRITE_THROUGH - int mips_config_cwfon = 0; - int mips_config_wbon = 0; -#else - int mips_config_cwfon = 1; - int mips_config_wbon = 1; -#endif - - conf = read_c0_conf(); - conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); - conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; - conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; - conf |= mips_config_wbon ? TX39_CONF_WBON : 0; - conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; - - write_c0_conf(conf); - write_c0_cache(0); - } - - /* initialize board */ - jmr3927_board_init(); - - argptr = prom_getcmdline(); - - if ((argptr = strstr(argptr, "toeon")) != NULL) - jmr3927_ccfg_toeon = 1; - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "ip=")) == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " ip=bootp"); - } - -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - int i; - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i); - req.mapbase = TX3927_SIO_REG(i); - req.irq = i == 0 ? - JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; - if (i == 0) - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = JMR3927_IMCLK; - early_serial_txx9_setup(&req); - } - } -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "console=")) == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS1,115200"); - } -#endif -#endif -} - -static void tx3927_setup(void); - -static void __init jmr3927_board_init(void) -{ - tx3927_setup(); - - /* SIO0 DTR on */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); - - jmr3927_led_set(0); - - printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", - jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, - jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, - jmr3927_dipsw1(), jmr3927_dipsw2(), - jmr3927_dipsw3(), jmr3927_dipsw4()); -} - -static void __init tx3927_setup(void) -{ - int i; -#ifdef CONFIG_PCI - unsigned long mips_pci_io_base = JMR3927_PCIIO; - unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; - unsigned long mips_pci_mem_base = JMR3927_PCIMEM; - unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; - /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ - unsigned long mips_pci_io_pciaddr = 0; -#endif - - /* SDRAMC are configured by PROM */ - - /* ROMC */ - tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; - tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; - tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; - tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; - - /* CCFG */ - /* enable Timeout BusError */ - if (jmr3927_ccfg_toeon) - tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; - - /* clear BusErrorOnWrite flag */ - tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; - /* Disable PCI snoop */ - tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; - /* do reset on watchdog */ - tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; - -#ifdef DO_WRITE_THROUGH - /* Enable PCI SNOOP - with write through only */ - tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; -#endif - - /* Pin selection */ - tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; - tx3927_ccfgptr->pcfg |= - TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | - (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); - - printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", - tx3927_ccfgptr->crir, - tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); - - /* TMR */ - for (i = 0; i < TX3927_NR_TMR; i++) - txx9_tmr_init(TX3927_TMR_REG(i)); - - /* DMA */ - tx3927_dmaptr->mcr = 0; - for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { - /* reset channel */ - tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; - tx3927_dmaptr->ch[i].ccr = 0; - } - /* enable DMA */ -#ifdef __BIG_ENDIAN - tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; -#else - tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; -#endif - -#ifdef CONFIG_PCI - /* PCIC */ - printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", - tx3927_pcicptr->did, tx3927_pcicptr->vid, - tx3927_pcicptr->rid); - if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { - printk("External\n"); - /* XXX */ - } else { - printk("Internal\n"); - - /* Reset PCI Bus */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, - JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - - - /* Disable External PCI Config. Access */ - tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; -#ifdef __BIG_ENDIAN - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | - TX3927_PCIC_LBC_TIBSE | - TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; -#endif - /* LB->PCI mappings */ - tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); - tx3927_pcicptr->ilbioma = mips_pci_io_base; - tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; - tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->ilbmma = mips_pci_mem_base; - tx3927_pcicptr->ipbmma = mips_pci_mem_base; - /* PCI->LB mappings */ - tx3927_pcicptr->iobas = 0xffffffff; - tx3927_pcicptr->ioba = 0; - tx3927_pcicptr->tlbioma = 0; - tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->mba = 0; - tx3927_pcicptr->tlbmma = 0; - /* Enable Direct mapping Address Space Decoder */ - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; - - /* Clear All Local Bus Status */ - tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; - /* Enable All Local Bus Interrupts */ - tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; - /* Clear All PCI Status Error */ - tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; - /* Enable All PCI Status Error Interrupts */ - tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; - - /* PCIC Int => IRC IRQ10 */ - tx3927_pcicptr->il = TX3927_IR_PCI; - /* Target Control (per errata) */ - tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; - - /* Enable Bus Arbiter */ - tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; - - tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - } -#endif /* CONFIG_PCI */ - - /* PIO */ - /* PIO[15:12] connected to LEDs */ - __raw_writel(0x0000f000, &tx3927_pioptr->dir); - __raw_writel(0, &tx3927_pioptr->maskcpu); - __raw_writel(0, &tx3927_pioptr->maskext); - txx9_gpio_init(TX3927_PIO_REG, 0, 16); - gpio_request(11, "dipsw1"); - gpio_request(10, "dipsw2"); - { - unsigned int conf; - - conf = read_c0_conf(); - if (!(conf & TX39_CONF_ICE)) - printk("TX3927 I-Cache disabled.\n"); - if (!(conf & TX39_CONF_DCE)) - printk("TX3927 D-Cache disabled.\n"); - else if (!(conf & TX39_CONF_WBON)) - printk("TX3927 D-Cache WriteThrough.\n"); - else if (!(conf & TX39_CONF_CWFON)) - printk("TX3927 D-Cache WriteBack.\n"); - else - printk("TX3927 D-Cache WriteBack (CWF) .\n"); - } -} - -/* This trick makes rtc-ds1742 driver usable as is. */ -unsigned long __swizzle_addr_b(unsigned long port) -{ - if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR) - return port; - port = (port & 0xffff0000) | (port & 0x7fff << 1); -#ifdef __BIG_ENDIAN - return port; -#else - return port | 1; -#endif -} -EXPORT_SYMBOL(__swizzle_addr_b); - -static int __init jmr3927_rtc_init(void) -{ - static struct resource __initdata res = { - .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, - .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev; - dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(jmr3927_rtc_init); - -/* Watchdog support */ - -static int __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("txx9wdt", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} - -static int __init jmr3927_wdt_init(void) -{ - return txx9_wdt_init(TX3927_TMR_REG(2)); -} -device_initcall(jmr3927_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)JMR3927_IMCLK; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 80fa5ab..4608e43 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o -obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o ops-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index e974394..41dcd6a 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -31,7 +31,7 @@ #include #include -#include +#include int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 2d234ca..26013ba 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -37,7 +37,7 @@ #include #include -#include +#include #undef DEBUG #ifdef DEBUG diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c new file mode 100644 index 0000000..64d4510 --- /dev/null +++ b/arch/mips/pci/fixup-rbtx4938.c @@ -0,0 +1,92 @@ +/* + * Toshiba rbtx4938 pci routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include + +#include + +extern struct pci_controller tx4938_pci_controller[]; + +static int pci_get_irq(const struct pci_dev *dev, int pin) +{ + int irq = pin; + u8 slot = PCI_SLOT(dev->devfn); + struct pci_controller *controller = (struct pci_controller *)dev->sysdata; + + if (controller == &tx4938_pci_controller[1]) { + /* TX4938 PCIC1 */ + switch (slot) { + case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; + break; + case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; + break; + } + return 0; + } + + /* IRQ rotation */ + irq--; /* 0-3 */ + if (dev->bus->parent == NULL && + (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { + /* PCI CardSlot (IDSEL=A23) */ + /* PCIA => PCIA (IDSEL=A23) */ + irq = (irq + 0 + slot) % 4; + } else { + /* PCI Backplane */ + irq = (irq + 33 - slot) % 4; + } + irq++; /* 1-4 */ + + switch (irq) { + case 1: + irq = RBTX4938_IRQ_IOC_PCIA; + break; + case 2: + irq = RBTX4938_IRQ_IOC_PCIB; + break; + case 3: + irq = RBTX4938_IRQ_IOC_PCIC; + break; + case 4: + irq = RBTX4938_IRQ_IOC_PCID; + break; + } + return irq; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + unsigned char irq = 0; + + irq = pci_get_irq(dev, pin); + + printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", + dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn), irq); + + return irq; +} + +/* + * Do platform specific device initialization at pci_enable_device() time + */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c deleted file mode 100644 index f2ba06e..0000000 --- a/arch/mips/pci/fixup-tx4938.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Toshiba rbtx4938 pci routines - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include - -#include - -extern struct pci_controller tx4938_pci_controller[]; - -static int pci_get_irq(const struct pci_dev *dev, int pin) -{ - int irq = pin; - u8 slot = PCI_SLOT(dev->devfn); - struct pci_controller *controller = (struct pci_controller *)dev->sysdata; - - if (controller == &tx4938_pci_controller[1]) { - /* TX4938 PCIC1 */ - switch (slot) { - case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; - break; - case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; - break; - } - return 0; - } - - /* IRQ rotation */ - irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { - /* PCI CardSlot (IDSEL=A23) */ - /* PCIA => PCIA (IDSEL=A23) */ - irq = (irq + 0 + slot) % 4; - } else { - /* PCI Backplane */ - irq = (irq + 33 - slot) % 4; - } - irq++; /* 1-4 */ - - switch (irq) { - case 1: - irq = RBTX4938_IRQ_IOC_PCIA; - break; - case 2: - irq = RBTX4938_IRQ_IOC_PCIB; - break; - case 3: - irq = RBTX4938_IRQ_IOC_PCIC; - break; - case 4: - irq = RBTX4938_IRQ_IOC_PCID; - break; - } - return irq; -} - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned char irq = 0; - - irq = pci_get_irq(dev, pin); - - printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", - dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), irq); - - return irq; -} - -/* - * Do platform specific device initialization at pci_enable_device() time - */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c index aa698bd..5d398f6 100644 --- a/arch/mips/pci/ops-tx3927.c +++ b/arch/mips/pci/ops-tx3927.c @@ -39,7 +39,7 @@ #include #include -#include +#include static inline int mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where) diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 1bbafeb..54730ee 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -40,7 +40,7 @@ #include #include #include -#include +#include /* initialize in setup */ struct resource pci_io_resource = { diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c index a450c40..34494b8 100644 --- a/arch/mips/pci/ops-tx4938.c +++ b/arch/mips/pci/ops-tx4938.c @@ -15,7 +15,7 @@ #include #include -#include +#include /* initialize in setup */ struct resource pci_io_resource = { diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/pci-jmr3927.c index cb84f4e..7fb6bd7 100644 --- a/arch/mips/pci/pci-jmr3927.c +++ b/arch/mips/pci/pci-jmr3927.c @@ -31,7 +31,7 @@ #include #include -#include +#include #include struct resource pci_io_resource = { diff --git a/arch/mips/tx4927/Kconfig b/arch/mips/tx4927/Kconfig deleted file mode 100644 index 5fbbe12..0000000 --- a/arch/mips/tx4927/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config TOSHIBA_FPCIB0 - bool "FPCIB0 Backplane Support" - depends on TOSHIBA_RBTX4927 diff --git a/arch/mips/tx4927/common/Makefile b/arch/mips/tx4927/common/Makefile deleted file mode 100644 index a7fe76a..0000000 --- a/arch/mips/tx4927/common/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Makefile for common code for Toshiba TX4927 based systems -# - -obj-y += tx4927_prom.o tx4927_irq.o - -obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o -obj-$(CONFIG_KGDB) += tx4927_dbgio.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4927/common/smsc_fdc37m81x.c b/arch/mips/tx4927/common/smsc_fdc37m81x.c deleted file mode 100644 index 33f517b..0000000 --- a/arch/mips/tx4927/common/smsc_fdc37m81x.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Interface for smsc fdc48m81x Super IO chip - * - * Author: MontaVista Software, Inc. source@mvista.com - * - * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Copyright 2004 (c) MontaVista Software, Inc. - */ -#include -#include -#include -#include - -#define DEBUG - -/* Common Registers */ -#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 -#define SMSC_FDC37M81X_CONFIG_DATA 0x01 -#define SMSC_FDC37M81X_CONF 0x02 -#define SMSC_FDC37M81X_INDEX 0x03 -#define SMSC_FDC37M81X_DNUM 0x07 -#define SMSC_FDC37M81X_DID 0x20 -#define SMSC_FDC37M81X_DREV 0x21 -#define SMSC_FDC37M81X_PCNT 0x22 -#define SMSC_FDC37M81X_PMGT 0x23 -#define SMSC_FDC37M81X_OSC 0x24 -#define SMSC_FDC37M81X_CONFPA0 0x26 -#define SMSC_FDC37M81X_CONFPA1 0x27 -#define SMSC_FDC37M81X_TEST4 0x2B -#define SMSC_FDC37M81X_TEST5 0x2C -#define SMSC_FDC37M81X_TEST1 0x2D -#define SMSC_FDC37M81X_TEST2 0x2E -#define SMSC_FDC37M81X_TEST3 0x2F - -/* Logical device numbers */ -#define SMSC_FDC37M81X_FDD 0x00 -#define SMSC_FDC37M81X_SERIAL1 0x04 -#define SMSC_FDC37M81X_SERIAL2 0x05 -#define SMSC_FDC37M81X_KBD 0x07 - -/* Logical device Config Registers */ -#define SMSC_FDC37M81X_ACTIVE 0x30 -#define SMSC_FDC37M81X_BASEADDR0 0x60 -#define SMSC_FDC37M81X_BASEADDR1 0x61 -#define SMSC_FDC37M81X_INT 0x70 -#define SMSC_FDC37M81X_INT2 0x72 -#define SMSC_FDC37M81X_MODE 0xF0 - -/* Chip Config Values */ -#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 -#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa -#define SMSC_FDC37M81X_CHIP_ID 0x4d - -static unsigned long g_smsc_fdc37m81x_base = 0; - -static inline unsigned char smsc_fdc37m81x_rd(unsigned char index) -{ - outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); - - return inb(g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); -} - -static inline void smsc_dc37m81x_wr(unsigned char index, unsigned char data) -{ - outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); - outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); -} - -void smsc_fdc37m81x_config_beg(void) -{ - if (g_smsc_fdc37m81x_base) { - outb(SMSC_FDC37M81X_CONFIG_ENTER, - g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); - } -} - -void smsc_fdc37m81x_config_end(void) -{ - if (g_smsc_fdc37m81x_base) - outb(SMSC_FDC37M81X_CONFIG_EXIT, - g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); -} - -u8 smsc_fdc37m81x_config_get(u8 reg) -{ - u8 val = 0; - - if (g_smsc_fdc37m81x_base) - val = smsc_fdc37m81x_rd(reg); - - return val; -} - -void smsc_fdc37m81x_config_set(u8 reg, u8 val) -{ - if (g_smsc_fdc37m81x_base) - smsc_dc37m81x_wr(reg, val); -} - -unsigned long __init smsc_fdc37m81x_init(unsigned long port) -{ - const int field = sizeof(unsigned long) * 2; - u8 chip_id; - - if (g_smsc_fdc37m81x_base) - printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n", - field, g_smsc_fdc37m81x_base); - - g_smsc_fdc37m81x_base = port; - - smsc_fdc37m81x_config_beg(); - - chip_id = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DID); - if (chip_id == SMSC_FDC37M81X_CHIP_ID) - smsc_fdc37m81x_config_end(); - else { - printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n", - chip_id); - g_smsc_fdc37m81x_base = 0; - } - - return g_smsc_fdc37m81x_base; -} - -#ifdef DEBUG -void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg) -{ - printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, - smsc_fdc37m81x_rd(reg)); -} - -void smsc_fdc37m81x_config_dump(void) -{ - u8 orig; - char *fname = "smsc_fdc37m81x_config_dump()"; - - smsc_fdc37m81x_config_beg(); - - orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM); - - printk("%s: common\n", fname); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_DNUM); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_DID); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_DREV); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_PCNT); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_PMGT); - - printk("%s: keyboard\n", fname); - smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_ACTIVE); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_INT); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_INT2); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_LDCR_F0); - - smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, orig); - - smsc_fdc37m81x_config_end(); -} -#endif diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c deleted file mode 100644 index ea1ff23..0000000 --- a/arch/mips/tx4927/common/tx4927_dbgio.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * linux/arch/mips/tx4927/common/tx4927_dbgio.c - * - * kgdb interface for gdb - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include - -u8 getDebugChar(void) -{ - extern u8 txx9_sio_kdbg_rd(void); - return (txx9_sio_kdbg_rd()); -} - -int putDebugChar(u8 byte) -{ - extern int txx9_sio_kdbg_wr( u8 ch ); - return (txx9_sio_kdbg_wr(byte)); -} diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c deleted file mode 100644 index 0aabd57..0000000 --- a/arch/mips/tx4927/common/tx4927_irq.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Common tx4927 irq handler - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#ifdef CONFIG_TOSHIBA_RBTX4927 -#include -#endif - -void __init tx4927_irq_init(void) -{ - mips_cpu_irq_init(); - txx9_irq_init(TX4927_IRC_REG); - set_irq_chained_handler(TX4927_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) /* cpu timer */ - do_IRQ(TX4927_IRQ_CPU_TIMER); - else if (pending & STATUSF_IP2) { /* tx4927 pic */ - int irq = txx9_irq(); -#ifdef CONFIG_TOSHIBA_RBTX4927 - if (irq == TX4927_IRQ_NEST_EXT_ON_PIC) - irq = toshiba_rbtx4927_irq_nested(irq); -#endif - if (unlikely(irq < 0)) { - spurious_interrupt(); - return; - } - do_IRQ(irq); - } else if (pending & STATUSF_IP0) /* user line 0 */ - do_IRQ(TX4927_IRQ_USER0); - else if (pending & STATUSF_IP1) /* user line 1 */ - do_IRQ(TX4927_IRQ_USER1); - else - spurious_interrupt(); -} diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c deleted file mode 100644 index cc2aa9d..0000000 --- a/arch/mips/tx4927/common/tx4927_prom.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * linux/arch/mips/tx4927/common/tx4927_prom.c - * - * common tx4927 memory interface - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include - -static unsigned int __init tx4927_process_sdccr(unsigned long addr) -{ - u64 val; - unsigned int sdccr_ce; - unsigned int sdccr_bs; - unsigned int sdccr_rs; - unsigned int sdccr_cs; - unsigned int sdccr_mw; - unsigned int bs = 0; - unsigned int rs = 0; - unsigned int cs = 0; - unsigned int mw = 0; - unsigned int msize = 0; - - val = __raw_readq((void __iomem *)addr); - - /* MVMCP -- need #defs for these bits masks */ - sdccr_ce = ((val & (1 << 10)) >> 10); - sdccr_bs = ((val & (1 << 8)) >> 8); - sdccr_rs = ((val & (3 << 5)) >> 5); - sdccr_cs = ((val & (3 << 2)) >> 2); - sdccr_mw = ((val & (1 << 0)) >> 0); - - if (sdccr_ce) { - switch (sdccr_bs) { - case 0:{ - bs = 2; - break; - } - case 1:{ - bs = 4; - break; - } - } - switch (sdccr_rs) { - case 0:{ - rs = 2048; - break; - } - case 1:{ - rs = 4096; - break; - } - case 2:{ - rs = 8192; - break; - } - case 3:{ - rs = 0; - break; - } - } - switch (sdccr_cs) { - case 0:{ - cs = 256; - break; - } - case 1:{ - cs = 512; - break; - } - case 2:{ - cs = 1024; - break; - } - case 3:{ - cs = 2048; - break; - } - } - switch (sdccr_mw) { - case 0:{ - mw = 8; - break; - } /* 8 bytes = 64 bits */ - case 1:{ - mw = 4; - break; - } /* 4 bytes = 32 bits */ - } - } - - /* bytes per chip MB per chip num chips */ - msize = (((rs * cs * mw) / (1024 * 1024)) * bs); - - return (msize); -} - - -unsigned int __init tx4927_get_mem_size(void) -{ - unsigned int c0; - unsigned int c1; - unsigned int c2; - unsigned int c3; - unsigned int total; - - /* MVMCP -- need #defs for these registers */ - c0 = tx4927_process_sdccr(0xff1f8000); - c1 = tx4927_process_sdccr(0xff1f8008); - c2 = tx4927_process_sdccr(0xff1f8010); - c3 = tx4927_process_sdccr(0xff1f8018); - total = c0 + c1 + c2 + c3; - - return (total); -} diff --git a/arch/mips/tx4927/toshiba_rbtx4927/Makefile b/arch/mips/tx4927/toshiba_rbtx4927/Makefile deleted file mode 100644 index 13f9672..0000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -obj-y += toshiba_rbtx4927_prom.o -obj-y += toshiba_rbtx4927_setup.o -obj-y += toshiba_rbtx4927_irq.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c deleted file mode 100644 index c18901a..0000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c - * - * Toshiba RBTX4927 specific interrupt handlers - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -/* -IRQ Device -00 RBTX4927-ISA/00 -01 RBTX4927-ISA/01 PS2/Keyboard -02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) -03 RBTX4927-ISA/03 -04 RBTX4927-ISA/04 -05 RBTX4927-ISA/05 -06 RBTX4927-ISA/06 -07 RBTX4927-ISA/07 -08 RBTX4927-ISA/08 -09 RBTX4927-ISA/09 -10 RBTX4927-ISA/10 -11 RBTX4927-ISA/11 -12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time) -13 RBTX4927-ISA/13 -14 RBTX4927-ISA/14 IDE -15 RBTX4927-ISA/15 - -16 TX4927-CP0/00 Software 0 -17 TX4927-CP0/01 Software 1 -18 TX4927-CP0/02 Cascade TX4927-CP0 -19 TX4927-CP0/03 Multiplexed -- do not use -20 TX4927-CP0/04 Multiplexed -- do not use -21 TX4927-CP0/05 Multiplexed -- do not use -22 TX4927-CP0/06 Multiplexed -- do not use -23 TX4927-CP0/07 CPU TIMER - -24 TX4927-PIC/00 -25 TX4927-PIC/01 -26 TX4927-PIC/02 -27 TX4927-PIC/03 Cascade RBTX4927-IOC -28 TX4927-PIC/04 -29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet -30 TX4927-PIC/06 -31 TX4927-PIC/07 -32 TX4927-PIC/08 TX4927 SerialIO Channel 0 -33 TX4927-PIC/09 TX4927 SerialIO Channel 1 -34 TX4927-PIC/10 -35 TX4927-PIC/11 -36 TX4927-PIC/12 -37 TX4927-PIC/13 -38 TX4927-PIC/14 -39 TX4927-PIC/15 -40 TX4927-PIC/16 TX4927 PCI PCI-C -41 TX4927-PIC/17 -42 TX4927-PIC/18 -43 TX4927-PIC/19 -44 TX4927-PIC/20 -45 TX4927-PIC/21 -46 TX4927-PIC/22 TX4927 PCI PCI-ERR -47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) -48 TX4927-PIC/24 -49 TX4927-PIC/25 -50 TX4927-PIC/26 -51 TX4927-PIC/27 -52 TX4927-PIC/28 -53 TX4927-PIC/29 -54 TX4927-PIC/30 -55 TX4927-PIC/31 - -56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4] -57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5] -58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported] -59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6] -60 RBTX4927-IOC/04 -61 RBTX4927-IOC/05 -62 RBTX4927-IOC/06 -63 RBTX4927-IOC/07 - -NOTES: -SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 -SouthBridge/ISA/pin=0 no pci irq used by this device -SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 -SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 -SouthBridge/PMC/pin=0 no pci irq used by this device -SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 -SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) -JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6 -*/ - -#include -#include -#include -#include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif -#include - -#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 -#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 - -#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ -#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ - -#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC -#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) - -extern int tx4927_using_backplane; - -static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); -static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); - -#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" -static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { - .name = TOSHIBA_RBTX4927_IOC_NAME, - .ack = toshiba_rbtx4927_irq_ioc_disable, - .mask = toshiba_rbtx4927_irq_ioc_disable, - .mask_ack = toshiba_rbtx4927_irq_ioc_disable, - .unmask = toshiba_rbtx4927_irq_ioc_enable, -}; -#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL -#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL - -int toshiba_rbtx4927_irq_nested(int sw_irq) -{ - u8 level3; - - level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; - if (level3) { - sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && - tx4927_using_backplane) { - int irq = i8259_irq(); - if (irq >= 0) - sw_irq = irq; - } -#endif - } - return (sw_irq); -} - -static struct irqaction toshiba_rbtx4927_irq_ioc_action = { - .handler = no_action, - .flags = IRQF_SHARED, - .mask = CPU_MASK_NONE, - .name = TOSHIBA_RBTX4927_IOC_NAME -}; - -static void __init toshiba_rbtx4927_irq_ioc_init(void) -{ - int i; - - for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) - set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, - handle_level_irq); - - setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, - &toshiba_rbtx4927_irq_ioc_action); -} - -static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) -{ - unsigned char v; - - v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); - v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); - writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); -} - -static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) -{ - unsigned char v; - - v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); - v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); - writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); - mmiowb(); -} - -void __init arch_init_irq(void) -{ - extern void tx4927_irq_init(void); - - tx4927_irq_init(); - toshiba_rbtx4927_irq_ioc_init(); -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) - init_i8259_irqs(); -#endif - /* Onboard 10M Ether: High Active */ - set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); -} diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c deleted file mode 100644 index fdbad4b..0000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * rbtx4927 specific prom routines - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include - -void __init prom_init_cmdline(void) -{ - int argc = (int) fw_arg0; - char **argv = (char **) fw_arg1; - int i; /* Always ignore the "-c" at argv[0] */ - - /* ignore all built-in args if any f/w args given */ - if (argc > 1) { - *arcs_cmdline = '\0'; - } - - for (i = 1; i < argc; i++) { - if (i != 1) { - strcat(arcs_cmdline, " "); - } - strcat(arcs_cmdline, argv[i]); - } -} - -void __init prom_init(void) -{ - extern int tx4927_get_mem_size(void); - extern char* toshiba_name; - int msize; - - prom_init_cmdline(); - - if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { - mips_machtype = MACH_TOSHIBA_RBTX4927; - toshiba_name = "TX4927"; - } else { - mips_machtype = MACH_TOSHIBA_RBTX4937; - toshiba_name = "TX4937"; - } - - msize = tx4927_get_mem_size(); - add_memory_region(0, msize << 20, BOOT_MEM_RAM); -} - -void __init prom_free_prom_memory(void) -{ -} - -const char *get_system_type(void) -{ - return "Toshiba RBTX4927/RBTX4937"; -} - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c deleted file mode 100644 index 185f303..0000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ /dev/null @@ -1,703 +0,0 @@ -/* - * Toshiba rbtx4927 specific setup - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2002 MontaVista Software Inc. - * Author: Michael Pruznick, michael_pruznick@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif -#include -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif - -/* These functions are used for rebooting or halting the machine*/ -extern void toshiba_rbtx4927_restart(char *command); -extern void toshiba_rbtx4927_halt(void); -extern void toshiba_rbtx4927_power_off(void); - -int tx4927_using_backplane = 0; - -extern void toshiba_rbtx4927_irq_setup(void); - -char *prom_getcmdline(void); - -#ifdef CONFIG_PCI -#undef TX4927_SUPPORT_COMMAND_IO -#undef TX4927_SUPPORT_PCI_66 -int tx4927_cpu_clock = 100000000; /* 100MHz */ -unsigned long mips_pci_io_base; -unsigned long mips_pci_io_size; -unsigned long mips_pci_mem_base; -unsigned long mips_pci_mem_size; -/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ -unsigned long mips_pci_io_pciaddr = 0; -unsigned long mips_memory_upper; -static int tx4927_ccfg_toeon = 1; -static int tx4927_pcic_trdyto = 0; /* default: disabled */ -unsigned long tx4927_ce_base[8]; -int tx4927_pci66 = 0; /* 0:auto */ -#endif - -char *toshiba_name = ""; - -#ifdef CONFIG_PCI -extern struct pci_controller tx4927_controller; - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) -{ - static struct pci_dev dev; - static struct pci_bus bus; - - dev.sysdata = (void *)hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ -} - -EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, dword, u32 *) -EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, dword, u32) - -static int __init tx4927_pcibios_init(void) -{ - unsigned int id; - u32 pci_devfn; - int devfn_start = 0; - int devfn_stop = 0xff; - int busno = 0; /* One bus on the Toshiba */ - struct pci_controller *hose = &tx4927_controller; - - for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { - early_read_config_dword(hose, busno, busno, pci_devfn, - PCI_VENDOR_ID, &id); - - if (id == 0xffffffff) { - continue; - } - - if (id == 0x94601055) { - u8 v08_64; - u32 v32_b0; - u8 v08_e1; - - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x64, &v08_64); - early_read_config_dword(hose, busno, busno, - pci_devfn, 0xb0, &v32_b0); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0xe1, &v08_e1); - - /* serial irq control */ - v08_64 = 0xd0; - - /* serial irq pin */ - v32_b0 |= 0x00010000; - - /* ide irq on isa14 */ - v08_e1 &= 0xf0; - v08_e1 |= 0x0d; - - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x64, v08_64); - early_write_config_dword(hose, busno, busno, - pci_devfn, 0xb0, v32_b0); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0xe1, v08_e1); - } - - if (id == 0x91301055) { - u8 v08_04; - u8 v08_09; - u8 v08_41; - u8 v08_43; - u8 v08_5c; - - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x04, &v08_04); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x09, &v08_09); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x41, &v08_41); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x43, &v08_43); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x5c, &v08_5c); - - /* enable ide master/io */ - v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); - - /* enable ide native mode */ - v08_09 |= 0x05; - - /* enable primary ide */ - v08_41 |= 0x80; - - /* enable secondary ide */ - v08_43 |= 0x80; - - /* - * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! - * - * This line of code is intended to provide the user with a work - * around solution to the anomalies cited in SMSC's anomaly sheet - * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". - * - * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! - */ - v08_5c |= 0x01; - - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x5c, v08_5c); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x04, v08_04); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x09, v08_09); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x41, v08_41); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x43, v08_43); - } - - } - - register_pci_controller(&tx4927_controller); - return 0; -} - -arch_initcall(tx4927_pcibios_init); - -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; - -void __init tx4927_pci_setup(void) -{ - static int called = 0; - extern unsigned int tx4927_get_mem_size(void); - - mips_memory_upper = tx4927_get_mem_size() << 20; - mips_memory_upper += KSEG0; - mips_pci_io_base = TX4927_PCIIO; - mips_pci_io_size = TX4927_PCIIO_SIZE; - mips_pci_mem_base = TX4927_PCIMEM; - mips_pci_mem_size = TX4927_PCIMEM_SIZE; - - if (!called) { - printk - ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", - toshiba_name, - (unsigned short) (tx4927_pcicptr->pciid >> 16), - (unsigned short) (tx4927_pcicptr->pciid & 0xffff), - (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), - (!(tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIXARB)) ? "External" : - "Internal"); - called = 1; - } - printk("%s PCIC --%s PCICLK:", toshiba_name, - (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); - if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { - int pciclk = 0; - if (mips_machtype == MACH_TOSHIBA_RBTX4937) - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { - case TX4937_CCFG_PCIDIVMODE_4: - pciclk = tx4927_cpu_clock / 4; - break; - case TX4937_CCFG_PCIDIVMODE_4_5: - pciclk = tx4927_cpu_clock * 2 / 9; - break; - case TX4937_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4937_CCFG_PCIDIVMODE_5_5: - pciclk = tx4927_cpu_clock * 2 / 11; - break; - case TX4937_CCFG_PCIDIVMODE_8: - pciclk = tx4927_cpu_clock / 8; - break; - case TX4937_CCFG_PCIDIVMODE_9: - pciclk = tx4927_cpu_clock / 9; - break; - case TX4937_CCFG_PCIDIVMODE_10: - pciclk = tx4927_cpu_clock / 10; - break; - case TX4937_CCFG_PCIDIVMODE_11: - pciclk = tx4927_cpu_clock / 11; - break; - } - - else - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { - case TX4927_CCFG_PCIDIVMODE_2_5: - pciclk = tx4927_cpu_clock * 2 / 5; - break; - case TX4927_CCFG_PCIDIVMODE_3: - pciclk = tx4927_cpu_clock / 3; - break; - case TX4927_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4927_CCFG_PCIDIVMODE_6: - pciclk = tx4927_cpu_clock / 6; - break; - } - - printk("Internal(%dMHz)", pciclk / 1000000); - } else - printk("External"); - printk("\n"); - - /* GB->PCI mappings */ - tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; - tx4927_pcicptr->g2piogbase = mips_pci_io_base | -#ifdef __BIG_ENDIAN - TX4927_PCIC_G2PIOGBASE_ECHG -#else - TX4927_PCIC_G2PIOGBASE_BSDIS -#endif - ; - - tx4927_pcicptr->g2piopbase = 0; - - tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4; - tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base | -#ifdef __BIG_ENDIAN - TX4927_PCIC_G2PMnGBASE_ECHG -#else - TX4927_PCIC_G2PMnGBASE_BSDIS -#endif - ; - tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base; - - tx4927_pcicptr->g2pmmask[1] = 0; - tx4927_pcicptr->g2pmgbase[1] = 0; - tx4927_pcicptr->g2pmpbase[1] = 0; - tx4927_pcicptr->g2pmmask[2] = 0; - tx4927_pcicptr->g2pmgbase[2] = 0; - tx4927_pcicptr->g2pmpbase[2] = 0; - - - /* PCI->GB mappings (I/O 256B) */ - tx4927_pcicptr->p2giopbase = 0; /* 256B */ - - /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ - tx4927_pcicptr->p2gm0plbase = 0; - tx4927_pcicptr->p2gm0pubase = 0; - tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN | -#ifdef __BIG_ENDIAN - TX4927_PCIC_P2GMnGBASE_TECHG -#else - TX4927_PCIC_P2GMnGBASE_TBSDIS -#endif - ; - - /* PCI->GB mappings (MEM 16MB) -not used */ - tx4927_pcicptr->p2gm1plbase = 0xffffffff; - tx4927_pcicptr->p2gm1pubase = 0xffffffff; - tx4927_pcicptr->p2gmgbase[1] = 0; - - /* PCI->GB mappings (MEM 1MB) -not used */ - tx4927_pcicptr->p2gm2pbase = 0xffffffff; - tx4927_pcicptr->p2gmgbase[2] = 0; - - - /* Enable Initiator Memory 0 Space, I/O Space, Config */ - tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK; - tx4927_pcicptr->pciccfg |= - TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE | - TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR; - - - /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ - tx4927_pcicptr->pcicfg1 = 0; - - if (tx4927_pcic_trdyto >= 0) { - tx4927_pcicptr->g2ptocnt &= ~0xff; - tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); - } - - /* Clear All Local Bus Status */ - tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL; - /* Enable All Local Bus Interrupts */ - tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL; - /* Clear All Initiator Status */ - tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL; - /* Enable All Initiator Interrupts */ - tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL; - /* Clear All PCI Status Error */ - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr->pcistatus & 0x0000ffff) | - (TX4927_PCIC_PCISTATUS_ALL << 16); - /* Enable All PCI Status Error Interrupts */ - tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL; - - /* PCIC Int => IRC IRQ16 */ - tx4927_pcicptr->pcicfg2 = - (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC; - - if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) { - /* XXX */ - } else { - /* Reset Bus Arbiter */ - tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA; - /* Enable Bus Arbiter */ - tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN; - } - - tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; -} -#endif /* CONFIG_PCI */ - -static void __noreturn wait_forever(void) -{ - while (1) - if (cpu_wait) - (*cpu_wait)(); -} - -void toshiba_rbtx4927_restart(char *command) -{ - printk(KERN_NOTICE "System Rebooting...\n"); - - /* enable the s/w reset register */ - writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); - - /* wait for enable to be seen */ - while ((readb(RBTX4927_SW_RESET_ENABLE) & - RBTX4927_SW_RESET_ENABLE_SET) == 0x00); - - /* do a s/w reset */ - writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); - - /* do something passive while waiting for reset */ - local_irq_disable(); - wait_forever(); - /* no return */ -} - -void toshiba_rbtx4927_halt(void) -{ - printk(KERN_NOTICE "System Halted\n"); - local_irq_disable(); - wait_forever(); - /* no return */ -} - -void toshiba_rbtx4927_power_off(void) -{ - toshiba_rbtx4927_halt(); - /* no return */ -} - -void __init plat_mem_setup(void) -{ - int i; - u32 cp0_config; - char *argptr; - - printk("CPU is %s\n", toshiba_name); - - /* f/w leaves this on at startup */ - clear_c0_status(ST0_ERL); - - /* enable caches -- HCP5 does this, pmon does not */ - cp0_config = read_c0_config(); - cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); - write_c0_config(cp0_config); - - set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); - - ioport_resource.end = 0xffffffff; - iomem_resource.end = 0xffffffff; - - _machine_restart = toshiba_rbtx4927_restart; - _machine_halt = toshiba_rbtx4927_halt; - pm_power_off = toshiba_rbtx4927_power_off; - - for (i = 0; i < TX4927_NR_TMR; i++) - txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); - -#ifdef CONFIG_PCI - - /* PCIC */ - /* - * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. - * - * For TX4927: - * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). - * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) - * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) - * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) - * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) - * i.e. S9[3]: ON (83MHz), OFF (100MHz) - * - * For TX4937: - * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) - * PCIDIVMODE[10] is 0. - * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) - * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) - * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) - * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) - * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) - * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) - * - */ - if (mips_machtype == MACH_TOSHIBA_RBTX4937) - switch ((unsigned long)tx4927_ccfgptr-> - ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { - case TX4937_CCFG_PCIDIVMODE_8: - case TX4937_CCFG_PCIDIVMODE_4: - tx4927_cpu_clock = 266666666; /* 266MHz */ - break; - case TX4937_CCFG_PCIDIVMODE_9: - case TX4937_CCFG_PCIDIVMODE_4_5: - tx4927_cpu_clock = 300000000; /* 300MHz */ - break; - default: - tx4927_cpu_clock = 333333333; /* 333MHz */ - } - else - switch ((unsigned long)tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { - case TX4927_CCFG_PCIDIVMODE_2_5: - case TX4927_CCFG_PCIDIVMODE_5: - tx4927_cpu_clock = 166666666; /* 166MHz */ - break; - default: - tx4927_cpu_clock = 200000000; /* 200MHz */ - } - - /* CCFG */ - /* do reset on watchdog */ - tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR; - /* enable Timeout BusError */ - if (tx4927_ccfg_toeon) - tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; - - tx4927_pci_setup(); - if (tx4927_using_backplane == 1) - printk("backplane board IS installed\n"); - else - printk("No Backplane \n"); - - /* this is on ISA bus behind PCI bus, so need PCI up first */ -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) { - smsc_fdc37m81x_init(0x3f0); - smsc_fdc37m81x_config_beg(); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, - SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, - 1); - smsc_fdc37m81x_config_end(); - } -#endif -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (char *)(0xff1ff300 + i * 0x100); - req.mapbase = 0xff1ff300 + i * 0x100; - req.irq = TX4927_IRQ_PIC_BEG + 8 + i; - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = 50000000; - early_serial_txx9_setup(&req); - } - } -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (strstr(argptr, "console=") == NULL) { - strcat(argptr, " console=ttyS0,38400"); - } -#endif -#endif - -#ifdef CONFIG_ROOT_NFS - argptr = prom_getcmdline(); - if (strstr(argptr, "root=") == NULL) { - strcat(argptr, " root=/dev/nfs rw"); - } -#endif - -#ifdef CONFIG_IP_PNP - argptr = prom_getcmdline(); - if (strstr(argptr, "ip=") == NULL) { - strcat(argptr, " ip=any"); - } -#endif -} - -void __init plat_time_init(void) -{ - mips_hpt_frequency = tx4927_cpu_clock / 2; - if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) - txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, - TXX9_IRQ_BASE + 17, - 50000000); -} - -static int __init toshiba_rbtx4927_rtc_init(void) -{ - static struct resource __initdata res = { - .start = 0x1c010000, - .end = 0x1c010000 + 0x800 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("rtc-ds1742", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(toshiba_rbtx4927_rtc_init); - -static int __init rbtx4927_ne_init(void) -{ - static struct resource __initdata res[] = { - { - .start = RBTX4927_RTL_8019_BASE, - .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, - .flags = IORESOURCE_IO, - }, { - .start = RBTX4927_RTL_8019_IRQ, - .flags = IORESOURCE_IRQ, - } - }; - struct platform_device *dev = - platform_device_register_simple("ne", -1, - res, ARRAY_SIZE(res)); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(rbtx4927_ne_init); - -/* Watchdog support */ - -static int __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("txx9wdt", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} - -static int __init rbtx4927_wdt_init(void) -{ - return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); -} -device_initcall(rbtx4927_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)50000000; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/tx4938/Kconfig b/arch/mips/tx4938/Kconfig deleted file mode 100644 index d90e9cd..0000000 --- a/arch/mips/tx4938/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -if TOSHIBA_RBTX4938 - -comment "Multiplex Pin Select" -choice - prompt "PIO[58:61]" - default TOSHIBA_RBTX4938_MPLEX_PIO58_61 - -config TOSHIBA_RBTX4938_MPLEX_PIO58_61 - bool "PIO" -config TOSHIBA_RBTX4938_MPLEX_NAND - bool "NAND" -config TOSHIBA_RBTX4938_MPLEX_ATA - bool "ATA" - -endchoice - -config TX4938_NAND_BOOT - depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND - bool "NAND Boot Support (EXPERIMENTAL)" - help - This is only for Toshiba RBTX4938 reference board, which has NAND IPL. - Select this option if you need to use NAND boot. - -endif diff --git a/arch/mips/tx4938/common/Makefile b/arch/mips/tx4938/common/Makefile deleted file mode 100644 index 56aa1ed..0000000 --- a/arch/mips/tx4938/common/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for common code for Toshiba TX4927 based systems -# - -obj-y += prom.o irq.o -obj-$(CONFIG_KGDB) += dbgio.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4938/common/dbgio.c b/arch/mips/tx4938/common/dbgio.c deleted file mode 100644 index 33b9c67..0000000 --- a/arch/mips/tx4938/common/dbgio.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/arch/mips/tx4938/common/dbgio.c - * - * kgdb interface for gdb - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Support for TX4938 in 2.6 - Hiroshi DOYU - */ - -#include - -extern u8 txx9_sio_kdbg_rd(void); -extern int txx9_sio_kdbg_wr( u8 ch ); - -u8 getDebugChar(void) -{ - return (txx9_sio_kdbg_rd()); -} - -int putDebugChar(u8 byte) -{ - return (txx9_sio_kdbg_wr(byte)); -} - diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c deleted file mode 100644 index c059b89..0000000 --- a/arch/mips/tx4938/common/irq.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/arch/mips/tx4938/common/irq.c - * - * Common tx4938 irq handler - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include - -void __init -tx4938_irq_init(void) -{ - mips_cpu_irq_init(); - txx9_irq_init(TX4938_IRC_REG); - set_irq_chained_handler(TX4938_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); -} - -int toshiba_rbtx4938_irq_nested(int irq); - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP7) - do_IRQ(TX4938_IRQ_CPU_TIMER); - else if (pending & STATUSF_IP2) { - int irq = txx9_irq(); - if (irq == TX4938_IRQ_PIC_BEG + TX4938_IR_INT(0)) - irq = toshiba_rbtx4938_irq_nested(irq); - if (irq >= 0) - do_IRQ(irq); - else - spurious_interrupt(); - } else if (pending & STATUSF_IP1) - do_IRQ(TX4938_IRQ_USER1); - else if (pending & STATUSF_IP0) - do_IRQ(TX4938_IRQ_USER0); -} diff --git a/arch/mips/tx4938/common/prom.c b/arch/mips/tx4938/common/prom.c deleted file mode 100644 index 20baeae..0000000 --- a/arch/mips/tx4938/common/prom.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * linux/arch/mips/tx4938/common/prom.c - * - * common tx4938 memory interface - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -#include -#include -#include - -static unsigned int __init -tx4938_process_sdccr(u64 * addr) -{ - u64 val; - unsigned int sdccr_ce; - unsigned int sdccr_rs; - unsigned int sdccr_cs; - unsigned int sdccr_mw; - unsigned int rs = 0; - unsigned int cs = 0; - unsigned int mw = 0; - unsigned int bc = 4; - unsigned int msize = 0; - - val = ____raw_readq((void __iomem *)addr); - - /* MVMCP -- need #defs for these bits masks */ - sdccr_ce = ((val & (1 << 10)) >> 10); - sdccr_rs = ((val & (3 << 5)) >> 5); - sdccr_cs = ((val & (7 << 2)) >> 2); - sdccr_mw = ((val & (1 << 0)) >> 0); - - if (sdccr_ce) { - switch (sdccr_rs) { - case 0:{ - rs = 2048; - break; - } - case 1:{ - rs = 4096; - break; - } - case 2:{ - rs = 8192; - break; - } - default:{ - rs = 0; - break; - } - } - switch (sdccr_cs) { - case 0:{ - cs = 256; - break; - } - case 1:{ - cs = 512; - break; - } - case 2:{ - cs = 1024; - break; - } - case 3:{ - cs = 2048; - break; - } - case 4:{ - cs = 4096; - break; - } - default:{ - cs = 0; - break; - } - } - switch (sdccr_mw) { - case 0:{ - mw = 8; - break; - } /* 8 bytes = 64 bits */ - case 1:{ - mw = 4; - break; - } /* 4 bytes = 32 bits */ - } - } - - /* bytes per chip MB per chip bank count */ - msize = (((rs * cs * mw) / (1024 * 1024)) * (bc)); - - /* MVMCP -- bc hard coded to 4 from table 9.3.1 */ - /* boad supports bc=2 but no way to detect */ - - return (msize); -} - -unsigned int __init -tx4938_get_mem_size(void) -{ - unsigned int c0; - unsigned int c1; - unsigned int c2; - unsigned int c3; - unsigned int total; - - /* MVMCP -- need #defs for these registers */ - c0 = tx4938_process_sdccr((u64 *) 0xff1f8000); - c1 = tx4938_process_sdccr((u64 *) 0xff1f8008); - c2 = tx4938_process_sdccr((u64 *) 0xff1f8010); - c3 = tx4938_process_sdccr((u64 *) 0xff1f8018); - total = c0 + c1 + c2 + c3; - - return (total); -} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/Makefile b/arch/mips/tx4938/toshiba_rbtx4938/Makefile deleted file mode 100644 index 2316dd7..0000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for common code for Toshiba TX4927 based systems -# - -obj-y += prom.o setup.o irq.o spi_eeprom.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c deleted file mode 100644 index 4d6a8dc..0000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c - * - * Toshiba RBTX4938 specific interrupt handlers - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -/* -IRQ Device - -16 TX4938-CP0/00 Software 0 -17 TX4938-CP0/01 Software 1 -18 TX4938-CP0/02 Cascade TX4938-CP0 -19 TX4938-CP0/03 Multiplexed -- do not use -20 TX4938-CP0/04 Multiplexed -- do not use -21 TX4938-CP0/05 Multiplexed -- do not use -22 TX4938-CP0/06 Multiplexed -- do not use -23 TX4938-CP0/07 CPU TIMER - -24 TX4938-PIC/00 -25 TX4938-PIC/01 -26 TX4938-PIC/02 Cascade RBTX4938-IOC -27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet -28 TX4938-PIC/04 -29 TX4938-PIC/05 TX4938 ETH1 -30 TX4938-PIC/06 TX4938 ETH0 -31 TX4938-PIC/07 -32 TX4938-PIC/08 TX4938 SIO 0 -33 TX4938-PIC/09 TX4938 SIO 1 -34 TX4938-PIC/10 TX4938 DMA0 -35 TX4938-PIC/11 TX4938 DMA1 -36 TX4938-PIC/12 TX4938 DMA2 -37 TX4938-PIC/13 TX4938 DMA3 -38 TX4938-PIC/14 -39 TX4938-PIC/15 -40 TX4938-PIC/16 TX4938 PCIC -41 TX4938-PIC/17 TX4938 TMR0 -42 TX4938-PIC/18 TX4938 TMR1 -43 TX4938-PIC/19 TX4938 TMR2 -44 TX4938-PIC/20 -45 TX4938-PIC/21 -46 TX4938-PIC/22 TX4938 PCIERR -47 TX4938-PIC/23 -48 TX4938-PIC/24 -49 TX4938-PIC/25 -50 TX4938-PIC/26 -51 TX4938-PIC/27 -52 TX4938-PIC/28 -53 TX4938-PIC/29 -54 TX4938-PIC/30 -55 TX4938-PIC/31 TX4938 SPI - -56 RBTX4938-IOC/00 PCI-D -57 RBTX4938-IOC/01 PCI-C -58 RBTX4938-IOC/02 PCI-B -59 RBTX4938-IOC/03 PCI-A -60 RBTX4938-IOC/04 RTC -61 RBTX4938-IOC/05 ATA -62 RBTX4938-IOC/06 MODEM -63 RBTX4938-IOC/07 SWINT -*/ -#include -#include -#include - -static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); -static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); - -#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" -static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { - .name = TOSHIBA_RBTX4938_IOC_NAME, - .ack = toshiba_rbtx4938_irq_ioc_disable, - .mask = toshiba_rbtx4938_irq_ioc_disable, - .mask_ack = toshiba_rbtx4938_irq_ioc_disable, - .unmask = toshiba_rbtx4938_irq_ioc_enable, -}; - -int -toshiba_rbtx4938_irq_nested(int sw_irq) -{ - u8 level3; - - level3 = readb(rbtx4938_imstat_addr); - if (level3) - /* must use fls so onboard ATA has priority */ - sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; - - return sw_irq; -} - -static struct irqaction toshiba_rbtx4938_irq_ioc_action = { - .handler = no_action, - .flags = 0, - .mask = CPU_MASK_NONE, - .name = TOSHIBA_RBTX4938_IOC_NAME, -}; - -/**********************************************************************************/ -/* Functions for ioc */ -/**********************************************************************************/ -static void __init -toshiba_rbtx4938_irq_ioc_init(void) -{ - int i; - - for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) - set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, - handle_level_irq); - - setup_irq(RBTX4938_IRQ_IOCINT, - &toshiba_rbtx4938_irq_ioc_action); -} - -static void -toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) -{ - unsigned char v; - - v = readb(rbtx4938_imask_addr); - v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); - writeb(v, rbtx4938_imask_addr); - mmiowb(); -} - -static void -toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) -{ - unsigned char v; - - v = readb(rbtx4938_imask_addr); - v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); - writeb(v, rbtx4938_imask_addr); - mmiowb(); -} - -void __init arch_init_irq(void) -{ - extern void tx4938_irq_init(void); - - /* Now, interrupt control disabled, */ - /* all IRC interrupts are masked, */ - /* all IRC interrupt mode are Low Active. */ - - /* mask all IOC interrupts */ - writeb(0, rbtx4938_imask_addr); - - /* clear SoftInt interrupts */ - writeb(0, rbtx4938_softint_addr); - tx4938_irq_init(); - toshiba_rbtx4938_irq_ioc_init(); - /* Onboard 10M Ether: High Active */ - set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); -} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c deleted file mode 100644 index 1644bff..0000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/prom.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c - * - * rbtx4938 specific prom routines - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -#include -#include -#include -#include - -#include -#include -#include - -void __init prom_init_cmdline(void) -{ - int argc = (int) fw_arg0; - char **argv = (char **) fw_arg1; - int i; - - /* ignore all built-in args if any f/w args given */ - if (argc > 1) { - *arcs_cmdline = '\0'; - } - - for (i = 1; i < argc; i++) { - if (i != 1) { - strcat(arcs_cmdline, " "); - } - strcat(arcs_cmdline, argv[i]); - } -} - -void __init prom_init(void) -{ - extern int tx4938_get_mem_size(void); - int msize; -#ifndef CONFIG_TX4938_NAND_BOOT - prom_init_cmdline(); -#endif - - msize = tx4938_get_mem_size(); - add_memory_region(0, msize << 20, BOOT_MEM_RAM); - - return; -} - -void __init prom_free_prom_memory(void) -{ -} - -void __init prom_fixup_mem_map(unsigned long start, unsigned long end) -{ - return; -} - -const char *get_system_type(void) -{ - return "Toshiba RBTX4938"; -} - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c deleted file mode 100644 index 3a3659e..0000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ /dev/null @@ -1,1124 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c - * - * Setup pointers to hardware-dependent routines. - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif -#include -#include -#include - -extern char * __init prom_getcmdline(void); -static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); - -/* These functions are used for rebooting or halting the machine*/ -extern void rbtx4938_machine_restart(char *command); -extern void rbtx4938_machine_halt(void); -extern void rbtx4938_machine_power_off(void); - -/* clocks */ -unsigned int txx9_master_clock; -unsigned int txx9_cpu_clock; -unsigned int txx9_gbus_clock; - -unsigned long rbtx4938_ce_base[8]; -unsigned long rbtx4938_ce_size[8]; -int txboard_pci66_mode; -static int tx4938_pcic_trdyto; /* default: disabled */ -static int tx4938_pcic_retryto; /* default: disabled */ -static int tx4938_ccfg_toeon = 1; - -struct tx4938_pcic_reg *pcicptrs[4] = { - tx4938_pcicptr /* default setting for TX4938 */ -}; - -static struct { - unsigned long base; - unsigned long size; -} phys_regions[16] __initdata; -static int num_phys_regions __initdata; - -#define PHYS_REGION_MINSIZE 0x10000 - -void rbtx4938_machine_halt(void) -{ - printk(KERN_NOTICE "System Halted\n"); - local_irq_disable(); - - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void rbtx4938_machine_power_off(void) -{ - rbtx4938_machine_halt(); - /* no return */ -} - -void rbtx4938_machine_restart(char *command) -{ - local_irq_disable(); - - printk("Rebooting..."); - writeb(1, rbtx4938_softresetlock_addr); - writeb(1, rbtx4938_sfvol_addr); - writeb(1, rbtx4938_softreset_addr); - while(1) - ; -} - -void __init -txboard_add_phys_region(unsigned long base, unsigned long size) -{ - if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { - printk("phys_region overflow\n"); - return; - } - phys_regions[num_phys_regions].base = base; - phys_regions[num_phys_regions].size = size; - num_phys_regions++; -} -unsigned long __init -txboard_find_free_phys_region(unsigned long begin, unsigned long end, - unsigned long size) -{ - unsigned long base; - int i; - - for (base = begin / size * size; base < end; base += size) { - for (i = 0; i < num_phys_regions; i++) { - if (phys_regions[i].size && - base <= phys_regions[i].base + (phys_regions[i].size - 1) && - base + (size - 1) >= phys_regions[i].base) - break; - } - if (i == num_phys_regions) - return base; - } - return 0; -} -unsigned long __init -txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, - unsigned long *size) -{ - unsigned long sz, base; - for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { - base = txboard_find_free_phys_region(begin, end, sz); - if (base) { - *size = sz; - return base; - } - } - return 0; -} -unsigned long __init -txboard_request_phys_region_range(unsigned long begin, unsigned long end, - unsigned long size) -{ - unsigned long base; - base = txboard_find_free_phys_region(begin, end, size); - if (base) - txboard_add_phys_region(base, size); - return base; -} -unsigned long __init -txboard_request_phys_region(unsigned long size) -{ - unsigned long base; - unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ - base = txboard_find_free_phys_region(begin, end, size); - if (base) - txboard_add_phys_region(base, size); - return base; -} -unsigned long __init -txboard_request_phys_region_shrink(unsigned long *size) -{ - unsigned long base; - unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ - base = txboard_find_free_phys_region_shrink(begin, end, size); - if (base) - txboard_add_phys_region(base, *size); - return base; -} - -#ifdef CONFIG_PCI -void __init -tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, - struct pci_controller *channel, - unsigned long pci_io_base, - int extarb) -{ - int i; - - /* Disable All Initiator Space */ - pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| - TX4938_PCIC_PCICCFG_G2PMEN(1)| - TX4938_PCIC_PCICCFG_G2PMEN(2)| - TX4938_PCIC_PCICCFG_G2PIOEN); - - /* GB->PCI mappings */ - pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; - pcicptr->g2piogbase = pci_io_base | -#ifdef __BIG_ENDIAN - TX4938_PCIC_G2PIOGBASE_ECHG -#else - TX4938_PCIC_G2PIOGBASE_BSDIS -#endif - ; - pcicptr->g2piopbase = 0; - for (i = 0; i < 3; i++) { - pcicptr->g2pmmask[i] = 0; - pcicptr->g2pmgbase[i] = 0; - pcicptr->g2pmpbase[i] = 0; - } - if (channel->mem_resource->end) { - pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; - pcicptr->g2pmgbase[0] = channel->mem_resource->start | -#ifdef __BIG_ENDIAN - TX4938_PCIC_G2PMnGBASE_ECHG -#else - TX4938_PCIC_G2PMnGBASE_BSDIS -#endif - ; - pcicptr->g2pmpbase[0] = channel->mem_resource->start; - } - /* PCI->GB mappings (I/O 256B) */ - pcicptr->p2giopbase = 0; /* 256B */ - pcicptr->p2giogbase = 0; - /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ - pcicptr->p2gm0plbase = 0; - pcicptr->p2gm0pubase = 0; - pcicptr->p2gmgbase[0] = 0 | - TX4938_PCIC_P2GMnGBASE_TMEMEN | -#ifdef __BIG_ENDIAN - TX4938_PCIC_P2GMnGBASE_TECHG -#else - TX4938_PCIC_P2GMnGBASE_TBSDIS -#endif - ; - /* PCI->GB mappings (MEM 16MB) */ - pcicptr->p2gm1plbase = 0xffffffff; - pcicptr->p2gm1pubase = 0xffffffff; - pcicptr->p2gmgbase[1] = 0; - /* PCI->GB mappings (MEM 1MB) */ - pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ - pcicptr->p2gmgbase[2] = 0; - - pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; - /* Enable Initiator Memory Space */ - if (channel->mem_resource->end) - pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); - /* Enable Initiator I/O Space */ - if (channel->io_resource->end) - pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; - /* Enable Initiator Config */ - pcicptr->pciccfg |= - TX4938_PCIC_PCICCFG_ICAEN | - TX4938_PCIC_PCICCFG_TCAR; - - /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ - pcicptr->pcicfg1 = 0; - - pcicptr->g2ptocnt &= ~0xffff; - - if (tx4938_pcic_trdyto >= 0) { - pcicptr->g2ptocnt &= ~0xff; - pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); - } - - if (tx4938_pcic_retryto >= 0) { - pcicptr->g2ptocnt &= ~0xff00; - pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); - } - - /* Clear All Local Bus Status */ - pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; - /* Enable All Local Bus Interrupts */ - pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; - /* Clear All Initiator Status */ - pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; - /* Enable All Initiator Interrupts */ - pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; - /* Clear All PCI Status Error */ - pcicptr->pcistatus = - (pcicptr->pcistatus & 0x0000ffff) | - (TX4938_PCIC_PCISTATUS_ALL << 16); - /* Enable All PCI Status Error Interrupts */ - pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; - - if (!extarb) { - /* Reset Bus Arbiter */ - pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; - pcicptr->pbabm = 0; - /* Enable Bus Arbiter */ - pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; - } - - /* PCIC Int => IRC IRQ16 */ - pcicptr->pcicfg2 = - (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; - - pcicptr->pcistatus = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; -} - -int __init -tx4938_report_pciclk(void) -{ - unsigned long pcode = TX4938_REV_PCODE(); - int pciclk = 0; - printk("TX%lx PCIC --%s PCICLK:", - pcode, - (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { - - switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { - case TX4938_CCFG_PCIDIVMODE_4: - pciclk = txx9_cpu_clock / 4; break; - case TX4938_CCFG_PCIDIVMODE_4_5: - pciclk = txx9_cpu_clock * 2 / 9; break; - case TX4938_CCFG_PCIDIVMODE_5: - pciclk = txx9_cpu_clock / 5; break; - case TX4938_CCFG_PCIDIVMODE_5_5: - pciclk = txx9_cpu_clock * 2 / 11; break; - case TX4938_CCFG_PCIDIVMODE_8: - pciclk = txx9_cpu_clock / 8; break; - case TX4938_CCFG_PCIDIVMODE_9: - pciclk = txx9_cpu_clock / 9; break; - case TX4938_CCFG_PCIDIVMODE_10: - pciclk = txx9_cpu_clock / 10; break; - case TX4938_CCFG_PCIDIVMODE_11: - pciclk = txx9_cpu_clock / 11; break; - } - printk("Internal(%dMHz)", pciclk / 1000000); - } else { - printk("External"); - pciclk = -1; - } - printk("\n"); - return pciclk; -} - -void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) -{ - pcicptrs[ch] = pcicptr; -} - -struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) -{ - return pcicptrs[ch]; -} - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) -{ - static struct pci_dev dev; - static struct pci_bus bus; - - dev.sysdata = bus.sysdata = hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ -} - -EARLY_PCI_OP(read, word, u16 *) - -int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) -{ - u32 pci_devfn; - unsigned short vid; - int devfn_start = 0; - int devfn_stop = 0xff; - int cap66 = -1; - u16 stat; - - printk("PCI: Checking 66MHz capabilities...\n"); - - for (pci_devfn=devfn_start; pci_devfn 0; -} - -int __init -tx4938_pciclk66_setup(void) -{ - int pciclk; - - /* Assert M66EN */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; - /* Double PCICLK (if possible) */ - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { - unsigned int pcidivmode = - tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; - switch (pcidivmode) { - case TX4938_CCFG_PCIDIVMODE_8: - case TX4938_CCFG_PCIDIVMODE_4: - pcidivmode = TX4938_CCFG_PCIDIVMODE_4; - pciclk = txx9_cpu_clock / 4; - break; - case TX4938_CCFG_PCIDIVMODE_9: - case TX4938_CCFG_PCIDIVMODE_4_5: - pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; - pciclk = txx9_cpu_clock * 2 / 9; - break; - case TX4938_CCFG_PCIDIVMODE_10: - case TX4938_CCFG_PCIDIVMODE_5: - pcidivmode = TX4938_CCFG_PCIDIVMODE_5; - pciclk = txx9_cpu_clock / 5; - break; - case TX4938_CCFG_PCIDIVMODE_11: - case TX4938_CCFG_PCIDIVMODE_5_5: - default: - pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; - pciclk = txx9_cpu_clock * 2 / 11; - break; - } - tx4938_ccfgptr->ccfg = - (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) - | pcidivmode; - printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", - (unsigned long)tx4938_ccfgptr->ccfg); - } else { - pciclk = -1; - } - return pciclk; -} - -extern struct pci_controller tx4938_pci_controller[]; -static int __init tx4938_pcibios_init(void) -{ - unsigned long mem_base[2]; - unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ - unsigned long io_base[2]; - unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ - /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ - int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); - - PCIBIOS_MIN_IO = 0x00001000UL; - - mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); - io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); - - printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", - (unsigned short)(tx4938_pcicptr->pciid >> 16), - (unsigned short)(tx4938_pcicptr->pciid & 0xffff), - (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), - extarb ? "External" : "Internal"); - - /* setup PCI area */ - tx4938_pci_controller[0].io_resource->start = io_base[0]; - tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; - tx4938_pci_controller[0].mem_resource->start = mem_base[0]; - tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; - - set_tx4938_pcicptr(0, tx4938_pcicptr); - - register_pci_controller(&tx4938_pci_controller[0]); - - if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { - printk("TX4938_CCFG_PCI66 already configured\n"); - txboard_pci66_mode = -1; /* already configured */ - } - - /* Reset PCI Bus */ - writeb(0, rbtx4938_pcireset_addr); - /* Reset PCIC */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; - if (txboard_pci66_mode > 0) - tx4938_pciclk66_setup(); - mdelay(10); - /* clear PCIC reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; - writeb(1, rbtx4938_pcireset_addr); - mmiowb(); - tx4938_report_pcic_status1(tx4938_pcicptr); - - tx4938_report_pciclk(); - tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); - if (txboard_pci66_mode == 0 && - txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { - /* Reset PCI Bus */ - writeb(0, rbtx4938_pcireset_addr); - /* Reset PCIC */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; - tx4938_pciclk66_setup(); - mdelay(10); - /* clear PCIC reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; - writeb(1, rbtx4938_pcireset_addr); - mmiowb(); - /* Reinitialize PCIC */ - tx4938_report_pciclk(); - tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); - } - - mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); - io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); - /* Reset PCIC1 */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; - /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ - if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) - tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; - else - tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; - mdelay(10); - /* clear PCIC1 reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; - tx4938_report_pcic_status1(tx4938_pcic1ptr); - - printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", - (unsigned short)(tx4938_pcic1ptr->pciid >> 16), - (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), - (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); - printk("%s PCICLK:%dMHz\n", - (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", - txx9_gbus_clock / - ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / - 1000000); - - /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ - tx4938_pci_controller[1].io_resource->start = - io_base[1] - io_base[0]; - tx4938_pci_controller[1].io_resource->end = - io_base[1] - io_base[0] + io_size[1] - 1; - tx4938_pci_controller[1].mem_resource->start = mem_base[1]; - tx4938_pci_controller[1].mem_resource->end = - mem_base[1] + mem_size[1] - 1; - set_tx4938_pcicptr(1, tx4938_pcic1ptr); - - register_pci_controller(&tx4938_pci_controller[1]); - - tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); - - /* map ioport 0 to PCI I/O space address 0 */ - set_io_port_base(KSEG1 + io_base[0]); - - return 0; -} - -arch_initcall(tx4938_pcibios_init); - -#endif /* CONFIG_PCI */ - -/* SPI support */ - -/* chip select for SPI devices */ -#define SEEPROM1_CS 7 /* PIO7 */ -#define SEEPROM2_CS 0 /* IOC */ -#define SEEPROM3_CS 1 /* IOC */ -#define SRTC_CS 2 /* IOC */ - -#ifdef CONFIG_PCI -static int __init rbtx4938_ethaddr_init(void) -{ - unsigned char dat[17]; - unsigned char sum; - int i; - - /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ - if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) { - printk(KERN_ERR "seeprom: read error.\n"); - return -ENODEV; - } else { - if (strcmp(dat, "MAC") != 0) - printk(KERN_WARNING "seeprom: bad signature.\n"); - for (i = 0, sum = 0; i < sizeof(dat); i++) - sum += dat[i]; - if (sum) - printk(KERN_WARNING "seeprom: bad checksum.\n"); - } - for (i = 0; i < 2; i++) { - unsigned int id = - TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); - struct platform_device *pdev; - if (!(tx4938_ccfgptr->pcfg & - (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) - continue; - pdev = platform_device_alloc("tc35815-mac", id); - if (!pdev || - platform_device_add_data(pdev, &dat[4 + 6 * i], 6) || - platform_device_add(pdev)) - platform_device_put(pdev); - } - return 0; -} -device_initcall(rbtx4938_ethaddr_init); -#endif /* CONFIG_PCI */ - -static void __init rbtx4938_spi_setup(void) -{ - /* set SPI_SEL */ - tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; -} - -static struct resource rbtx4938_fpga_resource; - -static char pcode_str[8]; -static struct resource tx4938_reg_resource = { - .start = TX4938_REG_BASE, - .end = TX4938_REG_BASE + TX4938_REG_SIZE, - .name = pcode_str, - .flags = IORESOURCE_MEM -}; - -void __init tx4938_board_setup(void) -{ - int i; - unsigned long divmode; - int cpuclk = 0; - unsigned long pcode = TX4938_REV_PCODE(); - - ioport_resource.start = 0x1000; - ioport_resource.end = 0xffffffff; - iomem_resource.start = 0x1000; - iomem_resource.end = 0xffffffff; /* expand to 4GB */ - - sprintf(pcode_str, "TX%lx", pcode); - /* SDRAMC,EBUSC are configured by PROM */ - for (i = 0; i < 8; i++) { - if (!(tx4938_ebuscptr->cr[i] & 0x8)) - continue; /* disabled */ - rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); - txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); - } - - /* clocks */ - if (txx9_master_clock) { - /* calculate gbus_clock and cpu_clock_freq from master_clock */ - divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; - switch (divmode) { - case TX4938_CCFG_DIVMODE_8: - case TX4938_CCFG_DIVMODE_10: - case TX4938_CCFG_DIVMODE_12: - case TX4938_CCFG_DIVMODE_16: - case TX4938_CCFG_DIVMODE_18: - txx9_gbus_clock = txx9_master_clock * 4; break; - default: - txx9_gbus_clock = txx9_master_clock; - } - switch (divmode) { - case TX4938_CCFG_DIVMODE_2: - case TX4938_CCFG_DIVMODE_8: - cpuclk = txx9_gbus_clock * 2; break; - case TX4938_CCFG_DIVMODE_2_5: - case TX4938_CCFG_DIVMODE_10: - cpuclk = txx9_gbus_clock * 5 / 2; break; - case TX4938_CCFG_DIVMODE_3: - case TX4938_CCFG_DIVMODE_12: - cpuclk = txx9_gbus_clock * 3; break; - case TX4938_CCFG_DIVMODE_4: - case TX4938_CCFG_DIVMODE_16: - cpuclk = txx9_gbus_clock * 4; break; - case TX4938_CCFG_DIVMODE_4_5: - case TX4938_CCFG_DIVMODE_18: - cpuclk = txx9_gbus_clock * 9 / 2; break; - } - txx9_cpu_clock = cpuclk; - } else { - if (txx9_cpu_clock == 0) { - txx9_cpu_clock = 300000000; /* 300MHz */ - } - /* calculate gbus_clock and master_clock from cpu_clock_freq */ - cpuclk = txx9_cpu_clock; - divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; - switch (divmode) { - case TX4938_CCFG_DIVMODE_2: - case TX4938_CCFG_DIVMODE_8: - txx9_gbus_clock = cpuclk / 2; break; - case TX4938_CCFG_DIVMODE_2_5: - case TX4938_CCFG_DIVMODE_10: - txx9_gbus_clock = cpuclk * 2 / 5; break; - case TX4938_CCFG_DIVMODE_3: - case TX4938_CCFG_DIVMODE_12: - txx9_gbus_clock = cpuclk / 3; break; - case TX4938_CCFG_DIVMODE_4: - case TX4938_CCFG_DIVMODE_16: - txx9_gbus_clock = cpuclk / 4; break; - case TX4938_CCFG_DIVMODE_4_5: - case TX4938_CCFG_DIVMODE_18: - txx9_gbus_clock = cpuclk * 2 / 9; break; - } - switch (divmode) { - case TX4938_CCFG_DIVMODE_8: - case TX4938_CCFG_DIVMODE_10: - case TX4938_CCFG_DIVMODE_12: - case TX4938_CCFG_DIVMODE_16: - case TX4938_CCFG_DIVMODE_18: - txx9_master_clock = txx9_gbus_clock / 4; break; - default: - txx9_master_clock = txx9_gbus_clock; - } - } - /* change default value to udelay/mdelay take reasonable time */ - loops_per_jiffy = txx9_cpu_clock / HZ / 2; - - /* CCFG */ - /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; - /* do reset on watchdog */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR; - /* clear PCIC1 reset */ - if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; - - /* enable Timeout BusError */ - if (tx4938_ccfg_toeon) - tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; - - /* DMA selection */ - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; - - /* Use external clock for external arbiter */ - if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; - - printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", - pcode_str, - cpuclk / 1000000, txx9_master_clock / 1000000, - (unsigned long)tx4938_ccfgptr->crir, - tx4938_ccfgptr->ccfg, - tx4938_ccfgptr->pcfg); - - printk("%s SDRAMC --", pcode_str); - for (i = 0; i < 4; i++) { - unsigned long long cr = tx4938_sdramcptr->cr[i]; - unsigned long ram_base, ram_size; - if (!((unsigned long)cr & 0x00000400)) - continue; /* disabled */ - ram_base = (unsigned long)(cr >> 49) << 21; - ram_size = ((unsigned long)(cr >> 33) + 1) << 21; - if (ram_base >= 0x20000000) - continue; /* high memory (ignore) */ - printk(" CR%d:%016Lx", i, cr); - txboard_add_phys_region(ram_base, ram_size); - } - printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); - - /* SRAM */ - if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { - unsigned int size = 0x800; - unsigned long base = - (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); - txboard_add_phys_region(base, size); - } - - /* TMR */ - for (i = 0; i < TX4938_NR_TMR; i++) - txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); - - /* enable DMA */ - for (i = 0; i < 2; i++) - ____raw_writeq(TX4938_DMA_MCR_MSTEN, - (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); - - /* PIO */ - __raw_writel(0, &tx4938_pioptr->maskcpu); - __raw_writel(0, &tx4938_pioptr->maskext); - - /* TX4938 internal registers */ - if (request_resource(&iomem_resource, &tx4938_reg_resource)) - printk("request resource for internal registers failed\n"); -} - -#ifdef CONFIG_PCI -static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) -{ - unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); - unsigned long g2pstatus = pcicptr->g2pstatus; - unsigned long pcicstatus = pcicptr->pcicstatus; - static struct { - unsigned long flag; - const char *str; - } pcistat_tbl[] = { - { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, - { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, - { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, - { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, - { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, - { PCI_STATUS_PARITY, "MasterParityError" }, - }, g2pstat_tbl[] = { - { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, - { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, - }, pcicstat_tbl[] = { - { TX4938_PCIC_PCICSTATUS_PME, "PME" }, - { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, - { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, - { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, - { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, - { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, - { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, - { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, - }; - int i; - - printk("pcistat:%04x(", pcistatus); - for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) - if (pcistatus & pcistat_tbl[i].flag) - printk("%s ", pcistat_tbl[i].str); - printk("), g2pstatus:%08lx(", g2pstatus); - for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) - if (g2pstatus & g2pstat_tbl[i].flag) - printk("%s ", g2pstat_tbl[i].str); - printk("), pcicstatus:%08lx(", pcicstatus); - for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) - if (pcicstatus & pcicstat_tbl[i].flag) - printk("%s ", pcicstat_tbl[i].str); - printk(")\n"); -} - -void tx4938_report_pcic_status(void) -{ - int i; - struct tx4938_pcic_reg *pcicptr; - for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) - tx4938_report_pcic_status1(pcicptr); -} - -#endif /* CONFIG_PCI */ - -void __init plat_time_init(void) -{ - mips_hpt_frequency = txx9_cpu_clock / 2; - if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS) - txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, - TXX9_IRQ_BASE + TX4938_IR_TMR(0), - txx9_gbus_clock / 2); -} - -void __init plat_mem_setup(void) -{ - unsigned long long pcfg; - char *argptr; - - iomem_resource.end = 0xffffffff; /* 4GB */ - - if (txx9_master_clock == 0) - txx9_master_clock = 25000000; /* 25MHz */ - tx4938_board_setup(); -#ifndef CONFIG_PCI - set_io_port_base(RBTX4938_ETHER_BASE); -#endif - -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - int i; - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (char *)(0xff1ff300 + i * 0x100); - req.mapbase = 0xff1ff300 + i * 0x100; - req.irq = RBTX4938_IRQ_IRC_SIO(i); - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = 50000000; - early_serial_txx9_setup(&req); - } - } -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (strstr(argptr, "console=") == NULL) { - strcat(argptr, " console=ttyS0,38400"); - } -#endif -#endif - -#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 - printk("PIOSEL: disabling both ata and nand selection\n"); - local_irq_disable(); - tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); -#endif - -#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND - printk("PIOSEL: enabling nand selection\n"); - tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; -#endif - -#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA - printk("PIOSEL: enabling ata selection\n"); - tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; -#endif - -#ifdef CONFIG_IP_PNP - argptr = prom_getcmdline(); - if (strstr(argptr, "ip=") == NULL) { - strcat(argptr, " ip=any"); - } -#endif - - -#ifdef CONFIG_FB - { - conswitchp = &dummy_con; - } -#endif - - rbtx4938_spi_setup(); - pcfg = tx4938_ccfgptr->pcfg; /* updated */ - /* fixup piosel */ - if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == - TX4938_PCFG_ATA_SEL) - writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04, - rbtx4938_piosel_addr); - else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == - TX4938_PCFG_NDF_SEL) - writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08, - rbtx4938_piosel_addr); - else - writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04), - rbtx4938_piosel_addr); - - rbtx4938_fpga_resource.name = "FPGA Registers"; - rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); - rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; - rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; - if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) - printk("request resource for fpga failed\n"); - - _machine_restart = rbtx4938_machine_restart; - _machine_halt = rbtx4938_machine_halt; - pm_power_off = rbtx4938_machine_power_off; - - writeb(0xff, rbtx4938_led_addr); - printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", - readb(rbtx4938_fpga_rev_addr), - readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); -} - -static int __init rbtx4938_ne_init(void) -{ - struct resource res[] = { - { - .start = RBTX4938_RTL_8019_BASE, - .end = RBTX4938_RTL_8019_BASE + 0x20 - 1, - .flags = IORESOURCE_IO, - }, { - .start = RBTX4938_RTL_8019_IRQ, - .flags = IORESOURCE_IRQ, - } - }; - struct platform_device *dev = - platform_device_register_simple("ne", -1, - res, ARRAY_SIZE(res)); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(rbtx4938_ne_init); - -/* GPIO support */ - -int gpio_to_irq(unsigned gpio) -{ - return -EINVAL; -} - -int irq_to_gpio(unsigned irq) -{ - return -EINVAL; -} - -static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock); - -static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) -{ - u8 val; - unsigned long flags; - spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags); - val = readb(rbtx4938_spics_addr); - if (value) - val |= 1 << offset; - else - val &= ~(1 << offset); - writeb(val, rbtx4938_spics_addr); - mmiowb(); - spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags); -} - -static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip, - unsigned int offset, int value) -{ - rbtx4938_spi_gpio_set(chip, offset, value); - return 0; -} - -static struct gpio_chip rbtx4938_spi_gpio_chip = { - .set = rbtx4938_spi_gpio_set, - .direction_output = rbtx4938_spi_gpio_dir_out, - .label = "RBTX4938-SPICS", - .base = 16, - .ngpio = 3, -}; - -/* SPI support */ - -static void __init txx9_spi_init(unsigned long base, int irq) -{ - struct resource res[] = { - { - .start = base, - .end = base + 0x20 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .flags = IORESOURCE_IRQ, - }, - }; - platform_device_register_simple("spi_txx9", 0, - res, ARRAY_SIZE(res)); -} - -static int __init rbtx4938_spi_init(void) -{ - struct spi_board_info srtc_info = { - .modalias = "rtc-rs5c348", - .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */ - .bus_num = 0, - .chip_select = 16 + SRTC_CS, - /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */ - .mode = SPI_MODE_1 | SPI_CS_HIGH, - }; - spi_register_board_info(&srtc_info, 1); - spi_eeprom_register(SEEPROM1_CS); - spi_eeprom_register(16 + SEEPROM2_CS); - spi_eeprom_register(16 + SEEPROM3_CS); - gpio_request(16 + SRTC_CS, "rtc-rs5c348"); - gpio_direction_output(16 + SRTC_CS, 0); - gpio_request(SEEPROM1_CS, "seeprom1"); - gpio_direction_output(SEEPROM1_CS, 1); - gpio_request(16 + SEEPROM2_CS, "seeprom2"); - gpio_direction_output(16 + SEEPROM2_CS, 1); - gpio_request(16 + SEEPROM3_CS, "seeprom3"); - gpio_direction_output(16 + SEEPROM3_CS, 1); - txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI); - return 0; -} - -static int __init rbtx4938_arch_init(void) -{ - txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); - gpiochip_add(&rbtx4938_spi_gpio_chip); - return rbtx4938_spi_init(); -} -arch_initcall(rbtx4938_arch_init); - -/* Watchdog support */ - -static int __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("txx9wdt", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} - -static int __init rbtx4938_wdt_init(void) -{ - return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); -} -device_initcall(rbtx4938_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "spi-baseclk")) - return (struct clk *)(txx9_gbus_clock / 2 / 4); - if (!strcmp(id, "imbus_clk")) - return (struct clk *)(txx9_gbus_clock / 2); - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c deleted file mode 100644 index 4d6b4ad..0000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include - -#define AT250X0_PAGE_SIZE 8 - -/* register board information for at25 driver */ -int __init spi_eeprom_register(int chipid) -{ - static struct spi_eeprom eeprom = { - .name = "at250x0", - .byte_len = 128, - .page_size = AT250X0_PAGE_SIZE, - .flags = EE_ADDR1, - }; - struct spi_board_info info = { - .modalias = "at25", - .max_speed_hz = 1500000, /* 1.5Mbps */ - .bus_num = 0, - .chip_select = chipid, - .platform_data = &eeprom, - /* Mode 0: High-Active, Sample-Then-Shift */ - }; - - return spi_register_board_info(&info, 1); -} - -/* simple temporary spi driver to provide early access to seeprom. */ - -static struct read_param { - int chipid; - int address; - unsigned char *buf; - int len; -} *read_param; - -static int __init early_seeprom_probe(struct spi_device *spi) -{ - int stat = 0; - u8 cmd[2]; - int len = read_param->len; - char *buf = read_param->buf; - int address = read_param->address; - - dev_info(&spi->dev, "spiclk %u KHz.\n", - (spi->max_speed_hz + 500) / 1000); - if (read_param->chipid != spi->chip_select) - return -ENODEV; - while (len > 0) { - /* spi_write_then_read can only work with small chunk */ - int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE; - cmd[0] = 0x03; /* AT25_READ */ - cmd[1] = address; - stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c); - buf += c; - len -= c; - address += c; - } - return stat; -} - -static struct spi_driver early_seeprom_driver __initdata = { - .driver = { - .name = "at25", - .owner = THIS_MODULE, - }, - .probe = early_seeprom_probe, -}; - -int __init spi_eeprom_read(int chipid, int address, - unsigned char *buf, int len) -{ - int ret; - struct read_param param = { - .chipid = chipid, - .address = address, - .buf = buf, - .len = len - }; - - read_param = ¶m; - ret = spi_register_driver(&early_seeprom_driver); - if (!ret) - spi_unregister_driver(&early_seeprom_driver); - return ret; -} diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig new file mode 100644 index 0000000..98d1034 --- /dev/null +++ b/arch/mips/txx9/Kconfig @@ -0,0 +1,28 @@ +config TOSHIBA_FPCIB0 + bool "FPCIB0 Backplane Support" + depends on TOSHIBA_RBTX4927 + +if TOSHIBA_RBTX4938 + +comment "Multiplex Pin Select" +choice + prompt "PIO[58:61]" + default TOSHIBA_RBTX4938_MPLEX_PIO58_61 + +config TOSHIBA_RBTX4938_MPLEX_PIO58_61 + bool "PIO" +config TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND" +config TOSHIBA_RBTX4938_MPLEX_ATA + bool "ATA" + +endchoice + +config TX4938_NAND_BOOT + depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND Boot Support (EXPERIMENTAL)" + help + This is only for Toshiba RBTX4938 reference board, which has NAND IPL. + Select this option if you need to use NAND boot. + +endif diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile new file mode 100644 index 0000000..8cb4a7e --- /dev/null +++ b/arch/mips/txx9/generic/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for common code for TXx9 based systems +# + +obj-$(CONFIG_TOSHIBA_RBTX4927) += mem_tx4927.o irq_tx4927.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += mem_tx4938.o irq_tx4938.o +obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o +obj-$(CONFIG_KGDB) += dbgio.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/generic/dbgio.c b/arch/mips/txx9/generic/dbgio.c new file mode 100644 index 0000000..33b9c67 --- /dev/null +++ b/arch/mips/txx9/generic/dbgio.c @@ -0,0 +1,48 @@ +/* + * linux/arch/mips/tx4938/common/dbgio.c + * + * kgdb interface for gdb + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Support for TX4938 in 2.6 - Hiroshi DOYU + */ + +#include + +extern u8 txx9_sio_kdbg_rd(void); +extern int txx9_sio_kdbg_wr( u8 ch ); + +u8 getDebugChar(void) +{ + return (txx9_sio_kdbg_rd()); +} + +int putDebugChar(u8 byte) +{ + return (txx9_sio_kdbg_wr(byte)); +} + diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c new file mode 100644 index 0000000..685ecc2 --- /dev/null +++ b/arch/mips/txx9/generic/irq_tx4927.c @@ -0,0 +1,64 @@ +/* + * Common tx4927 irq handler + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_RBTX4927 +#include +#endif + +void __init tx4927_irq_init(void) +{ + mips_cpu_irq_init(); + txx9_irq_init(TX4927_IRC_REG); + set_irq_chained_handler(TX4927_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) /* cpu timer */ + do_IRQ(TX4927_IRQ_CPU_TIMER); + else if (pending & STATUSF_IP2) { /* tx4927 pic */ + int irq = txx9_irq(); +#ifdef CONFIG_TOSHIBA_RBTX4927 + if (irq == TX4927_IRQ_NEST_EXT_ON_PIC) + irq = toshiba_rbtx4927_irq_nested(irq); +#endif + if (unlikely(irq < 0)) { + spurious_interrupt(); + return; + } + do_IRQ(irq); + } else if (pending & STATUSF_IP0) /* user line 0 */ + do_IRQ(TX4927_IRQ_USER0); + else if (pending & STATUSF_IP1) /* user line 1 */ + do_IRQ(TX4927_IRQ_USER1); + else + spurious_interrupt(); +} diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c new file mode 100644 index 0000000..0886d91 --- /dev/null +++ b/arch/mips/txx9/generic/irq_tx4938.c @@ -0,0 +1,48 @@ +/* + * linux/arch/mips/tx4938/common/irq.c + * + * Common tx4938 irq handler + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +void __init +tx4938_irq_init(void) +{ + mips_cpu_irq_init(); + txx9_irq_init(TX4938_IRC_REG); + set_irq_chained_handler(TX4938_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); +} + +int toshiba_rbtx4938_irq_nested(int irq); + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status(); + + if (pending & STATUSF_IP7) + do_IRQ(TX4938_IRQ_CPU_TIMER); + else if (pending & STATUSF_IP2) { + int irq = txx9_irq(); + if (irq == TX4938_IRQ_PIC_BEG + TX4938_IR_INT(0)) + irq = toshiba_rbtx4938_irq_nested(irq); + if (irq >= 0) + do_IRQ(irq); + else + spurious_interrupt(); + } else if (pending & STATUSF_IP1) + do_IRQ(TX4938_IRQ_USER1); + else if (pending & STATUSF_IP0) + do_IRQ(TX4938_IRQ_USER0); +} diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c new file mode 100644 index 0000000..12dfc37 --- /dev/null +++ b/arch/mips/txx9/generic/mem_tx4927.c @@ -0,0 +1,141 @@ +/* + * linux/arch/mips/tx4927/common/tx4927_prom.c + * + * common tx4927 memory interface + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +static unsigned int __init tx4927_process_sdccr(unsigned long addr) +{ + u64 val; + unsigned int sdccr_ce; + unsigned int sdccr_bs; + unsigned int sdccr_rs; + unsigned int sdccr_cs; + unsigned int sdccr_mw; + unsigned int bs = 0; + unsigned int rs = 0; + unsigned int cs = 0; + unsigned int mw = 0; + unsigned int msize = 0; + + val = __raw_readq((void __iomem *)addr); + + /* MVMCP -- need #defs for these bits masks */ + sdccr_ce = ((val & (1 << 10)) >> 10); + sdccr_bs = ((val & (1 << 8)) >> 8); + sdccr_rs = ((val & (3 << 5)) >> 5); + sdccr_cs = ((val & (3 << 2)) >> 2); + sdccr_mw = ((val & (1 << 0)) >> 0); + + if (sdccr_ce) { + switch (sdccr_bs) { + case 0:{ + bs = 2; + break; + } + case 1:{ + bs = 4; + break; + } + } + switch (sdccr_rs) { + case 0:{ + rs = 2048; + break; + } + case 1:{ + rs = 4096; + break; + } + case 2:{ + rs = 8192; + break; + } + case 3:{ + rs = 0; + break; + } + } + switch (sdccr_cs) { + case 0:{ + cs = 256; + break; + } + case 1:{ + cs = 512; + break; + } + case 2:{ + cs = 1024; + break; + } + case 3:{ + cs = 2048; + break; + } + } + switch (sdccr_mw) { + case 0:{ + mw = 8; + break; + } /* 8 bytes = 64 bits */ + case 1:{ + mw = 4; + break; + } /* 4 bytes = 32 bits */ + } + } + + /* bytes per chip MB per chip num chips */ + msize = (((rs * cs * mw) / (1024 * 1024)) * bs); + + return (msize); +} + + +unsigned int __init tx4927_get_mem_size(void) +{ + unsigned int c0; + unsigned int c1; + unsigned int c2; + unsigned int c3; + unsigned int total; + + /* MVMCP -- need #defs for these registers */ + c0 = tx4927_process_sdccr(0xff1f8000); + c1 = tx4927_process_sdccr(0xff1f8008); + c2 = tx4927_process_sdccr(0xff1f8010); + c3 = tx4927_process_sdccr(0xff1f8018); + total = c0 + c1 + c2 + c3; + + return (total); +} diff --git a/arch/mips/txx9/generic/mem_tx4938.c b/arch/mips/txx9/generic/mem_tx4938.c new file mode 100644 index 0000000..20baeae --- /dev/null +++ b/arch/mips/txx9/generic/mem_tx4938.c @@ -0,0 +1,124 @@ +/* + * linux/arch/mips/tx4938/common/prom.c + * + * common tx4938 memory interface + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include +#include +#include + +static unsigned int __init +tx4938_process_sdccr(u64 * addr) +{ + u64 val; + unsigned int sdccr_ce; + unsigned int sdccr_rs; + unsigned int sdccr_cs; + unsigned int sdccr_mw; + unsigned int rs = 0; + unsigned int cs = 0; + unsigned int mw = 0; + unsigned int bc = 4; + unsigned int msize = 0; + + val = ____raw_readq((void __iomem *)addr); + + /* MVMCP -- need #defs for these bits masks */ + sdccr_ce = ((val & (1 << 10)) >> 10); + sdccr_rs = ((val & (3 << 5)) >> 5); + sdccr_cs = ((val & (7 << 2)) >> 2); + sdccr_mw = ((val & (1 << 0)) >> 0); + + if (sdccr_ce) { + switch (sdccr_rs) { + case 0:{ + rs = 2048; + break; + } + case 1:{ + rs = 4096; + break; + } + case 2:{ + rs = 8192; + break; + } + default:{ + rs = 0; + break; + } + } + switch (sdccr_cs) { + case 0:{ + cs = 256; + break; + } + case 1:{ + cs = 512; + break; + } + case 2:{ + cs = 1024; + break; + } + case 3:{ + cs = 2048; + break; + } + case 4:{ + cs = 4096; + break; + } + default:{ + cs = 0; + break; + } + } + switch (sdccr_mw) { + case 0:{ + mw = 8; + break; + } /* 8 bytes = 64 bits */ + case 1:{ + mw = 4; + break; + } /* 4 bytes = 32 bits */ + } + } + + /* bytes per chip MB per chip bank count */ + msize = (((rs * cs * mw) / (1024 * 1024)) * (bc)); + + /* MVMCP -- bc hard coded to 4 from table 9.3.1 */ + /* boad supports bc=2 but no way to detect */ + + return (msize); +} + +unsigned int __init +tx4938_get_mem_size(void) +{ + unsigned int c0; + unsigned int c1; + unsigned int c2; + unsigned int c3; + unsigned int total; + + /* MVMCP -- need #defs for these registers */ + c0 = tx4938_process_sdccr((u64 *) 0xff1f8000); + c1 = tx4938_process_sdccr((u64 *) 0xff1f8008); + c2 = tx4938_process_sdccr((u64 *) 0xff1f8010); + c3 = tx4938_process_sdccr((u64 *) 0xff1f8018); + total = c0 + c1 + c2 + c3; + + return (total); +} diff --git a/arch/mips/txx9/generic/smsc_fdc37m81x.c b/arch/mips/txx9/generic/smsc_fdc37m81x.c new file mode 100644 index 0000000..69e4874 --- /dev/null +++ b/arch/mips/txx9/generic/smsc_fdc37m81x.c @@ -0,0 +1,172 @@ +/* + * Interface for smsc fdc48m81x Super IO chip + * + * Author: MontaVista Software, Inc. source@mvista.com + * + * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright 2004 (c) MontaVista Software, Inc. + */ +#include +#include +#include +#include + +#define DEBUG + +/* Common Registers */ +#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 +#define SMSC_FDC37M81X_CONFIG_DATA 0x01 +#define SMSC_FDC37M81X_CONF 0x02 +#define SMSC_FDC37M81X_INDEX 0x03 +#define SMSC_FDC37M81X_DNUM 0x07 +#define SMSC_FDC37M81X_DID 0x20 +#define SMSC_FDC37M81X_DREV 0x21 +#define SMSC_FDC37M81X_PCNT 0x22 +#define SMSC_FDC37M81X_PMGT 0x23 +#define SMSC_FDC37M81X_OSC 0x24 +#define SMSC_FDC37M81X_CONFPA0 0x26 +#define SMSC_FDC37M81X_CONFPA1 0x27 +#define SMSC_FDC37M81X_TEST4 0x2B +#define SMSC_FDC37M81X_TEST5 0x2C +#define SMSC_FDC37M81X_TEST1 0x2D +#define SMSC_FDC37M81X_TEST2 0x2E +#define SMSC_FDC37M81X_TEST3 0x2F + +/* Logical device numbers */ +#define SMSC_FDC37M81X_FDD 0x00 +#define SMSC_FDC37M81X_SERIAL1 0x04 +#define SMSC_FDC37M81X_SERIAL2 0x05 +#define SMSC_FDC37M81X_KBD 0x07 + +/* Logical device Config Registers */ +#define SMSC_FDC37M81X_ACTIVE 0x30 +#define SMSC_FDC37M81X_BASEADDR0 0x60 +#define SMSC_FDC37M81X_BASEADDR1 0x61 +#define SMSC_FDC37M81X_INT 0x70 +#define SMSC_FDC37M81X_INT2 0x72 +#define SMSC_FDC37M81X_MODE 0xF0 + +/* Chip Config Values */ +#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 +#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa +#define SMSC_FDC37M81X_CHIP_ID 0x4d + +static unsigned long g_smsc_fdc37m81x_base = 0; + +static inline unsigned char smsc_fdc37m81x_rd(unsigned char index) +{ + outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); + + return inb(g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); +} + +static inline void smsc_dc37m81x_wr(unsigned char index, unsigned char data) +{ + outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); + outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); +} + +void smsc_fdc37m81x_config_beg(void) +{ + if (g_smsc_fdc37m81x_base) { + outb(SMSC_FDC37M81X_CONFIG_ENTER, + g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); + } +} + +void smsc_fdc37m81x_config_end(void) +{ + if (g_smsc_fdc37m81x_base) + outb(SMSC_FDC37M81X_CONFIG_EXIT, + g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); +} + +u8 smsc_fdc37m81x_config_get(u8 reg) +{ + u8 val = 0; + + if (g_smsc_fdc37m81x_base) + val = smsc_fdc37m81x_rd(reg); + + return val; +} + +void smsc_fdc37m81x_config_set(u8 reg, u8 val) +{ + if (g_smsc_fdc37m81x_base) + smsc_dc37m81x_wr(reg, val); +} + +unsigned long __init smsc_fdc37m81x_init(unsigned long port) +{ + const int field = sizeof(unsigned long) * 2; + u8 chip_id; + + if (g_smsc_fdc37m81x_base) + printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n", + field, g_smsc_fdc37m81x_base); + + g_smsc_fdc37m81x_base = port; + + smsc_fdc37m81x_config_beg(); + + chip_id = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DID); + if (chip_id == SMSC_FDC37M81X_CHIP_ID) + smsc_fdc37m81x_config_end(); + else { + printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n", + chip_id); + g_smsc_fdc37m81x_base = 0; + } + + return g_smsc_fdc37m81x_base; +} + +#ifdef DEBUG +void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg) +{ + printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, + smsc_fdc37m81x_rd(reg)); +} + +void smsc_fdc37m81x_config_dump(void) +{ + u8 orig; + char *fname = "smsc_fdc37m81x_config_dump()"; + + smsc_fdc37m81x_config_beg(); + + orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM); + + printk("%s: common\n", fname); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_DNUM); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_DID); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_DREV); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_PCNT); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_PMGT); + + printk("%s: keyboard\n", fname); + smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_ACTIVE); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_INT); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_INT2); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_LDCR_F0); + + smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, orig); + + smsc_fdc37m81x_config_end(); +} +#endif diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile new file mode 100644 index 0000000..5f83ea3 --- /dev/null +++ b/arch/mips/txx9/jmr3927/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for TOSHIBA JMR-TX3927 board +# + +obj-y += prom.o init.o irq.o setup.o +obj-$(CONFIG_KGDB) += kgdb_io.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/jmr3927/init.c b/arch/mips/txx9/jmr3927/init.c new file mode 100644 index 0000000..1bbb534 --- /dev/null +++ b/arch/mips/txx9/jmr3927/init.c @@ -0,0 +1,57 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * arch/mips/jmr3927/common/init.c + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +extern void __init prom_init_cmdline(void); + +const char *get_system_type(void) +{ + return "Toshiba" +#ifdef CONFIG_TOSHIBA_JMR3927 + " JMR_TX3927" +#endif + ; +} + +extern void puts(const char *cp); + +void __init prom_init(void) +{ +#ifdef CONFIG_TOSHIBA_JMR3927 + /* CCFG */ + if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) + puts("Warning: TX3927 TLB off\n"); +#endif + + prom_init_cmdline(); + add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); +} diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c new file mode 100644 index 0000000..85e1daf --- /dev/null +++ b/arch/mips/txx9/jmr3927/irq.c @@ -0,0 +1,174 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#if JMR3927_IRQ_END > NR_IRQS +#error JMR3927_IRQ_END > NR_IRQS +#endif + +static unsigned char irc_level[TX3927_NUM_IR] = { + 5, 5, 5, 5, 5, 5, /* INT[5:0] */ + 7, 7, /* SIO */ + 5, 5, 5, 0, 0, /* DMA, PIO, PCI */ + 6, 6, 6 /* TMR */ +}; + +/* + * CP0_STATUS is a thread's resource (saved/restored on context switch). + * So disable_irq/enable_irq MUST handle IOC/IRC registers. + */ +static void mask_irq_ioc(unsigned int irq) +{ + /* 0: mask */ + unsigned int irq_nr = irq - JMR3927_IRQ_IOC; + unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); + unsigned int bit = 1 << irq_nr; + jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); + /* flush write buffer */ + (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); +} +static void unmask_irq_ioc(unsigned int irq) +{ + /* 0: mask */ + unsigned int irq_nr = irq - JMR3927_IRQ_IOC; + unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); + unsigned int bit = 1 << irq_nr; + jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); + /* flush write buffer */ + (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long cp0_cause = read_c0_cause(); + int irq; + + if ((cp0_cause & CAUSEF_IP7) == 0) + return; + irq = (cp0_cause >> CAUSEB_IP2) & 0x0f; + + do_IRQ(irq + JMR3927_IRQ_IRC); +} + +static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id) +{ + unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); + int i; + + for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { + if (istat & (1 << i)) { + irq = JMR3927_IRQ_IOC + i; + do_IRQ(irq); + } + } + return IRQ_HANDLED; +} + +static struct irqaction ioc_action = { + .handler = jmr3927_ioc_interrupt, + .mask = CPU_MASK_NONE, + .name = "IOC", +}; + +static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) +{ + printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); + printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", + tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); + + return IRQ_HANDLED; +} +static struct irqaction pcierr_action = { + .handler = jmr3927_pcierr_interrupt, + .mask = CPU_MASK_NONE, + .name = "PCI error", +}; + +static void __init jmr3927_irq_init(void); + +void __init arch_init_irq(void) +{ + /* Now, interrupt control disabled, */ + /* all IRC interrupts are masked, */ + /* all IRC interrupt mode are Low Active. */ + + /* mask all IOC interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR); + /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */ + jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR); + + /* clear PCI Soft interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR); + /* clear PCI Reset interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + + jmr3927_irq_init(); + + /* setup IOC interrupt 1 (PCI, MODEM) */ + setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); + +#ifdef CONFIG_PCI + setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); +#endif + + /* enable all CPU interrupt bits. */ + set_c0_status(ST0_IM); /* IE bit is still 0. */ +} + +static struct irq_chip jmr3927_irq_ioc = { + .name = "jmr3927_ioc", + .ack = mask_irq_ioc, + .mask = mask_irq_ioc, + .mask_ack = mask_irq_ioc, + .unmask = unmask_irq_ioc, +}; + +static void __init jmr3927_irq_init(void) +{ + u32 i; + + txx9_irq_init(TX3927_IRC_REG); + for (i = 0; i < TXx9_MAX_IR; i++) + txx9_irq_set_pri(i, irc_level[i]); + for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) + set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); +} diff --git a/arch/mips/txx9/jmr3927/kgdb_io.c b/arch/mips/txx9/jmr3927/kgdb_io.c new file mode 100644 index 0000000..5bd757e --- /dev/null +++ b/arch/mips/txx9/jmr3927/kgdb_io.c @@ -0,0 +1,105 @@ +/* + * BRIEF MODULE DESCRIPTION + * Low level uart routines to directly access a TX[34]927 SIO. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com or source@mvista.com + * + * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#define TIMEOUT 0xffffff + +static int remoteDebugInitialized = 0; +static void debugInit(int baud); + +int putDebugChar(unsigned char c) +{ + int i = 0; + + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(38400); + } + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(0)->tfifo = c; + + return 1; +} + +unsigned char getDebugChar(void) +{ + int i = 0; + int dicr; + char c; + + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(38400); + } + + /* diable RX int. */ + dicr = tx3927_sioptr(0)->dicr; + tx3927_sioptr(0)->dicr = 0; + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID) + ; + c = tx3927_sioptr(0)->rfifo; + + /* clear RX int. status */ + tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS; + /* enable RX int. */ + tx3927_sioptr(0)->dicr = dicr; + + return c; +} + +static void debugInit(int baud) +{ + tx3927_sioptr(0)->lcr = 0x020; + tx3927_sioptr(0)->dicr = 0; + tx3927_sioptr(0)->disr = 0x4100; + tx3927_sioptr(0)->cisr = 0x014; + tx3927_sioptr(0)->fcr = 0; + tx3927_sioptr(0)->flcr = 0x02; + tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) | + TXx927_SIBGR_BCLK_T0; +} diff --git a/arch/mips/txx9/jmr3927/prom.c b/arch/mips/txx9/jmr3927/prom.c new file mode 100644 index 0000000..8bc1049 --- /dev/null +++ b/arch/mips/txx9/jmr3927/prom.c @@ -0,0 +1,98 @@ +/* + * BRIEF MODULE DESCRIPTION + * PROM library initialisation code, assuming a version of + * pmon is the boot code. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Based on arch/mips/au1000/common/prom.c + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/xx files. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +#include +#include + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + int prom_argc = fw_arg0; + char **prom_argv = (char **) fw_arg1; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while(actr < prom_argc) { + strcpy(cp, prom_argv[actr]); + cp += strlen(prom_argv[actr]); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ + --cp; + *cp = '\0'; +} + +void __init prom_free_prom_memory(void) +{ +} + +#define TIMEOUT 0xffffff + +void +prom_putchar(char c) +{ + int i = 0; + + do { + i++; + if (i>TIMEOUT) + break; + } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(1)->tfifo = c; + return; +} + +void +puts(const char *cp) +{ + while (*cp) + prom_putchar(*cp++); + prom_putchar('\r'); + prom_putchar('\n'); +} diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c new file mode 100644 index 0000000..41e0f3b --- /dev/null +++ b/arch/mips/txx9/jmr3927/setup.c @@ -0,0 +1,445 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#endif + +#include +#include +#include +#include +#include + +extern void puts(const char *cp); + +/* don't enable - see errata */ +static int jmr3927_ccfg_toeon; + +static inline void do_reset(void) +{ +#if 1 /* Resetting PCI bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); + (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ + mdelay(1); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); +#endif + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); +} + +static void jmr3927_machine_restart(char *command) +{ + local_irq_disable(); + puts("Rebooting..."); + do_reset(); +} + +static void jmr3927_machine_halt(void) +{ + puts("JMR-TX3927 halted.\n"); + while (1); +} + +static void jmr3927_machine_power_off(void) +{ + puts("JMR-TX3927 halted. Please turn off the power.\n"); + while (1); +} + +void __init plat_time_init(void) +{ + txx9_clockevent_init(TX3927_TMR_REG(0), + TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0), + JMR3927_IMCLK); + txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK); +} + +#define DO_WRITE_THROUGH +#define DO_ENABLE_CACHE + +extern char * __init prom_getcmdline(void); +static void jmr3927_board_init(void); +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +void __init plat_mem_setup(void) +{ + char *argptr; + + set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); + + _machine_restart = jmr3927_machine_restart; + _machine_halt = jmr3927_machine_halt; + pm_power_off = jmr3927_machine_power_off; + + /* + * IO/MEM resources. + */ + ioport_resource.start = pci_io_resource.start; + ioport_resource.end = pci_io_resource.end; + iomem_resource.start = 0; + iomem_resource.end = 0xffffffff; + + /* Reboot on panic */ + panic_timeout = 180; + + /* cache setup */ + { + unsigned int conf; +#ifdef DO_ENABLE_CACHE + int mips_ic_disable = 0, mips_dc_disable = 0; +#else + int mips_ic_disable = 1, mips_dc_disable = 1; +#endif +#ifdef DO_WRITE_THROUGH + int mips_config_cwfon = 0; + int mips_config_wbon = 0; +#else + int mips_config_cwfon = 1; + int mips_config_wbon = 1; +#endif + + conf = read_c0_conf(); + conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); + conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; + conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; + conf |= mips_config_wbon ? TX39_CONF_WBON : 0; + conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; + + write_c0_conf(conf); + write_c0_cache(0); + } + + /* initialize board */ + jmr3927_board_init(); + + argptr = prom_getcmdline(); + + if ((argptr = strstr(argptr, "toeon")) != NULL) + jmr3927_ccfg_toeon = 1; + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "ip=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " ip=bootp"); + } + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i); + req.mapbase = TX3927_SIO_REG(i); + req.irq = i == 0 ? + JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; + if (i == 0) + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = JMR3927_IMCLK; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "console=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " console=ttyS1,115200"); + } +#endif +#endif +} + +static void tx3927_setup(void); + +static void __init jmr3927_board_init(void) +{ + tx3927_setup(); + + /* SIO0 DTR on */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); + + jmr3927_led_set(0); + + printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", + jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, + jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, + jmr3927_dipsw1(), jmr3927_dipsw2(), + jmr3927_dipsw3(), jmr3927_dipsw4()); +} + +static void __init tx3927_setup(void) +{ + int i; +#ifdef CONFIG_PCI + unsigned long mips_pci_io_base = JMR3927_PCIIO; + unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; + unsigned long mips_pci_mem_base = JMR3927_PCIMEM; + unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; + /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ + unsigned long mips_pci_io_pciaddr = 0; +#endif + + /* SDRAMC are configured by PROM */ + + /* ROMC */ + tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; + tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; + tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; + tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; + + /* CCFG */ + /* enable Timeout BusError */ + if (jmr3927_ccfg_toeon) + tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; + + /* clear BusErrorOnWrite flag */ + tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; + /* Disable PCI snoop */ + tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; + /* do reset on watchdog */ + tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; + +#ifdef DO_WRITE_THROUGH + /* Enable PCI SNOOP - with write through only */ + tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; +#endif + + /* Pin selection */ + tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; + tx3927_ccfgptr->pcfg |= + TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | + (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); + + printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", + tx3927_ccfgptr->crir, + tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); + + /* TMR */ + for (i = 0; i < TX3927_NR_TMR; i++) + txx9_tmr_init(TX3927_TMR_REG(i)); + + /* DMA */ + tx3927_dmaptr->mcr = 0; + for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { + /* reset channel */ + tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; + tx3927_dmaptr->ch[i].ccr = 0; + } + /* enable DMA */ +#ifdef __BIG_ENDIAN + tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; +#else + tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; +#endif + +#ifdef CONFIG_PCI + /* PCIC */ + printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", + tx3927_pcicptr->did, tx3927_pcicptr->vid, + tx3927_pcicptr->rid); + if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { + printk("External\n"); + /* XXX */ + } else { + printk("Internal\n"); + + /* Reset PCI Bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, + JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + + + /* Disable External PCI Config. Access */ + tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; +#ifdef __BIG_ENDIAN + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | + TX3927_PCIC_LBC_TIBSE | + TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; +#endif + /* LB->PCI mappings */ + tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); + tx3927_pcicptr->ilbioma = mips_pci_io_base; + tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; + tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); + tx3927_pcicptr->ilbmma = mips_pci_mem_base; + tx3927_pcicptr->ipbmma = mips_pci_mem_base; + /* PCI->LB mappings */ + tx3927_pcicptr->iobas = 0xffffffff; + tx3927_pcicptr->ioba = 0; + tx3927_pcicptr->tlbioma = 0; + tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); + tx3927_pcicptr->mba = 0; + tx3927_pcicptr->tlbmma = 0; + /* Enable Direct mapping Address Space Decoder */ + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; + + /* Clear All Local Bus Status */ + tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; + /* Enable All Local Bus Interrupts */ + tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; + /* Clear All PCI Status Error */ + tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; + /* Enable All PCI Status Error Interrupts */ + tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; + + /* PCIC Int => IRC IRQ10 */ + tx3927_pcicptr->il = TX3927_IR_PCI; + /* Target Control (per errata) */ + tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; + + /* Enable Bus Arbiter */ + tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; + + tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_IO | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + } +#endif /* CONFIG_PCI */ + + /* PIO */ + /* PIO[15:12] connected to LEDs */ + __raw_writel(0x0000f000, &tx3927_pioptr->dir); + __raw_writel(0, &tx3927_pioptr->maskcpu); + __raw_writel(0, &tx3927_pioptr->maskext); + txx9_gpio_init(TX3927_PIO_REG, 0, 16); + gpio_request(11, "dipsw1"); + gpio_request(10, "dipsw2"); + { + unsigned int conf; + + conf = read_c0_conf(); + if (!(conf & TX39_CONF_ICE)) + printk("TX3927 I-Cache disabled.\n"); + if (!(conf & TX39_CONF_DCE)) + printk("TX3927 D-Cache disabled.\n"); + else if (!(conf & TX39_CONF_WBON)) + printk("TX3927 D-Cache WriteThrough.\n"); + else if (!(conf & TX39_CONF_CWFON)) + printk("TX3927 D-Cache WriteBack.\n"); + else + printk("TX3927 D-Cache WriteBack (CWF) .\n"); + } +} + +/* This trick makes rtc-ds1742 driver usable as is. */ +unsigned long __swizzle_addr_b(unsigned long port) +{ + if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR) + return port; + port = (port & 0xffff0000) | (port & 0x7fff << 1); +#ifdef __BIG_ENDIAN + return port; +#else + return port | 1; +#endif +} +EXPORT_SYMBOL(__swizzle_addr_b); + +static int __init jmr3927_rtc_init(void) +{ + static struct resource __initdata res = { + .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, + .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev; + dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(jmr3927_rtc_init); + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init jmr3927_wdt_init(void) +{ + return txx9_wdt_init(TX3927_TMR_REG(2)); +} +device_initcall(jmr3927_wdt_init); + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "imbus_clk")) + return (struct clk *)JMR3927_IMCLK; + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/txx9/rbtx4927/Makefile b/arch/mips/txx9/rbtx4927/Makefile new file mode 100644 index 0000000..f3e1f59 --- /dev/null +++ b/arch/mips/txx9/rbtx4927/Makefile @@ -0,0 +1,3 @@ +obj-y += prom.o setup.o irq.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c new file mode 100644 index 0000000..936e50e --- /dev/null +++ b/arch/mips/txx9/rbtx4927/irq.c @@ -0,0 +1,214 @@ +/* + * Toshiba RBTX4927 specific interrupt handlers + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* +IRQ Device +00 RBTX4927-ISA/00 +01 RBTX4927-ISA/01 PS2/Keyboard +02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) +03 RBTX4927-ISA/03 +04 RBTX4927-ISA/04 +05 RBTX4927-ISA/05 +06 RBTX4927-ISA/06 +07 RBTX4927-ISA/07 +08 RBTX4927-ISA/08 +09 RBTX4927-ISA/09 +10 RBTX4927-ISA/10 +11 RBTX4927-ISA/11 +12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time) +13 RBTX4927-ISA/13 +14 RBTX4927-ISA/14 IDE +15 RBTX4927-ISA/15 + +16 TX4927-CP0/00 Software 0 +17 TX4927-CP0/01 Software 1 +18 TX4927-CP0/02 Cascade TX4927-CP0 +19 TX4927-CP0/03 Multiplexed -- do not use +20 TX4927-CP0/04 Multiplexed -- do not use +21 TX4927-CP0/05 Multiplexed -- do not use +22 TX4927-CP0/06 Multiplexed -- do not use +23 TX4927-CP0/07 CPU TIMER + +24 TX4927-PIC/00 +25 TX4927-PIC/01 +26 TX4927-PIC/02 +27 TX4927-PIC/03 Cascade RBTX4927-IOC +28 TX4927-PIC/04 +29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet +30 TX4927-PIC/06 +31 TX4927-PIC/07 +32 TX4927-PIC/08 TX4927 SerialIO Channel 0 +33 TX4927-PIC/09 TX4927 SerialIO Channel 1 +34 TX4927-PIC/10 +35 TX4927-PIC/11 +36 TX4927-PIC/12 +37 TX4927-PIC/13 +38 TX4927-PIC/14 +39 TX4927-PIC/15 +40 TX4927-PIC/16 TX4927 PCI PCI-C +41 TX4927-PIC/17 +42 TX4927-PIC/18 +43 TX4927-PIC/19 +44 TX4927-PIC/20 +45 TX4927-PIC/21 +46 TX4927-PIC/22 TX4927 PCI PCI-ERR +47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) +48 TX4927-PIC/24 +49 TX4927-PIC/25 +50 TX4927-PIC/26 +51 TX4927-PIC/27 +52 TX4927-PIC/28 +53 TX4927-PIC/29 +54 TX4927-PIC/30 +55 TX4927-PIC/31 + +56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4] +57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5] +58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported] +59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6] +60 RBTX4927-IOC/04 +61 RBTX4927-IOC/05 +62 RBTX4927-IOC/06 +63 RBTX4927-IOC/07 + +NOTES: +SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 +SouthBridge/ISA/pin=0 no pci irq used by this device +SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 +SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 +SouthBridge/PMC/pin=0 no pci irq used by this device +SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 +SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) +JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6 +*/ + +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#endif +#include + +#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 +#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 + +#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ +#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ + +#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC +#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) + +extern int tx4927_using_backplane; + +static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); +static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); + +#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" +static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { + .name = TOSHIBA_RBTX4927_IOC_NAME, + .ack = toshiba_rbtx4927_irq_ioc_disable, + .mask = toshiba_rbtx4927_irq_ioc_disable, + .mask_ack = toshiba_rbtx4927_irq_ioc_disable, + .unmask = toshiba_rbtx4927_irq_ioc_enable, +}; +#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL +#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL + +int toshiba_rbtx4927_irq_nested(int sw_irq) +{ + u8 level3; + + level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; + if (level3) { + sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; +#ifdef CONFIG_TOSHIBA_FPCIB0 + if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && + tx4927_using_backplane) { + int irq = i8259_irq(); + if (irq >= 0) + sw_irq = irq; + } +#endif + } + return (sw_irq); +} + +static struct irqaction toshiba_rbtx4927_irq_ioc_action = { + .handler = no_action, + .flags = IRQF_SHARED, + .mask = CPU_MASK_NONE, + .name = TOSHIBA_RBTX4927_IOC_NAME +}; + +static void __init toshiba_rbtx4927_irq_ioc_init(void) +{ + int i; + + for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; + i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) + set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, + handle_level_irq); + + setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, + &toshiba_rbtx4927_irq_ioc_action); +} + +static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) +{ + unsigned char v; + + v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); +} + +static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) +{ + unsigned char v; + + v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); + mmiowb(); +} + +void __init arch_init_irq(void) +{ + extern void tx4927_irq_init(void); + + tx4927_irq_init(); + toshiba_rbtx4927_irq_ioc_init(); +#ifdef CONFIG_TOSHIBA_FPCIB0 + if (tx4927_using_backplane) + init_i8259_irqs(); +#endif + /* Onboard 10M Ether: High Active */ + set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); +} diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c new file mode 100644 index 0000000..0020bbe --- /dev/null +++ b/arch/mips/txx9/rbtx4927/prom.c @@ -0,0 +1,91 @@ +/* + * rbtx4927 specific prom routines + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include + +void __init prom_init_cmdline(void) +{ + int argc = (int) fw_arg0; + char **argv = (char **) fw_arg1; + int i; /* Always ignore the "-c" at argv[0] */ + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) { + *arcs_cmdline = '\0'; + } + + for (i = 1; i < argc; i++) { + if (i != 1) { + strcat(arcs_cmdline, " "); + } + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + extern int tx4927_get_mem_size(void); + extern char* toshiba_name; + int msize; + + prom_init_cmdline(); + + if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { + mips_machtype = MACH_TOSHIBA_RBTX4927; + toshiba_name = "TX4927"; + } else { + mips_machtype = MACH_TOSHIBA_RBTX4937; + toshiba_name = "TX4937"; + } + + msize = tx4927_get_mem_size(); + add_memory_region(0, msize << 20, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ +} + +const char *get_system_type(void) +{ + return "Toshiba RBTX4927/RBTX4937"; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c new file mode 100644 index 0000000..df1b6e9 --- /dev/null +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -0,0 +1,703 @@ +/* + * Toshiba rbtx4927 specific setup + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2002 MontaVista Software Inc. + * Author: Michael Pruznick, michael_pruznick@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#endif +#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#endif + +/* These functions are used for rebooting or halting the machine*/ +extern void toshiba_rbtx4927_restart(char *command); +extern void toshiba_rbtx4927_halt(void); +extern void toshiba_rbtx4927_power_off(void); + +int tx4927_using_backplane = 0; + +extern void toshiba_rbtx4927_irq_setup(void); + +char *prom_getcmdline(void); + +#ifdef CONFIG_PCI +#undef TX4927_SUPPORT_COMMAND_IO +#undef TX4927_SUPPORT_PCI_66 +int tx4927_cpu_clock = 100000000; /* 100MHz */ +unsigned long mips_pci_io_base; +unsigned long mips_pci_io_size; +unsigned long mips_pci_mem_base; +unsigned long mips_pci_mem_size; +/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ +unsigned long mips_pci_io_pciaddr = 0; +unsigned long mips_memory_upper; +static int tx4927_ccfg_toeon = 1; +static int tx4927_pcic_trdyto = 0; /* default: disabled */ +unsigned long tx4927_ce_base[8]; +int tx4927_pci66 = 0; /* 0:auto */ +#endif + +char *toshiba_name = ""; + +#ifdef CONFIG_PCI +extern struct pci_controller tx4927_controller; + +static struct pci_dev *fake_pci_dev(struct pci_controller *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.sysdata = (void *)hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + bus.parent = NULL; + dev.bus = &bus; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +static int early_##rw##_config_##size(struct pci_controller *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, byte, u8 *) +EARLY_PCI_OP(read, dword, u32 *) +EARLY_PCI_OP(write, byte, u8) +EARLY_PCI_OP(write, dword, u32) + +static int __init tx4927_pcibios_init(void) +{ + unsigned int id; + u32 pci_devfn; + int devfn_start = 0; + int devfn_stop = 0xff; + int busno = 0; /* One bus on the Toshiba */ + struct pci_controller *hose = &tx4927_controller; + + for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { + early_read_config_dword(hose, busno, busno, pci_devfn, + PCI_VENDOR_ID, &id); + + if (id == 0xffffffff) { + continue; + } + + if (id == 0x94601055) { + u8 v08_64; + u32 v32_b0; + u8 v08_e1; + + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x64, &v08_64); + early_read_config_dword(hose, busno, busno, + pci_devfn, 0xb0, &v32_b0); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0xe1, &v08_e1); + + /* serial irq control */ + v08_64 = 0xd0; + + /* serial irq pin */ + v32_b0 |= 0x00010000; + + /* ide irq on isa14 */ + v08_e1 &= 0xf0; + v08_e1 |= 0x0d; + + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x64, v08_64); + early_write_config_dword(hose, busno, busno, + pci_devfn, 0xb0, v32_b0); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0xe1, v08_e1); + } + + if (id == 0x91301055) { + u8 v08_04; + u8 v08_09; + u8 v08_41; + u8 v08_43; + u8 v08_5c; + + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x04, &v08_04); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x09, &v08_09); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x41, &v08_41); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x43, &v08_43); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x5c, &v08_5c); + + /* enable ide master/io */ + v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + /* enable ide native mode */ + v08_09 |= 0x05; + + /* enable primary ide */ + v08_41 |= 0x80; + + /* enable secondary ide */ + v08_43 |= 0x80; + + /* + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + * + * This line of code is intended to provide the user with a work + * around solution to the anomalies cited in SMSC's anomaly sheet + * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". + * + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + */ + v08_5c |= 0x01; + + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x5c, v08_5c); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x04, v08_04); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x09, v08_09); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x41, v08_41); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x43, v08_43); + } + + } + + register_pci_controller(&tx4927_controller); + return 0; +} + +arch_initcall(tx4927_pcibios_init); + +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +void __init tx4927_pci_setup(void) +{ + static int called = 0; + extern unsigned int tx4927_get_mem_size(void); + + mips_memory_upper = tx4927_get_mem_size() << 20; + mips_memory_upper += KSEG0; + mips_pci_io_base = TX4927_PCIIO; + mips_pci_io_size = TX4927_PCIIO_SIZE; + mips_pci_mem_base = TX4927_PCIMEM; + mips_pci_mem_size = TX4927_PCIMEM_SIZE; + + if (!called) { + printk + ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + toshiba_name, + (unsigned short) (tx4927_pcicptr->pciid >> 16), + (unsigned short) (tx4927_pcicptr->pciid & 0xffff), + (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), + (!(tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIXARB)) ? "External" : + "Internal"); + called = 1; + } + printk("%s PCIC --%s PCICLK:", toshiba_name, + (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); + if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { + int pciclk = 0; + if (mips_machtype == MACH_TOSHIBA_RBTX4937) + switch ((unsigned long) tx4927_ccfgptr-> + ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { + case TX4937_CCFG_PCIDIVMODE_4: + pciclk = tx4927_cpu_clock / 4; + break; + case TX4937_CCFG_PCIDIVMODE_4_5: + pciclk = tx4927_cpu_clock * 2 / 9; + break; + case TX4937_CCFG_PCIDIVMODE_5: + pciclk = tx4927_cpu_clock / 5; + break; + case TX4937_CCFG_PCIDIVMODE_5_5: + pciclk = tx4927_cpu_clock * 2 / 11; + break; + case TX4937_CCFG_PCIDIVMODE_8: + pciclk = tx4927_cpu_clock / 8; + break; + case TX4937_CCFG_PCIDIVMODE_9: + pciclk = tx4927_cpu_clock / 9; + break; + case TX4937_CCFG_PCIDIVMODE_10: + pciclk = tx4927_cpu_clock / 10; + break; + case TX4937_CCFG_PCIDIVMODE_11: + pciclk = tx4927_cpu_clock / 11; + break; + } + + else + switch ((unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + pciclk = tx4927_cpu_clock * 2 / 5; + break; + case TX4927_CCFG_PCIDIVMODE_3: + pciclk = tx4927_cpu_clock / 3; + break; + case TX4927_CCFG_PCIDIVMODE_5: + pciclk = tx4927_cpu_clock / 5; + break; + case TX4927_CCFG_PCIDIVMODE_6: + pciclk = tx4927_cpu_clock / 6; + break; + } + + printk("Internal(%dMHz)", pciclk / 1000000); + } else + printk("External"); + printk("\n"); + + /* GB->PCI mappings */ + tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; + tx4927_pcicptr->g2piogbase = mips_pci_io_base | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PIOGBASE_ECHG +#else + TX4927_PCIC_G2PIOGBASE_BSDIS +#endif + ; + + tx4927_pcicptr->g2piopbase = 0; + + tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4; + tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PMnGBASE_ECHG +#else + TX4927_PCIC_G2PMnGBASE_BSDIS +#endif + ; + tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base; + + tx4927_pcicptr->g2pmmask[1] = 0; + tx4927_pcicptr->g2pmgbase[1] = 0; + tx4927_pcicptr->g2pmpbase[1] = 0; + tx4927_pcicptr->g2pmmask[2] = 0; + tx4927_pcicptr->g2pmgbase[2] = 0; + tx4927_pcicptr->g2pmpbase[2] = 0; + + + /* PCI->GB mappings (I/O 256B) */ + tx4927_pcicptr->p2giopbase = 0; /* 256B */ + + /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ + tx4927_pcicptr->p2gm0plbase = 0; + tx4927_pcicptr->p2gm0pubase = 0; + tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4927_PCIC_P2GMnGBASE_TECHG +#else + TX4927_PCIC_P2GMnGBASE_TBSDIS +#endif + ; + + /* PCI->GB mappings (MEM 16MB) -not used */ + tx4927_pcicptr->p2gm1plbase = 0xffffffff; + tx4927_pcicptr->p2gm1pubase = 0xffffffff; + tx4927_pcicptr->p2gmgbase[1] = 0; + + /* PCI->GB mappings (MEM 1MB) -not used */ + tx4927_pcicptr->p2gm2pbase = 0xffffffff; + tx4927_pcicptr->p2gmgbase[2] = 0; + + + /* Enable Initiator Memory 0 Space, I/O Space, Config */ + tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK; + tx4927_pcicptr->pciccfg |= + TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE | + TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR; + + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + tx4927_pcicptr->pcicfg1 = 0; + + if (tx4927_pcic_trdyto >= 0) { + tx4927_pcicptr->g2ptocnt &= ~0xff; + tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); + } + + /* Clear All Local Bus Status */ + tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL; + /* Enable All Local Bus Interrupts */ + tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL; + /* Clear All Initiator Status */ + tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL; + /* Enable All Initiator Interrupts */ + tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL; + /* Clear All PCI Status Error */ + tx4927_pcicptr->pcistatus = + (tx4927_pcicptr->pcistatus & 0x0000ffff) | + (TX4927_PCIC_PCISTATUS_ALL << 16); + /* Enable All PCI Status Error Interrupts */ + tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL; + + /* PCIC Int => IRC IRQ16 */ + tx4927_pcicptr->pcicfg2 = + (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC; + + if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) { + /* XXX */ + } else { + /* Reset Bus Arbiter */ + tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA; + /* Enable Bus Arbiter */ + tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN; + } + + tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; +} +#endif /* CONFIG_PCI */ + +static void __noreturn wait_forever(void) +{ + while (1) + if (cpu_wait) + (*cpu_wait)(); +} + +void toshiba_rbtx4927_restart(char *command) +{ + printk(KERN_NOTICE "System Rebooting...\n"); + + /* enable the s/w reset register */ + writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); + + /* wait for enable to be seen */ + while ((readb(RBTX4927_SW_RESET_ENABLE) & + RBTX4927_SW_RESET_ENABLE_SET) == 0x00); + + /* do a s/w reset */ + writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); + + /* do something passive while waiting for reset */ + local_irq_disable(); + wait_forever(); + /* no return */ +} + +void toshiba_rbtx4927_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + wait_forever(); + /* no return */ +} + +void toshiba_rbtx4927_power_off(void) +{ + toshiba_rbtx4927_halt(); + /* no return */ +} + +void __init plat_mem_setup(void) +{ + int i; + u32 cp0_config; + char *argptr; + + printk("CPU is %s\n", toshiba_name); + + /* f/w leaves this on at startup */ + clear_c0_status(ST0_ERL); + + /* enable caches -- HCP5 does this, pmon does not */ + cp0_config = read_c0_config(); + cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); + write_c0_config(cp0_config); + + set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); + + ioport_resource.end = 0xffffffff; + iomem_resource.end = 0xffffffff; + + _machine_restart = toshiba_rbtx4927_restart; + _machine_halt = toshiba_rbtx4927_halt; + pm_power_off = toshiba_rbtx4927_power_off; + + for (i = 0; i < TX4927_NR_TMR; i++) + txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); + +#ifdef CONFIG_PCI + + /* PCIC */ + /* + * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. + * + * For TX4927: + * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). + * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) + * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) + * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) + * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) + * i.e. S9[3]: ON (83MHz), OFF (100MHz) + * + * For TX4937: + * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) + * PCIDIVMODE[10] is 0. + * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) + * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) + * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) + * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) + * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) + * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) + * + */ + if (mips_machtype == MACH_TOSHIBA_RBTX4937) + switch ((unsigned long)tx4927_ccfgptr-> + ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { + case TX4937_CCFG_PCIDIVMODE_8: + case TX4937_CCFG_PCIDIVMODE_4: + tx4927_cpu_clock = 266666666; /* 266MHz */ + break; + case TX4937_CCFG_PCIDIVMODE_9: + case TX4937_CCFG_PCIDIVMODE_4_5: + tx4927_cpu_clock = 300000000; /* 300MHz */ + break; + default: + tx4927_cpu_clock = 333333333; /* 333MHz */ + } + else + switch ((unsigned long)tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + case TX4927_CCFG_PCIDIVMODE_5: + tx4927_cpu_clock = 166666666; /* 166MHz */ + break; + default: + tx4927_cpu_clock = 200000000; /* 200MHz */ + } + + /* CCFG */ + /* do reset on watchdog */ + tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR; + /* enable Timeout BusError */ + if (tx4927_ccfg_toeon) + tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; + + tx4927_pci_setup(); + if (tx4927_using_backplane == 1) + printk("backplane board IS installed\n"); + else + printk("No Backplane \n"); + + /* this is on ISA bus behind PCI bus, so need PCI up first */ +#ifdef CONFIG_TOSHIBA_FPCIB0 + if (tx4927_using_backplane) { + smsc_fdc37m81x_init(0x3f0); + smsc_fdc37m81x_config_beg(); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, + SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, + 1); + smsc_fdc37m81x_config_end(); + } +#endif +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)(0xff1ff300 + i * 0x100); + req.mapbase = 0xff1ff300 + i * 0x100; + req.irq = TX4927_IRQ_PIC_BEG + 8 + i; + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = 50000000; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } +#endif +#endif + +#ifdef CONFIG_ROOT_NFS + argptr = prom_getcmdline(); + if (strstr(argptr, "root=") == NULL) { + strcat(argptr, " root=/dev/nfs rw"); + } +#endif + +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } +#endif +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = tx4927_cpu_clock / 2; + if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) + txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, + TXX9_IRQ_BASE + 17, + 50000000); +} + +static int __init toshiba_rbtx4927_rtc_init(void) +{ + static struct resource __initdata res = { + .start = 0x1c010000, + .end = 0x1c010000 + 0x800 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("rtc-ds1742", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(toshiba_rbtx4927_rtc_init); + +static int __init rbtx4927_ne_init(void) +{ + static struct resource __initdata res[] = { + { + .start = RBTX4927_RTL_8019_BASE, + .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, + .flags = IORESOURCE_IO, + }, { + .start = RBTX4927_RTL_8019_IRQ, + .flags = IORESOURCE_IRQ, + } + }; + struct platform_device *dev = + platform_device_register_simple("ne", -1, + res, ARRAY_SIZE(res)); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(rbtx4927_ne_init); + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init rbtx4927_wdt_init(void) +{ + return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); +} +device_initcall(rbtx4927_wdt_init); + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "imbus_clk")) + return (struct clk *)50000000; + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/txx9/rbtx4938/Makefile b/arch/mips/txx9/rbtx4938/Makefile new file mode 100644 index 0000000..9dcc52a --- /dev/null +++ b/arch/mips/txx9/rbtx4938/Makefile @@ -0,0 +1,3 @@ +obj-y += prom.o setup.o irq.o spi_eeprom.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c new file mode 100644 index 0000000..f498482 --- /dev/null +++ b/arch/mips/txx9/rbtx4938/irq.c @@ -0,0 +1,159 @@ +/* + * Toshiba RBTX4938 specific interrupt handlers + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +/* +IRQ Device + +16 TX4938-CP0/00 Software 0 +17 TX4938-CP0/01 Software 1 +18 TX4938-CP0/02 Cascade TX4938-CP0 +19 TX4938-CP0/03 Multiplexed -- do not use +20 TX4938-CP0/04 Multiplexed -- do not use +21 TX4938-CP0/05 Multiplexed -- do not use +22 TX4938-CP0/06 Multiplexed -- do not use +23 TX4938-CP0/07 CPU TIMER + +24 TX4938-PIC/00 +25 TX4938-PIC/01 +26 TX4938-PIC/02 Cascade RBTX4938-IOC +27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet +28 TX4938-PIC/04 +29 TX4938-PIC/05 TX4938 ETH1 +30 TX4938-PIC/06 TX4938 ETH0 +31 TX4938-PIC/07 +32 TX4938-PIC/08 TX4938 SIO 0 +33 TX4938-PIC/09 TX4938 SIO 1 +34 TX4938-PIC/10 TX4938 DMA0 +35 TX4938-PIC/11 TX4938 DMA1 +36 TX4938-PIC/12 TX4938 DMA2 +37 TX4938-PIC/13 TX4938 DMA3 +38 TX4938-PIC/14 +39 TX4938-PIC/15 +40 TX4938-PIC/16 TX4938 PCIC +41 TX4938-PIC/17 TX4938 TMR0 +42 TX4938-PIC/18 TX4938 TMR1 +43 TX4938-PIC/19 TX4938 TMR2 +44 TX4938-PIC/20 +45 TX4938-PIC/21 +46 TX4938-PIC/22 TX4938 PCIERR +47 TX4938-PIC/23 +48 TX4938-PIC/24 +49 TX4938-PIC/25 +50 TX4938-PIC/26 +51 TX4938-PIC/27 +52 TX4938-PIC/28 +53 TX4938-PIC/29 +54 TX4938-PIC/30 +55 TX4938-PIC/31 TX4938 SPI + +56 RBTX4938-IOC/00 PCI-D +57 RBTX4938-IOC/01 PCI-C +58 RBTX4938-IOC/02 PCI-B +59 RBTX4938-IOC/03 PCI-A +60 RBTX4938-IOC/04 RTC +61 RBTX4938-IOC/05 ATA +62 RBTX4938-IOC/06 MODEM +63 RBTX4938-IOC/07 SWINT +*/ +#include +#include +#include + +static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); + +#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" +static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { + .name = TOSHIBA_RBTX4938_IOC_NAME, + .ack = toshiba_rbtx4938_irq_ioc_disable, + .mask = toshiba_rbtx4938_irq_ioc_disable, + .mask_ack = toshiba_rbtx4938_irq_ioc_disable, + .unmask = toshiba_rbtx4938_irq_ioc_enable, +}; + +int +toshiba_rbtx4938_irq_nested(int sw_irq) +{ + u8 level3; + + level3 = readb(rbtx4938_imstat_addr); + if (level3) + /* must use fls so onboard ATA has priority */ + sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; + + return sw_irq; +} + +static struct irqaction toshiba_rbtx4938_irq_ioc_action = { + .handler = no_action, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = TOSHIBA_RBTX4938_IOC_NAME, +}; + +/**********************************************************************************/ +/* Functions for ioc */ +/**********************************************************************************/ +static void __init +toshiba_rbtx4938_irq_ioc_init(void) +{ + int i; + + for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; + i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) + set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, + handle_level_irq); + + setup_irq(RBTX4938_IRQ_IOCINT, + &toshiba_rbtx4938_irq_ioc_action); +} + +static void +toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) +{ + unsigned char v; + + v = readb(rbtx4938_imask_addr); + v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + writeb(v, rbtx4938_imask_addr); + mmiowb(); +} + +static void +toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) +{ + unsigned char v; + + v = readb(rbtx4938_imask_addr); + v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + writeb(v, rbtx4938_imask_addr); + mmiowb(); +} + +void __init arch_init_irq(void) +{ + extern void tx4938_irq_init(void); + + /* Now, interrupt control disabled, */ + /* all IRC interrupts are masked, */ + /* all IRC interrupt mode are Low Active. */ + + /* mask all IOC interrupts */ + writeb(0, rbtx4938_imask_addr); + + /* clear SoftInt interrupts */ + writeb(0, rbtx4938_softint_addr); + tx4938_irq_init(); + toshiba_rbtx4938_irq_ioc_init(); + /* Onboard 10M Ether: High Active */ + set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); +} diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c new file mode 100644 index 0000000..134fcc2 --- /dev/null +++ b/arch/mips/txx9/rbtx4938/prom.c @@ -0,0 +1,72 @@ +/* + * rbtx4938 specific prom routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include +#include +#include +#include + +#include +#include +#include + +void __init prom_init_cmdline(void) +{ + int argc = (int) fw_arg0; + char **argv = (char **) fw_arg1; + int i; + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) { + *arcs_cmdline = '\0'; + } + + for (i = 1; i < argc; i++) { + if (i != 1) { + strcat(arcs_cmdline, " "); + } + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + extern int tx4938_get_mem_size(void); + int msize; +#ifndef CONFIG_TX4938_NAND_BOOT + prom_init_cmdline(); +#endif + + msize = tx4938_get_mem_size(); + add_memory_region(0, msize << 20, BOOT_MEM_RAM); + + return; +} + +void __init prom_free_prom_memory(void) +{ +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ + return; +} + +const char *get_system_type(void) +{ + return "Toshiba RBTX4938"; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c new file mode 100644 index 0000000..bbd572c --- /dev/null +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -0,0 +1,1122 @@ +/* + * Setup pointers to hardware-dependent routines. + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#endif +#include +#include +#include + +extern char * __init prom_getcmdline(void); +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); + +/* These functions are used for rebooting or halting the machine*/ +extern void rbtx4938_machine_restart(char *command); +extern void rbtx4938_machine_halt(void); +extern void rbtx4938_machine_power_off(void); + +/* clocks */ +unsigned int txx9_master_clock; +unsigned int txx9_cpu_clock; +unsigned int txx9_gbus_clock; + +unsigned long rbtx4938_ce_base[8]; +unsigned long rbtx4938_ce_size[8]; +int txboard_pci66_mode; +static int tx4938_pcic_trdyto; /* default: disabled */ +static int tx4938_pcic_retryto; /* default: disabled */ +static int tx4938_ccfg_toeon = 1; + +struct tx4938_pcic_reg *pcicptrs[4] = { + tx4938_pcicptr /* default setting for TX4938 */ +}; + +static struct { + unsigned long base; + unsigned long size; +} phys_regions[16] __initdata; +static int num_phys_regions __initdata; + +#define PHYS_REGION_MINSIZE 0x10000 + +void rbtx4938_machine_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void rbtx4938_machine_power_off(void) +{ + rbtx4938_machine_halt(); + /* no return */ +} + +void rbtx4938_machine_restart(char *command) +{ + local_irq_disable(); + + printk("Rebooting..."); + writeb(1, rbtx4938_softresetlock_addr); + writeb(1, rbtx4938_sfvol_addr); + writeb(1, rbtx4938_softreset_addr); + while(1) + ; +} + +void __init +txboard_add_phys_region(unsigned long base, unsigned long size) +{ + if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { + printk("phys_region overflow\n"); + return; + } + phys_regions[num_phys_regions].base = base; + phys_regions[num_phys_regions].size = size; + num_phys_regions++; +} +unsigned long __init +txboard_find_free_phys_region(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + int i; + + for (base = begin / size * size; base < end; base += size) { + for (i = 0; i < num_phys_regions; i++) { + if (phys_regions[i].size && + base <= phys_regions[i].base + (phys_regions[i].size - 1) && + base + (size - 1) >= phys_regions[i].base) + break; + } + if (i == num_phys_regions) + return base; + } + return 0; +} +unsigned long __init +txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, + unsigned long *size) +{ + unsigned long sz, base; + for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { + base = txboard_find_free_phys_region(begin, end, sz); + if (base) { + *size = sz; + return base; + } + } + return 0; +} +unsigned long __init +txboard_request_phys_region_range(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region(unsigned long size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region_shrink(unsigned long *size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region_shrink(begin, end, size); + if (base) + txboard_add_phys_region(base, *size); + return base; +} + +#ifdef CONFIG_PCI +void __init +tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, + struct pci_controller *channel, + unsigned long pci_io_base, + int extarb) +{ + int i; + + /* Disable All Initiator Space */ + pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| + TX4938_PCIC_PCICCFG_G2PMEN(1)| + TX4938_PCIC_PCICCFG_G2PMEN(2)| + TX4938_PCIC_PCICCFG_G2PIOEN); + + /* GB->PCI mappings */ + pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; + pcicptr->g2piogbase = pci_io_base | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PIOGBASE_ECHG +#else + TX4938_PCIC_G2PIOGBASE_BSDIS +#endif + ; + pcicptr->g2piopbase = 0; + for (i = 0; i < 3; i++) { + pcicptr->g2pmmask[i] = 0; + pcicptr->g2pmgbase[i] = 0; + pcicptr->g2pmpbase[i] = 0; + } + if (channel->mem_resource->end) { + pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; + pcicptr->g2pmgbase[0] = channel->mem_resource->start | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PMnGBASE_ECHG +#else + TX4938_PCIC_G2PMnGBASE_BSDIS +#endif + ; + pcicptr->g2pmpbase[0] = channel->mem_resource->start; + } + /* PCI->GB mappings (I/O 256B) */ + pcicptr->p2giopbase = 0; /* 256B */ + pcicptr->p2giogbase = 0; + /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ + pcicptr->p2gm0plbase = 0; + pcicptr->p2gm0pubase = 0; + pcicptr->p2gmgbase[0] = 0 | + TX4938_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4938_PCIC_P2GMnGBASE_TECHG +#else + TX4938_PCIC_P2GMnGBASE_TBSDIS +#endif + ; + /* PCI->GB mappings (MEM 16MB) */ + pcicptr->p2gm1plbase = 0xffffffff; + pcicptr->p2gm1pubase = 0xffffffff; + pcicptr->p2gmgbase[1] = 0; + /* PCI->GB mappings (MEM 1MB) */ + pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ + pcicptr->p2gmgbase[2] = 0; + + pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; + /* Enable Initiator Memory Space */ + if (channel->mem_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); + /* Enable Initiator I/O Space */ + if (channel->io_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; + /* Enable Initiator Config */ + pcicptr->pciccfg |= + TX4938_PCIC_PCICCFG_ICAEN | + TX4938_PCIC_PCICCFG_TCAR; + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + pcicptr->pcicfg1 = 0; + + pcicptr->g2ptocnt &= ~0xffff; + + if (tx4938_pcic_trdyto >= 0) { + pcicptr->g2ptocnt &= ~0xff; + pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); + } + + if (tx4938_pcic_retryto >= 0) { + pcicptr->g2ptocnt &= ~0xff00; + pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); + } + + /* Clear All Local Bus Status */ + pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; + /* Enable All Local Bus Interrupts */ + pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; + /* Clear All Initiator Status */ + pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; + /* Enable All Initiator Interrupts */ + pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; + /* Clear All PCI Status Error */ + pcicptr->pcistatus = + (pcicptr->pcistatus & 0x0000ffff) | + (TX4938_PCIC_PCISTATUS_ALL << 16); + /* Enable All PCI Status Error Interrupts */ + pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; + + if (!extarb) { + /* Reset Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; + pcicptr->pbabm = 0; + /* Enable Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; + } + + /* PCIC Int => IRC IRQ16 */ + pcicptr->pcicfg2 = + (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; + + pcicptr->pcistatus = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; +} + +int __init +tx4938_report_pciclk(void) +{ + unsigned long pcode = TX4938_REV_PCODE(); + int pciclk = 0; + printk("TX%lx PCIC --%s PCICLK:", + pcode, + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + + switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_4: + pciclk = txx9_cpu_clock / 4; break; + case TX4938_CCFG_PCIDIVMODE_4_5: + pciclk = txx9_cpu_clock * 2 / 9; break; + case TX4938_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4938_CCFG_PCIDIVMODE_5_5: + pciclk = txx9_cpu_clock * 2 / 11; break; + case TX4938_CCFG_PCIDIVMODE_8: + pciclk = txx9_cpu_clock / 8; break; + case TX4938_CCFG_PCIDIVMODE_9: + pciclk = txx9_cpu_clock / 9; break; + case TX4938_CCFG_PCIDIVMODE_10: + pciclk = txx9_cpu_clock / 10; break; + case TX4938_CCFG_PCIDIVMODE_11: + pciclk = txx9_cpu_clock / 11; break; + } + printk("Internal(%dMHz)", pciclk / 1000000); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) +{ + pcicptrs[ch] = pcicptr; +} + +struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) +{ + return pcicptrs[ch]; +} + +static struct pci_dev *fake_pci_dev(struct pci_controller *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.sysdata = bus.sysdata = hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + bus.parent = NULL; + dev.bus = &bus; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +static int early_##rw##_config_##size(struct pci_controller *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, word, u16 *) + +int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) +{ + u32 pci_devfn; + unsigned short vid; + int devfn_start = 0; + int devfn_stop = 0xff; + int cap66 = -1; + u16 stat; + + printk("PCI: Checking 66MHz capabilities...\n"); + + for (pci_devfn=devfn_start; pci_devfn 0; +} + +int __init +tx4938_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; + /* Double PCICLK (if possible) */ + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = + tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4; + pciclk = txx9_cpu_clock / 4; + break; + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; + pciclk = txx9_cpu_clock * 2 / 9; + break; + case TX4938_CCFG_PCIDIVMODE_10: + case TX4938_CCFG_PCIDIVMODE_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5; + pciclk = txx9_cpu_clock / 5; + break; + case TX4938_CCFG_PCIDIVMODE_11: + case TX4938_CCFG_PCIDIVMODE_5_5: + default: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; + pciclk = txx9_cpu_clock * 2 / 11; + break; + } + tx4938_ccfgptr->ccfg = + (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) + | pcidivmode; + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)tx4938_ccfgptr->ccfg); + } else { + pciclk = -1; + } + return pciclk; +} + +extern struct pci_controller tx4938_pci_controller[]; +static int __init tx4938_pcibios_init(void) +{ + unsigned long mem_base[2]; + unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ + unsigned long io_base[2]; + unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ + /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ + int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); + + PCIBIOS_MIN_IO = 0x00001000UL; + + mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); + io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); + + printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + (unsigned short)(tx4938_pcicptr->pciid >> 16), + (unsigned short)(tx4938_pcicptr->pciid & 0xffff), + (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), + extarb ? "External" : "Internal"); + + /* setup PCI area */ + tx4938_pci_controller[0].io_resource->start = io_base[0]; + tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; + tx4938_pci_controller[0].mem_resource->start = mem_base[0]; + tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; + + set_tx4938_pcicptr(0, tx4938_pcicptr); + + register_pci_controller(&tx4938_pci_controller[0]); + + if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { + printk("TX4938_CCFG_PCI66 already configured\n"); + txboard_pci66_mode = -1; /* already configured */ + } + + /* Reset PCI Bus */ + writeb(0, rbtx4938_pcireset_addr); + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + if (txboard_pci66_mode > 0) + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + writeb(1, rbtx4938_pcireset_addr); + mmiowb(); + tx4938_report_pcic_status1(tx4938_pcicptr); + + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + if (txboard_pci66_mode == 0 && + txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { + /* Reset PCI Bus */ + writeb(0, rbtx4938_pcireset_addr); + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + writeb(1, rbtx4938_pcireset_addr); + mmiowb(); + /* Reinitialize PCIC */ + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + } + + mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); + io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); + /* Reset PCIC1 */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; + /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; + else + tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; + mdelay(10); + /* clear PCIC1 reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + tx4938_report_pcic_status1(tx4938_pcic1ptr); + + printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", + (unsigned short)(tx4938_pcic1ptr->pciid >> 16), + (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), + (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); + printk("%s PCICLK:%dMHz\n", + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", + txx9_gbus_clock / + ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / + 1000000); + + /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ + tx4938_pci_controller[1].io_resource->start = + io_base[1] - io_base[0]; + tx4938_pci_controller[1].io_resource->end = + io_base[1] - io_base[0] + io_size[1] - 1; + tx4938_pci_controller[1].mem_resource->start = mem_base[1]; + tx4938_pci_controller[1].mem_resource->end = + mem_base[1] + mem_size[1] - 1; + set_tx4938_pcicptr(1, tx4938_pcic1ptr); + + register_pci_controller(&tx4938_pci_controller[1]); + + tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); + + /* map ioport 0 to PCI I/O space address 0 */ + set_io_port_base(KSEG1 + io_base[0]); + + return 0; +} + +arch_initcall(tx4938_pcibios_init); + +#endif /* CONFIG_PCI */ + +/* SPI support */ + +/* chip select for SPI devices */ +#define SEEPROM1_CS 7 /* PIO7 */ +#define SEEPROM2_CS 0 /* IOC */ +#define SEEPROM3_CS 1 /* IOC */ +#define SRTC_CS 2 /* IOC */ + +#ifdef CONFIG_PCI +static int __init rbtx4938_ethaddr_init(void) +{ + unsigned char dat[17]; + unsigned char sum; + int i; + + /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ + if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) { + printk(KERN_ERR "seeprom: read error.\n"); + return -ENODEV; + } else { + if (strcmp(dat, "MAC") != 0) + printk(KERN_WARNING "seeprom: bad signature.\n"); + for (i = 0, sum = 0; i < sizeof(dat); i++) + sum += dat[i]; + if (sum) + printk(KERN_WARNING "seeprom: bad checksum.\n"); + } + for (i = 0; i < 2; i++) { + unsigned int id = + TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); + struct platform_device *pdev; + if (!(tx4938_ccfgptr->pcfg & + (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) + continue; + pdev = platform_device_alloc("tc35815-mac", id); + if (!pdev || + platform_device_add_data(pdev, &dat[4 + 6 * i], 6) || + platform_device_add(pdev)) + platform_device_put(pdev); + } + return 0; +} +device_initcall(rbtx4938_ethaddr_init); +#endif /* CONFIG_PCI */ + +static void __init rbtx4938_spi_setup(void) +{ + /* set SPI_SEL */ + tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; +} + +static struct resource rbtx4938_fpga_resource; + +static char pcode_str[8]; +static struct resource tx4938_reg_resource = { + .start = TX4938_REG_BASE, + .end = TX4938_REG_BASE + TX4938_REG_SIZE, + .name = pcode_str, + .flags = IORESOURCE_MEM +}; + +void __init tx4938_board_setup(void) +{ + int i; + unsigned long divmode; + int cpuclk = 0; + unsigned long pcode = TX4938_REV_PCODE(); + + ioport_resource.start = 0x1000; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0x1000; + iomem_resource.end = 0xffffffff; /* expand to 4GB */ + + sprintf(pcode_str, "TX%lx", pcode); + /* SDRAMC,EBUSC are configured by PROM */ + for (i = 0; i < 8; i++) { + if (!(tx4938_ebuscptr->cr[i] & 0x8)) + continue; /* disabled */ + rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); + txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); + } + + /* clocks */ + if (txx9_master_clock) { + /* calculate gbus_clock and cpu_clock_freq from master_clock */ + divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = txx9_master_clock * 4; break; + default: + txx9_gbus_clock = txx9_master_clock; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + cpuclk = txx9_gbus_clock * 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + cpuclk = txx9_gbus_clock * 5 / 2; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + cpuclk = txx9_gbus_clock * 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + cpuclk = txx9_gbus_clock * 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + cpuclk = txx9_gbus_clock * 9 / 2; break; + } + txx9_cpu_clock = cpuclk; + } else { + if (txx9_cpu_clock == 0) { + txx9_cpu_clock = 300000000; /* 300MHz */ + } + /* calculate gbus_clock and master_clock from cpu_clock_freq */ + cpuclk = txx9_cpu_clock; + divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + txx9_gbus_clock = cpuclk / 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + txx9_gbus_clock = cpuclk * 2 / 5; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + txx9_gbus_clock = cpuclk / 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + txx9_gbus_clock = cpuclk / 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = cpuclk * 2 / 9; break; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_master_clock = txx9_gbus_clock / 4; break; + default: + txx9_master_clock = txx9_gbus_clock; + } + } + /* change default value to udelay/mdelay take reasonable time */ + loops_per_jiffy = txx9_cpu_clock / HZ / 2; + + /* CCFG */ + /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; + /* do reset on watchdog */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR; + /* clear PCIC1 reset */ + if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + + /* enable Timeout BusError */ + if (tx4938_ccfg_toeon) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; + + /* DMA selection */ + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; + + /* Use external clock for external arbiter */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; + + printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", + pcode_str, + cpuclk / 1000000, txx9_master_clock / 1000000, + (unsigned long)tx4938_ccfgptr->crir, + tx4938_ccfgptr->ccfg, + tx4938_ccfgptr->pcfg); + + printk("%s SDRAMC --", pcode_str); + for (i = 0; i < 4; i++) { + unsigned long long cr = tx4938_sdramcptr->cr[i]; + unsigned long ram_base, ram_size; + if (!((unsigned long)cr & 0x00000400)) + continue; /* disabled */ + ram_base = (unsigned long)(cr >> 49) << 21; + ram_size = ((unsigned long)(cr >> 33) + 1) << 21; + if (ram_base >= 0x20000000) + continue; /* high memory (ignore) */ + printk(" CR%d:%016Lx", i, cr); + txboard_add_phys_region(ram_base, ram_size); + } + printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); + + /* SRAM */ + if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { + unsigned int size = 0x800; + unsigned long base = + (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); + txboard_add_phys_region(base, size); + } + + /* TMR */ + for (i = 0; i < TX4938_NR_TMR; i++) + txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); + + /* enable DMA */ + for (i = 0; i < 2; i++) + ____raw_writeq(TX4938_DMA_MCR_MSTEN, + (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); + + /* PIO */ + __raw_writel(0, &tx4938_pioptr->maskcpu); + __raw_writel(0, &tx4938_pioptr->maskext); + + /* TX4938 internal registers */ + if (request_resource(&iomem_resource, &tx4938_reg_resource)) + printk("request resource for internal registers failed\n"); +} + +#ifdef CONFIG_PCI +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) +{ + unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); + unsigned long g2pstatus = pcicptr->g2pstatus; + unsigned long pcicstatus = pcicptr->pcicstatus; + static struct { + unsigned long flag; + const char *str; + } pcistat_tbl[] = { + { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, + { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, + { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, + { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, + { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, + { PCI_STATUS_PARITY, "MasterParityError" }, + }, g2pstat_tbl[] = { + { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, + { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, + }, pcicstat_tbl[] = { + { TX4938_PCIC_PCICSTATUS_PME, "PME" }, + { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, + { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, + { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, + { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, + { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, + { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, + { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, + }; + int i; + + printk("pcistat:%04x(", pcistatus); + for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) + if (pcistatus & pcistat_tbl[i].flag) + printk("%s ", pcistat_tbl[i].str); + printk("), g2pstatus:%08lx(", g2pstatus); + for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) + if (g2pstatus & g2pstat_tbl[i].flag) + printk("%s ", g2pstat_tbl[i].str); + printk("), pcicstatus:%08lx(", pcicstatus); + for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) + if (pcicstatus & pcicstat_tbl[i].flag) + printk("%s ", pcicstat_tbl[i].str); + printk(")\n"); +} + +void tx4938_report_pcic_status(void) +{ + int i; + struct tx4938_pcic_reg *pcicptr; + for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) + tx4938_report_pcic_status1(pcicptr); +} + +#endif /* CONFIG_PCI */ + +void __init plat_time_init(void) +{ + mips_hpt_frequency = txx9_cpu_clock / 2; + if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS) + txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, + TXX9_IRQ_BASE + TX4938_IR_TMR(0), + txx9_gbus_clock / 2); +} + +void __init plat_mem_setup(void) +{ + unsigned long long pcfg; + char *argptr; + + iomem_resource.end = 0xffffffff; /* 4GB */ + + if (txx9_master_clock == 0) + txx9_master_clock = 25000000; /* 25MHz */ + tx4938_board_setup(); +#ifndef CONFIG_PCI + set_io_port_base(RBTX4938_ETHER_BASE); +#endif + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)(0xff1ff300 + i * 0x100); + req.mapbase = 0xff1ff300 + i * 0x100; + req.irq = RBTX4938_IRQ_IRC_SIO(i); + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = 50000000; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } +#endif +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 + printk("PIOSEL: disabling both ata and nand selection\n"); + local_irq_disable(); + tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND + printk("PIOSEL: enabling nand selection\n"); + tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA + printk("PIOSEL: enabling ata selection\n"); + tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; +#endif + +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } +#endif + + +#ifdef CONFIG_FB + { + conswitchp = &dummy_con; + } +#endif + + rbtx4938_spi_setup(); + pcfg = tx4938_ccfgptr->pcfg; /* updated */ + /* fixup piosel */ + if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_ATA_SEL) + writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04, + rbtx4938_piosel_addr); + else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_NDF_SEL) + writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08, + rbtx4938_piosel_addr); + else + writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04), + rbtx4938_piosel_addr); + + rbtx4938_fpga_resource.name = "FPGA Registers"; + rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); + rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; + rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; + if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) + printk("request resource for fpga failed\n"); + + _machine_restart = rbtx4938_machine_restart; + _machine_halt = rbtx4938_machine_halt; + pm_power_off = rbtx4938_machine_power_off; + + writeb(0xff, rbtx4938_led_addr); + printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", + readb(rbtx4938_fpga_rev_addr), + readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); +} + +static int __init rbtx4938_ne_init(void) +{ + struct resource res[] = { + { + .start = RBTX4938_RTL_8019_BASE, + .end = RBTX4938_RTL_8019_BASE + 0x20 - 1, + .flags = IORESOURCE_IO, + }, { + .start = RBTX4938_RTL_8019_IRQ, + .flags = IORESOURCE_IRQ, + } + }; + struct platform_device *dev = + platform_device_register_simple("ne", -1, + res, ARRAY_SIZE(res)); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(rbtx4938_ne_init); + +/* GPIO support */ + +int gpio_to_irq(unsigned gpio) +{ + return -EINVAL; +} + +int irq_to_gpio(unsigned irq) +{ + return -EINVAL; +} + +static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock); + +static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + u8 val; + unsigned long flags; + spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags); + val = readb(rbtx4938_spics_addr); + if (value) + val |= 1 << offset; + else + val &= ~(1 << offset); + writeb(val, rbtx4938_spics_addr); + mmiowb(); + spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags); +} + +static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip, + unsigned int offset, int value) +{ + rbtx4938_spi_gpio_set(chip, offset, value); + return 0; +} + +static struct gpio_chip rbtx4938_spi_gpio_chip = { + .set = rbtx4938_spi_gpio_set, + .direction_output = rbtx4938_spi_gpio_dir_out, + .label = "RBTX4938-SPICS", + .base = 16, + .ngpio = 3, +}; + +/* SPI support */ + +static void __init txx9_spi_init(unsigned long base, int irq) +{ + struct resource res[] = { + { + .start = base, + .end = base + 0x20 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .flags = IORESOURCE_IRQ, + }, + }; + platform_device_register_simple("spi_txx9", 0, + res, ARRAY_SIZE(res)); +} + +static int __init rbtx4938_spi_init(void) +{ + struct spi_board_info srtc_info = { + .modalias = "rtc-rs5c348", + .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */ + .bus_num = 0, + .chip_select = 16 + SRTC_CS, + /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */ + .mode = SPI_MODE_1 | SPI_CS_HIGH, + }; + spi_register_board_info(&srtc_info, 1); + spi_eeprom_register(SEEPROM1_CS); + spi_eeprom_register(16 + SEEPROM2_CS); + spi_eeprom_register(16 + SEEPROM3_CS); + gpio_request(16 + SRTC_CS, "rtc-rs5c348"); + gpio_direction_output(16 + SRTC_CS, 0); + gpio_request(SEEPROM1_CS, "seeprom1"); + gpio_direction_output(SEEPROM1_CS, 1); + gpio_request(16 + SEEPROM2_CS, "seeprom2"); + gpio_direction_output(16 + SEEPROM2_CS, 1); + gpio_request(16 + SEEPROM3_CS, "seeprom3"); + gpio_direction_output(16 + SEEPROM3_CS, 1); + txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI); + return 0; +} + +static int __init rbtx4938_arch_init(void) +{ + txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); + gpiochip_add(&rbtx4938_spi_gpio_chip); + return rbtx4938_spi_init(); +} +arch_initcall(rbtx4938_arch_init); + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init rbtx4938_wdt_init(void) +{ + return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); +} +device_initcall(rbtx4938_wdt_init); + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "spi-baseclk")) + return (struct clk *)(txx9_gbus_clock / 2 / 4); + if (!strcmp(id, "imbus_clk")) + return (struct clk *)(txx9_gbus_clock / 2); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/txx9/rbtx4938/spi_eeprom.c b/arch/mips/txx9/rbtx4938/spi_eeprom.c new file mode 100644 index 0000000..a7ea8b0 --- /dev/null +++ b/arch/mips/txx9/rbtx4938/spi_eeprom.c @@ -0,0 +1,99 @@ +/* + * spi_eeprom.c + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +#define AT250X0_PAGE_SIZE 8 + +/* register board information for at25 driver */ +int __init spi_eeprom_register(int chipid) +{ + static struct spi_eeprom eeprom = { + .name = "at250x0", + .byte_len = 128, + .page_size = AT250X0_PAGE_SIZE, + .flags = EE_ADDR1, + }; + struct spi_board_info info = { + .modalias = "at25", + .max_speed_hz = 1500000, /* 1.5Mbps */ + .bus_num = 0, + .chip_select = chipid, + .platform_data = &eeprom, + /* Mode 0: High-Active, Sample-Then-Shift */ + }; + + return spi_register_board_info(&info, 1); +} + +/* simple temporary spi driver to provide early access to seeprom. */ + +static struct read_param { + int chipid; + int address; + unsigned char *buf; + int len; +} *read_param; + +static int __init early_seeprom_probe(struct spi_device *spi) +{ + int stat = 0; + u8 cmd[2]; + int len = read_param->len; + char *buf = read_param->buf; + int address = read_param->address; + + dev_info(&spi->dev, "spiclk %u KHz.\n", + (spi->max_speed_hz + 500) / 1000); + if (read_param->chipid != spi->chip_select) + return -ENODEV; + while (len > 0) { + /* spi_write_then_read can only work with small chunk */ + int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE; + cmd[0] = 0x03; /* AT25_READ */ + cmd[1] = address; + stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c); + buf += c; + len -= c; + address += c; + } + return stat; +} + +static struct spi_driver early_seeprom_driver __initdata = { + .driver = { + .name = "at25", + .owner = THIS_MODULE, + }, + .probe = early_seeprom_probe, +}; + +int __init spi_eeprom_read(int chipid, int address, + unsigned char *buf, int len) +{ + int ret; + struct read_param param = { + .chipid = chipid, + .address = address, + .buf = buf, + .len = len + }; + + read_param = ¶m; + ret = spi_register_driver(&early_seeprom_driver); + if (!ret) + spi_unregister_driver(&early_seeprom_driver); + return ret; +} diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h deleted file mode 100644 index a162268..0000000 --- a/include/asm-mips/jmr3927/jmr3927.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Defines for the TJSYS JMR-TX3927 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Toshiba Corporation - */ -#ifndef __ASM_TX3927_JMR3927_H -#define __ASM_TX3927_JMR3927_H - -#include -#include -#include -#include - -/* CS */ -#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ -#define JMR3927_ROMCE1 0x1e000000 /* 4M */ -#define JMR3927_ROMCE2 0x14000000 /* 16M */ -#define JMR3927_ROMCE3 0x10000000 /* 64M */ -#define JMR3927_ROMCE5 0x1d000000 /* 4M */ -#define JMR3927_SDCS0 0x00000000 /* 32M */ -#define JMR3927_SDCS1 0x02000000 /* 32M */ -/* PCI Direct Mappings */ - -#define JMR3927_PCIMEM 0x08000000 -#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */ -#define JMR3927_PCIIO 0x15000000 -#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */ - -#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ -#define JMR3927_PORT_BASE KSEG1 - -/* Address map (virtual address) */ -#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) -#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) -#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) -#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) -#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) - -#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) -#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) -#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) -#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) -#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) -#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000) -#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000) -#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000) -#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000) -#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) -#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) - -/* Flash ROM */ -#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) -#define JMR3927_FLASH_SIZE 0x00400000 - -/* bits for IOC_REV/IOC_BREV (high byte) */ -#define JMR3927_IDT_MASK 0xfc -#define JMR3927_REV_MASK 0x03 -#define JMR3927_IOC_IDT 0xe0 - -/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ -#define JMR3927_IOC_INTB_PCIA 0 -#define JMR3927_IOC_INTB_PCIB 1 -#define JMR3927_IOC_INTB_PCIC 2 -#define JMR3927_IOC_INTB_PCID 3 -#define JMR3927_IOC_INTB_MODEM 4 -#define JMR3927_IOC_INTB_INT6 5 -#define JMR3927_IOC_INTB_INT7 6 -#define JMR3927_IOC_INTB_SOFT 7 -#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA) -#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB) -#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC) -#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID) -#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM) -#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6) -#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7) -#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT) - -/* bits for IOC_RESET (high byte) */ -#define JMR3927_IOC_RESET_CPU 1 -#define JMR3927_IOC_RESET_PCI 2 - -#if defined(__BIG_ENDIAN) -#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) -#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) -#elif defined(__LITTLE_ENDIAN) -#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d)) -#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1)) -#else -#error "No Endian" -#endif - -/* LED macro */ -#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) - -#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) - -/* DIPSW4 macro */ -#define jmr3927_dipsw1() (gpio_get_value(11) == 0) -#define jmr3927_dipsw2() (gpio_get_value(10) == 0) -#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) -#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) - -/* - * IRQ mappings - */ - -/* These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an JMR machine. Add new 'spaces' as new - * IRQ hardware is supported. - */ -#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ -#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ - -#define JMR3927_IRQ_IRC TXX9_IRQ_BASE -#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) -#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) - -#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) -#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) -#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2) -#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3) -#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4) -#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) -#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) -#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) -#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) -#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) -#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) -#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) -#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) -#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) -#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) -#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) -#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID) -#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM) -#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) -#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) -#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) - -/* IOC (PCI, MODEM) */ -#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 -/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ -#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 - -/* Clocks */ -#define JMR3927_CORECLK 132710400 /* 132.7MHz */ -#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ -#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ - -/* - * TX3927 Pin Configuration: - * - * PCFG bits Avail Dead - * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3] - * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4] - * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF, - * GDBGE* PIO[2:1] - * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12] - * SELTMR[2:0]:000 TIMER[1:0] - * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6], - * DMAREQ[1],DMAACK[1] - * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8] - * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14] - * SELDONE:1 DMADONE PIO[7] - * - * Usable pins are: - * RXD[1;0],TXD[1:0],CTS[0],RTS[0], - * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11] - * INT[3:0] - */ - -#endif /* __ASM_TX3927_JMR3927_H */ diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h deleted file mode 100644 index fb58033..0000000 --- a/include/asm-mips/jmr3927/tx3927.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Toshiba Corporation - */ -#ifndef __ASM_TX3927_H -#define __ASM_TX3927_H - -#include - -#define TX3927_SDRAMC_REG 0xfffe8000 -#define TX3927_ROMC_REG 0xfffe9000 -#define TX3927_DMA_REG 0xfffeb000 -#define TX3927_IRC_REG 0xfffec000 -#define TX3927_PCIC_REG 0xfffed000 -#define TX3927_CCFG_REG 0xfffee000 -#define TX3927_NR_TMR 3 -#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100) -#define TX3927_NR_SIO 2 -#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) -#define TX3927_PIO_REG 0xfffef500 - -struct tx3927_sdramc_reg { - volatile unsigned long cr[8]; - volatile unsigned long tr[3]; - volatile unsigned long cmd; - volatile unsigned long smrs[2]; -}; - -struct tx3927_romc_reg { - volatile unsigned long cr[8]; -}; - -struct tx3927_dma_reg { - struct tx3927_dma_ch_reg { - volatile unsigned long cha; - volatile unsigned long sar; - volatile unsigned long dar; - volatile unsigned long cntr; - volatile unsigned long sair; - volatile unsigned long dair; - volatile unsigned long ccr; - volatile unsigned long csr; - } ch[4]; - volatile unsigned long dbr[8]; - volatile unsigned long tdhr; - volatile unsigned long mcr; - volatile unsigned long unused0; -}; - -#include - -#ifdef __BIG_ENDIAN -#define endian_def_s2(e1, e2) \ - volatile unsigned short e1, e2 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned short e1;volatile unsigned char e2, e3 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned char e1, e2;volatile unsigned short e3 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e1, e2, e3, e4 -#else -#define endian_def_s2(e1, e2) \ - volatile unsigned short e2, e1 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned char e3, e2;volatile unsigned short e1 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned short e3;volatile unsigned char e2, e1 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e4, e3, e2, e1 -#endif - -struct tx3927_pcic_reg { - endian_def_s2(did, vid); - endian_def_s2(pcistat, pcicmd); - endian_def_b4(cc, scc, rpli, rid); - endian_def_b4(unused0, ht, mlt, cls); - volatile unsigned long ioba; /* +10 */ - volatile unsigned long mba; - volatile unsigned long unused1[5]; - endian_def_s2(svid, ssvid); - volatile unsigned long unused2; /* +30 */ - endian_def_sb2(unused3, unused4, capptr); - volatile unsigned long unused5; - endian_def_b4(ml, mg, ip, il); - volatile unsigned long unused6; /* +40 */ - volatile unsigned long istat; - volatile unsigned long iim; - volatile unsigned long rrt; - volatile unsigned long unused7[3]; /* +50 */ - volatile unsigned long ipbmma; - volatile unsigned long ipbioma; /* +60 */ - volatile unsigned long ilbmma; - volatile unsigned long ilbioma; - volatile unsigned long unused8[9]; - volatile unsigned long tc; /* +90 */ - volatile unsigned long tstat; - volatile unsigned long tim; - volatile unsigned long tccmd; - volatile unsigned long pcirrt; /* +a0 */ - volatile unsigned long pcirrt_cmd; - volatile unsigned long pcirrdt; - volatile unsigned long unused9[3]; - volatile unsigned long tlboap; - volatile unsigned long tlbiap; - volatile unsigned long tlbmma; /* +c0 */ - volatile unsigned long tlbioma; - volatile unsigned long sc_msg; - volatile unsigned long sc_be; - volatile unsigned long tbl; /* +d0 */ - volatile unsigned long unused10[3]; - volatile unsigned long pwmng; /* +e0 */ - volatile unsigned long pwmngs; - volatile unsigned long unused11[6]; - volatile unsigned long req_trace; /* +100 */ - volatile unsigned long pbapmc; - volatile unsigned long pbapms; - volatile unsigned long pbapmim; - volatile unsigned long bm; /* +110 */ - volatile unsigned long cpcibrs; - volatile unsigned long cpcibgs; - volatile unsigned long pbacs; - volatile unsigned long iobas; /* +120 */ - volatile unsigned long mbas; - volatile unsigned long lbc; - volatile unsigned long lbstat; - volatile unsigned long lbim; /* +130 */ - volatile unsigned long pcistatim; - volatile unsigned long ica; - volatile unsigned long icd; - volatile unsigned long iiadp; /* +140 */ - volatile unsigned long iscdp; - volatile unsigned long mmas; - volatile unsigned long iomas; - volatile unsigned long ipciaddr; /* +150 */ - volatile unsigned long ipcidata; - volatile unsigned long ipcibe; -}; - -struct tx3927_ccfg_reg { - volatile unsigned long ccfg; - volatile unsigned long crir; - volatile unsigned long pcfg; - volatile unsigned long tear; - volatile unsigned long pdcr; -}; - -/* - * SDRAMC - */ - -/* - * ROMC - */ - -/* - * DMA - */ -/* bits for MCR */ -#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch)) -#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch)) -#define TX3927_DMA_MCR_RSFIF 0x00000080 -#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) -#define TX3927_DMA_MCR_LE 0x00000004 -#define TX3927_DMA_MCR_RPRT 0x00000002 -#define TX3927_DMA_MCR_MSTEN 0x00000001 - -/* bits for CCRn */ -#define TX3927_DMA_CCR_DBINH 0x04000000 -#define TX3927_DMA_CCR_SBINH 0x02000000 -#define TX3927_DMA_CCR_CHRST 0x01000000 -#define TX3927_DMA_CCR_RVBYTE 0x00800000 -#define TX3927_DMA_CCR_ACKPOL 0x00400000 -#define TX3927_DMA_CCR_REQPL 0x00200000 -#define TX3927_DMA_CCR_EGREQ 0x00100000 -#define TX3927_DMA_CCR_CHDN 0x00080000 -#define TX3927_DMA_CCR_DNCTL 0x00060000 -#define TX3927_DMA_CCR_EXTRQ 0x00010000 -#define TX3927_DMA_CCR_INTRQD 0x0000e000 -#define TX3927_DMA_CCR_INTENE 0x00001000 -#define TX3927_DMA_CCR_INTENC 0x00000800 -#define TX3927_DMA_CCR_INTENT 0x00000400 -#define TX3927_DMA_CCR_CHNEN 0x00000200 -#define TX3927_DMA_CCR_XFACT 0x00000100 -#define TX3927_DMA_CCR_SNOP 0x00000080 -#define TX3927_DMA_CCR_DSTINC 0x00000040 -#define TX3927_DMA_CCR_SRCINC 0x00000020 -#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) -#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2) -#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4) -#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5) -#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) -#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) -#define TX3927_DMA_CCR_MEMIO 0x00000002 -#define TX3927_DMA_CCR_ONEAD 0x00000001 - -/* bits for CSRn */ -#define TX3927_DMA_CSR_CHNACT 0x00000100 -#define TX3927_DMA_CSR_ABCHC 0x00000080 -#define TX3927_DMA_CSR_NCHNC 0x00000040 -#define TX3927_DMA_CSR_NTRNFC 0x00000020 -#define TX3927_DMA_CSR_EXTDN 0x00000010 -#define TX3927_DMA_CSR_CFERR 0x00000008 -#define TX3927_DMA_CSR_CHERR 0x00000004 -#define TX3927_DMA_CSR_DESERR 0x00000002 -#define TX3927_DMA_CSR_SORERR 0x00000001 - -/* - * IRC - */ -#define TX3927_IR_INT0 0 -#define TX3927_IR_INT1 1 -#define TX3927_IR_INT2 2 -#define TX3927_IR_INT3 3 -#define TX3927_IR_INT4 4 -#define TX3927_IR_INT5 5 -#define TX3927_IR_SIO0 6 -#define TX3927_IR_SIO1 7 -#define TX3927_IR_SIO(ch) (6 + (ch)) -#define TX3927_IR_DMA 8 -#define TX3927_IR_PIO 9 -#define TX3927_IR_PCI 10 -#define TX3927_IR_TMR(ch) (13 + (ch)) -#define TX3927_NUM_IR 16 - -/* - * PCIC - */ -/* bits for PCICMD */ -/* see PCI_COMMAND_XXX in linux/pci.h */ - -/* bits for PCISTAT */ -/* see PCI_STATUS_XXX in linux/pci.h */ -#define PCI_STATUS_NEW_CAP 0x0010 - -/* bits for TC */ -#define TX3927_PCIC_TC_OF16E 0x00000020 -#define TX3927_PCIC_TC_IF8E 0x00000010 -#define TX3927_PCIC_TC_OF8E 0x00000008 - -/* bits for IOBA/MBA */ -/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ - -/* bits for PBAPMC */ -#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 -#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002 -#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001 - -/* bits for LBSTAT/LBIM */ -#define TX3927_PCIC_LBIM_ALL 0x0000003e - -/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900 - -/* bits for LBC */ -#define TX3927_PCIC_LBC_IBSE 0x00004000 -#define TX3927_PCIC_LBC_TIBSE 0x00002000 -#define TX3927_PCIC_LBC_TMFBSE 0x00001000 -#define TX3927_PCIC_LBC_HRST 0x00000800 -#define TX3927_PCIC_LBC_SRST 0x00000400 -#define TX3927_PCIC_LBC_EPCAD 0x00000200 -#define TX3927_PCIC_LBC_MSDSE 0x00000100 -#define TX3927_PCIC_LBC_CRR 0x00000080 -#define TX3927_PCIC_LBC_ILMDE 0x00000040 -#define TX3927_PCIC_LBC_ILIDE 0x00000020 - -#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX3927_CCFG_TLBOFF 0x00020000 -#define TX3927_CCFG_BEOW 0x00010000 -#define TX3927_CCFG_WR 0x00008000 -#define TX3927_CCFG_TOE 0x00004000 -#define TX3927_CCFG_PCIXARB 0x00002000 -#define TX3927_CCFG_PCI3 0x00001000 -#define TX3927_CCFG_PSNP 0x00000800 -#define TX3927_CCFG_PPRI 0x00000400 -#define TX3927_CCFG_PLLM 0x00000030 -#define TX3927_CCFG_ENDIAN 0x00000004 -#define TX3927_CCFG_HALT 0x00000002 -#define TX3927_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX3927_PCFG_SYSCLKEN 0x08000000 -#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000 -#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch)) -#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000 -#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch)) -#define TX3927_PCFG_SELALL 0x0003ffff -#define TX3927_PCFG_SELCS 0x00020000 -#define TX3927_PCFG_SELDSF 0x00010000 -#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 -#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) -#define TX3927_PCFG_SELSIO_ALL 0x00003000 -#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch)) -#define TX3927_PCFG_SELTMR_ALL 0x00000e00 -#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch)) -#define TX3927_PCFG_SELDONE 0x00000100 -#define TX3927_PCFG_INTDMA_ALL 0x000000f0 -#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch)) -#define TX3927_PCFG_SELDMA_ALL 0x0000000f -#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) - -#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) -#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) -#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) -#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) -#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) -#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) -#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) -#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) - -#endif /* __ASM_TX3927_H */ diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h deleted file mode 100644 index 25dcf2f..0000000 --- a/include/asm-mips/jmr3927/txx927.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Common definitions for TX3927/TX4927 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Toshiba Corporation - */ -#ifndef __ASM_TXX927_H -#define __ASM_TXX927_H - -struct txx927_sio_reg { - volatile unsigned long lcr; - volatile unsigned long dicr; - volatile unsigned long disr; - volatile unsigned long cisr; - volatile unsigned long fcr; - volatile unsigned long flcr; - volatile unsigned long bgr; - volatile unsigned long tfifo; - volatile unsigned long rfifo; -}; - -/* - * SIO - */ -/* SILCR : Line Control */ -#define TXx927_SILCR_SCS_MASK 0x00000060 -#define TXx927_SILCR_SCS_IMCLK 0x00000000 -#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020 -#define TXx927_SILCR_SCS_SCLK 0x00000040 -#define TXx927_SILCR_SCS_SCLK_BG 0x00000060 -#define TXx927_SILCR_UEPS 0x00000010 -#define TXx927_SILCR_UPEN 0x00000008 -#define TXx927_SILCR_USBL_MASK 0x00000004 -#define TXx927_SILCR_USBL_1BIT 0x00000004 -#define TXx927_SILCR_USBL_2BIT 0x00000000 -#define TXx927_SILCR_UMODE_MASK 0x00000003 -#define TXx927_SILCR_UMODE_8BIT 0x00000000 -#define TXx927_SILCR_UMODE_7BIT 0x00000001 - -/* SIDICR : DMA/Int. Control */ -#define TXx927_SIDICR_TDE 0x00008000 -#define TXx927_SIDICR_RDE 0x00004000 -#define TXx927_SIDICR_TIE 0x00002000 -#define TXx927_SIDICR_RIE 0x00001000 -#define TXx927_SIDICR_SPIE 0x00000800 -#define TXx927_SIDICR_CTSAC 0x00000600 -#define TXx927_SIDICR_STIE_MASK 0x0000003f -#define TXx927_SIDICR_STIE_OERS 0x00000020 -#define TXx927_SIDICR_STIE_CTSS 0x00000010 -#define TXx927_SIDICR_STIE_RBRKD 0x00000008 -#define TXx927_SIDICR_STIE_TRDY 0x00000004 -#define TXx927_SIDICR_STIE_TXALS 0x00000002 -#define TXx927_SIDICR_STIE_UBRKD 0x00000001 - -/* SIDISR : DMA/Int. Status */ -#define TXx927_SIDISR_UBRK 0x00008000 -#define TXx927_SIDISR_UVALID 0x00004000 -#define TXx927_SIDISR_UFER 0x00002000 -#define TXx927_SIDISR_UPER 0x00001000 -#define TXx927_SIDISR_UOER 0x00000800 -#define TXx927_SIDISR_ERI 0x00000400 -#define TXx927_SIDISR_TOUT 0x00000200 -#define TXx927_SIDISR_TDIS 0x00000100 -#define TXx927_SIDISR_RDIS 0x00000080 -#define TXx927_SIDISR_STIS 0x00000040 -#define TXx927_SIDISR_RFDN_MASK 0x0000001f - -/* SICISR : Change Int. Status */ -#define TXx927_SICISR_OERS 0x00000020 -#define TXx927_SICISR_CTSS 0x00000010 -#define TXx927_SICISR_RBRKD 0x00000008 -#define TXx927_SICISR_TRDY 0x00000004 -#define TXx927_SICISR_TXALS 0x00000002 -#define TXx927_SICISR_UBRKD 0x00000001 - -/* SIFCR : FIFO Control */ -#define TXx927_SIFCR_SWRST 0x00008000 -#define TXx927_SIFCR_RDIL_MASK 0x00000180 -#define TXx927_SIFCR_RDIL_1 0x00000000 -#define TXx927_SIFCR_RDIL_4 0x00000080 -#define TXx927_SIFCR_RDIL_8 0x00000100 -#define TXx927_SIFCR_RDIL_12 0x00000180 -#define TXx927_SIFCR_RDIL_MAX 0x00000180 -#define TXx927_SIFCR_TDIL_MASK 0x00000018 -#define TXx927_SIFCR_TDIL_MASK 0x00000018 -#define TXx927_SIFCR_TDIL_1 0x00000000 -#define TXx927_SIFCR_TDIL_4 0x00000001 -#define TXx927_SIFCR_TDIL_8 0x00000010 -#define TXx927_SIFCR_TDIL_MAX 0x00000010 -#define TXx927_SIFCR_TFRST 0x00000004 -#define TXx927_SIFCR_RFRST 0x00000002 -#define TXx927_SIFCR_FRSTE 0x00000001 -#define TXx927_SIO_TX_FIFO 8 -#define TXx927_SIO_RX_FIFO 16 - -/* SIFLCR : Flow Control */ -#define TXx927_SIFLCR_RCS 0x00001000 -#define TXx927_SIFLCR_TES 0x00000800 -#define TXx927_SIFLCR_RTSSC 0x00000200 -#define TXx927_SIFLCR_RSDE 0x00000100 -#define TXx927_SIFLCR_TSDE 0x00000080 -#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e -#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e -#define TXx927_SIFLCR_TBRK 0x00000001 - -/* SIBGR : Baudrate Control */ -#define TXx927_SIBGR_BCLK_MASK 0x00000300 -#define TXx927_SIBGR_BCLK_T0 0x00000000 -#define TXx927_SIBGR_BCLK_T2 0x00000100 -#define TXx927_SIBGR_BCLK_T4 0x00000200 -#define TXx927_SIBGR_BCLK_T6 0x00000300 -#define TXx927_SIBGR_BRD_MASK 0x000000ff - -/* - * PIO - */ - -#endif /* __ASM_TXX927_H */ diff --git a/include/asm-mips/tx4927/smsc_fdc37m81x.h b/include/asm-mips/tx4927/smsc_fdc37m81x.h deleted file mode 100644 index 5d93bab..0000000 --- a/include/asm-mips/tx4927/smsc_fdc37m81x.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h - * - * Interface for smsc fdc48m81x Super IO chip - * - * Author: MontaVista Software, Inc. source@mvista.com - * - * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Manish Lachwani, mlachwani@mvista.com - */ - -#ifndef _SMSC_FDC37M81X_H_ -#define _SMSC_FDC37M81X_H_ - -/* Common Registers */ -#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 -#define SMSC_FDC37M81X_CONFIG_DATA 0x01 -#define SMSC_FDC37M81X_CONF 0x02 -#define SMSC_FDC37M81X_INDEX 0x03 -#define SMSC_FDC37M81X_DNUM 0x07 -#define SMSC_FDC37M81X_DID 0x20 -#define SMSC_FDC37M81X_DREV 0x21 -#define SMSC_FDC37M81X_PCNT 0x22 -#define SMSC_FDC37M81X_PMGT 0x23 -#define SMSC_FDC37M81X_OSC 0x24 -#define SMSC_FDC37M81X_CONFPA0 0x26 -#define SMSC_FDC37M81X_CONFPA1 0x27 -#define SMSC_FDC37M81X_TEST4 0x2B -#define SMSC_FDC37M81X_TEST5 0x2C -#define SMSC_FDC37M81X_TEST1 0x2D -#define SMSC_FDC37M81X_TEST2 0x2E -#define SMSC_FDC37M81X_TEST3 0x2F - -/* Logical device numbers */ -#define SMSC_FDC37M81X_FDD 0x00 -#define SMSC_FDC37M81X_PARALLEL 0x03 -#define SMSC_FDC37M81X_SERIAL1 0x04 -#define SMSC_FDC37M81X_SERIAL2 0x05 -#define SMSC_FDC37M81X_KBD 0x07 -#define SMSC_FDC37M81X_AUXIO 0x08 -#define SMSC_FDC37M81X_NONE 0xff - -/* Logical device Config Registers */ -#define SMSC_FDC37M81X_ACTIVE 0x30 -#define SMSC_FDC37M81X_BASEADDR0 0x60 -#define SMSC_FDC37M81X_BASEADDR1 0x61 -#define SMSC_FDC37M81X_INT 0x70 -#define SMSC_FDC37M81X_INT2 0x72 -#define SMSC_FDC37M81X_LDCR_F0 0xF0 - -/* Chip Config Values */ -#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 -#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa -#define SMSC_FDC37M81X_CHIP_ID 0x4d - -unsigned long __init smsc_fdc37m81x_init(unsigned long port); - -void smsc_fdc37m81x_config_beg(void); - -void smsc_fdc37m81x_config_end(void); - -void smsc_fdc37m81x_config_set(u8 reg, u8 val); - -#endif diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h deleted file mode 100644 index d6b32ac..0000000 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H -#define __ASM_TX4927_TOSHIBA_RBTX4927_H - -#include - -#ifdef CONFIG_PCI -#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO -#else -#define TBTX4927_ISA_IO_OFFSET 0 -#endif - -#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL -#define RBTX4927_SW_RESET_DO_SET 0x01 - -#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL -#define RBTX4927_SW_RESET_ENABLE_SET 0x01 - -#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) -#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) - -int toshiba_rbtx4927_irq_nested(int sw_irq); - -#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */ diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h deleted file mode 100644 index 1d4816f..0000000 --- a/include/asm-mips/tx4927/tx4927.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2006 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TX4927_TX4927_H -#define __ASM_TX4927_TX4927_H - -#include - -#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE -#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - -#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE -#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) - - -#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) -#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) -#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) -#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) - -#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) - -#define TX4927_CCFG_TOE 0x00004000 -#define TX4927_CCFG_WR 0x00008000 -#define TX4927_CCFG_TINTDIS 0x01000000 - -#define TX4927_PCIMEM 0x08000000 -#define TX4927_PCIMEM_SIZE 0x08000000 -#define TX4927_PCIIO 0x16000000 -#define TX4927_PCIIO_SIZE 0x01000000 - -#define TX4927_SDRAMC_REG 0xff1f8000 -#define TX4927_EBUSC_REG 0xff1f9000 -#define TX4927_PCIC_REG 0xff1fd000 -#define TX4927_CCFG_REG 0xff1fe000 -#define TX4927_IRC_REG 0xff1ff600 -#define TX4927_NR_TMR 3 -#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) - -/* bits for ISTAT3/IMASK3/IMSTAT3 */ -#define TX4927_INT3B_PCID 0 -#define TX4927_INT3B_PCIC 1 -#define TX4927_INT3B_PCIB 2 -#define TX4927_INT3B_PCIA 3 -#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) -#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) -#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) -#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) - -#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG -#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ - -#define TX4927_IR_PCIC 16 -#define TX4927_IR_PCIERR 22 -#define TX4927_IR_PCIPMA 23 -#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) -#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) -#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) -#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) -#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) -#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) -#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) - -#ifdef _LANGUAGE_ASSEMBLY -#define _CONST64(c) c -#else -#define _CONST64(c) c##ull - -#include - -struct tx4927_sdramc_reg { - volatile unsigned long long cr[4]; - volatile unsigned long long unused0[4]; - volatile unsigned long long tr; - volatile unsigned long long unused1[2]; - volatile unsigned long long cmd; -}; - -struct tx4927_ebusc_reg { - volatile unsigned long long cr[8]; -}; - -struct tx4927_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; -}; - -struct tx4927_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmcut; - volatile unsigned long long pdmcnt; /* +220 */ - volatile unsigned long long pdmsts; - volatile unsigned long long unused8[2]; - volatile unsigned long long pdmdb[4]; /* +240 */ - volatile unsigned long long pdmtdh; /* +260 */ - volatile unsigned long long pdmdms; -}; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* - * PCIC - */ - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4927_PCIC_PBACFG_RPBA 0x00000004 -#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc - -/* bits for PCICCFG */ -#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 -#define TX4927_PCIC_PCICCFG_HRST 0x00000800 -#define TX4927_PCIC_PCICCFG_SRST 0x00000400 -#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 -#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 -#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 -#define TX4927_PCIC_PCICCFG_IISE 0x00000020 -#define TX4927_PCIC_PCICCFG_ATR 0x00000010 -#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4927_CCFG_PCI66 0x00800000 -#define TX4927_CCFG_PCIMIDE 0x00400000 -#define TX4927_CCFG_PCIXARB 0x00002000 -#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 -#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 -#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 -#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 -#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 - -#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 -#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 -#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 -#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 -#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 -#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 -#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 -#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 - -/* PCFG : Pin Configuration */ -#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 -#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) - -/* CLKCTR : Clock Control */ -#define TX4927_CLKCTR_PCICKD 0x00400000 -#define TX4927_CLKCTR_PCIRST 0x00000040 - -#ifndef _LANGUAGE_ASSEMBLY - -#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) -#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) -#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) -#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) - -#endif /* _LANGUAGE_ASSEMBLY */ - -#endif /* __ASM_TX4927_TX4927_H */ diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h deleted file mode 100644 index dfed7be..0000000 --- a/include/asm-mips/tx4938/rbtx4938.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * linux/include/asm-mips/tx4938/rbtx4938.h - * Definitions for TX4937/TX4938 - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TX_BOARDS_RBTX4938_H -#define __ASM_TX_BOARDS_RBTX4938_H - -#include -#include -#include - -/* CS */ -#define RBTX4938_CE0 0x1c000000 /* 64M */ -#define RBTX4938_CE2 0x17f00000 /* 1M */ - -/* Address map */ -#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) -#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) -#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) -#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) -#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) -#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) -#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) -#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) -#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) -#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) -#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) -#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) -#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) -#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) -#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) -#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) -#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) -#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) -#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) -#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) -#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) -#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) -#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) -#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) - -/* Ethernet port address (Jumperless Mode (W12:Open)) */ -#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) - -/* bits for ISTAT/IMASK/IMSTAT */ -#define RBTX4938_INTB_PCID 0 -#define RBTX4938_INTB_PCIC 1 -#define RBTX4938_INTB_PCIB 2 -#define RBTX4938_INTB_PCIA 3 -#define RBTX4938_INTB_RTC 4 -#define RBTX4938_INTB_ATA 5 -#define RBTX4938_INTB_MODEM 6 -#define RBTX4938_INTB_SWINT 7 -#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) -#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) -#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) -#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) -#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) -#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) -#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) -#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) - -#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR) -#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR) -#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR) -#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR) -#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR) -#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR) -#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR) -#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR) -#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR) -#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR) -#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR) -#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR) -#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR) -#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) -#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) -#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) -#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) -#define rbtx4938_softresetlock_addr \ - ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) -#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) - -/* - * IRQ mappings - */ - -#define RBTX4938_SOFT_INT0 0 /* not used */ -#define RBTX4938_SOFT_INT1 1 /* not used */ -#define RBTX4938_IRC_INT 2 -#define RBTX4938_TIMER_INT 7 - -/* These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new - * IRQ hardware is supported. - */ -#define RBTX4938_NR_IRQ_LOCAL 8 -#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ -#define RBTX4938_NR_IRQ_IOC 8 - -#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE -#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - -#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE -#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) -#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) -#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) -#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) -#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1) -#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7) - -#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0 -#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7 - -#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */ -#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */ -#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG -#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL) -#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC) -#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) - -#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0) -#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1) -#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT) -#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT) -#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) -#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) -#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) -#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) -#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) -#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) -#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) -#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) -#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) -#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) -#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) -#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) -#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) -#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) -#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) -#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) -#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) -#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) -#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) -#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) -#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) -#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) -#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) -#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) - - -/* IOC (PCI, etc) */ -#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) -/* Onboard 10M Ether */ -#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) - -#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) -#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) - -#endif /* __ASM_TX_BOARDS_RBTX4938_H */ diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h deleted file mode 100644 index 6a60c83..0000000 --- a/include/asm-mips/tx4938/spi.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * linux/include/asm-mips/tx4938/spi.h - * Definitions for TX4937/TX4938 SPI - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TX_BOARDS_TX4938_SPI_H -#define __ASM_TX_BOARDS_TX4938_SPI_H - -extern int spi_eeprom_register(int chipid); -extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); - -#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h deleted file mode 100644 index e8807f5..0000000 --- a/include/asm-mips/tx4938/tx4938.h +++ /dev/null @@ -1,628 +0,0 @@ -/* - * linux/include/asm-mips/tx4938/tx4938.h - * Definitions for TX4937/TX4938 - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TX_BOARDS_TX4938_H -#define __ASM_TX_BOARDS_TX4938_H - -#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) -#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) - -#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG - -#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC) -#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR) - -#define TX4938_PCIIO_0 0x10000000 -#define TX4938_PCIIO_1 0x01010000 -#define TX4938_PCIMEM_0 0x08000000 -#define TX4938_PCIMEM_1 0x11000000 - -#define TX4938_PCIIO_SIZE_0 0x01000000 -#define TX4938_PCIIO_SIZE_1 0x00010000 -#define TX4938_PCIMEM_SIZE_0 0x08000000 -#define TX4938_PCIMEM_SIZE_1 0x00010000 - -#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */ -#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ - -/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ -#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000) -#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000) -#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000) -#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000) -#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000) -#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800) -#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000) -#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000) -#define TX4938_NR_TMR 3 -#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100) -#define TX4938_NR_SIO 2 -#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100) -#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500) -#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600) -#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) -#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) - -#ifdef __ASSEMBLY__ -#define _CONST64(c) c -#else -#define _CONST64(c) c##ull - -#include - -#ifdef __BIG_ENDIAN -#define endian_def_l2(e1, e2) \ - volatile unsigned long e1, e2 -#define endian_def_s2(e1, e2) \ - volatile unsigned short e1, e2 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned short e1;volatile unsigned char e2, e3 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned char e1, e2;volatile unsigned short e3 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e1, e2, e3, e4 -#else -#define endian_def_l2(e1, e2) \ - volatile unsigned long e2, e1 -#define endian_def_s2(e1, e2) \ - volatile unsigned short e2, e1 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned char e3, e2;volatile unsigned short e1 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned short e3;volatile unsigned char e2, e1 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e4, e3, e2, e1 -#endif - - -struct tx4938_sdramc_reg { - volatile unsigned long long cr[4]; - volatile unsigned long long unused0[4]; - volatile unsigned long long tr; - volatile unsigned long long unused1[2]; - volatile unsigned long long cmd; - volatile unsigned long long sfcmd; -}; - -struct tx4938_ebusc_reg { - volatile unsigned long long cr[8]; -}; - -struct tx4938_dma_reg { - struct tx4938_dma_ch_reg { - volatile unsigned long long cha; - volatile unsigned long long sar; - volatile unsigned long long dar; - endian_def_l2(unused0, cntr); - endian_def_l2(unused1, sair); - endian_def_l2(unused2, dair); - endian_def_l2(unused3, ccr); - endian_def_l2(unused4, csr); - } ch[4]; - volatile unsigned long long dbr[8]; - volatile unsigned long long tdhr; - volatile unsigned long long midr; - endian_def_l2(unused0, mcr); -}; - -struct tx4938_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmctr; - volatile unsigned long long pdmcfg; /* +220 */ - volatile unsigned long long pdmsts; -}; - -struct tx4938_aclc_reg { - volatile unsigned long acctlen; - volatile unsigned long acctldis; - volatile unsigned long acregacc; - volatile unsigned long unused0; - volatile unsigned long acintsts; - volatile unsigned long acintmsts; - volatile unsigned long acinten; - volatile unsigned long acintdis; - volatile unsigned long acsemaph; - volatile unsigned long unused1[7]; - volatile unsigned long acgpidat; - volatile unsigned long acgpodat; - volatile unsigned long acslten; - volatile unsigned long acsltdis; - volatile unsigned long acfifosts; - volatile unsigned long unused2[11]; - volatile unsigned long acdmasts; - volatile unsigned long acdmasel; - volatile unsigned long unused3[6]; - volatile unsigned long acaudodat; - volatile unsigned long acsurrdat; - volatile unsigned long accentdat; - volatile unsigned long aclfedat; - volatile unsigned long acaudiat; - volatile unsigned long unused4; - volatile unsigned long acmodoat; - volatile unsigned long acmodidat; - volatile unsigned long unused5[15]; - volatile unsigned long acrevid; -}; - - -struct tx4938_tmr_reg { - volatile unsigned long tcr; - volatile unsigned long tisr; - volatile unsigned long cpra; - volatile unsigned long cprb; - volatile unsigned long itmr; - volatile unsigned long unused0[3]; - volatile unsigned long ccdr; - volatile unsigned long unused1[3]; - volatile unsigned long pgmr; - volatile unsigned long unused2[3]; - volatile unsigned long wtmr; - volatile unsigned long unused3[43]; - volatile unsigned long trr; -}; - -struct tx4938_sio_reg { - volatile unsigned long lcr; - volatile unsigned long dicr; - volatile unsigned long disr; - volatile unsigned long cisr; - volatile unsigned long fcr; - volatile unsigned long flcr; - volatile unsigned long bgr; - volatile unsigned long tfifo; - volatile unsigned long rfifo; -}; - -struct tx4938_ndfmc_reg { - endian_def_l2(unused0, dtr); - endian_def_l2(unused1, mcr); - endian_def_l2(unused2, sr); - endian_def_l2(unused3, isr); - endian_def_l2(unused4, imr); - endian_def_l2(unused5, spr); - endian_def_l2(unused6, rstr); -}; - -struct tx4938_spi_reg { - volatile unsigned long mcr; - volatile unsigned long cr0; - volatile unsigned long cr1; - volatile unsigned long fs; - volatile unsigned long unused1; - volatile unsigned long sr; - volatile unsigned long dr; - volatile unsigned long unused2; -}; - -struct tx4938_sramc_reg { - volatile unsigned long long cr; -}; - -struct tx4938_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; - volatile unsigned long long unused3; - volatile unsigned long long jmpadr; -}; - -#undef endian_def_l2 -#undef endian_def_s2 -#undef endian_def_sb2 -#undef endian_def_b2s -#undef endian_def_b4 - -#endif /* __ASSEMBLY__ */ - -/* - * NDFMC - */ - -/* NDFMCR : NDFMC Mode Control */ -#define TX4938_NDFMCR_WE 0x80 -#define TX4938_NDFMCR_ECC_ALL 0x60 -#define TX4938_NDFMCR_ECC_RESET 0x60 -#define TX4938_NDFMCR_ECC_READ 0x40 -#define TX4938_NDFMCR_ECC_ON 0x20 -#define TX4938_NDFMCR_ECC_OFF 0x00 -#define TX4938_NDFMCR_CE 0x10 -#define TX4938_NDFMCR_BSPRT 0x04 -#define TX4938_NDFMCR_ALE 0x02 -#define TX4938_NDFMCR_CLE 0x01 - -/* NDFMCR : NDFMC Status */ -#define TX4938_NDFSR_BUSY 0x80 - -/* NDFMCR : NDFMC Reset */ -#define TX4938_NDFRSTR_RST 0x01 - -/* - * IRC - */ - -#define TX4938_IR_ECCERR 0 -#define TX4938_IR_WTOERR 1 -#define TX4938_NUM_IR_INT 6 -#define TX4938_IR_INT(n) (2 + (n)) -#define TX4938_NUM_IR_SIO 2 -#define TX4938_IR_SIO(n) (8 + (n)) -#define TX4938_NUM_IR_DMA 4 -#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ -#define TX4938_IR_PIO 14 -#define TX4938_IR_PDMAC 15 -#define TX4938_IR_PCIC 16 -#define TX4938_NUM_IR_TMR 3 -#define TX4938_IR_TMR(n) (17 + (n)) -#define TX4938_IR_NDFMC 21 -#define TX4938_IR_PCIERR 22 -#define TX4938_IR_PCIPME 23 -#define TX4938_IR_ACLC 24 -#define TX4938_IR_ACLCPME 25 -#define TX4938_IR_PCIC1 26 -#define TX4938_IR_SPI 31 -#define TX4938_NUM_IR 32 -/* multiplex */ -#define TX4938_IR_ETH0 TX4938_IR_INT(4) -#define TX4938_IR_ETH1 TX4938_IR_INT(3) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) -#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) -#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) -#define TX4938_CCFG_TINTDIS 0x01000000 -#define TX4938_CCFG_PCI66 0x00800000 -#define TX4938_CCFG_PCIMODE 0x00400000 -#define TX4938_CCFG_PCI1_66 0x00200000 -#define TX4938_CCFG_DIVMODE_MASK 0x001e0000 -#define TX4938_CCFG_DIVMODE_2 (0x4 << 17) -#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) -#define TX4938_CCFG_DIVMODE_3 (0x5 << 17) -#define TX4938_CCFG_DIVMODE_4 (0x6 << 17) -#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) -#define TX4938_CCFG_DIVMODE_8 (0x0 << 17) -#define TX4938_CCFG_DIVMODE_10 (0xb << 17) -#define TX4938_CCFG_DIVMODE_12 (0x1 << 17) -#define TX4938_CCFG_DIVMODE_16 (0x2 << 17) -#define TX4938_CCFG_DIVMODE_18 (0x9 << 17) -#define TX4938_CCFG_BEOW 0x00010000 -#define TX4938_CCFG_WR 0x00008000 -#define TX4938_CCFG_TOE 0x00004000 -#define TX4938_CCFG_PCIXARB 0x00002000 -#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) -#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) -#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10) -#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10) -#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10) -#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10) -#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10) -#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10) -#define TX4938_CCFG_PCI1DMD 0x00000100 -#define TX4938_CCFG_SYSSP_MASK 0x000000c0 -#define TX4938_CCFG_ENDIAN 0x00000004 -#define TX4938_CCFG_HALT 0x00000002 -#define TX4938_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) -#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) -#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) -#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) -#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) -#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) -#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 -#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) -#define TX4938_PCFG_SYSCLKEN 0x08000000 -#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 -#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) -#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000 -#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) -#define TX4938_PCFG_SEL2 0x00000200 -#define TX4938_PCFG_SEL1 0x00000100 -#define TX4938_PCFG_DMASEL_ALL 0x0000000f -#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000 -#define TX4938_PCFG_DMASEL0_SIO1 0x00000001 -#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000 -#define TX4938_PCFG_DMASEL1_SIO1 0x00000002 -#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000 -#define TX4938_PCFG_DMASEL2_SIO0 0x00000004 -#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000 -#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 - -/* CLKCTR : Clock Control */ -#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) -#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) -#define TX4938_CLKCTR_ETH1CKD 0x80000000 -#define TX4938_CLKCTR_ETH0CKD 0x40000000 -#define TX4938_CLKCTR_SPICKD 0x20000000 -#define TX4938_CLKCTR_SRAMCKD 0x10000000 -#define TX4938_CLKCTR_PCIC1CKD 0x08000000 -#define TX4938_CLKCTR_DMA1CKD 0x04000000 -#define TX4938_CLKCTR_ACLCKD 0x02000000 -#define TX4938_CLKCTR_PIOCKD 0x01000000 -#define TX4938_CLKCTR_DMACKD 0x00800000 -#define TX4938_CLKCTR_PCICKD 0x00400000 -#define TX4938_CLKCTR_TM0CKD 0x00100000 -#define TX4938_CLKCTR_TM1CKD 0x00080000 -#define TX4938_CLKCTR_TM2CKD 0x00040000 -#define TX4938_CLKCTR_SIO0CKD 0x00020000 -#define TX4938_CLKCTR_SIO1CKD 0x00010000 -#define TX4938_CLKCTR_ETH1RST 0x00008000 -#define TX4938_CLKCTR_ETH0RST 0x00004000 -#define TX4938_CLKCTR_SPIRST 0x00002000 -#define TX4938_CLKCTR_SRAMRST 0x00001000 -#define TX4938_CLKCTR_PCIC1RST 0x00000800 -#define TX4938_CLKCTR_DMA1RST 0x00000400 -#define TX4938_CLKCTR_ACLRST 0x00000200 -#define TX4938_CLKCTR_PIORST 0x00000100 -#define TX4938_CLKCTR_DMARST 0x00000080 -#define TX4938_CLKCTR_PCIRST 0x00000040 -#define TX4938_CLKCTR_TM0RST 0x00000010 -#define TX4938_CLKCTR_TM1RST 0x00000008 -#define TX4938_CLKCTR_TM2RST 0x00000004 -#define TX4938_CLKCTR_SIO0RST 0x00000002 -#define TX4938_CLKCTR_SIO1RST 0x00000001 - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4938_PCIC_PBACFG_FIXPA 0x00000008 -#define TX4938_PCIC_PBACFG_RPBA 0x00000004 -#define TX4938_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4938_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8 -#define TX4938_PCIC_PCICSTATUS_PME 0x00000400 -#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200 -#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100 -#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080 -#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020 -#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010 -#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008 -#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002 -#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001 - -/* bits for PCICCFG */ -#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 -#define TX4938_PCIC_PCICCFG_HRST 0x00000800 -#define TX4938_PCIC_PCICCFG_SRST 0x00000400 -#define TX4938_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) -#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100 -#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080 -#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040 -#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020 -#define TX4938_PCIC_PCICCFG_TCAR 0x00000010 -#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32) - -/* bits for PDMCFG */ -#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000 -#define TX4938_PCIC_PDMCFG_EXFER 0x00100000 -#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800 -#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11) -#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400 -#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200 -#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100 -#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080 -#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040 -#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020 -#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c -#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 -#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 -#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 -#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002 -#define TX4938_PCIC_PDMCFG_CHRST 0x00000001 - -/* bits for PDMSTS */ -#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 -#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 -#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 -#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000 -#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800 -#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400 -#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200 -#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100 -#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080 -#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040 -#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020 -#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008 -#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004 -#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002 -#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001 -#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0 -#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f - -/* - * DMA - */ -/* bits for MCR */ -#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch)) -#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch)) -#define TX4938_DMA_MCR_RSFIF 0x00000080 -#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) -#define TX4938_DMA_MCR_RPRT 0x00000002 -#define TX4938_DMA_MCR_MSTEN 0x00000001 - -/* bits for CCRn */ -#define TX4938_DMA_CCR_IMMCHN 0x20000000 -#define TX4938_DMA_CCR_USEXFSZ 0x10000000 -#define TX4938_DMA_CCR_LE 0x08000000 -#define TX4938_DMA_CCR_DBINH 0x04000000 -#define TX4938_DMA_CCR_SBINH 0x02000000 -#define TX4938_DMA_CCR_CHRST 0x01000000 -#define TX4938_DMA_CCR_RVBYTE 0x00800000 -#define TX4938_DMA_CCR_ACKPOL 0x00400000 -#define TX4938_DMA_CCR_REQPL 0x00200000 -#define TX4938_DMA_CCR_EGREQ 0x00100000 -#define TX4938_DMA_CCR_CHDN 0x00080000 -#define TX4938_DMA_CCR_DNCTL 0x00060000 -#define TX4938_DMA_CCR_EXTRQ 0x00010000 -#define TX4938_DMA_CCR_INTRQD 0x0000e000 -#define TX4938_DMA_CCR_INTENE 0x00001000 -#define TX4938_DMA_CCR_INTENC 0x00000800 -#define TX4938_DMA_CCR_INTENT 0x00000400 -#define TX4938_DMA_CCR_CHNEN 0x00000200 -#define TX4938_DMA_CCR_XFACT 0x00000100 -#define TX4938_DMA_CCR_SMPCHN 0x00000020 -#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) -#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2) -#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3) -#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4) -#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5) -#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) -#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) -#define TX4938_DMA_CCR_MEMIO 0x00000002 -#define TX4938_DMA_CCR_SNGAD 0x00000001 - -/* bits for CSRn */ -#define TX4938_DMA_CSR_CHNEN 0x00000400 -#define TX4938_DMA_CSR_STLXFER 0x00000200 -#define TX4938_DMA_CSR_CHNACT 0x00000100 -#define TX4938_DMA_CSR_ABCHC 0x00000080 -#define TX4938_DMA_CSR_NCHNC 0x00000040 -#define TX4938_DMA_CSR_NTRNFC 0x00000020 -#define TX4938_DMA_CSR_EXTDN 0x00000010 -#define TX4938_DMA_CSR_CFERR 0x00000008 -#define TX4938_DMA_CSR_CHERR 0x00000004 -#define TX4938_DMA_CSR_DESERR 0x00000002 -#define TX4938_DMA_CSR_SORERR 0x00000001 - -#ifndef __ASSEMBLY__ - -#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) -#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) -#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) -#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) -#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) -#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) -#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) -#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) -#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) -#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) -#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) -#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) - - -#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) -#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) - -#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) -#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) - -#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) -#define TX4938_EBUSC_SIZE(ch) \ - (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) - - -#endif /* !__ASSEMBLY__ */ - -#endif diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h new file mode 100644 index 0000000..29e5498 --- /dev/null +++ b/include/asm-mips/txx9/jmr3927.h @@ -0,0 +1,177 @@ +/* + * Defines for the TJSYS JMR-TX3927 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000-2001 Toshiba Corporation + */ +#ifndef __ASM_TXX9_JMR3927_H +#define __ASM_TXX9_JMR3927_H + +#include +#include +#include +#include + +/* CS */ +#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ +#define JMR3927_ROMCE1 0x1e000000 /* 4M */ +#define JMR3927_ROMCE2 0x14000000 /* 16M */ +#define JMR3927_ROMCE3 0x10000000 /* 64M */ +#define JMR3927_ROMCE5 0x1d000000 /* 4M */ +#define JMR3927_SDCS0 0x00000000 /* 32M */ +#define JMR3927_SDCS1 0x02000000 /* 32M */ +/* PCI Direct Mappings */ + +#define JMR3927_PCIMEM 0x08000000 +#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */ +#define JMR3927_PCIIO 0x15000000 +#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */ + +#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ +#define JMR3927_PORT_BASE KSEG1 + +/* Address map (virtual address) */ +#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) +#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) +#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) +#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) +#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) + +#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) +#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) +#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) +#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) +#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) +#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000) +#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000) +#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000) +#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000) +#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) +#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) + +/* Flash ROM */ +#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) +#define JMR3927_FLASH_SIZE 0x00400000 + +/* bits for IOC_REV/IOC_BREV (high byte) */ +#define JMR3927_IDT_MASK 0xfc +#define JMR3927_REV_MASK 0x03 +#define JMR3927_IOC_IDT 0xe0 + +/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ +#define JMR3927_IOC_INTB_PCIA 0 +#define JMR3927_IOC_INTB_PCIB 1 +#define JMR3927_IOC_INTB_PCIC 2 +#define JMR3927_IOC_INTB_PCID 3 +#define JMR3927_IOC_INTB_MODEM 4 +#define JMR3927_IOC_INTB_INT6 5 +#define JMR3927_IOC_INTB_INT7 6 +#define JMR3927_IOC_INTB_SOFT 7 +#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA) +#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB) +#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC) +#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID) +#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM) +#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6) +#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7) +#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT) + +/* bits for IOC_RESET (high byte) */ +#define JMR3927_IOC_RESET_CPU 1 +#define JMR3927_IOC_RESET_PCI 2 + +#if defined(__BIG_ENDIAN) +#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) +#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) +#elif defined(__LITTLE_ENDIAN) +#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d)) +#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1)) +#else +#error "No Endian" +#endif + +/* LED macro */ +#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) + +#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) + +/* DIPSW4 macro */ +#define jmr3927_dipsw1() (gpio_get_value(11) == 0) +#define jmr3927_dipsw2() (gpio_get_value(10) == 0) +#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) +#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) + +/* + * IRQ mappings + */ + +/* These are the virtual IRQ numbers, we divide all IRQ's into + * 'spaces', the 'space' determines where and how to enable/disable + * that particular IRQ on an JMR machine. Add new 'spaces' as new + * IRQ hardware is supported. + */ +#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ +#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ + +#define JMR3927_IRQ_IRC TXX9_IRQ_BASE +#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) +#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) + +#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) +#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) +#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2) +#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3) +#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4) +#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) +#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) +#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) +#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) +#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) +#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) +#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) +#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) +#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) +#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) +#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) +#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID) +#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM) +#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) +#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) +#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) + +/* IOC (PCI, MODEM) */ +#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 +/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ +#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 + +/* Clocks */ +#define JMR3927_CORECLK 132710400 /* 132.7MHz */ +#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ +#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ + +/* + * TX3927 Pin Configuration: + * + * PCFG bits Avail Dead + * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3] + * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4] + * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF, + * GDBGE* PIO[2:1] + * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12] + * SELTMR[2:0]:000 TIMER[1:0] + * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6], + * DMAREQ[1],DMAACK[1] + * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8] + * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14] + * SELDONE:1 DMADONE PIO[7] + * + * Usable pins are: + * RXD[1;0],TXD[1:0],CTS[0],RTS[0], + * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11] + * INT[3:0] + */ + +#endif /* __ASM_TXX9_JMR3927_H */ diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h new file mode 100644 index 0000000..5531342 --- /dev/null +++ b/include/asm-mips/txx9/rbtx4927.h @@ -0,0 +1,49 @@ +/* + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_TXX9_RBTX4927_H +#define __ASM_TXX9_RBTX4927_H + +#include + +#ifdef CONFIG_PCI +#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO +#else +#define TBTX4927_ISA_IO_OFFSET 0 +#endif + +#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL +#define RBTX4927_SW_RESET_DO_SET 0x01 + +#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL +#define RBTX4927_SW_RESET_ENABLE_SET 0x01 + +#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) +#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) + +int toshiba_rbtx4927_irq_nested(int sw_irq); + +#endif /* __ASM_TXX9_RBTX4927_H */ diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h new file mode 100644 index 0000000..8450f73 --- /dev/null +++ b/include/asm-mips/txx9/rbtx4938.h @@ -0,0 +1,167 @@ +/* + * Definitions for TX4937/TX4938 + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TXX9_RBTX4938_H +#define __ASM_TXX9_RBTX4938_H + +#include +#include +#include + +/* CS */ +#define RBTX4938_CE0 0x1c000000 /* 64M */ +#define RBTX4938_CE2 0x17f00000 /* 1M */ + +/* Address map */ +#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) +#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) +#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) +#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) +#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) +#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) +#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) +#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) +#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) +#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) +#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) +#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) +#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) +#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) +#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) +#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) +#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) +#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) +#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) +#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) +#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) +#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) +#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) +#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) + +/* Ethernet port address (Jumperless Mode (W12:Open)) */ +#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) + +/* bits for ISTAT/IMASK/IMSTAT */ +#define RBTX4938_INTB_PCID 0 +#define RBTX4938_INTB_PCIC 1 +#define RBTX4938_INTB_PCIB 2 +#define RBTX4938_INTB_PCIA 3 +#define RBTX4938_INTB_RTC 4 +#define RBTX4938_INTB_ATA 5 +#define RBTX4938_INTB_MODEM 6 +#define RBTX4938_INTB_SWINT 7 +#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) +#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) +#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) +#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) +#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) +#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) +#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) +#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) + +#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR) +#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR) +#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR) +#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR) +#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR) +#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR) +#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR) +#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR) +#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR) +#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR) +#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR) +#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR) +#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR) +#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) +#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) +#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) +#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) +#define rbtx4938_softresetlock_addr \ + ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) +#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) + +/* + * IRQ mappings + */ + +#define RBTX4938_SOFT_INT0 0 /* not used */ +#define RBTX4938_SOFT_INT1 1 /* not used */ +#define RBTX4938_IRC_INT 2 +#define RBTX4938_TIMER_INT 7 + +/* These are the virtual IRQ numbers, we divide all IRQ's into + * 'spaces', the 'space' determines where and how to enable/disable + * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new + * IRQ hardware is supported. + */ +#define RBTX4938_NR_IRQ_LOCAL 8 +#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ +#define RBTX4938_NR_IRQ_IOC 8 + +#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE +#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) + +#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE +#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) +#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) +#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) +#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) +#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1) +#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7) + +#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0 +#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7 + +#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */ +#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */ +#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG +#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL) +#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC) +#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) + +#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0) +#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1) +#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT) +#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT) +#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) +#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) +#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) +#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) +#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) +#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) +#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) +#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) +#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) +#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) +#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) +#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) +#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) +#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) +#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) +#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) +#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) +#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) +#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) +#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) +#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) +#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) +#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) +#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) + + +/* IOC (PCI, etc) */ +#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) +/* Onboard 10M Ether */ +#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) + +#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) +#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) + +#endif /* __ASM_TXX9_RBTX4938_H */ diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h new file mode 100644 index 0000000..9375e4f --- /dev/null +++ b/include/asm-mips/txx9/smsc_fdc37m81x.h @@ -0,0 +1,67 @@ +/* + * Interface for smsc fdc48m81x Super IO chip + * + * Author: MontaVista Software, Inc. source@mvista.com + * + * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Manish Lachwani, mlachwani@mvista.com + */ + +#ifndef _SMSC_FDC37M81X_H_ +#define _SMSC_FDC37M81X_H_ + +/* Common Registers */ +#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 +#define SMSC_FDC37M81X_CONFIG_DATA 0x01 +#define SMSC_FDC37M81X_CONF 0x02 +#define SMSC_FDC37M81X_INDEX 0x03 +#define SMSC_FDC37M81X_DNUM 0x07 +#define SMSC_FDC37M81X_DID 0x20 +#define SMSC_FDC37M81X_DREV 0x21 +#define SMSC_FDC37M81X_PCNT 0x22 +#define SMSC_FDC37M81X_PMGT 0x23 +#define SMSC_FDC37M81X_OSC 0x24 +#define SMSC_FDC37M81X_CONFPA0 0x26 +#define SMSC_FDC37M81X_CONFPA1 0x27 +#define SMSC_FDC37M81X_TEST4 0x2B +#define SMSC_FDC37M81X_TEST5 0x2C +#define SMSC_FDC37M81X_TEST1 0x2D +#define SMSC_FDC37M81X_TEST2 0x2E +#define SMSC_FDC37M81X_TEST3 0x2F + +/* Logical device numbers */ +#define SMSC_FDC37M81X_FDD 0x00 +#define SMSC_FDC37M81X_PARALLEL 0x03 +#define SMSC_FDC37M81X_SERIAL1 0x04 +#define SMSC_FDC37M81X_SERIAL2 0x05 +#define SMSC_FDC37M81X_KBD 0x07 +#define SMSC_FDC37M81X_AUXIO 0x08 +#define SMSC_FDC37M81X_NONE 0xff + +/* Logical device Config Registers */ +#define SMSC_FDC37M81X_ACTIVE 0x30 +#define SMSC_FDC37M81X_BASEADDR0 0x60 +#define SMSC_FDC37M81X_BASEADDR1 0x61 +#define SMSC_FDC37M81X_INT 0x70 +#define SMSC_FDC37M81X_INT2 0x72 +#define SMSC_FDC37M81X_LDCR_F0 0xF0 + +/* Chip Config Values */ +#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 +#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa +#define SMSC_FDC37M81X_CHIP_ID 0x4d + +unsigned long __init smsc_fdc37m81x_init(unsigned long port); + +void smsc_fdc37m81x_config_beg(void); + +void smsc_fdc37m81x_config_end(void); + +void smsc_fdc37m81x_config_set(u8 reg, u8 val); + +#endif diff --git a/include/asm-mips/txx9/spi.h b/include/asm-mips/txx9/spi.h new file mode 100644 index 0000000..ddfb2a0 --- /dev/null +++ b/include/asm-mips/txx9/spi.h @@ -0,0 +1,19 @@ +/* + * Definitions for TX4937/TX4938 SPI + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TXX9_SPI_H +#define __ASM_TXX9_SPI_H + +extern int spi_eeprom_register(int chipid); +extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); + +#endif /* __ASM_TXX9_SPI_H */ diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h new file mode 100644 index 0000000..63b62d6 --- /dev/null +++ b/include/asm-mips/txx9/tx3927.h @@ -0,0 +1,319 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Toshiba Corporation + */ +#ifndef __ASM_TXX9_TX3927_H +#define __ASM_TXX9_TX3927_H + +#include + +#define TX3927_SDRAMC_REG 0xfffe8000 +#define TX3927_ROMC_REG 0xfffe9000 +#define TX3927_DMA_REG 0xfffeb000 +#define TX3927_IRC_REG 0xfffec000 +#define TX3927_PCIC_REG 0xfffed000 +#define TX3927_CCFG_REG 0xfffee000 +#define TX3927_NR_TMR 3 +#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100) +#define TX3927_NR_SIO 2 +#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) +#define TX3927_PIO_REG 0xfffef500 + +struct tx3927_sdramc_reg { + volatile unsigned long cr[8]; + volatile unsigned long tr[3]; + volatile unsigned long cmd; + volatile unsigned long smrs[2]; +}; + +struct tx3927_romc_reg { + volatile unsigned long cr[8]; +}; + +struct tx3927_dma_reg { + struct tx3927_dma_ch_reg { + volatile unsigned long cha; + volatile unsigned long sar; + volatile unsigned long dar; + volatile unsigned long cntr; + volatile unsigned long sair; + volatile unsigned long dair; + volatile unsigned long ccr; + volatile unsigned long csr; + } ch[4]; + volatile unsigned long dbr[8]; + volatile unsigned long tdhr; + volatile unsigned long mcr; + volatile unsigned long unused0; +}; + +#include + +#ifdef __BIG_ENDIAN +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 +#else +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 +#endif + +struct tx3927_pcic_reg { + endian_def_s2(did, vid); + endian_def_s2(pcistat, pcicmd); + endian_def_b4(cc, scc, rpli, rid); + endian_def_b4(unused0, ht, mlt, cls); + volatile unsigned long ioba; /* +10 */ + volatile unsigned long mba; + volatile unsigned long unused1[5]; + endian_def_s2(svid, ssvid); + volatile unsigned long unused2; /* +30 */ + endian_def_sb2(unused3, unused4, capptr); + volatile unsigned long unused5; + endian_def_b4(ml, mg, ip, il); + volatile unsigned long unused6; /* +40 */ + volatile unsigned long istat; + volatile unsigned long iim; + volatile unsigned long rrt; + volatile unsigned long unused7[3]; /* +50 */ + volatile unsigned long ipbmma; + volatile unsigned long ipbioma; /* +60 */ + volatile unsigned long ilbmma; + volatile unsigned long ilbioma; + volatile unsigned long unused8[9]; + volatile unsigned long tc; /* +90 */ + volatile unsigned long tstat; + volatile unsigned long tim; + volatile unsigned long tccmd; + volatile unsigned long pcirrt; /* +a0 */ + volatile unsigned long pcirrt_cmd; + volatile unsigned long pcirrdt; + volatile unsigned long unused9[3]; + volatile unsigned long tlboap; + volatile unsigned long tlbiap; + volatile unsigned long tlbmma; /* +c0 */ + volatile unsigned long tlbioma; + volatile unsigned long sc_msg; + volatile unsigned long sc_be; + volatile unsigned long tbl; /* +d0 */ + volatile unsigned long unused10[3]; + volatile unsigned long pwmng; /* +e0 */ + volatile unsigned long pwmngs; + volatile unsigned long unused11[6]; + volatile unsigned long req_trace; /* +100 */ + volatile unsigned long pbapmc; + volatile unsigned long pbapms; + volatile unsigned long pbapmim; + volatile unsigned long bm; /* +110 */ + volatile unsigned long cpcibrs; + volatile unsigned long cpcibgs; + volatile unsigned long pbacs; + volatile unsigned long iobas; /* +120 */ + volatile unsigned long mbas; + volatile unsigned long lbc; + volatile unsigned long lbstat; + volatile unsigned long lbim; /* +130 */ + volatile unsigned long pcistatim; + volatile unsigned long ica; + volatile unsigned long icd; + volatile unsigned long iiadp; /* +140 */ + volatile unsigned long iscdp; + volatile unsigned long mmas; + volatile unsigned long iomas; + volatile unsigned long ipciaddr; /* +150 */ + volatile unsigned long ipcidata; + volatile unsigned long ipcibe; +}; + +struct tx3927_ccfg_reg { + volatile unsigned long ccfg; + volatile unsigned long crir; + volatile unsigned long pcfg; + volatile unsigned long tear; + volatile unsigned long pdcr; +}; + +/* + * SDRAMC + */ + +/* + * ROMC + */ + +/* + * DMA + */ +/* bits for MCR */ +#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch)) +#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch)) +#define TX3927_DMA_MCR_RSFIF 0x00000080 +#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) +#define TX3927_DMA_MCR_LE 0x00000004 +#define TX3927_DMA_MCR_RPRT 0x00000002 +#define TX3927_DMA_MCR_MSTEN 0x00000001 + +/* bits for CCRn */ +#define TX3927_DMA_CCR_DBINH 0x04000000 +#define TX3927_DMA_CCR_SBINH 0x02000000 +#define TX3927_DMA_CCR_CHRST 0x01000000 +#define TX3927_DMA_CCR_RVBYTE 0x00800000 +#define TX3927_DMA_CCR_ACKPOL 0x00400000 +#define TX3927_DMA_CCR_REQPL 0x00200000 +#define TX3927_DMA_CCR_EGREQ 0x00100000 +#define TX3927_DMA_CCR_CHDN 0x00080000 +#define TX3927_DMA_CCR_DNCTL 0x00060000 +#define TX3927_DMA_CCR_EXTRQ 0x00010000 +#define TX3927_DMA_CCR_INTRQD 0x0000e000 +#define TX3927_DMA_CCR_INTENE 0x00001000 +#define TX3927_DMA_CCR_INTENC 0x00000800 +#define TX3927_DMA_CCR_INTENT 0x00000400 +#define TX3927_DMA_CCR_CHNEN 0x00000200 +#define TX3927_DMA_CCR_XFACT 0x00000100 +#define TX3927_DMA_CCR_SNOP 0x00000080 +#define TX3927_DMA_CCR_DSTINC 0x00000040 +#define TX3927_DMA_CCR_SRCINC 0x00000020 +#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) +#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2) +#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4) +#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5) +#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) +#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) +#define TX3927_DMA_CCR_MEMIO 0x00000002 +#define TX3927_DMA_CCR_ONEAD 0x00000001 + +/* bits for CSRn */ +#define TX3927_DMA_CSR_CHNACT 0x00000100 +#define TX3927_DMA_CSR_ABCHC 0x00000080 +#define TX3927_DMA_CSR_NCHNC 0x00000040 +#define TX3927_DMA_CSR_NTRNFC 0x00000020 +#define TX3927_DMA_CSR_EXTDN 0x00000010 +#define TX3927_DMA_CSR_CFERR 0x00000008 +#define TX3927_DMA_CSR_CHERR 0x00000004 +#define TX3927_DMA_CSR_DESERR 0x00000002 +#define TX3927_DMA_CSR_SORERR 0x00000001 + +/* + * IRC + */ +#define TX3927_IR_INT0 0 +#define TX3927_IR_INT1 1 +#define TX3927_IR_INT2 2 +#define TX3927_IR_INT3 3 +#define TX3927_IR_INT4 4 +#define TX3927_IR_INT5 5 +#define TX3927_IR_SIO0 6 +#define TX3927_IR_SIO1 7 +#define TX3927_IR_SIO(ch) (6 + (ch)) +#define TX3927_IR_DMA 8 +#define TX3927_IR_PIO 9 +#define TX3927_IR_PCI 10 +#define TX3927_IR_TMR(ch) (13 + (ch)) +#define TX3927_NUM_IR 16 + +/* + * PCIC + */ +/* bits for PCICMD */ +/* see PCI_COMMAND_XXX in linux/pci.h */ + +/* bits for PCISTAT */ +/* see PCI_STATUS_XXX in linux/pci.h */ +#define PCI_STATUS_NEW_CAP 0x0010 + +/* bits for TC */ +#define TX3927_PCIC_TC_OF16E 0x00000020 +#define TX3927_PCIC_TC_IF8E 0x00000010 +#define TX3927_PCIC_TC_OF8E 0x00000008 + +/* bits for IOBA/MBA */ +/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ + +/* bits for PBAPMC */ +#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 +#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002 +#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001 + +/* bits for LBSTAT/LBIM */ +#define TX3927_PCIC_LBIM_ALL 0x0000003e + +/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900 + +/* bits for LBC */ +#define TX3927_PCIC_LBC_IBSE 0x00004000 +#define TX3927_PCIC_LBC_TIBSE 0x00002000 +#define TX3927_PCIC_LBC_TMFBSE 0x00001000 +#define TX3927_PCIC_LBC_HRST 0x00000800 +#define TX3927_PCIC_LBC_SRST 0x00000400 +#define TX3927_PCIC_LBC_EPCAD 0x00000200 +#define TX3927_PCIC_LBC_MSDSE 0x00000100 +#define TX3927_PCIC_LBC_CRR 0x00000080 +#define TX3927_PCIC_LBC_ILMDE 0x00000040 +#define TX3927_PCIC_LBC_ILIDE 0x00000020 + +#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX3927_CCFG_TLBOFF 0x00020000 +#define TX3927_CCFG_BEOW 0x00010000 +#define TX3927_CCFG_WR 0x00008000 +#define TX3927_CCFG_TOE 0x00004000 +#define TX3927_CCFG_PCIXARB 0x00002000 +#define TX3927_CCFG_PCI3 0x00001000 +#define TX3927_CCFG_PSNP 0x00000800 +#define TX3927_CCFG_PPRI 0x00000400 +#define TX3927_CCFG_PLLM 0x00000030 +#define TX3927_CCFG_ENDIAN 0x00000004 +#define TX3927_CCFG_HALT 0x00000002 +#define TX3927_CCFG_ACEHOLD 0x00000001 + +/* PCFG : Pin Configuration */ +#define TX3927_PCFG_SYSCLKEN 0x08000000 +#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000 +#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch)) +#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000 +#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch)) +#define TX3927_PCFG_SELALL 0x0003ffff +#define TX3927_PCFG_SELCS 0x00020000 +#define TX3927_PCFG_SELDSF 0x00010000 +#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 +#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) +#define TX3927_PCFG_SELSIO_ALL 0x00003000 +#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch)) +#define TX3927_PCFG_SELTMR_ALL 0x00000e00 +#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch)) +#define TX3927_PCFG_SELDONE 0x00000100 +#define TX3927_PCFG_INTDMA_ALL 0x000000f0 +#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch)) +#define TX3927_PCFG_SELDMA_ALL 0x0000000f +#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) + +#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) +#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) +#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) +#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) +#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) +#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) +#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) +#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) + +#endif /* __ASM_TXX9_TX3927_H */ diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h new file mode 100644 index 0000000..f21a7b1 --- /dev/null +++ b/include/asm-mips/txx9/tx4927.h @@ -0,0 +1,280 @@ +/* + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2006 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_TXX9_TX4927_H +#define __ASM_TXX9_TX4927_H + +#include + +#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE +#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) + +#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE +#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) + + +#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) +#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) +#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) +#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) + +#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) + +#define TX4927_CCFG_TOE 0x00004000 +#define TX4927_CCFG_WR 0x00008000 +#define TX4927_CCFG_TINTDIS 0x01000000 + +#define TX4927_PCIMEM 0x08000000 +#define TX4927_PCIMEM_SIZE 0x08000000 +#define TX4927_PCIIO 0x16000000 +#define TX4927_PCIIO_SIZE 0x01000000 + +#define TX4927_SDRAMC_REG 0xff1f8000 +#define TX4927_EBUSC_REG 0xff1f9000 +#define TX4927_PCIC_REG 0xff1fd000 +#define TX4927_CCFG_REG 0xff1fe000 +#define TX4927_IRC_REG 0xff1ff600 +#define TX4927_NR_TMR 3 +#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) + +/* bits for ISTAT3/IMASK3/IMSTAT3 */ +#define TX4927_INT3B_PCID 0 +#define TX4927_INT3B_PCIC 1 +#define TX4927_INT3B_PCIB 2 +#define TX4927_INT3B_PCIA 3 +#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) +#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) +#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) +#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) + +#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG +#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ + +#define TX4927_IR_PCIC 16 +#define TX4927_IR_PCIERR 22 +#define TX4927_IR_PCIPMA 23 +#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) +#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) +#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) +#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) +#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) +#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) +#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) + +#ifdef _LANGUAGE_ASSEMBLY +#define _CONST64(c) c +#else +#define _CONST64(c) c##ull + +#include + +struct tx4927_sdramc_reg { + volatile unsigned long long cr[4]; + volatile unsigned long long unused0[4]; + volatile unsigned long long tr; + volatile unsigned long long unused1[2]; + volatile unsigned long long cmd; +}; + +struct tx4927_ebusc_reg { + volatile unsigned long long cr[8]; +}; + +struct tx4927_ccfg_reg { + volatile unsigned long long ccfg; + volatile unsigned long long crir; + volatile unsigned long long pcfg; + volatile unsigned long long tear; + volatile unsigned long long clkctr; + volatile unsigned long long unused0; + volatile unsigned long long garbc; + volatile unsigned long long unused1; + volatile unsigned long long unused2; + volatile unsigned long long ramp; +}; + +struct tx4927_pcic_reg { + volatile unsigned long pciid; + volatile unsigned long pcistatus; + volatile unsigned long pciccrev; + volatile unsigned long pcicfg1; + volatile unsigned long p2gm0plbase; /* +10 */ + volatile unsigned long p2gm0pubase; + volatile unsigned long p2gm1plbase; + volatile unsigned long p2gm1pubase; + volatile unsigned long p2gm2pbase; /* +20 */ + volatile unsigned long p2giopbase; + volatile unsigned long unused0; + volatile unsigned long pcisid; + volatile unsigned long unused1; /* +30 */ + volatile unsigned long pcicapptr; + volatile unsigned long unused2; + volatile unsigned long pcicfg2; + volatile unsigned long g2ptocnt; /* +40 */ + volatile unsigned long unused3[15]; + volatile unsigned long g2pstatus; /* +80 */ + volatile unsigned long g2pmask; + volatile unsigned long pcisstatus; + volatile unsigned long pcimask; + volatile unsigned long p2gcfg; /* +90 */ + volatile unsigned long p2gstatus; + volatile unsigned long p2gmask; + volatile unsigned long p2gccmd; + volatile unsigned long unused4[24]; /* +a0 */ + volatile unsigned long pbareqport; /* +100 */ + volatile unsigned long pbacfg; + volatile unsigned long pbastatus; + volatile unsigned long pbamask; + volatile unsigned long pbabm; /* +110 */ + volatile unsigned long pbacreq; + volatile unsigned long pbacgnt; + volatile unsigned long pbacstate; + volatile unsigned long long g2pmgbase[3]; /* +120 */ + volatile unsigned long long g2piogbase; + volatile unsigned long g2pmmask[3]; /* +140 */ + volatile unsigned long g2piomask; + volatile unsigned long long g2pmpbase[3]; /* +150 */ + volatile unsigned long long g2piopbase; + volatile unsigned long pciccfg; /* +170 */ + volatile unsigned long pcicstatus; + volatile unsigned long pcicmask; + volatile unsigned long unused5; + volatile unsigned long long p2gmgbase[3]; /* +180 */ + volatile unsigned long long p2giogbase; + volatile unsigned long g2pcfgadrs; /* +1a0 */ + volatile unsigned long g2pcfgdata; + volatile unsigned long unused6[8]; + volatile unsigned long g2pintack; + volatile unsigned long g2pspc; + volatile unsigned long unused7[12]; /* +1d0 */ + volatile unsigned long long pdmca; /* +200 */ + volatile unsigned long long pdmga; + volatile unsigned long long pdmpa; + volatile unsigned long long pdmcut; + volatile unsigned long long pdmcnt; /* +220 */ + volatile unsigned long long pdmsts; + volatile unsigned long long unused8[2]; + volatile unsigned long long pdmdb[4]; /* +240 */ + volatile unsigned long long pdmtdh; /* +260 */ + volatile unsigned long long pdmdms; +}; + +#endif /* _LANGUAGE_ASSEMBLY */ + +/* + * PCIC + */ + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4927_PCIC_PBACFG_RPBA 0x00000004 +#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for G2PIOGBASE */ +#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc + +/* bits for PCICCFG */ +#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 +#define TX4927_PCIC_PCICCFG_HRST 0x00000800 +#define TX4927_PCIC_PCICCFG_SRST 0x00000400 +#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 +#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 +#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 +#define TX4927_PCIC_PCICCFG_IISE 0x00000020 +#define TX4927_PCIC_PCICCFG_ATR 0x00000010 +#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) +#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) + +/* bits for P2GIOGBASE */ +#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) +#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) + +#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX4927_CCFG_PCI66 0x00800000 +#define TX4927_CCFG_PCIMIDE 0x00400000 +#define TX4927_CCFG_PCIXARB 0x00002000 +#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 +#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 +#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 +#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 +#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 + +#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 +#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 +#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 +#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 +#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 +#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 +#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 +#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 + +/* PCFG : Pin Configuration */ +#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 +#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) + +/* CLKCTR : Clock Control */ +#define TX4927_CLKCTR_PCICKD 0x00400000 +#define TX4927_CLKCTR_PCIRST 0x00000040 + +#ifndef _LANGUAGE_ASSEMBLY + +#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) +#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) +#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) +#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) + +#endif /* _LANGUAGE_ASSEMBLY */ + +#endif /* __ASM_TXX9_TX4927_H */ diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h new file mode 100644 index 0000000..7f9cfef --- /dev/null +++ b/include/asm-mips/txx9/tx4938.h @@ -0,0 +1,627 @@ +/* + * Definitions for TX4937/TX4938 + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TXX9_TX4938_H +#define __ASM_TXX9_TX4938_H + +#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) +#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) + +#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG + +#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC) +#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR) + +#define TX4938_PCIIO_0 0x10000000 +#define TX4938_PCIIO_1 0x01010000 +#define TX4938_PCIMEM_0 0x08000000 +#define TX4938_PCIMEM_1 0x11000000 + +#define TX4938_PCIIO_SIZE_0 0x01000000 +#define TX4938_PCIIO_SIZE_1 0x00010000 +#define TX4938_PCIMEM_SIZE_0 0x08000000 +#define TX4938_PCIMEM_SIZE_1 0x00010000 + +#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */ +#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ + +/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ +#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000) +#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000) +#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000) +#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000) +#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000) +#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800) +#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000) +#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000) +#define TX4938_NR_TMR 3 +#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100) +#define TX4938_NR_SIO 2 +#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100) +#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500) +#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600) +#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) +#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) + +#ifdef __ASSEMBLY__ +#define _CONST64(c) c +#else +#define _CONST64(c) c##ull + +#include + +#ifdef __BIG_ENDIAN +#define endian_def_l2(e1, e2) \ + volatile unsigned long e1, e2 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 +#else +#define endian_def_l2(e1, e2) \ + volatile unsigned long e2, e1 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 +#endif + + +struct tx4938_sdramc_reg { + volatile unsigned long long cr[4]; + volatile unsigned long long unused0[4]; + volatile unsigned long long tr; + volatile unsigned long long unused1[2]; + volatile unsigned long long cmd; + volatile unsigned long long sfcmd; +}; + +struct tx4938_ebusc_reg { + volatile unsigned long long cr[8]; +}; + +struct tx4938_dma_reg { + struct tx4938_dma_ch_reg { + volatile unsigned long long cha; + volatile unsigned long long sar; + volatile unsigned long long dar; + endian_def_l2(unused0, cntr); + endian_def_l2(unused1, sair); + endian_def_l2(unused2, dair); + endian_def_l2(unused3, ccr); + endian_def_l2(unused4, csr); + } ch[4]; + volatile unsigned long long dbr[8]; + volatile unsigned long long tdhr; + volatile unsigned long long midr; + endian_def_l2(unused0, mcr); +}; + +struct tx4938_pcic_reg { + volatile unsigned long pciid; + volatile unsigned long pcistatus; + volatile unsigned long pciccrev; + volatile unsigned long pcicfg1; + volatile unsigned long p2gm0plbase; /* +10 */ + volatile unsigned long p2gm0pubase; + volatile unsigned long p2gm1plbase; + volatile unsigned long p2gm1pubase; + volatile unsigned long p2gm2pbase; /* +20 */ + volatile unsigned long p2giopbase; + volatile unsigned long unused0; + volatile unsigned long pcisid; + volatile unsigned long unused1; /* +30 */ + volatile unsigned long pcicapptr; + volatile unsigned long unused2; + volatile unsigned long pcicfg2; + volatile unsigned long g2ptocnt; /* +40 */ + volatile unsigned long unused3[15]; + volatile unsigned long g2pstatus; /* +80 */ + volatile unsigned long g2pmask; + volatile unsigned long pcisstatus; + volatile unsigned long pcimask; + volatile unsigned long p2gcfg; /* +90 */ + volatile unsigned long p2gstatus; + volatile unsigned long p2gmask; + volatile unsigned long p2gccmd; + volatile unsigned long unused4[24]; /* +a0 */ + volatile unsigned long pbareqport; /* +100 */ + volatile unsigned long pbacfg; + volatile unsigned long pbastatus; + volatile unsigned long pbamask; + volatile unsigned long pbabm; /* +110 */ + volatile unsigned long pbacreq; + volatile unsigned long pbacgnt; + volatile unsigned long pbacstate; + volatile unsigned long long g2pmgbase[3]; /* +120 */ + volatile unsigned long long g2piogbase; + volatile unsigned long g2pmmask[3]; /* +140 */ + volatile unsigned long g2piomask; + volatile unsigned long long g2pmpbase[3]; /* +150 */ + volatile unsigned long long g2piopbase; + volatile unsigned long pciccfg; /* +170 */ + volatile unsigned long pcicstatus; + volatile unsigned long pcicmask; + volatile unsigned long unused5; + volatile unsigned long long p2gmgbase[3]; /* +180 */ + volatile unsigned long long p2giogbase; + volatile unsigned long g2pcfgadrs; /* +1a0 */ + volatile unsigned long g2pcfgdata; + volatile unsigned long unused6[8]; + volatile unsigned long g2pintack; + volatile unsigned long g2pspc; + volatile unsigned long unused7[12]; /* +1d0 */ + volatile unsigned long long pdmca; /* +200 */ + volatile unsigned long long pdmga; + volatile unsigned long long pdmpa; + volatile unsigned long long pdmctr; + volatile unsigned long long pdmcfg; /* +220 */ + volatile unsigned long long pdmsts; +}; + +struct tx4938_aclc_reg { + volatile unsigned long acctlen; + volatile unsigned long acctldis; + volatile unsigned long acregacc; + volatile unsigned long unused0; + volatile unsigned long acintsts; + volatile unsigned long acintmsts; + volatile unsigned long acinten; + volatile unsigned long acintdis; + volatile unsigned long acsemaph; + volatile unsigned long unused1[7]; + volatile unsigned long acgpidat; + volatile unsigned long acgpodat; + volatile unsigned long acslten; + volatile unsigned long acsltdis; + volatile unsigned long acfifosts; + volatile unsigned long unused2[11]; + volatile unsigned long acdmasts; + volatile unsigned long acdmasel; + volatile unsigned long unused3[6]; + volatile unsigned long acaudodat; + volatile unsigned long acsurrdat; + volatile unsigned long accentdat; + volatile unsigned long aclfedat; + volatile unsigned long acaudiat; + volatile unsigned long unused4; + volatile unsigned long acmodoat; + volatile unsigned long acmodidat; + volatile unsigned long unused5[15]; + volatile unsigned long acrevid; +}; + + +struct tx4938_tmr_reg { + volatile unsigned long tcr; + volatile unsigned long tisr; + volatile unsigned long cpra; + volatile unsigned long cprb; + volatile unsigned long itmr; + volatile unsigned long unused0[3]; + volatile unsigned long ccdr; + volatile unsigned long unused1[3]; + volatile unsigned long pgmr; + volatile unsigned long unused2[3]; + volatile unsigned long wtmr; + volatile unsigned long unused3[43]; + volatile unsigned long trr; +}; + +struct tx4938_sio_reg { + volatile unsigned long lcr; + volatile unsigned long dicr; + volatile unsigned long disr; + volatile unsigned long cisr; + volatile unsigned long fcr; + volatile unsigned long flcr; + volatile unsigned long bgr; + volatile unsigned long tfifo; + volatile unsigned long rfifo; +}; + +struct tx4938_ndfmc_reg { + endian_def_l2(unused0, dtr); + endian_def_l2(unused1, mcr); + endian_def_l2(unused2, sr); + endian_def_l2(unused3, isr); + endian_def_l2(unused4, imr); + endian_def_l2(unused5, spr); + endian_def_l2(unused6, rstr); +}; + +struct tx4938_spi_reg { + volatile unsigned long mcr; + volatile unsigned long cr0; + volatile unsigned long cr1; + volatile unsigned long fs; + volatile unsigned long unused1; + volatile unsigned long sr; + volatile unsigned long dr; + volatile unsigned long unused2; +}; + +struct tx4938_sramc_reg { + volatile unsigned long long cr; +}; + +struct tx4938_ccfg_reg { + volatile unsigned long long ccfg; + volatile unsigned long long crir; + volatile unsigned long long pcfg; + volatile unsigned long long tear; + volatile unsigned long long clkctr; + volatile unsigned long long unused0; + volatile unsigned long long garbc; + volatile unsigned long long unused1; + volatile unsigned long long unused2; + volatile unsigned long long ramp; + volatile unsigned long long unused3; + volatile unsigned long long jmpadr; +}; + +#undef endian_def_l2 +#undef endian_def_s2 +#undef endian_def_sb2 +#undef endian_def_b2s +#undef endian_def_b4 + +#endif /* __ASSEMBLY__ */ + +/* + * NDFMC + */ + +/* NDFMCR : NDFMC Mode Control */ +#define TX4938_NDFMCR_WE 0x80 +#define TX4938_NDFMCR_ECC_ALL 0x60 +#define TX4938_NDFMCR_ECC_RESET 0x60 +#define TX4938_NDFMCR_ECC_READ 0x40 +#define TX4938_NDFMCR_ECC_ON 0x20 +#define TX4938_NDFMCR_ECC_OFF 0x00 +#define TX4938_NDFMCR_CE 0x10 +#define TX4938_NDFMCR_BSPRT 0x04 +#define TX4938_NDFMCR_ALE 0x02 +#define TX4938_NDFMCR_CLE 0x01 + +/* NDFMCR : NDFMC Status */ +#define TX4938_NDFSR_BUSY 0x80 + +/* NDFMCR : NDFMC Reset */ +#define TX4938_NDFRSTR_RST 0x01 + +/* + * IRC + */ + +#define TX4938_IR_ECCERR 0 +#define TX4938_IR_WTOERR 1 +#define TX4938_NUM_IR_INT 6 +#define TX4938_IR_INT(n) (2 + (n)) +#define TX4938_NUM_IR_SIO 2 +#define TX4938_IR_SIO(n) (8 + (n)) +#define TX4938_NUM_IR_DMA 4 +#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ +#define TX4938_IR_PIO 14 +#define TX4938_IR_PDMAC 15 +#define TX4938_IR_PCIC 16 +#define TX4938_NUM_IR_TMR 3 +#define TX4938_IR_TMR(n) (17 + (n)) +#define TX4938_IR_NDFMC 21 +#define TX4938_IR_PCIERR 22 +#define TX4938_IR_PCIPME 23 +#define TX4938_IR_ACLC 24 +#define TX4938_IR_ACLCPME 25 +#define TX4938_IR_PCIC1 26 +#define TX4938_IR_SPI 31 +#define TX4938_NUM_IR 32 +/* multiplex */ +#define TX4938_IR_ETH0 TX4938_IR_INT(4) +#define TX4938_IR_ETH1 TX4938_IR_INT(3) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) +#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) +#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) +#define TX4938_CCFG_TINTDIS 0x01000000 +#define TX4938_CCFG_PCI66 0x00800000 +#define TX4938_CCFG_PCIMODE 0x00400000 +#define TX4938_CCFG_PCI1_66 0x00200000 +#define TX4938_CCFG_DIVMODE_MASK 0x001e0000 +#define TX4938_CCFG_DIVMODE_2 (0x4 << 17) +#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) +#define TX4938_CCFG_DIVMODE_3 (0x5 << 17) +#define TX4938_CCFG_DIVMODE_4 (0x6 << 17) +#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) +#define TX4938_CCFG_DIVMODE_8 (0x0 << 17) +#define TX4938_CCFG_DIVMODE_10 (0xb << 17) +#define TX4938_CCFG_DIVMODE_12 (0x1 << 17) +#define TX4938_CCFG_DIVMODE_16 (0x2 << 17) +#define TX4938_CCFG_DIVMODE_18 (0x9 << 17) +#define TX4938_CCFG_BEOW 0x00010000 +#define TX4938_CCFG_WR 0x00008000 +#define TX4938_CCFG_TOE 0x00004000 +#define TX4938_CCFG_PCIXARB 0x00002000 +#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) +#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) +#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10) +#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10) +#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10) +#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10) +#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10) +#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10) +#define TX4938_CCFG_PCI1DMD 0x00000100 +#define TX4938_CCFG_SYSSP_MASK 0x000000c0 +#define TX4938_CCFG_ENDIAN 0x00000004 +#define TX4938_CCFG_HALT 0x00000002 +#define TX4938_CCFG_ACEHOLD 0x00000001 + +/* PCFG : Pin Configuration */ +#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) +#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) +#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) +#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) +#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) +#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) +#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 +#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) +#define TX4938_PCFG_SYSCLKEN 0x08000000 +#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 +#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) +#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000 +#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) +#define TX4938_PCFG_SEL2 0x00000200 +#define TX4938_PCFG_SEL1 0x00000100 +#define TX4938_PCFG_DMASEL_ALL 0x0000000f +#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000 +#define TX4938_PCFG_DMASEL0_SIO1 0x00000001 +#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000 +#define TX4938_PCFG_DMASEL1_SIO1 0x00000002 +#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000 +#define TX4938_PCFG_DMASEL2_SIO0 0x00000004 +#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000 +#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 + +/* CLKCTR : Clock Control */ +#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) +#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) +#define TX4938_CLKCTR_ETH1CKD 0x80000000 +#define TX4938_CLKCTR_ETH0CKD 0x40000000 +#define TX4938_CLKCTR_SPICKD 0x20000000 +#define TX4938_CLKCTR_SRAMCKD 0x10000000 +#define TX4938_CLKCTR_PCIC1CKD 0x08000000 +#define TX4938_CLKCTR_DMA1CKD 0x04000000 +#define TX4938_CLKCTR_ACLCKD 0x02000000 +#define TX4938_CLKCTR_PIOCKD 0x01000000 +#define TX4938_CLKCTR_DMACKD 0x00800000 +#define TX4938_CLKCTR_PCICKD 0x00400000 +#define TX4938_CLKCTR_TM0CKD 0x00100000 +#define TX4938_CLKCTR_TM1CKD 0x00080000 +#define TX4938_CLKCTR_TM2CKD 0x00040000 +#define TX4938_CLKCTR_SIO0CKD 0x00020000 +#define TX4938_CLKCTR_SIO1CKD 0x00010000 +#define TX4938_CLKCTR_ETH1RST 0x00008000 +#define TX4938_CLKCTR_ETH0RST 0x00004000 +#define TX4938_CLKCTR_SPIRST 0x00002000 +#define TX4938_CLKCTR_SRAMRST 0x00001000 +#define TX4938_CLKCTR_PCIC1RST 0x00000800 +#define TX4938_CLKCTR_DMA1RST 0x00000400 +#define TX4938_CLKCTR_ACLRST 0x00000200 +#define TX4938_CLKCTR_PIORST 0x00000100 +#define TX4938_CLKCTR_DMARST 0x00000080 +#define TX4938_CLKCTR_PCIRST 0x00000040 +#define TX4938_CLKCTR_TM0RST 0x00000010 +#define TX4938_CLKCTR_TM1RST 0x00000008 +#define TX4938_CLKCTR_TM2RST 0x00000004 +#define TX4938_CLKCTR_SIO0RST 0x00000002 +#define TX4938_CLKCTR_SIO1RST 0x00000001 + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4938_PCIC_PBACFG_FIXPA 0x00000008 +#define TX4938_PCIC_PBACFG_RPBA 0x00000004 +#define TX4938_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4938_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for G2PIOGBASE */ +#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8 +#define TX4938_PCIC_PCICSTATUS_PME 0x00000400 +#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200 +#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100 +#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080 +#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020 +#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010 +#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008 +#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002 +#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001 + +/* bits for PCICCFG */ +#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 +#define TX4938_PCIC_PCICCFG_HRST 0x00000800 +#define TX4938_PCIC_PCICCFG_SRST 0x00000400 +#define TX4938_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) +#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100 +#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080 +#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040 +#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020 +#define TX4938_PCIC_PCICCFG_TCAR 0x00000010 +#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) +#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) + +/* bits for P2GIOGBASE */ +#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) +#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) + +#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32) + +/* bits for PDMCFG */ +#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000 +#define TX4938_PCIC_PDMCFG_EXFER 0x00100000 +#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800 +#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11) +#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400 +#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200 +#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100 +#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080 +#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040 +#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020 +#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c +#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 +#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 +#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 +#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002 +#define TX4938_PCIC_PDMCFG_CHRST 0x00000001 + +/* bits for PDMSTS */ +#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 +#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 +#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 +#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000 +#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800 +#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400 +#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200 +#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100 +#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080 +#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040 +#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020 +#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008 +#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004 +#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002 +#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001 +#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0 +#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f + +/* + * DMA + */ +/* bits for MCR */ +#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch)) +#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch)) +#define TX4938_DMA_MCR_RSFIF 0x00000080 +#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) +#define TX4938_DMA_MCR_RPRT 0x00000002 +#define TX4938_DMA_MCR_MSTEN 0x00000001 + +/* bits for CCRn */ +#define TX4938_DMA_CCR_IMMCHN 0x20000000 +#define TX4938_DMA_CCR_USEXFSZ 0x10000000 +#define TX4938_DMA_CCR_LE 0x08000000 +#define TX4938_DMA_CCR_DBINH 0x04000000 +#define TX4938_DMA_CCR_SBINH 0x02000000 +#define TX4938_DMA_CCR_CHRST 0x01000000 +#define TX4938_DMA_CCR_RVBYTE 0x00800000 +#define TX4938_DMA_CCR_ACKPOL 0x00400000 +#define TX4938_DMA_CCR_REQPL 0x00200000 +#define TX4938_DMA_CCR_EGREQ 0x00100000 +#define TX4938_DMA_CCR_CHDN 0x00080000 +#define TX4938_DMA_CCR_DNCTL 0x00060000 +#define TX4938_DMA_CCR_EXTRQ 0x00010000 +#define TX4938_DMA_CCR_INTRQD 0x0000e000 +#define TX4938_DMA_CCR_INTENE 0x00001000 +#define TX4938_DMA_CCR_INTENC 0x00000800 +#define TX4938_DMA_CCR_INTENT 0x00000400 +#define TX4938_DMA_CCR_CHNEN 0x00000200 +#define TX4938_DMA_CCR_XFACT 0x00000100 +#define TX4938_DMA_CCR_SMPCHN 0x00000020 +#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) +#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2) +#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3) +#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4) +#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5) +#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) +#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) +#define TX4938_DMA_CCR_MEMIO 0x00000002 +#define TX4938_DMA_CCR_SNGAD 0x00000001 + +/* bits for CSRn */ +#define TX4938_DMA_CSR_CHNEN 0x00000400 +#define TX4938_DMA_CSR_STLXFER 0x00000200 +#define TX4938_DMA_CSR_CHNACT 0x00000100 +#define TX4938_DMA_CSR_ABCHC 0x00000080 +#define TX4938_DMA_CSR_NCHNC 0x00000040 +#define TX4938_DMA_CSR_NTRNFC 0x00000020 +#define TX4938_DMA_CSR_EXTDN 0x00000010 +#define TX4938_DMA_CSR_CFERR 0x00000008 +#define TX4938_DMA_CSR_CHERR 0x00000004 +#define TX4938_DMA_CSR_DESERR 0x00000002 +#define TX4938_DMA_CSR_SORERR 0x00000001 + +#ifndef __ASSEMBLY__ + +#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) +#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) +#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) +#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) +#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) +#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) +#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) +#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) +#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) +#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) +#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) +#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) + + +#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) +#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) + +#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) +#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) + +#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) +#define TX4938_EBUSC_SIZE(ch) \ + (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) + + +#endif /* !__ASSEMBLY__ */ + +#endif diff --git a/include/asm-mips/txx9/txx927.h b/include/asm-mips/txx9/txx927.h new file mode 100644 index 0000000..97dd7ad --- /dev/null +++ b/include/asm-mips/txx9/txx927.h @@ -0,0 +1,121 @@ +/* + * Common definitions for TX3927/TX4927 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Toshiba Corporation + */ +#ifndef __ASM_TXX9_TXX927_H +#define __ASM_TXX9_TXX927_H + +struct txx927_sio_reg { + volatile unsigned long lcr; + volatile unsigned long dicr; + volatile unsigned long disr; + volatile unsigned long cisr; + volatile unsigned long fcr; + volatile unsigned long flcr; + volatile unsigned long bgr; + volatile unsigned long tfifo; + volatile unsigned long rfifo; +}; + +/* + * SIO + */ +/* SILCR : Line Control */ +#define TXx927_SILCR_SCS_MASK 0x00000060 +#define TXx927_SILCR_SCS_IMCLK 0x00000000 +#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020 +#define TXx927_SILCR_SCS_SCLK 0x00000040 +#define TXx927_SILCR_SCS_SCLK_BG 0x00000060 +#define TXx927_SILCR_UEPS 0x00000010 +#define TXx927_SILCR_UPEN 0x00000008 +#define TXx927_SILCR_USBL_MASK 0x00000004 +#define TXx927_SILCR_USBL_1BIT 0x00000004 +#define TXx927_SILCR_USBL_2BIT 0x00000000 +#define TXx927_SILCR_UMODE_MASK 0x00000003 +#define TXx927_SILCR_UMODE_8BIT 0x00000000 +#define TXx927_SILCR_UMODE_7BIT 0x00000001 + +/* SIDICR : DMA/Int. Control */ +#define TXx927_SIDICR_TDE 0x00008000 +#define TXx927_SIDICR_RDE 0x00004000 +#define TXx927_SIDICR_TIE 0x00002000 +#define TXx927_SIDICR_RIE 0x00001000 +#define TXx927_SIDICR_SPIE 0x00000800 +#define TXx927_SIDICR_CTSAC 0x00000600 +#define TXx927_SIDICR_STIE_MASK 0x0000003f +#define TXx927_SIDICR_STIE_OERS 0x00000020 +#define TXx927_SIDICR_STIE_CTSS 0x00000010 +#define TXx927_SIDICR_STIE_RBRKD 0x00000008 +#define TXx927_SIDICR_STIE_TRDY 0x00000004 +#define TXx927_SIDICR_STIE_TXALS 0x00000002 +#define TXx927_SIDICR_STIE_UBRKD 0x00000001 + +/* SIDISR : DMA/Int. Status */ +#define TXx927_SIDISR_UBRK 0x00008000 +#define TXx927_SIDISR_UVALID 0x00004000 +#define TXx927_SIDISR_UFER 0x00002000 +#define TXx927_SIDISR_UPER 0x00001000 +#define TXx927_SIDISR_UOER 0x00000800 +#define TXx927_SIDISR_ERI 0x00000400 +#define TXx927_SIDISR_TOUT 0x00000200 +#define TXx927_SIDISR_TDIS 0x00000100 +#define TXx927_SIDISR_RDIS 0x00000080 +#define TXx927_SIDISR_STIS 0x00000040 +#define TXx927_SIDISR_RFDN_MASK 0x0000001f + +/* SICISR : Change Int. Status */ +#define TXx927_SICISR_OERS 0x00000020 +#define TXx927_SICISR_CTSS 0x00000010 +#define TXx927_SICISR_RBRKD 0x00000008 +#define TXx927_SICISR_TRDY 0x00000004 +#define TXx927_SICISR_TXALS 0x00000002 +#define TXx927_SICISR_UBRKD 0x00000001 + +/* SIFCR : FIFO Control */ +#define TXx927_SIFCR_SWRST 0x00008000 +#define TXx927_SIFCR_RDIL_MASK 0x00000180 +#define TXx927_SIFCR_RDIL_1 0x00000000 +#define TXx927_SIFCR_RDIL_4 0x00000080 +#define TXx927_SIFCR_RDIL_8 0x00000100 +#define TXx927_SIFCR_RDIL_12 0x00000180 +#define TXx927_SIFCR_RDIL_MAX 0x00000180 +#define TXx927_SIFCR_TDIL_MASK 0x00000018 +#define TXx927_SIFCR_TDIL_MASK 0x00000018 +#define TXx927_SIFCR_TDIL_1 0x00000000 +#define TXx927_SIFCR_TDIL_4 0x00000001 +#define TXx927_SIFCR_TDIL_8 0x00000010 +#define TXx927_SIFCR_TDIL_MAX 0x00000010 +#define TXx927_SIFCR_TFRST 0x00000004 +#define TXx927_SIFCR_RFRST 0x00000002 +#define TXx927_SIFCR_FRSTE 0x00000001 +#define TXx927_SIO_TX_FIFO 8 +#define TXx927_SIO_RX_FIFO 16 + +/* SIFLCR : Flow Control */ +#define TXx927_SIFLCR_RCS 0x00001000 +#define TXx927_SIFLCR_TES 0x00000800 +#define TXx927_SIFLCR_RTSSC 0x00000200 +#define TXx927_SIFLCR_RSDE 0x00000100 +#define TXx927_SIFLCR_TSDE 0x00000080 +#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e +#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e +#define TXx927_SIFLCR_TBRK 0x00000001 + +/* SIBGR : Baudrate Control */ +#define TXx927_SIBGR_BCLK_MASK 0x00000300 +#define TXx927_SIBGR_BCLK_T0 0x00000000 +#define TXx927_SIBGR_BCLK_T2 0x00000100 +#define TXx927_SIBGR_BCLK_T4 0x00000200 +#define TXx927_SIBGR_BCLK_T6 0x00000300 +#define TXx927_SIBGR_BRD_MASK 0x000000ff + +/* + * PIO + */ + +#endif /* __ASM_TXX9_TXX927_H */ From anemo@mba.ocn.ne.jp Thu Jul 10 16:31:30 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 10 Jul 2008 16:31:36 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:7897 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20026554AbYGJPba (ORCPT ); Thu, 10 Jul 2008 16:31:30 +0100 Received: from localhost (p7221-ipad210funabasi.chiba.ocn.ne.jp [58.88.126.221]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 8FD38AABB; Fri, 11 Jul 2008 00:31:22 +0900 (JST) Date: Fri, 11 Jul 2008 00:33:08 +0900 (JST) Message-Id: <20080711.003308.108121397.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 2/3] reorganize txx9 pci code From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19762 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 151592 Lines: 4745 Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto --- arch/mips/Kconfig | 3 +- arch/mips/pci/Makefile | 8 +- arch/mips/pci/fixup-jmr3927.c | 25 +- arch/mips/pci/fixup-rbtx4927.c | 112 ++----- arch/mips/pci/fixup-rbtx4938.c | 52 +--- arch/mips/pci/ops-tx3927.c | 87 +++++- arch/mips/pci/ops-tx4927.c | 514 +++++++++++++++++++--------- arch/mips/pci/ops-tx4938.c | 214 ------------ arch/mips/pci/pci-jmr3927.c | 58 --- arch/mips/pci/pci-tx4927.c | 83 +++++ arch/mips/pci/pci-tx4938.c | 134 +++++++ arch/mips/txx9/Kconfig | 11 +- arch/mips/txx9/generic/Makefile | 2 + arch/mips/txx9/generic/pci.c | 377 ++++++++++++++++++++ arch/mips/txx9/generic/setup.c | 51 +++ arch/mips/txx9/jmr3927/irq.c | 2 + arch/mips/txx9/jmr3927/setup.c | 108 ++----- arch/mips/txx9/rbtx4927/irq.c | 20 +- arch/mips/txx9/rbtx4927/setup.c | 499 +++++++-------------------- arch/mips/txx9/rbtx4938/setup.c | 667 ++++++------------------------------ include/asm-mips/txx9/generic.h | 23 ++ include/asm-mips/txx9/pci.h | 36 ++ include/asm-mips/txx9/rbtx4927.h | 29 ++- include/asm-mips/txx9/tx3927.h | 4 + include/asm-mips/txx9/tx4927.h | 318 +++++++---------- include/asm-mips/txx9/tx4927pcic.h | 199 +++++++++++ include/asm-mips/txx9/tx4938.h | 226 ++----------- 27 files changed, 1851 insertions(+), 2011 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3202960..2ea6fff 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -575,7 +575,7 @@ config TOSHIBA_RBTX4927 select HW_HAS_PCI select IRQ_CPU select IRQ_TXX9 - select I8259 if TOSHIBA_FPCIB0 + select PCI_TX4927 select SWAP_IO_SPACE select SYS_HAS_CPU_TX49XX select SYS_SUPPORTS_32BIT_KERNEL @@ -598,6 +598,7 @@ config TOSHIBA_RBTX4938 select HW_HAS_PCI select IRQ_CPU select IRQ_TXX9 + select PCI_TX4927 select SWAP_IO_SPACE select SYS_HAS_CPU_TX49XX select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 4608e43..9087648 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -15,6 +15,8 @@ obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o +obj-$(CONFIG_PCI_TX3927) += ops-tx3927.o +obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o # # These are still pretty much in the old state, watch, go blind. @@ -41,9 +43,9 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o -obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o -obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o -obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o ops-tx4938.o +obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o +obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o pci-tx4927.o pci-tx4938.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o pci-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index 41dcd6a..d5edaf2 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -28,36 +28,31 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include -#include - +#include #include int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; - /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ - if (dev->vendor == PCI_VENDOR_ID_EFAR && - dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1) - return irq; /* IRQ rotation (PICMG) */ irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) { + if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) { /* PCI CardSlot (IDSEL=A23, DevNu=12) */ /* PCIA => PCIC (IDSEL=A23) */ /* NOTE: JMR3927 JP1 must be set to OPEN */ irq = (irq + 2) % 4; - } else if (dev->bus->parent == NULL && - slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) { + } else if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) { /* PCI CardSlot (IDSEL=A22, DevNu=11) */ /* PCIA => PCIA (IDSEL=A22) */ /* NOTE: JMR3927 JP1 must be set to OPEN */ irq = (irq + 0) % 4; } else { /* PCI Backplane */ - irq = (irq + 3 + slot) % 4; + if (txx9_pci_option & TXX9_PCI_OPT_PICMG) + irq = (irq + 33 - slot) % 4; + else + irq = (irq + 3 + slot) % 4; } irq++; /* 1-4 */ @@ -66,15 +61,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) irq = JMR3927_IRQ_IOC_PCIA; break; case 2: - // wrong for backplane irq = JMR3927_IRQ_IOC_PCIB; - irq = JMR3927_IRQ_IOC_PCID; + irq = JMR3927_IRQ_IOC_PCIB; break; case 3: irq = JMR3927_IRQ_IOC_PCIC; break; case 4: - // wrong for backplane irq = JMR3927_IRQ_IOC_PCID; - irq = JMR3927_IRQ_IOC_PCIB; + irq = JMR3927_IRQ_IOC_PCID; break; } diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 26013ba..abab485 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -33,102 +33,42 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include -#include -#include +#include +#include -#include - -#undef DEBUG -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -/* look up table for backplane pci irq for slots 17-20 by pin # */ -static unsigned char backplane_pci_irq[4][4] = { - /* PJ6 SLOT: 17, PIN: 1 */ {TX4927_IRQ_IOC_PCIA, - /* PJ6 SLOT: 17, PIN: 2 */ - TX4927_IRQ_IOC_PCIB, - /* PJ6 SLOT: 17, PIN: 3 */ - TX4927_IRQ_IOC_PCIC, - /* PJ6 SLOT: 17, PIN: 4 */ - TX4927_IRQ_IOC_PCID}, - /* SB SLOT: 18, PIN: 1 */ {TX4927_IRQ_IOC_PCIB, - /* SB SLOT: 18, PIN: 2 */ - TX4927_IRQ_IOC_PCIC, - /* SB SLOT: 18, PIN: 3 */ - TX4927_IRQ_IOC_PCID, - /* SB SLOT: 18, PIN: 4 */ - TX4927_IRQ_IOC_PCIA}, - /* PJ5 SLOT: 19, PIN: 1 */ {TX4927_IRQ_IOC_PCIC, - /* PJ5 SLOT: 19, PIN: 2 */ - TX4927_IRQ_IOC_PCID, - /* PJ5 SLOT: 19, PIN: 3 */ - TX4927_IRQ_IOC_PCIA, - /* PJ5 SLOT: 19, PIN: 4 */ - TX4927_IRQ_IOC_PCIB}, - /* PJ4 SLOT: 20, PIN: 1 */ {TX4927_IRQ_IOC_PCID, - /* PJ4 SLOT: 20, PIN: 2 */ - TX4927_IRQ_IOC_PCIA, - /* PJ4 SLOT: 20, PIN: 3 */ - TX4927_IRQ_IOC_PCIB, - /* PJ4 SLOT: 20, PIN: 4 */ - TX4927_IRQ_IOC_PCIC} -}; - -static int pci_get_irq(const struct pci_dev *dev, int pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; - DBG("pci_get_irq: pin is %d\n", pin); /* IRQ rotation */ irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - PCI_SLOT(dev->devfn) == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { - printk("Onboard PCI_SLOT(dev->devfn) is %d\n", - PCI_SLOT(dev->devfn)); - /* IDSEL=A23 is tx4927 onboard pci slot */ - irq = (irq + PCI_SLOT(dev->devfn)) % 4; - irq++; /* 1-4 */ - DBG("irq is now %d\n", irq); - - switch (irq) { - case 1: - irq = TX4927_IRQ_IOC_PCIA; - break; - case 2: - irq = TX4927_IRQ_IOC_PCIB; - break; - case 3: - irq = TX4927_IRQ_IOC_PCIC; - break; - case 4: - irq = TX4927_IRQ_IOC_PCID; - break; - } + if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { + /* PCI CardSlot (IDSEL=A23) */ + /* PCIA => PCIA */ + irq = (irq + 0 + slot) % 4; } else { /* PCI Backplane */ - DBG("PCI Backplane PCI_SLOT(dev->devfn) is %d\n", - PCI_SLOT(dev->devfn)); - irq = backplane_pci_irq[PCI_SLOT(dev->devfn) - 17][irq]; + if (txx9_pci_option & TXX9_PCI_OPT_PICMG) + irq = (irq + 33 - slot) % 4; + else + irq = (irq + 3 + slot) % 4; } - DBG("assigned irq %d\n", irq); - return irq; -} - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned char irq; - - printk("PCI Setup for pin %d \n", pin); - - if (dev->device == 0x9130) /* IDE */ - irq = 14; - else - irq = pci_get_irq(dev, pin); + irq++; /* 1-4 */ + switch (irq) { + case 1: + irq = RBTX4927_IRQ_IOC_PCIA; + break; + case 2: + irq = RBTX4927_IRQ_IOC_PCIB; + break; + case 3: + irq = RBTX4927_IRQ_IOC_PCIC; + break; + case 4: + irq = RBTX4927_IRQ_IOC_PCID; + break; + } return irq; } diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c index 64d4510..39c9958 100644 --- a/arch/mips/pci/fixup-rbtx4938.c +++ b/arch/mips/pci/fixup-rbtx4938.c @@ -10,45 +10,28 @@ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) */ #include -#include -#include -#include - +#include #include -extern struct pci_controller tx4938_pci_controller[]; - -static int pci_get_irq(const struct pci_dev *dev, int pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - int irq = pin; - u8 slot = PCI_SLOT(dev->devfn); - struct pci_controller *controller = (struct pci_controller *)dev->sysdata; - - if (controller == &tx4938_pci_controller[1]) { - /* TX4938 PCIC1 */ - switch (slot) { - case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; - break; - case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; - break; - } - return 0; - } + int irq = tx4938_pcic1_map_irq(dev, slot); + if (irq >= 0) + return irq; + irq = pin; /* IRQ rotation */ irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { + if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { /* PCI CardSlot (IDSEL=A23) */ /* PCIA => PCIA (IDSEL=A23) */ irq = (irq + 0 + slot) % 4; } else { /* PCI Backplane */ - irq = (irq + 33 - slot) % 4; + if (txx9_pci_option & TXX9_PCI_OPT_PICMG) + irq = (irq + 33 - slot) % 4; + else + irq = (irq + 3 + slot) % 4; } irq++; /* 1-4 */ @@ -69,19 +52,6 @@ static int pci_get_irq(const struct pci_dev *dev, int pin) return irq; } -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned char irq = 0; - - irq = pci_get_irq(dev, pin); - - printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", - dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), irq); - - return irq; -} - /* * Do platform specific device initialization at pci_enable_device() time */ diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c index 5d398f6..8a17a39 100644 --- a/arch/mips/pci/ops-tx3927.c +++ b/arch/mips/pci/ops-tx3927.c @@ -8,7 +8,7 @@ * * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c * - * Define the pci_ops for JMR3927. + * Define the pci_ops for TX3927. * * Much of the code is derived from the original DDB5074 port by * Geert Uytterhoeven @@ -39,7 +39,7 @@ #include #include -#include +#include static inline int mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where) @@ -68,7 +68,7 @@ static inline int check_abort(void) return PCIBIOS_SUCCESSFUL; } -static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, +static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) { int ret; @@ -94,7 +94,7 @@ static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, return check_abort(); } -static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, +static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { int ret; @@ -125,7 +125,80 @@ static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, return check_abort(); } -struct pci_ops jmr3927_pci_ops = { - jmr3927_pci_read_config, - jmr3927_pci_write_config, +static struct pci_ops tx3927_pci_ops = { + .read = tx3927_pci_read_config, + .write = tx3927_pci_write_config, }; + +void __init tx3927_pcic_setup(struct pci_controller *channel, + unsigned long sdram_size, int extarb) +{ + unsigned long flags; + unsigned long io_base = + channel->io_resource->start + mips_io_port_base - IO_BASE; + unsigned long io_size = + channel->io_resource->end - channel->io_resource->start; + unsigned long io_pciaddr = + channel->io_resource->start - channel->io_offset; + unsigned long mem_base = + channel->mem_resource->start; + unsigned long mem_size = + channel->mem_resource->end - channel->mem_resource->start; + unsigned long mem_pciaddr = + channel->mem_resource->start - channel->mem_offset; + + printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s", + tx3927_pcicptr->did, tx3927_pcicptr->vid, + tx3927_pcicptr->rid, + extarb ? "External" : "Internal"); + channel->pci_ops = &tx3927_pci_ops; + + local_irq_save(flags); + /* Disable External PCI Config. Access */ + tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; +#ifdef __BIG_ENDIAN + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | + TX3927_PCIC_LBC_TIBSE | + TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; +#endif + /* LB->PCI mappings */ + tx3927_pcicptr->iomas = ~(io_size - 1); + tx3927_pcicptr->ilbioma = io_base; + tx3927_pcicptr->ipbioma = io_pciaddr; + tx3927_pcicptr->mmas = ~(mem_size - 1); + tx3927_pcicptr->ilbmma = mem_base; + tx3927_pcicptr->ipbmma = mem_pciaddr; + /* PCI->LB mappings */ + tx3927_pcicptr->iobas = 0xffffffff; + tx3927_pcicptr->ioba = 0; + tx3927_pcicptr->tlbioma = 0; + tx3927_pcicptr->mbas = ~(sdram_size - 1); + tx3927_pcicptr->mba = 0; + tx3927_pcicptr->tlbmma = 0; + /* Enable Direct mapping Address Space Decoder */ + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; + + /* Clear All Local Bus Status */ + tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; + /* Enable All Local Bus Interrupts */ + tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; + /* Clear All PCI Status Error */ + tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; + /* Enable All PCI Status Error Interrupts */ + tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; + + /* PCIC Int => IRC IRQ10 */ + tx3927_pcicptr->il = TX3927_IR_PCI; + /* Target Control (per errata) */ + tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; + + /* Enable Bus Arbiter */ + if (!extarb) + tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; + + tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_IO | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + local_irq_restore(flags); +} diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 54730ee..c6b49bc 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -1,206 +1,408 @@ /* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com + * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc. * - * Copyright (C) 2000-2001 Toshiba Corporation - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c - * - * Define the pci_ops for the Toshiba rbtx4927 - * - * Much of the code is derived from the original DDB5074 port by - * Geert Uytterhoeven - * - * Copyright 2004 MontaVista Software Inc. - * Author: Manish Lachwani (mlachwani@mvista.com) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Based on linux/arch/mips/pci/ops-tx4938.c, + * linux/arch/mips/pci/fixup-rbtx4938.c, + * linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * 2003-2005 (c) MontaVista Software, Inc. + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. */ -#include -#include #include -#include -#include - -/* initialize in setup */ -struct resource pci_io_resource = { - .name = "TX4927 PCI IO SPACE", - .start = 0x1000, - .end = (0x1000 + (TX4927_PCIIO_SIZE)) - 1, - .flags = IORESOURCE_IO -}; +#include -/* initialize in setup */ -struct resource pci_mem_resource = { - .name = "TX4927 PCI MEM SPACE", - .start = TX4927_PCIMEM, - .end = TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; +static struct { + struct pci_controller *channel; + struct tx4927_pcic_reg __iomem *pcicptr; +} pcicptrs[2]; /* TX4938 has 2 pcic */ + +static void __init set_tx4927_pcicptr(struct pci_controller *channel, + struct tx4927_pcic_reg __iomem *pcicptr) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (pcicptrs[i].channel == channel) { + pcicptrs[i].pcicptr = pcicptr; + return; + } + } + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (!pcicptrs[i].channel) { + pcicptrs[i].channel = channel; + pcicptrs[i].pcicptr = pcicptr; + return; + } + } + BUG(); +} -static int mkaddr(int bus, int dev_fn, int where, int *flagsp) +struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( + struct pci_controller *channel) { - if (bus > 0) { - /* Type 1 configuration */ - tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; - } else { - if (dev_fn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) - return -1; + int i; - /* Type 0 configuration */ - tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc); + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (pcicptrs[i].channel == channel) + return pcicptrs[i].pcicptr; } + return NULL; +} + +static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where, + struct tx4927_pcic_reg __iomem *pcicptr) +{ + if (bus->parent == NULL && + devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) + return -1; + __raw_writel(((bus->number & 0xff) << 0x10) + | ((devfn & 0xff) << 0x08) | (where & 0xfc) + | (bus->parent ? 1 : 0), + &pcicptr->g2pcfgadrs); /* clear M_ABORT and Disable M_ABORT Int. */ - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr->pcistatus & 0x0000ffff) | - (PCI_STATUS_REC_MASTER_ABORT << 16); - tx4927_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; + __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) + | (PCI_STATUS_REC_MASTER_ABORT << 16), + &pcicptr->pcistatus); return 0; } -static int check_abort(int flags) +static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr) { int code = PCIBIOS_SUCCESSFUL; - if (tx4927_pcicptr-> - pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr-> - pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT - << 16); - tx4927_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; + + /* wait write cycle completion before checking error status */ + while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) + ; + if (__raw_readl(&pcicptr->pcistatus) + & (PCI_STATUS_REC_MASTER_ABORT << 16)) { + __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) + | (PCI_STATUS_REC_MASTER_ABORT << 16), + &pcicptr->pcistatus); code = PCIBIOS_DEVICE_NOT_FOUND; } return code; } -static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 * val) +static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 3; +#endif + return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 2; +#endif + return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr) +{ + return __raw_readl(&pcicptr->g2pcfgdata); +} +static void icd_writeb(u8 val, int offset, + struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 3; +#endif + __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static void icd_writew(u16 val, int offset, + struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 2; +#endif + __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr) { - int flags, retval, dev, busno, func; + __raw_writel(val, &pcicptr->g2pcfgdata); +} - busno = bus->number; - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); +static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus) +{ + struct pci_controller *channel = bus->sysdata; + return get_tx4927_pcicptr(channel); +} - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busno = bus->number; - } else { - busno = 0; - } +static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); - if (mkaddr(busno, devfn, where, &flags)) + if (mkaddr(bus, devfn, where, pcicptr)) { + *val = 0xffffffff; return -1; - + } switch (size) { case 1: - *val = *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)); -#else - ((where & 0x3) ^ 0x3)); -#endif + *val = icd_readb(where & 3, pcicptr); break; case 2: - *val = *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)); -#else - ((where & 0x3) ^ 0x2)); -#endif - break; - case 4: - *val = tx4927_pcicptr->g2pcfgdata; + *val = icd_readw(where & 3, pcicptr); break; + default: + *val = icd_readl(pcicptr); } + return check_abort(pcicptr); +} - retval = check_abort(flags); - if (retval == PCIBIOS_DEVICE_NOT_FOUND) - *val = 0xffffffff; +static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); - return retval; + if (mkaddr(bus, devfn, where, pcicptr)) + return -1; + switch (size) { + case 1: + icd_writeb(val, where & 3, pcicptr); + break; + case 2: + icd_writew(val, where & 3, pcicptr); + break; + default: + icd_writel(val, pcicptr); + } + return check_abort(pcicptr); } -static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) +static struct pci_ops tx4927_pci_ops = { + .read = tx4927_pci_config_read, + .write = tx4927_pci_config_write, +}; + +static struct { + u8 trdyto; + u8 retryto; + u16 gbwc; +} tx4927_pci_opts __devinitdata = { + .trdyto = 0, + .retryto = 0, + .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */ +}; + +void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, + struct pci_controller *channel, int extarb) { - int flags, dev, busno, func; - busno = bus->number; - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); + int i; + unsigned long flags; - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busno = bus->number; - } else { - busno = 0; - } + set_tx4927_pcicptr(channel, pcicptr); - if (mkaddr(busno, devfn, where, &flags)) - return -1; + if (!channel->pci_ops) + printk(KERN_INFO + "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + __raw_readl(&pcicptr->pciid) >> 16, + __raw_readl(&pcicptr->pciid) & 0xffff, + __raw_readl(&pcicptr->pciccrev) & 0xff, + extarb ? "External" : "Internal"); + channel->pci_ops = &tx4927_pci_ops; - switch (size) { - case 1: - *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)) = val; + local_irq_save(flags); + + /* Disable All Initiator Space */ + __raw_writel(__raw_readl(&pcicptr->pciccfg) + & ~(TX4927_PCIC_PCICCFG_G2PMEN(0) + | TX4927_PCIC_PCICCFG_G2PMEN(1) + | TX4927_PCIC_PCICCFG_G2PMEN(2) + | TX4927_PCIC_PCICCFG_G2PIOEN), + &pcicptr->pciccfg); + + /* GB->PCI mappings */ + __raw_writel((channel->io_resource->end - channel->io_resource->start) + >> 4, + &pcicptr->g2piomask); + ____raw_writeq((channel->io_resource->start + + channel->io_map_base - IO_BASE) | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PIOGBASE_ECHG #else - ((where & 0x3) ^ 0x3)) = val; + TX4927_PCIC_G2PIOGBASE_BSDIS #endif - break; - - case 2: - *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)) = val; + , &pcicptr->g2piogbase); + ____raw_writeq(channel->io_resource->start - channel->io_offset, + &pcicptr->g2piopbase); + for (i = 0; i < 3; i++) { + __raw_writel(0, &pcicptr->g2pmmask[i]); + ____raw_writeq(0, &pcicptr->g2pmgbase[i]); + ____raw_writeq(0, &pcicptr->g2pmpbase[i]); + } + if (channel->mem_resource->end) { + __raw_writel((channel->mem_resource->end + - channel->mem_resource->start) >> 4, + &pcicptr->g2pmmask[0]); + ____raw_writeq(channel->mem_resource->start | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PMnGBASE_ECHG #else - ((where & 0x3) ^ 0x2)) = val; + TX4927_PCIC_G2PMnGBASE_BSDIS #endif - break; - case 4: - tx4927_pcicptr->g2pcfgdata = val; - break; + , &pcicptr->g2pmgbase[0]); + ____raw_writeq(channel->mem_resource->start - + channel->mem_offset, + &pcicptr->g2pmpbase[0]); + } + /* PCI->GB mappings (I/O 256B) */ + __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ + ____raw_writeq(0, &pcicptr->p2giogbase); + /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ + __raw_writel(0, &pcicptr->p2gm0plbase); + __raw_writel(0, &pcicptr->p2gm0pubase); + ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4927_PCIC_P2GMnGBASE_TECHG +#else + TX4927_PCIC_P2GMnGBASE_TBSDIS +#endif + , &pcicptr->p2gmgbase[0]); + /* PCI->GB mappings (MEM 16MB) */ + __raw_writel(0xffffffff, &pcicptr->p2gm1plbase); + __raw_writel(0xffffffff, &pcicptr->p2gm1pubase); + ____raw_writeq(0, &pcicptr->p2gmgbase[1]); + /* PCI->GB mappings (MEM 1MB) */ + __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */ + ____raw_writeq(0, &pcicptr->p2gmgbase[2]); + + /* Clear all (including IRBER) except for GBWC */ + __raw_writel((tx4927_pci_opts.gbwc << 16) + & TX4927_PCIC_PCICCFG_GBWC_MASK, + &pcicptr->pciccfg); + /* Enable Initiator Memory Space */ + if (channel->mem_resource->end) + __raw_writel(__raw_readl(&pcicptr->pciccfg) + | TX4927_PCIC_PCICCFG_G2PMEN(0), + &pcicptr->pciccfg); + /* Enable Initiator I/O Space */ + if (channel->io_resource->end) + __raw_writel(__raw_readl(&pcicptr->pciccfg) + | TX4927_PCIC_PCICCFG_G2PIOEN, + &pcicptr->pciccfg); + /* Enable Initiator Config */ + __raw_writel(__raw_readl(&pcicptr->pciccfg) + | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR, + &pcicptr->pciccfg); + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + __raw_writel(0, &pcicptr->pcicfg1); + + __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff) + | (tx4927_pci_opts.trdyto & 0xff) + | ((tx4927_pci_opts.retryto & 0xff) << 8), + &pcicptr->g2ptocnt); + + /* Clear All Local Bus Status */ + __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus); + /* Enable All Local Bus Interrupts */ + __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask); + /* Clear All Initiator Status */ + __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus); + /* Enable All Initiator Interrupts */ + __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask); + /* Clear All PCI Status Error */ + __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) + | (TX4927_PCIC_PCISTATUS_ALL << 16), + &pcicptr->pcistatus); + /* Enable All PCI Status Error Interrupts */ + __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask); + + if (!extarb) { + /* Reset Bus Arbiter */ + __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); + __raw_writel(0, &pcicptr->pbabm); + /* Enable Bus Arbiter */ + __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg); } - return check_abort(flags); + __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY + | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, + &pcicptr->pcistatus); + local_irq_restore(flags); + + printk(KERN_DEBUG + "PCI: COMMAND=%04x,PCIMASK=%04x," + "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n", + __raw_readl(&pcicptr->pcistatus) & 0xffff, + __raw_readl(&pcicptr->pcimask) & 0xffff, + __raw_readl(&pcicptr->g2ptocnt) & 0xff, + (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8, + (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff); } -struct pci_ops tx4927_pci_ops = { - tx4927_pcibios_read_config, - tx4927_pcibios_write_config -}; +static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr) +{ + __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16); + __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus); + __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus); + static struct { + __u32 flag; + const char *str; + } pcistat_tbl[] = { + { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, + { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, + { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, + { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, + { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, + { PCI_STATUS_PARITY, "MasterParityError" }, + }, g2pstat_tbl[] = { + { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" }, + { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" }, + }, pcicstat_tbl[] = { + { TX4927_PCIC_PCICSTATUS_PME, "PME" }, + { TX4927_PCIC_PCICSTATUS_TLB, "TLB" }, + { TX4927_PCIC_PCICSTATUS_NIB, "NIB" }, + { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" }, + { TX4927_PCIC_PCICSTATUS_PERR, "PERR" }, + { TX4927_PCIC_PCICSTATUS_SERR, "SERR" }, + { TX4927_PCIC_PCICSTATUS_GBE, "GBE" }, + { TX4927_PCIC_PCICSTATUS_IWB, "IWB" }, + }; + int i, cont; -/* - * h/w only supports devices 0x00 to 0x14 - */ -struct pci_controller tx4927_controller = { - .pci_ops = &tx4927_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, -}; + printk(KERN_ERR ""); + if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) { + printk(KERN_CONT "pcistat:%04x(", pcistatus); + for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++) + if (pcistatus & pcistat_tbl[i].flag) + printk(KERN_CONT "%s%s", + cont++ ? " " : "", pcistat_tbl[i].str); + printk(KERN_CONT ") "); + } + if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) { + printk(KERN_CONT "g2pstatus:%08x(", g2pstatus); + for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) + if (g2pstatus & g2pstat_tbl[i].flag) + printk(KERN_CONT "%s%s", + cont++ ? " " : "", g2pstat_tbl[i].str); + printk(KERN_CONT ") "); + } + if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) { + printk(KERN_CONT "pcicstatus:%08x(", pcicstatus); + for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) + if (pcicstatus & pcicstat_tbl[i].flag) + printk(KERN_CONT "%s%s", + cont++ ? " " : "", pcicstat_tbl[i].str); + printk(KERN_CONT ")"); + } + printk(KERN_CONT "\n"); +} + +void tx4927_report_pcic_status(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (pcicptrs[i].pcicptr) + tx4927_report_pcic_status1(pcicptrs[i].pcicptr); + } +} diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c deleted file mode 100644 index 34494b8..0000000 --- a/arch/mips/pci/ops-tx4938.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Define the pci_ops for the Toshiba rbtx4938 - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include - -#include -#include - -/* initialize in setup */ -struct resource pci_io_resource = { - .name = "pci IO space", - .start = 0, - .end = 0, - .flags = IORESOURCE_IO -}; - -/* initialize in setup */ -struct resource pci_mem_resource = { - .name = "pci memory space", - .start = 0, - .end = 0, - .flags = IORESOURCE_MEM -}; - -struct resource tx4938_pcic1_pci_io_resource = { - .name = "PCI1 IO", - .start = 0, - .end = 0, - .flags = IORESOURCE_IO -}; -struct resource tx4938_pcic1_pci_mem_resource = { - .name = "PCI1 mem", - .start = 0, - .end = 0, - .flags = IORESOURCE_MEM -}; - -static int mkaddr(int bus, int dev_fn, int where, - struct tx4938_pcic_reg *pcicptr) -{ - if (bus > 0) { - /* Type 1 configuration */ - pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; - } else { - if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0)) - return -1; - - /* Type 0 configuration */ - pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc); - } - /* clear M_ABORT and Disable M_ABORT Int. */ - pcicptr->pcistatus = - (pcicptr->pcistatus & 0x0000ffff) | - (PCI_STATUS_REC_MASTER_ABORT << 16); - pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; - - return 0; -} - -static int check_abort(struct tx4938_pcic_reg *pcicptr) -{ - int code = PCIBIOS_SUCCESSFUL; - /* wait write cycle completion before checking error status */ - while (pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB) - ; - if (pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { - pcicptr->pcistatus = - (pcicptr-> - pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT - << 16); - pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; - code = PCIBIOS_DEVICE_NOT_FOUND; - } - return code; -} - -extern struct pci_controller tx4938_pci_controller[]; -extern struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch); - -static struct tx4938_pcic_reg *pci_bus_to_pcicptr(struct pci_bus *bus) -{ - struct pci_controller *channel = bus->sysdata; - return get_tx4938_pcicptr(channel - &tx4938_pci_controller[0]); -} - -static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - int retval, dev, busno, func; - struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus); - void __iomem *cfgdata = - (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata; - - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); - - /* check if the bus is top-level */ - if (bus->parent != NULL) - busno = bus->number; - else { - busno = 0; - } - - if (mkaddr(busno, devfn, where, pcicptr)) - return -1; - - switch (size) { - case 1: -#ifdef __BIG_ENDIAN - cfgdata += (where & 3) ^ 3; -#else - cfgdata += where & 3; -#endif - *val = __raw_readb(cfgdata); - break; - case 2: -#ifdef __BIG_ENDIAN - cfgdata += (where & 2) ^ 2; -#else - cfgdata += where & 2; -#endif - *val = __raw_readw(cfgdata); - break; - case 4: - *val = __raw_readl(cfgdata); - break; - } - - retval = check_abort(pcicptr); - if (retval == PCIBIOS_DEVICE_NOT_FOUND) - *val = 0xffffffff; - - return retval; -} - -static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - int dev, busno, func; - struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus); - void __iomem *cfgdata = - (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata; - - busno = bus->number; - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); - - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busno = bus->number; - } else { - busno = 0; - } - - if (mkaddr(busno, devfn, where, pcicptr)) - return -1; - - switch (size) { - case 1: -#ifdef __BIG_ENDIAN - cfgdata += (where & 3) ^ 3; -#else - cfgdata += where & 3; -#endif - __raw_writeb(val, cfgdata); - break; - case 2: -#ifdef __BIG_ENDIAN - cfgdata += (where & 2) ^ 2; -#else - cfgdata += where & 2; -#endif - __raw_writew(val, cfgdata); - break; - case 4: - __raw_writel(val, cfgdata); - break; - } - - return check_abort(pcicptr); -} - -struct pci_ops tx4938_pci_ops = { - tx4938_pcibios_read_config, - tx4938_pcibios_write_config -}; - -struct pci_controller tx4938_pci_controller[] = { - /* h/w only supports devices 0x00 to 0x14 */ - { - .pci_ops = &tx4938_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, - }, - /* h/w only supports devices 0x00 to 0x14 */ - { - .pci_ops = &tx4938_pci_ops, - .io_resource = &tx4938_pcic1_pci_io_resource, - .mem_resource = &tx4938_pcic1_pci_mem_resource, - } -}; diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/pci-jmr3927.c deleted file mode 100644 index 7fb6bd7..0000000 --- a/arch/mips/pci/pci-jmr3927.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -#include -#include - -struct resource pci_io_resource = { - .name = "IO MEM", - .start = 0x1000, /* reserve regacy I/O space */ - .end = 0x1000 + JMR3927_PCIIO_SIZE - 1, - .flags = IORESOURCE_IO -}; - -struct resource pci_mem_resource = { - .name = "PCI MEM", - .start = JMR3927_PCIMEM, - .end = JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops jmr3927_pci_ops; - -struct pci_controller jmr3927_controller = { - .pci_ops = &jmr3927_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, - .mem_offset = JMR3927_PCIMEM -}; diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c new file mode 100644 index 0000000..27e86a0 --- /dev/null +++ b/arch/mips/pci/pci-tx4927.c @@ -0,0 +1,83 @@ +/* + * linux/arch/mips/pci/pci-tx4927.c + * + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * Copyright 2001, 2003-2005 MontaVista Software Inc. + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +int __init tx4927_report_pciclk(void) +{ + int pciclk = 0; + + printk(KERN_INFO "PCIC --%s PCICLK:", + (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ? + " PCI66" : ""); + if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) { + u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg); + switch ((unsigned long)ccfg & + TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + pciclk = txx9_cpu_clock * 2 / 5; break; + case TX4927_CCFG_PCIDIVMODE_3: + pciclk = txx9_cpu_clock / 3; break; + case TX4927_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4927_CCFG_PCIDIVMODE_6: + pciclk = txx9_cpu_clock / 6; break; + } + printk("Internal(%u.%uMHz)", + (pciclk + 50000) / 1000000, + ((pciclk + 50000) / 100000) % 10); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +int __init tx4927_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4927_ccfg_set(TX4927_CCFG_PCI66); + /* Double PCICLK (if possible) */ + if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = 0; + u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg); + pcidivmode = (unsigned long)ccfg & + TX4927_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4927_CCFG_PCIDIVMODE_5: + case TX4927_CCFG_PCIDIVMODE_2_5: + pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5; + pciclk = txx9_cpu_clock * 2 / 5; + break; + case TX4927_CCFG_PCIDIVMODE_6: + case TX4927_CCFG_PCIDIVMODE_3: + default: + pcidivmode = TX4927_CCFG_PCIDIVMODE_3; + pciclk = txx9_cpu_clock / 3; + } + tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK, + pcidivmode); + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg)); + } else + pciclk = -1; + return pciclk; +} diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c new file mode 100644 index 0000000..e537551 --- /dev/null +++ b/arch/mips/pci/pci-tx4938.c @@ -0,0 +1,134 @@ +/* + * linux/arch/mips/pci/pci-tx4938.c + * + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * Copyright 2001, 2003-2005 MontaVista Software Inc. + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +int __init tx4938_report_pciclk(void) +{ + int pciclk = 0; + + printk(KERN_INFO "PCIC --%s PCICLK:", + (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ? + " PCI66" : ""); + if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) { + u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg); + switch ((unsigned long)ccfg & + TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_4: + pciclk = txx9_cpu_clock / 4; break; + case TX4938_CCFG_PCIDIVMODE_4_5: + pciclk = txx9_cpu_clock * 2 / 9; break; + case TX4938_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4938_CCFG_PCIDIVMODE_5_5: + pciclk = txx9_cpu_clock * 2 / 11; break; + case TX4938_CCFG_PCIDIVMODE_8: + pciclk = txx9_cpu_clock / 8; break; + case TX4938_CCFG_PCIDIVMODE_9: + pciclk = txx9_cpu_clock / 9; break; + case TX4938_CCFG_PCIDIVMODE_10: + pciclk = txx9_cpu_clock / 10; break; + case TX4938_CCFG_PCIDIVMODE_11: + pciclk = txx9_cpu_clock / 11; break; + } + printk("Internal(%u.%uMHz)", + (pciclk + 50000) / 1000000, + ((pciclk + 50000) / 100000) % 10); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +void __init tx4938_report_pci1clk(void) +{ + __u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg); + unsigned int pciclk = + txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2); + + printk(KERN_INFO "PCIC1 -- %sPCICLK:%u.%uMHz\n", + (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "", + (pciclk + 50000) / 1000000, + ((pciclk + 50000) / 100000) % 10); +} + +int __init tx4938_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4938_ccfg_set(TX4938_CCFG_PCI66); + /* Double PCICLK (if possible) */ + if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = 0; + u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg); + pcidivmode = (unsigned long)ccfg & + TX4938_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4; + pciclk = txx9_cpu_clock / 4; + break; + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; + pciclk = txx9_cpu_clock * 2 / 9; + break; + case TX4938_CCFG_PCIDIVMODE_10: + case TX4938_CCFG_PCIDIVMODE_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5; + pciclk = txx9_cpu_clock / 5; + break; + case TX4938_CCFG_PCIDIVMODE_11: + case TX4938_CCFG_PCIDIVMODE_5_5: + default: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; + pciclk = txx9_cpu_clock * 2 / 11; + break; + } + tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK, + pcidivmode); + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg)); + } else + pciclk = -1; + return pciclk; +} + +int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot) +{ + if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) { + switch (slot) { + case TX4927_PCIC_IDSEL_AD_TO_SLOT(31): + if (__raw_readq(&tx4938_ccfgptr->pcfg) & + TX4938_PCFG_ETH0_SEL) + return TXX9_IRQ_BASE + TX4938_IR_ETH0; + break; + case TX4927_PCIC_IDSEL_AD_TO_SLOT(30): + if (__raw_readq(&tx4938_ccfgptr->pcfg) & + TX4938_PCFG_ETH1_SEL) + return TXX9_IRQ_BASE + TX4938_IR_ETH1; + break; + } + return 0; + } + return -1; +} diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig index 98d1034..b8cdb19 100644 --- a/arch/mips/txx9/Kconfig +++ b/arch/mips/txx9/Kconfig @@ -1,6 +1,12 @@ config TOSHIBA_FPCIB0 bool "FPCIB0 Backplane Support" - depends on TOSHIBA_RBTX4927 + depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX) + select I8259 + +config PICMG_PCI_BACKPLANE_DEFAULT + bool "Support for PICMG PCI Backplane" + depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX) + default y if !TOSHIBA_FPCIB0 if TOSHIBA_RBTX4938 @@ -26,3 +32,6 @@ config TX4938_NAND_BOOT Select this option if you need to use NAND boot. endif + +config PCI_TX4927 + bool diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile index 8cb4a7e..b80b6e0 100644 --- a/arch/mips/txx9/generic/Makefile +++ b/arch/mips/txx9/generic/Makefile @@ -2,6 +2,8 @@ # Makefile for common code for TXx9 based systems # +obj-y += setup.o +obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_TOSHIBA_RBTX4927) += mem_tx4927.o irq_tx4927.o obj-$(CONFIG_TOSHIBA_RBTX4938) += mem_tx4938.o irq_tx4938.o obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c new file mode 100644 index 0000000..8173faa --- /dev/null +++ b/arch/mips/txx9/generic/pci.c @@ -0,0 +1,377 @@ +/* + * linux/arch/mips/txx9/pci.c + * + * Based on linux/arch/mips/txx9/rbtx4927/setup.c, + * linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * Copyright 2001-2005 MontaVista Software Inc. + * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#include +#include +#endif + +static int __init +early_read_config_word(struct pci_controller *hose, + int top_bus, int bus, int devfn, int offset, u16 *value) +{ + struct pci_dev fake_dev; + struct pci_bus fake_bus; + + fake_dev.bus = &fake_bus; + fake_dev.sysdata = hose; + fake_dev.devfn = devfn; + fake_bus.number = bus; + fake_bus.sysdata = hose; + fake_bus.ops = hose->pci_ops; + + if (bus != top_bus) + /* Fake a parent bus structure. */ + fake_bus.parent = &fake_bus; + else + fake_bus.parent = NULL; + + return pci_read_config_word(&fake_dev, offset, value); +} + +int __init txx9_pci66_check(struct pci_controller *hose, int top_bus, + int current_bus) +{ + u32 pci_devfn; + unsigned short vid; + int cap66 = -1; + u16 stat; + + /* It seems SLC90E66 needs some time after PCI reset... */ + mdelay(80); + + printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n"); + + for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { + if (PCI_FUNC(pci_devfn)) + continue; + if (early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_VENDOR_ID, &vid) != + PCIBIOS_SUCCESSFUL) + continue; + if (vid == 0xffff) + continue; + + /* check 66MHz capability */ + if (cap66 < 0) + cap66 = 1; + if (cap66) { + early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_STATUS, &stat); + if (!(stat & PCI_STATUS_66MHZ)) { + printk(KERN_DEBUG + "PCI: %02x:%02x not 66MHz capable.\n", + current_bus, pci_devfn); + cap66 = 0; + break; + } + } + } + return cap66 > 0; +} + +static struct resource primary_pci_mem_res[2] = { + { .name = "PCI MEM" }, + { .name = "PCI MMIO" }, +}; +static struct resource primary_pci_io_res = { .name = "PCI IO" }; +struct pci_controller txx9_primary_pcic = { + .mem_resource = &primary_pci_mem_res[0], + .io_resource = &primary_pci_io_res, +}; + +#ifdef CONFIG_64BIT +int txx9_pci_mem_high __initdata = 1; +#else +int txx9_pci_mem_high __initdata; +#endif + +/* + * allocate pci_controller and resources. + * mem_base, io_base: physical addresss. 0 for auto assignment. + * mem_size and io_size means max size on auto assignment. + * pcic must be &txx9_primary_pcic or NULL. + */ +struct pci_controller *__init +txx9_alloc_pci_controller(struct pci_controller *pcic, + unsigned long mem_base, unsigned long mem_size, + unsigned long io_base, unsigned long io_size) +{ + struct pcic { + struct pci_controller c; + struct resource r_mem[2]; + struct resource r_io; + } *new = NULL; + int min_size = 0x10000; + + if (!pcic) { + new = kzalloc(sizeof(*new), GFP_KERNEL); + if (!new) + return NULL; + new->r_mem[0].name = "PCI mem"; + new->r_mem[1].name = "PCI mmio"; + new->r_io.name = "PCI io"; + new->c.mem_resource = new->r_mem; + new->c.io_resource = &new->r_io; + pcic = &new->c; + } else + BUG_ON(pcic != &txx9_primary_pcic); + pcic->io_resource->flags = IORESOURCE_IO; + + /* + * for auto assignment, first search a (big) region for PCI + * MEM, then search a region for PCI IO. + */ + if (mem_base) { + pcic->mem_resource[0].start = mem_base; + pcic->mem_resource[0].end = mem_base + mem_size - 1; + if (request_resource(&iomem_resource, &pcic->mem_resource[0])) + goto free_and_exit; + } else { + unsigned long min = 0, max = 0x20000000; /* low 512MB */ + if (!mem_size) { + /* default size for auto assignment */ + if (txx9_pci_mem_high) + mem_size = 0x20000000; /* mem:512M(max) */ + else + mem_size = 0x08000000; /* mem:128M(max) */ + } + if (txx9_pci_mem_high) { + min = 0x20000000; + max = 0xe0000000; + } + /* search free region for PCI MEM */ + for (; mem_size >= min_size; mem_size /= 2) { + if (allocate_resource(&iomem_resource, + &pcic->mem_resource[0], + mem_size, min, max, + mem_size, NULL, NULL) == 0) + break; + } + if (mem_size < min_size) + goto free_and_exit; + } + + pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY; + if (io_base) { + pcic->mem_resource[1].start = io_base; + pcic->mem_resource[1].end = io_base + io_size - 1; + if (request_resource(&iomem_resource, &pcic->mem_resource[1])) + goto release_and_exit; + } else { + if (!io_size) + /* default size for auto assignment */ + io_size = 0x01000000; /* io:16M(max) */ + /* search free region for PCI IO in low 512MB */ + for (; io_size >= min_size; io_size /= 2) { + if (allocate_resource(&iomem_resource, + &pcic->mem_resource[1], + io_size, 0, 0x20000000, + io_size, NULL, NULL) == 0) + break; + } + if (io_size < min_size) + goto release_and_exit; + io_base = pcic->mem_resource[1].start; + } + + pcic->mem_resource[0].flags = IORESOURCE_MEM; + if (pcic == &txx9_primary_pcic && + mips_io_port_base == (unsigned long)-1) { + /* map ioport 0 to PCI I/O space address 0 */ + set_io_port_base(IO_BASE + pcic->mem_resource[1].start); + pcic->io_resource->start = 0; + pcic->io_offset = 0; /* busaddr == ioaddr */ + pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start; + } else { + /* physaddr to ioaddr */ + pcic->io_resource->start = + io_base - (mips_io_port_base - IO_BASE); + pcic->io_offset = io_base - (mips_io_port_base - IO_BASE); + pcic->io_map_base = mips_io_port_base; + } + pcic->io_resource->end = pcic->io_resource->start + io_size - 1; + + pcic->mem_offset = 0; /* busaddr == physaddr */ + + printk(KERN_INFO "PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n", + (unsigned long long)pcic->mem_resource[1].start, + (unsigned long long)pcic->mem_resource[1].end, + (unsigned long long)pcic->mem_resource[0].start, + (unsigned long long)pcic->mem_resource[0].end); + + /* register_pci_controller() will request MEM resource */ + release_resource(&pcic->mem_resource[0]); + return pcic; + release_and_exit: + release_resource(&pcic->mem_resource[0]); + free_and_exit: + kfree(new); + printk(KERN_ERR "PCI: Failed to allocate resources.\n"); + return NULL; +} + +static int __init +txx9_arch_pci_init(void) +{ + PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */ + return 0; +} +arch_initcall(txx9_arch_pci_init); + +/* IRQ/IDSEL mapping */ +int txx9_pci_option = +#ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT + TXX9_PCI_OPT_PICMG | +#endif + TXX9_PCI_OPT_CLK_AUTO; + +enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT; + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static irqreturn_t i8259_interrupt(int irq, void *dev_id) +{ + int isairq; + + isairq = i8259_irq(); + if (unlikely(isairq <= I8259A_IRQ_BASE)) + return IRQ_NONE; + generic_handle_irq(isairq); + return IRQ_HANDLED; +} + +static int __init +txx9_i8259_irq_setup(int irq) +{ + int err; + + init_i8259_irqs(); + err = request_irq(irq, &i8259_interrupt, IRQF_DISABLED|IRQF_SHARED, + "cascade(i8259)", (void *)(long)irq); + if (!err) + printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq); + return err; +} + +static void __init quirk_slc90e66_bridge(struct pci_dev *dev) +{ + int irq; /* PCI/ISA Bridge interrupt */ + u8 reg_64; + u32 reg_b0; + u8 reg_e1; + irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */ + if (!irq) + return; + txx9_i8259_irq_setup(irq); + pci_read_config_byte(dev, 0x64, ®_64); + pci_read_config_dword(dev, 0xb0, ®_b0); + pci_read_config_byte(dev, 0xe1, ®_e1); + /* serial irq control */ + reg_64 = 0xd0; + /* serial irq pin */ + reg_b0 |= 0x00010000; + /* ide irq on isa14 */ + reg_e1 &= 0xf0; + reg_e1 |= 0x0d; + pci_write_config_byte(dev, 0x64, reg_64); + pci_write_config_dword(dev, 0xb0, reg_b0); + pci_write_config_byte(dev, 0xe1, reg_e1); + + smsc_fdc37m81x_init(0x3f0); + smsc_fdc37m81x_config_beg(); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, + SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, + 1); + smsc_fdc37m81x_config_end(); +} + +static void quirk_slc90e66_ide(struct pci_dev *dev) +{ + unsigned char dat; + int regs[2] = {0x41, 0x43}; + int i; + + /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14); + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat); + printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat); + /* enable SMSC SLC90E66 IDE */ + for (i = 0; i < ARRAY_SIZE(regs); i++) { + pci_read_config_byte(dev, regs[i], &dat); + pci_write_config_byte(dev, regs[i], dat | 0x80); + pci_read_config_byte(dev, regs[i], &dat); + printk(KERN_CONT " IDETIM%d %02x", i, dat); + } + pci_read_config_byte(dev, 0x5c, &dat); + /* + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + * + * This line of code is intended to provide the user with a work + * around solution to the anomalies cited in SMSC's anomaly sheet + * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". + * + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + */ + dat |= 0x01; + pci_write_config_byte(dev, regs[i], dat); + pci_read_config_byte(dev, 0x5c, &dat); + printk(KERN_CONT " REG5C %02x", dat); + printk(KERN_CONT "\n"); +} +#endif /* CONFIG_TOSHIBA_FPCIB0 */ + +static void final_fixup(struct pci_dev *dev) +{ + unsigned char bist; + + /* Do build-in self test */ + if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL && + (bist & PCI_BIST_CAPABLE)) { + unsigned long timeout; + pci_set_power_state(dev, PCI_D0); + printk(KERN_INFO "PCI: %s BIST...", pci_name(dev)); + pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START); + timeout = jiffies + HZ * 2; /* timeout after 2 sec */ + do { + pci_read_config_byte(dev, PCI_BIST, &bist); + if (time_after(jiffies, timeout)) + break; + } while (bist & PCI_BIST_START); + if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START)) + printk(KERN_CONT "failed. (0x%x)\n", bist); + else + printk(KERN_CONT "OK.\n"); + } +} + +#ifdef CONFIG_TOSHIBA_FPCIB0 +#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0, + quirk_slc90e66_bridge); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, + quirk_slc90e66_ide); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, + quirk_slc90e66_ide); +#endif +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup); +DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup); diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c new file mode 100644 index 0000000..46a6311 --- /dev/null +++ b/arch/mips/txx9/generic/setup.c @@ -0,0 +1,51 @@ +/* + * linux/arch/mips/txx9/generic/setup.c + * + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * 2003-2005 (c) MontaVista Software, Inc. + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include + +/* EBUSC settings of TX4927, etc. */ +struct resource txx9_ce_res[8]; +static char txx9_ce_res_name[8][4]; /* "CEn" */ + +/* pcode, internal register */ +char txx9_pcode_str[8]; +static struct resource txx9_reg_res = { + .name = txx9_pcode_str, + .flags = IORESOURCE_MEM, +}; +void __init +txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) { + sprintf(txx9_ce_res_name[i], "CE%d", i); + txx9_ce_res[i].flags = IORESOURCE_MEM; + txx9_ce_res[i].name = txx9_ce_res_name[i]; + } + + sprintf(txx9_pcode_str, "TX%x", pcode); + if (base) { + txx9_reg_res.start = base & 0xfffffffffULL; + txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1); + request_resource(&iomem_resource, &txx9_reg_res); + } +} + +/* clocks */ +unsigned int txx9_master_clock; +unsigned int txx9_cpu_clock; +unsigned int txx9_gbus_clock; diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c index 85e1daf..b97d22e 100644 --- a/arch/mips/txx9/jmr3927/irq.c +++ b/arch/mips/txx9/jmr3927/irq.c @@ -109,6 +109,7 @@ static struct irqaction ioc_action = { .name = "IOC", }; +#ifdef CONFIG_PCI static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) { printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); @@ -122,6 +123,7 @@ static struct irqaction pcierr_action = { .mask = CPU_MASK_NONE, .name = "PCI error", }; +#endif static void __init jmr3927_irq_init(void); diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 41e0f3b..baa8c8d 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -44,6 +43,7 @@ #include #include #include +#include #include #include @@ -96,8 +96,6 @@ void __init plat_time_init(void) extern char * __init prom_getcmdline(void); static void jmr3927_board_init(void); -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; void __init plat_mem_setup(void) { @@ -112,8 +110,8 @@ void __init plat_mem_setup(void) /* * IO/MEM resources. */ - ioport_resource.start = pci_io_resource.start; - ioport_resource.end = pci_io_resource.end; + ioport_resource.start = 0; + ioport_resource.end = 0xffffffff; iomem_resource.start = 0; iomem_resource.end = 0xffffffff; @@ -191,9 +189,33 @@ void __init plat_mem_setup(void) static void tx3927_setup(void); +static void __init jmr3927_pci_setup(void) +{ +#ifdef CONFIG_PCI + int extarb = !(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB); + struct pci_controller *c; + + c = txx9_alloc_pci_controller(&txx9_primary_pcic, + JMR3927_PCIMEM, JMR3927_PCIMEM_SIZE, + JMR3927_PCIIO, JMR3927_PCIIO_SIZE); + register_pci_controller(c); + if (!extarb) { + /* Reset PCI Bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, + JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + } + tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb); +#endif /* CONFIG_PCI */ +} + static void __init jmr3927_board_init(void) { tx3927_setup(); + jmr3927_pci_setup(); /* SIO0 DTR on */ jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); @@ -210,14 +232,6 @@ static void __init jmr3927_board_init(void) static void __init tx3927_setup(void) { int i; -#ifdef CONFIG_PCI - unsigned long mips_pci_io_base = JMR3927_PCIIO; - unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; - unsigned long mips_pci_mem_base = JMR3927_PCIMEM; - unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; - /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ - unsigned long mips_pci_io_pciaddr = 0; -#endif /* SDRAMC are configured by PROM */ @@ -272,74 +286,6 @@ static void __init tx3927_setup(void) tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; #endif -#ifdef CONFIG_PCI - /* PCIC */ - printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", - tx3927_pcicptr->did, tx3927_pcicptr->vid, - tx3927_pcicptr->rid); - if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { - printk("External\n"); - /* XXX */ - } else { - printk("Internal\n"); - - /* Reset PCI Bus */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, - JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - - - /* Disable External PCI Config. Access */ - tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; -#ifdef __BIG_ENDIAN - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | - TX3927_PCIC_LBC_TIBSE | - TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; -#endif - /* LB->PCI mappings */ - tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); - tx3927_pcicptr->ilbioma = mips_pci_io_base; - tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; - tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->ilbmma = mips_pci_mem_base; - tx3927_pcicptr->ipbmma = mips_pci_mem_base; - /* PCI->LB mappings */ - tx3927_pcicptr->iobas = 0xffffffff; - tx3927_pcicptr->ioba = 0; - tx3927_pcicptr->tlbioma = 0; - tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->mba = 0; - tx3927_pcicptr->tlbmma = 0; - /* Enable Direct mapping Address Space Decoder */ - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; - - /* Clear All Local Bus Status */ - tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; - /* Enable All Local Bus Interrupts */ - tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; - /* Clear All PCI Status Error */ - tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; - /* Enable All PCI Status Error Interrupts */ - tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; - - /* PCIC Int => IRC IRQ10 */ - tx3927_pcicptr->il = TX3927_IR_PCI; - /* Target Control (per errata) */ - tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; - - /* Enable Bus Arbiter */ - tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; - - tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - } -#endif /* CONFIG_PCI */ - /* PIO */ /* PIO[15:12] connected to LEDs */ __raw_writel(0x0000f000, &tx3927_pioptr->dir); diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c index 936e50e..bef1447 100644 --- a/arch/mips/txx9/rbtx4927/irq.c +++ b/arch/mips/txx9/rbtx4927/irq.c @@ -111,9 +111,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #include #include #include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif #include #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 @@ -125,8 +122,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) -extern int tx4927_using_backplane; - static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); @@ -146,17 +141,8 @@ int toshiba_rbtx4927_irq_nested(int sw_irq) u8 level3; level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; - if (level3) { + if (level3) sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && - tx4927_using_backplane) { - int irq = i8259_irq(); - if (irq >= 0) - sw_irq = irq; - } -#endif - } return (sw_irq); } @@ -205,10 +191,6 @@ void __init arch_init_irq(void) tx4927_irq_init(); toshiba_rbtx4927_irq_ioc_init(); -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) - init_i8259_irqs(); -#endif /* Onboard 10M Ether: High Active */ set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); } diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index df1b6e9..86b870a 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -47,10 +47,10 @@ #include #include #include -#include #include #include #include +#include #include #include @@ -58,10 +58,10 @@ #include #include #include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif +#include +#include #include +#include /* for TX4937 */ #ifdef CONFIG_SERIAL_TXX9 #include #endif @@ -70,356 +70,116 @@ extern void toshiba_rbtx4927_restart(char *command); extern void toshiba_rbtx4927_halt(void); extern void toshiba_rbtx4927_power_off(void); - -int tx4927_using_backplane = 0; - extern void toshiba_rbtx4927_irq_setup(void); char *prom_getcmdline(void); -#ifdef CONFIG_PCI -#undef TX4927_SUPPORT_COMMAND_IO -#undef TX4927_SUPPORT_PCI_66 -int tx4927_cpu_clock = 100000000; /* 100MHz */ -unsigned long mips_pci_io_base; -unsigned long mips_pci_io_size; -unsigned long mips_pci_mem_base; -unsigned long mips_pci_mem_size; -/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ -unsigned long mips_pci_io_pciaddr = 0; -unsigned long mips_memory_upper; static int tx4927_ccfg_toeon = 1; -static int tx4927_pcic_trdyto = 0; /* default: disabled */ -unsigned long tx4927_ce_base[8]; -int tx4927_pci66 = 0; /* 0:auto */ -#endif char *toshiba_name = ""; #ifdef CONFIG_PCI -extern struct pci_controller tx4927_controller; - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) +static void __init tx4927_pci_setup(void) { - static struct pci_dev dev; - static struct pci_bus bus; - - dev.sysdata = (void *)hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ + int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB); + struct pci_controller *c = &txx9_primary_pcic; + + register_pci_controller(c); + + if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) + txx9_pci_option = + (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | + TXX9_PCI_OPT_CLK_66; /* already configured */ + + /* Reset PCI Bus */ + writeb(1, rbtx4927_pcireset_addr); + /* Reset PCIC */ + txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_66) + tx4927_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); + writeb(0, rbtx4927_pcireset_addr); + iob(); + + tx4927_report_pciclk(); + tx4927_pcic_setup(tx4927_pcicptr, c, extarb); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_AUTO && + txx9_pci66_check(c, 0, 0)) { + /* Reset PCI Bus */