From rdsandiford@googlemail.com Sun Jun 1 15:16:16 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Jun 2008 15:16:21 +0100 (BST) Received: from p549F48FC.dip.t-dialin.net ([84.159.72.252]:46557 "EHLO p549F48FC.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20024082AbYFAOQQ (ORCPT ); Sun, 1 Jun 2008 15:16:16 +0100 Received: from nf-out-0910.google.com ([64.233.182.190]:17982 "EHLO nf-out-0910.google.com") by lappi.linux-mips.net with ESMTP id S525092AbYFANsi (ORCPT ); Sun, 1 Jun 2008 15:48:38 +0200 Received: by nf-out-0910.google.com with SMTP id h3so255793nfh.14 for ; Sun, 01 Jun 2008 06:48:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:mail-followup-to:cc:subject:references:date:in-reply-to:message-id:user-agent:mime-version:content-type; bh=wQ9vm4lyOa0FwB3vbUSXt7M3H3FKPmMrM8RaH8p6ls0=; b=ntrGWNHjrClrq+zPWo11fO9xFxZbIg/zmLRDRnJtbQTXz1XsXI4q2huhVG5tqnEXXQMaYNPCqCPLiYNu64EjbSwmaFtOkeF9e02cuzg3RaXAtpDMSQeEpejZuo3qOdQgYtbOg9pkrfb63+Sn9dUe6AMZDqnfK3TqoGIR6tg17NY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:mail-followup-to:cc:subject:references:date:in-reply-to:message-id:user-agent:mime-version:content-type; b=j/2msfeVfv/5kYMKufrf7PAGhu5nA9e5BnBxrDXZoONr557oyAonbv4E6ACCVIRUd82Eig3CvwqKTnNR2kMMT6IpSNzpeQEPU70LWKVxVxWk3PomKN2QVrhKVzSJJRiJb8r4Dt5qE8SdoT9ugn6pH+0abgUJaunUz8gULi3sKAQ= Received: by 10.210.58.17 with SMTP id g17mr3408365eba.190.1212328095771; Sun, 01 Jun 2008 06:48:15 -0700 (PDT) Received: from localhost ( [79.67.7.203]) by mx.google.com with ESMTPS id g9sm3883073gvc.0.2008.06.01.06.48.10 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 01 Jun 2008 06:48:13 -0700 (PDT) From: Richard Sandiford To: "Maciej W. Rozycki" Mail-Followup-To: "Maciej W. Rozycki" ,Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Cc: Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org Subject: Re: Changing the treatment of the MIPS HI and LO registers References: <87tzgj4nh6.fsf@firetop.home> <87abib4d9t.fsf@firetop.home> <87r6bm1ebd.fsf@firetop.home> <878wxtvarg.fsf@firetop.home> Date: Sun, 01 Jun 2008 14:48:08 +0100 In-Reply-To: <878wxtvarg.fsf@firetop.home> (Richard Sandiford's message of "Thu\, 29 May 2008 08\:18\:27 +0100") Message-ID: <8763stz2p3.fsf@firetop.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19390 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rdsandiford@googlemail.com Precedence: bulk X-list: linux-mips This thread seems to have stagnated (if a thread can stagnate). Maciej said: > OK, it is good to have a way to make use of some TImode functionality > 64-bit hardware provides, but it still does not provide a clean solution > to the compatibility problem seen here. While a construct like: > > #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4) > [new wonderful TImode stuff] > #else > [old compatibility asm crap] > #endif > > will certainly work, it is as ugly as you can get. I am not sure I would > be happy to see it in Linux, though obviously Ralf and the others may > disagree. but TBH, I don't see why it's so ugly. I imagine the definitions of int128_t and uint128_t (or whatever you decide to call them) would use the condition above. Then there'd be a macro to say whether the TImode stuff is available. I.e.: #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4) typedef ... int128_t ...; typedef ... uint128_t ...; #define WE_HAVE_TIMODE 1 /* replace with a good name */ #endif So there'd only be one copy of the __GNUC__ check. The uses would simply be: #if WE_HAVE_TIMODE ... #else ... #endif That seems no worse than the kind of preprocessor condition you find all over the Linux source. Of course, the other alternative is simply to put the mfhi in the asm itself. While using "h" should in theory produce slightly better code, the difference is probably marginal (or at least accidental) in practice. GCC doesn't know that the asm performs a multiplication or division, so it isn't necessarily going to defer the mfhi for as long as you might like. (Better scheduling is of course another reason why the TImode version ought to be better. A third reason is that it would allow the compiler to constant-fold the result for constant delays periods; as the comment says, this currently only happens for the initialisation of usecs, not the multiplication itself.) I've attached an updated patch below. Differences from the last time are: - I've fixed the movti patterns for MIPS16. - I've added -mfix-r4000 support to the new TImode patterns. Also, now that the highpart patterns store directly into a GPR, it's easy to extend them to -mfix-r4000 too. - I've added a load of -mfix-r4000 tests. - I've added the promised TImode testcases. They cover addition, subtraction and logic as well as multiplication: - timode-1.c makes sure that everything is open-coded - timode-2.c makes sure that execution succeeds - int-moves-[12].c shadow the movtf tests I added earlier today Tested on mips64el-linux-gnu and mipsisa64-elfoabi. I'll reinstate the 48 hour warning, mostly as a way of seeing whether the thread is still alive. I don't think my last message made it through to linux-mips@. If this one does, and you're wanting some context, the discussion started here: http://gcc.gnu.org/ml/gcc-patches/2008-05/msg01750.html Basically, I'm trying to fix a wrong-code problem that would become especially dangerous with GCC's new register allocator. The only acceptable way I can see of doing it involves removing support for the asm "h" constraint. ("hi" would still be supported in clobber lists.) Richard gcc/ * doc/md.texi: Synchronize with later constraints.md change. * longlong.h (umul_ppmm): Replace the MIPS asm implementation with a C implementation. * config/mips/mips.c (mips_legitimize_move): Remove MFHI and MFLO handling. (mips_subword): Assume TImode for CONST_INTs if TARGET_64BIT. (mips_split_doubleword_move): Use special MTHI and MFHI instructions when moving to and from MD_REGNUM. (mips_output_move): Don't handle moves from GPRs to HI_REGNUM. Handle moves from LO_REGNUM to GPRs using MFLO, MACC or DMACC. Handle byte and halfword moves. (mips_hard_regno_mode_ok_p): Handle MD_REGS and DSP_ACC_REGS separately. * config/mips/constraints.md (h): Turn into NO_REGS. (l, x): Update documentation. * config/mips/mips.md (UNSPEC_MFHILO): Delete. (UNSPEC_MFHI, UNSPEC_MTHI, UNSPEC_SET_HILO): New. (UNSPEC_TLS_LDM, UNSPEC_TLS_GET_TP): Renumber. (HILO): New mode iterator. (MOVE128): Add TI. (any_div): New code iterator. (u): Extend code attribute to div and udiv. (*add3_mips16, *movdi_64bit_mips16, *movsi_mips16): Use d_operand in the splitters. Remove redundant CONST_INT checks. (mulsi3_mult3, mul3_internal, mul3_r4000, *mul_acc_si) (*macc, *msac, *msac_using_macc, *macc2, *msac2, *mul_sub_si) (*muls): Remove "=h" clobbers. Adjust peephole2s and define_splits accordingly, using normal moves instead of unspecs to move LO into a GPR. Use d_operand and lo_operand instead of *_REG_P checks. (mulsidi3): Handle expansion in C code. (mulsidi3_32bit_internal): Rename to... (mulsidi3_32bit): ...this. (mulsidi3_32bit_r4000): Fix insn separator. (*mulsidi3_64bit): Rename to... (mulsidi3_64bit): ...this. Combine DImode "=h" and "=l" clobbers into a TImode "=x" clobber. In the split, use an UNSPEC_SET_HILO to set LO and HI to the multiplication result. Use a normal move for MFLO and an unspec for MFHI. (*mulsidi3_64bit_parts): Replace with... (mulsidi3_64bit_hilo): ...this new instruction. (mulsi3_highpart): Extend to TARGET_FIX_R4000. (mulsi3_highpart_internal): Turn into a define_insn_and_split and extend it to TARGET_FIX_R4000. Store the destination in a GPR instead of HI. Split the instruction into a separate multiplication and MFHI if !TARGET_FIX_R4000. (muldi3_highpart): Likewise. (mulsi3_highpart_mulhi_internal): Remove the first alternative and the "=h" clobber. (*mulsi3_highpart_neg_mulhi_internal): Likewise. (mulditi3): New expander. (mulditi3_internal, mulditi3_r4000): New patterns. (madsi): Remove "=h" clobber. (divmod4, udivmod4): Turn into define_insn_and_splits. Force the modulus result to be a GPR and split the instruction into a division followed by an MFHI after reload. (divmod4_hilo_): New instruction. (*lea_high64): Use d_operand in the define_peephole2. Likewise the MIPS16 HIGH define_split. (*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16): Change type of acc<->gpr moves to "multi". (*movdi_64bit): Replace the single "x" alternative with alternatives for moving into and out of "a". (*movhi_internal, *movqi_internal): Likewise. Use mips_output_move. (*movsi_internal): Extend the "d<-A" alternative to "d<-a". (*movdi_64bit_mips16, *movsi_mips16): Add d<-a alternatives. Use d_operand in the splitters. Remove redundant CONST_INT checks. (*movhi_mips16, *movqi_mips16): Likewise. Use mips_output_move. (movti): New expander. (*movti, *movti_mips16): New insns. (mfhilo_, *mfhilo_, *mfhilo__macc): Delete. (mfhi_): New pattern. (mthi_): Likewise. * config/mips/predicates.md (fpr_operand): Delete. (d_operand): New predicate. gcc/testsuite/ * gcc.dg/torture/mips-hilo-1.c: Delete. * gcc.target/mips/pr35232.c: Likewise. * gcc.target/mips/fix-vr4130-1.c: Use modulus to create an mfhi. * gcc.target/mips/fix-vr4130-3.c: Likewise. * gcc.target/mips/int-moves-1.c: New test. * gcc.target/mips/int-moves-2.c: Likewise. * gcc.target/mips/fix-r4000-1.c: Likewise. * gcc.target/mips/fix-r4000-2.c: Likewise. * gcc.target/mips/fix-r4000-3.c: Likewise. * gcc.target/mips/fix-r4000-4.c: Likewise. * gcc.target/mips/fix-r4000-5.c: Likewise. * gcc.target/mips/fix-r4000-6.c: Likewise. * gcc.target/mips/fix-r4000-7.c: Likewise. * gcc.target/mips/fix-r4000-8.c: Likewise. * gcc.target/mips/fix-r4000-9.c: Likewise. * gcc.target/mips/fix-r4000-10.c: Likewise. * gcc.target/mips/fix-r4000-11.c: Likewise. * gcc.target/mips/fix-r4000-12.c: Likewise. * gcc.target/mips/timode-1.c: Likewise. * gcc.target/mips/timode-2.c: Likewise. Index: gcc/doc/md.texi =================================================================== --- gcc/doc/md.texi 2008-06-01 10:23:31.000000000 +0100 +++ gcc/doc/md.texi 2008-06-01 14:08:13.000000000 +0100 @@ -2498,13 +2498,15 @@ generating MIPS16 code. A floating-point register (if available). @item h -The @code{hi} register. +Formerly the @code{hi} register. This constraint is no longer supported. @item l -The @code{lo} register. +The @code{lo} register. Use this register to store values that are +no bigger than a word. @item x -The @code{hi} and @code{lo} registers. +The concatenated @code{hi} and @code{lo} registers. Use this register +to store doubleword values. @item c A register suitable for use in an indirect jump. This will always be Index: gcc/longlong.h =================================================================== --- gcc/longlong.h 2008-06-01 10:23:31.000000000 +0100 +++ gcc/longlong.h 2008-06-01 14:06:06.000000000 +0100 @@ -623,12 +623,12 @@ #define UDIV_TIME 150 #endif /* __m88000__ */ #if defined (__mips__) && W_TYPE_SIZE == 32 -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("multu %2,%3" \ - : "=l" ((USItype) (w0)), \ - "=h" ((USItype) (w1)) \ - : "d" ((USItype) (u)), \ - "d" ((USItype) (v))) +#define umul_ppmm(w1, w0, u, v) \ + do { \ + UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \ + (w1) = (USItype) (__x >> 32); \ + (w0) = (USItype) (__x); \ + } while (0) #define UMUL_TIME 10 #define UDIV_TIME 100 Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c 2008-06-01 14:01:19.000000000 +0100 +++ gcc/config/mips/mips.c 2008-06-01 14:06:06.000000000 +0100 @@ -2659,23 +2659,6 @@ mips_legitimize_move (enum machine_mode return true; } - /* Check for individual, fully-reloaded mflo and mfhi instructions. */ - if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD - && REG_P (src) && MD_REG_P (REGNO (src)) - && REG_P (dest) && GP_REG_P (REGNO (dest))) - { - int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM; - if (GET_MODE_SIZE (mode) <= 4) - emit_insn (gen_mfhilo_si (gen_lowpart (SImode, dest), - gen_lowpart (SImode, src), - gen_rtx_REG (SImode, other_regno))); - else - emit_insn (gen_mfhilo_di (gen_lowpart (DImode, dest), - gen_lowpart (DImode, src), - gen_rtx_REG (DImode, other_regno))); - return true; - } - /* We need to deal with constants that would be legitimate immediate_operands but aren't legitimate move_operands. */ if (CONSTANT_P (src) && !move_operand (src, mode)) @@ -3472,7 +3455,7 @@ mips_subword (rtx op, bool high_p) mode = GET_MODE (op); if (mode == VOIDmode) - mode = DImode; + mode = TARGET_64BIT ? TImode : DImode; if (TARGET_BIG_ENDIAN ? !high_p : high_p) byte = UNITS_PER_WORD; @@ -3523,6 +3506,8 @@ mips_split_64bit_move_p (rtx dest, rtx s void mips_split_doubleword_move (rtx dest, rtx src) { + rtx low_dest; + if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src)) { if (!TARGET_64BIT && GET_MODE (dest) == DImode) @@ -3536,12 +3521,27 @@ mips_split_doubleword_move (rtx dest, rt else gcc_unreachable (); } + else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST) + { + low_dest = mips_subword (dest, false); + mips_emit_move (low_dest, mips_subword (src, false)); + if (TARGET_64BIT) + emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest)); + else + emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest)); + } + else if (REG_P (src) && REGNO (src) == MD_REG_FIRST) + { + mips_emit_move (mips_subword (dest, false), mips_subword (src, false)); + if (TARGET_64BIT) + emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src)); + else + emit_insn (gen_mfhisi_di (mips_subword (dest, true), src)); + } else { /* The operation can be split into two normal moves. Decide in which order to do them. */ - rtx low_dest; - low_dest = mips_subword (dest, false); if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src)) @@ -3584,8 +3584,9 @@ mips_output_move (rtx dest, rtx src) if (GP_REG_P (REGNO (dest))) return "move\t%0,%z1"; - if (MD_REG_P (REGNO (dest))) - return "mt%0\t%z1"; + /* Moves to HI are handled by special .md insns. */ + if (REGNO (dest) == LO_REGNUM) + return "mtlo\t%z1"; if (DSP_ACC_REG_P (REGNO (dest))) { @@ -3608,14 +3609,29 @@ mips_output_move (rtx dest, rtx src) } } if (dest_code == MEM) - return dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0"; + switch (GET_MODE_SIZE (mode)) + { + case 1: return "sb\t%z1,%0"; + case 2: return "sh\t%z1,%0"; + case 4: return "sw\t%z1,%0"; + case 8: return "sd\t%z1,%0"; + } } if (dest_code == REG && GP_REG_P (REGNO (dest))) { if (src_code == REG) { - /* Handled by separate patterns. */ - gcc_assert (!MD_REG_P (REGNO (src))); + /* Moves from HI are handled by special .md insns. */ + if (REGNO (src) == LO_REGNUM) + { + /* When generating VR4120 or VR4130 code, we use MACC and + DMACC instead of MFLO. This avoids both the normal + MIPS III HI/LO hazards and the errata related to + -mfix-vr4130. */ + if (ISA_HAS_MACCHI) + return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%."; + return "mflo\t%0"; + } if (DSP_ACC_REG_P (REGNO (src))) { @@ -3642,7 +3658,13 @@ mips_output_move (rtx dest, rtx src) } if (src_code == MEM) - return dbl_p ? "ld\t%0,%1" : "lw\t%0,%1"; + switch (GET_MODE_SIZE (mode)) + { + case 1: return "lbu\t%0,%1"; + case 2: return "lhu\t%0,%1"; + case 4: return "lw\t%0,%1"; + case 8: return "ld\t%0,%1"; + } if (src_code == CONST_INT) { @@ -8937,13 +8959,30 @@ mips_hard_regno_mode_ok_p (unsigned int if (ACC_REG_P (regno) && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode))) { - if (size <= UNITS_PER_WORD) - return true; + if (MD_REG_P (regno)) + { + /* After a multiplication or division, clobbering HI makes + the value of LO unpredictable, and vice versa. This means + that, for all interesting cases, HI and LO are effectively + a single register. - if (size <= UNITS_PER_WORD * 2) - return (DSP_ACC_REG_P (regno) - ? ((regno - DSP_ACC_REG_FIRST) & 1) == 0 - : regno == MD_REG_FIRST); + We model this by requiring that any value that uses HI + also uses LO. */ + if (size <= UNITS_PER_WORD * 2) + return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST); + } + else + { + /* DSP accumulators do not have the same restrictions as + HI and LO, so we can treat them as normal doubleword + registers. */ + if (size <= UNITS_PER_WORD) + return true; + + if (size <= UNITS_PER_WORD * 2 + && ((regno - DSP_ACC_REG_FIRST) & 1) == 0) + return true; + } } if (ALL_COP_REG_P (regno)) Index: gcc/config/mips/constraints.md =================================================================== --- gcc/config/mips/constraints.md 2008-06-01 10:23:31.000000000 +0100 +++ gcc/config/mips/constraints.md 2008-06-01 14:07:37.000000000 +0100 @@ -29,14 +29,16 @@ (define_register_constraint "t" "T_REG" (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" "A floating-point register (if available).") -(define_register_constraint "h" "TARGET_BIG_ENDIAN ? MD0_REG : MD1_REG" - "The @code{hi} register.") +(define_register_constraint "h" "NO_REGS" + "Formerly the @code{hi} register. This constraint is no longer supported.") (define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG" - "The @code{lo} register.") + "The @code{lo} register. Use this register to store values that are + no bigger than a word.") (define_register_constraint "x" "MD_REGS" - "The @code{hi} and @code{lo} registers.") + "The concatenated @code{hi} and @code{lo} registers. Use this register + to store doubleword values.") (define_register_constraint "b" "ALL_REGS" "@internal") Index: gcc/config/mips/mips.md =================================================================== --- gcc/config/mips/mips.md 2008-06-01 14:01:19.000000000 +0100 +++ gcc/config/mips/mips.md 2008-06-01 14:16:33.000000000 +0100 @@ -44,9 +44,11 @@ (define_constants (UNSPEC_LOAD_CALL 23) (UNSPEC_LOAD_GOT 24) (UNSPEC_GP 25) - (UNSPEC_MFHILO 26) - (UNSPEC_TLS_LDM 27) - (UNSPEC_TLS_GET_TP 28) + (UNSPEC_MFHI 26) + (UNSPEC_MTHI 27) + (UNSPEC_SET_HILO 28) + (UNSPEC_TLS_LDM 29) + (UNSPEC_TLS_GET_TP 30) (UNSPEC_MFHC1 31) (UNSPEC_MTHC1 32) (UNSPEC_CLEAR_HAZARD 33) @@ -484,6 +486,10 @@ (define_mode_iterator GPR [SI (DI "TARGE ;; modes. (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) +;; This mode iterator allows :HILO to be used as the mode of the +;; concatenated HI and LO registers. +(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")]) + ;; This mode iterator allows :P to be used for patterns that operate on ;; pointer-sized quantities. Exactly one of the two alternatives will match. (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) @@ -497,7 +503,7 @@ (define_mode_iterator MOVE64 [DI DF (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")]) ;; 128-bit modes for which we provide move patterns on 64-bit targets. -(define_mode_iterator MOVE128 [TF]) +(define_mode_iterator MOVE128 [TI TF]) ;; This mode iterator allows the QI and HI extension patterns to be ;; defined from the same template. @@ -613,6 +619,10 @@ (define_code_iterator any_extend [sign_e ;; from the same template. (define_code_iterator any_shift [ashift ashiftrt lshiftrt]) +;; This code iterator allows unsigned and signed division to be generated +;; from the same template. +(define_code_iterator any_div [div udiv]) + ;; This code iterator allows all native floating-point comparisons to be ;; generated from the same template. (define_code_iterator fcond [unordered uneq unlt unle eq lt le]) @@ -631,6 +641,7 @@ (define_code_iterator any_le [le leu]) ;; expands to an empty string when doing a signed operation and ;; "u" when doing an unsigned operation. (define_code_attr u [(sign_extend "") (zero_extend "u") + (div "") (udiv "u") (gt "") (gtu "u") (ge "") (geu "u") (lt "") (ltu "u") @@ -864,13 +875,10 @@ (define_insn "*add3_mips16" ;; simply adding a constant to a register. (define_split - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "d_operand") (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand")))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) > 0x7f && INTVAL (operands[1]) <= 0x7f + 0x7f) || (INTVAL (operands[1]) < - 0x80 @@ -893,16 +901,11 @@ (define_split }) (define_split - [(set (match_operand:SI 0 "register_operand") - (plus:SI (match_operand:SI 1 "register_operand") + [(set (match_operand:SI 0 "d_operand") + (plus:SI (match_operand:SI 1 "d_operand") (match_operand:SI 2 "const_int_operand")))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && REG_P (operands[1]) - && M16_REG_P (REGNO (operands[1])) && REGNO (operands[0]) != REGNO (operands[1]) - && GET_CODE (operands[2]) == CONST_INT && ((INTVAL (operands[2]) > 0x7 && INTVAL (operands[2]) <= 0x7 + 0x7f) || (INTVAL (operands[2]) < - 0x8 @@ -925,13 +928,10 @@ (define_split }) (define_split - [(set (match_operand:DI 0 "register_operand") + [(set (match_operand:DI 0 "d_operand") (plus:DI (match_dup 0) (match_operand:DI 1 "const_int_operand")))] "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) > 0xf && INTVAL (operands[1]) <= 0xf + 0xf) || (INTVAL (operands[1]) < - 0x10 @@ -954,16 +954,11 @@ (define_split }) (define_split - [(set (match_operand:DI 0 "register_operand") - (plus:DI (match_operand:DI 1 "register_operand") + [(set (match_operand:DI 0 "d_operand") + (plus:DI (match_operand:DI 1 "d_operand") (match_operand:DI 2 "const_int_operand")))] "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && REG_P (operands[1]) - && M16_REG_P (REGNO (operands[1])) && REGNO (operands[0]) != REGNO (operands[1]) - && GET_CODE (operands[2]) == CONST_INT && ((INTVAL (operands[2]) > 0x7 && INTVAL (operands[2]) <= 0x7 + 0xf) || (INTVAL (operands[2]) < - 0x8 @@ -1174,8 +1169,7 @@ (define_insn "mulsi3_mult3" [(set (match_operand:SI 0 "register_operand" "=d,l") (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d"))) - (clobber (match_scratch:SI 3 "=h,h")) - (clobber (match_scratch:SI 4 "=l,X"))] + (clobber (match_scratch:SI 3 "=l,X"))] "ISA_HAS_MUL3" { if (which_alternative == 1) @@ -1194,30 +1188,26 @@ (define_insn "mulsi3_mult3" ;; Operand 0: LO ;; Operand 1: GPR (1st multiplication operand) ;; Operand 2: GPR (2nd multiplication operand) -;; Operand 3: HI -;; Operand 4: GPR (destination) +;; Operand 3: GPR (destination) (define_peephole2 [(parallel - [(set (match_operand:SI 0 "register_operand") - (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand"))) - (clobber (match_operand:SI 3 "register_operand")) + [(set (match_operand:SI 0 "lo_operand") + (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand"))) (clobber (scratch:SI))]) - (set (match_operand:SI 4 "register_operand") - (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))] + (set (match_operand:SI 3 "d_operand") + (match_dup 0))] "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])" [(parallel - [(set (match_dup 4) + [(set (match_dup 3) (mult:SI (match_dup 1) (match_dup 2))) - (clobber (match_dup 3)) (clobber (match_dup 0))])]) (define_insn "mul3_internal" [(set (match_operand:GPR 0 "register_operand" "=l") (mult:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "register_operand" "d"))) - (clobber (match_scratch:GPR 3 "=h"))] + (match_operand:GPR 2 "register_operand" "d")))] "!TARGET_FIX_R4000" "mult\t%1,%2" [(set_attr "type" "imul") @@ -1227,8 +1217,7 @@ (define_insn "mul3_r4000" [(set (match_operand:GPR 0 "register_operand" "=d") (mult:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d"))) - (clobber (match_scratch:GPR 3 "=h")) - (clobber (match_scratch:GPR 4 "=l"))] + (clobber (match_scratch:GPR 3 "=l"))] "TARGET_FIX_R4000" "mult\t%1,%2\;mflo\t%0" [(set_attr "type" "imul") @@ -1242,16 +1231,13 @@ (define_insn "mul3_r4000" ;; Operand 0: LO ;; Operand 1: GPR (1st multiplication operand) ;; Operand 2: GPR (2nd multiplication operand) -;; Operand 3: HI -;; Operand 4: GPR (destination) +;; Operand 3: GPR (destination) (define_peephole2 - [(parallel - [(set (match_operand:SI 0 "register_operand") - (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand"))) - (clobber (match_operand:SI 3 "register_operand"))]) - (set (match_operand:SI 4 "register_operand") - (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))] + [(set (match_operand:SI 0 "lo_operand") + (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand"))) + (set (match_operand:SI 3 "d_operand") + (match_dup 0))] "ISA_HAS_MACC && !ISA_HAS_MUL3" [(set (match_dup 0) (const_int 0)) @@ -1260,11 +1246,10 @@ (define_peephole2 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 0))) - (set (match_dup 4) + (set (match_dup 3) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) - (match_dup 0))) - (clobber (match_dup 3))])]) + (match_dup 0)))])]) ;; Multiply-accumulate patterns @@ -1283,9 +1268,8 @@ (define_insn "*mul_acc_si" (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d") (match_operand:SI 2 "register_operand" "d,d,d")) (match_operand:SI 3 "register_operand" "0,l,*d"))) - (clobber (match_scratch:SI 4 "=h,h,h")) - (clobber (match_scratch:SI 5 "=X,3,l")) - (clobber (match_scratch:SI 6 "=X,X,&d"))] + (clobber (match_scratch:SI 4 "=X,3,l")) + (clobber (match_scratch:SI 5 "=X,X,&d"))] "(TARGET_MIPS3900 || GENERATE_MADD_MSUB) && !TARGET_MIPS16" @@ -1301,53 +1285,45 @@ (define_insn "*mul_acc_si" (set_attr "mode" "SI") (set_attr "length" "4,4,8")]) -;; Split the above insn if we failed to get LO allocated. +;; Split *mul_acc_si if both the source and destination accumulator +;; values are GPRs. (define_split - [(set (match_operand:SI 0 "register_operand") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) - (match_operand:SI 3 "register_operand"))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && GP_REG_P (true_regnum (operands[3]))" - [(parallel [(set (match_dup 6) + [(set (match_operand:SI 0 "d_operand") + (plus:SI (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand")) + (match_operand:SI 3 "d_operand"))) + (clobber (match_operand:SI 4 "lo_operand")) + (clobber (match_operand:SI 5 "d_operand"))] + "reload_completed && !TARGET_DEBUG_D_MODE" + [(parallel [(set (match_dup 5) (mult:SI (match_dup 1) (match_dup 2))) - (clobber (match_dup 4)) - (clobber (match_dup 5))]) - (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))] + (clobber (match_dup 4))]) + (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))] "") -;; Splitter to copy result of MADD to a general register +;; Split *mul_acc_si if the destination accumulator value is in a GPR +;; and the source accumulator value is in LO. (define_split - [(set (match_operand:SI 0 "register_operand") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) - (match_operand:SI 3 "register_operand"))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && true_regnum (operands[3]) == LO_REGNUM" + [(set (match_operand:SI 0 "d_operand") + (plus:SI (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand")) + (match_operand:SI 3 "lo_operand"))) + (clobber (match_dup 3)) + (clobber (scratch:SI))] + "reload_completed && !TARGET_DEBUG_D_MODE" [(parallel [(set (match_dup 3) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4)) - (clobber (match_dup 5)) - (clobber (match_dup 6))]) - (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))] - "") + (clobber (scratch:SI)) + (clobber (scratch:SI))]) + (set (match_dup 0) (match_dup 3))]) (define_insn "*macc" [(set (match_operand:SI 0 "register_operand" "=l,d") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d")) (match_operand:SI 3 "register_operand" "0,l"))) - (clobber (match_scratch:SI 4 "=h,h")) - (clobber (match_scratch:SI 5 "=X,3"))] + (clobber (match_scratch:SI 4 "=X,3"))] "ISA_HAS_MACC" { if (which_alternative == 1) @@ -1368,8 +1344,7 @@ (define_insn "*msac" (minus:SI (match_operand:SI 1 "register_operand" "0,l") (mult:SI (match_operand:SI 2 "register_operand" "d,d") (match_operand:SI 3 "register_operand" "d,d")))) - (clobber (match_scratch:SI 4 "=h,h")) - (clobber (match_scratch:SI 5 "=X,1"))] + (clobber (match_scratch:SI 4 "=X,1"))] "ISA_HAS_MSAC" { if (which_alternative == 1) @@ -1388,21 +1363,19 @@ (define_insn_and_split "*msac_using_macc (minus:SI (match_operand:SI 1 "register_operand" "0,l") (mult:SI (match_operand:SI 2 "register_operand" "d,d") (match_operand:SI 3 "register_operand" "d,d")))) - (clobber (match_scratch:SI 4 "=h,h")) - (clobber (match_scratch:SI 5 "=X,1")) - (clobber (match_scratch:SI 6 "=d,d"))] + (clobber (match_scratch:SI 4 "=X,1")) + (clobber (match_scratch:SI 5 "=d,d"))] "ISA_HAS_MACC && !ISA_HAS_MSAC" "#" "&& reload_completed" - [(set (match_dup 6) + [(set (match_dup 5) (neg:SI (match_dup 3))) (parallel [(set (match_dup 0) (plus:SI (mult:SI (match_dup 2) - (match_dup 6)) + (match_dup 5)) (match_dup 1))) - (clobber (match_dup 4)) - (clobber (match_dup 5))])] + (clobber (match_dup 4))])] "" [(set_attr "type" "imadd") (set_attr "length" "8")]) @@ -1417,8 +1390,7 @@ (define_insn "*macc2" (set (match_operand:SI 3 "register_operand" "=d") (plus:SI (mult:SI (match_dup 1) (match_dup 2)) - (match_dup 0))) - (clobber (match_scratch:SI 4 "=h"))] + (match_dup 0)))] "ISA_HAS_MACC && reload_completed" "macc\t%3,%1,%2" [(set_attr "type" "imadd") @@ -1432,8 +1404,7 @@ (define_insn "*msac2" (set (match_operand:SI 3 "register_operand" "=d") (minus:SI (match_dup 0) (mult:SI (match_dup 1) - (match_dup 2)))) - (clobber (match_scratch:SI 4 "=h"))] + (match_dup 2))))] "ISA_HAS_MSAC && reload_completed" "msac\t%3,%1,%2" [(set_attr "type" "imadd") @@ -1444,23 +1415,19 @@ (define_insn "*msac2" ;; ;; Operand 0: LO ;; Operand 1: macc/msac -;; Operand 2: HI -;; Operand 3: GPR (destination) +;; Operand 2: GPR (destination) (define_peephole2 [(parallel - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "lo_operand") (match_operand:SI 1 "macc_msac_operand")) - (clobber (match_operand:SI 2 "register_operand")) (clobber (scratch:SI))]) - (set (match_operand:SI 3 "register_operand") - (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))] + (set (match_operand:SI 2 "d_operand") + (match_dup 0))] "" [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 3) - (match_dup 1)) - (clobber (match_dup 2))])] - "") + (set (match_dup 2) + (match_dup 1))])]) ;; When we have a three-address multiplication instruction, it should ;; be faster to do a separate multiply and add, rather than moving @@ -1474,32 +1441,26 @@ (define_peephole2 ;; Operand 2: GPR (addend) ;; Operand 3: GPR (destination) ;; Operand 4: macc/msac -;; Operand 5: HI -;; Operand 6: new multiplication -;; Operand 7: new addition/subtraction +;; Operand 5: new multiplication +;; Operand 6: new addition/subtraction (define_peephole2 [(match_scratch:SI 0 "d") - (set (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) + (set (match_operand:SI 1 "lo_operand") + (match_operand:SI 2 "d_operand")) (match_dup 0) (parallel - [(set (match_operand:SI 3 "register_operand") + [(set (match_operand:SI 3 "d_operand") (match_operand:SI 4 "macc_msac_operand")) - (clobber (match_operand:SI 5 "register_operand")) (clobber (match_dup 1))])] - "ISA_HAS_MUL3 - && true_regnum (operands[1]) == LO_REGNUM - && peep2_reg_dead_p (2, operands[1]) - && GP_REG_P (true_regnum (operands[3]))" + "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])" [(parallel [(set (match_dup 0) - (match_dup 6)) - (clobber (match_dup 5)) + (match_dup 5)) (clobber (match_dup 1))]) (set (match_dup 3) - (match_dup 7))] + (match_dup 6))] { - operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); - operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, + operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, operands[2], operands[0]); }) @@ -1509,33 +1470,30 @@ (define_peephole2 ;; Operand 1: LO ;; Operand 2: GPR (addend) ;; Operand 3: macc/msac -;; Operand 4: HI -;; Operand 5: GPR (destination) -;; Operand 6: new multiplication -;; Operand 7: new addition/subtraction +;; Operand 4: GPR (destination) +;; Operand 5: new multiplication +;; Operand 6: new addition/subtraction (define_peephole2 [(match_scratch:SI 0 "d") - (set (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) + (set (match_operand:SI 1 "lo_operand") + (match_operand:SI 2 "d_operand")) (match_dup 0) (parallel [(set (match_dup 1) (match_operand:SI 3 "macc_msac_operand")) - (clobber (match_operand:SI 4 "register_operand")) (clobber (scratch:SI))]) (match_dup 0) - (set (match_operand:SI 5 "register_operand") - (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))] + (set (match_operand:SI 4 "d_operand") + (match_dup 1))] "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])" [(parallel [(set (match_dup 0) - (match_dup 6)) - (clobber (match_dup 4)) + (match_dup 5)) (clobber (match_dup 1))]) - (set (match_dup 5) - (match_dup 7))] + (set (match_dup 4) + (match_dup 6))] { - operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); - operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, + operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1); + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, operands[2], operands[0]); }) @@ -1544,9 +1502,8 @@ (define_insn "*mul_sub_si" (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d") (mult:SI (match_operand:SI 2 "register_operand" "d,d,d") (match_operand:SI 3 "register_operand" "d,d,d")))) - (clobber (match_scratch:SI 4 "=h,h,h")) - (clobber (match_scratch:SI 5 "=X,1,l")) - (clobber (match_scratch:SI 6 "=X,X,&d"))] + (clobber (match_scratch:SI 4 "=X,1,l")) + (clobber (match_scratch:SI 5 "=X,X,&d"))] "GENERATE_MADD_MSUB" "@ msub\t%2,%3 @@ -1556,52 +1513,45 @@ (define_insn "*mul_sub_si" (set_attr "mode" "SI") (set_attr "length" "4,8,8")]) -;; Split the above insn if we failed to get LO allocated. +;; Split *mul_sub_si if both the source and destination accumulator +;; values are GPRs. (define_split - [(set (match_operand:SI 0 "register_operand") - (minus:SI (match_operand:SI 1 "register_operand") - (mult:SI (match_operand:SI 2 "register_operand") - (match_operand:SI 3 "register_operand")))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && GP_REG_P (true_regnum (operands[1]))" - [(parallel [(set (match_dup 6) + [(set (match_operand:SI 0 "d_operand") + (minus:SI (match_operand:SI 1 "d_operand") + (mult:SI (match_operand:SI 2 "d_operand") + (match_operand:SI 3 "d_operand")))) + (clobber (match_operand:SI 4 "lo_operand")) + (clobber (match_operand:SI 5 "d_operand"))] + "reload_completed && !TARGET_DEBUG_D_MODE" + [(parallel [(set (match_dup 5) (mult:SI (match_dup 2) (match_dup 3))) - (clobber (match_dup 4)) - (clobber (match_dup 5))]) - (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))] + (clobber (match_dup 4))]) + (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))] "") -;; Splitter to copy result of MSUB to a general register +;; Split *mul_acc_si if the destination accumulator value is in a GPR +;; and the source accumulator value is in LO. (define_split - [(set (match_operand:SI 0 "register_operand") - (minus:SI (match_operand:SI 1 "register_operand") - (mult:SI (match_operand:SI 2 "register_operand") - (match_operand:SI 3 "register_operand")))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && true_regnum (operands[1]) == LO_REGNUM" + [(set (match_operand:SI 0 "d_operand") + (minus:SI (match_operand:SI 1 "lo_operand") + (mult:SI (match_operand:SI 2 "d_operand") + (match_operand:SI 3 "d_operand")))) + (clobber (match_dup 1)) + (clobber (scratch:SI))] + "reload_completed && !TARGET_DEBUG_D_MODE" [(parallel [(set (match_dup 1) (minus:SI (match_dup 1) (mult:SI (match_dup 2) (match_dup 3)))) - (clobber (match_dup 4)) - (clobber (match_dup 5)) - (clobber (match_dup 6))]) - (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))] + (clobber (scratch:SI)) + (clobber (scratch:SI))]) + (set (match_dup 0) (match_dup 1))] "") (define_insn "*muls" - [(set (match_operand:SI 0 "register_operand" "=l,d") + [(set (match_operand:SI 0 "register_operand" "=l,d") (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d")))) - (clobber (match_scratch:SI 3 "=h,h")) - (clobber (match_scratch:SI 4 "=X,l"))] + (clobber (match_scratch:SI 3 "=X,l"))] "ISA_HAS_MULS" "@ muls\t$0,%1,%2 @@ -1609,31 +1559,23 @@ (define_insn "*muls" [(set_attr "type" "imul,imul3") (set_attr "mode" "SI")]) -;; ??? We could define a mulditi3 pattern when TARGET_64BIT. - (define_expand "mulsidi3" - [(parallel - [(set (match_operand:DI 0 "register_operand") - (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) - (any_extend:DI (match_operand:SI 2 "register_operand")))) - (clobber (scratch:DI)) - (clobber (scratch:DI)) - (clobber (scratch:DI))])] + [(set (match_operand:DI 0 "register_operand") + (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) + (any_extend:DI (match_operand:SI 2 "register_operand"))))] "!TARGET_64BIT || !TARGET_FIX_R4000" { - if (!TARGET_64BIT) - { - if (!TARGET_FIX_R4000) - emit_insn (gen_mulsidi3_32bit_internal (operands[0], operands[1], - operands[2])); - else - emit_insn (gen_mulsidi3_32bit_r4000 (operands[0], operands[1], - operands[2])); - DONE; - } + if (TARGET_64BIT) + emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2])); + else if (TARGET_FIX_R4000) + emit_insn (gen_mulsidi3_32bit_r4000 (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_mulsidi3_32bit (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "mulsidi3_32bit_internal" +(define_insn "mulsidi3_32bit" [(set (match_operand:DI 0 "register_operand" "=x") (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))] @@ -1648,42 +1590,35 @@ (define_insn "mulsidi3_32bit_r4000" (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) (clobber (match_scratch:DI 3 "=x"))] "!TARGET_64BIT && TARGET_FIX_R4000" - "mult\t%1,%2\;mflo\t%L0;mfhi\t%M0" + "mult\t%1,%2\;mflo\t%L0\;mfhi\t%M0" [(set_attr "type" "imul") (set_attr "mode" "SI") (set_attr "length" "12")]) -(define_insn_and_split "*mulsidi3_64bit" +(define_insn_and_split "mulsidi3_64bit" [(set (match_operand:DI 0 "register_operand" "=d") (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) - (clobber (match_scratch:DI 3 "=l")) - (clobber (match_scratch:DI 4 "=h")) - (clobber (match_scratch:DI 5 "=d"))] + (clobber (match_scratch:TI 3 "=x")) + (clobber (match_scratch:DI 4 "=d"))] "TARGET_64BIT && !TARGET_FIX_R4000" "#" "&& reload_completed" - [(parallel - [(set (match_dup 3) - (sign_extend:DI - (mult:SI (match_dup 1) - (match_dup 2)))) - (set (match_dup 4) - (ashiftrt:DI - (mult:DI (any_extend:DI (match_dup 1)) - (any_extend:DI (match_dup 2))) - (const_int 32)))]) - - ;; OP5 <- LO, OP0 <- HI - (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO)) - (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO)) - - ;; Zero-extend OP5. - (set (match_dup 5) - (ashift:DI (match_dup 5) + [(set (match_dup 3) + (unspec:TI [(mult:DI (any_extend:DI (match_dup 1)) + (any_extend:DI (match_dup 2)))] + UNSPEC_SET_HILO)) + + ;; OP4 <- LO, OP0 <- HI + (set (match_dup 4) (match_dup 5)) + (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI)) + + ;; Zero-extend OP4. + (set (match_dup 4) + (ashift:DI (match_dup 4) (const_int 32))) - (set (match_dup 5) - (lshiftrt:DI (match_dup 5) + (set (match_dup 4) + (lshiftrt:DI (match_dup 4) (const_int 32))) ;; Shift OP0 into place. @@ -1694,24 +1629,21 @@ (define_insn_and_split "*mulsidi3_64b ;; OR the two halves together (set (match_dup 0) (ior:DI (match_dup 0) - (match_dup 5)))] - "" + (match_dup 4)))] + { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); } [(set_attr "type" "imul") (set_attr "mode" "SI") (set_attr "length" "24")]) -(define_insn "*mulsidi3_64bit_parts" - [(set (match_operand:DI 0 "register_operand" "=l") - (sign_extend:DI - (mult:SI (match_operand:SI 2 "register_operand" "d") - (match_operand:SI 3 "register_operand" "d")))) - (set (match_operand:DI 1 "register_operand" "=h") - (ashiftrt:DI - (mult:DI (any_extend:DI (match_dup 2)) - (any_extend:DI (match_dup 3))) - (const_int 32)))] +(define_insn "mulsidi3_64bit_hilo" + [(set (match_operand:TI 0 "register_operand" "=x") + (unspec:TI + [(mult:DI + (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d")))] + UNSPEC_SET_HILO))] "TARGET_64BIT && !TARGET_FIX_R4000" - "mult\t%2,%3" + "mult\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -1755,7 +1687,7 @@ (define_expand "mulsi3_highpart" (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) (any_extend:DI (match_operand:SI 2 "register_operand"))) (const_int 32))))] - "ISA_HAS_MULHI || !TARGET_FIX_R4000" + "ISA_HAS_MULHI" { if (ISA_HAS_MULHI) emit_insn (gen_mulsi3_highpart_mulhi_internal (operands[0], @@ -1767,72 +1699,133 @@ (define_expand "mulsi3_highpart" DONE; }) -(define_insn "mulsi3_highpart_internal" - [(set (match_operand:SI 0 "register_operand" "=h") +(define_insn_and_split "mulsi3_highpart_internal" + [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) (const_int 32)))) (clobber (match_scratch:SI 3 "=l"))] - "!ISA_HAS_MULHI && !TARGET_FIX_R4000" - "mult\t%1,%2" + "!ISA_HAS_MULHI" + { return TARGET_FIX_R4000 ? "mult\t%1,%2\n\tmfhi\t%0" : "#"; } + "&& reload_completed && !TARGET_FIX_R4000" + [(const_int 0)] +{ + rtx hilo; + + if (TARGET_64BIT) + { + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_mulsidi3_64bit_hilo (hilo, operands[1], operands[2])); + emit_insn (gen_mfhisi_ti (operands[0], hilo)); + } + else + { + hilo = gen_rtx_REG (DImode, MD_REG_FIRST); + emit_insn (gen_mulsidi3_32bit (hilo, operands[1], operands[2])); + emit_insn (gen_mfhisi_di (operands[0], hilo)); + } + DONE; +} [(set_attr "type" "imul") - (set_attr "mode" "SI")]) + (set_attr "mode" "SI") + (set_attr "length" "8")]) (define_insn "mulsi3_highpart_mulhi_internal" - [(set (match_operand:SI 0 "register_operand" "=h,d") + [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI - (any_extend:DI (match_operand:SI 1 "register_operand" "d,d")) - (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))) + (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=l,l")) - (clobber (match_scratch:SI 4 "=X,h"))] + (clobber (match_scratch:SI 3 "=l"))] "ISA_HAS_MULHI" - "@ - mult\t%1,%2 - mulhi\t%0,%1,%2" - [(set_attr "type" "imul,imul3") + "mulhi\t%0,%1,%2" + [(set_attr "type" "imul3") (set_attr "mode" "SI")]) (define_insn "*mulsi3_highpart_neg_mulhi_internal" - [(set (match_operand:SI 0 "register_operand" "=h,d") + [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (neg:DI (mult:DI - (any_extend:DI (match_operand:SI 1 "register_operand" "d,d")) - (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))) + (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=l,l")) - (clobber (match_scratch:SI 4 "=X,h"))] + (clobber (match_scratch:SI 3 "=l"))] "ISA_HAS_MULHI" - "@ - mulshi\t%.,%1,%2 - mulshi\t%0,%1,%2" - [(set_attr "type" "imul,imul3") + "mulshi\t%0,%1,%2" + [(set_attr "type" "imul3") (set_attr "mode" "SI")]) ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120 ;; errata MD(0), which says that dmultu does not always produce the ;; correct result. -(define_insn "muldi3_highpart" - [(set (match_operand:DI 0 "register_operand" "=h") +(define_insn_and_split "muldi3_highpart" + [(set (match_operand:DI 0 "register_operand" "=d") (truncate:DI (lshiftrt:TI - (mult:TI - (any_extend:TI (match_operand:DI 1 "register_operand" "d")) - (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) + (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) (const_int 64)))) (clobber (match_scratch:DI 3 "=l"))] - "TARGET_64BIT && !TARGET_FIX_R4000 + "TARGET_64BIT && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" + { return TARGET_FIX_R4000 ? "dmult\t%1,%2\n\tmfhi\t%0" : "#"; } + "&& reload_completed && !TARGET_FIX_R4000" + [(const_int 0)] +{ + rtx hilo; + + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_mulditi3_internal (hilo, operands[1], operands[2])); + emit_insn (gen_mfhidi_ti (operands[0], hilo)); + DONE; +} + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "8")]) + +(define_expand "mulditi3" + [(set (match_operand:TI 0 "register_operand") + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) + (any_extend:TI (match_operand:DI 2 "register_operand"))))] + "TARGET_64BIT && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" +{ + if (TARGET_FIX_R4000) + emit_insn (gen_mulditi3_r4000 (operands[0], operands[1], operands[2])); + else + emit_insn (gen_mulditi3_internal (operands[0], operands[1], + operands[2])); + DONE; +}) + +(define_insn "mulditi3_internal" + [(set (match_operand:TI 0 "register_operand" "=x") + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) + (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))] + "TARGET_64BIT + && !TARGET_FIX_R4000 && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" "dmult\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) +(define_insn "mulditi3_r4000" + [(set (match_operand:TI 0 "register_operand" "=d") + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) + (any_extend:TI (match_operand:DI 2 "register_operand" "d")))) + (clobber (match_scratch:TI 3 "=x"))] + "TARGET_64BIT + && TARGET_FIX_R4000 + && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" + "dmult\t%1,%2\;mflo\t%L0\;mfhi\t%M0" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "12")]) + ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate ;; instruction. The HI/LO registers are used as a 64-bit accumulator. @@ -1840,8 +1833,7 @@ (define_insn "madsi" [(set (match_operand:SI 0 "register_operand" "+l") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")) - (match_dup 0))) - (clobber (match_scratch:SI 3 "=h"))] + (match_dup 0)))] "TARGET_MAD" "mad\t%1,%2" [(set_attr "type" "imadd") @@ -2016,29 +2008,74 @@ (define_insn "*recip3" ;; VR4120 errata MD(A1): signed division instructions do not work correctly ;; with negative operands. We use special libgcc functions instead. -(define_insn "divmod4" +(define_insn_and_split "divmod4" [(set (match_operand:GPR 0 "register_operand" "=l") (div:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d"))) - (set (match_operand:GPR 3 "register_operand" "=h") + (set (match_operand:GPR 3 "register_operand" "=d") (mod:GPR (match_dup 1) (match_dup 2)))] "!TARGET_FIX_VR4120" - { return mips_output_division ("div\t$0,%1,%2", operands); } - [(set_attr "type" "idiv") - (set_attr "mode" "")]) + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx hilo; + + if (TARGET_64BIT) + { + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_divmod4_hilo_ti (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_ti (operands[3], hilo)); + } + else + { + hilo = gen_rtx_REG (DImode, MD_REG_FIRST); + emit_insn (gen_divmod4_hilo_di (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_di (operands[3], hilo)); + } + DONE; +}) -(define_insn "udivmod4" +(define_insn_and_split "udivmod4" [(set (match_operand:GPR 0 "register_operand" "=l") (udiv:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d"))) - (set (match_operand:GPR 3 "register_operand" "=h") + (set (match_operand:GPR 3 "register_operand" "=d") (umod:GPR (match_dup 1) (match_dup 2)))] "" - { return mips_output_division ("divu\t$0,%1,%2", operands); } + "#" + "reload_completed" + [(const_int 0)] +{ + rtx hilo; + + if (TARGET_64BIT) + { + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_udivmod4_hilo_ti (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_ti (operands[3], hilo)); + } + else + { + hilo = gen_rtx_REG (DImode, MD_REG_FIRST); + emit_insn (gen_udivmod4_hilo_di (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_di (operands[3], hilo)); + } + DONE; +}) + +(define_insn "divmod4_hilo_" + [(set (match_operand:HILO 0 "register_operand" "=x") + (unspec:HILO + [(any_div:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "register_operand" "d"))] + UNSPEC_SET_HILO))] + "" + { return mips_output_division ("div\t%.,%1,%2", operands); } [(set_attr "type" "idiv") - (set_attr "mode" "")]) + (set_attr "mode" "")]) ;; ;; .................... @@ -3240,7 +3277,7 @@ (define_insn_and_split "*lea_high64" ;; dsll32 op1,op1,0 ;; daddu op1,op1,op0 (define_peephole2 - [(set (match_operand:DI 1 "register_operand") + [(set (match_operand:DI 1 "d_operand") (high:DI (match_operand:DI 2 "absolute_symbolic_operand"))) (match_scratch:DI 0 "d")] "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" @@ -3293,8 +3330,8 @@ (define_insn_and_split "*lea64" ;; ;; on MIPS16 targets. (define_split - [(set (match_operand:SI 0 "register_operand" "=d") - (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))] + [(set (match_operand:SI 0 "d_operand") + (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))] "TARGET_MIPS16 && reload_completed" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))] @@ -3463,7 +3500,7 @@ (define_insn "*movdi_32bit" && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store") + [(set_attr "type" "multi,multi,load,store,multi,multi,mtc,load,mfc,store") (set_attr "mode" "DI") (set_attr "length" "8,16,*,*,8,8,8,*,8,*")]) @@ -3474,7 +3511,7 @@ (define_insn "*movdi_gp32_fp64" && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore") + [(set_attr "type" "multi,multi,load,store,multi,multi,mtc,fpload,mfc,fpstore") (set_attr "mode" "DI") (set_attr "length" "8,16,*,*,8,8,8,*,8,*")]) @@ -3485,29 +3522,29 @@ (define_insn "*movdi_32bit_mips16" && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo") + [(set_attr "type" "multi,multi,multi,multi,multi,load,store,multi") (set_attr "mode" "DI") (set_attr "length" "8,8,8,8,12,*,*,8")]) (define_insn "*movdi_64bit" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m") - (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m") + (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] "TARGET_64BIT && !TARGET_MIPS16 && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store") + [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,load,mfc,store") (set_attr "mode" "DI") - (set_attr "length" "4,*,*,*,*,4,*,4,*,4,8,*,8,*")]) + (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,8,*,8,*")]) (define_insn "*movdi_64bit_mips16" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m") - (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") + (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d,*a"))] "TARGET_64BIT && TARGET_MIPS16 && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "move,move,move,arith,arith,load,const,load,store") + [(set_attr "type" "move,move,move,arith,arith,load,const,load,store,mfhilo") (set_attr "mode" "DI") (set_attr_alternative "length" [(const_int 4) @@ -3522,7 +3559,8 @@ (define_insn "*movdi_64bit_mips16" (const_int 8) (const_string "*") (const_string "*") - (const_string "*")])]) + (const_string "*") + (const_int 4)])]) ;; On the mips16, we can split ld $r,N($r) into an add and a load, @@ -3530,14 +3568,11 @@ (define_insn "*movdi_64bit_mips16" ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:DI 0 "register_operand") + [(set (match_operand:DI 0 "d_operand") (mem:DI (plus:DI (match_dup 0) (match_operand:DI 1 "const_int_operand"))))] "TARGET_64BIT && TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x10) || (INTVAL (operands[1]) >= 32 * 8 @@ -3588,7 +3623,7 @@ (define_expand "movsi" (define_insn "*movsi_internal" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") - (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))] + (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] "!TARGET_MIPS16 && (register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode))" @@ -3598,13 +3633,13 @@ (define_insn "*movsi_internal" (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,4,4,4,*,4,*")]) (define_insn "*movsi_mips16" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m") - (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") + (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d,*a"))] "TARGET_MIPS16 && (register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "move,move,move,arith,arith,load,const,load,store") + [(set_attr "type" "move,move,move,arith,arith,load,const,load,store,mfhilo") (set_attr "mode" "SI") (set_attr_alternative "length" [(const_int 4) @@ -3619,20 +3654,18 @@ (define_insn "*movsi_mips16" (const_int 8) (const_string "*") (const_string "*") - (const_string "*")])]) + (const_string "*") + (const_int 4)])]) ;; On the mips16, we can split lw $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "d_operand") (mem:SI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand"))))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x80) || (INTVAL (operands[1]) >= 32 * 4 @@ -3668,12 +3701,9 @@ (define_split ;; instructions. (define_split - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "d_operand") (match_operand:SI 1 "const_int_operand"))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 0x100 && INTVAL (operands[1]) <= 0xff + 0x7f" [(set (match_dup 0) (match_dup 1)) @@ -3796,36 +3826,24 @@ (define_expand "movhi" }) (define_insn "*movhi_internal" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*x") - (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d") + (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))] "!TARGET_MIPS16 && (register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode))" - "@ - move\t%0,%1 - li\t%0,%1 - lhu\t%0,%1 - sh\t%z1,%0 - mt%0\t%1" - [(set_attr "type" "move,arith,load,store,mthilo") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,arith,load,store,mthilo,mfhilo") (set_attr "mode" "HI") - (set_attr "length" "4,4,*,*,4")]) + (set_attr "length" "4,4,*,*,4,4")]) (define_insn "*movhi_mips16" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m") - (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") + (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] "TARGET_MIPS16 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" - "@ - move\t%0,%1 - move\t%0,%1 - move\t%0,%1 - li\t%0,%1 - # - lhu\t%0,%1 - sh\t%1,%0" - [(set_attr "type" "move,move,move,arith,arith,load,store") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,move,move,arith,arith,load,store,mfhilo") (set_attr "mode" "HI") (set_attr_alternative "length" [(const_int 4) @@ -3838,6 +3856,7 @@ (define_insn "*movhi_mips16" (const_int 8) (const_int 12)) (const_string "*") + (const_string "*") (const_string "*")])]) @@ -3846,13 +3865,10 @@ (define_insn "*movhi_mips16" ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:HI 0 "register_operand") + [(set (match_operand:HI 0 "d_operand") (mem:HI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand"))))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x80) || (INTVAL (operands[1]) >= 32 * 2 @@ -3900,51 +3916,36 @@ (define_expand "movqi" }) (define_insn "*movqi_internal" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*x") - (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d") + (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))] "!TARGET_MIPS16 && (register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode))" - "@ - move\t%0,%1 - li\t%0,%1 - lbu\t%0,%1 - sb\t%z1,%0 - mt%0\t%1" - [(set_attr "type" "move,arith,load,store,mthilo") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,arith,load,store,mthilo,mfhilo") (set_attr "mode" "QI") - (set_attr "length" "4,4,*,*,4")]) + (set_attr "length" "4,4,*,*,4,4")]) (define_insn "*movqi_mips16" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m") - (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") + (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] "TARGET_MIPS16 && (register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" - "@ - move\t%0,%1 - move\t%0,%1 - move\t%0,%1 - li\t%0,%1 - # - lbu\t%0,%1 - sb\t%1,%0" - [(set_attr "type" "move,move,move,arith,arith,load,store") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,move,move,arith,arith,load,store,mfhilo") (set_attr "mode" "QI") - (set_attr "length" "4,4,4,4,8,*,*")]) + (set_attr "length" "4,4,4,4,8,*,*,4")]) ;; On the mips16, we can split lb $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:QI 0 "register_operand") + [(set (match_operand:QI 0 "d_operand") (mem:QI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand"))))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x80) || (INTVAL (operands[1]) >= 32 @@ -4064,6 +4065,39 @@ (define_insn "*movdf_mips16" (set_attr "mode" "DF") (set_attr "length" "8,8,8,*,*")]) +;; 128-bit integer moves + +(define_expand "movti" + [(set (match_operand:TI 0) + (match_operand:TI 1))] + "TARGET_64BIT" +{ + if (mips_legitimize_move (TImode, operands[0], operands[1])) + DONE; +}) + +(define_insn "*movti" + [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,m,*a,*d") + (match_operand:TI 1 "move_operand" "di,m,dJ,*d*J,*a"))] + "TARGET_64BIT + && !TARGET_MIPS16 + && (register_operand (operands[0], TImode) + || reg_or_0_operand (operands[1], TImode))" + "#" + [(set_attr "type" "multi,load,store,multi,multi") + (set_attr "length" "8,*,*,8,8")]) + +(define_insn "*movti_mips16" + [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") + (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] + "TARGET_64BIT + && TARGET_MIPS16 + && (register_operand (operands[0], TImode) + || register_operand (operands[1], TImode))" + "#" + [(set_attr "type" "multi,multi,multi,multi,multi,load,store,multi") + (set_attr "length" "8,8,8,12,16,*,*,8")]) + ;; 128-bit floating point moves (define_expand "movtf" @@ -4122,7 +4156,7 @@ (define_split ;; When generating mips16 code, split moves of negative constants into ;; a positive "li" followed by a negation. (define_split - [(set (match_operand 0 "register_operand") + [(set (match_operand 0 "d_operand") (match_operand 1 "const_int_operand"))] "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0" [(set (match_dup 2) @@ -4171,44 +4205,27 @@ (define_insn "movv2sf_hardfloat_32bit" (set_attr "mode" "SF") (set_attr "length" "4,8,*,*,*,8,8,8,*,*")]) -;; The HI and LO registers are not truly independent. If we move an mthi -;; instruction before an mflo instruction, it will make the result of the -;; mflo unpredictable. The same goes for mtlo and mfhi. -;; -;; We cope with this by making the mflo and mfhi patterns use both HI and LO. -;; Operand 1 is the register we want, operand 2 is the other one. -;; -;; When generating VR4120 or VR4130 code, we use macc{,hi} and -;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal -;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130. - -(define_expand "mfhilo_" - [(set (match_operand:GPR 0 "register_operand") - (unspec:GPR [(match_operand:GPR 1 "register_operand") - (match_operand:GPR 2 "register_operand")] - UNSPEC_MFHILO))]) - -(define_insn "*mfhilo_" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") - (match_operand:GPR 2 "register_operand" "l,h")] - UNSPEC_MFHILO))] - "!ISA_HAS_MACCHI" - "mf%1\t%0" +;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI +;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards +;; and the errata related to -mfix-vr4130. +(define_insn "mfhi_" + [(set (match_operand:GPR 0 "register_operand" "=d") + (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")] + UNSPEC_MFHI))] + "" + { return ISA_HAS_MACCHI ? "macchi\t%0,%.,%." : "mfhi\t%0"; } [(set_attr "type" "mfhilo") - (set_attr "mode" "")]) + (set_attr "mode" "")]) -(define_insn "*mfhilo__macc" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") - (match_operand:GPR 2 "register_operand" "l,h")] - UNSPEC_MFHILO))] - "ISA_HAS_MACCHI" - "@ - macchi\t%0,%.,%. - macc\t%0,%.,%." - [(set_attr "type" "mfhilo") - (set_attr "mode" "")]) +(define_insn "mthi_" + [(set (match_operand:HILO 0 "register_operand" "=x") + (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ") + (match_operand:GPR 2 "register_operand" "l")] + UNSPEC_MTHI))] + "" + "mthi\t%z1" + [(set_attr "type" "mthilo") + (set_attr "mode" "SI")]) ;; Emit a doubleword move in which exactly one of the operands is ;; a floating-point register. We can't just emit two normal moves @@ -5120,11 +5137,10 @@ (define_insn "*lshrdi3_mips16" ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. (define_split - [(set (match_operand:GPR 0 "register_operand") - (any_shift:GPR (match_operand:GPR 1 "register_operand") + [(set (match_operand:GPR 0 "d_operand") + (any_shift:GPR (match_operand:GPR 1 "d_operand") (match_operand:GPR 2 "const_int_operand")))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16" [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8))) Index: gcc/config/mips/predicates.md =================================================================== --- gcc/config/mips/predicates.md 2008-06-01 10:23:31.000000000 +0100 +++ gcc/config/mips/predicates.md 2008-06-01 14:06:06.000000000 +0100 @@ -76,9 +76,11 @@ (define_predicate "const_0_or_1_operand" (ior (match_test "op == CONST0_RTX (GET_MODE (op))") (match_test "op == CONST1_RTX (GET_MODE (op))")))) -(define_predicate "fpr_operand" +(define_predicate "d_operand" (and (match_code "reg") - (match_test "FP_REG_P (REGNO (op))"))) + (match_test "TARGET_MIPS16 + ? M16_REG_P (REGNO (op)) + : GP_REG_P (REGNO (op))"))) (define_predicate "lo_operand" (and (match_code "reg") Index: gcc/testsuite/gcc.dg/torture/mips-hilo-1.c =================================================================== --- gcc/testsuite/gcc.dg/torture/mips-hilo-1.c 2008-06-01 10:23:31.000000000 +0100 +++ /dev/null 2008-05-31 10:25:53.548096750 +0100 @@ -1,73 +0,0 @@ -/* f1 checks that an mtlo is not moved before an mfhi. f2 does the same - for an mthi and an mflo. */ -/* { dg-do run { target mips*-*-* } } */ -/* { dg-options "-mtune=rm7000" } */ - -extern void abort (void); -extern void exit (int); - -#define DECLARE(TYPE) \ - TYPE __attribute__ ((noinline)) __attribute__ ((nomips16)) \ - f1##TYPE (TYPE x1, TYPE x2, TYPE x3) \ - { \ - TYPE t1, t2; \ - \ - asm ("mult\t%1,%2" : "=h" (t1) : "d" (x1), "d" (x2) : "lo"); \ - asm ("mflo\t%0" : "=r" (t2) : "l" (x3) : "hi"); \ - return t1 + t2; \ - } \ - \ - TYPE __attribute__ ((noinline)) __attribute__ ((nomips16)) \ - f2##TYPE (TYPE x1, TYPE x2, TYPE x3) \ - { \ - TYPE t1, t2; \ - \ - asm ("mult\t%1,%2" : "=l" (t1) : "d" (x1), "d" (x2) : "hi"); \ - asm ("mfhi\t%0" : "=r" (t2) : "h" (x3) : "lo"); \ - return t1 + t2; \ - } - -#define TEST(TYPE) \ - if (f1##TYPE (1, 2, 10) != 10) \ - abort (); \ - if (f2##TYPE (1, 2, 40) != 42) \ - abort () - -typedef char c; -typedef signed char sc; -typedef unsigned char uc; -typedef short s; -typedef unsigned short us; -typedef int i; -typedef unsigned int ui; -typedef long long ll; -typedef unsigned long long ull; - -DECLARE (c) -DECLARE (sc) -DECLARE (uc) -DECLARE (s) -DECLARE (us) -DECLARE (i) -DECLARE (ui) -#if defined (__mips64) -DECLARE (ll) -DECLARE (ull) -#endif - -int -main () -{ - TEST (c); - TEST (sc); - TEST (uc); - TEST (s); - TEST (us); - TEST (i); - TEST (ui); -#if defined (__mips64) - TEST (ll); - TEST (ull); -#endif - exit (0); -} Index: gcc/testsuite/gcc.target/mips/pr35232.c =================================================================== --- gcc/testsuite/gcc.target/mips/pr35232.c 2008-06-01 10:23:31.000000000 +0100 +++ /dev/null 2008-05-31 10:25:53.548096750 +0100 @@ -1,17 +0,0 @@ -/* { dg-do run } */ -/* { dg-mips-options "-O" } */ - -NOMIPS16 unsigned int -f1 (unsigned long long x) -{ - unsigned int r; - asm ("# %0" : "=a" (r) : "0" (x)); - asm ("# %0" : "=h" (r) : "0" (r)); - return r; -} - -int -main (void) -{ - return f1 (4) != 4; -} Index: gcc/testsuite/gcc.target/mips/fix-vr4130-1.c =================================================================== --- gcc/testsuite/gcc.target/mips/fix-vr4130-1.c 2008-06-01 10:23:31.000000000 +0100 +++ gcc/testsuite/gcc.target/mips/fix-vr4130-1.c 2008-06-01 14:06:06.000000000 +0100 @@ -1,4 +1,8 @@ /* { dg-do compile } */ /* { dg-mips-options "-march=vr4130 -mfix-vr4130" } */ -NOMIPS16 int foo (void) { int r; asm ("# foo" : "=h" (r)); return r; } +NOMIPS16 unsigned int +foo (unsigned int x, unsigned int y) +{ + return x % y; +} /* { dg-final { scan-assembler "\tmacchi\t" } } */ Index: gcc/testsuite/gcc.target/mips/fix-vr4130-3.c =================================================================== --- gcc/testsuite/gcc.target/mips/fix-vr4130-3.c 2008-06-01 10:23:31.000000000 +0100 +++ gcc/testsuite/gcc.target/mips/fix-vr4130-3.c 2008-06-01 14:06:06.000000000 +0100 @@ -1,10 +1,8 @@ /* { dg-do compile } */ /* { dg-mips-options "-march=vr4130 -mgp64 -mfix-vr4130" } */ -NOMIPS16 long long -foo (void) +NOMIPS16 unsigned long long +foo (unsigned long long x, unsigned long long y) { - long long r; - asm ("# foo" : "=h" (r)); - return r; + return x % y; } /* { dg-final { scan-assembler "\tdmacchi\t" } } */ Index: gcc/testsuite/gcc.target/mips/int-moves-1.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/int-moves-1.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,40 @@ +/* { dg-do compile { target mips16_attribute } } */ +/* { dg-mips-options "-mgp64 -msoft-float -O2 -EL" } */ +/* { dg-add-options mips16_attribute } */ + +typedef unsigned uint128_t __attribute__((mode(TI))); + +extern uint128_t g[16]; +extern unsigned char gstuff[0x10000]; + +NOMIPS16 uint128_t +foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} + +MIPS16 uint128_t +bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} Index: gcc/testsuite/gcc.target/mips/int-moves-2.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/int-moves-2.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,40 @@ +/* { dg-do compile { target mips16_attribute } } */ +/* { dg-mips-options "-mgp64 -msoft-float -O2 -EB" } */ +/* { dg-add-options mips16_attribute } */ + +typedef unsigned uint128_t __attribute__((mode(TI))); + +extern uint128_t g[16]; +extern unsigned char gstuff[0x10000]; + +NOMIPS16 uint128_t +foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} + +MIPS16 uint128_t +bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} Index: gcc/testsuite/gcc.target/mips/fix-r4000-1.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-1.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,6 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -O2 -dp" } */ +typedef int int32_t; +typedef int uint32_t; +int32_t foo (int32_t x, int32_t y) { return x * y; } +uint32_t bar (uint32_t x, uint32_t y) { return x * y; } +/* { dg-final { scan-assembler-times "[concat {\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-2.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-2.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */ +typedef int int32_t; +typedef long long int64_t; +int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-3.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-3.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */ +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-4.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-4.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */ +typedef int int32_t; +typedef long long int64_t; +int64_t foo (int32_t x, int32_t y) { return (int64_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-5.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-5.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */ +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +uint64_t foo (uint32_t x, uint32_t y) { return (uint64_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-6.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-6.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,6 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ +typedef long long int64_t; +typedef unsigned long long uint64_t; +int64_t foo (int64_t x, int64_t y) { return x * y; } +uint64_t bar (uint64_t x, uint64_t y) { return x * y; } +/* { dg-final { scan-assembler-times "[concat {\tdmult\t\$[45],\$[45][^\n]+muldi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-7.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-7.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */ +typedef long long int64_t; +typedef int int128_t __attribute__((mode(TI))); +int64_t foo (int64_t x, int64_t y) { return ((int128_t) x * y) >> 64; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-8.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-8.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */ +typedef unsigned long long uint64_t; +typedef unsigned int uint128_t __attribute__((mode(TI))); +uint64_t foo (uint64_t x, uint64_t y) { return ((uint128_t) x * y) >> 64; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-9.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-9.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */ +typedef long long int64_t; +typedef int int128_t __attribute__((mode(TI))); +int128_t foo (int64_t x, int64_t y) { return (int128_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-10.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-10.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */ +typedef unsigned long long uint64_t; +typedef unsigned int uint128_t __attribute__((mode(TI))); +uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-11.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-11.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,4 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ +typedef long long int64_t; +int64_t foo (int64_t x) { return x / 11993; } +/* { dg-final { scan-assembler "[concat {\tdmult\t\$4,\$[0-9]+[^\n]+smuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-12.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-12.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,4 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ +typedef unsigned long long uint64_t; +uint64_t foo (uint64_t x) { return x / 11993; } +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$4,\$[0-9]+[^\n]+umuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/timode-1.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/timode-1.c 2008-06-01 14:21:51.000000000 +0100 @@ -0,0 +1,65 @@ +/* { dg-mips-options "-mgp64" } */ +typedef int int128_t __attribute__((mode(TI))); +typedef unsigned int uint128_t __attribute__((mode(TI))); + +#define UINT128_CONST(A, B) \ + (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL)) + +volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222); +volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003); +volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666); +volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500); +volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66); +volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100); +volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66); +volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66); +volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660); +volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6); +volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6); + +volatile int amount = 4; + +volatile uint128_t result; + +int +main (void) +{ + result = a * b; + if (result != c) + return 1; + + result = c + d; + if (result != e) + return 1; + + result = e - d; + if (result != c) + return 1; + + result = d & e; + if (result != f) + return 1; + + result = d ^ e; + if (result != g) + return 1; + + result = d | e; + if (result != h) + return 1; + + result = g << amount; + if (result != i) + return 1; + + result = g >> amount; + if (result != j) + return 1; + + result = (int128_t) g >> amount; + if (result != k) + return 1; + + return 0; +} +/* { dg-final { scan-assembler-not "\tjal" } } */ Index: gcc/testsuite/gcc.target/mips/timode-2.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/timode-2.c 2008-06-01 14:21:36.000000000 +0100 @@ -0,0 +1,64 @@ +/* { dg-do run { target mips64 } } */ +typedef int int128_t __attribute__((mode(TI))); +typedef unsigned int uint128_t __attribute__((mode(TI))); + +#define UINT128_CONST(A, B) \ + (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL)) + +volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222); +volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003); +volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666); +volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500); +volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66); +volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100); +volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66); +volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66); +volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660); +volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6); +volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6); + +volatile int amount = 4; + +volatile uint128_t result; + +int +main (void) +{ + result = a * b; + if (result != c) + return 1; + + result = c + d; + if (result != e) + return 1; + + result = e - d; + if (result != c) + return 1; + + result = d & e; + if (result != f) + return 1; + + result = d ^ e; + if (result != g) + return 1; + + result = d | e; + if (result != h) + return 1; + + result = g << amount; + if (result != i) + return 1; + + result = g >> amount; + if (result != j) + return 1; + + result = (int128_t) g >> amount; + if (result != k) + return 1; + + return 0; +} From anemo@mba.ocn.ne.jp Sun Jun 1 17:33:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Jun 2008 17:33:49 +0100 (BST) Received: from p549F48FC.dip.t-dialin.net ([84.159.72.252]:20181 "EHLO p549F48FC.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20024203AbYFAQdr (ORCPT ); Sun, 1 Jun 2008 17:33:47 +0100 Received: from [122.1.235.107] ([122.1.235.107]:21985 "EHLO smtp.mba.ocn.ne.jp") by lappi.linux-mips.net with ESMTP id S1111367AbYFAQ2q (ORCPT ); Sun, 1 Jun 2008 18:28:46 +0200 Received: from localhost (p7240-ipad212funabasi.chiba.ocn.ne.jp [58.91.171.240]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 390ECAA2B; Mon, 2 Jun 2008 01:26:52 +0900 (JST) Date: Mon, 02 Jun 2008 01:28:14 +0900 (JST) Message-Id: <20080602.012814.35471915.anemo@mba.ocn.ne.jp> To: adrian.bunk@movial.fi Cc: chris@mips.com, ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: mips: CONF_CM_DEFAULT build error From: Atsushi Nemoto In-Reply-To: <20080525170718.GD1791@cs181133002.pp.htv.fi> References: <20080525170718.GD1791@cs181133002.pp.htv.fi> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19391 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sun, 25 May 2008 20:07:24 +0300, Adrian Bunk wrote: > Commit 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 > ([MIPS] Allow setting of the cache attribute at run time.) > causes the following build error with pnx8550-jbs_defconfig > and pnx8550-stb810_defconfig: I wondered why the commit has my S-O-B, and finally found that I had fixed a section mismatch caused by the original patch (on queue tree on linux-mips.org) and Ralf had folded my fix into the original patch, with my S-O-B. Folding on the queue tree will be good on many case, but sometimes a bit confusing. :-) Anyway, here is a patch to fix the build failure. Thank you for reporting. ------------------------------------------------------ Subject: [PATCH] MIPS: Fix CONF_CM_DEFAULT build error From: Atsushi Nemoto Signed-off-by: Atsushi Nemoto --- diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index 60e2f93..8a75677 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -134,6 +134,6 @@ #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) -#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT) +#define CONF_CM_DEFAULT (_page_cachable_default >> _CACHE_SHIFT) #endif /* _ASM_PGTABLE_BITS_H */ From sshtylyov@ru.mvista.com Sun Jun 1 19:02:12 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Jun 2008 19:02:14 +0100 (BST) Received: from p549F48FC.dip.t-dialin.net ([84.159.72.252]:39557 "EHLO p549F48FC.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20024340AbYFASCJ (ORCPT ); Sun, 1 Jun 2008 19:02:09 +0100 Received: from h155.mvista.com ([63.81.120.155]:19062 "EHLO imap.sh.mvista.com") by lappi.linux-mips.net with ESMTP id S1111459AbYFAR4y (ORCPT ); Sun, 1 Jun 2008 19:56:54 +0200 Received: from [127.0.0.1] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 8DB163EC9; Sun, 1 Jun 2008 10:56:19 -0700 (PDT) Message-ID: <4842E2C0.1020106@ru.mvista.com> Date: Sun, 01 Jun 2008 21:56:16 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 1.5.0.14 (Windows/20071210) MIME-Version: 1.0 To: Manuel Lauss Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: make r4k clocksource/clockevent usable in other codepaths References: <20080528122838.GA5976@roarinelk.homelinux.net> In-Reply-To: <20080528122838.GA5976@roarinelk.homelinux.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19392 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Manuel Lauss wrote: > Make the r4k cp0 counter clocksource and clockevent modules > library code so it may be used e.g. as a fallback in case other > clocksources/events aren't available. > > Signed-off-by: Manuel Lauss > [...] > diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h > index d3bd5c5..01a4c93 100644 > --- a/include/asm-mips/time.h > +++ b/include/asm-mips/time.h > @@ -50,27 +50,35 @@ extern int (*perf_irq)(void); > /* > * Initialize the calling CPU's compare interrupt as clockevent device > */ > -#ifdef CONFIG_CEVT_R4K > -extern int mips_clockevent_init(void); > +#ifdef CONFIG_CEVT_R4K_LIB > extern unsigned int __weak get_c0_compare_int(void); > -#else > +extern int r4k_clockevent_init(void); > +#endif > + > static inline int mips_clockevent_init(void) > { > +#ifdef CONFIG_CEVT_R4K > + return r4k_clockevent_init(); > +#else > return -ENXIO; > -} > #endif > +} > > /* > * Initialize the count register as a clocksource > */ > -#ifdef CONFIG_CEVT_R4K > -extern int init_mips_clocksource(void); > -#else > +#ifdef CONFIG_CSRC_R4K_LIB > +extern int init_r4k_clocksource(void); > +#endif > Hm, does it make sense to hedge ''extern' declaration by #ifdef's? WBR, Sergei From m.jancar@satca.net Mon Jun 2 13:07:36 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Jun 2008 13:07:38 +0100 (BST) Received: from p549F5CCF.dip.t-dialin.net ([84.159.92.207]:63632 "EHLO p549F5CCF.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20022163AbYFBMHg (ORCPT ); Mon, 2 Jun 2008 13:07:36 +0100 Received: from skerikoff.satca.net ([81.90.243.194]:61401 "EHLO smtp.satca.net") by lappi.linux-mips.net with ESMTP id S525904AbYFBLwC (ORCPT ); Mon, 2 Jun 2008 13:52:02 +0200 Received: from localhost (unknown [127.0.0.1]) by smtp.satca.net (Postfix) with ESMTP id F0F92E418E7; Mon, 2 Jun 2008 10:28:53 +0000 (UTC) X-Virus-Scanned: amavisd-new at satca.net Received: from smtp.satca.net ([127.0.0.1]) by localhost (skerikoff.satca.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Uyv-Ac8CyG26; Mon, 2 Jun 2008 12:28:49 +0200 (CEST) Received: from [192.168.51.201] (unknown [192.168.51.201]) by smtp.satca.net (Postfix) with ESMTP id 4BBB3E41089; Mon, 2 Jun 2008 10:28:49 +0000 (UTC) Message-ID: <4843DEFD.9020303@satca.net> Date: Mon, 02 Jun 2008 13:52:29 +0200 From: Marian Jancar User-Agent: Thunderbird 2.0.0.5 (X11/20070719) MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: [PATCH 5/7] gcov: add gcov profiling infrastructure References: <48313DE6.30802@de.ibm.com> <20080523001136.59ec8b34.akpm@linux-foundation.org> <20080523084506.GB719@linux-mips.org> In-Reply-To: <20080523084506.GB719@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.jancar@satca.net Precedence: bulk X-list: linux-mips Ralf Baechle wrote: >> {standard input}: Assembler messages: >> {standard input}:2716: Error: Branch out of range >> {standard input}:2819: Error: Branch out of range >> {standard input}:2884: Error: Branch out of range >> {standard input}:3032: Error: Branch out of range >> {standard input}:3097: Error: Branch out of range >> {standard input}:3151: Error: Branch out of range >> {standard input}:3216: Error: Branch out of range >> make[1]: *** [drivers/telephony/ixj.o] Error 1 >> make: *** [drivers/telephony/ixj.o] Error 2 > > A known problem which I had decieded to ignore until it begins to actually > bite. It's triggered by something like this > > __asm__ __volatile__( > " .set mips3 \n" > "1: ll %0, %1 # atomic_add \n" > " addu %0, %2 \n" > " sc %0, %1 \n" > " beqz %0, 2f \n" > " .subsection 2 \n" > "2: b 1b \n" > " .previous \n" > " .set mips0 \n" > : "=&r" (temp), "=m" (v->counter) > : "Ir" (i), "m" (v->counter)); > > when compiled into a large compilation unit. Please unignore :) It bites when compiling madwifi (without profiling or anything such). Marian From dmitri.vorobiev@gmail.com Mon Jun 2 17:07:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Jun 2008 17:07:49 +0100 (BST) Received: from p549F5CCF.dip.t-dialin.net ([84.159.92.207]:38583 "EHLO p549F5CCF.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20021677AbYFBQHr (ORCPT ); Mon, 2 Jun 2008 17:07:47 +0100 Received: from yx-out-1718.google.com ([74.125.44.155]:51528 "EHLO yx-out-1718.google.com") by lappi.linux-mips.net with ESMTP id S525977AbYFBQGI (ORCPT ); Mon, 2 Jun 2008 18:06:08 +0200 Received: by yx-out-1718.google.com with SMTP id 36so74630yxh.24 for ; Mon, 02 Jun 2008 09:05:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; bh=PVaRdja2mkx32MMyluimCzLHxRHHYxW3TBjgtP3Vro4=; b=pqcJIEtZkul3OnPZGmS63oFubYOCB8zeKzARs7oc1eadDdCQ3NMcPvaj59/0EtYldRy+ER3xeQpY3FxfLsQU95XNBpGaTB763UQJiuo/5xDj49Ezn2TMQaEBYZ8SCElDc1xftDzkQZWqpi4eoBATncWQaFH+WsDkfdCz3g5kzsI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=R6s2WQK7WH/I8wucKhxrLhLRVF5X/20ilTT39MMOvI33v4BLVImEEd2M0RxEYc3zaNh0TD4jIaxmfRjCnbug57AwgAk4KPpfbJ/UGnRUoF6hKU2sECfI77nhApCqGzi/Kg1aAnwtbDQTCpACLFTTsyFfVLOB12jHI9YcqhNwtdg= Received: by 10.151.155.21 with SMTP id h21mr4663643ybo.142.1212421217947; Mon, 02 Jun 2008 08:40:17 -0700 (PDT) Received: by 10.150.140.6 with HTTP; Mon, 2 Jun 2008 08:40:17 -0700 (PDT) Message-ID: <90edad820806020840m2e9f5588x81f8c387aef23c6c@mail.gmail.com> Date: Mon, 2 Jun 2008 18:40:17 +0300 From: "Dmitri Vorobiev" To: "Thomas Bogendoerfer" Subject: Re: Malta build errors with 2.6.26-rc1 Cc: "Martin Michlmayr" , linux-mips@linux-mips.org, ralf@linux-mips.org In-Reply-To: <20080529200506.GA27783@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20080512163107.GA19052@deprecation.cyrius.com> <90edad820805121246o328d1cdaide88594ce9d328b7@mail.gmail.com> <20080528071240.GB10393@deprecation.cyrius.com> <20080528085033.GA6250@alpha.franken.de> <20080528151025.GA15325@deprecation.cyrius.com> <20080529200506.GA27783@alpha.franken.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips 2008/5/29 Thomas Bogendoerfer : > On Wed, May 28, 2008 at 05:10:25PM +0200, Martin Michlmayr wrote: >> * Thomas Bogendoerfer [2008-05-28 10:50]: >> > I didn't fix the problems above. The change to traps.c only fixes >> > traps.c for 64bit builds and it's a totally different issue. Looking >> > at the warning/errors someone needs to fix some data types and use >> > CKSEG0ADDR(). I don't have the hardware, so I could only provide an >> > untested patch, if no one else steps forward... >> >> QEMU emulates Malta, so I (or someone else here) should be able to >> test the patch. > > > Fix 64bit Malta by using CKSEG0ADDR and correct casts > > Signed-off-by: Thomas Bogendoerfer > --- > > arch/mips/mips-boards/generic/amon.c | 4 ++-- > include/asm-mips/gic.h | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/mips/mips-boards/generic/amon.c b/arch/mips/mips-boards/generic/amon.c > index b7633fd..96236bf 100644 > --- a/arch/mips/mips-boards/generic/amon.c > +++ b/arch/mips/mips-boards/generic/amon.c > @@ -28,7 +28,7 @@ > > int amon_cpu_avail(int cpu) > { > - struct cpulaunch *launch = (struct cpulaunch *)KSEG0ADDR(CPULAUNCH); > + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); > > if (cpu < 0 || cpu >= NCPULAUNCH) { > pr_debug("avail: cpu%d is out of range\n", cpu); > @@ -53,7 +53,7 @@ void amon_cpu_start(int cpu, > unsigned long gp, unsigned long a0) > { > volatile struct cpulaunch *launch = > - (struct cpulaunch *)KSEG0ADDR(CPULAUNCH); > + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); > > if (!amon_cpu_avail(cpu)) > return; > diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h > index 3a492f2..954807d 100644 > --- a/include/asm-mips/gic.h > +++ b/include/asm-mips/gic.h > @@ -24,8 +24,8 @@ > > #define MSK(n) ((1 << (n)) - 1) > #define REG32(addr) (*(volatile unsigned int *) (addr)) > -#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS) > -#define REGP(base, phys) REG32((unsigned int)(base) + (phys)) > +#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS) > +#define REGP(base, phys) REG32((unsigned long)(base) + (phys)) > > /* Accessors */ > #define GIC_REG(segment, offset) \ My test was performed using a Malta 4Kc board. I was able to boot the target up to the shell prompt with this patch applied to the current Linus tree. So, you might want to add Tested-by: Dmitri Vorobiev From dmitri.vorobiev@gmail.com Tue Jun 3 08:07:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Jun 2008 08:07:40 +0100 (BST) Received: from p549F5460.dip.t-dialin.net ([84.159.84.96]:8578 "EHLO p549F5460.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20022386AbYFCHHh (ORCPT ); Tue, 3 Jun 2008 08:07:37 +0100 Received: from yw-out-1718.google.com ([74.125.46.156]:48301 "EHLO yw-out-1718.google.com") by lappi.linux-mips.net with ESMTP id S526979AbYFCGp4 (ORCPT ); Tue, 3 Jun 2008 08:45:56 +0200 Received: by yw-out-1718.google.com with SMTP id 9so590008ywk.24 for ; Mon, 02 Jun 2008 23:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; bh=HUh9VzF+W9Owg4wWpAWeWM/7NkysXXf/LPIZvTMGGKo=; b=Ig5Io+0azmnHODlHiTV5cHmMLibrmwtLE8y1YgpzAVXlu6i4zraZyQBt0FYbr+RzSXKjJKeF+aol3ITEKyfztHEryDhCI1OSisMMpP92PJfB09LWS77cTcDM0CYrsOjHThWK0jH5reLDIko//gWXxA6HiEZE1uX3elsQyn++Oqw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=vDgr1bG1B3WIvFOT9WfWkz+GS/rbBg8yC4rnuTmTFwYvkXMl2W8RkoPKs/VfG/Ho+VZuTvwGItyR2h8GnmSYEPCcYKoMYzqjP70fnQ/8FdX23sCIybv1GGINjqyGn5ntqS/dfUY8Hmmg35A2Ers4wVluQedkAG50VcZJ6w4ou80= Received: by 10.151.145.17 with SMTP id x17mr2001074ybn.20.1212475509161; Mon, 02 Jun 2008 23:45:09 -0700 (PDT) Received: by 10.150.140.6 with HTTP; Mon, 2 Jun 2008 23:45:08 -0700 (PDT) Message-ID: <90edad820806022345g6383e5b3hf2d0e73eed3e375e@mail.gmail.com> Date: Tue, 3 Jun 2008 09:45:08 +0300 From: "Dmitri Vorobiev" To: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: email does not get through to linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips Hi Ralf, When I send mail to linux-mips at linux-mips dot org from one of my mail accounts (located in the domain movial dot fi), my emails apparently do not get through. I do not see the messages in the Web archive, neither do I receive these messages in my Gmail account, which is also subscribed to the linux-mips mailing list. I tried sending messages using both Thunderbird and Git. Messages did not arrive in both cases. Will you please check what's going on? I suspect that other users of the mailing list could experience similar problems, and that is why I'm Cc:ing the mailing list itself now. Thanks, Dmitri Vorobiev From ralf@linux-mips.org Tue Jun 3 11:33:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Jun 2008 11:33:40 +0100 (BST) Received: from p549F5460.dip.t-dialin.net ([84.159.84.96]:8578 "EHLO p549F5460.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20030694AbYFCKdh (ORCPT ); Tue, 3 Jun 2008 11:33:37 +0100 Received: from vigor.karmaclothing.net ([217.169.26.28]:46261 "EHLO vigor.karmaclothing.net") by lappi.linux-mips.net with ESMTP id S527010AbYFCI1X (ORCPT ); Tue, 3 Jun 2008 10:27:23 +0200 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m538QrGr001314; Tue, 3 Jun 2008 09:26:53 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m538Qq49001313; Tue, 3 Jun 2008 09:26:52 +0100 Date: Tue, 3 Jun 2008 09:26:52 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: email does not get through to linux-mips.org Message-ID: <20080603082652.GB27478@linux-mips.org> References: <90edad820806022345g6383e5b3hf2d0e73eed3e375e@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <90edad820806022345g6383e5b3hf2d0e73eed3e375e@mail.gmail.com> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 03, 2008 at 09:45:08AM +0300, Dmitri Vorobiev wrote: > When I send mail to linux-mips at linux-mips dot org from one of my > mail accounts (located in the domain movial dot fi), my emails > apparently do not get through. I do not see the messages in the Web > archive, neither do I receive these messages in my Gmail account, > which is also subscribed to the linux-mips mailing list. > > I tried sending messages using both Thunderbird and Git. Messages did > not arrive in both cases. > > Will you please check what's going on? I suspect that other users of > the mailing list could experience similar problems, and that is why > I'm Cc:ing the mailing list itself now. Unfortunately I'm aware of the problem. Since a few days a packet raping machine otherwise known as Cisco PIX is molesting conectivity of linux-mips.org resuling in SMTP sessions with some hosts to fail. To keep the show running I installed a temporary workaround. The email which you forwarded me in private got lost in the spam filter as a side effect of an attempted workaround for above problem, so I'm now going to engineer something better. Ralf From dmitri.vorobiev@gmail.com Tue Jun 3 12:02:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Jun 2008 12:02:36 +0100 (BST) Received: from p549F5460.dip.t-dialin.net ([84.159.84.96]:8578 "EHLO p549F5460.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20031462AbYFCLCd (ORCPT ); Tue, 3 Jun 2008 12:02:33 +0100 Received: from yw-out-1718.google.com ([74.125.46.157]:24494 "EHLO yw-out-1718.google.com") by lappi.linux-mips.net with ESMTP id S527144AbYFCIj3 (ORCPT ); Tue, 3 Jun 2008 10:39:29 +0200 Received: by yw-out-1718.google.com with SMTP id 9so604272ywk.24 for ; Tue, 03 Jun 2008 01:38:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; bh=wpE3Jak1lMhMl5hLgogLX2umKsR/sorZKVk4iX9Sk5s=; b=f47c5TKoUK2ueTGtf1LE+VL3JbJjOYVmTh0pWIf/mVsSZSpTSmu6XioIK6rxN9C0cciTRAhZ9geXtB54GiGfpYwknRcZVlmxB829u88t7WHjApXn19iM1hcfxOYRiQ+en23UMLBKzilxBeHymX+G+xZ4AJ80NAA8NdWW44FWwFw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=gaEnFOqGsIDnXt+JaI3dhD6V0rJNTeGic2wNDceMZl2IyVLt9M9dM6YvLCnkt7lMyNv5I1B1z3wtXPYJvGMWsAFeQGVaMRANpzsI6wzHcXVyatv7QCegMoqHLLXR/dIUKdD5HdwX/BdM5TiYSetdFjU/0ju6ZZKIlmKlvEMZ9bQ= Received: by 10.151.158.2 with SMTP id k2mr583176ybo.70.1212482299775; Tue, 03 Jun 2008 01:38:19 -0700 (PDT) Received: by 10.150.140.6 with HTTP; Tue, 3 Jun 2008 01:38:19 -0700 (PDT) Message-ID: <90edad820806030138x7837f69exbf3362470ca0021c@mail.gmail.com> Date: Tue, 3 Jun 2008 11:38:19 +0300 From: "Dmitri Vorobiev" To: "Thomas Bogendoerfer" Subject: Re: Malta build errors with 2.6.26-rc1 Cc: "Martin Michlmayr" , linux-mips@linux-mips.org, ralf@linux-mips.org In-Reply-To: <90edad820806020840m2e9f5588x81f8c387aef23c6c@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20080512163107.GA19052@deprecation.cyrius.com> <90edad820805121246o328d1cdaide88594ce9d328b7@mail.gmail.com> <20080528071240.GB10393@deprecation.cyrius.com> <20080528085033.GA6250@alpha.franken.de> <20080528151025.GA15325@deprecation.cyrius.com> <20080529200506.GA27783@alpha.franken.de> <90edad820806020840m2e9f5588x81f8c387aef23c6c@mail.gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips > > So, you might want to add > > Tested-by: Dmitri Vorobiev Ouch, I made a typo. Corrected version: Tested-by: Dmitri Vorobiev P.S. Sorry for a duplicate post, but we're currently having some problems with email at linux-mips.org... Dmitri > From mano@roarinelk.homelinux.net Tue Jun 3 15:12:12 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Jun 2008 15:12:14 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:33197 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20032857AbYFCOMM (ORCPT ); Tue, 3 Jun 2008 15:12:12 +0100 Received: (qmail 24431 invoked by uid 1000); 3 Jun 2008 16:12:10 +0200 Date: Tue, 3 Jun 2008 16:12:10 +0200 From: Manuel Lauss To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: make r4k clocksource/clockevent usable in other codepaths Message-ID: <20080603141210.GA21501@roarinelk.homelinux.net> References: <20080528122838.GA5976@roarinelk.homelinux.net> <4842E2C0.1020106@ru.mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4842E2C0.1020106@ru.mvista.com> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips hi Sergei, > Manuel Lauss wrote: >> Make the r4k cp0 counter clocksource and clockevent modules >> library code so it may be used e.g. as a fallback in case other >> clocksources/events aren't available. >> >> Signed-off-by: Manuel Lauss >> > [...] > >> diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h >> index d3bd5c5..01a4c93 100644 >> --- a/include/asm-mips/time.h >> +++ b/include/asm-mips/time.h >> @@ -50,27 +50,35 @@ extern int (*perf_irq)(void); >> /* >> * Initialize the calling CPU's compare interrupt as clockevent device >> */ >> -#ifdef CONFIG_CEVT_R4K >> -extern int mips_clockevent_init(void); >> +#ifdef CONFIG_CEVT_R4K_LIB >> extern unsigned int __weak get_c0_compare_int(void); >> -#else >> +extern int r4k_clockevent_init(void); >> +#endif >> + >> static inline int mips_clockevent_init(void) >> { >> +#ifdef CONFIG_CEVT_R4K >> + return r4k_clockevent_init(); >> +#else >> return -ENXIO; >> -} >> #endif >> +} >> /* >> * Initialize the count register as a clocksource >> */ >> -#ifdef CONFIG_CEVT_R4K >> -extern int init_mips_clocksource(void); >> -#else >> +#ifdef CONFIG_CSRC_R4K_LIB >> +extern int init_r4k_clocksource(void); >> +#endif >> > > Hm, does it make sense to hedge ''extern' declaration by #ifdef's? To be honest, I didn't think about that (and I don't know the exact semantics of 'extern' either), I just followed the original code ;-) MfG, Manuel Lauss From bunk@kernel.org Wed Jun 4 17:00:32 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Jun 2008 17:00:34 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:16577 "EHLO p549F73B8.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20038175AbYFDQAc (ORCPT ); Wed, 4 Jun 2008 17:00:32 +0100 Received: from smtp5.pp.htv.fi ([213.243.153.39]:28311 "EHLO smtp5.pp.htv.fi") by lappi.linux-mips.net with ESMTP id S1097866AbYFDQAb (ORCPT ); Wed, 4 Jun 2008 18:00:31 +0200 Received: from cs181133002.pp.htv.fi (cs181133002.pp.htv.fi [82.181.133.2]) by smtp5.pp.htv.fi (Postfix) with ESMTP id 5D65A5BC046; Wed, 4 Jun 2008 19:00:25 +0300 (EEST) Date: Wed, 4 Jun 2008 18:59:51 +0300 From: Adrian Bunk To: Marc St-Jean Cc: linux-mips@linux-mips.org, Brian_Oostenbrink@pmc-sierra.com Subject: Status of PMC MSP71xx support? Message-ID: <20080604155951.GC4189@cs181133002.pp.htv.fi> References: <310540780805210817q177554acof9c5a60129a6a824@mail.gmail.com> <310540780805210834v745502e9i308cbebfe0a0167e@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <310540780805210834v745502e9i308cbebfe0a0167e@mail.gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bunk@kernel.org Precedence: bulk X-list: linux-mips On Wed, May 21, 2008 at 09:34:35AM -0600, Marc St-Jean wrote: > Hi Adrian, Hi Marc, > It did compile with all patches, but at the time I moved on from PMC, > several drivers patches needed more work and had not yet been accepted > in the upstream kernel tree. > > The contact at PMC that took over the work was Brian Oostenbrink, I'm > forwarding this so he can answer you question. thanks for this information. Brian, are you or someone else working on getting all required stuff for making it usable into the kernel in the forseeable future? In the current state what is shipped in the kernel tree is useless and a good candidate for removal. > Marc cu Adrian -- "Is there not promise of rain?" Ling Tan asked suddenly out of the darkness. There had been need of rain for many days. "Only a promise," Lao Er said. Pearl S. Buck - Dragon Seed From Rod_Sillett@pmc-sierra.com Thu Jun 5 02:35:58 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 02:36:00 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:2222 "EHLO bby1mta03.pmc-sierra.bc.ca") by ftp.linux-mips.org with ESMTP id S20021633AbYFEBf6 convert rfc822-to-8bit (ORCPT ); Thu, 5 Jun 2008 02:35:58 +0100 Received: from bby1mta03.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id 23FE510713A7; Wed, 4 Jun 2008 18:37:32 -0700 (PDT) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (BBY1EXG02.pmc-sierra.bc.ca [216.241.231.167]) by bby1mta03.pmc-sierra.bc.ca (Postfix) with SMTP id ED26410713DF; Wed, 4 Jun 2008 18:37:31 -0700 (PDT) Received: from BBY1EXM09.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.157]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.3959); Wed, 4 Jun 2008 18:36:12 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 8BIT Subject: RE: Status of PMC MSP71xx support? Date: Wed, 4 Jun 2008 18:35:08 -0700 Message-ID: <92F38F1DC286C7409E29F0C6FBFB6E4F0134B636@BBY1EXM09.pmc_nt.nt.pmc-sierra.bc.ca> In-Reply-To: <8A9D56C5E50F774BABE033F1710B35760138FF57@BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Status of PMC MSP71xx support? Thread-Index: AcjGXDI8bKZ0Up11QmqlnFytGPSKmQAA6eagABK41GA= References: <8A9D56C5E50F774BABE033F1710B35760138FF57@BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca> From: "Rod Sillett" To: Cc: "Brian Oostenbrink" , X-OriginalArrivalTime: 05 Jun 2008 01:36:12.0996 (UTC) FILETIME=[89E10840:01C8C6AC] X-PMX-Version: 5.4.2.338381, Antispam-Engine: 2.6.0.325393, Antispam-Data: 2008.6.4.181942 X-PMC-SpamCheck: Gauge=IIIIIII, Probability=7%, Report='BODY_SIZE_1000_LESS 0, BODY_SIZE_300_399 0, BODY_SIZE_5000_LESS 0, __BOUNCE_CHALLENGE_SUBJ 0, __CT 0, __CTE 0, __CT_TEXT_PLAIN 0, __HAS_MSGID 0, __IMS_MSGID 0, __MIME_TEXT_ONLY 0, __MIME_VERSION 0, __SANE_MSGID 0' Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19400 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Rod_Sillett@pmc-sierra.com Precedence: bulk X-list: linux-mips Hi Adrian, Yes, the msp71xx platform is still actively supported by PMC. I am responsible for merging the changes back to the community. As a first step (a learning experience for me) I was planning to submit updated GPIO and LED support in the next few weeks. Best Regards, Rod Sillett From chetannanda@gmail.com Thu Jun 5 11:03:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 11:03:28 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:14056 "EHLO ti-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20021862AbYFEKDZ (ORCPT ); Thu, 5 Jun 2008 11:03:25 +0100 Received: by ti-out-0910.google.com with SMTP id i7so152191tid.20 for ; Thu, 05 Jun 2008 03:02:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:mime-version:content-type:content-transfer-encoding :content-disposition; bh=YVVvVbAjpysHLwtKLqpRAYDXH17e/Z/OchQz59UNc0Y=; b=JYhLPQX1sVbxKHM/FVHoidj3r6vYn6GSb/BKeD/XZ+68zozxBQtBT6c6VE/h/QN2LQ g/IEw8LeSrsUlIuxZo3AKrzpUoPO1pYq2c6DOOADpFq2CNm/9Q+CUdERaNo8XK9Wut2p zfLwaUCDN7kscSsLnpQkVEhY+NO1zILGLB8Po= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:mime-version:content-type :content-transfer-encoding:content-disposition; b=u/g7LmSRHc0ZGThd0MA4Cnd1YLn0dFrYlGSpOZxPmy9GkbXNJ/K7+HSkGXKb19yR7l qWzh0pU5vXkCKY1F6ghJ2Z+RgCVCiMMsfpRKxx4EdvPIraIhGrhsdNpIYqTqI3gMzZdH KFPErGxm2tS8Ta+tTmhTToAc82D4TjNYk/cFk= Received: by 10.110.15.9 with SMTP id 9mr333229tio.44.1212660162689; Thu, 05 Jun 2008 03:02:42 -0700 (PDT) Received: by 10.110.11.2 with HTTP; Thu, 5 Jun 2008 03:02:42 -0700 (PDT) Message-ID: <7f245da80806050302m6b449e6m1f84dc7ef7efff46@mail.gmail.com> Date: Thu, 5 Jun 2008 15:32:42 +0530 From: "Chetan Nanda" To: linux-mips@linux-mips.org Subject: understanding head.S MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19401 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chetannanda@gmail.com Precedence: bulk X-list: linux-mips Hi All, I was reading the boot code for MIPS. in head.S file before jumping to 'start_kernel' it calculate the stack pointer address as follow: " PTR_LA $28, init_thread_union PTR_ADDIU sp, $28, _THREAD_SIZE - 32 set_saved_sp sp, t0, t1 PTR_SUBU sp, 4 * SZREG # init stack pointer " Can anyone please explains me this 4 lines of code? Why ' _THREAD_SIZE - 32' is added in 'sp' ? What 'set_saved_sp' will do ? and then why we subtract '4 * SZREG' from 'sp' ? Please hep me to understand this code better. Thanks, Chetan Nanda From tbm@cyrius.com Thu Jun 5 12:12:05 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 12:12:07 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:41888 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S20022077AbYFELMF (ORCPT ); Thu, 5 Jun 2008 12:12:05 +0100 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 55396D8DD; Thu, 5 Jun 2008 11:12:03 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 1B785150F70; Thu, 5 Jun 2008 13:11:49 +0200 (CEST) Date: Thu, 5 Jun 2008 13:11:48 +0200 From: Martin Michlmayr To: Ralf Baechle Cc: Dmitri Vorobiev , Theodore Tso , linux-mips@linux-mips.org, linux-ext4@vger.kernel.org Subject: Re: ext4dev build failure on mips: "empty_zero_page" undefined Message-ID: <20080605111148.GA4483@deprecation.cyrius.com> References: <20080512130604.GA15008@deprecation.cyrius.com> <90edad820805120654n50f7a00cm3c7b4a4f9346d5ea@mail.gmail.com> <20080512143426.GB7029@mit.edu> <90edad820805120746l61e67362vbd177d63e8b05dc8@mail.gmail.com> <20080513045028.GC22226@linux-mips.org> <20080528070637.GA10393@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080528070637.GA10393@deprecation.cyrius.com> User-Agent: Mutt/1.5.17+20080114 (2008-01-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-m