From rdsandiford@googlemail.com Sun Jun 1 15:16:16 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Jun 2008 15:16:21 +0100 (BST) Received: from p549F48FC.dip.t-dialin.net ([84.159.72.252]:46557 "EHLO p549F48FC.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20024082AbYFAOQQ (ORCPT ); Sun, 1 Jun 2008 15:16:16 +0100 Received: from nf-out-0910.google.com ([64.233.182.190]:17982 "EHLO nf-out-0910.google.com") by lappi.linux-mips.net with ESMTP id S525092AbYFANsi (ORCPT ); Sun, 1 Jun 2008 15:48:38 +0200 Received: by nf-out-0910.google.com with SMTP id h3so255793nfh.14 for ; Sun, 01 Jun 2008 06:48:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:mail-followup-to:cc:subject:references:date:in-reply-to:message-id:user-agent:mime-version:content-type; bh=wQ9vm4lyOa0FwB3vbUSXt7M3H3FKPmMrM8RaH8p6ls0=; b=ntrGWNHjrClrq+zPWo11fO9xFxZbIg/zmLRDRnJtbQTXz1XsXI4q2huhVG5tqnEXXQMaYNPCqCPLiYNu64EjbSwmaFtOkeF9e02cuzg3RaXAtpDMSQeEpejZuo3qOdQgYtbOg9pkrfb63+Sn9dUe6AMZDqnfK3TqoGIR6tg17NY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:mail-followup-to:cc:subject:references:date:in-reply-to:message-id:user-agent:mime-version:content-type; b=j/2msfeVfv/5kYMKufrf7PAGhu5nA9e5BnBxrDXZoONr557oyAonbv4E6ACCVIRUd82Eig3CvwqKTnNR2kMMT6IpSNzpeQEPU70LWKVxVxWk3PomKN2QVrhKVzSJJRiJb8r4Dt5qE8SdoT9ugn6pH+0abgUJaunUz8gULi3sKAQ= Received: by 10.210.58.17 with SMTP id g17mr3408365eba.190.1212328095771; Sun, 01 Jun 2008 06:48:15 -0700 (PDT) Received: from localhost ( [79.67.7.203]) by mx.google.com with ESMTPS id g9sm3883073gvc.0.2008.06.01.06.48.10 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 01 Jun 2008 06:48:13 -0700 (PDT) From: Richard Sandiford To: "Maciej W. Rozycki" Mail-Followup-To: "Maciej W. Rozycki" ,Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Cc: Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org Subject: Re: Changing the treatment of the MIPS HI and LO registers References: <87tzgj4nh6.fsf@firetop.home> <87abib4d9t.fsf@firetop.home> <87r6bm1ebd.fsf@firetop.home> <878wxtvarg.fsf@firetop.home> Date: Sun, 01 Jun 2008 14:48:08 +0100 In-Reply-To: <878wxtvarg.fsf@firetop.home> (Richard Sandiford's message of "Thu\, 29 May 2008 08\:18\:27 +0100") Message-ID: <8763stz2p3.fsf@firetop.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19390 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rdsandiford@googlemail.com Precedence: bulk X-list: linux-mips This thread seems to have stagnated (if a thread can stagnate). Maciej said: > OK, it is good to have a way to make use of some TImode functionality > 64-bit hardware provides, but it still does not provide a clean solution > to the compatibility problem seen here. While a construct like: > > #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4) > [new wonderful TImode stuff] > #else > [old compatibility asm crap] > #endif > > will certainly work, it is as ugly as you can get. I am not sure I would > be happy to see it in Linux, though obviously Ralf and the others may > disagree. but TBH, I don't see why it's so ugly. I imagine the definitions of int128_t and uint128_t (or whatever you decide to call them) would use the condition above. Then there'd be a macro to say whether the TImode stuff is available. I.e.: #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4) typedef ... int128_t ...; typedef ... uint128_t ...; #define WE_HAVE_TIMODE 1 /* replace with a good name */ #endif So there'd only be one copy of the __GNUC__ check. The uses would simply be: #if WE_HAVE_TIMODE ... #else ... #endif That seems no worse than the kind of preprocessor condition you find all over the Linux source. Of course, the other alternative is simply to put the mfhi in the asm itself. While using "h" should in theory produce slightly better code, the difference is probably marginal (or at least accidental) in practice. GCC doesn't know that the asm performs a multiplication or division, so it isn't necessarily going to defer the mfhi for as long as you might like. (Better scheduling is of course another reason why the TImode version ought to be better. A third reason is that it would allow the compiler to constant-fold the result for constant delays periods; as the comment says, this currently only happens for the initialisation of usecs, not the multiplication itself.) I've attached an updated patch below. Differences from the last time are: - I've fixed the movti patterns for MIPS16. - I've added -mfix-r4000 support to the new TImode patterns. Also, now that the highpart patterns store directly into a GPR, it's easy to extend them to -mfix-r4000 too. - I've added a load of -mfix-r4000 tests. - I've added the promised TImode testcases. They cover addition, subtraction and logic as well as multiplication: - timode-1.c makes sure that everything is open-coded - timode-2.c makes sure that execution succeeds - int-moves-[12].c shadow the movtf tests I added earlier today Tested on mips64el-linux-gnu and mipsisa64-elfoabi. I'll reinstate the 48 hour warning, mostly as a way of seeing whether the thread is still alive. I don't think my last message made it through to linux-mips@. If this one does, and you're wanting some context, the discussion started here: http://gcc.gnu.org/ml/gcc-patches/2008-05/msg01750.html Basically, I'm trying to fix a wrong-code problem that would become especially dangerous with GCC's new register allocator. The only acceptable way I can see of doing it involves removing support for the asm "h" constraint. ("hi" would still be supported in clobber lists.) Richard gcc/ * doc/md.texi: Synchronize with later constraints.md change. * longlong.h (umul_ppmm): Replace the MIPS asm implementation with a C implementation. * config/mips/mips.c (mips_legitimize_move): Remove MFHI and MFLO handling. (mips_subword): Assume TImode for CONST_INTs if TARGET_64BIT. (mips_split_doubleword_move): Use special MTHI and MFHI instructions when moving to and from MD_REGNUM. (mips_output_move): Don't handle moves from GPRs to HI_REGNUM. Handle moves from LO_REGNUM to GPRs using MFLO, MACC or DMACC. Handle byte and halfword moves. (mips_hard_regno_mode_ok_p): Handle MD_REGS and DSP_ACC_REGS separately. * config/mips/constraints.md (h): Turn into NO_REGS. (l, x): Update documentation. * config/mips/mips.md (UNSPEC_MFHILO): Delete. (UNSPEC_MFHI, UNSPEC_MTHI, UNSPEC_SET_HILO): New. (UNSPEC_TLS_LDM, UNSPEC_TLS_GET_TP): Renumber. (HILO): New mode iterator. (MOVE128): Add TI. (any_div): New code iterator. (u): Extend code attribute to div and udiv. (*add3_mips16, *movdi_64bit_mips16, *movsi_mips16): Use d_operand in the splitters. Remove redundant CONST_INT checks. (mulsi3_mult3, mul3_internal, mul3_r4000, *mul_acc_si) (*macc, *msac, *msac_using_macc, *macc2, *msac2, *mul_sub_si) (*muls): Remove "=h" clobbers. Adjust peephole2s and define_splits accordingly, using normal moves instead of unspecs to move LO into a GPR. Use d_operand and lo_operand instead of *_REG_P checks. (mulsidi3): Handle expansion in C code. (mulsidi3_32bit_internal): Rename to... (mulsidi3_32bit): ...this. (mulsidi3_32bit_r4000): Fix insn separator. (*mulsidi3_64bit): Rename to... (mulsidi3_64bit): ...this. Combine DImode "=h" and "=l" clobbers into a TImode "=x" clobber. In the split, use an UNSPEC_SET_HILO to set LO and HI to the multiplication result. Use a normal move for MFLO and an unspec for MFHI. (*mulsidi3_64bit_parts): Replace with... (mulsidi3_64bit_hilo): ...this new instruction. (mulsi3_highpart): Extend to TARGET_FIX_R4000. (mulsi3_highpart_internal): Turn into a define_insn_and_split and extend it to TARGET_FIX_R4000. Store the destination in a GPR instead of HI. Split the instruction into a separate multiplication and MFHI if !TARGET_FIX_R4000. (muldi3_highpart): Likewise. (mulsi3_highpart_mulhi_internal): Remove the first alternative and the "=h" clobber. (*mulsi3_highpart_neg_mulhi_internal): Likewise. (mulditi3): New expander. (mulditi3_internal, mulditi3_r4000): New patterns. (madsi): Remove "=h" clobber. (divmod4, udivmod4): Turn into define_insn_and_splits. Force the modulus result to be a GPR and split the instruction into a division followed by an MFHI after reload. (divmod4_hilo_): New instruction. (*lea_high64): Use d_operand in the define_peephole2. Likewise the MIPS16 HIGH define_split. (*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16): Change type of acc<->gpr moves to "multi". (*movdi_64bit): Replace the single "x" alternative with alternatives for moving into and out of "a". (*movhi_internal, *movqi_internal): Likewise. Use mips_output_move. (*movsi_internal): Extend the "d<-A" alternative to "d<-a". (*movdi_64bit_mips16, *movsi_mips16): Add d<-a alternatives. Use d_operand in the splitters. Remove redundant CONST_INT checks. (*movhi_mips16, *movqi_mips16): Likewise. Use mips_output_move. (movti): New expander. (*movti, *movti_mips16): New insns. (mfhilo_, *mfhilo_, *mfhilo__macc): Delete. (mfhi_): New pattern. (mthi_): Likewise. * config/mips/predicates.md (fpr_operand): Delete. (d_operand): New predicate. gcc/testsuite/ * gcc.dg/torture/mips-hilo-1.c: Delete. * gcc.target/mips/pr35232.c: Likewise. * gcc.target/mips/fix-vr4130-1.c: Use modulus to create an mfhi. * gcc.target/mips/fix-vr4130-3.c: Likewise. * gcc.target/mips/int-moves-1.c: New test. * gcc.target/mips/int-moves-2.c: Likewise. * gcc.target/mips/fix-r4000-1.c: Likewise. * gcc.target/mips/fix-r4000-2.c: Likewise. * gcc.target/mips/fix-r4000-3.c: Likewise. * gcc.target/mips/fix-r4000-4.c: Likewise. * gcc.target/mips/fix-r4000-5.c: Likewise. * gcc.target/mips/fix-r4000-6.c: Likewise. * gcc.target/mips/fix-r4000-7.c: Likewise. * gcc.target/mips/fix-r4000-8.c: Likewise. * gcc.target/mips/fix-r4000-9.c: Likewise. * gcc.target/mips/fix-r4000-10.c: Likewise. * gcc.target/mips/fix-r4000-11.c: Likewise. * gcc.target/mips/fix-r4000-12.c: Likewise. * gcc.target/mips/timode-1.c: Likewise. * gcc.target/mips/timode-2.c: Likewise. Index: gcc/doc/md.texi =================================================================== --- gcc/doc/md.texi 2008-06-01 10:23:31.000000000 +0100 +++ gcc/doc/md.texi 2008-06-01 14:08:13.000000000 +0100 @@ -2498,13 +2498,15 @@ generating MIPS16 code. A floating-point register (if available). @item h -The @code{hi} register. +Formerly the @code{hi} register. This constraint is no longer supported. @item l -The @code{lo} register. +The @code{lo} register. Use this register to store values that are +no bigger than a word. @item x -The @code{hi} and @code{lo} registers. +The concatenated @code{hi} and @code{lo} registers. Use this register +to store doubleword values. @item c A register suitable for use in an indirect jump. This will always be Index: gcc/longlong.h =================================================================== --- gcc/longlong.h 2008-06-01 10:23:31.000000000 +0100 +++ gcc/longlong.h 2008-06-01 14:06:06.000000000 +0100 @@ -623,12 +623,12 @@ #define UDIV_TIME 150 #endif /* __m88000__ */ #if defined (__mips__) && W_TYPE_SIZE == 32 -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("multu %2,%3" \ - : "=l" ((USItype) (w0)), \ - "=h" ((USItype) (w1)) \ - : "d" ((USItype) (u)), \ - "d" ((USItype) (v))) +#define umul_ppmm(w1, w0, u, v) \ + do { \ + UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \ + (w1) = (USItype) (__x >> 32); \ + (w0) = (USItype) (__x); \ + } while (0) #define UMUL_TIME 10 #define UDIV_TIME 100 Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c 2008-06-01 14:01:19.000000000 +0100 +++ gcc/config/mips/mips.c 2008-06-01 14:06:06.000000000 +0100 @@ -2659,23 +2659,6 @@ mips_legitimize_move (enum machine_mode return true; } - /* Check for individual, fully-reloaded mflo and mfhi instructions. */ - if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD - && REG_P (src) && MD_REG_P (REGNO (src)) - && REG_P (dest) && GP_REG_P (REGNO (dest))) - { - int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM; - if (GET_MODE_SIZE (mode) <= 4) - emit_insn (gen_mfhilo_si (gen_lowpart (SImode, dest), - gen_lowpart (SImode, src), - gen_rtx_REG (SImode, other_regno))); - else - emit_insn (gen_mfhilo_di (gen_lowpart (DImode, dest), - gen_lowpart (DImode, src), - gen_rtx_REG (DImode, other_regno))); - return true; - } - /* We need to deal with constants that would be legitimate immediate_operands but aren't legitimate move_operands. */ if (CONSTANT_P (src) && !move_operand (src, mode)) @@ -3472,7 +3455,7 @@ mips_subword (rtx op, bool high_p) mode = GET_MODE (op); if (mode == VOIDmode) - mode = DImode; + mode = TARGET_64BIT ? TImode : DImode; if (TARGET_BIG_ENDIAN ? !high_p : high_p) byte = UNITS_PER_WORD; @@ -3523,6 +3506,8 @@ mips_split_64bit_move_p (rtx dest, rtx s void mips_split_doubleword_move (rtx dest, rtx src) { + rtx low_dest; + if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src)) { if (!TARGET_64BIT && GET_MODE (dest) == DImode) @@ -3536,12 +3521,27 @@ mips_split_doubleword_move (rtx dest, rt else gcc_unreachable (); } + else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST) + { + low_dest = mips_subword (dest, false); + mips_emit_move (low_dest, mips_subword (src, false)); + if (TARGET_64BIT) + emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest)); + else + emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest)); + } + else if (REG_P (src) && REGNO (src) == MD_REG_FIRST) + { + mips_emit_move (mips_subword (dest, false), mips_subword (src, false)); + if (TARGET_64BIT) + emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src)); + else + emit_insn (gen_mfhisi_di (mips_subword (dest, true), src)); + } else { /* The operation can be split into two normal moves. Decide in which order to do them. */ - rtx low_dest; - low_dest = mips_subword (dest, false); if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src)) @@ -3584,8 +3584,9 @@ mips_output_move (rtx dest, rtx src) if (GP_REG_P (REGNO (dest))) return "move\t%0,%z1"; - if (MD_REG_P (REGNO (dest))) - return "mt%0\t%z1"; + /* Moves to HI are handled by special .md insns. */ + if (REGNO (dest) == LO_REGNUM) + return "mtlo\t%z1"; if (DSP_ACC_REG_P (REGNO (dest))) { @@ -3608,14 +3609,29 @@ mips_output_move (rtx dest, rtx src) } } if (dest_code == MEM) - return dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0"; + switch (GET_MODE_SIZE (mode)) + { + case 1: return "sb\t%z1,%0"; + case 2: return "sh\t%z1,%0"; + case 4: return "sw\t%z1,%0"; + case 8: return "sd\t%z1,%0"; + } } if (dest_code == REG && GP_REG_P (REGNO (dest))) { if (src_code == REG) { - /* Handled by separate patterns. */ - gcc_assert (!MD_REG_P (REGNO (src))); + /* Moves from HI are handled by special .md insns. */ + if (REGNO (src) == LO_REGNUM) + { + /* When generating VR4120 or VR4130 code, we use MACC and + DMACC instead of MFLO. This avoids both the normal + MIPS III HI/LO hazards and the errata related to + -mfix-vr4130. */ + if (ISA_HAS_MACCHI) + return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%."; + return "mflo\t%0"; + } if (DSP_ACC_REG_P (REGNO (src))) { @@ -3642,7 +3658,13 @@ mips_output_move (rtx dest, rtx src) } if (src_code == MEM) - return dbl_p ? "ld\t%0,%1" : "lw\t%0,%1"; + switch (GET_MODE_SIZE (mode)) + { + case 1: return "lbu\t%0,%1"; + case 2: return "lhu\t%0,%1"; + case 4: return "lw\t%0,%1"; + case 8: return "ld\t%0,%1"; + } if (src_code == CONST_INT) { @@ -8937,13 +8959,30 @@ mips_hard_regno_mode_ok_p (unsigned int if (ACC_REG_P (regno) && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode))) { - if (size <= UNITS_PER_WORD) - return true; + if (MD_REG_P (regno)) + { + /* After a multiplication or division, clobbering HI makes + the value of LO unpredictable, and vice versa. This means + that, for all interesting cases, HI and LO are effectively + a single register. - if (size <= UNITS_PER_WORD * 2) - return (DSP_ACC_REG_P (regno) - ? ((regno - DSP_ACC_REG_FIRST) & 1) == 0 - : regno == MD_REG_FIRST); + We model this by requiring that any value that uses HI + also uses LO. */ + if (size <= UNITS_PER_WORD * 2) + return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST); + } + else + { + /* DSP accumulators do not have the same restrictions as + HI and LO, so we can treat them as normal doubleword + registers. */ + if (size <= UNITS_PER_WORD) + return true; + + if (size <= UNITS_PER_WORD * 2 + && ((regno - DSP_ACC_REG_FIRST) & 1) == 0) + return true; + } } if (ALL_COP_REG_P (regno)) Index: gcc/config/mips/constraints.md =================================================================== --- gcc/config/mips/constraints.md 2008-06-01 10:23:31.000000000 +0100 +++ gcc/config/mips/constraints.md 2008-06-01 14:07:37.000000000 +0100 @@ -29,14 +29,16 @@ (define_register_constraint "t" "T_REG" (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" "A floating-point register (if available).") -(define_register_constraint "h" "TARGET_BIG_ENDIAN ? MD0_REG : MD1_REG" - "The @code{hi} register.") +(define_register_constraint "h" "NO_REGS" + "Formerly the @code{hi} register. This constraint is no longer supported.") (define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG" - "The @code{lo} register.") + "The @code{lo} register. Use this register to store values that are + no bigger than a word.") (define_register_constraint "x" "MD_REGS" - "The @code{hi} and @code{lo} registers.") + "The concatenated @code{hi} and @code{lo} registers. Use this register + to store doubleword values.") (define_register_constraint "b" "ALL_REGS" "@internal") Index: gcc/config/mips/mips.md =================================================================== --- gcc/config/mips/mips.md 2008-06-01 14:01:19.000000000 +0100 +++ gcc/config/mips/mips.md 2008-06-01 14:16:33.000000000 +0100 @@ -44,9 +44,11 @@ (define_constants (UNSPEC_LOAD_CALL 23) (UNSPEC_LOAD_GOT 24) (UNSPEC_GP 25) - (UNSPEC_MFHILO 26) - (UNSPEC_TLS_LDM 27) - (UNSPEC_TLS_GET_TP 28) + (UNSPEC_MFHI 26) + (UNSPEC_MTHI 27) + (UNSPEC_SET_HILO 28) + (UNSPEC_TLS_LDM 29) + (UNSPEC_TLS_GET_TP 30) (UNSPEC_MFHC1 31) (UNSPEC_MTHC1 32) (UNSPEC_CLEAR_HAZARD 33) @@ -484,6 +486,10 @@ (define_mode_iterator GPR [SI (DI "TARGE ;; modes. (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) +;; This mode iterator allows :HILO to be used as the mode of the +;; concatenated HI and LO registers. +(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")]) + ;; This mode iterator allows :P to be used for patterns that operate on ;; pointer-sized quantities. Exactly one of the two alternatives will match. (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) @@ -497,7 +503,7 @@ (define_mode_iterator MOVE64 [DI DF (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")]) ;; 128-bit modes for which we provide move patterns on 64-bit targets. -(define_mode_iterator MOVE128 [TF]) +(define_mode_iterator MOVE128 [TI TF]) ;; This mode iterator allows the QI and HI extension patterns to be ;; defined from the same template. @@ -613,6 +619,10 @@ (define_code_iterator any_extend [sign_e ;; from the same template. (define_code_iterator any_shift [ashift ashiftrt lshiftrt]) +;; This code iterator allows unsigned and signed division to be generated +;; from the same template. +(define_code_iterator any_div [div udiv]) + ;; This code iterator allows all native floating-point comparisons to be ;; generated from the same template. (define_code_iterator fcond [unordered uneq unlt unle eq lt le]) @@ -631,6 +641,7 @@ (define_code_iterator any_le [le leu]) ;; expands to an empty string when doing a signed operation and ;; "u" when doing an unsigned operation. (define_code_attr u [(sign_extend "") (zero_extend "u") + (div "") (udiv "u") (gt "") (gtu "u") (ge "") (geu "u") (lt "") (ltu "u") @@ -864,13 +875,10 @@ (define_insn "*add3_mips16" ;; simply adding a constant to a register. (define_split - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "d_operand") (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand")))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) > 0x7f && INTVAL (operands[1]) <= 0x7f + 0x7f) || (INTVAL (operands[1]) < - 0x80 @@ -893,16 +901,11 @@ (define_split }) (define_split - [(set (match_operand:SI 0 "register_operand") - (plus:SI (match_operand:SI 1 "register_operand") + [(set (match_operand:SI 0 "d_operand") + (plus:SI (match_operand:SI 1 "d_operand") (match_operand:SI 2 "const_int_operand")))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && REG_P (operands[1]) - && M16_REG_P (REGNO (operands[1])) && REGNO (operands[0]) != REGNO (operands[1]) - && GET_CODE (operands[2]) == CONST_INT && ((INTVAL (operands[2]) > 0x7 && INTVAL (operands[2]) <= 0x7 + 0x7f) || (INTVAL (operands[2]) < - 0x8 @@ -925,13 +928,10 @@ (define_split }) (define_split - [(set (match_operand:DI 0 "register_operand") + [(set (match_operand:DI 0 "d_operand") (plus:DI (match_dup 0) (match_operand:DI 1 "const_int_operand")))] "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) > 0xf && INTVAL (operands[1]) <= 0xf + 0xf) || (INTVAL (operands[1]) < - 0x10 @@ -954,16 +954,11 @@ (define_split }) (define_split - [(set (match_operand:DI 0 "register_operand") - (plus:DI (match_operand:DI 1 "register_operand") + [(set (match_operand:DI 0 "d_operand") + (plus:DI (match_operand:DI 1 "d_operand") (match_operand:DI 2 "const_int_operand")))] "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && REG_P (operands[1]) - && M16_REG_P (REGNO (operands[1])) && REGNO (operands[0]) != REGNO (operands[1]) - && GET_CODE (operands[2]) == CONST_INT && ((INTVAL (operands[2]) > 0x7 && INTVAL (operands[2]) <= 0x7 + 0xf) || (INTVAL (operands[2]) < - 0x8 @@ -1174,8 +1169,7 @@ (define_insn "mulsi3_mult3" [(set (match_operand:SI 0 "register_operand" "=d,l") (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d"))) - (clobber (match_scratch:SI 3 "=h,h")) - (clobber (match_scratch:SI 4 "=l,X"))] + (clobber (match_scratch:SI 3 "=l,X"))] "ISA_HAS_MUL3" { if (which_alternative == 1) @@ -1194,30 +1188,26 @@ (define_insn "mulsi3_mult3" ;; Operand 0: LO ;; Operand 1: GPR (1st multiplication operand) ;; Operand 2: GPR (2nd multiplication operand) -;; Operand 3: HI -;; Operand 4: GPR (destination) +;; Operand 3: GPR (destination) (define_peephole2 [(parallel - [(set (match_operand:SI 0 "register_operand") - (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand"))) - (clobber (match_operand:SI 3 "register_operand")) + [(set (match_operand:SI 0 "lo_operand") + (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand"))) (clobber (scratch:SI))]) - (set (match_operand:SI 4 "register_operand") - (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))] + (set (match_operand:SI 3 "d_operand") + (match_dup 0))] "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])" [(parallel - [(set (match_dup 4) + [(set (match_dup 3) (mult:SI (match_dup 1) (match_dup 2))) - (clobber (match_dup 3)) (clobber (match_dup 0))])]) (define_insn "mul3_internal" [(set (match_operand:GPR 0 "register_operand" "=l") (mult:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "register_operand" "d"))) - (clobber (match_scratch:GPR 3 "=h"))] + (match_operand:GPR 2 "register_operand" "d")))] "!TARGET_FIX_R4000" "mult\t%1,%2" [(set_attr "type" "imul") @@ -1227,8 +1217,7 @@ (define_insn "mul3_r4000" [(set (match_operand:GPR 0 "register_operand" "=d") (mult:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d"))) - (clobber (match_scratch:GPR 3 "=h")) - (clobber (match_scratch:GPR 4 "=l"))] + (clobber (match_scratch:GPR 3 "=l"))] "TARGET_FIX_R4000" "mult\t%1,%2\;mflo\t%0" [(set_attr "type" "imul") @@ -1242,16 +1231,13 @@ (define_insn "mul3_r4000" ;; Operand 0: LO ;; Operand 1: GPR (1st multiplication operand) ;; Operand 2: GPR (2nd multiplication operand) -;; Operand 3: HI -;; Operand 4: GPR (destination) +;; Operand 3: GPR (destination) (define_peephole2 - [(parallel - [(set (match_operand:SI 0 "register_operand") - (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand"))) - (clobber (match_operand:SI 3 "register_operand"))]) - (set (match_operand:SI 4 "register_operand") - (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))] + [(set (match_operand:SI 0 "lo_operand") + (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand"))) + (set (match_operand:SI 3 "d_operand") + (match_dup 0))] "ISA_HAS_MACC && !ISA_HAS_MUL3" [(set (match_dup 0) (const_int 0)) @@ -1260,11 +1246,10 @@ (define_peephole2 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 0))) - (set (match_dup 4) + (set (match_dup 3) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) - (match_dup 0))) - (clobber (match_dup 3))])]) + (match_dup 0)))])]) ;; Multiply-accumulate patterns @@ -1283,9 +1268,8 @@ (define_insn "*mul_acc_si" (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d") (match_operand:SI 2 "register_operand" "d,d,d")) (match_operand:SI 3 "register_operand" "0,l,*d"))) - (clobber (match_scratch:SI 4 "=h,h,h")) - (clobber (match_scratch:SI 5 "=X,3,l")) - (clobber (match_scratch:SI 6 "=X,X,&d"))] + (clobber (match_scratch:SI 4 "=X,3,l")) + (clobber (match_scratch:SI 5 "=X,X,&d"))] "(TARGET_MIPS3900 || GENERATE_MADD_MSUB) && !TARGET_MIPS16" @@ -1301,53 +1285,45 @@ (define_insn "*mul_acc_si" (set_attr "mode" "SI") (set_attr "length" "4,4,8")]) -;; Split the above insn if we failed to get LO allocated. +;; Split *mul_acc_si if both the source and destination accumulator +;; values are GPRs. (define_split - [(set (match_operand:SI 0 "register_operand") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) - (match_operand:SI 3 "register_operand"))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && GP_REG_P (true_regnum (operands[3]))" - [(parallel [(set (match_dup 6) + [(set (match_operand:SI 0 "d_operand") + (plus:SI (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand")) + (match_operand:SI 3 "d_operand"))) + (clobber (match_operand:SI 4 "lo_operand")) + (clobber (match_operand:SI 5 "d_operand"))] + "reload_completed && !TARGET_DEBUG_D_MODE" + [(parallel [(set (match_dup 5) (mult:SI (match_dup 1) (match_dup 2))) - (clobber (match_dup 4)) - (clobber (match_dup 5))]) - (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))] + (clobber (match_dup 4))]) + (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))] "") -;; Splitter to copy result of MADD to a general register +;; Split *mul_acc_si if the destination accumulator value is in a GPR +;; and the source accumulator value is in LO. (define_split - [(set (match_operand:SI 0 "register_operand") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) - (match_operand:SI 3 "register_operand"))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && true_regnum (operands[3]) == LO_REGNUM" + [(set (match_operand:SI 0 "d_operand") + (plus:SI (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand")) + (match_operand:SI 3 "lo_operand"))) + (clobber (match_dup 3)) + (clobber (scratch:SI))] + "reload_completed && !TARGET_DEBUG_D_MODE" [(parallel [(set (match_dup 3) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4)) - (clobber (match_dup 5)) - (clobber (match_dup 6))]) - (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))] - "") + (clobber (scratch:SI)) + (clobber (scratch:SI))]) + (set (match_dup 0) (match_dup 3))]) (define_insn "*macc" [(set (match_operand:SI 0 "register_operand" "=l,d") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d")) (match_operand:SI 3 "register_operand" "0,l"))) - (clobber (match_scratch:SI 4 "=h,h")) - (clobber (match_scratch:SI 5 "=X,3"))] + (clobber (match_scratch:SI 4 "=X,3"))] "ISA_HAS_MACC" { if (which_alternative == 1) @@ -1368,8 +1344,7 @@ (define_insn "*msac" (minus:SI (match_operand:SI 1 "register_operand" "0,l") (mult:SI (match_operand:SI 2 "register_operand" "d,d") (match_operand:SI 3 "register_operand" "d,d")))) - (clobber (match_scratch:SI 4 "=h,h")) - (clobber (match_scratch:SI 5 "=X,1"))] + (clobber (match_scratch:SI 4 "=X,1"))] "ISA_HAS_MSAC" { if (which_alternative == 1) @@ -1388,21 +1363,19 @@ (define_insn_and_split "*msac_using_macc (minus:SI (match_operand:SI 1 "register_operand" "0,l") (mult:SI (match_operand:SI 2 "register_operand" "d,d") (match_operand:SI 3 "register_operand" "d,d")))) - (clobber (match_scratch:SI 4 "=h,h")) - (clobber (match_scratch:SI 5 "=X,1")) - (clobber (match_scratch:SI 6 "=d,d"))] + (clobber (match_scratch:SI 4 "=X,1")) + (clobber (match_scratch:SI 5 "=d,d"))] "ISA_HAS_MACC && !ISA_HAS_MSAC" "#" "&& reload_completed" - [(set (match_dup 6) + [(set (match_dup 5) (neg:SI (match_dup 3))) (parallel [(set (match_dup 0) (plus:SI (mult:SI (match_dup 2) - (match_dup 6)) + (match_dup 5)) (match_dup 1))) - (clobber (match_dup 4)) - (clobber (match_dup 5))])] + (clobber (match_dup 4))])] "" [(set_attr "type" "imadd") (set_attr "length" "8")]) @@ -1417,8 +1390,7 @@ (define_insn "*macc2" (set (match_operand:SI 3 "register_operand" "=d") (plus:SI (mult:SI (match_dup 1) (match_dup 2)) - (match_dup 0))) - (clobber (match_scratch:SI 4 "=h"))] + (match_dup 0)))] "ISA_HAS_MACC && reload_completed" "macc\t%3,%1,%2" [(set_attr "type" "imadd") @@ -1432,8 +1404,7 @@ (define_insn "*msac2" (set (match_operand:SI 3 "register_operand" "=d") (minus:SI (match_dup 0) (mult:SI (match_dup 1) - (match_dup 2)))) - (clobber (match_scratch:SI 4 "=h"))] + (match_dup 2))))] "ISA_HAS_MSAC && reload_completed" "msac\t%3,%1,%2" [(set_attr "type" "imadd") @@ -1444,23 +1415,19 @@ (define_insn "*msac2" ;; ;; Operand 0: LO ;; Operand 1: macc/msac -;; Operand 2: HI -;; Operand 3: GPR (destination) +;; Operand 2: GPR (destination) (define_peephole2 [(parallel - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "lo_operand") (match_operand:SI 1 "macc_msac_operand")) - (clobber (match_operand:SI 2 "register_operand")) (clobber (scratch:SI))]) - (set (match_operand:SI 3 "register_operand") - (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))] + (set (match_operand:SI 2 "d_operand") + (match_dup 0))] "" [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 3) - (match_dup 1)) - (clobber (match_dup 2))])] - "") + (set (match_dup 2) + (match_dup 1))])]) ;; When we have a three-address multiplication instruction, it should ;; be faster to do a separate multiply and add, rather than moving @@ -1474,32 +1441,26 @@ (define_peephole2 ;; Operand 2: GPR (addend) ;; Operand 3: GPR (destination) ;; Operand 4: macc/msac -;; Operand 5: HI -;; Operand 6: new multiplication -;; Operand 7: new addition/subtraction +;; Operand 5: new multiplication +;; Operand 6: new addition/subtraction (define_peephole2 [(match_scratch:SI 0 "d") - (set (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) + (set (match_operand:SI 1 "lo_operand") + (match_operand:SI 2 "d_operand")) (match_dup 0) (parallel - [(set (match_operand:SI 3 "register_operand") + [(set (match_operand:SI 3 "d_operand") (match_operand:SI 4 "macc_msac_operand")) - (clobber (match_operand:SI 5 "register_operand")) (clobber (match_dup 1))])] - "ISA_HAS_MUL3 - && true_regnum (operands[1]) == LO_REGNUM - && peep2_reg_dead_p (2, operands[1]) - && GP_REG_P (true_regnum (operands[3]))" + "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])" [(parallel [(set (match_dup 0) - (match_dup 6)) - (clobber (match_dup 5)) + (match_dup 5)) (clobber (match_dup 1))]) (set (match_dup 3) - (match_dup 7))] + (match_dup 6))] { - operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); - operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, + operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, operands[2], operands[0]); }) @@ -1509,33 +1470,30 @@ (define_peephole2 ;; Operand 1: LO ;; Operand 2: GPR (addend) ;; Operand 3: macc/msac -;; Operand 4: HI -;; Operand 5: GPR (destination) -;; Operand 6: new multiplication -;; Operand 7: new addition/subtraction +;; Operand 4: GPR (destination) +;; Operand 5: new multiplication +;; Operand 6: new addition/subtraction (define_peephole2 [(match_scratch:SI 0 "d") - (set (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) + (set (match_operand:SI 1 "lo_operand") + (match_operand:SI 2 "d_operand")) (match_dup 0) (parallel [(set (match_dup 1) (match_operand:SI 3 "macc_msac_operand")) - (clobber (match_operand:SI 4 "register_operand")) (clobber (scratch:SI))]) (match_dup 0) - (set (match_operand:SI 5 "register_operand") - (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))] + (set (match_operand:SI 4 "d_operand") + (match_dup 1))] "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])" [(parallel [(set (match_dup 0) - (match_dup 6)) - (clobber (match_dup 4)) + (match_dup 5)) (clobber (match_dup 1))]) - (set (match_dup 5) - (match_dup 7))] + (set (match_dup 4) + (match_dup 6))] { - operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); - operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, + operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1); + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, operands[2], operands[0]); }) @@ -1544,9 +1502,8 @@ (define_insn "*mul_sub_si" (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d") (mult:SI (match_operand:SI 2 "register_operand" "d,d,d") (match_operand:SI 3 "register_operand" "d,d,d")))) - (clobber (match_scratch:SI 4 "=h,h,h")) - (clobber (match_scratch:SI 5 "=X,1,l")) - (clobber (match_scratch:SI 6 "=X,X,&d"))] + (clobber (match_scratch:SI 4 "=X,1,l")) + (clobber (match_scratch:SI 5 "=X,X,&d"))] "GENERATE_MADD_MSUB" "@ msub\t%2,%3 @@ -1556,52 +1513,45 @@ (define_insn "*mul_sub_si" (set_attr "mode" "SI") (set_attr "length" "4,8,8")]) -;; Split the above insn if we failed to get LO allocated. +;; Split *mul_sub_si if both the source and destination accumulator +;; values are GPRs. (define_split - [(set (match_operand:SI 0 "register_operand") - (minus:SI (match_operand:SI 1 "register_operand") - (mult:SI (match_operand:SI 2 "register_operand") - (match_operand:SI 3 "register_operand")))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && GP_REG_P (true_regnum (operands[1]))" - [(parallel [(set (match_dup 6) + [(set (match_operand:SI 0 "d_operand") + (minus:SI (match_operand:SI 1 "d_operand") + (mult:SI (match_operand:SI 2 "d_operand") + (match_operand:SI 3 "d_operand")))) + (clobber (match_operand:SI 4 "lo_operand")) + (clobber (match_operand:SI 5 "d_operand"))] + "reload_completed && !TARGET_DEBUG_D_MODE" + [(parallel [(set (match_dup 5) (mult:SI (match_dup 2) (match_dup 3))) - (clobber (match_dup 4)) - (clobber (match_dup 5))]) - (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))] + (clobber (match_dup 4))]) + (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))] "") -;; Splitter to copy result of MSUB to a general register +;; Split *mul_acc_si if the destination accumulator value is in a GPR +;; and the source accumulator value is in LO. (define_split - [(set (match_operand:SI 0 "register_operand") - (minus:SI (match_operand:SI 1 "register_operand") - (mult:SI (match_operand:SI 2 "register_operand") - (match_operand:SI 3 "register_operand")))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && true_regnum (operands[1]) == LO_REGNUM" + [(set (match_operand:SI 0 "d_operand") + (minus:SI (match_operand:SI 1 "lo_operand") + (mult:SI (match_operand:SI 2 "d_operand") + (match_operand:SI 3 "d_operand")))) + (clobber (match_dup 1)) + (clobber (scratch:SI))] + "reload_completed && !TARGET_DEBUG_D_MODE" [(parallel [(set (match_dup 1) (minus:SI (match_dup 1) (mult:SI (match_dup 2) (match_dup 3)))) - (clobber (match_dup 4)) - (clobber (match_dup 5)) - (clobber (match_dup 6))]) - (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))] + (clobber (scratch:SI)) + (clobber (scratch:SI))]) + (set (match_dup 0) (match_dup 1))] "") (define_insn "*muls" - [(set (match_operand:SI 0 "register_operand" "=l,d") + [(set (match_operand:SI 0 "register_operand" "=l,d") (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d")))) - (clobber (match_scratch:SI 3 "=h,h")) - (clobber (match_scratch:SI 4 "=X,l"))] + (clobber (match_scratch:SI 3 "=X,l"))] "ISA_HAS_MULS" "@ muls\t$0,%1,%2 @@ -1609,31 +1559,23 @@ (define_insn "*muls" [(set_attr "type" "imul,imul3") (set_attr "mode" "SI")]) -;; ??? We could define a mulditi3 pattern when TARGET_64BIT. - (define_expand "mulsidi3" - [(parallel - [(set (match_operand:DI 0 "register_operand") - (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) - (any_extend:DI (match_operand:SI 2 "register_operand")))) - (clobber (scratch:DI)) - (clobber (scratch:DI)) - (clobber (scratch:DI))])] + [(set (match_operand:DI 0 "register_operand") + (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) + (any_extend:DI (match_operand:SI 2 "register_operand"))))] "!TARGET_64BIT || !TARGET_FIX_R4000" { - if (!TARGET_64BIT) - { - if (!TARGET_FIX_R4000) - emit_insn (gen_mulsidi3_32bit_internal (operands[0], operands[1], - operands[2])); - else - emit_insn (gen_mulsidi3_32bit_r4000 (operands[0], operands[1], - operands[2])); - DONE; - } + if (TARGET_64BIT) + emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2])); + else if (TARGET_FIX_R4000) + emit_insn (gen_mulsidi3_32bit_r4000 (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_mulsidi3_32bit (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "mulsidi3_32bit_internal" +(define_insn "mulsidi3_32bit" [(set (match_operand:DI 0 "register_operand" "=x") (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))] @@ -1648,42 +1590,35 @@ (define_insn "mulsidi3_32bit_r4000" (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) (clobber (match_scratch:DI 3 "=x"))] "!TARGET_64BIT && TARGET_FIX_R4000" - "mult\t%1,%2\;mflo\t%L0;mfhi\t%M0" + "mult\t%1,%2\;mflo\t%L0\;mfhi\t%M0" [(set_attr "type" "imul") (set_attr "mode" "SI") (set_attr "length" "12")]) -(define_insn_and_split "*mulsidi3_64bit" +(define_insn_and_split "mulsidi3_64bit" [(set (match_operand:DI 0 "register_operand" "=d") (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) - (clobber (match_scratch:DI 3 "=l")) - (clobber (match_scratch:DI 4 "=h")) - (clobber (match_scratch:DI 5 "=d"))] + (clobber (match_scratch:TI 3 "=x")) + (clobber (match_scratch:DI 4 "=d"))] "TARGET_64BIT && !TARGET_FIX_R4000" "#" "&& reload_completed" - [(parallel - [(set (match_dup 3) - (sign_extend:DI - (mult:SI (match_dup 1) - (match_dup 2)))) - (set (match_dup 4) - (ashiftrt:DI - (mult:DI (any_extend:DI (match_dup 1)) - (any_extend:DI (match_dup 2))) - (const_int 32)))]) - - ;; OP5 <- LO, OP0 <- HI - (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO)) - (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO)) - - ;; Zero-extend OP5. - (set (match_dup 5) - (ashift:DI (match_dup 5) + [(set (match_dup 3) + (unspec:TI [(mult:DI (any_extend:DI (match_dup 1)) + (any_extend:DI (match_dup 2)))] + UNSPEC_SET_HILO)) + + ;; OP4 <- LO, OP0 <- HI + (set (match_dup 4) (match_dup 5)) + (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI)) + + ;; Zero-extend OP4. + (set (match_dup 4) + (ashift:DI (match_dup 4) (const_int 32))) - (set (match_dup 5) - (lshiftrt:DI (match_dup 5) + (set (match_dup 4) + (lshiftrt:DI (match_dup 4) (const_int 32))) ;; Shift OP0 into place. @@ -1694,24 +1629,21 @@ (define_insn_and_split "*mulsidi3_64b ;; OR the two halves together (set (match_dup 0) (ior:DI (match_dup 0) - (match_dup 5)))] - "" + (match_dup 4)))] + { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); } [(set_attr "type" "imul") (set_attr "mode" "SI") (set_attr "length" "24")]) -(define_insn "*mulsidi3_64bit_parts" - [(set (match_operand:DI 0 "register_operand" "=l") - (sign_extend:DI - (mult:SI (match_operand:SI 2 "register_operand" "d") - (match_operand:SI 3 "register_operand" "d")))) - (set (match_operand:DI 1 "register_operand" "=h") - (ashiftrt:DI - (mult:DI (any_extend:DI (match_dup 2)) - (any_extend:DI (match_dup 3))) - (const_int 32)))] +(define_insn "mulsidi3_64bit_hilo" + [(set (match_operand:TI 0 "register_operand" "=x") + (unspec:TI + [(mult:DI + (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d")))] + UNSPEC_SET_HILO))] "TARGET_64BIT && !TARGET_FIX_R4000" - "mult\t%2,%3" + "mult\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -1755,7 +1687,7 @@ (define_expand "mulsi3_highpart" (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) (any_extend:DI (match_operand:SI 2 "register_operand"))) (const_int 32))))] - "ISA_HAS_MULHI || !TARGET_FIX_R4000" + "ISA_HAS_MULHI" { if (ISA_HAS_MULHI) emit_insn (gen_mulsi3_highpart_mulhi_internal (operands[0], @@ -1767,72 +1699,133 @@ (define_expand "mulsi3_highpart" DONE; }) -(define_insn "mulsi3_highpart_internal" - [(set (match_operand:SI 0 "register_operand" "=h") +(define_insn_and_split "mulsi3_highpart_internal" + [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) (const_int 32)))) (clobber (match_scratch:SI 3 "=l"))] - "!ISA_HAS_MULHI && !TARGET_FIX_R4000" - "mult\t%1,%2" + "!ISA_HAS_MULHI" + { return TARGET_FIX_R4000 ? "mult\t%1,%2\n\tmfhi\t%0" : "#"; } + "&& reload_completed && !TARGET_FIX_R4000" + [(const_int 0)] +{ + rtx hilo; + + if (TARGET_64BIT) + { + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_mulsidi3_64bit_hilo (hilo, operands[1], operands[2])); + emit_insn (gen_mfhisi_ti (operands[0], hilo)); + } + else + { + hilo = gen_rtx_REG (DImode, MD_REG_FIRST); + emit_insn (gen_mulsidi3_32bit (hilo, operands[1], operands[2])); + emit_insn (gen_mfhisi_di (operands[0], hilo)); + } + DONE; +} [(set_attr "type" "imul") - (set_attr "mode" "SI")]) + (set_attr "mode" "SI") + (set_attr "length" "8")]) (define_insn "mulsi3_highpart_mulhi_internal" - [(set (match_operand:SI 0 "register_operand" "=h,d") + [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI - (any_extend:DI (match_operand:SI 1 "register_operand" "d,d")) - (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))) + (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=l,l")) - (clobber (match_scratch:SI 4 "=X,h"))] + (clobber (match_scratch:SI 3 "=l"))] "ISA_HAS_MULHI" - "@ - mult\t%1,%2 - mulhi\t%0,%1,%2" - [(set_attr "type" "imul,imul3") + "mulhi\t%0,%1,%2" + [(set_attr "type" "imul3") (set_attr "mode" "SI")]) (define_insn "*mulsi3_highpart_neg_mulhi_internal" - [(set (match_operand:SI 0 "register_operand" "=h,d") + [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (neg:DI (mult:DI - (any_extend:DI (match_operand:SI 1 "register_operand" "d,d")) - (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))) + (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=l,l")) - (clobber (match_scratch:SI 4 "=X,h"))] + (clobber (match_scratch:SI 3 "=l"))] "ISA_HAS_MULHI" - "@ - mulshi\t%.,%1,%2 - mulshi\t%0,%1,%2" - [(set_attr "type" "imul,imul3") + "mulshi\t%0,%1,%2" + [(set_attr "type" "imul3") (set_attr "mode" "SI")]) ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120 ;; errata MD(0), which says that dmultu does not always produce the ;; correct result. -(define_insn "muldi3_highpart" - [(set (match_operand:DI 0 "register_operand" "=h") +(define_insn_and_split "muldi3_highpart" + [(set (match_operand:DI 0 "register_operand" "=d") (truncate:DI (lshiftrt:TI - (mult:TI - (any_extend:TI (match_operand:DI 1 "register_operand" "d")) - (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) + (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) (const_int 64)))) (clobber (match_scratch:DI 3 "=l"))] - "TARGET_64BIT && !TARGET_FIX_R4000 + "TARGET_64BIT && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" + { return TARGET_FIX_R4000 ? "dmult\t%1,%2\n\tmfhi\t%0" : "#"; } + "&& reload_completed && !TARGET_FIX_R4000" + [(const_int 0)] +{ + rtx hilo; + + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_mulditi3_internal (hilo, operands[1], operands[2])); + emit_insn (gen_mfhidi_ti (operands[0], hilo)); + DONE; +} + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "8")]) + +(define_expand "mulditi3" + [(set (match_operand:TI 0 "register_operand") + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) + (any_extend:TI (match_operand:DI 2 "register_operand"))))] + "TARGET_64BIT && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" +{ + if (TARGET_FIX_R4000) + emit_insn (gen_mulditi3_r4000 (operands[0], operands[1], operands[2])); + else + emit_insn (gen_mulditi3_internal (operands[0], operands[1], + operands[2])); + DONE; +}) + +(define_insn "mulditi3_internal" + [(set (match_operand:TI 0 "register_operand" "=x") + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) + (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))] + "TARGET_64BIT + && !TARGET_FIX_R4000 && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" "dmult\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) +(define_insn "mulditi3_r4000" + [(set (match_operand:TI 0 "register_operand" "=d") + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) + (any_extend:TI (match_operand:DI 2 "register_operand" "d")))) + (clobber (match_scratch:TI 3 "=x"))] + "TARGET_64BIT + && TARGET_FIX_R4000 + && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" + "dmult\t%1,%2\;mflo\t%L0\;mfhi\t%M0" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "12")]) + ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate ;; instruction. The HI/LO registers are used as a 64-bit accumulator. @@ -1840,8 +1833,7 @@ (define_insn "madsi" [(set (match_operand:SI 0 "register_operand" "+l") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")) - (match_dup 0))) - (clobber (match_scratch:SI 3 "=h"))] + (match_dup 0)))] "TARGET_MAD" "mad\t%1,%2" [(set_attr "type" "imadd") @@ -2016,29 +2008,74 @@ (define_insn "*recip3" ;; VR4120 errata MD(A1): signed division instructions do not work correctly ;; with negative operands. We use special libgcc functions instead. -(define_insn "divmod4" +(define_insn_and_split "divmod4" [(set (match_operand:GPR 0 "register_operand" "=l") (div:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d"))) - (set (match_operand:GPR 3 "register_operand" "=h") + (set (match_operand:GPR 3 "register_operand" "=d") (mod:GPR (match_dup 1) (match_dup 2)))] "!TARGET_FIX_VR4120" - { return mips_output_division ("div\t$0,%1,%2", operands); } - [(set_attr "type" "idiv") - (set_attr "mode" "")]) + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx hilo; + + if (TARGET_64BIT) + { + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_divmod4_hilo_ti (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_ti (operands[3], hilo)); + } + else + { + hilo = gen_rtx_REG (DImode, MD_REG_FIRST); + emit_insn (gen_divmod4_hilo_di (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_di (operands[3], hilo)); + } + DONE; +}) -(define_insn "udivmod4" +(define_insn_and_split "udivmod4" [(set (match_operand:GPR 0 "register_operand" "=l") (udiv:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d"))) - (set (match_operand:GPR 3 "register_operand" "=h") + (set (match_operand:GPR 3 "register_operand" "=d") (umod:GPR (match_dup 1) (match_dup 2)))] "" - { return mips_output_division ("divu\t$0,%1,%2", operands); } + "#" + "reload_completed" + [(const_int 0)] +{ + rtx hilo; + + if (TARGET_64BIT) + { + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_udivmod4_hilo_ti (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_ti (operands[3], hilo)); + } + else + { + hilo = gen_rtx_REG (DImode, MD_REG_FIRST); + emit_insn (gen_udivmod4_hilo_di (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_di (operands[3], hilo)); + } + DONE; +}) + +(define_insn "divmod4_hilo_" + [(set (match_operand:HILO 0 "register_operand" "=x") + (unspec:HILO + [(any_div:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "register_operand" "d"))] + UNSPEC_SET_HILO))] + "" + { return mips_output_division ("div\t%.,%1,%2", operands); } [(set_attr "type" "idiv") - (set_attr "mode" "")]) + (set_attr "mode" "")]) ;; ;; .................... @@ -3240,7 +3277,7 @@ (define_insn_and_split "*lea_high64" ;; dsll32 op1,op1,0 ;; daddu op1,op1,op0 (define_peephole2 - [(set (match_operand:DI 1 "register_operand") + [(set (match_operand:DI 1 "d_operand") (high:DI (match_operand:DI 2 "absolute_symbolic_operand"))) (match_scratch:DI 0 "d")] "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" @@ -3293,8 +3330,8 @@ (define_insn_and_split "*lea64" ;; ;; on MIPS16 targets. (define_split - [(set (match_operand:SI 0 "register_operand" "=d") - (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))] + [(set (match_operand:SI 0 "d_operand") + (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))] "TARGET_MIPS16 && reload_completed" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))] @@ -3463,7 +3500,7 @@ (define_insn "*movdi_32bit" && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store") + [(set_attr "type" "multi,multi,load,store,multi,multi,mtc,load,mfc,store") (set_attr "mode" "DI") (set_attr "length" "8,16,*,*,8,8,8,*,8,*")]) @@ -3474,7 +3511,7 @@ (define_insn "*movdi_gp32_fp64" && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore") + [(set_attr "type" "multi,multi,load,store,multi,multi,mtc,fpload,mfc,fpstore") (set_attr "mode" "DI") (set_attr "length" "8,16,*,*,8,8,8,*,8,*")]) @@ -3485,29 +3522,29 @@ (define_insn "*movdi_32bit_mips16" && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo") + [(set_attr "type" "multi,multi,multi,multi,multi,load,store,multi") (set_attr "mode" "DI") (set_attr "length" "8,8,8,8,12,*,*,8")]) (define_insn "*movdi_64bit" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m") - (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m") + (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] "TARGET_64BIT && !TARGET_MIPS16 && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store") + [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,load,mfc,store") (set_attr "mode" "DI") - (set_attr "length" "4,*,*,*,*,4,*,4,*,4,8,*,8,*")]) + (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,8,*,8,*")]) (define_insn "*movdi_64bit_mips16" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m") - (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") + (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d,*a"))] "TARGET_64BIT && TARGET_MIPS16 && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "move,move,move,arith,arith,load,const,load,store") + [(set_attr "type" "move,move,move,arith,arith,load,const,load,store,mfhilo") (set_attr "mode" "DI") (set_attr_alternative "length" [(const_int 4) @@ -3522,7 +3559,8 @@ (define_insn "*movdi_64bit_mips16" (const_int 8) (const_string "*") (const_string "*") - (const_string "*")])]) + (const_string "*") + (const_int 4)])]) ;; On the mips16, we can split ld $r,N($r) into an add and a load, @@ -3530,14 +3568,11 @@ (define_insn "*movdi_64bit_mips16" ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:DI 0 "register_operand") + [(set (match_operand:DI 0 "d_operand") (mem:DI (plus:DI (match_dup 0) (match_operand:DI 1 "const_int_operand"))))] "TARGET_64BIT && TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x10) || (INTVAL (operands[1]) >= 32 * 8 @@ -3588,7 +3623,7 @@ (define_expand "movsi" (define_insn "*movsi_internal" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") - (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))] + (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] "!TARGET_MIPS16 && (register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode))" @@ -3598,13 +3633,13 @@ (define_insn "*movsi_internal" (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,4,4,4,*,4,*")]) (define_insn "*movsi_mips16" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m") - (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") + (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d,*a"))] "TARGET_MIPS16 && (register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "move,move,move,arith,arith,load,const,load,store") + [(set_attr "type" "move,move,move,arith,arith,load,const,load,store,mfhilo") (set_attr "mode" "SI") (set_attr_alternative "length" [(const_int 4) @@ -3619,20 +3654,18 @@ (define_insn "*movsi_mips16" (const_int 8) (const_string "*") (const_string "*") - (const_string "*")])]) + (const_string "*") + (const_int 4)])]) ;; On the mips16, we can split lw $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "d_operand") (mem:SI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand"))))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x80) || (INTVAL (operands[1]) >= 32 * 4 @@ -3668,12 +3701,9 @@ (define_split ;; instructions. (define_split - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "d_operand") (match_operand:SI 1 "const_int_operand"))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 0x100 && INTVAL (operands[1]) <= 0xff + 0x7f" [(set (match_dup 0) (match_dup 1)) @@ -3796,36 +3826,24 @@ (define_expand "movhi" }) (define_insn "*movhi_internal" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*x") - (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d") + (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))] "!TARGET_MIPS16 && (register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode))" - "@ - move\t%0,%1 - li\t%0,%1 - lhu\t%0,%1 - sh\t%z1,%0 - mt%0\t%1" - [(set_attr "type" "move,arith,load,store,mthilo") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,arith,load,store,mthilo,mfhilo") (set_attr "mode" "HI") - (set_attr "length" "4,4,*,*,4")]) + (set_attr "length" "4,4,*,*,4,4")]) (define_insn "*movhi_mips16" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m") - (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") + (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] "TARGET_MIPS16 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" - "@ - move\t%0,%1 - move\t%0,%1 - move\t%0,%1 - li\t%0,%1 - # - lhu\t%0,%1 - sh\t%1,%0" - [(set_attr "type" "move,move,move,arith,arith,load,store") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,move,move,arith,arith,load,store,mfhilo") (set_attr "mode" "HI") (set_attr_alternative "length" [(const_int 4) @@ -3838,6 +3856,7 @@ (define_insn "*movhi_mips16" (const_int 8) (const_int 12)) (const_string "*") + (const_string "*") (const_string "*")])]) @@ -3846,13 +3865,10 @@ (define_insn "*movhi_mips16" ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:HI 0 "register_operand") + [(set (match_operand:HI 0 "d_operand") (mem:HI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand"))))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x80) || (INTVAL (operands[1]) >= 32 * 2 @@ -3900,51 +3916,36 @@ (define_expand "movqi" }) (define_insn "*movqi_internal" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*x") - (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d") + (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))] "!TARGET_MIPS16 && (register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode))" - "@ - move\t%0,%1 - li\t%0,%1 - lbu\t%0,%1 - sb\t%z1,%0 - mt%0\t%1" - [(set_attr "type" "move,arith,load,store,mthilo") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,arith,load,store,mthilo,mfhilo") (set_attr "mode" "QI") - (set_attr "length" "4,4,*,*,4")]) + (set_attr "length" "4,4,*,*,4,4")]) (define_insn "*movqi_mips16" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m") - (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") + (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] "TARGET_MIPS16 && (register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" - "@ - move\t%0,%1 - move\t%0,%1 - move\t%0,%1 - li\t%0,%1 - # - lbu\t%0,%1 - sb\t%1,%0" - [(set_attr "type" "move,move,move,arith,arith,load,store") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,move,move,arith,arith,load,store,mfhilo") (set_attr "mode" "QI") - (set_attr "length" "4,4,4,4,8,*,*")]) + (set_attr "length" "4,4,4,4,8,*,*,4")]) ;; On the mips16, we can split lb $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:QI 0 "register_operand") + [(set (match_operand:QI 0 "d_operand") (mem:QI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand"))))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x80) || (INTVAL (operands[1]) >= 32 @@ -4064,6 +4065,39 @@ (define_insn "*movdf_mips16" (set_attr "mode" "DF") (set_attr "length" "8,8,8,*,*")]) +;; 128-bit integer moves + +(define_expand "movti" + [(set (match_operand:TI 0) + (match_operand:TI 1))] + "TARGET_64BIT" +{ + if (mips_legitimize_move (TImode, operands[0], operands[1])) + DONE; +}) + +(define_insn "*movti" + [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,m,*a,*d") + (match_operand:TI 1 "move_operand" "di,m,dJ,*d*J,*a"))] + "TARGET_64BIT + && !TARGET_MIPS16 + && (register_operand (operands[0], TImode) + || reg_or_0_operand (operands[1], TImode))" + "#" + [(set_attr "type" "multi,load,store,multi,multi") + (set_attr "length" "8,*,*,8,8")]) + +(define_insn "*movti_mips16" + [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") + (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] + "TARGET_64BIT + && TARGET_MIPS16 + && (register_operand (operands[0], TImode) + || register_operand (operands[1], TImode))" + "#" + [(set_attr "type" "multi,multi,multi,multi,multi,load,store,multi") + (set_attr "length" "8,8,8,12,16,*,*,8")]) + ;; 128-bit floating point moves (define_expand "movtf" @@ -4122,7 +4156,7 @@ (define_split ;; When generating mips16 code, split moves of negative constants into ;; a positive "li" followed by a negation. (define_split - [(set (match_operand 0 "register_operand") + [(set (match_operand 0 "d_operand") (match_operand 1 "const_int_operand"))] "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0" [(set (match_dup 2) @@ -4171,44 +4205,27 @@ (define_insn "movv2sf_hardfloat_32bit" (set_attr "mode" "SF") (set_attr "length" "4,8,*,*,*,8,8,8,*,*")]) -;; The HI and LO registers are not truly independent. If we move an mthi -;; instruction before an mflo instruction, it will make the result of the -;; mflo unpredictable. The same goes for mtlo and mfhi. -;; -;; We cope with this by making the mflo and mfhi patterns use both HI and LO. -;; Operand 1 is the register we want, operand 2 is the other one. -;; -;; When generating VR4120 or VR4130 code, we use macc{,hi} and -;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal -;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130. - -(define_expand "mfhilo_" - [(set (match_operand:GPR 0 "register_operand") - (unspec:GPR [(match_operand:GPR 1 "register_operand") - (match_operand:GPR 2 "register_operand")] - UNSPEC_MFHILO))]) - -(define_insn "*mfhilo_" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") - (match_operand:GPR 2 "register_operand" "l,h")] - UNSPEC_MFHILO))] - "!ISA_HAS_MACCHI" - "mf%1\t%0" +;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI +;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards +;; and the errata related to -mfix-vr4130. +(define_insn "mfhi_" + [(set (match_operand:GPR 0 "register_operand" "=d") + (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")] + UNSPEC_MFHI))] + "" + { return ISA_HAS_MACCHI ? "macchi\t%0,%.,%." : "mfhi\t%0"; } [(set_attr "type" "mfhilo") - (set_attr "mode" "")]) + (set_attr "mode" "")]) -(define_insn "*mfhilo__macc" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") - (match_operand:GPR 2 "register_operand" "l,h")] - UNSPEC_MFHILO))] - "ISA_HAS_MACCHI" - "@ - macchi\t%0,%.,%. - macc\t%0,%.,%." - [(set_attr "type" "mfhilo") - (set_attr "mode" "")]) +(define_insn "mthi_" + [(set (match_operand:HILO 0 "register_operand" "=x") + (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ") + (match_operand:GPR 2 "register_operand" "l")] + UNSPEC_MTHI))] + "" + "mthi\t%z1" + [(set_attr "type" "mthilo") + (set_attr "mode" "SI")]) ;; Emit a doubleword move in which exactly one of the operands is ;; a floating-point register. We can't just emit two normal moves @@ -5120,11 +5137,10 @@ (define_insn "*lshrdi3_mips16" ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. (define_split - [(set (match_operand:GPR 0 "register_operand") - (any_shift:GPR (match_operand:GPR 1 "register_operand") + [(set (match_operand:GPR 0 "d_operand") + (any_shift:GPR (match_operand:GPR 1 "d_operand") (match_operand:GPR 2 "const_int_operand")))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16" [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8))) Index: gcc/config/mips/predicates.md =================================================================== --- gcc/config/mips/predicates.md 2008-06-01 10:23:31.000000000 +0100 +++ gcc/config/mips/predicates.md 2008-06-01 14:06:06.000000000 +0100 @@ -76,9 +76,11 @@ (define_predicate "const_0_or_1_operand" (ior (match_test "op == CONST0_RTX (GET_MODE (op))") (match_test "op == CONST1_RTX (GET_MODE (op))")))) -(define_predicate "fpr_operand" +(define_predicate "d_operand" (and (match_code "reg") - (match_test "FP_REG_P (REGNO (op))"))) + (match_test "TARGET_MIPS16 + ? M16_REG_P (REGNO (op)) + : GP_REG_P (REGNO (op))"))) (define_predicate "lo_operand" (and (match_code "reg") Index: gcc/testsuite/gcc.dg/torture/mips-hilo-1.c =================================================================== --- gcc/testsuite/gcc.dg/torture/mips-hilo-1.c 2008-06-01 10:23:31.000000000 +0100 +++ /dev/null 2008-05-31 10:25:53.548096750 +0100 @@ -1,73 +0,0 @@ -/* f1 checks that an mtlo is not moved before an mfhi. f2 does the same - for an mthi and an mflo. */ -/* { dg-do run { target mips*-*-* } } */ -/* { dg-options "-mtune=rm7000" } */ - -extern void abort (void); -extern void exit (int); - -#define DECLARE(TYPE) \ - TYPE __attribute__ ((noinline)) __attribute__ ((nomips16)) \ - f1##TYPE (TYPE x1, TYPE x2, TYPE x3) \ - { \ - TYPE t1, t2; \ - \ - asm ("mult\t%1,%2" : "=h" (t1) : "d" (x1), "d" (x2) : "lo"); \ - asm ("mflo\t%0" : "=r" (t2) : "l" (x3) : "hi"); \ - return t1 + t2; \ - } \ - \ - TYPE __attribute__ ((noinline)) __attribute__ ((nomips16)) \ - f2##TYPE (TYPE x1, TYPE x2, TYPE x3) \ - { \ - TYPE t1, t2; \ - \ - asm ("mult\t%1,%2" : "=l" (t1) : "d" (x1), "d" (x2) : "hi"); \ - asm ("mfhi\t%0" : "=r" (t2) : "h" (x3) : "lo"); \ - return t1 + t2; \ - } - -#define TEST(TYPE) \ - if (f1##TYPE (1, 2, 10) != 10) \ - abort (); \ - if (f2##TYPE (1, 2, 40) != 42) \ - abort () - -typedef char c; -typedef signed char sc; -typedef unsigned char uc; -typedef short s; -typedef unsigned short us; -typedef int i; -typedef unsigned int ui; -typedef long long ll; -typedef unsigned long long ull; - -DECLARE (c) -DECLARE (sc) -DECLARE (uc) -DECLARE (s) -DECLARE (us) -DECLARE (i) -DECLARE (ui) -#if defined (__mips64) -DECLARE (ll) -DECLARE (ull) -#endif - -int -main () -{ - TEST (c); - TEST (sc); - TEST (uc); - TEST (s); - TEST (us); - TEST (i); - TEST (ui); -#if defined (__mips64) - TEST (ll); - TEST (ull); -#endif - exit (0); -} Index: gcc/testsuite/gcc.target/mips/pr35232.c =================================================================== --- gcc/testsuite/gcc.target/mips/pr35232.c 2008-06-01 10:23:31.000000000 +0100 +++ /dev/null 2008-05-31 10:25:53.548096750 +0100 @@ -1,17 +0,0 @@ -/* { dg-do run } */ -/* { dg-mips-options "-O" } */ - -NOMIPS16 unsigned int -f1 (unsigned long long x) -{ - unsigned int r; - asm ("# %0" : "=a" (r) : "0" (x)); - asm ("# %0" : "=h" (r) : "0" (r)); - return r; -} - -int -main (void) -{ - return f1 (4) != 4; -} Index: gcc/testsuite/gcc.target/mips/fix-vr4130-1.c =================================================================== --- gcc/testsuite/gcc.target/mips/fix-vr4130-1.c 2008-06-01 10:23:31.000000000 +0100 +++ gcc/testsuite/gcc.target/mips/fix-vr4130-1.c 2008-06-01 14:06:06.000000000 +0100 @@ -1,4 +1,8 @@ /* { dg-do compile } */ /* { dg-mips-options "-march=vr4130 -mfix-vr4130" } */ -NOMIPS16 int foo (void) { int r; asm ("# foo" : "=h" (r)); return r; } +NOMIPS16 unsigned int +foo (unsigned int x, unsigned int y) +{ + return x % y; +} /* { dg-final { scan-assembler "\tmacchi\t" } } */ Index: gcc/testsuite/gcc.target/mips/fix-vr4130-3.c =================================================================== --- gcc/testsuite/gcc.target/mips/fix-vr4130-3.c 2008-06-01 10:23:31.000000000 +0100 +++ gcc/testsuite/gcc.target/mips/fix-vr4130-3.c 2008-06-01 14:06:06.000000000 +0100 @@ -1,10 +1,8 @@ /* { dg-do compile } */ /* { dg-mips-options "-march=vr4130 -mgp64 -mfix-vr4130" } */ -NOMIPS16 long long -foo (void) +NOMIPS16 unsigned long long +foo (unsigned long long x, unsigned long long y) { - long long r; - asm ("# foo" : "=h" (r)); - return r; + return x % y; } /* { dg-final { scan-assembler "\tdmacchi\t" } } */ Index: gcc/testsuite/gcc.target/mips/int-moves-1.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/int-moves-1.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,40 @@ +/* { dg-do compile { target mips16_attribute } } */ +/* { dg-mips-options "-mgp64 -msoft-float -O2 -EL" } */ +/* { dg-add-options mips16_attribute } */ + +typedef unsigned uint128_t __attribute__((mode(TI))); + +extern uint128_t g[16]; +extern unsigned char gstuff[0x10000]; + +NOMIPS16 uint128_t +foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} + +MIPS16 uint128_t +bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} Index: gcc/testsuite/gcc.target/mips/int-moves-2.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/int-moves-2.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,40 @@ +/* { dg-do compile { target mips16_attribute } } */ +/* { dg-mips-options "-mgp64 -msoft-float -O2 -EB" } */ +/* { dg-add-options mips16_attribute } */ + +typedef unsigned uint128_t __attribute__((mode(TI))); + +extern uint128_t g[16]; +extern unsigned char gstuff[0x10000]; + +NOMIPS16 uint128_t +foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} + +MIPS16 uint128_t +bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} Index: gcc/testsuite/gcc.target/mips/fix-r4000-1.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-1.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,6 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -O2 -dp" } */ +typedef int int32_t; +typedef int uint32_t; +int32_t foo (int32_t x, int32_t y) { return x * y; } +uint32_t bar (uint32_t x, uint32_t y) { return x * y; } +/* { dg-final { scan-assembler-times "[concat {\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-2.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-2.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */ +typedef int int32_t; +typedef long long int64_t; +int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-3.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-3.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */ +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-4.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-4.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */ +typedef int int32_t; +typedef long long int64_t; +int64_t foo (int32_t x, int32_t y) { return (int64_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-5.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-5.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */ +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +uint64_t foo (uint32_t x, uint32_t y) { return (uint64_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-6.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-6.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,6 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ +typedef long long int64_t; +typedef unsigned long long uint64_t; +int64_t foo (int64_t x, int64_t y) { return x * y; } +uint64_t bar (uint64_t x, uint64_t y) { return x * y; } +/* { dg-final { scan-assembler-times "[concat {\tdmult\t\$[45],\$[45][^\n]+muldi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-7.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-7.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */ +typedef long long int64_t; +typedef int int128_t __attribute__((mode(TI))); +int64_t foo (int64_t x, int64_t y) { return ((int128_t) x * y) >> 64; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-8.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-8.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */ +typedef unsigned long long uint64_t; +typedef unsigned int uint128_t __attribute__((mode(TI))); +uint64_t foo (uint64_t x, uint64_t y) { return ((uint128_t) x * y) >> 64; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-9.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-9.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */ +typedef long long int64_t; +typedef int int128_t __attribute__((mode(TI))); +int128_t foo (int64_t x, int64_t y) { return (int128_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-10.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-10.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */ +typedef unsigned long long uint64_t; +typedef unsigned int uint128_t __attribute__((mode(TI))); +uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-11.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-11.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,4 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ +typedef long long int64_t; +int64_t foo (int64_t x) { return x / 11993; } +/* { dg-final { scan-assembler "[concat {\tdmult\t\$4,\$[0-9]+[^\n]+smuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-12.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-12.c 2008-06-01 14:06:06.000000000 +0100 @@ -0,0 +1,4 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ +typedef unsigned long long uint64_t; +uint64_t foo (uint64_t x) { return x / 11993; } +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$4,\$[0-9]+[^\n]+umuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/timode-1.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/timode-1.c 2008-06-01 14:21:51.000000000 +0100 @@ -0,0 +1,65 @@ +/* { dg-mips-options "-mgp64" } */ +typedef int int128_t __attribute__((mode(TI))); +typedef unsigned int uint128_t __attribute__((mode(TI))); + +#define UINT128_CONST(A, B) \ + (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL)) + +volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222); +volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003); +volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666); +volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500); +volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66); +volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100); +volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66); +volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66); +volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660); +volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6); +volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6); + +volatile int amount = 4; + +volatile uint128_t result; + +int +main (void) +{ + result = a * b; + if (result != c) + return 1; + + result = c + d; + if (result != e) + return 1; + + result = e - d; + if (result != c) + return 1; + + result = d & e; + if (result != f) + return 1; + + result = d ^ e; + if (result != g) + return 1; + + result = d | e; + if (result != h) + return 1; + + result = g << amount; + if (result != i) + return 1; + + result = g >> amount; + if (result != j) + return 1; + + result = (int128_t) g >> amount; + if (result != k) + return 1; + + return 0; +} +/* { dg-final { scan-assembler-not "\tjal" } } */ Index: gcc/testsuite/gcc.target/mips/timode-2.c =================================================================== --- /dev/null 2008-05-31 10:25:53.548096750 +0100 +++ gcc/testsuite/gcc.target/mips/timode-2.c 2008-06-01 14:21:36.000000000 +0100 @@ -0,0 +1,64 @@ +/* { dg-do run { target mips64 } } */ +typedef int int128_t __attribute__((mode(TI))); +typedef unsigned int uint128_t __attribute__((mode(TI))); + +#define UINT128_CONST(A, B) \ + (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL)) + +volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222); +volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003); +volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666); +volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500); +volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66); +volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100); +volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66); +volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66); +volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660); +volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6); +volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6); + +volatile int amount = 4; + +volatile uint128_t result; + +int +main (void) +{ + result = a * b; + if (result != c) + return 1; + + result = c + d; + if (result != e) + return 1; + + result = e - d; + if (result != c) + return 1; + + result = d & e; + if (result != f) + return 1; + + result = d ^ e; + if (result != g) + return 1; + + result = d | e; + if (result != h) + return 1; + + result = g << amount; + if (result != i) + return 1; + + result = g >> amount; + if (result != j) + return 1; + + result = (int128_t) g >> amount; + if (result != k) + return 1; + + return 0; +} From anemo@mba.ocn.ne.jp Sun Jun 1 17:33:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Jun 2008 17:33:49 +0100 (BST) Received: from p549F48FC.dip.t-dialin.net ([84.159.72.252]:20181 "EHLO p549F48FC.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20024203AbYFAQdr (ORCPT ); Sun, 1 Jun 2008 17:33:47 +0100 Received: from [122.1.235.107] ([122.1.235.107]:21985 "EHLO smtp.mba.ocn.ne.jp") by lappi.linux-mips.net with ESMTP id S1111367AbYFAQ2q (ORCPT ); Sun, 1 Jun 2008 18:28:46 +0200 Received: from localhost (p7240-ipad212funabasi.chiba.ocn.ne.jp [58.91.171.240]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 390ECAA2B; Mon, 2 Jun 2008 01:26:52 +0900 (JST) Date: Mon, 02 Jun 2008 01:28:14 +0900 (JST) Message-Id: <20080602.012814.35471915.anemo@mba.ocn.ne.jp> To: adrian.bunk@movial.fi Cc: chris@mips.com, ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: mips: CONF_CM_DEFAULT build error From: Atsushi Nemoto In-Reply-To: <20080525170718.GD1791@cs181133002.pp.htv.fi> References: <20080525170718.GD1791@cs181133002.pp.htv.fi> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19391 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sun, 25 May 2008 20:07:24 +0300, Adrian Bunk wrote: > Commit 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 > ([MIPS] Allow setting of the cache attribute at run time.) > causes the following build error with pnx8550-jbs_defconfig > and pnx8550-stb810_defconfig: I wondered why the commit has my S-O-B, and finally found that I had fixed a section mismatch caused by the original patch (on queue tree on linux-mips.org) and Ralf had folded my fix into the original patch, with my S-O-B. Folding on the queue tree will be good on many case, but sometimes a bit confusing. :-) Anyway, here is a patch to fix the build failure. Thank you for reporting. ------------------------------------------------------ Subject: [PATCH] MIPS: Fix CONF_CM_DEFAULT build error From: Atsushi Nemoto Signed-off-by: Atsushi Nemoto --- diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index 60e2f93..8a75677 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -134,6 +134,6 @@ #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) -#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT) +#define CONF_CM_DEFAULT (_page_cachable_default >> _CACHE_SHIFT) #endif /* _ASM_PGTABLE_BITS_H */ From sshtylyov@ru.mvista.com Sun Jun 1 19:02:12 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Jun 2008 19:02:14 +0100 (BST) Received: from p549F48FC.dip.t-dialin.net ([84.159.72.252]:39557 "EHLO p549F48FC.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20024340AbYFASCJ (ORCPT ); Sun, 1 Jun 2008 19:02:09 +0100 Received: from h155.mvista.com ([63.81.120.155]:19062 "EHLO imap.sh.mvista.com") by lappi.linux-mips.net with ESMTP id S1111459AbYFAR4y (ORCPT ); Sun, 1 Jun 2008 19:56:54 +0200 Received: from [127.0.0.1] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 8DB163EC9; Sun, 1 Jun 2008 10:56:19 -0700 (PDT) Message-ID: <4842E2C0.1020106@ru.mvista.com> Date: Sun, 01 Jun 2008 21:56:16 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 1.5.0.14 (Windows/20071210) MIME-Version: 1.0 To: Manuel Lauss Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: make r4k clocksource/clockevent usable in other codepaths References: <20080528122838.GA5976@roarinelk.homelinux.net> In-Reply-To: <20080528122838.GA5976@roarinelk.homelinux.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19392 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Manuel Lauss wrote: > Make the r4k cp0 counter clocksource and clockevent modules > library code so it may be used e.g. as a fallback in case other > clocksources/events aren't available. > > Signed-off-by: Manuel Lauss > [...] > diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h > index d3bd5c5..01a4c93 100644 > --- a/include/asm-mips/time.h > +++ b/include/asm-mips/time.h > @@ -50,27 +50,35 @@ extern int (*perf_irq)(void); > /* > * Initialize the calling CPU's compare interrupt as clockevent device > */ > -#ifdef CONFIG_CEVT_R4K > -extern int mips_clockevent_init(void); > +#ifdef CONFIG_CEVT_R4K_LIB > extern unsigned int __weak get_c0_compare_int(void); > -#else > +extern int r4k_clockevent_init(void); > +#endif > + > static inline int mips_clockevent_init(void) > { > +#ifdef CONFIG_CEVT_R4K > + return r4k_clockevent_init(); > +#else > return -ENXIO; > -} > #endif > +} > > /* > * Initialize the count register as a clocksource > */ > -#ifdef CONFIG_CEVT_R4K > -extern int init_mips_clocksource(void); > -#else > +#ifdef CONFIG_CSRC_R4K_LIB > +extern int init_r4k_clocksource(void); > +#endif > Hm, does it make sense to hedge ''extern' declaration by #ifdef's? WBR, Sergei From m.jancar@satca.net Mon Jun 2 13:07:36 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Jun 2008 13:07:38 +0100 (BST) Received: from p549F5CCF.dip.t-dialin.net ([84.159.92.207]:63632 "EHLO p549F5CCF.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20022163AbYFBMHg (ORCPT ); Mon, 2 Jun 2008 13:07:36 +0100 Received: from skerikoff.satca.net ([81.90.243.194]:61401 "EHLO smtp.satca.net") by lappi.linux-mips.net with ESMTP id S525904AbYFBLwC (ORCPT ); Mon, 2 Jun 2008 13:52:02 +0200 Received: from localhost (unknown [127.0.0.1]) by smtp.satca.net (Postfix) with ESMTP id F0F92E418E7; Mon, 2 Jun 2008 10:28:53 +0000 (UTC) X-Virus-Scanned: amavisd-new at satca.net Received: from smtp.satca.net ([127.0.0.1]) by localhost (skerikoff.satca.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Uyv-Ac8CyG26; Mon, 2 Jun 2008 12:28:49 +0200 (CEST) Received: from [192.168.51.201] (unknown [192.168.51.201]) by smtp.satca.net (Postfix) with ESMTP id 4BBB3E41089; Mon, 2 Jun 2008 10:28:49 +0000 (UTC) Message-ID: <4843DEFD.9020303@satca.net> Date: Mon, 02 Jun 2008 13:52:29 +0200 From: Marian Jancar User-Agent: Thunderbird 2.0.0.5 (X11/20070719) MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: [PATCH 5/7] gcov: add gcov profiling infrastructure References: <48313DE6.30802@de.ibm.com> <20080523001136.59ec8b34.akpm@linux-foundation.org> <20080523084506.GB719@linux-mips.org> In-Reply-To: <20080523084506.GB719@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.jancar@satca.net Precedence: bulk X-list: linux-mips Ralf Baechle wrote: >> {standard input}: Assembler messages: >> {standard input}:2716: Error: Branch out of range >> {standard input}:2819: Error: Branch out of range >> {standard input}:2884: Error: Branch out of range >> {standard input}:3032: Error: Branch out of range >> {standard input}:3097: Error: Branch out of range >> {standard input}:3151: Error: Branch out of range >> {standard input}:3216: Error: Branch out of range >> make[1]: *** [drivers/telephony/ixj.o] Error 1 >> make: *** [drivers/telephony/ixj.o] Error 2 > > A known problem which I had decieded to ignore until it begins to actually > bite. It's triggered by something like this > > __asm__ __volatile__( > " .set mips3 \n" > "1: ll %0, %1 # atomic_add \n" > " addu %0, %2 \n" > " sc %0, %1 \n" > " beqz %0, 2f \n" > " .subsection 2 \n" > "2: b 1b \n" > " .previous \n" > " .set mips0 \n" > : "=&r" (temp), "=m" (v->counter) > : "Ir" (i), "m" (v->counter)); > > when compiled into a large compilation unit. Please unignore :) It bites when compiling madwifi (without profiling or anything such). Marian From dmitri.vorobiev@gmail.com Mon Jun 2 17:07:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Jun 2008 17:07:49 +0100 (BST) Received: from p549F5CCF.dip.t-dialin.net ([84.159.92.207]:38583 "EHLO p549F5CCF.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20021677AbYFBQHr (ORCPT ); Mon, 2 Jun 2008 17:07:47 +0100 Received: from yx-out-1718.google.com ([74.125.44.155]:51528 "EHLO yx-out-1718.google.com") by lappi.linux-mips.net with ESMTP id S525977AbYFBQGI (ORCPT ); Mon, 2 Jun 2008 18:06:08 +0200 Received: by yx-out-1718.google.com with SMTP id 36so74630yxh.24 for ; Mon, 02 Jun 2008 09:05:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; bh=PVaRdja2mkx32MMyluimCzLHxRHHYxW3TBjgtP3Vro4=; b=pqcJIEtZkul3OnPZGmS63oFubYOCB8zeKzARs7oc1eadDdCQ3NMcPvaj59/0EtYldRy+ER3xeQpY3FxfLsQU95XNBpGaTB763UQJiuo/5xDj49Ezn2TMQaEBYZ8SCElDc1xftDzkQZWqpi4eoBATncWQaFH+WsDkfdCz3g5kzsI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=R6s2WQK7WH/I8wucKhxrLhLRVF5X/20ilTT39MMOvI33v4BLVImEEd2M0RxEYc3zaNh0TD4jIaxmfRjCnbug57AwgAk4KPpfbJ/UGnRUoF6hKU2sECfI77nhApCqGzi/Kg1aAnwtbDQTCpACLFTTsyFfVLOB12jHI9YcqhNwtdg= Received: by 10.151.155.21 with SMTP id h21mr4663643ybo.142.1212421217947; Mon, 02 Jun 2008 08:40:17 -0700 (PDT) Received: by 10.150.140.6 with HTTP; Mon, 2 Jun 2008 08:40:17 -0700 (PDT) Message-ID: <90edad820806020840m2e9f5588x81f8c387aef23c6c@mail.gmail.com> Date: Mon, 2 Jun 2008 18:40:17 +0300 From: "Dmitri Vorobiev" To: "Thomas Bogendoerfer" Subject: Re: Malta build errors with 2.6.26-rc1 Cc: "Martin Michlmayr" , linux-mips@linux-mips.org, ralf@linux-mips.org In-Reply-To: <20080529200506.GA27783@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20080512163107.GA19052@deprecation.cyrius.com> <90edad820805121246o328d1cdaide88594ce9d328b7@mail.gmail.com> <20080528071240.GB10393@deprecation.cyrius.com> <20080528085033.GA6250@alpha.franken.de> <20080528151025.GA15325@deprecation.cyrius.com> <20080529200506.GA27783@alpha.franken.de> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips 2008/5/29 Thomas Bogendoerfer : > On Wed, May 28, 2008 at 05:10:25PM +0200, Martin Michlmayr wrote: >> * Thomas Bogendoerfer [2008-05-28 10:50]: >> > I didn't fix the problems above. The change to traps.c only fixes >> > traps.c for 64bit builds and it's a totally different issue. Looking >> > at the warning/errors someone needs to fix some data types and use >> > CKSEG0ADDR(). I don't have the hardware, so I could only provide an >> > untested patch, if no one else steps forward... >> >> QEMU emulates Malta, so I (or someone else here) should be able to >> test the patch. > > > Fix 64bit Malta by using CKSEG0ADDR and correct casts > > Signed-off-by: Thomas Bogendoerfer > --- > > arch/mips/mips-boards/generic/amon.c | 4 ++-- > include/asm-mips/gic.h | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/mips/mips-boards/generic/amon.c b/arch/mips/mips-boards/generic/amon.c > index b7633fd..96236bf 100644 > --- a/arch/mips/mips-boards/generic/amon.c > +++ b/arch/mips/mips-boards/generic/amon.c > @@ -28,7 +28,7 @@ > > int amon_cpu_avail(int cpu) > { > - struct cpulaunch *launch = (struct cpulaunch *)KSEG0ADDR(CPULAUNCH); > + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); > > if (cpu < 0 || cpu >= NCPULAUNCH) { > pr_debug("avail: cpu%d is out of range\n", cpu); > @@ -53,7 +53,7 @@ void amon_cpu_start(int cpu, > unsigned long gp, unsigned long a0) > { > volatile struct cpulaunch *launch = > - (struct cpulaunch *)KSEG0ADDR(CPULAUNCH); > + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); > > if (!amon_cpu_avail(cpu)) > return; > diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h > index 3a492f2..954807d 100644 > --- a/include/asm-mips/gic.h > +++ b/include/asm-mips/gic.h > @@ -24,8 +24,8 @@ > > #define MSK(n) ((1 << (n)) - 1) > #define REG32(addr) (*(volatile unsigned int *) (addr)) > -#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS) > -#define REGP(base, phys) REG32((unsigned int)(base) + (phys)) > +#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS) > +#define REGP(base, phys) REG32((unsigned long)(base) + (phys)) > > /* Accessors */ > #define GIC_REG(segment, offset) \ My test was performed using a Malta 4Kc board. I was able to boot the target up to the shell prompt with this patch applied to the current Linus tree. So, you might want to add Tested-by: Dmitri Vorobiev From dmitri.vorobiev@gmail.com Tue Jun 3 08:07:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Jun 2008 08:07:40 +0100 (BST) Received: from p549F5460.dip.t-dialin.net ([84.159.84.96]:8578 "EHLO p549F5460.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20022386AbYFCHHh (ORCPT ); Tue, 3 Jun 2008 08:07:37 +0100 Received: from yw-out-1718.google.com ([74.125.46.156]:48301 "EHLO yw-out-1718.google.com") by lappi.linux-mips.net with ESMTP id S526979AbYFCGp4 (ORCPT ); Tue, 3 Jun 2008 08:45:56 +0200 Received: by yw-out-1718.google.com with SMTP id 9so590008ywk.24 for ; Mon, 02 Jun 2008 23:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; bh=HUh9VzF+W9Owg4wWpAWeWM/7NkysXXf/LPIZvTMGGKo=; b=Ig5Io+0azmnHODlHiTV5cHmMLibrmwtLE8y1YgpzAVXlu6i4zraZyQBt0FYbr+RzSXKjJKeF+aol3ITEKyfztHEryDhCI1OSisMMpP92PJfB09LWS77cTcDM0CYrsOjHThWK0jH5reLDIko//gWXxA6HiEZE1uX3elsQyn++Oqw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=vDgr1bG1B3WIvFOT9WfWkz+GS/rbBg8yC4rnuTmTFwYvkXMl2W8RkoPKs/VfG/Ho+VZuTvwGItyR2h8GnmSYEPCcYKoMYzqjP70fnQ/8FdX23sCIybv1GGINjqyGn5ntqS/dfUY8Hmmg35A2Ers4wVluQedkAG50VcZJ6w4ou80= Received: by 10.151.145.17 with SMTP id x17mr2001074ybn.20.1212475509161; Mon, 02 Jun 2008 23:45:09 -0700 (PDT) Received: by 10.150.140.6 with HTTP; Mon, 2 Jun 2008 23:45:08 -0700 (PDT) Message-ID: <90edad820806022345g6383e5b3hf2d0e73eed3e375e@mail.gmail.com> Date: Tue, 3 Jun 2008 09:45:08 +0300 From: "Dmitri Vorobiev" To: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: email does not get through to linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips Hi Ralf, When I send mail to linux-mips at linux-mips dot org from one of my mail accounts (located in the domain movial dot fi), my emails apparently do not get through. I do not see the messages in the Web archive, neither do I receive these messages in my Gmail account, which is also subscribed to the linux-mips mailing list. I tried sending messages using both Thunderbird and Git. Messages did not arrive in both cases. Will you please check what's going on? I suspect that other users of the mailing list could experience similar problems, and that is why I'm Cc:ing the mailing list itself now. Thanks, Dmitri Vorobiev From ralf@linux-mips.org Tue Jun 3 11:33:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Jun 2008 11:33:40 +0100 (BST) Received: from p549F5460.dip.t-dialin.net ([84.159.84.96]:8578 "EHLO p549F5460.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20030694AbYFCKdh (ORCPT ); Tue, 3 Jun 2008 11:33:37 +0100 Received: from vigor.karmaclothing.net ([217.169.26.28]:46261 "EHLO vigor.karmaclothing.net") by lappi.linux-mips.net with ESMTP id S527010AbYFCI1X (ORCPT ); Tue, 3 Jun 2008 10:27:23 +0200 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m538QrGr001314; Tue, 3 Jun 2008 09:26:53 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m538Qq49001313; Tue, 3 Jun 2008 09:26:52 +0100 Date: Tue, 3 Jun 2008 09:26:52 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: email does not get through to linux-mips.org Message-ID: <20080603082652.GB27478@linux-mips.org> References: <90edad820806022345g6383e5b3hf2d0e73eed3e375e@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <90edad820806022345g6383e5b3hf2d0e73eed3e375e@mail.gmail.com> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 03, 2008 at 09:45:08AM +0300, Dmitri Vorobiev wrote: > When I send mail to linux-mips at linux-mips dot org from one of my > mail accounts (located in the domain movial dot fi), my emails > apparently do not get through. I do not see the messages in the Web > archive, neither do I receive these messages in my Gmail account, > which is also subscribed to the linux-mips mailing list. > > I tried sending messages using both Thunderbird and Git. Messages did > not arrive in both cases. > > Will you please check what's going on? I suspect that other users of > the mailing list could experience similar problems, and that is why > I'm Cc:ing the mailing list itself now. Unfortunately I'm aware of the problem. Since a few days a packet raping machine otherwise known as Cisco PIX is molesting conectivity of linux-mips.org resuling in SMTP sessions with some hosts to fail. To keep the show running I installed a temporary workaround. The email which you forwarded me in private got lost in the spam filter as a side effect of an attempted workaround for above problem, so I'm now going to engineer something better. Ralf From dmitri.vorobiev@gmail.com Tue Jun 3 12:02:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Jun 2008 12:02:36 +0100 (BST) Received: from p549F5460.dip.t-dialin.net ([84.159.84.96]:8578 "EHLO p549F5460.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20031462AbYFCLCd (ORCPT ); Tue, 3 Jun 2008 12:02:33 +0100 Received: from yw-out-1718.google.com ([74.125.46.157]:24494 "EHLO yw-out-1718.google.com") by lappi.linux-mips.net with ESMTP id S527144AbYFCIj3 (ORCPT ); Tue, 3 Jun 2008 10:39:29 +0200 Received: by yw-out-1718.google.com with SMTP id 9so604272ywk.24 for ; Tue, 03 Jun 2008 01:38:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; bh=wpE3Jak1lMhMl5hLgogLX2umKsR/sorZKVk4iX9Sk5s=; b=f47c5TKoUK2ueTGtf1LE+VL3JbJjOYVmTh0pWIf/mVsSZSpTSmu6XioIK6rxN9C0cciTRAhZ9geXtB54GiGfpYwknRcZVlmxB829u88t7WHjApXn19iM1hcfxOYRiQ+en23UMLBKzilxBeHymX+G+xZ4AJ80NAA8NdWW44FWwFw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=gaEnFOqGsIDnXt+JaI3dhD6V0rJNTeGic2wNDceMZl2IyVLt9M9dM6YvLCnkt7lMyNv5I1B1z3wtXPYJvGMWsAFeQGVaMRANpzsI6wzHcXVyatv7QCegMoqHLLXR/dIUKdD5HdwX/BdM5TiYSetdFjU/0ju6ZZKIlmKlvEMZ9bQ= Received: by 10.151.158.2 with SMTP id k2mr583176ybo.70.1212482299775; Tue, 03 Jun 2008 01:38:19 -0700 (PDT) Received: by 10.150.140.6 with HTTP; Tue, 3 Jun 2008 01:38:19 -0700 (PDT) Message-ID: <90edad820806030138x7837f69exbf3362470ca0021c@mail.gmail.com> Date: Tue, 3 Jun 2008 11:38:19 +0300 From: "Dmitri Vorobiev" To: "Thomas Bogendoerfer" Subject: Re: Malta build errors with 2.6.26-rc1 Cc: "Martin Michlmayr" , linux-mips@linux-mips.org, ralf@linux-mips.org In-Reply-To: <90edad820806020840m2e9f5588x81f8c387aef23c6c@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20080512163107.GA19052@deprecation.cyrius.com> <90edad820805121246o328d1cdaide88594ce9d328b7@mail.gmail.com> <20080528071240.GB10393@deprecation.cyrius.com> <20080528085033.GA6250@alpha.franken.de> <20080528151025.GA15325@deprecation.cyrius.com> <20080529200506.GA27783@alpha.franken.de> <90edad820806020840m2e9f5588x81f8c387aef23c6c@mail.gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips > > So, you might want to add > > Tested-by: Dmitri Vorobiev Ouch, I made a typo. Corrected version: Tested-by: Dmitri Vorobiev P.S. Sorry for a duplicate post, but we're currently having some problems with email at linux-mips.org... Dmitri > From mano@roarinelk.homelinux.net Tue Jun 3 15:12:12 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Jun 2008 15:12:14 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:33197 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20032857AbYFCOMM (ORCPT ); Tue, 3 Jun 2008 15:12:12 +0100 Received: (qmail 24431 invoked by uid 1000); 3 Jun 2008 16:12:10 +0200 Date: Tue, 3 Jun 2008 16:12:10 +0200 From: Manuel Lauss To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: make r4k clocksource/clockevent usable in other codepaths Message-ID: <20080603141210.GA21501@roarinelk.homelinux.net> References: <20080528122838.GA5976@roarinelk.homelinux.net> <4842E2C0.1020106@ru.mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4842E2C0.1020106@ru.mvista.com> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips hi Sergei, > Manuel Lauss wrote: >> Make the r4k cp0 counter clocksource and clockevent modules >> library code so it may be used e.g. as a fallback in case other >> clocksources/events aren't available. >> >> Signed-off-by: Manuel Lauss >> > [...] > >> diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h >> index d3bd5c5..01a4c93 100644 >> --- a/include/asm-mips/time.h >> +++ b/include/asm-mips/time.h >> @@ -50,27 +50,35 @@ extern int (*perf_irq)(void); >> /* >> * Initialize the calling CPU's compare interrupt as clockevent device >> */ >> -#ifdef CONFIG_CEVT_R4K >> -extern int mips_clockevent_init(void); >> +#ifdef CONFIG_CEVT_R4K_LIB >> extern unsigned int __weak get_c0_compare_int(void); >> -#else >> +extern int r4k_clockevent_init(void); >> +#endif >> + >> static inline int mips_clockevent_init(void) >> { >> +#ifdef CONFIG_CEVT_R4K >> + return r4k_clockevent_init(); >> +#else >> return -ENXIO; >> -} >> #endif >> +} >> /* >> * Initialize the count register as a clocksource >> */ >> -#ifdef CONFIG_CEVT_R4K >> -extern int init_mips_clocksource(void); >> -#else >> +#ifdef CONFIG_CSRC_R4K_LIB >> +extern int init_r4k_clocksource(void); >> +#endif >> > > Hm, does it make sense to hedge ''extern' declaration by #ifdef's? To be honest, I didn't think about that (and I don't know the exact semantics of 'extern' either), I just followed the original code ;-) MfG, Manuel Lauss From bunk@kernel.org Wed Jun 4 17:00:32 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Jun 2008 17:00:34 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:16577 "EHLO p549F73B8.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20038175AbYFDQAc (ORCPT ); Wed, 4 Jun 2008 17:00:32 +0100 Received: from smtp5.pp.htv.fi ([213.243.153.39]:28311 "EHLO smtp5.pp.htv.fi") by lappi.linux-mips.net with ESMTP id S1097866AbYFDQAb (ORCPT ); Wed, 4 Jun 2008 18:00:31 +0200 Received: from cs181133002.pp.htv.fi (cs181133002.pp.htv.fi [82.181.133.2]) by smtp5.pp.htv.fi (Postfix) with ESMTP id 5D65A5BC046; Wed, 4 Jun 2008 19:00:25 +0300 (EEST) Date: Wed, 4 Jun 2008 18:59:51 +0300 From: Adrian Bunk To: Marc St-Jean Cc: linux-mips@linux-mips.org, Brian_Oostenbrink@pmc-sierra.com Subject: Status of PMC MSP71xx support? Message-ID: <20080604155951.GC4189@cs181133002.pp.htv.fi> References: <310540780805210817q177554acof9c5a60129a6a824@mail.gmail.com> <310540780805210834v745502e9i308cbebfe0a0167e@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <310540780805210834v745502e9i308cbebfe0a0167e@mail.gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bunk@kernel.org Precedence: bulk X-list: linux-mips On Wed, May 21, 2008 at 09:34:35AM -0600, Marc St-Jean wrote: > Hi Adrian, Hi Marc, > It did compile with all patches, but at the time I moved on from PMC, > several drivers patches needed more work and had not yet been accepted > in the upstream kernel tree. > > The contact at PMC that took over the work was Brian Oostenbrink, I'm > forwarding this so he can answer you question. thanks for this information. Brian, are you or someone else working on getting all required stuff for making it usable into the kernel in the forseeable future? In the current state what is shipped in the kernel tree is useless and a good candidate for removal. > Marc cu Adrian -- "Is there not promise of rain?" Ling Tan asked suddenly out of the darkness. There had been need of rain for many days. "Only a promise," Lao Er said. Pearl S. Buck - Dragon Seed From Rod_Sillett@pmc-sierra.com Thu Jun 5 02:35:58 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 02:36:00 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:2222 "EHLO bby1mta03.pmc-sierra.bc.ca") by ftp.linux-mips.org with ESMTP id S20021633AbYFEBf6 convert rfc822-to-8bit (ORCPT ); Thu, 5 Jun 2008 02:35:58 +0100 Received: from bby1mta03.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id 23FE510713A7; Wed, 4 Jun 2008 18:37:32 -0700 (PDT) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (BBY1EXG02.pmc-sierra.bc.ca [216.241.231.167]) by bby1mta03.pmc-sierra.bc.ca (Postfix) with SMTP id ED26410713DF; Wed, 4 Jun 2008 18:37:31 -0700 (PDT) Received: from BBY1EXM09.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.157]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.3959); Wed, 4 Jun 2008 18:36:12 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 8BIT Subject: RE: Status of PMC MSP71xx support? Date: Wed, 4 Jun 2008 18:35:08 -0700 Message-ID: <92F38F1DC286C7409E29F0C6FBFB6E4F0134B636@BBY1EXM09.pmc_nt.nt.pmc-sierra.bc.ca> In-Reply-To: <8A9D56C5E50F774BABE033F1710B35760138FF57@BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Status of PMC MSP71xx support? Thread-Index: AcjGXDI8bKZ0Up11QmqlnFytGPSKmQAA6eagABK41GA= References: <8A9D56C5E50F774BABE033F1710B35760138FF57@BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca> From: "Rod Sillett" To: Cc: "Brian Oostenbrink" , X-OriginalArrivalTime: 05 Jun 2008 01:36:12.0996 (UTC) FILETIME=[89E10840:01C8C6AC] X-PMX-Version: 5.4.2.338381, Antispam-Engine: 2.6.0.325393, Antispam-Data: 2008.6.4.181942 X-PMC-SpamCheck: Gauge=IIIIIII, Probability=7%, Report='BODY_SIZE_1000_LESS 0, BODY_SIZE_300_399 0, BODY_SIZE_5000_LESS 0, __BOUNCE_CHALLENGE_SUBJ 0, __CT 0, __CTE 0, __CT_TEXT_PLAIN 0, __HAS_MSGID 0, __IMS_MSGID 0, __MIME_TEXT_ONLY 0, __MIME_VERSION 0, __SANE_MSGID 0' Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19400 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Rod_Sillett@pmc-sierra.com Precedence: bulk X-list: linux-mips Hi Adrian, Yes, the msp71xx platform is still actively supported by PMC. I am responsible for merging the changes back to the community. As a first step (a learning experience for me) I was planning to submit updated GPIO and LED support in the next few weeks. Best Regards, Rod Sillett From chetannanda@gmail.com Thu Jun 5 11:03:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 11:03:28 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:14056 "EHLO ti-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20021862AbYFEKDZ (ORCPT ); Thu, 5 Jun 2008 11:03:25 +0100 Received: by ti-out-0910.google.com with SMTP id i7so152191tid.20 for ; Thu, 05 Jun 2008 03:02:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:mime-version:content-type:content-transfer-encoding :content-disposition; bh=YVVvVbAjpysHLwtKLqpRAYDXH17e/Z/OchQz59UNc0Y=; b=JYhLPQX1sVbxKHM/FVHoidj3r6vYn6GSb/BKeD/XZ+68zozxBQtBT6c6VE/h/QN2LQ g/IEw8LeSrsUlIuxZo3AKrzpUoPO1pYq2c6DOOADpFq2CNm/9Q+CUdERaNo8XK9Wut2p zfLwaUCDN7kscSsLnpQkVEhY+NO1zILGLB8Po= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:mime-version:content-type :content-transfer-encoding:content-disposition; b=u/g7LmSRHc0ZGThd0MA4Cnd1YLn0dFrYlGSpOZxPmy9GkbXNJ/K7+HSkGXKb19yR7l qWzh0pU5vXkCKY1F6ghJ2Z+RgCVCiMMsfpRKxx4EdvPIraIhGrhsdNpIYqTqI3gMzZdH KFPErGxm2tS8Ta+tTmhTToAc82D4TjNYk/cFk= Received: by 10.110.15.9 with SMTP id 9mr333229tio.44.1212660162689; Thu, 05 Jun 2008 03:02:42 -0700 (PDT) Received: by 10.110.11.2 with HTTP; Thu, 5 Jun 2008 03:02:42 -0700 (PDT) Message-ID: <7f245da80806050302m6b449e6m1f84dc7ef7efff46@mail.gmail.com> Date: Thu, 5 Jun 2008 15:32:42 +0530 From: "Chetan Nanda" To: linux-mips@linux-mips.org Subject: understanding head.S MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19401 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chetannanda@gmail.com Precedence: bulk X-list: linux-mips Hi All, I was reading the boot code for MIPS. in head.S file before jumping to 'start_kernel' it calculate the stack pointer address as follow: " PTR_LA $28, init_thread_union PTR_ADDIU sp, $28, _THREAD_SIZE - 32 set_saved_sp sp, t0, t1 PTR_SUBU sp, 4 * SZREG # init stack pointer " Can anyone please explains me this 4 lines of code? Why ' _THREAD_SIZE - 32' is added in 'sp' ? What 'set_saved_sp' will do ? and then why we subtract '4 * SZREG' from 'sp' ? Please hep me to understand this code better. Thanks, Chetan Nanda From tbm@cyrius.com Thu Jun 5 12:12:05 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 12:12:07 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:41888 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S20022077AbYFELMF (ORCPT ); Thu, 5 Jun 2008 12:12:05 +0100 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 55396D8DD; Thu, 5 Jun 2008 11:12:03 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 1B785150F70; Thu, 5 Jun 2008 13:11:49 +0200 (CEST) Date: Thu, 5 Jun 2008 13:11:48 +0200 From: Martin Michlmayr To: Ralf Baechle Cc: Dmitri Vorobiev , Theodore Tso , linux-mips@linux-mips.org, linux-ext4@vger.kernel.org Subject: Re: ext4dev build failure on mips: "empty_zero_page" undefined Message-ID: <20080605111148.GA4483@deprecation.cyrius.com> References: <20080512130604.GA15008@deprecation.cyrius.com> <90edad820805120654n50f7a00cm3c7b4a4f9346d5ea@mail.gmail.com> <20080512143426.GB7029@mit.edu> <90edad820805120746l61e67362vbd177d63e8b05dc8@mail.gmail.com> <20080513045028.GC22226@linux-mips.org> <20080528070637.GA10393@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080528070637.GA10393@deprecation.cyrius.com> User-Agent: Mutt/1.5.17+20080114 (2008-01-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19402 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips * Martin Michlmayr [2008-05-28 09:06]: > * Ralf Baechle [2008-05-13 05:50]: > > I prefer to do it myself so I can apply it at the same time to the MIPS > > -stable branches. > > > > I'm a little irriated that this thread seems to be only about > > empty_zero_page but apparently not zero_page_mask? empty_zero_page is > > actualy an array of pages on MIPS and ZERO_PAGE() will pick the right one > > for a particular user space mapping based on the virtual address but > > ZERO_PAGE() also references zero_page_mask. So I sense more brokenness > > here. > > Just as a reminder, this issue is still there (at least with rc4). Still present in rc5. -- Martin Michlmayr http://www.cyrius.com/ From wangbj@dslab.lzu.edu.cn Thu Jun 5 12:15:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 12:15:40 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:42976 "EHLO mail.dslab.lzu.edu.cn") by ftp.linux-mips.org with ESMTP id S20022083AbYFELPh (ORCPT ); Thu, 5 Jun 2008 12:15:37 +0100 Received: from [192.168.2.104] (unknown [202.201.14.140]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by mail.dslab.lzu.edu.cn (Postfix) with ESMTP id 739CB84A; Thu, 5 Jun 2008 19:15:29 +0800 (CST) Subject: Re: understanding head.S From: "Wang, Baojun" Reply-To: wangbj@dslab.lzu.edu.cn To: Chetan Nanda , linux-mips@linux-mips.org In-Reply-To: <7f245da80806050302m6b449e6m1f84dc7ef7efff46@mail.gmail.com> References: <7f245da80806050302m6b449e6m1f84dc7ef7efff46@mail.gmail.com> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="=-csPKN7XTP6IfPmq+Hyyb" Organization: DSLab, Lanzhou University Date: Thu, 05 Jun 2008 19:15:24 +0800 Message-Id: <1212664525.24330.22.camel@localhost.dslab> Mime-Version: 1.0 X-Mailer: Evolution 2.22.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19403 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wangbj@dslab.lzu.edu.cn Precedence: bulk X-list: linux-mips --=-csPKN7XTP6IfPmq+Hyyb Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A8 2008-06-05=E5=9B=9B=E7=9A=84 15:32 +0530=EF=BC=8CChetan Nanda=E5= =86=99=E9=81=93=EF=BC=9A > Hi All, > I was reading the boot code for MIPS. > in head.S file before jumping to 'start_kernel' it calculate the stack > pointer address as follow: >=20 > " > PTR_LA $28, init_thread_union > PTR_ADDIU sp, $28, _THREAD_SIZE - 32 make sp point to the stack top so that we can allocate stack space later, -32 is a reserved area for local variable, saved GPR, arguments (function stack frame).. due to the abi > set_saved_sp sp, t0, t1 set_saved_sp is defined (as a assembler macro) in include/asm-mips/stackframe.h (if you're using vim, I think it will be easy to use vim with cscope..) > PTR_SUBU sp, 4 * SZREG # init stack pointer SZREG is defined to the general purpose register size, it is 32bit in MIPS32 and 64bit in MIPS64, so the last line allocates 16/32 bytes to build a stack frame.. You could refer to the MIPS ABI if you need further information (the kernel don't follow the standard ABI all the time though..) >=20 > Can anyone please explains me this 4 lines of code? > Why ' _THREAD_SIZE - 32' is added in 'sp' ? > What 'set_saved_sp' will do ? > and then why we subtract '4 * SZREG' from 'sp' ? >=20 > Please hep me to understand this code better. >=20 > Thanks, > Chetan Nanda >=20 --=20 Wang, Baojun Lanzhou Univers= ity Distributed & Embedded System Lab http://dslab.lzu.edu= .cn School of Information Science and Engeneering wangbj@dslab.lzu.edu= .cn Tianshui South Road 222. Lanzhou 730000 .P.R.Ch= ina Tel: +86-931-8912025 Fax: +86-931-8912= 022 --=-csPKN7XTP6IfPmq+Hyyb Content-Type: application/pgp-signature; name=signature.asc Content-Description: =?gb2312?Q?=D5=E2=CA=C7=D0=C5=BC=FE=B5=C4=CA=FD=D7=D6=C7=A9?= =?gb2312?Q?=C3=FB=B2=BF=B7=D6?= -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iEYEABECAAYFAkhHyswACgkQIuIOr7tpgg3Y8ACfbwWAK3ZVgIuY7nBSYwTqWioE 0PkAoKkWiav4TVeEgmAIn8+s40/FIJi/ =ywvl -----END PGP SIGNATURE----- --=-csPKN7XTP6IfPmq+Hyyb-- From dmitri.vorobiev@movial.fi Thu Jun 5 12:22:58 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 12:23:01 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:54701 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S20022095AbYFELW6 (ORCPT ); Thu, 5 Jun 2008 12:22:58 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 1ED78C803F; Thu, 5 Jun 2008 14:22:57 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id ejIQC5ZGtISp; Thu, 5 Jun 2008 14:22:57 +0300 (EEST) Received: from sd048.hel.movial.fi (sd048.hel.movial.fi [172.17.49.48]) by smtp.movial.fi (Postfix) with ESMTP id 012E4C801D; Thu, 5 Jun 2008 14:22:57 +0300 (EEST) Subject: Re: ext4dev build failure on mips: "empty_zero_page" undefined From: Dmitri Vorobiev To: Martin Michlmayr Cc: Ralf Baechle , Dmitri Vorobiev , Theodore Tso , linux-mips@linux-mips.org, linux-ext4@vger.kernel.org In-Reply-To: <20080605111148.GA4483@deprecation.cyrius.com> References: <20080512130604.GA15008@deprecation.cyrius.com> <90edad820805120654n50f7a00cm3c7b4a4f9346d5ea@mail.gmail.com> <20080512143426.GB7029@mit.edu> <90edad820805120746l61e67362vbd177d63e8b05dc8@mail.gmail.com> <20080513045028.GC22226@linux-mips.org> <20080528070637.GA10393@deprecation.cyrius.com> <20080605111148.GA4483@deprecation.cyrius.com> Content-Type: text/plain Organization: Movial Creative Technologies Date: Thu, 05 Jun 2008 14:22:57 +0300 Message-Id: <1212664977.4840.6.camel@sd048.hel.movial.fi> Mime-Version: 1.0 X-Mailer: Evolution 2.6.3 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19404 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips On Thu, 2008-06-05 at 13:11 +0200, Martin Michlmayr wrote: > * Martin Michlmayr [2008-05-28 09:06]: > > * Ralf Baechle [2008-05-13 05:50]: > > > I prefer to do it myself so I can apply it at the same time to the MIPS > > > -stable branches. > > > > > > I'm a little irriated that this thread seems to be only about > > > empty_zero_page but apparently not zero_page_mask? empty_zero_page is > > > actualy an array of pages on MIPS and ZERO_PAGE() will pick the right one > > > for a particular user space mapping based on the virtual address but > > > ZERO_PAGE() also references zero_page_mask. So I sense more brokenness > > > here. > > > > Just as a reminder, this issue is still there (at least with rc4). > > Still present in rc5. It looks like the discussion related to this issue has faded out. Ralf seemed to have some objections to using ZERO_PAGE() outside of the context of getting a user-mapped page, but I think that ext4 driver is still doing that. Ralf, will it be possible to use the patch I sent earlier as a temporary solution? Just to make sure the kernel builds? Thanks, Dmitri > From dmitri.vorobiev@movial.fi Thu Jun 5 12:42:17 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 12:42:19 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:65196 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S20022130AbYFELmR (ORCPT ); Thu, 5 Jun 2008 12:42:17 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id AAD28C8044 for ; Thu, 5 Jun 2008 14:42:15 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id x6XOKoP+Pym4 for ; Thu, 5 Jun 2008 14:42:15 +0300 (EEST) Received: from [172.17.49.48] (sd048.hel.movial.fi [172.17.49.48]) by smtp.movial.fi (Postfix) with ESMTP id 8296FC801D for ; Thu, 5 Jun 2008 14:42:15 +0300 (EEST) Message-ID: <4847D117.2090302@movial.fi> Date: Thu, 05 Jun 2008 14:42:15 +0300 From: Dmitri Vorobiev Organization: Movial Creative Technologies User-Agent: Icedove 1.5.0.14eol (X11/20080509) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Please let me try if this works now... Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19405 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips Sorry for extra traffic, I'm just testing if I can send messages to this list. Dmitri From tbm@cyrius.com Thu Jun 5 12:58:19 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 12:58:21 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:29862 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S20022151AbYFEL6T (ORCPT ); Thu, 5 Jun 2008 12:58:19 +0100 Received: by sorrow.cyrius.com (Postfix, from userid 10) id BD61FD8DE; Thu, 5 Jun 2008 11:58:16 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 4BDA0150F76; Thu, 5 Jun 2008 13:57:59 +0200 (CEST) Date: Thu, 5 Jun 2008 13:57:59 +0200 From: Martin Michlmayr To: Adrian Bunk Cc: Chris Dearman , Atsushi Nemoto , Ralf Baechle , Thomas Bogendoerfer , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: mips/kernel/traps.c build error Message-ID: <20080605115759.GA5043@deprecation.cyrius.com> References: <20080525164311.GB1791@cs181133002.pp.htv.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080525164311.GB1791@cs181133002.pp.htv.fi> User-Agent: Mutt/1.5.17+20080114 (2008-01-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19406 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips * Adrian Bunk [2008-05-25 19:43]: > /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/mips/kernel/traps.c: In function 'show_raw_backtrace': > /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/mips/kernel/traps.c:92: error: cast from pointer to integer of different size > make[2]: *** [arch/mips/kernel/traps.o] Error 1 > > <-- snip --> > > "[MIPS] Fix check for valid stack pointer during backtrace" in the mips > tree fixes it, and should therefore also go into 2.6.26. It's still not in mainline as of rc5. -- Martin Michlmayr http://www.cyrius.com/ From blf.ireland@gmail.com Thu Jun 5 13:47:01 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 13:47:04 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:62408 "EHLO rv-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S20022188AbYFEMrB (ORCPT ); Thu, 5 Jun 2008 13:47:01 +0100 Received: by rv-out-0708.google.com with SMTP id c5so564259rvf.24 for ; Thu, 05 Jun 2008 05:46:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:sender :to:subject:mime-version:content-type:content-transfer-encoding :content-disposition:x-google-sender-auth; bh=lQNYOKFaiqU3+K73qp+i02KEGERjGYqERt3abZ9aXdQ=; b=r28VmdN49d2uyfxhc5cyj8+u1yd5dhfkEFke+/ZRKEm1m/t7jpj+yU00sqNUO5QAMM ljdAmRNdRhc4BqpR1obsQFcrXtcDmft3cNeDmyUq+Wsqa/iUfLAwvMsl3LMiSlXusY0S JDKP74bgVehwAZg3/TTkOVAeUYBjiP3NYQDUM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:sender:to:subject:mime-version:content-type :content-transfer-encoding:content-disposition:x-google-sender-auth; b=kfe5n4do21UwnuGQl8I3ddXxkCfA1S/AjFSzQ3zGEUao7LsXGBixVbTe8VGK3bws7Z 3WVKs1Z4MAnpkRKHKN6OCp0sqZLoZO/OBYE7fS10OQqjZsziBXaULHvu14M3fTzFO0PP im9+Ope5/zl5kEtrlpJkLdbBLjtyTTW5aZ7jI= Received: by 10.141.175.5 with SMTP id c5mr823116rvp.54.1212670001034; Thu, 05 Jun 2008 05:46:41 -0700 (PDT) Received: by 10.141.197.19 with HTTP; Thu, 5 Jun 2008 05:46:40 -0700 (PDT) Message-ID: Date: Thu, 5 Jun 2008 14:46:40 +0200 From: "Brian Foster" To: linux-mips@linux-mips.org Subject: [Q] Pre-built cross-compilers for little-endian MIPS-Linux kernel (SDE-Lite vs? mipsel-linux) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline X-Google-Sender-Auth: 86461a57dfdfe4e1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19407 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips I'm confused about pre-built cross-compiling tool-chains for building the MIPS-Linux kernel. (Please note my question is confined to building the kernel, cross.) My Host is x86 running Linux. My Target is an embedded SoC using the 4KSd core, and is little-endian. Linux (of the 2.6.20 vintage) has been ported to the SoC, using mipsel-sdelinux-V6.04.00-4 to compile the kernel. The development system also includes 5.03 SDE-Lite, albeit I'm not too clear what that's used for: I know the debugger, sde-gdb, is used with the FS2 EJTAG Probe, but am uncertain if anything else is actually used .... Anyways, that's all getting a bit old. Hence, in time, the kernel will be up-reved (to at least 2.6.24). I also want to use later toolchain(s?), and I am currently trying to work out what's what, with the goal (if possible) of using them to built the current (2.6.20-ish kernel). The http://www.linux-mips.org/wiki/MIPS_SDE_Installation page is rather confusing, talking first about SDE 6.x, and then jumping into a discussion of cross tool-chains. Whilst I assume I can use the most recent mipsel-linux (mipsel-sdelinux-v6.05.00-4) to built the kernel, is it possible to use the most recent SDE-Lite (v6.06.01) to build the Linux kernel? If so, what do I need to tweak so `sde-gcc' (with appropriate magic) is used instead of `mipsel-linux-gcc' (with whatever magic it's using)? cheers! -blf- -- "How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools." | http://www.stopesso.com From tytso@MIT.EDU Thu Jun 5 19:39:11 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 19:39:13 +0100 (BST) Received: from BISCAYNE-ONE-STATION.MIT.EDU ([18.7.7.80]:39309 "EHLO biscayne-one-station.mit.edu") by ftp.linux-mips.org with ESMTP id S20024061AbYFESjL (ORCPT ); Thu, 5 Jun 2008 19:39:11 +0100 Received: from outgoing.mit.edu (OUTGOING-AUTH.MIT.EDU [18.7.22.103]) by biscayne-one-station.mit.edu (8.13.6/8.9.2) with ESMTP id m55IcvTU003603; Thu, 5 Jun 2008 14:38:57 -0400 (EDT) Received: from closure.thunk.org (c-98-216-98-217.hsd1.ma.comcast.net [98.216.98.217]) (authenticated bits=0) (User authenticated as tytso@ATHENA.MIT.EDU) by outgoing.mit.edu (8.13.6/8.12.4) with ESMTP id m55IcsjQ008235 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 5 Jun 2008 14:38:55 -0400 (EDT) Received: from tytso by closure.thunk.org with local (Exim 4.67) (envelope-from ) id 1K4KMQ-0007dv-Eh; Thu, 05 Jun 2008 14:38:54 -0400 Date: Thu, 5 Jun 2008 14:38:54 -0400 From: Theodore Tso To: Dmitri Vorobiev Cc: Martin Michlmayr , Ralf Baechle , Dmitri Vorobiev , linux-mips@linux-mips.org, linux-ext4@vger.kernel.org Subject: Re: ext4dev build failure on mips: "empty_zero_page" undefined Message-ID: <20080605183854.GN25477@mit.edu> References: <20080512130604.GA15008@deprecation.cyrius.com> <90edad820805120654n50f7a00cm3c7b4a4f9346d5ea@mail.gmail.com> <20080512143426.GB7029@mit.edu> <90edad820805120746l61e67362vbd177d63e8b05dc8@mail.gmail.com> <20080513045028.GC22226@linux-mips.org> <20080528070637.GA10393@deprecation.cyrius.com> <20080605111148.GA4483@deprecation.cyrius.com> <1212664977.4840.6.camel@sd048.hel.movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1212664977.4840.6.camel@sd048.hel.movial.fi> User-Agent: Mutt/1.5.15+20070412 (2007-04-11) X-Scanned-By: MIMEDefang 2.42 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19408 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tytso@MIT.EDU Precedence: bulk X-list: linux-mips On Thu, Jun 05, 2008 at 02:22:57PM +0300, Dmitri Vorobiev wrote: > > It looks like the discussion related to this issue has faded out. Ralf > seemed to have some objections to using ZERO_PAGE() outside of the > context of getting a user-mapped page, but I think that ext4 driver is > still doing that. > I thought I had sent a reply indicating that yes, we are using ZERO_PAGE outside of getting a user-mapped page, because this is happening when we need to write zero's to directly to a filesystem block. This case arises when we have a file which contains preallocated space that has not yet been initialized, and the user program seeks into the middle of the unitialized extent range, and writes into the middle of that space. In some cases, it is more efficient to zero out a small range of blocks on disk rather than splitting the extent in the middle. We could explicitly allocate a page, and zero it out, and use it to write zeros from the ext4 filesystem, code, but that seems silly, given that ZERO_PAGE exists and is available on all other architectures. Cristoph Hellwig had complained about the use of ZERO_PAGE, but when I gave him the above explanation, he agreed that this was indeed probably the best way to do things. If you really insist I suppose we could have a MIPS specific patch where we allocate a 4k page and zero it, so we can use it from our kernel code because you don't want to export and make available the ZERO_PAGE that gets used by the rest of the kernel, but that seems awfully silly, and would be a waste of 4k of memory..... Someone from MIPS land would have to test it, as well, as I dont think any of the ext4 developers have access to a MIPS platform. - Ted From daniel.j.laird@googlemail.com Thu Jun 5 20:45:18 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 20:45:24 +0100 (BST) Received: from wx-out-0506.google.com ([66.249.82.230]:24108 "EHLO wx-out-0506.google.com") by ftp.linux-mips.org with ESMTP id S28575944AbYFETpS (ORCPT ); Thu, 5 Jun 2008 20:45:18 +0100 Received: by wx-out-0506.google.com with SMTP id s13so605486wxc.21 for ; Thu, 05 Jun 2008 12:45:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:sender :to:subject:cc:mime-version:content-type:content-transfer-encoding :content-disposition:x-google-sender-auth; bh=8CD9XVpVJqugWOHYmIWZbL6Yz9Jc3aEU8t/JrNA8bQE=; b=daaSKpPkt/8hcPTVqWqu0oq3cCcA4J8UQGMWgnvbMdLf4ZgLJR1m5TbhfNpUTugeM2 p/fhiWe5dV4rBJ61ln+RbG5jriRRoKScXH8RTs9+TNpLfl9J7s/uVS0r5EDbog38Q/Q2 OEhFpt3/3Hr5W7tXY0LZVnw4gustSDZqBb/P0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=message-id:date:from:sender:to:subject:cc:mime-version:content-type :content-transfer-encoding:content-disposition:x-google-sender-auth; b=QP7wielJSj2wl7xLV259Ifj21KSn/LUgQrQRJuBsbtwxXrMPL0UOIz73BP0SPN+ZLp msv0BnvykC179mGNbB3U2qUX0nOEBGamX3eP7mtSoQt7vUBIh5X9TDDj7qI3tPPPOM5a +t89Qn7+Uc+hshUX3CbEywMzSOuAHIJXrxFx4= Received: by 10.90.101.17 with SMTP id y17mr1984877agb.82.1212695113373; Thu, 05 Jun 2008 12:45:13 -0700 (PDT) Received: by 10.90.70.11 with HTTP; Thu, 5 Jun 2008 12:45:13 -0700 (PDT) Message-ID: <64660ef00806051245n5ba8ffc5hece63f743d2e2d01@mail.gmail.com> Date: Thu, 5 Jun 2008 20:45:13 +0100 From: "Daniel Laird" To: linux-mips@linux-mips.org Subject: [PATCH] : Add support for NXP PNX833x (STB222/5) into linux kernel Cc: ralf@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline X-Google-Sender-Auth: b72ba0c454018c89 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19409 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: daniel.j.laird@nxp.com Precedence: bulk X-list: linux-mips Tried to post earlier and did not get through, can send patch file separately if mail server wont accept it. Daniel Laird ------------------------------------------------------ The following patch add support for the NXP PNX833x SOC. More specifically it adds support for the STB222/5 variant. This has I2C support, NAND and onboard ethernet support. SATA, USB, NOR flash, WATCHDOG are all pending patches after I get this in :-). arch/mips/Kconfig | 33 arch/mips/Makefile | 8 arch/mips/configs/pnx8335-stb225_defconfig | 1150 +++++++++++++++++++++ arch/mips/nxp/pnx833x/common/Makefile | 1 arch/mips/nxp/pnx833x/common/gdb_hook.c | 162 +++ arch/mips/nxp/pnx833x/common/interrupts.c | 363 ++++++ arch/mips/nxp/pnx833x/common/platform.c | 337 ++++++ arch/mips/nxp/pnx833x/common/prom.c | 69 + arch/mips/nxp/pnx833x/common/reset.c | 48 arch/mips/nxp/pnx833x/common/setup.c | 63 + arch/mips/nxp/pnx833x/stb22x/Makefile | 1 arch/mips/nxp/pnx833x/stb22x/board.c | 138 ++ drivers/i2c/busses/Kconfig | 12 drivers/i2c/busses/Makefile | 1 drivers/i2c/busses/i2c-pnx0105.c | 328 ++++++ drivers/net/Kconfig | 9 drivers/net/Makefile | 1 drivers/net/ip3902.c | 1534 +++++++++++++++++++++++++++++ include/asm-mips/mach-pnx833x/gpio.h | 171 +++ include/asm-mips/mach-pnx833x/irq.h | 138 ++ include/asm-mips/mach-pnx833x/pnx833x.h | 194 +++ include/asm-mips/mach-pnx833x/war.h | 25 include/linux/i2c-id.h | 1 include/linux/i2c-pnx0105.h | 58 + 24 files changed, 4845 insertions(+) Signed-off-by: daniel.j.laird diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/configs/pnx8335-stb225_defconfig linux-2.6.26-rc4/arch/mips/configs/pnx8335-stb225_defconfig --- linux-2.6.26-rc4.orig/arch/mips/configs/pnx8335-stb225_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/configs/pnx8335-stb225_defconfig 2008-06-04 15:58:03.000000000 +0100 @@ -0,0 +1,1150 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc4 +# Wed Jun 4 15:57:17 2008 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +CONFIG_NXP_STB225=y +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_WR_PPMC is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SOC_PNX833X=y +CONFIG_SOC_PNX8335=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_128=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=128 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +CONFIG_INET_AH=y +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x18000000 +CONFIG_MTD_PHYSMAP_LEN=0x04000000 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +CONFIG_ATA_SFF=y +# CONFIG_SATA_MV is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_IP3902 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_ALGOPCA=y + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_PCA_PLATFORM is not set +CONFIG_I2C_PNX0105=y + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +CONFIG_DVB_CORE=y +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_L64781 is not set +CONFIG_DVB_TDA1004X=y +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_TDA10048 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522 is not set +# CONFIG_DVB_S5H1411 is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_LOGO is not set + +# +# Sound +# +CONFIG_SOUND=m + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_DETECT=y +# CONFIG_SND_PCM_XRUN_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# ALSA MIPS devices +# + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# ALSA SoC audio for Freescale SOCs +# + +# +# SoC Audio for the Texas Instruments OMAP +# + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_CODEPAGE_932=m +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=m +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SAMPLES is not set +CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/Kconfig linux-2.6.26-rc4/arch/mips/Kconfig --- linux-2.6.26-rc4.orig/arch/mips/Kconfig 2008-06-03 10:56:51.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/Kconfig 2008-06-03 17:12:19.000000000 +0100 @@ -311,6 +311,19 @@ select SYS_HAS_CPU_VR41XX select GENERIC_HARDIRQS_NO__DO_IRQ +config NXP_STB220 + bool "NXP STB220 board" + select SOC_PNX833X + help + Support for NXP Semiconductors STB220 Development Board. + +config NXP_STB225 + bool "NXP 225 board" + select SOC_PNX833X + select SOC_PNX8335 + help + Support for NXP Semiconductors STB225 Development Board. + config PNX8550_JBS bool "NXP PNX8550 based JBS board" select PNX8550 @@ -947,6 +960,26 @@ bool select SERIAL_RM9000 +config SOC_PNX833X + bool + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select DMA_NONCOHERENT + select SYS_HAS_EARLY_PRINTK + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ + select SYS_SUPPORTS_KGDB + select GENERIC_GPIO + select CPU_MIPSR2_IRQ_VI + +config SOC_PNX8335 + bool + select SOC_PNX833X + config PNX8550 bool select SOC_PNX8550 diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/Makefile linux-2.6.26-rc4/arch/mips/Makefile --- linux-2.6.26-rc4.orig/arch/mips/Makefile 2008-06-03 10:56:51.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/Makefile 2008-06-03 17:13:03.000000000 +0100 @@ -409,6 +409,14 @@ # load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 +# NXP STB225 +core-$(CONFIG_SOC_PNX833X) += arch/mips/nxp/pnx833x/common/ +cflags-$(CONFIG_SOC_PNX833X) += -Iinclude/asm-mips/mach-pnx833x +libs-$(CONFIG_NXP_STB220) += arch/mips/nxp/pnx833x/stb22x/ +load-$(CONFIG_NXP_STB220) += 0xffffffff80001000 +libs-$(CONFIG_NXP_STB225) += arch/mips/nxp/pnx833x/stb22x/ +load-$(CONFIG_NXP_STB225) += 0xffffffff80001000 + # # Common NXP PNX8550 # diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/gdb_hook.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/gdb_hook.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/gdb_hook.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/gdb_hook.c 2008-06-05 11:16:42.000000000 +0100 @@ -0,0 +1,162 @@ +/* + * gdb_hook.c: gdb hook for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * Based on PNX8550. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/*********************************************** +* INCLUDE FILES * +************************************************/ + +#include +#include + +/*********************************************** +* LOCAL MACROS * +************************************************/ + +#define UART0 (unsigned char *)PNX833X_UART0_PORTS_START +#define UART1 (unsigned char *)PNX833X_UART1_PORTS_START + +/*********************************************** +* LOCAL TYPEDEFS * +************************************************/ + +/*********************************************** +* STATIC FUNCTION PROTOTYPES * +************************************************/ + +/*********************************************** +* STATIC DATA * +************************************************/ + +static unsigned char *kgdb_uart = UART1; +static unsigned char *console_uart = UART0; +static volatile int delay_count; + +/*********************************************** +* EXPORTED DATA * +************************************************/ + +/*********************************************** +* FUNCTION IMPLEMENTATION * +************************************************/ + +static unsigned int serial_in(unsigned char *base_address, int offset) +{ + return *((unsigned int volatile *)(base_address + offset)); +} + +static void serial_out(unsigned char *base_address, int offset, int value) +{ + *((unsigned int volatile *)(base_address + offset)) = value; +} + +static void do_delay(void) +{ + int i; + for (i = 0; i < 10000; i++) + delay_count++; +} + +static int put_char(unsigned char *base_address, char c) +{ + /* Wait for TX to be ready */ + while (((serial_in(base_address, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO) >> 16) > 15) + do_delay(); + + /* Send the next character */ + serial_out(base_address, PNX8XXX_FIFO, c); + serial_out(base_address, PNX8XXX_ICLR, PNX8XXX_UART_INT_TX); + + return 1; +} + +static char get_char(unsigned char *base_address) +{ + char output; + + /* Wait for RX to be ready */ + while ((serial_in(base_address, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_RXFIFO) == 0) + do_delay(); + + /* Get the character */ + output = serial_in(base_address, PNX8XXX_FIFO) & 0xFF; + + /* Move onto the next character in the buffer */ + serial_out(base_address, PNX8XXX_LCR, serial_in(base_address, PNX8XXX_LCR) | PNX8XXX_UART_LCR_RX_NEXT); + serial_out(base_address, PNX8XXX_ICLR, PNX8XXX_UART_INT_RX); + + return output; +} + +static void serial_init(unsigned char *base_address) +{ + serial_out(base_address, PNX8XXX_LCR, PNX8XXX_UART_LCR_8BIT | PNX8XXX_UART_LCR_TX_RST | PNX8XXX_UART_LCR_RX_RST); + serial_out(base_address, PNX8XXX_MCR, PNX8XXX_UART_MCR_DTR | PNX8XXX_UART_MCR_RTS); + serial_out(base_address, PNX8XXX_BAUD, 1); /* 115200 Baud */ + serial_out(base_address, PNX8XXX_CFG, 0x00060030); + serial_out(base_address, PNX8XXX_ICLR, -1); + serial_out(base_address, PNX8XXX_IEN, 0); +} + +static void setup_serial_output(void) +{ + static bool initialised; + if (!initialised) { + serial_init(kgdb_uart); + serial_init(console_uart); + initialised = true; + } +} + +int rs_kgdb_hook(int tty_no, int speed) +{ + kgdb_uart = tty_no ? UART1 : UART0; + console_uart = tty_no ? UART0 : UART1; + + setup_serial_output(); + + return speed; +} + +int prom_putchar(char c) +{ + setup_serial_output(); + return put_char(console_uart, c); +} + +char prom_getchar(void) +{ + setup_serial_output(); + return get_char(console_uart); +} + +int put_debug_char(char c) +{ + setup_serial_output(); + return put_char(kgdb_uart, c); +} + +char get_debug_char(void) +{ + setup_serial_output(); + return get_char(kgdb_uart); +} diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/interrupts.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/interrupts.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/interrupts.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/interrupts.c 2008-06-05 11:44:06.000000000 +0100 @@ -0,0 +1,363 @@ +/* + * interrupts.c: Interrupt mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] = +{ + 0, /* unused */ + 4, /* PNX833X_PIC_I2C0_INT 1 */ + 4, /* PNX833X_PIC_I2C1_INT 2 */ + 1, /* PNX833X_PIC_UART0_INT 3 */ + 1, /* PNX833X_PIC_UART1_INT 4 */ + 6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */ + 6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */ + 7, /* PNX833X_PIC_GPIO_INT 7 */ + 4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */ + 5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */ + 4, /* PNX833X_PIC_CONFIG_INT 10 */ + 4, /* PNX833X_PIC_AOI_INT 11 */ + 9, /* PNX833X_PIC_SYNC_INT 12 */ + 9, /* PNX8335_PIC_SATA_INT 13 */ + 4, /* PNX833X_PIC_OSD_INT 14 */ + 9, /* PNX833X_PIC_DISP1_INT 15 */ + 4, /* PNX833X_PIC_DEINTERLACER_INT 16 */ + 9, /* PNX833X_PIC_DISPLAY2_INT 17 */ + 4, /* PNX833X_PIC_VC_INT 18 */ + 4, /* PNX833X_PIC_SC_INT 19 */ + 9, /* PNX833X_PIC_IDE_INT 20 */ + 9, /* PNX833X_PIC_IDE_DMA_INT 21 */ + 6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */ + 6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */ + 4, /* PNX833X_PIC_SGDX_DMA_INT 24 */ + 4, /* PNX833X_PIC_TS_OUT_INT 25 */ + 4, /* PNX833X_PIC_IR_INT 26 */ + 3, /* PNX833X_PIC_VMSP1_INT 27 */ + 3, /* PNX833X_PIC_VMSP2_INT 28 */ + 4, /* PNX833X_PIC_PIBC_INT 29 */ + 4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */ + 4, /* PNX833X_PIC_SGDX_TPD_INT 31 */ + 5, /* PNX833X_PIC_USB_INT 32 */ + 4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */ + 4, /* PNX833X_PIC_CLOCK_INT 34 */ + 4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */ + 4, /* PNX833X_PIC_VMSP_DMA_INT 36 */ +#if defined(CONFIG_SOC_PNX8335) + 4, /* PNX8335_PIC_MIU_INT 37 */ + 4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */ + 9, /* PNX8335_PIC_SYNC_HD_INT 39 */ + 9, /* PNX8335_PIC_DISP_HD_INT 40 */ + 9, /* PNX8335_PIC_DISP_SCALER_INT 41 */ + 4, /* PNX8335_PIC_OSD_HD1_INT 42 */ + 4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */ + 4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */ + 4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */ + 4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */ + 4, /* PNX8335_PIC_DENC_TTX_INT 47 */ + 4, /* PNX8335_PIC_MMI_SIF0_INT 48 */ + 4, /* PNX8335_PIC_MMI_SIF1_INT 49 */ + 4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */ + 4, /* PNX8335_PIC_PIBCS_INT 51 */ + 12, /* PNX8335_PIC_ETHERNET_INT 52 */ + 3, /* PNX8335_PIC_VMSP1_0_INT 53 */ + 3, /* PNX8335_PIC_VMSP1_1_INT 54 */ + 4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */ + 4, /* PNX8335_PIC_TDGR_DE_INT 56 */ + 4, /* PNX8335_PIC_IR1_IRQ_INT 57 */ +#endif +}; + +static void pic_dispatch(void) +{ + unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC); + + if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) { + unsigned long priority = PNX833X_PIC_INT_PRIORITY; + PNX833X_PIC_INT_PRIORITY = irq_prio[irq]; + + if (irq == PNX833X_PIC_GPIO_INT) { + unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE; + int pin; + while ((pin = ffs(mask & 0xffff))) { + pin -= 1; + do_IRQ(PNX833X_GPIO_IRQ_BASE + pin); + mask &= ~(1 << pin); + } + } else { + do_IRQ(irq + PNX833X_PIC_IRQ_BASE); + } + + PNX833X_PIC_INT_PRIORITY = priority; + } else { + printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq); + } +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & STATUSF_IP4) + pic_dispatch(); + else if (pending & STATUSF_IP7) + do_IRQ(PNX833X_TIMER_IRQ); + else + spurious_interrupt(); +} + +static inline void pnx833x_hard_enable_pic_irq(unsigned int irq) +{ + /* Currently we do this by setting IRQ priority to 1. + If priority support is being implemented, 1 should be repalced + by a better value. */ + PNX833X_PIC_INT_REG(irq) = irq_prio[irq]; +} + +static inline void pnx833x_hard_disable_pic_irq(unsigned int irq) +{ + /* Disable IRQ by writing setting it's priority to 0 */ + PNX833X_PIC_INT_REG(irq) = 0; +} + +static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */ +#define IRQFLAG_STARTED 1 +#define IRQFLAG_DISABLED 2 + +static DEFINE_SPINLOCK(irq_lock); + +static unsigned int pnx833x_startup_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&irq_lock, flags); + + irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */ + pnx833x_hard_enable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&irq_lock, flags); + return 0; +} + +static void pnx833x_shutdown_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&irq_lock, flags); + + irqflags[pic_irq] = 0; /* not started */ + pnx833x_hard_disable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&irq_lock, flags); +} + +static void pnx833x_enable_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&irq_lock, flags); + + irqflags[pic_irq] &= ~IRQFLAG_DISABLED; + if (irqflags[pic_irq] == IRQFLAG_STARTED) + pnx833x_hard_enable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&irq_lock, flags); +} + +static void pnx833x_disable_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&irq_lock, flags); + + irqflags[pic_irq] |= IRQFLAG_DISABLED; + pnx833x_hard_disable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&irq_lock, flags); +} + +static void pnx833x_ack_pic_irq(unsigned int irq) +{ +} + +static void pnx833x_end_pic_irq(unsigned int irq) +{ +} + +static DEFINE_SPINLOCK(gpio_irq_lock); + +static unsigned int pnx833x_startup_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&gpio_irq_lock, flags); + gpio_enable_irq(pin); + spin_unlock_irqrestore(&gpio_irq_lock, flags); + return 0; +} + +static void pnx833x_enable_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&gpio_irq_lock, flags); + gpio_enable_irq(pin); + spin_unlock_irqrestore(&gpio_irq_lock, flags); +} + +static void pnx833x_disable_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&gpio_irq_lock, flags); + gpio_disable_irq(pin); + spin_unlock_irqrestore(&gpio_irq_lock, flags); +} + +static void pnx833x_ack_gpio_irq(unsigned int irq) +{ +} + +static void pnx833x_end_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&gpio_irq_lock, flags); + gpio_clear_irq(pin); + spin_unlock_irqrestore(&gpio_irq_lock, flags); +} + +static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + int gpio_mode; + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + gpio_mode = GPIO_INT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + gpio_mode = GPIO_INT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + gpio_mode = GPIO_INT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + gpio_mode = GPIO_INT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + gpio_mode = GPIO_INT_LEVEL_LOW; + break; + default: + gpio_mode = GPIO_INT_NONE; + break; + } + + gpio_setup_irq(gpio_mode, pin); + + return 0; +} + +static struct irq_chip pnx833x_pic_irq_type = { + .typename = "PNX-PIC", + .startup = pnx833x_startup_pic_irq, + .shutdown = pnx833x_shutdown_pic_irq, + .enable = pnx833x_enable_pic_irq, + .disable = pnx833x_disable_pic_irq, + .ack = pnx833x_ack_pic_irq, + .end = pnx833x_end_pic_irq +}; + +static struct irq_chip pnx833x_gpio_irq_type = { + .typename = "PNX-GPIO", + .startup = pnx833x_startup_gpio_irq, + .shutdown = pnx833x_disable_gpio_irq, + .enable = pnx833x_enable_gpio_irq, + .disable = pnx833x_disable_gpio_irq, + .ack = pnx833x_ack_gpio_irq, + .end = pnx833x_end_gpio_irq, + .set_type = pnx833x_set_type_gpio_irq +}; + +void __init arch_init_irq(void) +{ + unsigned int irq; + + /* setup standard internal cpu irqs */ + mips_cpu_irq_init(); + + /* Set IRQ information in irq_desc */ + for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) { + pnx833x_hard_disable_pic_irq(irq); + set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq); + } + + for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++) + set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq); + + /* Set PIC priority limiter register to 0 */ + PNX833X_PIC_INT_PRIORITY = 0; + + /* Setup GPIO IRQ dispatching */ + pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT); + + /* Enable PIC IRQs (HWIRQ2) */ + if (cpu_has_vint) + set_vi_handler(4, pic_dispatch); + + write_c0_status(read_c0_status() | IE_IRQ2); +} + + +void __init plat_time_init(void) +{ + /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */ + + extern unsigned long mips_hpt_frequency; + unsigned long reg = PNX833X_CLOCK_CPUCP_CTL; + + if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) { + /* Functional clock is disabled so use crystal frequency */ + mips_hpt_frequency = 25; + } else { +#if defined(CONFIG_SOC_PNX8335) + /* Functional clock is enabled, so get clock multiplier */ + mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ)); +#else + static const unsigned long int freq[4] = {240, 160, 120, 80}; + mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)]; +#endif + } + + printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency); + + mips_hpt_frequency *= 500000; +} + diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/Makefile linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/Makefile --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/Makefile 2008-03-03 13:09:30.000000000 +0000 @@ -0,0 +1 @@ +obj-y := interrupts.o platform.o prom.o setup.o reset.o gdb_hook.o diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/platform.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/platform.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/platform.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/platform.c 2008-06-05 11:09:06.000000000 +0100 @@ -0,0 +1,337 @@ +/* + * platform.c: platform support for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#if defined(CONFIG_SERIAL_PNX8XXX) || defined(CONFIG_SERIAL_PNX8XXX_MODULE) +static u64 uart_dmamask = ~(u32)0; + +static struct resource pnx833x_uart_resources[] = { + [0] = { + .start = PNX833X_UART0_PORTS_START, + .end = PNX833X_UART0_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX833X_PIC_UART0_INT, + .end = PNX833X_PIC_UART0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = PNX833X_UART1_PORTS_START, + .end = PNX833X_UART1_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = PNX833X_PIC_UART1_INT, + .end = PNX833X_PIC_UART1_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct pnx8xxx_port pnx8xxx_ports[] = { + [0] = { + .port = { + .type = PORT_PNX8XXX, + .iotype = UPIO_MEM, + .membase = (void __iomem *)PNX833X_UART0_PORTS_START, + .mapbase = PNX833X_UART0_PORTS_START, + .irq = PNX833X_PIC_UART0_INT, + .uartclk = 3692300, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .line = 0, + }, + }, + [1] = { + .port = { + .type = PORT_PNX8XXX, + .iotype = UPIO_MEM, + .membase = (void __iomem *)PNX833X_UART1_PORTS_START, + .mapbase = PNX833X_UART1_PORTS_START, + .irq = PNX833X_PIC_UART1_INT, + .uartclk = 3692300, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .line = 1, + }, + }, +}; + +static struct platform_device pnx833x_uart_device = { + .name = "pnx8xxx-uart", + .id = -1, + .dev = { + .dma_mask = &uart_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = pnx8xxx_ports, + }, + .num_resources = ARRAY_SIZE(pnx833x_uart_resources), + .resource = pnx833x_uart_resources, +}; +#endif + +#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) +static u64 ehci_dmamask = ~(u32)0; + +static struct resource pnx833x_usb_ehci_resources[] = { + [0] = { + .start = PNX833X_USB_PORTS_START, + .end = PNX833X_USB_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX833X_PIC_USB_INT, + .end = PNX833X_PIC_USB_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pnx833x_usb_ehci_device = { + .name = "pnx833x-ehci", + .id = -1, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources), + .resource = pnx833x_usb_ehci_resources, +}; +#endif + +#if defined(CONFIG_I2C_PNX0105) || defined(CONFIG_I2C_PNX0105_MODULE) +static struct resource pnx833x_i2c0_resources[] = { + { + .start = PNX833X_I2C0_PORTS_START, + .end = PNX833X_I2C0_PORTS_END, + .flags = IORESOURCE_MEM, + }, + { + .start = PNX833X_PIC_I2C0_INT, + .end = PNX833X_PIC_I2C0_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource pnx833x_i2c1_resources[] = { + { + .start = PNX833X_I2C1_PORTS_START, + .end = PNX833X_I2C1_PORTS_END, + .flags = IORESOURCE_MEM, + }, + { + .start = PNX833X_PIC_I2C1_INT, + .end = PNX833X_PIC_I2C1_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = { + { + .base = PNX833X_I2C0_PORTS_START, + .irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */ + .clock = 6, /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Prefered HDCP) */ + .bus_addr = 0, /* no slave support */ + }, + { + .base = PNX833X_I2C1_PORTS_START, + .irq = -1, /* on high freq, polling is faster */ + /*.irq = PNX833X_PIC_I2C1_INT,*/ + .clock = 4, /* 0 == 400 kHz, 4 == 100 kHz. 100 kHz seems a safe default for now */ + .bus_addr = 0, /* no slave support */ + }, +}; + +static struct platform_device pnx833x_i2c0_device = { + .name = "i2c-pnx0105", + .id = 0, + .dev = { + .platform_data = &pnx833x_i2c_dev[0], + }, + .num_resources = ARRAY_SIZE(pnx833x_i2c0_resources), + .resource = pnx833x_i2c0_resources, +}; + +static struct platform_device pnx833x_i2c1_device = { + .name = "i2c-pnx0105", + .id = 1, + .dev = { + .platform_data = &pnx833x_i2c_dev[1], + }, + .num_resources = ARRAY_SIZE(pnx833x_i2c1_resources), + .resource = pnx833x_i2c1_resources, +}; +#endif + +#if defined(CONFIG_IP3902) || defined(CONFIG_IP3902_MODULE) +static u64 ethernet_dmamask = ~(u32)0; + +static struct resource pnx833x_ethernet_resources[] = { + [0] = { + .start = PNX8335_IP3902_PORTS_START, + .end = PNX8335_IP3902_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8335_PIC_ETHERNET_INT, + .end = PNX8335_PIC_ETHERNET_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pnx833x_ethernet_device = { + .name = "ip3902-eth", + .id = -1, + .dev = { + .dma_mask = ðernet_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources), + .resource = pnx833x_ethernet_resources, +}; +#endif + +#if defined(CONFIG_SATA_PNX833X) || defined(CONFIG_SATA_PNX833X_MODULE) +static struct resource pnx833x_sata_resources[] = { + [0] = { + .start = PNX8335_SATA_PORTS_START, + .end = PNX8335_SATA_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8335_PIC_SATA_INT, + .end = PNX8335_PIC_SATA_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pnx833x_sata_device = { + .name = "pnx833x-sata", + .id = -1, + .num_resources = ARRAY_SIZE(pnx833x_sata_resources), + .resource = pnx833x_sata_resources, +}; +#endif + +#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) + +#define STB225_NAND_BASE 0x18000000 /* I/O location(gets remapped)*/ +#define STB225_NAND_CLE_MASK 0x00100000 /* I/O location with CLE high */ +#define STB225_NAND_ALE_MASK 0x00010000 /* I/O location with ALE high */ + +#ifdef CONFIG_MTD_PARTITIONS +static const char *part_probes[] = { "cmdlinepart", 0 }; +#endif + +static void +pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long)this->IO_ADDR_W; + + if (cmd == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) + writeb(cmd, (void __iomem *)(nandaddr + STB225_NAND_CLE_MASK)); + else + writeb(cmd, (void __iomem *) (nandaddr + STB225_NAND_ALE_MASK)); +} + +static struct platform_nand_data pnx833x_flash_nand_data = { + .chip = { + .chip_delay = 25, +#ifdef CONFIG_MTD_PARTITIONS + .part_probe_types = part_probes, +#endif + }, + .ctrl = { + .cmd_ctrl = pnx833x_flash_nand_cmd_ctrl + } +}; + +/* Set start to be the correct address (STB225_NAND_BASE with no 0xb!!), + 12 bytes more seems to be the standard that allows for NAND access.*/ +static struct resource pnx833x_flash_nand_resource = { + .start = STB225_NAND_BASE, + .end = STB225_NAND_BASE + 12, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device pnx833x_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = 1, + .resource = &pnx833x_flash_nand_resource, + .dev = { + .platform_data = &pnx833x_flash_nand_data, + }, +}; +#endif /* CONFIG_MTD_NAND_PLATFORM */ + +static struct platform_device *pnx833x_platform_devices[] __initdata = { +#if defined(CONFIG_SERIAL_PNX8XXX) || defined(CONFIG_SERIAL_PNX8XXX_MODULE) + &pnx833x_uart_device, +#endif +#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) + &pnx833x_usb_ehci_device, +#endif +#if defined(CONFIG_I2C_PNX0105) || defined(CONFIG_I2C_PNX0105_MODULE) + &pnx833x_i2c0_device, + &pnx833x_i2c1_device, +#endif +#if defined(CONFIG_IP3902) || defined(CONFIG_IP3902_MODULE) + &pnx833x_ethernet_device, +#endif +#if defined(CONFIG_SATA_PNX833X) || defined(CONFIG_SATA_PNX833X_MODULE) + &pnx833x_sata_device, +#endif +#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) + &pnx833x_flash_nand, +#endif +}; + +int __init pnx833x_platform_init(void) +{ + int res; + + if (ARRAY_SIZE(pnx833x_platform_devices)) { + res = platform_add_devices(pnx833x_platform_devices, + ARRAY_SIZE(pnx833x_platform_devices)); + } + return res; +} + +arch_initcall(pnx833x_platform_init); diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/prom.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/prom.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/prom.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/prom.c 2008-06-05 09:26:59.000000000 +0100 @@ -0,0 +1,69 @@ +/* + * prom.c: + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +void __init prom_init_cmdline(void) +{ + int argc = fw_arg0; + char **argv = (char **)fw_arg1; + char *c = &(arcs_cmdline[0]); + int i; + + for (i = 1; i < argc; i++) { + strcpy(c, argv[i]); + c += strlen(argv[i]); + if (i < argc-1) + *c++ = ' '; + } + *c = 0; +} + +char __init *prom_getenv(char *envname) +{ + extern char **prom_envp; + char **env = prom_envp; + int i; + + i = strlen(envname); + + while (*env) { + if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=') + return *env + i + 1; + env++; + } + + return 0; +} + +void __init prom_free_prom_memory(void) +{ +} + +char * __init prom_getcmdline(void) +{ + return arcs_cmdline; +} + diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/reset.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/reset.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/reset.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/reset.c 2008-06-05 11:27:00.000000000 +0100 @@ -0,0 +1,48 @@ +/* + * reset.c: reset support for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +void pnx833x_machine_restart(char *command) +{ + printk(KERN_ALERT "\n\nRestarting ...\n\n"); + + PNX833X_RESET_CONTROL_2 = 0; + PNX833X_RESET_CONTROL = 0; +} + +void pnx833x_machine_halt(void) +{ + printk(KERN_ALERT "\n\nSystem halted.\n\n"); + + while (1) + __asm__ __volatile__ ("wait"); +} + +void pnx833x_machine_power_off(void) +{ + printk(KERN_ALERT "\n\nPower off not implemented."); + pnx833x_machine_halt(); +} diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/setup.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/setup.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/setup.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/setup.c 2008-06-05 11:46:31.000000000 +0100 @@ -0,0 +1,63 @@ +/* + * setup.c: Setup PNX833X Soc. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +extern void pnx833x_board_setup(void); +extern void pnx833x_machine_restart(char *); +extern void pnx833x_machine_halt(void); +extern void pnx833x_machine_power_off(void); + +int __init plat_mem_setup(void) +{ + /* fake pci bus to avoid bounce buffers */ + PCI_DMA_BUS_IS_PHYS = 1; + + /* set mips clock to 320MHz */ +#if defined(CONFIG_SOC_PNX8335) + PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ); +#endif + gpio_init(); /* so it will be ready in board_setup() */ + + pnx833x_board_setup(); + + _machine_restart = pnx833x_machine_restart; + _machine_halt = pnx833x_machine_halt; + pm_power_off = pnx833x_machine_power_off; + + /* IO/MEM resources. */ + set_io_port_base(KSEG1); + ioport_resource.start = 0; + ioport_resource.end = ~0; + iomem_resource.start = 0; + iomem_resource.end = ~0; + + return 0; +} diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/board.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/board.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/board.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/board.c 2008-06-05 11:17:10.000000000 +0100 @@ -0,0 +1,138 @@ +/* + * board.c: STB225 board support. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include + +/* endianess twiddlers */ +#define PNX8335_DEBUG0 0x4400 +#define PNX8335_DEBUG1 0x4404 +#define PNX8335_DEBUG2 0x4408 +#define PNX8335_DEBUG3 0x440c +#define PNX8335_DEBUG4 0x4410 +#define PNX8335_DEBUG5 0x4414 +#define PNX8335_DEBUG6 0x4418 +#define PNX8335_DEBUG7 0x441c + +int prom_argc; +char **prom_argv = 0, **prom_envp = 0; + +extern void prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "NXP STB22x"; +} + +static inline unsigned long env_or_default(char *env, unsigned long dfl) +{ + char *str = prom_getenv(env); + return str ? simple_strtol(str, 0, 0) : dfl; +} + +void __init prom_init(void) +{ + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize = env_or_default("memsize", 0x02000000); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void __init pnx833x_board_setup(void) +{ +#if defined(CONFIG_SERIAL_PNX8XXX) || defined(CONFIG_SERIAL_PNX8XXX_MODULE) + gpio_select_function_alt(4); + gpio_select_output(4); + gpio_select_function_alt(5); + gpio_select_input(5); + gpio_select_function_alt(6); + gpio_select_input(6); + gpio_select_function_alt(7); + gpio_select_output(7); +#endif + +#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE) + gpio_select_function_alt(25); + gpio_select_function_alt(26); +#endif + +#if defined(CONFIG_IP3902) || defined(CONFIG_IP3902_MODULE) + gpio_select_function_alt(27); + gpio_select_function_alt(28); + gpio_select_function_alt(29); + gpio_select_function_alt(30); + gpio_select_function_alt(31); + gpio_select_function_alt(32); + gpio_select_function_alt(33); +#endif + +#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) + /* Setup MIU for NAND access on CS0... + * + * (it seems that we must also configure CS1 for reliable operation, + * otherwise the first read ID command will fail if it's read as 4 bytes + * but pass if it's read as 1 word.) + */ + + /* Setup MIU CS0 & CS1 timing */ + PNX833X_MIU_SEL0 = 0; + PNX833X_MIU_SEL1 = 0; + PNX833X_MIU_SEL0_TIMING = 0x50003081; + PNX833X_MIU_SEL1_TIMING = 0x50003081; + + /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */ + gpio_select_function_alt(0); + + /* Setup GPIO 04 to input NAND read/busy signal */ + gpio_select_function_io(4); + gpio_select_input(4); + + /* Setup GPIO 05 to disable NAND write protect */ + gpio_select_function_io(5); + gpio_select_output(5); + gpio_write(1, 5); + +#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE) + + /* Set up MIU for 16-bit NOR access on CS0 and CS1... */ + + /* Setup MIU CS0 & CS1 timing */ + PNX833X_MIU_SEL0 = 1; + PNX833X_MIU_SEL1 = 1; + PNX833X_MIU_SEL0_TIMING = 0x6A08D082; + PNX833X_MIU_SEL1_TIMING = 0x6A08D082; + + /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */ + gpio_select_function_alt(0); +#endif +} diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/Makefile linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/Makefile --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/Makefile 2008-03-03 13:09:30.000000000 +0000 @@ -0,0 +1 @@ +lib-y := board.o diff -urN --exclude=.svn linux-2.6.26-rc4.orig/drivers/i2c/busses/i2c-pnx0105.c linux-2.6.26-rc4/drivers/i2c/busses/i2c-pnx0105.c --- linux-2.6.26-rc4.orig/drivers/i2c/busses/i2c-pnx0105.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/drivers/i2c/busses/i2c-pnx0105.c 2008-06-05 11:25:57.000000000 +0100 @@ -0,0 +1,328 @@ +/* + * i2c-pnx0105.c: driver for PNX833X I2C (IP0105 Block) + * + * Copyright 2008 NXP Semiconductors + * Daniel Laird + * + * Copyright (C) 2006 Nikita Youshchenko + * + * Partially based on i2c-pca-isa driver, Copyright (C) 2004 Arcom Control + * Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static inline unsigned long i2c_pnx0105_in(struct i2c_pnx0105_dev *dev, int offset) +{ + return readl((unsigned long *)(dev->base + offset)); +} + +static inline void i2c_pnx0105_out(struct i2c_pnx0105_dev *dev, int offset, unsigned long value) +{ + writel(value, (unsigned long *)(dev->base + offset)); +} + +static void i2c_pnx0105_writebyte(void *pa, int reg, int val) +{ + struct i2c_algo_pca_data *algo_data = container_of(pa, struct i2c_algo_pca_data, data); + struct i2c_pnx0105_dev *dev = container_of(algo_data, struct i2c_pnx0105_dev, algo_data); + int old_si; + +#ifdef DEBUG + static char *names[] = { "T/O", "DAT", "ADR", "CON"}; + printk(KERN_DEBUG "i2c_pnx0105(0x%08lx): write %s <= %#04x\n", dev->base, names[reg], val); +#endif + + switch (reg) { + + case I2C_PCA_DAT: + i2c_pnx0105_out(dev, I2C_PNX0105_DAT, val & 255); + break; + + case I2C_PCA_ADR: + i2c_pnx0105_out(dev, I2C_PNX0105_ADDRESS, val & 255); + break; + + case I2C_PCA_CON: + /* Possible RACE: just after init, or after stop, + SI bit is zero. That means that when STA bit + is written, hardware starts to process it + immediately. It could complete very fast (or + perhaps thread may get preempted), so when code + several lines below is executed, SI could already + be set to indicate that STA processing is complete. + In this case, SI must NOT be cleared here, so + hardware won't continue and send slave address + before it was written to register. + However, if SI bit is currently set, hardware + won't process command immediately, and SI should + be cleared at the bottom, to enable processing. + Solution: just check SI here, and clear it only + if it was set before any new value was written + to command register. + */ + old_si = i2c_pnx0105_in(dev, I2C_PNX0105_INT_STATUS) & 1; + + i2c_pnx0105_out(dev, I2C_PNX0105_CONTROL, val & 255); + + /* We have to process STO bit separately */ + if (val & I2C_PCA_CON_STO) + i2c_pnx0105_out(dev, I2C_PNX0105_STOP, 1); + + /* And also SI bit ... */ + if (old_si && !(val & I2C_PCA_CON_SI)) { + i2c_pnx0105_out(dev, I2C_PNX0105_INT_CLEAR, 1); + if (dev->irq > -1 && !(val & I2C_PCA_CON_STO)) + i2c_pnx0105_out(dev, I2C_PNX0105_INT_ENABLE, 1); + } + + break; + + default: + BUG(); + } +} + +static int i2c_pnx0105_readbyte(void *pa, int reg) +{ + struct i2c_algo_pca_data *algo_data = container_of(pa, struct i2c_algo_pca_data, data); + struct i2c_pnx0105_dev *dev = container_of(algo_data, struct i2c_pnx0105_dev, algo_data); + int res = 0; + + switch (reg) { + + case I2C_PCA_STA: + if (dev->timeout) { + res = 0xff; + dev->timeout = 0; + } else + res = i2c_pnx0105_in(dev, I2C_PNX0105_STATUS) & 255; + break; + + case I2C_PCA_DAT: + res = i2c_pnx0105_in(dev, I2C_PNX0105_DAT) & 255; + break; + + case I2C_PCA_CON: + res = i2c_pnx0105_in(dev, I2C_PNX0105_CONTROL) & 255; + + /* Read SI bit from elsewhere */ + if (i2c_pnx0105_in(dev, I2C_PNX0105_INT_STATUS)) + res |= I2C_PCA_CON_SI; + else + res &= ~I2C_PCA_CON_SI; + + break; + + default: + BUG(); + } + +#ifdef DEBUG + { + static char *names[] = { "STA", "DAT", "ADR", "CON"}; + printk(KERN_DEBUG "i2c_pnx0105(0x%08lx): read %s => %#04x\n", dev->base, names[reg], res); + } +#endif + return res; +} + +static inline void i2c_pnx0105_reset(struct i2c_pnx0105_dev *dev) +{ + unsigned long val = i2c_pnx0105_in(dev, I2C_PNX0105_CONTROL) & 0x47; + i2c_pnx0105_out(dev, I2C_PNX0105_CONTROL, val | 0x40); + i2c_pnx0105_out(dev, I2C_PNX0105_STOP, 1); + i2c_pnx0105_out(dev, I2C_PNX0105_INT_CLEAR, 1); + udelay(200); + i2c_pnx0105_out(dev, I2C_PNX0105_CONTROL, val); +} + +static inline int i2c_pnx0105_intr_condition(struct i2c_pnx0105_dev *dev) +{ + return i2c_pnx0105_in(dev, I2C_PNX0105_INT_STATUS) & 1; +} + +static int i2c_pnx0105_waitforcompletion(void *pa) +{ + struct i2c_algo_pca_data *algo_data = container_of(pa, struct i2c_algo_pca_data, data); + struct i2c_pnx0105_dev *dev = container_of(algo_data, struct i2c_pnx0105_dev, algo_data); + + /* Set some timeout */ +#define JIFFIES_TO_WAIT ((HZ / 100) + 1) /* attempt to model 10 milliseconds */ + + if (dev->irq > -1) { + wait_event_timeout(dev->wait, + i2c_pnx0105_intr_condition(dev), JIFFIES_TO_WAIT); + } else { + unsigned long end = jiffies + JIFFIES_TO_WAIT; + while (!i2c_pnx0105_intr_condition(dev) && + time_before(jiffies, end)) { + if (in_atomic()) + udelay(100); + else + schedule(); + } + } + + if (i2c_pnx0105_intr_condition(dev)) + return 0; + + /* Timeout. Reset device and make next status read to return 0xff */ + i2c_pnx0105_reset(dev); + dev->timeout = 1; + return -EIO; /* Ignored anyway */ +} + +static irqreturn_t i2c_pnx0105_interrupt(int this_irq, void *dev_id) +{ + struct i2c_pnx0105_dev *dev = (struct i2c_pnx0105_dev *)dev_id; + + /* Disable interrupt for a while (until it's actually handled) */ + i2c_pnx0105_out(dev, I2C_PNX0105_INT_ENABLE, 0); + + /* Wake up any process waiting for this interrupt */ + wake_up_interruptible(&dev->wait); + + return IRQ_HANDLED; +} + +static int __devinit i2c_pnx0105_probe(struct platform_device *pdev) +{ + struct i2c_pnx0105_dev *dev = (struct i2c_pnx0105_dev *) pdev->dev.platform_data; + struct i2c_algo_pca_data *algo_data = &dev->algo_data; + struct i2c_adapter *adap = &dev->adap; + int res; + + algo_data->write_byte = i2c_pnx0105_writebyte; + algo_data->read_byte = i2c_pnx0105_readbyte; + algo_data->wait_for_completion = i2c_pnx0105_waitforcompletion; + + adap->owner = THIS_MODULE; + adap->id = I2C_HW_A_PNX0105; + adap->algo_data = algo_data; + strncpy(adap->name, pdev->name, I2C_NAME_SIZE); + + dev->timeout = 0; + init_waitqueue_head(&dev->wait); + + if (request_region(dev->base, I2C_PNX0105_IO_SIZE, "i2c-pnx") == 0) { + printk(KERN_ERR "i2c-pnx0105: request_region(0x%08lx) failed\n", + dev->base); + return -EBUSY; + } + + /* Disable interrupt - just to be sure ... */ + i2c_pnx0105_out(dev, I2C_PNX0105_INT_ENABLE, 0); + + if (dev->irq > -1) { + res = request_irq(dev->irq, i2c_pnx0105_interrupt, 0, "i2c-pnx", dev); + if (res < 0) { + printk(KERN_ERR "i2c-pnx0105: request_irq() failed\n"); + goto err_region; + } + } + + /* Rude attempt to probe hardware, to avoid future hangups if it is + not responding */ + i2c_pnx0105_out(dev, I2C_PNX0105_CONTROL, 0x60); + udelay(200); + res = i2c_pnx0105_intr_condition(dev) ? 0 : -ENODEV; + i2c_pnx0105_reset(dev); + + if (res < 0) { + printk(KERN_ERR "i2c-pnx0105: device at 0x%08lx is not responding\n", + dev->base); + goto err_irq; + } + + res = i2c_pca_add_bus(adap); + if (res < 0) { + printk(KERN_ERR "i2c-pnx0105: i2c_pca_add_bus() failed\n"); + goto err_irq; + } + + printk(KERN_INFO "i2c-pnx0105: registered device at 0x%08lx", dev->base); + if (dev->irq > -1) + printk(KERN_ERR ", irq %d", dev->irq); + printk(KERN_INFO "\n"); + + return 0; + +err_irq: + if (dev->irq > -1) + free_irq(dev->irq, dev); + +err_region: + release_region(dev->base, I2C_PNX0105_IO_SIZE); + + return res; +} + +static int __devexit i2c_pnx0105_remove(struct platform_device *pdev) +{ + struct i2c_pnx0105_dev *dev = (struct i2c_pnx0105_dev *) pdev->dev.platform_data; + struct i2c_adapter *adap = &dev->adap; + int res; + + res = i2c_del_adapter(adap); + if (res < 0) + return res; + + if (dev->irq > -1) + free_irq(dev->irq, dev); + + release_region(dev->base, I2C_PNX0105_IO_SIZE); + + return 0; +} + +static struct platform_driver i2c_pnx0105_driver = { + .probe = i2c_pnx0105_probe, + .remove = __devexit_p(i2c_pnx0105_remove), + .driver = { + .owner = THIS_MODULE, + .name = "i2c-pnx0105", + }, +}; + +static int __init i2c_pnx0105_init(void) +{ + return platform_driver_register(&i2c_pnx0105_driver); +} + +static void __exit i2c_pnx0105_cleanup(void) +{ + platform_driver_unregister(&i2c_pnx0105_driver); +} + +module_init(i2c_pnx0105_init); +module_exit(i2c_pnx0105_cleanup); + +MODULE_AUTHOR("Nikita Youshchenko "); +MODULE_DESCRIPTION("PNX833X I2C driver"); +MODULE_LICENSE("GPL"); + + diff -urN --exclude=.svn linux-2.6.26-rc4.orig/drivers/i2c/busses/Kconfig linux-2.6.26-rc4/drivers/i2c/busses/Kconfig --- linux-2.6.26-rc4.orig/drivers/i2c/busses/Kconfig 2008-06-03 10:56:53.000000000 +0100 +++ linux-2.6.26-rc4/drivers/i2c/busses/Kconfig 2008-06-04 09:29:35.000000000 +0100 @@ -677,6 +677,18 @@ This driver can also be built as a module. If so, the module will be called i2c-pnx. +config I2C_PNX0105 + tristate "I2C bus support for Philips PNX8XXX targets" + depends on I2C && SOC_PNX833X + select I2C_ALGOPCA + default y + help + Support for NXP PNX SoC internal I2C (IP0105). + Say y or m if you want to use PNX I2C interfaces. + + This driver can also be built as a module. If so, the module + will be called i2c-pnx0105. + config I2C_PMCMSP tristate "PMC MSP I2C TWI Controller" depends on PMC_MSP diff -urN --exclude=.svn linux-2.6.26-rc4.orig/drivers/i2c/busses/Makefile linux-2.6.26-rc4/drivers/i2c/busses/Makefile --- linux-2.6.26-rc4.orig/drivers/i2c/busses/Makefile 2008-06-03 10:56:53.000000000 +0100 +++ linux-2.6.26-rc4/drivers/i2c/busses/Makefile 2008-06-04 09:29:40.000000000 +0100 @@ -34,6 +34,7 @@ obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o obj-$(CONFIG_I2C_PNX) += i2c-pnx.o +obj-$(CONFIG_I2C_PNX0105) += i2c-pnx0105.o obj-$(CONFIG_I2C_PROSAVAGE) += i2c-prosavage.o obj-$(CONFIG_I2C_PXA) += i2c-pxa.o obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o diff -urN --exclude=.svn linux-2.6.26-rc4.orig/drivers/net/ip3902.c linux-2.6.26-rc4/drivers/net/ip3902.c --- linux-2.6.26-rc4.orig/drivers/net/ip3902.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/drivers/net/ip3902.c 2008-06-05 11:27:28.000000000 +0100 @@ -0,0 +1,1534 @@ +/* + * ip3902.c: NXP ip3902 embedded 10/100 Ethernet controller support + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * Based on ax88796.c, by Ben Dooks. + * Based on previous ip3902.c by Nikita V. Youshchenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRVNAME "ip3902-eth" +#define DRVVERSION "1.00" + +#define IP3902_NAPI + +/* "Strange hardware" support macros */ + +/* These control endianness of descriptors and statuses. + * If none if LITTLE_ENDIAN_xxx and BIG_ENDIAN_xxx is defined, system endian + * is used for xxx */ +#define LITTLE_ENDIAN_DESCRIPTORS +#undef BIG_ENDIAN_DESCRIPTORS +#undef LITTLE_ENDIAN_STATUSES +#define BIG_ENDIAN_STATUSES + +#define ETH_RX_SKB_SIZE 0x600 /* 1536 bytes, just over max mtu */ +#define TX_RING_SIZE 64 +#define RX_RING_SIZE 64 +#define IP3902_NAPI_WEIGHT 48 +#define MAX_LRO_DESCRIPTORS 6 +#define LRO_THRESHOLD 3 + +#define BYTES_IN_ETHERNET_CRC 4 +#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) + +#define NEXT_TX(i) (((i) == TX_RING_SIZE-1) ? 0 : (i)+1) +#define NEXT_RX(i) (((i) == RX_RING_SIZE-1) ? 0 : (i)+1) + +/* Access to IP3902 registers */ + +/* Alcatel (Packet Engines) core registers */ +#define MAC1_REG 0x000 /* R/W: MAC configuration register 1 */ +#define MAC2_REG 0x004 /* R/W: MAC configuration register 2 */ +#define IPGT_REG 0x008 /* R/W: Back-to-Back Inter-Packet-Gap register */ +#define IPGR_REG 0x00c /* R/W: Non Back-to-Back Inter-Packet-Gap register */ +#define CLRT_REG 0x010 /* R/W: Collision window / Retry register */ +#define MAXF_REG 0x014 /* R/W: Maximum Frame register */ +#define SUPP_REG 0x018 /* R/W: PHY Support register */ +#define TEST_REG 0x01C /* R/W: Test register */ +#define MCFG_REG 0x020 /* R/W: MII Mgmt Con???guration register */ +#define MCMD_REG 0x024 /* R/W: MII Mgmt Command register */ +#define MADR_REG 0x028 /* R/W: MII Mgmt Address register */ +#define MWTD_REG 0x02C /* WO: MII Mgmt Write Data register */ +#define MRDD_REG 0x030 /* RO: MII Mgmt Read Data register */ +#define MIND_REG 0x034 /* RO: MII Mgmt Indicators register */ +#define SA0_REG 0x040 /* R/W: Station Address 0 register */ +#define SA1_REG 0x044 /* R/W: Station Address 1 register */ +#define SA2_REG 0x048 /* R/W: Station Address 2 register */ + +/* Control registers */ +#define COMMAND_REG 0x100 /* R/W: Command register */ +#define STATUS_REG 0x104 /* RO: Status register */ +#define RX_DESC_REG 0x108 /* R/W: Receive descriptor base address register */ +#define RX_STATUS_REG 0x10C /* R/W: Receive status base address register */ +#define RX_DESC_NUMBER_REG 0x110 /* R/W: Receive number of descriptors register */ +#define RX_PRODUCE_INDEX_REG 0x114 /* RO: Receive produce index register */ +#define RX_CONSUME_INDEX_REG 0x118 /* R/W: Receive consume index register */ +#define TX_DESC_REG 0x11C /* R/W: Non real-time transmit descriptor base address register */ +#define TX_STATUS_REG 0x120 /* R/W: Non real-time transmit status base address register */ +#define TX_DESC_NUMBER_REG 0x124 /* R/W: Non real-time transmit number of descriptors register */ +#define TX_PRODUCE_INDEX_REG 0x128 /* R/W: Non real-time transmit produce index register */ +#define TX_CONSUME_INDEX_REG 0x12C /* RO: Non real-time transmit consume index register */ +#define TX_RT_DESC_REG 0x130 /* R/W: Real-time transmit descriptor base address register */ +#define TX_RT_STATUS_REG 0x134 /* R/W: Real-time transmit status base address register */ +#define TX_RT_DESC_NUMBER_REG 0x138 /* R/W: Real-time transmit number of descriptors register */ +#define TX_RT_PRODUCE_INDEX_REG 0x13C /* R/W: Real-time transmit produce index register */ +#define TX_RT_CONSUME_INDEX_REG 0x140 /* RO: Real-time transmit consume index register */ +#define QOS_TIMEOUT_REG 0x148 /* R/W: Transmit quality of service time-out register */ +#define TSV0_REG 0x158 /* RO: Transmit status vector 0 register */ +#define TSV1_REG 0x15C /* RO: Transmit status vector 1 register */ +#define RSV_REG 0x160 /* RO: Receive status vector register */ +#define FC_COUNTER_REG 0x170 /* R/W: Flow control counter register */ +#define FC_STATUS_REG 0x174 /* RO: Flow control status register */ + +/* Rx filter registers */ +#define FILTER_CTRL_REG 0x200 /* R/W: Receive filter control register */ +#define FILTER_WOL_STATUS_REG 0x204 /* RO: Receive filter WoL status register */ +#define FILTER_WOL_CLEAR_REG 0x208 /* WO: Receive filter WoL clear register */ +#define HASH_FILTER_L_REG 0x210 /* R/W: Hash filter table LSBs register */ +#define HASH_FILTER_H_REG 0x214 /* R/W: Hash filter table MSBs register */ + +/* DVP Standard registers */ +#define INT_STATUS_REG 0xFE0 /* RO: Interrupt status register */ +#define INT_ENABLE_REG 0xFE4 /* R/W: Interrupt enable register */ +#define INT_CLEAR_REG 0xFE8 /* WO: Interrupt clear register */ +#define INT_SET_REG 0xFEC /* WO: Interrupt set register */ +#define POWERDOWN_REG 0xFF4 /* R/W: Power-down register */ +#define MODULE_ID_REG 0xFFC /* RO: Module ID register */ + +/* Bits for MAC1 register */ +#define MAC1_SOFT_RESET (1 << 15) +#define MAC1_TX_FLOW_CONTROL (1 << 3) +#define MAC1_RX_FLOW_CONTROL (1 << 2) +#define MAC1_RECEIVE_PASS_ALL (1 << 1) +#define MAC1_RECEIVE_ENABLE (1 << 0) + +/* Bits for MAC2 register */ +#define MAC2_AUTO_DETECT_PAD_ENABLE (1 << 7) +#define MAC2_VLAN_PAD_ENABLE (1 << 6) +#define MAC2_PAD_CRC_ENABLE (1 << 5) +#define MAC2_CRC_ENABLE (1 << 4) +#define MAC2_FULL_DUPLEX (1 << 0) + +#define INITIAL_MAC2 (MAC2_AUTO_DETECT_PAD_ENABLE | MAC2_VLAN_PAD_ENABLE | MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE) + +/* Recommended values for IPGT register (see sec. 3.3.2.3 0f datasheet */ +#define IPGT_FD_VALUE 0x15 +#define IPGT_HD_VALUE 0x12 + +/* Bits for MCMD register */ +#define MCMD_READ (1 << 0) + +/* Bits for MIND register */ +#define MIND_NOT_VALID (1 << 2) +#define MIND_BUSY (1 << 0) + +/* Bits for command register */ +#define COMMAND_ENABLE_QOS (1 << 11) +#define COMMAND_FULL_DUPLEX (1 << 10) +#define COMMAND_RMII_MODE (1 << 9) +#define COMMAND_TX_FLOW_CONTROL (1 << 8) +#define COMMAND_PROMISC (1 << 7) +#define COMMAND_ALLOW_SHORT (1 << 6) +#define COMMAND_RX_RESET (1 << 5) +#define COMMAND_TX_RESET (1 << 4) +#define COMMAND_RESET (1 << 3) +#define COMMAND_TX_RT_ENABLE (1 << 2) +#define COMMAND_TX_ENABLE (1 << 1) +#define COMMAND_RX_ENABLE (1 << 0) + +/* Bits for receive filter control register */ +#define FILTER_ACCEPT_SELF (1 << 5) +#define FILTER_ACCEPT_MCAST_HASH (1 << 4) +#define FILTER_ACCEPT_UCAST_HASH (1 << 3) +#define FILTER_ACCEPT_MCAST_ANY (1 << 2) +#define FILTER_ACCEPT_BCAST_ANY (1 << 1) +#define FILTER_ACCEPT_UCAST_ANY (1 << 0) + +/* Bits for interrupt registers */ +#define WAKEUP_INT (1 << 13) +#define SOFT_INT (1 << 12) +#define TX_RT_DONE_INT (1 << 11) +#define TX_RT_FINISHED_INT (1 << 10) +#define TX_RT_ERROR_INT (1 << 9) +#define TX_RT_UNDERRUN_INT (1 << 8) +#define TX_DONE_INT (1 << 7) +#define TX_FINISHED_INT (1 << 6) +#define TX_ERROR_INT (1 << 5) +#define TX_UNDERRUN_INT (1 << 4) +#define RX_DONE_INT (1 << 3) +#define RX_FINISHED_INT (1 << 2) +#define RX_ERROR_INT (1 << 1) +#define RX_OVERRUN_INT (1 << 0) + +/* Bit for POWERDOWN register */ +#define POWERDOWN_VALUE (1 << 31) + +/* Bits for TX control */ +#define TX_CONTROL_INT (1 << 31) +#define TX_CONTROL_LAST (1 << 30) +#define TX_CONTROL_CRC (1 << 29) +#define TX_CONTROL_PAD (1 << 28) +#define TX_CONTROL_HUGE (1 << 27) +#define TX_CONTROL_OVERRIDE (1 << 26) + +/* these flags used for non-last fragment of a frame */ +#define TX_CONTROL_ALL_NOTLAST (TX_CONTROL_CRC | TX_CONTROL_PAD | TX_CONTROL_OVERRIDE) +/* these flags used for last fragment of a frame, and for single-fragment + * frames */ +#define TX_CONTROL_ALL_LAST (TX_CONTROL_ALL_NOTLAST | TX_CONTROL_LAST | TX_CONTROL_INT) + +/* Bits for TX status */ +#define TX_STATUS_ERROR (1 << 31) +#define TX_STATUS_UNDERRUN (1 << 29) +#define TX_STATUS_LATE_COLLISION (1 << 28) +#define TX_STATUS_MANY_COLLISIONS (1 << 27) +#define TX_STATUS_MANY_DEFER (1 << 26) +#define TX_STATUS_COLLISIONS(s) ((s >> 21) & 15) + +/* Bits for RX control */ +#define RX_CONTROL_INT (1 << 31) + +/* Bits for RX status */ +#define RX_STATUS_ERROR (1 << 31) +#define RX_STATUS_LAST_FRAG (1 << 30) +#define RX_STATUS_OVERRUN (1 << 28) +#define RX_STATUS_ALIGNMENT_ERROR (1 << 27) +#define RX_STATUS_RANGE_ERROR (1 << 26) +#define RX_STATUS_LENGTH_ERROR (1 << 25) +#define RX_STATUS_SYMBOL_ERROR (1 << 24) +#define RX_STATUS_CRC_ERROR (1 << 23) +#define RX_STATUS_BROADCAST (1 << 22) +#define RX_STATUS_MULTICAST (1 << 21) +#define RX_STATUS_FAIL_FILTER (1 << 20) +#define RX_STATUS_VLAN (1 << 19) +#define RX_STATUS_CONTROL_FRAME (1 << 18) +#define RX_STATUS_LENGTH(s) ((s & 0x7ff) + 1) + +/* Bits for RSV register */ +#define RSV_VLAN (1 << 30) +#define RSV_CONTROL_FRAME (1 << 27) +#define RSV_DRIBBLE_NIBBLE (1 << 26) +#define RSV_BROADCAST (1 << 25) +#define RSV_MULTICAST (1 << 24) +#define RSV_LENGTH_OUT_OF_RANGE (1 << 22) +#define RSV_LENGTH_CHECK_ERROR (1 << 21) +#define RSV_CRC_ERROR (1 << 20) +#define RSV_RECEIVE_CODE_VIOLATION (1 << 19) +#define RSV_MASK 0xFFFF + +static char *mac_address; +module_param(mac_address, charp, S_IRUGO); +MODULE_PARM_DESC(mac_address, "MAC address of the device"); + + +/* device private data */ +struct ip3902_descriptor { + unsigned long address; + unsigned long control; +}; + +struct ip3902_rx_status { + unsigned long status; + unsigned long hash_crc; +}; + +struct ip3902_dma_struct { + struct ip3902_descriptor rx_desc[RX_RING_SIZE]; + struct ip3902_rx_status rx_status[RX_RING_SIZE]; + struct ip3902_descriptor tx_desc[TX_RING_SIZE]; + unsigned long tx_status[TX_RING_SIZE]; +}; + +struct ip3902_private { + spinlock_t mii_lock; + struct mii_if_info mii; + u32 msg_enable; + + spinlock_t lock; + struct net_device *ndev; + struct platform_device *pdev; + struct resource *bus; + void __iomem *mem; +#ifdef IP3902_NAPI + struct napi_struct napi; +#endif + + struct ip3902_dma_struct *ds; /* descriptors and statuses */ + dma_addr_t ds_dma; + + struct sk_buff *rx_skb[RX_RING_SIZE]; /* where to recieve to */ + struct sk_buff *tx_skb[TX_RING_SIZE]; /* where to send from */ + bool tx_first_desc[TX_RING_SIZE]; /* true if this is the first desc of an skb */ + + int rx_next_allocate; /* index in rx ring where skb should be allocated */ + int rx_next_consume; /* index in rx ring where data should be read when available */ + int tx_next_produce; /* index in tx ring where new data should be put */ + int tx_next_deallocate; /* index in tx ring of first not freed skb */ + +#ifdef CONFIG_INET_LRO + bool use_lro; + int lro_count; + struct net_lro_mgr lro_mgr; + struct net_lro_desc lro_desc[MAX_LRO_DESCRIPTORS]; + struct timer_list lro_timer; +#endif + + unsigned char running; + unsigned char resume_open; + +}; + +static inline unsigned long ip3902_read_reg(struct net_device *ndev, int reg) +{ + unsigned long value = readl((void * __iomem)(ndev->base_addr + reg)); + return value; +} + +static inline void ip3902_write_reg(struct net_device *ndev, int reg, + unsigned long val) +{ + writel(val, (void * __iomem)(ndev->base_addr + reg)); +} + +static inline void ip3902_write_tx_desc(struct ip3902_private *ip3902_priv, int pos, unsigned long address, unsigned long control) +{ +#if defined(BIG_ENDIAN_DESCRIPTORS) + ip3902_priv->ds->tx_desc[pos].address = cpu_to_be32(address); + ip3902_priv->ds->tx_desc[pos].control = cpu_to_be32(control); +#elif defined(LITTLE_ENDIAN_DESCRIPTORS) + ip3902_priv->ds->tx_desc[pos].address = cpu_to_le32(address); + ip3902_priv->ds->tx_desc[pos].control = cpu_to_le32(control); +#else + ip3902_priv->ds->tx_desc[pos].address = address; + ip3902_priv->ds->tx_desc[pos].control = control; +#endif + wmb(); +} + +static inline void ip3902_read_tx_desc(struct ip3902_private *ip3902_priv, int pos, dma_addr_t *address, int *length) +{ +#if defined(BIG_ENDIAN_DESCRIPTORS) + *address = (dma_addr_t)be32_to_cpu(ip3902_priv->ds->tx_desc[pos].address); + *length = (int)be32_to_cpu(ip3902_priv->ds->tx_desc[pos].control) & 0xffff; +#elif defined(LITTLE_ENDIAN_DESCRIPTORS) + *address = (dma_addr_t)le32_to_cpu(ip3902_priv->ds->tx_desc[pos].address); + *length = (int)le32_to_cpu(ip3902_priv->ds->tx_desc[pos].control) & 0xffff; +#else + *address = (dma_addr_t)ip3902_priv->ds->tx_desc[pos].address; + *length = (int)ip3902_priv->ds->tx_desc[pos].control & 0xffff; +#endif +} + +static inline unsigned long ip3902_read_tx_status(struct ip3902_private *ip3902_priv, int pos) +{ +#if defined(BIG_ENDIAN_STATUSES) + return be32_to_cpu(ip3902_priv->ds->tx_status[pos]); +#elif defined(LITTLE_ENDIAN_STATUSES) + return le32_to_cpu(ip3902_priv->ds->tx_status[pos]); +#else + return ip3902_priv->ds->tx_status[pos]; +#endif +} + +static inline void ip3902_write_rx_desc(struct ip3902_private *ip3902_priv, int pos, unsigned long address, unsigned long control) +{ +#if defined(BIG_ENDIAN_DESCRIPTORS) + ip3902_priv->ds->rx_desc[pos].address = cpu_to_be32(address); + ip3902_priv->ds->rx_desc[pos].control = cpu_to_be32(control); +#elif defined(LITTLE_ENDIAN_DESCRIPTORS) + ip3902_priv->ds->rx_desc[pos].address = cpu_to_le32(address); + ip3902_priv->ds->rx_desc[pos].control = cpu_to_le32(control); +#else + ip3902_priv->ds->rx_desc[pos].address = address; + ip3902_priv->ds->rx_desc[pos].control = control; +#endif + wmb(); +} + +static inline void ip3902_read_rx_desc(struct ip3902_private *ip3902_priv, int pos, dma_addr_t *address, int *length) +{ +#if defined(BIG_ENDIAN_DESCRIPTORS) + *address = (dma_addr_t)be32_to_cpu(ip3902_priv->ds->rx_desc[pos].address); + *length = (int)be32_to_cpu(ip3902_priv->ds->rx_desc[pos].control) & 0xffff; +#elif defined(LITTLE_ENDIAN_DESCRIPTORS) + *address = (dma_addr_t)le32_to_cpu(ip3902_priv->ds->rx_desc[pos].address); + *length = (int)le32_to_cpu(ip3902_priv->ds->rx_desc[pos].control) & 0xffff; +#else + *address = (dma_addr_t)ip3902_priv->ds->rx_desc[pos].address; + *length = (int)ip3902_priv->ds->rx_desc[pos].control & 0xffff; +#endif +} + +static inline unsigned long ip3902_read_rx_status(struct net_device *ndev, struct ip3902_private *ip3902_priv, int pos) +{ +#if defined(BIG_ENDIAN_STATUSES) + return be32_to_cpu(ip3902_priv->ds->rx_status[pos].status); +#elif defined(LITTLE_ENDIAN_STATUSES) + return le32_to_cpu(ip3902_priv->ds->rx_status[pos].status); +#else + return ip3902_priv->ds->rx_status[pos].status; +#endif +} + +static inline void ip3902_write_madr_reg(struct net_device *ndev, int phy_id, int location) +{ + /* assume ranges of phy_id and location are correct - we set masks in + * struct mii_if_info for that */ + + unsigned long val = (phy_id << 8) | location; + ip3902_write_reg(ndev, MADR_REG, val); +} + +static inline int ip3902_wait_mdio_op_complete(struct net_device *ndev, unsigned long mask) +{ + int timeout = 10000; /* to avoid hangup in case of unexpected badness ... */ + + while (--timeout > 0) { + if ((ip3902_read_reg(ndev, MIND_REG) & mask) == 0) + return 0; + udelay(1); + } + + return -EIO; +} + +static int ip3902_mdio_read(struct net_device *ndev, int phy_id, int location) +{ + ip3902_write_madr_reg(ndev, phy_id, location); + ip3902_write_reg(ndev, MCMD_REG, 0); + ip3902_write_reg(ndev, MCMD_REG, MCMD_READ); + if (ip3902_wait_mdio_op_complete(ndev, MIND_NOT_VALID | MIND_BUSY) < 0) + return 0; + else + return ip3902_read_reg(ndev, MRDD_REG) & 0xffff; +} + +static void ip3902_mdio_write(struct net_device *ndev, int phy_id, int location, int val) +{ + ip3902_write_madr_reg(ndev, phy_id, location); + ip3902_write_reg(ndev, MWTD_REG, val & 0xffff); + ip3902_wait_mdio_op_complete(ndev, MIND_BUSY); +} + +static inline int ip3902_nr_free_descs(int head, int tail, int size) +{ + int free; + + if (head >= tail) + free = (tail + size) - head; + else + free = tail - head; + + return free; +} + +static void ip3902_eth_rx_refill_descs(struct net_device *ndev, struct ip3902_private *ip3902_priv) +{ + do { + int rx_index = ip3902_priv->rx_next_allocate; + struct sk_buff *skb = netdev_alloc_skb(ndev, ETH_RX_SKB_SIZE + dma_get_cache_alignment()); + + if (skb) { + int unaligned = (((u32)skb->data) + ETH_HLEN) & (dma_get_cache_alignment() - 1); + unsigned long desc_address; + + if (unaligned) + skb_reserve(skb, (dma_get_cache_alignment() - unaligned)); + + desc_address = dma_map_single(NULL, skb->data, ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); + ip3902_write_rx_desc(ip3902_priv, rx_index, desc_address, (ETH_RX_SKB_SIZE - 1) | RX_CONTROL_INT); + + ip3902_priv->rx_skb[rx_index] = skb; + ip3902_priv->rx_next_allocate = NEXT_RX(rx_index); + } else { + ip3902_write_reg(ndev, RX_CONSUME_INDEX_REG, ip3902_priv->rx_next_allocate); + return; + } + } while (ip3902_priv->rx_next_allocate != ip3902_priv->rx_next_consume); + + ip3902_write_reg(ndev, RX_CONSUME_INDEX_REG, ip3902_priv->rx_next_allocate); +} + +static int ip3902_eth_receive_queue(struct net_device *ndev, struct ip3902_private *ip3902_priv, int budget) +{ + int rx_index = ip3902_priv->rx_next_consume; + int write_index = ip3902_read_reg(ndev, RX_PRODUCE_INDEX_REG); + int received = 0; + int limit; + + do { + limit = write_index; + spin_lock(&ip3902_priv->lock); + while (rx_index != limit) { + unsigned long status = ip3902_read_rx_status(ndev, ip3902_priv, rx_index); + + if (!(status & RX_STATUS_LAST_FRAG)) { + printk(DRVNAME ": broken RX status: %08lx\n", status); + continue; + } + + if (status & RX_STATUS_FAIL_FILTER) + continue; + + /* Looks like hardware returns RANGE_ERROR for each frame */ + if (status & (RX_STATUS_OVERRUN | RX_STATUS_ALIGNMENT_ERROR | RX_STATUS_LENGTH_ERROR | RX_STATUS_CRC_ERROR)) { + ndev->stats.rx_errors++; + + if (status & RX_STATUS_OVERRUN) + ndev->stats.rx_fifo_errors++; + + if (status & RX_STATUS_ALIGNMENT_ERROR) + ndev->stats.rx_frame_errors++; + + if (status & (RX_STATUS_RANGE_ERROR | RX_STATUS_LENGTH_ERROR)) + ndev->stats.rx_length_errors++; + + if (status & RX_STATUS_CRC_ERROR) + ndev->stats.rx_crc_errors++; + + } else { + if (--budget < 0) { + /* we got packets, but no quota */ + /* store current ring pointer state */ + ip3902_priv->rx_next_consume = rx_index; + return received; + } else { + struct sk_buff *skb = ip3902_priv->rx_skb[rx_index]; + int length = RX_STATUS_LENGTH(status); + dma_addr_t data_addr; + int data_length; + + ndev->stats.rx_packets++; + ndev->stats.rx_bytes += length; + if (status & RX_STATUS_MULTICAST) + ndev->stats.multicast++; + + skb_put(skb, length - BYTES_IN_ETHERNET_CRC); + skb->protocol = eth_type_trans(skb, ndev); + +#ifdef CONFIG_INET_LRO + if (ip3902_priv->use_lro) + lro_receive_skb(&ip3902_priv->lro_mgr, skb, ip3902_priv); + else + netif_receive_skb(skb); + + ip3902_priv->lro_count++; +#else +#ifdef IP3902_NAPI + netif_receive_skb(skb); +#else + netif_rx(skb); +#endif +#endif + + ip3902_read_rx_desc(ip3902_priv, rx_index, &data_addr, &data_length); + dma_unmap_single(NULL, data_addr, ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); + + ip3902_priv->rx_skb[rx_index] = NULL; + ndev->last_rx = jiffies; + received++; + } + } + rx_index = NEXT_RX(rx_index); + } + + spin_unlock(&ip3902_priv->lock); + ip3902_priv->rx_next_consume = rx_index; + ip3902_eth_rx_refill_descs(ndev, ip3902_priv); + write_index = ip3902_read_reg(ndev, RX_PRODUCE_INDEX_REG); + } while (limit != write_index); + +#ifdef CONFIG_INET_LRO + if (ip3902_priv->use_lro) { + if (timer_pending(&ip3902_priv->lro_timer)) { + mod_timer(&ip3902_priv->lro_timer, jiffies + 2); + } else { + ip3902_priv->lro_timer.expires = jiffies + 2; + add_timer(&ip3902_priv->lro_timer); + } + } +#endif + + return received; +} + +#ifdef IP3902_NAPI +static int ip3902_poll(struct napi_struct *napi, int budget) +{ + struct ip3902_private *ip3902_priv = container_of(napi, struct ip3902_private, napi); + struct net_device *ndev = ip3902_priv->ndev; + int work_done; + + work_done = ip3902_eth_receive_queue(ndev, ip3902_priv, budget); + + if (work_done < budget) { + ip3902_write_reg(ndev, INT_CLEAR_REG, RX_DONE_INT); + ip3902_write_reg(ndev, INT_CLEAR_REG, 0); + netif_rx_complete(ndev, napi); + ip3902_write_reg(ndev, INT_ENABLE_REG, (TX_UNDERRUN_INT | RX_DONE_INT | RX_OVERRUN_INT)); + } + + return work_done; +} +#endif + +#ifdef CONFIG_INET_LRO +static void ip3902_lro_timeout(unsigned long data) +{ + struct ip3902_private *ip3902_priv = (struct ip3902_private *)data; + + spin_lock(&ip3902_priv->lock); + if (ip3902_priv->lro_count <= LRO_THRESHOLD) { + ip3902_priv->use_lro = false; + ip3902_priv->lro_count = 0; + } + lro_flush_all(&ip3902_priv->lro_mgr); + spin_unlock(&ip3902_priv->lock); +} +#endif + +#define ip3902_eth_free_completed_tx_descs(ndev, priv) ip3902_eth_free_tx_descs(ndev, priv, 0) +#define ip3902_eth_free_all_tx_descs(ndev, priv) ip3902_eth_free_tx_descs(ndev, priv, 1) + +static void ip3902_eth_free_tx_descs(struct net_device *ndev, struct ip3902_private *ip3902_priv, int force) +{ + int limit; + + if (force) + limit = ip3902_priv->tx_next_produce; + else + limit = ip3902_read_reg(ndev, TX_CONSUME_INDEX_REG); + + while (ip3902_priv->tx_next_deallocate != limit) { + int length; + int tx_index; + unsigned long status; + dma_addr_t addr; + struct sk_buff *skb; + + tx_index = ip3902_priv->tx_next_deallocate; + + ip3902_priv->tx_next_deallocate = NEXT_TX(tx_index); + ip3902_read_tx_desc(ip3902_priv, tx_index, &addr, &length); + skb = ip3902_priv->tx_skb[tx_index]; + + status = ip3902_read_tx_status(ip3902_priv, tx_index); + if (status & TX_STATUS_ERROR) { + ndev->stats.tx_errors++; + if (status & TX_STATUS_LATE_COLLISION) + ndev->stats.tx_aborted_errors++; + + if (status & (TX_STATUS_MANY_COLLISIONS | TX_STATUS_MANY_DEFER)) + ndev->stats.tx_window_errors++; + + } else { + ndev->stats.tx_packets++; + ndev->stats.tx_bytes += skb->len; + ndev->stats.collisions += TX_STATUS_COLLISIONS(status); + } + + if (skb) + ip3902_priv->tx_skb[tx_index] = NULL; + + if (ip3902_priv->tx_first_desc[tx_index] == true) + dma_unmap_single(NULL, addr, length, DMA_TO_DEVICE); + else + dma_unmap_page(NULL, addr, length, DMA_TO_DEVICE); + + if (skb) + dev_kfree_skb_irq(skb); + } +} + +static void ip3902_reset_tx(struct net_device *ndev, struct ip3902_private *ip3902_priv, int initial) +{ + unsigned long val; + + /* Reset Tx hardware */ + val = ip3902_read_reg(ndev, COMMAND_REG); + val &= ~(COMMAND_TX_RT_ENABLE | COMMAND_TX_ENABLE); + val |= COMMAND_TX_RESET; + ip3902_write_reg(ndev, COMMAND_REG, val); + + if (!initial) + ip3902_eth_free_all_tx_descs(ndev, ip3902_priv); + + ip3902_priv->tx_next_produce = 0; + ip3902_priv->tx_next_deallocate = 0; + + /* Configure Tx registers */ + ip3902_write_reg(ndev, TX_DESC_REG, ip3902_priv->ds_dma + offsetof(struct ip3902_dma_struct, tx_desc)); + ip3902_write_reg(ndev, TX_STATUS_REG, ip3902_priv->ds_dma + offsetof(struct ip3902_dma_struct, tx_status)); + ip3902_write_reg(ndev, TX_DESC_NUMBER_REG, TX_RING_SIZE - 1); + ip3902_write_reg(ndev, TX_PRODUCE_INDEX_REG, ip3902_priv->tx_next_produce); + ip3902_write_reg(ndev, TX_CONSUME_INDEX_REG, ip3902_priv->tx_next_deallocate); +} + +static void ip3902_reset_rx(struct net_device *ndev, struct ip3902_private *ip3902_priv, int init) +{ + unsigned long val; + + /* Reset Rx hardware */ + val = ip3902_read_reg(ndev, COMMAND_REG); + val &= ~COMMAND_RX_ENABLE; + val |= COMMAND_RX_RESET; + ip3902_write_reg(ndev, COMMAND_REG, val); + + /* Set maximum frame size register */ + ip3902_write_reg(ndev, MAXF_REG, ETH_RX_SKB_SIZE); + + if (init) { + ip3902_priv->rx_next_allocate = 0; + ip3902_priv->rx_next_consume = 0; + ip3902_eth_rx_refill_descs(ndev, ip3902_priv); + } + + /* Prepare skb's for Rx (any skb's already prepared will be reused) + * and configure Rx registers */ + ip3902_write_reg(ndev, RX_DESC_REG, ip3902_priv->ds_dma + offsetof(struct ip3902_dma_struct, rx_desc)); + ip3902_write_reg(ndev, RX_STATUS_REG, ip3902_priv->ds_dma + offsetof(struct ip3902_dma_struct, rx_status)); + ip3902_write_reg(ndev, RX_DESC_NUMBER_REG, RX_RING_SIZE - 1); + ip3902_write_reg(ndev, RX_PRODUCE_INDEX_REG, ip3902_priv->rx_next_consume); +} + +static inline void ip3902_start_tx(struct net_device *ndev) +{ + unsigned long val; + + val = ip3902_read_reg(ndev, COMMAND_REG); + val |= COMMAND_TX_ENABLE; + ip3902_write_reg(ndev, COMMAND_REG, val); +} + +static inline void ip3902_start_rx(struct net_device *ndev) +{ + unsigned long val; + + /* First on high-level ... */ + val = ip3902_read_reg(ndev, COMMAND_REG); + val |= (COMMAND_RX_ENABLE | COMMAND_ALLOW_SHORT); + ip3902_write_reg(ndev, COMMAND_REG, val); + + /* ... and then on low-level (after high level is ready to receive) */ + val = ip3902_read_reg(ndev, MAC1_REG); + val |= MAC1_RECEIVE_ENABLE; /* flow control frames won't be passed to driver */ + ip3902_write_reg(ndev, MAC1_REG, val); +} + +/* Interrupt handler body - split out to use both in interrupt handler + * and in net poll controller. + * + * Internal routine, called with lock held. */ +static void ip3902_do_handle_interrupt(struct net_device *ndev, struct ip3902_private *ip3902_priv, unsigned long status) +{ + ip3902_write_reg(ndev, INT_CLEAR_REG, status); + ip3902_write_reg(ndev, INT_CLEAR_REG, 0); + + if (status & TX_UNDERRUN_INT) { + printk(KERN_ERR DRVNAME ": %s: fatal Tx underrun, resetting Tx\n", ndev->name); + ip3902_reset_tx(ndev, ip3902_priv, 0); + ip3902_start_tx(ndev); + } + + if (status & RX_OVERRUN_INT) { + printk(KERN_ERR DRVNAME ": %s: fatal Rx overrun, resetting Rx\n", ndev->name); + ip3902_reset_rx(ndev, ip3902_priv, 0); + ip3902_start_rx(ndev); + } else if (status & RX_DONE_INT) { +#ifdef IP3902_NAPI + /* Disable the Rx interrupt */ + ip3902_write_reg(ndev, INT_ENABLE_REG, (RX_OVERRUN_INT | TX_UNDERRUN_INT)); + netif_rx_schedule(ndev, &ip3902_priv->napi); +#else + ip3902_eth_receive_queue(ndev, ip3902_priv, RX_RING_SIZE); +#endif + } +} + +static irqreturn_t ip3902_interrupt(int irq, void *dev_instance) +{ + struct net_device *ndev = (struct net_device *) dev_instance; + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + unsigned long status; + + status = ip3902_read_reg(ndev, INT_STATUS_REG) & (TX_DONE_INT | TX_UNDERRUN_INT | RX_DONE_INT | RX_OVERRUN_INT); + do { + if (!status) { + return IRQ_NONE; + } else { + ip3902_do_handle_interrupt(ndev, ip3902_priv, status); + status = ip3902_read_reg(ndev, INT_STATUS_REG) & (TX_DONE_INT | TX_UNDERRUN_INT | RX_DONE_INT | RX_OVERRUN_INT); + } + } while (status); + + return IRQ_HANDLED; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +static void ip3902_net_poll(struct net_device *ndev) +{ + disable_irq_lockdep(ndev->irq); + ip3902_interrupt(ndev->irq, ndev); + enable_irq_lockdep(ndev->irq); +} +#endif + +static int eth_alloc_tx_desc_index(struct ip3902_private *ip3902_priv) +{ + int tx_desc_curr; + + tx_desc_curr = ip3902_priv->tx_next_produce; + ip3902_priv->tx_next_produce = NEXT_TX(tx_desc_curr); + + return tx_desc_curr; +} + +static void eth_tx_fill_frag_descs(struct ip3902_private *ip3902_priv, struct sk_buff *skb) +{ + int frag = 0; + int tx_index; + + do { + skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; + unsigned long desc_address; + unsigned long desc_control; + + tx_index = eth_alloc_tx_desc_index(ip3902_priv); + + if (frag == (skb_shinfo(skb)->nr_frags - 1)) { + desc_control = (this_frag->size - 1) | TX_CONTROL_ALL_NOTLAST; + ip3902_priv->tx_skb[tx_index] = skb; + } else { + desc_control = (this_frag->size - 1) | TX_CONTROL_ALL_LAST; + ip3902_priv->tx_skb[tx_index] = NULL; + } + + ip3902_priv->tx_first_desc[tx_index] = false; + desc_address = dma_map_page(NULL, this_frag->page, + this_frag->page_offset, + this_frag->size, + DMA_TO_DEVICE); + ip3902_write_tx_desc(ip3902_priv, tx_index, desc_address, desc_control); + } while (++frag < skb_shinfo(skb)->nr_frags); +} + +static int ip3902_submit_skb_for_tx(struct net_device *ndev, struct sk_buff *skb) +{ + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + int nr_frags; + int free_desc; + int ret = 0; + +#ifdef CONFIG_INET_LRO + if (ip3902_priv->lro_count > LRO_THRESHOLD) + ip3902_priv->use_lro = true; + + ip3902_priv->lro_count = 0; +#endif + + free_desc = ip3902_nr_free_descs(ip3902_priv->tx_next_produce, ip3902_priv->tx_next_deallocate, TX_RING_SIZE); + nr_frags = skb_shinfo(skb)->nr_frags; + + if (free_desc <= nr_frags) { + ip3902_eth_free_completed_tx_descs(ndev, ip3902_priv); + free_desc = ip3902_nr_free_descs(ip3902_priv->tx_next_produce, ip3902_priv->tx_next_deallocate, TX_RING_SIZE); + } + + if (free_desc > nr_frags) { + unsigned long desc_address; + unsigned long desc_control; + int tx_index; + int length; + + tx_index = eth_alloc_tx_desc_index(ip3902_priv); + + if (nr_frags) { + eth_tx_fill_frag_descs(ip3902_priv, skb); + length = skb_headlen(skb); + desc_control = (length - 1) | TX_CONTROL_ALL_NOTLAST; + ip3902_priv->tx_skb[tx_index] = NULL; + } else { + length = skb->len; + desc_control = (length - 1) | TX_CONTROL_ALL_LAST; + ip3902_priv->tx_skb[tx_index] = skb; + } + + ip3902_priv->tx_first_desc[tx_index] = true; + desc_address = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); + + ip3902_write_tx_desc(ip3902_priv, tx_index, desc_address, desc_control); + ip3902_write_reg(ndev, TX_PRODUCE_INDEX_REG, ip3902_priv->tx_next_produce); + ip3902_eth_free_completed_tx_descs(ndev, ip3902_priv); + } else { + ret = -ENOMEM; + } + + return ret; +} + +static int ip3902_start_xmit(struct sk_buff *skb, struct net_device *ndev) +{ + int ret; + + BUG_ON(netif_queue_stopped(ndev)); + BUG_ON(skb == NULL); + ret = ip3902_submit_skb_for_tx(ndev, skb); + + if (ret) { + printk(KERN_ERR "%s: transmit with queue full\n", ndev->name); + netif_stop_queue(ndev); + } else { + ndev->stats.tx_bytes += skb->len; + ndev->stats.tx_packets++; + ndev->trans_start = jiffies; + } + + return ret; /* success */ +} + +static void ip3902_do_set_rx_filter(struct net_device *ndev, struct ip3902_private *ip3902_priv) +{ + unsigned long creg, freg; + + creg = ip3902_read_reg(ndev, COMMAND_REG); + if (ndev->flags & IFF_PROMISC) { + /* If interface is in promiscuous mode, just disable filter */ + ip3902_write_reg(ndev, COMMAND_REG, creg | COMMAND_PROMISC); + return; + } + /* Enable filter */ + ip3902_write_reg(ndev, COMMAND_REG, creg & ~COMMAND_PROMISC); + + /* Frames for self address and broadcast frames are always accepted */ + freg = FILTER_ACCEPT_SELF | FILTER_ACCEPT_BCAST_ANY; + + if (ndev->flags & IFF_ALLMULTI) { + /* Accept all multicast frames */ + freg |= FILTER_ACCEPT_MCAST_ANY; + } else if (ndev->mc_count > 0) { + /* Accept some multicast frames */ + u64 hash_mask = 0; + struct dev_mc_list *mc; + + freg |= FILTER_ACCEPT_MCAST_HASH; + for (mc = ndev->mc_list; mc; mc = mc->next) { + int b = (ether_crc(ETH_ALEN, mc->dmi_addr) >> 23) & 0x3f; + hash_mask |= (1 << b); + } + ip3902_write_reg(ndev, HASH_FILTER_L_REG, hash_mask & 0xffffffff); + ip3902_write_reg(ndev, HASH_FILTER_H_REG, hash_mask >> 32); + } + + ip3902_write_reg(ndev, FILTER_CTRL_REG, freg); +} + +static void ip3902_set_rx_filter(struct net_device *ndev) +{ + struct ip3902_private *ip3902_priv = (struct ip3902_private *)netdev_priv(ndev); + + ip3902_do_set_rx_filter(ndev, ip3902_priv); +} + +static void set_duplex_mode(struct net_device *ndev, int duplex) +{ + unsigned long val; + + if (duplex) { + /* Full Duplex mode */ + + val = ip3902_read_reg(ndev, MAC2_REG); + val |= MAC2_FULL_DUPLEX; + ip3902_write_reg(ndev, MAC2_REG, val); + + ip3902_write_reg(ndev, IPGT_REG, IPGT_FD_VALUE); + + val = ip3902_read_reg(ndev, COMMAND_REG); + val |= COMMAND_FULL_DUPLEX; + ip3902_write_reg(ndev, COMMAND_REG, val); + } else { + /* Half Duplex mode */ + + val = ip3902_read_reg(ndev, MAC2_REG); + val &= ~MAC2_FULL_DUPLEX; + ip3902_write_reg(ndev, MAC2_REG, val); + + ip3902_write_reg(ndev, IPGT_REG, IPGT_HD_VALUE); + + val = ip3902_read_reg(ndev, COMMAND_REG); + val &= ~COMMAND_FULL_DUPLEX; + ip3902_write_reg(ndev, COMMAND_REG, val); + } +} + +static int ip3902_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) +{ + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + unsigned int duplex_changed; + unsigned long flags; + int rc; + + if (!netif_running(ndev)) + return -EINVAL; + + spin_lock_irqsave(&ip3902_priv->mii_lock, flags); + rc = generic_mii_ioctl(&ip3902_priv->mii, if_mii(req), cmd, &duplex_changed); + spin_unlock_irqrestore(&ip3902_priv->mii_lock, flags); + if (duplex_changed) + set_duplex_mode(ndev, ip3902_priv->mii.full_duplex); + + return rc; +} + +/* ethtool ops */ + +static void ip3902_get_drvinfo(struct net_device *ndev, + struct ethtool_drvinfo *info) +{ + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + + strcpy(info->driver, DRVNAME); + strcpy(info->version, DRVVERSION); + strcpy(info->bus_info, ip3902_priv->ndev->name); +} + +static int ip3902_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd) +{ + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + unsigned long flags; + + spin_lock_irqsave(&ip3902_priv->mii_lock, flags); + mii_ethtool_gset(&ip3902_priv->mii, cmd); + spin_lock_irqsave(&ip3902_priv->mii_lock, flags); + + return 0; +} + +static int ip3902_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd) +{ + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + unsigned long flags; + int rc; + + spin_lock_irqsave(&ip3902_priv->mii_lock, flags); + rc = mii_ethtool_sset(&ip3902_priv->mii, cmd); + spin_lock_irqsave(&ip3902_priv->mii_lock, flags); + + return rc; +} + +static int ip3902_nway_reset(struct net_device *ndev) +{ + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + return mii_nway_restart(&ip3902_priv->mii); +} + +static u32 ip3902_get_link(struct net_device *ndev) +{ + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + return mii_link_ok(&ip3902_priv->mii); +} + +static const struct ethtool_ops ip3902_ethtool_ops = { + .get_drvinfo = ip3902_get_drvinfo, + .get_settings = ip3902_get_settings, + .set_settings = ip3902_set_settings, + .nway_reset = ip3902_nway_reset, + .get_link = ip3902_get_link, + .get_sg = ethtool_op_get_sg, + .set_sg = ethtool_op_set_sg, +}; + +/* setup code */ + +static void ip3902_eth_update_mac_address(struct net_device *ndev) +{ + ip3902_write_reg(ndev, SA0_REG, (ndev->dev_addr[5] << 8) | ndev->dev_addr[4]); + ip3902_write_reg(ndev, SA1_REG, (ndev->dev_addr[3] << 8) | ndev->dev_addr[2]); + ip3902_write_reg(ndev, SA2_REG, (ndev->dev_addr[1] << 8) | ndev->dev_addr[0]); +} + +static int ip3902_eth_set_mac_address(struct net_device *ndev, void *addr) +{ + int i; + + for (i = 0; i < 6; i++) + /* +2 is for the offset of the HW addr type */ + ndev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; + + ip3902_eth_update_mac_address(ndev); + return 0; +} + +static void ip3902_hw_deinit(struct net_device *ndev) +{ + unsigned long val; + + /* Stop Rx and Tx hardware and disable interrupts */ + val = ip3902_read_reg(ndev, COMMAND_REG); + val &= ~(COMMAND_TX_ENABLE | COMMAND_RX_ENABLE); + ip3902_write_reg(ndev, COMMAND_REG, val); + ip3902_write_reg(ndev, INT_ENABLE_REG, 0); + + /* Put low-level hardware into reset, and high-level into poweroff */ + ip3902_write_reg(ndev, MAC1_REG, MAC1_SOFT_RESET); + ip3902_write_reg(ndev, POWERDOWN_REG, POWERDOWN_VALUE); +} + +static int ethernet_phy_get(struct net_device *ndev) +{ + int addr; + + for (addr = 1; addr < 32; addr++) { + int stat; + stat = ip3902_mdio_read(ndev, addr, MII_BMSR); + if ((stat != 0) && (stat != 0xffff)) + return addr; + } + printk(KERN_ERR DRVNAME ": could not locate PHY\n"); + return -EIO; +} + +static int ip3902_hw_init(struct net_device *ndev, struct ip3902_private *ip3902_priv) +{ + int ret = 0; + + /* Poweron hardware */ + ip3902_write_reg(ndev, POWERDOWN_REG, 0); + + /* Move low level out of reset (also initialize the registers)*/ + ip3902_write_reg(ndev, MAC1_REG, 0); + ip3902_write_reg(ndev, MAC2_REG, INITIAL_MAC2); + + ip3902_priv->mii.phy_id = ethernet_phy_get(ndev); + + if (ip3902_priv->mii.phy_id < 0) { + ret = ip3902_priv->mii.phy_id; + } else { + ip3902_eth_update_mac_address(ndev); + + /* "Initialize" command register (before resets - those routines + * use read-modify-write operations on that register */ + ip3902_write_reg(ndev, COMMAND_REG, COMMAND_ALLOW_SHORT); + + /* Reset and configure Rx and Tx */ + ip3902_reset_tx(ndev, ip3902_priv, 1); + ip3902_reset_rx(ndev, ip3902_priv, 1); + + /* Initialize Rx filtering */ + ip3902_do_set_rx_filter(ndev, ip3902_priv); + + /* Clear all interrupts, and enable interesting interrupts */ + ip3902_write_reg(ndev, INT_CLEAR_REG, 0xffffffff); + ip3902_write_reg(ndev, INT_CLEAR_REG, 0); + ip3902_write_reg(ndev, INT_ENABLE_REG, (TX_UNDERRUN_INT | RX_DONE_INT | RX_OVERRUN_INT)); + + /* Start Tx and Rx hardware */ + ip3902_start_tx(ndev); + ip3902_start_rx(ndev); + } + return 0; +} + +static int ip3902_open(struct net_device *ndev) +{ + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + int ret; + + dev_dbg(&ip3902_priv->ndev->dev, "%s: open\n", ndev->name); + + ret = request_irq(ndev->irq, ip3902_interrupt, 0, ndev->name, ndev); + if (ret) + return ret; + + ret = ip3902_hw_init(ndev, ip3902_priv); + + if (ret) + return ret; + + mii_check_media(&ip3902_priv->mii, netif_msg_link(ip3902_priv), 1); + set_duplex_mode(ndev, ip3902_priv->mii.full_duplex); + +#ifdef CONFIG_INET_LRO + init_timer(&ip3902_priv->lro_timer); + ip3902_priv->lro_timer.data = (unsigned long) ip3902_priv; + ip3902_priv->lro_timer.function = ip3902_lro_timeout; +#endif + + netif_start_queue(ndev); + +#ifdef IP3902_NAPI + napi_enable(&ip3902_priv->napi); +#endif + + ip3902_priv->running = 1; + + return 0; +} + +static int ip3902_close(struct net_device *ndev) +{ + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + + dev_dbg(&ip3902_priv->ndev->dev, "%s: close\n", ndev->name); + + ip3902_priv->running = 0; + wmb(); + +#ifdef CONFIG_INET_LRO + del_timer(&ip3902_priv->lro_timer); +#endif + +#ifdef IP3902_NAPI + napi_disable(&ip3902_priv->napi); +#endif + + ip3902_hw_deinit(ndev); + + netif_stop_queue(ndev); + + ip3902_eth_free_all_tx_descs(ndev, ip3902_priv); + + free_irq(ndev->irq, ndev); + return 0; +} + +static int parse_mac_address(struct net_device *ndev) +{ + int n = sscanf(mac_address, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &ndev->dev_addr[0], &ndev->dev_addr[1], + &ndev->dev_addr[2], &ndev->dev_addr[3], + &ndev->dev_addr[4], &ndev->dev_addr[5]); + + if (n == 6) + return 0; + + printk(KERN_WARNING DRVNAME": failed to parse mac address string \"%s\"\n", mac_address); + return -EINVAL; +} + +static void ip3902_hw_shutdown(struct net_device *ndev, struct ip3902_private *ip3902_priv) +{ + dma_free_coherent(NULL, sizeof(*(ip3902_priv->ds)), ip3902_priv->ds, ip3902_priv->ds_dma); +} + +static int ip3902_hw_startup(struct net_device *ndev, struct ip3902_private *ip3902_priv) +{ + ip3902_priv->ds = dma_alloc_coherent(NULL, sizeof(*(ip3902_priv->ds)), &ip3902_priv->ds_dma, GFP_KERNEL); + if (!ip3902_priv->ds) { + printk(KERN_ERR DRVNAME ": can't allocate DMA structure\n"); + ip3902_hw_shutdown(ndev, ip3902_priv); + return -ENOMEM; + } + + /* Poweron hardware */ + ip3902_write_reg(ndev, POWERDOWN_REG, 0); + + /* set mii clock */ + ip3902_write_reg(ndev, MCFG_REG, 0x1c); + + /* Move low level out of reset (also initialize the registers)*/ + ip3902_write_reg(ndev, MAC1_REG, 0); + ip3902_write_reg(ndev, MAC2_REG, INITIAL_MAC2); + + if (!mac_address || parse_mac_address(ndev) < 0) { + unsigned long val; + + val = ip3902_read_reg(ndev, SA0_REG); + ndev->dev_addr[5] = (val >> 8) & 255; + ndev->dev_addr[4] = val & 255; + val = ip3902_read_reg(ndev, SA1_REG); + ndev->dev_addr[3] = (val >> 8) & 255; + ndev->dev_addr[2] = val & 255; + val = ip3902_read_reg(ndev, SA2_REG); + ndev->dev_addr[1] = (val >> 8) & 255; + ndev->dev_addr[0] = val & 255; + } + + /* Put low-level hardware into reset, and high-level into poweroff */ + ip3902_write_reg(ndev, MAC1_REG, MAC1_SOFT_RESET); + ip3902_write_reg(ndev, POWERDOWN_REG, POWERDOWN_VALUE); + + return 0; +} + +static int ip3902_init_dev(struct net_device *ndev, struct ip3902_private *ip3902_priv) +{ + int ret; + + ret = ip3902_hw_startup(ndev, ip3902_priv); + + if (!ret) { + ndev->hard_start_xmit = ip3902_start_xmit; + ndev->set_mac_address = ip3902_eth_set_mac_address; + ndev->set_multicast_list = ip3902_set_rx_filter; + ndev->open = ip3902_open; + ndev->stop = ip3902_close; + ndev->do_ioctl = ip3902_ioctl; + ndev->features = 0; +#ifdef CONFIG_NET_POLL_CONTROLLER + ndev->poll_controller = ip3902_net_poll; +#endif + SET_ETHTOOL_OPS(ndev, &ip3902_ethtool_ops); + + ip3902_priv->msg_enable = NETIF_MSG_LINK; + ip3902_priv->mii.phy_id_mask = 0x1f; + ip3902_priv->mii.reg_num_mask = 0x1f; + ip3902_priv->mii.mdio_read = ip3902_mdio_read; + ip3902_priv->mii.mdio_write = ip3902_mdio_write; + ip3902_priv->mii.dev = ndev; + + spin_lock_init(&ip3902_priv->lock); + + ret = register_netdev(ndev); + + if (ret) + ip3902_hw_shutdown(ndev, ip3902_priv); + } + + return ret; +} + +#ifdef CONFIG_INET_LRO +static int ip3902_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv) +{ + unsigned int ip_len; + struct iphdr *iph; + + /* non tcp packet */ + skb_reset_network_header(skb); + iph = ip_hdr(skb); + if (iph->protocol != IPPROTO_TCP) + return -1; + + ip_len = ip_hdrlen(skb); + skb_set_transport_header(skb, ip_len); + *tcph = tcp_hdr(skb); + + /* check if ip header and tcp header are complete */ + if (iph->tot_len < ip_len + tcp_hdrlen(skb)) + return -1; + + *hdr_flags = LRO_IPV4 | LRO_TCP; + *iphdr = iph; + + return 0; +} +#endif + +static int ip3902_remove(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + + platform_set_drvdata(pdev, NULL); + + unregister_netdev(ndev); + + iounmap(ip3902_priv->mem); + release_resource(ip3902_priv->bus); + kfree(ip3902_priv->bus); + + free_netdev(ndev); + + return 0; +} + +/* ip3902_probe + * + * This is the entry point when the platform device system uses to + * notify us of a new device to attach to. Allocate memory, find + * the resources and information passed, and map the necessary registers. +*/ + +static int ip3902_probe(struct platform_device *pdev) +{ + struct net_device *ndev; + struct ip3902_private *ip3902_priv; + struct resource *res; + size_t size; + int ret; + + ndev = alloc_etherdev(sizeof(struct ip3902_private)); + + if (ndev == NULL) + return -ENOMEM; + + ip3902_priv = netdev_priv(ndev); + + memset(ip3902_priv, 0, sizeof(struct ip3902_private)); + + spin_lock_init(&ip3902_priv->mii_lock); + + ip3902_priv->ndev = ndev; + ip3902_priv->pdev = pdev; + +#ifdef IP3902_NAPI + netif_napi_add(ndev, &ip3902_priv->napi, ip3902_poll, IP3902_NAPI_WEIGHT); +#endif + +#ifdef CONFIG_INET_LRO + ip3902_priv->use_lro = false; + ip3902_priv->lro_count = 0; + ip3902_priv->lro_mgr.max_aggr = IP3902_NAPI_WEIGHT; + ip3902_priv->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS; + ip3902_priv->lro_mgr.lro_arr = ip3902_priv->lro_desc; + ip3902_priv->lro_mgr.get_skb_header = ip3902_get_skb_hdr; +#ifdef IP3902_NAPI + ip3902_priv->lro_mgr.features = LRO_F_NAPI; +#else + ip3902_priv->lro_mgr.features = 0; +#endif + ip3902_priv->lro_mgr.dev = ndev; + ip3902_priv->lro_mgr.ip_summed = 0; + ip3902_priv->lro_mgr.ip_summed_aggr = 0; +#endif + + platform_set_drvdata(pdev, ndev); + + /* find the platform resources */ + ndev->irq = platform_get_irq(pdev, 0); + if (ndev->irq < 0) { + dev_err(&pdev->dev, "no IRQ specified\n"); + ret = -ENXIO; + goto exit_mem; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no MEM specified\n"); + ret = -ENXIO; + goto exit_mem; + } + size = (res->end - res->start) + 1; + + ip3902_priv->bus = request_mem_region(res->start & 0x1fffffff, size, pdev->name); + if (ip3902_priv->bus == NULL) { + dev_err(&pdev->dev, "cannot reserve registers\n"); + ret = -ENXIO; + goto exit_mem; + } + + ip3902_priv->mem = ioremap(res->start & 0x1fffffff, size); + ndev->base_addr = (unsigned long)ip3902_priv->mem; + + if (ip3902_priv->mem == NULL) { + dev_err(&pdev->dev, "Cannot ioremap area (%08llx,%08llx)\n", + (unsigned long long)res->start, + (unsigned long long)res->end); + + ret = -ENXIO; + goto exit_req; + } + + SET_NETDEV_DEV(ndev, &pdev->dev); + + /* got resources, now initialise and register device */ + ret = ip3902_init_dev(ndev, ip3902_priv); + if (!ret) { + printk(KERN_INFO "NXP ip3902 10/100 Ethernet platform driver irq %d base %08lx\n", ndev->irq, ndev->base_addr); + return 0; + } + +exit_req: + release_resource(ip3902_priv->bus); + kfree(ip3902_priv->bus); + +exit_mem: + free_netdev(ndev); + + return ret; +} + +/* suspend and resume */ + +#ifdef CONFIG_PM +static int ip3902_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + + ip3902_priv->resume_open = ip3902_priv->running; + + netif_device_detach(ndev); + ip3902_close(ndev); + + return 0; +} + +static int ip3902_resume(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct ip3902_private *ip3902_priv = netdev_priv(ndev); + + netif_device_attach(ndev); + + if (ip3902_priv->resume_open) + ip3902_open(ndev); + + return 0; +} + +#else + #define ip3902_suspend NULL + #define ip3902_resume NULL +#endif + +static struct platform_driver ip3902drv = { + .driver = { + .name = "ip3902-eth", + .owner = THIS_MODULE, + }, + .probe = ip3902_probe, + .remove = ip3902_remove, + .suspend = ip3902_suspend, + .resume = ip3902_resume, +}; + +static int __init ip3902drv_init(void) +{ + return platform_driver_register(&ip3902drv); +} + +static void __exit ip3902drv_exit(void) +{ + platform_driver_unregister(&ip3902drv); +} + +module_init(ip3902drv_init); +module_exit(ip3902drv_exit); + +MODULE_DESCRIPTION("NXP IP3902 10/100 Ethernet platform driver"); +MODULE_AUTHOR("Chris Steel, "); +MODULE_LICENSE("GPL v2"); diff -urN --exclude=.svn linux-2.6.26-rc4.orig/drivers/net/Kconfig linux-2.6.26-rc4/drivers/net/Kconfig --- linux-2.6.26-rc4.orig/drivers/net/Kconfig 2008-06-03 10:56:55.000000000 +0100 +++ linux-2.6.26-rc4/drivers/net/Kconfig 2008-06-03 17:16:59.000000000 +0100 @@ -1884,6 +1884,15 @@ Say Y here if you want to use the NE2000 compatible controller on the Renesas H8/300 processor. +config IP3902 + tristate "NXP IP3902 ethernet hardware support" + depends on SOC_PNX8335 && NET_ETHERNET + select MII + select CRC32 + help + This is a driver for NXP IP3902 ethernet hardware found + in PNX8335 and probably other SOCs. + source "drivers/net/fec_8xx/Kconfig" source "drivers/net/fs_enet/Kconfig" diff -urN --exclude=.svn linux-2.6.26-rc4.orig/drivers/net/Makefile linux-2.6.26-rc4/drivers/net/Makefile --- linux-2.6.26-rc4.orig/drivers/net/Makefile 2008-06-03 10:56:55.000000000 +0100 +++ linux-2.6.26-rc4/drivers/net/Makefile 2008-06-03 17:17:11.000000000 +0100 @@ -122,6 +122,7 @@ obj-$(CONFIG_FORCEDETH) += forcedeth.o obj-$(CONFIG_NE_H8300) += ne-h8300.o obj-$(CONFIG_AX88796) += ax88796.o +obj-$(CONFIG_IP3902) += ip3902.o obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o diff -urN --exclude=.svn linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/gpio.h linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/gpio.h --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/gpio.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/gpio.h 2008-06-05 11:07:19.000000000 +0100 @@ -0,0 +1,171 @@ +/* + * gpio.h: GPIO Support for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H +#define __ASM_MIPS_MACH_PNX833X_GPIO_H + +/* BIG FAT WARNING: races danger! + No protections exist here. Current users are only early init code, + when locking is not needed because no cuncurency yet exists there, + and GPIO IRQ dispatcher, which does locking. + However, if many uses will ever happen, proper locking will be needed + - including locking between different uses +*/ + +#include "pnx833x.h" + +#define SET_REG_BIT(reg, bit) reg |= (1 << (bit)) +#define CLEAR_REG_BIT(reg, bit) reg &= ~(1 << (bit)) + +/* Initialize GPIO to a known state */ +static inline void gpio_init(void) +{ + PNX833X_PIO_DIR = 0; + PNX833X_PIO_DIR2 = 0; + PNX833X_PIO_SEL = 0; + PNX833X_PIO_SEL2 = 0; + PNX833X_PIO_INT_EDGE = 0; + PNX833X_PIO_INT_HI = 0; + PNX833X_PIO_INT_LO = 0; + + /* clear any GPIO interrupt requests */ + PNX833X_PIO_INT_CLEAR = 0xffff; + PNX833X_PIO_INT_CLEAR = 0; + PNX833X_PIO_INT_ENABLE = 0; +} + +/* Select GPIO direction for a pin */ +static inline void gpio_select_input(unsigned int pin) +{ + if (pin < 32) + CLEAR_REG_BIT(PNX833X_PIO_DIR, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31); +} +static inline void gpio_select_output(unsigned int pin) +{ + if (pin < 32) + SET_REG_BIT(PNX833X_PIO_DIR, pin); + else + SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31); +} + +/* Select GPIO or alternate function for a pin */ +static inline void gpio_select_function_io(unsigned int pin) +{ + if (pin < 32) + CLEAR_REG_BIT(PNX833X_PIO_SEL, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31); +} +static inline void gpio_select_function_alt(unsigned int pin) +{ + if (pin < 32) + SET_REG_BIT(PNX833X_PIO_SEL, pin); + else + SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31); +} + +/* Read GPIO pin */ +static inline int gpio_read(unsigned int pin) +{ + if (pin < 32) + return(PNX833X_PIO_IN >> pin) & 1; + else + return(PNX833X_PIO_IN2 >> (pin & 31)) & 1; +} + +/* Write GPIO pin */ +static inline void gpio_write(unsigned int val, unsigned int pin) +{ + if (pin < 32) { + if (val) + SET_REG_BIT(PNX833X_PIO_OUT, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_OUT, pin); + } else { + if (val) + SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31); + else + CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31); + } +} + +/* Configure GPIO interrupt */ +#define GPIO_INT_NONE 0 +#define GPIO_INT_LEVEL_LOW 1 +#define GPIO_INT_LEVEL_HIGH 2 +#define GPIO_INT_EDGE_RISING 3 +#define GPIO_INT_EDGE_FALLING 4 +#define GPIO_INT_EDGE_BOTH 5 +static inline void gpio_setup_irq(int when, unsigned int pin) +{ + switch (when) { + case GPIO_INT_LEVEL_LOW: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_LEVEL_HIGH: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_RISING: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_FALLING: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_BOTH: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + default: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + } +} + +/* Enable/disable GPIO interrupt */ +static inline void gpio_enable_irq(unsigned int pin) +{ + SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); +} +static inline void gpio_disable_irq(unsigned int pin) +{ + CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); +} + +/* Clear GPIO interrupt request */ +static inline void gpio_clear_irq(unsigned int pin) +{ + SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); +} + +#endif diff -urN --exclude=.svn linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/irq.h linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/irq.h --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/irq.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/irq.h 2008-06-05 10:28:19.000000000 +0100 @@ -0,0 +1,138 @@ +/* + * irq.h: IRQ mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H +#define __ASM_MIPS_MACH_PNX833X_IRQ_H +/* + * The "IRQ numbers" are completely virtual. + * + * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48. + * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt, + * numbers 49..64 for (virtual) GPIO interrupts. + * + * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57, + * connected to PIC, which uses core hardware interrupt 2, and also + * a timer interrupt through hardware interrupt 5. + * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt, + * numbers 65..80 for (virtual) GPIO interrupts. + * + */ + +#if defined(CONFIG_SOC_PNX8335) + #define PNX833X_PIC_NUM_IRQ 58 +#else + #define PNX833X_PIC_NUM_IRQ 37 +#endif + +#define MIPS_CPU_NUM_IRQ 8 +#define PNX833X_GPIO_NUM_IRQ 16 + +#define MIPS_CPU_IRQ_BASE 0 +#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ) +#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ) +#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ) + + +#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) + +/* Interrupts supported by PIC */ +#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1) +#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2) +#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3) +#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4) +#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5) +#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6) +#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7) +#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8) +#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9) +#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10) +#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11) +#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12) +#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13) +#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13) +#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14) +#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15) +#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16) +#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17) +#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18) +#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19) +#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20) +#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21) +#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22) +#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23) +#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24) +#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25) +#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26) +#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27) +#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28) +#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29) +#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30) +#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31) +#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32) +#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33) +#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34) +#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35) +#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36) + +#if defined(CONFIG_SOC_PNX8335) +#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37) +#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38) +#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39) +#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40) +#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41) +#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42) +#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43) +#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44) +#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45) +#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46) +#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47) +#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48) +#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49) +#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50) +#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51) +#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52) +#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53) +#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54) +#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55) +#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56) +#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57) +#endif + +/* GPIO interrupts */ +#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0) +#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1) +#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2) +#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3) +#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4) +#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5) +#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6) +#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7) +#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8) +#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9) +#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10) +#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11) +#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12) +#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13) +#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14) +#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15) + +#endif + diff -urN --exclude=.svn linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/pnx833x.h linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/pnx833x.h --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/pnx833x.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/pnx833x.h 2008-06-05 10:11:24.000000000 +0100 @@ -0,0 +1,194 @@ +/* + * pnx833x.h: Register mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H +#define __ASM_MIPS_MACH_PNX833X_PNX833X_H + +/* All regs are accessed in KSEG1 */ +#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul) + +#define PNX833X_REG(offs) *((volatile unsigned long *)(PNX833X_BASE + offs)) + +/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */ + +/* Read access to multibit fields */ +#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) +#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field) + +/* Use PNX833X_FIELD to extract a field from val */ +#define PNX_FIELD(cpu, val, reg, field) \ + (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ + PNX##cpu##_##reg##_##field##_SHIFT) +#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) +#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) +#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) + +/* Use PNX833X_REGFIELD to extract a field from a register */ +#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field) +#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field) +#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field) + + +#define PNX_WRITEFIELD(cpu, val, reg, field) \ + PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \ + ((val) << PNX##cpu##_##reg##_##field##_SHIFT) +#define PNX833X_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(833X, val, reg, field) +#define PNX8330_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(8330, val, reg, field) +#define PNX8335_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(8335, val, reg, field) + + +/* Macros to detect CPU type */ + +#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC) +#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000 +#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12 +#define PNX8330_CONFIG_MODULE_MAJREV 4 +#define PNX8335_CONFIG_MODULE_MAJREV 5 +#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ + PNX8330_CONFIG_MODULE_MAJREV) +#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ + PNX8335_CONFIG_MODULE_MAJREV) + + + +#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) +#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) + +#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) +#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) +#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4) +#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */ +#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 +#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) + +#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) +#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 + +#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0 + +#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004) +#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */ + +#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040) +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000 +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19 + +#define PNX833X_PIO_IN PNX833X_REG(0xF000) +#define PNX833X_PIO_OUT PNX833X_REG(0xF004) +#define PNX833X_PIO_DIR PNX833X_REG(0xF008) +#define PNX833X_PIO_SEL PNX833X_REG(0xF014) +#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020) +#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024) +#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028) +#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0) +#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4) +#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8) +#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C) +#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060) +#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064) +#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068) + +#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000) +#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF) +#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000) +#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF) + +#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000) +#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF) + +#define PNX833X_CONFIG_USB PNX833X_REG(0x7008) + +#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000) +#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF) +#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000) +#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF) + +#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000) +#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF) +#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC) + +#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX833X_IDE_MODULE_ID_VALUE 0xA009 + + +#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004) +#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008) +#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C) +#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010) +#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014) +#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018) +#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C) +#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020) + +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 + +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 + +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9 + +#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000) + +#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) +#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 + +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 + +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 + +#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) +#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0 + +#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \ + PNX833X_MIU_CONFIG_SPI = \ + ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \ + ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \ + ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \ + ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT) + +#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000) +#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF) +#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC) + +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902 + +#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000) +#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF) +#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC) + +#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX8335_SATA_MODULE_ID_VALUE 0xA099 + +#endif diff -urN --exclude=.svn linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/war.h linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/war.h --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/war.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/war.h 2008-06-05 09:34:22.000000000 +0100 @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H +#define __ASM_MIPS_MACH_PNX833X_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ diff -urN --exclude=.svn linux-2.6.26-rc4.orig/include/linux/i2c-id.h linux-2.6.26-rc4/include/linux/i2c-id.h --- linux-2.6.26-rc4.orig/include/linux/i2c-id.h 2008-06-05 11:41:44.000000000 +0100 +++ linux-2.6.26-rc4/include/linux/i2c-id.h 2008-06-04 09:33:51.000000000 +0100 @@ -129,6 +129,7 @@ /* --- PCA 9564 based algorithms */ #define I2C_HW_A_ISA 0x1a0000 /* generic ISA Bus interface card */ +#define I2C_HW_A_PNX0105 0x1a0001 /* NXP PNX833X SoC I2C */ /* --- PowerPC on-chip adapters */ #define I2C_HW_OCP 0x120000 /* IBM on-chip I2C adapter */ diff -urN --exclude=.svn linux-2.6.26-rc4.orig/include/linux/i2c-pnx0105.h linux-2.6.26-rc4/include/linux/i2c-pnx0105.h --- linux-2.6.26-rc4.orig/include/linux/i2c-pnx0105.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/include/linux/i2c-pnx0105.h 2008-06-05 09:32:31.000000000 +0100 @@ -0,0 +1,58 @@ +/* + * i2c-pnx0105.h: driver for PNX833X I2C (IP0105 Block) + * Copyright (C) 2006 Nikita Youshchenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _LINUX_I2C_PNX0105_H +#define _LINUX_I2C_PNX0105_H + +#include +#include +#include + +struct i2c_pnx0105_dev { + unsigned long base; + int irq; + unsigned char clock; /* value to write to freq bits of control reg */ + unsigned char bus_addr; /* bus address for slave mode; currently not supported */ + + int timeout; /* non-zero when timeout was detected */ + wait_queue_head_t wait; + + struct i2c_algo_pca_data algo_data; + struct i2c_adapter adap; +}; + +/* Register area size */ +#define I2C_PNX0105_IO_SIZE 0x1000 + +/* Register offsets */ +#define I2C_PNX0105_CONTROL 0x0000 +#define I2C_PNX0105_DAT 0x0004 +#define I2C_PNX0105_STATUS 0x0008 +#define I2C_PNX0105_ADDRESS 0x000C +#define I2C_PNX0105_STOP 0x0010 +#define I2C_PNX0105_PD 0x0014 +#define I2C_PNX0105_SET_PINS 0x0018 +#define I2C_PNX0105_OBS_PINS 0x001C +#define I2C_PNX0105_INT_STATUS 0x0FE0 +#define I2C_PNX0105_INT_ENABLE 0x0FE4 +#define I2C_PNX0105_INT_CLEAR 0x0FE8 +#define I2C_PNX0105_INT_SET 0x0FEC +#define I2C_PNX0105_POWER_DOWN 0x0FF4 +#define I2C_PNX0105_MODULE_ID 0x0FFC + +#endif From florian.fainelli@telecomint.eu Thu Jun 5 21:43:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 21:43:35 +0100 (BST) Received: from smtp4.int-evry.fr ([157.159.10.71]:26803 "HELO smtp4.int-evry.fr") by ftp.linux-mips.org with SMTP id S28574914AbYFEUnd convert rfc822-to-8bit (ORCPT ); Thu, 5 Jun 2008 21:43:33 +0100 Received: from smtp2.int-evry.fr (smtp2.int-evry.fr [157.159.10.45]) by smtp4.int-evry.fr (Postfix) with ESMTP id 65890FE4090; Thu, 5 Jun 2008 22:43:27 +0200 (CEST) Received: from smtp-ext.int-evry.fr (smtp-ext.int-evry.fr [157.159.11.17]) by smtp2.int-evry.fr (Postfix) with ESMTP id 32BD03EEC75; Thu, 5 Jun 2008 22:43:24 +0200 (CEST) Received: from lenovo.local (60.130.195-77.rev.gaoland.net [77.195.130.60]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp-ext.int-evry.fr (Postfix) with ESMTP id BA0F59007E; Thu, 5 Jun 2008 22:43:23 +0200 (CEST) From: Florian Fainelli To: "Daniel Laird" Subject: Re: [PATCH] : Add support for NXP PNX833x (STB222/5) into linux kernel Date: Thu, 5 Jun 2008 22:43:18 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, ralf@linux-mips.org References: <64660ef00806051245n5ba8ffc5hece63f743d2e2d01@mail.gmail.com> In-Reply-To: <64660ef00806051245n5ba8ffc5hece63f743d2e2d01@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200806052243.18653.florian.fainelli@telecomint.eu> X-INT-MailScanner-Information: Please contact the ISP for more information X-MailScanner-ID: 32BD03EEC75.97174 X-INT-MailScanner: Found to be clean X-INT-MailScanner-SpamCheck: X-INT-MailScanner-From: florian.fainelli@telecomint.eu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19410 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian.fainelli@telecomint.eu Precedence: bulk X-list: linux-mips Hello Daniel, Le Thursday 05 June 2008 21:45:13 Daniel Laird, vous avez crit: > The following patch add support for the NXP PNX833x SOC. More > specifically it adds support for > the STB222/5 variant. This has I2C support, NAND and onboard ethernet > support. You should send the i2c parts to Jean Delvare and Ben Dooks, the I2C maintainers. Ethernet part should be sent to the netdev mailing-list. You can send the other pending parts to their respective maintainers, since your drivers will be either platform drivers, and/or they depend on CONFIG_NXP_STB225, they can be merged now, and get active when MIPS code is merged as well. I have posted some comments below in the body of your email, code looks overall very good. > +/*********************************************** > +* INCLUDE FILES * > +************************************************/ > + > +#include > +#include You might want to get rid of such comments with lines of *, and probably reorder the inclusion to include first linux then asm headers. > +#if defined(CONFIG_SATA_PNX833X) || defined(CONFIG_SATA_PNX833X_MODULE) > +static struct resource pnx833x_sata_resources[] = { > + [0] = { > + .start = PNX8335_SATA_PORTS_START, > + .end = PNX8335_SATA_PORTS_END, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { > + .start = PNX8335_PIC_SATA_INT, > + .end = PNX8335_PIC_SATA_INT, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static struct platform_device pnx833x_sata_device = { > + .name = "pnx833x-sata", > + .id = -1, > + .num_resources = ARRAY_SIZE(pnx833x_sata_resources), > + .resource = pnx833x_sata_resources, > +}; > +#endif What about defining those resources anyway ? > + > +#if defined(CONFIG_MTD_NAND_PLATFORM) || > defined(CONFIG_MTD_NAND_PLATFORM_MODULE) Same here and others below too. > + > +#define STB225_NAND_BASE 0x18000000 /* I/O location(gets > remapped)*/ +#define STB225_NAND_CLE_MASK 0x00100000 /* I/O location > with CLE high */ +#define STB225_NAND_ALE_MASK 0x00010000 /* I/O > location with ALE high */ + You might want to put this in an header file instead. > +void pnx833x_machine_halt(void) > +{ > + printk(KERN_ALERT "\n\nSystem halted.\n\n"); > + > + while (1) > + __asm__ __volatile__ ("wait"); > +} You might want to use cpu_relax(); instead of the assembly wait instruction. > + > +void pnx833x_machine_power_off(void) > +{ > + printk(KERN_ALERT "\n\nPower off not implemented."); > + pnx833x_machine_halt(); > +} And put some less alarming message here, like "*** You can safely turn off the board". > +int __init plat_mem_setup(void) > +{ > + /* fake pci bus to avoid bounce buffers */ > + PCI_DMA_BUS_IS_PHYS = 1; > + > + /* set mips clock to 320MHz */ > +#if defined(CONFIG_SOC_PNX8335) > + PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ); > +#endif > + gpio_init(); /* so it will be ready in board_setup() */ You can move the GPIO code into its own C file, and use arch_initcall to initialise it. Prefixing gpio_init with pnx83xx is better to be consistent with other functions. See below for more comments about the GPIO code. > +static inline unsigned long ip3902_read_reg(struct net_device *ndev, int > reg) +{ > + unsigned long value = readl((void * __iomem)(ndev->base_addr + > reg)); + return value; Useless cast to void * __iomem in general, did your compiler produced a warning on this ? Netdev people will probably ask you to use NAPI unconditionnaly for new drivers. > +#ifdef IP3902_NAPI > +static int ip3902_poll(struct napi_struct *napi, int budget) > +{ > + struct ip3902_private *ip3902_priv = container_of(napi, struct > ip3902_private, napi); > + struct net_device *ndev = ip3902_priv->ndev; > + int work_done; > + > + work_done = ip3902_eth_receive_queue(ndev, ip3902_priv, budget); > + > + if (work_done < budget) { > + ip3902_write_reg(ndev, INT_CLEAR_REG, RX_DONE_INT); > + ip3902_write_reg(ndev, INT_CLEAR_REG, 0); > + netif_rx_complete(ndev, napi); > + ip3902_write_reg(ndev, INT_ENABLE_REG, (TX_UNDERRUN_INT | > RX_DONE_INT | RX_OVERRUN_INT)); > + } > + > + return work_done; > +} > +#endif > +/* BIG FAT WARNING: races danger! > + No protections exist here. Current users are only early init code, > + when locking is not needed because no cuncurency yet exists there, > + and GPIO IRQ dispatcher, which does locking. > + However, if many uses will ever happen, proper locking will be needed > + - including locking between different uses You should consider using the GPIO library, or read what is done for BCM47xx, AU1000 and TX4938. This should be easy since you comply with most of your functions to this GPIO API. Providing your board specific gpio functions, the rest of the API will handle locking and interrupt context for you. Also, prefix your functions so that they will not collide with the other implementations naming scheme. Such functions might be provided by the C file instead, in the archicture code. Remapping GPIO registers or things like that can be done there as well at board boot time. -- Cordialement, Florian Fainelli ------------------------------ From drzeus@drzeus.cx Thu Jun 5 22:03:42 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 22:03:44 +0100 (BST) Received: from server.drzeus.cx ([85.8.24.28]:23526 "EHLO smtp.drzeus.cx") by ftp.linux-mips.org with ESMTP id S28575261AbYFEVDm (ORCPT ); Thu, 5 Jun 2008 22:03:42 +0100 Received: from mjolnir.drzeus.cx (wlan252.drzeus.cx [::ffff:10.8.2.252]) (AUTH: LOGIN drzeus, TLS: TLS 1.0,256bits,RSA_AES_256_CBC_SHA1) by smtp.drzeus.cx with esmtp; Thu, 05 Jun 2008 22:58:31 +0200 id 0000000000120041.0000000048485377.00006685 Date: Thu, 5 Jun 2008 23:03:11 +0200 From: Pierre Ossman To: Manuel Lauss , ralf@linux-mips.org Cc: Sergei Shtylyov , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/9] Alchemy: export get_au1x00_speed for modules Message-ID: <20080605230311.7f98cd1a@mjolnir.drzeus.cx> In-Reply-To: <20080519094953.GA22445@roarinelk.homelinux.net> References: <20080519080339.GA21985@roarinelk.homelinux.net> <20080519080416.GB21985@roarinelk.homelinux.net> <483149E0.6010009@ru.mvista.com> <20080519094953.GA22445@roarinelk.homelinux.net> X-Mailer: Claws Mail 3.4.0 (GTK+ 2.13.1; i386-redhat-linux-gnu) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwCAMAAABg3Am1AAAAAXNSR0IArs4c6QAAADNQTFRFEgwFRSofeTwxZEI1h1lFl1ZHeGBetHZk24VzuZJ43p2GsbKw/Lmg2MTL/NO3/+/Q//fpWFujUwAAAk5JREFUSMeNlVcWnDAMRd0bLux/tVGxiAEzic7hZ+Zd1IU6NtbYdn8daic/cgj52CPqLQ8hOBdjzsD8G2hHsCiPBS2/nTyABi93zvsYUyql1v6KSz30AeUAJLAK1uuDUI94WA7GDsAePtRDfwFRgP7DA8vvwOgQ1R5oYQUKAwOsfwDHDcAcWH+e5xagiooey1SwSAy0L8C7BaDKdgKWoNQtIjYEfHQGzMcKwNgCpLdgBn14ZzXNSPkJWK201vjiHMkXZg7AuQWCA7G2DPTiMSIsLSZxbgEIwlqEjE+9WBu0yaWOHwDLLQE9WmMieCBgtG1IAFgBzo7tlojGtbI3wFljuU4JdL3ghPeO+tFr2QHG0DOBSuN0kofaU302zmKbcTrgAWDUywG0OvXELi6gZScAdq6WnhYgvYDGu0YQjYSZs3ROID0B4y+jjpWyAhjePWkAjKwD5o09xioNBoro/+YQZjzTg8ce1CJtwFvwAMDFBEjv6cgI0P/u0DqtGJOjNSAm4e0jABxsgDYXSADQw2wwsFyzdePCAviE48QexseKNiGcp4jgKNEVAGC7QEwY5+S6Qpf50NzujHrdYgEKH0o8ZJ/AQR8HAGiaugDjG2i4ddZx4wToPwB0gQsEfjyFRKf1M+kLQC8u5iuoX8BhxYCQJPZXQ7LQdDnQR87/BdCpQQSJpREh7EMSQOvpYwJaqbAHgrUXkWehxhmUUjpsQ+IDSHlzEvidywrtDYSpnHVioNbstBLi9o3Dn/WqZ3Nw1pUQy8bN3/QdiPiVUZfpP4cDVEKd2cXEAAAAAElFTkSuQmCC X-Face: @{|$W51qEixc&6}dq_38NM^&.vv|'{O)ae?DMZ1%VYxuhN2}5VpQ!'gx[{V+8Xw'+cV5*491_)-SU2YT8s@4`H;@:ELS'/P(@.JxxJi/C8mG0H#A^R X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19411 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: drzeus@drzeus.cx Precedence: bulk X-list: linux-mips This is a MIME-formatted message. If you see this text it means that your E-mail software does not support MIME-formatted messages. --=_freyr.drzeus.cx-26245-1212699512-0001-2 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Mon, 19 May 2008 11:49:53 +0200 Manuel Lauss wrote: > Hi Sergei, >=20 > >> From 8492076e98c7fd47c9dee53984dbd9568ace357d Mon Sep 17 00:00:00 2001 > >> From: Manuel Lauss > >> Date: Wed, 7 May 2008 13:42:55 +0200 > >> Subject: [PATCH] Alchemy: export get_au1x00_speed for modules > >> > >> au1xmmc.c driver depends on it, so export it for modules. > >> > >> Signed-off-by: Manuel Lauss > >> =20 > > > > I thought that has been merged. >=20 > Yes, Ralf merged it into linux-mips repo, but it is not yet in > mainline and the rest of the patches are against linus' git. >=20 So who should push this to Linus? If this set is the only patches depending on it, it would be easiest if I carry it in my tree. Rgds Pierre --=_freyr.drzeus.cx-26245-1212699512-0001-2 Content-Type: application/pgp-signature; name="signature.asc" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iEYEARECAAYFAkhIVJQACgkQ7b8eESbyJLheAwCdEbCUdthYIFY9xWyPlgzf8j5s NB4AoN7J9S8IZiCVuPjHMjETlskzPz2P =vy/z -----END PGP SIGNATURE----- --=_freyr.drzeus.cx-26245-1212699512-0001-2-- From drzeus@drzeus.cx Thu Jun 5 22:06:20 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 22:06:22 +0100 (BST) Received: from server.drzeus.cx ([85.8.24.28]:39827 "EHLO smtp.drzeus.cx") by ftp.linux-mips.org with ESMTP id S28575311AbYFEVGU (ORCPT ); Thu, 5 Jun 2008 22:06:20 +0100 Received: from mjolnir.drzeus.cx (wlan252.drzeus.cx [::ffff:10.8.2.252]) (AUTH: LOGIN drzeus, TLS: TLS 1.0,256bits,RSA_AES_256_CBC_SHA1) by smtp.drzeus.cx with esmtp; Thu, 05 Jun 2008 23:01:10 +0200 id 0000000000120046.0000000048485416.000066AC Date: Thu, 5 Jun 2008 23:05:52 +0200 From: Pierre Ossman To: Manuel Lauss Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, sshtylyov@ru.mvista.com Subject: Re: [PATCH 8/9] au1xmmc: abort requests early if no card is present Message-ID: <20080605230552.68c14b2d@mjolnir.drzeus.cx> In-Reply-To: <20080519080804.GI21985@roarinelk.homelinux.net> References: <20080519080339.GA21985@roarinelk.homelinux.net> <20080519080804.GI21985@roarinelk.homelinux.net> X-Mailer: Claws Mail 3.4.0 (GTK+ 2.13.1; i386-redhat-linux-gnu) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwCAMAAABg3Am1AAAAAXNSR0IArs4c6QAAADNQTFRFEgwFRSofeTwxZEI1h1lFl1ZHeGBetHZk24VzuZJ43p2GsbKw/Lmg2MTL/NO3/+/Q//fpWFujUwAAAk5JREFUSMeNlVcWnDAMRd0bLux/tVGxiAEzic7hZ+Zd1IU6NtbYdn8daic/cgj52CPqLQ8hOBdjzsD8G2hHsCiPBS2/nTyABi93zvsYUyql1v6KSz30AeUAJLAK1uuDUI94WA7GDsAePtRDfwFRgP7DA8vvwOgQ1R5oYQUKAwOsfwDHDcAcWH+e5xagiooey1SwSAy0L8C7BaDKdgKWoNQtIjYEfHQGzMcKwNgCpLdgBn14ZzXNSPkJWK201vjiHMkXZg7AuQWCA7G2DPTiMSIsLSZxbgEIwlqEjE+9WBu0yaWOHwDLLQE9WmMieCBgtG1IAFgBzo7tlojGtbI3wFljuU4JdL3ghPeO+tFr2QHG0DOBSuN0kofaU302zmKbcTrgAWDUywG0OvXELi6gZScAdq6WnhYgvYDGu0YQjYSZs3ROID0B4y+jjpWyAhjePWkAjKwD5o09xioNBoro/+YQZjzTg8ce1CJtwFvwAMDFBEjv6cgI0P/u0DqtGJOjNSAm4e0jABxsgDYXSADQw2wwsFyzdePCAviE48QexseKNiGcp4jgKNEVAGC7QEwY5+S6Qpf50NzujHrdYgEKH0o8ZJ/AQR8HAGiaugDjG2i4ddZx4wToPwB0gQsEfjyFRKf1M+kLQC8u5iuoX8BhxYCQJPZXQ7LQdDnQR87/BdCpQQSJpREh7EMSQOvpYwJaqbAHgrUXkWehxhmUUjpsQ+IDSHlzEvidywrtDYSpnHVioNbstBLi9o3Dn/WqZ3Nw1pUQy8bN3/QdiPiVUZfpP4cDVEKd2cXEAAAAAElFTkSuQmCC X-Face: @{|$W51qEixc&6}dq_38NM^&.vv|'{O)ae?DMZ1%VYxuhN2}5VpQ!'gx[{V+8Xw'+cV5*491_)-SU2YT8s@4`H;@:ELS'/P(@.JxxJi/C8mG0H#A^R X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19412 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: drzeus@drzeus.cx Precedence: bulk X-list: linux-mips This is a MIME-formatted message. If you see this text it means that your E-mail software does not support MIME-formatted messages. --=_freyr.drzeus.cx-26284-1212699671-0001-2 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Mon, 19 May 2008 10:08:04 +0200 Manuel Lauss wrote: > From ec41439903048bf98e301dbd03426c63156ebc0e Mon Sep 17 00:00:00 2001 > From: Manuel Lauss > Date: Sun, 18 May 2008 15:52:43 +0200 > Subject: [PATCH] au1xmmc: abort requests early if no card is present >=20 > Don't process a request if no card is present. >=20 > Signed-off-by: Manuel Lauss > --- > drivers/mmc/host/au1xmmc.c | 7 +++++++ > 1 files changed, 7 insertions(+), 0 deletions(-) >=20 > diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c > index be09a14..0b30582 100644 > --- a/drivers/mmc/host/au1xmmc.c > +++ b/drivers/mmc/host/au1xmmc.c > @@ -689,6 +689,13 @@ static void au1xmmc_request(struct mmc_host *mmc, st= ruct mmc_request *mrq) > host->mrq =3D mrq; > host->status =3D HOST_S_CMD; > =20 > + /* fail request immediately if no card is present */ > + if (0 =3D=3D au1xmmc_card_inserted(host)) { > + mrq->cmd->error =3D -ETIMEDOUT; > + au1xmmc_finish_request(host); > + return; > + } > + > if (mrq->data) { > FLUSH_FIFO(host); > ret =3D au1xmmc_prepare_data(host, mrq->data); You should use -ENOMEDIUM for this case. Rgds Pierre --=_freyr.drzeus.cx-26284-1212699671-0001-2 Content-Type: application/pgp-signature; name="signature.asc" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iEYEARECAAYFAkhIVTUACgkQ7b8eESbyJLiLtgCg+C7ANMrwgGFwwOyoAHHPyKul GkwAn111N+IAIR83Oecf9H+AMPJ50Drc =dL38 -----END PGP SIGNATURE----- --=_freyr.drzeus.cx-26284-1212699671-0001-2-- From drzeus@drzeus.cx Thu Jun 5 22:08:31 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 22:08:33 +0100 (BST) Received: from server.drzeus.cx ([85.8.24.28]:11142 "EHLO smtp.drzeus.cx") by ftp.linux-mips.org with ESMTP id S28575334AbYFEVIb (ORCPT ); Thu, 5 Jun 2008 22:08:31 +0100 Received: from mjolnir.drzeus.cx (wlan252.drzeus.cx [::ffff:10.8.2.252]) (AUTH: LOGIN drzeus, TLS: TLS 1.0,256bits,RSA_AES_256_CBC_SHA1) by smtp.drzeus.cx with esmtp; Thu, 05 Jun 2008 23:03:21 +0200 id 0000000000120041.000000004848549A.000066C1 Date: Thu, 5 Jun 2008 23:08:03 +0200 From: Pierre Ossman To: Manuel Lauss Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, sshtylyov@ru.mvista.com Subject: Re: [PATCH 9/9] au1xmmc: Add back PB1200/DB1200 MMC activity LED support Message-ID: <20080605230803.75c16798@mjolnir.drzeus.cx> In-Reply-To: <20080519080837.GJ21985@roarinelk.homelinux.net> References: <20080519080339.GA21985@roarinelk.homelinux.net> <20080519080837.GJ21985@roarinelk.homelinux.net> X-Mailer: Claws Mail 3.4.0 (GTK+ 2.13.1; i386-redhat-linux-gnu) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwCAMAAABg3Am1AAAAAXNSR0IArs4c6QAAADNQTFRFEgwFRSofeTwxZEI1h1lFl1ZHeGBetHZk24VzuZJ43p2GsbKw/Lmg2MTL/NO3/+/Q//fpWFujUwAAAk5JREFUSMeNlVcWnDAMRd0bLux/tVGxiAEzic7hZ+Zd1IU6NtbYdn8daic/cgj52CPqLQ8hOBdjzsD8G2hHsCiPBS2/nTyABi93zvsYUyql1v6KSz30AeUAJLAK1uuDUI94WA7GDsAePtRDfwFRgP7DA8vvwOgQ1R5oYQUKAwOsfwDHDcAcWH+e5xagiooey1SwSAy0L8C7BaDKdgKWoNQtIjYEfHQGzMcKwNgCpLdgBn14ZzXNSPkJWK201vjiHMkXZg7AuQWCA7G2DPTiMSIsLSZxbgEIwlqEjE+9WBu0yaWOHwDLLQE9WmMieCBgtG1IAFgBzo7tlojGtbI3wFljuU4JdL3ghPeO+tFr2QHG0DOBSuN0kofaU302zmKbcTrgAWDUywG0OvXELi6gZScAdq6WnhYgvYDGu0YQjYSZs3ROID0B4y+jjpWyAhjePWkAjKwD5o09xioNBoro/+YQZjzTg8ce1CJtwFvwAMDFBEjv6cgI0P/u0DqtGJOjNSAm4e0jABxsgDYXSADQw2wwsFyzdePCAviE48QexseKNiGcp4jgKNEVAGC7QEwY5+S6Qpf50NzujHrdYgEKH0o8ZJ/AQR8HAGiaugDjG2i4ddZx4wToPwB0gQsEfjyFRKf1M+kLQC8u5iuoX8BhxYCQJPZXQ7LQdDnQR87/BdCpQQSJpREh7EMSQOvpYwJaqbAHgrUXkWehxhmUUjpsQ+IDSHlzEvidywrtDYSpnHVioNbstBLi9o3Dn/WqZ3Nw1pUQy8bN3/QdiPiVUZfpP4cDVEKd2cXEAAAAAElFTkSuQmCC X-Face: @{|$W51qEixc&6}dq_38NM^&.vv|'{O)ae?DMZ1%VYxuhN2}5VpQ!'gx[{V+8Xw'+cV5*491_)-SU2YT8s@4`H;@:ELS'/P(@.JxxJi/C8mG0H#A^R X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19413 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: drzeus@drzeus.cx Precedence: bulk X-list: linux-mips This is a MIME-formatted message. If you see this text it means that your E-mail software does not support MIME-formatted messages. --=_freyr.drzeus.cx-26305-1212699802-0001-2 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Mon, 19 May 2008 10:08:37 +0200 Manuel Lauss wrote: > From 5747bd6933bb212ab83044fa79adf185d248513f Mon Sep 17 00:00:00 2001 > From: Manuel Lauss > Date: Sun, 18 May 2008 16:05:56 +0200 > Subject: [PATCH] au1xmmc: Add back PB1200/DB1200 MMC activity LED support. >=20 > Add back PB1200/DB1200 MMC activity LED support just the way > it was done in the original driver source. >=20 > Signed-off-by: Manuel Lauss You might want to consider using the LED subsystem now that the MMC core exports a trigger. Look at my next tree for how sdhci uses it. Rgds Pierre --=_freyr.drzeus.cx-26305-1212699802-0001-2 Content-Type: application/pgp-signature; name="signature.asc" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iEYEARECAAYFAkhIVbgACgkQ7b8eESbyJLhfjwCcDhRypz12rLcHo9OjwCFox0Es VHsAn3rixdlWM6RjXxYs3XZuKtExIKkM =5RbK -----END PGP SIGNATURE----- --=_freyr.drzeus.cx-26305-1212699802-0001-2-- From drzeus@drzeus.cx Thu Jun 5 22:09:52 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 22:09:54 +0100 (BST) Received: from server.drzeus.cx ([85.8.24.28]:23229 "EHLO smtp.drzeus.cx") by ftp.linux-mips.org with ESMTP id S28575359AbYFEVJw (ORCPT ); Thu, 5 Jun 2008 22:09:52 +0100 Received: from mjolnir.drzeus.cx (wlan252.drzeus.cx [::ffff:10.8.2.252]) (AUTH: LOGIN drzeus, TLS: TLS 1.0,256bits,RSA_AES_256_CBC_SHA1) by smtp.drzeus.cx with esmtp; Thu, 05 Jun 2008 23:04:41 +0200 id 0000000000120045.00000000484854E9.000066D5 Date: Thu, 5 Jun 2008 23:09:23 +0200 From: Pierre Ossman To: Manuel Lauss Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, sshtylyov@ru.mvista.com Subject: Re: [PATCH 0/9] au1xmmc updates #3 Message-ID: <20080605230923.0268dd23@mjolnir.drzeus.cx> In-Reply-To: <20080519080339.GA21985@roarinelk.homelinux.net> References: <20080519080339.GA21985@roarinelk.homelinux.net> X-Mailer: Claws Mail 3.4.0 (GTK+ 2.13.1; i386-redhat-linux-gnu) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwCAMAAABg3Am1AAAAAXNSR0IArs4c6QAAADNQTFRFEgwFRSofeTwxZEI1h1lFl1ZHeGBetHZk24VzuZJ43p2GsbKw/Lmg2MTL/NO3/+/Q//fpWFujUwAAAk5JREFUSMeNlVcWnDAMRd0bLux/tVGxiAEzic7hZ+Zd1IU6NtbYdn8daic/cgj52CPqLQ8hOBdjzsD8G2hHsCiPBS2/nTyABi93zvsYUyql1v6KSz30AeUAJLAK1uuDUI94WA7GDsAePtRDfwFRgP7DA8vvwOgQ1R5oYQUKAwOsfwDHDcAcWH+e5xagiooey1SwSAy0L8C7BaDKdgKWoNQtIjYEfHQGzMcKwNgCpLdgBn14ZzXNSPkJWK201vjiHMkXZg7AuQWCA7G2DPTiMSIsLSZxbgEIwlqEjE+9WBu0yaWOHwDLLQE9WmMieCBgtG1IAFgBzo7tlojGtbI3wFljuU4JdL3ghPeO+tFr2QHG0DOBSuN0kofaU302zmKbcTrgAWDUywG0OvXELi6gZScAdq6WnhYgvYDGu0YQjYSZs3ROID0B4y+jjpWyAhjePWkAjKwD5o09xioNBoro/+YQZjzTg8ce1CJtwFvwAMDFBEjv6cgI0P/u0DqtGJOjNSAm4e0jABxsgDYXSADQw2wwsFyzdePCAviE48QexseKNiGcp4jgKNEVAGC7QEwY5+S6Qpf50NzujHrdYgEKH0o8ZJ/AQR8HAGiaugDjG2i4ddZx4wToPwB0gQsEfjyFRKf1M+kLQC8u5iuoX8BhxYCQJPZXQ7LQdDnQR87/BdCpQQSJpREh7EMSQOvpYwJaqbAHgrUXkWehxhmUUjpsQ+IDSHlzEvidywrtDYSpnHVioNbstBLi9o3Dn/WqZ3Nw1pUQy8bN3/QdiPiVUZfpP4cDVEKd2cXEAAAAAElFTkSuQmCC X-Face: @{|$W51qEixc&6}dq_38NM^&.vv|'{O)ae?DMZ1%VYxuhN2}5VpQ!'gx[{V+8Xw'+cV5*491_)-SU2YT8s@4`H;@:ELS'/P(@.JxxJi/C8mG0H#A^R X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19414 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: drzeus@drzeus.cx Precedence: bulk X-list: linux-mips This is a MIME-formatted message. If you see this text it means that your E-mail software does not support MIME-formatted messages. --=_freyr.drzeus.cx-26325-1212699881-0001-2 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Mon, 19 May 2008 10:03:39 +0200 Manuel Lauss wrote: > Hello, >=20 > The following set of patches remove demoboard-specific code from the > au1xmmc.c driver and adds new features. >=20 The role of maintainer is vacant if you want it. *nudge* ;) --=_freyr.drzeus.cx-26325-1212699881-0001-2 Content-Type: application/pgp-signature; name="signature.asc" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iEYEARECAAYFAkhIVggACgkQ7b8eESbyJLjmZQCgvOjMBWmXUaowz3LOXda2GWwC yEQAnR4+cYGtHueM1rSRZFrThlvTu5RM =LfR8 -----END PGP SIGNATURE----- --=_freyr.drzeus.cx-26325-1212699881-0001-2-- From dmitri.vorobiev@movial.fi Thu Jun 5 22:34:16 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 22:34:19 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:58838 "HELO smtp.movial.fi") by ftp.linux-mips.org with SMTP id S28575864AbYFEVeQ convert rfc822-to-8bit (ORCPT ); Thu, 5 Jun 2008 22:34:16 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id E13B6C803F; Fri, 6 Jun 2008 00:34:10 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id 9J+EoFurkprS; Fri, 6 Jun 2008 00:34:10 +0300 (EEST) Received: from webmail.movial.fi (webmail.movial.fi [62.236.91.25]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.movial.fi (Postfix) with ESMTP id C20FDC801D; Fri, 6 Jun 2008 00:34:10 +0300 (EEST) Received: by webmail.movial.fi (Postfix, from userid 33) id B037023CD79; Fri, 6 Jun 2008 00:34:10 +0300 (EEST) Received: from 84.249.59.97 (SquirrelMail authenticated user dvorobye) by webmail.movial.fi with HTTP; Fri, 6 Jun 2008 00:34:10 +0300 (EEST) Message-ID: <38408.84.249.59.97.1212701650.squirrel@webmail.movial.fi> In-Reply-To: <20080605183854.GN25477@mit.edu> References: <20080512130604.GA15008@deprecation.cyrius.com> <90edad820805120654n50f7a00cm3c7b4a4f9346d5ea@mail.gmail.com> <20080512143426.GB7029@mit.edu> <90edad820805120746l61e67362vbd177d63e8b05dc8@mail.gmail.com> <20080513045028.GC22226@linux-mips.org> <20080528070637.GA10393@deprecation.cyrius.com> <20080605111148.GA4483@deprecation.cyrius.com> <1212664977.4840.6.camel@sd048.hel.movial.fi> <20080605183854.GN25477@mit.edu> Date: Fri, 6 Jun 2008 00:34:10 +0300 (EEST) Subject: Re: ext4dev build failure on mips: "empty_zero_page" undefined From: "Vorobiev Dmitri" To: "Theodore Tso" Cc: "Dmitri Vorobiev" , "Martin Michlmayr" , "Ralf Baechle" , "Dmitri Vorobiev" , linux-mips@linux-mips.org, linux-ext4@vger.kernel.org User-Agent: SquirrelMail/1.4.9a MIME-Version: 1.0 Content-Type: text/plain;charset=iso-8859-15 X-Priority: 3 (Normal) Importance: Normal Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19415 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips Theodore Tso wrote: > > If you really insist I suppose we could have a MIPS specific patch > where we allocate a 4k page and zero it, so we can use it from our > kernel code because you don't want to export and make available the > ZERO_PAGE that gets used by the rest of the kernel, but that seems > awfully silly, and would be a waste of 4k of memory..... Someone from > MIPS land would have to test it, as well, as I dont think any of the > ext4 developers have access to a MIPS platform. Ted, Ralf seems to be unwilling to accept the ZERO_PAGE() export. If you send the MIPS-specific patch, I can do the testing for you as I have a MIPS Malta board at my disposal. Thanks, Dmitri From ths@networkno.de Thu Jun 5 22:51:55 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Jun 2008 22:51:57 +0100 (BST) Received: from relay01.mx.bawue.net ([193.7.176.67]:30389 "HELO relay01.mx.bawue.net") by ftp.linux-mips.org with SMTP id S28575467AbYFEVvz (ORCPT ); Thu, 5 Jun 2008 22:51:55 +0100 Received: from lagash (88-106-136-149.dynamic.dsl.as9105.com [88.106.136.149]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by relay01.mx.bawue.net (Postfix) with ESMTP id 5603448916; Thu, 5 Jun 2008 23:51:54 +0200 (CEST) Received: from ths by lagash with local (Exim 4.69) (envelope-from ) id 1K4NNA-0001ea-8L; Thu, 05 Jun 2008 22:51:52 +0100 Date: Thu, 5 Jun 2008 22:51:52 +0100 From: Thiemo Seufer To: Vorobiev Dmitri Cc: Theodore Tso , Martin Michlmayr , Ralf Baechle , Dmitri Vorobiev , linux-mips@linux-mips.org, linux-ext4@vger.kernel.org Subject: Re: ext4dev build failure on mips: "empty_zero_page" undefined Message-ID: <20080605215152.GB15504@networkno.de> References: <20080512130604.GA15008@deprecation.cyrius.com> <90edad820805120654n50f7a00cm3c7b4a4f9346d5ea@mail.gmail.com> <20080512143426.GB7029@mit.edu> <90edad820805120746l61e67362vbd177d63e8b05dc8@mail.gmail.com> <20080513045028.GC22226@linux-mips.org> <20080528070637.GA10393@deprecation.cyrius.com> <20080605111148.GA4483@deprecation.cyrius.com> <1212664977.4840.6.camel@sd048.hel.movial.fi> <20080605183854.GN25477@mit.edu> <38408.84.249.59.97.1212701650.squirrel@webmail.movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <38408.84.249.59.97.1212701650.squirrel@webmail.movial.fi> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19416 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Vorobiev Dmitri wrote: > Theodore Tso wrote: > > > > If you really insist I suppose we could have a MIPS specific patch > > where we allocate a 4k page and zero it, so we can use it from our > > kernel code because you don't want to export and make available the > > ZERO_PAGE that gets used by the rest of the kernel, but that seems > > awfully silly, and would be a waste of 4k of memory..... Someone from > > MIPS land would have to test it, as well, as I dont think any of the > > ext4 developers have access to a MIPS platform. > > Ted, Ralf seems to be unwilling to accept the ZERO_PAGE() export. If you > send the MIPS-specific patch, I can do the testing for you as I have a > MIPS Malta board at my disposal. AFAIU the problematic case are systems with R4000/R4400 SC/MC CPUs since they use 8 zero pages of different color. Have a look at arch/mips/mm/init.c:setup_zero_pages. Thiemo From dvomlehn@cisco.com Fri Jun 6 02:25:28 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 02:25:30 +0100 (BST) Received: from sj-iport-6.cisco.com ([171.71.176.117]:35886 "EHLO sj-iport-6.cisco.com") by ftp.linux-mips.org with ESMTP id S28576363AbYFFBZ2 (ORCPT ); Fri, 6 Jun 2008 02:25:28 +0100 X-IronPort-AV: E=Sophos;i="4.27,598,1204531200"; d="scan'208";a="109172505" Received: from sj-dkim-2.cisco.com ([171.71.179.186]) by sj-iport-6.cisco.com with ESMTP; 05 Jun 2008 18:25:21 -0700 Received: from sj-core-2.cisco.com (sj-core-2.cisco.com [171.71.177.254]) by sj-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id m561PLDF002740; Thu, 5 Jun 2008 18:25:21 -0700 Received: from cliff.cisco.com (cliff.cisco.com [171.69.11.141]) by sj-core-2.cisco.com (8.13.8/8.13.8) with ESMTP id m561PKgf002787; Fri, 6 Jun 2008 01:25:20 GMT Received: from [127.0.0.1] ([64.101.20.200]) by cliff.cisco.com (8.6.12/8.6.5) with ESMTP id BAA23770; Fri, 6 Jun 2008 01:25:18 GMT Message-ID: <484891DA.2080202@cisco.com> Date: Thu, 05 Jun 2008 18:24:42 -0700 From: David VomLehn User-Agent: Thunderbird 2.0.0.14 (Windows/20080421) MIME-Version: 1.0 To: wangbj@dslab.lzu.edu.cn CC: Chetan Nanda , linux-mips@linux-mips.org Subject: Re: understanding head.S References: <7f245da80806050302m6b449e6m1f84dc7ef7efff46@mail.gmail.com> <1212664525.24330.22.camel@localhost.dslab> In-Reply-To: <1212664525.24330.22.camel@localhost.dslab> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=3121; t=1212715521; x=1213579521; c=relaxed/simple; s=sjdkim2002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20Re=3A=20understanding=20head.S |Sender:=20; bh=r5Ecb04ZaYMY8B/kTL/JGbDJf/Wfq9ISIR8yQvT/x2M=; b=eXJGuGEKq/7HvUW7wBxod7xf2OKqu3xIc1y82cyvmezliZcxVSxWHccwJr 6TviE+ehqewYHyqwazo9vSnmmbPIlGB27wifcOgVQ4uyp9yL4JM/y5imF2Zb dJ5SukPE1f; Authentication-Results: sj-dkim-2; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim2002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19417 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Wang, Baojun wrote: > 在 2008-06-05四的 15:32 +0530，Chetan Nanda写道： > >> Hi All, >> I was reading the boot code for MIPS. >> in head.S file before jumping to 'start_kernel' it calculate the stack >> pointer address as follow: >> >> " >> PTR_LA $28, init_thread_union >> PTR_ADDIU sp, $28, _THREAD_SIZE - 32 >> > make sp point to the stack top so that we can allocate stack space > later, -32 is a reserved area for local variable, saved GPR, arguments > (function stack frame).. due to the abi > The MIPS ABI, whose official name is "System V Application Binary Interface: MIPS(r) Processor Supplement, 3rd Edition", may be found at http://math-atlas.sourceforge.net/devel/assembly/mipsabi32.pdf.. The code generated by gcc does not conform to the MIPS ABI in all cases, but it is the closest thing we have to a standard. The init_thread_union item is a pre-allocated stack area. The PTR_LA loads the address of the beginning of that item, but since the stack grows down, toward smaller addresses, we need to set the stack pointer to the highest address in the stack area. I'm pretty sure the MIPS ABI doesn't mention anything about the 32-byte area as it doesn't address the case of how kernel stacks should be initialized. It's not clear to me what it's there for, but it might be helpful for detecting stack underflows or for giving a little extra space before a buffer overflow corrupts other kernel data structures. >> set_saved_sp sp, t0, t1 >> > set_saved_sp is defined (as a assembler macro) in > include/asm-mips/stackframe.h (if you're using vim, I think it will be > easy to use vim with cscope..) > We must load the stack pointer with pointer to a valid kernel stack before calling any C code to handle interrupts or exceptions. The assembly language macro set_saved_sp is how we store the kernel stack pointer to use in such a case. The SAVE_SOME macro is generally used to restore the stack pointer. >> PTR_SUBU sp, 4 * SZREG # init stack pointer >> > SZREG is defined to the general purpose register size, it is 32bit in > MIPS32 and 64bit in MIPS64, so the last line allocates 16/32 bytes to > build a stack frame.. You could refer to the MIPS ABI if you need > further information (the kernel don't follow the standard ABI all the > time though..) > The MIPS ABI states that the caller of a function must reserve space for four arguments, which are passed in the registers a0-a3, even if the function being called is not being passed four arguments. Since SZREG is the size of one register, 4 * SZREG reserves enough space for these four arguments. See the section "C Stack Frame" on page 3-46 and Figures 3-37 and Figure 3-38 in the MIPS ABI for details about what C stack frames look like. >> Can anyone please explains me this 4 lines of code? >> Why ' _THREAD_SIZE - 32' is added in 'sp' ? >> What 'set_saved_sp' will do ? >> and then why we subtract '4 * SZREG' from 'sp' ? >> >> Please hep me to understand this code better. >> >> Thanks, >> Chetan Nanda >> From dmitri.vorobiev@movial.fi Fri Jun 6 07:57:49 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 07:57:52 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:9649 "HELO smtp.movial.fi") by ftp.linux-mips.org with SMTP id S20037413AbYFFG5t (ORCPT ); Fri, 6 Jun 2008 07:57:49 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 1F588C803F; Fri, 6 Jun 2008 09:57:43 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id PL4QcO-BG5Tq; Fri, 6 Jun 2008 09:57:43 +0300 (EEST) Received: from [172.17.49.48] (sd048.hel.movial.fi [172.17.49.48]) by smtp.movial.fi (Postfix) with ESMTP id F3D2FC801D; Fri, 6 Jun 2008 09:57:42 +0300 (EEST) Message-ID: <4848DFEC.1010800@movial.fi> Date: Fri, 06 Jun 2008 09:57:48 +0300 From: Dmitri Vorobiev Organization: Movial Creative Technologies User-Agent: Icedove 1.5.0.14eol (X11/20080509) MIME-Version: 1.0 To: Thiemo Seufer CC: Theodore Tso , Martin Michlmayr , Ralf Baechle , Dmitri Vorobiev , linux-mips@linux-mips.org, linux-ext4@vger.kernel.org Subject: Re: ext4dev build failure on mips: "empty_zero_page" undefined References: <20080512130604.GA15008@deprecation.cyrius.com> <90edad820805120654n50f7a00cm3c7b4a4f9346d5ea@mail.gmail.com> <20080512143426.GB7029@mit.edu> <90edad820805120746l61e67362vbd177d63e8b05dc8@mail.gmail.com> <20080513045028.GC22226@linux-mips.org> <20080528070637.GA10393@deprecation.cyrius.com> <20080605111148.GA4483@deprecation.cyrius.com> <1212664977.4840.6.camel@sd048.hel.movial.fi> <20080605183854.GN25477@mit.edu> <38408.84.249.59.97.1212701650.squirrel@webmail.movial.fi> <20080605215152.GB15504@networkno.de> In-Reply-To: <20080605215152.GB15504@networkno.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19418 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips Thiemo Seufer wrote: > Vorobiev Dmitri wrote: >> Theodore Tso wrote: >>> If you really insist I suppose we could have a MIPS specific patch >>> where we allocate a 4k page and zero it, so we can use it from our >>> kernel code because you don't want to export and make available the >>> ZERO_PAGE that gets used by the rest of the kernel, but that seems >>> awfully silly, and would be a waste of 4k of memory..... Someone from >>> MIPS land would have to test it, as well, as I dont think any of the >>> ext4 developers have access to a MIPS platform. >> Ted, Ralf seems to be unwilling to accept the ZERO_PAGE() export. If you >> send the MIPS-specific patch, I can do the testing for you as I have a >> MIPS Malta board at my disposal. > > AFAIU the problematic case are systems with R4000/R4400 SC/MC CPUs > since they use 8 zero pages of different color. Have a look at > arch/mips/mm/init.c:setup_zero_pages. OK, thanks for the info. However, I won't be able to tackle into the issue during this and the next week as I'm having a business trip. Therefore, if the issue is urgent, I'd be grateful if someone could take over. Thanks, Dmitri From mano@roarinelk.homelinux.net Fri Jun 6 08:16:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 08:16:49 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:29353 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20022857AbYFFHQr (ORCPT ); Fri, 6 Jun 2008 08:16:47 +0100 Received: (qmail 16539 invoked by uid 1000); 6 Jun 2008 09:16:46 +0200 Date: Fri, 6 Jun 2008 09:16:46 +0200 From: Manuel Lauss To: Pierre Ossman Cc: ralf@linux-mips.org, Sergei Shtylyov , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/9] Alchemy: export get_au1x00_speed for modules Message-ID: <20080606071646.GA16498@roarinelk.homelinux.net> References: <20080519080339.GA21985@roarinelk.homelinux.net> <20080519080416.GB21985@roarinelk.homelinux.net> <483149E0.6010009@ru.mvista.com> <20080519094953.GA22445@roarinelk.homelinux.net> <20080605230311.7f98cd1a@mjolnir.drzeus.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080605230311.7f98cd1a@mjolnir.drzeus.cx> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19419 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hi Folks, On Thu, Jun 05, 2008 at 11:03:11PM +0200, Pierre Ossman wrote: > On Mon, 19 May 2008 11:49:53 +0200 > Manuel Lauss wrote: > > > Hi Sergei, > > > > >> From 8492076e98c7fd47c9dee53984dbd9568ace357d Mon Sep 17 00:00:00 2001 > > >> From: Manuel Lauss > > >> Date: Wed, 7 May 2008 13:42:55 +0200 > > >> Subject: [PATCH] Alchemy: export get_au1x00_speed for modules > > >> > > >> au1xmmc.c driver depends on it, so export it for modules. > > >> > > >> Signed-off-by: Manuel Lauss > > >> > > > > > > I thought that has been merged. > > > > Yes, Ralf merged it into linux-mips repo, but it is not yet in > > mainline and the rest of the patches are against linus' git. > > > > So who should push this to Linus? If this set is the only patches > depending on it, it would be easiest if I carry it in my tree. I'd prefer if you (Pierre) carried them all since they all depend on each other (kind of, anyway). And it seems Ralf has gone silent anyway :) Thank you! Manuel Lauss From mano@roarinelk.homelinux.net Fri Jun 6 08:17:30 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 08:17:32 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:23249 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20022937AbYFFHRa (ORCPT ); Fri, 6 Jun 2008 08:17:30 +0100 Received: (qmail 16558 invoked by uid 1000); 6 Jun 2008 09:17:29 +0200 Date: Fri, 6 Jun 2008 09:17:29 +0200 From: Manuel Lauss To: Pierre Ossman Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, sshtylyov@ru.mvista.com Subject: Re: [PATCH 8/9] au1xmmc: abort requests early if no card is present Message-ID: <20080606071729.GB16498@roarinelk.homelinux.net> References: <20080519080339.GA21985@roarinelk.homelinux.net> <20080519080804.GI21985@roarinelk.homelinux.net> <20080605230552.68c14b2d@mjolnir.drzeus.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080605230552.68c14b2d@mjolnir.drzeus.cx> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19420 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hi Pierre, On Thu, Jun 05, 2008 at 11:05:52PM +0200, Pierre Ossman wrote: > On Mon, 19 May 2008 10:08:04 +0200 > Manuel Lauss wrote: > > > From ec41439903048bf98e301dbd03426c63156ebc0e Mon Sep 17 00:00:00 2001 > > From: Manuel Lauss > > Date: Sun, 18 May 2008 15:52:43 +0200 > > Subject: [PATCH] au1xmmc: abort requests early if no card is present > > > > Don't process a request if no card is present. > > > > Signed-off-by: Manuel Lauss > > --- > > drivers/mmc/host/au1xmmc.c | 7 +++++++ > > 1 files changed, 7 insertions(+), 0 deletions(-) > > > > diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c > > index be09a14..0b30582 100644 > > --- a/drivers/mmc/host/au1xmmc.c > > +++ b/drivers/mmc/host/au1xmmc.c > > @@ -689,6 +689,13 @@ static void au1xmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) > > host->mrq = mrq; > > host->status = HOST_S_CMD; > > > > + /* fail request immediately if no card is present */ > > + if (0 == au1xmmc_card_inserted(host)) { > > + mrq->cmd->error = -ETIMEDOUT; > > + au1xmmc_finish_request(host); > > + return; > > + } > > + > > if (mrq->data) { > > FLUSH_FIFO(host); > > ret = au1xmmc_prepare_data(host, mrq->data); > > You should use -ENOMEDIUM for this case. Didn't know it existed, consider it changed. Thanks! Manuel Lauss From mano@roarinelk.homelinux.net Fri Jun 6 08:18:34 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 08:18:36 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:31415 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20023306AbYFFHSe (ORCPT ); Fri, 6 Jun 2008 08:18:34 +0100 Received: (qmail 16577 invoked by uid 1000); 6 Jun 2008 09:18:31 +0200 Date: Fri, 6 Jun 2008 09:18:31 +0200 From: Manuel Lauss To: Pierre Ossman Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, sshtylyov@ru.mvista.com Subject: Re: [PATCH 0/9] au1xmmc updates #3 Message-ID: <20080606071831.GC16498@roarinelk.homelinux.net> References: <20080519080339.GA21985@roarinelk.homelinux.net> <20080605230923.0268dd23@mjolnir.drzeus.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080605230923.0268dd23@mjolnir.drzeus.cx> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19421 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hi Pierre, On Thu, Jun 05, 2008 at 11:09:23PM +0200, Pierre Ossman wrote: > On Mon, 19 May 2008 10:03:39 +0200 > Manuel Lauss wrote: > > > Hello, > > > > The following set of patches remove demoboard-specific code from the > > au1xmmc.c driver and adds new features. > > > > The role of maintainer is vacant if you want it. *nudge* ;) I'll do it as long as I have hardware or you find someone better. Thanks! Manuel Lauss From mano@roarinelk.homelinux.net Fri Jun 6 08:46:00 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 08:46:03 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:51388 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20023148AbYFFHp5 (ORCPT ); Fri, 6 Jun 2008 08:45:57 +0100 Received: (qmail 16781 invoked by uid 1000); 6 Jun 2008 09:45:56 +0200 Date: Fri, 6 Jun 2008 09:45:56 +0200 From: Manuel Lauss To: Pierre Ossman Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, sshtylyov@ru.mvista.com Subject: Re: [PATCH 9/9] au1xmmc: Add back PB1200/DB1200 MMC activity LED support Message-ID: <20080606074556.GE16498@roarinelk.homelinux.net> References: <20080519080339.GA21985@roarinelk.homelinux.net> <20080519080837.GJ21985@roarinelk.homelinux.net> <20080605230803.75c16798@mjolnir.drzeus.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080605230803.75c16798@mjolnir.drzeus.cx> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19422 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hi Pierre, On Thu, Jun 05, 2008 at 11:08:03PM +0200, Pierre Ossman wrote: > On Mon, 19 May 2008 10:08:37 +0200 > Manuel Lauss wrote: > > > From 5747bd6933bb212ab83044fa79adf185d248513f Mon Sep 17 00:00:00 2001 > > From: Manuel Lauss > > Date: Sun, 18 May 2008 16:05:56 +0200 > > Subject: [PATCH] au1xmmc: Add back PB1200/DB1200 MMC activity LED support. > > > > Add back PB1200/DB1200 MMC activity LED support just the way > > it was done in the original driver source. > > > > Signed-off-by: Manuel Lauss > > You might want to consider using the LED subsystem now that the MMC > core exports a trigger. Look at my next tree for how sdhci uses it. I tried that originally. The LED subsystem seems quite complex for something as simple as turning on a bit in a register. I don't have a DB1200 to test so I went the safe route and added a simple callback to toggle the LED bit in the DB1200 FPGA. I'll try to come up with something over the weekend and then resend the whole series. Thanks! Manuel Lauss From daniel.j.laird@googlemail.com Fri Jun 6 09:32:17 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 09:32:20 +0100 (BST) Received: from hs-out-0708.google.com ([64.233.178.243]:42563 "EHLO hs-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S20026335AbYFFIcR convert rfc822-to-8bit (ORCPT ); Fri, 6 Jun 2008 09:32:17 +0100 Received: by hs-out-0708.google.com with SMTP id x43so693058hsb.0 for ; Fri, 06 Jun 2008 01:32:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:sender :to:subject:cc:mime-version:content-type:content-transfer-encoding :content-disposition:x-google-sender-auth; bh=Go2P2G0qNEcYeyCEmD5pP95ZAtBbgwVUBSojMN2kOs0=; b=pX8lIwwF7pyc03lzAIchY5xlovNnb7PgRLTGd1/tMFS+QxnE3+eBDqIeppQXfCn2+W BaUGVN5lTZo3BEJuR/qcpP/jxeoeKjqPTdhWmCa0FHOk4owEaDCrKPmCdo/kEvl8dUnI S2Xo0wvKKh9zvNNPg1Os10hC3nykDWyiK28cc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=message-id:date:from:sender:to:subject:cc:mime-version:content-type :content-transfer-encoding:content-disposition:x-google-sender-auth; b=xw8JwuctoZrTkYYucCvGxSwVsUUW87k8f6YDg02k9Alvuv2sBiUJWzcsBSzI1+ERlm 6OKapvgkzVS2xCp2Hkz1iapaJonKkQwiwu37lRrqHzPtZJVN0cdUugIAY2+/2JBqCHMn xc1iXRQqf2ydxTxcaXwDJ87KBxvuk+wUKfoa8= Received: by 10.90.119.20 with SMTP id r20mr2952477agc.60.1212741135564; Fri, 06 Jun 2008 01:32:15 -0700 (PDT) Received: by 10.90.70.11 with HTTP; Fri, 6 Jun 2008 01:32:15 -0700 (PDT) Message-ID: <64660ef00806060132j1aab8d9fh968cbf3f2fc56bc2@mail.gmail.com> Date: Fri, 6 Jun 2008 09:32:15 +0100 From: "Daniel Laird" To: "Florian Fainelli" , "Daniel Laird" Subject: RE: [PATCH] : Add support for NXP PNX833x (STB222/5) into linux kernel Cc: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Content-Disposition: inline X-Google-Sender-Auth: b1cc2a38c41178a4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19423 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: daniel.j.laird@nxp.com Precedence: bulk X-list: linux-mips > From: florian.fainelli@telecomint.eu > To: daniel.j.laird@nxp.com > Subject: Re: [PATCH] : Add support for NXP PNX833x (STB222/5) into linux kernel > Date: Thu, 5 Jun 2008 22:43:18 +0200 > CC: linux-mips@linux-mips.org; ralf@linux-mips.org > > Hello Daniel, > > Le Thursday 05 June 2008 21:45:13 Daniel Laird, vous avez crit : > > The following patch add support for the NXP PNX833x SOC. More > > specifically it adds support for > > the STB222/5 variant. This has I2C support, NAND and onboard ethernet > > support. > > You should send the i2c parts to Jean Delvare and Ben Dooks, the I2C > maintainers. Ethernet part should be sent to the netdev mailing-list. > > You can send the other pending parts to their respective maintainers, since > your drivers will be either platform drivers, and/or they depend on > CONFIG_NXP_STB225, they can be merged now, and get active when MIPS code is > merged as well. > > I have posted some comments below in the body of your email, code looks > overall very good. > > > +/*********************************************** > > +* INCLUDE FILES * > > +************************************************/ > > + > > +#include > > +#include > > You might want to get rid of such comments with lines of *, and probably > reorder the inclusion to include first linux then asm headers. Agreed. > > > +#if defined(CONFIG_SATA_PNX833X) || defined(CONFIG_SATA_PNX833X_MODULE) > > +static struct resource pnx833x_sata_resources[] = { > > + [0] = { > > + .start = PNX8335_SATA_PORTS_START, > > + .end = PNX8335_SATA_PORTS_END, > > + .flags = IORESOURCE_MEM, > > + }, > > + [1] = { > > + .start = PNX8335_PIC_SATA_INT, > > + .end = PNX8335_PIC_SATA_INT, > > + .flags = IORESOURCE_IRQ, > > + }, > > +}; > > + > > +static struct platform_device pnx833x_sata_device = { > > + .name = "pnx833x-sata", > > + .id = -1, > > + .num_resources = ARRAY_SIZE(pnx833x_sata_resources), > > + .resource = pnx833x_sata_resources, > > +}; > > +#endif > > What about defining those resources anyway ? > > + > > +#if defined(CONFIG_MTD_NAND_PLATFORM) || > > defined(CONFIG_MTD_NAND_PLATFORM_MODULE) > > Same here and others below too. > Is there any harm in having them always defined even if not implemented? I was playing safe. > > + > > +#define STB225_NAND_BASE 0x18000000 /* I/O location(gets > > remapped)*/ +#define STB225_NAND_CLE_MASK 0x00100000 /* I/O location > > with CLE high */ +#define STB225_NAND_ALE_MASK 0x00010000 /* I/O > > location with ALE high */ + > > You might want to put this in an header file instead. Agreed will do this. > > > +void pnx833x_machine_halt(void) > > +{ > > + printk(KERN_ALERT "\n\nSystem halted.\n\n"); > > + > > + while (1) > > + __asm__ __volatile__ ("wait"); > > +} > > You might want to use cpu_relax(); instead of the assembly wait instruction. > Sounds good. > > + > > +void pnx833x_machine_power_off(void) > > +{ > > + printk(KERN_ALERT "\n\nPower off not implemented."); > > + pnx833x_machine_halt(); > > +} > > And put some less alarming message here, like "*** You can safely turn off the > board". > Agreed. > > +int __init plat_mem_setup(void) > > +{ > > + /* fake pci bus to avoid bounce buffers */ > > + PCI_DMA_BUS_IS_PHYS = 1; > > + > > + /* set mips clock to 320MHz */ > > +#if defined(CONFIG_SOC_PNX8335) > > + PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ); > > +#endif > > + gpio_init(); /* so it will be ready in board_setup() */ > > You can move the GPIO code into its own C file, and use arch_initcall to > initialise it. Prefixing gpio_init with pnx83xx is better to be consistent > with other functions. See below for more comments about the GPIO code. > I will prefix all gpio functions for safety. I will look into gpio library and submit a later patch for that. I would quite like to get this in and then optimise or I will take to long and miss the window again :-( > > +static inline unsigned long ip3902_read_reg(struct net_device *ndev, int > > reg) +{ > > + unsigned long value = readl((void * __iomem)(ndev->base_addr + > > reg)); + return value; > > Useless cast to void * __iomem in general, did your compiler produced a > warning on this ? > > Netdev people will probably ask you to use NAPI unconditionnaly for new > drivers. > Will do. > > +#ifdef IP3902_NAPI > > +static int ip3902_poll(struct napi_struct *napi, int budget) > > +{ > > + struct ip3902_private *ip3902_priv = container_of(napi, struct > > ip3902_private, napi); > > + struct net_device *ndev = ip3902_priv->ndev; > > + int work_done; > > + > > + work_done = ip3902_eth_receive_queue(ndev, ip3902_priv, budget); > > + > > + if (work_done < budget) { > > + ip3902_write_reg(ndev, INT_CLEAR_REG, RX_DONE_INT); > > + ip3902_write_reg(ndev, INT_CLEAR_REG, 0); > > + netif_rx_complete(ndev, napi); > > + ip3902_write_reg(ndev, INT_ENABLE_REG, (TX_UNDERRUN_INT | > > RX_DONE_INT | RX_OVERRUN_INT)); > > + } > > + > > + return work_done; > > +} > > +#endif > > > > > +/* BIG FAT WARNING: races danger! > > + No protections exist here. Current users are only early init code, > > + when locking is not needed because no cuncurency yet exists there, > > + and GPIO IRQ dispatcher, which does locking. > > + However, if many uses will ever happen, proper locking will be needed > > + - including locking between different uses > > You should consider using the GPIO library, or read what is done for BCM47xx, > AU1000 and TX4938. This should be easy since you comply with most of your > functions to this GPIO API. Providing your board specific gpio functions, the > rest of the API will handle locking and interrupt context for you. > > Also, prefix your functions so that they will not collide with the other > implementations naming scheme. > > Such functions might be provided by the C file instead, in the archicture > code. Remapping GPIO registers or things like that can be done there as well > at board boot time. > -- > Cordialement, Florian Fainelli > ------------------------------ > Many thanks for all comments, will do gpio library in a later patch. Will split i2c and ip3902 off into patches to the i2c and netdev mailing lists. Hopefully update the linux-mips patch today. Daniel From drzeus@drzeus.cx Fri Jun 6 11:11:51 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 11:11:53 +0100 (BST) Received: from server.drzeus.cx ([85.8.24.28]:38041 "EHLO smtp.drzeus.cx") by ftp.linux-mips.org with ESMTP id S20047621AbYFFKLv (ORCPT ); Fri, 6 Jun 2008 11:11:51 +0100 Received: from mjolnir.drzeus.cx (wlan249.drzeus.cx [::ffff:10.8.2.249]) (AUTH: LOGIN drzeus, TLS: TLS 1.0,256bits,RSA_AES_256_CBC_SHA1) by smtp.drzeus.cx with esmtp; Fri, 06 Jun 2008 12:06:30 +0200 id 0000000000120034.0000000048490C26.000001EF Date: Fri, 6 Jun 2008 12:11:19 +0200 From: Pierre Ossman To: Manuel Lauss Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, sshtylyov@ru.mvista.com Subject: Re: [PATCH 0/9] au1xmmc updates #3 Message-ID: <20080606121119.64ee6d18@mjolnir.drzeus.cx> In-Reply-To: <20080606071831.GC16498@roarinelk.homelinux.net> References: <20080519080339.GA21985@roarinelk.homelinux.net> <20080605230923.0268dd23@mjolnir.drzeus.cx> <20080606071831.GC16498@roarinelk.homelinux.net> X-Mailer: Claws Mail 3.4.0 (GTK+ 2.13.2; i386-redhat-linux-gnu) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwCAMAAABg3Am1AAAAAXNSR0IArs4c6QAAADNQTFRFEgwFRSofeTwxZEI1h1lFl1ZHeGBetHZk24VzuZJ43p2GsbKw/Lmg2MTL/NO3/+/Q//fpWFujUwAAAk5JREFUSMeNlVcWnDAMRd0bLux/tVGxiAEzic7hZ+Zd1IU6NtbYdn8daic/cgj52CPqLQ8hOBdjzsD8G2hHsCiPBS2/nTyABi93zvsYUyql1v6KSz30AeUAJLAK1uuDUI94WA7GDsAePtRDfwFRgP7DA8vvwOgQ1R5oYQUKAwOsfwDHDcAcWH+e5xagiooey1SwSAy0L8C7BaDKdgKWoNQtIjYEfHQGzMcKwNgCpLdgBn14ZzXNSPkJWK201vjiHMkXZg7AuQWCA7G2DPTiMSIsLSZxbgEIwlqEjE+9WBu0yaWOHwDLLQE9WmMieCBgtG1IAFgBzo7tlojGtbI3wFljuU4JdL3ghPeO+tFr2QHG0DOBSuN0kofaU302zmKbcTrgAWDUywG0OvXELi6gZScAdq6WnhYgvYDGu0YQjYSZs3ROID0B4y+jjpWyAhjePWkAjKwD5o09xioNBoro/+YQZjzTg8ce1CJtwFvwAMDFBEjv6cgI0P/u0DqtGJOjNSAm4e0jABxsgDYXSADQw2wwsFyzdePCAviE48QexseKNiGcp4jgKNEVAGC7QEwY5+S6Qpf50NzujHrdYgEKH0o8ZJ/AQR8HAGiaugDjG2i4ddZx4wToPwB0gQsEfjyFRKf1M+kLQC8u5iuoX8BhxYCQJPZXQ7LQdDnQR87/BdCpQQSJpREh7EMSQOvpYwJaqbAHgrUXkWehxhmUUjpsQ+IDSHlzEvidywrtDYSpnHVioNbstBLi9o3Dn/WqZ3Nw1pUQy8bN3/QdiPiVUZfpP4cDVEKd2cXEAAAAAElFTkSuQmCC X-Face: @{|$W51qEixc&6}dq_38NM^&.vv|'{O)ae?DMZ1%VYxuhN2}5VpQ!'gx[{V+8Xw'+cV5*491_)-SU2YT8s@4`H;@:ELS'/P(@.JxxJi/C8mG0H#A^R X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19424 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: drzeus@drzeus.cx Precedence: bulk X-list: linux-mips This is a MIME-formatted message. If you see this text it means that your E-mail software does not support MIME-formatted messages. --=_freyr.drzeus.cx-495-1212746790-0001-2 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Fri, 6 Jun 2008 09:18:31 +0200 Manuel Lauss wrote: > >=20 > > The role of maintainer is vacant if you want it. *nudge* ;) >=20 >=20 > I'll do it as long as I have hardware or you find someone better. >=20 Great. Please include a patch for the MAINTAINERS file in your next set then. Rgds Pierre --=_freyr.drzeus.cx-495-1212746790-0001-2 Content-Type: application/pgp-signature; name="signature.asc" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iEYEARECAAYFAkhJDUwACgkQ7b8eESbyJLhm0ACcCjGJ8INZM1goPpREsTU3SXyW KiAAnRSVanS24WeW35qeaw6M0d4/6nCe =yeHp -----END PGP SIGNATURE----- --=_freyr.drzeus.cx-495-1212746790-0001-2-- From sshtylyov@ru.mvista.com Fri Jun 6 12:45:57 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 12:45:59 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:30911 "HELO imap.sh.mvista.com") by ftp.linux-mips.org with SMTP id S28580514AbYFFLp5 (ORCPT ); Fri, 6 Jun 2008 12:45:57 +0100 Received: from [127.0.0.1] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id D7FBA3ECE; Fri, 6 Jun 2008 04:45:51 -0700 (PDT) Message-ID: <4849236B.8060100@ru.mvista.com> Date: Fri, 06 Jun 2008 15:45:47 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 1.5.0.14 (Windows/20071210) MIME-Version: 1.0 To: Manuel Lauss Cc: Pierre Ossman , ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/9] Alchemy: export get_au1x00_speed for modules References: <20080519080339.GA21985@roarinelk.homelinux.net> <20080519080416.GB21985@roarinelk.homelinux.net> <483149E0.6010009@ru.mvista.com> <20080519094953.GA22445@roarinelk.homelinux.net> <20080605230311.7f98cd1a@mjolnir.drzeus.cx> <20080606071646.GA16498@roarinelk.homelinux.net> In-Reply-To: <20080606071646.GA16498@roarinelk.homelinux.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19425 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Manuel Lauss wrote: >>>>> From 8492076e98c7fd47c9dee53984dbd9568ace357d Mon Sep 17 00:00:00 2001 >>>>> From: Manuel Lauss >>>>> Date: Wed, 7 May 2008 13:42:55 +0200 >>>>> Subject: [PATCH] Alchemy: export get_au1x00_speed for modules >>>>> >>>>> au1xmmc.c driver depends on it, so export it for modules. >>>>> >>>>> Signed-off-by: Manuel Lauss >>>>> >>>>> >>>> I thought that has been merged. >>>> >>> Yes, Ralf merged it into linux-mips repo, but it is not yet in >>> mainline and the rest of the patches are against linus' git. >>> >>> >> So who should push this to Linus? If this set is the only patches >> depending on it, it would be easiest if I carry it in my tree. >> > > I'd prefer if you (Pierre) carried them all since they all depend on > each other (kind of, anyway). And it seems Ralf has gone silent anyway :) > Ralf has pushed this patch to Linus, and it has gone into the Linus' tree today. > Thank you! > Manuel Lauss > WBR, Sergei From daniel.j.laird@googlemail.com Fri Jun 6 12:59:09 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 12:59:13 +0100 (BST) Received: from hs-out-0708.google.com ([64.233.178.243]:43938 "EHLO hs-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S28581655AbYFFL7J (ORCPT ); Fri, 6 Jun 2008 12:59:09 +0100 Received: by hs-out-0708.google.com with SMTP id x43so744268hsb.0 for ; Fri, 06 Jun 2008 04:59:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:sender :to:subject:mime-version:content-type:content-transfer-encoding :content-disposition:x-google-sender-auth; bh=fy8zOVZDgoi7obeWPavATvqReyUSR4NXQ3r9YdBt1JE=; b=AToMDBR1i+hQ/j2EoOoW1vDl+Xa2kluvuy1GbK+rA6FEipRViCqif5W4EDZSwlcG0x KsNw3qids44lFMYrTeyewCwMLkYcaFRP2cs/i/lasYTbd32DWWqKUL9Jsdxwn/2RqDK2 H9Mwtcj2ZV3mw3BgzOB4a2EsuB9aWicvHaaMs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=message-id:date:from:sender:to:subject:mime-version:content-type :content-transfer-encoding:content-disposition:x-google-sender-auth; b=p+p0987IJNYlupiQx2LkxkwyM3XUIBnsz66BlySvu0hM11zBFPXDWwhj1RXgTO44Lp Q5CJg1pIf98kFGwaN4XcmlfdPkJfvR/5qY3cqe1llo5Aky4+fOMqtG3u+VHrdJxnJ81S BYY7Tb3h9+eGTPl8/7B566Vq3ygTFEMPToXz8= Received: by 10.90.113.17 with SMTP id l17mr3226388agc.68.1212753546198; Fri, 06 Jun 2008 04:59:06 -0700 (PDT) Received: by 10.90.70.11 with HTTP; Fri, 6 Jun 2008 04:59:06 -0700 (PDT) Message-ID: <64660ef00806060459n5473afeer91b8441b4fc27ad3@mail.gmail.com> Date: Fri, 6 Jun 2008 12:59:06 +0100 From: "Daniel Laird" To: linux-mips@linux-mips.org Subject: =?WINDOWS-1256?Q?[PATCH]_:_Add_support_for_NXP_PNX833x_?= =?WINDOWS-1256?Q?(STB222/5)_into_linux_kernel=FE_(UPDATED)?= MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline X-Google-Sender-Auth: 324dabce9b6aadcd Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19426 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: daniel.j.laird@nxp.com Precedence: bulk X-list: linux-mips Use of GPIO library will be posted as new patch once I get this is. Have corrected suggestions posted. Many thanks ---------------------------------- The following patch add support for the NXP PNX833x SOC. More specifically it adds support for the STB222/5 variant. arch/mips/Kconfig | 33 arch/mips/Makefile | 8 arch/mips/configs/pnx8335-stb225_defconfig | 1150 +++++++++++++++++++++++++++++ arch/mips/nxp/pnx833x/common/Makefile | 1 arch/mips/nxp/pnx833x/common/gdb_hook.c | 134 +++ arch/mips/nxp/pnx833x/common/interrupts.c | 364 +++++++++ arch/mips/nxp/pnx833x/common/platform.c | 309 +++++++ arch/mips/nxp/pnx833x/common/prom.c | 70 + arch/mips/nxp/pnx833x/common/reset.c | 50 + arch/mips/nxp/pnx833x/common/setup.c | 64 + arch/mips/nxp/pnx833x/stb22x/Makefile | 1 arch/mips/nxp/pnx833x/stb22x/board.c | 133 +++ include/asm-mips/mach-pnx833x/gpio.h | 172 ++++ include/asm-mips/mach-pnx833x/irq.h | 139 +++ include/asm-mips/mach-pnx833x/pnx833x.h | 202 +++++ include/asm-mips/mach-pnx833x/war.h | 25 16 files changed, 2855 insertions(+) Signed-off-by: daniel.j.laird diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/configs/pnx8335-stb225_defconfig linux-2.6.26-rc4/arch/mips/configs/pnx8335-stb225_defconfig --- linux-2.6.26-rc4.orig/arch/mips/configs/pnx8335-stb225_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/configs/pnx8335-stb225_defconfig 2008-06-04 15:58:03.000000000 +0100 @@ -0,0 +1,1150 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc4 +# Wed Jun 4 15:57:17 2008 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +CONFIG_NXP_STB225=y +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_WR_PPMC is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SOC_PNX833X=y +CONFIG_SOC_PNX8335=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_128=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=128 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +CONFIG_INET_AH=y +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x18000000 +CONFIG_MTD_PHYSMAP_LEN=0x04000000 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +CONFIG_ATA_SFF=y +# CONFIG_SATA_MV is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_IP3902 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_ALGOPCA=y + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_PCA_PLATFORM is not set +CONFIG_I2C_PNX0105=y + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +CONFIG_DVB_CORE=y +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_L64781 is not set +CONFIG_DVB_TDA1004X=y +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_TDA10048 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522 is not set +# CONFIG_DVB_S5H1411 is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_LOGO is not set + +# +# Sound +# +CONFIG_SOUND=m + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_DETECT=y +# CONFIG_SND_PCM_XRUN_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# ALSA MIPS devices +# + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# ALSA SoC audio for Freescale SOCs +# + +# +# SoC Audio for the Texas Instruments OMAP +# + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_CODEPAGE_932=m +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=m +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SAMPLES is not set +CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/Kconfig linux-2.6.26-rc4/arch/mips/Kconfig --- linux-2.6.26-rc4.orig/arch/mips/Kconfig 2008-06-03 10:56:51.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/Kconfig 2008-06-03 17:12:19.000000000 +0100 @@ -311,6 +311,19 @@ select SYS_HAS_CPU_VR41XX select GENERIC_HARDIRQS_NO__DO_IRQ +config NXP_STB220 + bool "NXP STB220 board" + select SOC_PNX833X + help + Support for NXP Semiconductors STB220 Development Board. + +config NXP_STB225 + bool "NXP 225 board" + select SOC_PNX833X + select SOC_PNX8335 + help + Support for NXP Semiconductors STB225 Development Board. + config PNX8550_JBS bool "NXP PNX8550 based JBS board" select PNX8550 @@ -947,6 +960,26 @@ bool select SERIAL_RM9000 +config SOC_PNX833X + bool + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select DMA_NONCOHERENT + select SYS_HAS_EARLY_PRINTK + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ + select SYS_SUPPORTS_KGDB + select GENERIC_GPIO + select CPU_MIPSR2_IRQ_VI + +config SOC_PNX8335 + bool + select SOC_PNX833X + config PNX8550 bool select SOC_PNX8550 diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/Makefile linux-2.6.26-rc4/arch/mips/Makefile --- linux-2.6.26-rc4.orig/arch/mips/Makefile 2008-06-03 10:56:51.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/Makefile 2008-06-03 17:13:03.000000000 +0100 @@ -409,6 +409,14 @@ # load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 +# NXP STB225 +core-$(CONFIG_SOC_PNX833X) += arch/mips/nxp/pnx833x/common/ +cflags-$(CONFIG_SOC_PNX833X) += -Iinclude/asm-mips/mach-pnx833x +libs-$(CONFIG_NXP_STB220) += arch/mips/nxp/pnx833x/stb22x/ +load-$(CONFIG_NXP_STB220) += 0xffffffff80001000 +libs-$(CONFIG_NXP_STB225) += arch/mips/nxp/pnx833x/stb22x/ +load-$(CONFIG_NXP_STB225) += 0xffffffff80001000 + # # Common NXP PNX8550 # diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/gdb_hook.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/gdb_hook.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/gdb_hook.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/gdb_hook.c 2008-06-06 11:29:01.000000000 +0100 @@ -0,0 +1,134 @@ +/* + * gdb_hook.c: gdb hook for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on PNX8550. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include + +#define UART0 (unsigned char *)PNX833X_UART0_PORTS_START +#define UART1 (unsigned char *)PNX833X_UART1_PORTS_START + +static unsigned char *kgdb_uart = UART1; +static unsigned char *console_uart = UART0; +static volatile int delay_count; + +static unsigned int serial_in(unsigned char *base_address, int offset) +{ + return *((unsigned int volatile *)(base_address + offset)); +} + +static void serial_out(unsigned char *base_address, int offset, int value) +{ + *((unsigned int volatile *)(base_address + offset)) = value; +} + +static void do_delay(void) +{ + int i; + for (i = 0; i < 10000; i++) + delay_count++; +} + +static int put_char(unsigned char *base_address, char c) +{ + /* Wait for TX to be ready */ + while (((serial_in(base_address, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO) >> 16) > 15) + do_delay(); + + /* Send the next character */ + serial_out(base_address, PNX8XXX_FIFO, c); + serial_out(base_address, PNX8XXX_ICLR, PNX8XXX_UART_INT_TX); + + return 1; +} + +static char get_char(unsigned char *base_address) +{ + char output; + + /* Wait for RX to be ready */ + while ((serial_in(base_address, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_RXFIFO) == 0) + do_delay(); + + /* Get the character */ + output = serial_in(base_address, PNX8XXX_FIFO) & 0xFF; + + /* Move onto the next character in the buffer */ + serial_out(base_address, PNX8XXX_LCR, serial_in(base_address, PNX8XXX_LCR) | PNX8XXX_UART_LCR_RX_NEXT); + serial_out(base_address, PNX8XXX_ICLR, PNX8XXX_UART_INT_RX); + + return output; +} + +static void serial_init(unsigned char *base_address) +{ + serial_out(base_address, PNX8XXX_LCR, PNX8XXX_UART_LCR_8BIT | PNX8XXX_UART_LCR_TX_RST | PNX8XXX_UART_LCR_RX_RST); + serial_out(base_address, PNX8XXX_MCR, PNX8XXX_UART_MCR_DTR | PNX8XXX_UART_MCR_RTS); + serial_out(base_address, PNX8XXX_BAUD, 1); /* 115200 Baud */ + serial_out(base_address, PNX8XXX_CFG, 0x00060030); + serial_out(base_address, PNX8XXX_ICLR, -1); + serial_out(base_address, PNX8XXX_IEN, 0); +} + +static void setup_serial_output(void) +{ + static bool initialised; + if (!initialised) { + serial_init(kgdb_uart); + serial_init(console_uart); + initialised = true; + } +} + +int rs_kgdb_hook(int tty_no, int speed) +{ + kgdb_uart = tty_no ? UART1 : UART0; + console_uart = tty_no ? UART0 : UART1; + + setup_serial_output(); + + return speed; +} + +int prom_putchar(char c) +{ + setup_serial_output(); + return put_char(console_uart, c); +} + +char prom_getchar(void) +{ + setup_serial_output(); + return get_char(console_uart); +} + +int put_debug_char(char c) +{ + setup_serial_output(); + return put_char(kgdb_uart, c); +} + +char get_debug_char(void) +{ + setup_serial_output(); + return get_char(kgdb_uart); +} diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/interrupts.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/interrupts.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/interrupts.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/interrupts.c 2008-06-06 11:29:17.000000000 +0100 @@ -0,0 +1,364 @@ +/* + * interrupts.c: Interrupt mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] = +{ + 0, /* unused */ + 4, /* PNX833X_PIC_I2C0_INT 1 */ + 4, /* PNX833X_PIC_I2C1_INT 2 */ + 1, /* PNX833X_PIC_UART0_INT 3 */ + 1, /* PNX833X_PIC_UART1_INT 4 */ + 6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */ + 6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */ + 7, /* PNX833X_PIC_GPIO_INT 7 */ + 4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */ + 5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */ + 4, /* PNX833X_PIC_CONFIG_INT 10 */ + 4, /* PNX833X_PIC_AOI_INT 11 */ + 9, /* PNX833X_PIC_SYNC_INT 12 */ + 9, /* PNX8335_PIC_SATA_INT 13 */ + 4, /* PNX833X_PIC_OSD_INT 14 */ + 9, /* PNX833X_PIC_DISP1_INT 15 */ + 4, /* PNX833X_PIC_DEINTERLACER_INT 16 */ + 9, /* PNX833X_PIC_DISPLAY2_INT 17 */ + 4, /* PNX833X_PIC_VC_INT 18 */ + 4, /* PNX833X_PIC_SC_INT 19 */ + 9, /* PNX833X_PIC_IDE_INT 20 */ + 9, /* PNX833X_PIC_IDE_DMA_INT 21 */ + 6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */ + 6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */ + 4, /* PNX833X_PIC_SGDX_DMA_INT 24 */ + 4, /* PNX833X_PIC_TS_OUT_INT 25 */ + 4, /* PNX833X_PIC_IR_INT 26 */ + 3, /* PNX833X_PIC_VMSP1_INT 27 */ + 3, /* PNX833X_PIC_VMSP2_INT 28 */ + 4, /* PNX833X_PIC_PIBC_INT 29 */ + 4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */ + 4, /* PNX833X_PIC_SGDX_TPD_INT 31 */ + 5, /* PNX833X_PIC_USB_INT 32 */ + 4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */ + 4, /* PNX833X_PIC_CLOCK_INT 34 */ + 4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */ + 4, /* PNX833X_PIC_VMSP_DMA_INT 36 */ +#if defined(CONFIG_SOC_PNX8335) + 4, /* PNX8335_PIC_MIU_INT 37 */ + 4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */ + 9, /* PNX8335_PIC_SYNC_HD_INT 39 */ + 9, /* PNX8335_PIC_DISP_HD_INT 40 */ + 9, /* PNX8335_PIC_DISP_SCALER_INT 41 */ + 4, /* PNX8335_PIC_OSD_HD1_INT 42 */ + 4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */ + 4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */ + 4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */ + 4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */ + 4, /* PNX8335_PIC_DENC_TTX_INT 47 */ + 4, /* PNX8335_PIC_MMI_SIF0_INT 48 */ + 4, /* PNX8335_PIC_MMI_SIF1_INT 49 */ + 4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */ + 4, /* PNX8335_PIC_PIBCS_INT 51 */ + 12, /* PNX8335_PIC_ETHERNET_INT 52 */ + 3, /* PNX8335_PIC_VMSP1_0_INT 53 */ + 3, /* PNX8335_PIC_VMSP1_1_INT 54 */ + 4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */ + 4, /* PNX8335_PIC_TDGR_DE_INT 56 */ + 4, /* PNX8335_PIC_IR1_IRQ_INT 57 */ +#endif +}; + +static void pic_dispatch(void) +{ + unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC); + + if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) { + unsigned long priority = PNX833X_PIC_INT_PRIORITY; + PNX833X_PIC_INT_PRIORITY = irq_prio[irq]; + + if (irq == PNX833X_PIC_GPIO_INT) { + unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE; + int pin; + while ((pin = ffs(mask & 0xffff))) { + pin -= 1; + do_IRQ(PNX833X_GPIO_IRQ_BASE + pin); + mask &= ~(1 << pin); + } + } else { + do_IRQ(irq + PNX833X_PIC_IRQ_BASE); + } + + PNX833X_PIC_INT_PRIORITY = priority; + } else { + printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq); + } +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & STATUSF_IP4) + pic_dispatch(); + else if (pending & STATUSF_IP7) + do_IRQ(PNX833X_TIMER_IRQ); + else + spurious_interrupt(); +} + +static inline void pnx833x_hard_enable_pic_irq(unsigned int irq) +{ + /* Currently we do this by setting IRQ priority to 1. + If priority support is being implemented, 1 should be repalced + by a better value. */ + PNX833X_PIC_INT_REG(irq) = irq_prio[irq]; +} + +static inline void pnx833x_hard_disable_pic_irq(unsigned int irq) +{ + /* Disable IRQ by writing setting it's priority to 0 */ + PNX833X_PIC_INT_REG(irq) = 0; +} + +static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */ +#define IRQFLAG_STARTED 1 +#define IRQFLAG_DISABLED 2 + +static DEFINE_SPINLOCK(pnx833x_irq_lock); + +static unsigned int pnx833x_startup_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */ + pnx833x_hard_enable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); + return 0; +} + +static void pnx833x_shutdown_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] = 0; /* not started */ + pnx833x_hard_disable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); +} + +static void pnx833x_enable_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] &= ~IRQFLAG_DISABLED; + if (irqflags[pic_irq] == IRQFLAG_STARTED) + pnx833x_hard_enable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); +} + +static void pnx833x_disable_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] |= IRQFLAG_DISABLED; + pnx833x_hard_disable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); +} + +static void pnx833x_ack_pic_irq(unsigned int irq) +{ +} + +static void pnx833x_end_pic_irq(unsigned int irq) +{ +} + +static DEFINE_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock); + +static unsigned int pnx833x_startup_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); + pnx833x_gpio_enable_irq(pin); + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); + return 0; +} + +static void pnx833x_enable_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); + pnx833x_gpio_enable_irq(pin); + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); +} + +static void pnx833x_disable_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); + pnx833x_gpio_disable_irq(pin); + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); +} + +static void pnx833x_ack_gpio_irq(unsigned int irq) +{ +} + +static void pnx833x_end_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); + pnx833x_gpio_clear_irq(pin); + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); +} + +static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + int gpio_mode; + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + gpio_mode = GPIO_INT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + gpio_mode = GPIO_INT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + gpio_mode = GPIO_INT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + gpio_mode = GPIO_INT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + gpio_mode = GPIO_INT_LEVEL_LOW; + break; + default: + gpio_mode = GPIO_INT_NONE; + break; + } + + pnx833x_gpio_setup_irq(gpio_mode, pin); + + return 0; +} + +static struct irq_chip pnx833x_pic_irq_type = { + .typename = "PNX-PIC", + .startup = pnx833x_startup_pic_irq, + .shutdown = pnx833x_shutdown_pic_irq, + .enable = pnx833x_enable_pic_irq, + .disable = pnx833x_disable_pic_irq, + .ack = pnx833x_ack_pic_irq, + .end = pnx833x_end_pic_irq +}; + +static struct irq_chip pnx833x_gpio_irq_type = { + .typename = "PNX-GPIO", + .startup = pnx833x_startup_gpio_irq, + .shutdown = pnx833x_disable_gpio_irq, + .enable = pnx833x_enable_gpio_irq, + .disable = pnx833x_disable_gpio_irq, + .ack = pnx833x_ack_gpio_irq, + .end = pnx833x_end_gpio_irq, + .set_type = pnx833x_set_type_gpio_irq +}; + +void __init arch_init_irq(void) +{ + unsigned int irq; + + /* setup standard internal cpu irqs */ + mips_cpu_irq_init(); + + /* Set IRQ information in irq_desc */ + for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) { + pnx833x_hard_disable_pic_irq(irq); + set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq); + } + + for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++) + set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq); + + /* Set PIC priority limiter register to 0 */ + PNX833X_PIC_INT_PRIORITY = 0; + + /* Setup GPIO IRQ dispatching */ + pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT); + + /* Enable PIC IRQs (HWIRQ2) */ + if (cpu_has_vint) + set_vi_handler(4, pic_dispatch); + + write_c0_status(read_c0_status() | IE_IRQ2); +} + + +void __init plat_time_init(void) +{ + /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */ + + extern unsigned long mips_hpt_frequency; + unsigned long reg = PNX833X_CLOCK_CPUCP_CTL; + + if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) { + /* Functional clock is disabled so use crystal frequency */ + mips_hpt_frequency = 25; + } else { +#if defined(CONFIG_SOC_PNX8335) + /* Functional clock is enabled, so get clock multiplier */ + mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ)); +#else + static const unsigned long int freq[4] = {240, 160, 120, 80}; + mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)]; +#endif + } + + printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency); + + mips_hpt_frequency *= 500000; +} + diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/Makefile linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/Makefile --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/Makefile 2008-03-03 13:09:30.000000000 +0000 @@ -0,0 +1 @@ +obj-y := interrupts.o platform.o prom.o setup.o reset.o gdb_hook.o diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/platform.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/platform.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/platform.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/platform.c 2008-06-06 11:29:35.000000000 +0100 @@ -0,0 +1,309 @@ +/* + * platform.c: platform support for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static u64 uart_dmamask = ~(u32)0; + +static struct resource pnx833x_uart_resources[] = { + [0] = { + .start = PNX833X_UART0_PORTS_START, + .end = PNX833X_UART0_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX833X_PIC_UART0_INT, + .end = PNX833X_PIC_UART0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = PNX833X_UART1_PORTS_START, + .end = PNX833X_UART1_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = PNX833X_PIC_UART1_INT, + .end = PNX833X_PIC_UART1_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct pnx8xxx_port pnx8xxx_ports[] = { + [0] = { + .port = { + .type = PORT_PNX8XXX, + .iotype = UPIO_MEM, + .membase = (void __iomem *)PNX833X_UART0_PORTS_START, + .mapbase = PNX833X_UART0_PORTS_START, + .irq = PNX833X_PIC_UART0_INT, + .uartclk = 3692300, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .line = 0, + }, + }, + [1] = { + .port = { + .type = PORT_PNX8XXX, + .iotype = UPIO_MEM, + .membase = (void __iomem *)PNX833X_UART1_PORTS_START, + .mapbase = PNX833X_UART1_PORTS_START, + .irq = PNX833X_PIC_UART1_INT, + .uartclk = 3692300, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .line = 1, + }, + }, +}; + +static struct platform_device pnx833x_uart_device = { + .name = "pnx8xxx-uart", + .id = -1, + .dev = { + .dma_mask = &uart_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = pnx8xxx_ports, + }, + .num_resources = ARRAY_SIZE(pnx833x_uart_resources), + .resource = pnx833x_uart_resources, +}; + +static u64 ehci_dmamask = ~(u32)0; + +static struct resource pnx833x_usb_ehci_resources[] = { + [0] = { + .start = PNX833X_USB_PORTS_START, + .end = PNX833X_USB_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX833X_PIC_USB_INT, + .end = PNX833X_PIC_USB_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pnx833x_usb_ehci_device = { + .name = "pnx833x-ehci", + .id = -1, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources), + .resource = pnx833x_usb_ehci_resources, +}; + +static struct resource pnx833x_i2c0_resources[] = { + { + .start = PNX833X_I2C0_PORTS_START, + .end = PNX833X_I2C0_PORTS_END, + .flags = IORESOURCE_MEM, + }, + { + .start = PNX833X_PIC_I2C0_INT, + .end = PNX833X_PIC_I2C0_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource pnx833x_i2c1_resources[] = { + { + .start = PNX833X_I2C1_PORTS_START, + .end = PNX833X_I2C1_PORTS_END, + .flags = IORESOURCE_MEM, + }, + { + .start = PNX833X_PIC_I2C1_INT, + .end = PNX833X_PIC_I2C1_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = { + { + .base = PNX833X_I2C0_PORTS_START, + .irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */ + .clock = 6, /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Prefered HDCP) */ + .bus_addr = 0, /* no slave support */ + }, + { + .base = PNX833X_I2C1_PORTS_START, + .irq = -1, /* on high freq, polling is faster */ + /*.irq = PNX833X_PIC_I2C1_INT,*/ + .clock = 4, /* 0 == 400 kHz, 4 == 100 kHz. 100 kHz seems a safe default for now */ + .bus_addr = 0, /* no slave support */ + }, +}; + +static struct platform_device pnx833x_i2c0_device = { + .name = "i2c-pnx0105", + .id = 0, + .dev = { + .platform_data = &pnx833x_i2c_dev[0], + }, + .num_resources = ARRAY_SIZE(pnx833x_i2c0_resources), + .resource = pnx833x_i2c0_resources, +}; + +static struct platform_device pnx833x_i2c1_device = { + .name = "i2c-pnx0105", + .id = 1, + .dev = { + .platform_data = &pnx833x_i2c_dev[1], + }, + .num_resources = ARRAY_SIZE(pnx833x_i2c1_resources), + .resource = pnx833x_i2c1_resources, +}; + +static u64 ethernet_dmamask = ~(u32)0; + +static struct resource pnx833x_ethernet_resources[] = { + [0] = { + .start = PNX8335_IP3902_PORTS_START, + .end = PNX8335_IP3902_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8335_PIC_ETHERNET_INT, + .end = PNX8335_PIC_ETHERNET_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pnx833x_ethernet_device = { + .name = "ip3902-eth", + .id = -1, + .dev = { + .dma_mask = ðernet_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources), + .resource = pnx833x_ethernet_resources, +}; + +static struct resource pnx833x_sata_resources[] = { + [0] = { + .start = PNX8335_SATA_PORTS_START, + .end = PNX8335_SATA_PORTS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8335_PIC_SATA_INT, + .end = PNX8335_PIC_SATA_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pnx833x_sata_device = { + .name = "pnx833x-sata", + .id = -1, + .num_resources = ARRAY_SIZE(pnx833x_sata_resources), + .resource = pnx833x_sata_resources, +}; + +#ifdef CONFIG_MTD_PARTITIONS +static const char *part_probes[] = { "cmdlinepart", 0 }; +#endif + +static void +pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long)this->IO_ADDR_W; + + if (cmd == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) + writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_CLE_MASK)); + else + writeb(cmd, (void __iomem *) (nandaddr + PNX8335_NAND_ALE_MASK)); +} + +static struct platform_nand_data pnx833x_flash_nand_data = { + .chip = { + .chip_delay = 25, +#ifdef CONFIG_MTD_PARTITIONS + .part_probe_types = part_probes, +#endif + }, + .ctrl = { + .cmd_ctrl = pnx833x_flash_nand_cmd_ctrl + } +}; + +/* Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!), + 12 bytes more seems to be the standard that allows for NAND access.*/ +static struct resource pnx833x_flash_nand_resource = { + .start = PNX8335_NAND_BASE, + .end = PNX8335_NAND_BASE + 12, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device pnx833x_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = 1, + .resource = &pnx833x_flash_nand_resource, + .dev = { + .platform_data = &pnx833x_flash_nand_data, + }, +}; + +static struct platform_device *pnx833x_platform_devices[] __initdata = { + &pnx833x_uart_device, + &pnx833x_usb_ehci_device, + &pnx833x_i2c0_device, + &pnx833x_i2c1_device, + &pnx833x_ethernet_device, + &pnx833x_sata_device, + &pnx833x_flash_nand, +}; + +int __init pnx833x_platform_init(void) +{ + int res; + + if (ARRAY_SIZE(pnx833x_platform_devices)) { + res = platform_add_devices(pnx833x_platform_devices, + ARRAY_SIZE(pnx833x_platform_devices)); + } + return res; +} + +arch_initcall(pnx833x_platform_init); diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/prom.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/prom.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/prom.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/prom.c 2008-06-06 11:29:55.000000000 +0100 @@ -0,0 +1,70 @@ +/* + * prom.c: + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +void __init prom_init_cmdline(void) +{ + int argc = fw_arg0; + char **argv = (char **)fw_arg1; + char *c = &(arcs_cmdline[0]); + int i; + + for (i = 1; i < argc; i++) { + strcpy(c, argv[i]); + c += strlen(argv[i]); + if (i < argc-1) + *c++ = ' '; + } + *c = 0; +} + +char __init *prom_getenv(char *envname) +{ + extern char **prom_envp; + char **env = prom_envp; + int i; + + i = strlen(envname); + + while (*env) { + if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=') + return *env + i + 1; + env++; + } + + return 0; +} + +void __init prom_free_prom_memory(void) +{ +} + +char * __init prom_getcmdline(void) +{ + return arcs_cmdline; +} + diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/reset.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/reset.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/reset.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/reset.c 2008-06-06 11:30:01.000000000 +0100 @@ -0,0 +1,50 @@ +/* + * reset.c: reset support for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +void pnx833x_machine_restart(char *command) +{ + printk(KERN_ALERT "\n\n*** Restarting ***\n\n"); + + PNX833X_RESET_CONTROL_2 = 0; + PNX833X_RESET_CONTROL = 0; +} + +void pnx833x_machine_halt(void) +{ + printk(KERN_ALERT "\n\n*** System halted. ***\n\n"); + + while (1) + __asm__ __volatile__ ("wait"); + +} + +void pnx833x_machine_power_off(void) +{ + printk(KERN_ALERT "\n\n*** You can safely turn off the board. ***"); + pnx833x_machine_halt(); +} diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/setup.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/setup.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/setup.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/setup.c 2008-06-06 11:30:16.000000000 +0100 @@ -0,0 +1,64 @@ +/* + * setup.c: Setup PNX833X Soc. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +extern void pnx833x_board_setup(void); +extern void pnx833x_machine_restart(char *); +extern void pnx833x_machine_halt(void); +extern void pnx833x_machine_power_off(void); + +int __init plat_mem_setup(void) +{ + /* fake pci bus to avoid bounce buffers */ + PCI_DMA_BUS_IS_PHYS = 1; + + /* set mips clock to 320MHz */ +#if defined(CONFIG_SOC_PNX8335) + PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ); +#endif + pnx833x_gpio_init(); /* so it will be ready in board_setup() */ + + pnx833x_board_setup(); + + _machine_restart = pnx833x_machine_restart; + _machine_halt = pnx833x_machine_halt; + pm_power_off = pnx833x_machine_power_off; + + /* IO/MEM resources. */ + set_io_port_base(KSEG1); + ioport_resource.start = 0; + ioport_resource.end = ~0; + iomem_resource.start = 0; + iomem_resource.end = ~0; + + return 0; +} diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/board.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/board.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/board.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/board.c 2008-06-06 11:28:50.000000000 +0100 @@ -0,0 +1,133 @@ +/* + * board.c: STB225 board support. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on software written by: + * Nikita Youshchenko , based on PNX8550 code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include + +/* endianess twiddlers */ +#define PNX8335_DEBUG0 0x4400 +#define PNX8335_DEBUG1 0x4404 +#define PNX8335_DEBUG2 0x4408 +#define PNX8335_DEBUG3 0x440c +#define PNX8335_DEBUG4 0x4410 +#define PNX8335_DEBUG5 0x4414 +#define PNX8335_DEBUG6 0x4418 +#define PNX8335_DEBUG7 0x441c + +int prom_argc; +char **prom_argv = 0, **prom_envp = 0; + +extern void prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "NXP STB22x"; +} + +static inline unsigned long env_or_default(char *env, unsigned long dfl) +{ + char *str = prom_getenv(env); + return str ? simple_strtol(str, 0, 0) : dfl; +} + +void __init prom_init(void) +{ + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize = env_or_default("memsize", 0x02000000); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} + +void __init pnx833x_board_setup(void) +{ + pnx833x_gpio_select_function_alt(4); + pnx833x_gpio_select_output(4); + pnx833x_gpio_select_function_alt(5); + pnx833x_gpio_select_input(5); + pnx833x_gpio_select_function_alt(6); + pnx833x_gpio_select_input(6); + pnx833x_gpio_select_function_alt(7); + pnx833x_gpio_select_output(7); + + pnx833x_gpio_select_function_alt(25); + pnx833x_gpio_select_function_alt(26); + + pnx833x_gpio_select_function_alt(27); + pnx833x_gpio_select_function_alt(28); + pnx833x_gpio_select_function_alt(29); + pnx833x_gpio_select_function_alt(30); + pnx833x_gpio_select_function_alt(31); + pnx833x_gpio_select_function_alt(32); + pnx833x_gpio_select_function_alt(33); + +#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) + /* Setup MIU for NAND access on CS0... + * + * (it seems that we must also configure CS1 for reliable operation, + * otherwise the first read ID command will fail if it's read as 4 bytes + * but pass if it's read as 1 word.) + */ + + /* Setup MIU CS0 & CS1 timing */ + PNX833X_MIU_SEL0 = 0; + PNX833X_MIU_SEL1 = 0; + PNX833X_MIU_SEL0_TIMING = 0x50003081; + PNX833X_MIU_SEL1_TIMING = 0x50003081; + + /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */ + pnx833x_gpio_select_function_alt(0); + + /* Setup GPIO 04 to input NAND read/busy signal */ + pnx833x_gpio_select_function_io(4); + pnx833x_gpio_select_input(4); + + /* Setup GPIO 05 to disable NAND write protect */ + pnx833x_gpio_select_function_io(5); + pnx833x_gpio_select_output(5); + pnx833x_gpio_write(1, 5); + +#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE) + + /* Set up MIU for 16-bit NOR access on CS0 and CS1... */ + + /* Setup MIU CS0 & CS1 timing */ + PNX833X_MIU_SEL0 = 1; + PNX833X_MIU_SEL1 = 1; + PNX833X_MIU_SEL0_TIMING = 0x6A08D082; + PNX833X_MIU_SEL1_TIMING = 0x6A08D082; + + /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */ + pnx833x_gpio_select_function_alt(0); +#endif +} diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/Makefile linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/Makefile --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/Makefile 2008-03-03 13:09:30.000000000 +0000 @@ -0,0 +1 @@ +lib-y := board.o diff -urN --exclude=.svn linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/gpio.h linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/gpio.h --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/gpio.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/gpio.h 2008-06-06 11:29:09.000000000 +0100 @@ -0,0 +1,172 @@ +/* + * gpio.h: GPIO Support for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H +#define __ASM_MIPS_MACH_PNX833X_GPIO_H + +/* BIG FAT WARNING: races danger! + No protections exist here. Current users are only early init code, + when locking is not needed because no cuncurency yet exists there, + and GPIO IRQ dispatcher, which does locking. + However, if many uses will ever happen, proper locking will be needed + - including locking between different uses +*/ + +#include "pnx833x.h" + +#define SET_REG_BIT(reg, bit) reg |= (1 << (bit)) +#define CLEAR_REG_BIT(reg, bit) reg &= ~(1 << (bit)) + +/* Initialize GPIO to a known state */ +static inline void pnx833x_gpio_init(void) +{ + PNX833X_PIO_DIR = 0; + PNX833X_PIO_DIR2 = 0; + PNX833X_PIO_SEL = 0; + PNX833X_PIO_SEL2 = 0; + PNX833X_PIO_INT_EDGE = 0; + PNX833X_PIO_INT_HI = 0; + PNX833X_PIO_INT_LO = 0; + + /* clear any GPIO interrupt requests */ + PNX833X_PIO_INT_CLEAR = 0xffff; + PNX833X_PIO_INT_CLEAR = 0; + PNX833X_PIO_INT_ENABLE = 0; +} + +/* Select GPIO direction for a pin */ +static inline void pnx833x_gpio_select_input(unsigned int pin) +{ + if (pin < 32) + CLEAR_REG_BIT(PNX833X_PIO_DIR, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31); +} +static inline void pnx833x_gpio_select_output(unsigned int pin) +{ + if (pin < 32) + SET_REG_BIT(PNX833X_PIO_DIR, pin); + else + SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31); +} + +/* Select GPIO or alternate function for a pin */ +static inline void pnx833x_gpio_select_function_io(unsigned int pin) +{ + if (pin < 32) + CLEAR_REG_BIT(PNX833X_PIO_SEL, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31); +} +static inline void pnx833x_gpio_select_function_alt(unsigned int pin) +{ + if (pin < 32) + SET_REG_BIT(PNX833X_PIO_SEL, pin); + else + SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31); +} + +/* Read GPIO pin */ +static inline int pnx833x_gpio_read(unsigned int pin) +{ + if (pin < 32) + return(PNX833X_PIO_IN >> pin) & 1; + else + return(PNX833X_PIO_IN2 >> (pin & 31)) & 1; +} + +/* Write GPIO pin */ +static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin) +{ + if (pin < 32) { + if (val) + SET_REG_BIT(PNX833X_PIO_OUT, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_OUT, pin); + } else { + if (val) + SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31); + else + CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31); + } +} + +/* Configure GPIO interrupt */ +#define GPIO_INT_NONE 0 +#define GPIO_INT_LEVEL_LOW 1 +#define GPIO_INT_LEVEL_HIGH 2 +#define GPIO_INT_EDGE_RISING 3 +#define GPIO_INT_EDGE_FALLING 4 +#define GPIO_INT_EDGE_BOTH 5 +static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin) +{ + switch (when) { + case GPIO_INT_LEVEL_LOW: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_LEVEL_HIGH: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_RISING: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_FALLING: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_BOTH: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + default: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + } +} + +/* Enable/disable GPIO interrupt */ +static inline void pnx833x_gpio_enable_irq(unsigned int pin) +{ + SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); +} +static inline void pnx833x_gpio_disable_irq(unsigned int pin) +{ + CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); +} + +/* Clear GPIO interrupt request */ +static inline void pnx833x_gpio_clear_irq(unsigned int pin) +{ + SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); +} + +#endif diff -urN --exclude=.svn linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/irq.h linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/irq.h --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/irq.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/irq.h 2008-06-06 11:29:30.000000000 +0100 @@ -0,0 +1,139 @@ +/* + * irq.h: IRQ mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H +#define __ASM_MIPS_MACH_PNX833X_IRQ_H +/* + * The "IRQ numbers" are completely virtual. + * + * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48. + * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt, + * numbers 49..64 for (virtual) GPIO interrupts. + * + * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57, + * connected to PIC, which uses core hardware interrupt 2, and also + * a timer interrupt through hardware interrupt 5. + * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt, + * numbers 65..80 for (virtual) GPIO interrupts. + * + */ + +#if defined(CONFIG_SOC_PNX8335) + #define PNX833X_PIC_NUM_IRQ 58 +#else + #define PNX833X_PIC_NUM_IRQ 37 +#endif + +#define MIPS_CPU_NUM_IRQ 8 +#define PNX833X_GPIO_NUM_IRQ 16 + +#define MIPS_CPU_IRQ_BASE 0 +#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ) +#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ) +#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ) + + +#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) + +/* Interrupts supported by PIC */ +#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1) +#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2) +#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3) +#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4) +#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5) +#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6) +#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7) +#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8) +#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9) +#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10) +#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11) +#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12) +#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13) +#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13) +#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14) +#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15) +#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16) +#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17) +#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18) +#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19) +#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20) +#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21) +#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22) +#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23) +#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24) +#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25) +#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26) +#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27) +#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28) +#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29) +#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30) +#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31) +#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32) +#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33) +#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34) +#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35) +#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36) + +#if defined(CONFIG_SOC_PNX8335) +#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37) +#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38) +#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39) +#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40) +#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41) +#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42) +#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43) +#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44) +#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45) +#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46) +#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47) +#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48) +#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49) +#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50) +#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51) +#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52) +#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53) +#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54) +#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55) +#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56) +#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57) +#endif + +/* GPIO interrupts */ +#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0) +#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1) +#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2) +#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3) +#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4) +#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5) +#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6) +#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7) +#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8) +#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9) +#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10) +#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11) +#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12) +#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13) +#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14) +#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15) + +#endif + diff -urN --exclude=.svn linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/pnx833x.h linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/pnx833x.h --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/pnx833x.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/pnx833x.h 2008-06-06 11:29:43.000000000 +0100 @@ -0,0 +1,202 @@ +/* + * pnx833x.h: Register mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H +#define __ASM_MIPS_MACH_PNX833X_PNX833X_H + +/* All regs are accessed in KSEG1 */ +#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul) + +#define PNX833X_REG(offs) *((volatile unsigned long *)(PNX833X_BASE + offs)) + +/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */ + +/* Read access to multibit fields */ +#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) +#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field) + +/* Use PNX833X_FIELD to extract a field from val */ +#define PNX_FIELD(cpu, val, reg, field) \ + (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ + PNX##cpu##_##reg##_##field##_SHIFT) +#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) +#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) +#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) + +/* Use PNX833X_REGFIELD to extract a field from a register */ +#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field) +#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field) +#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field) + + +#define PNX_WRITEFIELD(cpu, val, reg, field) \ + PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \ + ((val) << PNX##cpu##_##reg##_##field##_SHIFT) +#define PNX833X_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(833X, val, reg, field) +#define PNX8330_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(8330, val, reg, field) +#define PNX8335_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(8335, val, reg, field) + + +/* Macros to detect CPU type */ + +#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC) +#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000 +#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12 +#define PNX8330_CONFIG_MODULE_MAJREV 4 +#define PNX8335_CONFIG_MODULE_MAJREV 5 +#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ + PNX8330_CONFIG_MODULE_MAJREV) +#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ + PNX8335_CONFIG_MODULE_MAJREV) + + + +#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) +#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) + +#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) +#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) +#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4) +#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */ +#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 +#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) + +#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) +#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 + +#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0 + +#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004) +#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */ + +#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040) +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000 +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19 + +#define PNX833X_PIO_IN PNX833X_REG(0xF000) +#define PNX833X_PIO_OUT PNX833X_REG(0xF004) +#define PNX833X_PIO_DIR PNX833X_REG(0xF008) +#define PNX833X_PIO_SEL PNX833X_REG(0xF014) +#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020) +#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024) +#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028) +#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0) +#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4) +#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8) +#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C) +#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060) +#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064) +#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068) + +#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000) +#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF) +#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000) +#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF) + +#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000) +#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF) + +#define PNX833X_CONFIG_USB PNX833X_REG(0x7008) + +#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000) +#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF) +#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000) +#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF) + +#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000) +#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF) +#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC) + +#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX833X_IDE_MODULE_ID_VALUE 0xA009 + + +#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004) +#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008) +#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C) +#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010) +#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014) +#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018) +#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C) +#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020) + +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 + +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 + +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9 + +#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000) + +#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) +#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 + +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 + +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 + +#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) +#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0 + +#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \ + PNX833X_MIU_CONFIG_SPI = \ + ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \ + ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \ + ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \ + ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT) + +#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000) +#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF) +#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC) + +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902 + + /* I/O location(gets remapped)*/ +#define PNX8335_NAND_BASE 0x18000000 +/* I/O location with CLE high */ +#define PNX8335_NAND_CLE_MASK 0x00100000 +/* I/O location with ALE high */ +#define PNX8335_NAND_ALE_MASK 0x00010000 + +#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000) +#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF) +#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC) + +#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX8335_SATA_MODULE_ID_VALUE 0xA099 + +#endif diff -urN --exclude=.svn linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/war.h linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/war.h --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/war.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/war.h 2008-06-05 09:34:22.000000000 +0100 @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H +#define __ASM_MIPS_MACH_PNX833X_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ From tytso@mit.edu Fri Jun 6 14:16:19 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 14:16:21 +0100 (BST) Received: from www.church-of-our-saviour.org ([69.25.196.31]:22442 "EHLO thunker.thunk.org") by ftp.linux-mips.org with ESMTP id S28585996AbYFFNQT (ORCPT ); Fri, 6 Jun 2008 14:16:19 +0100 Received: from root (helo=closure.thunk.org) by thunker.thunk.org with local-esmtp (Exim 4.50 #1 (Debian)) id 1K4bqH-000799-7j; Fri, 06 Jun 2008 09:18:53 -0400 Received: from tytso by closure.thunk.org with local (Exim 4.67) (envelope-from ) id 1K4bnH-0002rc-7l; Fri, 06 Jun 2008 09:15:47 -0400 Date: Fri, 6 Jun 2008 09:15:47 -0400 From: Theodore Tso To: Thiemo Seufer Cc: Vorobiev Dmitri , Martin Michlmayr , Ralf Baechle , Dmitri Vorobiev , linux-mips@linux-mips.org, linux-ext4@vger.kernel.org Subject: Re: ext4dev build failure on mips: "empty_zero_page" undefined Message-ID: <20080606131547.GB9033@mit.edu> References: <90edad820805120654n50f7a00cm3c7b4a4f9346d5ea@mail.gmail.com> <20080512143426.GB7029@mit.edu> <90edad820805120746l61e67362vbd177d63e8b05dc8@mail.gmail.com> <20080513045028.GC22226@linux-mips.org> <20080528070637.GA10393@deprecation.cyrius.com> <20080605111148.GA4483@deprecation.cyrius.com> <1212664977.4840.6.camel@sd048.hel.movial.fi> <20080605183854.GN25477@mit.edu> <38408.84.249.59.97.1212701650.squirrel@webmail.movial.fi> <20080605215152.GB15504@networkno.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080605215152.GB15504@networkno.de> User-Agent: Mutt/1.5.15+20070412 (2007-04-11) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: tytso@mit.edu X-SA-Exim-Scanned: No (on thunker.thunk.org); SAEximRunCond expanded to false Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19427 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tytso@mit.edu Precedence: bulk X-list: linux-mips On Thu, Jun 05, 2008 at 10:51:52PM +0100, Thiemo Seufer wrote: > > Ted, Ralf seems to be unwilling to accept the ZERO_PAGE() export. If you > > send the MIPS-specific patch, I can do the testing for you as I have a > > MIPS Malta board at my disposal. Ralf sent me a private note saying he would take care of this, but that he had been very busy with real-world life items. > AFAIU the problematic case are systems with R4000/R4400 SC/MC CPUs > since they use 8 zero pages of different color. Have a look at > arch/mips/mm/init.c:setup_zero_pages. Right. So we're not actually going to ever write to the page, but we are going to add the page to a bio and submit for writing. I assume that's not going to cause VECI/VCED exceptions, right? If the act of DMA'ing, or worse yet, for older devices/drivers which have to use PIO to write out a block device is going to cause "thousand and thousands of exceptions", it sounds like MIPS CPU designers need to be slapped silly.... - Ted From br1@einfach.org Fri Jun 6 15:42:01 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Jun 2008 15:42:03 +0100 (BST) Received: from mail30g.wh2.ocn.ne.jp ([220.111.41.239]:37231 "HELO mail30g.wh2.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S28642419AbYFFOmB (ORCPT ); Fri, 6 Jun 2008 15:42:01 +0100 Received: from vs30a.wh2.ocn.ne.jp (220.111.41.231) by mail30g.wh2.ocn.ne.jp (RS ver 1.0.95vs) with SMTP id 1-096493303; Fri, 6 Jun 2008 23:41:56 +0900 (JST) From: bruno randolf To: ralf@linux-mips.org Subject: [patch] add au1500 reserved interrupt Date: Fri, 6 Jun 2008 16:42:03 +0200 User-Agent: KMail/1.9.7 Cc: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200806061642.03883.br1@einfach.org> X-SF-Loop: 1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19428 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: br1@einfach.org Precedence: bulk X-list: linux-mips au1000: add au1500 reserved interrupt in the conversion done in the commits 95c4eb3ef4484ca85da5c98780d358cffd546b90 9d360ab4a7568a8d177280f651a8a772ae52b9b9 [MIPS] Alchemy: Renumber interrupts so irq_cpu can work. one reserved interrupt on au1500 was missed. this broke the au1000 ethernet driver. this patch against 2.6.25.4 makes it work again. Signed-off-by: Bruno Randolf --- a/include/asm-mips/mach-au1x00/au1000.h 2008-05-15 17:00:12.000000000 +0200 +++ b/include/asm-mips/mach-au1x00/au1000.h 2008-06-06 16:22:51.000000000 +0200 @@ -623,6 +623,7 @@ AU1000_RTC_MATCH1_INT, AU1000_RTC_MATCH2_INT, AU1500_PCI_ERR_INT, + AU1500_RESERVED_INT, AU1000_USB_DEV_REQ_INT, AU1000_USB_DEV_SUS_INT, AU1000_USB_HOST_INT, From luke@dashjr.org Sun Jun 8 05:32:12 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Jun 2008 05:32:15 +0100 (BST) Received: from wsip-70-184-212-2.om.om.cox.net ([70.184.212.2]:23526 "EHLO hachi.dashjr.org") by ftp.linux-mips.org with ESMTP id S29038660AbYFHEcM (ORCPT ); Sun, 8 Jun 2008 05:32:12 +0100 Received: from yokochan.lan (yokochan.lan [IPv6:2002:440d:6de2:0:20d:60ff:fe77:7d85]) (Authenticated sender: luke-jr) by hachi.dashjr.org (Postfix) with ESMTP id 3E565961B73; Sun, 8 Jun 2008 04:32:10 +0000 (UTC) From: Luke -Jr Organization: -Jr Family To: "Maciej W. Rozycki" Subject: Re: bcm33xx port Date: Sat, 7 Jun 2008 23:32:01 -0500 User-Agent: KMail/1.9.9 Cc: linux-kernel , linux-mips@linux-mips.org References: <200806072113.26433.luke@dashjr.org> In-Reply-To: PGP-Key-Fingerprint: CE5A D56A 36CC 69FA E7D2 3558 665F C11D D53E 9583 Jabber-ID: luke@dashjr.org MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200806072332.06460.luke@dashjr.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19430 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: luke@dashjr.org Precedence: bulk X-list: linux-mips On Saturday 07 June 2008, Maciej W. Rozycki wrote: > On Sat, 7 Jun 2008, Luke -Jr wrote: > > > I'm not too up on MIPS but there're a few things in the log which stand > > > out to me: > > > > > > Determined physical RAM map: > > > memory: 00fa0000 @ 00000000 (usable) > > > User-defined physical RAM map: > > > memory: 007a1200 @ 00000000 (usable) > > > > > > Can you confirm these sizes and locations for RAM? Does anything > > > change if you don't force the size constraint? > > > > According to > > http://research.msrg.utoronto.ca/ece344/2007s/os161/mips.html , MIPS has > > a pretty odd memory layout, and I'm honestly not sure how Linux usually > > handles it. I don't feel competent to try and summarize the details on > > that page here. > > Nothing odd about the memory layout I would say unless you want to go > beyond 512MB with a 32-bit system which is not the case here. Well, I always imagined memory layout as being a simple flat range from 0 to all_memory_in_system, but this is my first experience with it at such a low level, so I guess I don't know what's "odd" or "normal". > > > CPU frequency 32.00 MHz > > > > > > Really? Is your bootloader setting the CPU up correctly before handing > > > control to Linux? > > > > The CPU is 200 MHz, I believe. The bootloader is just a part of VxWorks, > > not really meant to boot anything else. > > CFE is pretty much standard for Broadcom platforms and far from being > specific to VxWorks. VxWorks, including the boot loader, is not CFE as far as I am aware. If you're referring to the "CFEv2" in the log, that appears to be the default of a switch (eg, if Linux doesn't detect anything else). > I'd be more concerned about: > > Calibrating delay loop (skipped)... 0.00 BogoMIPS preset The calibration code was crashing, so I set it to a fixed 1 value. Worst case, some code won't delay as long as it wants to, right? > > > Reserved instruction in kernel code[#1]: > > > > > > You're compiling with an appropriate -march switch? > > > > I believe so... It appears to be a "reserved instruction" only because of > > the memory area it tries to access. The instruction in question is "store > > word", nothing complex. > > You have got something seriously broken -- __bzero traps exceptions on > stores for graceful recovery as user addresses may be accessed as is the > case here. If the reserved instruction exception handler is reached, then > clearly the store instruction is not the immediate cause. What else could it be? From geert@linux-m68k.org Sun Jun 8 09:39:04 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Jun 2008 09:39:07 +0100 (BST) Received: from winston.telenet-ops.be ([195.130.137.75]:32642 "EHLO winston.telenet-ops.be") by ftp.linux-mips.org with ESMTP id S29038107AbYFHIjE (ORCPT ); Sun, 8 Jun 2008 09:39:04 +0100 Received: from localhost (localhost.localdomain [127.0.0.1]) by winston.telenet-ops.be (Postfix) with SMTP id 9834DA004D for ; Sun, 8 Jun 2008 10:39:03 +0200 (CEST) Received: from anakin.of.borg (78-21-204-88.access.telenet.be [78.21.204.88]) by winston.telenet-ops.be (Postfix) with ESMTP id 1319AA000C for ; Sun, 8 Jun 2008 10:39:02 +0200 (CEST) Received: from anakin.of.borg (localhost [127.0.0.1]) by anakin.of.borg (8.14.3/8.14.3/Debian-4) with ESMTP id m588d0I0021784 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT) for ; Sun, 8 Jun 2008 10:39:01 +0200 Received: from localhost (geert@localhost) by anakin.of.borg (8.14.3/8.14.3/Submit) with ESMTP id m588cvQ2021781 for ; Sun, 8 Jun 2008 10:38:59 +0200 X-Authentication-Warning: anakin.of.borg: geert owned process doing -bs Date: Sun, 8 Jun 2008 10:38:54 +0200 (CEST) From: Geert Uytterhoeven To: Linux/MIPS Development Subject: Re: linux-next: Tree for June 6 (fwd) Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19431 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips FYI... ---------- Forwarded message ---------- Date: Fri, 6 Jun 2008 21:11:51 +1000 From: Stephen Rothwell To: Dmitri Vorobiev Cc: linux-next@vger.kernel.org, LKML Subject: Re: linux-next: Tree for June 6 Hi Dmitri, On Fri, 06 Jun 2008 11:48:37 +0300 Dmitri Vorobiev wrote: > > Please see http://lkml.org/lkml/2008/6/4/152 where you'll find the > description of how I built a MIPS cross-toolchain and a working MIPS config. Thanks for that. Sorry I didn't respond sooner. We have managed to make a working tool chain and I will add some MIPS builds soon. Was the attached config just the malta_defconfig in the kernel tree, or there something special about it. I noticed that a straight defconfig build works for mips and mipsel. Would you expect all{no,mod}config to work? What would be a good 64 bit test config? It is easier for us if we just use the configs out of the kernel tree, but others are possible (its just harder to keep them up to date). -- Cheers, Stephen Rothwell sfr@canb.auug.org.au http://www.canb.auug.org.au/~sfr/ From macro@linux-mips.org Sun Jun 8 13:53:10 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Jun 2008 13:53:13 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:34288 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S20023669AbYFHMxK (ORCPT ); Sun, 8 Jun 2008 13:53:10 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m58Cr778021068; Sun, 8 Jun 2008 14:53:07 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m58Cr66i021064; Sun, 8 Jun 2008 13:53:06 +0100 Date: Sun, 8 Jun 2008 13:53:05 +0100 (BST) From: "Maciej W. Rozycki" To: Luke -Jr cc: linux-kernel , linux-mips@linux-mips.org Subject: Re: bcm33xx port In-Reply-To: <200806072332.06460.luke@dashjr.org> Message-ID: References: <200806072113.26433.luke@dashjr.org> <200806072332.06460.luke@dashjr.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19432 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, 7 Jun 2008, Luke -Jr wrote: > Well, I always imagined memory layout as being a simple flat range from 0 to > all_memory_in_system, but this is my first experience with it at such a low > level, so I guess I don't know what's "odd" or "normal". You mean the layout of virtual memory? Well, have a look at what the Alpha defines as sparse memory for something certainly less straightforward than what MIPS segments are. Anyway, what's reported here is physical memory and there is nothing special about it. > VxWorks, including the boot loader, is not CFE as far as I am aware. If you're > referring to the "CFEv2" in the log, that appears to be the default of a > switch (eg, if Linux doesn't detect anything else). That message is not included in the standard kernel -- how can I know it is meaningless? As I wrote CFE is standard Broadcom firmware. > The calibration code was crashing, so I set it to a fixed 1 value. > Worst case, some code won't delay as long as it wants to, right? That's grossly wrong. If you need to preset it for the time being till you debug calibration, then for a MIPS processor assume one instruction per clock tick and two instructions per loop -- that may not be entirely correct, but is a good approximation. Otherwise you risk peripheral devices are not driven correctly with all sorts of the nasty results. > > You have got something seriously broken -- __bzero traps exceptions on > > stores for graceful recovery as user addresses may be accessed as is the > > case here. If the reserved instruction exception handler is reached, then > > clearly the store instruction is not the immediate cause. > > What else could it be? Well, you've got the system and I have no crystal ball. You have means to debug it. See how control is passed to the RI exception. Find which of the TLB exceptions happens and how it proceeds. Etc... Maciej From luke@dashjr.org Sun Jun 8 19:57:12 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Jun 2008 19:57:14 +0100 (BST) Received: from wsip-70-184-212-2.om.om.cox.net ([70.184.212.2]:65463 "EHLO hachi.dashjr.org") by ftp.linux-mips.org with ESMTP id S20026287AbYFHS5M (ORCPT ); Sun, 8 Jun 2008 19:57:12 +0100 Received: from yokochan.lan (yokochan.lan [IPv6:2002:440d:6de2:0:20d:60ff:fe77:7d85]) (Authenticated sender: luke-jr) by hachi.dashjr.org (Postfix) with ESMTP id 32749961BC7; Sun, 8 Jun 2008 18:57:09 +0000 (UTC) From: Luke -Jr Organization: -Jr Family To: "Maciej W. Rozycki" Subject: Re: bcm33xx port Date: Sun, 8 Jun 2008 13:56:56 -0500 User-Agent: KMail/1.9.9 Cc: linux-kernel , linux-mips@linux-mips.org References: <200806072113.26433.luke@dashjr.org> <200806072332.06460.luke@dashjr.org> In-Reply-To: PGP-Key-Fingerprint: CE5A D56A 36CC 69FA E7D2 3558 665F C11D D53E 9583 Jabber-ID: luke@dashjr.org MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200806081357.02601.luke@dashjr.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19433 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: luke@dashjr.org Precedence: bulk X-list: linux-mips On Sunday 08 June 2008, Maciej W. Rozycki wrote: > On Sat, 7 Jun 2008, Luke -Jr wrote: > > VxWorks, including the boot loader, is not CFE as far as I am aware. If > > you're referring to the "CFEv2" in the log, that appears to be the > > default of a switch (eg, if Linux doesn't detect anything else). > > That message is not included in the standard kernel -- how can I know it > is meaningless? As I wrote CFE is standard Broadcom firmware. It's not? Guess it came from the bcm63xx patches OpenWrt has that I'm using as a base for this... Either way, it seems unlikely something claiming to be "VxWorks System Boot" is a standard firmware. > > The calibration code was crashing, so I set it to a fixed 1 value. > > Worst case, some code won't delay as long as it wants to, right? > > That's grossly wrong. If you need to preset it for the time being till > you debug calibration, then for a MIPS processor assume one instruction > per clock tick and two instructions per loop -- that may not be entirely > correct, but is a good approximation. Otherwise you risk peripheral > devices are not driven correctly with all sorts of the nasty results. Meaning this? preset_lpj = loops_per_jiffy = 2; > > > You have got something seriously broken -- __bzero traps exceptions on > > > stores for graceful recovery as user addresses may be accessed as is > > > the case here. If the reserved instruction exception handler is > > > reached, then clearly the store instruction is not the immediate cause. > > > > What else could it be? > > Well, you've got the system and I have no crystal ball. You have means > to debug it. See how control is passed to the RI exception. Find which > of the TLB exceptions happens and how it proceeds. Etc... Unfortunately, I don't understand how to "see how control is passed" or finding TLB exceptions... Could you point me in the right direction to learn about this? On Sunday 08 June 2008, Kevin D. Kissell wrote: > The universe of possible failures is large. The two most likely categories > are (a) configuring the build for a variant of the architecture (64-bit, > MIPS32R2) that your hardware doesn't support - this is what Maciej was > referring to, CONFIG_CPU_MIPS32_R1=y > and (b) control being transferred to a block of memory that isn't actually > code, as can happen if exception vectors or global pointers-to-functions > aren't set up correctly, or if the kernel stack is being corrupted. When > you say "the instruction in question is a store word", how do you know that? The RI error spits out a bunch of info, including epc which presumably points to the instruction causing the problem: ac85ffc0; this is 'sw a1,-64(a0)' Luke From kevink@mips.com Sun Jun 8 20:52:18 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Jun 2008 20:52:20 +0100 (BST) Received: from mx.mips.com ([63.167.95.198]:40354 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S20026418AbYFHTwS (ORCPT ); Sun, 8 Jun 2008 20:52:18 +0100 Received: from mercury.mips.com (mercury [192.168.64.101]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id m58JooQY005872; Sun, 8 Jun 2008 12:50:51 -0700 (PDT) Received: from [127.0.0.1] (grendel [192.168.236.16]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id m58Jpe4h003247; Sun, 8 Jun 2008 12:51:40 -0700 (PDT) Message-ID: <484C38A6.7080503@mips.com> Date: Sun, 08 Jun 2008 21:53:10 +0200 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.14 (Windows/20080421) MIME-Version: 1.0 To: Luke -Jr CC: "Maciej W. Rozycki" , linux-kernel , linux-mips@linux-mips.org Subject: Re: bcm33xx port References: <200806072113.26433.luke@dashjr.org> <200806072332.06460.luke@dashjr.org> <200806081357.02601.luke@dashjr.org> In-Reply-To: <200806081357.02601.luke@dashjr.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19434 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@mips.com Precedence: bulk X-list: linux-mips Luke -Jr wrote: > On Sunday 08 June 2008, Kevin D. Kissell wrote: > >> and (b) control being transferred to a block of memory that isn't actually >> code, as can happen if exception vectors or global pointers-to-functions >> aren't set up correctly, or if the kernel stack is being corrupted. When >> you say "the instruction in question is a store word", how do you know that? >> > > The RI error spits out a bunch of info, including epc which presumably points > to the instruction causing the problem: ac85ffc0; this is 'sw a1,-64(a0)' > But unless the processor itself is actually defective, there is no way that a SW instruction can cause an RI exception. Sometimes a kernel crash is so violent that the kernel stack frame cannot be reliably decoded by the crash dump code, and this would appear to be one of those cases. I find the address of 0xac85ffc0 to be a bit suspicious, myself. That's a kseg1 (non-cacheable identity map) address for physical address 0x0c85ffc0, which would be legitimate (though suspicious) if you had 256MB of RAM, but the boot log quote you posted earlier suggests that you've only got 16M. Is there really memory of some kind at that address? Are you calling routines in a boot ROM from Linux? Debugging Linux kernel crashes is probably not the best way to learn the MIPS privileged resource architecture. I'd strongly recommend http://www.amazon.com/See-MIPS-Second-Dominic-Sweetman/dp/0120884216/ Regards, Kevin K. From macro@linux-mips.org Sun Jun 8 20:59:36 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Jun 2008 20:59:38 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:49395 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S20026468AbYFHT7g (ORCPT ); Sun, 8 Jun 2008 20:59:36 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m58JxTCt022439; Sun, 8 Jun 2008 21:59:29 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m58JxKia022435; Sun, 8 Jun 2008 20:59:28 +0100 Date: Sun, 8 Jun 2008 20:59:19 +0100 (BST) From: "Maciej W. Rozycki" To: Luke -Jr cc: linux-kernel , linux-mips@linux-mips.org Subject: Re: bcm33xx port In-Reply-To: <200806081357.02601.luke@dashjr.org> Message-ID: References: <200806072113.26433.luke@dashjr.org> <200806072332.06460.luke@dashjr.org> <200806081357.02601.luke@dashjr.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19435 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, 8 Jun 2008, Luke -Jr wrote: > It's not? Guess it came from the bcm63xx patches OpenWrt has that I'm using as > a base for this... Either way, it seems unlikely something claiming to > be "VxWorks System Boot" is a standard firmware. It would be best if the patches you are referring to got merged with the mainline. Otherwise whoever uses them is essentially on their own -- people lack the resources needed to chase random changes out there in general. > > That's grossly wrong. If you need to preset it for the time being till > > you debug calibration, then for a MIPS processor assume one instruction > > per clock tick and two instructions per loop -- that may not be entirely > > correct, but is a good approximation. Otherwise you risk peripheral > > devices are not driven correctly with all sorts of the nasty results. > > Meaning this? > preset_lpj = loops_per_jiffy = 2; Not exactly. Try harder -- this is simple arithmetic and you've got all the data given above already. :) > > Well, you've got the system and I have no crystal ball. You have means > > to debug it. See how control is passed to the RI exception. Find which > > of the TLB exceptions happens and how it proceeds. Etc... > > Unfortunately, I don't understand how to "see how control is passed" or > finding TLB exceptions... Could you point me in the right direction to learn > about this? You can check how the return address is set at the function's entry point to see how it's called. As to the TLB exceptions -- well, read the MIPS architecture spec first. Then -- well, referring you to arch/mips/mm/tlbex.c would be pure cruelty ;) -- but have a look at do_page_fault(), which is where all the processing important here is done -- the machine code generated from tlbex.c handles the success paths only. > > and (b) control being transferred to a block of memory that isn't actually > > code, as can happen if exception vectors or global pointers-to-functions > > aren't set up correctly, or if the kernel stack is being corrupted. When > > you say "the instruction in question is a store word", how do you know that? > > The RI error spits out a bunch of info, including epc which presumably points > to the instruction causing the problem: ac85ffc0; this is 'sw a1,-64(a0)' I have seen that already and wrote these stores in __bzero are protected. Perhaps the fixup fails for some reason, but you need to investigate it and this is why I suggested to see how the RI handler is reached. Since this is a known point the failure leads to, you should be able to work backwards from there quite easily. Maciej From macro@linux-mips.org Sun Jun 8 21:14:18 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Jun 2008 21:14:20 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:40692 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S20026543AbYFHUOS (ORCPT ); Sun, 8 Jun 2008 21:14:18 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m58KEFcc022536; Sun, 8 Jun 2008 22:14:15 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m58KE6pu022532; Sun, 8 Jun 2008 21:14:06 +0100 Date: Sun, 8 Jun 2008 21:14:06 +0100 (BST) From: "Maciej W. Rozycki" To: "Kevin D. Kissell" cc: Luke -Jr , linux-kernel , linux-mips@linux-mips.org Subject: Re: bcm33xx port In-Reply-To: <484C38A6.7080503@mips.com> Message-ID: References: <200806072113.26433.luke@dashjr.org> <200806072332.06460.luke@dashjr.org> <200806081357.02601.luke@dashjr.org> <484C38A6.7080503@mips.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19436 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, 8 Jun 2008, Kevin D. Kissell wrote: > > The RI error spits out a bunch of info, including epc which presumably points > > to the instruction causing the problem: ac85ffc0; this is 'sw a1,-64(a0)' > > > But unless the processor itself is actually defective, there is no way that > a SW instruction can cause an RI exception. Sometimes a kernel crash > is so violent that the kernel stack frame cannot be reliably decoded by > the crash dump code, and this would appear to be one of those cases. > I find the address of 0xac85ffc0 to be a bit suspicious, myself. That's > a kseg1 (non-cacheable identity map) address for physical address > 0x0c85ffc0, which would be legitimate (though suspicious) if you had > 256MB of RAM, but the boot log quote you posted earlier suggests > that you've only got 16M. Is there really memory of some kind at > that address? Are you calling routines in a boot ROM from Linux? Well, 0xac85ffc0 is the instruction word corresponding to 'sw a1,-64(a0)'. :) The actual address of the failure is apparently 0x004e010c, which is pretty much a standard location somewhere within a user executable proper. Maciej From luke@dashjr.org Sun Jun 8 21:20:51 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Jun 2008 21:20:53 +0100 (BST) Received: from wsip-70-184-212-2.om.om.cox.net ([70.184.212.2]:12752 "EHLO hachi.dashjr.org") by ftp.linux-mips.org with ESMTP id S20026579AbYFHUUv (ORCPT ); Sun, 8 Jun 2008 21:20:51 +0100 Received: from yokochan.lan (yokochan.lan [IPv6:2002:440d:6de2:0:20d:60ff:fe77:7d85]) (Authenticated sender: luke-jr) by hachi.dashjr.org (Postfix) with ESMTP id 74160961BC8; Sun, 8 Jun 2008 20:20:48 +0000 (UTC) From: Luke -Jr Organization: -Jr Family To: "Kevin D. Kissell" Subject: Re: bcm33xx port Date: Sun, 8 Jun 2008 15:20:38 -0500 User-Agent: KMail/1.9.9 Cc: "Maciej W. Rozycki" , linux-kernel , linux-mips@linux-mips.org References: <200806072113.26433.luke@dashjr.org> <200806081357.02601.luke@dashjr.org> <484C38A6.7080503@mips.com> In-Reply-To: <484C38A6.7080503@mips.com> PGP-Key-Fingerprint: CE5A D56A 36CC 69FA E7D2 3558 665F C11D D53E 9583 Jabber-ID: luke@dashjr.org MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200806081520.43090.luke@dashjr.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19437 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: luke@dashjr.org Precedence: bulk X-list: linux-mips On Sunday 08 June 2008, Kevin D. Kissell wrote: > Luke -Jr wrote: > > On Sunday 08 June 2008, Kevin D. Kissell wrote: > >> and (b) control being transferred to a block of memory that isn't > >> actually code, as can happen if exception vectors or global > >> pointers-to-functions aren't set up correctly, or if the kernel stack is > >> being corrupted. When you say "the instruction in question is a store > >> word", how do you know that? > > > > The RI error spits out a bunch of info, including epc which presumably > > points to the instruction causing the problem: ac85ffc0; this is 'sw > > a1,-64(a0)' > > But unless the processor itself is actually defective, there is no way that > a SW instruction can cause an RI exception. Sometimes a kernel crash > is so violent that the kernel stack frame cannot be reliably decoded by > the crash dump code, and this would appear to be one of those cases. In that case, wouldn't the "kernel stack" appear to be complete nonsense? Yet the stack in this case is quite logical and consistent. Furthermore, if I skip the bzero stuff (by commenting out the call), it will crash shortly thereafter when the ELF loader attempts to write to it in another way. Is it very unlikely that the bcm3345 is simply raising the wrong exception (or perhaps Linux is misinterpreting the exception)? > I find the address of 0xac85ffc0 to be a bit suspicious, myself. That's > a kseg1 (non-cacheable identity map) address for physical address > 0x0c85ffc0, which would be legitimate (though suspicious) if you had > 256MB of RAM, but the boot log quote you posted earlier suggests > that you've only got 16M. Is there really memory of some kind at > that address? Are you calling routines in a boot ROM from Linux? ac85ffc0 is the instruction for 'sw a1,-64(a0)', not an address. The board has only 8 MB RAM, to the best I can tell from looking up the RAM chip (hynix KOREA HY57V641620HG 0229A T-7). > Debugging Linux kernel crashes is probably not the best way to learn > the MIPS privileged resource architecture. I'd strongly recommend > http://www.amazon.com/See-MIPS-Second-Dominic-Sweetman/dp/0120884216/ Can you recommend any gratis materials to read? I don't have room in my budget to spend money on this hobby right now.. Luke From luke@dashjr.org Sun Jun 8 21:27:34 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Jun 2008 21:27:36 +0100 (BST) Received: from wsip-70-184-212-2.om.om.cox.net ([70.184.212.2]:63877 "EHLO hachi.dashjr.org") by ftp.linux-mips.org with ESMTP id S20026628AbYFHU1e (ORCPT ); Sun, 8 Jun 2008 21:27:34 +0100 Received: from yokochan.lan (yokochan.lan [IPv6:2002:440d:6de2:0:20d:60ff:fe77:7d85]) (Authenticated sender: luke-jr) by hachi.dashjr.org (Postfix) with ESMTP id 5323C961BC8; Sun, 8 Jun 2008 20:27:32 +0000 (UTC) From: Luke -Jr Organization: -Jr Family To: "Maciej W. Rozycki" Subject: Re: bcm33xx port Date: Sun, 8 Jun 2008 15:27:28 -0500 User-Agent: KMail/1.9.9 Cc: linux-kernel , linux-mips@linux-mips.org References: <200806072113.26433.luke@dashjr.org> <200806081357.02601.luke@dashjr.org> In-Reply-To: PGP-Key-Fingerprint: CE5A D56A 36CC 69FA E7D2 3558 665F C11D D53E 9583 Jabber-ID: luke@dashjr.org MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200806081527.31221.luke@dashjr.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19438 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: luke@dashjr.org Precedence: bulk X-list: linux-mips On Sunday 08 June 2008, Maciej W. Rozycki wrote: > On Sun, 8 Jun 2008, Luke -Jr wrote: > > the bcm63xx patches OpenWrt has that I'm using as a base for this... > > It would be best if the patches you are referring to got merged with the > mainline. Otherwise whoever uses them is essentially on their own -- > people lack the resources needed to chase random changes out there in > general. Is merging with mainline something I can help with, being a beginner in this area generally and not having any part in writing them? > > > That's grossly wrong. If you need to preset it for the time being > > > till you debug calibration, then for a MIPS processor assume one > > > instruction per clock tick and two instructions per loop -- that may > > > not be entirely correct, but is a good approximation. Otherwise you > > > risk peripheral devices are not driven correctly with all sorts of the > > > nasty results. > > > > Meaning this? > > preset_lpj = loops_per_jiffy = 2; > > Not exactly. Try harder -- this is simple arithmetic and you've got all > the data given above already. :) 200 / 2? I'm not really sure what a 'jiffy' is.. > > > and (b) control being transferred to a block of memory that isn't > > > actually code, as can happen if exception vectors or global > > > pointers-to-functions aren't set up correctly, or if the kernel stack > > > is being corrupted. When you say "the instruction in question is a > > > store word", how do you know that? > > > > The RI error spits out a bunch of info, including epc which presumably > > points to the instruction causing the problem: ac85ffc0; this is 'sw > > a1,-64(a0)' > > I have seen that already and wrote these stores in __bzero are protected. > Perhaps the fixup fails for some reason, but you need to investigate it > and this is why I suggested to see how the RI handler is reached. Since > this is a known point the failure leads to, you should be able to work > backwards from there quite easily. Ah, so what you're saying is that perhaps the 'sw' is triggering a TLB exception, and the handler for *that* is causing the RI problem? Thanks, Luke From macro@linux-mips.org Sun Jun 8 23:13:44 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Jun 2008 23:13:46 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:27641 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S20027182AbYFHWNo (ORCPT ); Sun, 8 Jun 2008 23:13:44 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m58MDa9d022937; Mon, 9 Jun 2008 00:13:36 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m58MDN0g022933; Sun, 8 Jun 2008 23:13:32 +0100 Date: Sun, 8 Jun 2008 23:13:22 +0100 (BST) From: "Maciej W. Rozycki" To: Luke -Jr cc: linux-kernel , linux-mips@linux-mips.org Subject: Re: bcm33xx port In-Reply-To: <200806081527.31221.luke@dashjr.org> Message-ID: References: <200806072113.26433.luke@dashjr.org> <200806081357.02601.luke@dashjr.org> <200806081527.31221.luke@dashjr.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19439 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, 8 Jun 2008, Luke -Jr wrote: > Is merging with mainline something I can help with, being a beginner in this > area generally and not having any part in writing them? Well, you can certainly serve as a messenger telling them if they want people to get proper support from upstream maintainers they better merge sooner rather than later. Otherwise it is them who should really be bothered with cases like yours. The general principle is: "merge as soon as you can, even if code is incomplete" as you get more attention and perhaps developers involved as a result, some free support (e.g. with bulk changes done automatically to all the relevant bits in the tree) and avoid duplicated work; also when at the time of the merge you are told to rewrite your code differently. > > Not exactly. Try harder -- this is simple arithmetic and you've got all > > the data given above already. :) > > 200 / 2? I'm not really sure what a 'jiffy' is.. Hmm, I have thought it can be inferred from the code involved or failing that -- Google... Well, anyway, a jiffy is a tick of the kernel timer or, specifically in this context and to be more precise, the interval between such two consecutive ticks or, in other words, 1/HZ. > > I have seen that already and wrote these stores in __bzero are protected. > > Perhaps the fixup fails for some reason, but you need to investigate it > > and this is why I suggested to see how the RI handler is reached. Since > > this is a known point the failure leads to, you should be able to work > > backwards from there quite easily. > > Ah, so what you're saying is that perhaps the 'sw' is triggering a TLB > exception, and the handler for *that* is causing the RI problem? This is almost certain what happens here. The pointer involved is a valid (user) address and is correctly aligned, so you cannot get an address error exception. A TLB exception is next on the list to check. Of course you cannot rule out I-cache corruption or suchlike, but if I were you, I would start with simple assumptions first. Maciej From luke@dashjr.org Mon Jun 9 00:36:49 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 00:36:51 +0100 (BST) Received: from wsip-70-184-212-2.om.om.cox.net ([70.184.212.2]:47817 "EHLO hachi.dashjr.org") by ftp.linux-mips.org with ESMTP id S20027411AbYFHXgt (ORCPT ); Mon, 9 Jun 2008 00:36:49 +0100 Received: from yokochan.lan (yokochan.lan [IPv6:2002:440d:6de2:0:20d:60ff:fe77:7d85]) (Authenticated sender: luke-jr) by hachi.dashjr.org (Postfix) with ESMTP id E13CC961BCF; Sun, 8 Jun 2008 23:36:46 +0000 (UTC) From: Luke -Jr Organization: -Jr Family To: "Maciej W. Rozycki" Subject: Re: bcm33xx port Date: Sun, 8 Jun 2008 18:36:37 -0500 User-Agent: KMail/1.9.9 Cc: linux-kernel , linux-mips@linux-mips.org References: <200806072113.26433.luke@dashjr.org> <200806081527.31221.luke@dashjr.org> In-Reply-To: PGP-Key-Fingerprint: CE5A D56A 36CC 69FA E7D2 3558 665F C11D D53E 9583 Jabber-ID: luke@dashjr.org MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200806081836.42351.luke@dashjr.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19440 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: luke@dashjr.org Precedence: bulk X-list: linux-mips On Sunday 08 June 2008, Maciej W. Rozycki wrote: > On Sun, 8 Jun 2008, Luke -Jr wrote: > > Is merging with mainline something I can help with, being a beginner in > > this area generally and not having any part in writing them? > > Well, you can certainly serve as a messenger telling them if they want > people to get proper support from upstream maintainers they better merge > sooner rather than later. Apparently the reason for lack of merge is due to missing (proprietary?) drivers for DSL, Ethernet, and WiFi on the bcm63xx platform. I'll pass on the "incomplete is ok" message, though, and hopefully that will help :) > The general principle is: "merge as soon as you can, even if code is > incomplete" as you get more attention and perhaps developers involved as a > result, some free support (e.g. with bulk changes done automatically to > all the relevant bits in the tree) and avoid duplicated work; also when at > the time of the merge you are told to rewrite your code differently. Does this apply even to my trivial/barely begun attempts so far? When bcm63xx gets merged, should I be planning to merge my stuff even before it boots? > > > Not exactly. Try harder -- this is simple arithmetic and you've got > > > all the data given above already. :) > > > > 200 / 2? I'm not really sure what a 'jiffy' is.. > > Hmm, I have thought it can be inferred from the code involved or failing > that -- Google... Well, anyway, a jiffy is a tick of the kernel timer or, > specifically in this context and to be more precise, the interval between > such two consecutive ticks or, in other words, 1/HZ. jiffy = 1 / 200000 HZ = 0.000005 sec/tick loop = 200000 instructions / 2 instructions per loop = 100000 loops/sec So 0.00000000005 loops per jiffy? But it can't be, since loops_per_jiffy isn't floating point... :/ > > > I have seen that already and wrote these stores in __bzero are > > > protected. Perhaps the fixup fails for some reason, but you need to > > > investigate it and this is why I suggested to see how the RI handler is > > > reached. Since this is a known point the failure leads to, you should > > > be able to work backwards from there quite easily. > > > > Ah, so what you're saying is that perhaps the 'sw' is triggering a TLB > > exception, and the handler for *that* is causing the RI problem? > > This is almost certain what happens here. The pointer involved is a > valid (user) address and is correctly aligned, so you cannot get an > address error exception. A TLB exception is next on the list to check. Is there an easy way to printk out a complete trace of the exception stack? From sync.jma@gmail.com Mon Jun 9 04:01:15 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 04:01:17 +0100 (BST) Received: from wf-out-1314.google.com ([209.85.200.168]:56863 "EHLO wf-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20029302AbYFIDBP (ORCPT ); Mon, 9 Jun 2008 04:01:15 +0100 Received: by wf-out-1314.google.com with SMTP id 28so2391175wff.21 for ; Sun, 08 Jun 2008 20:01:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:mime-version:content-type:content-transfer-encoding :content-disposition; bh=DQmkV6WrooTb8F5oyLS6ACGCvTI6htP5BKynnKylmW4=; b=UGB6BcTUITgGMjJudDORuoHIiPT2hmaDwx2wPfiay8t/z7pbZYKS851i7iNjTwySI8 FR42ZUS8Ie4ZTRi1GSWwgnfNMS+fG3pmZK5MMm69Mb1J4IhdGZdWsR+EqiVzL4V4vJLh CVg8httadTF76RpsHiluY18WtE1xQiAJSBrBA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:mime-version:content-type :content-transfer-encoding:content-disposition; b=M/iBUuovy3dnOsdV9AFrlDHQRMrTmKFBfEQBC8mlQ6d6M/mwdiXDFKNC8OA91SCRQ1 Ap02/KqF3eR1QJ/WcKazKLJ2GXVVd/5u+W3dRdmdFMHAvBju6DDUhy5KUJjyjQr7mThy kG5cfkEHP4PVT696YsRDNinzwKxF3KWeH1wVU= Received: by 10.142.126.17 with SMTP id y17mr1202934wfc.170.1212980473022; Sun, 08 Jun 2008 20:01:13 -0700 (PDT) Received: by 10.143.42.1 with HTTP; Sun, 8 Jun 2008 20:01:12 -0700 (PDT) Message-ID: Date: Mon, 9 Jun 2008 11:01:12 +0800 From: J.Ma To: "linux-mips@linux-mips.org" Subject: linux-2.6.25.4 Porting OOPS MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19441 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sync.jma@gmail.com Precedence: bulk X-list: linux-mips Hi all, I am a newbie in kernel, so please be gentle.:) For these days, I am working on porting linux-2.6.25.4 to my own Broadcom's SOC board, and I choose BCM47xx to start when menuconfig. Everything goes well, I ported timer, serial, flash,etc. howerver, it just broken when jumping to the userspace routine /sbin/init, please take a look at the oops dump belowed. Could anyone give me a hint kindly? I doubt it might be the toolchain's problem(maybe syscall_exit got a invalid para), bcz the mipsel-linux- toolchain I used is built for linux-2.6.12. Since it would be a huge work to rebuild a new 2.6.25-based toolchain, I sent this email to check if any experienced guy could acknowledge this. Thanks in advance. open /dev/console done. try execute_command. try /sbin/init. Data bus error, epc == 8038c180, ra == 8000dd10 Oops[#1]: Cpu 0 $ 0 : 00000000 10008000 fffda000 00000001 $ 4 : 811bf000 fffda000 811bff00 fffda000 $ 8 : 81007b20 00000044 2aaad268 2ab45c5c $12 : 00000248 007cd68b 2ab48f4c 004670d0 $16 : 811bf000 80380000 7fb0a1d8 87d05a50 $20 : 87d7c7f8 87d05a50 87cfb1a0 7fb0a1d8 $24 : 000001b7 2aaa8a9c $28 : 87d78000 87d79da0 87cfb1f0 8000dd10 Hi : 308287f7 Lo : b4e07b20 epc : 8038c180 0x8038c180 Not tainted ra : 8000dd10 copy_user_highpage+0x98/0x158 Status: 10008003 KERNEL EXL IE Cause : 0080001c PrId : 00020000 (Broadcom BCM4710) Modules linked in: Process init (pid: 206, threadinfo=87d78000, task=87c32df8) Stack : 00000000 81007b20 87d7fc28 87d05a50 00000000 81007b20 87d7fc28 810237e0 800774f8 80077440 87cfb1a0 87d7c004 00000000 00000000 00000000 00000000 00000000 00000000 003d969b 87d7fc28 003d969b 87d05a50 87cfb1f0 7fb0a1d8 87d7c7f8 00030000 7fb0a624 80078c88 87cfb1a0 00000000 87c32df8 802c3b0c 87d7c7f8 87cfb1f0 003d969b 87cfb1a0 802c35ec 00000000 00000000 00000000 ... Call Trace: [<800774f8>] do_wp_page+0x58c/0x818 [<80077440>] do_wp_page+0x4d4/0x818 [<80078c88>] handle_mm_fault+0x778/0x86c [<802c3b0c>] _spin_unlock_irq+0x10/0x3c [<802c35ec>] __down_read+0x48/0x150 [<8000d6f0>] do_page_fault+0x100/0x340 [<80002a00>] ret_from_exception+0x0/0x24 [<80002a78>] syscall_exit+0x0/0x38 Code: cca40100 8ca80000 8ca90004 <8caa0008> 8cab000c cc9e0100 ac880000 ac890004 ac8a0008 note: init[206] exited with preempt_count 2 BUG: scheduling while atomic: init/206/0x10000002 Call Trace: [<80008384>] dump_stack+0x8/0x34 [<802c0c6c>] schedule+0x74/0x5b8 [<80023e90>] __cond_resched+0x30/0x5c [<802c1304>] _cond_resched+0x4c/0x60 [<802c2a50>] down_read+0x28/0x3c [<80056ecc>] acct_collect+0x48/0x1a8 [<8002c340>] do_exit+0x2a0/0x738 [<80008a80>] do_be+0x0/0x16c Data bus error, epc == 8038c180, ra == 8000dd10 Oops[#2]: Cpu 0 $ 0 : 00000000 10008000 fffda000 00000002 $ 4 : 811c4000 fffda000 811c4f00 fffda000 $ 8 : 81007b20 00000001 81023940 00080000 $12 : 00000000 80386980 00000001 2ab437dc $16 : 811c4000 80380000 7fb0a1dc 87d05058 $20 : 87d0a7f8 87d05058 87cfb000 7fb0a1dc $24 : 00000001 0046703c $28 : 87c18000 87c19da0 87cfb050 8000dd10 Hi : 308287f7 Lo : b4e07b20 epc : 8038c180 0x8038c180 Tainted: G D ra : 8000dd10 copy_user_highpage+0x98/0x158 Status: 10008003 KERNEL EXL IE Cause : 0080001c PrId : 00020000 (Broadcom BCM4710) Modules linked in: Process init (pid: 1, threadinfo=87c18000, task=87c16000) Stack : 00000000 81007b20 87d17c28 87d05058 00000000 81007b20 87d17c28 81023880 800774f8 80077440 00000000 10008000 00000001 ffffffff 00000000 00000000 00000000 00000000 003d969b 87d17c28 003d969b 87d05058 87cfb050 7fb0a1dc 87d0a7f8 00030000 7fb0a624 80078c88 000000ce 00000000 87c16000 802c3b0c 87d0a7f8 87cfb050 003d969b 87cfb000 802c35ec 8001fa34 87c18000 87c19e60 ... Call Trace: [<800774f8>] do_wp_page+0x58c/0x818 [<80077440>] do_wp_page+0x4d4/0x818 [<80078c88>] handle_mm_fault+0x778/0x86c [<802c3b0c>] _spin_unlock_irq+0x10/0x3c [<802c35ec>] __down_read+0x48/0x150 [<8001fa34>] enqueue_task_fair+0x2c/0x44 [<8000d6f0>] do_page_fault+0x100/0x340 [<80027908>] do_fork+0x254/0x338 [<800277d0>] do_fork+0x11c/0x338 [<8001f9cc>] set_next_entity+0x28/0x64 [<8001f9cc>] set_next_entity+0x28/0x64 [<8001fd84>] pick_next_task_fair+0xc0/0xf0 [<8001fdfc>] put_prev_task_fair+0x48/0x64 [<8001fde4>] put_prev_task_fair+0x30/0x64 [<802c1160>] schedule+0x568/0x5b8 [<80002a00>] ret_from_exception+0x0/0x24 [<80002b80>] work_resched+0x8/0x44 Code: cca40100 8ca80000 8ca90004 <8caa0008> 8cab000c cc9e0100 ac880000 ac890004 ac8a0008 note: init[1] exited with preempt_count 2 Kernel panic - not syncing: Attempted to kill init! -- FIXME if it is wrong. From markus.gothe@27m.se Mon Jun 9 06:53:34 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 06:53:37 +0100 (BST) Received: from mail.lysator.liu.se ([130.236.254.3]:20637 "EHLO mail.lysator.liu.se") by ftp.linux-mips.org with ESMTP id S20029819AbYFIFxe (ORCPT ); Mon, 9 Jun 2008 06:53:34 +0100 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.lysator.liu.se (Postfix) with ESMTP id 1AD2F200A226; Mon, 9 Jun 2008 07:53:29 +0200 (CEST) Received: from mail.lysator.liu.se ([127.0.0.1]) by localhost (lenin.lysator.liu.se [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 26769-01-46; Mon, 9 Jun 2008 07:53:28 +0200 (CEST) Received: from [192.168.10.105] (h-79-136-60-134.NA.cust.bahnhof.se [79.136.60.134]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.lysator.liu.se (Postfix) with ESMTP id DC864200A213; Mon, 9 Jun 2008 07:53:27 +0200 (CEST) Cc: "linux-mips@linux-mips.org" Message-Id: <20B109E2-594E-4329-95C7-F67E9A7882E2@27m.se> From: Markus Gothe To: J.Ma In-Reply-To: Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg=pgp-sha1; boundary="Apple-Mail-11-607889873" Mime-Version: 1.0 (Apple Message framework v924) Subject: Re: [SPAM] linux-2.6.25.4 Porting OOPS Date: Mon, 9 Jun 2008 07:53:27 +0200 References: X-Pgp-Agent: GPGMail d53 (v53, Leopard) Content-Transfer-Encoding: 7bit X-Mailer: Apple Mail (2.924) X-Virus-Scanned: by amavisd-new-20030616-p10 (Debian) at lysator.liu.se Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19442 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markus.gothe@27m.se Precedence: bulk X-list: linux-mips This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --Apple-Mail-11-607889873 Content-Type: multipart/alternative; boundary=Apple-Mail-10-607889831 --Apple-Mail-10-607889831 Content-Type: text/plain; charset=ISO-8859-1; format=flowed; delsp=yes Content-Transfer-Encoding: quoted-printable Start with checking the memory mapping as hinted by: ra : 8000dd10 copy_user_highpage+0x98/0x158 //Markus On 9 Jun 2008, at 05:01, J.Ma wrote: > Hi all, > I am a newbie in kernel, so please be gentle.:) > For these days, I am working on porting linux-2.6.25.4 to my own > Broadcom's SOC board, and I choose BCM47xx to start when menuconfig. > Everything goes well, I ported timer, serial, flash,etc. howerver, it > just broken when jumping to the userspace routine /sbin/init, please > take a look at the oops dump belowed. > Could anyone give me a hint kindly? I doubt it might be the > toolchain's problem(maybe syscall_exit got a invalid para), bcz the > mipsel-linux- toolchain I used is built for linux-2.6.12. Since it > would be a huge work to rebuild a new 2.6.25-based toolchain, I sent > this email to check if any experienced guy could acknowledge this. > Thanks in advance. > > > > open /dev/console done. > try execute_command. > try /sbin/init. > Data bus error, epc =3D=3D 8038c180, ra =3D=3D 8000dd10 > Oops[#1]: > Cpu 0 > $ 0 : 00000000 10008000 fffda000 00000001 > $ 4 : 811bf000 fffda000 811bff00 fffda000 > $ 8 : 81007b20 00000044 2aaad268 2ab45c5c > $12 : 00000248 007cd68b 2ab48f4c 004670d0 > $16 : 811bf000 80380000 7fb0a1d8 87d05a50 > $20 : 87d7c7f8 87d05a50 87cfb1a0 7fb0a1d8 > $24 : 000001b7 2aaa8a9c > $28 : 87d78000 87d79da0 87cfb1f0 8000dd10 > Hi : 308287f7 > Lo : b4e07b20 > epc : 8038c180 0x8038c180 Not tainted > ra : 8000dd10 copy_user_highpage+0x98/0x158 > Status: 10008003 KERNEL EXL IE > Cause : 0080001c > PrId : 00020000 (Broadcom BCM4710) > Modules linked in: > Process init (pid: 206, threadinfo=3D87d78000, task=3D87c32df8) > Stack : 00000000 81007b20 87d7fc28 87d05a50 00000000 81007b20 =20 > 87d7fc28 810237e0 > 800774f8 80077440 87cfb1a0 87d7c004 00000000 00000000 =20 > 00000000 00000000 > 00000000 00000000 003d969b 87d7fc28 003d969b 87d05a50 =20 > 87cfb1f0 7fb0a1d8 > 87d7c7f8 00030000 7fb0a624 80078c88 87cfb1a0 00000000 =20 > 87c32df8 802c3b0c > 87d7c7f8 87cfb1f0 003d969b 87cfb1a0 802c35ec 00000000 =20 > 00000000 00000000 > ... > Call Trace: > [<800774f8>] do_wp_page+0x58c/0x818 > [<80077440>] do_wp_page+0x4d4/0x818 > [<80078c88>] handle_mm_fault+0x778/0x86c > [<802c3b0c>] _spin_unlock_irq+0x10/0x3c > [<802c35ec>] __down_read+0x48/0x150 > [<8000d6f0>] do_page_fault+0x100/0x340 > [<80002a00>] ret_from_exception+0x0/0x24 > [<80002a78>] syscall_exit+0x0/0x38 > > > Code: cca40100 8ca80000 8ca90004 <8caa0008> 8cab000c cc9e0100 > ac880000 ac890004 ac8a0008 > note: init[206] exited with preempt_count 2 > BUG: scheduling while atomic: init/206/0x10000002 > Call Trace: > [<80008384>] dump_stack+0x8/0x34 > [<802c0c6c>] schedule+0x74/0x5b8 > [<80023e90>] __cond_resched+0x30/0x5c > [<802c1304>] _cond_resched+0x4c/0x60 > [<802c2a50>] down_read+0x28/0x3c > [<80056ecc>] acct_collect+0x48/0x1a8 > [<8002c340>] do_exit+0x2a0/0x738 > [<80008a80>] do_be+0x0/0x16c > > Data bus error, epc =3D=3D 8038c180, ra =3D=3D 8000dd10 > Oops[#2]: > Cpu 0 > $ 0 : 00000000 10008000 fffda000 00000002 > $ 4 : 811c4000 fffda000 811c4f00 fffda000 > $ 8 : 81007b20 00000001 81023940 00080000 > $12 : 00000000 80386980 00000001 2ab437dc > $16 : 811c4000 80380000 7fb0a1dc 87d05058 > $20 : 87d0a7f8 87d05058 87cfb000 7fb0a1dc > $24 : 00000001 0046703c > $28 : 87c18000 87c19da0 87cfb050 8000dd10 > Hi : 308287f7 > Lo : b4e07b20 > epc : 8038c180 0x8038c180 Tainted: G D > ra : 8000dd10 copy_user_highpage+0x98/0x158 > Status: 10008003 KERNEL EXL IE > Cause : 0080001c > PrId : 00020000 (Broadcom BCM4710) > Modules linked in: > Process init (pid: 1, threadinfo=3D87c18000, task=3D87c16000) > Stack : 00000000 81007b20 87d17c28 87d05058 00000000 81007b20 =20 > 87d17c28 81023880 > 800774f8 80077440 00000000 10008000 00000001 ffffffff =20 > 00000000 00000000 > 00000000 00000000 003d969b 87d17c28 003d969b 87d05058 =20 > 87cfb050 7fb0a1dc > 87d0a7f8 00030000 7fb0a624 80078c88 000000ce 00000000 =20 > 87c16000 802c3b0c > 87d0a7f8 87cfb050 003d969b 87cfb000 802c35ec 8001fa34 =20 > 87c18000 87c19e60 > ... > Call Trace: > [<800774f8>] do_wp_page+0x58c/0x818 > [<80077440>] do_wp_page+0x4d4/0x818 > [<80078c88>] handle_mm_fault+0x778/0x86c > [<802c3b0c>] _spin_unlock_irq+0x10/0x3c > [<802c35ec>] __down_read+0x48/0x150 > [<8001fa34>] enqueue_task_fair+0x2c/0x44 > [<8000d6f0>] do_page_fault+0x100/0x340 > [<80027908>] do_fork+0x254/0x338 > [<800277d0>] do_fork+0x11c/0x338 > [<8001f9cc>] set_next_entity+0x28/0x64 > [<8001f9cc>] set_next_entity+0x28/0x64 > [<8001fd84>] pick_next_task_fair+0xc0/0xf0 > [<8001fdfc>] put_prev_task_fair+0x48/0x64 > [<8001fde4>] put_prev_task_fair+0x30/0x64 > [<802c1160>] schedule+0x568/0x5b8 > [<80002a00>] ret_from_exception+0x0/0x24 > [<80002b80>] work_resched+0x8/0x44 > > > Code: cca40100 8ca80000 8ca90004 <8caa0008> 8cab000c cc9e0100 > ac880000 ac890004 ac8a0008 > note: init[1] exited with preempt_count 2 > Kernel panic - not syncing: Attempted to kill init! > > > > --=20 > FIXME if it is wrong. > _______________________________________ Mr Markus Gothe Software Engineer Phone: +46 (0)13 21 81 20 (ext. 1046) Fax: +46 (0)13 21 21 15 Mobile: +46 (0)70 348 44 35 Diskettgatan 11, SE-583 35 Link=F6ping, Sweden www.27m.com --Apple-Mail-10-607889831 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Start with checking the = memory mapping as hinted by:
ra    : 8000dd10 = copy_user_highpage+0x98/0x158

//Markus

On 9 Jun 2008, at 05:01, J.Ma wrote:

Hi = all,
   I am a newbie in kernel, so please be = gentle.:)
   For these days, I am working on porting = linux-2.6.25.4 to my own
Broadcom's SOC board, and I choose BCM47xx = to start when menuconfig.
Everything goes well, I ported timer, = serial, flash,etc. howerver, it
just broken when jumping to the = userspace routine /sbin/init, please
take a look at the oops dump = belowed.
   Could anyone give me a hint kindly? I = doubt it might be the
toolchain's problem(maybe syscall_exit got a = invalid para), bcz the
mipsel-linux- toolchain I used is built for = linux-2.6.12. Since it
would be a huge work to rebuild a new = 2.6.25-based toolchain, I sent
this email to check if any experienced = guy could acknowledge this.
   Thanks in = advance.



open /dev/console done.
try = execute_command.
try /sbin/init.
Data bus error, epc =3D=3D = 8038c180, ra =3D=3D 8000dd10
Oops[#1]:
Cpu 0
$ 0   : = 00000000 10008000 fffda000 00000001
$ 4   : 811bf000 = fffda000 811bff00 fffda000
$ 8   : 81007b20 00000044 = 2aaad268 2ab45c5c
$12   : 00000248 007cd68b 2ab48f4c = 004670d0
$16   : 811bf000 80380000 7fb0a1d8 87d05a50
$20 =   : 87d7c7f8 87d05a50 87cfb1a0 7fb0a1d8
$24   : = 000001b7 2aaa8a9c
$28   : 87d78000 87d79da0 87cfb1f0 = 8000dd10
Hi    : 308287f7
Lo    : = b4e07b20
epc   : 8038c180 0x8038c180 =     Not tainted
ra    : 8000dd10 = copy_user_highpage+0x98/0x158
Status: 10008003 =    KERNEL EXL IE
Cause : 0080001c
PrId  : = 00020000 (Broadcom BCM4710)
Modules linked in:
Process init (pid: = 206, threadinfo=3D87d78000, task=3D87c32df8)
Stack : 00000000 = 81007b20 87d7fc28 87d05a50 00000000 81007b20 87d7fc28 810237e0
=        800774f8 80077440 87cfb1a0 = 87d7c004 00000000 00000000 00000000 00000000
=        00000000 00000000 003d969b = 87d7fc28 003d969b 87d05a50 87cfb1f0 7fb0a1d8
=        87d7c7f8 00030000 7fb0a624 = 80078c88 87cfb1a0 00000000 87c32df8 802c3b0c
=        87d7c7f8 87cfb1f0 003d969b = 87cfb1a0 802c35ec 00000000 00000000 00000000
=        ...
Call = Trace:
[<800774f8>] do_wp_page+0x58c/0x818
[<80077440>] = do_wp_page+0x4d4/0x818
[<80078c88>] = handle_mm_fault+0x778/0x86c
[<802c3b0c>] = _spin_unlock_irq+0x10/0x3c
[<802c35ec>] = __down_read+0x48/0x150
[<8000d6f0>] = do_page_fault+0x100/0x340
[<80002a00>] = ret_from_exception+0x0/0x24
[<80002a78>] = syscall_exit+0x0/0x38


Code: cca40100  8ca80000 =  8ca90004 <8caa0008> 8cab000c  cc9e0100
ac880000 =  ac890004  ac8a0008
note: init[206] exited with = preempt_count 2
BUG: scheduling while atomic: = init/206/0x10000002
Call Trace:
[<80008384>] = dump_stack+0x8/0x34
[<802c0c6c>] = schedule+0x74/0x5b8
[<80023e90>] = __cond_resched+0x30/0x5c
[<802c1304>] = _cond_resched+0x4c/0x60
[<802c2a50>] = down_read+0x28/0x3c
[<80056ecc>] = acct_collect+0x48/0x1a8
[<8002c340>] = do_exit+0x2a0/0x738
[<80008a80>] do_be+0x0/0x16c

Data bus = error, epc =3D=3D 8038c180, ra =3D=3D 8000dd10
Oops[#2]:
Cpu = 0
$ 0   : 00000000 10008000 fffda000 00000002
$ 4 =   : 811c4000 fffda000 811c4f00 fffda000
$ 8   : = 81007b20 00000001 81023940 00080000
$12   : 00000000 = 80386980 00000001 2ab437dc
$16   : 811c4000 80380000 = 7fb0a1dc 87d05058
$20   : 87d0a7f8 87d05058 87cfb000 = 7fb0a1dc
$24   : 00000001 0046703c
$28   : = 87c18000 87c19da0 87cfb050 8000dd10
Hi    : = 308287f7
Lo    : b4e07b20
epc   : = 8038c180 0x8038c180     Tainted: G =      D
ra    : 8000dd10 = copy_user_highpage+0x98/0x158
Status: 10008003 =    KERNEL EXL IE
Cause : 0080001c
PrId  : = 00020000 (Broadcom BCM4710)
Modules linked in:
Process init (pid: = 1, threadinfo=3D87c18000, task=3D87c16000)
Stack : 00000000 81007b20 = 87d17c28 87d05058 00000000 81007b20 87d17c28 81023880
=        800774f8 80077440 00000000 = 10008000 00000001 ffffffff 00000000 00000000
=        00000000 00000000 003d969b = 87d17c28 003d969b 87d05058 87cfb050 7fb0a1dc
=        87d0a7f8 00030000 7fb0a624 = 80078c88 000000ce 00000000 87c16000 802c3b0c
=        87d0a7f8 87cfb050 003d969b = 87cfb000 802c35ec 8001fa34 87c18000 87c19e60
=        ...
Call = Trace:
[<800774f8>] do_wp_page+0x58c/0x818
[<80077440>] = do_wp_page+0x4d4/0x818
[<80078c88>] = handle_mm_fault+0x778/0x86c
[<802c3b0c>] = _spin_unlock_irq+0x10/0x3c
[<802c35ec>] = __down_read+0x48/0x150
[<8001fa34>] = enqueue_task_fair+0x2c/0x44
[<8000d6f0>] = do_page_fault+0x100/0x340
[<80027908>] = do_fork+0x254/0x338
[<800277d0>] = do_fork+0x11c/0x338
[<8001f9cc>] = set_next_entity+0x28/0x64
[<8001f9cc>] = set_next_entity+0x28/0x64
[<8001fd84>] = pick_next_task_fair+0xc0/0xf0
[<8001fdfc>] = put_prev_task_fair+0x48/0x64
[<8001fde4>] = put_prev_task_fair+0x30/0x64
[<802c1160>] = schedule+0x568/0x5b8
[<80002a00>] = ret_from_exception+0x0/0x24
[<80002b80>] = work_resched+0x8/0x44


Code: cca40100  8ca80000 =  8ca90004 <8caa0008> 8cab000c  cc9e0100
ac880000 =  ac890004  ac8a0008
note: init[1] exited with preempt_count = 2
Kernel panic - not syncing: Attempted to kill = init!



--
FIXME if it is = wrong.



Mr Markus = Gothe
Software Engineer

Phone: = +46 (0)13 21 81 20 (ext. 1046)
Fax: +46 = (0)13 21 21 15
Mobile: +46 (0)70 348 44 = 35
Diskettgatan 11, SE-583 35 Link=F6ping, = Sweden



= --Apple-Mail-10-607889831-- --Apple-Mail-11-607889873 content-type: application/pgp-signature; x-mac-type=70674453; name=PGP.sig content-description: This is a digitally signed message part content-disposition: inline; filename=PGP.sig content-transfer-encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.8 (Darwin) iEYEARECAAYFAkhMxVcACgkQ6I0XmJx2NryARQCfT341f3nPpY98PX3TRquWE5GC jqcAnjONVX8rijkYvJMm7QL8CAi+pSnO =+FXh -----END PGP SIGNATURE----- --Apple-Mail-11-607889873-- From luke@dashjr.org Mon Jun 9 07:05:48 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:05:50 +0100 (BST) Received: from wsip-70-184-212-2.om.om.cox.net ([70.184.212.2]:14820 "EHLO hachi.dashjr.org") by ftp.linux-mips.org with ESMTP id S20029853AbYFIGFs (ORCPT ); Mon, 9 Jun 2008 07:05:48 +0100 Received: from yokochan.lan (yokochan.lan [IPv6:2002:440d:6de2:0:20d:60ff:fe77:7d85]) (Authenticated sender: luke-jr) by hachi.dashjr.org (Postfix) with ESMTP id F120D961B98; Mon, 9 Jun 2008 06:05:45 +0000 (UTC) From: Luke -Jr Organization: -Jr Family To: "Maciej W. Rozycki" Subject: Re: bcm33xx port Date: Mon, 9 Jun 2008 01:05:28 -0500 User-Agent: KMail/1.9.9 Cc: linux-kernel , linux-mips@linux-mips.org References: <200806072113.26433.luke@dashjr.org> <200806081527.31221.luke@dashjr.org> In-Reply-To: PGP-Key-Fingerprint: CE5A D56A 36CC 69FA E7D2 3558 665F C11D D53E 9583 Jabber-ID: luke@dashjr.org MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200806090105.37978.luke@dashjr.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19443 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: luke@dashjr.org Precedence: bulk X-list: linux-mips On Sunday 08 June 2008, Maciej W. Rozycki wrote: > On Sun, 8 Jun 2008, Luke -Jr wrote: > > > I have seen that already and wrote these stores in __bzero are > > > protected. Perhaps the fixup fails for some reason, but you need to > > > investigate it and this is why I suggested to see how the RI handler is > > > reached. Since this is a known point the failure leads to, you should > > > be able to work backwards from there quite easily. > > > > Ah, so what you're saying is that perhaps the 'sw' is triggering a TLB > > exception, and the handler for *that* is causing the RI problem? > > This is almost certain what happens here. The pointer involved is a > valid (user) address and is correctly aligned, so you cannot get an > address error exception. A TLB exception is next on the list to check. I added some code to do_ri: if (unlikely(!user_mode(regs))) { long real_epc; asm("move %0, $sp" : "=r"(real_epc)); printk("----- LJR -------\n"); show_raw_backtrace(real_epc); printk("----- LJRx-------\n"); } Which gave me some potentially useful info: ----- LJR ------- Call Trace: [<80011460>] ret_from_exception+0x0/0x24 [<80069de4>] vma_link+0x48/0x114 [<8001b1f0>] blast_icache16+0x0/0xec [<800aa27c>] padzero+0x5c/0x74 [<800c6774>] __bzero+0x38/0x164 [<800ab04c>] load_elf_binary+0x948/0x145c [<800aac6c>] load_elf_binary+0x568/0x145c [<80083b80>] __path_lookup_intent_open+0x60/0xe4 [<80083b50>] __path_lookup_intent_open+0x30/0xe4 [<80080044>] permission+0x10c/0x148 [<8007bfd4>] search_binary_handler+0x78/0x18c [<800aa15c>] load_script+0x25c/0x270 [<800aa148>] load_script+0x248/0x270 [<800aa7b4>] load_elf_binary+0xb0/0x145c [<8007c204>] get_arg_page+0x4c/0xc4 [<8001cab4>] r4k_flush_cache_page+0x1c/0x28 [<8007bfd4>] search_binary_handler+0x78/0x18c [<8007e004>] do_execve+0x18c/0x258 [<8007dfe4>] do_execve+0x16c/0x258 [<80081074>] getname+0x24/0x118 [<8001570c>] sys_execve+0x4c/0x78 [<80030610>] release_console_sem+0x114/0x358 [<80018410>] stack_done+0x20/0x3c [<80031038>] vprintk+0x368/0x448 [<8007554c>] get_unused_fd_flags+0x60/0x184 [<80081074>] getname+0x24/0x118 [<80010478>] init_post+0x60/0xe8 [<80015584>] kernel_execve+0x8/0x20 [<800136cc>] kernel_thread_helper+0x10/0x18 [<800136bc>] kernel_thread_helper+0x0/0x18 ----- LJRx------- Too tired to debug further tonight, but hopefully this stack will stand out to someone :) Luke From mano@roarinelk.homelinux.net Mon Jun 9 07:35:23 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:35:25 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:11393 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20029913AbYFIGfX (ORCPT ); Mon, 9 Jun 2008 07:35:23 +0100 Received: (qmail 8802 invoked by uid 1000); 9 Jun 2008 08:35:21 +0200 Date: Mon, 9 Jun 2008 08:35:21 +0200 From: Manuel Lauss To: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: [PATCH 0/8] au1xmmc updates #4 Message-ID: <20080609063521.GA8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19444 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hello, The following set of patches updates the au1xmmc driver with new features and moves code not belonging to the driver source to MIPS/Alchemy board files. I also took the opportunity to clean up the drivers probe() and irq() handlers to make it a "proper" platform device (patches #1 and #2). Patches #3, #4 and #6 implement new features, #5 and #7 are cleanups. The patches are intended to be applied on top of each other, against current mainline git (2.6.23-rc5+). Changes since V3: - previous patches #1 and #2 are dropped since they are already upstream. ("Alchemy: export get_au1x00_speed for modules" and "Alchemy: dbdma: add API to delete custom DDMA device") - few additional minor fixes and patches folded into others. - I'm taking over maintainership of the driver for as long as I have hardware to test it on. Changes since V2: - address almost all Sergei Shtylyov's comments: pb1200/db1200 mmc device registration moved back to original location, remove the au1xmmc.h header as part of codingstyle cleanup other nits. - 2 more patches (#8, #9) Changes since V1: - fix a bug in patch #6: SDIO irq should be checked for independently from other irq events. - more trivial cleanups Db1200 users, please test! I verified the poll timer works on one of older boards, however since I don't have Db1200 and Pb1200 boards I'm not sure whether the driver still works with both SD controllers enabled! Thanks! Manuel Lauss From mano@roarinelk.homelinux.net Mon Jun 9 07:36:14 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:36:17 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:33934 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20029892AbYFIGgO (ORCPT ); Mon, 9 Jun 2008 07:36:14 +0100 Received: (qmail 8815 invoked by uid 1000); 9 Jun 2008 08:36:13 +0200 Date: Mon, 9 Jun 2008 08:36:13 +0200 From: Manuel Lauss To: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: [PATCH 1/8] au1xmmc: remove db1200 board code, rewrite probe. Message-ID: <20080609063612.GB8724@roarinelk.homelinux.net> References: <20080609063521.GA8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080609063521.GA8724@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19445 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips From 73c332090c720cf35244421a6c4b6c92e21457b7 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 7 May 2008 14:57:01 +0200 Subject: [PATCH] au1xmmc: remove db1200 board code, rewrite probe. Remove the DB1200 board-specific functions (card present, read-only, activity LED methods) and instead add platform data which is passed to the driver. This also allows for platforms to implement other carddetect schemes (e.g. dedicated irq) without having to pollute the driver code. The poll timer (used for pb1200) is kept for compatibility. With the board-specific stuff gone, the driver's ->probe() code can be cleaned up considerably. Signed-off-by: Manuel Lauss --- drivers/mmc/host/au1xmmc.c | 573 +++++++++++++++++------------ drivers/mmc/host/au1xmmc.h | 9 +- include/asm-mips/mach-au1x00/au1100_mmc.h | 16 +- 3 files changed, 353 insertions(+), 245 deletions(-) diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index cc5f7bc..d8776d6 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -41,8 +41,9 @@ #include #include #include - +#include #include + #include #include #include @@ -54,6 +55,7 @@ #define DRIVER_NAME "au1xxx-mmc" /* Set this to enable special debugging macros */ +/* #define DEBUG */ #ifdef DEBUG #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args) @@ -61,32 +63,6 @@ #define DBG(fmt, idx, args...) #endif -const struct { - u32 iobase; - u32 tx_devid, rx_devid; - u16 bcsrpwr; - u16 bcsrstatus; - u16 wpstatus; -} au1xmmc_card_table[] = { - { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0, - BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP }, -#ifndef CONFIG_MIPS_DB1200 - { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1, - BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP } -#endif -}; - -#define AU1XMMC_CONTROLLER_COUNT (ARRAY_SIZE(au1xmmc_card_table)) - -/* This array stores pointers for the hosts (used by the IRQ handler) */ -struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT]; -static int dma = 1; - -#ifdef MODULE -module_param(dma, bool, 0); -MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)"); -#endif - static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) { u32 val = au_readl(HOST_CONFIG(host)); @@ -135,26 +111,33 @@ static inline void SEND_STOP(struct au1xmmc_host *host) static void au1xmmc_set_power(struct au1xmmc_host *host, int state) { - - u32 val = au1xmmc_card_table[host->id].bcsrpwr; - - bcsr->board &= ~val; - if (state) bcsr->board |= val; - - au_sync_delay(1); + if (host->platdata && host->platdata->set_power) + host->platdata->set_power(host->mmc, state); } -static inline int au1xmmc_card_inserted(struct au1xmmc_host *host) +static int au1xmmc_card_inserted(struct au1xmmc_host *host) { - return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus) - ? 1 : 0; + int ret; + + if (host->platdata && host->platdata->card_inserted) + ret = host->platdata->card_inserted(host->mmc); + else + ret = 1; /* assume there is a card */ + + return ret; } static int au1xmmc_card_readonly(struct mmc_host *mmc) { struct au1xmmc_host *host = mmc_priv(mmc); - return (bcsr->status & au1xmmc_card_table[host->id].wpstatus) - ? 1 : 0; + int ret; + + if (host->platdata && host->platdata->card_readonly) + ret = host->platdata->card_readonly(mmc); + else + ret = 0; /* assume card is read-write */ + + return ret; } static void au1xmmc_finish_request(struct au1xmmc_host *host) @@ -163,7 +146,7 @@ static void au1xmmc_finish_request(struct au1xmmc_host *host) struct mmc_request *mrq = host->mrq; host->mrq = NULL; - host->flags &= HOST_F_ACTIVE; + host->flags &= HOST_F_ACTIVE | HOST_F_DMA; host->dma.len = 0; host->dma.dir = 0; @@ -174,8 +157,6 @@ static void au1xmmc_finish_request(struct au1xmmc_host *host) host->status = HOST_S_IDLE; - bcsr->disk_leds |= (1 << 8); - mmc_request_done(host->mmc, mrq); } @@ -299,11 +280,13 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) if (!data->error) { if (host->flags & HOST_F_DMA) { +#ifdef CONFIG_SOC_AU1200 /* DBDMA */ u32 chan = DMA_CHANNEL(host); chan_tab_t *c = *((chan_tab_t **) chan); au1x_dma_chan_t *cp = c->chan_ptr; data->bytes_xfered = cp->ddma_bytecnt; +#endif } else data->bytes_xfered = @@ -420,18 +403,18 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) break; if (status & SD_STATUS_RC) { - DBG("RX CRC Error [%d + %d].\n", host->id, + DBG("RX CRC Error [%d + %d].\n", host->pdev->id, host->pio.len, count); break; } if (status & SD_STATUS_RO) { - DBG("RX Overrun [%d + %d]\n", host->id, + DBG("RX Overrun [%d + %d]\n", host->pdev->id, host->pio.len, count); break; } else if (status & SD_STATUS_RU) { - DBG("RX Underrun [%d + %d]\n", host->id, + DBG("RX Underrun [%d + %d]\n", host->pdev->id, host->pio.len, count); break; } @@ -528,6 +511,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) host->status = HOST_S_DATA; if (host->flags & HOST_F_DMA) { +#ifdef CONFIG_SOC_AU1200 /* DBDMA */ u32 channel = DMA_CHANNEL(host); /* Start the DMA as soon as the buffer gets something in it */ @@ -540,6 +524,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) } au1xxx_dbdma_start(channel); +#endif } } @@ -571,12 +556,8 @@ static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) static int au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) { - int datalen = data->blocks * data->blksz; - if (dma != 0) - host->flags |= HOST_F_DMA; - if (data->flags & MMC_DATA_READ) host->flags |= HOST_F_RECV; else @@ -596,6 +577,7 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) au_writel(data->blksz - 1, HOST_BLKSIZE(host)); if (host->flags & HOST_F_DMA) { +#ifdef CONFIG_SOC_AU1200 /* DBDMA */ int i; u32 channel = DMA_CHANNEL(host); @@ -621,11 +603,12 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) len, flags); } - if (!ret) + if (!ret) goto dataerr; datalen -= len; } +#endif } else { host->pio.index = 0; @@ -641,8 +624,9 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) return 0; - dataerr: - dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir); +dataerr: + dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, + host->dma.dir); return -ETIMEDOUT; } @@ -663,8 +647,6 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) host->mrq = mrq; host->status = HOST_S_CMD; - bcsr->disk_leds &= ~(1 << 8); - if (mrq->data) { FLUSH_FIFO(host); flags = mrq->data->flags; @@ -728,149 +710,145 @@ static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios) } } -static void au1xmmc_dma_callback(int irq, void *dev_id) -{ - struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id; - - /* Avoid spurious interrupts */ - - if (!host->mrq) - return; - - if (host->flags & HOST_F_STOP) - SEND_STOP(host); - - tasklet_schedule(&host->data_task); -} - #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) #define STATUS_DATA_IN (SD_STATUS_NE) #define STATUS_DATA_OUT (SD_STATUS_TH) static irqreturn_t au1xmmc_irq(int irq, void *dev_id) { - + struct au1xmmc_host *host = dev_id; u32 status; - int i, ret = 0; - - disable_irq(AU1100_SD_IRQ); - for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { - struct au1xmmc_host * host = au1xmmc_hosts[i]; - u32 handled = 1; - - status = au_readl(HOST_STATUS(host)); + status = au_readl(HOST_STATUS(host)); - if (host->mrq && (status & STATUS_TIMEOUT)) { - if (status & SD_STATUS_RAT) - host->mrq->cmd->error = -ETIMEDOUT; + if (!(status & SD_STATUS_I)) + return IRQ_NONE; /* not ours */ - else if (status & SD_STATUS_DT) - host->mrq->data->error = -ETIMEDOUT; + if (host->mrq && (status & STATUS_TIMEOUT)) { + if (status & SD_STATUS_RAT) + host->mrq->cmd->error = -ETIMEDOUT; + else if (status & SD_STATUS_DT) + host->mrq->data->error = -ETIMEDOUT; - /* In PIO mode, interrupts might still be enabled */ - IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); + /* In PIO mode, interrupts might still be enabled */ + IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); - //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF); - tasklet_schedule(&host->finish_task); - } + /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */ + tasklet_schedule(&host->finish_task); + } #if 0 - else if (status & SD_STATUS_DD) { - - /* Sometimes we get a DD before a NE in PIO mode */ - - if (!(host->flags & HOST_F_DMA) && - (status & SD_STATUS_NE)) - au1xmmc_receive_pio(host); - else { - au1xmmc_data_complete(host, status); - //tasklet_schedule(&host->data_task); - } - } -#endif - else if (status & (SD_STATUS_CR)) { - if (host->status == HOST_S_CMD) - au1xmmc_cmd_complete(host,status); - } - else if (!(host->flags & HOST_F_DMA)) { - if ((host->flags & HOST_F_XMIT) && - (status & STATUS_DATA_OUT)) - au1xmmc_send_pio(host); - else if ((host->flags & HOST_F_RECV) && - (status & STATUS_DATA_IN)) - au1xmmc_receive_pio(host); - } - else if (status & 0x203FBC70) { - DBG("Unhandled status %8.8x\n", host->id, status); - handled = 0; + else if (status & SD_STATUS_DD) { + /* Sometimes we get a DD before a NE in PIO mode */ + if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE)) + au1xmmc_receive_pio(host); + else { + au1xmmc_data_complete(host, status); + /* tasklet_schedule(&host->data_task); */ } - - au_writel(status, HOST_STATUS(host)); - au_sync(); - - ret |= handled; } - - enable_irq(AU1100_SD_IRQ); - return ret; -} - -static void au1xmmc_poll_event(unsigned long arg) -{ - struct au1xmmc_host *host = (struct au1xmmc_host *) arg; - - int card = au1xmmc_card_inserted(host); - int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0; - - if (card != controller) { - host->flags &= ~HOST_F_ACTIVE; - if (card) host->flags |= HOST_F_ACTIVE; - mmc_detect_change(host->mmc, 0); +#endif + else if (status & SD_STATUS_CR) { + if (host->status == HOST_S_CMD) + au1xmmc_cmd_complete(host, status); + + } else if (!(host->flags & HOST_F_DMA)) { + if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT)) + au1xmmc_send_pio(host); + else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN)) + au1xmmc_receive_pio(host); + + } else if (status & 0x203F3C70) { + DBG("Unhandled status %8.8x\n", host->pdev->id, + status); } - if (host->mrq != NULL) { - u32 status = au_readl(HOST_STATUS(host)); - DBG("PENDING - %8.8x\n", host->id, status); - } + au_writel(status, HOST_STATUS(host)); + au_sync(); - mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT); + return IRQ_HANDLED; } -static dbdev_tab_t au1xmmc_mem_dbdev = -{ - DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0 +#ifdef CONFIG_SOC_AU1200 +/* 8bit memory DMA device */ +static dbdev_tab_t au1xmmc_mem_dbdev = { + .dev_id = DSCR_CMD0_ALWAYS, + .dev_flags = DEV_FLAGS_ANYUSE, + .dev_tsize = 0, + .dev_devwidth = 8, + .dev_physaddr = 0x00000000, + .dev_intlevel = 0, + .dev_intpolarity = 0, }; +static int memid; -static void au1xmmc_init_dma(struct au1xmmc_host *host) +static void au1xmmc_dbdma_callback(int irq, void *dev_id) { + struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id; - u32 rxchan, txchan; + /* Avoid spurious interrupts */ + if (!host->mrq) + return; - int txid = au1xmmc_card_table[host->id].tx_devid; - int rxid = au1xmmc_card_table[host->id].rx_devid; + if (host->flags & HOST_F_STOP) + SEND_STOP(host); - /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride - of 8 bits. And since devices are shared, we need to create - our own to avoid freaking out other devices - */ + tasklet_schedule(&host->data_task); +} - int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); +static int au1xmmc_dbdma_init(struct au1xmmc_host *host) +{ + struct resource *res; + int txid, rxid; + + res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0); + if (!res) + return -ENODEV; + txid = res->start; + + res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1); + if (!res) + return -ENODEV; + rxid = res->start; + + if (!memid) + return -ENODEV; + + host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid, + au1xmmc_dbdma_callback, (void *)host); + if (!host->tx_chan) { + dev_err(&host->pdev->dev, "cannot allocate TX DMA\n"); + return -ENODEV; + } + + host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid, + au1xmmc_dbdma_callback, (void *)host); + if (!host->rx_chan) { + dev_err(&host->pdev->dev, "cannot allocate RX DMA\n"); + au1xxx_dbdma_chan_free(host->tx_chan); + return -ENODEV; + } - txchan = au1xxx_dbdma_chan_alloc(memid, txid, - au1xmmc_dma_callback, (void *) host); + au1xxx_dbdma_set_devwidth(host->tx_chan, 8); + au1xxx_dbdma_set_devwidth(host->rx_chan, 8); - rxchan = au1xxx_dbdma_chan_alloc(rxid, memid, - au1xmmc_dma_callback, (void *) host); + au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT); + au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); - au1xxx_dbdma_set_devwidth(txchan, 8); - au1xxx_dbdma_set_devwidth(rxchan, 8); + /* DBDMA is good to go */ + host->flags |= HOST_F_DMA; - au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT); - au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT); + return 0; +} - host->tx_chan = txchan; - host->rx_chan = rxchan; +static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) +{ + if (host->flags & HOST_F_DMA) { + host->flags &= ~HOST_F_DMA; + au1xxx_dbdma_chan_free(host->tx_chan); + au1xxx_dbdma_chan_free(host->rx_chan); + } } +#endif static const struct mmc_host_ops au1xmmc_ops = { .request = au1xmmc_request, @@ -878,116 +856,235 @@ static const struct mmc_host_ops au1xmmc_ops = { .get_ro = au1xmmc_card_readonly, }; -static int __devinit au1xmmc_probe(struct platform_device *pdev) +static void au1xmmc_poll_event(unsigned long arg) { + struct au1xmmc_host *host = (struct au1xmmc_host *)arg; + int card = au1xmmc_card_inserted(host); + int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0; + + if (card != controller) { + host->flags &= ~HOST_F_ACTIVE; + if (card) + host->flags |= HOST_F_ACTIVE; + mmc_detect_change(host->mmc, 0); + } - int i, ret = 0; +#ifdef DEBUG + if (host->mrq != NULL) { + u32 status = au_readl(HOST_STATUS(host)); + DBG("PENDING - %8.8x\n", host->pdev->id, status); + } +#endif + mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT); +} - /* THe interrupt is shared among all controllers */ - ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, IRQF_DISABLED, "MMC", 0); +static void au1xmmc_init_cd_poll_timer(struct au1xmmc_host *host) +{ + init_timer(&host->timer); + host->timer.function = au1xmmc_poll_event; + host->timer.data = (unsigned long)host; + host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT; +} - if (ret) { - printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n", - AU1100_SD_IRQ, ret); - return -ENXIO; +static int __devinit au1xmmc_probe(struct platform_device *pdev) +{ + struct mmc_host *mmc; + struct au1xmmc_host *host; + struct resource *r; + int ret; + + mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); + if (!mmc) { + dev_err(&pdev->dev, "no memory for mmc_host\n"); + ret = -ENOMEM; + goto out0; } - disable_irq(AU1100_SD_IRQ); + host = mmc_priv(mmc); + host->mmc = mmc; + host->platdata = pdev->dev.platform_data; + host->pdev = pdev; - for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { - struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); - struct au1xmmc_host *host = 0; + ret = -ENODEV; + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no mmio defined\n"); + goto out1; + } - if (!mmc) { - printk(DRIVER_NAME "ERROR: no mem for host %d\n", i); - au1xmmc_hosts[i] = 0; - continue; - } + host->ioarea = request_mem_region(r->start, r->end - r->start + 1, + pdev->name); + if (!host->ioarea) { + dev_err(&pdev->dev, "mmio already in use\n"); + goto out1; + } - mmc->ops = &au1xmmc_ops; + host->iobase = (unsigned long)ioremap(r->start, 0x3c); + if (!host->iobase) { + dev_err(&pdev->dev, "cannot remap mmio\n"); + goto out2; + } + + r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!r) { + dev_err(&pdev->dev, "no IRQ defined\n"); + goto out3; + } - mmc->f_min = 450000; - mmc->f_max = 24000000; + host->irq = r->start; + /* IRQ is shared among both SD controllers */ + ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED, + DRIVER_NAME, host); + if (ret) { + dev_err(&pdev->dev, "cannot grab IRQ\n"); + goto out3; + } - mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; - mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; + mmc->ops = &au1xmmc_ops; - mmc->max_blk_size = 2048; - mmc->max_blk_count = 512; + mmc->f_min = 450000; + mmc->f_max = 24000000; - mmc->ocr_avail = AU1XMMC_OCR; + mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; + mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; - host = mmc_priv(mmc); - host->mmc = mmc; + mmc->max_blk_size = 2048; + mmc->max_blk_count = 512; - host->id = i; - host->iobase = au1xmmc_card_table[host->id].iobase; - host->clock = 0; - host->power_mode = MMC_POWER_OFF; + mmc->ocr_avail = AU1XMMC_OCR; + mmc->caps = 0; - host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0; - host->status = HOST_S_IDLE; + host->status = HOST_S_IDLE; - init_timer(&host->timer); + /* board-specific carddetect setup, if any */ + if (host->platdata && host->platdata->cd_setup) { + ret = host->platdata->cd_setup(mmc, 1); + if (ret) { + dev_err(&pdev->dev, "board CD setup failed\n"); + goto out4; + } + } else { + /* poll the board-specific is-card-in-socket-? method */ + au1xmmc_init_cd_poll_timer(host); + } - host->timer.function = au1xmmc_poll_event; - host->timer.data = (unsigned long) host; - host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT; + tasklet_init(&host->data_task, au1xmmc_tasklet_data, + (unsigned long)host); - tasklet_init(&host->data_task, au1xmmc_tasklet_data, - (unsigned long) host); + tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, + (unsigned long)host); - tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, - (unsigned long) host); +#ifdef CONFIG_SOC_AU1200 + ret = au1xmmc_dbdma_init(host); + if (ret) + printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n"); +#endif - spin_lock_init(&host->lock); +#ifdef CONFIG_LEDS_CLASS + if (host->platdata && host->platdata->led) { + struct led_classdev *led = host->platdata->led; + led->name = mmc_hostname(mmc); + led->brightness = LED_OFF; + led->default_trigger = mmc_hostname(mmc); + ret = led_classdev_register(mmc_dev(mmc), led); + if (ret) + goto out5; + } +#endif - if (dma != 0) - au1xmmc_init_dma(host); + au1xmmc_reset_controller(host); - au1xmmc_reset_controller(host); + ret = mmc_add_host(mmc); + if (ret) { + dev_err(&pdev->dev, "cannot add mmc host\n"); + goto out6; + } - mmc_add_host(mmc); - au1xmmc_hosts[i] = host; + platform_set_drvdata(pdev, mmc); + /* start the carddetect poll timer if necessary */ + if (!(host->platdata && host->platdata->cd_setup)) add_timer(&host->timer); - printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n", - host->id, host->iobase, dma ? "dma" : "pio"); - } + printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X" + " (mode=%s)\n", pdev->id, host->iobase, + host->flags & HOST_F_DMA ? "dma" : "pio"); - enable_irq(AU1100_SD_IRQ); + return 0; /* all ok */ - return 0; +out6: +#ifdef CONFIG_LEDS_CLASS + if (host->platdata && host->platdata->led) + led_classdev_unregister(host->platdata->led); +out5: +#endif + au_writel(0, HOST_ENABLE(host)); + au_writel(0, HOST_CONFIG(host)); + au_writel(0, HOST_CONFIG2(host)); + au_sync(); + +#ifdef CONFIG_SOC_AU1200 + au1xmmc_dbdma_shutdown(host); +#endif + + tasklet_kill(&host->data_task); + tasklet_kill(&host->finish_task); + + if (host->platdata && host->platdata->cd_setup) + host->platdata->cd_setup(mmc, 0); +out4: + free_irq(host->irq, host); +out3: + iounmap((void *)host->iobase); +out2: + release_resource(host->ioarea); + kfree(host->ioarea); +out1: + mmc_free_host(mmc); +out0: + return ret; } static int __devexit au1xmmc_remove(struct platform_device *pdev) { + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct au1xmmc_host *host; + + if (mmc) { + host = mmc_priv(mmc); + + mmc_remove_host(mmc); - int i; +#ifdef CONFIG_LEDS_CLASS + if (host->platdata && host->platdata->led) + led_classdev_unregister(host->platdata->led); +#endif - disable_irq(AU1100_SD_IRQ); + if (host->platdata && host->platdata->cd_setup) + host->platdata->cd_setup(mmc, 0); + else + del_timer_sync(&host->timer); - for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { - struct au1xmmc_host *host = au1xmmc_hosts[i]; - if (!host) continue; + au_writel(0, HOST_ENABLE(host)); + au_writel(0, HOST_CONFIG(host)); + au_writel(0, HOST_CONFIG2(host)); + au_sync(); tasklet_kill(&host->data_task); tasklet_kill(&host->finish_task); - del_timer_sync(&host->timer); +#ifdef CONFIG_SOC_AU1200 + au1xmmc_dbdma_shutdown(host); +#endif au1xmmc_set_power(host, 0); - mmc_remove_host(host->mmc); + free_irq(host->irq, host); + iounmap((void *)host->iobase); + release_resource(host->ioarea); + kfree(host->ioarea); - au1xxx_dbdma_chan_free(host->tx_chan); - au1xxx_dbdma_chan_free(host->rx_chan); - - au_writel(0x0, HOST_ENABLE(host)); - au_sync(); + mmc_free_host(mmc); } - - free_irq(AU1100_SD_IRQ, 0); return 0; } @@ -1004,21 +1101,31 @@ static struct platform_driver au1xmmc_driver = { static int __init au1xmmc_init(void) { +#ifdef CONFIG_SOC_AU1200 + /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride + * of 8 bits. And since devices are shared, we need to create + * our own to avoid freaking out other devices. + */ + memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); + if (!memid) + printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n"); +#endif return platform_driver_register(&au1xmmc_driver); } static void __exit au1xmmc_exit(void) { +#ifdef CONFIG_SOC_AU1200 + if (memid) + au1xxx_ddma_del_device(memid); +#endif platform_driver_unregister(&au1xmmc_driver); } module_init(au1xmmc_init); module_exit(au1xmmc_exit); -#ifdef MODULE MODULE_AUTHOR("Advanced Micro Devices, Inc"); MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:au1xxx-mmc"); -#endif - diff --git a/drivers/mmc/host/au1xmmc.h b/drivers/mmc/host/au1xmmc.h index 341cbdf..3b40065 100644 --- a/drivers/mmc/host/au1xmmc.h +++ b/drivers/mmc/host/au1xmmc.h @@ -49,8 +49,6 @@ struct au1xmmc_host { struct mmc_host *mmc; struct mmc_request *mrq; - u32 id; - u32 flags; u32 iobase; u32 clock; @@ -73,11 +71,14 @@ struct au1xmmc_host { u32 tx_chan; u32 rx_chan; + int irq; + struct timer_list timer; struct tasklet_struct finish_task; struct tasklet_struct data_task; - - spinlock_t lock; + struct au1xmmc_platform_data *platdata; + struct platform_device *pdev; + struct resource *ioarea; }; /* Status flags used by the host structure */ diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h index 9e0028f..c35e209 100644 --- a/include/asm-mips/mach-au1x00/au1100_mmc.h +++ b/include/asm-mips/mach-au1x00/au1100_mmc.h @@ -38,15 +38,15 @@ #ifndef __ASM_AU1100_MMC_H #define __ASM_AU1100_MMC_H - -#define NUM_AU1100_MMC_CONTROLLERS 2 - -#if defined(CONFIG_SOC_AU1100) -#define AU1100_SD_IRQ AU1100_SD_INT -#elif defined(CONFIG_SOC_AU1200) -#define AU1100_SD_IRQ AU1200_SD_INT -#endif - +#include + +struct au1xmmc_platform_data { + int(*cd_setup)(void *mmc_host, int on); + int(*card_inserted)(void *mmc_host); + int(*card_readonly)(void *mmc_host); + void(*set_power)(void *mmc_host, int state); + struct led_classdev *led; +}; #define SD0_BASE 0xB0600000 #define SD1_BASE 0xB0680000 -- 1.5.5.3 From mano@roarinelk.homelinux.net Mon Jun 9 07:37:04 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:37:06 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:9651 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20029939AbYFIGhE (ORCPT ); Mon, 9 Jun 2008 07:37:04 +0100 Received: (qmail 8840 invoked by uid 1000); 9 Jun 2008 08:37:02 +0200 Date: Mon, 9 Jun 2008 08:37:02 +0200 From: Manuel Lauss To: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: [PATCH 2/8] Alchemy: register mmc platform device for db1200/pb1200 boards. Message-ID: <20080609063702.GC8724@roarinelk.homelinux.net> References: <20080609063521.GA8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080609063521.GA8724@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19446 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips From 536f44d2947f3883016b927a621e30782bd3149f Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sat, 17 May 2008 17:48:02 +0200 Subject: [PATCH] Alchemy: register mmc platform device for db1200/pb1200 boards Add au1xmmc platform data for PB1200/DB1200 boards, and wire up the 2 SD controllers for them. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/platform.c | 99 +++++++++++++++++++++++++++--------- arch/mips/au1000/pb1200/platform.c | 81 +++++++++++++++++++++++++++++ 2 files changed, 156 insertions(+), 24 deletions(-) diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index 8cae775..c235434 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -16,6 +16,8 @@ #include #include +#include +#include #define PORT(_base, _irq) \ { \ @@ -162,24 +164,6 @@ static struct resource au1xxx_usb_gdt_resources[] = { }, }; -static struct resource au1xxx_mmc_resources[] = { - [0] = { - .start = SD0_PHYS_ADDR, - .end = SD0_PHYS_ADDR + 0x40, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SD1_PHYS_ADDR, - .end = SD1_PHYS_ADDR + 0x40, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - } -}; - static u64 udc_dmamask = ~(u32)0; static struct platform_device au1xxx_usb_gdt_device = { @@ -248,16 +232,80 @@ static struct platform_device au1200_lcd_device = { static u64 au1xxx_mmc_dmamask = ~(u32)0; -static struct platform_device au1xxx_mmc_device = { +extern struct au1xmmc_platform_data au1xmmc_platdata[2]; + +static struct resource au1200_mmc0_resources[] = { + [0] = { + .start = SD0_PHYS_ADDR, + .end = SD0_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX0, + .end = DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX0, + .end = DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device au1200_mmc0_device = { .name = "au1xxx-mmc", .id = 0, .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = 0xffffffff, + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &au1xmmc_platdata[0], }, - .num_resources = ARRAY_SIZE(au1xxx_mmc_resources), - .resource = au1xxx_mmc_resources, + .num_resources = ARRAY_SIZE(au1200_mmc0_resources), + .resource = au1200_mmc0_resources, }; + +#ifndef CONFIG_MIPS_DB1200 +static struct resource au1200_mmc1_resources[] = { + [0] = { + .start = SD1_PHYS_ADDR, + .end = SD1_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX1, + .end = DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX1, + .end = DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } +}; + + +static struct platform_device au1200_mmc1_device = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &au1xmmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au1200_mmc1_resources), + .resource = au1200_mmc1_resources, +}; +#endif /* #ifndef CONFIG_MIPS_DB1200 */ #endif /* #ifdef CONFIG_SOC_AU1200 */ static struct platform_device au1x00_pcmcia_device = { @@ -295,7 +343,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xxx_usb_gdt_device, &au1xxx_usb_otg_device, &au1200_lcd_device, - &au1xxx_mmc_device, + &au1200_mmc0_device, +#ifndef CONFIG_MIPS_DB1200 + &au1200_mmc1_device, +#endif #endif #ifdef SMBUS_PSC_BASE &pbdb_smbus_device, diff --git a/arch/mips/au1000/pb1200/platform.c b/arch/mips/au1000/pb1200/platform.c index 5930110..faf3d92 100644 --- a/arch/mips/au1000/pb1200/platform.c +++ b/arch/mips/au1000/pb1200/platform.c @@ -19,9 +19,90 @@ */ #include +#include #include #include +#include + +static int mmc_activity = 0; + +static void pb1200mmc0_set_power(void *mmc_host, int state) +{ + if (state) + bcsr->board |= BCSR_BOARD_SD0PWR; + else + bcsr->board &= ~BCSR_BOARD_SD0PWR; + + au_sync_delay(1); +} + +static int pb1200mmc0_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0; +} + +static int pb1200mmc0_card_inserted(void *mmc_host) +{ + return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0; +} + +static void pb1200_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) { + if (++mmc_activity == 1) + bcsr->disk_leds &= ~(1 << 8); + } else { + if (--mmc_activity == 0) + bcsr->disk_leds |= (1 << 8); + } +} + +static struct led_classdev pb1200mmc_led = { + .brightness_set = pb1200_mmcled_set, +}; + +#ifndef CONFIG_MIPS_DB1200 +static void pb1200mmc1_set_power(void *mmc_host, int state) +{ + if (state) + bcsr->board |= BCSR_BOARD_SD1PWR; + else + bcsr->board &= ~BCSR_BOARD_SD1PWR; + + au_sync_delay(1); +} + +static int pb1200mmc1_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0; +} + +static int pb1200mmc1_card_inserted(void *mmc_host) +{ + return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0; +} +#endif + +const struct au1xmmc_platform_data au1xmmc_platdata[2] = { + [0] = { + .set_power = pb1200mmc0_set_power, + .card_inserted = pb1200mmc0_card_inserted, + .card_readonly = pb1200mmc0_card_readonly, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &pb1200mmc_led, + }, +#ifndef CONFIG_MIPS_DB1200 + [1] = { + .set_power = pb1200mmc1_set_power, + .card_inserted = pb1200mmc1_card_inserted, + .card_readonly = pb1200mmc1_card_readonly, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &pb1200mmc_led, + }, +#endif +}; static struct resource ide_resources[] = { [0] = { -- 1.5.5.3 From mano@roarinelk.homelinux.net Mon Jun 9 07:37:36 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:37:39 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:51393 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20029940AbYFIGhg (ORCPT ); Mon, 9 Jun 2008 07:37:36 +0100 Received: (qmail 8854 invoked by uid 1000); 9 Jun 2008 08:37:33 +0200 Date: Mon, 9 Jun 2008 08:37:33 +0200 From: Manuel Lauss To: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: [PATCH 3/8] au1xmmc: enable 4 bit transfer mode Message-ID: <20080609063733.GD8724@roarinelk.homelinux.net> References: <20080609063521.GA8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080609063521.GA8724@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19447 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips From f05df3bb70a64b2996e2c8f1591be35a351959c2 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sat, 17 May 2008 17:53:57 +0200 Subject: [PATCH] au1xmmc: enable 4 bit transfer mode Signed-off-by: Manuel Lauss --- drivers/mmc/host/au1xmmc.c | 22 +++++++++++++++++----- 1 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index d8776d6..2bd4cf4 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -95,14 +95,13 @@ static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) static inline void SEND_STOP(struct au1xmmc_host *host) { - - /* We know the value of CONFIG2, so avoid a read we don't need */ - u32 mask = SD_CONFIG2_EN; + u32 config2; WARN_ON(host->status != HOST_S_DATA); host->status = HOST_S_STOP; - au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host)); + config2 = au_readl(HOST_CONFIG2(host)); + au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host)); au_sync(); /* Send the stop commmand */ @@ -697,6 +696,7 @@ static void au1xmmc_reset_controller(struct au1xmmc_host *host) static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios) { struct au1xmmc_host *host = mmc_priv(mmc); + u32 config2; if (ios->power_mode == MMC_POWER_OFF) au1xmmc_set_power(host, 0); @@ -708,6 +708,18 @@ static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios) au1xmmc_set_clock(host, ios->clock); host->clock = ios->clock; } + + config2 = au_readl(HOST_CONFIG2(host)); + switch (ios->bus_width) { + case MMC_BUS_WIDTH_4: + config2 |= SD_CONFIG2_WB; + break; + case MMC_BUS_WIDTH_1: + config2 &= ~SD_CONFIG2_WB; + break; + } + au_writel(config2, HOST_CONFIG2(host)); + au_sync(); } #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) @@ -952,7 +964,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev) mmc->max_blk_count = 512; mmc->ocr_avail = AU1XMMC_OCR; - mmc->caps = 0; + mmc->caps = MMC_CAP_4_BIT_DATA; host->status = HOST_S_IDLE; -- 1.5.5.3 From mano@roarinelk.homelinux.net Mon Jun 9 07:38:04 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:38:06 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:59370 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20029931AbYFIGiE (ORCPT ); Mon, 9 Jun 2008 07:38:04 +0100 Received: (qmail 8874 invoked by uid 1000); 9 Jun 2008 08:38:03 +0200 Date: Mon, 9 Jun 2008 08:38:03 +0200 From: Manuel Lauss To: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: [PATCH 4/8] au1xmmc: SDIO IRQ support. Message-ID: <20080609063803.GE8724@roarinelk.homelinux.net> References: <20080609063521.GA8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080609063521.GA8724@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19448 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips From e4bbe21c402e8cdd3a1536db36779f3cae6d47d8 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sat, 17 May 2008 17:58:52 +0200 Subject: [PATCH] au1xmmc: SDIO IRQ support Wire up the SD controllers' SDIO IRQ capability. Signed-off-by: Manuel Lauss --- drivers/mmc/host/au1xmmc.c | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index 2bd4cf4..16b5640 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -736,6 +736,9 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id) if (!(status & SD_STATUS_I)) return IRQ_NONE; /* not ours */ + if (status & SD_STATUS_SI) /* SDIO */ + mmc_signal_sdio_irq(host->mmc); + if (host->mrq && (status & STATUS_TIMEOUT)) { if (status & SD_STATUS_RAT) host->mrq->cmd->error = -ETIMEDOUT; @@ -862,10 +865,21 @@ static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) } #endif +static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en) +{ + struct au1xmmc_host *host = mmc_priv(mmc); + + if (en) + IRQ_ON(host, SD_CONFIG_SI); + else + IRQ_OFF(host, SD_CONFIG_SI); +} + static const struct mmc_host_ops au1xmmc_ops = { .request = au1xmmc_request, .set_ios = au1xmmc_set_ios, .get_ro = au1xmmc_card_readonly, + .enable_sdio_irq = au1xmmc_enable_sdio_irq, }; static void au1xmmc_poll_event(unsigned long arg) @@ -964,7 +978,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev) mmc->max_blk_count = 512; mmc->ocr_avail = AU1XMMC_OCR; - mmc->caps = MMC_CAP_4_BIT_DATA; + mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; host->status = HOST_S_IDLE; -- 1.5.5.3 From mano@roarinelk.homelinux.net Mon Jun 9 07:38:36 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:38:39 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:57493 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20029933AbYFIGig (ORCPT ); Mon, 9 Jun 2008 07:38:36 +0100 Received: (qmail 8896 invoked by uid 1000); 9 Jun 2008 08:38:35 +0200 Date: Mon, 9 Jun 2008 08:38:35 +0200 From: Manuel Lauss To: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: [PATCH 5/8] au1xmmc: codingstyle tidying. Message-ID: <20080609063835.GF8724@roarinelk.homelinux.net> References: <20080609063521.GA8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080609063521.GA8724@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19449 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips From 629e26106e6fc0b653012e7229e3abd0bce554b2 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sat, 17 May 2008 18:30:00 +0200 Subject: [PATCH] au1xmmc: codingstyle tidying Clean up the codebase, no functional changes. - merge the au1xmmc.h header contents into the driver file, - indentation, spelling and style fixes. Signed-off-by: Manuel Lauss --- drivers/mmc/host/au1xmmc.c | 233 ++++++++++++++++++++++++++----------------- drivers/mmc/host/au1xmmc.h | 97 ------------------ 2 files changed, 141 insertions(+), 189 deletions(-) delete mode 100644 drivers/mmc/host/au1xmmc.h diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index 16b5640..fcbaf40 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -49,20 +49,104 @@ #include #include -#include -#include "au1xmmc.h" - #define DRIVER_NAME "au1xxx-mmc" /* Set this to enable special debugging macros */ /* #define DEBUG */ #ifdef DEBUG -#define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args) +#define DBG(fmt, idx, args...) \ + printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args) #else -#define DBG(fmt, idx, args...) +#define DBG(fmt, idx, args...) do {} while (0) #endif +/* Hardware definitions */ +#define AU1XMMC_DESCRIPTOR_COUNT 1 +#define AU1XMMC_DESCRIPTOR_SIZE 2048 + +#define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ + MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ + MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) + +/* This gives us a hard value for the stop command that we can write directly + * to the command register. + */ +#define STOP_CMD \ + (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO) + +/* This is the set of interrupts that we configure by default. */ +#define AU1XMMC_INTERRUPTS \ + (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \ + SD_CONFIG_CR | SD_CONFIG_I) + +/* The poll event (looking for insert/remove events runs twice a second. */ +#define AU1XMMC_DETECT_TIMEOUT (HZ/2) + +struct au1xmmc_host { + struct mmc_host *mmc; + struct mmc_request *mrq; + + u32 flags; + u32 iobase; + u32 clock; + u32 bus_width; + u32 power_mode; + + int status; + + struct { + int len; + int dir; + } dma; + + struct { + int index; + int offset; + int len; + } pio; + + u32 tx_chan; + u32 rx_chan; + + int irq; + + struct timer_list timer; + struct tasklet_struct finish_task; + struct tasklet_struct data_task; + struct au1xmmc_platform_data *platdata; + struct platform_device *pdev; + struct resource *ioarea; +}; + +/* Status flags used by the host structure */ +#define HOST_F_XMIT 0x0001 +#define HOST_F_RECV 0x0002 +#define HOST_F_DMA 0x0010 +#define HOST_F_ACTIVE 0x0100 +#define HOST_F_STOP 0x1000 + +#define HOST_S_IDLE 0x0001 +#define HOST_S_CMD 0x0002 +#define HOST_S_DATA 0x0003 +#define HOST_S_STOP 0x0004 + +/* Easy access macros */ +#define HOST_STATUS(h) ((h)->iobase + SD_STATUS) +#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) +#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) +#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) +#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) +#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) +#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) +#define HOST_CMD(h) ((h)->iobase + SD_CMD) +#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) +#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) +#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) + +#define DMA_CHANNEL(h) \ + (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) + static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) { u32 val = au_readl(HOST_CONFIG(host)); @@ -141,7 +225,6 @@ static int au1xmmc_card_readonly(struct mmc_host *mmc) static void au1xmmc_finish_request(struct au1xmmc_host *host) { - struct mmc_request *mrq = host->mrq; host->mrq = NULL; @@ -215,18 +298,14 @@ static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, au_sync(); /* Wait for the command to go on the line */ - - while(1) { - if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO)) - break; - } + while (au_readl(HOST_CMD(host)) & SD_CMD_GO) + /* nop */; /* Wait for the command to come back */ - if (wait) { u32 status = au_readl(HOST_STATUS(host)); - while(!(status & SD_STATUS_CR)) + while (!(status & SD_STATUS_CR)) status = au_readl(HOST_STATUS(host)); /* Clear the CR status */ @@ -240,12 +319,11 @@ static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) { - struct mmc_request *mrq = host->mrq; struct mmc_data *data; u32 crc; - WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP); + WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP)); if (host->mrq == NULL) return; @@ -256,15 +334,13 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) status = au_readl(HOST_STATUS(host)); /* The transaction is really over when the SD_STATUS_DB bit is clear */ - - while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) + while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) status = au_readl(HOST_STATUS(host)); data->error = 0; dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); /* Process any errors */ - crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); if (host->flags & HOST_F_XMIT) crc |= ((status & 0x07) == 0x02) ? 0 : 1; @@ -282,15 +358,13 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) #ifdef CONFIG_SOC_AU1200 /* DBDMA */ u32 chan = DMA_CHANNEL(host); - chan_tab_t *c = *((chan_tab_t **) chan); + chan_tab_t *c = *((chan_tab_t **)chan); au1x_dma_chan_t *cp = c->chan_ptr; data->bytes_xfered = cp->ddma_bytecnt; #endif - } - else + } else data->bytes_xfered = - (data->blocks * data->blksz) - - host->pio.len; + (data->blocks * data->blksz) - host->pio.len; } au1xmmc_finish_request(host); @@ -298,7 +372,7 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) static void au1xmmc_tasklet_data(unsigned long param) { - struct au1xmmc_host *host = (struct au1xmmc_host *) param; + struct au1xmmc_host *host = (struct au1xmmc_host *)param; u32 status = au_readl(HOST_STATUS(host)); au1xmmc_data_complete(host, status); @@ -308,11 +382,10 @@ static void au1xmmc_tasklet_data(unsigned long param) static void au1xmmc_send_pio(struct au1xmmc_host *host) { - - struct mmc_data *data = 0; - int sg_len, max, count = 0; - unsigned char *sg_ptr; - u32 status = 0; + struct mmc_data *data; + int sg_len, max, count; + unsigned char *sg_ptr, val; + u32 status; struct scatterlist *sg; data = host->mrq->data; @@ -327,14 +400,12 @@ static void au1xmmc_send_pio(struct au1xmmc_host *host) /* This is the space left inside the buffer */ sg_len = data->sg[host->pio.index].length - host->pio.offset; - /* Check to if we need less then the size of the sg_buffer */ - + /* Check if we need less than the size of the sg_buffer */ max = (sg_len > host->pio.len) ? host->pio.len : sg_len; - if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER; - - for(count = 0; count < max; count++ ) { - unsigned char val; + if (max > AU1XMMC_MAX_TRANSFER) + max = AU1XMMC_MAX_TRANSFER; + for (count = 0; count < max; count++) { status = au_readl(HOST_STATUS(host)); if (!(status & SD_STATUS_TH)) @@ -342,7 +413,7 @@ static void au1xmmc_send_pio(struct au1xmmc_host *host) val = *sg_ptr++; - au_writel((unsigned long) val, HOST_TXPORT(host)); + au_writel((unsigned long)val, HOST_TXPORT(host)); au_sync(); } @@ -366,11 +437,10 @@ static void au1xmmc_send_pio(struct au1xmmc_host *host) static void au1xmmc_receive_pio(struct au1xmmc_host *host) { - - struct mmc_data *data = 0; - int sg_len = 0, max = 0, count = 0; - unsigned char *sg_ptr = 0; - u32 status = 0; + struct mmc_data *data; + int max, count, sg_len = 0; + unsigned char *sg_ptr = NULL; + u32 status, val; struct scatterlist *sg; data = host->mrq->data; @@ -387,15 +457,15 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) /* This is the space left inside the buffer */ sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset; - /* Check to if we need less then the size of the sg_buffer */ - if (sg_len < max) max = sg_len; + /* Check if we need less than the size of the sg_buffer */ + if (sg_len < max) + max = sg_len; } if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER; - for(count = 0; count < max; count++ ) { - u32 val; + for (count = 0; count < max; count++) { status = au_readl(HOST_STATUS(host)); if (!(status & SD_STATUS_NE)) @@ -421,7 +491,7 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) val = au_readl(HOST_RXPORT(host)); if (sg_ptr) - *sg_ptr++ = (unsigned char) (val & 0xFF); + *sg_ptr++ = (unsigned char)(val & 0xFF); } host->pio.len -= count; @@ -433,7 +503,7 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) } if (host->pio.len == 0) { - //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); + /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */ IRQ_OFF(host, SD_CONFIG_NE); if (host->flags & HOST_F_STOP) @@ -443,17 +513,15 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) } } -/* static void au1xmmc_cmd_complete - This is called when a command has been completed - grab the response - and check for errors. Then start the data transfer if it is indicated. -*/ - +/* This is called when a command has been completed - grab the response + * and check for errors. Then start the data transfer if it is indicated. + */ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) { - struct mmc_request *mrq = host->mrq; struct mmc_command *cmd; - int trans; + u32 r[4]; + int i, trans; if (!host->mrq) return; @@ -463,9 +531,6 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) if (cmd->flags & MMC_RSP_PRESENT) { if (cmd->flags & MMC_RSP_136) { - u32 r[4]; - int i; - r[0] = au_readl(host->iobase + SD_RESP3); r[1] = au_readl(host->iobase + SD_RESP2); r[2] = au_readl(host->iobase + SD_RESP1); @@ -473,10 +538,9 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) /* The CRC is omitted from the response, so really * we only got 120 bytes, but the engine expects - * 128 bits, so we have to shift things up + * 128 bits, so we have to shift things up. */ - - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8; if (i != 3) cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; @@ -487,22 +551,20 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) * our response omits the CRC, our data ends up * being shifted 8 bits to the right. In this case, * that means that the OSR data starts at bit 31, - * so we can just read RESP0 and return that + * so we can just read RESP0 and return that. */ cmd->resp[0] = au_readl(host->iobase + SD_RESP0); } } /* Figure out errors */ - if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC)) cmd->error = -EILSEQ; trans = host->flags & (HOST_F_XMIT | HOST_F_RECV); if (!trans || cmd->error) { - - IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF); + IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); tasklet_schedule(&host->finish_task); return; } @@ -529,18 +591,15 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) { - unsigned int pbus = get_au1x00_speed(); unsigned int divisor; u32 config; /* From databook: - divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1 - */ - + * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1 + */ pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2); pbus /= 2; - divisor = ((pbus / rate) / 2) - 1; config = au_readl(HOST_CONFIG(host)); @@ -552,8 +611,8 @@ static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) au_sync(); } -static int -au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) +static int au1xmmc_prepare_data(struct au1xmmc_host *host, + struct mmc_data *data) { int datalen = data->blocks * data->blksz; @@ -582,7 +641,7 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) au1xxx_dbdma_stop(channel); - for(i = 0; i < host->dma.len; i++) { + for (i = 0; i < host->dma.len; i++) { u32 ret = 0, flags = DDMA_FLAGS_NOIE; struct scatterlist *sg = &data->sg[i]; int sg_len = sg->length; @@ -592,14 +651,12 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) if (i == host->dma.len - 1) flags = DDMA_FLAGS_IE; - if (host->flags & HOST_F_XMIT){ - ret = au1xxx_dbdma_put_source_flags(channel, - (void *) sg_virt(sg), len, flags); - } - else { - ret = au1xxx_dbdma_put_dest_flags(channel, - (void *) sg_virt(sg), - len, flags); + if (host->flags & HOST_F_XMIT) { + ret = au1xxx_dbdma_put_source_flags(channel, + (void *)sg_virt(sg), len, flags); + } else { + ret = au1xxx_dbdma_put_dest_flags(channel, + (void *)sg_virt(sg), len, flags); } if (!ret) @@ -608,8 +665,7 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) datalen -= len; } #endif - } - else { + } else { host->pio.index = 0; host->pio.offset = 0; host->pio.len = datalen; @@ -618,7 +674,7 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) IRQ_ON(host, SD_CONFIG_TH); else IRQ_ON(host, SD_CONFIG_NE); - //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF); + /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */ } return 0; @@ -629,15 +685,10 @@ dataerr: return -ETIMEDOUT; } -/* static void au1xmmc_request - This actually starts a command or data transaction -*/ - +/* This actually starts a command or data transaction */ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) { - struct au1xmmc_host *host = mmc_priv(mmc); - unsigned int flags = 0; int ret = 0; WARN_ON(irqs_disabled()); @@ -648,7 +699,6 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) if (mrq->data) { FLUSH_FIFO(host); - flags = mrq->data->flags; ret = au1xmmc_prepare_data(host, mrq->data); } @@ -663,7 +713,6 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) static void au1xmmc_reset_controller(struct au1xmmc_host *host) { - /* Apply the clock */ au_writel(SD_ENABLE_CE, HOST_ENABLE(host)); au_sync_delay(1); @@ -693,7 +742,7 @@ static void au1xmmc_reset_controller(struct au1xmmc_host *host) } -static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios) +static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct au1xmmc_host *host = mmc_priv(mmc); u32 config2; diff --git a/drivers/mmc/host/au1xmmc.h b/drivers/mmc/host/au1xmmc.h deleted file mode 100644 index 3b40065..0000000 --- a/drivers/mmc/host/au1xmmc.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef _AU1XMMC_H_ -#define _AU1XMMC_H_ - -/* Hardware definitions */ - -#define AU1XMMC_DESCRIPTOR_COUNT 1 -#define AU1XMMC_DESCRIPTOR_SIZE 2048 - -#define AU1XMMC_OCR ( MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ - MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ - MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) - -/* Easy access macros */ - -#define HOST_STATUS(h) ((h)->iobase + SD_STATUS) -#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) -#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) -#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) -#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) -#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) -#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) -#define HOST_CMD(h) ((h)->iobase + SD_CMD) -#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) -#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) -#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) - -#define DMA_CHANNEL(h) \ - ( ((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) - -/* This gives us a hard value for the stop command that we can write directly - * to the command register - */ - -#define STOP_CMD (SD_CMD_RT_1B|SD_CMD_CT_7|(0xC << SD_CMD_CI_SHIFT)|SD_CMD_GO) - -/* This is the set of interrupts that we configure by default */ - -#if 0 -#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_DD | \ - SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I) -#endif - -#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | \ - SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I) -/* The poll event (looking for insert/remove events runs twice a second */ -#define AU1XMMC_DETECT_TIMEOUT (HZ/2) - -struct au1xmmc_host { - struct mmc_host *mmc; - struct mmc_request *mrq; - - u32 flags; - u32 iobase; - u32 clock; - u32 bus_width; - u32 power_mode; - - int status; - - struct { - int len; - int dir; - } dma; - - struct { - int index; - int offset; - int len; - } pio; - - u32 tx_chan; - u32 rx_chan; - - int irq; - - struct timer_list timer; - struct tasklet_struct finish_task; - struct tasklet_struct data_task; - struct au1xmmc_platform_data *platdata; - struct platform_device *pdev; - struct resource *ioarea; -}; - -/* Status flags used by the host structure */ - -#define HOST_F_XMIT 0x0001 -#define HOST_F_RECV 0x0002 -#define HOST_F_DMA 0x0010 -#define HOST_F_ACTIVE 0x0100 -#define HOST_F_STOP 0x1000 - -#define HOST_S_IDLE 0x0001 -#define HOST_S_CMD 0x0002 -#define HOST_S_DATA 0x0003 -#define HOST_S_STOP 0x0004 - -#endif -- 1.5.5.3 From mano@roarinelk.homelinux.net Mon Jun 9 07:39:12 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:39:14 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:57539 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20029937AbYFIGjM (ORCPT ); Mon, 9 Jun 2008 07:39:12 +0100 Received: (qmail 8914 invoked by uid 1000); 9 Jun 2008 08:39:11 +0200 Date: Mon, 9 Jun 2008 08:39:11 +0200 From: Manuel Lauss To: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: [PATCH 6/8] au1xmmc: abort requests early if no card is present. Message-ID: <20080609063911.GG8724@roarinelk.homelinux.net> References: <20080609063521.GA8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080609063521.GA8724@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19450 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips From a478fbe20735b832696ba4cc0d3d21eb7371e689 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 18 May 2008 15:52:43 +0200 Subject: [PATCH] au1xmmc: abort requests early if no card is present Don't process an MMC request if no card is present. Signed-off-by: Manuel Lauss --- drivers/mmc/host/au1xmmc.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index fcbaf40..718eb87 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -697,6 +697,13 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) host->mrq = mrq; host->status = HOST_S_CMD; + /* fail request immediately if no card is present */ + if (0 == au1xmmc_card_inserted(host)) { + mrq->cmd->error = -ENOMEDIUM; + au1xmmc_finish_request(host); + return; + } + if (mrq->data) { FLUSH_FIFO(host); ret = au1xmmc_prepare_data(host, mrq->data); -- 1.5.5.3 From mano@roarinelk.homelinux.net Mon Jun 9 07:39:59 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:40:01 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:29384 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20029933AbYFIGj7 (ORCPT ); Mon, 9 Jun 2008 07:39:59 +0100 Received: (qmail 8932 invoked by uid 1000); 9 Jun 2008 08:39:58 +0200 Date: Mon, 9 Jun 2008 08:39:58 +0200 From: Manuel Lauss To: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: [PATCH 7/8] Alchemy: remove unused MMC macros from db1x00 header. Message-ID: <20080609063958.GH8724@roarinelk.homelinux.net> References: <20080609063521.GA8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080609063521.GA8724@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19451 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips From c637a7ed8d8d3cf845aca7775923df1076e06b8d Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 21 May 2008 15:13:51 +0200 Subject: [PATCH] Alchemy: remove unused MMC macros from db1x00 header. Signed-off-by: Manuel Lauss --- include/asm-mips/mach-db1x00/db1x00.h | 45 --------------------------------- 1 files changed, 0 insertions(+), 45 deletions(-) diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h index 612ae90..1a515b8 100644 --- a/include/asm-mips/mach-db1x00/db1x00.h +++ b/include/asm-mips/mach-db1x00/db1x00.h @@ -146,51 +146,6 @@ typedef volatile struct ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) /* - * SD controller macros - */ - -/* Detect card. */ -#define mmc_card_inserted(_n_, _res_) \ - do { \ - BCSR * const bcsr = (BCSR *)0xAE000000; \ - unsigned long mmc_wp, board_specific; \ - if ((_n_)) { \ - mmc_wp = BCSR_BOARD_SD1_WP; \ - } else { \ - mmc_wp = BCSR_BOARD_SD0_WP; \ - } \ - board_specific = au_readl((unsigned long)(&bcsr->specific)); \ - if (!(board_specific & mmc_wp)) {/* low means card present */ \ - *(int *)(_res_) = 1; \ - } else { \ - *(int *)(_res_) = 0; \ - } \ - } while (0) - -/* - * Apply power to card slot(s). - */ -#define mmc_power_on(_n_) \ - do { \ - BCSR * const bcsr = (BCSR *)0xAE000000; \ - unsigned long mmc_pwr, mmc_wp, board_specific; \ - if ((_n_)) { \ - mmc_pwr = BCSR_BOARD_SD1_PWR; \ - mmc_wp = BCSR_BOARD_SD1_WP; \ - } else { \ - mmc_pwr = BCSR_BOARD_SD0_PWR; \ - mmc_wp = BCSR_BOARD_SD0_WP; \ - } \ - board_specific = au_readl((unsigned long)(&bcsr->specific)); \ - if (!(board_specific & mmc_wp)) {/* low means card present */ \ - board_specific |= mmc_pwr; \ - au_writel(board_specific, (int)(&bcsr->specific)); \ - au_sync(); \ - } \ - } while (0) - - -/* * NAND defines * * Timing values as described in databook, * ns value stripped of the -- 1.5.5.3 From mano@roarinelk.homelinux.net Mon Jun 9 07:40:36 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:40:39 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:36277 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20029937AbYFIGkg (ORCPT ); Mon, 9 Jun 2008 07:40:36 +0100 Received: (qmail 8958 invoked by uid 1000); 9 Jun 2008 08:40:35 +0200 Date: Mon, 9 Jun 2008 08:40:35 +0200 From: Manuel Lauss To: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: [PATCH 8/8] au1xmmc: new maintainer. Message-ID: <20080609064035.GI8724@roarinelk.homelinux.net> References: <20080609063521.GA8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080609063521.GA8724@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19452 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips From dbed5b9f5b1107ed77f4e577486f1fd1131ad0a4 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Fri, 6 Jun 2008 20:31:20 +0200 Subject: [PATCH] au1xmmc: new maintainer Signed-off-by: Manuel Lauss --- MAINTAINERS | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 99f5665..b9e3b0d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -348,7 +348,9 @@ W: http://www.linux-usb.org/SpeedTouch/ S: Maintained ALCHEMY AU1XX0 MMC DRIVER -S: Orphan +P: Manuel Lauss +M: manuel.lauss@gmail.com +S: Maintained ALI1563 I2C DRIVER P: Rudolf Marek -- 1.5.5.3 From geert@linux-m68k.org Mon Jun 9 07:40:58 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 07:41:01 +0100 (BST) Received: from monty.telenet-ops.be ([195.130.132.56]:2432 "EHLO monty.telenet-ops.be") by ftp.linux-mips.org with ESMTP id S20029952AbYFIGk6 (ORCPT ); Mon, 9 Jun 2008 07:40:58 +0100 Received: from localhost (localhost.localdomain [127.0.0.1]) by monty.telenet-ops.be (Postfix) with SMTP id E2C5454012; Mon, 9 Jun 2008 08:40:57 +0200 (CEST) Received: from anakin.of.borg (78-21-204-88.access.telenet.be [78.21.204.88]) by monty.telenet-ops.be (Postfix) with ESMTP id D51E254022; Mon, 9 Jun 2008 08:40:57 +0200 (CEST) Received: from anakin.of.borg (localhost [127.0.0.1]) by anakin.of.borg (8.14.3/8.14.3/Debian-4) with ESMTP id m596evtr021336 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 9 Jun 2008 08:40:57 +0200 Received: from localhost (geert@localhost) by anakin.of.borg (8.14.3/8.14.3/Submit) with ESMTP id m596evjw021333; Mon, 9 Jun 2008 08:40:57 +0200 X-Authentication-Warning: anakin.of.borg: geert owned process doing -bs Date: Mon, 9 Jun 2008 08:40:57 +0200 (CEST) From: Geert Uytterhoeven To: Luke -Jr cc: "Maciej W. Rozycki" , linux-kernel , linux-mips@linux-mips.org Subject: Re: bcm33xx port In-Reply-To: <200806081836.42351.luke@dashjr.org> Message-ID: References: <200806072113.26433.luke@dashjr.org> <200806081527.31221.luke@dashjr.org> <200806081836.42351.luke@dashjr.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19453 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips On Sun, 8 Jun 2008, Luke -Jr wrote: > On Sunday 08 June 2008, Maciej W. Rozycki wrote: > > On Sun, 8 Jun 2008, Luke -Jr wrote: > > > > Not exactly. Try harder -- this is simple arithmetic and you've got > > > > all the data given above already. :) > > > > > > 200 / 2? I'm not really sure what a 'jiffy' is.. > > > > Hmm, I have thought it can be inferred from the code involved or failing > > that -- Google... Well, anyway, a jiffy is a tick of the kernel timer or, > > specifically in this context and to be more precise, the interval between > > such two consecutive ticks or, in other words, 1/HZ. ^^ Look at CONFIG_HZ, which is probably 100, 250, or 1000. > jiffy = 1 / 200000 HZ = 0.000005 sec/tick > loop = 200000 instructions / 2 instructions per loop = 100000 loops/sec > > So 0.00000000005 loops per jiffy? But it can't be, since loops_per_jiffy isn't > floating point... :/ So loops_per_jiffie is approx. CPU clock frequency / CONFIG_HZ. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From blf.ireland@gmail.com Mon Jun 9 11:55:46 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 11:55:57 +0100 (BST) Received: from rv-out-0708.google.com ([209.85.198.247]:60996 "EHLO rv-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S20030630AbYFIKzq (ORCPT ); Mon, 9 Jun 2008 11:55:46 +0100 Received: by rv-out-0708.google.com with SMTP id c5so1802838rvf.24 for ; Mon, 09 Jun 2008 03:55:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:sender :to:subject:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:references :x-google-sender-auth; bh=XOPG5A/bSu1RJWacPMEuPOJIwb78JOk8i5M1j+y+a5o=; b=ZSE6h1O2pNlVqCcGujnxydfjFmxkSo24dJiGGvx+gYS+kxF2ezpaAHv4qyX2Ve6o+A EOwSR0X48jQSCvIpIzoIlTs6RHt7AiU6IQGaj36eaxE2htj0TQBVBLXi21Twg/iZVV8O ZXml32pTbUFxVOVwmy9K1/1qgeYjXntwABRCg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:sender:to:subject:in-reply-to:mime-version :content-type:content-transfer-encoding:content-disposition :references:x-google-sender-auth; b=jXtIupBsYfG1abALmwrQgnie5F+hG0PhqS4Ml6eXMius44875sZ3cx9UvbpxyW1zHM GXWlaJoCxnZjd4MUP/d/7tgtuG3wIGMZm+d5N0/shuhjONJUJKDyM+5GcRKiklMtvoxL H6q9Kp262F52tcf9hnHOQEHfP2WnpAdmmXte8= Received: by 10.140.208.17 with SMTP id f17mr1952198rvg.218.1213008943333; Mon, 09 Jun 2008 03:55:43 -0700 (PDT) Received: by 10.141.197.19 with HTTP; Mon, 9 Jun 2008 03:55:43 -0700 (PDT) Message-ID: Date: Mon, 9 Jun 2008 12:55:43 +0200 From: "Brian Foster" To: linux-mips@linux-mips.org Subject: Adding(?) XI support to MIPS-Linux? In-Reply-To: <200806091050.m59AoUUl014012@smtp02.msg.oleane.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <200806091050.m59AoUUl014012@smtp02.msg.oleane.net> X-Google-Sender-Auth: 9fd0313f4c586b60 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19454 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips Hello, The MIPS 4KSd core (at least) implements an XI (eXecute Inhibit) page protection bit. XI is similar to the NX (No Execute) bit in the more recent AMD/Intel x86 families: Attempts to I-fetch from a page with XI set cause an exception. I've been asked to look into the possibility/difficulty of adding support for XI to MIPS-Linux (at least for the 4KSd core), for both kernel-mode and user-land. An admittedly very quick check of 2.6.25(-ish) suggests there is no support at all, at present, for XI for any MIPS core/configuration. Nor has a search of the 'Net found much of anything, with the possible exception of the PaX and grsecurity projects. Of course, I don't want to repeat work which has already been done. Has anyone studied adding, or better yet, already (tried to?) added, any support for XI? *Speculating*, and with the caveat I'm not completely up on MIPS TLB/memory-management/caches, I don't see kernel-mode as too much of an issue. There's no (known to me) cases of code-in-data/stack? Whilst I know bugger-all about module loading/unloading, I rather doubt there's anything too tricky going on there? User-land is clearly more difficult due to the `sigreturn' and FPU emulation trampolines, which reside in user-land stack. At the moment I am presuming a `vsyscall'-page scheme solves that problem, but have not researched the issue (esp. the FPU emulation) closely. A `vsyscall' which just contains the trampolines doesn't sound too difficult; but if you add to that (which I am NOT proposing!) the optimization of volatile time-of-day data (RO to user-land, RW to kernel-mode), then there would seem to be issues/gotchas with MIPS caching and/or page-protection? Does `gcc' for MIPS generate any trampolines in the stack/data? I keep seeing hints that `gcc' does in certain unspecified cases and/or architectures, but am at a lost just what is being talked about. Wikipedia suggests this only happens in (some?) cases of nested functions; as such, for C, they don't seem necessary and my initial inclination is say "don't use 'em!". I'm hoping to be able to avoid any support at all for executable stacks: I want all user-land code to have XI-set stacks. This is partly for simplicity (I presume), but also because the target is the the "secure" embedded world, where simply being able to assert you cannot, never, execute code in the stack (or in data) is much easier to pass muster with various certification authorities and testing laboratories. (PCI-PED is the area of immediate interest here.) I'm aware mprotect(2), at the least, is an issue, because it can be used to set a page to be both writable and executable. (Hence, more generally, I want to be able to assert that no memory with the exception of kseg0/kseg1, is ever concurrently writable and executable.) Advice, suggestions, pointers, comments are very welcome. cheers! -blf- -- "How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools." | http://www.stopesso.com From huacai.chen@intel.com Mon Jun 9 12:16:04 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 12:16:06 +0100 (BST) Received: from mga11.intel.com ([192.55.52.93]:63881 "EHLO mga11.intel.com") by ftp.linux-mips.org with ESMTP id S20030705AbYFILQE convert rfc822-to-8bit (ORCPT ); Mon, 9 Jun 2008 12:16:04 +0100 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 09 Jun 2008 04:15:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.27,612,1204531200"; d="scan'208";a="337992158" Received: from fmsmsx333.amr.corp.intel.com ([132.233.42.2]) by fmsmga002.fm.intel.com with ESMTP; 09 Jun 2008 04:13:55 -0700 Received: from pdsmsx414.ccr.corp.intel.com ([172.16.12.95]) by fmsmsx333.amr.corp.intel.com with Microsoft SMTPSVC(6.0.3790.1830); Mon, 9 Jun 2008 04:15:57 -0700 Received: from pdsmsx415.ccr.corp.intel.com ([172.16.12.184]) by pdsmsx414.ccr.corp.intel.com with Microsoft SMTPSVC(6.0.3790.1830); Mon, 9 Jun 2008 19:15:54 +0800 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT X-MimeOLE: Produced By Microsoft Exchange V6.5 Subject: [patch]modify the MIPS CPU classfication Date: Mon, 9 Jun 2008 19:15:58 +0800 Message-ID: <42DFA526FC41B1429CE7279EF83C6BDC01404341@pdsmsx415.ccr.corp.intel.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [patch]modify the MIPS CPU classfication Thread-Index: AcjKIjEbexxBO5k+To62Keu79ukJrg== From: "Chen, Huacai" To: , X-OriginalArrivalTime: 09 Jun 2008 11:15:54.0822 (UTC) FILETIME=[2F1D7E60:01C8CA22] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19455 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: huacai.chen@intel.com Precedence: bulk X-list: linux-mips The company ID of Loongson1/Loongson2 is PRID_COMP_LEGACY, but they were classified in the list whoes company ID is PRID_COMP_MIPS. This patch move them to the right place. Signed-off-by: Huacai Chen ----- diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 1c35cac..d3ffe93 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -68,6 +68,8 @@ #define PRID_IMP_RM9000 0x3400 #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 +#define PRID_IMP_LOONGSON1 0x4200 +#define PRID_IMP_LOONGSON2 0x6300 #define PRID_IMP_UNKNOWN 0xff00 @@ -90,8 +92,6 @@ #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 -#define PRID_IMP_LOONGSON1 0x4200 -#define PRID_IMP_LOONGSON2 0x6300 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE ----- From macro@linux-mips.org Mon Jun 9 13:33:41 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 13:33:43 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:1788 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S20031324AbYFIMdl (ORCPT ); Mon, 9 Jun 2008 13:33:41 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m59CXVfa026696; Mon, 9 Jun 2008 14:33:31 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m59CXUuf026692; Mon, 9 Jun 2008 13:33:30 +0100 Date: Mon, 9 Jun 2008 13:33:29 +0100 (BST) From: "Maciej W. Rozycki" To: "Chen, Huacai" cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [patch]modify the MIPS CPU classfication In-Reply-To: <42DFA526FC41B1429CE7279EF83C6BDC01404341@pdsmsx415.ccr.corp.intel.com> Message-ID: References: <42DFA526FC41B1429CE7279EF83C6BDC01404341@pdsmsx415.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19456 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 9 Jun 2008, Chen, Huacai wrote: > The company ID of Loongson1/Loongson2 is PRID_COMP_LEGACY, but they were > classified in the list whoes company ID is PRID_COMP_MIPS. This patch > move them to the right place. Note the list is currently sorted numerically and meant to stay such. Please update your patch accordingly. Maciej From blf.ireland@gmail.com Mon Jun 9 16:37:15 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 16:37:18 +0100 (BST) Received: from hs-out-0708.google.com ([64.233.178.240]:16231 "EHLO hs-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S20032162AbYFIPhP (ORCPT ); Mon, 9 Jun 2008 16:37:15 +0100 Received: by hs-out-0708.google.com with SMTP id x43so901313hsb.0 for ; Mon, 09 Jun 2008 08:37:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:sender :to:subject:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:references :x-google-sender-auth; bh=cugFjSLA+m0QVRhFuuNJQ+b5wa2s5x8Y6XGj62uecpg=; b=b6+2rj7ocokfw1MJ3+Bh4cGYbGrlaDV2BaQenjMe3oG74fGmeN6JvjtgDjYcYn2/pP yPdF1uJrKjmOcEoXLCjt/z4DMSHm7Earw67mxxJufIrsnDblTiULvi03bvZgjqS3mq6d BVn3FSM3T0m2+QnqUi4pvaDeP72AcEFLCrTCs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:sender:to:subject:in-reply-to:mime-version :content-type:content-transfer-encoding:content-disposition :references:x-google-sender-auth; b=mHpbBh1ZJRTxXGF50ITAMGOhOE2+QBmVoi4Zd8J5MEBlm250bX3jfpmuedYzCBzRYe 5ayKvLfgGsbD/zLJrJErusZC7ZLld5LLn+f1dwbtgbFZ3dn2BQ9aaTYW2FGRvgnDNBOf szwZqM+R/CORX3Nw/Da3dg6w+W1p4UwERqCOQ= Received: by 10.150.49.1 with SMTP id w1mr6543951ybw.24.1213025833748; Mon, 09 Jun 2008 08:37:13 -0700 (PDT) Received: by 10.150.156.11 with HTTP; Mon, 9 Jun 2008 08:37:13 -0700 (PDT) Message-ID: Date: Mon, 9 Jun 2008 17:37:13 +0200 From: "Brian Foster" To: linux-mips@linux-mips.org, "Andrew Dyer" Subject: Re: Re: Adding(?) XI support to MIPS-Linux? In-Reply-To: <200806091658.10937.brian.foster@innova-card.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <200806091658.10937.brian.foster@innova-card.com> X-Google-Sender-Auth: f108a826f98cf427 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19457 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips > Date: Monday 09 June 2008 > From: Andrew Dyer > > Brian Foster wrote: >> The MIPS 4KSd core (at least) implements an XI (eXecute Inhibit) >> page protection bit. XI is similar to the NX (No Execute) bit >> in the more recent AMD/Intel x86 families: Attempts to I-fetch >> from a page with XI set cause an exception. > > AFAIK this is the only part with this extension, so I doubt that > much has been done with it. > > I know that OpenBSD has done a bunch of work with x86 implementing > a similar protection scheme, you might do some searching on their > lists to see if they have any information on GCC mods required. Andrew, As far as I am aware, XI is part of the SMARTMIPS extension, and I _think_ SMARTMIPS is only implemented by the 4KS cores? Whilst other companies have licensed that core from MIPS, to the best of my knowledge the SoC I'm concerned with (Innova Card's USIP Pro) is the only one running Linux. So I suspect you're quite correct: Nothing's been done. I've been in contact with the PaX people, and they inform me "the experimental NX tweaks [ for MIPS ] didn't get anywhere due to lack of time/interest of the guy who started it." The "market segment" USIP is aimed at is sufficiently touchy about security I currently believe it's plausible (assuming it's technologically possible) to simply forbid (not support) concurrently executable-and-writable memory. As such, certain programs won't work. Tough. There's no call to support the (broken) JVM's et al. that "require" it, and I'm hoping that nested C/C++ functions are rare (ideally non-existent in the code which normally runs on USIP). It'd be nice if such code either fails to compile and/or fails to link/load, but that's some (highly useful) porcelain. Broadly, what I'm trying to say is I don't want to touch gcc (and/or binutils) and am unconvinced I have to. But I'm very much open to correction here! The x86 (including amd64) and, AFAIK, SuperH (sh) Linux kernels now support NX or equivalent; indeed, a test on my 2.6.22(-ish) amd64 workstation (Kubuntu 7.10) has a non-executable stack. As such, those could be a model worth studying/following, but I understand they have support for specially-marked binaries to have executable stacks (i.e., binutils/gcc mods, which I want to avoid). It's probably worth having a look at OpenBSD (thanks for the suggestion!). Advice, suggestions, pointers, comments, corrections are very welcome. cheers! -blf- -- "How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools." | http://www.stopesso.com From macro@linux-mips.org Mon Jun 9 17:20:00 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 17:20:02 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:53231 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S20031030AbYFIQUA (ORCPT ); Mon, 9 Jun 2008 17:20:00 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m59GJtEa028053; Mon, 9 Jun 2008 18:19:55 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m59GJsCH028049; Mon, 9 Jun 2008 17:19:54 +0100 Date: Mon, 9 Jun 2008 17:19:53 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: Daniel Jacobowitz , linux-mips@linux-mips.org Subject: [PATCH 1/2] mips: Remove obsolete isa_slot_offset Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19458 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips The isa_slot_offset variable and its __ISA_IO_base macro is not used anywhere anymore. It does not look like a decent interface per today's standards either. Remove both including all places of initialization. Signed-off-by: Maciej W. Rozycki --- Hello, This is the first half of a set of two changes resulting from my investigation of how proper iomap support should be done for the SB1250 in response to a report from Daniel. Tested successfully with a SWARM board with no regressions. Please apply. Maciej patch-2.6.26-rc1-20080505-isa-slot-offset-0 diff -up --recursive --new-file linux-2.6.26-rc1-20080505.macro/arch/mips/jazz/setup.c linux-2.6.26-rc1-20080505/arch/mips/jazz/setup.c --- linux-2.6.26-rc1-20080505.macro/arch/mips/jazz/setup.c 2008-05-05 02:55:23.000000000 +0000 +++ linux-2.6.26-rc1-20080505/arch/mips/jazz/setup.c 2008-06-08 23:37:22.000000000 +0000 @@ -79,7 +79,6 @@ void __init plat_mem_setup(void) if (mips_machtype == MACH_MIPS_MAGNUM_4000) EISA_bus = 1; #endif - isa_slot_offset = 0xe3000000; /* request I/O space for devices used on all i[345]86 PCs */ for (i = 0; i < ARRAY_SIZE(jazz_io_resources); i++) diff -up --recursive --new-file linux-2.6.26-rc1-20080505.macro/arch/mips/kernel/setup.c linux-2.6.26-rc1-20080505/arch/mips/kernel/setup.c --- linux-2.6.26-rc1-20080505.macro/arch/mips/kernel/setup.c 2008-05-05 02:55:23.000000000 +0000 +++ linux-2.6.26-rc1-20080505/arch/mips/kernel/setup.c 2008-06-08 23:38:07.000000000 +0000 @@ -68,13 +68,6 @@ static char command_line[CL_SIZE]; const unsigned long mips_io_port_base __read_mostly = -1; EXPORT_SYMBOL(mips_io_port_base); -/* - * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. - */ -unsigned long isa_slot_offset; -EXPORT_SYMBOL(isa_slot_offset); - static struct resource code_resource = { .name = "Kernel code", }; static struct resource data_resource = { .name = "Kernel data", }; diff -up --recursive --new-file linux-2.6.26-rc1-20080505.macro/arch/mips/pci/pci-bcm1480.c linux-2.6.26-rc1-20080505/arch/mips/pci/pci-bcm1480.c --- linux-2.6.26-rc1-20080505.macro/arch/mips/pci/pci-bcm1480.c 2008-05-05 02:55:23.000000000 +0000 +++ linux-2.6.26-rc1-20080505/arch/mips/pci/pci-bcm1480.c 2008-06-08 23:39:17.000000000 +0000 @@ -254,8 +254,6 @@ static int __init bcm1480_pcibios_init(v ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536); bcm1480_controller.io_map_base -= bcm1480_controller.io_offset; set_io_port_base(bcm1480_controller.io_map_base); - isa_slot_offset = (unsigned long) - ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024); register_pci_controller(&bcm1480_controller); diff -up --recursive --new-file linux-2.6.26-rc1-20080505.macro/arch/mips/pci/pci-sb1250.c linux-2.6.26-rc1-20080505/arch/mips/pci/pci-sb1250.c --- linux-2.6.26-rc1-20080505.macro/arch/mips/pci/pci-sb1250.c 2007-10-11 04:56:52.000000000 +0000 +++ linux-2.6.26-rc1-20080505/arch/mips/pci/pci-sb1250.c 2008-06-08 23:39:46.000000000 +0000 @@ -256,8 +256,6 @@ static int __init sb1250_pcibios_init(vo set_io_port_base((unsigned long) ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536)); - isa_slot_offset = (unsigned long) - ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024); #ifdef CONFIG_SIBYTE_HAS_LDT /* diff -up --recursive --new-file linux-2.6.26-rc1-20080505.macro/arch/mips/sni/setup.c linux-2.6.26-rc1-20080505/arch/mips/sni/setup.c --- linux-2.6.26-rc1-20080505.macro/arch/mips/sni/setup.c 2008-05-05 02:55:23.000000000 +0000 +++ linux-2.6.26-rc1-20080505/arch/mips/sni/setup.c 2008-06-08 23:40:05.000000000 +0000 @@ -116,7 +116,6 @@ void __init plat_mem_setup(void) /* * Setup (E)ISA I/O memory access stuff */ - isa_slot_offset = CKSEG1ADDR(0xb0000000); #ifdef CONFIG_EISA EISA_bus = 1; #endif diff -up --recursive --new-file linux-2.6.26-rc1-20080505.macro/include/asm-mips/io.h linux-2.6.26-rc1-20080505/include/asm-mips/io.h --- linux-2.6.26-rc1-20080505.macro/include/asm-mips/io.h 2008-05-05 02:55:55.000000000 +0000 +++ linux-2.6.26-rc1-20080505/include/asm-mips/io.h 2008-06-08 23:23:23.000000000 +0000 @@ -161,13 +161,6 @@ static inline void * isa_bus_to_virt(uns #define bus_to_virt phys_to_virt /* - * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. This implies the assumption that there is only - * one of these busses. - */ -extern unsigned long isa_slot_offset; - -/* * Change "struct page" to physical address. */ #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) @@ -528,16 +521,6 @@ static inline void memcpy_toio(volatile } /* - * ISA space is 'always mapped' on currently supported MIPS systems, no need - * to explicitly ioremap() it. The fact that the ISA IO space is mapped - * to PAGE_OFFSET is pure coincidence - it does not mean ISA values - * are physical addresses. The following constant pointer can be - * used as the IO-area pointer (it can be iounmapped as well, so the - * analogy with PCI is quite large): - */ -#define __ISA_IO_base ((char *)(isa_slot_offset)) - -/* * The caches on some architectures aren't dma-coherent and have need to * handle this in software. There are three types of operations that * can be applied to dma buffers. From macro@linux-mips.org Mon Jun 9 17:20:18 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 17:20:21 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:55791 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S20031402AbYFIQUH (ORCPT ); Mon, 9 Jun 2008 17:20:07 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m59GK4I0028065; Mon, 9 Jun 2008 18:20:04 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m59GK3Fq028059; Mon, 9 Jun 2008 17:20:03 +0100 Date: Mon, 9 Jun 2008 17:20:03 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: Daniel Jacobowitz , linux-mips@linux-mips.org Subject: [PATCH 2/2] sb1250: Initialize io_map_base Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19459 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Correctly initialize io_map_base for the SB1250 PCI controller as required for proper iomap support. Based on a proposal from Daniel Jacobowitz. Signed-off-by: Maciej W. Rozycki --- Hello, This is the second half of a set of two changes resulting from my investigation of how proper iomap support should be done for the SB1250 in response to a report from Daniel. This patch has to be applied on top of the first half. Tested successfully with a SWARM board and a pair of DEFPA cards in the port I/O mode on either of the PCI buses each with no regressions. Note the driver used does not make use of the iomap feature at the moment so the feature was not exactly tested, but is conceptually correct. Please apply. Maciej patch-2.6.26-rc1-20080505-drow-sb1250-pci-io-3 diff -up --recursive --new-file linux-2.6.26-rc1-20080505.macro/arch/mips/pci/pci-sb1250.c linux-2.6.26-rc1-20080505/arch/mips/pci/pci-sb1250.c --- linux-2.6.26-rc1-20080505.macro/arch/mips/pci/pci-sb1250.c 2008-06-08 23:39:46.000000000 +0000 +++ linux-2.6.26-rc1-20080505/arch/mips/pci/pci-sb1250.c 2008-06-08 23:45:01.000000000 +0000 @@ -207,6 +207,7 @@ struct pci_controller sb1250_controller static int __init sb1250_pcibios_init(void) { + void __iomem *io_map_base; uint32_t cmdreg; uint64_t reg; extern int pci_probe_only; @@ -253,9 +254,9 @@ static int __init sb1250_pcibios_init(vo * works correctly with most of Linux's drivers. * XXX ehs: Should this happen in PCI Device mode? */ - - set_io_port_base((unsigned long) - ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536)); + io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024); + sb1250_controller.io_map_base = io_map_base; + set_io_port_base((unsigned long)io_map_base); #ifdef CONFIG_SIBYTE_HAS_LDT /* From KevinK@paralogos.com Mon Jun 9 20:32:57 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 20:33:00 +0100 (BST) Received: from smtp-wifi-out.orange.fr ([80.12.242.163]:4797 "EHLO smtp21.orange.fr") by ftp.linux-mips.org with ESMTP id S20033172AbYFITc5 (ORCPT ); Mon, 9 Jun 2008 20:32:57 +0100 Received: from [127.0.0.1] (unknown [81.253.22.6]) by mwinf5909 (SMTP Server) with ESMTP id B76B2A5F8; Mon, 9 Jun 2008 21:32:48 +0200 (CEST) X-ME-UUID: 20080609193248751.B76B2A5F8@mwinf5909 Message-ID: <484D856B.5030306@paralogos.com> Date: Mon, 09 Jun 2008 21:32:59 +0200 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.14 (Windows/20080421) MIME-Version: 1.0 To: Brian Foster Cc: linux-mips@linux-mips.org, Andrew Dyer Subject: Re: Adding(?) XI support to MIPS-Linux? References: <200806091658.10937.brian.foster@innova-card.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19460 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: KevinK@paralogos.com Precedence: bulk X-list: linux-mips Brian Foster wrote: > Andrew, > > As far as I am aware, XI is part of the SMARTMIPS extension, > and I _think_ SMARTMIPS is only implemented by the 4KS cores? > That is correct, though there has long been interest in having XI/RI as an option for non-SmartMIPS cores and I would not be surprised if sooner or later it became more generally available. > Whilst other companies have licensed that core from MIPS, to > the best of my knowledge the SoC I'm concerned with (Innova > Card's USIP Pro) is the only one running Linux. So I suspect > you're quite correct: Nothing's been done. > I believe that there is at least one other 4KS-family customer working with Linux, but they haven't been nearly as active as InnovaCard. I had some email exchanges with someone who was working on their kernel a couple of years back about this very topic. Indeed, I thought that they submitted some patches for basic RI/XI support at one point. Scan the linux-mips.org archives, if they survived the rehosting. > I've been in contact with the PaX people, and they inform me > "the experimental NX tweaks [ for MIPS ] didn't get anywhere > due to lack of time/interest of the guy who started it." > > The "market segment" USIP is aimed at is sufficiently touchy > about security I currently believe it's plausible (assuming > it's technologically possible) to simply forbid (not support) > concurrently executable-and-writable memory. As such, certain > programs won't work. Tough. There's no call to support the > (broken) JVM's et al. that "require" it, and I'm hoping that > nested C/C++ functions are rare (ideally non-existent in the > code which normally runs on USIP). It'd be nice if such code > either fails to compile and/or fails to link/load, but that's > some (highly useful) porcelain. > > Broadly, what I'm trying to say is I don't want to touch gcc > (and/or binutils) and am unconvinced I have to. But I'm very > much open to correction here! > > The x86 (including amd64) and, AFAIK, SuperH (sh) Linux kernels > now support NX or equivalent; indeed, a test on my 2.6.22(-ish) > amd64 workstation (Kubuntu 7.10) has a non-executable stack. > As such, those could be a model worth studying/following, but > I understand they have support for specially-marked binaries to > have executable stacks (i.e., binutils/gcc mods, which I want to > avoid). Well, strictly speaking, you wouldn't actually *need* to modify binutils to make specially tagged binaries. You could borrow an unused bit in the ELF header somewhere, have the kernel recognize it, and write your own little tool that only turns that bit on/off in an ELF file. In the longer term, I'd argue that if there's support for appropriate binary tagging in the x86 tools, that support should simply be enabled for MIPS targets and any other non-x86 archiectures with such support (e.g. Alpha, if anyone still uses them). Regards, Kevin K. From ths@networkno.de Mon Jun 9 21:46:30 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 21:46:32 +0100 (BST) Received: from relay01.mx.bawue.net ([193.7.176.67]:54231 "EHLO relay01.mx.bawue.net") by ftp.linux-mips.org with ESMTP id S20027200AbYFIUqa (ORCPT ); Mon, 9 Jun 2008 21:46:30 +0100 Received: from lagash (88-106-136-149.dynamic.dsl.as9105.com [88.106.136.149]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by relay01.mx.bawue.net (Postfix) with ESMTP id A715648916; Mon, 9 Jun 2008 22:46:28 +0200 (CEST) Received: from ths by lagash with local (Exim 4.69) (envelope-from ) id 1K5oG3-0000HB-MP; Mon, 09 Jun 2008 21:46:27 +0100 Date: Mon, 9 Jun 2008 21:46:27 +0100 From: Thiemo Seufer To: "Kevin D. Kissell" Cc: Brian Foster , linux-mips@linux-mips.org, Andrew Dyer Subject: Re: Adding(?) XI support to MIPS-Linux? Message-ID: <20080609204627.GE11233@networkno.de> References: <200806091658.10937.brian.foster@innova-card.com> <484D856B.5030306@paralogos.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <484D856B.5030306@paralogos.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19461 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Kevin D. Kissell wrote: [snip] >> Broadly, what I'm trying to say is I don't want to touch gcc >> (and/or binutils) and am unconvinced I have to. But I'm very >> much open to correction here! >> >> The x86 (including amd64) and, AFAIK, SuperH (sh) Linux kernels >> now support NX or equivalent; indeed, a test on my 2.6.22(-ish) >> amd64 workstation (Kubuntu 7.10) has a non-executable stack. >> As such, those could be a model worth studying/following, but >> I understand they have support for specially-marked binaries to >> have executable stacks (i.e., binutils/gcc mods, which I want to >> avoid). > Well, strictly speaking, you wouldn't actually *need* to modify binutils > to make specially tagged binaries. You could borrow an unused bit in > the ELF header somewhere, have the kernel recognize it, and write your > own little tool that only turns that bit on/off in an ELF file. This exists already in ld's -z execstack/noexecstack feature. It is not used by default because too many things depend on executable stacks on MIPS. Thiemo From rdsandiford@googlemail.com Mon Jun 9 22:13:43 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 22:13:48 +0100 (BST) Received: from ik-out-1112.google.com ([66.249.90.179]:27928 "EHLO ik-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S20030025AbYFIVNn (ORCPT ); Mon, 9 Jun 2008 22:13:43 +0100 Received: by ik-out-1112.google.com with SMTP id b32so1590615ika.0 for ; Mon, 09 Jun 2008 14:13:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:mail-followup-to:cc :subject:references:date:in-reply-to:message-id:user-agent :mime-version:content-type; bh=mGBXkMqeNQ7+20GTfcpxYUaORKq1ZJSI4FhHOH/VbFE=; b=kAc/e6URDuhrhp916u5b/O905SuAqHhtVzoRqUY1ZVBuwQsSs3Bt5e2U4EVM0Ppgul 7VbUqN5A9JvPWgIw69LrFLmylR1ZKBfoJ707Nbh9AYglupRd2wf8evr+tAxxyUEa1Kst 5h+tzdCkKiMNM0rJfXUu+b94pUqPZMu3JVdqw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:mail-followup-to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-type; b=Ywr+Qg0v/5STQfHuM4PVXcqI35IhL+TrAmMGjFHx3lypIzL9P7L9zfS+RqYsduQ3cZ 6/Knb7V2FD4s5ly9xqsX+0N1/M2T5ahY83b6NoORle7PO/7Je51afiiLJ2NoPsXqRav7 5AkimU6gmjmVbykbKLz3jSZBXkmYdmDjdFFE4= Received: by 10.210.28.4 with SMTP id b4mr3444889ebb.40.1213046020287; Mon, 09 Jun 2008 14:13:40 -0700 (PDT) Received: from localhost ( [79.75.55.39]) by mx.google.com with ESMTPS id i6sm16441688gve.4.2008.06.09.14.13.30 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 09 Jun 2008 14:13:36 -0700 (PDT) From: Richard Sandiford To: "Maciej W. Rozycki" Mail-Followup-To: "Maciej W. Rozycki" ,Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Cc: Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org Subject: Re: Changing the treatment of the MIPS HI and LO registers References: <87tzgj4nh6.fsf@firetop.home> <87abib4d9t.fsf@firetop.home> <87r6bm1ebd.fsf@firetop.home> <878wxtvarg.fsf@firetop.home> <8763stz2p3.fsf@firetop.home> Date: Mon, 09 Jun 2008 22:13:28 +0100 In-Reply-To: <8763stz2p3.fsf@firetop.home> (Richard Sandiford's message of "Sun\, 01 Jun 2008 14\:48\:08 +0100") Message-ID: <87zlpuxqfb.fsf@firetop.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19462 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rdsandiford@googlemail.com Precedence: bulk X-list: linux-mips Richard Sandiford writes: > I'll reinstate the 48 hour warning, mostly as a way of seeing > whether the thread is still alive. Here's the final version of the patch. I fixed the mulsi3_highpart condition and added a couple of missing attributes. Applied after retesting. I also made the following changes to the web page: Index: htdocs/gcc-4.4/changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.4/changes.html,v retrieving revision 1.11 diff -u -p -r1.11 changes.html --- htdocs/gcc-4.4/changes.html 9 Jun 2008 20:41:49 -0000 1.11 +++ htdocs/gcc-4.4/changes.html 9 Jun 2008 21:10:25 -0000 @@ -28,6 +28,28 @@ when -Wdeprecated or -pedantic is used. This extension has been deprecated for many years, but never warned about. + +
  • The MIPS port no longer recognizes the h + asm constraint. It was necessary to remove + this constraint in order to avoid generating unpredictable + code sequences. + +

    One of the main uses of the h constraint + was to extract the high part of a multiplication on + 64-bit targets. For example:

    + 
    +    asm ("dmultu\t%1,%2" : "=h" (result) : "r" (x), "r" (y));
    +

    You can now achieve the same effect using 128-bit types:

    + 
    +    typedef unsigned int uint128_t __attribute__((mode(TI)));
+    result = ((uint128_t) x * y) >> 64;
    +

    The second sequence is better in many ways. For example, + if x and y are constants, the + compiler can perform the multiplication at compile time. + If x and y are not constants, + the compiler can schedule the runtime multiplication + better than it can schedule an asm statement.

    +

    • General Optimizer Improvements

    @@ -75,6 +97,8 @@
    • Support for RMI's XLR processor is now available through the -march=xlr and -mtune=xlr options.
      • +
    • 64-bit targets can now perform 128-bit multiplications inline, + instead of relying on a libgcc function.

    Documentation improvements

    Please shout if you find anything wrong with either the patch or the documentation changes. Richard gcc/ * doc/md.texi: Synchronize with later constraints.md change. * longlong.h (umul_ppmm): Replace the MIPS asm implementation with a C implementation. * config/mips/mips.c (mips_legitimize_move): Remove MFHI and MFLO handling. (mips_subword): Assume TImode for CONST_INTs if TARGET_64BIT. (mips_split_doubleword_move): Use special MTHI and MFHI instructions when moving to and from MD_REGNUM. (mips_output_move): Don't handle moves from GPRs to HI_REGNUM. Handle moves from LO_REGNUM to GPRs using MFLO, MACC or DMACC. Handle byte and halfword moves. (mips_hard_regno_mode_ok_p): Handle MD_REGS and DSP_ACC_REGS separately. * config/mips/constraints.md (h): Turn into NO_REGS. (l, x): Update documentation. * config/mips/mips.md (UNSPEC_MFHILO): Delete. (UNSPEC_MFHI, UNSPEC_MTHI, UNSPEC_SET_HILO): New. (UNSPEC_TLS_LDM, UNSPEC_TLS_GET_TP): Renumber. (HILO): New mode iterator. (MOVE128): Add TI. (any_div): New code iterator. (u): Extend code attribute to div and udiv. (*add3_mips16, *movdi_64bit_mips16, *movsi_mips16): Use d_operand in the splitters. Remove redundant CONST_INT checks. (mulsi3_mult3, mul3_internal, mul3_r4000, *mul_acc_si) (*macc, *msac, *msac_using_macc, *macc2, *msac2, *mul_sub_si) (*muls): Remove "=h" clobbers. Adjust peephole2s and define_splits accordingly, using normal moves instead of unspecs to move LO into a GPR. Use d_operand and lo_operand instead of *_REG_P checks. (mulsidi3): Handle expansion in C code. (mulsidi3_32bit_internal): Rename to... (mulsidi3_32bit): ...this. (mulsidi3_32bit_r4000): Fix insn separator. (*mulsidi3_64bit): Rename to... (mulsidi3_64bit): ...this. Combine DImode "=h" and "=l" clobbers into a TImode "=x" clobber. In the split, use an UNSPEC_SET_HILO to set LO and HI to the multiplication result. Use a normal move for MFLO and an unspec for MFHI. (*mulsidi3_64bit_parts): Replace with... (mulsidi3_64bit_hilo): ...this new instruction. (mulsi3_highpart): Extend to TARGET_FIX_R4000. (mulsi3_highpart_internal): Turn into a define_insn_and_split and extend it to TARGET_FIX_R4000. Store the destination in a GPR instead of HI. Split the instruction into a separate multiplication and MFHI if !TARGET_FIX_R4000. (muldi3_highpart): Likewise. (mulsi3_highpart_mulhi_internal): Remove the first alternative and the "=h" clobber. (*mulsi3_highpart_neg_mulhi_internal): Likewise. (mulditi3): New expander. (mulditi3_internal, mulditi3_r4000): New patterns. (madsi): Remove "=h" clobber. (divmod4, udivmod4): Turn into define_insn_and_splits. Force the modulus result to be a GPR and split the instruction into a division followed by an MFHI after reload. (divmod4_hilo_): New instruction. (*lea_high64): Use d_operand in the define_peephole2. Likewise the MIPS16 HIGH define_split. (*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16): Change type of acc<->gpr moves to "multi". (*movdi_64bit): Replace the single "x" alternative with alternatives for moving into and out of "a". (*movhi_internal, *movqi_internal): Likewise. Use mips_output_move. (*movsi_internal): Extend the "d<-A" alternative to "d<-a". (*movdi_64bit_mips16, *movsi_mips16): Add d<-a alternatives. Use d_operand in the splitters. Remove redundant CONST_INT checks. (*movhi_mips16, *movqi_mips16): Likewise. Use mips_output_move. (movti): New expander. (*movti, *movti_mips16): New insns. (mfhilo_, *mfhilo_, *mfhilo__macc): Delete. (mfhi_): New pattern. (mthi_): Likewise. * config/mips/predicates.md (fpr_operand): Delete. (d_operand): New predicate. gcc/testsuite/ * gcc.dg/torture/mips-hilo-1.c: Delete. * gcc.target/mips/pr35232.c: Likewise. * gcc.target/mips/fix-vr4130-1.c: Use modulus to create an mfhi. * gcc.target/mips/fix-vr4130-3.c: Likewise. * gcc.target/mips/int-moves-1.c: New test. * gcc.target/mips/int-moves-2.c: Likewise. * gcc.target/mips/fix-r4000-1.c: Likewise. * gcc.target/mips/fix-r4000-2.c: Likewise. * gcc.target/mips/fix-r4000-3.c: Likewise. * gcc.target/mips/fix-r4000-4.c: Likewise. * gcc.target/mips/fix-r4000-5.c: Likewise. * gcc.target/mips/fix-r4000-6.c: Likewise. * gcc.target/mips/fix-r4000-7.c: Likewise. * gcc.target/mips/fix-r4000-8.c: Likewise. * gcc.target/mips/fix-r4000-9.c: Likewise. * gcc.target/mips/fix-r4000-10.c: Likewise. * gcc.target/mips/fix-r4000-11.c: Likewise. * gcc.target/mips/fix-r4000-12.c: Likewise. * gcc.target/mips/timode-1.c: Likewise. * gcc.target/mips/timode-2.c: Likewise. Index: gcc/doc/md.texi =================================================================== --- gcc/doc/md.texi 2008-06-09 21:42:44.000000000 +0100 +++ gcc/doc/md.texi 2008-06-09 21:45:18.000000000 +0100 @@ -2469,13 +2469,15 @@ generating MIPS16 code. A floating-point register (if available). @item h -The @code{hi} register. +Formerly the @code{hi} register. This constraint is no longer supported. @item l -The @code{lo} register. +The @code{lo} register. Use this register to store values that are +no bigger than a word. @item x -The @code{hi} and @code{lo} registers. +The concatenated @code{hi} and @code{lo} registers. Use this register +to store doubleword values. @item c A register suitable for use in an indirect jump. This will always be Index: gcc/longlong.h =================================================================== --- gcc/longlong.h 2008-06-09 21:42:44.000000000 +0100 +++ gcc/longlong.h 2008-06-09 21:45:18.000000000 +0100 @@ -623,12 +623,12 @@ #define UDIV_TIME 150 #endif /* __m88000__ */ #if defined (__mips__) && W_TYPE_SIZE == 32 -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("multu %2,%3" \ - : "=l" ((USItype) (w0)), \ - "=h" ((USItype) (w1)) \ - : "d" ((USItype) (u)), \ - "d" ((USItype) (v))) +#define umul_ppmm(w1, w0, u, v) \ + do { \ + UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \ + (w1) = (USItype) (__x >> 32); \ + (w0) = (USItype) (__x); \ + } while (0) #define UMUL_TIME 10 #define UDIV_TIME 100 Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c 2008-06-09 21:42:44.000000000 +0100 +++ gcc/config/mips/mips.c 2008-06-09 21:45:18.000000000 +0100 @@ -2675,23 +2675,6 @@ mips_legitimize_move (enum machine_mode return true; } - /* Check for individual, fully-reloaded mflo and mfhi instructions. */ - if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD - && REG_P (src) && MD_REG_P (REGNO (src)) - && REG_P (dest) && GP_REG_P (REGNO (dest))) - { - int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM; - if (GET_MODE_SIZE (mode) <= 4) - emit_insn (gen_mfhilo_si (gen_lowpart (SImode, dest), - gen_lowpart (SImode, src), - gen_rtx_REG (SImode, other_regno))); - else - emit_insn (gen_mfhilo_di (gen_lowpart (DImode, dest), - gen_lowpart (DImode, src), - gen_rtx_REG (DImode, other_regno))); - return true; - } - /* We need to deal with constants that would be legitimate immediate_operands but aren't legitimate move_operands. */ if (CONSTANT_P (src) && !move_operand (src, mode)) @@ -3488,7 +3471,7 @@ mips_subword (rtx op, bool high_p) mode = GET_MODE (op); if (mode == VOIDmode) - mode = DImode; + mode = TARGET_64BIT ? TImode : DImode; if (TARGET_BIG_ENDIAN ? !high_p : high_p) byte = UNITS_PER_WORD; @@ -3539,6 +3522,8 @@ mips_split_64bit_move_p (rtx dest, rtx s void mips_split_doubleword_move (rtx dest, rtx src) { + rtx low_dest; + if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src)) { if (!TARGET_64BIT && GET_MODE (dest) == DImode) @@ -3552,12 +3537,27 @@ mips_split_doubleword_move (rtx dest, rt else gcc_unreachable (); } + else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST) + { + low_dest = mips_subword (dest, false); + mips_emit_move (low_dest, mips_subword (src, false)); + if (TARGET_64BIT) + emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest)); + else + emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest)); + } + else if (REG_P (src) && REGNO (src) == MD_REG_FIRST) + { + mips_emit_move (mips_subword (dest, false), mips_subword (src, false)); + if (TARGET_64BIT) + emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src)); + else + emit_insn (gen_mfhisi_di (mips_subword (dest, true), src)); + } else { /* The operation can be split into two normal moves. Decide in which order to do them. */ - rtx low_dest; - low_dest = mips_subword (dest, false); if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src)) @@ -3600,8 +3600,9 @@ mips_output_move (rtx dest, rtx src) if (GP_REG_P (REGNO (dest))) return "move\t%0,%z1"; - if (MD_REG_P (REGNO (dest))) - return "mt%0\t%z1"; + /* Moves to HI are handled by special .md insns. */ + if (REGNO (dest) == LO_REGNUM) + return "mtlo\t%z1"; if (DSP_ACC_REG_P (REGNO (dest))) { @@ -3624,14 +3625,29 @@ mips_output_move (rtx dest, rtx src) } } if (dest_code == MEM) - return dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0"; + switch (GET_MODE_SIZE (mode)) + { + case 1: return "sb\t%z1,%0"; + case 2: return "sh\t%z1,%0"; + case 4: return "sw\t%z1,%0"; + case 8: return "sd\t%z1,%0"; + } } if (dest_code == REG && GP_REG_P (REGNO (dest))) { if (src_code == REG) { - /* Handled by separate patterns. */ - gcc_assert (!MD_REG_P (REGNO (src))); + /* Moves from HI are handled by special .md insns. */ + if (REGNO (src) == LO_REGNUM) + { + /* When generating VR4120 or VR4130 code, we use MACC and + DMACC instead of MFLO. This avoids both the normal + MIPS III HI/LO hazards and the errata related to + -mfix-vr4130. */ + if (ISA_HAS_MACCHI) + return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%."; + return "mflo\t%0"; + } if (DSP_ACC_REG_P (REGNO (src))) { @@ -3658,7 +3674,13 @@ mips_output_move (rtx dest, rtx src) } if (src_code == MEM) - return dbl_p ? "ld\t%0,%1" : "lw\t%0,%1"; + switch (GET_MODE_SIZE (mode)) + { + case 1: return "lbu\t%0,%1"; + case 2: return "lhu\t%0,%1"; + case 4: return "lw\t%0,%1"; + case 8: return "ld\t%0,%1"; + } if (src_code == CONST_INT) { @@ -8954,13 +8976,30 @@ mips_hard_regno_mode_ok_p (unsigned int if (ACC_REG_P (regno) && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode))) { - if (size <= UNITS_PER_WORD) - return true; + if (MD_REG_P (regno)) + { + /* After a multiplication or division, clobbering HI makes + the value of LO unpredictable, and vice versa. This means + that, for all interesting cases, HI and LO are effectively + a single register. - if (size <= UNITS_PER_WORD * 2) - return (DSP_ACC_REG_P (regno) - ? ((regno - DSP_ACC_REG_FIRST) & 1) == 0 - : regno == MD_REG_FIRST); + We model this by requiring that any value that uses HI + also uses LO. */ + if (size <= UNITS_PER_WORD * 2) + return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST); + } + else + { + /* DSP accumulators do not have the same restrictions as + HI and LO, so we can treat them as normal doubleword + registers. */ + if (size <= UNITS_PER_WORD) + return true; + + if (size <= UNITS_PER_WORD * 2 + && ((regno - DSP_ACC_REG_FIRST) & 1) == 0) + return true; + } } if (ALL_COP_REG_P (regno)) Index: gcc/config/mips/constraints.md =================================================================== --- gcc/config/mips/constraints.md 2008-06-09 21:42:44.000000000 +0100 +++ gcc/config/mips/constraints.md 2008-06-09 21:45:18.000000000 +0100 @@ -29,14 +29,16 @@ (define_register_constraint "t" "T_REG" (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" "A floating-point register (if available).") -(define_register_constraint "h" "TARGET_BIG_ENDIAN ? MD0_REG : MD1_REG" - "The @code{hi} register.") +(define_register_constraint "h" "NO_REGS" + "Formerly the @code{hi} register. This constraint is no longer supported.") (define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG" - "The @code{lo} register.") + "The @code{lo} register. Use this register to store values that are + no bigger than a word.") (define_register_constraint "x" "MD_REGS" - "The @code{hi} and @code{lo} registers.") + "The concatenated @code{hi} and @code{lo} registers. Use this register + to store doubleword values.") (define_register_constraint "b" "ALL_REGS" "@internal") Index: gcc/config/mips/mips.md =================================================================== --- gcc/config/mips/mips.md 2008-06-09 21:42:44.000000000 +0100 +++ gcc/config/mips/mips.md 2008-06-09 21:45:18.000000000 +0100 @@ -44,9 +44,11 @@ (define_constants (UNSPEC_LOAD_CALL 23) (UNSPEC_LOAD_GOT 24) (UNSPEC_GP 25) - (UNSPEC_MFHILO 26) - (UNSPEC_TLS_LDM 27) - (UNSPEC_TLS_GET_TP 28) + (UNSPEC_MFHI 26) + (UNSPEC_MTHI 27) + (UNSPEC_SET_HILO 28) + (UNSPEC_TLS_LDM 29) + (UNSPEC_TLS_GET_TP 30) (UNSPEC_MFHC1 31) (UNSPEC_MTHC1 32) (UNSPEC_CLEAR_HAZARD 33) @@ -484,6 +486,10 @@ (define_mode_iterator GPR [SI (DI "TARGE ;; modes. (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) +;; This mode iterator allows :HILO to be used as the mode of the +;; concatenated HI and LO registers. +(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")]) + ;; This mode iterator allows :P to be used for patterns that operate on ;; pointer-sized quantities. Exactly one of the two alternatives will match. (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) @@ -497,7 +503,7 @@ (define_mode_iterator MOVE64 [DI DF (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")]) ;; 128-bit modes for which we provide move patterns on 64-bit targets. -(define_mode_iterator MOVE128 [TF]) +(define_mode_iterator MOVE128 [TI TF]) ;; This mode iterator allows the QI and HI extension patterns to be ;; defined from the same template. @@ -613,6 +619,10 @@ (define_code_iterator any_extend [sign_e ;; from the same template. (define_code_iterator any_shift [ashift ashiftrt lshiftrt]) +;; This code iterator allows unsigned and signed division to be generated +;; from the same template. +(define_code_iterator any_div [div udiv]) + ;; This code iterator allows all native floating-point comparisons to be ;; generated from the same template. (define_code_iterator fcond [unordered uneq unlt unle eq lt le]) @@ -631,6 +641,7 @@ (define_code_iterator any_le [le leu]) ;; expands to an empty string when doing a signed operation and ;; "u" when doing an unsigned operation. (define_code_attr u [(sign_extend "") (zero_extend "u") + (div "") (udiv "u") (gt "") (gtu "u") (ge "") (geu "u") (lt "") (ltu "u") @@ -865,13 +876,10 @@ (define_insn "*add3_mips16" ;; simply adding a constant to a register. (define_split - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "d_operand") (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand")))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) > 0x7f && INTVAL (operands[1]) <= 0x7f + 0x7f) || (INTVAL (operands[1]) < - 0x80 @@ -894,16 +902,11 @@ (define_split }) (define_split - [(set (match_operand:SI 0 "register_operand") - (plus:SI (match_operand:SI 1 "register_operand") + [(set (match_operand:SI 0 "d_operand") + (plus:SI (match_operand:SI 1 "d_operand") (match_operand:SI 2 "const_int_operand")))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && REG_P (operands[1]) - && M16_REG_P (REGNO (operands[1])) && REGNO (operands[0]) != REGNO (operands[1]) - && GET_CODE (operands[2]) == CONST_INT && ((INTVAL (operands[2]) > 0x7 && INTVAL (operands[2]) <= 0x7 + 0x7f) || (INTVAL (operands[2]) < - 0x8 @@ -926,13 +929,10 @@ (define_split }) (define_split - [(set (match_operand:DI 0 "register_operand") + [(set (match_operand:DI 0 "d_operand") (plus:DI (match_dup 0) (match_operand:DI 1 "const_int_operand")))] "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) > 0xf && INTVAL (operands[1]) <= 0xf + 0xf) || (INTVAL (operands[1]) < - 0x10 @@ -955,16 +955,11 @@ (define_split }) (define_split - [(set (match_operand:DI 0 "register_operand") - (plus:DI (match_operand:DI 1 "register_operand") + [(set (match_operand:DI 0 "d_operand") + (plus:DI (match_operand:DI 1 "d_operand") (match_operand:DI 2 "const_int_operand")))] "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && REG_P (operands[1]) - && M16_REG_P (REGNO (operands[1])) && REGNO (operands[0]) != REGNO (operands[1]) - && GET_CODE (operands[2]) == CONST_INT && ((INTVAL (operands[2]) > 0x7 && INTVAL (operands[2]) <= 0x7 + 0xf) || (INTVAL (operands[2]) < - 0x8 @@ -1175,8 +1170,7 @@ (define_insn "mulsi3_mult3" [(set (match_operand:SI 0 "register_operand" "=d,l") (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d"))) - (clobber (match_scratch:SI 3 "=h,h")) - (clobber (match_scratch:SI 4 "=l,X"))] + (clobber (match_scratch:SI 3 "=l,X"))] "ISA_HAS_MUL3" { if (which_alternative == 1) @@ -1195,30 +1189,26 @@ (define_insn "mulsi3_mult3" ;; Operand 0: LO ;; Operand 1: GPR (1st multiplication operand) ;; Operand 2: GPR (2nd multiplication operand) -;; Operand 3: HI -;; Operand 4: GPR (destination) +;; Operand 3: GPR (destination) (define_peephole2 [(parallel - [(set (match_operand:SI 0 "register_operand") - (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand"))) - (clobber (match_operand:SI 3 "register_operand")) + [(set (match_operand:SI 0 "lo_operand") + (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand"))) (clobber (scratch:SI))]) - (set (match_operand:SI 4 "register_operand") - (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))] + (set (match_operand:SI 3 "d_operand") + (match_dup 0))] "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])" [(parallel - [(set (match_dup 4) + [(set (match_dup 3) (mult:SI (match_dup 1) (match_dup 2))) - (clobber (match_dup 3)) (clobber (match_dup 0))])]) (define_insn "mul3_internal" [(set (match_operand:GPR 0 "register_operand" "=l") (mult:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "register_operand" "d"))) - (clobber (match_scratch:GPR 3 "=h"))] + (match_operand:GPR 2 "register_operand" "d")))] "!TARGET_FIX_R4000" "mult\t%1,%2" [(set_attr "type" "imul") @@ -1228,8 +1218,7 @@ (define_insn "mul3_r4000" [(set (match_operand:GPR 0 "register_operand" "=d") (mult:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d"))) - (clobber (match_scratch:GPR 3 "=h")) - (clobber (match_scratch:GPR 4 "=l"))] + (clobber (match_scratch:GPR 3 "=l"))] "TARGET_FIX_R4000" "mult\t%1,%2\;mflo\t%0" [(set_attr "type" "imul") @@ -1243,16 +1232,13 @@ (define_insn "mul3_r4000" ;; Operand 0: LO ;; Operand 1: GPR (1st multiplication operand) ;; Operand 2: GPR (2nd multiplication operand) -;; Operand 3: HI -;; Operand 4: GPR (destination) +;; Operand 3: GPR (destination) (define_peephole2 - [(parallel - [(set (match_operand:SI 0 "register_operand") - (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand"))) - (clobber (match_operand:SI 3 "register_operand"))]) - (set (match_operand:SI 4 "register_operand") - (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))] + [(set (match_operand:SI 0 "lo_operand") + (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand"))) + (set (match_operand:SI 3 "d_operand") + (match_dup 0))] "ISA_HAS_MACC && !ISA_HAS_MUL3" [(set (match_dup 0) (const_int 0)) @@ -1261,11 +1247,10 @@ (define_peephole2 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 0))) - (set (match_dup 4) + (set (match_dup 3) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) - (match_dup 0))) - (clobber (match_dup 3))])]) + (match_dup 0)))])]) ;; Multiply-accumulate patterns @@ -1284,9 +1269,8 @@ (define_insn "*mul_acc_si" (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d") (match_operand:SI 2 "register_operand" "d,d,d")) (match_operand:SI 3 "register_operand" "0,l,*d"))) - (clobber (match_scratch:SI 4 "=h,h,h")) - (clobber (match_scratch:SI 5 "=X,3,l")) - (clobber (match_scratch:SI 6 "=X,X,&d"))] + (clobber (match_scratch:SI 4 "=X,3,l")) + (clobber (match_scratch:SI 5 "=X,X,&d"))] "(TARGET_MIPS3900 || GENERATE_MADD_MSUB) && !TARGET_MIPS16" @@ -1302,53 +1286,45 @@ (define_insn "*mul_acc_si" (set_attr "mode" "SI") (set_attr "length" "4,4,8")]) -;; Split the above insn if we failed to get LO allocated. +;; Split *mul_acc_si if both the source and destination accumulator +;; values are GPRs. (define_split - [(set (match_operand:SI 0 "register_operand") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) - (match_operand:SI 3 "register_operand"))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && GP_REG_P (true_regnum (operands[3]))" - [(parallel [(set (match_dup 6) + [(set (match_operand:SI 0 "d_operand") + (plus:SI (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand")) + (match_operand:SI 3 "d_operand"))) + (clobber (match_operand:SI 4 "lo_operand")) + (clobber (match_operand:SI 5 "d_operand"))] + "reload_completed && !TARGET_DEBUG_D_MODE" + [(parallel [(set (match_dup 5) (mult:SI (match_dup 1) (match_dup 2))) - (clobber (match_dup 4)) - (clobber (match_dup 5))]) - (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))] + (clobber (match_dup 4))]) + (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))] "") -;; Splitter to copy result of MADD to a general register +;; Split *mul_acc_si if the destination accumulator value is in a GPR +;; and the source accumulator value is in LO. (define_split - [(set (match_operand:SI 0 "register_operand") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) - (match_operand:SI 3 "register_operand"))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && true_regnum (operands[3]) == LO_REGNUM" + [(set (match_operand:SI 0 "d_operand") + (plus:SI (mult:SI (match_operand:SI 1 "d_operand") + (match_operand:SI 2 "d_operand")) + (match_operand:SI 3 "lo_operand"))) + (clobber (match_dup 3)) + (clobber (scratch:SI))] + "reload_completed && !TARGET_DEBUG_D_MODE" [(parallel [(set (match_dup 3) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4)) - (clobber (match_dup 5)) - (clobber (match_dup 6))]) - (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))] - "") + (clobber (scratch:SI)) + (clobber (scratch:SI))]) + (set (match_dup 0) (match_dup 3))]) (define_insn "*macc" [(set (match_operand:SI 0 "register_operand" "=l,d") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d")) (match_operand:SI 3 "register_operand" "0,l"))) - (clobber (match_scratch:SI 4 "=h,h")) - (clobber (match_scratch:SI 5 "=X,3"))] + (clobber (match_scratch:SI 4 "=X,3"))] "ISA_HAS_MACC" { if (which_alternative == 1) @@ -1369,8 +1345,7 @@ (define_insn "*msac" (minus:SI (match_operand:SI 1 "register_operand" "0,l") (mult:SI (match_operand:SI 2 "register_operand" "d,d") (match_operand:SI 3 "register_operand" "d,d")))) - (clobber (match_scratch:SI 4 "=h,h")) - (clobber (match_scratch:SI 5 "=X,1"))] + (clobber (match_scratch:SI 4 "=X,1"))] "ISA_HAS_MSAC" { if (which_alternative == 1) @@ -1389,21 +1364,19 @@ (define_insn_and_split "*msac_using_macc (minus:SI (match_operand:SI 1 "register_operand" "0,l") (mult:SI (match_operand:SI 2 "register_operand" "d,d") (match_operand:SI 3 "register_operand" "d,d")))) - (clobber (match_scratch:SI 4 "=h,h")) - (clobber (match_scratch:SI 5 "=X,1")) - (clobber (match_scratch:SI 6 "=d,d"))] + (clobber (match_scratch:SI 4 "=X,1")) + (clobber (match_scratch:SI 5 "=d,d"))] "ISA_HAS_MACC && !ISA_HAS_MSAC" "#" "&& reload_completed" - [(set (match_dup 6) + [(set (match_dup 5) (neg:SI (match_dup 3))) (parallel [(set (match_dup 0) (plus:SI (mult:SI (match_dup 2) - (match_dup 6)) + (match_dup 5)) (match_dup 1))) - (clobber (match_dup 4)) - (clobber (match_dup 5))])] + (clobber (match_dup 4))])] "" [(set_attr "type" "imadd") (set_attr "length" "8")]) @@ -1418,8 +1391,7 @@ (define_insn "*macc2" (set (match_operand:SI 3 "register_operand" "=d") (plus:SI (mult:SI (match_dup 1) (match_dup 2)) - (match_dup 0))) - (clobber (match_scratch:SI 4 "=h"))] + (match_dup 0)))] "ISA_HAS_MACC && reload_completed" "macc\t%3,%1,%2" [(set_attr "type" "imadd") @@ -1433,8 +1405,7 @@ (define_insn "*msac2" (set (match_operand:SI 3 "register_operand" "=d") (minus:SI (match_dup 0) (mult:SI (match_dup 1) - (match_dup 2)))) - (clobber (match_scratch:SI 4 "=h"))] + (match_dup 2))))] "ISA_HAS_MSAC && reload_completed" "msac\t%3,%1,%2" [(set_attr "type" "imadd") @@ -1445,23 +1416,19 @@ (define_insn "*msac2" ;; ;; Operand 0: LO ;; Operand 1: macc/msac -;; Operand 2: HI -;; Operand 3: GPR (destination) +;; Operand 2: GPR (destination) (define_peephole2 [(parallel - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "lo_operand") (match_operand:SI 1 "macc_msac_operand")) - (clobber (match_operand:SI 2 "register_operand")) (clobber (scratch:SI))]) - (set (match_operand:SI 3 "register_operand") - (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))] + (set (match_operand:SI 2 "d_operand") + (match_dup 0))] "" [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 3) - (match_dup 1)) - (clobber (match_dup 2))])] - "") + (set (match_dup 2) + (match_dup 1))])]) ;; When we have a three-address multiplication instruction, it should ;; be faster to do a separate multiply and add, rather than moving @@ -1475,32 +1442,26 @@ (define_peephole2 ;; Operand 2: GPR (addend) ;; Operand 3: GPR (destination) ;; Operand 4: macc/msac -;; Operand 5: HI -;; Operand 6: new multiplication -;; Operand 7: new addition/subtraction +;; Operand 5: new multiplication +;; Operand 6: new addition/subtraction (define_peephole2 [(match_scratch:SI 0 "d") - (set (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) + (set (match_operand:SI 1 "lo_operand") + (match_operand:SI 2 "d_operand")) (match_dup 0) (parallel - [(set (match_operand:SI 3 "register_operand") + [(set (match_operand:SI 3 "d_operand") (match_operand:SI 4 "macc_msac_operand")) - (clobber (match_operand:SI 5 "register_operand")) (clobber (match_dup 1))])] - "ISA_HAS_MUL3 - && true_regnum (operands[1]) == LO_REGNUM - && peep2_reg_dead_p (2, operands[1]) - && GP_REG_P (true_regnum (operands[3]))" + "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])" [(parallel [(set (match_dup 0) - (match_dup 6)) - (clobber (match_dup 5)) + (match_dup 5)) (clobber (match_dup 1))]) (set (match_dup 3) - (match_dup 7))] + (match_dup 6))] { - operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); - operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, + operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, operands[2], operands[0]); }) @@ -1510,33 +1471,30 @@ (define_peephole2 ;; Operand 1: LO ;; Operand 2: GPR (addend) ;; Operand 3: macc/msac -;; Operand 4: HI -;; Operand 5: GPR (destination) -;; Operand 6: new multiplication -;; Operand 7: new addition/subtraction +;; Operand 4: GPR (destination) +;; Operand 5: new multiplication +;; Operand 6: new addition/subtraction (define_peephole2 [(match_scratch:SI 0 "d") - (set (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "register_operand")) + (set (match_operand:SI 1 "lo_operand") + (match_operand:SI 2 "d_operand")) (match_dup 0) (parallel [(set (match_dup 1) (match_operand:SI 3 "macc_msac_operand")) - (clobber (match_operand:SI 4 "register_operand")) (clobber (scratch:SI))]) (match_dup 0) - (set (match_operand:SI 5 "register_operand") - (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))] + (set (match_operand:SI 4 "d_operand") + (match_dup 1))] "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])" [(parallel [(set (match_dup 0) - (match_dup 6)) - (clobber (match_dup 4)) + (match_dup 5)) (clobber (match_dup 1))]) - (set (match_dup 5) - (match_dup 7))] + (set (match_dup 4) + (match_dup 6))] { - operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); - operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, + operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1); + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, operands[2], operands[0]); }) @@ -1545,9 +1503,8 @@ (define_insn "*mul_sub_si" (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d") (mult:SI (match_operand:SI 2 "register_operand" "d,d,d") (match_operand:SI 3 "register_operand" "d,d,d")))) - (clobber (match_scratch:SI 4 "=h,h,h")) - (clobber (match_scratch:SI 5 "=X,1,l")) - (clobber (match_scratch:SI 6 "=X,X,&d"))] + (clobber (match_scratch:SI 4 "=X,1,l")) + (clobber (match_scratch:SI 5 "=X,X,&d"))] "GENERATE_MADD_MSUB" "@ msub\t%2,%3 @@ -1557,52 +1514,45 @@ (define_insn "*mul_sub_si" (set_attr "mode" "SI") (set_attr "length" "4,8,8")]) -;; Split the above insn if we failed to get LO allocated. +;; Split *mul_sub_si if both the source and destination accumulator +;; values are GPRs. (define_split - [(set (match_operand:SI 0 "register_operand") - (minus:SI (match_operand:SI 1 "register_operand") - (mult:SI (match_operand:SI 2 "register_operand") - (match_operand:SI 3 "register_operand")))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && GP_REG_P (true_regnum (operands[1]))" - [(parallel [(set (match_dup 6) + [(set (match_operand:SI 0 "d_operand") + (minus:SI (match_operand:SI 1 "d_operand") + (mult:SI (match_operand:SI 2 "d_operand") + (match_operand:SI 3 "d_operand")))) + (clobber (match_operand:SI 4 "lo_operand")) + (clobber (match_operand:SI 5 "d_operand"))] + "reload_completed && !TARGET_DEBUG_D_MODE" + [(parallel [(set (match_dup 5) (mult:SI (match_dup 2) (match_dup 3))) - (clobber (match_dup 4)) - (clobber (match_dup 5))]) - (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))] + (clobber (match_dup 4))]) + (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))] "") -;; Splitter to copy result of MSUB to a general register +;; Split *mul_acc_si if the destination accumulator value is in a GPR +;; and the source accumulator value is in LO. (define_split - [(set (match_operand:SI 0 "register_operand") - (minus:SI (match_operand:SI 1 "register_operand") - (mult:SI (match_operand:SI 2 "register_operand") - (match_operand:SI 3 "register_operand")))) - (clobber (match_scratch:SI 4)) - (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6))] - "reload_completed && !TARGET_DEBUG_D_MODE - && GP_REG_P (true_regnum (operands[0])) - && true_regnum (operands[1]) == LO_REGNUM" + [(set (match_operand:SI 0 "d_operand") + (minus:SI (match_operand:SI 1 "lo_operand") + (mult:SI (match_operand:SI 2 "d_operand") + (match_operand:SI 3 "d_operand")))) + (clobber (match_dup 1)) + (clobber (scratch:SI))] + "reload_completed && !TARGET_DEBUG_D_MODE" [(parallel [(set (match_dup 1) (minus:SI (match_dup 1) (mult:SI (match_dup 2) (match_dup 3)))) - (clobber (match_dup 4)) - (clobber (match_dup 5)) - (clobber (match_dup 6))]) - (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))] + (clobber (scratch:SI)) + (clobber (scratch:SI))]) + (set (match_dup 0) (match_dup 1))] "") (define_insn "*muls" - [(set (match_operand:SI 0 "register_operand" "=l,d") + [(set (match_operand:SI 0 "register_operand" "=l,d") (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "register_operand" "d,d")))) - (clobber (match_scratch:SI 3 "=h,h")) - (clobber (match_scratch:SI 4 "=X,l"))] + (clobber (match_scratch:SI 3 "=X,l"))] "ISA_HAS_MULS" "@ muls\t$0,%1,%2 @@ -1610,31 +1560,23 @@ (define_insn "*muls" [(set_attr "type" "imul,imul3") (set_attr "mode" "SI")]) -;; ??? We could define a mulditi3 pattern when TARGET_64BIT. - (define_expand "mulsidi3" - [(parallel - [(set (match_operand:DI 0 "register_operand") - (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) - (any_extend:DI (match_operand:SI 2 "register_operand")))) - (clobber (scratch:DI)) - (clobber (scratch:DI)) - (clobber (scratch:DI))])] + [(set (match_operand:DI 0 "register_operand") + (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) + (any_extend:DI (match_operand:SI 2 "register_operand"))))] "!TARGET_64BIT || !TARGET_FIX_R4000" { - if (!TARGET_64BIT) - { - if (!TARGET_FIX_R4000) - emit_insn (gen_mulsidi3_32bit_internal (operands[0], operands[1], - operands[2])); - else - emit_insn (gen_mulsidi3_32bit_r4000 (operands[0], operands[1], - operands[2])); - DONE; - } + if (TARGET_64BIT) + emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2])); + else if (TARGET_FIX_R4000) + emit_insn (gen_mulsidi3_32bit_r4000 (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_mulsidi3_32bit (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "mulsidi3_32bit_internal" +(define_insn "mulsidi3_32bit" [(set (match_operand:DI 0 "register_operand" "=x") (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))] @@ -1649,42 +1591,35 @@ (define_insn "mulsidi3_32bit_r4000" (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) (clobber (match_scratch:DI 3 "=x"))] "!TARGET_64BIT && TARGET_FIX_R4000" - "mult\t%1,%2\;mflo\t%L0;mfhi\t%M0" + "mult\t%1,%2\;mflo\t%L0\;mfhi\t%M0" [(set_attr "type" "imul") (set_attr "mode" "SI") (set_attr "length" "12")]) -(define_insn_and_split "*mulsidi3_64bit" +(define_insn_and_split "mulsidi3_64bit" [(set (match_operand:DI 0 "register_operand" "=d") (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) - (clobber (match_scratch:DI 3 "=l")) - (clobber (match_scratch:DI 4 "=h")) - (clobber (match_scratch:DI 5 "=d"))] + (clobber (match_scratch:TI 3 "=x")) + (clobber (match_scratch:DI 4 "=d"))] "TARGET_64BIT && !TARGET_FIX_R4000" "#" "&& reload_completed" - [(parallel - [(set (match_dup 3) - (sign_extend:DI - (mult:SI (match_dup 1) - (match_dup 2)))) - (set (match_dup 4) - (ashiftrt:DI - (mult:DI (any_extend:DI (match_dup 1)) - (any_extend:DI (match_dup 2))) - (const_int 32)))]) - - ;; OP5 <- LO, OP0 <- HI - (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO)) - (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO)) - - ;; Zero-extend OP5. - (set (match_dup 5) - (ashift:DI (match_dup 5) + [(set (match_dup 3) + (unspec:TI [(mult:DI (any_extend:DI (match_dup 1)) + (any_extend:DI (match_dup 2)))] + UNSPEC_SET_HILO)) + + ;; OP4 <- LO, OP0 <- HI + (set (match_dup 4) (match_dup 5)) + (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI)) + + ;; Zero-extend OP4. + (set (match_dup 4) + (ashift:DI (match_dup 4) (const_int 32))) - (set (match_dup 5) - (lshiftrt:DI (match_dup 5) + (set (match_dup 4) + (lshiftrt:DI (match_dup 4) (const_int 32))) ;; Shift OP0 into place. @@ -1695,24 +1630,21 @@ (define_insn_and_split "*mulsidi3_64b ;; OR the two halves together (set (match_dup 0) (ior:DI (match_dup 0) - (match_dup 5)))] - "" + (match_dup 4)))] + { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); } [(set_attr "type" "imul") (set_attr "mode" "SI") (set_attr "length" "24")]) -(define_insn "*mulsidi3_64bit_parts" - [(set (match_operand:DI 0 "register_operand" "=l") - (sign_extend:DI - (mult:SI (match_operand:SI 2 "register_operand" "d") - (match_operand:SI 3 "register_operand" "d")))) - (set (match_operand:DI 1 "register_operand" "=h") - (ashiftrt:DI - (mult:DI (any_extend:DI (match_dup 2)) - (any_extend:DI (match_dup 3))) - (const_int 32)))] +(define_insn "mulsidi3_64bit_hilo" + [(set (match_operand:TI 0 "register_operand" "=x") + (unspec:TI + [(mult:DI + (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d")))] + UNSPEC_SET_HILO))] "TARGET_64BIT && !TARGET_FIX_R4000" - "mult\t%2,%3" + "mult\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -1756,7 +1688,7 @@ (define_expand "mulsi3_highpart" (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) (any_extend:DI (match_operand:SI 2 "register_operand"))) (const_int 32))))] - "ISA_HAS_MULHI || !TARGET_FIX_R4000" + "" { if (ISA_HAS_MULHI) emit_insn (gen_mulsi3_highpart_mulhi_internal (operands[0], @@ -1768,72 +1700,133 @@ (define_expand "mulsi3_highpart" DONE; }) -(define_insn "mulsi3_highpart_internal" - [(set (match_operand:SI 0 "register_operand" "=h") +(define_insn_and_split "mulsi3_highpart_internal" + [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) (const_int 32)))) (clobber (match_scratch:SI 3 "=l"))] - "!ISA_HAS_MULHI && !TARGET_FIX_R4000" - "mult\t%1,%2" + "!ISA_HAS_MULHI" + { return TARGET_FIX_R4000 ? "mult\t%1,%2\n\tmfhi\t%0" : "#"; } + "&& reload_completed && !TARGET_FIX_R4000" + [(const_int 0)] +{ + rtx hilo; + + if (TARGET_64BIT) + { + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_mulsidi3_64bit_hilo (hilo, operands[1], operands[2])); + emit_insn (gen_mfhisi_ti (operands[0], hilo)); + } + else + { + hilo = gen_rtx_REG (DImode, MD_REG_FIRST); + emit_insn (gen_mulsidi3_32bit (hilo, operands[1], operands[2])); + emit_insn (gen_mfhisi_di (operands[0], hilo)); + } + DONE; +} [(set_attr "type" "imul") - (set_attr "mode" "SI")]) + (set_attr "mode" "SI") + (set_attr "length" "8")]) (define_insn "mulsi3_highpart_mulhi_internal" - [(set (match_operand:SI 0 "register_operand" "=h,d") + [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI - (any_extend:DI (match_operand:SI 1 "register_operand" "d,d")) - (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))) + (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=l,l")) - (clobber (match_scratch:SI 4 "=X,h"))] + (clobber (match_scratch:SI 3 "=l"))] "ISA_HAS_MULHI" - "@ - mult\t%1,%2 - mulhi\t%0,%1,%2" - [(set_attr "type" "imul,imul3") + "mulhi\t%0,%1,%2" + [(set_attr "type" "imul3") (set_attr "mode" "SI")]) (define_insn "*mulsi3_highpart_neg_mulhi_internal" - [(set (match_operand:SI 0 "register_operand" "=h,d") + [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (neg:DI (mult:DI - (any_extend:DI (match_operand:SI 1 "register_operand" "d,d")) - (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))) + (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=l,l")) - (clobber (match_scratch:SI 4 "=X,h"))] + (clobber (match_scratch:SI 3 "=l"))] "ISA_HAS_MULHI" - "@ - mulshi\t%.,%1,%2 - mulshi\t%0,%1,%2" - [(set_attr "type" "imul,imul3") + "mulshi\t%0,%1,%2" + [(set_attr "type" "imul3") (set_attr "mode" "SI")]) ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120 ;; errata MD(0), which says that dmultu does not always produce the ;; correct result. -(define_insn "muldi3_highpart" - [(set (match_operand:DI 0 "register_operand" "=h") +(define_insn_and_split "muldi3_highpart" + [(set (match_operand:DI 0 "register_operand" "=d") (truncate:DI (lshiftrt:TI - (mult:TI - (any_extend:TI (match_operand:DI 1 "register_operand" "d")) - (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) + (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) (const_int 64)))) (clobber (match_scratch:DI 3 "=l"))] - "TARGET_64BIT && !TARGET_FIX_R4000 + "TARGET_64BIT && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" + { return TARGET_FIX_R4000 ? "dmult\t%1,%2\n\tmfhi\t%0" : "#"; } + "&& reload_completed && !TARGET_FIX_R4000" + [(const_int 0)] +{ + rtx hilo; + + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_mulditi3_internal (hilo, operands[1], operands[2])); + emit_insn (gen_mfhidi_ti (operands[0], hilo)); + DONE; +} + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "8")]) + +(define_expand "mulditi3" + [(set (match_operand:TI 0 "register_operand") + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) + (any_extend:TI (match_operand:DI 2 "register_operand"))))] + "TARGET_64BIT && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" +{ + if (TARGET_FIX_R4000) + emit_insn (gen_mulditi3_r4000 (operands[0], operands[1], operands[2])); + else + emit_insn (gen_mulditi3_internal (operands[0], operands[1], + operands[2])); + DONE; +}) + +(define_insn "mulditi3_internal" + [(set (match_operand:TI 0 "register_operand" "=x") + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) + (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))] + "TARGET_64BIT + && !TARGET_FIX_R4000 && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" "dmult\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) +(define_insn "mulditi3_r4000" + [(set (match_operand:TI 0 "register_operand" "=d") + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) + (any_extend:TI (match_operand:DI 2 "register_operand" "d")))) + (clobber (match_scratch:TI 3 "=x"))] + "TARGET_64BIT + && TARGET_FIX_R4000 + && !( == ZERO_EXTEND && TARGET_FIX_VR4120)" + "dmult\t%1,%2\;mflo\t%L0\;mfhi\t%M0" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "12")]) + ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate ;; instruction. The HI/LO registers are used as a 64-bit accumulator. @@ -1841,8 +1834,7 @@ (define_insn "madsi" [(set (match_operand:SI 0 "register_operand" "+l") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")) - (match_dup 0))) - (clobber (match_scratch:SI 3 "=h"))] + (match_dup 0)))] "TARGET_MAD" "mad\t%1,%2" [(set_attr "type" "imadd") @@ -2017,29 +2009,80 @@ (define_insn "*recip3" ;; VR4120 errata MD(A1): signed division instructions do not work correctly ;; with negative operands. We use special libgcc functions instead. -(define_insn "divmod4" +(define_insn_and_split "divmod4" [(set (match_operand:GPR 0 "register_operand" "=l") (div:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d"))) - (set (match_operand:GPR 3 "register_operand" "=h") + (set (match_operand:GPR 3 "register_operand" "=d") (mod:GPR (match_dup 1) (match_dup 2)))] "!TARGET_FIX_VR4120" - { return mips_output_division ("div\t$0,%1,%2", operands); } - [(set_attr "type" "idiv") - (set_attr "mode" "")]) + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx hilo; + + if (TARGET_64BIT) + { + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_divmod4_hilo_ti (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_ti (operands[3], hilo)); + } + else + { + hilo = gen_rtx_REG (DImode, MD_REG_FIRST); + emit_insn (gen_divmod4_hilo_di (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_di (operands[3], hilo)); + } + DONE; +} + [(set_attr "type" "idiv") + (set_attr "mode" "") + (set_attr "length" "8")]) -(define_insn "udivmod4" +(define_insn_and_split "udivmod4" [(set (match_operand:GPR 0 "register_operand" "=l") (udiv:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d"))) - (set (match_operand:GPR 3 "register_operand" "=h") + (set (match_operand:GPR 3 "register_operand" "=d") (umod:GPR (match_dup 1) (match_dup 2)))] "" - { return mips_output_division ("divu\t$0,%1,%2", operands); } + "#" + "reload_completed" + [(const_int 0)] +{ + rtx hilo; + + if (TARGET_64BIT) + { + hilo = gen_rtx_REG (TImode, MD_REG_FIRST); + emit_insn (gen_udivmod4_hilo_ti (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_ti (operands[3], hilo)); + } + else + { + hilo = gen_rtx_REG (DImode, MD_REG_FIRST); + emit_insn (gen_udivmod4_hilo_di (hilo, operands[1], operands[2])); + emit_insn (gen_mfhi_di (operands[3], hilo)); + } + DONE; +} + [(set_attr "type" "idiv") + (set_attr "mode" "") + (set_attr "length" "8")]) + +(define_insn "divmod4_hilo_" + [(set (match_operand:HILO 0 "register_operand" "=x") + (unspec:HILO + [(any_div:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "register_operand" "d"))] + UNSPEC_SET_HILO))] + "" + { return mips_output_division ("div\t%.,%1,%2", operands); } [(set_attr "type" "idiv") - (set_attr "mode" "")]) + (set_attr "mode" "")]) ;; ;; .................... @@ -3241,7 +3284,7 @@ (define_insn_and_split "*lea_high64" ;; dsll32 op1,op1,0 ;; daddu op1,op1,op0 (define_peephole2 - [(set (match_operand:DI 1 "register_operand") + [(set (match_operand:DI 1 "d_operand") (high:DI (match_operand:DI 2 "absolute_symbolic_operand"))) (match_scratch:DI 0 "d")] "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" @@ -3294,8 +3337,8 @@ (define_insn_and_split "*lea64" ;; ;; on MIPS16 targets. (define_split - [(set (match_operand:SI 0 "register_operand" "=d") - (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))] + [(set (match_operand:SI 0 "d_operand") + (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))] "TARGET_MIPS16 && reload_completed" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))] @@ -3464,7 +3507,7 @@ (define_insn "*movdi_32bit" && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store") + [(set_attr "type" "multi,multi,load,store,multi,multi,mtc,load,mfc,store") (set_attr "mode" "DI") (set_attr "length" "8,16,*,*,8,8,8,*,8,*")]) @@ -3475,7 +3518,7 @@ (define_insn "*movdi_gp32_fp64" && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore") + [(set_attr "type" "multi,multi,load,store,multi,multi,mtc,fpload,mfc,fpstore") (set_attr "mode" "DI") (set_attr "length" "8,16,*,*,8,8,8,*,8,*")]) @@ -3486,29 +3529,29 @@ (define_insn "*movdi_32bit_mips16" && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo") + [(set_attr "type" "multi,multi,multi,multi,multi,load,store,multi") (set_attr "mode" "DI") (set_attr "length" "8,8,8,8,12,*,*,8")]) (define_insn "*movdi_64bit" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m") - (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m") + (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] "TARGET_64BIT && !TARGET_MIPS16 && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store") + [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,load,mfc,store") (set_attr "mode" "DI") - (set_attr "length" "4,*,*,*,*,4,*,4,*,4,8,*,8,*")]) + (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,8,*,8,*")]) (define_insn "*movdi_64bit_mips16" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m") - (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") + (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d,*a"))] "TARGET_64BIT && TARGET_MIPS16 && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "move,move,move,arith,arith,load,const,load,store") + [(set_attr "type" "move,move,move,arith,arith,load,const,load,store,mfhilo") (set_attr "mode" "DI") (set_attr_alternative "length" [(const_int 4) @@ -3523,7 +3566,8 @@ (define_insn "*movdi_64bit_mips16" (const_int 8) (const_string "*") (const_string "*") - (const_string "*")])]) + (const_string "*") + (const_int 4)])]) ;; On the mips16, we can split ld $r,N($r) into an add and a load, @@ -3531,14 +3575,11 @@ (define_insn "*movdi_64bit_mips16" ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:DI 0 "register_operand") + [(set (match_operand:DI 0 "d_operand") (mem:DI (plus:DI (match_dup 0) (match_operand:DI 1 "const_int_operand"))))] "TARGET_64BIT && TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x10) || (INTVAL (operands[1]) >= 32 * 8 @@ -3589,7 +3630,7 @@ (define_expand "movsi" (define_insn "*movsi_internal" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") - (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))] + (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] "!TARGET_MIPS16 && (register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode))" @@ -3599,13 +3640,13 @@ (define_insn "*movsi_internal" (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,4,4,4,*,4,*")]) (define_insn "*movsi_mips16" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m") - (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") + (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d,*a"))] "TARGET_MIPS16 && (register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "type" "move,move,move,arith,arith,load,const,load,store") + [(set_attr "type" "move,move,move,arith,arith,load,const,load,store,mfhilo") (set_attr "mode" "SI") (set_attr_alternative "length" [(const_int 4) @@ -3620,20 +3661,18 @@ (define_insn "*movsi_mips16" (const_int 8) (const_string "*") (const_string "*") - (const_string "*")])]) + (const_string "*") + (const_int 4)])]) ;; On the mips16, we can split lw $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "d_operand") (mem:SI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand"))))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x80) || (INTVAL (operands[1]) >= 32 * 4 @@ -3669,12 +3708,9 @@ (define_split ;; instructions. (define_split - [(set (match_operand:SI 0 "register_operand") + [(set (match_operand:SI 0 "d_operand") (match_operand:SI 1 "const_int_operand"))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 0x100 && INTVAL (operands[1]) <= 0xff + 0x7f" [(set (match_dup 0) (match_dup 1)) @@ -3797,36 +3833,24 @@ (define_expand "movhi" }) (define_insn "*movhi_internal" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*x") - (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d") + (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))] "!TARGET_MIPS16 && (register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode))" - "@ - move\t%0,%1 - li\t%0,%1 - lhu\t%0,%1 - sh\t%z1,%0 - mt%0\t%1" - [(set_attr "type" "move,arith,load,store,mthilo") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,arith,load,store,mthilo,mfhilo") (set_attr "mode" "HI") - (set_attr "length" "4,4,*,*,4")]) + (set_attr "length" "4,4,*,*,4,4")]) (define_insn "*movhi_mips16" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m") - (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") + (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] "TARGET_MIPS16 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" - "@ - move\t%0,%1 - move\t%0,%1 - move\t%0,%1 - li\t%0,%1 - # - lhu\t%0,%1 - sh\t%1,%0" - [(set_attr "type" "move,move,move,arith,arith,load,store") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,move,move,arith,arith,load,store,mfhilo") (set_attr "mode" "HI") (set_attr_alternative "length" [(const_int 4) @@ -3839,6 +3863,7 @@ (define_insn "*movhi_mips16" (const_int 8) (const_int 12)) (const_string "*") + (const_string "*") (const_string "*")])]) @@ -3847,13 +3872,10 @@ (define_insn "*movhi_mips16" ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:HI 0 "register_operand") + [(set (match_operand:HI 0 "d_operand") (mem:HI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand"))))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x80) || (INTVAL (operands[1]) >= 32 * 2 @@ -3901,51 +3923,36 @@ (define_expand "movqi" }) (define_insn "*movqi_internal" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*x") - (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d") + (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))] "!TARGET_MIPS16 && (register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode))" - "@ - move\t%0,%1 - li\t%0,%1 - lbu\t%0,%1 - sb\t%z1,%0 - mt%0\t%1" - [(set_attr "type" "move,arith,load,store,mthilo") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,arith,load,store,mthilo,mfhilo") (set_attr "mode" "QI") - (set_attr "length" "4,4,*,*,4")]) + (set_attr "length" "4,4,*,*,4,4")]) (define_insn "*movqi_mips16" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m") - (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") + (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] "TARGET_MIPS16 && (register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" - "@ - move\t%0,%1 - move\t%0,%1 - move\t%0,%1 - li\t%0,%1 - # - lbu\t%0,%1 - sb\t%1,%0" - [(set_attr "type" "move,move,move,arith,arith,load,store") + { return mips_output_move (operands[0], operands[1]); } + [(set_attr "type" "move,move,move,arith,arith,load,store,mfhilo") (set_attr "mode" "QI") - (set_attr "length" "4,4,4,4,8,*,*")]) + (set_attr "length" "4,4,4,4,8,*,*,4")]) ;; On the mips16, we can split lb $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:QI 0 "register_operand") + [(set (match_operand:QI 0 "d_operand") (mem:QI (plus:SI (match_dup 0) (match_operand:SI 1 "const_int_operand"))))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && REG_P (operands[0]) - && M16_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x80) || (INTVAL (operands[1]) >= 32 @@ -4065,6 +4072,39 @@ (define_insn "*movdf_mips16" (set_attr "mode" "DF") (set_attr "length" "8,8,8,*,*")]) +;; 128-bit integer moves + +(define_expand "movti" + [(set (match_operand:TI 0) + (match_operand:TI 1))] + "TARGET_64BIT" +{ + if (mips_legitimize_move (TImode, operands[0], operands[1])) + DONE; +}) + +(define_insn "*movti" + [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,m,*a,*d") + (match_operand:TI 1 "move_operand" "di,m,dJ,*d*J,*a"))] + "TARGET_64BIT + && !TARGET_MIPS16 + && (register_operand (operands[0], TImode) + || reg_or_0_operand (operands[1], TImode))" + "#" + [(set_attr "type" "multi,load,store,multi,multi") + (set_attr "length" "8,*,*,8,8")]) + +(define_insn "*movti_mips16" + [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") + (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] + "TARGET_64BIT + && TARGET_MIPS16 + && (register_operand (operands[0], TImode) + || register_operand (operands[1], TImode))" + "#" + [(set_attr "type" "multi,multi,multi,multi,multi,load,store,multi") + (set_attr "length" "8,8,8,12,16,*,*,8")]) + ;; 128-bit floating point moves (define_expand "movtf" @@ -4123,7 +4163,7 @@ (define_split ;; When generating mips16 code, split moves of negative constants into ;; a positive "li" followed by a negation. (define_split - [(set (match_operand 0 "register_operand") + [(set (match_operand 0 "d_operand") (match_operand 1 "const_int_operand"))] "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0" [(set (match_dup 2) @@ -4172,44 +4212,33 @@ (define_insn "movv2sf_hardfloat_32bit" (set_attr "mode" "SF") (set_attr "length" "4,8,*,*,*,8,8,8,*,*")]) -;; The HI and LO registers are not truly independent. If we move an mthi -;; instruction before an mflo instruction, it will make the result of the -;; mflo unpredictable. The same goes for mtlo and mfhi. -;; -;; We cope with this by making the mflo and mfhi patterns use both HI and LO. -;; Operand 1 is the register we want, operand 2 is the other one. -;; -;; When generating VR4120 or VR4130 code, we use macc{,hi} and -;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal -;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130. - -(define_expand "mfhilo_" - [(set (match_operand:GPR 0 "register_operand") - (unspec:GPR [(match_operand:GPR 1 "register_operand") - (match_operand:GPR 2 "register_operand")] - UNSPEC_MFHILO))]) - -(define_insn "*mfhilo_" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") - (match_operand:GPR 2 "register_operand" "l,h")] - UNSPEC_MFHILO))] - "!ISA_HAS_MACCHI" - "mf%1\t%0" +;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p +;; for the reason why we can't just use (reg:GPR HI_REGNUM). +;; +;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI +;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards +;; and the errata related to -mfix-vr4130. +(define_insn "mfhi_" + [(set (match_operand:GPR 0 "register_operand" "=d") + (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")] + UNSPEC_MFHI))] + "" + { return ISA_HAS_MACCHI ? "macchi\t%0,%.,%." : "mfhi\t%0"; } [(set_attr "type" "mfhilo") - (set_attr "mode" "")]) + (set_attr "mode" "")]) -(define_insn "*mfhilo__macc" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") - (match_operand:GPR 2 "register_operand" "l,h")] - UNSPEC_MFHILO))] - "ISA_HAS_MACCHI" - "@ - macchi\t%0,%.,%. - macc\t%0,%.,%." - [(set_attr "type" "mfhilo") - (set_attr "mode" "")]) +;; Set the high part of a HI/LO value, given that the low part has +;; already been set. See mips_hard_regno_mode_ok_p for the reason +;; why we can't just use (reg:GPR HI_REGNUM). +(define_insn "mthi_" + [(set (match_operand:HILO 0 "register_operand" "=x") + (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ") + (match_operand:GPR 2 "register_operand" "l")] + UNSPEC_MTHI))] + "" + "mthi\t%z1" + [(set_attr "type" "mthilo") + (set_attr "mode" "SI")]) ;; Emit a doubleword move in which exactly one of the operands is ;; a floating-point register. We can't just emit two normal moves @@ -5120,11 +5149,10 @@ (define_insn "*lshrdi3_mips16" ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. (define_split - [(set (match_operand:GPR 0 "register_operand") - (any_shift:GPR (match_operand:GPR 1 "register_operand") + [(set (match_operand:GPR 0 "d_operand") + (any_shift:GPR (match_operand:GPR 1 "d_operand") (match_operand:GPR 2 "const_int_operand")))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE - && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16" [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8))) Index: gcc/config/mips/predicates.md =================================================================== --- gcc/config/mips/predicates.md 2008-06-09 21:42:44.000000000 +0100 +++ gcc/config/mips/predicates.md 2008-06-09 21:45:18.000000000 +0100 @@ -76,9 +76,11 @@ (define_predicate "const_0_or_1_operand" (ior (match_test "op == CONST0_RTX (GET_MODE (op))") (match_test "op == CONST1_RTX (GET_MODE (op))")))) -(define_predicate "fpr_operand" +(define_predicate "d_operand" (and (match_code "reg") - (match_test "FP_REG_P (REGNO (op))"))) + (match_test "TARGET_MIPS16 + ? M16_REG_P (REGNO (op)) + : GP_REG_P (REGNO (op))"))) (define_predicate "lo_operand" (and (match_code "reg") Index: gcc/testsuite/gcc.dg/torture/mips-hilo-1.c =================================================================== --- gcc/testsuite/gcc.dg/torture/mips-hilo-1.c 2008-06-09 21:42:44.000000000 +0100 +++ /dev/null 2008-06-08 10:32:14.544096500 +0100 @@ -1,73 +0,0 @@ -/* f1 checks that an mtlo is not moved before an mfhi. f2 does the same - for an mthi and an mflo. */ -/* { dg-do run { target mips*-*-* } } */ -/* { dg-options "-mtune=rm7000" } */ - -extern void abort (void); -extern void exit (int); - -#define DECLARE(TYPE) \ - TYPE __attribute__ ((noinline)) __attribute__ ((nomips16)) \ - f1##TYPE (TYPE x1, TYPE x2, TYPE x3) \ - { \ - TYPE t1, t2; \ - \ - asm ("mult\t%1,%2" : "=h" (t1) : "d" (x1), "d" (x2) : "lo"); \ - asm ("mflo\t%0" : "=r" (t2) : "l" (x3) : "hi"); \ - return t1 + t2; \ - } \ - \ - TYPE __attribute__ ((noinline)) __attribute__ ((nomips16)) \ - f2##TYPE (TYPE x1, TYPE x2, TYPE x3) \ - { \ - TYPE t1, t2; \ - \ - asm ("mult\t%1,%2" : "=l" (t1) : "d" (x1), "d" (x2) : "hi"); \ - asm ("mfhi\t%0" : "=r" (t2) : "h" (x3) : "lo"); \ - return t1 + t2; \ - } - -#define TEST(TYPE) \ - if (f1##TYPE (1, 2, 10) != 10) \ - abort (); \ - if (f2##TYPE (1, 2, 40) != 42) \ - abort () - -typedef char c; -typedef signed char sc; -typedef unsigned char uc; -typedef short s; -typedef unsigned short us; -typedef int i; -typedef unsigned int ui; -typedef long long ll; -typedef unsigned long long ull; - -DECLARE (c) -DECLARE (sc) -DECLARE (uc) -DECLARE (s) -DECLARE (us) -DECLARE (i) -DECLARE (ui) -#if defined (__mips64) -DECLARE (ll) -DECLARE (ull) -#endif - -int -main () -{ - TEST (c); - TEST (sc); - TEST (uc); - TEST (s); - TEST (us); - TEST (i); - TEST (ui); -#if defined (__mips64) - TEST (ll); - TEST (ull); -#endif - exit (0); -} Index: gcc/testsuite/gcc.target/mips/pr35232.c =================================================================== --- gcc/testsuite/gcc.target/mips/pr35232.c 2008-06-09 21:42:44.000000000 +0100 +++ /dev/null 2008-06-08 10:32:14.544096500 +0100 @@ -1,17 +0,0 @@ -/* { dg-do run } */ -/* { dg-mips-options "-O" } */ - -NOMIPS16 unsigned int -f1 (unsigned long long x) -{ - unsigned int r; - asm ("# %0" : "=a" (r) : "0" (x)); - asm ("# %0" : "=h" (r) : "0" (r)); - return r; -} - -int -main (void) -{ - return f1 (4) != 4; -} Index: gcc/testsuite/gcc.target/mips/fix-vr4130-1.c =================================================================== --- gcc/testsuite/gcc.target/mips/fix-vr4130-1.c 2008-06-09 21:42:44.000000000 +0100 +++ gcc/testsuite/gcc.target/mips/fix-vr4130-1.c 2008-06-09 21:45:18.000000000 +0100 @@ -1,4 +1,8 @@ /* { dg-do compile } */ /* { dg-mips-options "-march=vr4130 -mfix-vr4130" } */ -NOMIPS16 int foo (void) { int r; asm ("# foo" : "=h" (r)); return r; } +NOMIPS16 unsigned int +foo (unsigned int x, unsigned int y) +{ + return x % y; +} /* { dg-final { scan-assembler "\tmacchi\t" } } */ Index: gcc/testsuite/gcc.target/mips/fix-vr4130-3.c =================================================================== --- gcc/testsuite/gcc.target/mips/fix-vr4130-3.c 2008-06-09 21:42:44.000000000 +0100 +++ gcc/testsuite/gcc.target/mips/fix-vr4130-3.c 2008-06-09 21:45:18.000000000 +0100 @@ -1,10 +1,8 @@ /* { dg-do compile } */ /* { dg-mips-options "-march=vr4130 -mgp64 -mfix-vr4130" } */ -NOMIPS16 long long -foo (void) +NOMIPS16 unsigned long long +foo (unsigned long long x, unsigned long long y) { - long long r; - asm ("# foo" : "=h" (r)); - return r; + return x % y; } /* { dg-final { scan-assembler "\tdmacchi\t" } } */ Index: gcc/testsuite/gcc.target/mips/int-moves-1.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/int-moves-1.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,40 @@ +/* { dg-do compile { target mips16_attribute } } */ +/* { dg-mips-options "-mgp64 -msoft-float -O2 -EL" } */ +/* { dg-add-options mips16_attribute } */ + +typedef unsigned uint128_t __attribute__((mode(TI))); + +extern uint128_t g[16]; +extern unsigned char gstuff[0x10000]; + +NOMIPS16 uint128_t +foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} + +MIPS16 uint128_t +bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} Index: gcc/testsuite/gcc.target/mips/int-moves-2.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/int-moves-2.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,40 @@ +/* { dg-do compile { target mips16_attribute } } */ +/* { dg-mips-options "-mgp64 -msoft-float -O2 -EB" } */ +/* { dg-add-options mips16_attribute } */ + +typedef unsigned uint128_t __attribute__((mode(TI))); + +extern uint128_t g[16]; +extern unsigned char gstuff[0x10000]; + +NOMIPS16 uint128_t +foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} + +MIPS16 uint128_t +bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4, + uint128_t *x, unsigned char *lstuff) +{ + g[0] = i1; + g[1] = i2; + g[2] = i3; + g[3] = i4; + x[0] = x[4]; + x[1] = 0; + x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL; + x[3] = g[4]; + x[4] = *(uint128_t *) (lstuff + 0x7fff); + return *(uint128_t *) (gstuff + 0x7fff); +} Index: gcc/testsuite/gcc.target/mips/fix-r4000-1.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-1.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,6 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -O2 -dp" } */ +typedef int int32_t; +typedef int uint32_t; +int32_t foo (int32_t x, int32_t y) { return x * y; } +uint32_t bar (uint32_t x, uint32_t y) { return x * y; } +/* { dg-final { scan-assembler-times "[concat {\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-2.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-2.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */ +typedef int int32_t; +typedef long long int64_t; +int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-3.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-3.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */ +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-4.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-4.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */ +typedef int int32_t; +typedef long long int64_t; +int64_t foo (int32_t x, int32_t y) { return (int64_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-5.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-5.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */ +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +uint64_t foo (uint32_t x, uint32_t y) { return (uint64_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-6.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-6.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,6 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ +typedef long long int64_t; +typedef unsigned long long uint64_t; +int64_t foo (int64_t x, int64_t y) { return x * y; } +uint64_t bar (uint64_t x, uint64_t y) { return x * y; } +/* { dg-final { scan-assembler-times "[concat {\tdmult\t\$[45],\$[45][^\n]+muldi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-7.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-7.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */ +typedef long long int64_t; +typedef int int128_t __attribute__((mode(TI))); +int64_t foo (int64_t x, int64_t y) { return ((int128_t) x * y) >> 64; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-8.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-8.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,7 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */ +typedef unsigned long long uint64_t; +typedef unsigned int uint128_t __attribute__((mode(TI))); +uint64_t foo (uint64_t x, uint64_t y) { return ((uint128_t) x * y) >> 64; } +/* ??? A highpart pattern would be a better choice, but we currently + don't use them. */ +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-9.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-9.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */ +typedef long long int64_t; +typedef int int128_t __attribute__((mode(TI))); +int128_t foo (int64_t x, int64_t y) { return (int128_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-10.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-10.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,8 @@ +/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication + result to $2, which prevents the register allocators from storing the + multiplication result in $2. */ +/* { dg-mips-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */ +typedef unsigned long long uint64_t; +typedef unsigned int uint128_t __attribute__((mode(TI))); +uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; } +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-11.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-11.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,4 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ +typedef long long int64_t; +int64_t foo (int64_t x) { return x / 11993; } +/* { dg-final { scan-assembler "[concat {\tdmult\t\$4,\$[0-9]+[^\n]+smuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/fix-r4000-12.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/fix-r4000-12.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,4 @@ +/* { dg-mips-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */ +typedef unsigned long long uint64_t; +uint64_t foo (uint64_t x) { return x / 11993; } +/* { dg-final { scan-assembler "[concat {\tdmultu\t\$4,\$[0-9]+[^\n]+umuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */ Index: gcc/testsuite/gcc.target/mips/timode-1.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/timode-1.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,65 @@ +/* { dg-mips-options "-mgp64" } */ +typedef int int128_t __attribute__((mode(TI))); +typedef unsigned int uint128_t __attribute__((mode(TI))); + +#define UINT128_CONST(A, B) \ + (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL)) + +volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222); +volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003); +volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666); +volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500); +volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66); +volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100); +volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66); +volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66); +volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660); +volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6); +volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6); + +volatile int amount = 4; + +volatile uint128_t result; + +int +main (void) +{ + result = a * b; + if (result != c) + return 1; + + result = c + d; + if (result != e) + return 1; + + result = e - d; + if (result != c) + return 1; + + result = d & e; + if (result != f) + return 1; + + result = d ^ e; + if (result != g) + return 1; + + result = d | e; + if (result != h) + return 1; + + result = g << amount; + if (result != i) + return 1; + + result = g >> amount; + if (result != j) + return 1; + + result = (int128_t) g >> amount; + if (result != k) + return 1; + + return 0; +} +/* { dg-final { scan-assembler-not "\tjal" } } */ Index: gcc/testsuite/gcc.target/mips/timode-2.c =================================================================== --- /dev/null 2008-06-08 10:32:14.544096500 +0100 +++ gcc/testsuite/gcc.target/mips/timode-2.c 2008-06-09 21:45:18.000000000 +0100 @@ -0,0 +1,64 @@ +/* { dg-do run { target mips64 } } */ +typedef int int128_t __attribute__((mode(TI))); +typedef unsigned int uint128_t __attribute__((mode(TI))); + +#define UINT128_CONST(A, B) \ + (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL)) + +volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222); +volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003); +volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666); +volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500); +volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66); +volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100); +volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66); +volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66); +volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660); +volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6); +volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6); + +volatile int amount = 4; + +volatile uint128_t result; + +int +main (void) +{ + result = a * b; + if (result != c) + return 1; + + result = c + d; + if (result != e) + return 1; + + result = e - d; + if (result != c) + return 1; + + result = d & e; + if (result != f) + return 1; + + result = d ^ e; + if (result != g) + return 1; + + result = d | e; + if (result != h) + return 1; + + result = g << amount; + if (result != i) + return 1; + + result = g >> amount; + if (result != j) + return 1; + + result = (int128_t) g >> amount; + if (result != k) + return 1; + + return 0; +} From macro@linux-mips.org Mon Jun 9 22:54:46 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Jun 2008 22:54:48 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:6386 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S20030582AbYFIVyq (ORCPT ); Mon, 9 Jun 2008 22:54:46 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m59Ls324030005; Mon, 9 Jun 2008 23:54:03 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m59Ls2tl030001; Mon, 9 Jun 2008 22:54:02 +0100 Date: Mon, 9 Jun 2008 22:54:01 +0100 (BST) From: "Maciej W. Rozycki" To: Richard Sandiford cc: Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org Subject: Re: Changing the treatment of the MIPS HI and LO registers In-Reply-To: <87zlpuxqfb.fsf@firetop.home> Message-ID: References: <87tzgj4nh6.fsf@firetop.home> <87abib4d9t.fsf@firetop.home> <87r6bm1ebd.fsf@firetop.home> <878wxtvarg.fsf@firetop.home> <8763stz2p3.fsf@firetop.home> <87zlpuxqfb.fsf@firetop.home> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19463 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 9 Jun 2008, Richard Sandiford wrote: > Please shout if you find anything wrong with either the patch or > the documentation changes. Lacking the time to review your changes or at least test at the run time (sorry!) I trust you have done a decent job as usually. Perhaps someone else can to that. Otherwise the results will come back and haunt you in some two years or suchlike when people start using this version of GCC to build the kernel. ;) To give you an indicator -- I am still using 4.1.2 and will keep doing so for another year or so. I may skip a version or two when I finally decide to upgrade though. Maciej From huacai.chen@intel.com Tue Jun 10 02:05:16 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Jun 2008 02:05:19 +0100 (BST) Received: from mga02.intel.com ([134.134.136.20]:34153 "EHLO mga02.intel.com") by ftp.linux-mips.org with ESMTP id S20033495AbYFJBFQ (ORCPT ); Tue, 10 Jun 2008 02:05:16 +0100 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 09 Jun 2008 18:02:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.27,615,1204531200"; d="scan'208";a="392776074" Received: from fmsmsx334.amr.corp.intel.com ([132.233.42.1]) by orsmga001.jf.intel.com with ESMTP; 09 Jun 2008 18:04:58 -0700 Received: from pdsmsx411.ccr.corp.intel.com ([172.16.12.89]) by fmsmsx334.amr.corp.intel.com with Microsoft SMTPSVC(6.0.3790.1830); Mon, 9 Jun 2008 18:05:08 -0700 Received: from pdsmsx415.ccr.corp.intel.com ([172.16.12.184]) by pdsmsx411.ccr.corp.intel.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 10 Jun 2008 09:05:05 +0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: 7bit Subject: RE: [patch]modify the MIPS CPU classfication Date: Tue, 10 Jun 2008 09:05:08 +0800 Message-ID: <42DFA526FC41B1429CE7279EF83C6BDC01404431@pdsmsx415.ccr.corp.intel.com> In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [patch]modify the MIPS CPU classfication Thread-Index: AcjKLQ3t3yNX5I2dSn6iZ6hMyMZZswAaL/6g References: <42DFA526FC41B1429CE7279EF83C6BDC01404341@pdsmsx415.ccr.corp.intel.com> From: "Chen, Huacai" To: "Maciej W. Rozycki" Cc: , X-OriginalArrivalTime: 10 Jun 2008 01:05:05.0973 (UTC) FILETIME=[051CAE50:01C8CA96] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19464 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: huacai.chen@intel.com Precedence: bulk X-list: linux-mips This is the new patch sorted numerically. Signed-off-by: Huacai Chen ---- diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 1c35cac..229a786 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -66,8 +66,10 @@ #define PRID_IMP_RM7000 0x2700 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ #define PRID_IMP_RM9000 0x3400 +#define PRID_IMP_LOONGSON1 0x4200 #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 +#define PRID_IMP_LOONGSON2 0x6300 #define PRID_IMP_UNKNOWN 0xff00 @@ -90,8 +92,6 @@ #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 -#define PRID_IMP_LOONGSON1 0x4200 -#define PRID_IMP_LOONGSON2 0x6300 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE ---- -----Original Message----- From: macro@cliff.in.clinika.pl [mailto:macro@cliff.in.clinika.pl] On Behalf Of Maciej W. Rozycki Sent: 2008$BG/(J6$B7n(J9$BF|(J 20:33 To: Chen, Huacai Cc: linux-mips@linux-mips.org; linux-kernel@vger.kernel.org Subject: Re: [patch]modify the MIPS CPU classfication On Mon, 9 Jun 2008, Chen, Huacai wrote: > The company ID of Loongson1/Loongson2 is PRID_COMP_LEGACY, but they were > classified in the list whoes company ID is PRID_COMP_MIPS. This patch > move them to the right place. Note the list is currently sorted numerically and meant to stay such. Please update your patch accordingly. Maciej From blf.ireland@gmail.com Tue Jun 10 10:32:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Jun 2008 10:32:36 +0100 (BST) Received: from rv-out-0708.google.com ([209.85.198.250]:43205 "EHLO rv-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S20034734AbYFJJcd (ORCPT ); Tue, 10 Jun 2008 10:32:33 +0100 Received: by rv-out-0708.google.com with SMTP id c5so2251753rvf.24 for ; Tue, 10 Jun 2008 02:32:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:sender :to:subject:cc:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:references :x-google-sender-auth; bh=m6hcMqdqR3dYKK3RKtnKC75JxTQKkLLNjByq7dqgCRg=; b=rxXS13friYsfQvskLu5syWfFlM5JDVTtDpkTJd+XNZFUTLVqGzh2k9k52JutIhNHrW 29ZZ/cnwD0zGKgXVEXoP5Z0Zc5TDe6tKkHuyk/kbk40wn5PL50ReRFjGM3ZMzA4Rv9JB luknjANcVAHP/667+YjVSnjp48AXUlBoSz8eY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:sender:to:subject:cc:in-reply-to:mime-version :content-type:content-transfer-encoding:content-disposition :references:x-google-sender-auth; b=V2uWoSm5MbHD1+YOwb0x7KY8Rul0DXy9AsabA1/TAL9O3gwQR+tX4UW8mXzis2DnTS ugJSZMuCPZetazVFtlx+4HtpDd2QbEAHnvonI3V0r+3pnO5UQ5T2uGzB+KuAsPKqE3lR xD1aSZuGykiexgBRnssMD1Z5pKXS4P3ZKL0Jo= Received: by 10.141.89.13 with SMTP id r13mr2834242rvl.177.1213090349448; Tue, 10 Jun 2008 02:32:29 -0700 (PDT) Received: by 10.141.185.4 with HTTP; Tue, 10 Jun 2008 02:32:29 -0700 (PDT) Message-ID: Date: Tue, 10 Jun 2008 11:32:29 +0200 From: "Brian Foster" To: "Kevin D. Kissell" , "Andrew Dyer" , "Thiemo Seufer" Subject: Re: Adding(?) XI support to MIPS-Linux? Cc: linux-mips@linux-mips.org In-Reply-To: <200806101119.06227.brian.foster@innova-card.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <200806091658.10937.brian.foster@innova-card.com> <484D856B.5030306@paralogos.com> <20080609204627.GE11233@networkno.de> <200806101119.06227.brian.foster@innova-card.com> X-Google-Sender-Auth: c5035d3b1c5fd2c5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19465 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips 1) Date: Mon, 09 Jun 2008 21:32:59 +0200 1) From: "Kevin D. Kissell" 1) 1) Brian Foster wrote: 1) > As far as I am aware, XI is part of the SMARTMIPS extension, 1) > and I _think_ SMARTMIPS is only implemented by the 4KS cores? 1) 1) That is correct, though there has long been interest in having XI/RI 1) as an option for non-SmartMIPS cores and I would not be surprised if 1) sooner or later it became more generally available. Ok, thanks for the confirmation. I'll keep this in mind w.r.t. to any proposed patches. 1) > Whilst other companies have licensed that core from MIPS, to 1) > the best of my knowledge the SoC I'm concerned with (Innova 1) > Card's USIP Pro) is the only one running Linux. [ ... ] 1) 1) I believe that there is at least one other 4KS-family customer working 1) with Linux, but they haven't been nearly as active as InnovaCard. 1) I had some email exchanges with someone who was working on their kernel 1) a couple of years back about this very topic. Indeed, I thought that 1) they submitted some patches for basic RI/XI support at one point. 1) Scan the linux-mips.org archives, if they survived the rehosting. I just spent a fair bit of the morning searching the archives, and cannot find anything related to 4KS, SmartMIPS, XI, or RI (except odd mentions here and there, none(?) of substance (on this subject), and all seeming to involve Innova Card). I'm *very* interested in seeing/learning what others have done or tried, so if you or anyone else has any information/whatever that you can share, please let me know! Thanks. 1)[ ... ] 1) > Broadly, what I'm trying to say is I don't want to touch gcc 1) > (and/or binutils) and am unconvinced I have to. But I'm very 1) > much open to correction here! 1) > 1) > The x86 (including amd64) and, AFAIK, SuperH (sh) Linux kernels 1) > now support NX or equivalent [ ... ]. 1) > I understand they have support for specially-marked binaries to 1) > have executable stacks (i.e., binutils/gcc mods, which I want to 1) > avoid). 1) 1) Well, strictly speaking, you wouldn't actually *need* to modify 1) binutils to make specially tagged binaries. [ ... ] Agreed. I was speaking loosely. 1) In the longer term, I'd argue that if there's support for appropriate 1) binary tagging in the x86 tools, that support should simply be enabled 1) for MIPS targets and any other non-x86 archiectures with such support 1) (e.g. Alpha, if anyone still uses them). Agreed. This is all *speculative* ATM. There seems to be a rational argument that for the specific situation I'm concerned with, an absolute imposition of non-executable stack(+data) would be "better". In the more general situation, including the longer term, tagged binaries are (very probably), perhaps unfortunately, desirable. 2) Date: Mon, 9 Jun 2008 21:46:27 +0100 2) From: Thiemo Seufer 2) 2) Kevin D. Kissell wrote: 2)[ ... ] 2) > Well, strictly speaking, you wouldn't actually *need* to modify 2) > binutils to make specially tagged binaries. [ ... ] 2) 2) This exists already in ld's -z execstack/noexecstack feature. Good point. Thanks for the reminder. 2) It is not used by default because too many things depend on executable 2) stacks on MIPS. Ah! Can you be more specific please? At the present time I'm only aware of three situations where executable stacks are magically used ("magic" meaning it's being done without the programmer explicitly coding it): 1. sigreturn. 2. something to do with FPU emulation? 3. pointer to a nested function (gcc extension). And, significantly, I am do not know of any need for the kernel-mode stacks to be executable. Except, perhaps, for case 3, the above are (should be?) user-land only. There are also "non-magic" users (JIT in some JVMs is, I believe, the usual example). These deliberate users, and case 3, I want to be able to argue I can blow off in the specific circumstance I am concerned about. That is, they simply fail. Always. But as said above, in general and for the longer term, that's presumably not acceptable (i.e., marked binaries are needed). cheers! -blf- -- "How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools." | http://www.stopesso.com From ths@networkno.de Tue Jun 10 10:57:04 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Jun 2008 10:57:06 +0100 (BST) Received: from relay01.mx.bawue.net ([193.7.176.67]:62433 "EHLO relay01.mx.bawue.net") by ftp.linux-mips.org with ESMTP id S20034741AbYFJJ5E (ORCPT ); Tue, 10 Jun 2008 10:57:04 +0100 Received: from lagash (88-106-136-149.dynamic.dsl.as9105.com [88.106.136.149]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by relay01.mx.bawue.net (Postfix) with ESMTP id E0E7748916; Tue, 10 Jun 2008 11:57:03 +0200 (CEST) Received: from ths by lagash with local (Exim 4.69) (envelope-from ) id 1K60b8-0004JS-Uu; Tue, 10 Jun 2008 10:57:02 +0100 Date: Tue, 10 Jun 2008 10:57:02 +0100 From: Thiemo Seufer To: Brian Foster Cc: "Kevin D. Kissell" , Andrew Dyer , linux-mips@linux-mips.org Subject: Re: Adding(?) XI support to MIPS-Linux? Message-ID: <20080610095702.GG11233@networkno.de> References: <200806091658.10937.brian.foster@innova-card.com> <484D856B.5030306@paralogos.com> <20080609204627.GE11233@networkno.de> <200806101119.06227.brian.foster@innova-card.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19466 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Brian Foster wrote: [snip] > 2) Kevin D. Kissell wrote: > 2)[ ... ] > 2) > Well, strictly speaking, you wouldn't actually *need* to modify > 2) > binutils to make specially tagged binaries. [ ... ] > 2) > 2) This exists already in ld's -z execstack/noexecstack feature. > > Good point. Thanks for the reminder. > > 2) It is not used by default because too many things depend on executable > 2) stacks on MIPS. > > Ah! Can you be more specific please? At the present time > I'm only aware of three situations where executable stacks > are magically used ("magic" meaning it's being done without > the programmer explicitly coding it): > > 1. sigreturn. > 2. something to do with FPU emulation? > 3. pointer to a nested function (gcc extension). Those, plus manually coded trampolines in e.g. foreign function interfacing (which are typically hidden in some library). I don't know if you can ignore that completely. :-) > And, significantly, I am do not know of any need for the > kernel-mode stacks to be executable. Except, perhaps, > for case 3, the above are (should be?) user-land only. AFAIK nested functions are frowned upon in kernelspace. Thiemo From ddaney@avtrex.com Tue Jun 10 17:21:56 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Jun 2008 17:21:59 +0100 (BST) Received: from smtp1.dnsmadeeasy.com ([205.234.170.144]:21889 "EHLO smtp1.dnsmadeeasy.com") by ftp.linux-mips.org with ESMTP id S29038288AbYFJQV4 (ORCPT ); Tue, 10 Jun 2008 17:21:56 +0100 Received: from smtp1.dnsmadeeasy.com (localhost [127.0.0.1]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP id 9EBDB31E0C9; Tue, 10 Jun 2008 16:21:55 +0000 (UTC) X-Authenticated-Name: js.dnsmadeeasy X-Transit-System: In case of SPAM please contact abuse@dnsmadeeasy.com Received: from avtrex.com (unknown [67.116.42.147]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP; Tue, 10 Jun 2008 16:21:55 +0000 (UTC) Received: from dl2.hq2.avtrex.com ([192.168.7.26]) by avtrex.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 10 Jun 2008 09:21:43 -0700 Message-ID: <484EAA16.80903@avtrex.com> Date: Tue, 10 Jun 2008 09:21:42 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: Thiemo Seufer Cc: Brian Foster , "Kevin D. Kissell" , Andrew Dyer , linux-mips@linux-mips.org Subject: Re: Adding(?) XI support to MIPS-Linux? References: <200806091658.10937.brian.foster@innova-card.com> <484D856B.5030306@paralogos.com> <20080609204627.GE11233@networkno.de> <200806101119.06227.brian.foster@innova-card.com> <20080610095702.GG11233@networkno.de> In-Reply-To: <20080610095702.GG11233@networkno.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 10 Jun 2008 16:21:43.0696 (UTC) FILETIME=[124F3900:01C8CB16] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19467 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@avtrex.com Precedence: bulk X-list: linux-mips Thiemo Seufer wrote: > Brian Foster wrote: > [snip] > >> 2) Kevin D. Kissell wrote: >> 2)[ ... ] >> 2) > Well, strictly speaking, you wouldn't actually *need* to modify >> 2) > binutils to make specially tagged binaries. [ ... ] >> 2) >> 2) This exists already in ld's -z execstack/noexecstack feature. >> >> Good point. Thanks for the reminder. >> >> 2) It is not used by default because too many things depend on executable >> 2) stacks on MIPS. >> >> Ah! Can you be more specific please? At the present time >> I'm only aware of three situations where executable stacks >> are magically used ("magic" meaning it's being done without >> the programmer explicitly coding it): >> >> 1. sigreturn. >> 2. something to do with FPU emulation? >> 3. pointer to a nested function (gcc extension). >> > > Those, plus manually coded trampolines in e.g. foreign function > interfacing (which are typically hidden in some library). I don't > know if you can ignore that completely. :-) > > The trampolines in libffi are user allocated, so there is a choice of where to place them. In libgcj (which uses the libffi trampolines) the trampolines are allocated on the heap and care is taken to set the execute permissions on the memory in question. Other users may have problems, but by now most code should work as XI support has been present on x86 for quite some time now. As long as there is a mechanism to make user space stacks (and heap) executable, there should be no problem. People running code that requires it can switch off the XI support. David Daney >> And, significantly, I am do not know of any need for the >> kernel-mode stacks to be executable. Except, perhaps, >> for case 3, the above are (should be?) user-land only. >> > > AFAIK nested functions are frowned upon in kernelspace. > > > Thiemo > > From clem.taylor@gmail.com Tue Jun 10 22:30:36 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Jun 2008 22:30:38 +0100 (BST) Received: from fk-out-0910.google.com ([209.85.128.187]:43256 "EHLO fk-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S28596368AbYFJVag (ORCPT ); Tue, 10 Jun 2008 22:30:36 +0100 Received: by fk-out-0910.google.com with SMTP id b27so1615417fka.0 for ; Tue, 10 Jun 2008 14:30:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:mime-version:content-type:content-transfer-encoding :content-disposition; bh=8PdoJ2MYVvVvw2kpR2m8vAmcTFqP0ZWz0a2GyawZNgM=; b=W1xs0hqycO2/s4UwRPYwlSGytc7WFvvT0Kqjj8wyqW/kuoPW88VNOgdjuPvt1eWYLU 6EVZpqjA7IGvNnEh02djJ98YkIuYYQk9sqxoeEvyF2RPflC5adVaTaRBWVq00kquSd6E rhXy6XmIAy/DNMJx13EMQauqa2Z79/fscOLME= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:mime-version:content-type :content-transfer-encoding:content-disposition; b=EnF7kOwXDow81nSZSjHCxhtDIbbSd3WNZhiqol8KA5OuELOWsXtKrw6nwXpbkNr8k3 W+D59SiAmH+RJwveyc3XvueIxdpO6l66nBvfiKZLrdAEnR/pRkOD6z18Mb8UichxzWjS zY6sukwo9Jj8dqfw+Ci176afJ0sVPPB5G408Q= Received: by 10.82.178.11 with SMTP id a11mr373976buf.47.1213133435067; Tue, 10 Jun 2008 14:30:35 -0700 (PDT) Received: by 10.82.146.3 with HTTP; Tue, 10 Jun 2008 14:30:35 -0700 (PDT) Message-ID: Date: Tue, 10 Jun 2008 17:30:35 -0400 From: "Clem Taylor" To: linux-mips@linux-mips.org Subject: early hang in 2.6.24 on au1550 (MIPSLE) MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19468 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: clem.taylor@gmail.com Precedence: bulk X-list: linux-mips A few months ago I switched from 2.6.16.16 to 2.6.24 on an AU1550 (MIPSLE) system. I started rolling this out to more systems, getting ready for a new software release and discovered that on fresh powerup, the 2.6.24 kernel sometimes (1 in 10-25 power cycles) fails to start. The bootloader (uboot) decompresses the kernel from a jffs2 filesystem and then jumps to it, but I don't get any serial messages from the kernel. If I switch back to the 2.6.16.16 kernel, everything is happy. The annoying thing is that I have been unable to catch the problem with the JTAG debugger connected, so I'm not sure where it is hanging. I've been looking at diffs in the arch/mips tree and nothing has jumped out at me. I don't think this is a hardware problem, this hardware platform has been fairly stable and it works just fine with the older kernel. I was wondering if anyone has any suggestions where I might look? Also, is anyone using 2.6.24 with a Au1550? Thanks, Clem From ricmm@gentoo.org Wed Jun 11 01:57:22 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 01:57:25 +0100 (BST) Received: from rs25s3.datacenter.cha.cantv.net ([200.44.33.34]:60091 "EHLO rs25s3.datacenter.cha.cantv.net") by ftp.linux-mips.org with ESMTP id S29039479AbYFKA5W (ORCPT ); Wed, 11 Jun 2008 01:57:22 +0100 X-DNSBL-MILTER: Passed Received: from [192.168.0.3] (dc9d0839d.dslam-172-17-49-239-0232-299.dsl.cantv.net [201.208.131.157] (may be forged)) by rs25s3.datacenter.cha.cantv.net (8.13.8/8.13.0/3.0) with ESMTP id m5B0vCpk007472; Tue, 10 Jun 2008 20:27:13 -0430 X-Matched-Lists: [] Message-ID: <484F22EE.5090601@gentoo.org> Date: Tue, 10 Jun 2008 20:27:18 -0430 From: Ricardo Mendoza User-Agent: Thunderbird 2.0.0.6 (X11/20071112) MIME-Version: 1.0 To: Clem Taylor CC: linux-mips@linux-mips.org Subject: Re: early hang in 2.6.24 on au1550 (MIPSLE) References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Virus-Scanned: ClamAV version 0.93.1, clamav-milter version 0.93.1 on 10.128.1.151 X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19469 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ricmm@gentoo.org Precedence: bulk X-list: linux-mips Clem Taylor wrote: > A few months ago I switched from 2.6.16.16 to 2.6.24 on an AU1550 > (MIPSLE) system. I started rolling this out to more systems, getting > ready for a new software release and discovered that on fresh powerup, > the 2.6.24 kernel sometimes (1 in 10-25 power cycles) fails to start. > The bootloader (uboot) decompresses the kernel from a jffs2 filesystem > and then jumps to it, but I don't get any serial messages from the > kernel. > > If I switch back to the 2.6.16.16 kernel, everything is happy. The > annoying thing is that I have been unable to catch the problem with > the JTAG debugger connected, so I'm not sure where it is hanging. > > I've been looking at diffs in the arch/mips tree and nothing has > jumped out at me. I don't think this is a hardware problem, this > hardware platform has been fairly stable and it works just fine with > the older kernel. I was wondering if anyone has any suggestions where > I might look? Also, is anyone using 2.6.24 with a Au1550? Nothing? What about time layer switch to make use of cevt and csrc devices for example. Gotta keep in mind that 2.6.16 is archaic; you should write an early printk implementation for au1550 and see where it dies. With another board once I experienced something similar and it happened to be timer interrupts getting skipped at times, so, you might be dying in calibration if your problem is similar. Ricardo From ralf@linux-mips.org Wed Jun 11 10:06:23 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 10:06:26 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:46017 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20024548AbYFKJGX (ORCPT ); Wed, 11 Jun 2008 10:06:23 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5B963HE030040; Wed, 11 Jun 2008 10:06:03 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5B961sC030027; Wed, 11 Jun 2008 10:06:01 +0100 Date: Wed, 11 Jun 2008 10:06:01 +0100 From: Ralf Baechle To: "Kevin D. Kissell" Cc: Brian Foster , linux-mips@linux-mips.org, Andrew Dyer Subject: Re: Adding(?) XI support to MIPS-Linux? Message-ID: <20080611090601.GB19755@linux-mips.org> References: <200806091658.10937.brian.foster@innova-card.com> <484D856B.5030306@paralogos.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <484D856B.5030306@paralogos.com> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19470 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 09, 2008 at 09:32:59PM +0200, Kevin D. Kissell wrote: > That is correct, though there has long been interest in having XI/RI as an > option > for non-SmartMIPS cores and I would not be surprised if sooner or later it > became more generally available. Cavium has it in their 64-bit core. I haven't verified this in the docs but apparently it is meant to be compatible with the old SmartMIPS ASE for MIPS32. Ralf From kevink@mips.com Wed Jun 11 10:36:24 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 10:36:27 +0100 (BST) Received: from mx.mips.com ([63.167.95.198]:50913 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S20039894AbYFKJfM (ORCPT ); Wed, 11 Jun 2008 10:35:12 +0100 Received: from mercury.mips.com (mercury [192.168.64.101]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id m5B9XgXo014244; Wed, 11 Jun 2008 02:33:42 -0700 (PDT) Received: from [127.0.0.1] (grendel [192.168.236.16]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id m5B9YIYo029524; Wed, 11 Jun 2008 02:34:34 -0700 (PDT) Message-ID: <484F9C76.4030104@mips.com> Date: Wed, 11 Jun 2008 11:35:50 +0200 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.14 (Windows/20080421) MIME-Version: 1.0 To: Ralf Baechle CC: "Kevin D. Kissell" , Brian Foster , linux-mips@linux-mips.org, Andrew Dyer Subject: Re: Adding(?) XI support to MIPS-Linux? References: <200806091658.10937.brian.foster@innova-card.com> <484D856B.5030306@paralogos.com> <20080611090601.GB19755@linux-mips.org> In-Reply-To: <20080611090601.GB19755@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19471 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@mips.com Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > On Mon, Jun 09, 2008 at 09:32:59PM +0200, Kevin D. Kissell wrote: > > >> That is correct, though there has long been interest in having XI/RI as an option for non-SmartMIPS cores and I would not be surprised if sooner or later it became more generally available. >> > > Cavium has it in their 64-bit core. I haven't verified this in the docs > but apparently it is meant to be compatible with the old SmartMIPS ASE > for MIPS32. > Do check the documentation. I can't comment officially, but I can observe that, in the hypothetical case where you'd want XI/RI semantics in a 64-bit processor, you might use exactly the same semantics (and therefore the same kernel C code support), but you might want to use different bits for XI/RI in a 64-bit TLB entry than in a 32-bit TLB entry (and therefore different header file definitions). Regards, Kevin K. From ralf@linux-mips.org Wed Jun 11 11:43:52 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 11:43:54 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:22695 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20024673AbYFKKnw (ORCPT ); Wed, 11 Jun 2008 11:43:52 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5BAhXax008197; Wed, 11 Jun 2008 11:43:33 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5BAhRHO008156; Wed, 11 Jun 2008 11:43:27 +0100 Date: Wed, 11 Jun 2008 11:43:27 +0100 From: Ralf Baechle To: Daniel Laird Cc: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: [PATCH] : Add support for NXP PNX833x (STB222/5) into linux kernel Message-ID: <20080611104327.GA777@linux-mips.org> References: <64660ef00806060132j1aab8d9fh968cbf3f2fc56bc2@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <64660ef00806060132j1aab8d9fh968cbf3f2fc56bc2@mail.gmail.com> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19472 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jun 06, 2008 at 09:32:15AM +0100, Daniel Laird wrote: > > > +#if defined(CONFIG_SATA_PNX833X) || defined(CONFIG_SATA_PNX833X_MODULE) > > > +static struct resource pnx833x_sata_resources[] = { > > > + [0] = { > > > + .start = PNX8335_SATA_PORTS_START, > > > + .end = PNX8335_SATA_PORTS_END, > > > + .flags = IORESOURCE_MEM, > > > + }, > > > + [1] = { > > > + .start = PNX8335_PIC_SATA_INT, > > > + .end = PNX8335_PIC_SATA_INT, > > > + .flags = IORESOURCE_IRQ, > > > + }, > > > +}; > > > + > > > +static struct platform_device pnx833x_sata_device = { > > > + .name = "pnx833x-sata", > > > + .id = -1, > > > + .num_resources = ARRAY_SIZE(pnx833x_sata_resources), > > > + .resource = pnx833x_sata_resources, > > > +}; > > > +#endif > > > > What about defining those resources anyway ? > > > + > > > +#if defined(CONFIG_MTD_NAND_PLATFORM) || > > > defined(CONFIG_MTD_NAND_PLATFORM_MODULE) > > > > Same here and others below too. > > > Is there any harm in having them always defined even if not > implemented? I was playing safe. You normally should register all platform devices based on their presence on the platform without consideration of the drivers actually being enabled. The Linux driver philosophy is that a driver can be enabled, compiled as a module and loaded separately from the kernel build and the driver should still be working. That will only work if the driver and its resources are always in - even at the (low!) price of being unused on a particular platform. It also helps tools that use sysfs to query hardware configuration. > > > +{ > > > + printk(KERN_ALERT "\n\nSystem halted.\n\n"); > > > + > > > + while (1) > > > + __asm__ __volatile__ ("wait"); > > > +} > > > > You might want to use cpu_relax(); instead of the assembly wait instruction. > > > Sounds good. Almost. cpu_relax() is defined to just barrier() on MIPS since there isn't really very much we could or need to do in tight loop - unlike the infamous Pentium 4 netburst architecture which burns serious amounts of power in such a loop. So best keep it as it is for now. The issue deserves a better solution though but that's beyond the scope of your patch. > > > +void pnx833x_machine_power_off(void) > > > +{ > > > + printk(KERN_ALERT "\n\nPower off not implemented."); > > > + pnx833x_machine_halt(); > > > +} > > > > And put some less alarming message here, like "*** You can safely turn off the > > board". No message at all. It's userspace which is supposed to communicate with the user not the kernel. Ralf From daniel.j.laird@googlemail.com Wed Jun 11 11:53:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 11:53:28 +0100 (BST) Received: from an-out-0708.google.com ([209.85.132.243]:12242 "EHLO an-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S20025437AbYFKKxZ (ORCPT ); Wed, 11 Jun 2008 11:53:25 +0100 Received: by an-out-0708.google.com with SMTP id d11so709092and.64 for ; Wed, 11 Jun 2008 03:53:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:cc:mime-version:content-type:content-transfer-encoding :content-disposition; bh=tK16nDURX+fBdd2iwvK12p+XVtEhh2WYxSYGULRFdp0=; b=Ece54CN2J31SOmCLvn/FYh3bIZIilt7Fp/kGgL4yoCZblF/CbOHxDlxZWkFmtneUK4 fBYywPQGW6K62K0IUOU1L1jtKEfEe3XrNsIMTI4d5Akr7QvdGF2jOeiF+7Re5tdgELgP tvQLUPFMjOXVHMxIsG7A1ocIC51sU0qDaqbIQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=message-id:date:from:to:subject:cc:mime-version:content-type :content-transfer-encoding:content-disposition; b=BHE9+AAmUga40wu+rcLfF50o5NLDqxlLJC4ircB0z8B4R/QZzknQF+A/hEwwlpCG4x PNvYrAi+D7WhIwqXfJ4Z8amgupsCYsW+Zdm8rT9H2TWvApjhQs3pI8ZhnX/LMcV/gIrT S1tm0LiS93+HR3YRgh1l+rVE5n0CQDHcLBI5U= Received: by 10.100.229.12 with SMTP id b12mr7336275anh.60.1213181604106; Wed, 11 Jun 2008 03:53:24 -0700 (PDT) Received: by 10.90.70.11 with HTTP; Wed, 11 Jun 2008 03:53:24 -0700 (PDT) Message-ID: <64660ef00806110353p66608c43ta1e1995aef8b8f6f@mail.gmail.com> Date: Wed, 11 Jun 2008 11:53:24 +0100 From: "Daniel Laird" To: "Ralf Baechle" Subject: Re: [PATCH] : Add support for NXP PNX833x (STB222/5) into linux kernel Cc: "Florian Fainelli" , linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19473 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: daniel.j.laird@googlemail.com Precedence: bulk X-list: linux-mips On the second patch I submitted I changed platform.c as requested so it registers all resources without the #ifdefs. I also found that cpu_relax was not quite what i wanted so left the while(1) loop for halt. I have left printk kernel messages in as well (can remove if preferred). If you require me to re-submit this second patch let me know (either as attachment or inline). I also split the ip3902, ip0105 and submitted to the i2c, netdev mailing list and am awaiting feedback. Daniel Laird From ralf@linux-mips.org Wed Jun 11 12:01:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 12:01:50 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:28863 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20025437AbYFKLBr (ORCPT ); Wed, 11 Jun 2008 12:01:47 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5BB1Q9I014717; Wed, 11 Jun 2008 12:01:27 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5BB1Pko014710; Wed, 11 Jun 2008 12:01:25 +0100 Date: Wed, 11 Jun 2008 12:01:25 +0100 From: Ralf Baechle To: Daniel Laird Cc: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: [PATCH] : Add support for NXP PNX833x (STB222/5) into linux kernel Message-ID: <20080611110125.GA8187@linux-mips.org> References: <64660ef00806110353p66608c43ta1e1995aef8b8f6f@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <64660ef00806110353p66608c43ta1e1995aef8b8f6f@mail.gmail.com> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19474 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 11, 2008 at 11:53:24AM +0100, Daniel Laird wrote: > On the second patch I submitted I changed platform.c as requested so > it registers all resources without the #ifdefs. > I also found that cpu_relax was not quite what i wanted so left the > while(1) loop for halt. > > I have left printk kernel messages in as well (can remove if preferred). > > If you require me to re-submit this second patch let me know (either > as attachment or inline). > > I also split the ip3902, ip0105 and submitted to the i2c, netdev > mailing list and am awaiting feedback. I'm replying to things in not quite chronological order, just looking at your patch in the other window. Ralf From ralf@linux-mips.org Wed Jun 11 12:43:57 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 12:44:00 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:46218 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20028959AbYFKLn5 (ORCPT ); Wed, 11 Jun 2008 12:43:57 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5BBhaSE029972; Wed, 11 Jun 2008 12:43:36 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5BBhZiw029965; Wed, 11 Jun 2008 12:43:35 +0100 Date: Wed, 11 Jun 2008 12:43:35 +0100 From: Ralf Baechle To: Daniel Laird Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] : Add support for =?utf-8?Q?NX?= =?utf-8?Q?P_PNX833x_=28STB222=2F5=29_into_linux_kernel=E2=80=8F?= (UPDATED) Message-ID: <20080611114335.GB777@linux-mips.org> References: <64660ef00806060459n5473afeer91b8441b4fc27ad3@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <64660ef00806060459n5473afeer91b8441b4fc27ad3@mail.gmail.com> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19475 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jun 06, 2008 at 12:59:06PM +0100, Daniel Laird wrote: > arch/mips/Kconfig | 33 > arch/mips/Makefile | 8 > arch/mips/configs/pnx8335-stb225_defconfig | 1150 +++++++++++++++++++++++++++++ > arch/mips/nxp/pnx833x/common/Makefile | 1 > arch/mips/nxp/pnx833x/common/gdb_hook.c | 134 +++ > arch/mips/nxp/pnx833x/common/interrupts.c | 364 +++++++++ > arch/mips/nxp/pnx833x/common/platform.c | 309 +++++++ > arch/mips/nxp/pnx833x/common/prom.c | 70 + > arch/mips/nxp/pnx833x/common/reset.c | 50 + > arch/mips/nxp/pnx833x/common/setup.c | 64 + > arch/mips/nxp/pnx833x/stb22x/Makefile | 1 > arch/mips/nxp/pnx833x/stb22x/board.c | 133 +++ > include/asm-mips/mach-pnx833x/gpio.h | 172 ++++ > include/asm-mips/mach-pnx833x/irq.h | 139 +++ > include/asm-mips/mach-pnx833x/pnx833x.h | 202 +++++ > include/asm-mips/mach-pnx833x/war.h | 25 > 16 files changed, 2855 insertions(+) > > Signed-off-by: daniel.j.laird > > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/arch/mips/configs/pnx8335-stb225_defconfig > linux-2.6.26-rc4/arch/mips/configs/pnx8335-stb225_defconfig > --- linux-2.6.26-rc4.orig/arch/mips/configs/pnx8335-stb225_defconfig 1970-01-01 > 01:00:00.000000000 +0100 Your mailer line wraps patches, can you resend the patch either as attachment or maybe using a proper mail client? Also http://www.linux-mips.org/wiki/Mailing-patches may have a few hints how to get a few mail clients to do the right thing with inlined patches. > +CONFIG_HZ_128=y A somewhat unusual choice, I'm curious as for why? > +static unsigned char *kgdb_uart = UART1; > +static unsigned char *console_uart = UART0; > +static volatile int delay_count; > + > +static unsigned int serial_in(unsigned char *base_address, int offset) > +{ > + return *((unsigned int volatile *)(base_address + offset)); > +} > + > +static void serial_out(unsigned char *base_address, int offset, int value) > +{ > + *((unsigned int volatile *)(base_address + offset)) = value; > +} > + > +static void do_delay(void) > +{ > + int i; > + for (i = 0; i < 10000; i++) > + delay_count++; > +} I assume you're using the volatile variable only to avoid gcc from optimizing the loop away? > +static int put_char(unsigned char *base_address, char c) > +{ > + /* Wait for TX to be ready */ > + while (((serial_in(base_address, PNX8XXX_FIFO) & > PNX8XXX_UART_FIFO_TXFIFO) >> 16) > 15) > + do_delay(); > + > + /* Send the next character */ > + serial_out(base_address, PNX8XXX_FIFO, c); > + serial_out(base_address, PNX8XXX_ICLR, PNX8XXX_UART_INT_TX); > + > + return 1; > +} > + > +static char get_char(unsigned char *base_address) > +{ > + char output; > + > + /* Wait for RX to be ready */ > + while ((serial_in(base_address, PNX8XXX_FIFO) & > PNX8XXX_UART_FIFO_RXFIFO) == 0) > + do_delay(); > + > + /* Get the character */ > + output = serial_in(base_address, PNX8XXX_FIFO) & 0xFF; > + > + /* Move onto the next character in the buffer */ > + serial_out(base_address, PNX8XXX_LCR, serial_in(base_address, > PNX8XXX_LCR) | PNX8XXX_UART_LCR_RX_NEXT); > + serial_out(base_address, PNX8XXX_ICLR, PNX8XXX_UART_INT_RX); > + > + return output; > +} > + > +static void serial_init(unsigned char *base_address) > +{ > + serial_out(base_address, PNX8XXX_LCR, PNX8XXX_UART_LCR_8BIT | > PNX8XXX_UART_LCR_TX_RST | PNX8XXX_UART_LCR_RX_RST); > + serial_out(base_address, PNX8XXX_MCR, PNX8XXX_UART_MCR_DTR | > PNX8XXX_UART_MCR_RTS); > + serial_out(base_address, PNX8XXX_BAUD, 1); /* 115200 Baud */ > + serial_out(base_address, PNX8XXX_CFG, 0x00060030); > + serial_out(base_address, PNX8XXX_ICLR, -1); > + serial_out(base_address, PNX8XXX_IEN, 0); > +} > + > +static void setup_serial_output(void) > +{ > + static bool initialised; > + if (!initialised) { > + serial_init(kgdb_uart); > + serial_init(console_uart); > + initialised = true; > + } > +} > + > +int rs_kgdb_hook(int tty_no, int speed) > +{ > + kgdb_uart = tty_no ? UART1 : UART0; > + console_uart = tty_no ? UART0 : UART1; > + > + setup_serial_output(); > + > + return speed; > +} > + > +int prom_putchar(char c) > +{ > + setup_serial_output(); > + return put_char(console_uart, c); > +} > + > +char prom_getchar(void) > +{ > + setup_serial_output(); > + return get_char(console_uart); > +} > + > +int put_debug_char(char c) > +{ > + setup_serial_output(); > + return put_char(kgdb_uart, c); > +} > + > +char get_debug_char(void) > +{ > + setup_serial_output(); > + return get_char(kgdb_uart); > +} > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/interrupts.c > linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/interrupts.c > --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/interrupts.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/interrupts.c 2008-06-06 > 11:29:17.000000000 +0100 > @@ -0,0 +1,364 @@ > +/* > + * interrupts.c: Interrupt mappings for PNX833X. > + * > + * Copyright 2008 NXP Semiconductors > + * Chris Steel > + * Daniel Laird > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] = > +{ > + 0, /* unused */ > + 4, /* PNX833X_PIC_I2C0_INT 1 */ > + 4, /* PNX833X_PIC_I2C1_INT 2 */ > + 1, /* PNX833X_PIC_UART0_INT 3 */ > + 1, /* PNX833X_PIC_UART1_INT 4 */ > + 6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */ > + 6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */ > + 7, /* PNX833X_PIC_GPIO_INT 7 */ > + 4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */ > + 5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */ > + 4, /* PNX833X_PIC_CONFIG_INT 10 */ > + 4, /* PNX833X_PIC_AOI_INT 11 */ > + 9, /* PNX833X_PIC_SYNC_INT 12 */ > + 9, /* PNX8335_PIC_SATA_INT 13 */ > + 4, /* PNX833X_PIC_OSD_INT 14 */ > + 9, /* PNX833X_PIC_DISP1_INT 15 */ > + 4, /* PNX833X_PIC_DEINTERLACER_INT 16 */ > + 9, /* PNX833X_PIC_DISPLAY2_INT 17 */ > + 4, /* PNX833X_PIC_VC_INT 18 */ > + 4, /* PNX833X_PIC_SC_INT 19 */ > + 9, /* PNX833X_PIC_IDE_INT 20 */ > + 9, /* PNX833X_PIC_IDE_DMA_INT 21 */ > + 6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */ > + 6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */ > + 4, /* PNX833X_PIC_SGDX_DMA_INT 24 */ > + 4, /* PNX833X_PIC_TS_OUT_INT 25 */ > + 4, /* PNX833X_PIC_IR_INT 26 */ > + 3, /* PNX833X_PIC_VMSP1_INT 27 */ > + 3, /* PNX833X_PIC_VMSP2_INT 28 */ > + 4, /* PNX833X_PIC_PIBC_INT 29 */ > + 4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */ > + 4, /* PNX833X_PIC_SGDX_TPD_INT 31 */ > + 5, /* PNX833X_PIC_USB_INT 32 */ > + 4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */ > + 4, /* PNX833X_PIC_CLOCK_INT 34 */ > + 4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */ > + 4, /* PNX833X_PIC_VMSP_DMA_INT 36 */ > +#if defined(CONFIG_SOC_PNX8335) > + 4, /* PNX8335_PIC_MIU_INT 37 */ > + 4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */ > + 9, /* PNX8335_PIC_SYNC_HD_INT 39 */ > + 9, /* PNX8335_PIC_DISP_HD_INT 40 */ > + 9, /* PNX8335_PIC_DISP_SCALER_INT 41 */ > + 4, /* PNX8335_PIC_OSD_HD1_INT 42 */ > + 4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */ > + 4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */ > + 4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */ > + 4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */ > + 4, /* PNX8335_PIC_DENC_TTX_INT 47 */ > + 4, /* PNX8335_PIC_MMI_SIF0_INT 48 */ > + 4, /* PNX8335_PIC_MMI_SIF1_INT 49 */ > + 4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */ > + 4, /* PNX8335_PIC_PIBCS_INT 51 */ > + 12, /* PNX8335_PIC_ETHERNET_INT 52 */ > + 3, /* PNX8335_PIC_VMSP1_0_INT 53 */ > + 3, /* PNX8335_PIC_VMSP1_1_INT 54 */ > + 4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */ > + 4, /* PNX8335_PIC_TDGR_DE_INT 56 */ > + 4, /* PNX8335_PIC_IR1_IRQ_INT 57 */ > +#endif > +}; > + > +static void pic_dispatch(void) > +{ > + unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC); > + > + if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) { > + unsigned long priority = PNX833X_PIC_INT_PRIORITY; > + PNX833X_PIC_INT_PRIORITY = irq_prio[irq]; > + > + if (irq == PNX833X_PIC_GPIO_INT) { > + unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE; > + int pin; > + while ((pin = ffs(mask & 0xffff))) { > + pin -= 1; > + do_IRQ(PNX833X_GPIO_IRQ_BASE + pin); > + mask &= ~(1 << pin); > + } > + } else { > + do_IRQ(irq + PNX833X_PIC_IRQ_BASE); > + } > + > + PNX833X_PIC_INT_PRIORITY = priority; > + } else { > + printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq); > + } > +} > + > +asmlinkage void plat_irq_dispatch(void) > +{ > + unsigned int pending = read_c0_status() & read_c0_cause(); > + > + if (pending & STATUSF_IP4) > + pic_dispatch(); > + else if (pending & STATUSF_IP7) > + do_IRQ(PNX833X_TIMER_IRQ); > + else > + spurious_interrupt(); > +} > + > +static inline void pnx833x_hard_enable_pic_irq(unsigned int irq) > +{ > + /* Currently we do this by setting IRQ priority to 1. > + If priority support is being implemented, 1 should be repalced > + by a better value. */ > + PNX833X_PIC_INT_REG(irq) = irq_prio[irq]; > +} > + > +static inline void pnx833x_hard_disable_pic_irq(unsigned int irq) > +{ > + /* Disable IRQ by writing setting it's priority to 0 */ > + PNX833X_PIC_INT_REG(irq) = 0; > +} > + > +static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */ > +#define IRQFLAG_STARTED 1 > +#define IRQFLAG_DISABLED 2 > + > +static DEFINE_SPINLOCK(pnx833x_irq_lock); > + > +static unsigned int pnx833x_startup_pic_irq(unsigned int irq) > +{ > + unsigned long flags; > + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; > + > + spin_lock_irqsave(&pnx833x_irq_lock, flags); > + > + irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */ > + pnx833x_hard_enable_pic_irq(pic_irq); > + > + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); > + return 0; > +} > + > +static void pnx833x_shutdown_pic_irq(unsigned int irq) > +{ > + unsigned long flags; > + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; > + > + spin_lock_irqsave(&pnx833x_irq_lock, flags); > + > + irqflags[pic_irq] = 0; /* not started */ > + pnx833x_hard_disable_pic_irq(pic_irq); > + > + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); > +} > + > +static void pnx833x_enable_pic_irq(unsigned int irq) > +{ > + unsigned long flags; > + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; > + > + spin_lock_irqsave(&pnx833x_irq_lock, flags); > + > + irqflags[pic_irq] &= ~IRQFLAG_DISABLED; > + if (irqflags[pic_irq] == IRQFLAG_STARTED) > + pnx833x_hard_enable_pic_irq(pic_irq); > + > + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); > +} > + > +static void pnx833x_disable_pic_irq(unsigned int irq) > +{ > + unsigned long flags; > + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; > + > + spin_lock_irqsave(&pnx833x_irq_lock, flags); > + > + irqflags[pic_irq] |= IRQFLAG_DISABLED; > + pnx833x_hard_disable_pic_irq(pic_irq); > + > + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); > +} > + > +static void pnx833x_ack_pic_irq(unsigned int irq) > +{ > +} > + > +static void pnx833x_end_pic_irq(unsigned int irq) > +{ > +} > + > +static DEFINE_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock); > + > +static unsigned int pnx833x_startup_gpio_irq(unsigned int irq) > +{ > + int pin = irq - PNX833X_GPIO_IRQ_BASE; > + unsigned long flags; > + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); > + pnx833x_gpio_enable_irq(pin); > + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); > + return 0; > +} > + > +static void pnx833x_enable_gpio_irq(unsigned int irq) > +{ > + int pin = irq - PNX833X_GPIO_IRQ_BASE; > + unsigned long flags; > + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); > + pnx833x_gpio_enable_irq(pin); > + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); > +} > + > +static void pnx833x_disable_gpio_irq(unsigned int irq) > +{ > + int pin = irq - PNX833X_GPIO_IRQ_BASE; > + unsigned long flags; > + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); > + pnx833x_gpio_disable_irq(pin); > + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); > +} > + > +static void pnx833x_ack_gpio_irq(unsigned int irq) > +{ > +} > + > +static void pnx833x_end_gpio_irq(unsigned int irq) > +{ > + int pin = irq - PNX833X_GPIO_IRQ_BASE; > + unsigned long flags; > + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); > + pnx833x_gpio_clear_irq(pin); > + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); > +} > + > +static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type) > +{ > + int pin = irq - PNX833X_GPIO_IRQ_BASE; > + int gpio_mode; > + > + switch (flow_type) { > + case IRQ_TYPE_EDGE_RISING: > + gpio_mode = GPIO_INT_EDGE_RISING; > + break; > + case IRQ_TYPE_EDGE_FALLING: > + gpio_mode = GPIO_INT_EDGE_FALLING; > + break; > + case IRQ_TYPE_EDGE_BOTH: > + gpio_mode = GPIO_INT_EDGE_BOTH; > + break; > + case IRQ_TYPE_LEVEL_HIGH: > + gpio_mode = GPIO_INT_LEVEL_HIGH; > + break; > + case IRQ_TYPE_LEVEL_LOW: > + gpio_mode = GPIO_INT_LEVEL_LOW; > + break; > + default: > + gpio_mode = GPIO_INT_NONE; > + break; > + } > + > + pnx833x_gpio_setup_irq(gpio_mode, pin); > + > + return 0; > +} > + > +static struct irq_chip pnx833x_pic_irq_type = { > + .typename = "PNX-PIC", > + .startup = pnx833x_startup_pic_irq, > + .shutdown = pnx833x_shutdown_pic_irq, > + .enable = pnx833x_enable_pic_irq, > + .disable = pnx833x_disable_pic_irq, > + .ack = pnx833x_ack_pic_irq, > + .end = pnx833x_end_pic_irq > +}; > + > +static struct irq_chip pnx833x_gpio_irq_type = { > + .typename = "PNX-GPIO", > + .startup = pnx833x_startup_gpio_irq, > + .shutdown = pnx833x_disable_gpio_irq, > + .enable = pnx833x_enable_gpio_irq, > + .disable = pnx833x_disable_gpio_irq, > + .ack = pnx833x_ack_gpio_irq, > + .end = pnx833x_end_gpio_irq, > + .set_type = pnx833x_set_type_gpio_irq > +}; > + > +void __init arch_init_irq(void) > +{ > + unsigned int irq; > + > + /* setup standard internal cpu irqs */ > + mips_cpu_irq_init(); > + > + /* Set IRQ information in irq_desc */ > + for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + > PNX833X_PIC_NUM_IRQ); irq++) { > + pnx833x_hard_disable_pic_irq(irq); > + set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq); > + } > + > + for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + > PNX833X_GPIO_NUM_IRQ); irq++) > + set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq); > + > + /* Set PIC priority limiter register to 0 */ > + PNX833X_PIC_INT_PRIORITY = 0; > + > + /* Setup GPIO IRQ dispatching */ > + pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT); > + > + /* Enable PIC IRQs (HWIRQ2) */ > + if (cpu_has_vint) > + set_vi_handler(4, pic_dispatch); > + > + write_c0_status(read_c0_status() | IE_IRQ2); > +} > + > + > +void __init plat_time_init(void) > +{ > + /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */ > + > + extern unsigned long mips_hpt_frequency; > + unsigned long reg = PNX833X_CLOCK_CPUCP_CTL; > + > + if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) { > + /* Functional clock is disabled so use crystal frequency */ > + mips_hpt_frequency = 25; > + } else { > +#if defined(CONFIG_SOC_PNX8335) > + /* Functional clock is enabled, so get clock multiplier */ > + mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ)); > +#else > + static const unsigned long int freq[4] = {240, 160, 120, 80}; > + mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)]; > +#endif > + } > + > + printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency); > + > + mips_hpt_frequency *= 500000; > +} > + > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/Makefile > linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/Makefile > --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/Makefile 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/Makefile 2008-03-03 > 13:09:30.000000000 +0000 > @@ -0,0 +1 @@ > +obj-y := interrupts.o platform.o prom.o setup.o reset.o gdb_hook.o > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/platform.c > linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/platform.c > --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/platform.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/platform.c 2008-06-06 > 11:29:35.000000000 +0100 > @@ -0,0 +1,309 @@ > +/* > + * platform.c: platform support for PNX833X. > + * > + * Copyright 2008 NXP Semiconductors > + * Chris Steel > + * Daniel Laird > + * > + * Based on software written by: > + * Nikita Youshchenko , based on PNX8550 code. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +static u64 uart_dmamask = ~(u32)0; > + > +static struct resource pnx833x_uart_resources[] = { > + [0] = { > + .start = PNX833X_UART0_PORTS_START, > + .end = PNX833X_UART0_PORTS_END, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { > + .start = PNX833X_PIC_UART0_INT, > + .end = PNX833X_PIC_UART0_INT, > + .flags = IORESOURCE_IRQ, > + }, > + [2] = { > + .start = PNX833X_UART1_PORTS_START, > + .end = PNX833X_UART1_PORTS_END, > + .flags = IORESOURCE_MEM, > + }, > + [3] = { > + .start = PNX833X_PIC_UART1_INT, > + .end = PNX833X_PIC_UART1_INT, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +struct pnx8xxx_port pnx8xxx_ports[] = { > + [0] = { > + .port = { > + .type = PORT_PNX8XXX, > + .iotype = UPIO_MEM, > + .membase = (void __iomem *)PNX833X_UART0_PORTS_START, > + .mapbase = PNX833X_UART0_PORTS_START, > + .irq = PNX833X_PIC_UART0_INT, > + .uartclk = 3692300, > + .fifosize = 16, > + .flags = UPF_BOOT_AUTOCONF, > + .line = 0, > + }, > + }, > + [1] = { > + .port = { > + .type = PORT_PNX8XXX, > + .iotype = UPIO_MEM, > + .membase = (void __iomem *)PNX833X_UART1_PORTS_START, > + .mapbase = PNX833X_UART1_PORTS_START, > + .irq = PNX833X_PIC_UART1_INT, > + .uartclk = 3692300, > + .fifosize = 16, > + .flags = UPF_BOOT_AUTOCONF, > + .line = 1, > + }, > + }, > +}; > + > +static struct platform_device pnx833x_uart_device = { > + .name = "pnx8xxx-uart", > + .id = -1, > + .dev = { > + .dma_mask = &uart_dmamask, > + .coherent_dma_mask = 0xffffffff, > + .platform_data = pnx8xxx_ports, > + }, > + .num_resources = ARRAY_SIZE(pnx833x_uart_resources), > + .resource = pnx833x_uart_resources, > +}; > + > +static u64 ehci_dmamask = ~(u32)0; > + > +static struct resource pnx833x_usb_ehci_resources[] = { > + [0] = { > + .start = PNX833X_USB_PORTS_START, > + .end = PNX833X_USB_PORTS_END, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { > + .start = PNX833X_PIC_USB_INT, > + .end = PNX833X_PIC_USB_INT, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static struct platform_device pnx833x_usb_ehci_device = { > + .name = "pnx833x-ehci", > + .id = -1, > + .dev = { > + .dma_mask = &ehci_dmamask, > + .coherent_dma_mask = 0xffffffff, > + }, > + .num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources), > + .resource = pnx833x_usb_ehci_resources, > +}; > + > +static struct resource pnx833x_i2c0_resources[] = { > + { > + .start = PNX833X_I2C0_PORTS_START, > + .end = PNX833X_I2C0_PORTS_END, > + .flags = IORESOURCE_MEM, > + }, > + { > + .start = PNX833X_PIC_I2C0_INT, > + .end = PNX833X_PIC_I2C0_INT, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static struct resource pnx833x_i2c1_resources[] = { > + { > + .start = PNX833X_I2C1_PORTS_START, > + .end = PNX833X_I2C1_PORTS_END, > + .flags = IORESOURCE_MEM, > + }, > + { > + .start = PNX833X_PIC_I2C1_INT, > + .end = PNX833X_PIC_I2C1_INT, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = { > + { > + .base = PNX833X_I2C0_PORTS_START, > + .irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */ > + .clock = 6, /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = > 50kHz(Prefered HDCP) */ > + .bus_addr = 0, /* no slave support */ > + }, > + { > + .base = PNX833X_I2C1_PORTS_START, > + .irq = -1, /* on high freq, polling is faster */ > + /*.irq = PNX833X_PIC_I2C1_INT,*/ > + .clock = 4, /* 0 == 400 kHz, 4 == 100 kHz. 100 kHz seems a safe > default for now */ > + .bus_addr = 0, /* no slave support */ > + }, > +}; > + > +static struct platform_device pnx833x_i2c0_device = { > + .name = "i2c-pnx0105", > + .id = 0, > + .dev = { > + .platform_data = &pnx833x_i2c_dev[0], > + }, > + .num_resources = ARRAY_SIZE(pnx833x_i2c0_resources), > + .resource = pnx833x_i2c0_resources, > +}; > + > +static struct platform_device pnx833x_i2c1_device = { > + .name = "i2c-pnx0105", > + .id = 1, > + .dev = { > + .platform_data = &pnx833x_i2c_dev[1], > + }, > + .num_resources = ARRAY_SIZE(pnx833x_i2c1_resources), > + .resource = pnx833x_i2c1_resources, > +}; > + > +static u64 ethernet_dmamask = ~(u32)0; > + > +static struct resource pnx833x_ethernet_resources[] = { > + [0] = { > + .start = PNX8335_IP3902_PORTS_START, > + .end = PNX8335_IP3902_PORTS_END, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { > + .start = PNX8335_PIC_ETHERNET_INT, > + .end = PNX8335_PIC_ETHERNET_INT, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static struct platform_device pnx833x_ethernet_device = { > + .name = "ip3902-eth", > + .id = -1, > + .dev = { > + .dma_mask = ðernet_dmamask, > + .coherent_dma_mask = 0xffffffff, > + }, > + .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources), > + .resource = pnx833x_ethernet_resources, > +}; > + > +static struct resource pnx833x_sata_resources[] = { > + [0] = { > + .start = PNX8335_SATA_PORTS_START, > + .end = PNX8335_SATA_PORTS_END, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { > + .start = PNX8335_PIC_SATA_INT, > + .end = PNX8335_PIC_SATA_INT, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static struct platform_device pnx833x_sata_device = { > + .name = "pnx833x-sata", > + .id = -1, > + .num_resources = ARRAY_SIZE(pnx833x_sata_resources), > + .resource = pnx833x_sata_resources, > +}; > + > +#ifdef CONFIG_MTD_PARTITIONS > +static const char *part_probes[] = { "cmdlinepart", 0 }; > +#endif > + > +static void > +pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) > +{ > + struct nand_chip *this = mtd->priv; > + unsigned long nandaddr = (unsigned long)this->IO_ADDR_W; > + > + if (cmd == NAND_CMD_NONE) > + return; > + > + if (ctrl & NAND_CLE) > + writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_CLE_MASK)); > + else > + writeb(cmd, (void __iomem *) (nandaddr + PNX8335_NAND_ALE_MASK)); > +} > + > +static struct platform_nand_data pnx833x_flash_nand_data = { > + .chip = { > + .chip_delay = 25, > +#ifdef CONFIG_MTD_PARTITIONS > + .part_probe_types = part_probes, > +#endif Is this #ifdef really needed? Same a few lines above. > + }, > + .ctrl = { > + .cmd_ctrl = pnx833x_flash_nand_cmd_ctrl > + } > +}; > + > +/* Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!), > + 12 bytes more seems to be the standard that allows for NAND access.*/ Linux comment style: /* * Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!), * 12 bytes more seems to be the standard that allows for NAND access. */ See Documentation/CodingStyle. > +static struct resource pnx833x_flash_nand_resource = { > + .start = PNX8335_NAND_BASE, > + .end = PNX8335_NAND_BASE + 12, > + .flags = IORESOURCE_MEM, > +}; > + > +static struct platform_device pnx833x_flash_nand = { > + .name = "gen_nand", > + .id = -1, > + .num_resources = 1, > + .resource = &pnx833x_flash_nand_resource, > + .dev = { > + .platform_data = &pnx833x_flash_nand_data, > + }, > +}; > + > +static struct platform_device *pnx833x_platform_devices[] __initdata = { > + &pnx833x_uart_device, > + &pnx833x_usb_ehci_device, > + &pnx833x_i2c0_device, > + &pnx833x_i2c1_device, > + &pnx833x_ethernet_device, > + &pnx833x_sata_device, > + &pnx833x_flash_nand, > +}; > + > +int __init pnx833x_platform_init(void) > +{ > + int res; > + > + if (ARRAY_SIZE(pnx833x_platform_devices)) { > + res = platform_add_devices(pnx833x_platform_devices, > + ARRAY_SIZE(pnx833x_platform_devices)); > + } > + return res; > +} ARRAY_SIZE(pnx833x_platform_devices) is always non-zero, so the if condition is unnecessary. If the if was ever non-true the uninitialized variable res would be returned. Also pnx833x_platform_init is only referenced by arch_initicall(), so it should be static, so: static int __init pnx833x_platform_init(void) { int res; res = platform_add_devices(pnx833x_platform_devices, ARRAY_SIZE(pnx833x_platform_devices)); return res; } > + > +arch_initcall(pnx833x_platform_init); > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/prom.c > linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/prom.c > --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/prom.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/prom.c 2008-06-06 > 11:29:55.000000000 +0100 > @@ -0,0 +1,70 @@ > +/* > + * prom.c: > + * > + * Copyright 2008 NXP Semiconductors > + * Chris Steel > + * Daniel Laird > + * > + * Based on software written by: > + * Nikita Youshchenko , based on PNX8550 code. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > +#include > +#include > +#include > + > +void __init prom_init_cmdline(void) > +{ > + int argc = fw_arg0; > + char **argv = (char **)fw_arg1; > + char *c = &(arcs_cmdline[0]); > + int i; > + > + for (i = 1; i < argc; i++) { > + strcpy(c, argv[i]); > + c += strlen(argv[i]); > + if (i < argc-1) > + *c++ = ' '; > + } > + *c = 0; > +} > + > +char __init *prom_getenv(char *envname) > +{ > + extern char **prom_envp; > + char **env = prom_envp; > + int i; > + > + i = strlen(envname); > + > + while (*env) { > + if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=') > + return *env + i + 1; > + env++; > + } > + > + return 0; > +} > + > +void __init prom_free_prom_memory(void) > +{ > +} > + > +char * __init prom_getcmdline(void) > +{ > + return arcs_cmdline; > +} > + > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/reset.c > linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/reset.c > --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/reset.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/reset.c 2008-06-06 > 11:30:01.000000000 +0100 > @@ -0,0 +1,50 @@ > +/* > + * reset.c: reset support for PNX833X. > + * > + * Copyright 2008 NXP Semiconductors > + * Chris Steel > + * Daniel Laird > + * > + * Based on software written by: > + * Nikita Youshchenko , based on PNX8550 code. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > +#include > +#include > +#include > + > +void pnx833x_machine_restart(char *command) > +{ > + printk(KERN_ALERT "\n\n*** Restarting ***\n\n"); > + > + PNX833X_RESET_CONTROL_2 = 0; > + PNX833X_RESET_CONTROL = 0; > +} Please remove the message; that should be done in userspace. > +void pnx833x_machine_halt(void) > +{ > + printk(KERN_ALERT "\n\n*** System halted. ***\n\n"); > + > + while (1) > + __asm__ __volatile__ ("wait"); > + > +} Ditto. > +void pnx833x_machine_power_off(void) > +{ > + printk(KERN_ALERT "\n\n*** You can safely turn off the board. ***"); > + pnx833x_machine_halt(); > +} Ditto. > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/setup.c > linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/setup.c > --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/setup.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/setup.c 2008-06-06 > 11:30:16.000000000 +0100 > @@ -0,0 +1,64 @@ > +/* > + * setup.c: Setup PNX833X Soc. > + * > + * Copyright 2008 NXP Semiconductors > + * Chris Steel > + * Daniel Laird > + * > + * Based on software written by: > + * Nikita Youshchenko , based on PNX8550 code. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +extern void pnx833x_board_setup(void); > +extern void pnx833x_machine_restart(char *); > +extern void pnx833x_machine_halt(void); > +extern void pnx833x_machine_power_off(void); > + > +int __init plat_mem_setup(void) > +{ > + /* fake pci bus to avoid bounce buffers */ > + PCI_DMA_BUS_IS_PHYS = 1; > + > + /* set mips clock to 320MHz */ > +#if defined(CONFIG_SOC_PNX8335) > + PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ); > +#endif > + pnx833x_gpio_init(); /* so it will be ready in board_setup() */ > + > + pnx833x_board_setup(); > + > + _machine_restart = pnx833x_machine_restart; > + _machine_halt = pnx833x_machine_halt; > + pm_power_off = pnx833x_machine_power_off; > + > + /* IO/MEM resources. */ > + set_io_port_base(KSEG1); > + ioport_resource.start = 0; > + ioport_resource.end = ~0; > + iomem_resource.start = 0; > + iomem_resource.end = ~0; > + > + return 0; > +} > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/board.c > linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/board.c > --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/board.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/board.c 2008-06-06 > 11:28:50.000000000 +0100 > @@ -0,0 +1,133 @@ > +/* > + * board.c: STB225 board support. > + * > + * Copyright 2008 NXP Semiconductors > + * Chris Steel > + * Daniel Laird > + * > + * Based on software written by: > + * Nikita Youshchenko , based on PNX8550 code. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > +#include > +#include > +#include > +#include > +#include > + > +/* endianess twiddlers */ > +#define PNX8335_DEBUG0 0x4400 > +#define PNX8335_DEBUG1 0x4404 > +#define PNX8335_DEBUG2 0x4408 > +#define PNX8335_DEBUG3 0x440c > +#define PNX8335_DEBUG4 0x4410 > +#define PNX8335_DEBUG5 0x4414 > +#define PNX8335_DEBUG6 0x4418 > +#define PNX8335_DEBUG7 0x441c > + > +int prom_argc; > +char **prom_argv = 0, **prom_envp = 0; > + > +extern void prom_init_cmdline(void); > +extern char *prom_getenv(char *envname); > + > +const char *get_system_type(void) > +{ > + return "NXP STB22x"; > +} > + > +static inline unsigned long env_or_default(char *env, unsigned long dfl) > +{ > + char *str = prom_getenv(env); > + return str ? simple_strtol(str, 0, 0) : dfl; > +} > + > +void __init prom_init(void) > +{ > + unsigned long memsize; > + > + prom_argc = fw_arg0; > + prom_argv = (char **)fw_arg1; > + prom_envp = (char **)fw_arg2; > + > + prom_init_cmdline(); > + > + memsize = env_or_default("memsize", 0x02000000); > + add_memory_region(0, memsize, BOOT_MEM_RAM); > +} > + > +void __init pnx833x_board_setup(void) > +{ > + pnx833x_gpio_select_function_alt(4); > + pnx833x_gpio_select_output(4); > + pnx833x_gpio_select_function_alt(5); > + pnx833x_gpio_select_input(5); > + pnx833x_gpio_select_function_alt(6); > + pnx833x_gpio_select_input(6); > + pnx833x_gpio_select_function_alt(7); > + pnx833x_gpio_select_output(7); > + > + pnx833x_gpio_select_function_alt(25); > + pnx833x_gpio_select_function_alt(26); > + > + pnx833x_gpio_select_function_alt(27); > + pnx833x_gpio_select_function_alt(28); > + pnx833x_gpio_select_function_alt(29); > + pnx833x_gpio_select_function_alt(30); > + pnx833x_gpio_select_function_alt(31); > + pnx833x_gpio_select_function_alt(32); > + pnx833x_gpio_select_function_alt(33); > + > +#if defined(CONFIG_MTD_NAND_PLATFORM) || > defined(CONFIG_MTD_NAND_PLATFORM_MODULE) > + /* Setup MIU for NAND access on CS0... > + * > + * (it seems that we must also configure CS1 for reliable operation, > + * otherwise the first read ID command will fail if it's read as 4 bytes > + * but pass if it's read as 1 word.) > + */ > + > + /* Setup MIU CS0 & CS1 timing */ > + PNX833X_MIU_SEL0 = 0; > + PNX833X_MIU_SEL1 = 0; > + PNX833X_MIU_SEL0_TIMING = 0x50003081; > + PNX833X_MIU_SEL1_TIMING = 0x50003081; > + > + /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does > not need this) */ > + pnx833x_gpio_select_function_alt(0); > + > + /* Setup GPIO 04 to input NAND read/busy signal */ > + pnx833x_gpio_select_function_io(4); > + pnx833x_gpio_select_input(4); > + > + /* Setup GPIO 05 to disable NAND write protect */ > + pnx833x_gpio_select_function_io(5); > + pnx833x_gpio_select_output(5); > + pnx833x_gpio_write(1, 5); > + > +#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE) > + > + /* Set up MIU for 16-bit NOR access on CS0 and CS1... */ > + > + /* Setup MIU CS0 & CS1 timing */ > + PNX833X_MIU_SEL0 = 1; > + PNX833X_MIU_SEL1 = 1; > + PNX833X_MIU_SEL0_TIMING = 0x6A08D082; > + PNX833X_MIU_SEL1_TIMING = 0x6A08D082; > + > + /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does > not need this) */ > + pnx833x_gpio_select_function_alt(0); > +#endif > +} > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/Makefile > linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/Makefile > --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/stb22x/Makefile 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/stb22x/Makefile 2008-03-03 > 13:09:30.000000000 +0000 > @@ -0,0 +1 @@ > +lib-y := board.o > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/gpio.h > linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/gpio.h > --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/gpio.h 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/gpio.h 2008-06-06 > 11:29:09.000000000 +0100 > @@ -0,0 +1,172 @@ > +/* > + * gpio.h: GPIO Support for PNX833X. > + * > + * Copyright 2008 NXP Semiconductors > + * Chris Steel > + * Daniel Laird > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > +#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H > +#define __ASM_MIPS_MACH_PNX833X_GPIO_H > + > +/* BIG FAT WARNING: races danger! > + No protections exist here. Current users are only early init code, > + when locking is not needed because no cuncurency yet exists there, > + and GPIO IRQ dispatcher, which does locking. > + However, if many uses will ever happen, proper locking will be needed > + - including locking between different uses > +*/ > + > +#include "pnx833x.h" > + > +#define SET_REG_BIT(reg, bit) reg |= (1 << (bit)) > +#define CLEAR_REG_BIT(reg, bit) reg &= ~(1 << (bit)) > + > +/* Initialize GPIO to a known state */ > +static inline void pnx833x_gpio_init(void) > +{ > + PNX833X_PIO_DIR = 0; > + PNX833X_PIO_DIR2 = 0; > + PNX833X_PIO_SEL = 0; > + PNX833X_PIO_SEL2 = 0; > + PNX833X_PIO_INT_EDGE = 0; > + PNX833X_PIO_INT_HI = 0; > + PNX833X_PIO_INT_LO = 0; > + > + /* clear any GPIO interrupt requests */ > + PNX833X_PIO_INT_CLEAR = 0xffff; > + PNX833X_PIO_INT_CLEAR = 0; > + PNX833X_PIO_INT_ENABLE = 0; > +} > + > +/* Select GPIO direction for a pin */ > +static inline void pnx833x_gpio_select_input(unsigned int pin) > +{ > + if (pin < 32) > + CLEAR_REG_BIT(PNX833X_PIO_DIR, pin); > + else > + CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31); > +} > +static inline void pnx833x_gpio_select_output(unsigned int pin) > +{ > + if (pin < 32) > + SET_REG_BIT(PNX833X_PIO_DIR, pin); > + else > + SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31); > +} > + > +/* Select GPIO or alternate function for a pin */ > +static inline void pnx833x_gpio_select_function_io(unsigned int pin) > +{ > + if (pin < 32) > + CLEAR_REG_BIT(PNX833X_PIO_SEL, pin); > + else > + CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31); > +} > +static inline void pnx833x_gpio_select_function_alt(unsigned int pin) > +{ > + if (pin < 32) > + SET_REG_BIT(PNX833X_PIO_SEL, pin); > + else > + SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31); > +} > + > +/* Read GPIO pin */ > +static inline int pnx833x_gpio_read(unsigned int pin) > +{ > + if (pin < 32) > + return(PNX833X_PIO_IN >> pin) & 1; > + else > + return(PNX833X_PIO_IN2 >> (pin & 31)) & 1; > +} > + > +/* Write GPIO pin */ > +static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin) > +{ > + if (pin < 32) { > + if (val) > + SET_REG_BIT(PNX833X_PIO_OUT, pin); > + else > + CLEAR_REG_BIT(PNX833X_PIO_OUT, pin); > + } else { > + if (val) > + SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31); > + else > + CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31); > + } > +} > + > +/* Configure GPIO interrupt */ > +#define GPIO_INT_NONE 0 > +#define GPIO_INT_LEVEL_LOW 1 > +#define GPIO_INT_LEVEL_HIGH 2 > +#define GPIO_INT_EDGE_RISING 3 > +#define GPIO_INT_EDGE_FALLING 4 > +#define GPIO_INT_EDGE_BOTH 5 > +static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin) > +{ > + switch (when) { > + case GPIO_INT_LEVEL_LOW: > + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); > + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); > + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); > + break; > + case GPIO_INT_LEVEL_HIGH: > + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); > + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); > + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); > + break; > + case GPIO_INT_EDGE_RISING: > + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); > + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); > + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); > + break; > + case GPIO_INT_EDGE_FALLING: > + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); > + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); > + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); > + break; > + case GPIO_INT_EDGE_BOTH: > + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); > + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); > + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); > + break; > + default: > + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); > + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); > + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); > + break; > + } > +} > + > +/* Enable/disable GPIO interrupt */ > +static inline void pnx833x_gpio_enable_irq(unsigned int pin) > +{ > + SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); > +} > +static inline void pnx833x_gpio_disable_irq(unsigned int pin) > +{ > + CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); > +} > + > +/* Clear GPIO interrupt request */ > +static inline void pnx833x_gpio_clear_irq(unsigned int pin) > +{ > + SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); > + CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); > +} > + > +#endif > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/irq.h > linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/irq.h > --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/irq.h 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/irq.h 2008-06-06 > 11:29:30.000000000 +0100 > @@ -0,0 +1,139 @@ > +/* > + * irq.h: IRQ mappings for PNX833X. > + * > + * Copyright 2008 NXP Semiconductors > + * Chris Steel > + * Daniel Laird > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > + > +#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H > +#define __ASM_MIPS_MACH_PNX833X_IRQ_H > +/* > + * The "IRQ numbers" are completely virtual. > + * > + * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48. > + * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt, > + * numbers 49..64 for (virtual) GPIO interrupts. > + * > + * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57, > + * connected to PIC, which uses core hardware interrupt 2, and also > + * a timer interrupt through hardware interrupt 5. > + * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt, > + * numbers 65..80 for (virtual) GPIO interrupts. > + * > + */ > + > +#if defined(CONFIG_SOC_PNX8335) > + #define PNX833X_PIC_NUM_IRQ 58 > +#else > + #define PNX833X_PIC_NUM_IRQ 37 > +#endif > + > +#define MIPS_CPU_NUM_IRQ 8 > +#define PNX833X_GPIO_NUM_IRQ 16 > + > +#define MIPS_CPU_IRQ_BASE 0 > +#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ) > +#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ) > +#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + > PNX833X_GPIO_NUM_IRQ) > + > + > +#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) > + > +/* Interrupts supported by PIC */ > +#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1) > +#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2) > +#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3) > +#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4) > +#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5) > +#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6) > +#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7) > +#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8) > +#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9) > +#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10) > +#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11) > +#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12) > +#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13) > +#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13) > +#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14) > +#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15) > +#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16) > +#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17) > +#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18) > +#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19) > +#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20) > +#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21) > +#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22) > +#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23) > +#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24) > +#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25) > +#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26) > +#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27) > +#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28) > +#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29) > +#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30) > +#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31) > +#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32) > +#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33) > +#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34) > +#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35) > +#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36) > + > +#if defined(CONFIG_SOC_PNX8335) > +#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37) > +#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38) > +#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39) > +#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40) > +#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41) > +#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42) > +#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43) > +#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44) > +#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45) > +#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46) > +#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47) > +#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48) > +#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49) > +#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50) > +#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51) > +#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52) > +#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53) > +#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54) > +#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55) > +#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56) > +#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57) > +#endif > + > +/* GPIO interrupts */ > +#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0) > +#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1) > +#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2) > +#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3) > +#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4) > +#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5) > +#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6) > +#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7) > +#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8) > +#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9) > +#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10) > +#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11) > +#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12) > +#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13) > +#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14) > +#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15) > + > +#endif > + CodingStyle: try to stay with in 80 columns. really is only meant to supply a few constants to the generic interrupt header in rsp. , see include/asm-mips/mach-generic/irq.h for which constants these are. Anything beyond that should go into a separate header file and be included where necessary. > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/pnx833x.h > linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/pnx833x.h > --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/pnx833x.h 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/pnx833x.h 2008-06-06 > 11:29:43.000000000 +0100 > @@ -0,0 +1,202 @@ > +/* > + * pnx833x.h: Register mappings for PNX833X. > + * > + * Copyright 2008 NXP Semiconductors > + * Chris Steel > + * Daniel Laird > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > +#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H > +#define __ASM_MIPS_MACH_PNX833X_PNX833X_H > + > +/* All regs are accessed in KSEG1 */ > +#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul) > + > +#define PNX833X_REG(offs) *((volatile unsigned long *)(PNX833X_BASE + offs)) > + > +/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */ > + > +/* Read access to multibit fields */ > +#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) > +#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field) > + > +/* Use PNX833X_FIELD to extract a field from val */ > +#define PNX_FIELD(cpu, val, reg, field) \ > + (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ > + PNX##cpu##_##reg##_##field##_SHIFT) > +#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) > +#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) > +#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) > + > +/* Use PNX833X_REGFIELD to extract a field from a register */ > +#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field) > +#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field) > +#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field) > + > + > +#define PNX_WRITEFIELD(cpu, val, reg, field) \ > + PNX##cpu##_##reg = (PNX##cpu##_##reg & > ~(PNX##cpu##_##reg##_##field##_MASK)) | \ > + ((val) << PNX##cpu##_##reg##_##field##_SHIFT) > +#define PNX833X_WRITEFIELD(val, reg, field) \ > + PNX_WRITEFIELD(833X, val, reg, field) > +#define PNX8330_WRITEFIELD(val, reg, field) \ > + PNX_WRITEFIELD(8330, val, reg, field) > +#define PNX8335_WRITEFIELD(val, reg, field) \ > + PNX_WRITEFIELD(8335, val, reg, field) > + > + > +/* Macros to detect CPU type */ > + > +#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC) > +#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000 > +#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12 > +#define PNX8330_CONFIG_MODULE_MAJREV 4 > +#define PNX8335_CONFIG_MODULE_MAJREV 5 > +#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ > + PNX8330_CONFIG_MODULE_MAJREV) > +#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ > + PNX8335_CONFIG_MODULE_MAJREV) > + > + > + > +#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) > +#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) > + > +#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) > +#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) > +#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4) > +#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */ > +#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 > +#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) > + > +#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) > +#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ > +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ > +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 > + > +#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) > +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f > +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0 > + > +#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004) > +#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */ > + > +#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040) > +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000 > +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19 > + > +#define PNX833X_PIO_IN PNX833X_REG(0xF000) > +#define PNX833X_PIO_OUT PNX833X_REG(0xF004) > +#define PNX833X_PIO_DIR PNX833X_REG(0xF008) > +#define PNX833X_PIO_SEL PNX833X_REG(0xF014) > +#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020) > +#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024) > +#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028) > +#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0) > +#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4) > +#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8) > +#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C) > +#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060) > +#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064) > +#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068) > + > +#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000) > +#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF) > +#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000) > +#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF) > + > +#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000) > +#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF) > + > +#define PNX833X_CONFIG_USB PNX833X_REG(0x7008) > + > +#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000) > +#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF) > +#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000) > +#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF) > + > +#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000) > +#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF) > +#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC) > + > +#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 > +#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16 > +#define PNX833X_IDE_MODULE_ID_VALUE 0xA009 > + > + > +#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004) > +#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008) > +#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C) > +#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010) > +#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014) > +#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018) > +#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C) > +#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020) > + > +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) > +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 > + > +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) > +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 > + > +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) > +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9 > + > +#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000) > + > +#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) > +#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 > + > +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) > +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 > + > +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) > +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 > + > +#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) > +#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0 > + > +#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \ > + PNX833X_MIU_CONFIG_SPI = \ > + ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \ > + ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \ > + ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \ > + ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT) > + > +#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000) > +#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF) > +#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC) > + > +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 > +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16 > +#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902 > + > + /* I/O location(gets remapped)*/ > +#define PNX8335_NAND_BASE 0x18000000 > +/* I/O location with CLE high */ > +#define PNX8335_NAND_CLE_MASK 0x00100000 > +/* I/O location with ALE high */ > +#define PNX8335_NAND_ALE_MASK 0x00010000 > + > +#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000) > +#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF) > +#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC) > + > +#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 > +#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16 > +#define PNX8335_SATA_MODULE_ID_VALUE 0xA099 > + > +#endif > diff -urN --exclude=.svn > linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/war.h > linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/war.h > --- linux-2.6.26-rc4.orig/include/asm-mips/mach-pnx833x/war.h 1970-01-01 > 01:00:00.000000000 +0100 > +++ linux-2.6.26-rc4/include/asm-mips/mach-pnx833x/war.h 2008-06-05 > 09:34:22.000000000 +0100 > @@ -0,0 +1,25 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle > + */ > +#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H > +#define __ASM_MIPS_MACH_PNX833X_WAR_H > + > +#define R4600_V1_INDEX_ICACHEOP_WAR 0 > +#define R4600_V1_HIT_CACHEOP_WAR 0 > +#define R4600_V2_HIT_CACHEOP_WAR 0 > +#define R5432_CP0_INTERRUPT_WAR 0 > +#define BCM1250_M3_WAR 0 > +#define SIBYTE_1956_WAR 0 > +#define MIPS4K_ICACHE_REFILL_WAR 0 > +#define MIPS_CACHE_SYNC_WAR 0 > +#define TX49XX_ICACHE_INDEX_INV_WAR 0 > +#define RM9000_CDEX_SMP_WAR 0 > +#define ICACHE_REFILLS_WORKAROUND_WAR 0 > +#define R10000_LLSC_WAR 0 > +#define MIPS34K_MISSED_ITLB_WAR 0 > + > +#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ Not too bad all in all. Cheers, Ralf From blf.ireland@gmail.com Wed Jun 11 14:25:04 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 14:25:07 +0100 (BST) Received: from fg-out-1718.google.com ([72.14.220.153]:1253 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S20041705AbYFKNRF convert rfc822-to-8bit (ORCPT ); Wed, 11 Jun 2008 14:17:05 +0100 Received: by fg-out-1718.google.com with SMTP id d23so2118853fga.32 for ; Wed, 11 Jun 2008 06:17:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:reply-to:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id:sender; bh=aPv/we3u6dvFFUaVPLjSSdNbmJNCJoi8BYnnmdRk/rc=; b=i5eofXAmD/hd43iP0USSZyFTf0m/uskW7iTepuW5nppoQheJ5laR8b6Qg0crV0Oqgx W9AkmU/S+oUxNTgu+9tNK66HBqW5Bwq8TTJ8gAN80nr+0RH+Xdus8hgFkijWPd7WtGt5 ApjEUpdLzODvpikFyGukkOlpg+8ABe7Oh7qLk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:reply-to:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id:sender; b=cn6+rWEclNJhEAgwhBDDV/PK3Dutvrtky5BR0d7DWKOeO7EIJKebPsPnuKS3sjS62A CM7dIAKq7m8Ra/liJ0x8E/PaX8UVA1t/PYyE4Oum7PtDgFupLzU0aW3Dc3sK9SgYxlfA WFfzv0rP64nQfrJrF1xavDhQvHdbg6lDqM4r8= Received: by 10.86.78.4 with SMTP id a4mr196186fgb.29.1213190224510; Wed, 11 Jun 2008 06:17:04 -0700 (PDT) Received: from innova-card.com ( [81.252.61.1]) by mx.google.com with ESMTPS id 3sm16296349fge.3.2008.06.11.06.16.59 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 11 Jun 2008 06:17:02 -0700 (PDT) From: Brian Foster Reply-To: Brian Foster To: David Daney , linux-mips@linux-mips.org Subject: Re: Adding(?) XI support to MIPS-Linux? Date: Wed, 11 Jun 2008 15:16:56 +0200 User-Agent: KMail/1.9.6 (enterprise 0.20070907.709405) Cc: Thiemo Seufer , "Kevin D. Kissell" , Andrew Dyer References: <200806091658.10937.brian.foster@innova-card.com> <20080610095702.GG11233@networkno.de> <484EAA16.80903@avtrex.com> In-Reply-To: <484EAA16.80903@avtrex.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200806111516.57406.brian.foster@innova-card.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19476 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips David Daney wrote: > Thiemo Seufer wrote: > > Brian Foster wrote: > >> 2) Kevin D. Kissell wrote: > >> 2)[... ‘ld -z noexecstack’ ] is not used by default because too many > >> 2) things depend on executable stacks on MIPS. > >> > >> Ah! Can you be more specific please? At the present time > >> I'm only aware of three situations where executable stacks > >> are magically used ("magic" meaning it's being done without > >> the programmer explicitly coding it): > >> > >> 1. sigreturn. > >> 2. something to do with FPU emulation? > >> 3. pointer to a nested function (gcc extension). > > > > Those, plus manually coded trampolines in e.g. foreign function > > interfacing (which are typically hidden in some library). I don't > > know if you can ignore that completely. :-) > > The trampolines in libffi are user allocated, so there is a choice of > where to place them. In libgcj (which uses the libffi trampolines) the > trampolines are allocated on the heap and care is taken to set the > execute permissions on the memory in question. Other users may have > problems, but by now most code should work as XI support has been > present on x86 for quite some time now. David, thanks for clarifying Thiemo's point; I wasn't quite sure what he meant by “foreign functions” albeit (as it happens) apparently guessed correctly. And for the specific example of ‘libffi’ (and ‘libgcj’); that's a new library (to me). > As long as there is a mechanism to make user space stacks (and heap) > executable, there should be no problem. People running code that > requires it can switch off the XI support. Agreed. It is (alas?) important for the general case and the longer term. But it's plausible that for the specific case I have, it's not important and maybe not even wanted. (I'm working in a security paranoid/sensitive area .... .) Please note this is rather *speculative* ATM! It's case 2 (above), the trampoline that has “something to do with FPU emulation”, which has me concerned ATM. The 4KSd core does not have an FPU. That encourages the use of ‘-msoft-float’ (at least for performance), but does not require it. (Albeit I wonder if, in the restricted world I'm playing in, if it could be “required” (assuming it doesn't have an issue?)? Hum .... .) The quick summary (which I'm sure others on this list can clarify/correct) is the FP trampoline, which is pushed on the user-land stack is, unlike sigreturn, not fixed code. It varies on a per-instance per-thread basis. Hence the simple ‘vsyscall’ mechanism ((to be?) used for sigreturn) is inappropriate. The trampoline is only used to execute a non-FP instruction () in the delay slot of an FP-instruction: # Non-FP instruction to execute in user-land BADINST # Bad instruction forcing return to FP emulator COOKIE # Bad instruction (not executed) for verification # Where to resume execution after Belch! ;-\ Whilst I can think of a few things that may work (temporarily change page permissions; or go ahead and use the ‘vsyscall’ page with some interlocking magic; or a new new dedicated per-thread page; or ...?) none seem appealing. Suggestions? Comments? Prior art to study? thanks & cheers! -blf- ( I'm experimenting with a new technique for posting to the list to save me some hassle. It *should* work, but .... ! ) -- “How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools.” | http://www.stopesso.com From ralf@linux-mips.org Wed Jun 11 17:17:40 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 17:17:42 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:38329 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20021526AbYFKQRk (ORCPT ); Wed, 11 Jun 2008 17:17:40 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5BGHHEQ000632; Wed, 11 Jun 2008 17:17:18 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5BGHGBK000625; Wed, 11 Jun 2008 17:17:16 +0100 Date: Wed, 11 Jun 2008 17:17:16 +0100 From: Ralf Baechle To: "Chen, Huacai" Cc: "Maciej W. Rozycki" , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [patch]modify the MIPS CPU classfication Message-ID: <20080611161716.GA30400@linux-mips.org> References: <42DFA526FC41B1429CE7279EF83C6BDC01404341@pdsmsx415.ccr.corp.intel.com> <42DFA526FC41B1429CE7279EF83C6BDC01404431@pdsmsx415.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <42DFA526FC41B1429CE7279EF83C6BDC01404431@pdsmsx415.ccr.corp.intel.com> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19477 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 10, 2008 at 09:05:08AM +0800, Chen, Huacai wrote: > This is the new patch sorted numerically. Thanks, queued for 2.6.27. Ralf From ddaney@avtrex.com Wed Jun 11 18:08:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 18:08:40 +0100 (BST) Received: from smtp1.dnsmadeeasy.com ([205.234.170.144]:38615 "EHLO smtp1.dnsmadeeasy.com") by ftp.linux-mips.org with ESMTP id S20043464AbYFKREl (ORCPT ); Wed, 11 Jun 2008 18:04:41 +0100 Received: from smtp1.dnsmadeeasy.com (localhost [127.0.0.1]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP id 0A1CC31E993; Wed, 11 Jun 2008 17:04:41 +0000 (UTC) X-Authenticated-Name: js.dnsmadeeasy X-Transit-System: In case of SPAM please contact abuse@dnsmadeeasy.com Received: from avtrex.com (unknown [67.116.42.147]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP; Wed, 11 Jun 2008 17:04:40 +0000 (UTC) Received: from dl2.hq2.avtrex.com ([192.168.7.26]) by avtrex.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 11 Jun 2008 10:04:26 -0700 Message-ID: <48500599.9080807@avtrex.com> Date: Wed, 11 Jun 2008 10:04:25 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: MIPS Linux List Cc: Ralf Baechle Subject: Resend: [PATCH] [MIPS] Fix asm constraints for 'ins' instructions. Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 11 Jun 2008 17:04:26.0342 (UTC) FILETIME=[342DB860:01C8CBE5] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19478 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@avtrex.com Precedence: bulk X-list: linux-mips This patch may have been lost in the Great LMO Firewall Saga, so I am resending it: -------- Original Message -------- Subject: [PATCH] [MIPS] Fix asm constraints for 'ins' instructions. Date: Tue, 27 May 2008 00:04:20 -0700 From: David Daney To: linux-mips@linux-mips.org The third operand to 'ins' must be a constant int, not a register. Signed-off-by: David Daney --- include/asm-mips/bitops.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 6427247..9a7274b 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m), "r" (~0)); + : "i" (bit), "m" (*m), "r" (~0)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (cpu_has_llsc) { __asm__ __volatile__( @@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m)); + : "i" (bit), "m" (*m)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (cpu_has_llsc) { __asm__ __volatile__( @@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr, "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m), "=&r" (res) - : "ri" (bit), "m" (*m) + : "i" (bit), "m" (*m) : "memory"); #endif } else if (cpu_has_llsc) { -- 1.5.4.5 From ralf@linux-mips.org Wed Jun 11 18:12:52 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 18:12:54 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:61871 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20021838AbYFKRMw (ORCPT ); Wed, 11 Jun 2008 18:12:52 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5BHCPn0021878; Wed, 11 Jun 2008 18:12:25 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5BHCL1j021853; Wed, 11 Jun 2008 18:12:21 +0100 Date: Wed, 11 Jun 2008 18:12:21 +0100 From: Ralf Baechle To: David Daney Cc: MIPS Linux List Subject: Re: Resend: [PATCH] [MIPS] Fix asm constraints for 'ins' instructions. Message-ID: <20080611171220.GC10820@linux-mips.org> References: <48500599.9080807@avtrex.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <48500599.9080807@avtrex.com> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19479 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 11, 2008 at 10:04:25AM -0700, David Daney wrote: > This patch may have been lost in the Great LMO Firewall Saga, so I am resending it: The firewall has been torched btw ;-) Ralf From ralf@linux-mips.org Wed Jun 11 18:15:31 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 18:15:33 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:32490 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20021988AbYFKRPb (ORCPT ); Wed, 11 Jun 2008 18:15:31 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5BHF9Tn023147; Wed, 11 Jun 2008 18:15:09 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5BHF2Ab022966; Wed, 11 Jun 2008 18:15:02 +0100 Date: Wed, 11 Jun 2008 18:15:02 +0100 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: Daniel Jacobowitz , linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] mips: Remove obsolete isa_slot_offset Message-ID: <20080611171502.GC30400@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19480 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 09, 2008 at 05:19:53PM +0100, Maciej W. Rozycki wrote: > The isa_slot_offset variable and its __ISA_IO_base macro is not used > anywhere anymore. It does not look like a decent interface per today's > standards either. Remove both including all places of initialization. Queued for 2.6.27, thanks. Ralf From ralf@linux-mips.org Wed Jun 11 18:19:52 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 18:19:54 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:12426 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20021578AbYFKRTw (ORCPT ); Wed, 11 Jun 2008 18:19:52 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5BHJVam024840; Wed, 11 Jun 2008 18:19:31 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5BHJVTr024833; Wed, 11 Jun 2008 18:19:31 +0100 Date: Wed, 11 Jun 2008 18:19:31 +0100 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: Daniel Jacobowitz , linux-mips@linux-mips.org Subject: Re: [PATCH 2/2] sb1250: Initialize io_map_base Message-ID: <20080611171931.GD30400@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19481 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 09, 2008 at 05:20:03PM +0100, Maciej W. Rozycki wrote: > Correctly initialize io_map_base for the SB1250 PCI controller as > required for proper iomap support. Based on a proposal from Daniel > Jacobowitz. Applied. > This is the second half of a set of two changes resulting from my > investigation of how proper iomap support should be done for the SB1250 in > response to a report from Daniel. This patch has to be applied on top of > the first half. Tested successfully with a SWARM board and a pair of I split the two siamese twins since the one is only a cleanup while the other is 2.6.26 / -stable stuff. Ralf From ralf@linux-mips.org Wed Jun 11 18:30:17 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 18:30:21 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:38369 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20021887AbYFKRaR (ORCPT ); Wed, 11 Jun 2008 18:30:17 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5BHToVd028593; Wed, 11 Jun 2008 18:29:50 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5BHToMi028586; Wed, 11 Jun 2008 18:29:50 +0100 Date: Wed, 11 Jun 2008 18:29:50 +0100 From: Ralf Baechle To: David Daney Cc: MIPS Linux List Subject: Re: Resend: [PATCH] [MIPS] Fix asm constraints for 'ins' instructions. Message-ID: <20080611172950.GA16600@linux-mips.org> References: <48500599.9080807@avtrex.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <48500599.9080807@avtrex.com> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19482 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 11, 2008 at 10:04:25AM -0700, David Daney wrote: > The third operand to 'ins' must be a constant int, not a register. > > Signed-off-by: David Daney > --- > include/asm-mips/bitops.h | 6 +++--- > 1 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h > index 6427247..9a7274b 100644 > --- a/include/asm-mips/bitops.h > +++ b/include/asm-mips/bitops.h > @@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) > "2: b 1b \n" > " .previous \n" > : "=&r" (temp), "=m" (*m) > - : "ir" (bit), "m" (*m), "r" (~0)); > + : "i" (bit), "m" (*m), "r" (~0)); > #endif /* CONFIG_CPU_MIPSR2 */ > } else if (cpu_has_llsc) { > __asm__ __volatile__( An old trick to get gcc to do the right thing. Basically at the stage when gcc is verifying the constraints it may not yet know that it can optimize things into an "i" argument, so compilation may fail if "r" isn't in the constraints. However we happen to know that due to the way the code is written gcc will always be able to make use of the "i" constraint so no code using "r" should ever be created. The trick is a bit ugly; I think it was used first in asm-i386/io.h ages ago and I would be happy if we could get rid of it without creating new problems. Maybe a gcc hacker here can tell more? Ralf From ralf@linux-mips.org Wed Jun 11 18:56:04 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 18:56:07 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:31658 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20041986AbYFKRol (ORCPT ); Wed, 11 Jun 2008 18:44:41 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5BHiLMP002131; Wed, 11 Jun 2008 18:44:21 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5BHiFIh002094; Wed, 11 Jun 2008 18:44:15 +0100 Date: Wed, 11 Jun 2008 18:44:15 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/5] [MIPS] The tickcount per-cpu variable can become static Message-ID: <20080611174415.GE30400@linux-mips.org> References: <12120730323761-git-send-email-dmitri.vorobiev@movial.fi> <12120730321843-git-send-email-dmitri.vorobiev@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <12120730321843-git-send-email-dmitri.vorobiev@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19483 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, May 29, 2008 at 05:57:12PM +0300, Dmitri Vorobiev wrote: > In arch/mips/mips-boards/generic/time.c, the `tickcount' per-cpu > variable is needlessly defined global, and this patch makes it > static. > > Noticed by sparse. Tested by booting a Qemu-emulated Malta board > up to the shell prompt. Patch is ok - except it tries to fix a piece of code which I've already removed so I'll drop this one. Ralf From ddaney@avtrex.com Wed Jun 11 18:56:45 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 18:56:48 +0100 (BST) Received: from smtp1.dnsmadeeasy.com ([205.234.170.144]:54486 "EHLO smtp1.dnsmadeeasy.com") by ftp.linux-mips.org with ESMTP id S20041731AbYFKRoM (ORCPT ); Wed, 11 Jun 2008 18:44:12 +0100 Received: from smtp1.dnsmadeeasy.com (localhost [127.0.0.1]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP id 13CE931DBFF; Wed, 11 Jun 2008 17:44:13 +0000 (UTC) X-Authenticated-Name: js.dnsmadeeasy X-Transit-System: In case of SPAM please contact abuse@dnsmadeeasy.com Received: from avtrex.com (unknown [67.116.42.147]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP; Wed, 11 Jun 2008 17:44:12 +0000 (UTC) Received: from dl2.hq2.avtrex.com ([192.168.7.26]) by avtrex.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 11 Jun 2008 10:43:58 -0700 Message-ID: <48500EDD.404@avtrex.com> Date: Wed, 11 Jun 2008 10:43:57 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: Ralf Baechle , GCC Mailing List Cc: MIPS Linux List , Richard Sandiford Subject: Re: Resend: [PATCH] [MIPS] Fix asm constraints for 'ins' instructions. References: <48500599.9080807@avtrex.com> <20080611172950.GA16600@linux-mips.org> In-Reply-To: <20080611172950.GA16600@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 11 Jun 2008 17:43:58.0766 (UTC) FILETIME=[BA40E4E0:01C8CBEA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19484 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@avtrex.com Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > On Wed, Jun 11, 2008 at 10:04:25AM -0700, David Daney wrote: > >> The third operand to 'ins' must be a constant int, not a register. >> >> Signed-off-by: David Daney >> --- >> include/asm-mips/bitops.h | 6 +++--- >> 1 files changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h >> index 6427247..9a7274b 100644 >> --- a/include/asm-mips/bitops.h >> +++ b/include/asm-mips/bitops.h >> @@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) >> "2: b 1b \n" >> " .previous \n" >> : "=&r" (temp), "=m" (*m) >> - : "ir" (bit), "m" (*m), "r" (~0)); >> + : "i" (bit), "m" (*m), "r" (~0)); >> #endif /* CONFIG_CPU_MIPSR2 */ >> } else if (cpu_has_llsc) { >> __asm__ __volatile__( > > An old trick to get gcc to do the right thing. Basically at the stage when > gcc is verifying the constraints it may not yet know that it can optimize > things into an "i" argument, so compilation may fail if "r" isn't in the > constraints. However we happen to know that due to the way the code is > written gcc will always be able to make use of the "i" constraint so no > code using "r" should ever be created. > > The trick is a bit ugly; I think it was used first in asm-i386/io.h ages ago > and I would be happy if we could get rid of it without creating new problems. > Maybe a gcc hacker here can tell more? It is not nice to lie to GCC. CCing GCC and Richard in hopes that a wider audience may shed some light on the issue. David Daney From maxim@codesourcery.com Wed Jun 11 19:41:38 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 19:41:40 +0100 (BST) Received: from mail.codesourcery.com ([65.74.133.4]:43740 "EHLO mail.codesourcery.com") by ftp.linux-mips.org with ESMTP id S20038523AbYFKSli (ORCPT ); Wed, 11 Jun 2008 19:41:38 +0100 Received: (qmail 20200 invoked from network); 11 Jun 2008 18:41:34 -0000 Received: from unknown (HELO mbp.local) (maxim@127.0.0.2) by mail.codesourcery.com with ESMTPA; 11 Jun 2008 18:41:34 -0000 Message-ID: <48501C55.5060602@codesourcery.com> Date: Wed, 11 Jun 2008 22:41:25 +0400 From: Maxim Kuvyrkov User-Agent: Thunderbird 2.0.0.14 (Macintosh/20080421) MIME-Version: 1.0 To: "Maciej W. Rozycki" , Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Subject: Re: Changing the treatment of the MIPS HI and LO registers References: <87tzgj4nh6.fsf@firetop.home> <87abib4d9t.fsf@firetop.home> <87r6bm1ebd.fsf@firetop.home> <878wxtvarg.fsf@firetop.home> <8763stz2p3.fsf@firetop.home> <87zlpuxqfb.fsf@firetop.home> In-Reply-To: <87zlpuxqfb.fsf@firetop.home> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19485 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maxim@codesourcery.com Precedence: bulk X-list: linux-mips Richard Sandiford wrote: ... > +
  • The MIPS port no longer recognizes the h > + asm constraint. It was necessary to remove > + this constraint in order to avoid generating unpredictable > + code sequences. > + > +

    One of the main uses of the h constraint > + was to extract the high part of a multiplication on > + 64-bit targets. For example:

    > + 
    > +    asm ("dmultu\t%1,%2" : "=h" (result) : "r" (x), "r" (y));
    > +

    You can now achieve the same effect using 128-bit types:

    > + 
    > +    typedef unsigned int uint128_t __attribute__((mode(TI)));
> +    result = ((uint128_t) x * y) >> 64;
    > +

    The second sequence is better in many ways. For example, > + if x and y are constants, the > + compiler can perform the multiplication at compile time. > + If x and y are not constants, > + the compiler can schedule the runtime multiplication > + better than it can schedule an asm statement.

    > +
    • > Hi, GLIBC contains the following code in stdlib/longlong.h: #if defined (__mips__) && W_TYPE_SIZE == 32 #define umul_ppmm(w1, w0, u, v) \ __asm__ ("multu %2,%3" \ : "=l" ((USItype) (w0)), \ "=h" ((USItype) (w1)) \ : "d" ((USItype) (u)), \ "d" ((USItype) (v))) #define UMUL_TIME 10 #define UDIV_TIME 100 #endif /* __mips__ */ What would be a correct fix in this case? Something like this: #define umul_ppmm(w1, w0, u, v) \ ({unsigned int __attribute__((mode(DI))) __xx; \ __xx = (unsigned int __attribute__((mode(DI)))) u * v; \ w0 = __xx & ((1 << 32) - 1); \ w1 = __xx >> 32;}) Or is there a better way? Thanks, Maxim From kevink@mips.com Wed Jun 11 19:50:41 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 19:50:44 +0100 (BST) Received: from mx.mips.com ([63.167.95.198]:33515 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S20039320AbYFKSul (ORCPT ); Wed, 11 Jun 2008 19:50:41 +0100 Received: from mercury.mips.com (mercury [192.168.64.101]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id m5BIn2f0015804; Wed, 11 Jun 2008 11:49:02 -0700 (PDT) Received: from [127.0.0.1] (grendel [192.168.236.16]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id m5BInbJW014977; Wed, 11 Jun 2008 11:49:53 -0700 (PDT) Message-ID: <48501E9E.1040202@mips.com> Date: Wed, 11 Jun 2008 20:51:10 +0200 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.14 (Windows/20080421) MIME-Version: 1.0 To: Brian Foster CC: David Daney , linux-mips@linux-mips.org, Thiemo Seufer , "Kevin D. Kissell" , Andrew Dyer Subject: Re: Adding(?) XI support to MIPS-Linux? References: <200806091658.10937.brian.foster@innova-card.com> <20080610095702.GG11233@networkno.de> <484EAA16.80903@avtrex.com> <200806111516.57406.brian.foster@innova-card.com> In-Reply-To: <200806111516.57406.brian.foster@innova-card.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19486 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@mips.com Precedence: bulk X-list: linux-mips Brian Foster wrote: > It's case 2 (above), the trampoline that has “something > to do with FPU emulation”, which has me concerned ATM. > The 4KSd core does not have an FPU. That encourages the > use of ‘-msoft-float’ (at least for performance), but does > not require it. (Albeit I wonder if, in the restricted > world I'm playing in, if it could be “required” (assuming > it doesn't have an issue?)? Hum .... .) > The use of -msoft-float historically required (and as far as I know still requires) a completely different ground-up userland build, so it gets used less than you might think. > The quick summary (which I'm sure others on this list can > clarify/correct) is the FP trampoline, which is pushed on > the user-land stack is, unlike sigreturn, not fixed code. > It varies on a per-instance per-thread basis. Hence the > simple ‘vsyscall’ mechanism ((to be?) used for sigreturn) > is inappropriate. > > The trampoline is only used to execute a non-FP instruction > () in the delay slot of an FP-instruction: > > # Non-FP instruction to execute in user-land > BADINST # Bad instruction forcing return to FP emulator > COOKIE # Bad instruction (not executed) for verification > # Where to resume execution after > > Belch! ;-\ Whilst I can think of a few things that may work > (temporarily change page permissions; or go ahead and use > the ‘vsyscall’ page with some interlocking magic; or a new > new dedicated per-thread page; or ...?) none seem appealing. > > Suggestions? Comments? Prior art to study? > As the jerk who originally bolted the FP emulator into the MIPS kernel and came up with the stack trampoline hack, I can explain why it seemed sane at the time. If an FP branch is emulated and to be taken, we have to find a way for the instruction in the delay slot to be executed prior to the transfer of control to the branch target. It has to execute with the user's permissions. Putting it on the user's stack and building a trampoline was the fairly classical way of doing it, but note that it's architecturally illegal to put a branch in a branch delay slot (floating point or otherwise), so there's no possibility of recursion. So one only needs 3-4 words (one could substitute another means of validation for the cookie) per thread. It just has to be part of the user's address space. I suppose that instead of using a few words just above the stack, one could use a few words just below the current "brk()" point, or, better still (but far more invasive) pad the text segment, which should always be executable, with 4 words that the kernel can find in a hurry. Regards, Kevin K. From rdsandiford@googlemail.com Wed Jun 11 19:54:22 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 19:54:24 +0100 (BST) Received: from ug-out-1314.google.com ([66.249.92.170]:2716 "EHLO ug-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20039520AbYFKSyW (ORCPT ); Wed, 11 Jun 2008 19:54:22 +0100 Received: by ug-out-1314.google.com with SMTP id 30so164372ugs.39 for ; Wed, 11 Jun 2008 11:54:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:mail-followup-to:cc :subject:references:date:in-reply-to:message-id:user-agent :mime-version:content-type; bh=ywuunZExzVpom9xfe8qpV3W1kdM7gCA637PSAqoa9BQ=; b=nJueQ3pw3vRk3syPU1gLlTMQW1nupuvDk1aR1TtUaldE9rUMa3C21LSg0omlsc5J0g iYc4p/kLObnr1VGJe0xU94nU0c2c/VEZGpaDtBtPnggaqdaod9lhEaD1JihlXrVvgGFo 75oxpsFiep4/xLCdeounVEi/pL2MbItrlq1no= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:mail-followup-to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-type; b=V3HZbpgtCqlGaH3Uf10uI48WgJku3dIrCcRaC2g7JVcZV+w2IiZZDKvIMfP/dlkIrw z+SI0tafZO6rpj/nYYAOs4p9d3FYAm5V05EviWOzbELPg0kWb3FDEyEEp8gcvKQAB2KV eLA1zv7BwFXtknHUvQ5haI/aCovs2mrqQJnCQ= Received: by 10.210.78.16 with SMTP id a16mr122963ebb.173.1213210460843; Wed, 11 Jun 2008 11:54:20 -0700 (PDT) Received: from localhost ( [79.75.55.39]) by mx.google.com with ESMTPS id m5sm404771gve.3.2008.06.11.11.54.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 11 Jun 2008 11:54:19 -0700 (PDT) From: Richard Sandiford To: Maxim Kuvyrkov Mail-Followup-To: Maxim Kuvyrkov ,"Maciej W. Rozycki" , Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Cc: "Maciej W. Rozycki" , Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org Subject: Re: Changing the treatment of the MIPS HI and LO registers References: <87tzgj4nh6.fsf@firetop.home> <87abib4d9t.fsf@firetop.home> <87r6bm1ebd.fsf@firetop.home> <878wxtvarg.fsf@firetop.home> <8763stz2p3.fsf@firetop.home> <87zlpuxqfb.fsf@firetop.home> <48501C55.5060602@codesourcery.com> Date: Wed, 11 Jun 2008 19:54:17 +0100 In-Reply-To: <48501C55.5060602@codesourcery.com> (Maxim Kuvyrkov's message of "Wed\, 11 Jun 2008 22\:41\:25 +0400") Message-ID: <87hcbzx0o6.fsf@firetop.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19487 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rdsandiford@googlemail.com Precedence: bulk X-list: linux-mips Maxim Kuvyrkov writes: > GLIBC contains the following code in stdlib/longlong.h: > > #if defined (__mips__) && W_TYPE_SIZE == 32 > #define umul_ppmm(w1, w0, u, v) \ > __asm__ ("multu %2,%3" \ > : "=l" ((USItype) (w0)), \ > "=h" ((USItype) (w1)) \ > : "d" ((USItype) (u)), \ > "d" ((USItype) (v))) > #define UMUL_TIME 10 > #define UDIV_TIME 100 > #endif /* __mips__ */ > > > What would be a correct fix in this case? Something like this: > > #define umul_ppmm(w1, w0, u, v) \ > ({unsigned int __attribute__((mode(DI))) __xx; \ > __xx = (unsigned int __attribute__((mode(DI)))) u * v; \ > w0 = __xx & ((1 << 32) - 1); \ > w1 = __xx >> 32;}) > > > Or is there a better way? All being well, you should just be able to do the same as I did for GCC's copy of longlong.h (included in the patch you responded to). Richard From christophertaeufert@web.de Wed Jun 11 20:33:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Jun 2008 20:33:50 +0100 (BST) Received: from fmmailgate01.web.de ([217.72.192.221]:3721 "EHLO fmmailgate01.web.de") by ftp.linux-mips.org with ESMTP id S20041617AbYFKTMp (ORCPT ); Wed, 11 Jun 2008 20:12:45 +0100 Received: from smtp08.web.de (fmsmtp08.dlan.cinetic.de [172.20.5.216]) by fmmailgate01.web.de (Postfix) with ESMTP id 6534FE3AABAE for ; Wed, 11 Jun 2008 21:12:40 +0200 (CEST) Received: from [87.188.98.65] (helo=[192.168.2.28]) by smtp08.web.de with asmtp (WEB.DE 4.109 #226) id 1K6VkL-0003t5-00 for linux-mips@linux-mips.org; Wed, 11 Jun 2008 21:12:37 +0200 Subject: kernel 2.4.16 patch for cmd64x ide controler driver on kernel 2.35.3 From: christopher To: linux-mips@linux-mips.org Content-Type: multipart/mixed; boundary="=-fOaVjnvrQVA4JnChdsZs" Date: Wed, 11 Jun 2008 21:12:39 +0200 Message-Id: <1213211559.8316.26.camel@fuckup-ubuntu> Mime-Version: 1.0 X-Mailer: Evolution 2.22.2 X-Sender: christophertaeufert@web.de X-Provags-ID: V01U2FsdGVkX19CB8kN0+FAuqPOQuFadJzymTKaiviQIhY2N9/R QDzawBwR0vJOIPWKdkZbuXwIEDQnRXZu7lkXz98Ahf0lNbcOJf umwCTAxUfoG7+0BJqtnw== Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19488 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: christophertaeufert@web.de Precedence: bulk X-list: linux-mips --=-fOaVjnvrQVA4JnChdsZs Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Hello at first excuse my bad english but i gave my best. I have a claxan nas110 mit a toshiba mispel cpu. On this nas i'm running an alternate firmware called OpenMCT these firmware uses in its actual realeas kernel 2.4.35.3. The original Firmware of the nas use Kernel 2.4.16 with some patches form claxan. In the nas i would like to use an sata hdd with an satat ide adapter. With the Original firmware the adapter works, but with the OpenMCT Firmware it doesn#T work correctly. So i made a patch fpr the cmd649 ide controler out of claxans 2.4.16 source and the original 2.4.16 source form the file cmd64x.c but when i try to applie the patch on 2.4.35.3 the are only 4 of 20 hunks that succeeded. with these 4 succeeded hunks the adpater will recognized during boot of the nas but i think when 16 hunks fail something must be wrong. the problem is that my knowlegd about programming the kernel is very little to nothing. so i'm looking for help to make the patch work correctly with the kernel 2.4.35.3 and hope some of you can help my to make the patch work. i attached the patch to this mail thanks christopher t=C3=A4ufert --=-fOaVjnvrQVA4JnChdsZs Content-Disposition: attachment; filename=015-cmd64x.h.patch Content-Type: text/x-patch; name=015-cmd64x.h.patch; charset=UTF-8 Content-Transfer-Encoding: 7bit --- linux-2.4.16/drivers/ide/cmd64x.c 2001-12-28 22:06:01.000000000 +0100 +++ linux/drivers/ide/cmd64x.c 2005-03-31 11:19:27.000000000 +0200 @@ -86,6 +86,7 @@ #include static int cmd64x_get_info(char *, char **, off_t, int); +static int cmd680_get_info(char *, char **, off_t, int); extern int (*cmd64x_display_info)(char *, char **, off_t, int); /* ide-proc.c */ extern char *ide_media_verbose(ide_drive_t *); static struct pci_dev *bmide_dev; @@ -180,24 +181,21 @@ return p-buffer; /* => must be less than 4k! */ } -#if 0 -static char * cmd64x_chipset_data (char *buf, struct pci_dev *dev) -{ - char *p = buf; - p += sprintf(p, "thingy stuff\n"); - return (char *)p; -} -static int __init cmd64x_get_info (char *buffer, char **addr, off_t offset, int count) +static int cmd680_get_info (char *buffer, char **addr, off_t offset, int count) { char *p = buffer; - p = cmd64x_chipset_data(buffer, bmide_dev); - return p-buffer; /* hoping it is less than 4K... */ + p += sprintf(p, "\n CMD680 Chipset.\n"); + p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n"); + p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n"); + p += sprintf(p, "PIO Mode: %s %s %s %s\n", + "?", "?", "?", "?"); + return p-buffer; /* => must be less than 4k! */ } -#endif #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */ byte cmd64x_proc = 0; +byte cmd680_proc = 0; /* * Registers and masks for easy access by drive index: @@ -345,10 +343,58 @@ setup_count, active_count, recovery_count); } -static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed) +static byte cmd680_taskfile_timing (ide_hwif_t *hwif) +{ + struct pci_dev *dev = hwif->pci_dev; + byte addr_mask = (hwif->channel) ? 0xB2 : 0xA2; + unsigned short timing; + + pci_read_config_word(dev, addr_mask, &timing); + + switch (timing) { + case 0x10c1: return 4; + case 0x10c3: return 3; + case 0x1281: return 2; + case 0x2283: return 1; + case 0x328a: + default: return 0; + } +} + +static void cmd680_tuneproc (ide_drive_t *drive, byte mode_wanted) { - byte speed= 0x00; - byte set_pio= ide_get_best_pio_mode(drive, 4, 5, NULL); + ide_hwif_t *hwif = HWIF(drive); + struct pci_dev *dev = hwif->pci_dev; + byte drive_pci; + unsigned short speedt; + + switch (drive->dn) { + case 0: drive_pci = 0xA4; break; + case 1: drive_pci = 0xA6; break; + case 2: drive_pci = 0xB4; break; + case 3: drive_pci = 0xB6; break; + default: return; + } + + pci_read_config_word(dev, drive_pci, &speedt); + + /* cheat for now and use the docs */ +// switch(cmd680_taskfile_timing(hwif)) { + switch(mode_wanted) { + case 4: speedt = 0x10c1; break; + case 3: speedt = 0x10C3; break; + case 2: speedt = 0x1104; break; + case 1: speedt = 0x2283; break; + case 0: + default: speedt = 0x328A; break; + } + pci_write_config_word(dev, drive_pci, speedt); +} + +static void config_cmd64x_chipset_for_pio (ide_drive_t *drive, byte set_speed) +{ + byte speed = 0x00; + byte set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL); cmd64x_tuneproc(drive, set_pio); speed = XFER_PIO_0 + set_pio; @@ -356,6 +402,41 @@ (void) ide_config_drive_speed(drive, speed); } +static void config_cmd680_chipset_for_pio (ide_drive_t *drive, byte set_speed) +{ + ide_hwif_t *hwif = HWIF(drive); + struct pci_dev *dev = hwif->pci_dev; + u8 unit = (drive->select.b.unit & 0x01); + u8 addr_mask = (hwif->channel) ? 0x84 : 0x80; + u8 speed = 0x00; + u8 mode_pci = 0x00; + u8 channel_timings = cmd680_taskfile_timing(hwif); + u8 set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL); + + pci_read_config_byte(dev, addr_mask, &mode_pci); + mode_pci &= ~((unit) ? 0x30 : 0x03); + + /* WARNING PIO timing mess is going to happen b/w devices, argh */ + if ((channel_timings != set_pio) && (set_pio > channel_timings)) + set_pio = channel_timings; + + cmd680_tuneproc(drive, set_pio); + speed = XFER_PIO_0 + set_pio; + if (set_speed) { + (void) ide_config_drive_speed(drive, speed); + drive->current_speed = speed; + } +} + +static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed) +{ + if (HWIF(drive)->pci_dev->device == PCI_DEVICE_ID_CMD_680) { + config_cmd680_chipset_for_pio(drive, set_speed); + } else { + config_cmd64x_chipset_for_pio(drive, set_speed); + } +} + static int cmd64x_tune_chipset (ide_drive_t *drive, byte speed) { #ifdef CONFIG_BLK_DEV_IDEDMA @@ -363,7 +444,7 @@ struct pci_dev *dev = hwif->pci_dev; int err = 0; - byte unit = (drive->select.b.unit & 0x01); + u8 unit = (drive->select.b.unit & 0x01); u8 pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0; u8 pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0; u8 regU = 0; @@ -424,8 +505,123 @@ return err; } +static int cmd680_tune_chipset (ide_drive_t *drive, byte speed) +{ + ide_hwif_t *hwif = HWIF(drive); + struct pci_dev *dev = hwif->pci_dev; + u8 addr_mask = (hwif->channel) ? 0x84 : 0x80; + u8 unit = (drive->select.b.unit & 0x01); + u8 dma_pci = 0; + u8 udma_pci = 0; + u8 mode_pci = 0; + u8 scsc = 0; + u16 ultra = 0; + u16 multi = 0; + int err = 0; + + pci_read_config_byte(dev, addr_mask, &mode_pci); + pci_read_config_byte(dev, 0x8A, &scsc); + + switch (drive->dn) { + case 0: dma_pci = 0xA8; udma_pci = 0xAC; break; + case 1: dma_pci = 0xAA; udma_pci = 0xAE; break; + case 2: dma_pci = 0xB8; udma_pci = 0xBC; break; + case 3: dma_pci = 0xBA; udma_pci = 0xBE; break; + default: return 1; + } + + pci_read_config_byte(dev, addr_mask, &mode_pci); + mode_pci &= ~((unit) ? 0x30 : 0x03); + pci_read_config_word(dev, dma_pci, &multi); + pci_read_config_word(dev, udma_pci, &ultra); + + if ((speed == XFER_UDMA_6) && (scsc & 0x30) == 0x00) { + pci_write_config_byte(dev, 0x8A, scsc|0x01); + pci_read_config_byte(dev, 0x8A, &scsc); + } + + switch(speed) { #ifdef CONFIG_BLK_DEV_IDEDMA -static int config_chipset_for_dma (ide_drive_t *drive, unsigned int rev, byte ultra_66) + case XFER_UDMA_6: + if ((scsc & 0x30) == 0x00) + goto speed_break; + multi = 0x10C1; + ultra &= ~0x3F; + ultra |= 0x01; + break; +speed_break : + speed = XFER_UDMA_5; + case XFER_UDMA_5: + multi = 0x10C1; + ultra &= ~0x3F; + ultra |= (((scsc & 0x30) == 0x00) ? 0x01 : 0x02); + break; + case XFER_UDMA_4: + multi = 0x10C1; + ultra &= ~0x3F; + ultra |= (((scsc & 0x30) == 0x00) ? 0x02 : 0x03); + break; + case XFER_UDMA_3: + multi = 0x10C1; + ultra &= ~0x3F; + ultra |= (((scsc & 0x30) == 0x00) ? 0x04 : 0x05); + break; + case XFER_UDMA_2: + multi = 0x10C1; + ultra &= ~0x3F; + ultra |= (((scsc & 0x30) == 0x00) ? 0x05 : 0x07); + break; + case XFER_UDMA_1: + multi = 0x10C1; + ultra &= ~0x3F; + ultra |= (((scsc & 0x30) == 0x00) ? 0x07 : 0x0B); + break; + case XFER_UDMA_0: + multi = 0x10C1; + ultra &= ~0x3F; + ultra |= (((scsc & 0x30) == 0x00) ? 0x0C : 0x0F); + break; + case XFER_MW_DMA_2: + multi = 0x10C1; + break; + case XFER_MW_DMA_1: + multi = 0x10C2; + break; + case XFER_MW_DMA_0: + multi = 0x2208; + break; +#endif /* CONFIG_BLK_DEV_IDEDMA */ + case XFER_PIO_4: cmd680_tuneproc(drive, 4); break; + case XFER_PIO_3: cmd680_tuneproc(drive, 3); break; + case XFER_PIO_2: cmd680_tuneproc(drive, 2); break; + case XFER_PIO_1: cmd680_tuneproc(drive, 1); break; + case XFER_PIO_0: cmd680_tuneproc(drive, 0); break; + default: + return 1; + } + + + if (speed >= XFER_MW_DMA_0) + config_cmd680_chipset_for_pio(drive, 0); + + if (speed >= XFER_UDMA_0) + mode_pci |= ((unit) ? 0x30 : 0x03); + else if (speed >= XFER_MW_DMA_0) + mode_pci |= ((unit) ? 0x20 : 0x02); + else + mode_pci |= ((unit) ? 0x10 : 0x01); + + pci_write_config_byte(dev, addr_mask, mode_pci); + pci_write_config_word(dev, dma_pci, multi); + pci_write_config_word(dev, udma_pci, ultra); + + err = ide_config_drive_speed(drive, speed); + drive->current_speed = speed; + return err; +} + +#ifdef CONFIG_BLK_DEV_IDEDMA +static int config_cmd64x_chipset_for_dma (ide_drive_t *drive, unsigned int rev, byte ultra_66) { struct hd_driveid *id = drive->id; ide_hwif_t *hwif = HWIF(drive); @@ -493,6 +689,10 @@ if (!drive->init_speed) drive->init_speed = speed; +//test +// set_pio = 0; +// speed = 0; +// config_chipset_for_pio(drive, set_pio); if (set_pio) @@ -510,6 +710,55 @@ return rval; } +static int config_cmd680_chipset_for_dma (ide_drive_t *drive) +{ + struct hd_driveid *id = drive->id; + byte udma_66 = eighty_ninty_three(drive); + byte speed = 0x00; + byte set_pio = 0x00; + int rval; + + if ((id->dma_ultra & 0x0040) && (udma_66)) speed = XFER_UDMA_6; + else if ((id->dma_ultra & 0x0020) && (udma_66)) speed = XFER_UDMA_5; + else if ((id->dma_ultra & 0x0010) && (udma_66)) speed = XFER_UDMA_4; + else if ((id->dma_ultra & 0x0008) && (udma_66)) speed = XFER_UDMA_3; + else if (id->dma_ultra & 0x0004) speed = XFER_UDMA_2; + else if (id->dma_ultra & 0x0002) speed = XFER_UDMA_1; + else if (id->dma_ultra & 0x0001) speed = XFER_UDMA_0; + else if (id->dma_mword & 0x0004) speed = XFER_MW_DMA_2; + else if (id->dma_mword & 0x0002) speed = XFER_MW_DMA_1; + else if (id->dma_mword & 0x0001) speed = XFER_MW_DMA_0; + else { + set_pio = 1; + } + + if (!drive->init_speed) + drive->init_speed = speed; + + config_chipset_for_pio(drive, set_pio); + + if (set_pio) + return ((int) ide_dma_off_quietly); + + if (cmd680_tune_chipset(drive, speed)) + return ((int) ide_dma_off); + + rval = (int)( ((id->dma_ultra >> 14) & 3) ? ide_dma_on : + ((id->dma_ultra >> 11) & 7) ? ide_dma_on : + ((id->dma_ultra >> 8) & 7) ? ide_dma_on : + ((id->dma_mword >> 8) & 7) ? ide_dma_on : + ((id->dma_1word >> 8) & 7) ? ide_dma_on : + ide_dma_off_quietly); + return rval; +} + +static int config_chipset_for_dma (ide_drive_t *drive, unsigned int rev, byte ultra_66) +{ + if (HWIF(drive)->pci_dev->device == PCI_DEVICE_ID_CMD_680) + return (config_cmd680_chipset_for_dma(drive)); + return (config_cmd64x_chipset_for_dma(drive, rev, ultra_66)); +} + static int cmd64x_config_drive_for_dma (ide_drive_t *drive) { struct hd_driveid *id = drive->id; @@ -519,12 +768,15 @@ byte can_ultra_33 = 0; byte can_ultra_66 = 0; byte can_ultra_100 = 0; + byte can_ultra_133 = 0; ide_dma_action_t dma_func = ide_dma_on; pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); class_rev &= 0xff; switch(dev->device) { + case PCI_DEVICE_ID_CMD_680: + can_ultra_133 = 1; case PCI_DEVICE_ID_CMD_649: can_ultra_100 = 1; case PCI_DEVICE_ID_CMD_648: @@ -550,7 +802,7 @@ } dma_func = ide_dma_off_quietly; if ((id->field_valid & 4) && (can_ultra_33)) { - if (id->dma_ultra & 0x002F) { + if (id->dma_ultra & 0x007F) { /* Force if Capable UltraDMA */ dma_func = config_chipset_for_dma(drive, class_rev, can_ultra_66); if ((id->field_valid & 2) && @@ -586,6 +838,18 @@ return HWIF(drive)->dmaproc(dma_func, drive); } +static int cmd680_dmaproc (ide_dma_action_t func, ide_drive_t *drive) +{ + switch (func) { + case ide_dma_check: + return cmd64x_config_drive_for_dma(drive); + default: + break; + } + /* Other cases are done by generic IDE-DMA code. */ + return ide_dmaproc(func, drive); +} + static int cmd64x_dmaproc (ide_dma_action_t func, ide_drive_t *drive) { byte dma_stat = 0; @@ -663,7 +927,78 @@ } #endif /* CONFIG_BLK_DEV_IDEDMA */ -unsigned int __init pci_init_cmd64x (struct pci_dev *dev, const char *name) +static int cmd680_busproc (ide_drive_t * drive, int state) +{ +#if 0 + ide_hwif_t *hwif = HWIF(drive); + u8 addr_mask = (hwif->channel) ? 0xB0 : 0xA0; + u32 stat_config = 0; + + pci_read_config_dword(hwif->pci_dev, addr_mask, &stat_config); + + if (!hwif) + return -EINVAL; + + switch (state) { + case BUSSTATE_ON: + hwif->drives[0].failures = 0; + hwif->drives[1].failures = 0; + break; + case BUSSTATE_OFF: + hwif->drives[0].failures = hwif->drives[0].max_failures + 1; + hwif->drives[1].failures = hwif->drives[1].max_failures + 1; + break; + case BUSSTATE_TRISTATE: + hwif->drives[0].failures = hwif->drives[0].max_failures + 1; + hwif->drives[1].failures = hwif->drives[1].max_failures + 1; + break; + default: + return 0; + } + hwif->bus_state = state; +#endif + return 0; +} + +void cmd680_reset (ide_drive_t *drive) +{ +#if 0 + ide_hwif_t *hwif = HWIF(drive); + u8 addr_mask = (hwif->channel) ? 0xB0 : 0xA0; + byte reset = 0; + + pci_read_config_byte(hwif->pci_dev, addr_mask, &reset); + pci_write_config_byte(hwif->pci_dev, addr_mask, reset|0x03); +#endif +} + +unsigned int cmd680_pci_init (struct pci_dev *dev, const char *name) +{ + u8 tmpbyte = 0; + pci_write_config_byte(dev, 0x80, 0x00); + pci_write_config_byte(dev, 0x84, 0x00); + pci_read_config_byte(dev, 0x8A, &tmpbyte); + pci_write_config_byte(dev, 0x8A, tmpbyte|0x01); + pci_write_config_word(dev, 0xA2, 0x328A); + pci_write_config_dword(dev, 0xA4, 0x328A); + pci_write_config_dword(dev, 0xA8, 0x4392); + pci_write_config_dword(dev, 0xAC, 0x4009); + pci_write_config_word(dev, 0xB2, 0x328A); + pci_write_config_dword(dev, 0xB4, 0x328A); + pci_write_config_dword(dev, 0xB8, 0x4392); + pci_write_config_dword(dev, 0xBC, 0x4009); + +#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) + if (!cmd64x_proc) { + cmd64x_proc = 1; + bmide_dev = dev; + cmd64x_display_info = &cmd680_get_info; + } +#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */ + return 0; +} + +unsigned int cmd64x_pci_init (struct pci_dev *dev, const char *name) { unsigned char mrdmode; unsigned int class_rev; @@ -707,9 +1042,9 @@ /* Set a good latency timer and cache line size value. */ (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); -#ifdef __sparc_v9__ + + /* Ethan: the cache line size fails to be updated. */ (void) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x10); -#endif /* Setup interrupts. */ @@ -723,7 +1058,12 @@ * back as set or not. The PCI0646U2 specs clarify * this point. */ +#if 1 (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02); +#else + /* use MEMORY READ MULTIPLE */ + (void) pci_write_config_byte(dev, MRDMODE, (mrdmode & 0xfc) | 0x01); +#endif /* Set reasonable active/recovery/address-setup values. */ (void) pci_write_config_byte(dev, ARTTIM0, 0x40); @@ -740,6 +1080,7 @@ #ifdef CONFIG_PPC (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0); #endif /* CONFIG_PPC */ + pci_write_config_byte(dev, CMDTIM, 0x21); #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) if (!cmd64x_proc) { @@ -748,11 +1089,43 @@ cmd64x_display_info = &cmd64x_get_info; } #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */ +//added by louis +// pci_write_config_byte(dev, 0x51, 0xe4); +// only for debug use +#if 0 + { + int i; + for (i = 0; i < 256; i++) { + u8 val; + if ( i % 16 == 0 ) + printk("\n%02x: ", i); + pci_read_config_byte(dev, i, &val); + printk("%02x ", val); + } + printk("\n"); + } +#endif return 0; } -unsigned int __init ata66_cmd64x (ide_hwif_t *hwif) +unsigned int __init pci_init_cmd64x (struct pci_dev *dev, const char *name) +{ + if (dev->device == PCI_DEVICE_ID_CMD_680) + return cmd680_pci_init (dev, name); + return cmd64x_pci_init (dev, name); +} + +unsigned int cmd680_ata66 (ide_hwif_t *hwif) +{ + byte ata66 = 0; + byte addr_mask = (hwif->channel) ? 0xB0 : 0xA0; + + pci_read_config_byte(hwif->pci_dev, addr_mask, &ata66); + return (ata66 & 0x01) ? 1 : 0; +} + +unsigned int cmd64x_ata66 (ide_hwif_t *hwif) { byte ata66 = 0; byte mask = (hwif->channel) ? 0x02 : 0x01; @@ -761,6 +1134,14 @@ return (ata66 & mask) ? 1 : 0; } +unsigned int __init ata66_cmd64x (ide_hwif_t *hwif) +{ + struct pci_dev *dev = hwif->pci_dev; + if (dev->device == PCI_DEVICE_ID_CMD_680) + return cmd680_ata66(hwif); + return cmd64x_ata66(hwif); +} + void __init ide_init_cmd64x (ide_hwif_t *hwif) { struct pci_dev *dev = hwif->pci_dev; @@ -769,8 +1150,6 @@ pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); class_rev &= 0xff; - hwif->tuneproc = &cmd64x_tuneproc; - hwif->speedproc = &cmd64x_tune_chipset; hwif->drives[0].autotune = 1; hwif->drives[1].autotune = 1; @@ -779,10 +1158,19 @@ #ifdef CONFIG_BLK_DEV_IDEDMA switch(dev->device) { + case PCI_DEVICE_ID_CMD_680: + hwif->busproc = &cmd680_busproc; + hwif->dmaproc = &cmd680_dmaproc; + hwif->resetproc = &cmd680_reset; + hwif->speedproc = &cmd680_tune_chipset; + hwif->tuneproc = &cmd680_tuneproc; + break; case PCI_DEVICE_ID_CMD_649: case PCI_DEVICE_ID_CMD_648: case PCI_DEVICE_ID_CMD_643: - hwif->dmaproc = &cmd64x_dmaproc; + hwif->dmaproc = &cmd64x_dmaproc; + hwif->tuneproc = &cmd64x_tuneproc; + hwif->speedproc = &cmd64x_tune_chipset; break; case PCI_DEVICE_ID_CMD_646: hwif->chipset = ide_cmd646; @@ -791,6 +1179,8 @@ } else { hwif->dmaproc = &cmd64x_dmaproc; } + hwif->tuneproc = &cmd64x_tuneproc; + hwif->speedproc = &cmd64x_tune_chipset; break; default: break; --=-fOaVjnvrQVA4JnChdsZs-- From paolo.bonzini@gmail.com Thu Jun 12 00:24:42 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 00:24:44 +0100 (BST) Received: from yw-out-1718.google.com ([74.125.46.156]:20446 "EHLO yw-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S20040942AbYFKXYm (ORCPT ); Thu, 12 Jun 2008 00:24:42 +0100 Received: by yw-out-1718.google.com with SMTP id 9so1690999ywk.24 for ; Wed, 11 Jun 2008 16:24:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding:sender; bh=igQVFScsQAz5rH5aanlAlNbrqEX1ZWZruq2DvHEezow=; b=S9RDrVL6/Da23VdeFyIOi3zkvfn/MNShv4pZhNBYbNfe4ZbbuiA3iSsc6iMDeRG4bF vqdiBDAA3SIZa1RTEFYJo9ecNtg82q2hU8qXwdqOtFHfMAenDMwF6g89aB06Vaeih9We NoMxcvIFiQbsx+ffTwjHEF4W3CAQkYuXM1fCM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding :sender; b=najfc6+uFswfjhA2qT6aB3WxJuIjiyqj2bF/EWXzPX3ZmEV/hVVNZx2Y9rU2ka4rLe fy5BjSYyhnWB8MryfueZl0NxUdjWCwiwLslnsZgAG0n4Dk8kuQeLHWwsBpgOeQAG6O+7 +DiAL0FnkVUSHiR4o5Eh0PDJleVFDtoXi9vds= Received: by 10.150.192.7 with SMTP id p7mr1135101ybf.91.1213226672307; Wed, 11 Jun 2008 16:24:32 -0700 (PDT) Received: from scientist-2.local ( [66.78.193.51]) by mx.google.com with ESMTPS id x56sm2000279pyg.10.2008.06.11.16.24.28 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 11 Jun 2008 16:24:31 -0700 (PDT) Message-ID: <48505EAC.6050404@gnu.org> Date: Wed, 11 Jun 2008 16:24:28 -0700 From: Paolo Bonzini User-Agent: Thunderbird 2.0.0.14 (Macintosh/20080421) MIME-Version: 1.0 To: Maxim Kuvyrkov CC: "Maciej W. Rozycki" , Ralf Baechle , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org, rdsandiford@googlemail.com Subject: Re: Changing the treatment of the MIPS HI and LO registers References: <87tzgj4nh6.fsf@firetop.home> <87abib4d9t.fsf@firetop.home> <87r6bm1ebd.fsf@firetop.home> <878wxtvarg.fsf@firetop.home> <8763stz2p3.fsf@firetop.home> <87zlpuxqfb.fsf@firetop.home> <48501C55.5060602@codesourcery.com> In-Reply-To: <48501C55.5060602@codesourcery.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19489 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bonzini@gnu.org Precedence: bulk X-list: linux-mips > GLIBC contains the following code in stdlib/longlong.h: > > #if defined (__mips__) && W_TYPE_SIZE == 32 > #define umul_ppmm(w1, w0, u, v) \ > __asm__ ("multu %2,%3" \ > : "=l" ((USItype) (w0)), \ > "=h" ((USItype) (w1)) \ > : "d" ((USItype) (u)), \ > "d" ((USItype) (v))) > #define UMUL_TIME 10 > #define UDIV_TIME 100 > #endif /* __mips__ */ > Actually, so does GCC itself. Can you prepare a patch? > What would be a correct fix in this case? Something like this: > > #define umul_ppmm(w1, w0, u, v) \ > ({unsigned int __attribute__((mode(DI))) __xx; \ > __xx = (unsigned int __attribute__((mode(DI)))) u * v; \ > w0 = __xx & ((1 << 32) - 1); \ > w1 = __xx >> 32;}) > > > Or is there a better way? Almost; this: #define umul_ppmm(w1, w0, u, v) \ ({UDWtype __xx; \ UWtype __u = (u), __v = (v); \ __xx = (UDWtype) __u * __v; \ w0 = (UWtype) __xx; \ w1 = __xx >> 32;}) should work. Paolo From ralf@linux-mips.org Thu Jun 12 08:26:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 08:26:27 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:34282 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28577823AbYFLH0Z (ORCPT ); Thu, 12 Jun 2008 08:26:25 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5C7Q5Da012575; Thu, 12 Jun 2008 08:26:05 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5C7Q551012569; Thu, 12 Jun 2008 08:26:05 +0100 Date: Thu, 12 Jun 2008 08:26:05 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/5] [MIPS] fix sparse warning about setup_early_printk() Message-ID: <20080612072604.GF30400@linux-mips.org> References: <12124843631664-git-send-email-dmitri.vorobiev@movial.fi> <12124843631742-git-send-email-dmitri.vorobiev@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <12124843631742-git-send-email-dmitri.vorobiev@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19490 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 03, 2008 at 12:12:40PM +0300, Dmitri Vorobiev wrote: > From: Dmitri Vorobiev > Date: Tue, 3 Jun 2008 12:12:40 +0300 > To: linux-mips@linux-mips.org, ralf@linux-mips.org > Subject: [PATCH 1/5] [MIPS] fix sparse warning about setup_early_printk() > > This patch fixes the following sparse warning: > > <<<<<<<< > > arch/mips/kernel/early_printk.c:35:13: warning: symbol 'setup_early_printk' > was not declared. Should it be static? > > <<<<<<<< > > The fix is to define a prototype of the setup_early_printk() function and > to include the appropriate header into arch/mips/kernel/early_printk.c. > > Signed-off-by: Dmitri Vorobiev > --- > arch/mips/kernel/early_printk.c | 1 + > arch/mips/kernel/setup.c | 6 +----- > include/asm-mips/setup.h | 2 ++ > 3 files changed, 4 insertions(+), 5 deletions(-) > > diff --git a/arch/mips/kernel/early_printk.c b/arch/mips/kernel/early_printk.c > index 9dccfa4..cb602c1 100644 > --- a/arch/mips/kernel/early_printk.c > +++ b/arch/mips/kernel/early_printk.c > @@ -7,6 +7,7 @@ > * Copyright (C) 2007 MIPS Technologies, Inc. > * written by Ralf Baechle (ralf@linux-mips.org) > */ > +#include > #include > #include Queued for 2.6.27 with includes sorted first followed by . Ralf From ralf@linux-mips.org Thu Jun 12 08:27:42 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 08:27:44 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:36074 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28577829AbYFLH1m (ORCPT ); Thu, 12 Jun 2008 08:27:42 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5C7RMNY013040; Thu, 12 Jun 2008 08:27:23 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5C7RM8O013039; Thu, 12 Jun 2008 08:27:22 +0100 Date: Thu, 12 Jun 2008 08:27:22 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/5] [MIPS] Make two functions static Message-ID: <20080612072722.GG30400@linux-mips.org> References: <12124843631664-git-send-email-dmitri.vorobiev@movial.fi> <12124843631632-git-send-email-dmitri.vorobiev@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <12124843631632-git-send-email-dmitri.vorobiev@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19491 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 03, 2008 at 12:12:41PM +0300, Dmitri Vorobiev wrote: > From: Dmitri Vorobiev > Date: Tue, 3 Jun 2008 12:12:41 +0300 > To: linux-mips@linux-mips.org, ralf@linux-mips.org > Subject: [PATCH 2/5] [MIPS] Make two functions static Queued for 2.6.27. Thanks, Ralf From ralf@linux-mips.org Thu Jun 12 08:37:08 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 08:37:10 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:3054 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S20022068AbYFLHhI (ORCPT ); Thu, 12 Jun 2008 08:37:08 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5C7amun016531; Thu, 12 Jun 2008 08:36:48 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5C7alfZ016523; Thu, 12 Jun 2008 08:36:47 +0100 Date: Thu, 12 Jun 2008 08:36:47 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 3/5] [MIPS] remove unused function alloc_legacy_irqno() Message-ID: <20080612073647.GH30400@linux-mips.org> References: <12124843631664-git-send-email-dmitri.vorobiev@movial.fi> <12124843634070-git-send-email-dmitri.vorobiev@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <12124843634070-git-send-email-dmitri.vorobiev@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19492 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 03, 2008 at 12:12:42PM +0300, Dmitri Vorobiev wrote: > The function alloc_legacy_irqno() is not used any more, and this > patch removes it. > > Inspired by a namespacecheck warning. NAK. While currently unused alloc_legacy_irqno() is needed for systems such as SGI IP27 which use dynamic interrupt number allocation and may feature EISA slots. So there eventually will be a caller. Ralf From ralf@linux-mips.org Thu Jun 12 08:41:10 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 08:41:12 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:26020 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28577949AbYFLHlK (ORCPT ); Thu, 12 Jun 2008 08:41:10 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5C7epWm018277; Thu, 12 Jun 2008 08:40:51 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5C7epP4018270; Thu, 12 Jun 2008 08:40:51 +0100 Date: Thu, 12 Jun 2008 08:40:51 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 4/5] [MIPS] unexport {allocate,free}_irqno Message-ID: <20080612074051.GI30400@linux-mips.org> References: <12124843631664-git-send-email-dmitri.vorobiev@movial.fi> <1212484363969-git-send-email-dmitri.vorobiev@movial.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1212484363969-git-send-email-dmitri.vorobiev@movial.fi> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19493 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 03, 2008 at 12:12:43PM +0300, Dmitri Vorobiev wrote: > The following routines > > allocate_irqno() > free_irqno() > > seem not to be used outside of the core kernel code, hence > exporting these functions is pointless. This patch removes > the export. And I don't see why one would want to use them in modules, so queue for 2.6.27 as well. Thanks, Ralf From rdsandiford@googlemail.com Thu Jun 12 09:27:16 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 09:27:19 +0100 (BST) Received: from ug-out-1314.google.com ([66.249.92.174]:54467 "EHLO ug-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S28577578AbYFLI1Q (ORCPT ); Thu, 12 Jun 2008 09:27:16 +0100 Received: by ug-out-1314.google.com with SMTP id 30so279217ugs.39 for ; Thu, 12 Jun 2008 01:27:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:mail-followup-to:cc :subject:references:date:in-reply-to:message-id:user-agent :mime-version:content-type; bh=wNjZmHEX6jVa8NDjAz4yAd+Haf+p5cjtOBBQPiuJcWg=; b=S6BlVV2UZ15i1fpwOtSE5N0Mxs/j/ka5ixLiGmcRaqZ85pa2RDfdx2FeKgmeuwjzVk phEhJjP1OAgwvxrel03jEIE9S4I1Kn7FadMUjszt0mT/OljT9dkIPkXhAlxbHb2LxWdk gMfizHIEUgvjCabD7AQWTQ+CIn4rNcV3xBrJA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:mail-followup-to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-type; b=bK5AwrOY/ATQ93WLvjgiElIZ1RY/EVxy54Gv8FUG0dMBqPEKwo8ncddSB25IXsTERf gtlxG+Ss8SxiWQej+hQu7EkGvoo/3Q9z9XPyfMVNJcTGz90WGoLiNSqj1QAyhBe3iLSK DWTigSGSpujNVGERqpwCieZdHsxztqr21u1ko= Received: by 10.210.54.19 with SMTP id c19mr823300eba.168.1213259234824; Thu, 12 Jun 2008 01:27:14 -0700 (PDT) Received: from localhost ( [79.75.55.39]) by mx.google.com with ESMTPS id t12sm1715476gvd.10.2008.06.12.01.27.12 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 12 Jun 2008 01:27:13 -0700 (PDT) From: Richard Sandiford To: David Daney Mail-Followup-To: David Daney ,Ralf Baechle , GCC Mailing List , MIPS Linux List , rdsandiford@googlemail.com Cc: Ralf Baechle , GCC Mailing List , MIPS Linux List Subject: Re: Resend: [PATCH] [MIPS] Fix asm constraints for 'ins' instructions. References: <48500599.9080807@avtrex.com> <20080611172950.GA16600@linux-mips.org> <48500EDD.404@avtrex.com> Date: Thu, 12 Jun 2008 09:27:10 +0100 In-Reply-To: <48500EDD.404@avtrex.com> (David Daney's message of "Wed\, 11 Jun 2008 10\:43\:57 -0700") Message-ID: <871w339hy9.fsf@firetop.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19494 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rdsandiford@googlemail.com Precedence: bulk X-list: linux-mips David Daney writes: > Ralf Baechle wrote: >> On Wed, Jun 11, 2008 at 10:04:25AM -0700, David Daney wrote: >> >>> The third operand to 'ins' must be a constant int, not a register. >>> >>> Signed-off-by: David Daney >>> --- >>> include/asm-mips/bitops.h | 6 +++--- >>> 1 files changed, 3 insertions(+), 3 deletions(-) >>> >>> diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h >>> index 6427247..9a7274b 100644 >>> --- a/include/asm-mips/bitops.h >>> +++ b/include/asm-mips/bitops.h >>> @@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) >>> "2: b 1b \n" >>> " .previous \n" >>> : "=&r" (temp), "=m" (*m) >>> - : "ir" (bit), "m" (*m), "r" (~0)); >>> + : "i" (bit), "m" (*m), "r" (~0)); >>> #endif /* CONFIG_CPU_MIPSR2 */ >>> } else if (cpu_has_llsc) { >>> __asm__ __volatile__( >> >> An old trick to get gcc to do the right thing. Basically at the stage when >> gcc is verifying the constraints it may not yet know that it can optimize >> things into an "i" argument, so compilation may fail if "r" isn't in the >> constraints. However we happen to know that due to the way the code is >> written gcc will always be able to make use of the "i" constraint so no >> code using "r" should ever be created. >> >> The trick is a bit ugly; I think it was used first in asm-i386/io.h ages ago >> and I would be happy if we could get rid of it without creating new problems. >> Maybe a gcc hacker here can tell more? > > It is not nice to lie to GCC. > > CCing GCC and Richard in hopes that a wider audience may shed some light on the issue. You _might_ be able to use "i#r" instead of "ri", but I wouldn't really recommend it. Even if it works now, I don't think there's any guarantee it will in future. There are tricks you could pull to detect the problem at compile time rather than assembly time, but that's probably not a big win. And again, I wouldn't recommend them. I'm not saying anything you don't know here, but if the argument is always a syntactic constant, the safest bet would be to apply David's patch and also convert the function into a macro. I notice some other ports use macros rather than inline functions here. I assume you've deliberately rejected macros as being too ugly though. Richard From ralf@linux-mips.org Thu Jun 12 10:02:38 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 10:02:40 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:42434 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28578097AbYFLJCi (ORCPT ); Thu, 12 Jun 2008 10:02:38 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5C92ENE020156; Thu, 12 Jun 2008 10:02:15 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5C927mG020100; Thu, 12 Jun 2008 10:02:07 +0100 Date: Thu, 12 Jun 2008 10:02:06 +0100 From: Ralf Baechle To: Manuel Lauss Cc: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/8] Alchemy: register mmc platform device for db1200/pb1200 boards. Message-ID: <20080612090206.GB21601@linux-mips.org> References: <20080609063521.GA8724@roarinelk.homelinux.net> <20080609063702.GC8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080609063702.GC8724@roarinelk.homelinux.net> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19495 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 09, 2008 at 08:37:02AM +0200, Manuel Lauss wrote: Only a few small nits ... > >From 536f44d2947f3883016b927a621e30782bd3149f Mon Sep 17 00:00:00 2001 > From: Manuel Lauss > Date: Sat, 17 May 2008 17:48:02 +0200 > Subject: [PATCH] Alchemy: register mmc platform device for db1200/pb1200 boards Please only post as part of the body what is supposed to go into the commit message. Three of these lines are junk which the maintainer applying the patch will have to remove ... > Add au1xmmc platform data for PB1200/DB1200 boards, and wire up > the 2 SD controllers for them. > > Signed-off-by: Manuel Lauss > --- > arch/mips/au1000/common/platform.c | 99 +++++++++++++++++++++++++++--------- > arch/mips/au1000/pb1200/platform.c | 81 +++++++++++++++++++++++++++++ > 2 files changed, 156 insertions(+), 24 deletions(-) > > diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c > index 8cae775..c235434 100644 > --- a/arch/mips/au1000/common/platform.c > +++ b/arch/mips/au1000/common/platform.c > @@ -16,6 +16,8 @@ > #include > > #include > +#include > +#include > > #define PORT(_base, _irq) \ > { \ > @@ -162,24 +164,6 @@ static struct resource au1xxx_usb_gdt_resources[] = { > }, > }; > > -static struct resource au1xxx_mmc_resources[] = { > - [0] = { > - .start = SD0_PHYS_ADDR, > - .end = SD0_PHYS_ADDR + 0x40, > - .flags = IORESOURCE_MEM, > - }, > - [1] = { > - .start = SD1_PHYS_ADDR, > - .end = SD1_PHYS_ADDR + 0x40, > - .flags = IORESOURCE_MEM, > - }, > - [2] = { > - .start = AU1200_SD_INT, > - .end = AU1200_SD_INT, > - .flags = IORESOURCE_IRQ, > - } > -}; > - > static u64 udc_dmamask = ~(u32)0; Okay, you didn't change this line but using DMA_32BIT_MASK would be cleaner ... > static struct platform_device au1xxx_usb_gdt_device = { > @@ -248,16 +232,80 @@ static struct platform_device au1200_lcd_device = { > > static u64 au1xxx_mmc_dmamask = ~(u32)0; Ditto. > -static struct platform_device au1xxx_mmc_device = { > +extern struct au1xmmc_platform_data au1xmmc_platdata[2]; > + > +static struct resource au1200_mmc0_resources[] = { > + [0] = { > + .start = SD0_PHYS_ADDR, > + .end = SD0_PHYS_ADDR + 0x7ffff, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { > + .start = AU1200_SD_INT, > + .end = AU1200_SD_INT, > + .flags = IORESOURCE_IRQ, > + }, > + [2] = { > + .start = DSCR_CMD0_SDMS_TX0, > + .end = DSCR_CMD0_SDMS_TX0, > + .flags = IORESOURCE_DMA, > + }, > + [3] = { > + .start = DSCR_CMD0_SDMS_RX0, > + .end = DSCR_CMD0_SDMS_RX0, > + .flags = IORESOURCE_DMA, > + } > +}; > + > +static struct platform_device au1200_mmc0_device = { > .name = "au1xxx-mmc", > .id = 0, > .dev = { > - .dma_mask = &au1xxx_mmc_dmamask, > - .coherent_dma_mask = 0xffffffff, > + .dma_mask = &au1xxx_mmc_dmamask, > + .coherent_dma_mask = 0xffffffff, DMA_32BIT_MASK. > + .platform_data = &au1xmmc_platdata[0], > }, > - .num_resources = ARRAY_SIZE(au1xxx_mmc_resources), > - .resource = au1xxx_mmc_resources, > + .num_resources = ARRAY_SIZE(au1200_mmc0_resources), > + .resource = au1200_mmc0_resources, > }; > + > +#ifndef CONFIG_MIPS_DB1200 > +static struct resource au1200_mmc1_resources[] = { > + [0] = { > + .start = SD1_PHYS_ADDR, > + .end = SD1_PHYS_ADDR + 0x7ffff, > + .flags = IORESOURCE_MEM, > + }, > + [1] = { > + .start = AU1200_SD_INT, > + .end = AU1200_SD_INT, > + .flags = IORESOURCE_IRQ, > + }, > + [2] = { > + .start = DSCR_CMD0_SDMS_TX1, > + .end = DSCR_CMD0_SDMS_TX1, > + .flags = IORESOURCE_DMA, > + }, > + [3] = { > + .start = DSCR_CMD0_SDMS_RX1, > + .end = DSCR_CMD0_SDMS_RX1, > + .flags = IORESOURCE_DMA, > + } > +}; > + > + > +static struct platform_device au1200_mmc1_device = { > + .name = "au1xxx-mmc", > + .id = 1, > + .dev = { > + .dma_mask = &au1xxx_mmc_dmamask, > + .coherent_dma_mask = 0xffffffff, DMA_32BIT_MASK. > + .platform_data = &au1xmmc_platdata[1], > + }, > + .num_resources = ARRAY_SIZE(au1200_mmc1_resources), > + .resource = au1200_mmc1_resources, > +}; > +#endif /* #ifndef CONFIG_MIPS_DB1200 */ > #endif /* #ifdef CONFIG_SOC_AU1200 */ > > static struct platform_device au1x00_pcmcia_device = { > @@ -295,7 +343,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { > &au1xxx_usb_gdt_device, > &au1xxx_usb_otg_device, > &au1200_lcd_device, > - &au1xxx_mmc_device, > + &au1200_mmc0_device, > +#ifndef CONFIG_MIPS_DB1200 > + &au1200_mmc1_device, > +#endif > #endif > #ifdef SMBUS_PSC_BASE > &pbdb_smbus_device, > diff --git a/arch/mips/au1000/pb1200/platform.c b/arch/mips/au1000/pb1200/platform.c > index 5930110..faf3d92 100644 > --- a/arch/mips/au1000/pb1200/platform.c > +++ b/arch/mips/au1000/pb1200/platform.c > @@ -19,9 +19,90 @@ > */ > > #include > +#include > #include > > #include > +#include > + > +static int mmc_activity = 0; Don't initialize static variables to 0. > + > +static void pb1200mmc0_set_power(void *mmc_host, int state) > +{ > + if (state) > + bcsr->board |= BCSR_BOARD_SD0PWR; > + else > + bcsr->board &= ~BCSR_BOARD_SD0PWR; > + > + au_sync_delay(1); > +} > + > +static int pb1200mmc0_card_readonly(void *mmc_host) > +{ > + return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0; > +} > + > +static int pb1200mmc0_card_inserted(void *mmc_host) > +{ > + return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0; > +} > + > +static void pb1200_mmcled_set(struct led_classdev *led, > + enum led_brightness brightness) > +{ > + if (brightness != LED_OFF) { > + if (++mmc_activity == 1) > + bcsr->disk_leds &= ~(1 << 8); > + } else { > + if (--mmc_activity == 0) > + bcsr->disk_leds |= (1 << 8); > + } > +} > + > +static struct led_classdev pb1200mmc_led = { > + .brightness_set = pb1200_mmcled_set, > +}; > + > +#ifndef CONFIG_MIPS_DB1200 > +static void pb1200mmc1_set_power(void *mmc_host, int state) > +{ > + if (state) > + bcsr->board |= BCSR_BOARD_SD1PWR; > + else > + bcsr->board &= ~BCSR_BOARD_SD1PWR; > + > + au_sync_delay(1); > +} > + > +static int pb1200mmc1_card_readonly(void *mmc_host) > +{ > + return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0; > +} > + > +static int pb1200mmc1_card_inserted(void *mmc_host) > +{ > + return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0; > +} > +#endif > + > +const struct au1xmmc_platform_data au1xmmc_platdata[2] = { > + [0] = { > + .set_power = pb1200mmc0_set_power, > + .card_inserted = pb1200mmc0_card_inserted, > + .card_readonly = pb1200mmc0_card_readonly, > + .cd_setup = NULL, /* use poll-timer in driver */ > + .led = &pb1200mmc_led, > + }, > +#ifndef CONFIG_MIPS_DB1200 > + [1] = { > + .set_power = pb1200mmc1_set_power, > + .card_inserted = pb1200mmc1_card_inserted, > + .card_readonly = pb1200mmc1_card_readonly, > + .cd_setup = NULL, /* use poll-timer in driver */ > + .led = &pb1200mmc_led, > + }, > +#endif > +}; > > static struct resource ide_resources[] = { > [0] = { > -- > 1.5.5.3 > From wangbj@lzu.edu.cn Thu Jun 12 10:43:08 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 10:43:11 +0100 (BST) Received: from mail2.lzu.edu.cn ([202.201.0.158]:25322 "HELO lzu.edu.cn") by ftp.linux-mips.org with SMTP id S28578173AbYFLJnI (ORCPT ); Thu, 12 Jun 2008 10:43:08 +0100 Received: from [192.168.2.104] (unknown [202.201.14.140]) by mail1.lzu.edu.cn (Coremail) with SMTP id AQAAf7Dr8wuX51BIDqAzAA==.4517S2; Thu, 12 Jun 2008 17:08:39 +0800 (CST) Subject: irq hande default_startup qestion From: "Wang, Baojun" Reply-To: wangbj@dslab.lzu.edu.cn To: linux-mips@linux-mips.org Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="=-EmmDG8reDwVQPiA2VVlj" Organization: DSLab, Lanzhou University Date: Thu, 12 Jun 2008 17:42:54 +0800 Message-Id: <1213263774.31495.9.camel@localhost.dslab> Mime-Version: 1.0 X-Mailer: Evolution 2.22.2 X-Coremail-Antispam: 1U3129KBjvJXoW7Gw1xAw17uFykJw1DJr4fKrg_yoW8JF1DpF 4rGwnYvFW3Xay0grWUCw40kr1ftwsxJry8Ar1rK343Zayq93yvv3Wvqrs7Ar1UGr9Fqr47 AF4SvFWIva13A3DanT9S1TB71UUUUUUv73VFW2AGmfu7bjvjm3AaLaJ3UjIYCTnIWjLIb7 Iv0xC_Jr1l5I8CrVACY4xI64kE6c02F40Ex7xfM7kC6x804xWl14x267AKxVWUJVW8JwAF xVCF77xC6IxKo4kEV4yl1I0EscIYIxCEI4klw4CSwwAFIxvE14AKwVWUJVWUGwASzI0EjI 02j7AqF2xKxwAq048E620vw7xCY7CE4x8GYI0EYx1lYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4l Yx0Ex4A2jsIE14v26r1j6r4UMx02cVAKzwCY0x0Ix7I2Y4AK64vIr41l4x8a64kEw24lx4 CE17CEb7AF67AKxVWUJVWUXjIFyTuYvjxUYmiiDUUUU Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19496 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wangbj@lzu.edu.cn Precedence: bulk X-list: linux-mips --=-EmmDG8reDwVQPiA2VVlj Content-Type: text/plain Content-Transfer-Encoding: quoted-printable hi, list: I have a question about default_startup() in kernel/irq/chip.c: /* * default startup function */ static unsigned int default_startup(unsigned int irq) { irq_desc[irq].chip->enable(irq); return 0; } By default, default_startup will call irq_chip->enable(), but some drivers like i8259A, in arch/mips/kenrel/i8259.c: static struct irq_chip i8259A_chip =3D { .name =3D "XT-PIC", .mask =3D disable_8259A_irq, .disable =3D disable_8259A_irq, .unmask =3D enable_8259A_irq, .mask_ack =3D mask_and_ack_8259A, #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF .set_affinity =3D plat_set_irq_affinity, #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ }; which don't initialize irq_chip->enable, in some (probably rare) case when irq_chip->startup() get called, it will cause NULL pointer reference. is it OK to change i8259A_chip (add .enable =3D xxx_unmask, .disable =3D xxx_mask) or just change default_startup() function? (irq_desc[irq].chip->unmask() or so?) Regards, Wang --=20 Wang, Baojun Lanzhou Univers= ity Distributed & Embedded System Lab http://dslab.lzu.edu= .cn School of Information Science and Engeneering wangbj@dslab.lzu.edu= .cn Tianshui South Road 222. Lanzhou 730000 .P.R.Ch= ina Tel: +86-931-8912025 Fax: +86-931-8912= 022 --=-EmmDG8reDwVQPiA2VVlj Content-Type: application/pgp-signature; name=signature.asc Content-Description: =?gb2312?Q?=D5=E2=CA=C7=D0=C5=BC=FE=B5=C4=CA=FD=D7=D6=C7=A9?= =?gb2312?Q?=C3=FB=B2=BF=B7=D6?= -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iEYEABECAAYFAkhQ754ACgkQIuIOr7tpgg09kwCfTgreFvQ9DSZEsDpJ5tcZK3tx X14AnRc9fzTdjAsSx5OMi7Bpm2yzB69w =CXtX -----END PGP SIGNATURE----- --=-EmmDG8reDwVQPiA2VVlj-- From sync.jma@gmail.com Thu Jun 12 10:51:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 10:51:50 +0100 (BST) Received: from wf-out-1314.google.com ([209.85.200.169]:9830 "EHLO wf-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S28578203AbYFLJvr (ORCPT ); Thu, 12 Jun 2008 10:51:47 +0100 Received: by wf-out-1314.google.com with SMTP id 28so4327568wff.21 for ; Thu, 12 Jun 2008 02:51:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:cc:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:references; bh=F6LGIQl4CuEpYvQniQv8GJhqbhAiN0X56tbvMyGVae0=; b=BnK61hr6HKyIPayHGszC/8nPm25oCOs+Q4AeGwZnUGL3LuVxfZAgAdCdC7Xy5LNgfz nlvpRQv6oFVlSQESWJ5b2DXC+xpUrPI3U+FJLpMUcolX8A5XI2o+oFI7eVI5Ay3AK0e6 GVpUcfMaxECfv5C8VzFGE+piYui0dHnHzFnrI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:cc:in-reply-to:mime-version :content-type:content-transfer-encoding:content-disposition :references; b=j1cr9Tatjtdw71sMTNy0wsT00PE5WRZZV58r9e6z8HgAaK6sv/0czwJ67u7ztSqx8b BHdlQUHNPeBqx9ZP/dGdtOPLhW9NMZu1XvPtxo59z5u2H9+U6zFKuc3Bv0WGSS4CiRAR HbxG/wm5xlI12EQFYwAt5AtI6NA3DC6YZGafU= Received: by 10.142.174.18 with SMTP id w18mr389646wfe.325.1213264304694; Thu, 12 Jun 2008 02:51:44 -0700 (PDT) Received: by 10.143.42.1 with HTTP; Thu, 12 Jun 2008 02:51:44 -0700 (PDT) Message-ID: Date: Thu, 12 Jun 2008 17:51:44 +0800 From: J.Ma To: "Markus Gothe" Subject: Re: [SPAM] linux-2.6.25.4 Porting OOPS Cc: "linux-mips@linux-mips.org" In-Reply-To: <20B109E2-594E-4329-95C7-F67E9A7882E2@27m.se> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20B109E2-594E-4329-95C7-F67E9A7882E2@27m.se> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19497 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sync.jma@gmail.com Precedence: bulk X-list: linux-mips On Mon, Jun 9, 2008 at 1:53 PM, Markus Gothe wrote: > Start with checking the memory mapping as hinted by: > ra : 8000dd10 copy_user_highpage+0x98/0x158 > //Markus Thank you for your advice, I checked this function and found that the problem might be "cpu_has_dc_aliases", After disabling MIPS_CACHE_ALIASES in probe_pcache(), the linux goes on with no oops. Could anyone here provide instructions about fusion MIPS SOC(R3K/R4K for example)? It confused me a lot. :) -- FIXME if it is wrong. From ralf@linux-mips.org Thu Jun 12 11:19:03 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 11:19:06 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:63459 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28578262AbYFLKTD (ORCPT ); Thu, 12 Jun 2008 11:19:03 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5CAIfwi011235; Thu, 12 Jun 2008 11:18:41 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5CAIdVY011227; Thu, 12 Jun 2008 11:18:39 +0100 Date: Thu, 12 Jun 2008 11:18:39 +0100 From: Ralf Baechle To: Manuel Lauss Cc: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/8] Alchemy: register mmc platform device for db1200/pb1200 boards. Message-ID: <20080612101839.GC21601@linux-mips.org> References: <20080609063521.GA8724@roarinelk.homelinux.net> <20080609063702.GC8724@roarinelk.homelinux.net> <20080612090206.GB21601@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080612090206.GB21601@linux-mips.org> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19498 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jun 12, 2008 at 10:02:06AM +0100, Ralf Baechle wrote: I cleaned the numerals for the DMA constants with below patch which now is in the 2.6.27 patch queue. Ralf From: Ralf Baechle [MIPS] Alchemy, PNX: Use symbolic constants for DMA masks. Signed-off-by: Ralf Baechle arch/mips/au1000/common/platform.c | 29 +++++++++++++++-------------- arch/mips/au1000/pb1200/platform.c | 5 +++-- arch/mips/nxp/pnx8550/common/platform.c | 9 +++++---- 3 files changed, 23 insertions(+), 20 deletions(-) Index: linux-queue/arch/mips/au1000/common/platform.c =================================================================== --- linux-queue.orig/arch/mips/au1000/common/platform.c +++ linux-queue/arch/mips/au1000/common/platform.c @@ -11,6 +11,7 @@ * warranty of any kind, whether express or implied. */ +#include #include #include #include @@ -77,14 +78,14 @@ static struct resource au1xxx_usb_ohci_r }; /* The dmamask must be set for OHCI to work */ -static u64 ohci_dmamask = ~(u32)0; +static u64 ohci_dmamask = DMA_32BIT_MASK; static struct platform_device au1xxx_usb_ohci_device = { .name = "au1xxx-ohci", .id = 0, .dev = { .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_32BIT_MASK, }, .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), .resource = au1xxx_usb_ohci_resources, @@ -106,14 +107,14 @@ static struct resource au1100_lcd_resour } }; -static u64 au1100_lcd_dmamask = ~(u32)0; +static u64 au1100_lcd_dmamask = DMA_32BIT_MASK; static struct platform_device au1100_lcd_device = { .name = "au1100-lcd", .id = 0, .dev = { .dma_mask = &au1100_lcd_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_32BIT_MASK, }, .num_resources = ARRAY_SIZE(au1100_lcd_resources), .resource = au1100_lcd_resources, @@ -135,14 +136,14 @@ static struct resource au1xxx_usb_ehci_r }, }; -static u64 ehci_dmamask = ~(u32)0; +static u64 ehci_dmamask = DMA_32BIT_MASK; static struct platform_device au1xxx_usb_ehci_device = { .name = "au1xxx-ehci", .id = 0, .dev = { .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_32BIT_MASK, }, .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources), .resource = au1xxx_usb_ehci_resources, @@ -180,14 +181,14 @@ static struct resource au1xxx_mmc_resour } }; -static u64 udc_dmamask = ~(u32)0; +static u64 udc_dmamask = DMA_32BIT_MASK; static struct platform_device au1xxx_usb_gdt_device = { .name = "au1xxx-udc", .id = 0, .dev = { .dma_mask = &udc_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_32BIT_MASK, }, .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources), .resource = au1xxx_usb_gdt_resources, @@ -207,14 +208,14 @@ static struct resource au1xxx_usb_otg_re }, }; -static u64 uoc_dmamask = ~(u32)0; +static u64 uoc_dmamask = DMA_32BIT_MASK; static struct platform_device au1xxx_usb_otg_device = { .name = "au1xxx-uoc", .id = 0, .dev = { .dma_mask = &uoc_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_32BIT_MASK, }, .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources), .resource = au1xxx_usb_otg_resources, @@ -233,27 +234,27 @@ static struct resource au1200_lcd_resour } }; -static u64 au1200_lcd_dmamask = ~(u32)0; +static u64 au1200_lcd_dmamask = DMA_32BIT_MASK; static struct platform_device au1200_lcd_device = { .name = "au1200-lcd", .id = 0, .dev = { .dma_mask = &au1200_lcd_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_32BIT_MASK, }, .num_resources = ARRAY_SIZE(au1200_lcd_resources), .resource = au1200_lcd_resources, }; -static u64 au1xxx_mmc_dmamask = ~(u32)0; +static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK; static struct platform_device au1xxx_mmc_device = { .name = "au1xxx-mmc", .id = 0, .dev = { .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_32BIT_MASK, }, .num_resources = ARRAY_SIZE(au1xxx_mmc_resources), .resource = au1xxx_mmc_resources, Index: linux-queue/arch/mips/au1000/pb1200/platform.c =================================================================== --- linux-queue.orig/arch/mips/au1000/pb1200/platform.c +++ linux-queue/arch/mips/au1000/pb1200/platform.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include @@ -36,14 +37,14 @@ static struct resource ide_resources[] = } }; -static u64 ide_dmamask = ~(u32)0; +static u64 ide_dmamask = DMA_32BIT_MASK; static struct platform_device ide_device = { .name = "au1200-ide", .id = 0, .dev = { .dma_mask = &ide_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_32BIT_MASK, }, .num_resources = ARRAY_SIZE(ide_resources), .resource = ide_resources Index: linux-queue/arch/mips/nxp/pnx8550/common/platform.c =================================================================== --- linux-queue.orig/arch/mips/nxp/pnx8550/common/platform.c +++ linux-queue/arch/mips/nxp/pnx8550/common/platform.c @@ -13,6 +13,7 @@ * warranty of any kind, whether express or implied. */ #include +#include #include #include #include @@ -91,16 +92,16 @@ struct pnx8xxx_port pnx8xxx_ports[] = { }; /* The dmamask must be set for OHCI to work */ -static u64 ohci_dmamask = ~(u32)0; +static u64 ohci_dmamask = DMA_32BIT_MASK; -static u64 uart_dmamask = ~(u32)0; +static u64 uart_dmamask = DMA_32BIT_MASK; static struct platform_device pnx8550_usb_ohci_device = { .name = "pnx8550-ohci", .id = -1, .dev = { .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_32BIT_MASK, }, .num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources), .resource = pnx8550_usb_ohci_resources, @@ -111,7 +112,7 @@ static struct platform_device pnx8550_ua .id = -1, .dev = { .dma_mask = &uart_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_32BIT_MASK, .platform_data = pnx8xxx_ports, }, .num_resources = ARRAY_SIZE(pnx8550_uart_resources), From ralf@linux-mips.org Thu Jun 12 11:22:06 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 11:22:08 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:2276 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28578255AbYFLKWG (ORCPT ); Thu, 12 Jun 2008 11:22:06 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5CALi0D012413; Thu, 12 Jun 2008 11:21:44 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5CALhc2012406; Thu, 12 Jun 2008 11:21:43 +0100 Date: Thu, 12 Jun 2008 11:21:43 +0100 From: Ralf Baechle To: Manuel Lauss Cc: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: Re: [PATCH 7/8] Alchemy: remove unused MMC macros from db1x00 header. Message-ID: <20080612102143.GD21601@linux-mips.org> References: <20080609063521.GA8724@roarinelk.homelinux.net> <20080609063958.GH8724@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080609063958.GH8724@roarinelk.homelinux.net> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19499 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 09, 2008 at 08:39:58AM +0200, Manuel Lauss wrote: > From: Manuel Lauss > Date: Mon, 9 Jun 2008 08:39:58 +0200 > To: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, > linux-kernel@vger.kernel.org > Subject: [PATCH 7/8] Alchemy: remove unused MMC macros from db1x00 header. > Content-Type: text/plain; charset=us-ascii Okay for this one. Since it's independant of the others I will put it into the 2.6.27 queue. Thanks, Ralf From ralf@linux-mips.org Thu Jun 12 12:48:29 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 12:48:32 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:31421 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28578322AbYFLLs3 (ORCPT ); Thu, 12 Jun 2008 12:48:29 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5CBm7Co022025; Thu, 12 Jun 2008 12:48:07 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5CBm3bc022000; Thu, 12 Jun 2008 12:48:03 +0100 Date: Thu, 12 Jun 2008 12:48:02 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org Subject: Re: [PATH] Better load address for big endian SNI RM Message-ID: <20080612114754.GA4097@linux-mips.org> References: <20080526231516.14BBCFA1C3@solo.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080526231516.14BBCFA1C3@solo.franken.de> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19500 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied. Thanks, Ralf From blf.ireland@gmail.com Thu Jun 12 13:03:20 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 13:03:22 +0100 (BST) Received: from fg-out-1718.google.com ([72.14.220.157]:43639 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S28578432AbYFLMDU convert rfc822-to-8bit (ORCPT ); Thu, 12 Jun 2008 13:03:20 +0100 Received: by fg-out-1718.google.com with SMTP id d23so2462965fga.32 for ; Thu, 12 Jun 2008 05:03:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:reply-to:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id:sender; bh=kccwkkXCQVK4PaEtjDzgJnZdQIc7ajthrp6s/BqtHrQ=; b=tcv1p138GORs2WtR9sOdD69BxPnhm2QopMCruKbTdYVnJ0CIPe9DjmFgr+3CDgkeo9 caUs9DzmitnAbofoNjZlp7ekhsnqjTo6EZZtc6nB1tyi6ChIVzPBVzx7dLuvjcgGkzvh W61eiz3Ql802eulCeMrW125iKG3w/kIJxRXfc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:reply-to:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id:sender; b=Sy5PrbABGJ14f9UKmtkZhiR8CWtHhmA8eqTsgSixH/O95ncmZ3T7fqDWII3r12Jt4l ili1TmVDl+LYcnz1Nvp+zM+xjfuqRNsGNH3C7mR40jkTDDXGmRnzrztqjH/aF9fPrXA7 +JIDcV3gxBD75zmSXy10xfM09W1dlcm79RfeI= Received: by 10.86.78.4 with SMTP id a4mr2111499fgb.29.1213272198525; Thu, 12 Jun 2008 05:03:18 -0700 (PDT) Received: from innova-card.com ( [81.252.61.1]) by mx.google.com with ESMTPS id 4sm2398547fge.5.2008.06.12.05.03.13 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 12 Jun 2008 05:03:16 -0700 (PDT) From: Brian Foster Reply-To: Brian Foster To: "Kevin D. Kissell" , linux-mips@linux-mips.org Subject: Re: Adding(?) XI support to MIPS-Linux? Date: Thu, 12 Jun 2008 14:03:13 +0200 User-Agent: KMail/1.9.6 (enterprise 0.20070907.709405) Cc: David Daney , Thiemo Seufer , "Kevin D. Kissell" , Andrew Dyer References: <200806091658.10937.brian.foster@innova-card.com> <200806111516.57406.brian.foster@innova-card.com> <48501E9E.1040202@mips.com> In-Reply-To: <48501E9E.1040202@mips.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200806121403.14181.brian.foster@innova-card.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19501 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips On Wednesday 11 June 2008 Kevin D. Kissell wrote: > Brian Foster wrote: > >[ ... the FPU emulation ] trampoline, which is pushed on > > the user-land stack is, unlike sigreturn, not fixed code. > > It varies on a per-instance per-thread basis. Hence the > > simple ‘vsyscall’ mechanism ((to be?) used for sigreturn) > > is inappropriate. > > > > The trampoline is only used to execute a non-FP instruction > > () in the delay slot of an FP-instruction [ ... ] > > > > Belch! ;-\ Whilst I can think of a few things that may work > > (temporarily change page permissions; or go ahead and use > > the ‘vsyscall’ page with some interlocking magic; or a new > > new dedicated per-thread page; or ...?) none seem appealing. >[ ... ] > As the jerk who originally bolted the FP emulator into the MIPS kernel > and came up with the stack trampoline hack, I can explain why it seemed > sane at the time. If an FP branch is emulated and to be taken, we have to > find a way for the instruction in the delay slot to be executed prior to the > transfer of control to the branch target. It has to execute with the user's > permissions. Putting it on the user's stack and building a trampoline was > the fairly classical way of doing it, but note that it's architecturally > illegal to put a branch in a branch delay slot (floating point or otherwise), > so there's no possibility of recursion. So one only needs 3-4 words (one > could substitute another means of validation for the cookie) per thread. Jerk, ;-) Yes, once I worked out what it was doing it all seemed cute (albeit I don't quite see what the danger is with recursion?). My “Belch!” was referring to the problems it now causes with non-executable stacks. > It just has to be part of the user's address space. I suppose > that instead of using a few words just above the stack, one could use > a few words just below the current "brk()" point, or, better still (but > far more invasive) pad the text segment, which should always be > executable, with 4 words that the kernel can find in a hurry. First, you need to really careful about multithreaded code concurrently doing FPU stuff. That is, it's possible there may be more than one “live” emulated FPU delay slot in the same address space. So stuffing the code into text, or near the brk()-point, or similar, all has concurrency issues. This is what makes the current on-the-stack approach neat; the stack _is_ per-thread so there's no concurrency mess. As for putting the trampoline near the brk()-point, besides the concurrency problem, there's also the issue that the containing page would have to be made user-executable (if temporarily). Unless I'm confused, that page is nominally data (heap-ish). With the addition of XI support, I would expect data to nominally also be non-executable. cheers! -blf- -- “How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools.” | http://www.stopesso.com From ralf@linux-mips.org Thu Jun 12 13:04:23 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 13:04:25 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:49639 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28578548AbYFLMEX (ORCPT ); Thu, 12 Jun 2008 13:04:23 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5CC421c028635; Thu, 12 Jun 2008 13:04:02 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5CC42gk028624; Thu, 12 Jun 2008 13:04:02 +0100 Date: Thu, 12 Jun 2008 13:04:02 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Add RM200 with R5000 CPU to known ARC machines Message-ID: <20080612120402.GB4097@linux-mips.org> References: <20080526231520.66C20FA1C3@solo.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080526231520.66C20FA1C3@solo.franken.de> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19502 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Applied, too. Ralf From mano@roarinelk.homelinux.net Thu Jun 12 13:18:30 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 13:18:32 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:35295 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28578378AbYFLMSa (ORCPT ); Thu, 12 Jun 2008 13:18:30 +0100 Received: (qmail 24748 invoked by uid 1000); 12 Jun 2008 14:18:28 +0200 Date: Thu, 12 Jun 2008 14:18:28 +0200 From: Manuel Lauss To: Ralf Baechle Cc: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: [PATCH 2/8] Alchemy: register mmc platform device for db1200/pb1200 boards. Message-ID: <20080612121828.GA24603@roarinelk.homelinux.net> References: <20080609063521.GA8724@roarinelk.homelinux.net> <20080609063702.GC8724@roarinelk.homelinux.net> <20080612090206.GB21601@linux-mips.org> <20080612101839.GC21601@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080612101839.GC21601@linux-mips.org> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19503 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hi Ralf, Pierre, On Thu, Jun 12, 2008 at 11:18:39AM +0100, Ralf Baechle wrote: > On Thu, Jun 12, 2008 at 10:02:06AM +0100, Ralf Baechle wrote: > > I cleaned the numerals for the DMA constants with below patch which now > is in the 2.6.27 patch queue. Here's a new version of [PATCH 2/8], against those changes. --- From: Manuel Lauss Add au1xmmc platform data for PB1200/DB1200 boards, and wire up the 2 SD controllers for them. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/platform.c | 98 +++++++++++++++++++++++++++--------- arch/mips/au1000/pb1200/platform.c | 81 +++++++++++++++++++++++++++++ 2 files changed, 155 insertions(+), 24 deletions(-) diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index d01fe5f..5c76c64 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -17,6 +17,8 @@ #include #include +#include +#include #define PORT(_base, _irq) \ { \ @@ -163,24 +165,6 @@ static struct resource au1xxx_usb_gdt_resources[] = { }, }; -static struct resource au1xxx_mmc_resources[] = { - [0] = { - .start = SD0_PHYS_ADDR, - .end = SD0_PHYS_ADDR + 0x40, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SD1_PHYS_ADDR, - .end = SD1_PHYS_ADDR + 0x40, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - } -}; - static u64 udc_dmamask = DMA_32BIT_MASK; static struct platform_device au1xxx_usb_gdt_device = { @@ -249,16 +233,79 @@ static struct platform_device au1200_lcd_device = { static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK; -static struct platform_device au1xxx_mmc_device = { +extern struct au1xmmc_platform_data au1xmmc_platdata[2]; + +static struct resource au1200_mmc0_resources[] = { + [0] = { + .start = SD0_PHYS_ADDR, + .end = SD0_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX0, + .end = DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX0, + .end = DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device au1200_mmc0_device = { .name = "au1xxx-mmc", .id = 0, .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[0], + }, + .num_resources = ARRAY_SIZE(au1200_mmc0_resources), + .resource = au1200_mmc0_resources, +}; + +#ifndef CONFIG_MIPS_DB1200 +static struct resource au1200_mmc1_resources[] = { + [0] = { + .start = SD1_PHYS_ADDR, + .end = SD1_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX1, + .end = DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, }, - .num_resources = ARRAY_SIZE(au1xxx_mmc_resources), - .resource = au1xxx_mmc_resources, + [3] = { + .start = DSCR_CMD0_SDMS_RX1, + .end = DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } }; + +static struct platform_device au1200_mmc1_device = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au1200_mmc1_resources), + .resource = au1200_mmc1_resources, +}; +#endif /* #ifndef CONFIG_MIPS_DB1200 */ #endif /* #ifdef CONFIG_SOC_AU1200 */ static struct platform_device au1x00_pcmcia_device = { @@ -296,7 +343,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xxx_usb_gdt_device, &au1xxx_usb_otg_device, &au1200_lcd_device, - &au1xxx_mmc_device, + &au1200_mmc0_device, +#ifndef CONFIG_MIPS_DB1200 + &au1200_mmc1_device, +#endif #endif #ifdef SMBUS_PSC_BASE &pbdb_smbus_device, diff --git a/arch/mips/au1000/pb1200/platform.c b/arch/mips/au1000/pb1200/platform.c index f8fb0ae..878b780 100644 --- a/arch/mips/au1000/pb1200/platform.c +++ b/arch/mips/au1000/pb1200/platform.c @@ -20,9 +20,90 @@ #include #include +#include #include #include +#include + +static int mmc_activity; + +static void pb1200mmc0_set_power(void *mmc_host, int state) +{ + if (state) + bcsr->board |= BCSR_BOARD_SD0PWR; + else + bcsr->board &= ~BCSR_BOARD_SD0PWR; + + au_sync_delay(1); +} + +static int pb1200mmc0_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0; +} + +static int pb1200mmc0_card_inserted(void *mmc_host) +{ + return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0; +} + +static void pb1200_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) { + if (++mmc_activity == 1) + bcsr->disk_leds &= ~(1 << 8); + } else { + if (--mmc_activity == 0) + bcsr->disk_leds |= (1 << 8); + } +} + +static struct led_classdev pb1200mmc_led = { + .brightness_set = pb1200_mmcled_set, +}; + +#ifndef CONFIG_MIPS_DB1200 +static void pb1200mmc1_set_power(void *mmc_host, int state) +{ + if (state) + bcsr->board |= BCSR_BOARD_SD1PWR; + else + bcsr->board &= ~BCSR_BOARD_SD1PWR; + + au_sync_delay(1); +} + +static int pb1200mmc1_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0; +} + +static int pb1200mmc1_card_inserted(void *mmc_host) +{ + return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0; +} +#endif + +const struct au1xmmc_platform_data au1xmmc_platdata[2] = { + [0] = { + .set_power = pb1200mmc0_set_power, + .card_inserted = pb1200mmc0_card_inserted, + .card_readonly = pb1200mmc0_card_readonly, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &pb1200mmc_led, + }, +#ifndef CONFIG_MIPS_DB1200 + [1] = { + .set_power = pb1200mmc1_set_power, + .card_inserted = pb1200mmc1_card_inserted, + .card_readonly = pb1200mmc1_card_readonly, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &pb1200mmc_led, + }, +#endif +}; static struct resource ide_resources[] = { [0] = { -- 1.5.5.3 From ralf@linux-mips.org Thu Jun 12 13:27:11 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 13:27:13 +0100 (BST) Received: from vigor.karmaclothing.net ([217.169.26.28]:46761 "EHLO vigor.karmaclothing.net") by ftp.linux-mips.org with ESMTP id S28578417AbYFLM1L (ORCPT ); Thu, 12 Jun 2008 13:27:11 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by vigor.karmaclothing.net (8.14.1/8.14.1) with ESMTP id m5CCQmle017976; Thu, 12 Jun 2008 13:26:49 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m5CCQkmL017897; Thu, 12 Jun 2008 13:26:46 +0100 Date: Thu, 12 Jun 2008 13:26:46 +0100 From: Ralf Baechle To: Manuel Lauss Cc: linux-mips@linux-mips.org, sshtylyov@ru.mvista.com, drzeus@drzeus.cx, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/8] Alchemy: register mmc platform device for db1200/pb1200 boards. Message-ID: <20080612122646.GA9493@linux-mips.org> References: <20080609063521.GA8724@roarinelk.homelinux.net> <20080609063702.GC8724@roarinelk.homelinux.net> <20080612090206.GB21601@linux-mips.org> <20080612101839.GC21601@linux-mips.org> <20080612121828.GA24603@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080612121828.GA24603@roarinelk.homelinux.net> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19504 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jun 12, 2008 at 02:18:28PM +0200, Manuel Lauss wrote: > Hi Ralf, Pierre, > > On Thu, Jun 12, 2008 at 11:18:39AM +0100, Ralf Baechle wrote: > > On Thu, Jun 12, 2008 at 10:02:06AM +0100, Ralf Baechle wrote: > > > > I cleaned the numerals for the DMA constants with below patch which now > > is in the 2.6.27 patch queue. > > Here's a new version of [PATCH 2/8], against those changes. Thanks, looking good, thus: Acked-by: Ralf Baechl Pierre, feel free to merge these MIPS bits into your tree. The whole series should probably go upstream together. Ralf From daniel.j.laird@googlemail.com Thu Jun 12 13:29:50 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Jun 2008 13:29:55 +0100 (BST) Received: from wr-out-0506.google.com ([64.233.184.230]:51950 "EHLO wr-out-0506.google.com") by ftp.linux-mips.org with ESMTP id S28578597AbYFLM3u (ORCPT ); Thu, 12 Jun 2008 13:29:50 +0100 Received: by wr-out-0506.google.com with SMTP id 58so2061100wri.8 for ; Thu, 12 Jun 2008 05:29:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:sender :to:subject:cc:mime-version:content-type:x-google-sender-auth; bh=d7O6ltFeaaP4nH4abOzuVDwctAWvlftPoZCbd9c0fgw=; b=M31x4X8EmbgnIzgq6bVOS1j3ehUxV9qJa5Gjn7AdkZxQRljjudVkyidmJvRk8+N/oB OSXihVGuiswcavpjo+79RHHNo2jmUL4zLjL6BWOrxzxQEImg/8tktyK5HyRrpI5B5m7s iUmB18hCPwSui2gOgGDVXv5gSefZ473KMRmzw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=message-id:date:from:sender:to:subject:cc:mime-version:content-type :x-google-sender-auth; b=aq3QqkJcEqldg7ZkIGDgiapB3ct9WQbJXSmTK3q357/KoF75DZfACuxlozj1MgEkrk d+v41g9KGEuSo+g3PWJuN6ZvuAY2pFyfya//YTZvTtwqJnaBKMhqtCxM/bNQFgdVx9zT qdaKRevoFGBiet29tCewq1xWe9eQduu8PFPrw= Received: by 10.90.31.6 with SMTP id e6mr575545age.43.1213273787424; Thu, 12 Jun 2008 05:29:47 -0700 (PDT) Received: by 10.90.70.11 with HTTP; Thu, 12 Jun 2008 05:29:47 -0700 (PDT) Message-ID: <64660ef00806120529l5c5979a0j6eb81c0dfc36fabb@mail.gmail.com> Date: Thu, 12 Jun 2008 13:29:47 +0100 From: "Daniel Laird" To: "Ralf Baechle" Subject: =?WINDOWS-1256?Q?[PATCH]_:_Add_support_for_NXP_PNX833x_?= =?WINDOWS-1256?Q?(STB222/5)_into_linux_kernel=FE_(UPDATE)?= Cc: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_40178_9324120.1213273787394" X-Google-Sender-Auth: 2576dc4542b7453c Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 19505 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: daniel.j.laird@nxp.com Precedence: bulk X-list: linux-mips ------=_Part_40178_9324120.1213273787394 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline The following patch add support for the NXP PNX833x SOC. More specifically it adds support for the STB222/5 variant. arch/mips/Kconfig | 33 arch/mips/Makefile | 8 arch/mips/configs/pnx8335-stb225_defconfig | 1150 ++++++++++++++++++++++++++++ arch/mips/nxp/pnx833x/common/Makefile | 1 arch/mips/nxp/pnx833x/common/gdb_hook.c | 134 +++ arch/mips/nxp/pnx833x/common/interrupts.c | 365 ++++++++ arch/mips/nxp/pnx833x/common/platform.c | 306 +++++++ arch/mips/nxp/pnx833x/common/prom.c | 70 + arch/mips/nxp/pnx833x/common/reset.c | 45 + arch/mips/nxp/pnx833x/common/setup.c | 64 + arch/mips/nxp/pnx833x/stb22x/Makefile | 1 arch/mips/nxp/pnx833x/stb22x/board.c | 133 +++ include/asm-mips/mach-pnx833x/gpio.h | 172 ++++ include/asm-mips/mach-pnx833x/irq-mapping.h | 126 +++ include/asm-mips/mach-pnx833x/irq.h | 53 + include/asm-mips/mach-pnx833x/pnx833x.h | 202 ++++ include/asm-mips/mach-pnx833x/war.h | 25 17 files changed, 2888 insertions(+) Signed-off-by: daniel.j.laird diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/configs/pnx8335-stb225_defconfig linux-2.6.26-rc4/arch/mips/configs/pnx8335-stb225_defconfig --- linux-2.6.26-rc4.orig/arch/mips/configs/pnx8335-stb225_defconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/configs/pnx8335-stb225_defconfig 2008-06-04 15:58:03.000000000 +0100 @@ -0,0 +1,1150 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc4 +# Wed Jun 4 15:57:17 2008 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +CONFIG_NXP_STB225=y +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_WR_PPMC is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SOC_PNX833X=y +CONFIG_SOC_PNX8335=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_128=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=128 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +CONFIG_INET_AH=y +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x18000000 +CONFIG_MTD_PHYSMAP_LEN=0x04000000 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +CONFIG_ATA_SFF=y +# CONFIG_SATA_MV is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_IP3902 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_ALGOPCA=y + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_PCA_PLATFORM is not set +CONFIG_I2C_PNX0105=y + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +CONFIG_DVB_CORE=y +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_L64781 is not set +CONFIG_DVB_TDA1004X=y +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_TDA10048 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522 is not set +# CONFIG_DVB_S5H1411 is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_LOGO is not set + +# +# Sound +# +CONFIG_SOUND=m + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_DETECT=y +# CONFIG_SND_PCM_XRUN_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# ALSA MIPS devices +# + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# ALSA SoC audio for Freescale SOCs +# + +# +# SoC Audio for the Texas Instruments OMAP +# + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_CODEPAGE_932=m +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=m +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SAMPLES is not set +CONFIG_CMDLINE="" +CONFIG_SYS_SUPPORTS_KGDB=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/Kconfig linux-2.6.26-rc4/arch/mips/Kconfig --- linux-2.6.26-rc4.orig/arch/mips/Kconfig 2008-06-03 10:56:51.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/Kconfig 2008-06-03 17:12:19.000000000 +0100 @@ -311,6 +311,19 @@ select SYS_HAS_CPU_VR41XX select GENERIC_HARDIRQS_NO__DO_IRQ +config NXP_STB220 + bool "NXP STB220 board" + select SOC_PNX833X + help + Support for NXP Semiconductors STB220 Development Board. + +config NXP_STB225 + bool "NXP 225 board" + select SOC_PNX833X + select SOC_PNX8335 + help + Support for NXP Semiconductors STB225 Development Board. + config PNX8550_JBS bool "NXP PNX8550 based JBS board" select PNX8550 @@ -947,6 +960,26 @@ bool select SERIAL_RM9000 +config SOC_PNX833X + bool + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select DMA_NONCOHERENT + select SYS_HAS_EARLY_PRINTK + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ + select SYS_SUPPORTS_KGDB + select GENERIC_GPIO + select CPU_MIPSR2_IRQ_VI + +config SOC_PNX8335 + bool + select SOC_PNX833X + config PNX8550 bool select SOC_PNX8550 diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/Makefile linux-2.6.26-rc4/arch/mips/Makefile --- linux-2.6.26-rc4.orig/arch/mips/Makefile 2008-06-03 10:56:51.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/Makefile 2008-06-03 17:13:03.000000000 +0100 @@ -409,6 +409,14 @@ # load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 +# NXP STB225 +core-$(CONFIG_SOC_PNX833X) += arch/mips/nxp/pnx833x/common/ +cflags-$(CONFIG_SOC_PNX833X) += -Iinclude/asm-mips/mach-pnx833x +libs-$(CONFIG_NXP_STB220) += arch/mips/nxp/pnx833x/stb22x/ +load-$(CONFIG_NXP_STB220) += 0xffffffff80001000 +libs-$(CONFIG_NXP_STB225) += arch/mips/nxp/pnx833x/stb22x/ +load-$(CONFIG_NXP_STB225) += 0xffffffff80001000 + # # Common NXP PNX8550 # diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/gdb_hook.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/gdb_hook.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/gdb_hook.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/gdb_hook.c 2008-06-06 11:29:01.000000000 +0100 @@ -0,0 +1,134 @@ +/* + * gdb_hook.c: gdb hook for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * Based on PNX8550. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include + +#define UART0 (unsigned char *)PNX833X_UART0_PORTS_START +#define UART1 (unsigned char *)PNX833X_UART1_PORTS_START + +static unsigned char *kgdb_uart = UART1; +static unsigned char *console_uart = UART0; +static volatile int delay_count; + +static unsigned int serial_in(unsigned char *base_address, int offset) +{ + return *((unsigned int volatile *)(base_address + offset)); +} + +static void serial_out(unsigned char *base_address, int offset, int value) +{ + *((unsigned int volatile *)(base_address + offset)) = value; +} + +static void do_delay(void) +{ + int i; + for (i = 0; i < 10000; i++) + delay_count++; +} + +static int put_char(unsigned char *base_address, char c) +{ + /* Wait for TX to be ready */ + while (((serial_in(base_address, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO) >> 16) > 15) + do_delay(); + + /* Send the next character */ + serial_out(base_address, PNX8XXX_FIFO, c); + serial_out(base_address, PNX8XXX_ICLR, PNX8XXX_UART_INT_TX); + + return 1; +} + +static char get_char(unsigned char *base_address) +{ + char output; + + /* Wait for RX to be ready */ + while ((serial_in(base_address, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_RXFIFO) == 0) + do_delay(); + + /* Get the character */ + output = serial_in(base_address, PNX8XXX_FIFO) & 0xFF; + + /* Move onto the next character in the buffer */ + serial_out(base_address, PNX8XXX_LCR, serial_in(base_address, PNX8XXX_LCR) | PNX8XXX_UART_LCR_RX_NEXT); + serial_out(base_address, PNX8XXX_ICLR, PNX8XXX_UART_INT_RX); + + return output; +} + +static void serial_init(unsigned char *base_address) +{ + serial_out(base_address, PNX8XXX_LCR, PNX8XXX_UART_LCR_8BIT | PNX8XXX_UART_LCR_TX_RST | PNX8XXX_UART_LCR_RX_RST); + serial_out(base_address, PNX8XXX_MCR, PNX8XXX_UART_MCR_DTR | PNX8XXX_UART_MCR_RTS); + serial_out(base_address, PNX8XXX_BAUD, 1); /* 115200 Baud */ + serial_out(base_address, PNX8XXX_CFG, 0x00060030); + serial_out(base_address, PNX8XXX_ICLR, -1); + serial_out(base_address, PNX8XXX_IEN, 0); +} + +static void setup_serial_output(void) +{ + static bool initialised; + if (!initialised) { + serial_init(kgdb_uart); + serial_init(console_uart); + initialised = true; + } +} + +int rs_kgdb_hook(int tty_no, int speed) +{ + kgdb_uart = tty_no ? UART1 : UART0; + console_uart = tty_no ? UART0 : UART1; + + setup_serial_output(); + + return speed; +} + +int prom_putchar(char c) +{ + setup_serial_output(); + return put_char(console_uart, c); +} + +char prom_getchar(void) +{ + setup_serial_output(); + return get_char(console_uart); +} + +int put_debug_char(char c) +{ + setup_serial_output(); + return put_char(kgdb_uart, c); +} + +char get_debug_char(void) +{ + setup_serial_output(); + return get_char(kgdb_uart); +} diff -urN --exclude=.svn linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/interrupts.c linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/interrupts.c --- linux-2.6.26-rc4.orig/arch/mips/nxp/pnx833x/common/interrupts.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.26-rc4/arch/mips/nxp/pnx833x/common/interrupts.c 2008-06-12 12:56:11.000000000 +0100 @@ -0,0 +1,365 @@ +/* + * interrupts.c: Interrupt mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel + * Daniel Laird + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] = +{ + 0, /* unused */ + 4, /* PNX833X_PIC_I2C0_INT 1 */ + 4, /* PNX833X_PIC_I2C1_INT 2 */ + 1, /* PNX833X_PIC_UART0_INT 3 */ + 1, /* PNX833X_PIC_UART1_INT 4 */ + 6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */ + 6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */ + 7, /* PNX833X_PIC_GPIO_INT 7 */ + 4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */ + 5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */ + 4, /* PNX833X_PIC_CONFIG_INT 10 */ + 4, /* PNX833X_PIC_AOI_INT 11 */ + 9, /* PNX833X_PIC_SYNC_INT 12 */ + 9, /* PNX8335_PIC_SATA_INT 13 */ + 4, /* PNX833X_PIC_OSD_INT 14 */ + 9, /* PNX833X_PIC_DISP1_INT 15 */ + 4, /* PNX833X_PIC_DEINTERLACER_INT 16 */ + 9, /* PNX833X_PIC_DISPLAY2_INT 17 */ + 4, /* PNX833X_PIC_VC_INT 18 */ + 4, /* PNX833X_PIC_SC_INT 19 */ + 9, /* PNX833X_PIC_IDE_INT 20 */ + 9, /* PNX833X_PIC_IDE_DMA_INT 21 */ + 6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */ + 6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */ + 4, /* PNX833X_PIC_SGDX_DMA_INT 24 */ + 4, /* PNX833X_PIC_TS_OUT_INT 25 */ + 4, /* PNX833X_PIC_IR_INT 26 */ + 3, /* PNX833X_PIC_VMSP1_INT 27 */ + 3, /* PNX833X_PIC_VMSP2_INT 28 */ + 4, /* PNX833X_PIC_PIBC_INT 29 */ + 4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */ + 4, /* PNX833X_PIC_SGDX_TPD_INT 31 */ + 5, /* PNX833X_PIC_USB_INT 32 */ + 4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */ + 4, /* PNX833X_PIC_CLOCK_INT 34 */ + 4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */ + 4, /* PNX833X_PIC_VMSP_DMA_INT 36 */ +#if defined(CONFIG_SOC_PNX8335) + 4, /* PNX8335_PIC_MIU_INT 37 */ + 4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */ + 9, /* PNX8335_PIC_SYNC_HD_INT 39 */ + 9, /* PNX8335_PIC_DISP_HD_INT 40 */ + 9, /* PNX8335_PIC_DISP_SCALER_INT 41 */ + 4, /* PNX8335_PIC_OSD_HD1_INT 42 */ + 4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */ + 4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */ + 4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */ + 4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */ + 4, /* PNX8335_PIC_DENC_TTX_INT 47 */ + 4, /* PNX8335_PIC_MMI_SIF0_INT 48 */ + 4, /* PNX8335_PIC_MMI_SIF1_INT 49 */ + 4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */ + 4, /* PNX8335_PIC_PIBCS_INT 51 */ + 12, /* PNX8335_PIC_ETHERNET_INT 52 */ + 3, /* PNX8335_PIC_VMSP1_0_INT 53 */ + 3, /* PNX8335_PIC_VMSP1_1_INT 54 */ + 4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */ + 4, /* PNX8335_PIC_TDGR_DE_INT 56 */ + 4, /* PNX8335_PIC_IR1_IRQ_INT 57 */ +#endif +}; + +static void pic_dispatch(void) +{ + unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC); + + if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) { + unsigned long priority = PNX833X_PIC_INT_PRIORITY; + PNX833X_PIC_INT_PRIORITY = irq_prio[irq]; + + if (irq == PNX833X_PIC_GPIO_INT) { + unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE; + int pin; + while ((pin = ffs(mask & 0xffff))) { + pin -= 1; + do_IRQ(PNX833X_GPIO_IRQ_BASE + pin); + mask &= ~(1 << pin); + } + } else { + do_IRQ(irq + PNX833X_PIC_IRQ_BASE); + } + + PNX833X_PIC_INT_PRIORITY = priority; + } else { + printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq); + } +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & STATUSF_IP4) + pic_dispatch(); + else if (pending & STATUSF_IP7) + do_IRQ(PNX833X_TIMER_IRQ); + else + spurious_interrupt(); +} + +static inline void pnx833x_hard_enable_pic_irq(unsigned int irq) +{ + /* Currently we do this by setting IRQ priority to 1. + If priority support is being implemented, 1 should be repalced + by a better value. */ + PNX833X_PIC_INT_REG(irq) = irq_prio[irq]; +} + +static inline void pnx833x_hard_disable_pic_irq(unsigned int irq) +{ + /* Disable IRQ by writing setting it's priority to 0 */ + PNX833X_PIC_INT_REG(irq) = 0; +} + +static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */ +#define IRQFLAG_STARTED 1 +#define IRQFLAG_DISABLED 2 + +static DEFINE_SPINLOCK(pnx833x_irq_lock); + +static unsigned int pnx833x_startup_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */ + pnx833x_hard_enable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); + return 0; +} + +static void pnx833x_shutdown_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] = 0; /* not started */ + pnx833x_hard_disable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); +} + +static void pnx833x_enable_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] &= ~IRQFLAG_DISABLED; + if (irqflags[pic_irq] == IRQFLAG_STARTED) + pnx833x_hard_enable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); +} + +static void pnx833x_disable_pic_irq(unsigned int irq) +{ + unsigned long flags; + unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; + + spin_lock_irqsave(&pnx833x_irq_lock, flags); + + irqflags[pic_irq] |= IRQFLAG_DISABLED; + pnx833x_hard_disable_pic_irq(pic_irq); + + spin_unlock_irqrestore(&pnx833x_irq_lock, flags); +} + +static void pnx833x_ack_pic_irq(unsigned int irq) +{ +} + +static void pnx833x_end_pic_irq(unsigned int irq) +{ +} + +static DEFINE_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock); + +static unsigned int pnx833x_startup_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); + pnx833x_gpio_enable_irq(pin); + spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); + return 0; +} + +static void pnx833x_enable_gpio_irq(unsigned int irq) +{ + int pin = irq - PNX833X_GPIO_IRQ_BASE; + unsigned long flags; + spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); + pnx833x_gpio_enable_irq(pin); + spin_unloc