From ralf@linux-mips.org Sat Mar 1 00:02:50 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Mar 2008 00:02:52 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:11976 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S28596315AbYCAACu (ORCPT ); Sat, 1 Mar 2008 00:02:50 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.14.1/8.13.8) with ESMTP id m2102mfN028235; Sat, 1 Mar 2008 00:02:49 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m2102l4U028233; Sat, 1 Mar 2008 00:02:47 GMT Date: Sat, 1 Mar 2008 00:02:47 +0000 From: Ralf Baechle To: Thiemo Seufer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Fix typo in comment Message-ID: <20080301000247.GA28191@linux-mips.org> References: <20080229004347.GA18731@networkno.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080229004347.GA18731@networkno.de> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18327 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Feb 29, 2008 at 12:43:47AM +0000, Thiemo Seufer wrote: Applied. Thanks, Ralf From ths@networkno.de Mon Mar 3 12:52:34 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Mar 2008 12:52:37 +0000 (GMT) Received: from relay01.mx.bawue.net ([193.7.176.67]:45245 "EHLO relay01.mx.bawue.net") by ftp.linux-mips.org with ESMTP id S28601036AbYCCMwe (ORCPT ); Mon, 3 Mar 2008 12:52:34 +0000 Received: from lagash (intrt.mips-uk.com [194.74.144.130]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by relay01.mx.bawue.net (Postfix) with ESMTP id EC22348918; Mon, 3 Mar 2008 13:52:28 +0100 (CET) Received: from ths by lagash with local (Exim 4.69) (envelope-from ) id 1JWA9c-0006dX-4M; Mon, 03 Mar 2008 12:52:28 +0000 Date: Mon, 3 Mar 2008 12:52:28 +0000 From: Thiemo Seufer To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] Fix PIO IDE on Broadcom SWARM Message-ID: <20080303125228.GD25396@networkno.de> References: <20080229013017.GB18731@networkno.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080229013017.GB18731@networkno.de> User-Agent: Mutt/1.5.17+20080114 (2008-01-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18328 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips This patch marks pages tainted by PIO IDE as dirty, instead of trying to flush them right away. This a) fixes PIO IDE for systems without dcache aliases (which lacked the necessary cache flush so far) b) improves performance a bit, since some pages may never need a cache flush c) obsoletes local_flush_data_cache_page Signed-off-by: Thiemo Seufer --- Changed to avoid some compiler warnings. Index: linux.git/include/asm-mips/mach-generic/ide.h =================================================================== --- linux.git.orig/include/asm-mips/mach-generic/ide.h 2008-03-02 20:15:24.000000000 +0000 +++ linux.git/include/asm-mips/mach-generic/ide.h 2008-03-02 21:52:46.000000000 +0000 @@ -107,107 +107,66 @@ #endif /* MIPS port and memory-mapped I/O string operations. */ -static inline void __ide_flush_prologue(void) +static inline void __ide_set_pages_dirty(const void *addr, unsigned long size) { -#ifdef CONFIG_SMP - if (cpu_has_dc_aliases) - preempt_disable(); -#endif -} + unsigned long end = (unsigned long)addr + size; -static inline void __ide_flush_epilogue(void) -{ -#ifdef CONFIG_SMP - if (cpu_has_dc_aliases) - preempt_enable(); -#endif -} - -static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) -{ - if (cpu_has_dc_aliases) { - unsigned long end = addr + size; - - while (addr < end) { - local_flush_data_cache_page((void *)addr); - addr += PAGE_SIZE; - } + while ((unsigned long)addr < end) { + SetPageDcacheDirty(virt_to_page(addr)); + addr += PAGE_SIZE; } } -/* - * insw() and gang might be called with interrupts disabled, so we can't - * send IPIs for flushing due to the potencial of deadlocks, see the comment - * above smp_call_function() in arch/mips/kernel/smp.c. We work around the - * problem by disabling preemption so we know we actually perform the flush - * on the processor that actually has the lines to be flushed which hopefully - * is even better for performance anyway. - */ static inline void __ide_insw(unsigned long port, void *addr, unsigned int count) { - __ide_flush_prologue(); insw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); + __ide_set_pages_dirty(addr, count * 2); } -static inline void __ide_insl(unsigned long port, void *addr, unsigned int count) +static inline void __ide_insl(unsigned long port, void *addr, + unsigned int count) { - __ide_flush_prologue(); insl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); + __ide_set_pages_dirty(addr, count * 4); } static inline void __ide_outsw(unsigned long port, const void *addr, unsigned long count) { - __ide_flush_prologue(); outsw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); + __ide_set_pages_dirty(addr, count * 2); } static inline void __ide_outsl(unsigned long port, const void *addr, unsigned long count) { - __ide_flush_prologue(); outsl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); + __ide_set_pages_dirty(addr, count * 4); } static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count) { - __ide_flush_prologue(); readsw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); + __ide_set_pages_dirty(addr, count * 2); } static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count) { - __ide_flush_prologue(); readsl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); + __ide_set_pages_dirty(addr, count * 4); } static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count) { - __ide_flush_prologue(); writesw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); + __ide_set_pages_dirty(addr, count * 2); } static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count) { - __ide_flush_prologue(); writesl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); + __ide_set_pages_dirty(addr, count * 4); } /* ide_insw calls insw, not __ide_insw. Why? */ Index: linux.git/arch/mips/mm/c-r3k.c =================================================================== --- linux.git.orig/arch/mips/mm/c-r3k.c 2008-03-02 20:15:24.000000000 +0000 +++ linux.git/arch/mips/mm/c-r3k.c 2008-03-02 21:42:33.000000000 +0000 @@ -266,10 +266,6 @@ r3k_flush_icache_range(kaddr, kaddr + PAGE_SIZE); } -static void local_r3k_flush_data_cache_page(void *addr) -{ -} - static void r3k_flush_data_cache_page(unsigned long addr) { } @@ -322,7 +318,6 @@ flush_icache_range = r3k_flush_icache_range; flush_cache_sigtramp = r3k_flush_cache_sigtramp; - local_flush_data_cache_page = local_r3k_flush_data_cache_page; flush_data_cache_page = r3k_flush_data_cache_page; _dma_cache_wback_inv = r3k_dma_cache_wback_inv; Index: linux.git/arch/mips/mm/c-r4k.c =================================================================== --- linux.git.orig/arch/mips/mm/c-r4k.c 2008-03-02 21:33:29.000000000 +0000 +++ linux.git/arch/mips/mm/c-r4k.c 2008-03-02 21:42:33.000000000 +0000 @@ -1296,7 +1296,6 @@ flush_cache_sigtramp = r4k_flush_cache_sigtramp; flush_icache_all = r4k_flush_icache_all; - local_flush_data_cache_page = local_r4k_flush_data_cache_page; flush_data_cache_page = r4k_flush_data_cache_page; flush_icache_range = r4k_flush_icache_range; Index: linux.git/arch/mips/mm/c-tx39.c =================================================================== --- linux.git.orig/arch/mips/mm/c-tx39.c 2008-03-02 20:15:24.000000000 +0000 +++ linux.git/arch/mips/mm/c-tx39.c 2008-03-02 21:42:33.000000000 +0000 @@ -210,11 +210,6 @@ tx39_blast_icache_page_indexed(page); } -static void local_tx39_flush_data_cache_page(void * addr) -{ - tx39_blast_dcache_page((unsigned long)addr); -} - static void tx39_flush_data_cache_page(unsigned long addr) { tx39_blast_dcache_page(addr); @@ -352,7 +347,6 @@ flush_icache_range = (void *) tx39h_flush_icache_all; flush_cache_sigtramp = (void *) tx39h_flush_icache_all; - local_flush_data_cache_page = (void *) tx39h_flush_icache_all; flush_data_cache_page = (void *) tx39h_flush_icache_all; _dma_cache_wback_inv = tx39h_dma_cache_wback_inv; @@ -377,7 +371,6 @@ flush_icache_range = tx39_flush_icache_range; flush_cache_sigtramp = tx39_flush_cache_sigtramp; - local_flush_data_cache_page = local_tx39_flush_data_cache_page; flush_data_cache_page = tx39_flush_data_cache_page; _dma_cache_wback_inv = tx39_dma_cache_wback_inv; Index: linux.git/arch/mips/mm/cache.c =================================================================== --- linux.git.orig/arch/mips/mm/cache.c 2008-03-02 20:15:24.000000000 +0000 +++ linux.git/arch/mips/mm/cache.c 2008-03-02 21:42:33.000000000 +0000 @@ -32,11 +32,9 @@ /* MIPS specific cache operations */ void (*flush_cache_sigtramp)(unsigned long addr); -void (*local_flush_data_cache_page)(void * addr); void (*flush_data_cache_page)(unsigned long addr); void (*flush_icache_all)(void); -EXPORT_SYMBOL_GPL(local_flush_data_cache_page); EXPORT_SYMBOL(flush_data_cache_page); #ifdef CONFIG_DMA_NONCOHERENT Index: linux.git/include/asm-mips/cacheflush.h =================================================================== --- linux.git.orig/include/asm-mips/cacheflush.h 2008-03-02 20:15:24.000000000 +0000 +++ linux.git/include/asm-mips/cacheflush.h 2008-03-02 21:42:33.000000000 +0000 @@ -76,7 +76,6 @@ extern void (*flush_cache_sigtramp)(unsigned long addr); extern void (*flush_icache_all)(void); -extern void (*local_flush_data_cache_page)(void * addr); extern void (*flush_data_cache_page)(unsigned long addr); /* From jamesz@modsystems.com Tue Mar 4 00:14:11 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Mar 2008 00:14:13 +0000 (GMT) Received: from dotcorporate.com ([67.50.105.12]:54975 "EHLO dotexchange.dotcorporation.com") by ftp.linux-mips.org with ESMTP id S28601221AbYCDAOL (ORCPT ); Tue, 4 Mar 2008 00:14:11 +0000 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C87D8C.AABEC29A" Subject: Re: smp8634 add memory at dram1 Date: Mon, 3 Mar 2008 16:14:09 -0800 Message-ID: <2D30722FBBDE6749973243F4F01BE984A242CA@dotexchange.dotcorporation.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Re: smp8634 add memory at dram1 Thread-Index: Ach9jKrAm1qYdsZ0S3224VXIW+0Tqg== From: "James Zipperer" To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18329 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jamesz@modsystems.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. ------_=_NextPart_001_01C87D8C.AABEC29A Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable =20 David Kuk" > wrote: > Dear YH >=20 > I am sorry i have been disturbed by other issues, the memory problem seems little bit difficult > to me. In our case, i saw that in prom.c under mips/tango2, the function prom_init , it shows > that : > memcfg_t > *m=3D(memcfg_t*)KSEG1ADDR(MEM_BASE_dram_controller_0+FM_MEMCFG);=20 > it's seems the kernel has hard coded to point the starting memory to DRAM controller 0's > starting address, if now, i have remap 64mb memory at DRAM controller 1 at remap register > 4, The problem is come, the kernel will ignore any memory before dram controller 0's starting > address. Even i have add 0x0c000000--0x10000000 as boot memory, it still think it's first > usable pfn is at 0x10000000.=20 >=20 > my solution is 3 steps >=20 > 1, modify the compiler, let the linux start address moved to 0x0c000000,=20 > 2. modify the YAMON, and map the DRAM 1 controller to remap register4 in YAMON stage > 3, modify the linux, to set the two piece of memory to the kernel as boot memory .=20 >=20 > it's this possible, or it have other better solution ? >=20 > thx a lot for your kindly help ! >=20 >=20 > best wishes > David =20 I'm running out of memory in linux on the smp86xx and attempting to implement this solution. Did you ever get it to work? No luck for me yet. I'm still a bit unclear why you must switch linux to run off DRAM 1 instead of leaving it on DRAM 0 and adding an additional call to add_memory_region in prom_init for DRAM 1. But then again, I haven't gotten that to work yet either :) =20 Any info/patches are greatly appreciated. Thanks! =20 -James =20 ------_=_NextPart_001_01C87D8C.AABEC29A Content-Type: text/html; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable

 

David Kuk" <david.kuk@entone.com> = wrote:

> Dear YH
>

> I am sorry i have been = disturbed by other issues, the memory problem seems little bit = difficult

> to me. In our case, i saw that in prom.c under mips/tango2, the = function prom_init , it shows

> that = :

> memcfg_t

> *m=3D(memcfg_t*)KSEG1ADDR(MEM_BASE_dram_controller_0+FM_M= EMCFG);

> it's seems the kernel has hard = coded to point the starting memory to DRAM controller = 0's

> starting address, if now, i = have remap 64mb memory at DRAM controller 1 at remap = register

> 4, The problem is come, the = kernel will ignore any memory before dram controller 0's = starting

> address. Even i have add 0x0c000000--0x10000000 as boot memory, it still think it's = first

> usable pfn is at 0x10000000.
>

> my solution is 3 steps
>

> 1, modify the compiler, let the linux start address moved to 0x0c000000,

> 2. modify the YAMON, and map the = DRAM 1 controller to remap register4 in YAMON = stage

> 3, modify the linux, to set the = two piece of memory to the kernel as boot memory = .

>

> it's this possible, or it have = other better solution ?
>

> thx a lot for your kindly help = !

>

>

> best = wishes

> David

 

I'm running out of memory in = linux on the smp86xx and attempting to implement = this solution.  Did you ever get = it to work?  No luck for me = yet.  I'm still a bit unclear why you = must switch linux to run off DRAM 1 instead of = leaving it on DRAM 0 and adding an additional call to add_memory_region in prom_init for DRAM 1.  But then again, I haven't = gotten that to work yet either :)

 

Any info/patches are greatly = appreciated.  = Thanks!

 

-James

 

=00 ------_=_NextPart_001_01C87D8C.AABEC29A-- From ddaney@avtrex.com Tue Mar 4 00:27:12 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Mar 2008 00:27:14 +0000 (GMT) Received: from smtp1.dnsmadeeasy.com ([205.234.170.144]:23186 "EHLO smtp1.dnsmadeeasy.com") by ftp.linux-mips.org with ESMTP id S28601225AbYCDA1M (ORCPT ); Tue, 4 Mar 2008 00:27:12 +0000 Received: from smtp1.dnsmadeeasy.com (localhost [127.0.0.1]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP id B6D4031569E; Tue, 4 Mar 2008 00:27:17 +0000 (UTC) X-Authenticated-Name: js.dnsmadeeasy X-Transit-System: In case of SPAM please contact abuse@dnsmadeeasy.com Received: from avtrex.com (unknown [67.116.42.147]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP; Tue, 4 Mar 2008 00:27:17 +0000 (UTC) Received: from dl2.hq2.avtrex.com ([192.168.7.26]) by avtrex.com with Microsoft SMTPSVC(6.0.3790.1830); Mon, 3 Mar 2008 16:26:57 -0800 Message-ID: <47CC974F.3090306@avtrex.com> Date: Mon, 03 Mar 2008 16:26:55 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.12 (X11/20080226) MIME-Version: 1.0 To: James Zipperer Cc: linux-mips@linux-mips.org Subject: Re: smp8634 add memory at dram1 References: <2D30722FBBDE6749973243F4F01BE984A242CA@dotexchange.dotcorporation.com> In-Reply-To: <2D30722FBBDE6749973243F4F01BE984A242CA@dotexchange.dotcorporation.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 04 Mar 2008 00:26:57.0316 (UTC) FILETIME=[747BD640:01C87D8E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18330 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@avtrex.com Precedence: bulk X-list: linux-mips James Zipperer wrote: > > > > I'm running out of memory in linux on the smp86xx and attempting to > implement this solution. Did you ever get it to work? No luck for me > yet. I'm still a bit unclear why you must switch linux to run off DRAM > 1 instead of leaving it on DRAM 0 and adding an additional call to > add_memory_region in prom_init for DRAM 1. But then again, I haven't > gotten that to work yet either :) > > > > Any info/patches are greatly appreciated. Thanks! > > > Typically DRAM 1 must be accessed through the TLB as its address lays outside of the 512MB window of KSEG[012]. The best way to make this memory available to Linux may still be up for debate. David Daney From jamesz@modsystems.com Tue Mar 4 01:59:13 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Mar 2008 01:59:15 +0000 (GMT) Received: from dotcorporate.com ([67.50.105.12]:30663 "EHLO dotexchange.dotcorporation.com") by ftp.linux-mips.org with ESMTP id S28601238AbYCDB7N convert rfc822-to-8bit (ORCPT ); Tue, 4 Mar 2008 01:59:13 +0000 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 8BIT Subject: RE: smp8634 add memory at dram1 Date: Mon, 3 Mar 2008 17:59:11 -0800 Message-ID: <2D30722FBBDE6749973243F4F01BE984A242CB@dotexchange.dotcorporation.com> In-Reply-To: <47CC974F.3090306@avtrex.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: smp8634 add memory at dram1 Thread-Index: Ach9jncajtrbM7+KS8auCZEQx2hQEQABxn5w From: "James Zipperer" To: "David Daney" Cc: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18331 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jamesz@modsystems.com Precedence: bulk X-list: linux-mips > James Zipperer wrote: > >> >> >> >> I'm running out of memory in linux on the smp86xx and attempting to >> implement this solution. Did you ever get it to work? No luck for me >> yet. I'm still a bit unclear why you must switch linux to run off DRAM >> 1 instead of leaving it on DRAM 0 and adding an additional call to >> add_memory_region in prom_init for DRAM 1. But then again, I haven't >> gotten that to work yet either :) >> >> >> >> Any info/patches are greatly appreciated. Thanks! >> >> >> > >Typically DRAM 1 must be accessed through the TLB as its address lays >outside of the 512MB window of KSEG[012]. > >The best way to make this memory available to Linux may still be up for >debate. > >David Daney I'm sure this is a dumb question due to the fact that my grasp of the problem is less than acceptable... Can remapped addresses (namely CPU_remap[34]_addr) be used for the call to add_memory_region()? That would allow the address for DRAM 1 to be within the 512MB window of KSEG[012]. I'm unclear whether the CPU_remap addresses count as PHSYICAL or VIRTUAL addresses. I'm guessing that my plan won't work since I tried it and it didn't work. My results were that the kernel booted but didn't report any additional memory available via the 'free' command. Thanks. -James From ralf@linux-mips.org Tue Mar 4 09:02:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Mar 2008 09:02:27 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:63721 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S28601299AbYCDJCZ (ORCPT ); Tue, 4 Mar 2008 09:02:25 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.14.1/8.13.8) with ESMTP id m2492LSJ030433; Tue, 4 Mar 2008 09:02:22 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.14.1/8.14.1/Submit) id m2492KDF030432; Tue, 4 Mar 2008 09:02:20 GMT Date: Tue, 4 Mar 2008 09:02:20 +0000 From: Ralf Baechle To: Andrew Morton Cc: linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: drivers/net/wireless/b43legacy/ on mips Message-ID: <20080304090220.GA2875@linux-mips.org> References: <20080303233651.82c592a4.akpm@linux-foundation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080303233651.82c592a4.akpm@linux-foundation.org> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18332 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Mar 03, 2008 at 11:36:51PM -0800, Andrew Morton wrote: > ERROR: "__ucmpdi2" [drivers/net/wireless/b43legacy/b43legacy.ko] undefined! > ERROR: "__ucmpdi2" [drivers/net/wireless/b43/b43.ko] undefined! > > int b43legacy_dma_init(struct b43legacy_wldev *dev) > { > struct b43legacy_dma *dma = &dev->dma; > struct b43legacy_dmaring *ring; > int err; > u64 dmamask; > enum b43legacy_dmatype type; > > dmamask = supported_dma_mask(dev); > switch (dmamask) { > default: > B43legacy_WARN_ON(1); > case DMA_30BIT_MASK: > type = B43legacy_DMA_30BIT; > break; > case DMA_32BIT_MASK: > type = B43legacy_DMA_32BIT; > break; > case DMA_64BIT_MASK: > type = B43legacy_DMA_64BIT; > break; > } > > because some versions of gcc emit a __ucmpdi2 call for switch statements. Was this when optimizing for size btw? It seems gcc is emitting alot more calls to libgcc when optimizing for size. > It might be fixable by switching to an open-coded if/compare/else sequence. It was just a EXPORT_SYMBOL(__ucmpdi2) missing. > Or maybe my mips compiler (gcc-3.4.5) is just too old.. I'm trying to keep the tools requirements the same as for x86. So for 32-bit kernels gcc 3.2 is the minimum but 3.2 is broken beyond recovery for 64-bit code so there a minimum of 3.3 is required. In practive it is ages that I've last seen a compiler older than gcc 3.4 being used to build a modern kernel for any architecture and 3.2 and 3.3 are a sufficient special case that maybe we should think about deprecating 3.2 and 3.3? Ralf From akpm@linux-foundation.org Tue Mar 4 09:19:40 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Mar 2008 09:19:42 +0000 (GMT) Received: from smtp1.linux-foundation.org ([140.211.169.13]:39100 "EHLO smtp1.linux-foundation.org") by ftp.linux-mips.org with ESMTP id S28588208AbYCDJTk (ORCPT ); Tue, 4 Mar 2008 09:19:40 +0000 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.14.2/Debian-2build1) with ESMTP id m249JHFf018416 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 4 Mar 2008 01:19:18 -0800 Received: from box (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id m249J52w000967; Tue, 4 Mar 2008 01:19:06 -0800 Date: Tue, 4 Mar 2008 01:19:05 -0800 From: Andrew Morton To: Ralf Baechle Cc: linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: drivers/net/wireless/b43legacy/ on mips Message-Id: <20080304011905.22e6e6d9.akpm@linux-foundation.org> In-Reply-To: <20080304090220.GA2875@linux-mips.org> References: <20080303233651.82c592a4.akpm@linux-foundation.org> <20080304090220.GA2875@linux-mips.org> X-Mailer: Sylpheed 2.4.1 (GTK+ 2.8.17; x86_64-unknown-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18333 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Tue, 4 Mar 2008 09:02:20 +0000 Ralf Baechle wrote: > On Mon, Mar 03, 2008 at 11:36:51PM -0800, Andrew Morton wrote: > > > ERROR: "__ucmpdi2" [drivers/net/wireless/b43legacy/b43legacy.ko] undefined! > > ERROR: "__ucmpdi2" [drivers/net/wireless/b43/b43.ko] undefined! > > > > int b43legacy_dma_init(struct b43legacy_wldev *dev) > > { > > struct b43legacy_dma *dma = &dev->dma; > > struct b43legacy_dmaring *ring; > > int err; > > u64 dmamask; > > enum b43legacy_dmatype type; > > > > dmamask = supported_dma_mask(dev); > > switch (dmamask) { > > default: > > B43legacy_WARN_ON(1); > > case DMA_30BIT_MASK: > > type = B43legacy_DMA_30BIT; > > break; > > case DMA_32BIT_MASK: > > type = B43legacy_DMA_32BIT; > > break; > > case DMA_64BIT_MASK: > > type = B43legacy_DMA_64BIT; > > break; > > } > > > > because some versions of gcc emit a __ucmpdi2 call for switch statements. > > Was this when optimizing for size btw? mips allmodconfig. So: yes. > It seems gcc is emitting alot more > calls to libgcc when optimizing for size. > > > It might be fixable by switching to an open-coded if/compare/else sequence. > > It was just a EXPORT_SYMBOL(__ucmpdi2) missing. doh. > > Or maybe my mips compiler (gcc-3.4.5) is just too old.. > > I'm trying to keep the tools requirements the same as for x86. So for > 32-bit kernels gcc 3.2 is the minimum but 3.2 is broken beyond recovery > for 64-bit code so there a minimum of 3.3 is required. > > In practive it is ages that I've last seen a compiler older than gcc 3.4 > being used to build a modern kernel for any architecture and 3.2 and 3.3 > are a sufficient special case that maybe we should think about deprecating > 3.2 and 3.3? That would make life easier for us. I don't know what the downstream implications would be. I'd need a new cross-compiler, for a start ;) From jamesz@modsystems.com Tue Mar 4 20:51:06 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Mar 2008 20:51:08 +0000 (GMT) Received: from dotcorporate.com ([67.50.105.12]:27964 "EHLO dotexchange.dotcorporation.com") by ftp.linux-mips.org with ESMTP id S28601762AbYCDUvG (ORCPT ); Tue, 4 Mar 2008 20:51:06 +0000 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C87E39.76196329" Subject: RE: smp8634 add memory at dram1 Date: Tue, 4 Mar 2008 12:51:03 -0800 Message-ID: <2D30722FBBDE6749973243F4F01BE984A242CC@dotexchange.dotcorporation.com> In-Reply-To: <2D30722FBBDE6749973243F4F01BE984A242CB@dotexchange.dotcorporation.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: smp8634 add memory at dram1 Thread-Index: Ach9jncajtrbM7+KS8auCZEQx2hQEQABxn5wACewQeA= From: "James Zipperer" To: "David Daney" Cc: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18334 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jamesz@modsystems.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. ------_=_NextPart_001_01C87E39.76196329 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable James Zipperer wrote: >>>=20 >>> =20 >>>=20 >>> I'm running out of memory in linux on the smp86xx and attempting to=20 >>> implement this solution. Did you ever get it to work? No luck for me=20 >>> yet. I'm still a bit unclear why you must switch linux to run off DRAM=20 >>> 1 instead of leaving it on DRAM 0 and adding an additional call to=20 >>> add_memory_region in prom_init for DRAM 1. But then again, I haven't=20 >>> gotten that to work yet either :) >>>=20 >>> =20 >>>=20 >>> Any info/patches are greatly appreciated. Thanks! >>>=20 >>> =20 >>>=20 >> >>Typically DRAM 1 must be accessed through the TLB as its address lays=20 >>outside of the 512MB window of KSEG[012]. >> >>The best way to make this memory available to Linux may still be up for=20 >>debate. >> >>David Daney >> > >I'm sure this is a dumb question due to the fact that my grasp of the >problem is less than acceptable... =20 > >Can remapped addresses (namely CPU_remap[34]_addr) be used for the call to >add_memory_region()? That would allow the address for DRAM 1 to be within >the 512MB window of KSEG[012]. I'm unclear whether the CPU_remap addresses >count as PHSYICAL or VIRTUAL addresses. =20 > >I'm guessing that my plan won't work since I tried it and it didn't work. >My results were that the kernel booted but didn't report any additional >memory available via the 'free' command. > >Thanks. > >-James So I think I've got a little better grasp on the problem. Is the reason you can't just remap DRAM 1 to 0x08000000 - 0x1000000000 because this is below the start address of linux 0x10020000? Can this restriction be worked around easily? =20 So as far as I can tell, the options are: =20 1. YH's proposed solution to use CPU remap registers to map DRAM1 to 0x08000000 - 0x10000000 in the bootloader, make linux run from DRAM1, and then add_memory_region for DRAM1 and DRAM0. =20 2. YH's other proposed solution to leave linux running from DRAM0, enable HIMEM, add_memory_region for DRAM1 using HIMEM, fix HIMEM issues regarding cache aliasing. =20 3. Work around adding memory that starts below linux (not sure if this is even possible). =20 Are there other options as well? Thanks! =20 -James =20 ------_=_NextPart_001_01C87E39.76196329 Content-Type: text/html; charset="US-ASCII" Content-Transfer-Encoding: quoted-printable

James = Zipperer wrote:

>>>

>>>  =

>>>

>>> I'm running out of memory in linux on the smp86xx = and attempting to

>>> implement this solution.  Did you ever get it to = work?  No luck for me =

>>> yet.  I'm still a bit unclear why you = must switch linux to run off DRAM

>>> 1 instead of leaving it on DRAM 0 and adding an = additional call to

>>> add_memory_region in prom_init for DRAM 1.  = But then again, I haven't

>>> gotten that to work yet either = :)

>>>

>>>  =

>>>

>>> Any info/patches are greatly appreciated.  = Thanks!

>>>

>>>  =

>>>

>>

>>Typically DRAM 1 must be accessed through the TLB as its address lays

>>outside of the 512MB window of KSEG[012].

>>

>>The best way to make this memory available to Linux may = still be up for

>>debate.

>>

>>David Daney

>>

>

>I'm sure this is a dumb question due to the fact that my = grasp of the >problem is less than acceptable... 

>

>Can remapped addresses (namely CPU_remap[34]_addr) be used for the call to >add_memory_region()?  That would allow the address = for DRAM 1 to be within >the 512MB window of KSEG[012].  I'm unclear whether the = CPU_remap addresses >count as PHSYICAL or VIRTUAL addresses. 

>

>I'm guessing that my plan won't work since I tried it and it = didn't work.  >My results were = that the kernel booted but didn't report any additional >memory available via = the 'free' command.

>

>Thanks.

>

>-James


So I think I've got a little better grasp on the problem.  Is the reason you can't just = remap DRAM 1 to 0x08000000 - 0x1000000000 because this is below the start address = of linux 0x10020000?  Can this restriction be worked around = easily?

 

So as far as I can tell, the = options are:

 

1. YH's proposed solution to use CPU remap registers to map DRAM1 to 0x08000000 - = 0x10000000 in the bootloader, make linux run from DRAM1, and then add_memory_region = for DRAM1 and DRAM0.

 

2. YH's other proposed solution to leave linux running = from DRAM0, enable HIMEM, add_memory_region for DRAM1 = using HIMEM, fix HIMEM issues regarding cache = aliasing.

 

3. Work around adding memory that = starts below linux (not sure if this is even = possible).

 

Are there other options as = well?  = Thanks!

 

-James

 

=00 ------_=_NextPart_001_01C87E39.76196329-- From opencode@gmx.net Wed Mar 5 12:35:28 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Mar 2008 12:35:31 +0000 (GMT) Received: from mail.gmx.net ([213.165.64.20]:45187 "HELO mail.gmx.net") by ftp.linux-mips.org with SMTP id S20032430AbYCEMf2 (ORCPT ); Wed, 5 Mar 2008 12:35:28 +0000 Received: (qmail invoked by alias); 05 Mar 2008 12:35:23 -0000 Received: from vpn27.rz.tu-ilmenau.de (EHLO [192.168.1.100]) [141.24.172.27] by mail.gmx.net (mp054) with SMTP; 05 Mar 2008 13:35:23 +0100 X-Authenticated: #44099387 X-Provags-ID: V01U2FsdGVkX19LO7FGJo1LqyDCRELHVaQ9xpYxfl0PvDlgFJmUo0 5SArwd1lD7ZZun Message-ID: <47CE9388.9050808@gmx.net> Date: Wed, 05 Mar 2008 13:35:20 +0100 From: Andi User-Agent: Thunderbird 2.0.0.12 (X11/20080227) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Problems booting Linux kernel on Sigma SMP8634 #2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Y-GMX-Trusted: 0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18335 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: opencode@gmx.net Precedence: bulk X-list: linux-mips Hey folks, first of all, sorry for _waisting_ the list with that topic again and again! this question is related to that one here, posted sooner on this list: http://www.linux-mips.org/archives/linux-mips/2008-02/msg00032.html I spent a bit more time on this topic and found out that there is seriously something going wrong with memory initialization and/or handling during Linux startup. I simply add "mem=32m" to the kernel command line, and the kernel runs longer, at least a bit. However, it than stops with nearly the same issue: Unable to handle kernel paging request at virtual address, but different addresses. Tried "16m, 64m" and other values, all behave in different way. Resulting to a crash at the position w/o any parameter or a bit later on. Since I am not so familiar MIPS and especially the fact that our hard- and software is more than closed, I am asking you guys to point me where to spend more time on in order to get this issue fixed and fire up a kernel on this box. I am sure there some more guys around using the smp8634. Is it necessary to load the microcode in order to get the kernel starting up? Maybe we don't need the audio/video-ucode but irq-handler-ucode looks very usefull ;-) Do we just have to copy this code at a certain memory address? Thank you in advance ... Regards, Andi From ddaney@avtrex.com Wed Mar 5 17:03:31 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Mar 2008 17:03:33 +0000 (GMT) Received: from smtp1.dnsmadeeasy.com ([205.234.170.144]:55465 "EHLO smtp1.dnsmadeeasy.com") by ftp.linux-mips.org with ESMTP id S28602383AbYCERDb (ORCPT ); Wed, 5 Mar 2008 17:03:31 +0000 Received: from smtp1.dnsmadeeasy.com (localhost [127.0.0.1]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP id 207183153C9; Wed, 5 Mar 2008 17:03:30 +0000 (UTC) X-Authenticated-Name: js.dnsmadeeasy X-Transit-System: In case of SPAM please contact abuse@dnsmadeeasy.com Received: from avtrex.com (unknown [67.116.42.147]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP; Wed, 5 Mar 2008 17:03:29 +0000 (UTC) Received: from dl2.hq2.avtrex.com ([192.168.7.26]) by avtrex.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 5 Mar 2008 09:03:15 -0800 Message-ID: <47CED252.20800@avtrex.com> Date: Wed, 05 Mar 2008 09:03:14 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.12 (X11/20080226) MIME-Version: 1.0 To: Andi Cc: linux-mips@linux-mips.org Subject: Re: Problems booting Linux kernel on Sigma SMP8634 #2 References: <47CE9388.9050808@gmx.net> In-Reply-To: <47CE9388.9050808@gmx.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Mar 2008 17:03:15.0676 (UTC) FILETIME=[CD9371C0:01C87EE2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18336 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@avtrex.com Precedence: bulk X-list: linux-mips Andi wrote: > Hey folks, > > first of all, sorry for _waisting_ the list with that topic again and again! > > this question is related to that one here, posted sooner on this list: > http://www.linux-mips.org/archives/linux-mips/2008-02/msg00032.html > > I spent a bit more time on this topic and found out that there is > seriously something going wrong with memory initialization and/or > handling during Linux startup. > > I simply add "mem=32m" to the kernel command line, and the kernel runs > longer, at least a bit. However, it than stops with nearly the same > issue: Unable to handle kernel paging request at virtual address, but > different addresses. Tried "16m, 64m" and other values, all behave in > different way. Resulting to a crash at the position w/o any parameter or > a bit later on. > > Since I am not so familiar MIPS and especially the fact that our hard- > and software is more than closed, I am asking you guys to point me where > to spend more time on in order to get this issue fixed and fire up a > kernel on this box. I build and successfully run kernels on the 8634 every day, so I don't think it is a problem with the 8634 port in general. You should probably ask for technical support from whomever supplied your hardware. They would know the technical details about how to configure the memory controller, the amount and location of the RAM on the board, etc. > > I am sure there some more guys around using the smp8634. Likely there are. It is used in many blu-ray disk players, among other things. > Is it necessary > to load the microcode in order to get the kernel starting up? No. > Maybe we don't need the audio/video-ucode but irq-handler-ucode looks > very usefull ;-) Do we just have to copy this code at a certain memory > address? N/A, the kernel does not rely on any microcode. The drivers for the audio/video handling hardware on the 8634 do require microcode, but in many cases it is loaded after the kernel is running. But the microcode is not needed for just running a bare bones kernel. David Daney From opencode@gmx.net Wed Mar 5 18:25:26 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Mar 2008 18:25:29 +0000 (GMT) Received: from mail.gmx.net ([213.165.64.20]:45504 "HELO mail.gmx.net") by ftp.linux-mips.org with SMTP id S28603017AbYCESZ0 (ORCPT ); Wed, 5 Mar 2008 18:25:26 +0000 Received: (qmail invoked by alias); 05 Mar 2008 18:25:20 -0000 Received: from vpn27.rz.tu-ilmenau.de (EHLO [192.168.1.100]) [141.24.172.27] by mail.gmx.net (mp047) with SMTP; 05 Mar 2008 19:25:20 +0100 X-Authenticated: #44099387 X-Provags-ID: V01U2FsdGVkX18ywJsmrzYydDPYR/YZLIVkeDgiCCg7zLKa3icl4n Z0AsugO2yLUOZ6 Message-ID: <47CEE58C.7020507@gmx.net> Date: Wed, 05 Mar 2008 19:25:16 +0100 From: Andi User-Agent: Thunderbird 2.0.0.12 (X11/20080227) MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org Subject: Re: Problems booting Linux kernel on Sigma SMP8634 #2 References: <47CE9388.9050808@gmx.net> <47CED252.20800@avtrex.com> In-Reply-To: <47CED252.20800@avtrex.com> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Y-GMX-Trusted: 0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18337 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: opencode@gmx.net Precedence: bulk X-list: linux-mips Hi, > I build and successfully run kernels on the 8634 every day, so I don't > think it is a problem with the 8634 port in general. > > You should probably ask for technical support from whomever supplied > your hardware. They would know the technical details about how to > configure the memory controller, the amount and location of the RAM on > the board, etc. Thats right. And I would really like to do so. But unfortunately there is not much information around about the hardware. Since the box originally runs a wince system, this project is more like a _free time_ projects of some Linux enthusiasts. You can get a overview about this here: http://www.t-hack.com/wiki/ There is also a forum, but unfortunately most posts are in German .. >> I am sure there some more guys around using the smp8634. > > Likely there are. It is used in many blu-ray disk players, among other > things. Ok, there is not much information about the smp8634 out there, which is really a pity. I know that Sigma is not really interested in publishing there specifications. Even the gpl part is not published, but I am sure you already know this :-) Do you know how to get some more detailed information about the smp8634? Ok, there are some parts that are not equal, like memory and flash! But this is a SoC, so most parts are the same. > N/A, the kernel does not rely on any microcode. Ok, thanks, so we can cancel this on our todo-list .. Regards, Andi From dvomlehn@cisco.com Wed Mar 5 22:56:05 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Mar 2008 22:56:08 +0000 (GMT) Received: from sj-iport-2.cisco.com ([171.71.176.71]:23379 "EHLO sj-iport-2.cisco.com") by ftp.linux-mips.org with ESMTP id S28602814AbYCEW4F (ORCPT ); Wed, 5 Mar 2008 22:56:05 +0000 Received: from sj-dkim-1.cisco.com ([171.71.179.21]) by sj-iport-2.cisco.com with ESMTP; 05 Mar 2008 14:55:57 -0800 Received: from sj-core-4.cisco.com (sj-core-4.cisco.com [171.68.223.138]) by sj-dkim-1.cisco.com (8.12.11/8.12.11) with ESMTP id m25Mtv65026063 for ; Wed, 5 Mar 2008 14:55:57 -0800 Received: from cliff.cisco.com (cliff.cisco.com [171.69.11.141]) by sj-core-4.cisco.com (8.12.10/8.12.6) with ESMTP id m25MtvJt001158 for ; Wed, 5 Mar 2008 22:55:57 GMT Received: from [127.0.0.1] ([64.100.148.129]) by cliff.cisco.com (8.6.12/8.6.5) with ESMTP id WAA08262 for ; Wed, 5 Mar 2008 22:55:56 GMT Message-ID: <47CF24F4.4010508@cisco.com> Date: Wed, 05 Mar 2008 14:55:48 -0800 From: David VomLehn User-Agent: Thunderbird 2.0.0.12 (Windows/20080213) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: Does HIGHMEM work on 32-bit MIPS ports? Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=2467; t=1204757757; x=1205621757; c=relaxed/simple; s=sjdkim1004; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20Re=3A=20Does=20HIGHMEM=20work=20on=2032-bit=20M IPS=20ports? |Sender:=20; bh=OllSub+IzBFbXhHc8sSRqFbdgkaVoYPay20En0pb9Fc=; b=bPgppIffRtg0BHu2mXdw+Y2UEtf0/YMyB5p0tRkmn4F1pZuzKdKdUM5flZ DBKHOL0o0aNdz7y8QGBUo28643qv/luzSHjby+oaf46mFEvNgbw1FMMIpb0w wly1GBVnBYNwSjswSJayJbYxQPFNMSTZHPTaPw/l5TCYXxJOfRbCU=; Authentication-Results: sj-dkim-1; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim1004 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18338 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips We've made significant progress in getting HIGHMEM to work on our 24K processor, but things do not completely work yet. Since I don't yet have confidence that we know everything that's going on, I"m not ready to submit a full-blown patch, but here's what we've done so far. Please send comments/suggestions... The function __flush_dcache_page (in arch/mips/mm/cache.c) was simply returning if the struct page* argument it was given indicated we had a page in high memory, so the dcache was never being flushed. This is an obvious Bad Thing. Our first modification was to expand the check for high memory. If the page had a temporary mapping, i.e. it was mapped through kmap_atomic(), we call flush_data_cache_page(). We then immediately return: if (PageHighMem(page)) { addr = (unsigned long)kmap_atomic_to_vaddr(page); if (addr != 0) { flush_data_cache_page(addr); } return; } (kmap_atomic_to_vaddr() returns the virtual address if the page is mapped with kmap_atomic(), otherwise it returns NULL). This change by itself is enough to be able to boot with NFS most of the time. I think it is not sufficient for permanently mapped kernel pages (those mapped with kmap_high()). So, I made two other modifications. Additional Modification #1: To me, it looks like the return should be moved to right after the call to flush_data_cache_page() so that we only return immediately for temporary kernel mappings. The next section of code, which I think already works correctly with high memory, is: if (mapping && !mapping_mapped(mapping)) { SetPageDcacheDirty(page); return; } We then have the following: addr = (unsigned long) page_address(page); flush_data_cache_page(addr); Additional Modification #2: If the page is in high memory, it may not have a kernel mapping, in which case page_address() will return NULL. So, I've modified the code to only call flush_data_cache_page() if the page_address() doesn't return NULL. With the two additional modifications above, thing are still not completely reliable. So, two questions: 1. Does what we've done so far make sense? 2. Since the behavior is still somewhat flaky, I'm still missing something. Any suggestions? -- David VomLehn, dvomlehn@cisco.com The opinions expressed herein are likely mine, but might not be my employer's... From daniel.j.laird@googlemail.com Thu Mar 6 09:07:22 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 06 Mar 2008 09:07:27 +0000 (GMT) Received: from wx-out-0506.google.com ([66.249.82.236]:6895 "EHLO wx-out-0506.google.com") by ftp.linux-mips.org with ESMTP id S28603157AbYCFJHW (ORCPT ); Thu, 6 Mar 2008 09:07:22 +0000 Received: by wx-out-0506.google.com with SMTP id h30so2873210wxd.21 for ; Thu, 06 Mar 2008 01:07:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:sender:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition:x-google-sender-auth; bh=bG4q/1JkeVwGOOkFv75OQeEAoITGieQGH2URLbtV0dc=; b=rO3wpYXfYP/odyIOV6NMxo5mAbi405L+iHYRNrla0l07uWVS9Ys6TOTShMIX5f+hVnPwBLDTj774uEfZZHb4PVcQwNAvCBdaKROEywsybOQhzn0AMRN5NZSfHpV9eegn4IXaFV1SnRbw4ZRgjz3NFsyVQrJk5/egtIDykDWJQWQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=message-id:date:from:sender:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition:x-google-sender-auth; b=btB6mKauczjT08NbYtcB5XgCg/mTIasMLDyQkH3jKAnTSWpynmfGEUesDwFzJKIpMXbNiJvqx/UqftoYs9idd/BxVOi3xERND0M3DWYnJJT/mMPS3QZlDfQoezcqXcoBvN8coN+VeLzakUtkryl+sWEo8Rton0285xSGFV9aj2w= Received: by 10.70.87.5 with SMTP id k5mr4620962wxb.13.1204794438255; Thu, 06 Mar 2008 01:07:18 -0800 (PST) Received: by 10.70.16.20 with HTTP; Thu, 6 Mar 2008 01:07:18 -0800 (PST) Message-ID: <64660ef00803060107m16fb4a4uc0153ea3c6658b8f@mail.gmail.com> Date: Thu, 6 Mar 2008 09:07:18 +0000 From: "Daniel Laird" To: linux-mips@linux-mips.org Subject: [PATCH] : Move arch/mips/philips to arch/mips/nxp MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline X-Google-Sender-Auth: 8a54cde7f39d13af Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 18339 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: daniel.j.laird@nxp.com Precedence: bulk X-list: linux-mips The following patch moves arch/mips/philips to arch/mips/nxp along with the supporting changes: This is required before I can start posting new chipset support. arch/mips/Kconfig | 4 arch/mips/Makefile | 12 - arch/mips/kernel/cpu-probe.c | 10 - arch/mips/nxp/pnx8550/common/Makefile | 29 +++ arch/mips/nxp/pnx8550/common/gdb_hook.c | 109 +++++++++++ arch/mips/nxp/pnx8550/common/int.c | 238 +++++++++++++++++++++++++ arch/mips/nxp/pnx8550/common/pci.c | 133 +++++++++++++ arch/mips/nxp/pnx8550/common/platform.c | 132 +++++++++++++ arch/mips/nxp/pnx8550/common/proc.c | 112 +++++++++++ arch/mips/nxp/pnx8550/common/prom.c | 129 +++++++++++++ arch/mips/nxp/pnx8550/common/reset.c | 49 +++++ arch/mips/nxp/pnx8550/common/setup.c | 157 ++++++++++++++++ arch/mips/nxp/pnx8550/common/time.c | 150 +++++++++++++++ arch/mips/nxp/pnx8550/jbs/Makefile | 4 arch/mips/nxp/pnx8550/jbs/board_setup.c | 65 ++++++ arch/mips/nxp/pnx8550/jbs/init.c | 53 +++++ arch/mips/nxp/pnx8550/jbs/irqmap.c | 36 +++ arch/mips/nxp/pnx8550/stb810/Makefile | 4 arch/mips/nxp/pnx8550/stb810/board_setup.c | 49 +++++ arch/mips/nxp/pnx8550/stb810/irqmap.c | 23 ++ arch/mips/nxp/pnx8550/stb810/prom_init.c | 46 ++++ arch/mips/philips/pnx8550/common/Makefile | 29 --- arch/mips/philips/pnx8550/common/gdb_hook.c | 109 ----------- arch/mips/philips/pnx8550/common/int.c | 238 ------------------------- arch/mips/philips/pnx8550/common/pci.c | 133 ------------- arch/mips/philips/pnx8550/common/platform.c | 132 ------------- arch/mips/philips/pnx8550/common/proc.c | 112 ----------- arch/mips/philips/pnx8550/common/prom.c | 129 ------------- arch/mips/philips/pnx8550/common/reset.c | 49 ----- arch/mips/philips/pnx8550/common/setup.c | 157 ---------------- arch/mips/philips/pnx8550/common/time.c | 150 --------------- arch/mips/philips/pnx8550/jbs/Makefile | 4 arch/mips/philips/pnx8550/jbs/board_setup.c | 65 ------ arch/mips/philips/pnx8550/jbs/init.c | 53 ----- arch/mips/philips/pnx8550/jbs/irqmap.c | 36 --- arch/mips/philips/pnx8550/stb810/Makefile | 4 arch/mips/philips/pnx8550/stb810/board_setup.c | 49 ----- arch/mips/philips/pnx8550/stb810/irqmap.c | 23 -- arch/mips/philips/pnx8550/stb810/prom_init.c | 46 ---- include/asm-mips/cpu.h | 2 40 files changed, 1532 insertions(+), 1532 deletions(-) Signed-off-by: daniel.j.laird diff -urN linux.orig/arch/mips/Kconfig linux/arch/mips/Kconfig --- linux.orig/arch/mips/Kconfig 2008-03-04 11:08:00.000000000 +0000 +++ linux/arch/mips/Kconfig 2008-03-04 11:13:18.000000000 +0000 @@ -309,12 +309,12 @@ select GENERIC_HARDIRQS_NO__DO_IRQ config PNX8550_JBS - bool "Philips PNX8550 based JBS board" + bool "NXP PNX8550 based JBS board" select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN config PNX8550_STB810 - bool "Philips PNX8550 based STB810 board" + bool "NXP PNX8550 based STB810 board" select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN diff -urN linux.orig/arch/mips/kernel/cpu-probe.c linux/arch/mips/kernel/cpu-probe.c --- linux.orig/arch/mips/kernel/cpu-probe.c 2008-03-04 11:08:00.000000000 +0000 +++ linux/arch/mips/kernel/cpu-probe.c 2008-03-04 11:13:18.000000000 +0000 @@ -778,7 +778,7 @@ } } -static inline void cpu_probe_philips(struct cpuinfo_mips *c) +static inline void cpu_probe_nxp(struct cpuinfo_mips *c) { decode_configs(c); switch (c->processor_id & 0xff00) { @@ -787,7 +787,7 @@ c->isa_level = MIPS_CPU_ISA_M32R1; break; default: - panic("Unknown Philips Core!"); /* REVISIT: die? */ + panic("Unknown NXP Core!"); /* REVISIT: die? */ break; } } @@ -887,7 +887,7 @@ case CPU_SR71000: name = "Sandcraft SR71000"; break; case CPU_BCM3302: name = "Broadcom BCM3302"; break; case CPU_BCM4710: name = "Broadcom BCM4710"; break; - case CPU_PR4450: name = "Philips PR4450"; break; + case CPU_PR4450: name = "NXP PR4450"; break; case CPU_LOONGSON2: name = "ICT Loongson-2"; break; default: BUG(); @@ -925,8 +925,8 @@ case PRID_COMP_SANDCRAFT: cpu_probe_sandcraft(c); break; - case PRID_COMP_PHILIPS: - cpu_probe_philips(c); + case PRID_COMP_NXP: + cpu_probe_nxp(c); break; default: c->cputype = CPU_UNKNOWN; diff -urN linux.orig/arch/mips/Makefile linux/arch/mips/Makefile --- linux.orig/arch/mips/Makefile 2008-03-04 11:08:00.000000000 +0000 +++ linux/arch/mips/Makefile 2008-03-04 11:13:18.000000000 +0000 @@ -410,21 +410,21 @@ load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 # -# Common Philips PNX8550 +# Common NXP PNX8550 # -core-$(CONFIG_SOC_PNX8550) += arch/mips/philips/pnx8550/common/ +core-$(CONFIG_SOC_PNX8550) += arch/mips/nxp/pnx8550/common/ cflags-$(CONFIG_SOC_PNX8550) += -Iinclude/asm-mips/mach-pnx8550 # -# Philips PNX8550 JBS board +# NXP PNX8550 JBS board # -libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/ +libs-$(CONFIG_PNX8550_JBS) += arch/mips/nxp/pnx8550/jbs/ #cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550 load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 -# Philips PNX8550 STB810 board +# NXP PNX8550 STB810 board # -libs-$(CONFIG_PNX8550_STB810) += arch/mips/philips/pnx8550/stb810/ +libs-$(CONFIG_PNX8550_STB810) += arch/mips/nxp/pnx8550/stb810/ load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000 # NEC EMMA2RH boards diff -urN linux.orig/arch/mips/nxp/pnx8550/common/gdb_hook.c linux/arch/mips/nxp/pnx8550/common/gdb_hook.c --- linux.orig/arch/mips/nxp/pnx8550/common/gdb_hook.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/common/gdb_hook.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,109 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * This is the interface to the remote debugger stub. + * + */ +#include +#include +#include +#include +#include + +#include +#include + +#include + +static struct serial_state rs_table[IP3106_NR_PORTS] = { +}; +static struct async_struct kdb_port_info = {0}; + +void rs_kgdb_hook(int tty_no) +{ + struct serial_state *ser = &rs_table[tty_no]; + + kdb_port_info.state = ser; + kdb_port_info.magic = SERIAL_MAGIC; + kdb_port_info.port = tty_no; + kdb_port_info.flags = ser->flags; + + /* + * Clear all interrupts + */ + /* Clear all the transmitter FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST; + /* Clear all the receiver FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST; + /* Clear all interrupts */ + ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX | + IP3106_UART_INT_ALLTX; + + /* + * Now, initialize the UART + */ + ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT; + ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud +} + +int putDebugChar(char c) +{ + /* Wait until FIFO not full */ + while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16) + ; + /* Send one char */ + ip3106_fifo(UART_BASE, kdb_port_info.port) = c; + + return 1; +} + +char getDebugChar(void) +{ + char ch; + + /* Wait until there is a char in the FIFO */ + while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) & + IP3106_UART_FIFO_RXFIFO) >> 8)) + ; + /* Read one char */ + ch = ip3106_fifo(UART_BASE, kdb_port_info.port) & + IP3106_UART_FIFO_RBRTHR; + /* Advance the RX FIFO read pointer */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT; + return (ch); +} + +void rs_disable_debug_interrupts(void) +{ + ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */ +} + +void rs_enable_debug_interrupts(void) +{ + /* Clear all the transmitter FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST; + /* Clear all the receiver FIFO counters (pointer and status) */ + ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST; + /* Clear all interrupts */ + ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX | + IP3106_UART_INT_ALLTX; + ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */ +} diff -urN linux.orig/arch/mips/nxp/pnx8550/common/int.c linux/arch/mips/nxp/pnx8550/common/int.c --- linux.orig/arch/mips/nxp/pnx8550/common/int.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/common/int.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,238 @@ +/* + * + * Copyright (C) 2005 Embedded Alley Solutions, Inc + * Ported to 2.6. + * + * Per Hallsmark, per.hallsmark@mvista.com + * Copyright (C) 2000, 2001 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * + * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* default prio for interrupts */ +/* first one is a no-no so therefore always prio 0 (disabled) */ +static char gic_prio[PNX8550_INT_GIC_TOTINT] = { + 0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49 + 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69 + 1 // 70 +}; + +static void hw0_irqdispatch(int irq) +{ + /* find out which interrupt */ + irq = PNX8550_GIC_VECTOR_0 >> 3; + + if (irq == 0) { + printk("hw0_irqdispatch: irq 0, spurious interrupt?\n"); + return; + } + do_IRQ(PNX8550_INT_GIC_MIN + irq); +} + + +static void timer_irqdispatch(int irq) +{ + irq = (0x01c0 & read_c0_config7()) >> 6; + + if (unlikely(irq == 0)) { + printk("timer_irqdispatch: irq 0, spurious interrupt?\n"); + return; + } + + if (irq & 0x1) + do_IRQ(PNX8550_INT_TIMER1); + if (irq & 0x2) + do_IRQ(PNX8550_INT_TIMER2); + if (irq & 0x4) + do_IRQ(PNX8550_INT_TIMER3); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP2) + hw0_irqdispatch(2); + else if (pending & STATUSF_IP7) { + if (read_c0_config7() & 0x01c0) + timer_irqdispatch(7); + } else + spurious_interrupt(); +} + +static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) +{ + unsigned long status = read_c0_status(); + + status &= ~((clr_mask & 0xFF) << 8); + status |= (set_mask & 0xFF) << 8; + + write_c0_status(status); +} + +static inline void mask_gic_int(unsigned int irq_nr) +{ + /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */ + PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */ +} + +static inline void unmask_gic_int(unsigned int irq_nr) +{ + /* set prio mask to lower four bits and enable interrupt */ + PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr]; +} + +static inline void mask_irq(unsigned int irq_nr) +{ + if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { + modify_cp0_intmask(1 << irq_nr, 0); + } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_GIC_MAX)) { + mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN); + } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_TIMER_MAX)) { + modify_cp0_intmask(1 << 7, 0); + } else { + printk("mask_irq: irq %d doesn't exist!\n", irq_nr); + } +} + +static inline void unmask_irq(unsigned int irq_nr) +{ + if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { + modify_cp0_intmask(0, 1 << irq_nr); + } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_GIC_MAX)) { + unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN); + } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) && + (irq_nr <= PNX8550_INT_TIMER_MAX)) { + modify_cp0_intmask(0, 1 << 7); + } else { + printk("mask_irq: irq %d doesn't exist!\n", irq_nr); + } +} + +int pnx8550_set_gic_priority(int irq, int priority) +{ + int gic_irq = irq-PNX8550_INT_GIC_MIN; + int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf; + + gic_prio[gic_irq] = priority; + PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]); + + return prev_priority; +} + +static struct irq_chip level_irq_type = { + .name = "PNX Level IRQ", + .ack = mask_irq, + .mask = mask_irq, + .mask_ack = mask_irq, + .unmask = unmask_irq, +}; + +static struct irqaction gic_action = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "GIC", +}; + +static struct irqaction timer_action = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "Timer", +}; + +void __init arch_init_irq(void) +{ + int i; + int configPR; + + for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { + set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + mask_irq(i); /* mask the irq just in case */ + } + + /* init of GIC/IPC interrupts */ + /* should be done before cp0 since cp0 init enables the GIC int */ + for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) { + int gic_int_line = i - PNX8550_INT_GIC_MIN; + if (gic_int_line == 0 ) + continue; // don't fiddle with int 0 + /* + * enable change of TARGET, ENABLE and ACTIVE_LOW bits + * set TARGET 0 to route through hw0 interrupt + * set ACTIVE_LOW 0 active high (correct?) + * + * We really should setup an interrupt description table + * to do this nicely. + * Note, PCI INTA is active low on the bus, but inverted + * in the GIC, so to us it's active high. + */ + PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000; + + /* mask/priority is still 0 so we will not get any + * interrupts until it is unmasked */ + + set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + } + + /* Priority level 0 */ + PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0; + + /* Set int vector table address */ + PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; + + set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, + handle_level_irq); + setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); + + /* init of Timer interrupts */ + for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) + set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + + /* Stop Timer 1-3 */ + configPR = read_c0_config7(); + configPR |= 0x00000038; + write_c0_config7(configPR); + + set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, + handle_level_irq); + setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); +} + +EXPORT_SYMBOL(pnx8550_set_gic_priority); diff -urN linux.orig/arch/mips/nxp/pnx8550/common/Makefile linux/arch/mips/nxp/pnx8550/common/Makefile --- linux.orig/arch/mips/nxp/pnx8550/common/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/common/Makefile 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,29 @@ +# +# Per Hallsmark, per.hallsmark@mvista.com +# +# ######################################################################## +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# +# ####################################################################### +# +# Makefile for the PNX8550 specific kernel interface routines +# under Linux. +# + +obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_KGDB) += gdb_hook.o + +EXTRA_CFLAGS += -Werror diff -urN linux.orig/arch/mips/nxp/pnx8550/common/pci.c linux/arch/mips/nxp/pnx8550/common/pci.c --- linux.orig/arch/mips/nxp/pnx8550/common/pci.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/common/pci.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,133 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * + * Author: source@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include + +#include +#include +#include + +static struct resource pci_io_resource = { + .start = PNX8550_PCIIO + 0x1000, /* reserve regacy I/O space */ + .end = PNX8550_PCIIO + PNX8550_PCIIO_SIZE, + .name = "pci IO space", + .flags = IORESOURCE_IO +}; + +static struct resource pci_mem_resource = { + .start = PNX8550_PCIMEM, + .end = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1, + .name = "pci memory space", + .flags = IORESOURCE_MEM +}; + +extern struct pci_ops pnx8550_pci_ops; + +static struct pci_controller pnx8550_controller = { + .pci_ops = &pnx8550_pci_ops, + .io_resource = &pci_io_resource, + .mem_resource = &pci_mem_resource, +}; + +/* Return the total size of DRAM-memory, (RANK0 + RANK1) */ +static inline unsigned long get_system_mem_size(void) +{ + /* Read IP2031_RANK0_ADDR_LO */ + unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010); + /* Read IP2031_RANK1_ADDR_HI */ + unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018); + + return dram_r1_hi - dram_r0_lo + 1; +} + +static int __init pnx8550_pci_setup(void) +{ + int pci_mem_code; + int mem_size = get_system_mem_size() >> 20; + + /* Clear the Global 2 Register, PCI Inta Output Enable Registers + Bit 1:Enable DAC Powerdown + -> 0:DACs are enabled and are working normally + 1:DACs are powerdown + Bit 0:Enable of PCI inta output + -> 0 = Disable PCI inta output + 1 = Enable PCI inta output + */ + PNX8550_GLB2_ENAB_INTA_O = 0; + + /* Calc the PCI mem size code */ + if (mem_size >= 128) + pci_mem_code = SIZE_128M; + else if (mem_size >= 64) + pci_mem_code = SIZE_64M; + else if (mem_size >= 32) + pci_mem_code = SIZE_32M; + else + pci_mem_code = SIZE_16M; + + /* Set PCI_XIO registers */ + outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO); + outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI); + outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO); + outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI); + + /* Send memory transaction via PCI_BASE2 */ + outl(0x00000001, PCI_BASE | PCI_IO); + + /* Unlock the setup register */ + outl(0xca, PCI_BASE | PCI_UNLOCKREG); + + /* + * BAR0 of PNX8550 (pci base 10) must be zero in order for ide + * to work, and in order for bus_to_baddr to work without any + * hacks. + */ + outl(0x00000000, PCI_BASE | PCI_BASE10); + + /* + *These two bars are set by default or the boot code. + * However, it's safer to set them here so we're not boot + * code dependent. + */ + outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */ + outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */ + + outl(PCI_EN_TA | + PCI_EN_PCI2MMI | + PCI_EN_XIO | + PCI_SETUP_BASE18_SIZE(SIZE_32M) | + PCI_SETUP_BASE18_EN | + PCI_SETUP_BASE14_EN | + PCI_SETUP_BASE10_PREF | + PCI_SETUP_BASE10_SIZE(pci_mem_code) | + PCI_SETUP_CFGMANAGE_EN | + PCI_SETUP_PCIARB_EN, + PCI_BASE | + PCI_SETUP); /* PCI_SETUP */ + outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */ + + register_pci_controller(&pnx8550_controller); + + return 0; +} + +arch_initcall(pnx8550_pci_setup); diff -urN linux.orig/arch/mips/nxp/pnx8550/common/platform.c linux/arch/mips/nxp/pnx8550/common/platform.c --- linux.orig/arch/mips/nxp/pnx8550/common/platform.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/common/platform.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,132 @@ +/* + * Platform device support for NXP PNX8550 SoCs + * + * Copyright 2005, Embedded Alley Solutions, Inc + * + * Based on arch/mips/au1000/common/platform.c + * Platform device support for Au1x00 SoCs. + * + * Copyright 2004, Matt Porter + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static struct resource pnx8550_usb_ohci_resources[] = { + [0] = { + .start = PNX8550_USB_OHCI_OP_BASE, + .end = PNX8550_USB_OHCI_OP_BASE + + PNX8550_USB_OHCI_OP_LEN, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8550_INT_USB, + .end = PNX8550_INT_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource pnx8550_uart_resources[] = { + [0] = { + .start = PNX8550_UART_PORT0, + .end = PNX8550_UART_PORT0 + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PNX8550_UART_INT(0), + .end = PNX8550_UART_INT(0), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = PNX8550_UART_PORT1, + .end = PNX8550_UART_PORT1 + 0xfff, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = PNX8550_UART_INT(1), + .end = PNX8550_UART_INT(1), + .flags = IORESOURCE_IRQ, + }, +}; + +struct pnx8xxx_port pnx8xxx_ports[] = { + [0] = { + .port = { + .type = PORT_PNX8XXX, + .iotype = UPIO_MEM, + .membase = (void __iomem *)PNX8550_UART_PORT0, + .mapbase = PNX8550_UART_PORT0, + .irq = PNX8550_UART_INT(0), + .uartclk = 3692300, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .line = 0, + }, + }, + [1] = { + .port = { + .type = PORT_PNX8XXX, + .iotype = UPIO_MEM, + .membase = (void __iomem *)PNX8550_UART_PORT1, + .mapbase = PNX8550_UART_PORT1, + .irq = PNX8550_UART_INT(1), + .uartclk = 3692300, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .line = 1, + }, + }, +}; + +/* The dmamask must be set for OHCI to work */ +static u64 ohci_dmamask = ~(u32)0; + +static u64 uart_dmamask = ~(u32)0; + +static struct platform_device pnx8550_usb_ohci_device = { + .name = "pnx8550-ohci", + .id = -1, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources), + .resource = pnx8550_usb_ohci_resources, +}; + +static struct platform_device pnx8550_uart_device = { + .name = "pnx8xxx-uart", + .id = -1, + .dev = { + .dma_mask = &uart_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = pnx8xxx_ports, + }, + .num_resources = ARRAY_SIZE(pnx8550_uart_resources), + .resource = pnx8550_uart_resources, +}; + +static struct platform_device *pnx8550_platform_devices[] __initdata = { + &pnx8550_usb_ohci_device, + &pnx8550_uart_device, +}; + +static int __init pnx8550_platform_init(void) +{ + return platform_add_devices(pnx8550_platform_devices, + ARRAY_SIZE(pnx8550_platform_devices)); +} + +arch_initcall(pnx8550_platform_init); diff -urN linux.orig/arch/mips/nxp/pnx8550/common/proc.c linux/arch/mips/nxp/pnx8550/common/proc.c --- linux.orig/arch/mips/nxp/pnx8550/common/proc.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/common/proc.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,112 @@ +/* + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +static int pnx8550_timers_read(char* page, char** start, off_t offset, int count, int* eof, void* data) +{ + int len = 0; + int configPR = read_c0_config7(); + + if (offset==0) { + len += sprintf(&page[len], "Timer: count, compare, tc, status\n"); + len += sprintf(&page[len], " 1: %11i, %8i, %1i, %s\n", + read_c0_count(), read_c0_compare(), + (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on"); + len += sprintf(&page[len], " 2: %11i, %8i, %1i, %s\n", + read_c0_count2(), read_c0_compare2(), + (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on"); + len += sprintf(&page[len], " 3: %11i, %8i, %1i, %s\n", + read_c0_count3(), read_c0_compare3(), + (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on"); + } + + return len; +} + +static int pnx8550_registers_read(char* page, char** start, off_t offset, int count, int* eof, void* data) +{ + int len = 0; + + if (offset==0) { + len += sprintf(&page[len], "config1: %#10.8x\n", read_c0_config1()); + len += sprintf(&page[len], "config2: %#10.8x\n", read_c0_config2()); + len += sprintf(&page[len], "config3: %#10.8x\n", read_c0_config3()); + len += sprintf(&page[len], "configPR: %#10.8x\n", read_c0_config7()); + len += sprintf(&page[len], "status: %#10.8x\n", read_c0_status()); + len += sprintf(&page[len], "cause: %#10.8x\n", read_c0_cause()); + len += sprintf(&page[len], "count: %#10.8x\n", read_c0_count()); + len += sprintf(&page[len], "count_2: %#10.8x\n", read_c0_count2()); + len += sprintf(&page[len], "count_3: %#10.8x\n", read_c0_count3()); + len += sprintf(&page[len], "compare: %#10.8x\n", read_c0_compare()); + len += sprintf(&page[len], "compare_2: %#10.8x\n", read_c0_compare2()); + len += sprintf(&page[len], "compare_3: %#10.8x\n", read_c0_compare3()); + } + + return len; +} + +static struct proc_dir_entry* pnx8550_dir = NULL; +static struct proc_dir_entry* pnx8550_timers = NULL; +static struct proc_dir_entry* pnx8550_registers = NULL; + +static int pnx8550_proc_init( void ) +{ + + // Create /proc/pnx8550 + pnx8550_dir = proc_mkdir("pnx8550", NULL); + if (!pnx8550_dir) { + printk(KERN_ERR "Can't create pnx8550 proc dir\n"); + return -1; + } + + // Create /proc/pnx8550/timers + pnx8550_timers = create_proc_read_entry( + "timers", + 0, + pnx8550_dir, + pnx8550_timers_read, + NULL); + + if (!pnx8550_timers) + printk(KERN_ERR "Can't create pnx8550 timers proc file\n"); + + // Create /proc/pnx8550/registers + pnx8550_registers = create_proc_read_entry( + "registers", + 0, + pnx8550_dir, + pnx8550_registers_read, + NULL); + + if (!pnx8550_registers) + printk(KERN_ERR "Can't create pnx8550 registers proc file\n"); + + return 0; +} + +__initcall(pnx8550_proc_init); diff -urN linux.orig/arch/mips/nxp/pnx8550/common/prom.c linux/arch/mips/nxp/pnx8550/common/prom.c --- linux.orig/arch/mips/nxp/pnx8550/common/prom.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/common/prom.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,129 @@ +/* + * + * Per Hallsmark, per.hallsmark@mvista.com + * + * Based on jmr3927/common/prom.c + * + * 2004 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include +#include +#include +#include + +#include +#include + +/* #define DEBUG_CMDLINE */ + +extern int prom_argc; +extern char **prom_argv, **prom_envp; + +typedef struct +{ + char *name; +/* char *val; */ +}t_env_var; + + +char * prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + int i; + + arcs_cmdline[0] = '\0'; + for (i = 0; i < prom_argc; i++) { + strcat(arcs_cmdline, prom_argv[i]); + strcat(arcs_cmdline, " "); + } +} + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + * Environment variables are stored in the form of "memsize=64". + */ + + t_env_var *env = (t_env_var *)prom_envp; + int i; + + i = strlen(envname); + + while(env->name) { + if(strncmp(envname, env->name, i) == 0) { + return(env->name + strlen(envname) + 1); + } + env++; + } + return(NULL); +} + +inline unsigned char str2hexnum(unsigned char c) +{ + if(c >= '0' && c <= '9') + return c - '0'; + if(c >= 'a' && c <= 'f') + return c - 'a' + 10; + if(c >= 'A' && c <= 'F') + return c - 'A' + 10; + return 0; /* foo */ +} + +inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for(i = 0; i < 6; i++) { + unsigned char num; + + if((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +int get_ethernet_addr(char *ethernet_addr) +{ + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + printk("ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + return 0; +} + +void __init prom_free_prom_memory(void) +{ +} + +extern int pnx8550_console_port; + +/* used by early printk */ +void prom_putchar(char c) +{ + if (pnx8550_console_port != -1) { + /* Wait until FIFO not full */ + while( ((ip3106_fifo(UART_BASE, pnx8550_console_port) & PNX8XXX_UART_FIFO_TXFIFO) >> 16) >= 16) + ; + /* Send one char */ + ip3106_fifo(UART_BASE, pnx8550_console_port) = c; + } +} + +EXPORT_SYMBOL(prom_getcmdline); +EXPORT_SYMBOL(get_ethernet_addr); +EXPORT_SYMBOL(str2eaddr); diff -urN linux.orig/arch/mips/nxp/pnx8550/common/reset.c linux/arch/mips/nxp/pnx8550/common/reset.c --- linux.orig/arch/mips/nxp/pnx8550/common/reset.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/common/reset.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,49 @@ +/*. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Reset the PNX8550 board. + * + */ +#include +#include +#include + +void pnx8550_machine_restart(char *command) +{ + char head[] = "************* Machine restart *************"; + char foot[] = "*******************************************"; + + printk("\n\n"); + printk("%s\n", head); + if (command != NULL) + printk("* %s\n", command); + printk("%s\n", foot); + + PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST; +} + +void pnx8550_machine_halt(void) +{ + printk("*** Machine halt. (Not implemented) ***\n"); +} + +void pnx8550_machine_power_off(void) +{ + printk("*** Machine power off. (Not implemented) ***\n"); +} diff -urN linux.orig/arch/mips/nxp/pnx8550/common/setup.c linux/arch/mips/nxp/pnx8550/common/setup.c --- linux.orig/arch/mips/nxp/pnx8550/common/setup.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/common/setup.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,157 @@ +/* + * + * 2.6 port, Embedded Alley Solutions, Inc + * + * Based on Per Hallsmark, per.hallsmark@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +extern void __init board_setup(void); +extern void pnx8550_machine_restart(char *); +extern void pnx8550_machine_halt(void); +extern void pnx8550_machine_power_off(void); +extern struct resource ioport_resource; +extern struct resource iomem_resource; +extern void rs_kgdb_hook(int tty_no); +extern char *prom_getcmdline(void); + +struct resource standard_io_resources[] = { + { + .start = 0x00, + .end = 0x1f, + .name = "dma1", + .flags = IORESOURCE_BUSY + }, { + .start = 0x40, + .end = 0x5f, + .name = "timer", + .flags = IORESOURCE_BUSY + }, { + .start = 0x80, + .end = 0x8f, + .name = "dma page reg", + .flags = IORESOURCE_BUSY + }, { + .start = 0xc0, + .end = 0xdf, + .name = "dma2", + .flags = IORESOURCE_BUSY + }, +}; + +#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources) + +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +/* Return the total size of DRAM-memory, (RANK0 + RANK1) */ +unsigned long get_system_mem_size(void) +{ + /* Read IP2031_RANK0_ADDR_LO */ + unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010); + /* Read IP2031_RANK1_ADDR_HI */ + unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018); + + return dram_r1_hi - dram_r0_lo + 1; +} + +int pnx8550_console_port = -1; + +void __init plat_mem_setup(void) +{ + int i; + char* argptr; + + board_setup(); /* board specific setup */ + + _machine_restart = pnx8550_machine_restart; + _machine_halt = pnx8550_machine_halt; + pm_power_off = pnx8550_machine_power_off; + + /* Clear the Global 2 Register, PCI Inta Output Enable Registers + Bit 1:Enable DAC Powerdown + -> 0:DACs are enabled and are working normally + 1:DACs are powerdown + Bit 0:Enable of PCI inta output + -> 0 = Disable PCI inta output + 1 = Enable PCI inta output + */ + PNX8550_GLB2_ENAB_INTA_O = 0; + + /* IO/MEM resources. */ + set_io_port_base(KSEG1); + ioport_resource.start = 0; + ioport_resource.end = ~0; + iomem_resource.start = 0; + iomem_resource.end = ~0; + + /* Request I/O space for devices on this board */ + for (i = 0; i < STANDARD_IO_RESOURCES; i++) + request_resource(&ioport_resource, standard_io_resources + i); + + /* Place the Mode Control bit for GPIO pin 16 in primary function */ + /* Pin 16 is used by UART1, UA1_TX */ + outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) | + (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT), + PNX8550_GPIO_MC1); + + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "console=ttyS")) != NULL) { + argptr += strlen("console=ttyS"); + pnx8550_console_port = *argptr == '0' ? 0 : 1; + + /* We must initialize the UART (console) before early printk */ + /* Set LCR to 8-bit and BAUD to 38400 (no 5) */ + ip3106_lcr(UART_BASE, pnx8550_console_port) = + PNX8XXX_UART_LCR_8BIT; + ip3106_baud(UART_BASE, pnx8550_console_port) = 5; + } + +#ifdef CONFIG_KGDB + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { + int line; + argptr += strlen("kgdb=ttyS"); + line = *argptr == '0' ? 0 : 1; + rs_kgdb_hook(line); + pr_info("KGDB: Using ttyS%i for session, " + "please connect your debugger\n", line ? 1 : 0); + } +#endif + return; +} diff -urN linux.orig/arch/mips/nxp/pnx8550/common/time.c linux/arch/mips/nxp/pnx8550/common/time.c --- linux.orig/arch/mips/nxp/pnx8550/common/time.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/common/time.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,150 @@ +/* + * Copyright 2001, 2002, 2003 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) + * + * Common time service routines for MIPS machines. See + * Documents/MIPS/README.txt. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +static unsigned long cpj; + +static cycle_t hpt_read(void) +{ + return read_c0_count2(); +} + +static struct clocksource pnx_clocksource = { + .name = "pnx8xxx", + .rating = 200, + .read = hpt_read, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *c = dev_id; + + /* clear MATCH, signal the event */ + c->event_handler(c); + + return IRQ_HANDLED; +} + +static struct irqaction pnx8xxx_timer_irq = { + .handler = pnx8xxx_timer_interrupt, + .flags = IRQF_DISABLED | IRQF_PERCPU, + .name = "pnx8xxx_timer", +}; + +static irqreturn_t monotonic_interrupt(int irq, void *dev_id) +{ + /* Timer 2 clear interrupt */ + write_c0_compare2(-1); + return IRQ_HANDLED; +} + +static struct irqaction monotonic_irqaction = { + .handler = monotonic_interrupt, + .flags = IRQF_DISABLED, + .name = "Monotonic timer", +}; + +static int pnx8xxx_set_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + write_c0_compare(delta); + return 0; +} + +static struct clock_event_device pnx8xxx_clockevent = { + .name = "pnx8xxx_clockevent", + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = pnx8xxx_set_next_event, +}; + +static inline void timer_ack(void) +{ + write_c0_compare(cpj); +} + +__init void plat_time_init(void) +{ + unsigned int configPR; + unsigned int n; + unsigned int m; + unsigned int p; + unsigned int pow2p; + + clockevents_register_device(&pnx8xxx_clockevent); + clocksource_register(&pnx_clocksource); + + /* Timer 1 start */ + configPR = read_c0_config7(); + configPR &= ~0x00000008; + write_c0_config7(configPR); + + /* Timer 2 start */ + configPR = read_c0_config7(); + configPR &= ~0x00000010; + write_c0_config7(configPR); + + /* Timer 3 stop */ + configPR = read_c0_config7(); + configPR |= 0x00000020; + write_c0_config7(configPR); + + + /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */ + /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */ + + n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16; + m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8; + p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2; + pow2p = (1 << p); + + db_assert(m != 0 && pow2p != 0); + + /* + * Compute the frequency as in the PNX8550 User Manual 1.0, p.186 + * (a.k.a. 8-10). Divide by HZ for a timer offset that results in + * HZ timer interrupts per second. + */ + mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p)); + cpj = (mips_hpt_frequency + HZ / 2) / HZ; + write_c0_count(0); + timer_ack(); + + /* Setup Timer 2 */ + write_c0_count2(0); + write_c0_compare2(0xffffffff); + + setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); + setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); +} diff -urN linux.orig/arch/mips/nxp/pnx8550/jbs/board_setup.c linux/arch/mips/nxp/pnx8550/jbs/board_setup.c --- linux.orig/arch/mips/nxp/pnx8550/jbs/board_setup.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/jbs/board_setup.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,65 @@ +/* + * JBS Specific board startup routines. + * + * Copyright 2005, Embedded Alley Solutions, Inc + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +/* CP0 hazard avoidance. */ +#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +void __init board_setup(void) +{ + unsigned long config0, configpr; + + config0 = read_c0_config(); + + /* clear all three cache coherency fields */ + config0 &= ~(0x7 | (7<<25) | (7<<28)); + config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | + (CONF_CM_DEFAULT<<28)); + write_c0_config(config0); + BARRIER; + + configpr = read_c0_config7(); + configpr |= (1<<19); /* enable tlb */ + write_c0_config7(configpr); + BARRIER; +} diff -urN linux.orig/arch/mips/nxp/pnx8550/jbs/init.c linux/arch/mips/nxp/pnx8550/jbs/init.c --- linux.orig/arch/mips/nxp/pnx8550/jbs/init.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/jbs/init.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,53 @@ +/* + * + * Copyright 2005 Embedded Alley Solutions, Inc + * source@embeddedalley.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "NXP PNX8550/JBS"; +} + +void __init prom_init(void) +{ + unsigned long memsize; + + //memsize = 0x02800000; /* Trimedia uses memory above */ + memsize = 0x08000000; /* Trimedia uses memory above */ + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff -urN linux.orig/arch/mips/nxp/pnx8550/jbs/irqmap.c linux/arch/mips/nxp/pnx8550/jbs/irqmap.c --- linux.orig/arch/mips/nxp/pnx8550/jbs/irqmap.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/jbs/irqmap.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,36 @@ +/* + * NXP JBS board irqmap. + * + * Copyright 2005 Embedded Alley Solutions, Inc + * source@embeddealley.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +char pnx8550_irq_tab[][5] __initdata = { + [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, +}; + diff -urN linux.orig/arch/mips/nxp/pnx8550/jbs/Makefile linux/arch/mips/nxp/pnx8550/jbs/Makefile --- linux.orig/arch/mips/nxp/pnx8550/jbs/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/jbs/Makefile 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,4 @@ + +# Makefile for the NXP JBS Board. + +lib-y := init.o board_setup.o irqmap.o diff -urN linux.orig/arch/mips/nxp/pnx8550/stb810/board_setup.c linux/arch/mips/nxp/pnx8550/stb810/board_setup.c --- linux.orig/arch/mips/nxp/pnx8550/stb810/board_setup.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/stb810/board_setup.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,49 @@ +/* + * STB810 specific board startup routines. + * + * Based on the arch/mips/nxp/pnx8550/jbs/board_setup.c + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +void __init board_setup(void) +{ + unsigned long config0, configpr; + + config0 = read_c0_config(); + + /* clear all three cache coherency fields */ + config0 &= ~(0x7 | (7<<25) | (7<<28)); + config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | + (CONF_CM_DEFAULT<<28)); + write_c0_config(config0); + + configpr = read_c0_config7(); + configpr |= (1<<19); /* enable tlb */ + write_c0_config7(configpr); +} diff -urN linux.orig/arch/mips/nxp/pnx8550/stb810/irqmap.c linux/arch/mips/nxp/pnx8550/stb810/irqmap.c --- linux.orig/arch/mips/nxp/pnx8550/stb810/irqmap.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/stb810/irqmap.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,23 @@ +/* + * NXP STB810 board irqmap. + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +char pnx8550_irq_tab[][5] __initdata = { + [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [10] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, +}; + diff -urN linux.orig/arch/mips/nxp/pnx8550/stb810/Makefile linux/arch/mips/nxp/pnx8550/stb810/Makefile --- linux.orig/arch/mips/nxp/pnx8550/stb810/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/stb810/Makefile 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,4 @@ + +# Makefile for the NXP STB810 Board. + +lib-y := prom_init.o board_setup.o irqmap.o diff -urN linux.orig/arch/mips/nxp/pnx8550/stb810/prom_init.c linux/arch/mips/nxp/pnx8550/stb810/prom_init.c --- linux.orig/arch/mips/nxp/pnx8550/stb810/prom_init.c 1970-01-01 01:00:00.000000000 +0100 +++ linux/arch/mips/nxp/pnx8550/stb810/prom_init.c 2008-03-04 11:13:18.000000000 +0000 @@ -0,0 +1,46 @@ +/* + * STB810 specific prom routines + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "NXP PNX8950/STB810"; +} + +void __init prom_init(void) +{ + unsigned long memsize; + + prom_argc = (int) fw_arg0; + prom_argv = (char **) fw_arg1; + prom_envp = (char **) fw_arg2; + + prom_init_cmdline(); + + memsize = 0x08000000; /* Trimedia uses memory above */ + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff -urN linux.orig/arch/mips/philips/pnx8550/common/gdb_hook.c linux/arch/mips/philips/pnx8550/common/gdb_hook.c --- linux.orig/arch/mips/philips/pnx8550/common/gdb_hook.c 2008-03-04 11:08:00.000000000 +0000 +++ linux/arch/mips/philips/pnx8550/common/gdb_hook.c 1970-01-01 01:00:00.000000000 +0100 @@ -1,109 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * This is the interface to the remote debugger stub. - * - */ -#include -#include -#include -#include -#include - -#include -#include - -#include - -static struct serial_state rs_table[IP3106_NR_PORTS] = { -}; -static struct async_struct kdb_port_info = {0}; - -void rs_kgdb_hook(int tty_no) -{ - struct serial_state *ser = &rs_table[tty_no]; - - kdb_port_info.state = ser; - kdb_port_info.magic = SERIAL_MAGIC; - kdb_port_info.port = tty_no; - kdb_port_info.flags = ser->flags; - - /* - * Clear all interrupts - */ - /* Clear all the transmitter FIFO counters (pointer and status) */ - ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST; - /* Clear all the receiver FIFO counters (pointer and status) */ - ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST; - /* Clear all interrupts */ - ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX | - IP3106_UART_INT_ALLTX; - - /* - * Now, initialize the UART - */ - ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT; - ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud -} - -int putDebugChar(char c) -{ - /* Wait until FIFO not full */ - while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16) - ; - /* Send one char */ - ip3106_fifo(UART_BASE, kdb_port_info.port) = c; - - return 1; -} - -char getDebugChar(void) -{ - char ch; - - /* Wait until there is a char in the FIFO */ - while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) & - IP3106_UART_FIFO_RXFIFO) >> 8)) - ; - /* Read one char */ - ch = ip3106_fifo(UART_BASE, kdb_port_info.port) & - IP3106_UART_FIFO_RBRTHR; - /* Advance the RX FIFO read pointer */ - ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT; - return (ch); -} - -void rs_disable_debug_interrupts(void) -{ - ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */ -} - -void rs_enable_debug_interrupts(void) -{ - /* Clear all the transmitter FIFO counters (pointer and status) */ - ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST; - /* Clear all the receiver FIFO counters (pointer and status) */ - ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST; - /* Clear all interrupts */ - ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX | - IP3106_UART_INT_ALLTX; - ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */ -} diff -urN linux.orig/arch/mip