From alex@alexlab.net Thu Nov  1 01:46:13 2007
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Date:	Thu, 1 Nov 2007 10:46:01 +0900
From:	"Hyon Lim" <alex@alexlab.net>
To:	"Andrew Dyer" <adyer@righthandtech.com>
Subject: Re: implementation of software suspend on MIPS. (system log)
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To:	Hyon Lim <alex@alexlab.net>
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Subject: Re: implementation of software suspend on MIPS. (system log)
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On Thu, 1 Nov 2007, Hyon Lim wrote:

> Yes. you're right. I did same as you said.
> However, is there any options for disassembly with variable name?
> Often I cannot find that variable's allocated register.
> There is only r0,r1... but I want a comment for variable assignment 
> status.

I just have to ask the question, but is it really necessary to code the 
whole thing in assembly?  I understand that the interface probably does 
need to be, but the main body of the function?  If it's very large or 
complicated, it would seem simpler to use C and write assembly glue to 
pull it all together rather than trying to debug hand assembly.  Many of 
us here have spent hours before tracking down problems with stale data in 
branch delay slots.  The compiler is a tad more convienient.

Regards,

-S-


From alex@alexlab.net Thu Nov  1 09:12:09 2007
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From tsbogend@alpha.franken.de Thu Nov  1 10:39:54 2007
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To:	linux-mips@linux-mips.org
Cc:	ralf@linux-mips.org
Subject: [PATCH] SNI: register a02r clockevent; don't use PIT timer
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Register A20R clockevent
Remove PIT timer setup because it doesn't work 

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---

diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 60bc62e..6f339af 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -1,6 +1,7 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/time.h>
+#include <linux/clockchips.h>
 
 #include <asm/i8253.h>
 #include <asm/sni.h>
@@ -80,7 +81,7 @@ static void __init sni_a20r_timer_setup(void)
 	unsigned int cpu = smp_processor_id();
 
 	cd->cpumask             = cpumask_of_cpu(cpu);
-
+	clockevents_register_device(cd);
 	action->dev_id = cd;
 	setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction);
 }
@@ -169,8 +170,6 @@ void __init plat_time_init(void)
 
 	mips_hpt_frequency = r4k_tick * HZ;
 
-	setup_pit_timer();
-
 	switch (sni_brd_type) {
 	case SNI_BRD_10:
 	case SNI_BRD_10NEW:


-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

From yoichi_yuasa@tripeaks.co.jp Thu Nov  1 12:30:46 2007
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To:	Ralf Baechle <ralf@linux-mips.org>
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Subject: [PATCH][MIPS] bcm47xx: remove unneeded clear_c0_status()
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Remove unneeded clear_c0_status().
irq_cpu routines take care of it.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>

diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/bcm47xx/irq.c mips/arch/mips/bcm47xx/irq.c
--- mips-orig/arch/mips/bcm47xx/irq.c	2007-10-26 23:35:58.630600250 +0900
+++ mips/arch/mips/bcm47xx/irq.c	2007-10-26 23:40:22.587096500 +0900
@@ -33,8 +33,6 @@ void plat_irq_dispatch(void)
 
 	cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
 
-	clear_c0_status(cause);
-
 	if (cause & CAUSEF_IP7)
 		do_IRQ(7);
 	if (cause & CAUSEF_IP2)

From yoichi_yuasa@tripeaks.co.jp Thu Nov  1 12:35:47 2007
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Subject: [PATCH][MIPS] clean up au1xxx_irqmap.c include files
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Clean up au1xxx_irqmap.c include files.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>

diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/au1000/common/au1xxx_irqmap.c mips/arch/mips/au1000/common/au1xxx_irqmap.c
--- mips-orig/arch/mips/au1000/common/au1xxx_irqmap.c	2007-10-26 23:35:58.350582750 +0900
+++ mips/arch/mips/au1000/common/au1xxx_irqmap.c	2007-10-26 23:54:59.221882750 +0900
@@ -25,27 +25,10 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
-#include <linux/errno.h>
 #include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/delay.h>
-#include <linux/bitops.h>
-
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/mipsregs.h>
-#include <asm/system.h>
-#include <asm/mach-au1x00/au1000.h>
+#include <linux/kernel.h>
+
+#include <au1000.h>
 
 /* The IC0 interrupt table.  This is processor, rather than
  * board dependent, so no reason to keep this info in the board

From alex@alexlab.net Thu Nov  1 12:36:58 2007
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From tsbogend@alpha.franken.de Thu Nov  1 12:52:35 2007
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To:	linux-mips@linux-mips.org
Cc:	ralf@linux-mips.org
Subject: [PATCH] JAZZ: disable PIT; cleanup R4030 clockevent
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PIT doesn't work, disable it completly
make r4030 clockevent code look like other mips clockevent code

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 97da953..c4f7e60 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -119,7 +119,6 @@ config MACH_JAZZ
 	select CEVT_R4K
 	select GENERIC_ISA_DMA
 	select IRQ_CPU
-	select I8253
 	select I8259
 	select ISA
 	select PCSPEAKER
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 1dac9e1..a629719 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -118,16 +118,16 @@ static void r4030_set_mode(enum clock_event_mode mode,
 struct clock_event_device r4030_clockevent = {
 	.name		= "r4030",
 	.features	= CLOCK_EVT_FEAT_PERIODIC,
-	.rating		= 100,
+	.rating		= 300,
 	.irq		= JAZZ_TIMER_IRQ,
-	.cpumask	= CPU_MASK_CPU0,
 	.set_mode	= r4030_set_mode,
 };
 
 static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
 {
-	r4030_clockevent.event_handler(&r4030_clockevent);
+	struct clock_event_device *cd = dev_id;
 
+	cd->event_handler(cd);
 	return IRQ_HANDLED;
 }
 
@@ -135,15 +135,22 @@ static struct irqaction r4030_timer_irqaction = {
 	.handler	= r4030_timer_interrupt,
 	.flags		= IRQF_DISABLED,
 	.mask		= CPU_MASK_CPU0,
-	.name		= "timer",
+	.name		= "R4030 timer",
 };
 
 void __init plat_time_init(void)
 {
-	struct irqaction *irq = &r4030_timer_irqaction;
+	struct clock_event_device *cd = &r4030_clockevent;
+	struct irqaction *action = &r4030_timer_irqaction;
+	unsigned int cpu = smp_processor_id();
 
 	BUG_ON(HZ != 100);
 
+	cd->cpumask             = cpumask_of_cpu(cpu);
+	clockevents_register_device(cd);
+	action->dev_id = cd;
+	setup_irq(JAZZ_TIMER_IRQ, action);
+
 	/*
 	 * Set clock to 100Hz.
 	 *
@@ -151,8 +158,4 @@ void __init plat_time_init(void)
 	 * a programmable 4-bit divider.  This makes it fairly inflexible.
 	 */
 	r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
-	setup_irq(JAZZ_TIMER_IRQ, irq);
-
-	clockevents_register_device(&r4030_clockevent);
-	setup_pit_timer();
 }



-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

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Date:	Thu, 1 Nov 2007 21:51:23 +0900
From:	Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
To:	Ralf Baechle <ralf@linux-mips.org>
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Subject: [PATCH][MIPS] fix Cobalt IRQ comment
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Fixed Cobalt IRQ comment.
Cobalt kernel uses CP0 counter now.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>

diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/mach-cobalt/irq.h mips/include/asm-mips/mach-cobalt/irq.h
--- mips-orig/include/asm-mips/mach-cobalt/irq.h	2007-10-27 17:13:58.239256750 +0900
+++ mips/include/asm-mips/mach-cobalt/irq.h	2007-10-27 17:17:45.905485000 +0900
@@ -35,7 +35,7 @@
  *	4 - ethernet
  *	5 - 16550 UART
  *	6 - cascade i8259
- *	7 - CP0 counter (unused)
+ *	7 - CP0 counter
  */
 #define MIPS_CPU_IRQ_BASE		16
 
@@ -48,7 +48,6 @@
 #define SCSI_IRQ			(MIPS_CPU_IRQ_BASE + 5)
 #define I8259_CASCADE_IRQ		(MIPS_CPU_IRQ_BASE + 6)
 
-
 #define GT641XX_IRQ_BASE		24
 
 #include <asm/irq_gt641xx.h>

From ralf@linux-mips.org Thu Nov  1 13:04:16 2007
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On Thu, Nov 01, 2007 at 09:30:36PM +0900, Yoichi Yuasa wrote:

> Remove unneeded clear_c0_status().
> irq_cpu routines take care of it.

Actually this write is plain nonsense; it has no effect.  The only time
acknowledging an interrupt in c0_cause is needed is for the two software
interrupts but the only user of these is SMTC.

  Ralf

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On Thu, Nov 01, 2007 at 09:35:39PM +0900, Yoichi Yuasa wrote:

> Clean up au1xxx_irqmap.c include files.

Thanks, queued up for 2.6.25.

  Ralf

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On Thu, Nov 01, 2007 at 09:51:23PM +0900, Yoichi Yuasa wrote:

> Fixed Cobalt IRQ comment.
> Cobalt kernel uses CP0 counter now.

Thanks, applied.

  Ralf

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On Thu, 1 Nov 2007, Hyon Lim wrote:

> I think the reason of assembly implementation is processor context
> replacement.

Understood.  Assembly may indeed be required for specific things like 
restoring register state or fiddling with the cache if there aren't 
already macros or functions in the kernel that do exactly what you need.

> The second reason that I thinking is calling convention of C language.

It's not uncommon at all to have assembly language glue, say between a 
BIOS callback and the C language routine that does the work.

In your original post, you mentioned tracking variables and things that 
suggested a module that does much more that just load some odd registers 
or flip around a function call stack.  If that is indeed the case, then 
for sake of maintainablility and readability, one would be strongly 
encouraged to write the core stuff in plain old C and sprinkle in assembly 
glue code as required.

Think about it this way.  MIPS is a pretty large family of CPUs, each with 
it's own strange behaviors.  Several of those people on this list spend a 
lot of time tweeking that assembly to make it work cleanly across various 
CPUs.  It's a lot easier to understand 25 lines of assembly interface code 
and 200 lines of C code, than an entire 1000 line module written in 
assembly.  It's also a lot easier when you can shove most of the work over 
to the compiler, especially if others like your work and want to 
generalize it for use on many other MIPS CPUs.

I guess the real question here is how complex do you think your code needs 
to be?  That should determine your path.

Regards,

-S-

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Hyon Lim wrote:
> I investigated kernel assembly source code in my kernel (2.6.10).
> I found that there are a lot of assembly directives (e.g., .align, .set
> reorder, .cpload, .frame etc.).
> Is there any documents which explains those directives? (not only I
> described above. All of directives)

Short of reading the assembler sourcecode I believe the best document
is "See MIPS Run Linux".


Thiemo

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From jscottkasten@yahoo.com Thu Nov  1 15:00:36 2007
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From:	"J. Scott Kasten" <jscottkasten@yahoo.com>
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To:	Hyon Lim <alex@alexlab.net>
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Subject: Re: implementation of software suspend on MIPS. (system log)
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On Thu, 1 Nov 2007, Hyon Lim wrote:

> Thank you for comments.
> The remain work of my software suspend on MIPS project is resume procedure.
> I already confirmed that suspend function was work. (See my post which
> contains system log).
>
> In an i386 implementation, there are only few assembly code for suspend and
> resume procedure.
> (You can refer :
> http://lxr.linux.no/source/arch/i386/power/swsusp.S?v=2.6.10)
> So, my work will be similar with i386 implementation. Assembly code used in
> i386 implementation are several processor context related job
> and copy saved page to memory. Instruction used in my MIPS implementation
> will be compatible to most of MIPS processor.
> Because the instruction used in implementation is very basic (store and load
> and branch).
>
> I agree your opinion related to maintainability and readability. So I
> implement my work with C and few assembly code.
> Thank you for advice.
>

I look forward to your eventual success. :)



From ralf@linux-mips.org Thu Nov  1 15:08:03 2007
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From:	Ralf Baechle <ralf@linux-mips.org>
To:	Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc:	linux-mips@linux-mips.org
Subject: Re: [PATCH] JAZZ: disable PIT; cleanup R4030 clockevent
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On Thu, Nov 01, 2007 at 01:52:36PM +0100, Thomas Bogendoerfer wrote:

> PIT doesn't work, disable it completly

I think this is the explanation:

include/asm-mips/mach-jazz/timex.h:#define CLOCK_TICK_RATE              100

while the PIT code actually expects 1193182.

Turns out that due to a recent Qemu bug which made the probe for the cp0
compare interrupt fail the Malta code did fall back from the compare timer
to the i8253 PIT for the clockevent device.  Works perfectly well.

  Ralf

From ralf@linux-mips.org Thu Nov  1 15:50:28 2007
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From:	Ralf Baechle <ralf@linux-mips.org>
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Subject: Re: [PATCH] SNI: register a02r clockevent; don't use PIT timer
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On Thu, Nov 01, 2007 at 11:36:42AM +0100, Thomas Bogendoerfer wrote:

> Register A20R clockevent
> Remove PIT timer setup because it doesn't work 
> 
> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

Applied.

  Ralf

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From:	Ralf Baechle <ralf@linux-mips.org>
To:	Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Subject: Re: [PATCH] JAZZ: disable PIT; cleanup R4030 clockevent
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On Thu, Nov 01, 2007 at 03:07:41PM +0000, Ralf Baechle wrote:

> On Thu, Nov 01, 2007 at 01:52:36PM +0100, Thomas Bogendoerfer wrote:
> 
> > PIT doesn't work, disable it completly
> 
> I think this is the explanation:
> 
> include/asm-mips/mach-jazz/timex.h:#define CLOCK_TICK_RATE              100
> 
> while the PIT code actually expects 1193182.
> 
> Turns out that due to a recent Qemu bug which made the probe for the cp0
> compare interrupt fail the Malta code did fall back from the compare timer
> to the i8253 PIT for the clockevent device.  Works perfectly well.

So I just fixed the MIPS part of the CLOCK_TICK_RATE mess which is really
all over the kernel.  I hope this should bring the i2853 to life for you.
Could you test this?  It's pretty much the only hope for Jazz to go tickless
so we should try to get it to work.  Unfortunately there is a locking issue
lurking there as well so I need some feedback if you can get it to work.

  Ralf

From Eckhardt@satorlaser.com Thu Nov  1 16:07:21 2007
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From:	Ulrich Eckhardt <eckhardt@satorlaser.com>
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To:	linux-mips <linux-mips@linux-mips.org>
Subject: Re: [PATCH] Put cast inside macro instead of all the callers
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I'm by far not a MIPS expert, but I'm puzzled by the code and how it uses 
signed integers for addresses. I just added some comments below, but I'm not 
sure if they are valid. Thank you for any clarification!

On Wednesday 31 October 2007, Andrew Sharp wrote:
> Since all the callers of the PHYS_TO_XKPHYS macro call with a constant,
> put the cast to LL inside the macro where it really should be rather
> than in all the callers.  This makes macros like PHYS_TO_XKSEG_UNCACHED
> work without gcc whining.

I'm not sure if this is always a compile-time constant so that you can adorn 
it with a LL. However, note that this is not a cast, a cast is at runtime.

>  	if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
>  		usp = CKSEG1ADDR(sp);
>  #ifdef CONFIG_64BIT
> -	else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0LL, 0) &&
> -		 (long long)sp < (long long)PHYS_TO_XKPHYS(8LL, 0))
> -		usp = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED,
> +	else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0, 0) &&
> +		 (long long)sp < (long long)PHYS_TO_XKPHYS(8, 0))
> +		usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
>  				     XKPHYS_TO_PHYS((long long)sp));

I'd say this code is broken in way too many aspects:
1. A plethora of casts. PHYS_TO_XKPHYS() should return a physical address 
(i.e. 32 or 64 bits unsigned integer) already, so casting its result should 
not be necessary.
2. Using a signed integer of undefined size for an address. At least use an 
explicit 64 bit unsigned integer (__u64).
3. The use of signed types makes me wonder about intended overflow semantics. 
Just for the record, signed overflow in C causes undefined behaviour, no 
diagnostic required, and recent GCC even assume that no overflow occurs as an 
optimisation!

>  #define PHYS_TO_XKSEG_CACHED(p)		PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
>  #define XKPHYS_TO_PHYS(p)		((p) & TO_PHYS_MASK)
>  #define PHYS_TO_XKPHYS(cm,a)		(_CONST64_(0x8000000000000000) | \
> -					 ((cm)<<59) | (a))
> +					 (_CONST64_(cm)<<59) | (a))

This macro will always(!!!) generate a negative number, is that intended?

Uli
- slightly puzzled -

-- 
Sator Laser GmbH
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From markus.gothe@27m.se Thu Nov  1 16:46:07 2007
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-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256

Thiemo Seufer wrote:
> Hyon Lim wrote:
>> I investigated kernel assembly source code in my kernel (2.6.10).
>>  I found that there are a lot of assembly directives (e.g.,
>> .align, .set reorder, .cpload, .frame etc.). Is there any
>> documents which explains those directives? (not only I described
>> above. All of directives)
>
> Short of reading the assembler sourcecode I believe the best
> document is "See MIPS Run Linux".
>
>
> Thiemo
>
Use the source Luke (or Google)... I think if you'vent got a clue
about assembler (or anything else you're doing) you need to do some
research before asking, that's my not so humble opinion.

- --
_______________________________________

Mr Markus Gothe
Software Engineer

Phone: +46 (0)13 21 81 20 (ext. 1046)
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From ralf@linux-mips.org Thu Nov  1 17:17:04 2007
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Subject: Re: [PATCH] Put cast inside macro instead of all the callers
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On Wed, Oct 31, 2007 at 02:11:24PM -0700, Andrew Sharp wrote:

> Resend: I tried sending this a couple of days ago but haven't seen it.
> Wondering if it got stuck in a spam filter or our lovely exchange
> server or something.

It seems the list's spam filter has developed some appetite for patches,
I'm afraid.  Generally please cc me on patches.

> Since all the callers of the PHYS_TO_XKPHYS macro call with a constant,
> put the cast to LL inside the macro where it really should be rather
> than in all the callers.  This makes macros like PHYS_TO_XKSEG_UNCACHED
> work without gcc whining.
> 
> Hopefully this will apply ok.

I'm afraid, no, the definition of PHYS_TO_XKPHYS did change 3 weeks ago ...

Anyway, I fixed that up and queued it for 2.6.25.

Thanks,

  Ralf

From andy.sharp@onstor.com Thu Nov  1 17:23:28 2007
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Subject: Re: [PATCH] Put cast inside macro instead of all the callers
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On Thu, 1 Nov 2007 17:04:01 +0100 Ulrich Eckhardt
<eckhardt@satorlaser.com> wrote:

> I'm by far not a MIPS expert, but I'm puzzled by the code and how it
> uses signed integers for addresses. I just added some comments below,
> but I'm not sure if they are valid. Thank you for any clarification!
> 
> On Wednesday 31 October 2007, Andrew Sharp wrote:
> > Since all the callers of the PHYS_TO_XKPHYS macro call with a
> > constant, put the cast to LL inside the macro where it really
> > should be rather than in all the callers.  This makes macros like
> > PHYS_TO_XKSEG_UNCACHED work without gcc whining.
> 
> I'm not sure if this is always a compile-time constant so that you
> can adorn it with a LL. However, note that this is not a cast, a cast
> is at runtime.

It is always a constant.

> >  	if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
> >  		usp = CKSEG1ADDR(sp);
> >  #ifdef CONFIG_64BIT
> > -	else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0LL,
> > 0) &&
> > -		 (long long)sp < (long long)PHYS_TO_XKPHYS(8LL, 0))
> > -		usp = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED,
> > +	else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0, 0)
> > &&
> > +		 (long long)sp < (long long)PHYS_TO_XKPHYS(8, 0))
> > +		usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
> >  				     XKPHYS_TO_PHYS((long
> > long)sp));
> 
> I'd say this code is broken in way too many aspects:
> 1. A plethora of casts. PHYS_TO_XKPHYS() should return a physical
> address (i.e. 32 or 64 bits unsigned integer) already, so casting its
> result should not be necessary.
> 2. Using a signed integer of undefined size for an address. At least
> use an explicit 64 bit unsigned integer (__u64).
> 3. The use of signed types makes me wonder about intended overflow
> semantics. Just for the record, signed overflow in C causes undefined
> behaviour, no diagnostic required, and recent GCC even assume that no
> overflow occurs as an optimisation!
> 
> >  #define PHYS_TO_XKSEG_CACHED(p)
> > PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) #define
> > XKPHYS_TO_PHYS(p)		((p) & TO_PHYS_MASK) #define
> > PHYS_TO_XKPHYS(cm,a)		(_CONST64_(0x8000000000000000)
> > | \
> > -					 ((cm)<<59) | (a))
> > +					 (_CONST64_(cm)<<59) | (a))
> 
> This macro will always(!!!) generate a negative number, is that
> intended?

Well, it's an address, not a number.  Does that help?  The point of the
macro is to convert physical addresses to a selectable type of virtual
address, of which mips has several.

Cheers,

a


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On Thu, Nov 01, 2007 at 05:04:01PM +0100, Ulrich Eckhardt wrote:

> I'm by far not a MIPS expert, but I'm puzzled by the code and how it uses 
> signed integers for addresses. I just added some comments below, but I'm not 
> sure if they are valid. Thank you for any clarification!

When going from 32-bit to 64-bit MIPS did sign-extend register values and
addresses, that is for example 0x80000000 became 0xffffffff80000000.  That
is the code sequence which on 32-bit is used to load the first address
actually happens to load the 2nd value on a 64-bit machine.  Which is an
extremly elegant solution on the hardware level but at a few places
software need to know.  The code tries to make clever use of sign extension
by the compiler to avoid multiple constants.

> On Wednesday 31 October 2007, Andrew Sharp wrote:
> > Since all the callers of the PHYS_TO_XKPHYS macro call with a constant,
> > put the cast to LL inside the macro where it really should be rather
> > than in all the callers.  This makes macros like PHYS_TO_XKSEG_UNCACHED
> > work without gcc whining.
> 
> I'm not sure if this is always a compile-time constant so that you can adorn 
> it with a LL. However, note that this is not a cast, a cast is at runtime.

No.  The compiler can evaluate the cast of a constant value at compile
time and that exactly is what the code is exploiting here.

> >  	if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
> >  		usp = CKSEG1ADDR(sp);
> >  #ifdef CONFIG_64BIT
> > -	else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0LL, 0) &&
> > -		 (long long)sp < (long long)PHYS_TO_XKPHYS(8LL, 0))
> > -		usp = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED,
> > +	else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0, 0) &&
> > +		 (long long)sp < (long long)PHYS_TO_XKPHYS(8, 0))
> > +		usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
> >  				     XKPHYS_TO_PHYS((long long)sp));
> 
> I'd say this code is broken in way too many aspects:
> 1. A plethora of casts. PHYS_TO_XKPHYS() should return a physical address 
> (i.e. 32 or 64 bits unsigned integer) already, so casting its result should 
> not be necessary.

No argument about the beauty of the whole thing.

> 2. Using a signed integer of undefined size for an address. At least use an 
> explicit 64 bit unsigned integer (__u64).

long long is 64-bit on Linux.

> 3. The use of signed types makes me wonder about intended overflow semantics. 
> Just for the record, signed overflow in C causes undefined behaviour, no 
> diagnostic required, and recent GCC even assume that no overflow occurs as an 
> optimisation!

There is no overflow possible here.

> >  #define PHYS_TO_XKSEG_CACHED(p)		PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
> >  #define XKPHYS_TO_PHYS(p)		((p) & TO_PHYS_MASK)
> >  #define PHYS_TO_XKPHYS(cm,a)		(_CONST64_(0x8000000000000000) | \
> > -					 ((cm)<<59) | (a))
> > +					 (_CONST64_(cm)<<59) | (a))
> 
> This macro will always(!!!) generate a negative number, is that intended?

Sort of.  Most users don't care, the address is just an address for them.
Note that the Linux idea of "all virtual addresses can be represented in
an unsigned long" and the MIPS concept of sign extending addresses conflict
at times, so sometimes addresses want to be handled with alot of care.

  Ralf

From vda.linux@googlemail.com Thu Nov  1 18:43:36 2007
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From:	Denys Vlasenko <vda.linux@googlemail.com>
To:	Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [IDE] Fix build bug
Date:	Thu, 1 Nov 2007 18:43:16 +0000
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	Andrew Morton <akpm@linux-foundation.org>,
	linux-kernel@vger.kernel.org, linux-ide@vger.kernel.org,
	linux-mips@linux-mips.org,
	Martijn Uffing <mp3project@sarijopen.student.utwente.nl>
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On Tuesday 30 October 2007 12:41, Ralf Baechle wrote:
> On Tue, Oct 30, 2007 at 11:34:29AM +0000, Denys Vlasenko wrote:
> 
> > On Thursday 25 October 2007 22:41, Bartlomiej Zolnierkiewicz wrote:
> > > > -static const struct ide_port_info generic_chipsets[] __devinitdata = {
> > > > +static struct ide_port_info generic_chipsets[] __devinitdata = {
> > > >  	/*  0 */ DECLARE_GENERIC_PCI_DEV("Unknown",	0),
> > > >  
> > > >  	{	/* 1 */
> > > 
> > > I would prefer to not remove const from generic_chipsets[] so:
> > > 
> > > [PATCH] drivers/ide/pci/generic: fix build for CONFIG_HOTPLUG=n
> > > 
> > > It turns out that const and __{dev}initdata cannot be mixed currently
> > > and that generic IDE PCI host driver is also affected by the same issue:
> > > 
> > > On Thursday 25 October 2007, Ralf Baechle wrote:
> > > >   CC      drivers/ide/pci/generic.o
> > > > drivers/ide/pci/generic.c:52: error: __setup_str_ide_generic_all_on causes a
> > > > +section type conflict
> > > 
> > > [ Also reported by Martijn Uffing <mp3project@sarijopen.student.utwente.nl>. ]
> > > 
> > > This patch workarounds the problem in a bit hackish way but without
> > > removing const from generic_chipsets[] (it adds const to __setup() so
> > > __setup_str_ide_generic_all becomes const).
> > 
> > You wouldn't believe how much const data is not marked as const because
> > we don't have __constinitdata etc. Literally megabytes.
> 
> The gain from marking it const is very little and once any non-const
> __initdata object is added to a compilation unit all other const declarations
> will have to be removed.  Bad tradeoff.

We can intrduce new, ro sections or teach gcc that combining const objects into
non-ro sections is not a crime. I wonder why it currently disallows that.
(And it does it only _somethimes_, const pointers happily go into rw sections!)
--
vda

From veerasena_b@yahoo.co.in Fri Nov  2 05:05:13 2007
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Date:	Fri, 2 Nov 2007 10:33:49 +0530 (IST)
From:	veerasena reddy <veerasena_b@yahoo.co.in>
Subject: NPTL support
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Hi,

I am trying to build the toolchain for MIPS processor using buildroot.
I am using gcc version of 3.4.3, binutils-2.15, uclibc-0.9.28 and linux-2.6.18.8 kernel.

Basically i need to enable NPTL feature support in my toolchain.
does uclibc-0.9.28 has the support for NPTL?
If not, how can i get it enabled for my above build configuration?

I see there is separate branch "uclibc-nptl" in uclibc. 
Do i need to use this (uclibc-nptl) to meet my requirement?

Could you please suggest me right approach to succssfully enable NPTL?

Thanks in advance.

Regards,
Veerasena.


      Why delete messages? Unlimited storage is just a click away. Go to http://help.yahoo.com/l/in/yahoo/mail/yahoomail/tools/tools-08.html


From kalyanatejaswi@gmail.com Fri Nov  2 05:46:05 2007
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Date:	Fri, 2 Nov 2007 11:15:51 +0530
From:	"kalyan tejaswi" <kalyanatejaswi@gmail.com>
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Subject: Oops with kernel 2.6.8
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Hi all,
I am using Malta-4Kc with kernel 2.6.8(from linux-mips.org) compiled with
gcc 3.4.4.

I can not boot over NFS.

The console log is attached.

Any hints are greatly appreciated.


Regards
Kalyan

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<div>Hi all,</div>
<div>I am using Malta-4Kc with&nbsp;kernel 2.6.8(from <a href="http://linux-mips.org">linux-mips.org</a>) compiled with gcc 3.4.4.</div>
<div>&nbsp;</div>
<div>I can not boot over NFS.</div>
<div>&nbsp;</div>
<div>The console log is attached.</div>
<div>&nbsp;</div>
<div>Any hints are greatly appreciated.</div>
<div>&nbsp;</div>
<div>&nbsp;</div>
<div>Regards</div>
<div>Kalyan</div>

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------=_Part_14509_19194610.1193982351721--

From Eckhardt@satorlaser.com Fri Nov  2 08:07:31 2007
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From:	Ulrich Eckhardt <eckhardt@satorlaser.com>
Organization: Sator Laser GmbH
To:	linux-mips <linux-mips@linux-mips.org>
Subject: Re: [PATCH] Put cast inside macro instead of all the callers
Date:	Fri, 2 Nov 2007 09:06:00 +0100
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On Thursday 01 November 2007, Ulrich Eckhardt wrote:
[...]
> - slightly puzzled -

Andrew, Ralf, thanks for the clarifications!

Uli

-- 
Sator Laser GmbH
Geschäftsführer: Michael Wöhrmann, Amtsgericht Hamburg HR B62 932

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From tsbogend@alpha.franken.de Fri Nov  2 10:20:37 2007
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To:	Ralf Baechle <ralf@linux-mips.org>
Cc:	linux-mips@linux-mips.org
Subject: Re: [PATCH] JAZZ: disable PIT; cleanup R4030 clockevent
Message-ID: <20071102101713.GA9110@alpha.franken.de>
References: <20071101125236.GA16577@alpha.franken.de> <20071101150741.GA8570@linux-mips.org> <20071101160210.GA20366@linux-mips.org>
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From:	tsbogend@alpha.franken.de (Thomas Bogendoerfer)
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On Thu, Nov 01, 2007 at 04:02:10PM +0000, Ralf Baechle wrote:
> all over the kernel.  I hope this should bring the i2853 to life for you.

it does now, even pit clockevent works now (if you apply the patch
below).

Thomas.


Fix ISA irq acknowledge
make r4030 clockevent code look like other mips clockevent code

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---

diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index ae25b48..d7f8a78 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -97,9 +97,10 @@ asmlinkage void plat_irq_dispatch(void)
 	if (pending & IE_IRQ4) {
 		r4030_read_reg32(JAZZ_TIMER_REGISTER);
 		do_IRQ(JAZZ_TIMER_IRQ);
-	} else if (pending & IE_IRQ2)
-		do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK));
-	else if (pending & IE_IRQ1) {
+	} else if (pending & IE_IRQ2) {
+		irq = *(volatile u8 *)JAZZ_EISA_IRQ_ACK;
+		do_IRQ(irq);
+	} else if (pending & IE_IRQ1) {
 		irq = *(volatile u8 *)JAZZ_IO_IRQ_SOURCE >> 2;
 		if (likely(irq > 0))
 			do_IRQ(irq + JAZZ_IRQ_START - 1);
@@ -117,16 +118,16 @@ static void r4030_set_mode(enum clock_event_mode mode,
 struct clock_event_device r4030_clockevent = {
 	.name		= "r4030",
 	.features	= CLOCK_EVT_FEAT_PERIODIC,
-	.rating		= 100,
+	.rating		= 300,
 	.irq		= JAZZ_TIMER_IRQ,
-	.cpumask	= CPU_MASK_CPU0,
 	.set_mode	= r4030_set_mode,
 };
 
 static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
 {
-	r4030_clockevent.event_handler(&r4030_clockevent);
+	struct clock_event_device *cd = dev_id;
 
+	cd->event_handler(cd);
 	return IRQ_HANDLED;
 }
 
@@ -134,15 +135,22 @@ static struct irqaction r4030_timer_irqaction = {
 	.handler	= r4030_timer_interrupt,
 	.flags		= IRQF_DISABLED,
 	.mask		= CPU_MASK_CPU0,
-	.name		= "timer",
+	.name		= "R4030 timer",
 };
 
 void __init plat_time_init(void)
 {
-	struct irqaction *irq = &r4030_timer_irqaction;
+	struct clock_event_device *cd = &r4030_clockevent;
+	struct irqaction *action = &r4030_timer_irqaction;
+	unsigned int cpu = smp_processor_id();
 
 	BUG_ON(HZ != 100);
 
+	cd->cpumask             = cpumask_of_cpu(cpu);
+	clockevents_register_device(cd);
+	action->dev_id = cd;
+	setup_irq(JAZZ_TIMER_IRQ, action);
+
 	/*
 	 * Set clock to 100Hz.
 	 *
@@ -150,8 +158,5 @@ void __init plat_time_init(void)
 	 * a programmable 4-bit divider.  This makes it fairly inflexible.
 	 */
 	r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
-	setup_irq(JAZZ_TIMER_IRQ, irq);
-
-	clockevents_register_device(&r4030_clockevent);
 	setup_pit_timer();
 }

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

From ralf@linux-mips.org Fri Nov  2 12:20:31 2007
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Date:	Fri, 2 Nov 2007 12:20:01 +0000
From:	Ralf Baechle <ralf@linux-mips.org>
To:	Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc:	linux-mips@linux-mips.org
Subject: Re: [PATCH] JAZZ: disable PIT; cleanup R4030 clockevent
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On Fri, Nov 02, 2007 at 11:17:13AM +0100, Thomas Bogendoerfer wrote:

> On Thu, Nov 01, 2007 at 04:02:10PM +0000, Ralf Baechle wrote:
> > all over the kernel.  I hope this should bring the i2853 to life for you.
> 
> it does now, even pit clockevent works now (if you apply the patch
> below).

Applied, thanks,

One thing I'm still wondering about, does the kernel actually go tickless
for you?

  Ralf

From markus.gothe@27m.se Fri Nov  2 12:32:24 2007
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From:	Markus Gothe <markus.gothe@27m.se>
Subject: Re: NPTL support
Date:	Fri, 2 Nov 2007 13:31:41 +0100
To:	veerasena reddy <veerasena_b@yahoo.co.in>
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You'll have to use the uClibc-nptl branch on their svn. In 0.9.28, no.

//Markus

On 2 Nov 2007, at 06:03, veerasena reddy wrote:

> Hi,
>
> I am trying to build the toolchain for MIPS processor using buildroot.
> I am using gcc version of 3.4.3, binutils-2.15, uclibc-0.9.28 and =20
> linux-2.6.18.8 kernel.
>
> Basically i need to enable NPTL feature support in my toolchain.
> does uclibc-0.9.28 has the support for NPTL?
> If not, how can i get it enabled for my above build configuration?
>
> I see there is separate branch "uclibc-nptl" in uclibc.
> Do i need to use this (uclibc-nptl) to meet my requirement?
>
> Could you please suggest me right approach to succssfully enable NPTL?
>
> Thanks in advance.
>
> Regards,
> Veerasena.
>
>
>       Why delete messages? Unlimited storage is just a click away. =20
> Go to http://help.yahoo.com/l/in/yahoo/mail/yahoomail/tools/=20
> tools-08.html
>
>

_______________________________________

Mr Markus Gothe
Software Engineer

Phone: +46 (0)13 21 81 20 (ext. 1046)
Fax: +46 (0)13 21 21 15
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From ralf@linux-mips.org Fri Nov  2 12:35:05 2007
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On Thu, Nov 01, 2007 at 06:43:16PM +0000, Denys Vlasenko wrote:

> We can intrduce new, ro sections or teach gcc that combining const objects into
> non-ro sections is not a crime. I wonder why it currently disallows that.
> (And it does it only _somethimes_, const pointers happily go into rw sections!)

The pattern seems to be that const-ness of the first object placed into
a particular section determines the writability of that section.  If that
conflicts with the requirements for a later object such as a non-const
object into a section r/o gcc doesn't consider making the section r/w
but throws an error instead.

  Ralf

From ralf@linux-mips.org Fri Nov  2 12:58:23 2007
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From:	Ralf Baechle <ralf@linux-mips.org>
To:	kalyan tejaswi <kalyanatejaswi@gmail.com>
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Subject: Re: Oops with kernel 2.6.8
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On Fri, Nov 02, 2007 at 11:15:51AM +0530, kalyan tejaswi wrote:

> Hi all,
> I am using Malta-4Kc with kernel 2.6.8(from linux-mips.org) compiled with
> gcc 3.4.4.
> 
> I can not boot over NFS.
> 
> The console log is attached.
> 
> Any hints are greatly appreciated.

2.6.8 is really old, over 3 years now.  So forgive if memory of the bugs
in that kernel is fading.  I think the one you're seeing was was caused
by memory prefetching beyond the end of memory.  The easy fix is to disable
prefetching.  See a  modern memcpy for how to do that.  There are several
other interesting issues hidden in 2.6.8 so I think you really should
upgrade.

  Ralf

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On Wed, 31 Oct 2007 16:39:00 +0000, Ralf Baechle <ralf@linux-mips.org> wrote:
> > > The only safe but ugly workaround is to change the return from exception
> > > code to detect if the EPC is in the range startin from the condition
> > > check in the idle loop to including the WAIT instruction and if so to
> > > patch the EPC to resume execution at the condition check or the
> > > instruction following the WAIT.
> > 
> > I'm also thinking of this approach.  Still wondering if it is worth to
> > implement.
> 
> The tickless kernel is very interesting for the low power fraction.  And
> it's especially those users who would suffer most the loss of the ability
> to use the WAIT instruction.  For a system running from two AAA cells the
> tradeoff is clear ...  So I think it's become a must.

Then, something like this?  Selecting in build-time is not so good,
but there are some CPUs which do not need this hack at all.
Synthesizing the ret_from_irq() at runtime might satisfy everyone?

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c8c47a2..621130c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -51,12 +51,17 @@ static void r39xx_wait(void)
  * But it is implementation-dependent wheter the pipelie restarts when
  * a non-enabled interrupt is requested.
  */
+#ifdef CONFIG_ROLLBACK_CPU_WAIT
+extern void cpu_wait_rollback(void);
+#define r4k_wait cpu_wait_rollback
+#else
 static void r4k_wait(void)
 {
 	__asm__("	.set	mips3			\n"
 		"	wait				\n"
 		"	.set	mips0			\n");
 }
+#endif
 
 /*
  * This variant is preferable as it allows testing need_resched and going to
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index e29598a..ffa043c 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -27,6 +27,20 @@
 #endif
 
 	.text
+#ifdef CONFIG_ROLLBACK_CPU_WAIT
+	.align	6
+FEXPORT(cpu_wait_rollback)
+	LONG_L	t0, TI_FLAGS($28)
+	andi	t0, _TIF_NEED_RESCHED
+	bnez	t0, 1f
+	.set	mips3
+	wait
+	.set	mips0
+1:
+	jr	ra
+	.align	6
+cpu_wait_rollback_end:
+#endif
 	.align	5
 #ifndef CONFIG_PREEMPT
 FEXPORT(ret_from_exception)
@@ -35,6 +49,14 @@ FEXPORT(ret_from_exception)
 #endif
 FEXPORT(ret_from_irq)
 	LONG_S	s0, TI_REGS($28)
+#ifdef CONFIG_ROLLBACK_CPU_WAIT
+	LONG_L	t0, PT_EPC(sp)
+	ori	t0, 0x3f
+	xori	t0, 0x3f
+	PTR_LA	t1, cpu_wait_rollback
+	bne	t0, t1, __ret_from_irq
+	LONG_S	t0, PT_EPC(sp)			# return to cpu_wait_rollback
+#endif
 FEXPORT(__ret_from_irq)
 	LONG_L	t0, PT_STATUS(sp)		# returning to kernel mode?
 	andi	t0, t0, KU_USER

From alex@alexlab.net Fri Nov  2 17:26:36 2007
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