From milindchoudhary@gmail.com Sun Apr 1 13:23:21 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Apr 2007 13:23:25 +0100 (BST) Received: from ug-out-1314.google.com ([66.249.92.169]:10000 "EHLO ug-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20022092AbXDAMXV (ORCPT ); Sun, 1 Apr 2007 13:23:21 +0100 Received: by ug-out-1314.google.com with SMTP id 40so1414217uga for ; Sun, 01 Apr 2007 05:22:21 -0700 (PDT) DKIM-Signature: a=rsa-sha1; c=relaxed/relaxed; d=gmail.com; s=beta; h=domainkey-signature:received:received:date:from:to:cc:subject:message-id:mime-version:content-type:content-disposition:user-agent; b=OIsOnIc/nn72fyNsbYZyrwp/5+yFw2AZAsZF6rmT+m/YXfF/xoKeZcpryT9skF8fCFd25tanLpWtRQiwqAHUr+LvQbYDk3A/O2ctA/skdJgGSRgQfORzcnSh+sJZPkNkvreNPmu3MXmaDD7jcQXXxCpF+Lmgoa3OeEyZC1XA8h0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=beta; h=received:date:from:to:cc:subject:message-id:mime-version:content-type:content-disposition:user-agent; b=Lo6AQ98DPI0i4inUNbdJL+9qUL3g8g2VMdG5B/1xruksc59ayC8odA7DLHg+bJMtTjXAQEXXVso/6jDmDHipBBiUX4i3/iVtBu9O7ECETHvw/QCsKLNKeNHl0YwwUd4k/w+cXjXsDw/Wuie38uwaj5LbLGawyDf7w8CltsdfsMw= Received: by 10.67.95.3 with SMTP id x3mr3465960ugl.1175430141370; Sun, 01 Apr 2007 05:22:21 -0700 (PDT) Received: from localhost ( [59.95.8.28]) by mx.google.com with ESMTP id e34sm5681534ugd.2007.04.01.05.22.17; Sun, 01 Apr 2007 05:22:20 -0700 (PDT) Date: Sun, 1 Apr 2007 17:53:19 +0530 From: Milind Arun Choudhary To: kernel-janitors@lists.osdl.org Cc: linux-kernel@vger.kernel.org, akpm@linux-foundation.org, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [KJ][PATCH] ROUND_UP cleanup in arch/mips/kernel/sysirix.c Message-ID: <20070401122319.GA10178@arun.site> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14782 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: milindchoudhary@gmail.com Precedence: bulk X-list: linux-mips ROUND_UP(32|64) cleanup, use ALIGN Signed-off-by: Milind Arun Choudhary --- sysirix.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c index 93a1484..59c25bc 100644 --- a/arch/mips/kernel/sysirix.c +++ b/arch/mips/kernel/sysirix.c @@ -1736,14 +1736,13 @@ struct irix_dirent32_callback { }; #define NAME_OFFSET32(de) ((int) ((de)->d_name - (char *) (de))) -#define ROUND_UP32(x) (((x)+sizeof(u32)-1) & ~(sizeof(u32)-1)) static int irix_filldir32(void *__buf, const char *name, int namlen, loff_t offset, u64 ino, unsigned int d_type) { struct irix_dirent32 __user *dirent; struct irix_dirent32_callback *buf = __buf; - unsigned short reclen = ROUND_UP32(NAME_OFFSET32(dirent) + namlen + 1); + unsigned short reclen = ALIGN(NAME_OFFSET32(dirent) + namlen + 1, sizeof(u32)); int err = 0; u32 d_ino; @@ -1838,14 +1837,13 @@ struct irix_dirent64_callback { }; #define NAME_OFFSET64(de) ((int) ((de)->d_name - (char *) (de))) -#define ROUND_UP64(x) (((x)+sizeof(u64)-1) & ~(sizeof(u64)-1)) static int irix_filldir64(void *__buf, const char *name, int namlen, loff_t offset, u64 ino, unsigned int d_type) { struct irix_dirent64 __user *dirent; struct irix_dirent64_callback * buf = __buf; - unsigned short reclen = ROUND_UP64(NAME_OFFSET64(dirent) + namlen + 1); + unsigned short reclen = ALIGN(NAME_OFFSET64(dirent) + namlen + 1,sizeof(u64)); int err = 0; if (!access_ok(VERIFY_WRITE, buf, sizeof(*buf))) -- Milind Arun Choudhary From zhigaoni@hitrendtech.com Mon Apr 2 07:22:24 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Apr 2007 07:22:26 +0100 (BST) Received: from mail.actions-semi.com ([211.96.231.237]:33883 "EHLO mailgw.actions.com.cn") by ftp.linux-mips.org with ESMTP id S20021669AbXDBGWY (ORCPT ); Mon, 2 Apr 2007 07:22:24 +0100 Received: from mailgw.actions.com.cn (localhost [127.0.0.1]) by mailgw.actions.com.cn (8.13.4/8.12.11) with ESMTP id l326Otma020013 for ; Mon, 2 Apr 2007 14:24:55 +0800 Received: from srv-mail.actions.com.cn [(172.16.1.16)] by mailgw.actions.com.cn (CEF-200 v3.4.3 Build 0915) with ESMTP id 911505638; Mon, 02 Apr 2007 14:24:54 +0800 Received: from srv-mail-02.actions.com.cn ([172.16.1.1]) by srv-mail.actions.com.cn with Microsoft SMTPSVC(6.0.3790.1830); Mon, 2 Apr 2007 14:19:08 +0800 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; 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------_=_NextPart_001_01C774EE.7BF409E8-- From yoichi_yuasa@tripeaks.co.jp Wed Apr 4 08:30:55 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 08:30:57 +0100 (BST) Received: from mo31.po.2iij.NET ([210.128.50.54]:51002 "EHLO mo31.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20021574AbXDDHaz (ORCPT ); Wed, 4 Apr 2007 08:30:55 +0100 Received: by mo.po.2iij.net (mo31) id l347TaNM069340; Wed, 4 Apr 2007 16:29:36 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox31) id l347TYpk098838 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 4 Apr 2007 16:29:34 +0900 (JST) Date: Wed, 4 Apr 2007 16:29:34 +0900 From: Yoichi Yuasa To: Andrew Morton Cc: yoichi_yuasa@tripeaks.co.jp, "Maciej W. Rozycki" , Linux Kernel Mailing List , linux-mips Subject: [PATCH] Fixed build error on zs serial driver Message-Id: <20070404162934.2635ef95.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14784 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi, This patch has fixed build error on zs serial driver. drivers/tc/zs.c:73:24: error: asm/dec/tc.h: No such file or directory make[2]: *** [drivers/tc/zs.o] Error 1 Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/tc/zs.c mips/drivers/tc/zs.c --- mips-orig/drivers/tc/zs.c 2007-04-04 15:01:22.952507000 +0900 +++ mips/drivers/tc/zs.c 2007-04-04 15:15:37.861935500 +0900 @@ -70,7 +70,6 @@ #include #include #include -#include #ifdef CONFIG_KGDB #include From yoichi_yuasa@tripeaks.co.jp Wed Apr 4 08:42:12 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 08:42:15 +0100 (BST) Received: from mo32.po.2iij.NET ([210.128.50.17]:42056 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20021619AbXDDHmM (ORCPT ); Wed, 4 Apr 2007 08:42:12 +0100 Received: by mo.po.2iij.net (mo32) id l347esd9051544; Wed, 4 Apr 2007 16:40:54 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox33) id l347eq2Z024520 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 4 Apr 2007 16:40:52 +0900 (JST) Date: Wed, 4 Apr 2007 16:40:52 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH][MIPS] remove pnx8550-v2pci_defconfig Message-Id: <20070404164052.1c9213be.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14785 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has removed pnx8550-v2pci_defconfig. It's already removed from Kconfig. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/pnx8550-v2pci_defconfig mips/arch/mips/configs/pnx8550-v2pci_defconfig --- mips-orig/arch/mips/configs/pnx8550-v2pci_defconfig 2007-04-04 15:00:37.269652000 +0900 +++ mips/arch/mips/configs/pnx8550-v2pci_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,1540 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Tue Feb 20 21:47:39 2007 -# -CONFIG_MIPS=y - -# -# Machine selection -# -CONFIG_ZONE_DMA=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_PNX8550=y -CONFIG_SOC_PNX8550=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPSR1=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_256 is not set -# CONFIG_HZ_1000 is not set -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=250 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -# CONFIG_KEXEC is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set -# CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_SYSFS_DEPRECATED=y -# CONFIG_RELAY is not set -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -# CONFIG_MODULE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Block layer -# -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_LEGACY is not set -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_SYSFS_DEPRECATED is not set - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_TCP_MD5SIG=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set -CONFIG_IPV6_SIT=m -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# Core Netfilter Configuration -# -# CONFIG_NETFILTER_NETLINK is not set -CONFIG_NF_CONNTRACK_ENABLED=m -CONFIG_NF_CONNTRACK_SUPPORT=y -# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -# CONFIG_NETFILTER_XT_MATCH_DSCP is not set -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -# CONFIG_NETFILTER_XT_MATCH_POLICY is not set -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set - -# -# IPv6: Netfilter Configuration (EXPERIMENTAL) -# -CONFIG_NF_CONNTRACK_IPV6=m -# CONFIG_IP6_NF_QUEUE is not set -# CONFIG_IP6_NF_IPTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_IEEE80211 is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -# CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set - -# -# Misc devices -# -CONFIG_SGI_IOC4=m -# CONFIG_TIFM_CORE is not set - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -CONFIG_BLK_DEV_IDEPCI=y -CONFIG_IDEPCI_SHARE_IRQ=y -# CONFIG_BLK_DEV_OFFBOARD is not set -# CONFIG_BLK_DEV_GENERIC is not set -# CONFIG_BLK_DEV_OPTI621 is not set -CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -CONFIG_IDEDMA_PCI_AUTO=y -# CONFIG_IDEDMA_ONLYDISK is not set -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -CONFIG_BLK_DEV_CMD64X=y -# CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5520 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_JMICRON is not set -# CONFIG_BLK_DEV_SC1200 is not set -# CONFIG_BLK_DEV_PIIX is not set -CONFIG_BLK_DEV_IT8213=m -# CONFIG_BLK_DEV_IT821X is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -CONFIG_BLK_DEV_TC86C001=m -# CONFIG_IDE_ARM is not set -CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set -CONFIG_IDEDMA_AUTO=y -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_TGT=m -CONFIG_SCSI_NETLINK=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -CONFIG_SCSI_SCAN_ASYNC=y - -# -# SCSI Transports -# -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_FC_ATTRS=y -CONFIG_SCSI_ISCSI_ATTRS=m -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set - -# -# SCSI low-level drivers -# -CONFIG_ISCSI_TCP=m -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -CONFIG_SCSI_AIC7XXX=m -CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 -CONFIG_AIC7XXX_RESET_DELAY_MS=15000 -# CONFIG_AIC7XXX_DEBUG_ENABLE is not set -CONFIG_AIC7XXX_DEBUG_MASK=0 -# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_AIC94XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ARCMSR is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_STEX is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_SRP is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# -# CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -CONFIG_TUN=m - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -# CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -CONFIG_NATSEMI=y -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -CONFIG_8139TOO=y -# CONFIG_8139TOO_PIO is not set -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_8139_OLD_RX_RESET is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_SC92031 is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -# CONFIG_QLA3XXX is not set -# CONFIG_ATL1 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -CONFIG_CHELSIO_T3=m -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set -CONFIG_NETXEN_NIC=m - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PPP=m -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -# CONFIG_PPP_BSDCOMP is not set -CONFIG_PPP_MPPE=m -# CONFIG_PPPOE is not set -# CONFIG_SLIP is not set -CONFIG_SLHC=m -# CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -# CONFIG_VT_CONSOLE is not set -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_COMPUTONE is not set -# CONFIG_ROCKETPORT is not set -# CONFIG_CYCLADES is not set -# CONFIG_DIGIEPCA is not set -# CONFIG_MOXA_INTELLIO is not set -# CONFIG_MOXA_SMARTIO is not set -CONFIG_MOXA_SMARTIO_NEW=m -# CONFIG_ISI is not set -# CONFIG_SYNCLINKMP is not set -# CONFIG_SYNCLINK_GT is not set -# CONFIG_N_HDLC is not set -# CONFIG_RISCOM8 is not set -# CONFIG_SPECIALIX is not set -# CONFIG_SX is not set -# CONFIG_RIO is not set -# CONFIG_STALDRV is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_PNX8XXX=y -CONFIG_SERIAL_PNX8XXX_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -CONFIG_HW_RANDOM=y -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -CONFIG_I2C=m -CONFIG_I2C_CHARDEV=m - -# -# I2C Algorithms -# -CONFIG_I2C_ALGOBIT=m -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set - -# -# I2C Hardware Bus support -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PASEMI is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_VOODOO3 is not set -# CONFIG_I2C_PCA_ISA is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ABITUGURU is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set -# CONFIG_USB_DABUSB is not set - -# -# Graphics support -# -CONFIG_FIRMWARE_EDID=y -CONFIG_FB=y -# CONFIG_FB_DDC is not set -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_SMIVGX is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_VIRTUAL is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set - -# -# Logo configuration -# -# CONFIG_LOGO is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# HID Devices -# -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_OTG is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_EHCI_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_UHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# may also be needed; see USB_STORAGE Help for more information -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set -CONFIG_USB_HIDDEV=y -# CONFIG_USB_AIPTEK is not set -# CONFIG_USB_WACOM is not set -# CONFIG_USB_ACECAD is not set -# CONFIG_USB_KBTAB is not set -# CONFIG_USB_POWERMATE is not set -# CONFIG_USB_TOUCHSCREEN is not set -# CONFIG_USB_YEALINK is not set -# CONFIG_USB_XPAD is not set -# CONFIG_USB_ATI_REMOTE is not set -# CONFIG_USB_ATI_REMOTE2 is not set -# CONFIG_USB_KEYSPAN_REMOTE is not set -# CONFIG_USB_APPLETOUCH is not set -# CONFIG_USB_GTCO is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET_MII is not set -# CONFIG_USB_USBNET is not set -CONFIG_USB_MON=y - -# -# USB port drivers -# - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_TEST is not set - -# -# USB DSL modem support -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -CONFIG_XFS_FS=m -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_SECURITY is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -# CONFIG_PROC_KCORE is not set -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -CONFIG_CONFIGFS_FS=m - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_CRAMFS=y -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=m -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=m -# CONFIG_SMB_NLS_DEFAULT is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Distributed Lock Manager -# -CONFIG_DLM=m -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set -# CONFIG_DLM_DEBUG is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" -CONFIG_SYS_SUPPORTS_KGDB=y - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=m -CONFIG_CRYPTO_HASH=m -CONFIG_CRYPTO_MANAGER=m -# CONFIG_CRYPTO_HMAC is not set -CONFIG_CRYPTO_XCBC=m -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_TGR192 is not set -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -# CONFIG_CRYPTO_DES is not set -CONFIG_CRYPTO_FCRYPT=m -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -CONFIG_CRYPTO_ARC4=m -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_CRC_CCITT=m -# CONFIG_CRC16 is not set -CONFIG_CRC32=y -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=m -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y From macro@linux-mips.org Wed Apr 4 12:42:32 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 12:42:33 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:24068 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20021835AbXDDLmc (ORCPT ); Wed, 4 Apr 2007 12:42:32 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id E5C01E1CB1; Wed, 4 Apr 2007 13:41:50 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KoYAnXcHhyhD; Wed, 4 Apr 2007 13:41:50 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 89EB5E1C9C; Wed, 4 Apr 2007 13:41:50 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.8) with ESMTP id l34BfwoG032386; Wed, 4 Apr 2007 13:41:59 +0200 Date: Wed, 4 Apr 2007 12:41:55 +0100 (BST) From: "Maciej W. Rozycki" To: Yoichi Yuasa cc: Andrew Morton , Linux Kernel Mailing List , linux-mips Subject: Re: [PATCH] Fixed build error on zs serial driver In-Reply-To: <20070404162934.2635ef95.yoichi_yuasa@tripeaks.co.jp> Message-ID: References: <20070404162934.2635ef95.yoichi_yuasa@tripeaks.co.jp> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.90.1/3011/Wed Apr 4 06:15:22 2007 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14786 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, 4 Apr 2007, Yoichi Yuasa wrote: > This patch has fixed build error on zs serial driver. > > drivers/tc/zs.c:73:24: error: asm/dec/tc.h: No such file or directory > make[2]: *** [drivers/tc/zs.o] Error 1 > > Yoichi > > Signed-off-by: Yoichi Yuasa Acked-by: Maciej W. Rozycki The driver is on its way out though. Maciej From ralf@linux-mips.org Wed Apr 4 13:34:38 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 13:34:39 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:25778 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021671AbXDDMei (ORCPT ); Wed, 4 Apr 2007 13:34:38 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l34BfLeb030628; Wed, 4 Apr 2007 12:41:21 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l34BfJMN030627; Wed, 4 Apr 2007 12:41:19 +0100 Date: Wed, 4 Apr 2007 12:41:19 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH][MIPS] remove pnx8550-v2pci_defconfig Message-ID: <20070404114119.GA29413@linux-mips.org> References: <20070404164052.1c9213be.yoichi_yuasa@tripeaks.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070404164052.1c9213be.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14787 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 04, 2007 at 04:40:52PM +0900, Yoichi Yuasa wrote: > This patch has removed pnx8550-v2pci_defconfig. > It's already removed from Kconfig. Thanks, applied. Ralf From ralf@linux-mips.org Wed Apr 4 13:42:57 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 13:42:59 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:39325 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021827AbXDDMm5 (ORCPT ); Wed, 4 Apr 2007 13:42:57 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l34Cgu8k031244 for ; Wed, 4 Apr 2007 13:42:57 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l34CgudS031243 for linux-mips@linux-mips.org; Wed, 4 Apr 2007 13:42:56 +0100 Date: Wed, 4 Apr 2007 13:42:56 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: Recently, on the other side of the fence ... Message-ID: <20070404124256.GA31237@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14788 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Date: Sat, 31 Mar 2007 02:01:36 +0300 From: Oleksandr Tymoshenko To: freebsd-mips@freebsd.org, freebsd-embedded@freebsd.org Subject: FreeBSD/MIPS project status update On behalf of FreeBSD/MIPS team I'm proud to announce that project has reached single-user stage. On the moment FreeBSD/MIPS runs only in malta board emulation mode of GXemul though adm5120 support is on it's way and people with real MIPS-based hardware can start playing with latest repo snapshot bringing FreeBSD on it. Many thanks to all who contributed with their time, efforts and experience. Especially to #bsdmips crowd for patience to newbies :) Attached mips.txt is a "recording" of sample GXemul session. Current p4 repo snapshot: http://kanar.ci0.org/mips2.tar.gz Check http://wiki.freebsd.org/FreeBSD/mips for sample build script P4 URL: http://perforce.freebsd.org/depotTreeBrowser.cgi?FSPC=//depot/projects/mips2/... -- gonzo GXemul 0.4.1 Copyright (C) 2003-2006 Anders Gavare Read the source code and/or documentation for other Copyright messages. Simple setup... net: simulating 10.0.0.0/8 (max outgoing: TCP=100, UDP=100) simulated gateway: 10.0.0.254 (60:50:40:30:20:10) using nameserver 192.168.0.1 machine "default": memory: 64 MB cpu0: 4Kc (I+D = 16+16 KB) machine: MALTA (evbmips, little endian) bootstring: kernel diskimage: /usr/home/gonzo/FreeBSD/mips.img IDE DISK id 0, read/write, 512 MB (1048576 sectors) loading /tftpboot/kernel starting cpu0 at 0x80127420 (gp=0x8033e180) ------------------------------------------------------------------------------- GXemul> c entry: mips_init() picache_stride = 4096 picache_loopcount = 4 pdcache_stride = 4096 pdcache_loopcount = 4 mips_cache_ops.mco_pdcache_wbinv_all == 0x802dcdb0 Exception vector at 80000000 almost out of space Kernel page table maps 16384 4K pages and is 511K KDB: debugger backends: ddb KDB: current backend: ddb cp: (null) cannot determine clock frequency, defaulting to 10MHz Copyright (c) 1992-2006 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD 7.0-CURRENT #65: Fri Mar 30 19:03:48 EEST 2007 gonzo@jeeves.bluezbox.com:/home/gonzo/FreeBSD/mips.build/mips/home/gonzo/FreeBSD/p4/mips2/src/sys/MALTA cpu0: MIPS Technologies processor v1.128 MMU: Standard TLB, 16 entries L1 i-cache: 2 ways of 512 sets, 16 bytes per line L1 d-cache: 2 ways of 512 sets, 16 bytes per line clock0: on motherboard clock0: [FAST] gt0: on motherboard pcib0: on gt0 [ 8259: TODO: Level triggered (MCA bus) ] [ 8259: WARNING: Bit 2 set ] [ 8259: TODO: Level triggered (MCA bus) ] [ 8259: WARNING: Bit 2 set ] pcib0: [FAST] pci0: on pcib0 uart0: <8250 or 16450 or compatible> on obio0 uart0: [FAST] uart0: console (115200,n,8,1) pci0: at device 9.0 (no driver attached) atapci0: port 0x1f0-0x1f7,0x3f6,0x170-0x177,0x376 at device 9.1 on pci0 ata0: on atapci0 ata0: WARNING - DMA allocation failed, disabling DMA ata1: on atapci0 ata1: WARNING - DMA allocation failed, disabling DMA Timecounter "MIPS32" frequency 10000000 Hz quality 800 Timecounters tick every 10.000 msec ad0: 514MB at ata0-master PIO4 Trying to mount root from ufs:ad0s1a warning: no time-of-day clock registered, system time will not be set accurately Enter full pathname of shell or RETURN for /bin/sh: # mount -o rw / # hostname mips.bluezbox.com # uname -a FreeBSD mips.bluezbox.com 7.0-CURRENT FreeBSD 7.0-CURRENT #65: Fri Mar 30 19:03:48 EEST 2007 gonzo@jeeves.bluezbox.com:/home/gonzo/FreeBSD/mips.build/mips/home/gonzo/FreeBSD/p4/mips2/src/sys/MALTA mips # cd /root # ls .cshrc .profile args.c hello.c .login Makefile hello signal.c # cat Makefile CFLAGS=-msoft-float -G0 -mabicalls -EL -Wl,-EL -static -march=mips32 CC=cc all: hello signal args hello: hello.c $(CC) $(CFLAGS) -o hello hello.c signal: signal.c $(CC) $(CFLAGS) -o signal signal.c args: args.c $(CC) $(CFLAGS) -o args args.c clean: rm -f signal hello args # cat hello.c #include int main(int argc, char * argv[]) { printf("Hello world\n"); } # cat args.c #include int main(int argc, char * argv[]) { int i ; printf("Arguments: %d\n", argc); for(i = 0; i < argc; i++) { printf("#%d == '%s'\n", i, argv[i]); } } # cat signal.c #include #include void sig_int(int signum) { printf("Interrupted!\n"); exit(0); } void sig_general(int signum) { printf("Signal: %d!\n", signum); } int main(int argc, char * argv[]) { int i = 0; signal(SIGINT, sig_int); signal(SIGUSR1, sig_general); signal(SIGUSR2, sig_general); while(i < 10) { sleep(1); if(i % 2) kill(getpid(), SIGUSR1); else kill(getpid(), SIGUSR2); printf(">> %d\n", i++); } kill(getpid(), SIGINT); i = 0; while(i < 10) { printf(">> %d\n", i++); sleep(1); } } # make cc -msoft-float -G0 -mabicalls -EL -Wl,-EL -static -march=mips32 -o signal signal.c cc -msoft-float -G0 -mabicalls -EL -Wl,-EL -static -march=mips32 -o args args.c # make clean rm -f signal hello args # make cc -msoft-float -G0 -mabicalls -EL -Wl,-EL -static -march=mips32 -o hello hello.c cc -msoft-float -G0 -mabicalls -EL -Wl,-EL -static -march=mips32 -o signal signal.c cc -msoft-float -G0 -mabicalls -EL -Wl,-EL -static -march=mips32 -o args args.c # ls -la total 2340 drwxr-xr-x 2 root wheel 512 Mar 30 19:41 . drwxr-xr-x 18 root wheel 512 Mar 27 13:27 .. -rw-r--r-- 2 root wheel 801 Mar 27 13:27 .cshrc -rw-r--r-- 1 root wheel 293 Mar 27 13:27 .login -rw-r--r-- 2 root wheel 251 Mar 27 13:27 .profile -rw-r--r-- 1 root wheel 283 Mar 30 16:09 Makefile -rwxr-xr-x 1 root wheel 367585 Mar 30 19:40 args -rw-r--r-- 1 root wheel 173 Mar 30 19:14 args.c -rwxr-xr-x 1 root wheel 367586 Mar 30 19:40 hello -rw-r--r-- 1 root wheel 91 Mar 27 18:17 hello.c -rwxr-xr-x 1 root wheel 372613 Mar 30 19:40 signal -rw-r--r-- 1 root wheel 552 Mar 27 17:42 signal.c # file hello args signal hello: ELF 32-bit LSB executable, MIPS, version 1 (FreeBSD), for FreeBSD 7.0 (700018), statically linked, for FreeBSD 7.0 (700018), not stripped args: ELF 32-bit LSB executable, MIPS, version 1 (FreeBSD), for FreeBSD 7.0 (700018), statically linked, for FreeBSD 7.0 (700018), not stripped signal: ELF 32-bit LSB executable, MIPS, version 1 (FreeBSD), for FreeBSD 7.0 (700018), statically linked, for FreeBSD 7.0 (700018), not stripped # ./hello Hello world # ./args this is a test Arguments: 5 #0 == './args' #1 == 'this' #2 == 'is' #3 == 'a' #4 == 'test' # ./signal Signal: 31! >> 0 Signal: 30! >> 1 Signal: 31! >> 2 Signal: 30! >> 3 Signal: 31! >> 4 Signal: 30! >> 5 Signal: 31! >> 6 Signal: 30! >> 7 Signal: 31! >> 8 Signal: 30! >> 9 Interrupted! # who am i who: /var/run/utmp: No such file or directory # id uid=0(root) gid=0(wheel) groups=0(wheel) # ifconfig -a lo0: flags=8008 mtu 16384 # ifconfig lo0 127.0.0.1 # ifconfig -a lo0: flags=8049 mtu 16384 inet 127.0.0.1 netmask 0xff000000 # ping -c 10 127.0.0.1 PING 127.0.0.1 (127.0.0.1): 56 data bytes 64 bytes from 127.0.0.1: icmp_seq=0 ttl=64 time=2.470 ms 64 bytes from 127.0.0.1: icmp_seq=1 ttl=64 time=1.646 ms 64 bytes from 127.0.0.1: icmp_seq=2 ttl=64 time=1.645 ms 64 bytes from 127.0.0.1: icmp_seq=3 ttl=64 time=1.643 ms 64 bytes from 127.0.0.1: icmp_seq=4 ttl=64 time=1.645 ms 64 bytes from 127.0.0.1: icmp_seq=5 ttl=64 time=1.641 ms 64 bytes from 127.0.0.1: icmp_seq=6 ttl=64 time=1.646 ms 64 bytes from 127.0.0.1: icmp_seq=7 ttl=64 time=1.643 ms 64 bytes from 127.0.0.1: icmp_seq=8 ttl=64 time=1.643 ms 64 bytes from 127.0.0.1: icmp_seq=9 ttl=64 time=1.645 ms --- 127.0.0.1 ping statistics --- 10 packets transmitted, 10 packets received, 0% packet loss round-trip min/avg/max/stddev = 1.641/1.727/2.470/0.248 ms # halt -p Waiting (max 60 seconds) for system process `vnlru' to stop...done Waiting (max 60 seconds) for system process `bufdaemon' to stop...done Waiting (max 60 seconds) for system process `syncer' to stop... Syncing disks, vnodes remaining...0 From sathesh_edara2003@yahoo.co.in Wed Apr 4 14:35:44 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 14:35:50 +0100 (BST) Received: from web7907.mail.in.yahoo.com ([202.86.4.83]:58758 "HELO web7907.mail.in.yahoo.com") by ftp.linux-mips.org with SMTP id S20021970AbXDDNfo (ORCPT ); Wed, 4 Apr 2007 14:35:44 +0100 Received: (qmail 96667 invoked by uid 60001); 4 Apr 2007 13:34:29 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.co.in; h=X-YMail-OSG:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-ID; b=DaEumORm0clT254KP0qq2VZgUZwDuV0OYSIUOsyZmgyotVyAVGy2fSgPWuAgcxRjjTDWghWKRfsG/Ab8ZmsocCjLqQNvDNLjPe8bOjMUdhRX3lXrkqclH4tCy2kmmnEpVyCF2H/hwcLoxSwoZt+NcjXleR/g7t8cISp6YOYZIbc=; X-YMail-OSG: Lk8FnbYVM1mNvnjVvlIGdqRn5ibc32iLDpkvNUOFpjC_zNB7yCqoscP5kcjtYmkOvO9DrNQZAiKvdSYA.U1N49L3pHZLpf5ZIeIsCa7HdTJZlMkCv4PSTk9ipgiUSQ-- Received: from [199.239.167.162] by web7907.mail.in.yahoo.com via HTTP; Wed, 04 Apr 2007 14:34:29 BST Date: Wed, 4 Apr 2007 14:34:29 +0100 (BST) From: sathesh babu Subject: Back ground user process display issue on linux-2.6.18 kernel To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="0-875335224-1175693669=:96419" Content-Transfer-Encoding: 8bit Message-ID: <718603.96419.qm@web7907.mail.in.yahoo.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14789 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sathesh_edara2003@yahoo.co.in Precedence: bulk X-list: linux-mips --0-875335224-1175693669=:96419 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi , We are running a sample user application "samp_app" in the background using "samp_app &" form rcS script file. We are using linux-2.6.18 kernel. In this application code we have put some debug messages to display it on console using printf() function. We are unable to see any of these debug messages on the console. When we run the same application in the foreground (without &) from same rcS script, we are getting these messages on console. WE RAN THE SAME APPLICATION AS A BACKGROUND PROCESS ('samp_app &') ON LINUX-2.6.12 KERNEL. WE ARE ABLE TO GET THESE DEBUG PRINTS. Could you please tell us what might be the reason for this behavior on linux-2.6.18. Did we miss any configuration option in the 2.6.18 kernel. Note that we are using same toolchain for both the kernel versions. Thanks in Advance. Regards, Sathesh. --------------------------------- Here’s a new way to find what you're looking for - Yahoo! Answers --0-875335224-1175693669=:96419 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit
Hi ,
 
We are running a sample user application "samp_app" in the background using "samp_app &" form rcS script file.
We are using linux-2.6.18 kernel.
In this application code we have put some debug messages to display it on console using printf() function.
We are unable to see any of these debug messages on the console.
When we run the same application in the foreground (without &) from same rcS script, we are getting these messages on console.
 
WE RAN THE SAME APPLICATION AS A BACKGROUND PROCESS ('samp_app &') ON LINUX-2.6.12 KERNEL. WE ARE ABLE TO GET THESE DEBUG PRINTS.
 
Could you please tell us what might be the reason for this behavior on linux-2.6.18.
Did we miss any configuration option in the 2.6.18 kernel.
 
Note that we are using same toolchain for both the kernel versions.
 
Thanks in Advance.
 
Regards,
Sathesh.

Here’s a new way to find what you're looking for - Yahoo! Answers --0-875335224-1175693669=:96419-- From zhangfx@lemote.com Wed Apr 4 15:31:10 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:31:12 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:19943 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20021836AbXDDObK (ORCPT ); Wed, 4 Apr 2007 15:31:10 +0100 Received: (qmail 16936 invoked by uid 511); 4 Apr 2007 14:30:21 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:21 -0000 Message-ID: <667328.695158602-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 12/16] cheat for support of more than 256MB memory Date: Wed, 4 Apr 2007 14:38:19 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-279305.257908167" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14790 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-279305.257908167 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- arch/mips/kernel/setup.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 4975da0..92a27bb 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -509,6 +509,14 @@ static void __init resource_init(void) res->end = end; res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; +#if defined(CONFIG_LEMOTE_FULONG) && defined(CONFIG_64BIT) + /* to keep memory continous, we tell system 0x10000000 - 0x20000000 is reserved + * for memory, in fact it is io region, don't occupy it + * + * SPARSEMEM? + */ + if (boot_mem_map.map[i].type != BOOT_MEM_RESERVED) +#endif request_resource(&iomem_resource, res); /* -- 1.4.4.4 ------MIME delimiter for sendEmail-279305.257908167-- From zhangfx@lemote.com Wed Apr 4 15:31:32 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:31:34 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:18919 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20021835AbXDDObL (ORCPT ); Wed, 4 Apr 2007 15:31:11 +0100 Received: (qmail 16924 invoked by uid 511); 4 Apr 2007 14:30:20 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:20 -0000 Message-ID: <8477.97710181908-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 8/16] define MODULE_PROC_FAMILY for Loongson2 Date: Wed, 4 Apr 2007 14:38:19 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-49769.2807848615" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14791 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-49769.2807848615 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- include/asm-mips/module.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h index 399d03f..f615324 100644 --- a/include/asm-mips/module.h +++ b/include/asm-mips/module.h @@ -112,6 +112,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "RM9000 " #elif defined CONFIG_CPU_SB1 #define MODULE_PROC_FAMILY "SB1 " +#elif defined CONFIG_CPU_LOONGSON2 +#define MODULE_PROC_FAMILY "LOONGSON2 " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif -- 1.4.4.4 ------MIME delimiter for sendEmail-49769.2807848615-- From zhangfx@lemote.com Wed Apr 4 15:31:54 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:31:56 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:19175 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022002AbXDDObN (ORCPT ); Wed, 4 Apr 2007 15:31:13 +0100 Received: (qmail 16927 invoked by uid 511); 4 Apr 2007 14:30:21 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:21 -0000 Message-ID: <258685.371696146-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 9/16] add serial port definition for lemote fulong Date: Wed, 4 Apr 2007 14:38:19 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-322815.350796194" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14792 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-322815.350796194 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- include/asm-mips/serial.h | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index d7a6513..9c9660e 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h @@ -204,6 +204,12 @@ #define IP32_SERIAL_PORT_DEFNS #endif /* CONFIG_SGI_IP32 */ +#if defined(CONFIG_LEMOTE_FULONG) +#define LEMOTE_FULONG_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ +#endif + #define SERIAL_PORT_DFNS \ DDB5477_SERIAL_PORT_DEFNS \ EV64120_SERIAL_PORT_DEFNS \ @@ -213,6 +219,7 @@ MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS + MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ + LEMOTE_FULONG_SERIAL_PORT_DEFNS #endif /* _ASM_SERIAL_H */ -- 1.4.4.4 ------MIME delimiter for sendEmail-322815.350796194-- From zhangfx@lemote.com Wed Apr 4 15:32:16 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:32:19 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:19431 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022004AbXDDObN (ORCPT ); Wed, 4 Apr 2007 15:31:13 +0100 Received: (qmail 16930 invoked by uid 511); 4 Apr 2007 14:30:21 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:21 -0000 Message-ID: <402414.148531051-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 10/16] make cpu_probe recognize Loongson2 Date: Wed, 4 Apr 2007 14:38:19 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-815403.761881502" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14793 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-815403.761881502 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- arch/mips/kernel/cpu-probe.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index ab755ea..125c72c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -464,6 +464,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) MIPS_CPU_LLSC; c->tlbsize = 64; break; + case PRID_IMP_LOONGSON2: + c->cputype = CPU_LOONGSON2; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | + MIPS_CPU_FPU | MIPS_CPU_LLSC | + MIPS_CPU_32FPR; + c->tlbsize = 64; + break; } } -- 1.4.4.4 ------MIME delimiter for sendEmail-815403.761881502-- From zhangfx@lemote.com Wed Apr 4 15:32:39 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:32:41 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:18663 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20021987AbXDDObN (ORCPT ); Wed, 4 Apr 2007 15:31:13 +0100 Received: (qmail 16911 invoked by uid 511); 4 Apr 2007 14:30:20 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:20 -0000 Message-ID: <927241.817207204-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 4/16] TO_PHYS_MASK for loongson2 Date: Wed, 4 Apr 2007 14:38:19 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-696152.640347467" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14794 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-696152.640347467 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- include/asm-mips/addrspace.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 964c5ed..a4d9a07 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -145,7 +145,7 @@ #define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ #endif -#if defined (CONFIG_CPU_R10000) +#if defined (CONFIG_CPU_R10000) || defined (CONFIG_CPU_LOONGSON2) #define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ #endif -- 1.4.4.4 ------MIME delimiter for sendEmail-696152.640347467-- From zhangfx@lemote.com Wed Apr 4 15:33:01 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:33:03 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:19687 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022010AbXDDObO (ORCPT ); Wed, 4 Apr 2007 15:31:14 +0100 Received: (qmail 16933 invoked by uid 511); 4 Apr 2007 14:30:21 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:21 -0000 Message-ID: <270731.699743436-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 11/16] add Loongson support to /proc/cpuinfo Date: Wed, 4 Apr 2007 14:38:19 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-304999.022585438" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14795 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-304999.022585438 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- arch/mips/kernel/proc.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 5ddc2e9..e915117 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -84,6 +84,7 @@ static const char *cpu_name[] = { [CPU_VR4181A] = "NEC VR4181A", [CPU_SR71000] = "Sandcraft SR71000", [CPU_PR4450] = "Philips PR4450", + [CPU_LOONGSON2] = "ICT Loongson-2", }; -- 1.4.4.4 ------MIME delimiter for sendEmail-304999.022585438-- From zhangfx@lemote.com Wed Apr 4 15:33:23 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:33:26 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:20711 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022028AbXDDObO (ORCPT ); Wed, 4 Apr 2007 15:31:14 +0100 Received: (qmail 16945 invoked by uid 511); 4 Apr 2007 14:30:21 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:21 -0000 Message-ID: <499517.799911217-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 15/16] work around for more than 256MB memory support Date: Wed, 4 Apr 2007 14:38:20 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-226124.783353047" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14796 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-226124.783353047 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- drivers/char/mem.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/char/mem.c b/drivers/char/mem.c index f5c160c..580ad3e 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -83,8 +83,12 @@ static inline int uncached_access(struct file *file, unsigned long addr) */ if (file->f_flags & O_SYNC) return 1; +#if defined(CONFIG_LEMOTE_FULONG) && defined(CONFIG_64BIT) + return (addr >= __pa(high_memory)) || ((addr >=0x10000000) && (addr < 0x20000000)); +#else return addr >= __pa(high_memory); #endif +#endif } #ifndef ARCH_HAS_VALID_PHYS_ADDR_RANGE -- 1.4.4.4 ------MIME delimiter for sendEmail-226124.783353047-- From zhangfx@lemote.com Wed Apr 4 15:33:46 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:33:48 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:20967 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022032AbXDDObP (ORCPT ); Wed, 4 Apr 2007 15:31:15 +0100 Received: (qmail 16948 invoked by uid 511); 4 Apr 2007 14:30:21 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:21 -0000 Message-ID: <932376.137093769-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 16/16] alsa sound support for mips Date: Wed, 4 Apr 2007 14:38:20 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-225282.322456227" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14797 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-225282.322456227 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- sound/core/pcm_native.c | 10 ++++++++++ sound/core/sgbuf.c | 9 +++++++++ 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index 3e276fc..9005bac 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -3145,7 +3145,11 @@ static struct page *snd_pcm_mmap_data_nopage(struct vm_area_struct *area, return NOPAGE_OOM; /* XXX: is this really due to OOM? */ } else { vaddr = runtime->dma_area + offset; +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) + page = virt_to_page(CAC_ADDR(vaddr)); +#else page = virt_to_page(vaddr); +#endif } get_page(page); if (type) @@ -3261,6 +3265,12 @@ static int snd_pcm_mmap(struct file *file, struct vm_area_struct *area) substream = pcm_file->substream; snd_assert(substream != NULL, return -ENXIO); +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) + /* all mmap using uncached mode */ + area->vm_page_prot = pgprot_noncached(area->vm_page_prot); + area->vm_flags |= ( VM_RESERVED | VM_IO); +#endif + offset = area->vm_pgoff << PAGE_SHIFT; switch (offset) { case SNDRV_PCM_MMAP_OFFSET_STATUS: diff --git a/sound/core/sgbuf.c b/sound/core/sgbuf.c index cefd228..535f0bc 100644 --- a/sound/core/sgbuf.c +++ b/sound/core/sgbuf.c @@ -91,12 +91,21 @@ void *snd_malloc_sgbuf_pages(struct device *device, } sgbuf->table[i].buf = tmpb.area; sgbuf->table[i].addr = tmpb.addr; +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) + sgbuf->page_table[i] = virt_to_page(CAC_ADDR(tmpb.area)); +#else sgbuf->page_table[i] = virt_to_page(tmpb.area); +#endif sgbuf->pages++; } sgbuf->size = size; +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) + /* maybe we should use uncached accelerated mode */ + dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP | VM_IO, pgprot_noncached(PAGE_KERNEL)); +#else dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP, PAGE_KERNEL); +#endif if (! dmab->area) goto _failed; return dmab->area; -- 1.4.4.4 ------MIME delimiter for sendEmail-225282.322456227-- From zhangfx@lemote.com Wed Apr 4 15:34:08 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:34:12 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:20199 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022020AbXDDObQ (ORCPT ); Wed, 4 Apr 2007 15:31:16 +0100 Received: (qmail 16905 invoked by uid 511); 4 Apr 2007 14:30:20 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:20 -0000 Message-ID: <255864.73368773-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC Date: Wed, 4 Apr 2007 14:38:18 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-857471.174168499" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14798 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-857471.174168499 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- arch/mips/Makefile | 8 ++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/lib-32/Makefile | 1 + arch/mips/lib-64/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/pci/Makefile | 1 + 6 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 92bca6a..2a6742d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -118,6 +118,7 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -Wa,-mips32 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ @@ -298,6 +299,13 @@ cflags-$(CONFIG_WR_PPMC) += -Iinclude/asm-mips/mach-wrppmc load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 # +# lemote fulong mini-PC board +# +core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/ +load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000 +cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote + +# # For all MIPS, Inc. eval boards # core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 4924626..40fdf79 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile index 8b94d4c..b4be604 100644 --- a/arch/mips/lib-32/Makefile +++ b/arch/mips/lib-32/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_CPU_SB1) += dump_tlb.o obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o +obj-$(CONFIG_CPU_LOONGSON2) += dump_tlb.o diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile index 8b94d4c..b4be604 100644 --- a/arch/mips/lib-64/Makefile +++ b/arch/mips/lib-64/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_CPU_SB1) += dump_tlb.o obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o +obj-$(CONFIG_CPU_LOONGSON2) += dump_tlb.o diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 293697b..b2dd42e 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o +obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_SB1) += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \ tlb-r4k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index bf85995..3a77235 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o +obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-lm2e.o -- 1.4.4.4 ------MIME delimiter for sendEmail-857471.174168499-- From zhangfx@lemote.com Wed Apr 4 15:34:32 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:34:34 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:21479 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022062AbXDDObS (ORCPT ); Wed, 4 Apr 2007 15:31:18 +0100 Received: (qmail 16914 invoked by uid 511); 4 Apr 2007 14:30:20 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:20 -0000 Message-ID: <329936.294906901-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 5/16] add MACH_GROUP_LEMOTE & MACH_LEMOTE_FULONG Date: Wed, 4 Apr 2007 14:38:19 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-416336.47012441" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14799 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-416336.47012441 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- include/asm-mips/bootinfo.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index c7c945b..f4607f1 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -213,6 +213,12 @@ #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ +/* + * Valid machtype for group LEMOTE + */ +#define MACH_GROUP_LEMOTE 27 +#define MACH_LEMOTE_FULONG 0 + #define CL_SIZE COMMAND_LINE_SIZE const char *get_system_type(void); -- 1.4.4.4 ------MIME delimiter for sendEmail-416336.47012441-- From zhangfx@lemote.com Wed Apr 4 15:34:54 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:34:57 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:21991 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022086AbXDDObS (ORCPT ); Wed, 4 Apr 2007 15:31:18 +0100 Received: (qmail 16917 invoked by uid 511); 4 Apr 2007 14:30:20 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:20 -0000 Message-ID: <554353.261224122-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 6/16] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 Date: Wed, 4 Apr 2007 14:38:19 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-413557.267355831" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14800 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-413557.267355831 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- include/asm-mips/cacheops.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index c4a1ec3..df7f2de 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h @@ -20,7 +20,11 @@ #define Index_Load_Tag_D 0x05 #define Index_Store_Tag_I 0x08 #define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else #define Hit_Invalidate_I 0x10 +#endif #define Hit_Invalidate_D 0x11 #define Hit_Writeback_Inv_D 0x15 -- 1.4.4.4 ------MIME delimiter for sendEmail-413557.267355831-- From zhangfx@lemote.com Wed Apr 4 15:35:16 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:35:21 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:18407 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20021993AbXDDObT (ORCPT ); Wed, 4 Apr 2007 15:31:19 +0100 Received: (qmail 16902 invoked by uid 511); 4 Apr 2007 14:30:20 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:20 -0000 Message-ID: <945333.042039664-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 1/16] new files for lemote fulong mini-PC support Date: Wed, 4 Apr 2007 14:38:18 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-892146.067301841" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14801 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-892146.067301841 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- arch/mips/lemote/README | 2 + arch/mips/lemote/lm2e/Makefile | 7 + arch/mips/lemote/lm2e/bonito-irq.c | 100 +++++++ arch/mips/lemote/lm2e/dbg_io.c | 162 +++++++++++ arch/mips/lemote/lm2e/irq.c | 157 ++++++++++ arch/mips/lemote/lm2e/mipsdha.c | 162 +++++++++++ arch/mips/lemote/lm2e/pci.c | 73 +++++ arch/mips/lemote/lm2e/prom.c | 112 ++++++++ arch/mips/lemote/lm2e/reset.c | 47 +++ arch/mips/lemote/lm2e/setup.c | 143 ++++++++++ arch/mips/pci/fixup-lm2e.c | 255 +++++++++++++++++ arch/mips/pci/ops-lm2e.c | 150 ++++++++++ include/asm-mips/mach-lemote/bonito.h | 395 ++++++++++++++++++++++++++ include/asm-mips/mach-lemote/dma-coherence.h | 43 +++ include/asm-mips/mach-lemote/mc146818rtc.h | 36 +++ 15 files changed, 1844 insertions(+), 0 deletions(-) diff --git a/arch/mips/lemote/README b/arch/mips/lemote/README new file mode 100644 index 0000000..96aa8ce --- /dev/null +++ b/arch/mips/lemote/README @@ -0,0 +1,2 @@ +lm2e: + board of lemote corp., which uses ict fpga north bridge and Loongson2E(godson2E) CPU. diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile new file mode 100644 index 0000000..4017b75 --- /dev/null +++ b/arch/mips/lemote/lm2e/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for Lemote Fulong mini-PC board. +# + +obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o mipsdha.o dbg_io.o + +EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/lemote/lm2e/bonito-irq.c b/arch/mips/lemote/lm2e/bonito-irq.c new file mode 100644 index 0000000..1ba153e --- /dev/null +++ b/arch/mips/lemote/lm2e/bonito-irq.c @@ -0,0 +1,100 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#define bonito_irq_shutdown bonito_irq_disable + +#define MIPS_ASSERT(x) if (!(x)) { panic("MIPS_ASSERT failed at %s:%d\n", __FILE__, __LINE__); } + +Bonito; + +static inline void bonito_irq_enable(unsigned int irq) +{ + BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); + iob(); +} + +static inline void bonito_irq_disable(unsigned int irq) +{ + BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); + iob(); +} + +static void bonito_irq_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + bonito_irq_enable(irq); +} + +static struct irq_chip bonito_irq_type = { + .name = "bonito_irq", + .ack = bonito_irq_disable, + .mask = bonito_irq_disable, + .mask_ack = bonito_irq_disable, + .unmask = bonito_irq_enable, + .eoi = bonito_irq_enable, + .end = bonito_irq_end, + NULL /* no affinity stuff for UP */ +}; + +static struct irqaction dma_timeout_irqaction = { + .handler = no_action, + .name = "dma_timeout", +}; + +void bonito_irq_init(void) +{ + u32 i; + + for (i= BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) { + set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); + } + + setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); +} diff --git a/arch/mips/lemote/lm2e/dbg_io.c b/arch/mips/lemote/lm2e/dbg_io.c new file mode 100644 index 0000000..06c9eb2 --- /dev/null +++ b/arch/mips/lemote/lm2e/dbg_io.c @@ -0,0 +1,162 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include + +#include /* For the serial port location and base baud */ + +/* --- CONFIG --- */ + +typedef unsigned char uint8; +typedef unsigned int uint32; + +/* --- END OF CONFIG --- */ + +#define UART16550_BAUD_2400 2400 +#define UART16550_BAUD_4800 4800 +#define UART16550_BAUD_9600 9600 +#define UART16550_BAUD_19200 19200 +#define UART16550_BAUD_38400 38400 +#define UART16550_BAUD_57600 57600 +#define UART16550_BAUD_115200 115200 + +#define UART16550_PARITY_NONE 0 +#define UART16550_PARITY_ODD 0x08 +#define UART16550_PARITY_EVEN 0x18 +#define UART16550_PARITY_MARK 0x28 +#define UART16550_PARITY_SPACE 0x38 + +#define UART16550_DATA_5BIT 0x0 +#define UART16550_DATA_6BIT 0x1 +#define UART16550_DATA_7BIT 0x2 +#define UART16550_DATA_8BIT 0x3 + +#define UART16550_STOP_1BIT 0x0 +#define UART16550_STOP_2BIT 0x4 + +/* ----------------------------------------------------- */ + +/* === CONFIG === */ + +#ifdef CONFIG_64BIT + +#define BASE (0xffffffffbfd003f8) + +#else + +#define BASE (0xbfd003f8) + +#endif + +#define MAX_BAUD BASE_BAUD + +/* === END OF CONFIG === */ + +#define REG_OFFSET 1 + +/* register offset */ +#define OFS_RCV_BUFFER 0 +#define OFS_TRANS_HOLD 0 +#define OFS_SEND_BUFFER 0 +#define OFS_INTR_ENABLE (1*REG_OFFSET) +#define OFS_INTR_ID (2*REG_OFFSET) +#define OFS_DATA_FORMAT (3*REG_OFFSET) +#define OFS_LINE_CONTROL (3*REG_OFFSET) +#define OFS_MODEM_CONTROL (4*REG_OFFSET) +#define OFS_RS232_OUTPUT (4*REG_OFFSET) +#define OFS_LINE_STATUS (5*REG_OFFSET) +#define OFS_MODEM_STATUS (6*REG_OFFSET) +#define OFS_RS232_INPUT (6*REG_OFFSET) +#define OFS_SCRATCH_PAD (7*REG_OFFSET) + +#define OFS_DIVISOR_LSB (0*REG_OFFSET) +#define OFS_DIVISOR_MSB (1*REG_OFFSET) + + +/* memory-mapped read/write of the port */ +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) + +void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) +{ + /* disable interrupts */ + UART16550_WRITE(OFS_INTR_ENABLE, 0); + + /* set up buad rate */ + { + uint32 divisor; + + /* set DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + divisor = MAX_BAUD / baud; + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); + + /* clear DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); + } + + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); +} + +static int remoteDebugInitialized = 0; + +uint8 getDebugChar(void) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(UART16550_BAUD_115200, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); + return UART16550_READ(OFS_RCV_BUFFER); +} + + +int putDebugChar(uint8 byte) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + /* + debugInit(UART16550_BAUD_115200, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT);*/ + + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); + UART16550_WRITE(OFS_SEND_BUFFER, byte); + return 1; +} + diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c new file mode 100644 index 0000000..eae1c67 --- /dev/null +++ b/arch/mips/lemote/lm2e/irq.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * the first level int-handler will jump here if it is a bonito irq + */ +static void bonito_irqdispatch(void) +{ + Bonito; + + int irq; + unsigned long int_status; + int i; + + /* workaround the IO dma problem: let cpu looping to allow DMA finish */ + int_status = BONITO_INTISR ; + if(int_status&(1<<10)){ + while(int_status&(1<<10)){ + udelay(1); + int_status = BONITO_INTISR; + } + } + + /* Get pending sources, masked by current enables */ + int_status = BONITO_INTISR & BONITO_INTEN; + + /* Scan all pending interrupt bits and execute appropriate actions */ + for (i=0; i<32 && int_status; i++) { + if (int_status & 1< i8259 interrupt + * 16-23 ------> mips cpu interrupt + * 32-63 ------> bonito irq + */ + + /* Sets the first-level interrupt dispatcher. */ + + mips_cpu_irq_init(); + init_i8259_irqs(); + bonito_irq_init(); + + //printk("GPIODATA=%x,GPIOIE=%x\n",BONITO_GPIODATA,BONITO_GPIOIE); + //printk("INTEN=%x,INTSET=%x,INTCLR=%x,INTISR=%x\n",BONITO_INTEN,BONITO_INTENSET,BONITO_INTENCLR,BONITO_INTISR); + + /* bonito irq at IP2 */ + setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); + /* 8259 irq at IP5 */ + setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); + + printk("init_IRQ done.\n"); +} diff --git a/arch/mips/lemote/lm2e/mipsdha.c b/arch/mips/lemote/lm2e/mipsdha.c new file mode 100644 index 0000000..0c97be9 --- /dev/null +++ b/arch/mips/lemote/lm2e/mipsdha.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static ssize_t mipsdha_proc_read(struct file *file, char *buf, size_t len, loff_t *ppos); + +static ssize_t mipsdha_proc_write(struct file *file, const char *buf, size_t len, loff_t *ppos); + + +static struct proc_dir_entry *mipsdha_proc_entry; + +#define INFO_SIZE 4096 +static char info_buf[INFO_SIZE]; + +static struct file_operations mipsdha_fops = +{ + owner: THIS_MODULE, + read: mipsdha_proc_read, + write: mipsdha_proc_write, +}; + +static enum {CMD_ERR, CMD_GIB, CMD_GPI} cmd; + +typedef struct pciinfo_s +{ + int bus,card,func; + unsigned short command; + unsigned short vendor,device; + unsigned base0,base1,base2,baserom; +} pciinfo_t; + + +static int __init mipsdha_proc_init(void) +{ + mipsdha_proc_entry = create_proc_entry("mipsdha", S_IWUSR | S_IRUGO, &proc_root); + if (mipsdha_proc_entry == NULL) { + printk("MIPSDHA: register /proc/mipsdha failed!\n"); + return 0; + } + + mipsdha_proc_entry->owner = THIS_MODULE; + mipsdha_proc_entry->proc_fops = &mipsdha_fops; + + cmd=CMD_ERR; + return 0; +} + +static ssize_t mipsdha_proc_write (struct file *file, const char *buf, size_t len, loff_t *ppos) +{ + char cmd_gib[]="GET IO BASE"; + char cmd_gpi[]="GET PCI INFO"; + + if (len >= INFO_SIZE) return -ENOMEM; + + if (copy_from_user(info_buf, buf, len)) return -EFAULT; + info_buf[len] = '\0'; + + if (strncmp(info_buf, cmd_gib, sizeof(cmd_gib)-1)==0) { + cmd = CMD_GIB; + return len; + } else if (strncmp(info_buf, cmd_gpi, sizeof(cmd_gpi)-1)==0) { + cmd = CMD_GPI; + return len; + } else { + return -EINVAL; + } +} + +static ssize_t mipsdha_proc_read (struct file *file, char *buf, size_t len, loff_t *ppos) +{ + int info_cnt; + pciinfo_t *pciinfo; + struct pci_dev *dev = NULL; + + switch (cmd) { + default: + printk("MIPSDHA: BUG found in function %s!(cmd=%d)\n", + __FUNCTION__, cmd); + return -EINVAL; + + + case CMD_ERR: + return -EINVAL; + + + case CMD_GIB: + *(unsigned long *)info_buf = + virt_to_phys((void *) mips_io_port_base); + info_cnt=sizeof(unsigned long); + break; + + + case CMD_GPI: + pciinfo = (pciinfo_t *) info_buf; + info_cnt = 0; + for_each_pci_dev(dev) { + + if (info_cnt+sizeof(pciinfo_t)>INFO_SIZE) return -ENOMEM; + + pciinfo->bus = dev->bus->number; + pciinfo->card = PCI_SLOT(dev->devfn); + pciinfo->func = PCI_FUNC(dev->devfn); + + if (pci_read_config_word(dev, PCI_COMMAND, &pciinfo->command) + != PCIBIOS_SUCCESSFUL) { + printk("MIPSDHA: BUG found in function %s!\n", + __FUNCTION__); + pciinfo->command=0; + } + + pciinfo->vendor = dev->vendor; + pciinfo->device = dev->device; + + pciinfo->base0 = (dev->resource[0]).start; + pciinfo->base1 = (dev->resource[1]).start; + pciinfo->base2 = (dev->resource[2]).start; + pciinfo->baserom = (dev->resource[PCI_ROM_RESOURCE]).start; + + pciinfo++; + info_cnt += sizeof(pciinfo_t); + } + break; + } + + if (len < info_cnt) return -ENOMEM; + if (copy_to_user(buf, info_buf, info_cnt)) return -EFAULT; + + return info_cnt; +} + +__initcall(mipsdha_proc_init); diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c new file mode 100644 index 0000000..d9a1724 --- /dev/null +++ b/arch/mips/lemote/lm2e/pci.c @@ -0,0 +1,73 @@ +/* + * pci.c + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include + +extern struct pci_ops loongson2e_pci_pci_ops; + +static struct resource loongson2e_pci_mem_resource = { + .name = "LOONGSON2E PCI MEM", + .start = 0x14000000UL, + .end = 0x1fffffffUL, + .flags = IORESOURCE_MEM, +}; + +static struct resource loongson2e_pci_io_resource = { + .name = "LOONGSON2E PCI IO MEM", + .start = 0x00004000UL, + .end = 0x1fffffffUL, + .flags = IORESOURCE_IO, +}; + + +static struct pci_controller loongson2e_pci_controller = { + .pci_ops = &loongson2e_pci_pci_ops, + .io_resource = &loongson2e_pci_io_resource, + .mem_resource = &loongson2e_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_offset = 0x00000000UL, +}; + + +static int __init pcibios_init(void) +{ + extern int pci_probe_only; + + pci_probe_only = 0; + +#ifdef CONFIG_TRACE_BOOT + printk("arch_initcall:pcibios_init\n"); + printk("register_pci_controller : %x\n",&loongson2e_pci_controller); +#endif + register_pci_controller(&loongson2e_pci_controller); + return 0; +} + +arch_initcall(pcibios_init); diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c new file mode 100644 index 0000000..172bd65 --- /dev/null +++ b/arch/mips/lemote/lm2e/prom.c @@ -0,0 +1,112 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include + +#include +#include + +extern char arcs_cmdline[CL_SIZE]; + +extern unsigned long bus_clock; +extern unsigned long cpu_clock; +extern unsigned int memsize,highmemsize; +extern int putDebugChar(unsigned char byte); + +static int argc; +/* pmon passes arguments in 32bit pointers */ +static int * arg; +static int * env; + +const char *get_system_type(void) +{ + return "Lemote Fulong mini-PC board"; +} + +void __init prom_init_cmdline(void) +{ + int i; + /* some 64bit toolchain can't convert int to a pointer correctly */ + long l; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < argc; i++) { + l = (long)arg[i]; + if (strlen(arcs_cmdline) + strlen(((char*)l) + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ((char*)l)); + strcat(arcs_cmdline, " "); + } +} + +void __init prom_init(void) +{ + long l; + argc=fw_arg0; + arg=(int *)fw_arg1; + env=(int *)fw_arg2; + + mips_machgroup = MACH_GROUP_LEMOTE; + mips_machtype = MACH_LEMOTE_FULONG; + + prom_init_cmdline(); + + if((strstr(arcs_cmdline, "console=")) == NULL) + strcat(arcs_cmdline, " console=ttyS0,115200"); + if((strstr(arcs_cmdline, "root=")) == NULL) + strcat(arcs_cmdline, " root=/dev/hda1"); + + l = (long)*env; + while (l!=0) { + if (strncmp("busclock", (char*)l, strlen("busclock")) == 0) { + bus_clock = simple_strtol((char*)l + strlen("busclock="), + NULL, 10); + } + if (strncmp("cpuclock", (char*)l, strlen("cpuclock")) == 0) { + cpu_clock = simple_strtol((char*)l + strlen("cpuclock="), + NULL, 10); + } + if (strncmp("memsize", (char*)l, strlen("memsize")) == 0) { + memsize = simple_strtol((char*)l + strlen("memsize="), + NULL, 10); + } + if (strncmp("highmemsize", (char*)l, strlen("highmemsize")) == 0) { + highmemsize = simple_strtol((char*)l + strlen("highmemsize="), + NULL, 10); + } + env++; + l=(long)*env; + } + if (memsize == 0) + memsize = 256; + + printk("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n", bus_clock, cpu_clock,memsize,highmemsize); +} + +void __init prom_free_prom_memory(void) +{ +} + +void prom_putchar(char c) +{ + putDebugChar(c); +} + diff --git a/arch/mips/lemote/lm2e/reset.c b/arch/mips/lemote/lm2e/reset.c new file mode 100644 index 0000000..4400f8d --- /dev/null +++ b/arch/mips/lemote/lm2e/reset.c @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static void loongson2e_restart(char *command) +{ +#ifdef CONFIG_32BIT + *(unsigned long *)0xbfe00104 &= ~(1<<2); + *(unsigned long *)0xbfe00104 |= (1<<2); +#else + *(unsigned long *)0xffffffffbfe00104 &= ~(1<<2); + *(unsigned long *)0xffffffffbfe00104 |= (1<<2); +#endif + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); +} + +static void loongson2e_halt(void) +{ + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); + while(1); +} + +static void loongson2e_power_off(void) +{ + loongson2e_halt(); +} + +void mips_reboot_setup(void) +{ + _machine_restart = loongson2e_restart; + _machine_halt = loongson2e_halt; + pm_power_off = loongson2e_power_off; +} diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c new file mode 100644 index 0000000..d75f00e --- /dev/null +++ b/arch/mips/lemote/lm2e/setup.c @@ -0,0 +1,143 @@ +/* + * BRIEF MODULE DESCRIPTION + * setup.c - board dependent boot routines + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_VT +#include +#include +#endif + +extern void mips_reboot_setup(void); + +#ifdef CONFIG_64BIT +#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p))) +#else +#define PTR_PAD(p) (p) +#endif + + +unsigned long cpu_clock; +unsigned long bus_clock; +unsigned int memsize; +unsigned int highmemsize = 0; + + +void __init plat_timer_setup(struct irqaction *irq) +{ + setup_irq(MIPS_CPU_IRQ_BASE + 7, irq); +} + +static void __init loongson2e_time_init(void) +{ + /* setup mips r4k timer */ + mips_hpt_frequency = cpu_clock / 2; +} + +static unsigned long __init mips_rtc_get_time(void) +{ + return mc146818_get_cmos_time(); +} + +void (*__wbflush)(void); +static void wbflush_loongson2e(void) +{ + *(volatile unsigned long *)CKSEG1; + asm(".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set mips3\n\t" + "sync\n\t" + "nop\n\t" + ".set\tpop\n\t" + ".set mips0\n\t"); +} + +void __init plat_mem_setup(void) +{ + set_io_port_base(PTR_PAD(0xbfd00000)); + + ioport_resource.start = 0; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0; + iomem_resource.end = 0xffffffff; + + mips_reboot_setup(); + + board_time_init = loongson2e_time_init; + rtc_mips_get_time = mips_rtc_get_time; + + __wbflush = wbflush_loongson2e; + + //add_memory_region(0x100000, (memsize<<20) - 0x100000, BOOT_MEM_RAM); + add_memory_region(0x0, (memsize<<20), BOOT_MEM_RAM); +#ifdef CONFIG_64BIT + if (highmemsize > 0) { + add_memory_region(0x10000000, 0x10000000, BOOT_MEM_RESERVED); + add_memory_region(0x20000000, highmemsize<<20, BOOT_MEM_RAM); + } +#endif + +#ifdef CONFIG_VT +#if defined(CONFIG_VGA_CONSOLE) + conswitchp = &vga_con; + + screen_info = (struct screen_info) { + 0, 25, /* orig-x, orig-y */ + 0, /* unused */ + 0, /* orig-video-page */ + 0, /* orig-video-mode */ + 80, /* orig-video-cols */ + 0,0,0, /* ega_ax, ega_bx, ega_cx */ + 25, /* orig-video-lines */ + VIDEO_TYPE_VGAC, /* orig-video-isVGA */ + 16 /* orig-video-points */ + }; +#elif defined(CONFIG_DUMMY_CONSOLE) + conswitchp = &dummy_con; +#endif +#endif + +} + diff --git a/arch/mips/pci/fixup-lm2e.c b/arch/mips/pci/fixup-lm2e.c new file mode 100644 index 0000000..113f5f1 --- /dev/null +++ b/arch/mips/pci/fixup-lm2e.c @@ -0,0 +1,255 @@ +/* + * fixup-lm2e.c + * + * Copyright (C) 2004 ICT CAS + * Author: Li xiaoyu, ICT CAS + * lixy@ict.ac.cn + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + unsigned int val; + if (PCI_SLOT(dev->devfn) == 4) { /* wireless card(notebook) */ + dev->irq = BONITO_IRQ_BASE + 26; + (void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + return dev->irq; + } else if (PCI_SLOT(dev->devfn) == 5) { /* via686b */ + switch (PCI_FUNC(dev->devfn)) { + case 2: + dev->irq = 10; + break; + case 3: + dev->irq = 11; + break; + case 5: + dev->irq = 9; + break; + } + (void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + return dev->irq; + }else if (PCI_SLOT(dev->devfn) == 6) { /* radeon 7000 */ + dev->irq = BONITO_IRQ_BASE + 27; + (void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + return dev->irq; + }else if (PCI_SLOT(dev->devfn) == 7) { /* 8139 */ + dev->irq = BONITO_IRQ_BASE + 26; + (void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + return dev->irq; + } else if (PCI_SLOT(dev->devfn) == 8) { /* nec usb */ + switch (PCI_FUNC(dev->devfn)) { + case 0: + dev->irq = BONITO_IRQ_BASE + 26; + break; + case 1: + dev->irq = BONITO_IRQ_BASE + 27; + dev->irq = 11; + break; + case 2: + dev->irq = BONITO_IRQ_BASE + 28; + break; + } + pci_read_config_dword(dev, 0xe0, &val); + pci_write_config_dword(dev, 0xe0, (val & ~7) | 0x4); + pci_write_config_dword(dev, 0xe4, 1<<5); + pci_write_config_dword(dev, PCI_INTERRUPT_LINE, dev->irq); + return dev->irq; + } else return 0; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + + +static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) +{ + unsigned char c; + + printk("via686b fix: ISA bridge\n"); + + /* Enable I/O Recovery time */ + pci_write_config_byte(pdev, 0x40, 0x08); + + /* Enable ISA refresh */ + pci_write_config_byte(pdev, 0x41, 0x01); + + /* disable ISA line buffer */ + pci_write_config_byte(pdev, 0x45, 0x00); + + /* Gate INTR, and flush line buffer */ + pci_write_config_byte(pdev, 0x46, 0xe0); + + /* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */ + //pci_write_config_byte(pdev, 0x47, 0x20); + /* enable PCI Delay Transaction, Enable EISA ports 4D0/4D1. + * enable time-out timer + */ + pci_write_config_byte(pdev, 0x47, 0xe6); + + /* enable level trigger on pci irqs: 9,10,11,13 */ + /* important! without this PCI interrupts won't work */ + outb(0x2e,0x4d1); + + /* 512 K PCI Decode */ + pci_write_config_byte(pdev, 0x48, 0x01); + + /* Wait for PGNT before grant to ISA Master/DMA */ + pci_write_config_byte(pdev, 0x4a, 0x84); + + /* Plug'n'Play */ + /* Parallel DRQ 3, Floppy DRQ 2 (default) */ + pci_write_config_byte(pdev, 0x50, 0x0e); + + /* IRQ Routing for Floppy and Parallel port */ + /* IRQ 6 for floppy, IRQ 7 for parallel port */ + pci_write_config_byte(pdev, 0x51, 0x76); + + /* IRQ Routing for serial ports (take IRQ 3 and 4) */ + pci_write_config_byte(pdev, 0x52, 0x34); + + /* All IRQ's level triggered. */ + pci_write_config_byte(pdev, 0x54, 0x00); + + + /* route PIRQA-D irq */ + pci_write_config_byte(pdev,0x55, 0x90); /* bit 7-4, PIRQA */ + pci_write_config_byte(pdev,0x56, 0xba); /* bit 7-4, PIRQC; 3-0, PIRQB */ + pci_write_config_byte(pdev,0x57, 0xd0); /* bit 7-4, PIRQD */ + + /* enable function 5/6, audio/modem */ + pci_read_config_byte(pdev,0x85, &c); + c &= ~(0x3<<2); + pci_write_config_byte(pdev,0x85,c); + + printk("via686b fix: ISA bridge done\n"); +} + + +static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) +{ + printk("via686b fix: IDE\n"); + + /* Modify IDE controller setup */ + pci_write_config_byte(pdev,PCI_LATENCY_TIMER, 48); + pci_write_config_byte(pdev, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER); + pci_write_config_byte(pdev, 0x40, 0x0b); + /* legacy mode */ + pci_write_config_byte(pdev, 0x42, 0x09); +#if 1 /* play safe, otherwise we may see notebook's usb keyboard lockup */ + /* disable read prefetch/write post buffers */ + pci_write_config_byte(pdev, 0x41, 0x02); //0xf2); + + /* use 3/4 as fifo thresh hold */ + pci_write_config_byte(pdev, 0x43, 0x0a);//qqqw + + pci_write_config_byte(pdev, 0x44, 0x00); + + pci_write_config_byte(pdev, 0x45, 0x00); +#else + pci_write_config_byte(pdev, 0x41, 0xc2); + pci_write_config_byte(pdev, 0x43, 0x35); + pci_write_config_byte(pdev, 0x44, 0x1c); + + pci_write_config_byte(pdev, 0x45, 0x10); +#endif + + printk("via686b fix: IDE done\n"); +} + +static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev) +{ + unsigned int val; + unsigned char c; + + /* enable IO */ + pci_write_config_byte(pdev, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER); + pci_read_config_dword(pdev, 0x4, &val); + pci_write_config_dword(pdev, 0x4, val | 1); + + /* route ac97 IRQ */ + pci_write_config_byte(pdev, 0x3c, 9); + pdev->irq = 9; + printk("ac97 interrupt = 9\n"); + + pci_read_config_byte(pdev, 0x8, &c); + printk("ac97 rev=%d\n",c); + + /* link control: enable link & SGD PCM output */ + pci_write_config_byte(pdev, 0x41, 0xcc); + + /* disable game port, FM, midi, sb, enable write to reg2c-2f */ + pci_write_config_byte(pdev, 0x42, 0x20); + + printk("Setting sub-vendor ID & device ID\n"); + + /* we are using Avance logic codec */ + pci_write_config_word(pdev, 0x2c, 0x1005); + pci_write_config_word(pdev, 0x2e, 0x4710); + pci_read_config_dword(pdev, 0x2c, &val); + printk("sub vendor-device id=%x\n",val); + + pci_write_config_byte(pdev, 0x42, 0x0); +} + +static void __init loongson2e_fixup_pcimap(struct pci_dev *pdev) +{ + Bonito; + static int first = 1; + + (void)pdev; + if (first) first = 0; else return; + + /* local to PCI mapping: [256M,512M] -> [256M,512M]; differ from pmon */ + /* + * cpu address space [256M,448M] is window for accessing pci space + * we set pcimap_lo[0,1,2] to map it to pci space [256M,448M] + * pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0 + */ + /* 1,00 0110 ,0001 01,00 0000 */ + BONITO_PCIMAP = 0x46140; + //1, 00 0010, 0000,01, 00 0000 + //BONITO_PCIMAP = 0x42040; + + /* + * PCI to local mapping: [2G,2G+256M] -> [0,256M] + */ + BONITO_PCIBASE0 = 0x80000000; + BONITO_PCIBASE1 = 0x00800000; + BONITO_PCIBASE2 = 0x90000000; + +} + +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, loongson2e_fixup_pcimap); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,loongson2e_686b_func0_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,loongson2e_686b_func1_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5,loongson2e_686b_func5_fixup); + diff --git a/arch/mips/pci/ops-lm2e.c b/arch/mips/pci/ops-lm2e.c new file mode 100644 index 0000000..c379241 --- /dev/null +++ b/arch/mips/pci/ops-lm2e.c @@ -0,0 +1,150 @@ +/* + * ops-lm2e.c + * + * Copyright (C) 2004 ICT CAS + * Author: Li xiaoyu, ICT CAS + * lixy@ict.ac.cn + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include + +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +static inline void +bflush (void) +{ + Bonito; + /* flush Bonito register writes */ + (void) BONITO_PCICMD; +} +static int lm2e_pci_config_access(unsigned char access_type, + struct pci_bus *bus, unsigned int devfn, int where, u32 * data) +{ + Bonito; + + unsigned char busnum = bus->number; + + u_int32_t addr, type; + void *addrp; + int device = devfn >> 3; + int function = devfn & 0x7; + int reg = where & ~3; + + if (busnum == 0) { + /* Type 0 configuration on onboard PCI bus */ + if (device > 20 || function > 7) { + *data = -1; /* device out of range */ + return PCIBIOS_DEVICE_NOT_FOUND; + } + addr = (1 << (device+11)) | (function << 8) | reg; + type = 0; + } else { + /* Type 1 configuration on offboard PCI bus */ + if (device > 31 || function > 7) { + *data = -1; /* device out of range */ + return PCIBIOS_DEVICE_NOT_FOUND; + } + addr = (busnum << 16) | (device << 11) | (function << 8) | reg; + type = 0x10000; + } + + /* clear aborts */ + BONITO_PCICMD |= BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT; + + BONITO_PCIMAP_CFG = (addr >> 16) | type; + bflush (); + + addrp = (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (addr & 0xffff)); + if (access_type == PCI_ACCESS_WRITE){ + *(volatile unsigned int *)addrp = cpu_to_le32(*data); + }else { + *data = le32_to_cpu(*(volatile unsigned int *)addrp); + } + if (BONITO_PCICMD & (BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT)) { + BONITO_PCICMD |= BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT; + *data = -1; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return PCIBIOS_SUCCESSFUL; + +} + + +static int lm2e_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + u32 data = 0; + + if (lm2e_pci_config_access(PCI_ACCESS_READ, bus, devfn, where,&data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + + +static int lm2e_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data = 0; + + if (size == 4) + data = val; + else { + if (lm2e_pci_config_access(PCI_ACCESS_READ, bus, devfn,where, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + } + + if (lm2e_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where,&data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops loongson2e_pci_pci_ops = { + .read = lm2e_pci_pcibios_read, + .write = lm2e_pci_pcibios_write +}; diff --git a/include/asm-mips/mach-lemote/bonito.h b/include/asm-mips/mach-lemote/bonito.h new file mode 100644 index 0000000..f453587 --- /dev/null +++ b/include/asm-mips/mach-lemote/bonito.h @@ -0,0 +1,395 @@ +/* + * Based on Algorithmics header + */ + +#ifndef _BONITO_H +#define _BONITI_H + +#ifdef __ASSEMBLER__ + +/* offsets from base register */ +#define BONITO(x) (x) + +#else /* !__ASSEMBLER */ + +/* offsets from base pointer, this construct allows optimisation */ +/* static char * const _bonito = PA_TO_KVA1(BONITO_BASE); */ +#define BONITO(x) *(volatile unsigned int *)(_bonito + (x)) + +#endif /* __ASSEMBLER__ */ + + +#define BONITO_BOOT_BASE 0x1fc00000 +#define BONITO_BOOT_SIZE 0x00100000 +#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) +#define BONITO_FLASH_BASE 0x1c000000 +#define BONITO_FLASH_SIZE 0x03000000 +#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) +#define BONITO_SOCKET_BASE 0x1f800000 +#define BONITO_SOCKET_SIZE 0x00400000 +#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) +#define BONITO_REG_BASE 0x1fe00000 +#define BONITO_REG_SIZE 0x00040000 +#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) +#define BONITO_DEV_BASE 0x1ff00000 +#define BONITO_DEV_SIZE 0x00100000 +#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) +#define BONITO_PCILO_BASE 0x10000000 +#define BONITO_PCILO_SIZE 0x0c000000 +#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) +#define BONITO_PCILO0_BASE 0x10000000 +#define BONITO_PCILO1_BASE 0x14000000 +#define BONITO_PCILO2_BASE 0x18000000 +#define BONITO_PCIHI_BASE 0x20000000 +#define BONITO_PCIHI_SIZE 0x20000000 +#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) +#define BONITO_PCIIO_BASE 0x1fd00000 +#define BONITO_PCIIO_SIZE 0x00100000 +#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) +#define BONITO_PCICFG_BASE 0x1fe80000 +#define BONITO_PCICFG_SIZE 0x00080000 +#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) + + +/* Bonito Register Bases */ + +#define BONITO_PCICONFIGBASE 0x00 +#define BONITO_REGBASE 0x100 + + +/* PCI Configuration Registers */ + +#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) +#define BONITO_PCIDID BONITO_PCI_REG(0x00) +#define BONITO_PCICMD BONITO_PCI_REG(0x04) +#define BONITO_PCICLASS BONITO_PCI_REG(0x08) +#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c) +#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) +#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) +#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) +#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30) +#define BONITO_PCIINT BONITO_PCI_REG(0x3c) + +#define BONITO_PCICMD_PERR 0x80000000 +#define BONITO_PCICMD_SERR 0x40000000 +#define BONITO_PCICMD_MABORT 0x20000000 +#define BONITO_PCICMD_MTABORT 0x10000000 +#define BONITO_PCICMD_TABORT 0x08000000 +#define BONITO_PCICMD_MPERR 0x01000000 +#define BONITO_PCICMD_PERRRESPEN 0x00000040 +#define BONITO_PCICMD_ASTEPEN 0x00000080 +#define BONITO_PCICMD_SERREN 0x00000100 +#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00 +#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8 + + + + +/* 1. Bonito h/w Configuration */ +/* Power on register */ + +#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00) + +#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000 +#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000 +#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000 +#define BONITO_BONPONCFG_CPUBIGEND 0x00004000 +#define BONITO_BONPONCFG_CPUPARITY 0x00002000 +#define BONITO_BONPONCFG_CPUTYPE 0x00000007 +#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0 +#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008 +#define BONITO_BONPONCFG_IS_ARBITER 0x00000010 +#define BONITO_BONPONCFG_ROMBOOT 0x000000c0 +#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6 + +#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) + +#define BONITO_PCIMAP_WINSIZE (1<<26) +#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) +#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) + +/* pcimembaseCfg */ + +#define BONITO_PCIMEMBASECFG_MASK 0xf0000000 +#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f +#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0 +#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0 +#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5 +#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400 +#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800 + +#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000 +#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12 +#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000 +#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17 +#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000 +#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000 + +#define BONITO_PCIMEMBASECFG_ASHIFT 23 +#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff +#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) +#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) + +#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) + + +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) + +#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ + (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ + (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ + ) + +/* PCICmd */ + +#define BONITO_PCICMD_MEMEN 0x00000002 +#define BONITO_PCICMD_MSTREN 0x00000004 + +#define Bonito static char * const _bonito = (char * const )CKSEG1ADDR(BONITO_REG_BASE) + +#define BONITO_IRQ_BASE 32 + +#endif /* !_BONITO_H */ diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h new file mode 100644 index 0000000..1df8b4d --- /dev/null +++ b/include/asm-mips/mach-lemote/dma-coherence.h @@ -0,0 +1,43 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Ralf Baechle + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + */ +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H + +struct device; + +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, + size_t size) +{ + return virt_to_phys(addr) | 0x80000000; +} + +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, + struct page *page) +{ + return page_to_phys(page) | 0x80000000; +} + +static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) +{ + return dma_addr & 0x7fffffff; +} + +static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) +{ +} + +static inline int plat_device_is_coherent(struct device *dev) +{ + return 0; +} + +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h new file mode 100644 index 0000000..7850f89 --- /dev/null +++ b/include/asm-mips/mach-lemote/mc146818rtc.h @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * + * RTC routines for PC style attached Dallas chip. + */ +#ifndef __ASM_MACH_GENERIC_MC146818RTC_H +#define __ASM_MACH_GENERIC_MC146818RTC_H + +#include + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ 8 + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + return inb_p(RTC_PORT(1)); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + outb_p(data, RTC_PORT(1)); +} + +#define RTC_ALWAYS_BCD 0 + +#ifndef mc146818_decode_year +#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) +#endif + +#endif /* __ASM_MACH_GENERIC_MC146818RTC_H */ -- 1.4.4.4 ------MIME delimiter for sendEmail-892146.067301841-- From zhangfx@lemote.com Wed Apr 4 15:35:41 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:35:45 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:21735 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20021934AbXDDObU (ORCPT ); Wed, 4 Apr 2007 15:31:20 +0100 Received: (qmail 16908 invoked by uid 511); 4 Apr 2007 14:30:20 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:20 -0000 Message-ID: <510138.627930672-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 3/16] Kconfig update for lemote fulong mini-PC Date: Wed, 4 Apr 2007 14:38:18 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-661401.500533433" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14802 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-661401.500533433 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- arch/mips/Kconfig | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 338bfa3..cedb0fa 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -16,6 +16,26 @@ choice prompt "System type" default SGI_IP22 +config LEMOTE_FULONG + bool "Support for Lemote's fulong mini-PC" + select SYS_HAS_CPU_LOONGSON2 + select DMA_NONCOHERENT + select BOOT_ELF32 + select BOARD_SCACHE + select HW_HAS_PCI + select I8259 + select ISA + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + select GENERIC_HARDIRQS_NO__DO_IRQ + help + Lemote Fulong mini-PC board, which uses Chinese Loongson-2E CPU and a fpga north bridge + + config MIPS_MTX1 bool "4G Systems MTX-1 board" select DMA_NONCOHERENT @@ -1142,6 +1162,13 @@ choice prompt "CPU type" default CPU_R4X00 +config CPU_LOONGSON2 + bool "LOONGSON2" + depends on SYS_HAS_CPU_LOONGSON2 + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -1352,6 +1379,9 @@ config CPU_SB1 endchoice +config SYS_HAS_CPU_LOONGSON2 + bool + config SYS_HAS_CPU_MIPS32_R1 bool @@ -1681,6 +1711,13 @@ config CPU_HAS_SMARTMIPS config CPU_HAS_WB bool +config 64BIT_CONTEXT + bool "Save 64bit integer registers" if CPU_LOONGSON2 && 32BIT + help + Loongson2 CPU is 64bit , when used in 32BIT mode, its integer registers + can still be accessed as 64bit, mainly for multimedia instructions. We must have + all 64bit save/restored to make sure those instructions to get correct result. + # # Vectored interrupt mode is an R2 feature # -- 1.4.4.4 ------MIME delimiter for sendEmail-661401.500533433-- From zhangfx@lemote.com Wed Apr 4 15:36:05 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:36:09 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:20455 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20021982AbXDDOb0 (ORCPT ); Wed, 4 Apr 2007 15:31:26 +0100 Received: (qmail 16942 invoked by uid 511); 4 Apr 2007 14:30:21 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:21 -0000 Message-ID: <418767.882601486-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 14/16] tlb handling support for Loongson2 processor Date: Wed, 4 Apr 2007 14:38:20 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-680318.29952179" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14803 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-680318.29952179 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- arch/mips/mm/tlb-r4k.c | 21 ++++++++++++++++++++- arch/mips/mm/tlbex.c | 8 +++++--- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 65160d4..cf1c893 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -48,6 +48,20 @@ extern void build_tlb_refill_handler(void); #endif /* CONFIG_MIPS_MT_SMTC */ +#if defined(CONFIG_CPU_LOONGSON2) +/* LOONGSON2 has a 4 entry itlb which is a subset of dtlb, unfortrunately, itlb is not totally transparent to software. + */ +#define FLUSH_ITLB write_c0_diag(4); + +#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); } + +#else + +#define FLUSH_ITLB +#define FLUSH_ITLB_VM(vma) + +#endif + void local_flush_tlb_all(void) { unsigned long flags; @@ -73,6 +87,7 @@ void local_flush_tlb_all(void) } tlbw_use_hazard(); write_c0_entryhi(old_ctx); + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -136,6 +151,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, } else { drop_mmu_context(mm, cpu); } + FLUSH_ITLB; EXIT_CRITICAL(flags); } } @@ -178,6 +194,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) } else { local_flush_tlb_all(); } + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -210,6 +227,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) finish: write_c0_entryhi(oldpid); + FLUSH_ITLB_VM(vma); EXIT_CRITICAL(flags); } } @@ -241,7 +259,7 @@ void local_flush_tlb_one(unsigned long page) tlbw_use_hazard(); } write_c0_entryhi(oldpid); - + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -293,6 +311,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) else tlb_write_indexed(); tlbw_use_hazard(); + FLUSH_ITLB_VM(vma); EXIT_CRITICAL(flags); } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 492c518..e1a58d9 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -893,6 +893,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case CPU_4KSC: case CPU_20KC: case CPU_25KF: + case CPU_LOONGSON2: tlbw(p); break; @@ -1276,7 +1277,8 @@ static void __init build_r4000_tlb_refill_handler(void) * need three, with the second nop'ed and the third being * unused. */ -#ifdef CONFIG_32BIT + /* Loongson2 ebase is different than r4k, we have more space */ +#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) if ((p - tlb_handler) > 64) panic("TLB refill handler space exceeded"); #else @@ -1289,7 +1291,7 @@ static void __init build_r4000_tlb_refill_handler(void) /* * Now fold the handler in the TLB refill handler space. */ -#ifdef CONFIG_32BIT +#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) f = final_handler; /* Simplest case, just copy the handler. */ copy_handler(relocs, labels, tlb_handler, p, f); @@ -1336,7 +1338,7 @@ static void __init build_r4000_tlb_refill_handler(void) final_len); f = final_handler; -#ifdef CONFIG_64BIT +#if defined(CONFIG_64BIT) && !defined(CONFIG_CPU_LOONGSON2) if (final_len > 32) final_len = 64; else -- 1.4.4.4 ------MIME delimiter for sendEmail-680318.29952179-- From zhangfx@lemote.com Wed Apr 4 15:36:29 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:36:32 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:22247 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022098AbXDDObf (ORCPT ); Wed, 4 Apr 2007 15:31:35 +0100 Received: (qmail 16939 invoked by uid 511); 4 Apr 2007 14:30:21 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:21 -0000 Message-ID: <680071.485086472-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 13/16] cache support for Loongson2 processor Date: Wed, 4 Apr 2007 14:38:20 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-232529.466579766" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14804 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-232529.466579766 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- arch/mips/mm/c-r4k.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 54 insertions(+), 0 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index df04a31..19762b5 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -335,6 +335,10 @@ static void r4k_flush_cache_all(void) static inline void local_r4k___flush_cache_all(void * args) { +#if defined(CONFIG_CPU_LOONGSON2) + r4k_blast_scache(); + return; +#endif r4k_blast_dcache(); r4k_blast_icache(); @@ -848,6 +852,26 @@ static void __init probe_pcache(void) c->options |= MIPS_CPU_PREFETCH; break; + case CPU_LOONGSON2: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + if (prid & 0x3) { + c->icache.ways = 4; + } else { + c->icache.ways = 2; + } + c->icache.waybit= 0; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + if (prid & 0x3) { + c->dcache.ways = 4; + } else { + c->dcache.ways = 2; + } + c->dcache.waybit = 0; + break; + default: if (!(config & MIPS_CONF_M)) panic("Don't know how to probe P-caches on this cpu."); @@ -963,6 +987,11 @@ static void __init probe_pcache(void) break; } +#ifdef CONFIG_CPU_LOONGSON2 + /* LOONGSON2 has 4 way icache, but when using indexed cache op, one op will act on all 4 ways*/ + c->icache.ways = 1; +#endif + printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", icache_size >> 10, cpu_has_vtag_icache ? "virtually tagged" : "physically tagged", @@ -1036,6 +1065,25 @@ static int __init probe_scache(void) return 1; } +#if defined(CONFIG_CPU_LOONGSON2) +static void __init loongson2_sc_init(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + scache_size = 512*1024; + c->scache.linesz = 32; + c->scache.ways = 4; + c->scache.waybit = 0; + c->scache.waysize = scache_size / (c->scache.ways); + c->scache.sets = scache_size /(c->scache.linesz * c->scache.ways); + printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", + scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); + + c->options |= MIPS_CPU_INCLUSIVE_CACHES; + return; +} +#endif + extern int r5k_sc_init(void); extern int rm7k_sc_init(void); extern int mips_sc_init(void); @@ -1085,6 +1133,12 @@ static void __init setup_scache(void) #endif return; +#if defined(CONFIG_CPU_LOONGSON2) + case CPU_LOONGSON2: + loongson2_sc_init(); + return; +#endif + default: if (c->isa_level == MIPS_CPU_ISA_M32R1 || c->isa_level == MIPS_CPU_ISA_M32R2 || -- 1.4.4.4 ------MIME delimiter for sendEmail-232529.466579766-- From zhangfx@lemote.com Wed Apr 4 15:36:52 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Apr 2007 15:36:56 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:21223 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022094AbXDDOcD (ORCPT ); Wed, 4 Apr 2007 15:32:03 +0100 Received: (qmail 16920 invoked by uid 511); 4 Apr 2007 14:30:20 -0000 Received: from unknown (HELO heart.lemote.com) (192.168.2.206) by lemote.com with SMTP; 4 Apr 2007 14:30:20 -0000 Message-ID: <215567.009846808-sendEmail@heart> From: "zhangfx@lemote.com" To: "linux-mips@linux-mips.org" Subject: [PATCH 7/16] add Loongson processor definitions Date: Wed, 4 Apr 2007 14:38:19 +0000 X-Mailer: sendEmail-1.55 MIME-Version: 1.0 Content-Type: multipart/related; boundary="----MIME delimiter for sendEmail-434393.153599562" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14805 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. To properly display this message you need a MIME-Version 1.0 compliant Email program. ------MIME delimiter for sendEmail-434393.153599562 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Signed-off-by: Fuxin Zhang --- include/asm-mips/cpu.h | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index d38fdbf..d289359 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -89,6 +89,8 @@ #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 +#define PRID_IMP_LOONGSON1 0x4200 +#define PRID_IMP_LOONGSON2 0x6300 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -200,7 +202,10 @@ #define CPU_SB1A 62 #define CPU_74K 63 #define CPU_R14000 64 -#define CPU_LAST 64 +#define CPU_LOONGSON1 65 +#define CPU_LOONGSON2 66 + +#define CPU_LAST 66 /* * ISA Level encodings -- 1.4.4.4 ------MIME delimiter for sendEmail-434393.153599562-- From sathesh_edara2003@yahoo.co.in Fri Apr 6 09:51:49 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Apr 2007 09:51:51 +0100 (BST) Received: from web7912.mail.in.yahoo.com ([202.86.4.88]:62570 "HELO web7912.mail.in.yahoo.com") by ftp.linux-mips.org with SMTP id S20022591AbXDFIvt (ORCPT ); Fri, 6 Apr 2007 09:51:49 +0100 Received: (qmail 73446 invoked by uid 60001); 6 Apr 2007 08:50:42 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.co.in; h=X-YMail-OSG:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-ID; b=LmZfybKhM1w8rjDBKB1NPYVjwm5XQddLxaS/HlNaGVD/kvxfBrSchcnjikXAlu+5C40k5+gkN5JbITp0ZxoO056TFEBI4w/Q4T5ZagRirKA5yK35gJz/c7MO8JrQVCS7vb6ZZeKf/NNHYLqQdfju/QKdRXmQTKMlZAe/QXn7uzg=; X-YMail-OSG: dvY71H4VM1nVwADJANrKHn8kEOtSAos14H8Xjh.B9dHIsfenc6Vt1OyrluGeIcj24LFV.GiUxz2Ug8zlnNt8WbPUCEEZJXNkpJEGflxXH_D5itj0XnPazr3CQ5tnow-- Received: from [199.239.167.162] by web7912.mail.in.yahoo.com via HTTP; Fri, 06 Apr 2007 09:50:41 BST Date: Fri, 6 Apr 2007 09:50:41 +0100 (BST) From: sathesh babu Subject: Back ground user process display issue on linux-2.6.18 kernel To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="0-259282827-1175849441=:72711" Content-Transfer-Encoding: 8bit Message-ID: <990986.72711.qm@web7912.mail.in.yahoo.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14806 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sathesh_edara2003@yahoo.co.in Precedence: bulk X-list: linux-mips --0-259282827-1175849441=:72711 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi , We are running a sample user application "samp_app" in the background using "samp_app &" form rcS script file. We are using linux-2.6.18 kernel. In this application code we have put some debug messages to display it on console using printf() function. We are unable to see any of these debug messages on the console. When we run the same application in the foreground (without &) from same rcS script, we are getting these messages on console. WE RAN THE SAME APPLICATION AS A BACKGROUND PROCESS ('samp_app &') ON LINUX-2.6.12 KERNEL. WE ARE ABLE TO GET THESE DEBUG PRINTS. Could you please tell us what might be the reason for this behavior on linux-2.6.18. Did we miss any configuration option in the 2.6.18 kernel. Note that we are using same toolchain for both the kernel versions. Thanks in Advance. Regards, Sathesh. --------------------------------- Here’s a new way to find what you're looking for - Yahoo! Answers --0-259282827-1175849441=:72711 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit
Hi ,
We are running a sample user application "samp_app" in the background using "samp_app &" form rcS script file.
We are using linux-2.6.18 kernel.
In this application code we have put some debug messages to display it on console using printf() function.
We are unable to see any of these debug messages on the console.
When we run the same application in the foreground (without &) from same rcS script, we are getting these messages on console.
 
WE RAN THE SAME APPLICATION AS A BACKGROUND PROCESS ('samp_app &') ON LINUX-2.6.12 KERNEL. WE ARE ABLE TO GET THESE DEBUG PRINTS.
 
Could you please tell us what might be the reason for this behavior on linux-2.6.18.
Did we miss any configuration option in the 2.6.18 kernel.
 
Note that we are using same toolchain for both the kernel versions.
 
Thanks in Advance.
 
Regards,
Sathesh.

Here’s a new way to find what you're looking for - Yahoo! Answers --0-259282827-1175849441=:72711-- From harsh512@yahoo.com Sat Apr 7 23:00:22 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Apr 2007 23:00:27 +0100 (BST) Received: from web53812.mail.re2.yahoo.com ([206.190.39.55]:44889 "HELO web53812.mail.re2.yahoo.com") by ftp.linux-mips.org with SMTP id S20022613AbXDGWAW (ORCPT ); Sat, 7 Apr 2007 23:00:22 +0100 Received: (qmail 42482 invoked by uid 60001); 7 Apr 2007 21:59:15 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=X-YMail-OSG:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-ID; b=KUbXwErGz5/XYep0feSfAgphBJo0VIOX63tguoAnmqKh5JfGFgl3HIlLEo3FI6mglqvOK6z7Fuz3GpdrRXIr0n6eGJxWSNHs3iB2H7TNM9jSk1F8bdn2m+kAS28n5cRfASwtqNejXQP51sz92YaW7+Ijn2cgkqNDhsLSiFWsIcs=; X-YMail-OSG: dH42JW8VM1nOwwHPR8lws9viGLih4Taf3D1nyzi19QtJ5.W3tppJbp62yQRncq7ft891NER_wcpArrrEPyImrCHrWKOnOgdy3LoEWGiZynZau3DyhCBUOfi0dtYN3g-- Received: from [76.192.205.82] by web53812.mail.re2.yahoo.com via HTTP; Sat, 07 Apr 2007 14:59:15 PDT Date: Sat, 7 Apr 2007 14:59:15 -0700 (PDT) From: h h Subject: Describing Physical RAM Map to Linux To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="0-490179268-1175983155=:41507" Content-Transfer-Encoding: 8bit Message-ID: <640437.41507.qm@web53812.mail.re2.yahoo.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14807 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: harsh512@yahoo.com Precedence: bulk X-list: linux-mips --0-490179268-1175983155=:41507 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi, I have a very basic question -- When describing physical memory to the kernel in prom_init(), should we describe the physical memory region where kernel is loaded or leave it out? We are using add_memory_region() call to describe physical memory to the kernel. If we do describe the memory region where kernel is loaded, how will kernel know not to use these pages for User processes? We are using 2.6.16 on Cavium/Octeon based platform. Thanks, JJ --------------------------------- Don't get soaked. Take a quick peek at the forecast with theYahoo! Search weather shortcut. --0-490179268-1175983155=:41507 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi,

I have a very basic question -- When describing physical memory to the kernel in
prom_init(), should we describe the physical memory region where kernel is loaded or leave it out?  We are using add_memory_region() call to describe physical memory to the kernel.  If we do describe the memory region where kernel is loaded, how will kernel know not to use these pages for User processes?

We are using 2.6.16 on Cavium/Octeon based platform.

Thanks,
JJ


Don't get soaked. Take a quick peek at the forecast
with theYahoo! Search weather shortcut. --0-490179268-1175983155=:41507-- From tsbogend@alpha.franken.de Sun Apr 8 12:38:11 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Apr 2007 12:38:13 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:40630 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20022051AbXDHLiL (ORCPT ); Sun, 8 Apr 2007 12:38:11 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1HaVfh-0003wA-00 for linux-mips@linux-mips.org; Sun, 08 Apr 2007 13:35:01 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 32808C2238; Sun, 8 Apr 2007 13:28:44 +0200 (CEST) Date: Sun, 8 Apr 2007 13:28:44 +0200 To: linux-mips@linux-mips.org Subject: [PATCH] Register PCI host bridge resource earlier Message-ID: <20070408112844.GA7553@alpha.franken.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.9i From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14808 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Hi, PCI based SNI RM machines have their EISA bus behind an Intel PCI/EISA bridge. So the PCI IO range must start at 0x0000. Changing that will break the PCI bus, because i8259.c already has registered it's IO addresses before the PCI bus gets initialized. Below is a patch, which will register the PCI host bridge resources inside register_pci_controller(). It also changes i8259.c to use insert_region(), because request_resource() will fail, if the IO space of the PIT hanging of the PCI host bridge (maybe passing the resource parent to init_i8259_irqs() is a cleaner fix for that). Signed-off-by: Thomas Bogendoerfer --- diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index f901140..67e01fd 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -77,6 +77,13 @@ pcibios_align_resource(void *data, struct resource *res, void __init register_pci_controller(struct pci_controller *hose) { + if (request_resource(&iomem_resource, hose->mem_resource) < 0) + goto out; + if (request_resource(&ioport_resource, hose->io_resource) < 0) { + release_resource(hose->mem_resource); + goto out; + } + *hose_tail = hose; hose_tail = &hose->next; @@ -87,6 +94,11 @@ void __init register_pci_controller(struct pci_controller *hose) printk(KERN_WARNING "registering PCI controller with io_map_base unset\n"); } + return; + +out: + printk(KERN_WARNING + "Skipping PCI bus scan due to resource conflict\n"); } /* Most MIPS systems have straight-forward swizzling needs. */ @@ -126,11 +138,6 @@ static int __init pcibios_init(void) /* Scan all of the recorded PCI controllers. */ for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { - if (request_resource(&iomem_resource, hose->mem_resource) < 0) - goto out; - if (request_resource(&ioport_resource, hose->io_resource) < 0) - goto out_free_mem_resource; - if (!hose->iommu) PCI_DMA_BUS_IS_PHYS = 1; @@ -149,14 +156,6 @@ static int __init pcibios_init(void) need_domain_info = 1; } } - continue; - -out_free_mem_resource: - release_resource(hose->mem_resource); - -out: - printk(KERN_WARNING - "Skipping PCI bus scan due to resource conflict\n"); } if (!pci_probe_only) diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 9c79703..2345160 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -328,8 +328,8 @@ void __init init_i8259_irqs (void) { int i; - request_resource(&ioport_resource, &pic1_io_resource); - request_resource(&ioport_resource, &pic2_io_resource); + insert_resource(&ioport_resource, &pic1_io_resource); + insert_resource(&ioport_resource, &pic2_io_resource); init_8259A(0); -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From tsbogend@alpha.franken.de Sun Apr 8 12:38:33 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Apr 2007 12:38:36 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:40886 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20022053AbXDHLiL (ORCPT ); Sun, 8 Apr 2007 12:38:11 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1HaVfh-0003wA-01 for linux-mips@linux-mips.org; Sun, 08 Apr 2007 13:35:01 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 4FFADC223A; Sun, 8 Apr 2007 13:34:57 +0200 (CEST) Date: Sun, 8 Apr 2007 13:34:57 +0200 To: linux-mips@linux-mips.org Subject: [PATCH] Change PCI host bridge setup/resources Message-ID: <20070408113457.GB7553@alpha.franken.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.9i From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14809 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips PCI host bridge setup for SNI RM machines with PCI is quite broken, now that Linux does it's resource setup own its own. It will use IO addresses, which are needed by the EISA config detection and assigns PCI memory addresses, which overlap with ISA legacy addresses (video ram). Below is a patch, which changes the way how the PCI memory addresses are used and sets the minimum IO address to give enough IO space for 8 EISA slots). This patch needs the other PCI resource change, I've posted. Signed-off-by: Thomas Bogendoerfer --- diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index 1dfc3f0..00d151f 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c @@ -43,7 +43,7 @@ static struct platform_device pcit_serial8250_device = { }; static struct plat_serial8250_port pcit_cplus_data[] = { - PORT(0x3f8, 4), + PORT(0x3f8, 0), PORT(0x2f8, 3), PORT(0x3e8, 4), PORT(0x2e8, 3), @@ -59,9 +59,9 @@ static struct platform_device pcit_cplus_serial8250_device = { }; static struct resource sni_io_resource = { - .start = 0x00001000UL, + .start = 0x00000000UL, .end = 0x03bfffffUL, - .name = "PCIT IO MEM", + .name = "PCIT IO", .flags = IORESOURCE_IO, }; @@ -92,6 +92,11 @@ static struct resource pcit_io_resources[] = { .name = "dma2", .flags = IORESOURCE_BUSY }, { + .start = 0xcf8, + .end = 0xcfb, + .name = "PCI config addr", + .flags = IORESOURCE_BUSY + }, { .start = 0xcfc, .end = 0xcff, .name = "PCI config data", @@ -100,107 +105,19 @@ static struct resource pcit_io_resources[] = { }; static struct resource sni_mem_resource = { - .start = 0x10000000UL, - .end = 0xffffffffUL, + .start = 0x18000000UL, + .end = 0x1fbfffffUL, .name = "PCIT PCI MEM", .flags = IORESOURCE_MEM }; -/* - * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used - * for other purposes. Be paranoid and allocate all of the before the PCI - * code gets a chance to to map anything else there ... - * - * This leaves the following areas available: - * - * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory - * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory - * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory - * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory - * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory - */ -static struct resource pcit_mem_resources[] = { - { - .start = 0x14000000, - .end = 0x17bfffff, - .name = "PCI IO", - .flags = IORESOURCE_BUSY - }, { - .start = 0x17c00000, - .end = 0x17ffffff, - .name = "Cache Replacement Area", - .flags = IORESOURCE_BUSY - }, { - .start = 0x180a0000, - .end = 0x180bffff, - .name = "Video RAM area", - .flags = IORESOURCE_BUSY - }, { - .start = 0x180c0000, - .end = 0x180fffff, - .name = "ISA Reserved", - .flags = IORESOURCE_BUSY - }, { - .start = 0x19000000, - .end = 0x1fbfffff, - .name = "PCI MEM", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1fc00000, - .end = 0x1fc7ffff, - .name = "Boot PROM", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1fc80000, - .end = 0x1fcfffff, - .name = "Diag PROM", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1fd00000, - .end = 0x1fdfffff, - .name = "X-Bus", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1fe00000, - .end = 0x1fefffff, - .name = "BIOS map", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1ff00000, - .end = 0x1ff7ffff, - .name = "NVRAM / EEPROM", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1fff0000, - .end = 0x1fffefff, - .name = "MAUI ASIC", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1ffff000, - .end = 0x1fffffff, - .name = "MP Agent", - .flags = IORESOURCE_BUSY - }, { - .start = 0x20000000, - .end = 0x9fffffff, - .name = "Main Memory", - .flags = IORESOURCE_BUSY - } -}; - static void __init sni_pcit_resource_init(void) { int i; /* request I/O space for devices used on all i[345]86 PCs */ for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++) - request_resource(&ioport_resource, pcit_io_resources + i); - - /* request mem space for pcimt-specific devices */ - for (i = 0; i < ARRAY_SIZE(pcit_mem_resources); i++) - request_resource(&sni_mem_resource, pcit_mem_resources + i); - - ioport_resource.end = sni_io_resource.end; + request_resource(&sni_io_resource, pcit_io_resources + i); } @@ -209,9 +126,10 @@ extern struct pci_ops sni_pcit_ops; static struct pci_controller sni_pcit_controller = { .pci_ops = &sni_pcit_ops, .mem_resource = &sni_mem_resource, - .mem_offset = 0x10000000UL, + .mem_offset = 0x00000000UL, .io_resource = &sni_io_resource, - .io_offset = 0x00000000UL + .io_offset = 0x00000000UL, + .io_map_base = SNI_PORT_BASE }; static void enable_pcit_irq(unsigned int irq) @@ -262,7 +180,7 @@ static void pcit_hwint0(void) int irq; clear_c0_status(IE_IRQ0); - irq = ffs((pending >> 16) & 0x7f); + irq = ffs((pending >> 16) & 0x3f); if (likely(irq > 0)) do_IRQ (irq + SNI_PCIT_INT_START - 1); @@ -289,6 +207,8 @@ static void sni_pcit_hwint_cplus(void) if (pending & C_IRQ0) pcit_hwint0(); + else if (pending & C_IRQ1) + do_IRQ (MIPS_CPU_IRQ_BASE + 3); else if (pending & C_IRQ2) do_IRQ (MIPS_CPU_IRQ_BASE + 4); else if (pending & C_IRQ3) @@ -317,21 +237,23 @@ void __init sni_pcit_cplus_irq_init(void) mips_cpu_irq_init(); for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) set_irq_chip(i, &pcit_irq_type); - *(volatile u32 *)SNI_PCIT_INT_REG = 0; + *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; sni_hwint = sni_pcit_hwint_cplus; change_c0_status(ST0_IM, IE_IRQ0); - setup_irq (SNI_PCIT_INT_START + 6, &sni_isa_irq); + setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); } void sni_pcit_init(void) { - sni_pcit_resource_init(); rtc_mips_get_time = mc146818_get_cmos_time; rtc_mips_set_time = mc146818_set_rtc_mmss; board_time_init = sni_cpu_time_init; + ioport_resource.end = sni_io_resource.end; #ifdef CONFIG_PCI + PCIBIOS_MIN_IO = 0x9000; register_pci_controller(&sni_pcit_controller); #endif + sni_pcit_resource_init(); } static int __init snirm_pcit_setup_devinit(void) diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c index 8e8593b..9ee208d 100644 --- a/arch/mips/sni/pcimt.c +++ b/arch/mips/sni/pcimt.c @@ -91,7 +91,7 @@ static struct platform_device pcimt_serial8250_device = { }; static struct resource sni_io_resource = { - .start = 0x00001000UL, + .start = 0x00000000UL, .end = 0x03bfffffUL, .name = "PCIMT IO MEM", .flags = IORESOURCE_IO, @@ -132,107 +132,19 @@ static struct resource pcimt_io_resources[] = { }; static struct resource sni_mem_resource = { - .start = 0x10000000UL, - .end = 0xffffffffUL, + .start = 0x18000000UL, + .end = 0x1fbfffffUL, .name = "PCIMT PCI MEM", .flags = IORESOURCE_MEM }; -/* - * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used - * for other purposes. Be paranoid and allocate all of the before the PCI - * code gets a chance to to map anything else there ... - * - * This leaves the following areas available: - * - * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory - * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory - * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory - * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory - * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory - */ -static struct resource pcimt_mem_resources[] = { - { - .start = 0x100a0000, - .end = 0x100bffff, - .name = "Video RAM area", - .flags = IORESOURCE_BUSY - }, { - .start = 0x100c0000, - .end = 0x100fffff, - .name = "ISA Reserved", - .flags = IORESOURCE_BUSY - }, { - .start = 0x14000000, - .end = 0x17bfffff, - .name = "PCI IO", - .flags = IORESOURCE_BUSY - }, { - .start = 0x17c00000, - .end = 0x17ffffff, - .name = "Cache Replacement Area", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1a000000, - .end = 0x1a000003, - .name = "PCI INT Acknowledge", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1fc00000, - .end = 0x1fc7ffff, - .name = "Boot PROM", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1fc80000, - .end = 0x1fcfffff, - .name = "Diag PROM", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1fd00000, - .end = 0x1fdfffff, - .name = "X-Bus", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1fe00000, - .end = 0x1fefffff, - .name = "BIOS map", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1ff00000, - .end = 0x1ff7ffff, - .name = "NVRAM / EEPROM", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1fff0000, - .end = 0x1fffefff, - .name = "ASIC PCI", - .flags = IORESOURCE_BUSY - }, { - .start = 0x1ffff000, - .end = 0x1fffffff, - .name = "MP Agent", - .flags = IORESOURCE_BUSY - }, { - .start = 0x20000000, - .end = 0x9fffffff, - .name = "Main Memory", - .flags = IORESOURCE_BUSY - } -}; - static void __init sni_pcimt_resource_init(void) { int i; /* request I/O space for devices used on all i[345]86 PCs */ for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++) - request_resource(&ioport_resource, pcimt_io_resources + i); - - /* request mem space for pcimt-specific devices */ - for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++) - request_resource(&sni_mem_resource, pcimt_mem_resources + i); - - ioport_resource.end = sni_io_resource.end; + request_resource(&sni_io_resource, pcimt_io_resources + i); } extern struct pci_ops sni_pcimt_ops; @@ -240,9 +152,10 @@ extern struct pci_ops sni_pcimt_ops; static struct pci_controller sni_controller = { .pci_ops = &sni_pcimt_ops, .mem_resource = &sni_mem_resource, - .mem_offset = 0x10000000UL, + .mem_offset = 0x00000000UL, .io_resource = &sni_io_resource, - .io_offset = 0x00000000UL + .io_offset = 0x00000000UL, + .io_map_base = SNI_PORT_BASE }; static void enable_pcimt_irq(unsigned int irq) @@ -363,15 +276,17 @@ void __init sni_pcimt_irq_init(void) void sni_pcimt_init(void) { - sni_pcimt_resource_init(); sni_pcimt_detect(); sni_pcimt_sc_init(); rtc_mips_get_time = mc146818_get_cmos_time; rtc_mips_set_time = mc146818_set_rtc_mmss; board_time_init = sni_cpu_time_init; + ioport_resource.end = sni_io_resource.end; #ifdef CONFIG_PCI + PCIBIOS_MIN_IO = 0x9000; register_pci_controller(&sni_controller); #endif + sni_pcimt_resource_init(); } static int __init snirm_pcimt_setup_devinit(void) -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From sshtylyov@ru.mvista.com Sun Apr 8 13:20:27 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Apr 2007 13:20:28 +0100 (BST) Received: from rtsoft2.corbina.net ([85.21.88.2]:1925 "HELO mail.dev.rtsoft.ru") by ftp.linux-mips.org with SMTP id S20022053AbXDHMU1 (ORCPT ); Sun, 8 Apr 2007 13:20:27 +0100 Received: (qmail 27635 invoked from network); 8 Apr 2007 12:18:59 -0000 Received: from wasted.dev.rtsoft.ru (HELO ?192.168.1.248?) (192.168.1.248) by mail.dev.rtsoft.ru with SMTP; 8 Apr 2007 12:18:59 -0000 Message-ID: <4618DDF0.1020604@ru.mvista.com> Date: Sun, 08 Apr 2007 16:20:00 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Thomas Bogendoerfer CC: linux-mips@linux-mips.org Subject: Re: [PATCH] Register PCI host bridge resource earlier References: <20070408112844.GA7553@alpha.franken.de> In-Reply-To: <20070408112844.GA7553@alpha.franken.de> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14810 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Thomas Bogendoerfer wrote: > PCI based SNI RM machines have their EISA bus behind an Intel PCI/EISA > bridge. So the PCI IO range must start at 0x0000. Changing that will > break the PCI bus, because i8259.c already has registered it's IO > addresses before the PCI bus gets initialized. Below is a patch, > which will register the PCI host bridge resources inside > register_pci_controller(). It also changes i8259.c to use insert_region(), > because request_resource() will fail, if the IO space of the PIT hanging > of the PCI host bridge (maybe passing the resource parent to > init_i8259_irqs() is a cleaner fix for that). First, I don't understand how PIT and PIC resources may intersect. Then, IIUC, using inert_resource() will cause PIT resource be the child of the PIC resource which doesn't make sense either. WBR, Sergei From tsbogend@alpha.franken.de Sun Apr 8 14:15:52 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Apr 2007 14:15:53 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:3773 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20022682AbXDHNPw (ORCPT ); Sun, 8 Apr 2007 14:15:52 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1HaXCE-0004L6-00; Sun, 08 Apr 2007 15:12:42 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id B344FC223A; Sun, 8 Apr 2007 15:12:28 +0200 (CEST) Date: Sun, 8 Apr 2007 15:12:28 +0200 To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Register PCI host bridge resource earlier Message-ID: <20070408131228.GA7819@alpha.franken.de> References: <20070408112844.GA7553@alpha.franken.de> <4618DDF0.1020604@ru.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4618DDF0.1020604@ru.mvista.com> User-Agent: Mutt/1.5.9i From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14811 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Sun, Apr 08, 2007 at 04:20:00PM +0400, Sergei Shtylyov wrote: > Thomas Bogendoerfer wrote: > > >PCI based SNI RM machines have their EISA bus behind an Intel PCI/EISA > >bridge. So the PCI IO range must start at 0x0000. Changing that will > >break the PCI bus, because i8259.c already has registered it's IO > >addresses before the PCI bus gets initialized. Below is a patch, > >which will register the PCI host bridge resources inside > >register_pci_controller(). It also changes i8259.c to use insert_region(), > >because request_resource() will fail, if the IO space of the PIT hanging > >of the PCI host bridge (maybe passing the resource parent to > >init_i8259_irqs() is a cleaner fix for that). > > First, I don't understand how PIT and PIC resources may intersect. Then, oops, I meant PIC resources. > IIUC, using inert_resource() will cause PIT resource be the child of the > PIC resource which doesn't make sense either. the insert_resource will make it child of the PCI resource, which makes perfect sense, because the ISA bus is behind the PCI host bridge. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From sshtylyov@ru.mvista.com Sun Apr 8 14:26:45 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Apr 2007 14:26:47 +0100 (BST) Received: from rtsoft2.corbina.net ([85.21.88.2]:11402 "HELO mail.dev.rtsoft.ru") by ftp.linux-mips.org with SMTP id S20022316AbXDHN0p (ORCPT ); Sun, 8 Apr 2007 14:26:45 +0100 Received: (qmail 28393 invoked from network); 8 Apr 2007 13:25:44 -0000 Received: from wasted.dev.rtsoft.ru (HELO ?192.168.1.248?) (192.168.1.248) by mail.dev.rtsoft.ru with SMTP; 8 Apr 2007 13:25:44 -0000 Message-ID: <4618ED95.6040304@ru.mvista.com> Date: Sun, 08 Apr 2007 17:26:45 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Thomas Bogendoerfer CC: linux-mips@linux-mips.org Subject: Re: [PATCH] Register PCI host bridge resource earlier References: <20070408112844.GA7553@alpha.franken.de> <4618DDF0.1020604@ru.mvista.com> <20070408131228.GA7819@alpha.franken.de> In-Reply-To: <20070408131228.GA7819@alpha.franken.de> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14812 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Thomas Bogendoerfer wrote: >>>PCI based SNI RM machines have their EISA bus behind an Intel PCI/EISA >>>bridge. So the PCI IO range must start at 0x0000. Changing that will >>>break the PCI bus, because i8259.c already has registered it's IO >>>addresses before the PCI bus gets initialized. Below is a patch, >>>which will register the PCI host bridge resources inside >>>register_pci_controller(). It also changes i8259.c to use insert_region(), >>>because request_resource() will fail, if the IO space of the PIT hanging >>>of the PCI host bridge (maybe passing the resource parent to >>>init_i8259_irqs() is a cleaner fix for that). >> First, I don't understand how PIT and PIC resources may intersect. Then, > oops, I meant PIC resources. >>IIUC, using inert_resource() will cause PIT resource be the child of the >>PIC resource which doesn't make sense either. > the insert_resource will make it child of the PCI resource, which makes > perfect sense, because the ISA bus is behind the PCI host bridge. If you read the comment to insert_resource() you'll see that it works contrarywise, i. e. the inserted resource is made parent of the conflicting ones. I.e. it should't work as you're intending it to. > Thomas. WBR, Sergei From tsbogend@alpha.franken.de Sun Apr 8 14:56:03 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Apr 2007 14:56:05 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:47295 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20022685AbXDHN4D (ORCPT ); Sun, 8 Apr 2007 14:56:03 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1HaXp7-0007RO-00; Sun, 08 Apr 2007 15:52:53 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 0156AC223B; Sun, 8 Apr 2007 15:52:44 +0200 (CEST) Date: Sun, 8 Apr 2007 15:52:44 +0200 To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Register PCI host bridge resource earlier Message-ID: <20070408135244.GA8016@alpha.franken.de> References: <20070408112844.GA7553@alpha.franken.de> <4618DDF0.1020604@ru.mvista.com> <20070408131228.GA7819@alpha.franken.de> <4618ED95.6040304@ru.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4618ED95.6040304@ru.mvista.com> User-Agent: Mutt/1.5.9i From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14813 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Sun, Apr 08, 2007 at 05:26:45PM +0400, Sergei Shtylyov wrote: > If you read the comment to insert_resource() you'll see that it works > contrarywise, i. e. the inserted resource is made parent of the conflicting > ones. I.e. it should't work as you're intending it to. why don't you think I haven't testet this ? 00000000-03bfffff : PCIT IO 00000000-0000001f : dma1 00000020-00000021 : pic1 00000040-0000005f : timer 00000060-0000006f : keyboard 00000080-0000008f : dma page reg 000000a0-000000a1 : pic2 000000c0-000000df : dma2 000002f8-000002ff : serial 000003c0-000003df : cirrusfb 000003f8-000003ff : serial 00000c80-00000c83 : EISA device @@@0000 00000cf8-00000cfb : PCI config addr 00000cfc-00000cff : PCI config data 00001000-000010ff : Madge Smart 16/4 EISA Ringnode 00001400-000014ff : Madge Smart 16/4 EISA Ringnode 00001800-000018ff : Madge Smart 16/4 EISA Ringnode 00001c00-00001cff : Madge Smart 16/4 EISA Ringnode that's exactly what I wrote. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From sshtylyov@ru.mvista.com Sun Apr 8 15:47:47 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Apr 2007 15:47:48 +0100 (BST) Received: from rtsoft2.corbina.net ([85.21.88.2]:19087 "HELO mail.dev.rtsoft.ru") by ftp.linux-mips.org with SMTP id S20022697AbXDHOrr (ORCPT ); Sun, 8 Apr 2007 15:47:47 +0100 Received: (qmail 28843 invoked from network); 8 Apr 2007 14:46:42 -0000 Received: from wasted.dev.rtsoft.ru (HELO ?192.168.1.248?) (192.168.1.248) by mail.dev.rtsoft.ru with SMTP; 8 Apr 2007 14:46:42 -0000 Message-ID: <4619008D.1030803@ru.mvista.com> Date: Sun, 08 Apr 2007 18:47:41 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Thomas Bogendoerfer CC: linux-mips@linux-mips.org Subject: Re: [PATCH] Register PCI host bridge resource earlier References: <20070408112844.GA7553@alpha.franken.de> <4618DDF0.1020604@ru.mvista.com> <20070408131228.GA7819@alpha.franken.de> <4618ED95.6040304@ru.mvista.com> <20070408135244.GA8016@alpha.franken.de> In-Reply-To: <20070408135244.GA8016@alpha.franken.de> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14814 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Thomas Bogendoerfer wrote: >> If you read the comment to insert_resource() you'll see that it works >>contrarywise, i. e. the inserted resource is made parent of the conflicting >>ones. I.e. it should't work as you're intending it to. > why don't you think I haven't testet this ? > 00000000-03bfffff : PCIT IO > 00000000-0000001f : dma1 > 00000020-00000021 : pic1 > 00000040-0000005f : timer > 00000060-0000006f : keyboard > 00000080-0000008f : dma page reg > 000000a0-000000a1 : pic2 > 000000c0-000000df : dma2 > 000002f8-000002ff : serial > 000003c0-000003df : cirrusfb > 000003f8-000003ff : serial > 00000c80-00000c83 : EISA device @@@0000 > 00000cf8-00000cfb : PCI config addr > 00000cfc-00000cff : PCI config data > 00001000-000010ff : Madge Smart 16/4 EISA Ringnode > 00001400-000014ff : Madge Smart 16/4 EISA Ringnode > 00001800-000018ff : Madge Smart 16/4 EISA Ringnode > 00001c00-00001cff : Madge Smart 16/4 EISA Ringnode > that's exactly what I wrote. I'm just not seeing how using insert_resource() vs request_resource() for i8259 ports can be relevant here. > Thomas. WBR, Sergei From tsbogend@alpha.franken.de Sun Apr 8 17:14:03 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Apr 2007 17:14:04 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:16328 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20022689AbXDHQOD (ORCPT ); Sun, 8 Apr 2007 17:14:03 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1HaZyf-000191-00; Sun, 08 Apr 2007 18:10:53 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 14BAFC223C; Sun, 8 Apr 2007 18:10:27 +0200 (CEST) Date: Sun, 8 Apr 2007 18:10:27 +0200 To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Register PCI host bridge resource earlier Message-ID: <20070408161027.GA8265@alpha.franken.de> References: <20070408112844.GA7553@alpha.franken.de> <4618DDF0.1020604@ru.mvista.com> <20070408131228.GA7819@alpha.franken.de> <4618ED95.6040304@ru.mvista.com> <20070408135244.GA8016@alpha.franken.de> <4619008D.1030803@ru.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4619008D.1030803@ru.mvista.com> User-Agent: Mutt/1.5.9i From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14815 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Sun, Apr 08, 2007 at 06:47:41PM +0400, Sergei Shtylyov wrote: > I'm just not seeing how using insert_resource() vs request_resource() > for i8259 ports can be relevant here. request_resource will fail, because the range is already taken by sni_io_resource, while insert_region inserts the resource into sni_io_resource. The problem is that init_i8259 doesn't have the right resource for doing the request_resource, if ioport_resource starting from 0x0000 is already taken by a PCI host bridge. I could probably write a patch, which adds a parameter to init_i8259 for the resource, where the request_resource is correct. No idea, whether this is worth the efford. Opions ? Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From sshtylyov@ru.mvista.com Sun Apr 8 17:58:45 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Apr 2007 17:58:46 +0100 (BST) Received: from rtsoft2.corbina.net ([85.21.88.2]:42393 "HELO mail.dev.rtsoft.ru") by ftp.linux-mips.org with SMTP id S20022706AbXDHQ6o (ORCPT ); Sun, 8 Apr 2007 17:58:44 +0100 Received: (qmail 29864 invoked from network); 8 Apr 2007 16:57:43 -0000 Received: from wasted.dev.rtsoft.ru (HELO ?192.168.1.248?) (192.168.1.248) by mail.dev.rtsoft.ru with SMTP; 8 Apr 2007 16:57:43 -0000 Message-ID: <46191F42.6020409@ru.mvista.com> Date: Sun, 08 Apr 2007 20:58:42 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Thomas Bogendoerfer CC: linux-mips@linux-mips.org Subject: Re: [PATCH] Register PCI host bridge resource earlier References: <20070408112844.GA7553@alpha.franken.de> <4618DDF0.1020604@ru.mvista.com> <20070408131228.GA7819@alpha.franken.de> <4618ED95.6040304@ru.mvista.com> <20070408135244.GA8016@alpha.franken.de> <4619008D.1030803@ru.mvista.com> <20070408161027.GA8265@alpha.franken.de> In-Reply-To: <20070408161027.GA8265@alpha.franken.de> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14816 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Thomas Bogendoerfer wrote: >> I'm just not seeing how using insert_resource() vs request_resource() >> for i8259 ports can be relevant here. > request_resource will fail, because the range is already taken by > sni_io_resource, while insert_region inserts the resource into > sni_io_resource. No, it shouldn't according to what I'm seeing in the code. Perhaps I'm missing something and need to actually try executing alike code a see... > The problem is that init_i8259 doesn't have the right > resource for doing the request_resource, if ioport_resource starting from > 0x0000 is already taken by a PCI host bridge. I'm not at all sure that giving out I/O addresses from 0 to PCI is a great idea -- is it indeed necessary? > I could probably write a > patch, which adds a parameter to init_i8259 for the resource, where the > request_resource is correct. No idea, whether this is worth the efford. > Opions ? Did you mean options, opinions, or something else? :-) > Thomas. WBR, Sergei From sshtylyov@ru.mvista.com Sun Apr 8 18:19:37 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Apr 2007 18:19:39 +0100 (BST) Received: from rtsoft2.corbina.net ([85.21.88.2]:57498 "HELO mail.dev.rtsoft.ru") by ftp.linux-mips.org with SMTP id S20022716AbXDHRTh (ORCPT ); Sun, 8 Apr 2007 18:19:37 +0100 Received: (qmail 29981 invoked from network); 8 Apr 2007 17:19:32 -0000 Received: from wasted.dev.rtsoft.ru (HELO ?192.168.1.248?) (192.168.1.248) by mail.dev.rtsoft.ru with SMTP; 8 Apr 2007 17:19:32 -0000 Message-ID: <4619245F.4030704@ru.mvista.com> Date: Sun, 08 Apr 2007 21:20:31 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Thomas Bogendoerfer CC: linux-mips@linux-mips.org Subject: Re: [PATCH] Change PCI host bridge setup/resources References: <20070408113457.GB7553@alpha.franken.de> In-Reply-To: <20070408113457.GB7553@alpha.franken.de> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14817 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Thomas Bogendoerfer wrote: > PCI host bridge setup for SNI RM machines with PCI is quite broken, now that > Linux does it's resource setup own its own. It will use IO addresses, > which are needed by the EISA config detection and assigns PCI memory > addresses, which overlap with ISA legacy addresses (video ram). Below > is a patch, which changes the way how the PCI memory addresses are > used and sets the minimum IO address to give enough IO space for > 8 EISA slots). This patch needs the other PCI resource change, I've > posted. > diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c > index 1dfc3f0..00d151f 100644 > --- a/arch/mips/sni/pcit.c > +++ b/arch/mips/sni/pcit.c > @@ -43,7 +43,7 @@ static struct platform_device pcit_serial8250_device = { > }; > > static struct plat_serial8250_port pcit_cplus_data[] = { > - PORT(0x3f8, 4), > + PORT(0x3f8, 0), > PORT(0x2f8, 3), > PORT(0x3e8, 4), > PORT(0x2e8, 3), Hm, what is that -- UART #1 without IRQ? > @@ -59,9 +59,9 @@ static struct platform_device pcit_cplus_serial8250_device = { > }; > > static struct resource sni_io_resource = { > - .start = 0x00001000UL, > + .start = 0x00000000UL, > .end = 0x03bfffffUL, > - .name = "PCIT IO MEM", > + .name = "PCIT IO", > .flags = IORESOURCE_IO, > }; Why us this necessary, only beacuse compatible peripherals are behind PCI? EISA is behind PCI as well, yet you're setting PCIBIOS_MIN_IO to 0x9000. Does this all really make sense? :-/ > @@ -92,6 +92,11 @@ static struct resource pcit_io_resources[] = { > .name = "dma2", > .flags = IORESOURCE_BUSY > }, { > + .start = 0xcf8, > + .end = 0xcfb, > + .name = "PCI config addr", > + .flags = IORESOURCE_BUSY > + }, { This is certainly *not* a PCI or [E]ISA resource. It's decoded by the *host* bridge. > .start = 0xcfc, > .end = 0xcff, > .name = "PCI config data", Well, why not just join them into one? > void sni_pcit_init(void) > { > - sni_pcit_resource_init(); > rtc_mips_get_time = mc146818_get_cmos_time; > rtc_mips_set_time = mc146818_set_rtc_mmss; > board_time_init = sni_cpu_time_init; > + ioport_resource.end = sni_io_resource.end; > #ifdef CONFIG_PCI > + PCIBIOS_MIN_IO = 0x9000; > register_pci_controller(&sni_pcit_controller); > #endif > + sni_pcit_resource_init(); > } WBR, Sergei From ralf@linux-mips.org Mon Apr 9 00:11:38 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2007 00:11:39 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:15832 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20022769AbXDHXLi (ORCPT ); Mon, 9 Apr 2007 00:11:38 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l38NBVnY031795; Mon, 9 Apr 2007 01:11:31 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l38NBUjW031794; Mon, 9 Apr 2007 01:11:30 +0200 Date: Mon, 9 Apr 2007 01:11:30 +0200 From: Ralf Baechle To: h h Cc: linux-mips@linux-mips.org Subject: Re: Describing Physical RAM Map to Linux Message-ID: <20070408231130.GA31563@linux-mips.org> References: <640437.41507.qm@web53812.mail.re2.yahoo.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <640437.41507.qm@web53812.mail.re2.yahoo.com> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14818 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Apr 07, 2007 at 02:59:15PM -0700, h h wrote: > I have a very basic question -- When describing physical memory to the kernel in > prom_init(), should we describe the physical memory region where kernel is loaded or leave it out? We are using add_memory_region() call to describe physical memory to the kernel. If we do describe the memory region where kernel is loaded, how will kernel know not to use these pages for User processes? The kernel does this automatically. > We are using 2.6.16 on Cavium/Octeon based platform. Which atm are only supported by Cavium's proprietary version of Linux ... Ralf From tsbogend@alpha.franken.de Mon Apr 9 00:27:29 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2007 00:27:30 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:19936 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20022049AbXDHX13 (ORCPT ); Mon, 9 Apr 2007 00:27:29 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1Hagk6-0007Fk-01; Mon, 09 Apr 2007 01:24:18 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id DC21AC223E; Mon, 9 Apr 2007 01:24:06 +0200 (CEST) Date: Mon, 9 Apr 2007 01:24:06 +0200 To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Register PCI host bridge resource earlier Message-ID: <20070408232406.GB9092@alpha.franken.de> References: <20070408112844.GA7553@alpha.franken.de> <4618DDF0.1020604@ru.mvista.com> <20070408131228.GA7819@alpha.franken.de> <4618ED95.6040304@ru.mvista.com> <20070408135244.GA8016@alpha.franken.de> <4619008D.1030803@ru.mvista.com> <20070408161027.GA8265@alpha.franken.de> <46191F42.6020409@ru.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <46191F42.6020409@ru.mvista.com> User-Agent: Mutt/1.5.9i From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14819 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Sun, Apr 08, 2007 at 08:58:42PM +0400, Sergei Shtylyov wrote: > >request_resource will fail, because the range is already taken by > >sni_io_resource, while insert_region inserts the resource into > >sni_io_resource. > > No, it shouldn't according to what I'm seeing in the code. Perhaps I'm > missing something and need to actually try executing alike code a see... after startup there is ioport_resource, which is 0x0000-IO_SPACE_LIMIT. My change in register_pci_controller will request the PCI IO space from 0x0000 to 0x3bffff (the maximum the PCI host bridge could address). request_resource from ioport_resource, which i8259.c tried to do, will fail now in that range, because it'ss taken by the PCI bridge. Therefore anybody wanting IO space in that range, must take it from the PCI IO space. So doing request_region (&sni_io_resource, &pci1_io_resource); would have worked as well. But the code right now doesn't have a handle for the parent resource. insert_region() on the other side searches for the parent resource over the whole given resource and plugs the wanted resource to the right sub resource. Fine for simple house keeping, which is IMHO ok in that place. > >The problem is that init_i8259 doesn't have the right > >resource for doing the request_resource, if ioport_resource starting from > >0x0000 is already taken by a PCI host bridge. > > I'm not at all sure that giving out I/O addresses from 0 to PCI is a > great idea -- is it indeed necessary? I'm feeling like an oldtimer right now. Ever heard of ISA busses ? The address space there starts from 0x0000. There is this infamous DMA controller waiting exactly at IO address 0x0000-0x001f. Floppy DMA needs to use that for example. Of course this would work even without the silly resource stuff (inb/outb don't care), EISA code wants to see 0x0000 as base address of the PCI/EISA bridge. Oh, and addresses for PCI devices (bridges are a different story) will start at PCIBIOS_MIN_IO. So there will be no PCI device resource starting at 0x0000. > >I could probably write a > >patch, which adds a parameter to init_i8259 for the resource, where the > >request_resource is correct. No idea, whether this is worth the efford. > > >Opions ? > > Did you mean options, opinions, or something else? :-) I wanted to know from someone, who knows what I talking about, if my current code is acceptable or needs more workout. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From tsbogend@alpha.franken.de Mon Apr 9 00:27:50 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2007 00:27:52 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:19680 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20022768AbXDHX13 (ORCPT ); Mon, 9 Apr 2007 00:27:29 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1Hagk6-0007Fk-00; Mon, 09 Apr 2007 01:24:18 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 10154C223D; Mon, 9 Apr 2007 01:07:10 +0200 (CEST) Date: Mon, 9 Apr 2007 01:07:10 +0200 To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Change PCI host bridge setup/resources Message-ID: <20070408230710.GA9092@alpha.franken.de> References: <20070408113457.GB7553@alpha.franken.de> <4619245F.4030704@ru.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4619245F.4030704@ru.mvista.com> User-Agent: Mutt/1.5.9i From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14820 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Sun, Apr 08, 2007 at 09:20:31PM +0400, Sergei Shtylyov wrote: > > static struct plat_serial8250_port pcit_cplus_data[] = { > >- PORT(0x3f8, 4), > >+ PORT(0x3f8, 0), > > PORT(0x2f8, 3), > > PORT(0x3e8, 4), > > PORT(0x2e8, 3), > > Hm, what is that -- UART #1 without IRQ? workaround for not fully working interrupts on UART1. IRQ 0 means polling. Read the source. > > static struct resource sni_io_resource = { > >- .start = 0x00001000UL, > >+ .start = 0x00000000UL, > > .end = 0x03bfffffUL, > >- .name = "PCIT IO MEM", > >+ .name = "PCIT IO", > > .flags = IORESOURCE_IO, > > }; > > Why us this necessary, only beacuse compatible peripherals are behind > PCI? > EISA is behind PCI as well, yet you're setting PCIBIOS_MIN_IO to 0x9000. > Does this all really make sense? :-/ it does, how about reading the PCI code ? EISA IO address space is 0x0000 - 0xffff, so this IO addresses need to be forwarded by the PCI host bridge. PCIBIOS_MIN_IO is for the PCI address assignment code, and tells this code to start allocating IO space starting at 0x9000. This is needed because the pci eisa code will use n + 0x1000 as EISA slot base addresses, which gives 0x8000 for the 8th (last) slot. So it's IMHO a good idea to avoid collisions between EISA and PCI for IO space. > This is certainly *not* a PCI or [E]ISA resource. It's decoded by the > *host* bridge. so ? It's an IO address no device should use, because it won't work. Therefore mark it busy. That's all the code does. > > .start = 0xcfc, > > .end = 0xcff, > > .name = "PCI config data", > > Well, why not just join them into one? what's your point ? This stuff is all about giving some hints and avoiding address assignment collisions. I could just drop the whole table and nothing will change, because the PCI code doesn't assign IO addresses below 0x9000. Fine with me, but I think it doesn't hurt to know, what IO addresses are used for some stuff. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From geert@linux-m68k.org Mon Apr 9 09:29:37 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2007 09:29:41 +0100 (BST) Received: from asia.telenet-ops.be ([195.130.137.74]:43451 "EHLO asia.telenet-ops.be") by ftp.linux-mips.org with ESMTP id S20022855AbXDII3h (ORCPT ); Mon, 9 Apr 2007 09:29:37 +0100 Received: from localhost (localhost.localdomain [127.0.0.1]) by asia.telenet-ops.be (Postfix) with SMTP id 4302ED41B9; Mon, 9 Apr 2007 10:29:27 +0200 (CEST) Received: from anakin.of.borg (d54C15D55.access.telenet.be [84.193.93.85]) by asia.telenet-ops.be (Postfix) with ESMTP id 449F3D418E; Mon, 9 Apr 2007 10:29:26 +0200 (CEST) Received: from anakin.of.borg (geert@localhost [127.0.0.1]) by anakin.of.borg (8.13.8/8.13.8/Debian-3) with ESMTP id l398TP1Q020259 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 9 Apr 2007 10:29:25 +0200 Received: from localhost (geert@localhost) by anakin.of.borg (8.13.8/8.13.8/Submit) with ESMTP id l398TOCn020255; Mon, 9 Apr 2007 10:29:24 +0200 X-Authentication-Warning: anakin.of.borg: geert owned process doing -bs Date: Mon, 9 Apr 2007 10:29:24 +0200 (CEST) From: Geert Uytterhoeven To: Thomas Bogendoerfer Cc: Sergei Shtylyov , linux-mips@linux-mips.org Subject: Re: [PATCH] Change PCI host bridge setup/resources In-Reply-To: <20070408230710.GA9092@alpha.franken.de> Message-ID: References: <20070408113457.GB7553@alpha.franken.de> <4619245F.4030704@ru.mvista.com> <20070408230710.GA9092@alpha.franken.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14821 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips On Mon, 9 Apr 2007, Thomas Bogendoerfer wrote: > On Sun, Apr 08, 2007 at 09:20:31PM +0400, Sergei Shtylyov wrote: > > This is certainly *not* a PCI or [E]ISA resource. It's decoded by the > > *host* bridge. > > so ? It's an IO address no device should use, because it won't work. > Therefore mark it busy. That's all the code does. Yep, it's transparently decoded ISA (which is behind PCI) to control the PCI bus. Just traditional PC legacy hacks :-) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From sshtylyov@ru.mvista.com Mon Apr 9 15:43:06 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2007 15:43:08 +0100 (BST) Received: from rtsoft2.corbina.net ([85.21.88.2]:13239 "HELO mail.dev.rtsoft.ru") by ftp.linux-mips.org with SMTP id S20022954AbXDIOnG (ORCPT ); Mon, 9 Apr 2007 15:43:06 +0100 Received: (qmail 22120 invoked from network); 9 Apr 2007 14:41:39 -0000 Received: from wasted.dev.rtsoft.ru (HELO ?192.168.1.248?) (192.168.1.248) by mail.dev.rtsoft.ru with SMTP; 9 Apr 2007 14:41:39 -0000 Message-ID: <461A50E0.1060602@ru.mvista.com> Date: Mon, 09 Apr 2007 18:42:40 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Thomas Bogendoerfer CC: linux-mips@linux-mips.org Subject: Re: [PATCH] Change PCI host bridge setup/resources References: <20070408113457.GB7553@alpha.franken.de> <4619245F.4030704@ru.mvista.com> <20070408230710.GA9092@alpha.franken.de> In-Reply-To: <20070408230710.GA9092@alpha.franken.de> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14822 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Thomas Bogendoerfer wrote: >>>static struct plat_serial8250_port pcit_cplus_data[] = { >>>- PORT(0x3f8, 4), >>>+ PORT(0x3f8, 0), >>> PORT(0x2f8, 3), >>> PORT(0x3e8, 4), >>> PORT(0x2e8, 3), >> Hm, what is that -- UART #1 without IRQ? > workaround for not fully working interrupts on UART1. IRQ 0 means > polling. Read the source. Thanks, I've read it quite a lot already. But is UART3 IRQ working (being the same as UART1's)? >>>static struct resource sni_io_resource = { >>>- .start = 0x00001000UL, >>>+ .start = 0x00000000UL, >>> .end = 0x03bfffffUL, >>>- .name = "PCIT IO MEM", >>>+ .name = "PCIT IO", >>> .flags = IORESOURCE_IO, >>>}; >> Why us this necessary, only beacuse compatible peripherals are behind >> PCI? >>EISA is behind PCI as well, yet you're setting PCIBIOS_MIN_IO to 0x9000. >>Does this all really make sense? :-/ > it does, how about reading the PCI code ? To me, it doesn't make much sense with or without reading the code. And note that no other boards claim ports 0x0000 thru 0x0fff to PCI. > EISA IO address space is 0x0000 - 0xffff, so this IO addresses need to > be forwarded by the PCI host bridge. No need to educate me about EISA. > PCIBIOS_MIN_IO is for the PCI > address assignment code, and tells this code to start allocating IO > space starting at 0x9000. I know that too. > This is needed because the pci eisa code > will use n + 0x1000 as EISA slot base addresses, which gives 0x8000 > for the 8th (last) slot. So it's IMHO a good idea to avoid collisions > between EISA and PCI for IO space. Yeah, and I'd given 0x00009000 as PCI I/O start address for that same purpose. [E]ISA resources, while being accessed (via PCI bus as a proxy) are generally not a part of PCI bus. >> This is certainly *not* a PCI or [E]ISA resource. It's decoded by the >>*host* bridge. > so ? It's an IO address no device should use, because it won't work. > Therefore mark it busy. That's all the code does. It just shouldn't appear under PCI bus in the resource hierarchy. >>> .start = 0xcfc, >>> .end = 0xcff, >>> .name = "PCI config data", >> Well, why not just join them into one? > what's your point ? This stuff is all about giving some hints and > avoiding address assignment collisions. I could just drop the whole > table and nothing will change, because the PCI code doesn't assign > IO addresses below 0x9000. Fine with me, but I think it doesn't hurt > to know, what IO addresses are used for some stuff. You're changing PCI I/O space start address for no apparent reason which seems to break general 8259 code. > Thomas. WBR, Sergei From sshtylyov@ru.mvista.com Mon Apr 9 15:43:41 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2007 15:43:43 +0100 (BST) Received: from rtsoft2.corbina.net ([85.21.88.2]:42167 "HELO mail.dev.rtsoft.ru") by ftp.linux-mips.org with SMTP id S20022954AbXDIOnl (ORCPT ); Mon, 9 Apr 2007 15:43:41 +0100 Received: (qmail 22185 invoked from network); 9 Apr 2007 14:43:38 -0000 Received: from wasted.dev.rtsoft.ru (HELO ?192.168.1.248?) (192.168.1.248) by mail.dev.rtsoft.ru with SMTP; 9 Apr 2007 14:43:38 -0000 Message-ID: <461A5157.3000908@ru.mvista.com> Date: Mon, 09 Apr 2007 18:44:39 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Geert Uytterhoeven CC: Thomas Bogendoerfer , linux-mips@linux-mips.org Subject: Re: [PATCH] Change PCI host bridge setup/resources References: <20070408113457.GB7553@alpha.franken.de> <4619245F.4030704@ru.mvista.com> <20070408230710.GA9092@alpha.franken.de> In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14823 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Geert Uytterhoeven wrote: >>> This is certainly *not* a PCI or [E]ISA resource. It's decoded by the >>>*host* bridge. >>so ? It's an IO address no device should use, because it won't work. >>Therefore mark it busy. That's all the code does. > Yep, it's transparently decoded ISA (which is behind PCI) to control the PCI > bus. Just traditional PC legacy hacks :-) Rubbish. I was complaining about the PCI config/data ports at 0xCF8/0xCFC which are by no means part of either [E]ISA or PCI. They're decoded by the host to PCI bridge. WBR, Sergei From sshtylyov@ru.mvista.com Mon Apr 9 16:10:54 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2007 16:10:55 +0100 (BST) Received: from rtsoft2.corbina.net ([85.21.88.2]:9154 "HELO mail.dev.rtsoft.ru") by ftp.linux-mips.org with SMTP id S20022965AbXDIPKy (ORCPT ); Mon, 9 Apr 2007 16:10:54 +0100 Received: (qmail 22895 invoked from network); 9 Apr 2007 15:10:47 -0000 Received: from wasted.dev.rtsoft.ru (HELO ?192.168.1.248?) (192.168.1.248) by mail.dev.rtsoft.ru with SMTP; 9 Apr 2007 15:10:47 -0000 Message-ID: <461A57B4.8020309@ru.mvista.com> Date: Mon, 09 Apr 2007 19:11:48 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Thomas Bogendoerfer CC: linux-mips@linux-mips.org Subject: Re: [PATCH] Register PCI host bridge resource earlier References: <20070408112844.GA7553@alpha.franken.de> <4618DDF0.1020604@ru.mvista.com> <20070408131228.GA7819@alpha.franken.de> <4618ED95.6040304@ru.mvista.com> <20070408135244.GA8016@alpha.franken.de> <4619008D.1030803@ru.mvista.com> <20070408161027.GA8265@alpha.franken.de> <46191F42.6020409@ru.mvista.com> <20070408232406.GB9092@alpha.franken.de> In-Reply-To: <20070408232406.GB9092@alpha.franken.de> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14824 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Thomas Bogendoerfer wrote: >>>request_resource will fail, because the range is already taken by >>>sni_io_resource, while insert_region inserts the resource into >>>sni_io_resource. >> No, it shouldn't according to what I'm seeing in the code. Perhaps I'm >>missing something and need to actually try executing alike code a see... > after startup there is ioport_resource, which is 0x0000-IO_SPACE_LIMIT. > My change in register_pci_controller will request the PCI IO space > from 0x0000 to 0x3bffff (the maximum the PCI host bridge could address). Why do you need to claim I/O ports from 0, at the first place (especially if nobody else does this)? Apparently in your EISA system, ports 0x0 thru 0x100 are reserved for ISA compat pereiplerals (they are behind the PCI-ISA bridge but that doesn't matter for this purpose), ports 0x100-0x3ff are not for PCI anyway (besides, that's legacy ISA card range, along with all the aliases), 0x1000-0x1cff, 0x2000-0x2cff, ... 0x8000-0x8cff are reserved for EISA slots and everything in beetween you're marking as unavailable to PCI too (besides, those ranges are ISA card alias ranges). So, what was the point of claiming all the lagacy ranges to belong to PCI and then prevent it from using them, (and break 8259 code by doing that)? > request_resource from ioport_resource, which i8259.c tried to do, will > fail now in that range, because it'ss taken by the PCI bridge. Therefore > anybody wanting IO space in that range, must take it from the PCI > IO space. So doing request_region (&sni_io_resource, &pci1_io_resource); > would have worked as well. But the code right now doesn't have a > handle for the parent resource. insert_region() on the other side > searches for the parent resource over the whole given resource and > plugs the wanted resource to the right sub resource. OK, seeing my mistake in the code interpretation now. But I must note that the comment to that function *is* misguiding: > Fine for simple house keeping, which is IMHO ok in that place. It's OK but I'm still not seeing why we need it at all. >>>The problem is that init_i8259 doesn't have the right >>>resource for doing the request_resource, if ioport_resource starting from >>>0x0000 is already taken by a PCI host bridge. >> I'm not at all sure that giving out I/O addresses from 0 to PCI is a >> great idea -- is it indeed necessary? > I'm feeling like an oldtimer right now. Ever heard of ISA busses ? The Alas, your irony is lost on me. :-) > address space there starts from 0x0000. There is this infamous DMA > controller waiting exactly at IO address 0x0000-0x001f. Floppy DMA > needs to use that for example. Of course this would work even without I even programmed ISA bus masters. :-) > the silly resource stuff (inb/outb don't care), EISA code wants to see > 0x0000 as base address of the PCI/EISA bridge. Does EISA code care about PCI bridge? Well, looking at drivers/eisa/pci_eisa.c looks like it indeed may care. Well, then I've probably lost the case. :-) >>>I could probably write a >>>patch, which adds a parameter to init_i8259 for the resource, where the >>>request_resource is correct. No idea, whether this is worth the efford. >>>Opions ? >> Did you mean options, opinions, or something else? :-) > I wanted to know from someone, who knows what I talking about, if my > current code is acceptable or needs more workout. You wanted it, you got it. > Thomas. WBR, Sergei From tsbogend@alpha.franken.de Mon Apr 9 16:21:47 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2007 16:21:48 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:23971 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20022973AbXDIPVr (ORCPT ); Mon, 9 Apr 2007 16:21:47 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1Havdc-0000eh-00; Mon, 09 Apr 2007 17:18:36 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 2B488C223F; Mon, 9 Apr 2007 17:16:30 +0200 (CEST) Date: Mon, 9 Apr 2007 17:16:30 +0200 To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Change PCI host bridge setup/resources Message-ID: <20070409151630.GA9284@alpha.franken.de> References: <20070408113457.GB7553@alpha.franken.de> <4619245F.4030704@ru.mvista.com> <20070408230710.GA9092@alpha.franken.de> <461A50E0.1060602@ru.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <461A50E0.1060602@ru.mvista.com> User-Agent: Mutt/1.5.9i From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14825 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Mon, Apr 09, 2007 at 06:42:40PM +0400, Sergei Shtylyov wrote: > >workaround for not fully working interrupts on UART1. IRQ 0 means > >polling. Read the source. > > Thanks, I've read it quite a lot already. But is UART3 IRQ working > (being the same as UART1's)? right now, none of the ISA interrupts are working on that machine, probably because I'm missing some IRQ routing setup. The workaround is there to get serial console working in userspace. > To me, it doesn't make much sense with or without reading the code. > And note that no other boards claim ports 0x0000 thru 0x0fff to PCI. no other board MIPS board has EISA behind PCI afaik. So this is a new situation. > Yeah, and I'd given 0x00009000 as PCI I/O start address for that same > purpose. [E]ISA resources, while being accessed (via PCI bus as a proxy) > are generally not a part of PCI bus. it would help, if you would try to understand the stuff first. Just read the EISA code... > You're changing PCI I/O space start address for no apparent reason which > seems to break general 8259 code. could you try to understand the issue please ? I could leave the i8259 code alone and everything will work as before. Only the entries for the PIC would be missing in /proc/iomem (which I could kludge around by adding them to the pcit/pcimt resource list). Every other platform won't see a difference, because no other platform needs to request the PCI IO space starting at 0x0000. I've checked the platform device code, and it uses insert_region() like my proposed change for i8259. So I'm pretty sure, that's the way to go. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From ralf@linux-mips.org Mon Apr 9 23:02:28 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Apr 2007 23:02:32 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:20360 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20023058AbXDIWC2 (ORCPT ); Mon, 9 Apr 2007 23:02:28 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l39M29pV022241; Tue, 10 Apr 2007 00:02:10 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l39M27ao022240; Tue, 10 Apr 2007 00:02:07 +0200 Date: Mon, 9 Apr 2007 23:02:07 +0100 From: Ralf Baechle To: "zhangfx@lemote.com" Cc: "linux-mips@linux-mips.org" Subject: Re: [PATCH 1/16] new files for lemote fulong mini-PC support Message-ID: <20070409220207.GA5804@linux-mips.org> References: <945333.042039664-sendEmail@heart> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <945333.042039664-sendEmail@heart> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14826 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 04, 2007 at 02:38:18PM +0000, zhangfx@lemote.com wrote: Let's see :-) > diff --git a/arch/mips/lemote/README b/arch/mips/lemote/README > new file mode 100644 > index 0000000..96aa8ce > --- /dev/null > +++ b/arch/mips/lemote/README > @@ -0,0 +1,2 @@ > +lm2e: > + board of lemote corp., which uses ict fpga north bridge and Loongson2E(godson2E) CPU. We generally don't keep documentation in the kernel code; such information is usually kept either in the Documentation directory or also as you do in the Kconfig. > diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile > new file mode 100644 > index 0000000..4017b75 > --- /dev/null > +++ b/arch/mips/lemote/lm2e/Makefile > @@ -0,0 +1,7 @@ > +# > +# Makefile for Lemote Fulong mini-PC board. > +# > + > +obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o mipsdha.o dbg_io.o Please format code to 80 columns max. > + > +EXTRA_AFLAGS := $(CFLAGS) > diff --git a/arch/mips/lemote/lm2e/bonito-irq.c b/arch/mips/lemote/lm2e/bonito-irq.c > new file mode 100644 > index 0000000..1ba153e > --- /dev/null > +++ b/arch/mips/lemote/lm2e/bonito-irq.c > @@ -0,0 +1,100 @@ > +/* > + * Copyright 2001 MontaVista Software Inc. > + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net > + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) > + * > + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include > + > +#include > + > +#define bonito_irq_shutdown bonito_irq_disable > + > +#define MIPS_ASSERT(x) if (!(x)) { panic("MIPS_ASSERT failed at %s:%d\n", __FILE__, __LINE__); } This macro is unused. Anyway, in Linux the BUG_ON() macro is prefered. > + > +Bonito; This one makes the code a bit odd to read ... > + > +static inline void bonito_irq_enable(unsigned int irq) > +{ > + BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); > + iob(); > +} iob() is one of the more obscure MIPS-specific operations which I would like to get rid of in favor of generic operations, like mmiowb(). Have you considered using mmiowb() instead? mmiowb() expands into a SYNC instruction which I guess is probably enough. > + > +static inline void bonito_irq_disable(unsigned int irq) > +{ > + BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); > + iob(); > +} > + > +static void bonito_irq_end(unsigned int irq) > +{ > + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) > + bonito_irq_enable(irq); > +} > + > +static struct irq_chip bonito_irq_type = { > + .name = "bonito_irq", > + .ack = bonito_irq_disable, > + .mask = bonito_irq_disable, > + .mask_ack = bonito_irq_disable, > + .unmask = bonito_irq_enable, > + .eoi = bonito_irq_enable, .eoi is only needed if handle_fasteoi_irq is being used. > + .end = bonito_irq_end, You define GENERIC_HARDIRQS_NO__DO_IRQ so .end is not needed. > + NULL /* no affinity stuff for UP */ Please use named initializers. But in this case the initializer is can be removed anyway, so probably should. > +}; > + > +static struct irqaction dma_timeout_irqaction = { > + .handler = no_action, > + .name = "dma_timeout", > +}; > + > +void bonito_irq_init(void) > +{ > + u32 i; > + > + for (i= BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) { > + set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); > + } > + > + setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); > +} > diff --git a/arch/mips/lemote/lm2e/dbg_io.c b/arch/mips/lemote/lm2e/dbg_io.c > new file mode 100644 > index 0000000..06c9eb2 > --- /dev/null > +++ b/arch/mips/lemote/lm2e/dbg_io.c > @@ -0,0 +1,162 @@ > +/* > + * Copyright 2001 MontaVista Software Inc. > + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net > + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) > + * > + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > +#include > + > +#include /* For the serial port location and base baud */ > + > +/* --- CONFIG --- */ > + > +typedef unsigned char uint8; > +typedef unsigned int uint32; Please use u8 and u32 instead. > + > +/* --- END OF CONFIG --- */ > + > +#define UART16550_BAUD_2400 2400 > +#define UART16550_BAUD_4800 4800 > +#define UART16550_BAUD_9600 9600 > +#define UART16550_BAUD_19200 19200 > +#define UART16550_BAUD_38400 38400 > +#define UART16550_BAUD_57600 57600 > +#define UART16550_BAUD_115200 115200 > + > +#define UART16550_PARITY_NONE 0 > +#define UART16550_PARITY_ODD 0x08 > +#define UART16550_PARITY_EVEN 0x18 > +#define UART16550_PARITY_MARK 0x28 > +#define UART16550_PARITY_SPACE 0x38 > + > +#define UART16550_DATA_5BIT 0x0 > +#define UART16550_DATA_6BIT 0x1 > +#define UART16550_DATA_7BIT 0x2 > +#define UART16550_DATA_8BIT 0x3 > + > +#define UART16550_STOP_1BIT 0x0 > +#define UART16550_STOP_2BIT 0x4 > + > +/* ----------------------------------------------------- */ > + > +/* === CONFIG === */ > + > +#ifdef CONFIG_64BIT > + > +#define BASE (0xffffffffbfd003f8) > + > +#else > + > +#define BASE (0xbfd003f8) > + > +#endif > + > +#define MAX_BAUD BASE_BAUD > + > +/* === END OF CONFIG === */ > + > +#define REG_OFFSET 1 > + > +/* register offset */ > +#define OFS_RCV_BUFFER 0 > +#define OFS_TRANS_HOLD 0 > +#define OFS_SEND_BUFFER 0 > +#define OFS_INTR_ENABLE (1*REG_OFFSET) > +#define OFS_INTR_ID (2*REG_OFFSET) > +#define OFS_DATA_FORMAT (3*REG_OFFSET) > +#define OFS_LINE_CONTROL (3*REG_OFFSET) > +#define OFS_MODEM_CONTROL (4*REG_OFFSET) > +#define OFS_RS232_OUTPUT (4*REG_OFFSET) > +#define OFS_LINE_STATUS (5*REG_OFFSET) > +#define OFS_MODEM_STATUS (6*REG_OFFSET) > +#define OFS_RS232_INPUT (6*REG_OFFSET) > +#define OFS_SCRATCH_PAD (7*REG_OFFSET) > + > +#define OFS_DIVISOR_LSB (0*REG_OFFSET) > +#define OFS_DIVISOR_MSB (1*REG_OFFSET) > + > + > +/* memory-mapped read/write of the port */ > +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) > +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) > + > +void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) > +{ > + /* disable interrupts */ > + UART16550_WRITE(OFS_INTR_ENABLE, 0); > + > + /* set up buad rate */ > + { > + uint32 divisor; > + > + /* set DIAB bit */ > + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); > + > + /* set divisor */ > + divisor = MAX_BAUD / baud; > + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); > + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); > + > + /* clear DIAB bit */ > + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); > + } > + > + /* set data format */ > + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); > +} > + > +static int remoteDebugInitialized = 0; > + > +uint8 getDebugChar(void) > +{ > + if (!remoteDebugInitialized) { > + remoteDebugInitialized = 1; > + debugInit(UART16550_BAUD_115200, > + UART16550_DATA_8BIT, > + UART16550_PARITY_NONE, UART16550_STOP_1BIT); > + } > + > + while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); > + return UART16550_READ(OFS_RCV_BUFFER); > +} > + > + > +int putDebugChar(uint8 byte) > +{ > + if (!remoteDebugInitialized) { > + remoteDebugInitialized = 1; > + /* Trailing whitespace. You may want to run something like this script: find $* -name CVS -prune -o -type f -print | \ fgrep -v defconfig | xargs --no-run-if-empty -- perl -pi -e 's/[ \t]+$//' over your code to remove it. > + debugInit(UART16550_BAUD_115200, > + UART16550_DATA_8BIT, > + UART16550_PARITY_NONE, UART16550_STOP_1BIT);*/ > + > + } > + > + while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); > + UART16550_WRITE(OFS_SEND_BUFFER, byte); > + return 1; > +} > + > diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c > new file mode 100644 > index 0000000..eae1c67 > --- /dev/null > +++ b/arch/mips/lemote/lm2e/irq.c > @@ -0,0 +1,157 @@ > +/* > + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include This includes plenty of unneeded header files. > + > +/* > + * the first level int-handler will jump here if it is a bonito irq > + */ > +static void bonito_irqdispatch(void) > +{ > + Bonito; j > + > + int irq; > + unsigned long int_status; > + int i; > + > + /* workaround the IO dma problem: let cpu looping to allow DMA finish */ > + int_status = BONITO_INTISR ; int_status will have differing size on 32-bit and 64-bit kernels but BONITO_INTISR always reads just a 32-bit word. > + if(int_status&(1<<10)){ > + while(int_status&(1<<10)){ > + udelay(1); > + int_status = BONITO_INTISR; > + } > + } Linux coding style: Indent with one tab per block. See Documentation/CodingStyle. > + > + /* Get pending sources, masked by current enables */ > + int_status = BONITO_INTISR & BONITO_INTEN; > + > + /* Scan all pending interrupt bits and execute appropriate actions */ > + for (i=0; i<32 && int_status; i++) { > + if (int_status & 1< + irq = i + BONITO_IRQ_BASE; > + /* Clear bit to optimise loop exit */ > + int_status &= ~(1< + do_IRQ(irq); > + > + } > + } This loop is slow; you may want to consider using something like __ffs() instead. Another optiization most MIPS platforms in Linux do is to not loop but return from interrupt after processing the first pending interrupt - looping and repeatedly checking all sources is rarely worth it. > + > + return; > +} > + > +static void i8259_irqdispatch(void) > +{ > + int irq; > + > + irq = i8259_irq(); > + > + do_IRQ(irq); > +} Bug alert: i8259_irq() may return -1 in case of a spurious IRQ. > + > +asmlinkage void plat_irq_dispatch(void) > +{ > + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; > + > + if (pending & CAUSEF_IP7) { > + do_IRQ(MIPS_CPU_IRQ_BASE + 7); > + } else if (pending & CAUSEF_IP5) { > + i8259_irqdispatch(); > + } else if (pending & CAUSEF_IP2) { > + bonito_irqdispatch(); > + } else { > + spurious_interrupt(); > + } > +} > + > +static struct irqaction cascade_irqaction = { > + .handler = no_action, > + .mask = CPU_MASK_NONE, > + .name = "cascade", > +}; > + > +void __init arch_init_irq(void) > +{ > + Bonito; > + extern void bonito_irq_init(void); > + > + printk("arch init irq\n"); > + /* > + * Clear all of the interrupts while we change the able around a bit. > + * int-handler is not on bootstrap > + */ > + clear_c0_status(ST0_IM | ST0_BEV); > + local_irq_disable(); > + > + /* most bonito irq should be level triggered */ > + BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR \ > + | BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; > + BONITO_INTSTEER = 0; > + > + /* > + * Mask out all interrupt by writing "1" to all bit position in > + * the interrupt reset reg. > + */ > + BONITO_INTENCLR = ~0; > + > + /* init all controller > + * 0-15 ------> i8259 interrupt > + * 16-23 ------> mips cpu interrupt > + * 32-63 ------> bonito irq > + */ > + > + /* Sets the first-level interrupt dispatcher. */ > + > + mips_cpu_irq_init(); > + init_i8259_irqs(); > + bonito_irq_init(); > + > + //printk("GPIODATA=%x,GPIOIE=%x\n",BONITO_GPIODATA,BONITO_GPIOIE); > + //printk("INTEN=%x,INTSET=%x,INTCLR=%x,INTISR=%x\n",BONITO_INTEN,BONITO_INTENSET,BONITO_INTENCLR,BONITO_INTISR); > + > + /* bonito irq at IP2 */ > + setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); > + /* 8259 irq at IP5 */ > + setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); > + > + printk("init_IRQ done.\n"); This printk looks like old debugging stuff that probably is no longer very useful. > +} > diff --git a/arch/mips/lemote/lm2e/mipsdha.c b/arch/mips/lemote/lm2e/mipsdha.c > new file mode 100644 > index 0000000..0c97be9 > --- /dev/null > +++ b/arch/mips/lemote/lm2e/mipsdha.c > @@ -0,0 +1,162 @@ > +/* > + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static ssize_t mipsdha_proc_read(struct file *file, char *buf, size_t len, loff_t *ppos); > + > +static ssize_t mipsdha_proc_write(struct file *file, const char *buf, size_t len, loff_t *ppos); > + > + > +static struct proc_dir_entry *mipsdha_proc_entry; > + > +#define INFO_SIZE 4096 > +static char info_buf[INFO_SIZE]; > + > +static struct file_operations mipsdha_fops = > +{ > + owner: THIS_MODULE, > + read: mipsdha_proc_read, > + write: mipsdha_proc_write, > +}; > + > +static enum {CMD_ERR, CMD_GIB, CMD_GPI} cmd; > + > +typedef struct pciinfo_s > +{ > + int bus,card,func; > + unsigned short command; > + unsigned short vendor,device; > + unsigned base0,base1,base2,baserom; > +} pciinfo_t; > + > + > +static int __init mipsdha_proc_init(void) > +{ > + mipsdha_proc_entry = create_proc_entry("mipsdha", S_IWUSR | S_IRUGO, &proc_root); > + if (mipsdha_proc_entry == NULL) { > + printk("MIPSDHA: register /proc/mipsdha failed!\n"); printk strings generally should have a KERN_* severity level. In this case for example KERN_ERR would seem suitable. > + return 0; > + } > + > + mipsdha_proc_entry->owner = THIS_MODULE; > + mipsdha_proc_entry->proc_fops = &mipsdha_fops; > + > + cmd=CMD_ERR; > + return 0; > +} > + > +static ssize_t mipsdha_proc_write (struct file *file, const char *buf, size_t len, loff_t *ppos) > +{ > + char cmd_gib[]="GET IO BASE"; > + char cmd_gpi[]="GET PCI INFO"; > + > + if (len >= INFO_SIZE) return -ENOMEM; ENOMEM means the machine ran out of memory. EINVAL woud be more apropriate here. > + > + if (copy_from_user(info_buf, buf, len)) return -EFAULT; I don't see anything that would prevent multiple processes from writing to the same buffer info_buf. > + info_buf[len] = '\0'; > + > + if (strncmp(info_buf, cmd_gib, sizeof(cmd_gib)-1)==0) { > + cmd = CMD_GIB; > + return len; > + } else if (strncmp(info_buf, cmd_gpi, sizeof(cmd_gpi)-1)==0) { > + cmd = CMD_GPI; > + return len; > + } else { > + return -EINVAL; > + } > +} > + > +static ssize_t mipsdha_proc_read (struct file *file, char *buf, size_t len, loff_t *ppos) > +{ > + int info_cnt; > + pciinfo_t *pciinfo; > + struct pci_dev *dev = NULL; > + > + switch (cmd) { > + default: > + printk("MIPSDHA: BUG found in function %s!(cmd=%d)\n", > + __FUNCTION__, cmd); > + return -EINVAL; CodingStyle: [...] The preferred way to ease multiple indentation levels in a switch statement is to align the "switch" and its subordinate "case" labels in the same column instead of "double-indenting" the "case" labels. E.g.: switch (suffix) { case 'G': case 'g': [...] > + > + > + case CMD_ERR: > + return -EINVAL; > + > + > + case CMD_GIB: > + *(unsigned long *)info_buf = > + virt_to_phys((void *) mips_io_port_base); > + info_cnt=sizeof(unsigned long); > + break; > + > + > + case CMD_GPI: > + pciinfo = (pciinfo_t *) info_buf; > + info_cnt = 0; > + for_each_pci_dev(dev) { > + > + if (info_cnt+sizeof(pciinfo_t)>INFO_SIZE) return -ENOMEM; > + > + pciinfo->bus = dev->bus->number; > + pciinfo->card = PCI_SLOT(dev->devfn); > + pciinfo->func = PCI_FUNC(dev->devfn); > + > + if (pci_read_config_word(dev, PCI_COMMAND, &pciinfo->command) > + != PCIBIOS_SUCCESSFUL) { > + printk("MIPSDHA: BUG found in function %s!\n", > + __FUNCTION__); > + pciinfo->command=0; > + } > + > + pciinfo->vendor = dev->vendor; > + pciinfo->device = dev->device; > + > + pciinfo->base0 = (dev->resource[0]).start; > + pciinfo->base1 = (dev->resource[1]).start; > + pciinfo->base2 = (dev->resource[2]).start; > + pciinfo->baserom = (dev->resource[PCI_ROM_RESOURCE]).start; > + > + pciinfo++; > + info_cnt += sizeof(pciinfo_t); > + } > + break; > + } > + > + if (len < info_cnt) return -ENOMEM; > + if (copy_to_user(buf, info_buf, info_cnt)) return -EFAULT; CodingStyle: [...] Don't put multiple statements on a single line unless you have something to hide: if (condition) do_this; do_something_everytime; [...] > + > + return info_cnt; > +} > + > +__initcall(mipsdha_proc_init); > diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c > new file mode 100644 > index 0000000..d9a1724 > --- /dev/null > +++ b/arch/mips/lemote/lm2e/pci.c > @@ -0,0 +1,73 @@ > +/* > + * pci.c > + * > + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > +#include > +#include > +#include > +#include > + > +extern struct pci_ops loongson2e_pci_pci_ops; > + > +static struct resource loongson2e_pci_mem_resource = { > + .name = "LOONGSON2E PCI MEM", > + .start = 0x14000000UL, > + .end = 0x1fffffffUL, > + .flags = IORESOURCE_MEM, > +}; > + > +static struct resource loongson2e_pci_io_resource = { > + .name = "LOONGSON2E PCI IO MEM", > + .start = 0x00004000UL, > + .end = 0x1fffffffUL, > + .flags = IORESOURCE_IO, > +}; > + > + > +static struct pci_controller loongson2e_pci_controller = { > + .pci_ops = &loongson2e_pci_pci_ops, > + .io_resource = &loongson2e_pci_io_resource, > + .mem_resource = &loongson2e_pci_mem_resource, > + .mem_offset = 0x00000000UL, > + .io_offset = 0x00000000UL, > +}; > + > + > +static int __init pcibios_init(void) > +{ > + extern int pci_probe_only; > + > + pci_probe_only = 0; pci_probe_only = 0 is the default. ... and I'm considering to remove this variable anyway. > +#ifdef CONFIG_TRACE_BOOT > + printk("arch_initcall:pcibios_init\n"); > + printk("register_pci_controller : %x\n",&loongson2e_pci_controller); > +#endif > + register_pci_controller(&loongson2e_pci_controller); > + return 0; > +} > + > +arch_initcall(pcibios_init); > diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c > new file mode 100644 > index 0000000..172bd65 > --- /dev/null > +++ b/arch/mips/lemote/lm2e/prom.c > @@ -0,0 +1,112 @@ > +/* > + * Based on Ocelot Linux port, which is > + * Copyright 2001 MontaVista Software Inc. > + * Author: jsun@mvista.com or jsun@junsun.net > + * > + * Copyright 2003 ICT CAS > + * Author: Michael Guo > + * > + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + */ > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +extern char arcs_cmdline[CL_SIZE]; This duplicates the declaration in . > + > +extern unsigned long bus_clock; > +extern unsigned long cpu_clock; > +extern unsigned int memsize,highmemsize; > +extern int putDebugChar(unsigned char byte); > + > +static int argc; > +/* pmon passes arguments in 32bit pointers */ > +static int * arg; > +static int * env; > + > +const char *get_system_type(void) > +{ > + return "Lemote Fulong mini-PC board"; > +} You may want to shorten that string. Script writers will also be happier if the value returned does not contain space, for example "lemote-fulong". > + > +void __init prom_init_cmdline(void) > +{ > + int i; > + /* some 64bit toolchain can't convert int to a pointer correctly */ Broken is broken, they don't deserve attention in the code. > + long l; > + > + /* arg[0] is "g", the rest is boot parameters */ > + arcs_cmdline[0] = '\0'; > + for (i = 1; i < argc; i++) { > + l = (long)arg[i]; > + if (strlen(arcs_cmdline) + strlen(((char*)l) + 1) > + >= sizeof(arcs_cmdline)) > + break; > + strcat(arcs_cmdline, ((char*)l)); > + strcat(arcs_cmdline, " "); > + } > +} > + > +void __init prom_init(void) > +{ > + long l; > + argc=fw_arg0; > + arg=(int *)fw_arg1; > + env=(int *)fw_arg2; > + > + mips_machgroup = MACH_GROUP_LEMOTE; > + mips_machtype = MACH_LEMOTE_FULONG; > + > + prom_init_cmdline(); > + > + if((strstr(arcs_cmdline, "console=")) == NULL) > + strcat(arcs_cmdline, " console=ttyS0,115200"); > + if((strstr(arcs_cmdline, "root=")) == NULL) > + strcat(arcs_cmdline, " root=/dev/hda1"); This will only work with CONFIG_SYSFS. Without the kernel will not be able to translate /dev/hda1 to a major/minor number. > + > + l = (long)*env; > + while (l!=0) { > + if (strncmp("busclock", (char*)l, strlen("busclock")) == 0) { > + bus_clock = simple_strtol((char*)l + strlen("busclock="), > + NULL, 10); > + } > + if (strncmp("cpuclock", (char*)l, strlen("cpuclock")) == 0) { > + cpu_clock = simple_strtol((char*)l + strlen("cpuclock="), > + NULL, 10); > + } > + if (strncmp("memsize", (char*)l, strlen("memsize")) == 0) { > + memsize = simple_strtol((char*)l + strlen("memsize="), > + NULL, 10); > + } > + if (strncmp("highmemsize", (char*)l, strlen("highmemsize")) == 0) { > + highmemsize = simple_strtol((char*)l + strlen("highmemsize="), > + NULL, 10); > + } > + env++; > + l=(long)*env; > + } > + if (memsize == 0) > + memsize = 256; > + > + printk("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n", bus_clock, cpu_clock,memsize,highmemsize); > +} > + > +void __init prom_free_prom_memory(void) > +{ > +} > + > +void prom_putchar(char c) > +{ > + putDebugChar(c); > +} > + > diff --git a/arch/mips/lemote/lm2e/reset.c b/arch/mips/lemote/lm2e/reset.c > new file mode 100644 > index 0000000..4400f8d > --- /dev/null > +++ b/arch/mips/lemote/lm2e/reset.c > @@ -0,0 +1,47 @@ > +/* > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static void loongson2e_restart(char *command) > +{ > +#ifdef CONFIG_32BIT > + *(unsigned long *)0xbfe00104 &= ~(1<<2); > + *(unsigned long *)0xbfe00104 |= (1<<2); > +#else > + *(unsigned long *)0xffffffffbfe00104 &= ~(1<<2); > + *(unsigned long *)0xffffffffbfe00104 |= (1<<2); > +#endif > + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); > +} > + > +static void loongson2e_halt(void) > +{ > + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); Windows 95? It's userland that should print such messages not the kernel. > + while(1); > +} > + > +static void loongson2e_power_off(void) > +{ > + loongson2e_halt(); > +} > + > +void mips_reboot_setup(void) > +{ > + _machine_restart = loongson2e_restart; > + _machine_halt = loongson2e_halt; > + pm_power_off = loongson2e_power_off; > +} > diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c > new file mode 100644 > index 0000000..d75f00e > --- /dev/null > +++ b/arch/mips/lemote/lm2e/setup.c > @@ -0,0 +1,143 @@ > +/* > + * BRIEF MODULE DESCRIPTION > + * setup.c - board dependent boot routines > + * > + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#ifdef CONFIG_VT > +#include > +#include > +#endif > + > +extern void mips_reboot_setup(void); > + > +#ifdef CONFIG_64BIT > +#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p))) > +#else > +#define PTR_PAD(p) (p) > +#endif > + > + > +unsigned long cpu_clock; > +unsigned long bus_clock; > +unsigned int memsize; > +unsigned int highmemsize = 0; > + > + > +void __init plat_timer_setup(struct irqaction *irq) > +{ > + setup_irq(MIPS_CPU_IRQ_BASE + 7, irq); > +} > + > +static void __init loongson2e_time_init(void) > +{ > + /* setup mips r4k timer */ > + mips_hpt_frequency = cpu_clock / 2; > +} > + > +static unsigned long __init mips_rtc_get_time(void) > +{ > + return mc146818_get_cmos_time(); > +} > + > +void (*__wbflush)(void); This duplicates a declaration from . > +static void wbflush_loongson2e(void) > +{ > + *(volatile unsigned long *)CKSEG1; BUT: do you really need this? The uncached read from RAM is extremly heavyweight, especiall from a lowly SODIMM. > + asm(".set\tpush\n\t" > + ".set\tnoreorder\n\t" > + ".set mips3\n\t" > + "sync\n\t" > + "nop\n\t" > + ".set\tpop\n\t" > + ".set mips0\n\t"); > +} > +void __init plat_mem_setup(void) > +{ > + set_io_port_base(PTR_PAD(0xbfd00000)); > + > + ioport_resource.start = 0; > + ioport_resource.end = 0xffffffff; > + iomem_resource.start = 0; > + iomem_resource.end = 0xffffffff; > + > + mips_reboot_setup(); > + > + board_time_init = loongson2e_time_init; > + rtc_mips_get_time = mips_rtc_get_time; > + > + __wbflush = wbflush_loongson2e; > + > + //add_memory_region(0x100000, (memsize<<20) - 0x100000, BOOT_MEM_RAM); > + add_memory_region(0x0, (memsize<<20), BOOT_MEM_RAM); > +#ifdef CONFIG_64BIT > + if (highmemsize > 0) { > + add_memory_region(0x10000000, 0x10000000, BOOT_MEM_RESERVED); > + add_memory_region(0x20000000, highmemsize<<20, BOOT_MEM_RAM); > + } > +#endif > + > +#ifdef CONFIG_VT > +#if defined(CONFIG_VGA_CONSOLE) > + conswitchp = &vga_con; > + > + screen_info = (struct screen_info) { > + 0, 25, /* orig-x, orig-y */ > + 0, /* unused */ > + 0, /* orig-video-page */ > + 0, /* orig-video-mode */ > + 80, /* orig-video-cols */ > + 0,0,0, /* ega_ax, ega_bx, ega_cx */ > + 25, /* orig-video-lines */ > + VIDEO_TYPE_VGAC, /* orig-video-isVGA */ > + 16 /* orig-video-points */ > + }; > +#elif defined(CONFIG_DUMMY_CONSOLE) > + conswitchp = &dummy_con; > +#endif > +#endif > + > +} > + > diff --git a/arch/mips/pci/fixup-lm2e.c b/arch/mips/pci/fixup-lm2e.c > new file mode 100644 > index 0000000..113f5f1 > --- /dev/null > +++ b/arch/mips/pci/fixup-lm2e.c > @@ -0,0 +1,255 @@ > +/* > + * fixup-lm2e.c > + * > + * Copyright (C) 2004 ICT CAS > + * Author: Li xiaoyu, ICT CAS > + * lixy@ict.ac.cn > + * > + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > +#include > +#include > +#include > + > +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) > +{ > + unsigned int val; > + if (PCI_SLOT(dev->devfn) == 4) { /* wireless card(notebook) */ > + dev->irq = BONITO_IRQ_BASE + 26; > + (void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); There is no need to write anything to PCI_INTERRUPT_LINE at all; Linux doesn't use it. PCI_INTERRUPT_LINE is one of the more shortsighted ideas in the PCI spec. Neat but useless ... > + return dev->irq; > + } else if (PCI_SLOT(dev->devfn) == 5) { /* via686b */ > + switch (PCI_FUNC(dev->devfn)) { > + case 2: > + dev->irq = 10; > + break; > + case 3: > + dev->irq = 11; > + break; > + case 5: > + dev->irq = 9; > + break; > + } > + (void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); > + return dev->irq; > + }else if (PCI_SLOT(dev->devfn) == 6) { /* radeon 7000 */ > + dev->irq = BONITO_IRQ_BASE + 27; > + (void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); > + return dev->irq; > + }else if (PCI_SLOT(dev->devfn) == 7) { /* 8139 */ > + dev->irq = BONITO_IRQ_BASE + 26; > + (void) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); > + return dev->irq; > + } else if (PCI_SLOT(dev->devfn) == 8) { /* nec usb */ > + switch (PCI_FUNC(dev->devfn)) { > + case 0: > + dev->irq = BONITO_IRQ_BASE + 26; > + break; > + case 1: > + dev->irq = BONITO_IRQ_BASE + 27; > + dev->irq = 11; > + break; > + case 2: > + dev->irq = BONITO_IRQ_BASE + 28; > + break; > + } > + pci_read_config_dword(dev, 0xe0, &val); > + pci_write_config_dword(dev, 0xe0, (val & ~7) | 0x4); > + pci_write_config_dword(dev, 0xe4, 1<<5); > + pci_write_config_dword(dev, PCI_INTERRUPT_LINE, dev->irq); > + return dev->irq; > + } else return 0; > +} > + > +/* Do platform specific device initialization at pci_enable_device() time */ > +int pcibios_plat_dev_init(struct pci_dev *dev) > +{ > + return 0; > +} > + > + > +static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) > +{ > + unsigned char c; > + > + printk("via686b fix: ISA bridge\n"); > + > + /* Enable I/O Recovery time */ > + pci_write_config_byte(pdev, 0x40, 0x08); > + > + /* Enable ISA refresh */ > + pci_write_config_byte(pdev, 0x41, 0x01); > + > + /* disable ISA line buffer */ > + pci_write_config_byte(pdev, 0x45, 0x00); > + > + /* Gate INTR, and flush line buffer */ > + pci_write_config_byte(pdev, 0x46, 0xe0); > + > + /* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */ > + //pci_write_config_byte(pdev, 0x47, 0x20); > + /* enable PCI Delay Transaction, Enable EISA ports 4D0/4D1. > + * enable time-out timer > + */ > + pci_write_config_byte(pdev, 0x47, 0xe6); > + > + /* enable level trigger on pci irqs: 9,10,11,13 */ > + /* important! without this PCI interrupts won't work */ > + outb(0x2e,0x4d1); > + > + /* 512 K PCI Decode */ > + pci_write_config_byte(pdev, 0x48, 0x01); > + > + /* Wait for PGNT before grant to ISA Master/DMA */ > + pci_write_config_byte(pdev, 0x4a, 0x84); > + > + /* Plug'n'Play */ > + /* Parallel DRQ 3, Floppy DRQ 2 (default) */ > + pci_write_config_byte(pdev, 0x50, 0x0e); > + > + /* IRQ Routing for Floppy and Parallel port */ > + /* IRQ 6 for floppy, IRQ 7 for parallel port */ > + pci_write_config_byte(pdev, 0x51, 0x76); > + > + /* IRQ Routing for serial ports (take IRQ 3 and 4) */ > + pci_write_config_byte(pdev, 0x52, 0x34); > + > + /* All IRQ's level triggered. */ > + pci_write_config_byte(pdev, 0x54, 0x00); > + > + > + /* route PIRQA-D irq */ > + pci_write_config_byte(pdev,0x55, 0x90); /* bit 7-4, PIRQA */ > + pci_write_config_byte(pdev,0x56, 0xba); /* bit 7-4, PIRQC; 3-0, PIRQB */ > + pci_write_config_byte(pdev,0x57, 0xd0); /* bit 7-4, PIRQD */ > + > + /* enable function 5/6, audio/modem */ > + pci_read_config_byte(pdev,0x85, &c); > + c &= ~(0x3<<2); > + pci_write_config_byte(pdev,0x85,c); > + > + printk("via686b fix: ISA bridge done\n"); > +} > + > + > +static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) > +{ > + printk("via686b fix: IDE\n"); > + > + /* Modify IDE controller setup */ > + pci_write_config_byte(pdev,PCI_LATENCY_TIMER, 48); > + pci_write_config_byte(pdev, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER); > + pci_write_config_byte(pdev, 0x40, 0x0b); > + /* legacy mode */ > + pci_write_config_byte(pdev, 0x42, 0x09); > +#if 1 /* play safe, otherwise we may see notebook's usb keyboard lockup */ > + /* disable read prefetch/write post buffers */ > + pci_write_config_byte(pdev, 0x41, 0x02); //0xf2); > + > + /* use 3/4 as fifo thresh hold */ > + pci_write_config_byte(pdev, 0x43, 0x0a);//qqqw > + > + pci_write_config_byte(pdev, 0x44, 0x00); > + > + pci_write_config_byte(pdev, 0x45, 0x00); > +#else > + pci_write_config_byte(pdev, 0x41, 0xc2); > + pci_write_config_byte(pdev, 0x43, 0x35); > + pci_write_config_byte(pdev, 0x44, 0x1c); > + > + pci_write_config_byte(pdev, 0x45, 0x10); > +#endif > + > + printk("via686b fix: IDE done\n"); > +} > + > +static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev) > +{ > + unsigned int val; > + unsigned char c; > + > + /* enable IO */ > + pci_write_config_byte(pdev, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER); > + pci_read_config_dword(pdev, 0x4, &val); > + pci_write_config_dword(pdev, 0x4, val | 1); > + > + /* route ac97 IRQ */ > + pci_write_config_byte(pdev, 0x3c, 9); > + pdev->irq = 9; > + printk("ac97 interrupt = 9\n"); > + > + pci_read_config_byte(pdev, 0x8, &c); > + printk("ac97 rev=%d\n",c); > + > + /* link control: enable link & SGD PCM output */ > + pci_write_config_byte(pdev, 0x41, 0xcc); > + > + /* disable game port, FM, midi, sb, enable write to reg2c-2f */ > + pci_write_config_byte(pdev, 0x42, 0x20); > + > + printk("Setting sub-vendor ID & device ID\n"); > + > + /* we are using Avance logic codec */ > + pci_write_config_word(pdev, 0x2c, 0x1005); > + pci_write_config_word(pdev, 0x2e, 0x4710); > + pci_read_config_dword(pdev, 0x2c, &val); > + printk("sub vendor-device id=%x\n",val); > + > + pci_write_config_byte(pdev, 0x42, 0x0); > +} > + > +static void __init loongson2e_fixup_pcimap(struct pci_dev *pdev) > +{ > + Bonito; > + static int first = 1; > + > + (void)pdev; > + if (first) first = 0; else return; > + > + /* local to PCI mapping: [256M,512M] -> [256M,512M]; differ from pmon */ > + /* > + * cpu address space [256M,448M] is window for accessing pci space > + * we set pcimap_lo[0,1,2] to map it to pci space [256M,448M] > + * pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0 > + */ > + /* 1,00 0110 ,0001 01,00 0000 */ > + BONITO_PCIMAP = 0x46140; > + //1, 00 0010, 0000,01, 00 0000 > + //BONITO_PCIMAP = 0x42040; > + > + /* > + * PCI to local mapping: [2G,2G+256M] -> [0,256M] > + */ > + BONITO_PCIBASE0 = 0x80000000; > + BONITO_PCIBASE1 = 0x00800000; > + BONITO_PCIBASE2 = 0x90000000; > + > +} > + > +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, loongson2e_fixup_pcimap); > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,loongson2e_686b_func0_fixup); > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,loongson2e_686b_func1_fixup); > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5,loongson2e_686b_func5_fixup); > + > diff --git a/arch/mips/pci/ops-lm2e.c b/arch/mips/pci/ops-lm2e.c > new file mode 100644 > index 0000000..c379241 > --- /dev/null > +++ b/arch/mips/pci/ops-lm2e.c > @@ -0,0 +1,150 @@ > +/* > + * ops-lm2e.c > + * > + * Copyright (C) 2004 ICT CAS > + * Author: Li xiaoyu, ICT CAS > + * lixy@ict.ac.cn > + * > + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > + > +#include > +#include > +#include > + > +#include > + > +#define PCI_ACCESS_READ 0 > +#define PCI_ACCESS_WRITE 1 > + > +static inline void > +bflush (void) > +{ > + Bonito; > + /* flush Bonito register writes */ > + (void) BONITO_PCICMD; > +} > +static int lm2e_pci_config_access(unsigned char access_type, > + struct pci_bus *bus, unsigned int devfn, int where, u32 * data) > +{ > + Bonito; > + > + unsigned char busnum = bus->number; > + > + u_int32_t addr, type; In Linux the use of u32 is prefered over u_int32_t. > + void *addrp; > + int device = devfn >> 3; already has a macro for this: device = PCI_FUNC(devfn); > + int function = devfn & 0x7; already has a macro for this: function = PCI_SLOT(devfn); > + int reg = where & ~3; The address will always be suitably aligned. If not blame the caller :-) > + if (busnum == 0) { > + /* Type 0 configuration on onboard PCI bus */ > + if (device > 20 || function > 7) { > + *data = -1; /* device out of range */ > + return PCIBIOS_DEVICE_NOT_FOUND; > + } > + addr = (1 << (device+11)) | (function << 8) | reg; > + type = 0; > + } else { > + /* Type 1 configuration on offboard PCI bus */ > + if (device > 31 || function > 7) { > + *data = -1; /* device out of range */ > + return PCIBIOS_DEVICE_NOT_FOUND; > + } > + addr = (busnum << 16) | (device << 11) | (function << 8) | reg; > + type = 0x10000; > + } > + > + /* clear aborts */ > + BONITO_PCICMD |= BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT; > + > + BONITO_PCIMAP_CFG = (addr >> 16) | type; > + bflush (); ^ No space between function call and following opening parenthesis. > + > + addrp = (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (addr & 0xffff)); > + if (access_type == PCI_ACCESS_WRITE){ > + *(volatile unsigned int *)addrp = cpu_to_le32(*data); > + }else { ^ Space. > + *data = le32_to_cpu(*(volatile unsigned int *)addrp); > + } > + if (BONITO_PCICMD & (BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT)) { > + BONITO_PCICMD |= BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT; > + *data = -1; > + return PCIBIOS_DEVICE_NOT_FOUND; Indentation. > + } > + > + return PCIBIOS_SUCCESSFUL; > + > +} > + > + > +static int lm2e_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn, > + int where, int size, u32 * val) > +{ > + u32 data = 0; > + > + if (lm2e_pci_config_access(PCI_ACCESS_READ, bus, devfn, where,&data)) > + return PCIBIOS_DEVICE_NOT_FOUND; > + > + if (size == 1) > + *val = (data >> ((where & 3) << 3)) & 0xff; > + else if (size == 2) > + *val = (data >> ((where & 3) << 3)) & 0xffff; > + else > + *val = data; > + > + return PCIBIOS_SUCCESSFUL; > +} > + > + > +static int lm2e_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn, > + int where, int size, u32 val) > +{ > + u32 data = 0; > + > + if (size == 4) > + data = val; > + else { > + if (lm2e_pci_config_access(PCI_ACCESS_READ, bus, devfn,where, &data)) > + return PCIBIOS_DEVICE_NOT_FOUND; > + > + if (size == 1) > + data = (data & ~(0xff << ((where & 3) << 3))) | > + (val << ((where & 3) << 3)); > + else if (size == 2) > + data = (data & ~(0xffff << ((where & 3) << 3))) | > + (val << ((where & 3) << 3)); > + } > + > + if (lm2e_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where,&data)) > + return PCIBIOS_DEVICE_NOT_FOUND; > + > + return PCIBIOS_SUCCESSFUL; > +} > + > +struct pci_ops loongson2e_pci_pci_ops = { > + .read = lm2e_pci_pcibios_read, > + .write = lm2e_pci_pcibios_write > +}; > diff --git a/include/asm-mips/mach-lemote/bonito.h b/include/asm-mips/mach-lemote/bonito.h > new file mode 100644 > index 0000000..f453587 > --- /dev/null > +++ b/include/asm-mips/mach-lemote/bonito.h > @@ -0,0 +1,395 @@ > +/* > + * Based on Algorithmics header > + */ > + > +#ifndef _BONITO_H > +#define _BONITI_H > + > +#ifdef __ASSEMBLER__ > + > +/* offsets from base register */ > +#define BONITO(x) (x) > + > +#else /* !__ASSEMBLER */ > + > +/* offsets from base pointer, this construct allows optimisation */ > +/* static char * const _bonito = PA_TO_KVA1(BONITO_BASE); */ > +#define BONITO(x) *(volatile unsigned int *)(_bonito + (x)) > + > +#endif /* __ASSEMBLER__ */ > + > + > +#define BONITO_BOOT_BASE 0x1fc00000 > +#define BONITO_BOOT_SIZE 0x00100000 > +#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) > +#define BONITO_FLASH_BASE 0x1c000000 > +#define BONITO_FLASH_SIZE 0x03000000 > +#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) > +#define BONITO_SOCKET_BASE 0x1f800000 > +#define BONITO_SOCKET_SIZE 0x00400000 > +#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) > +#define BONITO_REG_BASE 0x1fe00000 > +#define BONITO_REG_SIZE 0x00040000 > +#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) > +#define BONITO_DEV_BASE 0x1ff00000 > +#define BONITO_DEV_SIZE 0x00100000 > +#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) > +#define BONITO_PCILO_BASE 0x10000000 > +#define BONITO_PCILO_SIZE 0x0c000000 > +#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) > +#define BONITO_PCILO0_BASE 0x10000000 > +#define BONITO_PCILO1_BASE 0x14000000 > +#define BONITO_PCILO2_BASE 0x18000000 > +#define BONITO_PCIHI_BASE 0x20000000 > +#define BONITO_PCIHI_SIZE 0x20000000 > +#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) > +#define BONITO_PCIIO_BASE 0x1fd00000 > +#define BONITO_PCIIO_SIZE 0x00100000 > +#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) > +#define BONITO_PCICFG_BASE 0x1fe80000 > +#define BONITO_PCICFG_SIZE 0x00080000 > +#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) > + > + > +/* Bonito Register Bases */ > + > +#define BONITO_PCICONFIGBASE 0x00 > +#define BONITO_REGBASE 0x100 > + > + > +/* PCI Configuration Registers */ > + > +#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) > +#define BONITO_PCIDID BONITO_PCI_REG(0x00) > +#define BONITO_PCICMD BONITO_PCI_REG(0x04) > +#define BONITO_PCICLASS BONITO_PCI_REG(0x08) > +#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c) > +#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) > +#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) > +#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) > +#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30) > +#define BONITO_PCIINT BONITO_PCI_REG(0x3c) > + > +#define BONITO_PCICMD_PERR 0x80000000 > +#define BONITO_PCICMD_SERR 0x40000000 > +#define BONITO_PCICMD_MABORT 0x20000000 > +#define BONITO_PCICMD_MTABORT 0x10000000 > +#define BONITO_PCICMD_TABORT 0x08000000 > +#define BONITO_PCICMD_MPERR 0x01000000 > +#define BONITO_PCICMD_PERRRESPEN 0x00000040 > +#define BONITO_PCICMD_ASTEPEN 0x00000080 > +#define BONITO_PCICMD_SERREN 0x00000100 > +#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00 > +#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8 > + > + > + > + > +/* 1. Bonito h/w Configuration */ > +/* Power on register */ > + > +#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00) > + > +#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000 > +#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000 > +#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000 > +#define BONITO_BONPONCFG_CPUBIGEND 0x00004000 > +#define BONITO_BONPONCFG_CPUPARITY 0x00002000 > +#define BONITO_BONPONCFG_CPUTYPE 0x00000007 > +#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0 > +#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008 > +#define BONITO_BONPONCFG_IS_ARBITER 0x00000010 > +#define BONITO_BONPONCFG_ROMBOOT 0x000000c0 > +#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6 > + > +#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0< +#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1< +#define BONITO_BONPONCFG_ROMBOOT_SDRAM (0x2< +#define BONITO_BONPONCFG_ROMBOOT_CPURESET (0x3< + > +#define BONITO_BONPONCFG_ROMCS0WIDTH 0x00000100 > +#define BONITO_BONPONCFG_ROMCS1WIDTH 0x00000200 > +#define BONITO_BONPONCFG_ROMCS0FAST 0x00000400 > +#define BONITO_BONPONCFG_ROMCS1FAST 0x00000800 > +#define BONITO_BONPONCFG_CONFIG_DIS 0x00000020 > + > + > +/* Other Bonito configuration */ > + > +#define BONITO_BONGENCFG_OFFSET 0x4 > +#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET) > + > +#define BONITO_BONGENCFG_DEBUGMODE 0x00000001 > +#define BONITO_BONGENCFG_SNOOPEN 0x00000002 > +#define BONITO_BONGENCFG_CPUSELFRESET 0x00000004 > + > +#define BONITO_BONGENCFG_FORCE_IRQA 0x00000008 > +#define BONITO_BONGENCFG_IRQA_ISOUT 0x00000010 > +#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020 > +#define BONITO_BONGENCFG_BYTESWAP 0x00000040 > + > +#define BONITO_BONGENCFG_UNCACHED 0x00000080 > +#define BONITO_BONGENCFG_PREFETCHEN 0x00000100 > +#define BONITO_BONGENCFG_WBEHINDEN 0x00000200 > +#define BONITO_BONGENCFG_CACHEALG 0x00000c00 > +#define BONITO_BONGENCFG_CACHEALG_SHIFT 10 > +#define BONITO_BONGENCFG_PCIQUEUE 0x00001000 > +#define BONITO_BONGENCFG_CACHESTOP 0x00002000 > +#define BONITO_BONGENCFG_MSTRBYTESWAP 0x00004000 > +#define BONITO_BONGENCFG_BUSERREN 0x00008000 > +#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000 > +#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT 0x00020000 > + > +/* 2. IO & IDE configuration */ > + > +#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08) > + > +/* 3. IO & IDE configuration */ > + > +#define BONITO_SDCFG BONITO(BONITO_REGBASE + 0x0c) > + > +/* 4. PCI address map control */ > + > +#define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10) > +#define BONITO_PCIMEMBASECFG BONITO(BONITO_REGBASE + 0x14) > +#define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18) > + > +/* 5. ICU & GPIO regs */ > + > +/* GPIO Regs - r/w */ > + > +#define BONITO_GPIODATA_OFFSET 0x1c > +#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET) > +#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20) > + > +/* ICU Configuration Regs - r/w */ > + > +#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24) > +#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28) > +#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c) > + > +/* ICU Enable Regs - IntEn & IntISR are r/o. */ > + > +#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30) > +#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34) > +#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38) > +#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c) > + > +/* PCI mail boxes */ > + > +#define BONITO_PCIMAIL0_OFFSET 0x40 > +#define BONITO_PCIMAIL1_OFFSET 0x44 > +#define BONITO_PCIMAIL2_OFFSET 0x48 > +#define BONITO_PCIMAIL3_OFFSET 0x4c > +#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40) > +#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44) > +#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48) > +#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c) > + > + > +/* 6. PCI cache */ > + > +#define BONITO_PCICACHECTRL BONITO(BONITO_REGBASE + 0x50) > +#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54) > + > +#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58) > +#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c) > + > + > +/* > +#define BONITO_PCIRDPOST BONITO(BONITO_REGBASE + 0x60) > +#define BONITO_PCIDATA BONITO(BONITO_REGBASE + 0x64) > +*/ > + > +/* 7. IDE DMA & Copier */ > + > +#define BONITO_CONFIGBASE 0x000 > +#define BONITO_BONITOBASE 0x100 > +#define BONITO_LDMABASE 0x200 > +#define BONITO_COPBASE 0x300 > +#define BONITO_REG_BLOCKMASK 0x300 > + > +#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0) > +#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0) > +#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4) > +#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8) > +#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc) > + > +#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0) > +#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0) > +#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4) > +#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8) > +#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc) > + > + > +/* ###### Bit Definitions for individual Registers #### */ > + > +/* Gen DMA. */ > + > +#define BONITO_IDECOPDADDR_DMA_DADDR 0x0ffffffc > +#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT 2 > +#define BONITO_IDECOPPADDR_DMA_PADDR 0xfffffffc > +#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT 2 > +#define BONITO_IDECOPGO_DMA_SIZE 0x0000fffe > +#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0 > +#define BONITO_IDECOPGO_DMA_WRITE 0x00010000 > +#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000 > +#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16 > + > +#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000 > +#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000 > + > +/* DRAM - sdCfg */ > + > +#define BONITO_SDCFG_AROWBITS 0x00000003 > +#define BONITO_SDCFG_AROWBITS_SHIFT 0 > +#define BONITO_SDCFG_ACOLBITS 0x0000000c > +#define BONITO_SDCFG_ACOLBITS_SHIFT 2 > +#define BONITO_SDCFG_ABANKBIT 0x00000010 > +#define BONITO_SDCFG_ASIDES 0x00000020 > +#define BONITO_SDCFG_AABSENT 0x00000040 > +#define BONITO_SDCFG_AWIDTH64 0x00000080 > + > +#define BONITO_SDCFG_BROWBITS 0x00000300 > +#define BONITO_SDCFG_BROWBITS_SHIFT 8 > +#define BONITO_SDCFG_BCOLBITS 0x00000c00 > +#define BONITO_SDCFG_BCOLBITS_SHIFT 10 > +#define BONITO_SDCFG_BBANKBIT 0x00001000 > +#define BONITO_SDCFG_BSIDES 0x00002000 > +#define BONITO_SDCFG_BABSENT 0x00004000 > +#define BONITO_SDCFG_BWIDTH64 0x00008000 > + > +#define BONITO_SDCFG_EXTRDDATA 0x00010000 > +#define BONITO_SDCFG_EXTRASCAS 0x00020000 > +#define BONITO_SDCFG_EXTPRECH 0x00040000 > +#define BONITO_SDCFG_EXTRASWIDTH 0x00180000 > +#define BONITO_SDCFG_EXTRASWIDTH_SHIFT 19 > +#define BONITO_SDCFG_DRAMRESET 0x00200000 > +#define BONITO_SDCFG_DRAMEXTREGS 0x00400000 > +#define BONITO_SDCFG_DRAMPARITY 0x00800000 > + > +/* PCI Cache - pciCacheCtrl */ > + > +#define BONITO_PCICACHECTRL_CACHECMD 0x00000007 > +#define BONITO_PCICACHECTRL_CACHECMD_SHIFT 0 > +#define BONITO_PCICACHECTRL_CACHECMDLINE 0x00000018 > +#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3 > +#define BONITO_PCICACHECTRL_CMDEXEC 0x00000020 > + > +#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001 > +#define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002 > +#define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004 > + > +#define BONITO_IODEVCFG_BUFFBIT_CS1 0x00000008 > +#define BONITO_IODEVCFG_SPEEDBIT_CS1 0x00000010 > +#define BONITO_IODEVCFG_MOREABITS_CS1 0x00000020 > + > +#define BONITO_IODEVCFG_BUFFBIT_CS2 0x00000040 > +#define BONITO_IODEVCFG_SPEEDBIT_CS2 0x00000080 > +#define BONITO_IODEVCFG_MOREABITS_CS2 0x00000100 > + > +#define BONITO_IODEVCFG_BUFFBIT_CS3 0x00000200 > +#define BONITO_IODEVCFG_SPEEDBIT_CS3 0x00000400 > +#define BONITO_IODEVCFG_MOREABITS_CS3 0x00000800 > + > +#define BONITO_IODEVCFG_BUFFBIT_IDE 0x00001000 > +#define BONITO_IODEVCFG_SPEEDBIT_IDE 0x00002000 > +#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000 > +#define BONITO_IODEVCFG_MODEBIT_IDE 0x00008000 > +#define BONITO_IODEVCFG_DMAON_IDE 0x001f0000 > +#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16 > +#define BONITO_IODEVCFG_DMAOFF_IDE 0x01e00000 > +#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT 21 > +#define BONITO_IODEVCFG_EPROMSPLIT 0x02000000 > + > +/* gpio */ > +#define BONITO_GPIO_GPIOW 0x000003ff > +#define BONITO_GPIO_GPIOW_SHIFT 0 > +#define BONITO_GPIO_GPIOR 0x01ff0000 > +#define BONITO_GPIO_GPIOR_SHIFT 16 > +#define BONITO_GPIO_GPINR 0xfe000000 > +#define BONITO_GPIO_GPINR_SHIFT 25 > +#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N))) > +#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N))) > +#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N))) > + > +/* ICU */ > +#define BONITO_ICU_MBOXES 0x0000000f > +#define BONITO_ICU_MBOXES_SHIFT 0 > +#define BONITO_ICU_DMARDY 0x00000010 > +#define BONITO_ICU_DMAEMPTY 0x00000020 > +#define BONITO_ICU_COPYRDY 0x00000040 > +#define BONITO_ICU_COPYEMPTY 0x00000080 > +#define BONITO_ICU_COPYERR 0x00000100 > +#define BONITO_ICU_PCIIRQ 0x00000200 > +#define BONITO_ICU_MASTERERR 0x00000400 > +#define BONITO_ICU_SYSTEMERR 0x00000800 > +#define BONITO_ICU_DRAMPERR 0x00001000 > +#define BONITO_ICU_RETRYERR 0x00002000 > +#define BONITO_ICU_GPIOS 0x01ff0000 > +#define BONITO_ICU_GPIOS_SHIFT 16 > +#define BONITO_ICU_GPINS 0x7e000000 > +#define BONITO_ICU_GPINS_SHIFT 25 > +#define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N))) > +#define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N))) > +#define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N))) > + > +/* pcimap */ > + > +#define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f > +#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0 > +#define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0 > +#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6 > +#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 > +#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 > +#define BONITO_PCIMAP_PCIMAP_2 0x00040000 > +#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) > + > +#define BONITO_PCIMAP_WINSIZE (1<<26) > +#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) > +#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) > + > +/* pcimembaseCfg */ > + > +#define BONITO_PCIMEMBASECFG_MASK 0xf0000000 > +#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f > +#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0 > +#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0 > +#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5 > +#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400 > +#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800 > + > +#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000 > +#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12 > +#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000 > +#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17 > +#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000 > +#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000 > + > +#define BONITO_PCIMEMBASECFG_ASHIFT 23 > +#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff > +#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) > +#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) > + > +#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) > + > + > +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) > +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) > +#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) > + > +#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ > + (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ > + (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ > + ) > + > +/* PCICmd */ > + > +#define BONITO_PCICMD_MEMEN 0x00000002 > +#define BONITO_PCICMD_MSTREN 0x00000004 > + > +#define Bonito static char * const _bonito = (char * const )CKSEG1ADDR(BONITO_REG_BASE) This one makes the code a bit odd to read ... > + > +#define BONITO_IRQ_BASE 32 > + > +#endif /* !_BONITO_H */ > diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h > new file mode 100644 > index 0000000..1df8b4d > --- /dev/null > +++ b/include/asm-mips/mach-lemote/dma-coherence.h > @@ -0,0 +1,43 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2006 Ralf Baechle > + * > + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + */ > +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H > +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H > + > +struct device; > + > +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, > + size_t size) > +{ > + return virt_to_phys(addr) | 0x80000000; > +} > + > +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, > + struct page *page) > +{ > + return page_to_phys(page) | 0x80000000; > +} > + > +static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) > +{ > + return dma_addr & 0x7fffffff; > +} > + > +static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) > +{ > +} > + > +static inline int plat_device_is_coherent(struct device *dev) > +{ > + return 0; > +} > + > +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ > diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h > new file mode 100644 > index 0000000..7850f89 > --- /dev/null > +++ b/include/asm-mips/mach-lemote/mc146818rtc.h > @@ -0,0 +1,36 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 1998, 2001, 03 by Ralf Baechle > + * > + * RTC routines for PC style attached Dallas chip. > + */ > +#ifndef __ASM_MACH_GENERIC_MC146818RTC_H > +#define __ASM_MACH_GENERIC_MC146818RTC_H > + > +#include > + > +#define RTC_PORT(x) (0x70 + (x)) > +#define RTC_IRQ 8 > + > +static inline unsigned char CMOS_READ(unsigned long addr) > +{ > + outb_p(addr, RTC_PORT(0)); > + return inb_p(RTC_PORT(1)); > +} > + > +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) > +{ > + outb_p(addr, RTC_PORT(0)); > + outb_p(data, RTC_PORT(1)); > +} > + > +#define RTC_ALWAYS_BCD 0 > + > +#ifndef mc146818_decode_year > +#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) > +#endif > + > +#endif /* __ASM_MACH_GENERIC_MC146818RTC_H */ > -- > 1.4.4.4 > > Ralf From harsh512@yahoo.com Tue Apr 10 01:32:52 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Apr 2007 01:32:54 +0100 (BST) Received: from web53805.mail.re2.yahoo.com ([206.190.36.200]:15026 "HELO web53805.mail.re2.yahoo.com") by ftp.linux-mips.org with SMTP id S20023099AbXDJAcw (ORCPT ); Tue, 10 Apr 2007 01:32:52 +0100 Received: (qmail 45686 invoked by uid 60001); 10 Apr 2007 00:31:46 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:X-YMail-OSG:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=NUAg+sRncJRDBwv7gXLTunNYhCaci75i3uPq4j02NZZmo6rcDJFK0bY5vPBUv39bKREvTq3rkHn7HvBIxL9ehykFwp0V5m4vlubQZnkvWfEM/0bw7qIEg2qG0X/Yd9lA9BadtWh/tRJa8VbBx9l+5qPSg93M63gt9UJBLDiHY0w= ; Message-ID: <20070410003146.45684.qmail@web53805.mail.re2.yahoo.com> X-YMail-OSG: BkxMcj0VM1nulVNbHLW.81E0Q7anLDL.hsM9Gp4dujAvrDAXX6fOm05GRpZ1nMMEJ8zfdqA6688D9Go6pTS9Ch74PgLRqisuZEzn5KSeIsMZZ8FObMASHBvSRsmtqA-- Received: from [76.192.205.82] by web53805.mail.re2.yahoo.com via HTTP; Mon, 09 Apr 2007 17:31:46 PDT Date: Mon, 9 Apr 2007 17:31:46 -0700 (PDT) From: h h Subject: Re: Describing Physical RAM Map to Linux To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="0-2092484646-1176165106=:44285" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14827 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: harsh512@yahoo.com Precedence: bulk X-list: linux-mips --0-2092484646-1176165106=:44285 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit On Sat, Apr 07, 2007 at 02:59:15PM -0700, h h wrote: > I have a very basic question -- When describing physical memory to the kernel > in prom_init(), should we describe the physical memory region where kernel is > loaded or leave it out? We are using add_memory_region() call to describe > physical memory to the kernel. If we do describe the memory region where > kernel is loaded, how will kernel know not to use these pages for User > processes? Ralf wrote: The kernel does this automatically. --- Sorry I don't quite understand -- What does kernel do automatically? How does kernel automatically know how much RAM is installed? If you mean kernel automatically reserves the memory it is loaded in, my question is where is this being done? I am expecting calls to alloc_bootmem or reserve_bootmem with addresses for text/data/stack regions of kernel, but I don't see them. Any pointers would be appreciated. Thanks, --------------------------------- Need Mail bonding? Go to the Yahoo! Mail Q&A for great tips from Yahoo! Answers users. --0-2092484646-1176165106=:44285 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit 


On Sat, Apr 07, 2007 at 02:59:15PM -0700, h h wrote:

> I have a very basic question -- When describing physical memory to the kernel 
> in prom_init(), should we describe the physical memory region where kernel is 
> loaded or leave it out?  We are using add_memory_region() call to describe 
> physical memory to the kernel.  If we do describe the memory region where 
> kernel is loaded, how will kernel know not to use these pages for User 
> processes?

Ralf wrote:
The kernel does this automatically.

---

Sorry I don't quite understand -- What does kernel do 
automatically?  
How does kernel automatically know how much RAM is 
installed?

If you mean kernel automatically reserves
 the memory
it is loaded in, my question is where is this being 
done? I am expecting calls to alloc_bootmem or 
reserve_bootmem with addresses for text/data/stack
regions of kernel, but I don't see them.

Any pointers would be appreciated.


Thanks,

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Answers users. --0-2092484646-1176165106=:44285-- From macro@linux-mips.org Tue Apr 10 16:50:41 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Apr 2007 16:50:43 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:51974 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20021719AbXDJPul (ORCPT ); Tue, 10 Apr 2007 16:50:41 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id ADF26E1CAD; Tue, 10 Apr 2007 17:49:59 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LxiKL6ti4j6F; Tue, 10 Apr 2007 17:49:59 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 69FD2E1C6B; Tue, 10 Apr 2007 17:49:59 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.8) with ESMTP id l3AFoCo4023676; Tue, 10 Apr 2007 17:50:12 +0200 Date: Tue, 10 Apr 2007 16:50:07 +0100 (BST) From: "Maciej W. Rozycki" To: Thomas Bogendoerfer cc: Sergei Shtylyov , linux-mips@linux-mips.org Subject: Re: [PATCH] Change PCI host bridge setup/resources In-Reply-To: <20070409151630.GA9284@alpha.franken.de> Message-ID: References: <20070408113457.GB7553@alpha.franken.de> <4619245F.4030704@ru.mvista.com> <20070408230710.GA9092@alpha.franken.de> <461A50E0.1060602@ru.mvista.com> <20070409151630.GA9284@alpha.franken.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.90.1/3061/Tue Apr 10 13:56:50 2007 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14828 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 9 Apr 2007, Thomas Bogendoerfer wrote: > > To me, it doesn't make much sense with or without reading the code. > > And note that no other boards claim ports 0x0000 thru 0x0fff to PCI. > > no other board MIPS board has EISA behind PCI afaik. So this is a new > situation. To everybody involved: quite a few Alpha boxes use the PCEB bridge, which may or may not be the same as in here, so they may be used as a reference of how things may be set up. Though, being quite an old port, this code may not necessarily represent the best approach possible. Personally I think ISA and EISA resources that are behind a PCI bus (or any other, for that matter) should be registered as descendants to that bus. It's only the PC architecture that makes (E)ISA resources special -- almost any other platform will relocate them arbitrarily (they will not start from zero in the host address space, which may even have no notion of the I/O address space at all) and may have multiple copies if multiple PCI buses are used in a non-tree configuration. It may be useful to register PCI I/O windows in the MMIO space as appropriate too. Also mapping PCI I/O addresses from 0 does make sense in some actual hardware configurations which do not have any legacy bridges involved, so making sure code is prepared to do this is not an unreasonable thing to do. There is currently (or used to be, not so long ago) a problem with some code somewhere as I tried such a setup with a SWARM board and I recall getting a failure somewhere, which I mean to get back to at one point. Maciej From compudj@krystal.dyndns.org Wed Apr 11 01:45:30 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Apr 2007 01:45:33 +0100 (BST) Received: from bc.sympatico.ca ([209.226.175.184]:38124 "EHLO tomts22-srv.bellnexxia.net") by ftp.linux-mips.org with ESMTP id S20022140AbXDKApa convert rfc822-to-8bit (ORCPT ); Wed, 11 Apr 2007 01:45:30 +0100 Received: from krystal.dyndns.org ([65.95.37.112]) by tomts22-srv.bellnexxia.net (InterMail vM.5.01.06.13 201-253-122-130-113-20050324) with ESMTP id <20070411004341.NWUJ1767.tomts22-srv.bellnexxia.net@krystal.dyndns.org> for ; Tue, 10 Apr 2007 20:43:41 -0400 Received: from localhost (localhost [127.0.0.1]) (uid 1000) by krystal.dyndns.org with local; Tue, 10 Apr 2007 20:43:41 -0400 id 000DFC8D.461C2F3D.00004161 Date: Tue, 10 Apr 2007 20:43:41 -0400 From: Mathieu Desnoyers To: Andrew Morton , linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Subject: 2.6.21-rc6-mm1 build error with mips Message-ID: <20070411004341.GB15262@Krystal> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 8BIT X-Editor: vi X-Info: http://krystal.dyndns.org:8080 X-Operating-System: Linux/2.4.34-grsec (i686) X-Uptime: 20:41:14 up 67 days, 14:48, 3 users, load average: 1.65, 1.53, 1.33 User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14829 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mathieu.desnoyers@polymtl.ca Precedence: bulk X-list: linux-mips Hi Andrew, I get the following error when compiling 2.6.21-rc6-mm1 for MIPS : /opt/crosstool/gcc-3.4.5-glibc-2.3.6/mips-unknown-linux-gnu/bin/mips-unknown-linux-gnu-gcc -Wp,-MD,arch/mips/sgi-ip22/.ip22-time.o.d -nostdinc -isystem /opt/crosstool/gcc-3.4.5-glibc-2.3.6/mips-unknown-linux-gnu/lib/gcc/mips-unknown-linux-gnu/3.4.5/include -D__KERNEL__ -Iinclude -Iinclude2 -I/home/compudj/git/linux-2.6-lttng/include -include include/linux/autoconf.h -I/home/compudj/git/linux-2.6-lttng/arch/mips/sgi-ip22 -Iarch/mips/sgi-ip22 -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Os -mabi=32 -G 0 -mno-abicalls -fno-pic -pipe -msoft-float -ffreestanding -march=r5000 -Wa,--trap -I/home/compudj/git/linux-2.6-lttng/include/asm-mips/mach-ip22 -Iinclude/asm-mips/mach-ip22 -I/home/compudj/git/linux-2.6-lttng/include/asm-mips/mach-generic -Iinclude/asm-mips/mach-generic -fomit-frame-pointer -Wdeclaration-after-statement -D"KBUILD_STR(s)=#s" -D"KBUILD_BASENAME=KBUILD_STR(ip22_time)" -D"KBUILD_MODNAME=KBUILD_STR(ip22_time)" -c -o arch/mips/sgi-ip22/ip22-time.o /home/compudj/git/linux-2.6-lttng/arch/mips/sgi-ip22/ip22-time.c In file included from include2/asm/time.h:21, from /home/compudj/git/linux-2.6-lttng/arch/mips/sgi-ip22/ip22-time.c:25: /home/compudj/git/linux-2.6-lttng/include/linux/ptrace.h:64:27: asm/tracehook.h: No such file or directory In file included from include2/asm/time.h:21, from /home/compudj/git/linux-2.6-lttng/arch/mips/sgi-ip22/ip22-time.c:25: /home/compudj/git/linux-2.6-lttng/include/linux/ptrace.h: In function `ptrace_whole_regset': /home/compudj/git/linux-2.6-lttng/include/linux/ptrace.h:115: warning: implicit declaration of function `utrace_native_view' /home/compudj/git/linux-2.6-lttng/include/linux/ptrace.h:116: warning: passing arg 3 of `ptrace_regset_access' makes pointer from integer without a cast /home/compudj/git/linux-2.6-lttng/include/linux/ptrace.h: In function `ptrace_peekusr': /home/compudj/git/linux-2.6-lttng/include/linux/ptrace.h:166: warning: passing arg 3 of `ptrace_layout_access' makes pointer from integer without a cast /home/compudj/git/linux-2.6-lttng/include/linux/ptrace.h: In function `ptrace_pokeusr': /home/compudj/git/linux-2.6-lttng/include/linux/ptrace.h:177: warning: passing arg 3 of `ptrace_layout_access' makes pointer from integer without a cast /home/compudj/git/linux-2.6-lttng/arch/mips/sgi-ip22/ip22-time.c: In function `dosample': /home/compudj/git/linux-2.6-lttng/arch/mips/sgi-ip22/ip22-time.c:118: warning: passing arg 2 of `writeb' makes pointer from integer without a cast My .config : # # Automatically generated make config: don't edit # Linux kernel version: 2.6.21-rc6-mm1 # Tue Apr 10 16:33:18 2007 # CONFIG_MIPS=y # # Machine selection # CONFIG_ZONE_DMA=y # CONFIG_MIPS_MTX1 is not set # CONFIG_MIPS_BOSPORUS is not set # CONFIG_MIPS_PB1000 is not set # CONFIG_MIPS_PB1100 is not set # CONFIG_MIPS_PB1500 is not set # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_PB1200 is not set # CONFIG_MIPS_DB1000 is not set # CONFIG_MIPS_DB1100 is not set # CONFIG_MIPS_DB1500 is not set # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set # CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_MOMENCO_OCELOT_3 is not set # CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set # CONFIG_MARKEINS is not set CONFIG_SGI_IP22=y # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_TIME=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y CONFIG_SYS_HAS_EARLY_PRINTK=y CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y CONFIG_ARC32=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_ARC_CONSOLE is not set CONFIG_ARC_PROMLIB=y # # CPU selection # # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set # CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set CONFIG_SYS_HAS_CPU_R4X00=y CONFIG_SYS_HAS_CPU_R5000=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y # # Kernel type # CONFIG_32BIT=y # CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y CONFIG_IP22_CPU_SCACHE=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set # CONFIG_64BIT_PHYS_ADDR is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_ADAPTIVE_READAHEAD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set CONFIG_HZ_250=y # CONFIG_HZ_256 is not set # CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_HZ=250 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # # Code maturity level options # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SWAP_PREFETCH=y CONFIG_SYSVIPC=y # CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_SYSFS_DEPRECATED=y # CONFIG_RELAY is not set # CONFIG_BLK_DEV_INITRD is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set # CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PROC_SMAPS=y CONFIG_PROC_CLEAR_REFS=y CONFIG_PROC_PAGEMAP=y CONFIG_PROC_KPAGEMAP=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_PAGE_GROUP_BY_MOBILITY=y # # Loadable module support # CONFIG_MODULES=y # CONFIG_MODULE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_KMOD=y # # Process debugging support # CONFIG_UTRACE=y CONFIG_PTRACE=y # # Block layer # CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_EISA=y # CONFIG_EISA is not set CONFIG_MMU=y # # PCCARD (PCMCIA/CardBus) support # # # PCI Hotplug Support # # # Executable file formats # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y # CONFIG_PM is not set # # Networking # CONFIG_NET=y # # Networking options # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_IP_MROUTE is not set # CONFIG_ARPD is not set # CONFIG_SYN_COOKIES is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set # CONFIG_INET6_XFRM_TUNNEL is not set # CONFIG_INET6_TUNNEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # # DCCP Configuration (EXPERIMENTAL) # # CONFIG_IP_DCCP is not set # # SCTP Configuration (EXPERIMENTAL) # # CONFIG_IP_SCTP is not set # # TIPC Configuration (EXPERIMENTAL) # # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # # QoS and/or fair queueing # # CONFIG_NET_SCHED is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # # Wireless # # CONFIG_CFG80211 is not set # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set # # Device Drivers # # # Generic Driver Options # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_SYS_HYPERVISOR is not set # # Connector - unified userspace <-> kernelspace linker # # CONFIG_CONNECTOR is not set # # Memory Technology Devices (MTD) # # CONFIG_MTD is not set # # Parallel port support # # CONFIG_PARPORT is not set # # Plug and Play support # # CONFIG_PNPACPI is not set # # Block devices # # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # # Misc devices # # # ATA/ATAPI/MFM/RLL support # # CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y # CONFIG_CHR_DEV_OSST is not set CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # # CONFIG_SCSI_MULTI_LUN is not set CONFIG_SCSI_CONSTANTS=y # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # # SCSI low-level drivers # # CONFIG_ISCSI_TCP is not set CONFIG_SGIWD93_SCSI=y # CONFIG_SCSI_DEBUG is not set # # Serial ATA (prod) and Parallel ATA (experimental) drivers # # CONFIG_ATA is not set # # Multi-device support (RAID and LVM) # # CONFIG_MD is not set # # Fusion MPT device support # # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # # CONFIG_FIREWIRE is not set # # I2O device support # # # Network device support # CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # # PHY device support # # CONFIG_PHYLIB is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y # CONFIG_MII is not set # CONFIG_DM9000 is not set # CONFIG_B44 is not set CONFIG_SGISEEQ=y # # Ethernet (1000 Mbit) # # # Ethernet (10000 Mbit) # # # Token Ring devices # # # Wireless LAN # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set # CONFIG_RTL818X is not set # # Wan interfaces # # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem # # CONFIG_ISDN is not set # # Telephony Support # # CONFIG_PHONE is not set # # Input device support # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # # Userland interfaces # # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_STOWAWAY is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_I8042=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set # CONFIG_SERIAL_NONSTANDARD is not set # # Serial drivers # # CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # # CONFIG_SERIAL_IP22_ZILOG is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # # IPMI # # CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set # # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set CONFIG_INDYDOG=y CONFIG_HW_RANDOM=m # CONFIG_RTC is not set CONFIG_SGI_DS1286=y # CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # # TPM devices # # CONFIG_TCG_TPM is not set # # I2C support # # CONFIG_I2C is not set # # SPI support # # CONFIG_SPI is not set # CONFIG_SPI_MASTER is not set # # Dallas's 1-wire bus # # CONFIG_W1 is not set # # Hardware Monitoring support # CONFIG_HWMON=y # CONFIG_HWMON_VID is not set # CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_HWMON_DEBUG_CHIP is not set # # Sonics Silicon Backplane # # CONFIG_SSB is not set # # Multifunction device drivers # # CONFIG_MFD_SM501 is not set # # Multimedia devices # # CONFIG_VIDEO_DEV is not set # # Digital Video Broadcasting Devices # # CONFIG_DVB is not set # # Graphics support # # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_FB is not set # # Console display driver support # # CONFIG_VGA_CONSOLE is not set CONFIG_SGI_NEWPORT_CONSOLE=y CONFIG_DUMMY_CONSOLE=y CONFIG_FONT_8x16=y # # Logo configuration # # CONFIG_LOGO is not set # # Sound # # CONFIG_SOUND is not set # # HID Devices # CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set # # USB support # # CONFIG_USB_ARCH_HAS_HCD is not set # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # # USB Gadget Support # # CONFIG_USB_GADGET is not set # # MMC/SD Card support # # CONFIG_MMC is not set # # LED devices # # CONFIG_NEW_LEDS is not set # # LED drivers # # # LED Triggers # # # InfiniBand support # # # EDAC - error detection and reporting (RAS) (EXPERIMENTAL) # # # Real Time Clock # # CONFIG_RTC_CLASS is not set # # DMA Engine support # # CONFIG_DMA_ENGINE is not set # # DMA Clients # # CONFIG_ASYNC_TX_DMA is not set # # DMA Devices # # # Auxiliary Display support # # # Virtualization # # # Userspace I/O # # CONFIG_UIO is not set # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_EXT4DEV_FS is not set # CONFIG_REISER4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y # CONFIG_FUSE_FS is not set # # CD-ROM/DVD Filesystems # CONFIG_ISO9660_FS=y # CONFIG_JOLIET is not set # CONFIG_ZISOFS is not set # CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # # CONFIG_MSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # # Pseudo filesystems # CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # # Layered filesystems # # CONFIG_UNION_FS is not set # # Miscellaneous filesystems # # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # # Network File Systems # CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set CONFIG_NFSD=y # CONFIG_NFSD_V3 is not set CONFIG_NFSD_TCP=y CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set # CONFIG_9P_FS is not set # # Partition Types # CONFIG_PARTITION_ADVANCED=y # CONFIG_ACORN_PARTITION is not set # CONFIG_OSF_PARTITION is not set # CONFIG_AMIGA_PARTITION is not set # CONFIG_ATARI_PARTITION is not set # CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y # CONFIG_BSD_DISKLABEL is not set # CONFIG_MINIX_SUBPARTITION is not set # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # # Native Language Support # # CONFIG_NLS is not set # # Distributed Lock Manager # # CONFIG_DLM is not set # # Profiling support # # CONFIG_PROFILING is not set # # Instrumentation Support # CONFIG_MARKERS=y # CONFIG_MARKERS_DISABLE_OPTIMIZATION is not set CONFIG_MARKERS_ENABLE_OPTIMIZATION=y # CONFIG_LTT is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_MUST_CHECK=y # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_PROFILE_LIKELY is not set CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="" # # Security options # # CONFIG_KEYS is not set # CONFIG_INTEGRITY is not set # CONFIG_SECURITY is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set # # Cryptographic options # # CONFIG_CRYPTO is not set # # Library routines # CONFIG_BITREVERSE=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC32=y # CONFIG_CRC_ITU_T is not set # CONFIG_LIBCRC32C is not set # CONFIG_EEPROM_93CX6 is not set CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -- Mathieu Desnoyers Computer Engineering Ph.D. Student, Ecole Polytechnique de Montreal OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F BA06 3F25 A8FE 3BAE 9A68 From redhatter@gentoo.org Wed Apr 11 05:45:39 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Apr 2007 05:45:41 +0100 (BST) Received: from 202-47-55-78.adsl.gil.com.au ([202.47.55.78]:37292 "EHLO longlandclan.hopto.org") by ftp.linux-mips.org with ESMTP id S20021622AbXDKEpj (ORCPT ); Wed, 11 Apr 2007 05:45:39 +0100 Received: (qmail 14428 invoked from network); 11 Apr 2007 04:44:28 -0000 Received: from unknown (HELO ?10.0.0.251?) (10.0.0.251) by www.longlandclan.hopto.org with SMTP; 11 Apr 2007 04:44:28 -0000 Message-ID: <461C67D2.1050301@gentoo.org> Date: Wed, 11 Apr 2007 14:45:06 +1000 From: Stuart Longland Organization: Gentoo Foundation User-Agent: Thunderbird 1.5.0.10 (X11/20070310) MIME-Version: 1.0 To: Mathieu Desnoyers CC: Andrew Morton , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: 2.6.21-rc6-mm1 build error with mips References: <20070411004341.GB15262@Krystal> In-Reply-To: <20070411004341.GB15262@Krystal> X-Enigmail-Version: 0.94.0.0 OpenPGP: id=63264AB9; url=http://dev.gentoo.org/~redhatter/gpgkey.asc Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enigCE94A3094E41841476C4EB83" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14830 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: redhatter@gentoo.org Precedence: bulk X-list: linux-mips This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enigCE94A3094E41841476C4EB83 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Mathieu Desnoyers wrote: > Hi Andrew, >=20 > I get the following error when compiling 2.6.21-rc6-mm1 for MIPS : >=20 >=20 > /opt/crosstool/gcc-3.4.5-glibc-2.3.6/mips-unknown-linux-gnu/bin/mips-= unknown-linux-gnu-gcc -Wp,-MD,arch/mips/sgi-ip22/.ip22-time.o.d -nostdin= c -isystem /opt/crosstool/gcc-3.4.5-glibc-2.3.6/mips-unknown-linux-gnu/li= b/gcc/mips-unknown-linux-gnu/3.4.5/include -D__KERNEL__ -Iinclude -Iinclu= de2 -I/home/compudj/git/linux-2.6-lttng/include -include include/linux/au= toconf.h -I/home/compudj/git/linux-2.6-lttng/arch/mips/sgi-ip22 -Iarch/mi= ps/sgi-ip22 -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-= aliasing -fno-common -Os -mabi=3D32 -G 0 -mno-abicalls -fno-pic -pipe -ms= oft-float -ffreestanding -march=3Dr5000 -Wa,--trap -I/home/compudj/git/li= nux-2.6-lttng/include/asm-mips/mach-ip22 -Iinclude/asm-mips/mach-ip22 -I/= home/compudj/git/linux-2.6-lttng/include/asm-mips/mach-generic -Iinclude/= asm-mips/mach-generic -fomit-frame-pointer -Wdeclaration-after-statement = -D"KBUILD_STR(s)=3D#s" -D"KBUILD_BASENAME=3DKBUILD_STR(ip22_time)" -D"K= BUILD_MODNAME=3DKBUILD_STR(ip22_time)" -c -o arch/m ips/sgi-ip22/ip22-time.o /home/compudj/git/linux-2.6-lttng/arch/mips/sgi-= ip22/ip22-time.c > In file included from include2/asm/time.h:21, > from /home/compudj/git/linux-2.6-lttng/arch/mips/sgi-i= p22/ip22-time.c:25: > /home/compudj/git/linux-2.6-lttng/include/linux/ptrace.h:64:27: asm/tra= cehook.h: No such file or directory Last I checked... only sources from linux-mips.org's git repository work. Other source trees need to be specially patched to build for MIPS.= Regards, --=20 Stuart Longland (aka Redhatter) .'''. Gentoo Linux/MIPS Cobalt and Docs Developer '.'` : =2E . . . . . . . . . . . . . . . . . . . . . .'.' http://dev.gentoo.org/~redhatter :.' I haven't lost my mind... ...it's backed up on a tape somewhere. --------------enigCE94A3094E41841476C4EB83 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5-ecc0.1.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFGHGfSuarJ1mMmSrkRAqV3AJ9hpbmPAQicWUjAFf6P/z0eNsWFAgCeJYmi wk9IghTdzfZO2TqCefrBPdo= =QHfn -----END PGP SIGNATURE----- --------------enigCE94A3094E41841476C4EB83-- From markus.gothe@27m.se Thu Apr 12 09:44:02 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Apr 2007 09:44:05 +0100 (BST) Received: from mail.lysator.liu.se ([130.236.254.3]:29151 "EHLO mail.lysator.liu.se") by ftp.linux-mips.org with ESMTP id S20022346AbXDLIoC (ORCPT ); Thu, 12 Apr 2007 09:44:02 +0100 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.lysator.liu.se (Postfix) with ESMTP id A814F200A1EA for ; Thu, 12 Apr 2007 10:43:13 +0200 (CEST) Received: from mail.lysator.liu.se ([127.0.0.1]) by localhost (lenin.lysator.liu.se [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 01214-01-16 for ; Thu, 12 Apr 2007 10:43:11 +0200 (CEST) Received: from [192.168.27.65] (6.240.216.81.static.lk.siwnet.net [81.216.240.6]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.lysator.liu.se (Postfix) with ESMTP id B1258200A1E5 for ; Thu, 12 Apr 2007 10:43:11 +0200 (CEST) Message-ID: <461DF11F.404@27m.se> Date: Thu, 12 Apr 2007 10:43:11 +0200 From: Markus Gothe User-Agent: Icedove 1.5.0.10 (X11/20070329) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH] EMMA2RH I2C driver X-Enigmail-Version: 0.94.2.0 Content-Type: multipart/mixed; boundary="------------010904020106040805010500" X-Virus-Scanned: by amavisd-new-20030616-p10 (Debian) at lysator.liu.se Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14831 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markus.gothe@27m.se Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------010904020106040805010500 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 8bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 As Ralf pointed out in march I've been polishing the IIC-driver for EMMA2RH. I've shaped up the I2C-driver to be a platform-device-driver and added accurately memory-mapping/unmapping and irq-request/free. There was a datastructure missing which was pretty straight forward to figure out how to rebuild (i.e. i2c_algo_emma_data). The patch (for the patch) is attached. //Markus - -- _______________________________________ Mr Markus Gothe Software Engineer Phone: +46 (0)13 21 81 20 (ext. 1046) Fax: +46 (0)13 21 21 15 Mobile: +46 (0)73 718 72 80 Diskettgatan 11, SE-583 35 Linköping, Sweden www.27m.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) iD8DBQFGHfEc6I0XmJx2NrwRCMZ8AJ0QgruqOX2y+MxF/+RbpTbSciUsGwCfcH7M efI4rmnlkfxNezQbOWENjRY= =rJPp -----END PGP SIGNATURE----- --------------010904020106040805010500 Content-Type: text/x-patch; name="i2c-emma2rh.patch" Content-Transfer-Encoding: 8bit Content-Disposition: inline; filename="i2c-emma2rh.patch" --- drivers/i2c/algos/i2c-algo-emma2rh.c.orig 2007-03-15 13:32:35.000000000 +0100 +++ drivers/i2c/algos/i2c-algo-emma2rh.c 2007-04-12 10:08:58.000000000 +0200 @@ -14,7 +14,7 @@ Copyright (C) 1995-1997 Simon G. Vogl 1998-2000 Hans Berglund - With some changes from Kyösti Mälkki and + With some changes from Kyösti Mälkki and Frodo Looijaard ,and also from Martin Bailey @@ -51,13 +51,11 @@ #include #include -#include - -#include +#include "i2c-algo-emma2rh.h" #ifdef DEBUG #define i2c_emma2rh_debug(level,op) do { if (i2c_debug>=(level)) { op; } } while (0) -static int i2c_debug; +static int i2c_debug = 9; module_param(i2c_debug, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(i2c_debug, "debug level - 0 off; 1 normal; 2,3 more verbose; 9 i2c-protocol"); @@ -73,13 +71,15 @@ #define EMMA2RH_I2C_RETRIES 3 #define EMMA2RH_I2C_TIMEOUT 100 -/* --- setting states on the bus with the right timing: --------------- */ +/* --- setting states on the bus with the right timing: --------------- +*/ #define set_emma(adap, ctl, val) adap->setemma(adap->data, ctl, val) #define get_emma(adap, ctl) adap->getemma(adap->data, ctl) #define get_own(adap) adap->getown(adap->data) #define get_clock(adap) adap->getclock(adap->data) -/* --- other auxiliary functions -------------------------------------- */ +/* --- other auxiliary functions -------------------------------------- +*/ static void i2c_start(struct i2c_algo_emma_data *adap) { @@ -168,7 +168,8 @@ udelay(adap->udelay); } DEB2(if (i) - printk(KERN_DEBUG "%s: needed %d retries for %d\n", __FUNCTION__, i, addr)) ; + printk(KERN_DEBUG "%s: needed %d retries for %d\n", __FUNCTION__, +i, addr)) ; return ret; } @@ -352,7 +353,7 @@ static u32 emma_func(struct i2c_adapter *adap) { - return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; } /* --- exported algorithm data ---------------------------------------- */ --- drivers/i2c/algos/i2c-algo-emma2rh.h.orig 2007-03-15 13:32:50.000000000 +0100 +++ drivers/i2c/algos/i2c-algo-emma2rh.h 2007-04-12 10:08:18.000000000 +0200 @@ -17,7 +17,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA*/ -/* -------------------------------------------------------------------- */ +/* -------------------------------------------------------------------- +*/ #ifndef I2C_EMMA2RH_H #define I2C_EMMA2RH_H @@ -102,4 +103,19 @@ #define I2C_EMMA_SHR 0x40 #define I2C_EMMA_INT 0x50 #define I2C_EMMA_INTM 0x60 + +struct i2c_algo_emma_data { + void *data; /* private data for lolevel routines */ + void (*setemma) (void *data, int ctl, int val); + int (*getemma) (void *data, int ctl); + int (*getown) (void *data); + int (*getclock) (void *data); + void (*waitforpin) (void *data); + + /* local settings */ + int udelay; + int timeout; + +}; + #endif /* I2C_EMMA2RH_H */ --- drivers/i2c/busses/i2c-emma2rh.c.orig 2007-03-15 13:33:45.000000000 +0100 +++ drivers/i2c/busses/i2c-emma2rh.c 2007-04-12 10:06:48.000000000 +0200 @@ -14,7 +14,7 @@ Copyright (C) 1995-97 Simon G. Vogl 1998-99 Hans Berglund - With some changes from Kyösti Mälkki and even + With some changes from Kyösti Mälkki and even Frodo Looijaard Partialy rewriten by Oleg I. Vdovikin for mmapped support of @@ -47,17 +47,17 @@ #include #include #include -#include #include #include #include #include -#include -#define I2C_EMMA2RH "emma2rh-iic" +#include "../algos/i2c-algo-emma2rh.h" + static int i2c_debug = 0; -/* ----- global defines ----------------------------------------------- */ +/* ----- global defines ----------------------------------------------- +*/ #define DEB(x) if (i2c_debug>=1) x #define DEB2(x) if (i2c_debug>=2) x #define DEB3(x) if (i2c_debug>=3) x @@ -75,7 +75,8 @@ wait_queue_head_t wait; }; -/* ----- local functions ----------------------------------------------*/ +/* ----- local functions ---------------------------------------------- +*/ static void i2c_emma_setbyte(void *data, int ctl, int val) { int address = ((struct i2c_drvdata *)data)->base + ctl; @@ -148,9 +149,8 @@ udelay(100); } -static int __devinit i2c_emma_probe(struct device *dev) +static int __devinit i2c_emma_probe(struct platform_device *pdev) { - struct platform_device *pdev = to_platform_device(dev); struct i2c_drvdata *dd; int err = 0; struct resource *r; @@ -167,81 +167,108 @@ dd->alg.getclock = i2c_emma_getclock; dd->alg.waitforpin = i2c_emma_waitforpin; dd->alg.udelay = 80; - dd->alg.mdelay = 80; dd->alg.timeout = 200; - strcpy(dd->adap.name, dev->bus_id); + strcpy(dd->adap.name, pdev->name); dd->adap.id = 0x00; dd->adap.algo = NULL; dd->adap.algo_data = &dd->alg; dd->adap.client_register = i2c_emma_reg; dd->adap.client_unregister = i2c_emma_unreg; - spin_lock_init(&dd->lock); - - atomic_set(&dd->pending,0); - init_waitqueue_head(&dd->wait); - - dev_set_drvdata(dev, dd); - - r = platform_get_resource(pdev, 0, 0); - /* get resource of type '0' with #0 */ + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);/* get resource of type '0' with #0 */ + if (!r) { printk("Cannot get resource\n"); err = -ENODEV; goto out_free; - } - dd->base = r->start; - + } + + if (!request_mem_region(r->start, r->end - r->start + 1, pdev->name)) { + printk("Memory region busy\n"); + err = -EBUSY; + goto out_mem_region; + } + + dd->base = ioremap_nocache(r->start, r->end - r->start); + if (!dd->base) { + printk("Unable to map registers\n"); + err = -EIO; + goto out_ioremap; + } + dd->irq = platform_get_irq(pdev,0); dd->clock = FAST397; dd->own = 0x40 + pdev->id * 4; - err = request_irq(dd->irq, i2c_emma_handler, 0, dev->bus_id, dd); + err = request_irq(dd->irq, i2c_emma_handler, 0, pdev->name, dd); if (err < 0) goto out_free; + + spin_lock_init(&dd->lock); + atomic_set(&dd->pending,0); + init_waitqueue_head(&dd->wait); + + platform_set_drvdata(pdev, dd); + if ((err = i2c_emma_add_bus(&dd->adap)) < 0) goto out_irq; return 0; + out_irq: - free_irq(dd->irq, dev->bus_id); + free_irq(dd->irq, dd); +out_ioremap: + iounmap(dd->base); +out_mem_region: + release_mem_region(r->start, r->end - r->start + 1); out_free: - kfree(dd); + kfree(dd); out: - return err; + return err; } -static int __devexit i2c_emma_remove (struct device *dev) +static int __devexit i2c_emma_remove (struct platform_device *pdev) { - struct i2c_drvdata* dd = dev_get_drvdata(dev); - - if (dd) { - disable_irq(dd->irq); - free_irq(dd->irq, dev->bus_id); - i2c_emma_del_bus(&dd->adap); - kfree(dd); - } - return 0; -} - -static struct device_driver i2c_emma_driver = { - .bus = &platform_bus_type, - .name = I2C_EMMA2RH, - .probe = i2c_emma_probe, - .remove = i2c_emma_remove, + struct i2c_drvdata* dd = platform_get_drvdata(pdev); + struct resource *r; + + i2c_emma_del_bus(&dd->adap); + platform_set_drvdata(pdev, NULL); + r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if(r) + free_irq(r->start, dd); + + iounmap(dd->base); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if(r) + release_mem_region(r->start, r->end - r->start + 1); + kfree(dd); + + return 0; +} + +static struct platform_driver i2c_emma_driver = { + .probe = i2c_emma_probe, + .remove = __devexit_p(i2c_emma_remove), + .driver = { + .owner = THIS_MODULE, + .bus = &platform_bus_type, + .name = "emma2rh-iic", + } }; static int __init i2c_emma_init(void) { - return driver_register(&i2c_emma_driver); + return platform_driver_register(&i2c_emma_driver); } static void __exit i2c_emma_exit(void) { - driver_unregister(&i2c_emma_driver); + platform_driver_unregister(&i2c_emma_driver); } MODULE_AUTHOR("NEC Electronics Corporation "); --------------010904020106040805010500-- From anemo@mba.ocn.ne.jp Thu Apr 12 12:03:20 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Apr 2007 12:03:21 +0100 (BST) Received: from topsns2.0.225.230.202.in-addr.arpa ([202.230.225.126]:41652 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20022423AbXDLLDU (ORCPT ); Thu, 12 Apr 2007 12:03:20 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Thu, 12 Apr 2007 20:03:18 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 2B67F420D1; Thu, 12 Apr 2007 20:02:55 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 17AF7261FB; Thu, 12 Apr 2007 20:02:55 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id l3CB2sW0059360; Thu, 12 Apr 2007 20:02:54 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Thu, 12 Apr 2007 20:02:54 +0900 (JST) Message-Id: <20070412.200254.128619887.nemoto@toshiba-tops.co.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Fix BUG(), BUG_ON() handling From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14832 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips With commit 63dc68a8cf60cb110b147dab1704d990808b39e2, kernel can not handle BUG() and BUG_ON() properly since get_user() returns false for kernel code. Use __get_user() to skip unnecessary access_ok(). This patch also make BRK_BUG code encoded in the TNE instruction. Signed-off-by: Atsushi Nemoto --- diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 7d76a85..56a770c 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -650,7 +650,7 @@ asmlinkage void do_bp(struct pt_regs *regs) unsigned int opcode, bcode; siginfo_t info; - if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) + if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) goto out_sigsegv; /* @@ -700,7 +700,7 @@ asmlinkage void do_tr(struct pt_regs *regs) unsigned int opcode, tcode = 0; siginfo_t info; - if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) + if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) goto out_sigsegv; /* Immediate versions don't provide a code. */ diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h index 4d560a5..7eb63de 100644 --- a/include/asm-mips/bug.h +++ b/include/asm-mips/bug.h @@ -18,7 +18,8 @@ do { \ #define BUG_ON(condition) \ do { \ - __asm__ __volatile__("tne $0, %0" : : "r" (condition)); \ + __asm__ __volatile__("tne $0, %0, %1" \ + : : "r" (condition), "i" (BRK_BUG)); \ } while (0) #define HAVE_ARCH_BUG_ON From sshtylyov@ru.mvista.com Thu Apr 12 15:49:40 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Apr 2007 15:49:43 +0100 (BST) Received: from rtsoft2.corbina.net ([85.21.88.2]:63934 "HELO mail.dev.rtsoft.ru") by ftp.linux-mips.org with SMTP id S20023158AbXDLOtk (ORCPT ); Thu, 12 Apr 2007 15:49:40 +0100 Received: (qmail 29266 invoked from network); 12 Apr 2007 14:48:19 -0000 Received: from wasted.dev.rtsoft.ru (HELO ?192.168.1.248?) (192.168.1.248) by mail.dev.rtsoft.ru with SMTP; 12 Apr 2007 14:48:19 -0000 Message-ID: <461E46EF.4060004@ru.mvista.com> Date: Thu, 12 Apr 2007 18:49:19 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Markus Gothe CC: linux-mips@linux-mips.org Subject: Re: [PATCH] EMMA2RH I2C driver References: <461DF11F.404@27m.se> In-Reply-To: <461DF11F.404@27m.se> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14833 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Markus Gothe wrote: > As Ralf pointed out in march I've been polishing the IIC-driver for > EMMA2RH. > I've shaped up the I2C-driver to be a platform-device-driver and added > accurately memory-mapping/unmapping and irq-request/free. > There was a datastructure missing which was pretty straight forward to > figure out how to rebuild (i.e. i2c_algo_emma_data). Below are a few comments... > --- drivers/i2c/algos/i2c-algo-emma2rh.c.orig 2007-03-15 13:32:35.000000000 +0100 > +++ drivers/i2c/algos/i2c-algo-emma2rh.c 2007-04-12 10:08:58.000000000 +0200 [...] > @@ -73,13 +71,15 @@ > #define EMMA2RH_I2C_RETRIES 3 > #define EMMA2RH_I2C_TIMEOUT 100 > > -/* --- setting states on the bus with the right timing: --------------- */ > +/* --- setting states on the bus with the right timing: --------------- > +*/ > #define set_emma(adap, ctl, val) adap->setemma(adap->data, ctl, val) > #define get_emma(adap, ctl) adap->getemma(adap->data, ctl) > #define get_own(adap) adap->getown(adap->data) > #define get_clock(adap) adap->getclock(adap->data) > > -/* --- other auxiliary functions -------------------------------------- */ > +/* --- other auxiliary functions -------------------------------------- > +*/ > > static void i2c_start(struct i2c_algo_emma_data *adap) > { > @@ -168,7 +168,8 @@ > udelay(adap->udelay); > } > DEB2(if (i) > - printk(KERN_DEBUG "%s: needed %d retries for %d\n", __FUNCTION__, i, addr)) ; > + printk(KERN_DEBUG "%s: needed %d retries for %d\n", __FUNCTION__, > +i, addr)) ; Please don't "uglify" the code. If you intend to carry it to the new line indent properlu (by starting it under paren). > --- drivers/i2c/algos/i2c-algo-emma2rh.h.orig 2007-03-15 13:32:50.000000000 +0100 > +++ drivers/i2c/algos/i2c-algo-emma2rh.h 2007-04-12 10:08:18.000000000 +0200 > @@ -17,7 +17,8 @@ > You should have received a copy of the GNU General Public License > along with this program; if not, write to the Free Software > Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA*/ > -/* -------------------------------------------------------------------- */ > +/* -------------------------------------------------------------------- > +*/ No need to make the comment more ugly too. > #ifndef I2C_EMMA2RH_H > #define I2C_EMMA2RH_H > @@ -102,4 +103,19 @@ > #define I2C_EMMA_SHR 0x40 > #define I2C_EMMA_INT 0x50 > #define I2C_EMMA_INTM 0x60 > + > +struct i2c_algo_emma_data { > + void *data; /* private data for lolevel routines */ > + void (*setemma) (void *data, int ctl, int val); > + int (*getemma) (void *data, int ctl); > + int (*getown) (void *data); > + int (*getclock) (void *data); > + void (*waitforpin) (void *data); > + > + /* local settings */ > + int udelay; > + int timeout; > + > +}; > + > #endif /* I2C_EMMA2RH_H */ > --- drivers/i2c/busses/i2c-emma2rh.c.orig 2007-03-15 13:33:45.000000000 +0100 > +++ drivers/i2c/busses/i2c-emma2rh.c 2007-04-12 10:06:48.000000000 +0200 > @@ -14,7 +14,7 @@ > Copyright (C) 1995-97 Simon G. Vogl > 1998-99 Hans Berglund > > - With some changes from KyУЖsti MУЄlkki and even > + With some changes from KyÑ–sti MÑ„lkki and even > Frodo Looijaard I'm not sure what that change is. > @@ -167,81 +167,108 @@ > dd->alg.getclock = i2c_emma_getclock; > dd->alg.waitforpin = i2c_emma_waitforpin; > dd->alg.udelay = 80; > - dd->alg.mdelay = 80; > dd->alg.timeout = 200; > > - strcpy(dd->adap.name, dev->bus_id); > + strcpy(dd->adap.name, pdev->name); > dd->adap.id = 0x00; > dd->adap.algo = NULL; > dd->adap.algo_data = &dd->alg; > dd->adap.client_register = i2c_emma_reg; > dd->adap.client_unregister = i2c_emma_unreg; > > - spin_lock_init(&dd->lock); > - > - atomic_set(&dd->pending,0); > - init_waitqueue_head(&dd->wait); > - > - dev_set_drvdata(dev, dd); > - > - r = platform_get_resource(pdev, 0, 0); > - /* get resource of type '0' with #0 */ > > + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);/* get resource of type '0' with #0 */ > + Put at least one space between ; and comment, and no trailing whitespace, please. > if (!r) { > printk("Cannot get resource\n"); > err = -ENODEV; > goto out_free; > - } > - dd->base = r->start; > - > + } > + > + if (!request_mem_region(r->start, r->end - r->start + 1, pdev->name)) { > + printk("Memory region busy\n"); > + err = -EBUSY; > + goto out_mem_region; You've already failed to request region, why then free it? > + } > + > + dd->base = ioremap_nocache(r->start, r->end - r->start); > + if (!dd->base) { > + printk("Unable to map registers\n"); > + err = -EIO; > + goto out_ioremap; You've already failed to ioremap() it, why call iounmap()? > + } > + > dd->irq = platform_get_irq(pdev,0); > dd->clock = FAST397; > dd->own = 0x40 + pdev->id * 4; > > - err = request_irq(dd->irq, i2c_emma_handler, 0, dev->bus_id, dd); > + err = request_irq(dd->irq, i2c_emma_handler, 0, pdev->name, dd); > if (err < 0) > goto out_free; And you've forgetten to call iounmap() and release_mem_region() in this case... > + > + spin_lock_init(&dd->lock); > > + atomic_set(&dd->pending,0); > + init_waitqueue_head(&dd->wait); > + > + platform_set_drvdata(pdev, dd); > + > if ((err = i2c_emma_add_bus(&dd->adap)) < 0) > goto out_irq; > > return 0; > + > out_irq: > - free_irq(dd->irq, dev->bus_id); > + free_irq(dd->irq, dd); > +out_ioremap: > + iounmap(dd->base); > +out_mem_region: > + release_mem_region(r->start, r->end - r->start + 1); > out_free: > - kfree(dd); > + kfree(dd); > out: > - return err; > + return err; > } The cleanup code needs fixing, as you can see... WBR, Sergei From anemo@mba.ocn.ne.jp Fri Apr 13 18:17:07 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Apr 2007 18:17:09 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:47083 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20022007AbXDMRRH (ORCPT ); Fri, 13 Apr 2007 18:17:07 +0100 Received: from localhost (p6152-ipad02funabasi.chiba.ocn.ne.jp [61.214.24.152]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 8C5B4B486; Sat, 14 Apr 2007 02:15:45 +0900 (JST) Date: Sat, 14 Apr 2007 02:15:45 +0900 (JST) Message-Id: <20070414.021545.79071827.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] Allow CpU exception in kernel partially From: Atsushi Nemoto In-Reply-To: <20070310.012811.108982622.anemo@mba.ocn.ne.jp> References: <20070310.012811.108982622.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14834 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sat, 10 Mar 2007 01:28:11 +0900 (JST), Atsushi Nemoto wrote: > The save_fp_context()/restore_fp_context() might sleep on accessing > user stack and therefore might lose FPU ownership in middle of them. > Also we should not disable preempt around these functions. This patch > files this problem by allowing CpU exception in kernel partially. > > * Introduce TIF_ALLOW_FP_IN_KERNEL thread flag. If the flag was set, > CpU exception handler enables CU1 bit in interrupted kernel context > and returns without enabling interrupt (preempt) to make sure keep > FPU ownership until resume. > * Introduce enable_fp_in_kernel() and disable_fp_in_kernel(). While > we might lost FPU ownership in middle of CP0_STATUS manipulation > (for example local_irq_disable()), we can not assume CU1 bit always > reflects TIF_USEDFPU. Therefore enable_fp_in_kernel() must drop CU1 > bit if TIF_USEDFPU was cleared. > * The resume() function must drop CU1 bit in CP0_STATUS which are to > be saved. Unfortunately this is broken. > +static inline void disable_fp_in_kernel(void) > +{ > + BUG_ON(!__is_fpu_owner() && __fpu_enabled()); > + clear_thread_flag(TIF_ALLOW_FP_IN_KERNEL); > +} This BUG_ON hits me sometimes when I run debian installer. I tracked down the problem and understand why. If kernel preempted in middle of save_fp_context() and resumed, the CU1 bit will be enabled without TIF_USEDFPU flag. 1. Task A calls a system call. CP0_STATUS is saved on top of kernel stack. 2. setup_sigcontext() is called. 3. Task A own FPU. CP0_STATUS.CU1 in top of kernel stack is set. 4. save_fp_context() is called. 5. A timer interrupt happens. CP0_STATUS is saved on next kernel stack. 6. Task A is preempted by Task B. Both CP0_STATUS.CU1 in top of kernel stack and CP0_STATUS.CU1 in task_struct are both cleared. 7. Task A is resumed. On returning from resume(), CP0_STATUS.CU1 is 0. 8. On returning to save_fp_context(), RESUME_SOME() restores CP0_STATUS saved at (5). The CU1 bit in this value is 1. 9. Now CU1 is enabled without TIF_USEDFPU. This problem might be fixed by dropping CU1 on RESUME_SOME() if TIF_USEDFPU was cleared. But this adds some codes to critical path. So I'd like to revert this patch. I will send some patches in a few days: * a patch to revert this patch * updated "first way" patch (rewrites restore_fp_context/save_fp_context) * "third way" patch The "third way" I'm thinking of is something like this: static int protected_save_fp_context(struct sigcontext __user *sc) { int err; while (1) { preempt_disable(); own_fpu(1); err = save_fp_context(sc); /* this might fail */ preempt_enable(); if (likely(!err)) break; /* touch the sigcontext and try again */ err = __put_user(0, &sc->sc_fpregs[0]) | __put_user(0, &sc->sc_fpregs[31]) | __put_user(0, &sc->sc_fpc_csr); if (err) break; /* really bad sigcontext */ } return err; } The save_fp_context intentionally is called in atomic context, and if it failed, touch the sigcontext in nonatomic context (this might lose FPU ownership), and try again. I'll try some tests with this and send a patch if it worked fine. --- Atsushi Nemoto From anemo@mba.ocn.ne.jp Fri Apr 13 18:23:05 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Apr 2007 18:23:10 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:14059 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20022002AbXDMRXE (ORCPT ); Fri, 13 Apr 2007 18:23:04 +0100 Received: from localhost (p6152-ipad02funabasi.chiba.ocn.ne.jp [61.214.24.152]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 30B81B845; Sat, 14 Apr 2007 02:21:43 +0900 (JST) Date: Sat, 14 Apr 2007 02:21:43 +0900 (JST) Message-Id: <20070414.022143.82357892.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Disallow CpU exception in kernel again. From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14835 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips The commit 4d40bff7110e9e1a97ff8c01bdd6350e9867cc10 ("Allow CpU exception in kernel partially") was broken. The commit was to fix theoretical problem but broke usual case. Revert it for now. Signed-off-by: Atsushi Nemoto --- arch/mips/kernel/r2300_switch.S | 10 ++++------ arch/mips/kernel/r4k_switch.S | 10 ++++------ arch/mips/kernel/signal.c | 10 +++++----- arch/mips/kernel/signal32.c | 10 +++++----- arch/mips/kernel/traps.c | 21 +++------------------ include/asm-mips/fpu.h | 16 ---------------- include/asm-mips/thread_info.h | 1 - 7 files changed, 21 insertions(+), 57 deletions(-) diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 28c2e2e..656bde2 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S @@ -49,7 +49,8 @@ LEAF(resume) #ifndef CONFIG_CPU_HAS_LLSC sw zero, ll_bit #endif - mfc0 t2, CP0_STATUS + mfc0 t1, CP0_STATUS + sw t1, THREAD_STATUS(a0) cpu_save_nonscratch a0 sw ra, THREAD_REG31(a0) @@ -59,8 +60,8 @@ LEAF(resume) lw t3, TASK_THREAD_INFO(a0) lw t0, TI_FLAGS(t3) li t1, _TIF_USEDFPU - and t1, t0 - beqz t1, 1f + and t2, t0, t1 + beqz t2, 1f nor t1, zero, t1 and t0, t0, t1 @@ -73,13 +74,10 @@ LEAF(resume) li t1, ~ST0_CU1 and t0, t0, t1 sw t0, ST_OFF(t3) - /* clear thread_struct CU1 bit */ - and t2, t1 fpu_save_single a0, t0 # clobbers t0 1: - sw t2, THREAD_STATUS(a0) /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index c7698fd..cc566cf 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -48,7 +48,8 @@ #ifndef CONFIG_CPU_HAS_LLSC sw zero, ll_bit #endif - mfc0 t2, CP0_STATUS + mfc0 t1, CP0_STATUS + LONG_S t1, THREAD_STATUS(a0) cpu_save_nonscratch a0 LONG_S ra, THREAD_REG31(a0) @@ -58,8 +59,8 @@ PTR_L t3, TASK_THREAD_INFO(a0) LONG_L t0, TI_FLAGS(t3) li t1, _TIF_USEDFPU - and t1, t0 - beqz t1, 1f + and t2, t0, t1 + beqz t2, 1f nor t1, zero, t1 and t0, t0, t1 @@ -72,13 +73,10 @@ li t1, ~ST0_CU1 and t0, t0, t1 LONG_S t0, ST_OFF(t3) - /* clear thread_struct CU1 bit */ - and t2, t1 fpu_save_double a0 t0 t1 # c0_status passed in t0 # clobbers t1 1: - LONG_S t2, THREAD_STATUS(a0) /* * The order of restoring the registers takes care of the race diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 8c3c5a5..fa58119 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -113,10 +113,10 @@ int setup_sigcontext(struct pt_regs *reg * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ + preempt_disable(); own_fpu(1); - enable_fp_in_kernel(); err |= save_fp_context(sc); - disable_fp_in_kernel(); + preempt_enable(); } return err; } @@ -148,7 +148,10 @@ check_and_restore_fp_context(struct sigc err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; + preempt_disable(); + own_fpu(0); err |= restore_fp_context(sc); + preempt_enable(); return err ?: sig; } @@ -187,11 +190,8 @@ int restore_sigcontext(struct pt_regs *r if (used_math) { /* restore fpu context if we have used it before */ - own_fpu(0); - enable_fp_in_kernel(); if (!err) err = check_and_restore_fp_context(sc); - disable_fp_in_kernel(); } else { /* signal handler may have used FPU. Give it up. */ lose_fpu(0); diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 151fd2f..2cfdd78 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -209,10 +209,10 @@ static int setup_sigcontext32(struct pt_ * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ + preempt_disable(); own_fpu(1); - enable_fp_in_kernel(); err |= save_fp_context32(sc); - disable_fp_in_kernel(); + preempt_enable(); } return err; } @@ -225,6 +225,9 @@ check_and_restore_fp_context32(struct si err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; + preempt_disable(); + own_fpu(0); + preempt_enable(); err |= restore_fp_context32(sc); return err ?: sig; } @@ -261,11 +264,8 @@ static int restore_sigcontext32(struct p if (used_math) { /* restore fpu context if we have used it before */ - own_fpu(0); - enable_fp_in_kernel(); if (!err) err = check_and_restore_fp_context32(sc); - disable_fp_in_kernel(); } else { /* signal handler may have used FPU. Give it up. */ lose_fpu(0); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 56a770c..493cb29 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -757,11 +757,12 @@ asmlinkage void do_cpu(struct pt_regs *r { unsigned int cpid; + die_if_kernel("do_cpu invoked from kernel context!", regs); + cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; switch (cpid) { case 0: - die_if_kernel("do_cpu invoked from kernel context!", regs); if (!cpu_has_llsc) if (!simulate_llsc(regs)) return; @@ -772,9 +773,6 @@ asmlinkage void do_cpu(struct pt_regs *r break; case 1: - if (!test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) - die_if_kernel("do_cpu invoked from kernel context!", - regs); if (used_math()) /* Using the FPU again. */ own_fpu(1); else { /* First time FPU user. */ @@ -782,19 +780,7 @@ asmlinkage void do_cpu(struct pt_regs *r set_used_math(); } - if (raw_cpu_has_fpu) { - if (test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) { - local_irq_disable(); - if (cpu_has_fpu) - regs->cp0_status |= ST0_CU1; - /* - * We must return without enabling - * interrupts to ensure keep FPU - * ownership until resume. - */ - return; - } - } else { + if (!raw_cpu_has_fpu) { int sig; sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0); @@ -836,7 +822,6 @@ asmlinkage void do_cpu(struct pt_regs *r case 2: case 3: - die_if_kernel("do_cpu invoked from kernel context!", regs); break; } diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 4e12d1f..71436f9 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -68,8 +68,6 @@ do { \ /* We don't care about the c0 hazard here */ \ } while (0) -#define __fpu_enabled() (read_c0_status() & ST0_CU1) - #define enable_fpu() \ do { \ if (cpu_has_fpu) \ @@ -162,18 +160,4 @@ static inline fpureg_t *get_fpu_regs(str return tsk->thread.fpu.fpr; } -static inline void enable_fp_in_kernel(void) -{ - set_thread_flag(TIF_ALLOW_FP_IN_KERNEL); - /* make sure CU1 and FPU ownership are consistent */ - if (!__is_fpu_owner() && __fpu_enabled()) - __disable_fpu(); -} - -static inline void disable_fp_in_kernel(void) -{ - BUG_ON(!__is_fpu_owner() && __fpu_enabled()); - clear_thread_flag(TIF_ALLOW_FP_IN_KERNEL); -} - #endif /* _ASM_FPU_H */ diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index 6cf05f4..fbcda82 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -119,7 +119,6 @@ register struct thread_info *__current_t #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 #define TIF_FREEZE 19 -#define TIF_ALLOW_FP_IN_KERNEL 20 #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ #define _TIF_SYSCALL_TRACE (1<); Fri, 13 Apr 2007 18:33:04 +0100 Received: by hawaii.site (Postfix, from userid 500) id E32245484C9; Fri, 13 Apr 2007 10:32:25 -0700 (PDT) Date: Fri, 13 Apr 2007 10:32:25 -0700 From: Mark Mason To: linux-mips@linux-mips.org Subject: [PATCH] Add missing silicon revisions for BCM112x Message-ID: <20070413173225.GA4207@upwardaccess.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14836 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mmason@upwardaccess.com Precedence: bulk X-list: linux-mips Recent versions of the BCM112X processors aren't recognized by Linux (preventing Linux from booting on those processors). This patch adds support for those that are missing. Signed-off-by: Mark Mason --- arch/mips/sibyte/sb1250/setup.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index 87188f0..f4a6169 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c @@ -141,6 +141,18 @@ static int __init setup_bcm112x(void) periph_rev = 3; pass_str = "A2"; break; + case K_SYS_REVISION_BCM112x_A3: + periph_rev = 3; + pass_str = "A3"; + break; + case K_SYS_REVISION_BCM112x_A4: + periph_rev = 3; + pass_str = "A4"; + break; + case K_SYS_REVISION_BCM112x_B0: + periph_rev = 3; + pass_str = "B0"; + break; default: printk("Unknown %s rev %x\n", soc_str, soc_pass); ret = 1; -- 1.1.6.g9c88 From anemo@mba.ocn.ne.jp Fri Apr 13 18:38:47 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Apr 2007 18:38:49 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:9676 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20021982AbXDMRir (ORCPT ); Fri, 13 Apr 2007 18:38:47 +0100 Received: from localhost (p6152-ipad02funabasi.chiba.ocn.ne.jp [61.214.24.152]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id B1BEFB831; Sat, 14 Apr 2007 02:37:26 +0900 (JST) Date: Sat, 14 Apr 2007 02:37:26 +0900 (JST) Message-Id: <20070414.023726.128617751.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] Disallow CpU exception in kernel again. From: Atsushi Nemoto In-Reply-To: <20070414.022143.82357892.anemo@mba.ocn.ne.jp> References: <20070414.022143.82357892.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14837 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sat, 14 Apr 2007 02:21:43 +0900 (JST), Atsushi Nemoto wrote: > The commit 4d40bff7110e9e1a97ff8c01bdd6350e9867cc10 ("Allow CpU > exception in kernel partially") was broken. The commit was to fix > theoretical problem but broke usual case. Revert it for now. ... > @@ -225,6 +225,9 @@ check_and_restore_fp_context32(struct si > err = sig = fpcsr_pending(&sc->sc_fpc_csr); > if (err > 0) > err = 0; > + preempt_disable(); > + own_fpu(0); > + preempt_enable(); > err |= restore_fp_context32(sc); > return err ?: sig; > } Ooops this is broken. Revised. Subject: [PATCH] Disallow CpU exception in kernel again. The commit 4d40bff7110e9e1a97ff8c01bdd6350e9867cc10 ("Allow CpU exception in kernel partially") was broken. The commit was to fix theoretical problem but broke usual case. Revert it for now. Signed-off-by: Atsushi Nemoto --- arch/mips/kernel/r2300_switch.S | 10 ++++------ arch/mips/kernel/r4k_switch.S | 10 ++++------ arch/mips/kernel/signal.c | 10 +++++----- arch/mips/kernel/signal32.c | 10 +++++----- arch/mips/kernel/traps.c | 21 +++------------------ include/asm-mips/fpu.h | 16 ---------------- include/asm-mips/thread_info.h | 1 - 7 files changed, 21 insertions(+), 57 deletions(-) diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 28c2e2e..656bde2 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S @@ -49,7 +49,8 @@ LEAF(resume) #ifndef CONFIG_CPU_HAS_LLSC sw zero, ll_bit #endif - mfc0 t2, CP0_STATUS + mfc0 t1, CP0_STATUS + sw t1, THREAD_STATUS(a0) cpu_save_nonscratch a0 sw ra, THREAD_REG31(a0) @@ -59,8 +60,8 @@ LEAF(resume) lw t3, TASK_THREAD_INFO(a0) lw t0, TI_FLAGS(t3) li t1, _TIF_USEDFPU - and t1, t0 - beqz t1, 1f + and t2, t0, t1 + beqz t2, 1f nor t1, zero, t1 and t0, t0, t1 @@ -73,13 +74,10 @@ LEAF(resume) li t1, ~ST0_CU1 and t0, t0, t1 sw t0, ST_OFF(t3) - /* clear thread_struct CU1 bit */ - and t2, t1 fpu_save_single a0, t0 # clobbers t0 1: - sw t2, THREAD_STATUS(a0) /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index c7698fd..cc566cf 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -48,7 +48,8 @@ #ifndef CONFIG_CPU_HAS_LLSC sw zero, ll_bit #endif - mfc0 t2, CP0_STATUS + mfc0 t1, CP0_STATUS + LONG_S t1, THREAD_STATUS(a0) cpu_save_nonscratch a0 LONG_S ra, THREAD_REG31(a0) @@ -58,8 +59,8 @@ PTR_L t3, TASK_THREAD_INFO(a0) LONG_L t0, TI_FLAGS(t3) li t1, _TIF_USEDFPU - and t1, t0 - beqz t1, 1f + and t2, t0, t1 + beqz t2, 1f nor t1, zero, t1 and t0, t0, t1 @@ -72,13 +73,10 @@ li t1, ~ST0_CU1 and t0, t0, t1 LONG_S t0, ST_OFF(t3) - /* clear thread_struct CU1 bit */ - and t2, t1 fpu_save_double a0 t0 t1 # c0_status passed in t0 # clobbers t1 1: - LONG_S t2, THREAD_STATUS(a0) /* * The order of restoring the registers takes care of the race diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 8c3c5a5..fa58119 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -113,10 +113,10 @@ int setup_sigcontext(struct pt_regs *reg * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ + preempt_disable(); own_fpu(1); - enable_fp_in_kernel(); err |= save_fp_context(sc); - disable_fp_in_kernel(); + preempt_enable(); } return err; } @@ -148,7 +148,10 @@ check_and_restore_fp_context(struct sigc err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; + preempt_disable(); + own_fpu(0); err |= restore_fp_context(sc); + preempt_enable(); return err ?: sig; } @@ -187,11 +190,8 @@ int restore_sigcontext(struct pt_regs *r if (used_math) { /* restore fpu context if we have used it before */ - own_fpu(0); - enable_fp_in_kernel(); if (!err) err = check_and_restore_fp_context(sc); - disable_fp_in_kernel(); } else { /* signal handler may have used FPU. Give it up. */ lose_fpu(0); diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 151fd2f..53a337c 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -209,10 +209,10 @@ static int setup_sigcontext32(struct pt_ * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ + preempt_disable(); own_fpu(1); - enable_fp_in_kernel(); err |= save_fp_context32(sc); - disable_fp_in_kernel(); + preempt_enable(); } return err; } @@ -225,7 +225,10 @@ check_and_restore_fp_context32(struct si err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; + preempt_disable(); + own_fpu(0); err |= restore_fp_context32(sc); + preempt_enable(); return err ?: sig; } @@ -261,11 +264,8 @@ static int restore_sigcontext32(struct p if (used_math) { /* restore fpu context if we have used it before */ - own_fpu(0); - enable_fp_in_kernel(); if (!err) err = check_and_restore_fp_context32(sc); - disable_fp_in_kernel(); } else { /* signal handler may have used FPU. Give it up. */ lose_fpu(0); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 56a770c..493cb29 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -757,11 +757,12 @@ asmlinkage void do_cpu(struct pt_regs *r { unsigned int cpid; + die_if_kernel("do_cpu invoked from kernel context!", regs); + cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; switch (cpid) { case 0: - die_if_kernel("do_cpu invoked from kernel context!", regs); if (!cpu_has_llsc) if (!simulate_llsc(regs)) return; @@ -772,9 +773,6 @@ asmlinkage void do_cpu(struct pt_regs *r break; case 1: - if (!test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) - die_if_kernel("do_cpu invoked from kernel context!", - regs); if (used_math()) /* Using the FPU again. */ own_fpu(1); else { /* First time FPU user. */ @@ -782,19 +780,7 @@ asmlinkage void do_cpu(struct pt_regs *r set_used_math(); } - if (raw_cpu_has_fpu) { - if (test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) { - local_irq_disable(); - if (cpu_has_fpu) - regs->cp0_status |= ST0_CU1; - /* - * We must return without enabling - * interrupts to ensure keep FPU - * ownership until resume. - */ - return; - } - } else { + if (!raw_cpu_has_fpu) { int sig; sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0); @@ -836,7 +822,6 @@ asmlinkage void do_cpu(struct pt_regs *r case 2: case 3: - die_if_kernel("do_cpu invoked from kernel context!", regs); break; } diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 4e12d1f..71436f9 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -68,8 +68,6 @@ do { \ /* We don't care about the c0 hazard here */ \ } while (0) -#define __fpu_enabled() (read_c0_status() & ST0_CU1) - #define enable_fpu() \ do { \ if (cpu_has_fpu) \ @@ -162,18 +160,4 @@ static inline fpureg_t *get_fpu_regs(str return tsk->thread.fpu.fpr; } -static inline void enable_fp_in_kernel(void) -{ - set_thread_flag(TIF_ALLOW_FP_IN_KERNEL); - /* make sure CU1 and FPU ownership are consistent */ - if (!__is_fpu_owner() && __fpu_enabled()) - __disable_fpu(); -} - -static inline void disable_fp_in_kernel(void) -{ - BUG_ON(!__is_fpu_owner() && __fpu_enabled()); - clear_thread_flag(TIF_ALLOW_FP_IN_KERNEL); -} - #endif /* _ASM_FPU_H */ diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index 6cf05f4..fbcda82 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -119,7 +119,6 @@ register struct thread_info *__current_t #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 #define TIF_FREEZE 19 -#define TIF_ALLOW_FP_IN_KERNEL 20 #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ #define _TIF_SYSCALL_TRACE (1<); Fri, 13 Apr 2007 18:46:10 +0100 Received: from localhost (p6152-ipad02funabasi.chiba.ocn.ne.jp [61.214.24.152]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 62C33B80B; Sat, 14 Apr 2007 02:44:50 +0900 (JST) Date: Sat, 14 Apr 2007 02:44:50 +0900 (JST) Message-Id: <20070414.024450.07456615.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] Disallow CpU exception in kernel again. From: Atsushi Nemoto In-Reply-To: <20070414.023726.128617751.anemo@mba.ocn.ne.jp> References: <20070414.022143.82357892.anemo@mba.ocn.ne.jp> <20070414.023726.128617751.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14838 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sat, 14 Apr 2007 02:37:26 +0900 (JST), Atsushi Nemoto wrote: > Subject: [PATCH] Disallow CpU exception in kernel again. > > The commit 4d40bff7110e9e1a97ff8c01bdd6350e9867cc10 ("Allow CpU > exception in kernel partially") was broken. The commit was to fix > theoretical problem but broke usual case. Revert it for now. > > Signed-off-by: Atsushi Nemoto And this is for 2.6.20-stable. Signed-off-by: Atsushi Nemoto --- arch/mips/kernel/r2300_switch.S | 10 ++++------ arch/mips/kernel/r4k_switch.S | 10 ++++------ arch/mips/kernel/signal-common.h | 10 +++++----- arch/mips/kernel/signal32.c | 10 +++++----- arch/mips/kernel/traps.c | 21 +++------------------ include/asm-mips/fpu.h | 16 ---------------- include/asm-mips/thread_info.h | 1 - 7 files changed, 21 insertions(+), 57 deletions(-) diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 28c2e2e..656bde2 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S @@ -49,7 +49,8 @@ LEAF(resume) #ifndef CONFIG_CPU_HAS_LLSC sw zero, ll_bit #endif - mfc0 t2, CP0_STATUS + mfc0 t1, CP0_STATUS + sw t1, THREAD_STATUS(a0) cpu_save_nonscratch a0 sw ra, THREAD_REG31(a0) @@ -59,8 +60,8 @@ LEAF(resume) lw t3, TASK_THREAD_INFO(a0) lw t0, TI_FLAGS(t3) li t1, _TIF_USEDFPU - and t1, t0 - beqz t1, 1f + and t2, t0, t1 + beqz t2, 1f nor t1, zero, t1 and t0, t0, t1 @@ -73,13 +74,10 @@ LEAF(resume) li t1, ~ST0_CU1 and t0, t0, t1 sw t0, ST_OFF(t3) - /* clear thread_struct CU1 bit */ - and t2, t1 fpu_save_single a0, t0 # clobbers t0 1: - sw t2, THREAD_STATUS(a0) /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index c7698fd..cc566cf 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -48,7 +48,8 @@ #ifndef CONFIG_CPU_HAS_LLSC sw zero, ll_bit #endif - mfc0 t2, CP0_STATUS + mfc0 t1, CP0_STATUS + LONG_S t1, THREAD_STATUS(a0) cpu_save_nonscratch a0 LONG_S ra, THREAD_REG31(a0) @@ -58,8 +59,8 @@ PTR_L t3, TASK_THREAD_INFO(a0) LONG_L t0, TI_FLAGS(t3) li t1, _TIF_USEDFPU - and t1, t0 - beqz t1, 1f + and t2, t0, t1 + beqz t2, 1f nor t1, zero, t1 and t0, t0, t1 @@ -72,13 +73,10 @@ li t1, ~ST0_CU1 and t0, t0, t1 LONG_S t0, ST_OFF(t3) - /* clear thread_struct CU1 bit */ - and t2, t1 fpu_save_double a0 t0 t1 # c0_status passed in t0 # clobbers t1 1: - LONG_S t2, THREAD_STATUS(a0) /* * The order of restoring the registers takes care of the race diff --git a/arch/mips/kernel/signal-common.h b/arch/mips/kernel/signal-common.h index 87d8320..b625e9c 100644 --- a/arch/mips/kernel/signal-common.h +++ b/arch/mips/kernel/signal-common.h @@ -51,10 +51,10 @@ setup_sigcontext(struct pt_regs *regs, s * Save FPU state to signal context. Signal handler will "inherit" * current FPU state. */ + preempt_disable(); own_fpu(1); - enable_fp_in_kernel(); err |= save_fp_context(sc); - disable_fp_in_kernel(); + preempt_enable(); out: return err; @@ -71,7 +71,10 @@ check_and_restore_fp_context(struct sigc err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; + preempt_disable(); + own_fpu(0); err |= restore_fp_context(sc); + preempt_enable(); return err ?: sig; } @@ -119,11 +122,8 @@ restore_sigcontext(struct pt_regs *regs, if (used_math()) { /* restore fpu context if we have used it before */ - own_fpu(0); - enable_fp_in_kernel(); if (!err) err = check_and_restore_fp_context(sc); - disable_fp_in_kernel(); } else { /* signal handler may have used FPU. Give it up. */ lose_fpu(0); diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 4a32f99..1a3f541 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -145,7 +145,10 @@ check_and_restore_fp_context32(struct si err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; + preempt_disable(); + own_fpu(0); err |= restore_fp_context32(sc); + preempt_enable(); return err ?: sig; } @@ -379,11 +382,8 @@ static int restore_sigcontext32(struct p if (used_math()) { /* restore fpu context if we have used it before */ - own_fpu(0); - enable_fp_in_kernel(); if (!err) err = check_and_restore_fp_context32(sc); - disable_fp_in_kernel(); } else { /* signal handler may have used FPU. Give it up. */ lose_fpu(0); @@ -614,10 +614,10 @@ static inline int setup_sigcontext32(str * Save FPU state to signal context. Signal handler will "inherit" * current FPU state. */ + preempt_disable(); own_fpu(1); - enable_fp_in_kernel(); err |= save_fp_context32(sc); - disable_fp_in_kernel(); + preempt_enable(); out: return err; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index afb09e8..64b9dfb 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -758,11 +758,12 @@ asmlinkage void do_cpu(struct pt_regs *r { unsigned int cpid; + die_if_kernel("do_cpu invoked from kernel context!", regs); + cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; switch (cpid) { case 0: - die_if_kernel("do_cpu invoked from kernel context!", regs); if (!cpu_has_llsc) if (!simulate_llsc(regs)) return; @@ -773,9 +774,6 @@ asmlinkage void do_cpu(struct pt_regs *r break; case 1: - if (!test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) - die_if_kernel("do_cpu invoked from kernel context!", - regs); if (used_math()) /* Using the FPU again. */ own_fpu(1); else { /* First time FPU user. */ @@ -783,19 +781,7 @@ asmlinkage void do_cpu(struct pt_regs *r set_used_math(); } - if (raw_cpu_has_fpu) { - if (test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) { - local_irq_disable(); - if (cpu_has_fpu) - regs->cp0_status |= ST0_CU1; - /* - * We must return without enabling - * interrupts to ensure keep FPU - * ownership until resume. - */ - return; - } - } else { + if (!raw_cpu_has_fpu) { int sig; sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0); @@ -837,7 +823,6 @@ asmlinkage void do_cpu(struct pt_regs *r case 2: case 3: - die_if_kernel("do_cpu invoked from kernel context!", regs); break; } diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index dfecb7b..6b9d1bf 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -68,8 +68,6 @@ do { \ /* We don't care about the c0 hazard here */ \ } while (0) -#define __fpu_enabled() (read_c0_status() & ST0_CU1) - #define enable_fpu() \ do { \ if (cpu_has_fpu) \ @@ -162,18 +160,4 @@ static inline fpureg_t *get_fpu_regs(str return tsk->thread.fpu.fpr; } -static inline void enable_fp_in_kernel(void) -{ - set_thread_flag(TIF_ALLOW_FP_IN_KERNEL); - /* make sure CU1 and FPU ownership are consistent */ - if (!__is_fpu_owner() && __fpu_enabled()) - __disable_fpu(); -} - -static inline void disable_fp_in_kernel(void) -{ - BUG_ON(!__is_fpu_owner() && __fpu_enabled()); - clear_thread_flag(TIF_ALLOW_FP_IN_KERNEL); -} - #endif /* _ASM_FPU_H */ diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index 6cf05f4..fbcda82 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -119,7 +119,6 @@ register struct thread_info *__current_t #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 #define TIF_FREEZE 19 -#define TIF_ALLOW_FP_IN_KERNEL 20 #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ #define _TIF_SYSCALL_TRACE (1<); Sat, 14 Apr 2007 16:36:05 +0100 Received: from localhost (p8112-ipad211funabasi.chiba.ocn.ne.jp [58.91.164.112]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id C89E2ACB3; Sun, 15 Apr 2007 00:34:42 +0900 (JST) Date: Sun, 15 Apr 2007 00:34:42 +0900 (JST) Message-Id: <20070415.003442.41196965.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] rewrite restore_fp_context/save_fp_context (back again) From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14839 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips The setup_sigcontect()/restore_sigcontext() might sleep on put_user()/get_user() with preemption disabled (i.e. atomic context). Sleeping in atomic context is not allowed. This patch fixes this problem by rewriting restore_fp_context()/save_fp_context(). A path to save fp context was: (current.thread.fpu -> ) real FPU -> sigcontext on userstack And with this patch it is: (real FPU -> ) current.thread.fpu -> sigcontext on userstack While transfer between real FPU and current.thread.fpu can be done by usual context save/restore routines, all arch/mips/kernel/*_fpu.S, SMP-variant of {save,restore}_fp_context and SC_ symbols in asm-offset.h can be removed. There was an another approach: enabling CpU exception in kernel. That was once applied (then this "rewrite" patch was dropped) but now I see that was actually broken. So this patch is back again now. This patch is simpler and would not add additional overhead for most cases. There might be an yet another approach ("the third way"): call save_fp_context in atomic context, and if it failed, touch the sigcontext in nonatomic context (this might lose FPU ownership), and try again. This patch will be comming soon. Signed-off-by: Atsushi Nemoto --- This is an update of: http://www.linux-mips.org/archives/linux-mips/2007-03/msg00112.html This patch depends on: > Subject: Re: [PATCH] Disallow CpU exception in kernel again. > Message-Id: <20070414.023726.128617751.anemo@mba.ocn.ne.jp> arch/mips/kernel/Makefile | 36 ++++---- arch/mips/kernel/asm-offsets.c | 47 --------- arch/mips/kernel/r2300_fpu.S | 126 ----------------------- arch/mips/kernel/r4k_fpu.S | 188 ----------------------------------- arch/mips/kernel/r6000_fpu.S | 87 ---------------- arch/mips/kernel/signal.c | 46 +++++++-- arch/mips/kernel/signal32.c | 38 ++++++-- arch/mips/kernel/traps.c | 76 -------------- arch/mips/math-emu/kernel_linkage.c | 73 -------------- include/asm-mips/fpu.h | 9 -- 10 files changed, 84 insertions(+), 642 deletions(-) diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 4924626..8377760 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -14,24 +14,24 @@ binfmt_irix-objs := irixelf.o irixinv.o obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += mips_ksyms.o module.o -obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o -obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o -obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R4000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R3000) += r2300_switch.o +obj-$(CONFIG_CPU_TX39XX) += r2300_switch.o +obj-$(CONFIG_CPU_TX49XX) += r4k_switch.o +obj-$(CONFIG_CPU_R4000) += r4k_switch.o +obj-$(CONFIG_CPU_VR41XX) += r4k_switch.o +obj-$(CONFIG_CPU_R4300) += r4k_switch.o +obj-$(CONFIG_CPU_R4X00) += r4k_switch.o +obj-$(CONFIG_CPU_R5000) += r4k_switch.o +obj-$(CONFIG_CPU_R5432) += r4k_switch.o +obj-$(CONFIG_CPU_R8000) += r4k_switch.o +obj-$(CONFIG_CPU_RM7000) += r4k_switch.o +obj-$(CONFIG_CPU_RM9000) += r4k_switch.o +obj-$(CONFIG_CPU_NEVADA) += r4k_switch.o +obj-$(CONFIG_CPU_R10000) += r4k_switch.o +obj-$(CONFIG_CPU_SB1) += r4k_switch.o +obj-$(CONFIG_CPU_MIPS32) += r4k_switch.o +obj-$(CONFIG_CPU_MIPS64) += r4k_switch.o +obj-$(CONFIG_CPU_R6000) += r4k_switch.o obj-$(CONFIG_SMP) += smp.o diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 222de46..e312ed8 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -243,53 +243,6 @@ void output_mm_defines(void) linefeed; } -#ifdef CONFIG_32BIT -void output_sc_defines(void) -{ - text("/* Linux sigcontext offsets. */"); - offset("#define SC_REGS ", struct sigcontext, sc_regs); - offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs); - offset("#define SC_ACX ", struct sigcontext, sc_acx); - offset("#define SC_MDHI ", struct sigcontext, sc_mdhi); - offset("#define SC_MDLO ", struct sigcontext, sc_mdlo); - offset("#define SC_PC ", struct sigcontext, sc_pc); - offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); - offset("#define SC_FPC_EIR ", struct sigcontext, sc_fpc_eir); - offset("#define SC_HI1 ", struct sigcontext, sc_hi1); - offset("#define SC_LO1 ", struct sigcontext, sc_lo1); - offset("#define SC_HI2 ", struct sigcontext, sc_hi2); - offset("#define SC_LO2 ", struct sigcontext, sc_lo2); - offset("#define SC_HI3 ", struct sigcontext, sc_hi3); - offset("#define SC_LO3 ", struct sigcontext, sc_lo3); - linefeed; -} -#endif - -#ifdef CONFIG_64BIT -void output_sc_defines(void) -{ - text("/* Linux sigcontext offsets. */"); - offset("#define SC_REGS ", struct sigcontext, sc_regs); - offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs); - offset("#define SC_MDHI ", struct sigcontext, sc_mdhi); - offset("#define SC_MDLO ", struct sigcontext, sc_mdlo); - offset("#define SC_PC ", struct sigcontext, sc_pc); - offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); - linefeed; -} -#endif - -#ifdef CONFIG_MIPS32_COMPAT -void output_sc32_defines(void) -{ - text("/* Linux 32-bit sigcontext offsets. */"); - offset("#define SC32_FPREGS ", struct sigcontext32, sc_fpregs); - offset("#define SC32_FPC_CSR ", struct sigcontext32, sc_fpc_csr); - offset("#define SC32_FPC_EIR ", struct sigcontext32, sc_fpc_eir); - linefeed; -} -#endif - void output_signal_defined(void) { text("/* Linux signal numbers. */"); diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S deleted file mode 100644 index ac68e68..0000000 --- a/arch/mips/kernel/r2300_fpu.S +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1998 by Ralf Baechle - * - * Multi-arch abstraction and asm macros for easier reading: - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * - * Further modifications to make this work: - * Copyright (c) 1998 Harald Koerfgen - */ -#include -#include -#include -#include -#include -#include - -#define EX(a,b) \ -9: a,##b; \ - .section __ex_table,"a"; \ - PTR 9b,bad_stack; \ - .previous - - .set noreorder - .set mips1 - /* Save floating point context */ -LEAF(_save_fp_context) - li v0, 0 # assume success - cfc1 t1,fcr31 - EX(swc1 $f0,(SC_FPREGS+0)(a0)) - EX(swc1 $f1,(SC_FPREGS+8)(a0)) - EX(swc1 $f2,(SC_FPREGS+16)(a0)) - EX(swc1 $f3,(SC_FPREGS+24)(a0)) - EX(swc1 $f4,(SC_FPREGS+32)(a0)) - EX(swc1 $f5,(SC_FPREGS+40)(a0)) - EX(swc1 $f6,(SC_FPREGS+48)(a0)) - EX(swc1 $f7,(SC_FPREGS+56)(a0)) - EX(swc1 $f8,(SC_FPREGS+64)(a0)) - EX(swc1 $f9,(SC_FPREGS+72)(a0)) - EX(swc1 $f10,(SC_FPREGS+80)(a0)) - EX(swc1 $f11,(SC_FPREGS+88)(a0)) - EX(swc1 $f12,(SC_FPREGS+96)(a0)) - EX(swc1 $f13,(SC_FPREGS+104)(a0)) - EX(swc1 $f14,(SC_FPREGS+112)(a0)) - EX(swc1 $f15,(SC_FPREGS+120)(a0)) - EX(swc1 $f16,(SC_FPREGS+128)(a0)) - EX(swc1 $f17,(SC_FPREGS+136)(a0)) - EX(swc1 $f18,(SC_FPREGS+144)(a0)) - EX(swc1 $f19,(SC_FPREGS+152)(a0)) - EX(swc1 $f20,(SC_FPREGS+160)(a0)) - EX(swc1 $f21,(SC_FPREGS+168)(a0)) - EX(swc1 $f22,(SC_FPREGS+176)(a0)) - EX(swc1 $f23,(SC_FPREGS+184)(a0)) - EX(swc1 $f24,(SC_FPREGS+192)(a0)) - EX(swc1 $f25,(SC_FPREGS+200)(a0)) - EX(swc1 $f26,(SC_FPREGS+208)(a0)) - EX(swc1 $f27,(SC_FPREGS+216)(a0)) - EX(swc1 $f28,(SC_FPREGS+224)(a0)) - EX(swc1 $f29,(SC_FPREGS+232)(a0)) - EX(swc1 $f30,(SC_FPREGS+240)(a0)) - EX(swc1 $f31,(SC_FPREGS+248)(a0)) - EX(sw t1,(SC_FPC_CSR)(a0)) - cfc1 t0,$0 # implementation/version - jr ra - .set nomacro - EX(sw t0,(SC_FPC_EIR)(a0)) - .set macro - END(_save_fp_context) - -/* - * Restore FPU state: - * - fp gp registers - * - cp1 status/control register - * - * We base the decision which registers to restore from the signal stack - * frame on the current content of c0_status, not on the content of the - * stack frame which might have been changed by the user. - */ -LEAF(_restore_fp_context) - li v0, 0 # assume success - EX(lw t0,(SC_FPC_CSR)(a0)) - EX(lwc1 $f0,(SC_FPREGS+0)(a0)) - EX(lwc1 $f1,(SC_FPREGS+8)(a0)) - EX(lwc1 $f2,(SC_FPREGS+16)(a0)) - EX(lwc1 $f3,(SC_FPREGS+24)(a0)) - EX(lwc1 $f4,(SC_FPREGS+32)(a0)) - EX(lwc1 $f5,(SC_FPREGS+40)(a0)) - EX(lwc1 $f6,(SC_FPREGS+48)(a0)) - EX(lwc1 $f7,(SC_FPREGS+56)(a0)) - EX(lwc1 $f8,(SC_FPREGS+64)(a0)) - EX(lwc1 $f9,(SC_FPREGS+72)(a0)) - EX(lwc1 $f10,(SC_FPREGS+80)(a0)) - EX(lwc1 $f11,(SC_FPREGS+88)(a0)) - EX(lwc1 $f12,(SC_FPREGS+96)(a0)) - EX(lwc1 $f13,(SC_FPREGS+104)(a0)) - EX(lwc1 $f14,(SC_FPREGS+112)(a0)) - EX(lwc1 $f15,(SC_FPREGS+120)(a0)) - EX(lwc1 $f16,(SC_FPREGS+128)(a0)) - EX(lwc1 $f17,(SC_FPREGS+136)(a0)) - EX(lwc1 $f18,(SC_FPREGS+144)(a0)) - EX(lwc1 $f19,(SC_FPREGS+152)(a0)) - EX(lwc1 $f20,(SC_FPREGS+160)(a0)) - EX(lwc1 $f21,(SC_FPREGS+168)(a0)) - EX(lwc1 $f22,(SC_FPREGS+176)(a0)) - EX(lwc1 $f23,(SC_FPREGS+184)(a0)) - EX(lwc1 $f24,(SC_FPREGS+192)(a0)) - EX(lwc1 $f25,(SC_FPREGS+200)(a0)) - EX(lwc1 $f26,(SC_FPREGS+208)(a0)) - EX(lwc1 $f27,(SC_FPREGS+216)(a0)) - EX(lwc1 $f28,(SC_FPREGS+224)(a0)) - EX(lwc1 $f29,(SC_FPREGS+232)(a0)) - EX(lwc1 $f30,(SC_FPREGS+240)(a0)) - EX(lwc1 $f31,(SC_FPREGS+248)(a0)) - jr ra - ctc1 t0,fcr31 - END(_restore_fp_context) - .set reorder - - .type fault@function - .ent fault -fault: li v0, -EFAULT - jr ra - .end fault diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S deleted file mode 100644 index dbd42ad..0000000 --- a/arch/mips/kernel/r4k_fpu.S +++ /dev/null @@ -1,188 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle - * - * Multi-arch abstraction and asm macros for easier reading: - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. - * Copyright (C) 1999, 2001 Silicon Graphics, Inc. - */ -#include -#include -#include -#include -#include -#include - - .macro EX insn, reg, src - .set push - .set nomacro -.ex\@: \insn \reg, \src - .set pop - .section __ex_table,"a" - PTR .ex\@, fault - .previous - .endm - - .set noreorder - .set mips3 - -LEAF(_save_fp_context) - cfc1 t1, fcr31 - -#ifdef CONFIG_64BIT - /* Store the 16 odd double precision registers */ - EX sdc1 $f1, SC_FPREGS+8(a0) - EX sdc1 $f3, SC_FPREGS+24(a0) - EX sdc1 $f5, SC_FPREGS+40(a0) - EX sdc1 $f7, SC_FPREGS+56(a0) - EX sdc1 $f9, SC_FPREGS+72(a0) - EX sdc1 $f11, SC_FPREGS+88(a0) - EX sdc1 $f13, SC_FPREGS+104(a0) - EX sdc1 $f15, SC_FPREGS+120(a0) - EX sdc1 $f17, SC_FPREGS+136(a0) - EX sdc1 $f19, SC_FPREGS+152(a0) - EX sdc1 $f21, SC_FPREGS+168(a0) - EX sdc1 $f23, SC_FPREGS+184(a0) - EX sdc1 $f25, SC_FPREGS+200(a0) - EX sdc1 $f27, SC_FPREGS+216(a0) - EX sdc1 $f29, SC_FPREGS+232(a0) - EX sdc1 $f31, SC_FPREGS+248(a0) -#endif - - /* Store the 16 even double precision registers */ - EX sdc1 $f0, SC_FPREGS+0(a0) - EX sdc1 $f2, SC_FPREGS+16(a0) - EX sdc1 $f4, SC_FPREGS+32(a0) - EX sdc1 $f6, SC_FPREGS+48(a0) - EX sdc1 $f8, SC_FPREGS+64(a0) - EX sdc1 $f10, SC_FPREGS+80(a0) - EX sdc1 $f12, SC_FPREGS+96(a0) - EX sdc1 $f14, SC_FPREGS+112(a0) - EX sdc1 $f16, SC_FPREGS+128(a0) - EX sdc1 $f18, SC_FPREGS+144(a0) - EX sdc1 $f20, SC_FPREGS+160(a0) - EX sdc1 $f22, SC_FPREGS+176(a0) - EX sdc1 $f24, SC_FPREGS+192(a0) - EX sdc1 $f26, SC_FPREGS+208(a0) - EX sdc1 $f28, SC_FPREGS+224(a0) - EX sdc1 $f30, SC_FPREGS+240(a0) - EX sw t1, SC_FPC_CSR(a0) - jr ra - li v0, 0 # success - END(_save_fp_context) - -#ifdef CONFIG_MIPS32_COMPAT - /* Save 32-bit process floating point context */ -LEAF(_save_fp_context32) - cfc1 t1, fcr31 - - EX sdc1 $f0, SC32_FPREGS+0(a0) - EX sdc1 $f2, SC32_FPREGS+16(a0) - EX sdc1 $f4, SC32_FPREGS+32(a0) - EX sdc1 $f6, SC32_FPREGS+48(a0) - EX sdc1 $f8, SC32_FPREGS+64(a0) - EX sdc1 $f10, SC32_FPREGS+80(a0) - EX sdc1 $f12, SC32_FPREGS+96(a0) - EX sdc1 $f14, SC32_FPREGS+112(a0) - EX sdc1 $f16, SC32_FPREGS+128(a0) - EX sdc1 $f18, SC32_FPREGS+144(a0) - EX sdc1 $f20, SC32_FPREGS+160(a0) - EX sdc1 $f22, SC32_FPREGS+176(a0) - EX sdc1 $f24, SC32_FPREGS+192(a0) - EX sdc1 $f26, SC32_FPREGS+208(a0) - EX sdc1 $f28, SC32_FPREGS+224(a0) - EX sdc1 $f30, SC32_FPREGS+240(a0) - EX sw t1, SC32_FPC_CSR(a0) - cfc1 t0, $0 # implementation/version - EX sw t0, SC32_FPC_EIR(a0) - - jr ra - li v0, 0 # success - END(_save_fp_context32) -#endif - -/* - * Restore FPU state: - * - fp gp registers - * - cp1 status/control register - */ -LEAF(_restore_fp_context) - EX lw t0, SC_FPC_CSR(a0) -#ifdef CONFIG_64BIT - EX ldc1 $f1, SC_FPREGS+8(a0) - EX ldc1 $f3, SC_FPREGS+24(a0) - EX ldc1 $f5, SC_FPREGS+40(a0) - EX ldc1 $f7, SC_FPREGS+56(a0) - EX ldc1 $f9, SC_FPREGS+72(a0) - EX ldc1 $f11, SC_FPREGS+88(a0) - EX ldc1 $f13, SC_FPREGS+104(a0) - EX ldc1 $f15, SC_FPREGS+120(a0) - EX ldc1 $f17, SC_FPREGS+136(a0) - EX ldc1 $f19, SC_FPREGS+152(a0) - EX ldc1 $f21, SC_FPREGS+168(a0) - EX ldc1 $f23, SC_FPREGS+184(a0) - EX ldc1 $f25, SC_FPREGS+200(a0) - EX ldc1 $f27, SC_FPREGS+216(a0) - EX ldc1 $f29, SC_FPREGS+232(a0) - EX ldc1 $f31, SC_FPREGS+248(a0) -#endif - EX ldc1 $f0, SC_FPREGS+0(a0) - EX ldc1 $f2, SC_FPREGS+16(a0) - EX ldc1 $f4, SC_FPREGS+32(a0) - EX ldc1 $f6, SC_FPREGS+48(a0) - EX ldc1 $f8, SC_FPREGS+64(a0) - EX ldc1 $f10, SC_FPREGS+80(a0) - EX ldc1 $f12, SC_FPREGS+96(a0) - EX ldc1 $f14, SC_FPREGS+112(a0) - EX ldc1 $f16, SC_FPREGS+128(a0) - EX ldc1 $f18, SC_FPREGS+144(a0) - EX ldc1 $f20, SC_FPREGS+160(a0) - EX ldc1 $f22, SC_FPREGS+176(a0) - EX ldc1 $f24, SC_FPREGS+192(a0) - EX ldc1 $f26, SC_FPREGS+208(a0) - EX ldc1 $f28, SC_FPREGS+224(a0) - EX ldc1 $f30, SC_FPREGS+240(a0) - ctc1 t0, fcr31 - jr ra - li v0, 0 # success - END(_restore_fp_context) - -#ifdef CONFIG_MIPS32_COMPAT -LEAF(_restore_fp_context32) - /* Restore an o32 sigcontext. */ - EX lw t0, SC32_FPC_CSR(a0) - EX ldc1 $f0, SC32_FPREGS+0(a0) - EX ldc1 $f2, SC32_FPREGS+16(a0) - EX ldc1 $f4, SC32_FPREGS+32(a0) - EX ldc1 $f6, SC32_FPREGS+48(a0) - EX ldc1 $f8, SC32_FPREGS+64(a0) - EX ldc1 $f10, SC32_FPREGS+80(a0) - EX ldc1 $f12, SC32_FPREGS+96(a0) - EX ldc1 $f14, SC32_FPREGS+112(a0) - EX ldc1 $f16, SC32_FPREGS+128(a0) - EX ldc1 $f18, SC32_FPREGS+144(a0) - EX ldc1 $f20, SC32_FPREGS+160(a0) - EX ldc1 $f22, SC32_FPREGS+176(a0) - EX ldc1 $f24, SC32_FPREGS+192(a0) - EX ldc1 $f26, SC32_FPREGS+208(a0) - EX ldc1 $f28, SC32_FPREGS+224(a0) - EX ldc1 $f30, SC32_FPREGS+240(a0) - ctc1 t0, fcr31 - jr ra - li v0, 0 # success - END(_restore_fp_context32) -#endif - - .set reorder - - .type fault@function - .ent fault -fault: li v0, -EFAULT # failure - jr ra - .end fault diff --git a/arch/mips/kernel/r6000_fpu.S b/arch/mips/kernel/r6000_fpu.S deleted file mode 100644 index 43cda53..0000000 --- a/arch/mips/kernel/r6000_fpu.S +++ /dev/null @@ -1,87 +0,0 @@ -/* - * r6000_fpu.S: Save/restore floating point context for signal handlers. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996 by Ralf Baechle - * - * Multi-arch abstraction and asm macros for easier reading: - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include -#include -#include -#include - - .set noreorder - .set mips2 - /* Save floating point context */ - LEAF(_save_fp_context) - mfc0 t0,CP0_STATUS - sll t0,t0,2 - bgez t0,1f - nop - - cfc1 t1,fcr31 - /* Store the 16 double precision registers */ - sdc1 $f0,(SC_FPREGS+0)(a0) - sdc1 $f2,(SC_FPREGS+16)(a0) - sdc1 $f4,(SC_FPREGS+32)(a0) - sdc1 $f6,(SC_FPREGS+48)(a0) - sdc1 $f8,(SC_FPREGS+64)(a0) - sdc1 $f10,(SC_FPREGS+80)(a0) - sdc1 $f12,(SC_FPREGS+96)(a0) - sdc1 $f14,(SC_FPREGS+112)(a0) - sdc1 $f16,(SC_FPREGS+128)(a0) - sdc1 $f18,(SC_FPREGS+144)(a0) - sdc1 $f20,(SC_FPREGS+160)(a0) - sdc1 $f22,(SC_FPREGS+176)(a0) - sdc1 $f24,(SC_FPREGS+192)(a0) - sdc1 $f26,(SC_FPREGS+208)(a0) - sdc1 $f28,(SC_FPREGS+224)(a0) - sdc1 $f30,(SC_FPREGS+240)(a0) - jr ra - sw t0,SC_FPC_CSR(a0) -1: jr ra - nop - END(_save_fp_context) - -/* Restore FPU state: - * - fp gp registers - * - cp1 status/control register - * - * We base the decision which registers to restore from the signal stack - * frame on the current content of c0_status, not on the content of the - * stack frame which might have been changed by the user. - */ - LEAF(_restore_fp_context) - mfc0 t0,CP0_STATUS - sll t0,t0,2 - - bgez t0,1f - lw t0,SC_FPC_CSR(a0) - /* Restore the 16 double precision registers */ - ldc1 $f0,(SC_FPREGS+0)(a0) - ldc1 $f2,(SC_FPREGS+16)(a0) - ldc1 $f4,(SC_FPREGS+32)(a0) - ldc1 $f6,(SC_FPREGS+48)(a0) - ldc1 $f8,(SC_FPREGS+64)(a0) - ldc1 $f10,(SC_FPREGS+80)(a0) - ldc1 $f12,(SC_FPREGS+96)(a0) - ldc1 $f14,(SC_FPREGS+112)(a0) - ldc1 $f16,(SC_FPREGS+128)(a0) - ldc1 $f18,(SC_FPREGS+144)(a0) - ldc1 $f20,(SC_FPREGS+160)(a0) - ldc1 $f22,(SC_FPREGS+176)(a0) - ldc1 $f24,(SC_FPREGS+192)(a0) - ldc1 $f26,(SC_FPREGS+208)(a0) - ldc1 $f28,(SC_FPREGS+224)(a0) - ldc1 $f30,(SC_FPREGS+240)(a0) - jr ra - ctc1 t0,fcr31 -1: jr ra - nop - END(_restore_fp_context) diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index fa58119..83b16d5 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -78,6 +78,38 @@ struct rt_sigframe { /* * Helper routines */ +static int save_fp_context(struct sigcontext __user *sc) +{ + int i; + int err = 0; + + for (i = 0; i < 32; i++) { + err |= + __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); +#ifdef CONFIG_32BIT + i++; /* skip odd registers */ +#endif + } + err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); + return err; +} + +static int restore_fp_context(struct sigcontext __user *sc) +{ + int i; + int err = 0; + + for (i = 0; i < 32; i++) { + err |= + __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); +#ifdef CONFIG_32BIT + i++; /* skip odd registers */ +#endif + } + err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); + return err; +} + int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { int err = 0; @@ -113,10 +145,9 @@ int setup_sigcontext(struct pt_regs *reg * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ - preempt_disable(); - own_fpu(1); + /* save current context to task_struct */ + lose_fpu(1); err |= save_fp_context(sc); - preempt_enable(); } return err; } @@ -148,10 +179,7 @@ check_and_restore_fp_context(struct sigc err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; - preempt_disable(); - own_fpu(0); err |= restore_fp_context(sc); - preempt_enable(); return err ?: sig; } @@ -188,13 +216,13 @@ int restore_sigcontext(struct pt_regs *r err |= __get_user(used_math, &sc->sc_used_math); conditional_used_math(used_math); + /* signal handler may have used FPU. Give it up. */ + lose_fpu(0); + if (used_math) { /* restore fpu context if we have used it before */ if (!err) err = check_and_restore_fp_context(sc); - } else { - /* signal handler may have used FPU. Give it up. */ - lose_fpu(0); } return err; diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 53a337c..81b81d6 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -176,6 +176,30 @@ struct rt_sigframe32 { /* * sigcontext handlers */ +static int save_fp_context32(struct sigcontext32 __user *sc) +{ + int i; + int err = 0; + + for (i = 0; i < 32; i += 2) + err |= + __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); + err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); + return err; +} + +static int restore_fp_context32(struct sigcontext32 __user *sc) +{ + int i; + int err = 0; + + for (i = 0; i < 32; i += 2) + err |= + __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); + err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); + return err; +} + static int setup_sigcontext32(struct pt_regs *regs, struct sigcontext32 __user *sc) { @@ -209,10 +233,9 @@ static int setup_sigcontext32(struct pt_ * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ - preempt_disable(); - own_fpu(1); + /* save current context to task_struct */ + lose_fpu(1); err |= save_fp_context32(sc); - preempt_enable(); } return err; } @@ -225,10 +248,7 @@ check_and_restore_fp_context32(struct si err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; - preempt_disable(); - own_fpu(0); err |= restore_fp_context32(sc); - preempt_enable(); return err ?: sig; } @@ -262,13 +282,13 @@ static int restore_sigcontext32(struct p err |= __get_user(used_math, &sc->sc_used_math); conditional_used_math(used_math); + /* signal handler may have used FPU. Give it up. */ + lose_fpu(0); + if (used_math) { /* restore fpu context if we have used it before */ if (!err) err = check_and_restore_fp_context32(sc); - } else { - /* signal handler may have used FPU. Give it up. */ - lose_fpu(0); } return err; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 493cb29..83180b4 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1231,77 +1231,6 @@ static inline void mips_srs_init(void) #endif /* CONFIG_CPU_MIPSR2_SRS */ -/* - * This is used by native signal handling - */ -asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); -asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); - -extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); -extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); - -extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); -extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); - -#ifdef CONFIG_SMP -static int smp_save_fp_context(struct sigcontext __user *sc) -{ - return raw_cpu_has_fpu - ? _save_fp_context(sc) - : fpu_emulator_save_context(sc); -} - -static int smp_restore_fp_context(struct sigcontext __user *sc) -{ - return raw_cpu_has_fpu - ? _restore_fp_context(sc) - : fpu_emulator_restore_context(sc); -} -#endif - -static inline void signal_init(void) -{ -#ifdef CONFIG_SMP - /* For now just do the cpu_has_fpu check when the functions are invoked */ - save_fp_context = smp_save_fp_context; - restore_fp_context = smp_restore_fp_context; -#else - if (cpu_has_fpu) { - save_fp_context = _save_fp_context; - restore_fp_context = _restore_fp_context; - } else { - save_fp_context = fpu_emulator_save_context; - restore_fp_context = fpu_emulator_restore_context; - } -#endif -} - -#ifdef CONFIG_MIPS32_COMPAT - -/* - * This is used by 32-bit signal stuff on the 64-bit kernel - */ -asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); -asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); - -extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); -extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); - -extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); -extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); - -static inline void signal32_init(void) -{ - if (cpu_has_fpu) { - save_fp_context32 = _save_fp_context32; - restore_fp_context32 = _restore_fp_context32; - } else { - save_fp_context32 = fpu_emulator_save_context32; - restore_fp_context32 = fpu_emulator_restore_context32; - } -} -#endif - extern void cpu_cache_init(void); extern void tlb_init(void); extern void flush_tlb_handlers(void); @@ -1543,11 +1472,6 @@ void __init trap_init(void) else memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); - signal_init(); -#ifdef CONFIG_MIPS32_COMPAT - signal32_init(); -#endif - flush_icache_range(ebase, ebase + 0x400); flush_tlb_handlers(); } diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c index ed49ef0..f9a7741 100644 --- a/arch/mips/math-emu/kernel_linkage.c +++ b/arch/mips/math-emu/kernel_linkage.c @@ -20,10 +20,6 @@ * FPU Emulator */ #include -#include -#include -#include - #include #define SIGNALLING_NAN 0x7ff800007ff80000LL @@ -43,72 +39,3 @@ void fpu_emulator_init_fpu(void) current->thread.fpu.fpr[i] = SIGNALLING_NAN; } } - - -/* - * Emulator context save/restore to/from a signal context - * presumed to be on the user stack, and therefore accessed - * with appropriate macros from uaccess.h - */ - -int fpu_emulator_save_context(struct sigcontext __user *sc) -{ - int i; - int err = 0; - - for (i = 0; i < 32; i++) { - err |= - __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); - } - err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); - - return err; -} - -int fpu_emulator_restore_context(struct sigcontext __user *sc) -{ - int i; - int err = 0; - - for (i = 0; i < 32; i++) { - err |= - __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); - } - err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); - - return err; -} - -#ifdef CONFIG_64BIT -/* - * This is the o32 version - */ - -int fpu_emulator_save_context32(struct sigcontext32 __user *sc) -{ - int i; - int err = 0; - - for (i = 0; i < 32; i+=2) { - err |= - __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); - } - err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); - - return err; -} - -int fpu_emulator_restore_context32(struct sigcontext32 __user *sc) -{ - int i; - int err = 0; - - for (i = 0; i < 32; i+=2) { - err |= - __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); - } - err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); - - return err; -} -#endif diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 71436f9..666d7d4 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -24,15 +24,6 @@ #include #endif -struct sigcontext; -struct sigcontext32; - -extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); -extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); - -extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); -extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); - extern void fpu_emulator_init_fpu(void); extern void _init_fpu(void); extern void _save_fp(struct task_struct *); From tiansm@lemote.com Sun Apr 15 16:26:23 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:26:25 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:7129 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022598AbXDOP0X (ORCPT ); Sun, 15 Apr 2007 16:26:23 +0100 Received: (qmail 19499 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 15/16] work around for more than 256MB memory support Date: Sun, 15 Apr 2007 23:26:04 +0800 Message-Id: <11766507672043-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507672298-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <11766507661684-git-send-email-tiansm@lemote.com> <117665076617-git-send-email-tiansm@lemote.com> <1176650766907-git-send-email-tiansm@lemote.com> <11766507663301-git-send-email-tiansm@lemote.com> <11766507663039-git-send-email-tiansm@lemote.com> <1176650766685-git-send-email-tiansm@lemote.com> <11766507661790-git-send-email-tiansm@lemote.com> <11766507672298-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14840 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- drivers/char/mem.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/char/mem.c b/drivers/char/mem.c index f5c160c..580ad3e 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -83,8 +83,12 @@ static inline int uncached_access(struct file *file, unsigned long addr) */ if (file->f_flags & O_SYNC) return 1; +#if defined(CONFIG_LEMOTE_FULONG) && defined(CONFIG_64BIT) + return (addr >= __pa(high_memory)) || ((addr >=0x10000000) && (addr < 0x20000000)); +#else return addr >= __pa(high_memory); #endif +#endif } #ifndef ARCH_HAS_VALID_PHYS_ADDR_RANGE -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:26:45 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:26:48 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:10201 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022610AbXDOP0Z (ORCPT ); Sun, 15 Apr 2007 16:26:25 +0100 Received: (qmail 19432 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC Date: Sun, 15 Apr 2007 23:25:51 +0800 Message-Id: <11766507661726-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507661317-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14841 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- arch/mips/Makefile | 8 ++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/lib-32/Makefile | 1 + arch/mips/lib-64/Makefile | 1 + arch/mips/mm/Makefile | 1 + arch/mips/pci/Makefile | 1 + 6 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 92bca6a..2a6742d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -118,6 +118,7 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -Wa,-mips32 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ @@ -298,6 +299,13 @@ cflags-$(CONFIG_WR_PPMC) += -Iinclude/asm-mips/mach-wrppmc load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 # +# lemote fulong mini-PC board +# +core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/ +load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000 +cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote + +# # For all MIPS, Inc. eval boards # core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 4924626..40fdf79 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile index 8b94d4c..b4be604 100644 --- a/arch/mips/lib-32/Makefile +++ b/arch/mips/lib-32/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_CPU_SB1) += dump_tlb.o obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o +obj-$(CONFIG_CPU_LOONGSON2) += dump_tlb.o diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile index 8b94d4c..b4be604 100644 --- a/arch/mips/lib-64/Makefile +++ b/arch/mips/lib-64/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_CPU_SB1) += dump_tlb.o obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o +obj-$(CONFIG_CPU_LOONGSON2) += dump_tlb.o diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 293697b..ab24195 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o +obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_CPU_SB1) += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \ tlb-r4k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index bf85995..3a77235 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o +obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-lm2e.o -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:27:08 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:27:10 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:7897 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022614AbXDOP01 (ORCPT ); Sun, 15 Apr 2007 16:26:27 +0100 Received: (qmail 19483 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 11/16] add Loongson support to /proc/cpuinfo Date: Sun, 15 Apr 2007 23:26:00 +0800 Message-Id: <11766507663039-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507663301-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <11766507661684-git-send-email-tiansm@lemote.com> <117665076617-git-send-email-tiansm@lemote.com> <1176650766907-git-send-email-tiansm@lemote.com> <11766507663301-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14842 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- arch/mips/kernel/proc.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 5ddc2e9..e915117 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -84,6 +84,7 @@ static const char *cpu_name[] = { [CPU_VR4181A] = "NEC VR4181A", [CPU_SR71000] = "Sandcraft SR71000", [CPU_PR4450] = "Philips PR4450", + [CPU_LOONGSON2] = "ICT Loongson-2", }; -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:27:30 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:27:33 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:9945 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022619AbXDOP03 (ORCPT ); Sun, 15 Apr 2007 16:26:29 +0100 Received: (qmail 19447 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 5/16] add MACH_GROUP_LEMOTE & MACH_LEMOTE_FULONG Date: Sun, 15 Apr 2007 23:25:54 +0800 Message-Id: <11766507661526-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507661133-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14843 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- include/asm-mips/bootinfo.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index c7c945b..f4607f1 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -213,6 +213,12 @@ #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ +/* + * Valid machtype for group LEMOTE + */ +#define MACH_GROUP_LEMOTE 27 +#define MACH_LEMOTE_FULONG 0 + #define CL_SIZE COMMAND_LINE_SIZE const char *get_system_type(void); -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:27:53 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:27:55 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:8921 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022617AbXDOP03 (ORCPT ); Sun, 15 Apr 2007 16:26:29 +0100 Received: (qmail 19468 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 8/16] define MODULE_PROC_FAMILY for Loongson2 Date: Sun, 15 Apr 2007 23:25:57 +0800 Message-Id: <117665076617-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507661684-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <11766507661684-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14844 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- include/asm-mips/module.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h index 399d03f..f615324 100644 --- a/include/asm-mips/module.h +++ b/include/asm-mips/module.h @@ -112,6 +112,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "RM9000 " #elif defined CONFIG_CPU_SB1 #define MODULE_PROC_FAMILY "SB1 " +#elif defined CONFIG_CPU_LOONGSON2 +#define MODULE_PROC_FAMILY "LOONGSON2 " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:28:15 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:28:20 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:9433 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022624AbXDOP0i (ORCPT ); Sun, 15 Apr 2007 16:26:38 +0100 Received: (qmail 19427 invoked by uid 511); 15 Apr 2007 15:28:05 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:05 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 1/16] new files for lemote fulong mini-PC support Date: Sun, 15 Apr 2007 23:25:50 +0800 Message-Id: <11766507661317-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507651736-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14845 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang Signed-off-by: Songmao Tian --- arch/mips/lemote/lm2e/Makefile | 7 + arch/mips/lemote/lm2e/bonito-irq.c | 74 +++++ arch/mips/lemote/lm2e/dbg_io.c | 146 ++++++++++ arch/mips/lemote/lm2e/irq.c | 146 ++++++++++ arch/mips/lemote/lm2e/pci.c | 72 +++++ arch/mips/lemote/lm2e/prom.c | 109 ++++++++ arch/mips/lemote/lm2e/reset.c | 46 +++ arch/mips/lemote/lm2e/setup.c | 144 ++++++++++ arch/mips/pci/fixup-lm2e.c | 256 +++++++++++++++++ arch/mips/pci/ops-lm2e.c | 153 +++++++++++ include/asm-mips/mach-lemote/bonito.h | 381 ++++++++++++++++++++++++++ include/asm-mips/mach-lemote/dma-coherence.h | 43 +++ include/asm-mips/mach-lemote/mc146818rtc.h | 36 +++ 13 files changed, 1613 insertions(+), 0 deletions(-) diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile new file mode 100644 index 0000000..0ba6f12 --- /dev/null +++ b/arch/mips/lemote/lm2e/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for Lemote Fulong mini-PC board. +# + +obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o +EXTRA_AFLAGS := $(CFLAGS) + diff --git a/arch/mips/lemote/lm2e/bonito-irq.c b/arch/mips/lemote/lm2e/bonito-irq.c new file mode 100644 index 0000000..a81f0d6 --- /dev/null +++ b/arch/mips/lemote/lm2e/bonito-irq.c @@ -0,0 +1,74 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include + +#include + + +static inline void bonito_irq_enable(unsigned int irq) +{ + BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); + mmiowb(); +} + +static inline void bonito_irq_disable(unsigned int irq) +{ + BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); + mmiowb(); +} + +static struct irq_chip bonito_irq_type = { + .name = "bonito_irq", + .ack = bonito_irq_disable, + .mask = bonito_irq_disable, + .mask_ack = bonito_irq_disable, + .unmask = bonito_irq_enable, +}; + +static struct irqaction dma_timeout_irqaction = { + .handler = no_action, + .name = "dma_timeout", +}; + +void bonito_irq_init(void) +{ + u32 i; + + for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) { + set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); + } + + setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); +} diff --git a/arch/mips/lemote/lm2e/dbg_io.c b/arch/mips/lemote/lm2e/dbg_io.c new file mode 100644 index 0000000..f54bfaa --- /dev/null +++ b/arch/mips/lemote/lm2e/dbg_io.c @@ -0,0 +1,146 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include /* For the serial port location and base baud */ + +#define UART16550_BAUD_2400 2400 +#define UART16550_BAUD_4800 4800 +#define UART16550_BAUD_9600 9600 +#define UART16550_BAUD_19200 19200 +#define UART16550_BAUD_38400 38400 +#define UART16550_BAUD_57600 57600 +#define UART16550_BAUD_115200 115200 + +#define UART16550_PARITY_NONE 0 +#define UART16550_PARITY_ODD 0x08 +#define UART16550_PARITY_EVEN 0x18 +#define UART16550_PARITY_MARK 0x28 +#define UART16550_PARITY_SPACE 0x38 + +#define UART16550_DATA_5BIT 0x0 +#define UART16550_DATA_6BIT 0x1 +#define UART16550_DATA_7BIT 0x2 +#define UART16550_DATA_8BIT 0x3 + +#define UART16550_STOP_1BIT 0x0 +#define UART16550_STOP_2BIT 0x4 + +/* ----------------------------------------------------- */ + +/* === CONFIG === */ +#ifdef CONFIG_64BIT +#define BASE (0xffffffffbfd003f8) +#else +#define BASE (0xbfd003f8) +#endif + +#define MAX_BAUD BASE_BAUD +/* === END OF CONFIG === */ + +#define REG_OFFSET 1 + +/* register offset */ +#define OFS_RCV_BUFFER 0 +#define OFS_TRANS_HOLD 0 +#define OFS_SEND_BUFFER 0 +#define OFS_INTR_ENABLE (1*REG_OFFSET) +#define OFS_INTR_ID (2*REG_OFFSET) +#define OFS_DATA_FORMAT (3*REG_OFFSET) +#define OFS_LINE_CONTROL (3*REG_OFFSET) +#define OFS_MODEM_CONTROL (4*REG_OFFSET) +#define OFS_RS232_OUTPUT (4*REG_OFFSET) +#define OFS_LINE_STATUS (5*REG_OFFSET) +#define OFS_MODEM_STATUS (6*REG_OFFSET) +#define OFS_RS232_INPUT (6*REG_OFFSET) +#define OFS_SCRATCH_PAD (7*REG_OFFSET) + +#define OFS_DIVISOR_LSB (0*REG_OFFSET) +#define OFS_DIVISOR_MSB (1*REG_OFFSET) + +/* memory-mapped read/write of the port */ +#define UART16550_READ(y) (*((volatile u8*)(BASE + y))) +#define UART16550_WRITE(y, z) ((*((volatile u8*)(BASE + y))) = z) + +void debugInit(u32 baud, u8 data, u8 parity, u8 stop) +{ + /* disable interrupts */ + UART16550_WRITE(OFS_INTR_ENABLE, 0); + + /* set up buad rate */ + { + u32 divisor; + + /* set DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + divisor = MAX_BAUD / baud; + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); + + /* clear DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); + } + + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); +} + +static int remoteDebugInitialized = 0; + +u8 getDebugChar(void) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(UART16550_BAUD_115200, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0) ; + return UART16550_READ(OFS_RCV_BUFFER); +} + +int putDebugChar(u8 byte) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + /* + debugInit(UART16550_BAUD_115200, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); */ + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0) ; + UART16550_WRITE(OFS_SEND_BUFFER, byte); + return 1; +} diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c new file mode 100644 index 0000000..476ba9e --- /dev/null +++ b/arch/mips/lemote/lm2e/irq.c @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* + * the first level int-handler will jump here if it is a bonito irq + */ +static void bonito_irqdispatch(void) +{ + u32 int_status; + int i; + + /* workaround the IO dma problem: let cpu looping to allow DMA finish */ + int_status = BONITO_INTISR; + if (int_status & (1 << 10)) { + while (int_status & (1 << 10)) { + udelay(1); + int_status = BONITO_INTISR; + } + } + + /* Get pending sources, masked by current enables */ + int_status = BONITO_INTISR & BONITO_INTEN; + + if (int_status != 0) { + i = __ffs(int_status); + int_status &= ~(1 << i); + do_IRQ(i +BONITO_IRQ_BASE); + } + return; +} + +static void i8259_irqdispatch(void) +{ + int irq; + + irq = i8259_irq(); + if (irq >= 0) { + do_IRQ(irq); + } else { + spurious_interrupt(); + } + +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + + if (pending & CAUSEF_IP7) { + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + } else if (pending & CAUSEF_IP5) { + i8259_irqdispatch(); + } else if (pending & CAUSEF_IP2) { + bonito_irqdispatch(); + } else { + spurious_interrupt(); + } +} + +static struct irqaction cascade_irqaction = { + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", +}; + +void __init arch_init_irq(void) +{ + extern void bonito_irq_init(void); + + printk(KERN_INFO"arch init irq\n"); + /* + * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap + */ + clear_c0_status(ST0_IM | ST0_BEV); + local_irq_disable(); + + /* most bonito irq should be level triggered */ + BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR + | BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; + BONITO_INTSTEER = 0; + + /* + * Mask out all interrupt by writing "1" to all bit position in + * the interrupt reset reg. + */ + BONITO_INTENCLR = ~0; + + /* init all controller + * 0-15 ------> i8259 interrupt + * 16-23 ------> mips cpu interrupt + * 32-63 ------> bonito irq + */ + + /* Sets the first-level interrupt dispatcher. */ + mips_cpu_irq_init(); + init_i8259_irqs(); + bonito_irq_init(); + + /* + printk("GPIODATA=%x, GPIOIE=%x\n", BONITO_GPIODATA, BONITO_GPIOIE); + printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n", + BONITO_INTEN, BONITO_INTENSET, + BONITO_INTENCLR, BONITO_INTISR); + */ + + /* bonito irq at IP2 */ + setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); + /* 8259 irq at IP5 */ + setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); + +} diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c new file mode 100644 index 0000000..e9c5ce2 --- /dev/null +++ b/arch/mips/lemote/lm2e/pci.c @@ -0,0 +1,72 @@ +/* + * pci.c + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include + +extern struct pci_ops loongson2e_pci_pci_ops; + +static struct resource loongson2e_pci_mem_resource = { + .name = "LOONGSON2E PCI MEM", + .start = 0x14000000UL, + .end = 0x1fffffffUL, + .flags = IORESOURCE_MEM, +}; + +static struct resource loongson2e_pci_io_resource = { + .name = "LOONGSON2E PCI IO MEM", + .start = 0x00004000UL, + .end = 0x1fffffffUL, + .flags = IORESOURCE_IO, +}; + + +static struct pci_controller loongson2e_pci_controller = { + .pci_ops = &loongson2e_pci_pci_ops, + .io_resource = &loongson2e_pci_io_resource, + .mem_resource = &loongson2e_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_offset = 0x00000000UL, +}; + + +static int __init pcibios_init(void) +{ + extern int pci_probe_only; + pci_probe_only = 0; + +#ifdef CONFIG_TRACE_BOOT + printk(KERN_INFO"arch_initcall:pcibios_init\n"); + printk(KERN_INFO"register_pci_controller : %x\n",&loongson2e_pci_controller); +#endif + register_pci_controller(&loongson2e_pci_controller); + return 0; +} + +arch_initcall(pcibios_init); diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c new file mode 100644 index 0000000..bb70a69 --- /dev/null +++ b/arch/mips/lemote/lm2e/prom.c @@ -0,0 +1,109 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include + +#include +#include + +extern unsigned long bus_clock; +extern unsigned long cpu_clock; +extern unsigned int memsize, highmemsize; +extern int putDebugChar(unsigned char byte); + +static int argc; +/* pmon passes arguments in 32bit pointers */ +static int *arg; +static int *env; + +const char *get_system_type(void) +{ + return "lemote-fulong"; +} + +void __init prom_init_cmdline(void) +{ + int i; + long l; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < argc; i++) { + l = (long)arg[i]; + if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ((char *)l)); + strcat(arcs_cmdline, " "); + } +} + +void __init prom_init(void) +{ + long l; + argc = fw_arg0; + arg = (int *)fw_arg1; + env = (int *)fw_arg2; + + mips_machgroup = MACH_GROUP_LEMOTE; + mips_machtype = MACH_LEMOTE_FULONG; + + prom_init_cmdline(); + + if ((strstr(arcs_cmdline, "console=")) == NULL) + strcat(arcs_cmdline, " console=ttyS0,115200"); + if ((strstr(arcs_cmdline, "root=")) == NULL) + strcat(arcs_cmdline, " root=/dev/hda1"); + + l = (long)*env; + while (l != 0) { + if (strncmp("busclock", (char *)l, strlen("busclock")) == 0) { + bus_clock = simple_strtol((char *)l + strlen("busclock="), + NULL, 10); + } + if (strncmp("cpuclock", (char *)l, strlen("cpuclock")) == 0) { + cpu_clock = simple_strtol((char *)l + strlen("cpuclock="), + NULL, 10); + } + if (strncmp("memsize", (char *)l, strlen("memsize")) == 0) { + memsize = simple_strtol((char *)l + strlen("memsize="), + NULL, 10); + } + if (strncmp("highmemsize", (char *)l, strlen("highmemsize")) == 0) { + highmemsize = simple_strtol((char *)l + strlen("highmemsize="), + NULL, 10); + } + env++; + l = (long)*env; + } + if (memsize == 0) + memsize = 256; + + printk("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n", + bus_clock, cpu_clock, memsize, highmemsize); +} + +void __init prom_free_prom_memory(void) +{ +} + +void prom_putchar(char c) +{ + putDebugChar(c); +} diff --git a/arch/mips/lemote/lm2e/reset.c b/arch/mips/lemote/lm2e/reset.c new file mode 100644 index 0000000..0738732 --- /dev/null +++ b/arch/mips/lemote/lm2e/reset.c @@ -0,0 +1,46 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static void loongson2e_restart(char *command) +{ +#ifdef CONFIG_32BIT + *(unsigned long *)0xbfe00104 &= ~(1 << 2); + *(unsigned long *)0xbfe00104 |= (1 << 2); +#else + *(unsigned long *)0xffffffffbfe00104 &= ~(1 << 2); + *(unsigned long *)0xffffffffbfe00104 |= (1 << 2); +#endif + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); +} + +static void loongson2e_halt(void) +{ + while (1) ; +} + +static void loongson2e_power_off(void) +{ + loongson2e_halt(); +} + +void mips_reboot_setup(void) +{ + _machine_restart = loongson2e_restart; + _machine_halt = loongson2e_halt; + pm_power_off = loongson2e_power_off; +} diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c new file mode 100644 index 0000000..b372c58 --- /dev/null +++ b/arch/mips/lemote/lm2e/setup.c @@ -0,0 +1,144 @@ +/* + * BRIEF MODULE DESCRIPTION + * setup.c - board dependent boot routines + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_VT +#include +#include +#endif + +extern void mips_reboot_setup(void); + +#ifdef CONFIG_64BIT +#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p))) +#else +#define PTR_PAD(p) (p) +#endif + +unsigned long cpu_clock; +unsigned long bus_clock; +unsigned int memsize; +unsigned int highmemsize = 0; + +void __init plat_timer_setup(struct irqaction *irq) +{ + setup_irq(MIPS_CPU_IRQ_BASE + 7, irq); +} + +static void __init loongson2e_time_init(void) +{ + /* setup mips r4k timer */ + mips_hpt_frequency = cpu_clock / 2; +} + +static unsigned long __init mips_rtc_get_time(void) +{ + return mc146818_get_cmos_time(); +} + +void (*__wbflush) (void); +static void wbflush_loongson2e(void) +{ + asm(".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set mips3\n\t" + "sync\n\t" + "nop\n\t" + ".set\tpop\n\t" + ".set mips0\n\t"); +} + +void __init plat_mem_setup(void) +{ + set_io_port_base(PTR_PAD(0xbfd00000)); + + ioport_resource.start = 0; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0; + iomem_resource.end = 0xffffffff; + + mips_reboot_setup(); + + board_time_init = loongson2e_time_init; + rtc_mips_get_time = mips_rtc_get_time; + + __wbflush = wbflush_loongson2e; + + //add_memory_region(0x100000, (memsize<<20) - 0x100000, BOOT_MEM_RAM); + add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); +#ifdef CONFIG_64BIT + if (highmemsize > 0) { + add_memory_region(0x10000000, 0x10000000, BOOT_MEM_RESERVED); + add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM); + } +#endif + +#ifdef CONFIG_VT +#if defined(CONFIG_VGA_CONSOLE) + conswitchp = &vga_con; + + screen_info = (struct screen_info) { + 0, 25, /* orig-x, orig-y */ + 0, /* unused */ + 0, /* orig-video-page */ + 0, /* orig-video-mode */ + 80, /* orig-video-cols */ + 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ + 25, /* orig-video-lines */ + VIDEO_TYPE_VGAC, /* orig-video-isVGA */ + 16 /* orig-video-points */ + }; +#elif defined(CONFIG_DUMMY_CONSOLE) + conswitchp = &dummy_con; +#endif +#endif + +} + +#include +EXPORT_SYMBOL(__wbflush); + diff --git a/arch/mips/pci/fixup-lm2e.c b/arch/mips/pci/fixup-lm2e.c new file mode 100644 index 0000000..277f9fe --- /dev/null +++ b/arch/mips/pci/fixup-lm2e.c @@ -0,0 +1,256 @@ +/* + * fixup-lm2e.c + * + * Copyright (C) 2004 ICT CAS + * Author: Li xiaoyu, ICT CAS + * lixy@ict.ac.cn + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + unsigned int val; + if (PCI_SLOT(dev->devfn) == 4) { /* wireless card(notebook) */ + dev->irq = BONITO_IRQ_BASE + 26; + return dev->irq; + } else if (PCI_SLOT(dev->devfn) == 5) { /* via686b */ + switch (PCI_FUNC(dev->devfn)) { + case 2: + dev->irq = 10; + break; + case 3: + dev->irq = 11; + break; + case 5: + dev->irq = 9; + break; + } + return dev->irq; + } else if (PCI_SLOT(dev->devfn) == 6) { /* radeon 7000 */ + dev->irq = BONITO_IRQ_BASE + 27; + return dev->irq; + } else if (PCI_SLOT(dev->devfn) == 7) { /* 8139 */ + dev->irq = BONITO_IRQ_BASE + 26; + return dev->irq; + } else if (PCI_SLOT(dev->devfn) == 8) { /* nec usb */ + switch (PCI_FUNC(dev->devfn)) { + case 0: + dev->irq = BONITO_IRQ_BASE + 26; + break; + case 1: + dev->irq = BONITO_IRQ_BASE + 27; + dev->irq = 11; + break; + case 2: + dev->irq = BONITO_IRQ_BASE + 28; + break; + } + pci_read_config_dword(dev, 0xe0, &val); + pci_write_config_dword(dev, 0xe0, (val & ~7) | 0x4); + pci_write_config_dword(dev, 0xe4, 1 << 5); + return dev->irq; + } else + return 0; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) +{ + unsigned char c; + + printk(KERN_INFO"via686b fix: ISA bridge\n"); + + /* Enable I/O Recovery time */ + pci_write_config_byte(pdev, 0x40, 0x08); + + /* Enable ISA refresh */ + pci_write_config_byte(pdev, 0x41, 0x01); + + /* disable ISA line buffer */ + pci_write_config_byte(pdev, 0x45, 0x00); + + /* Gate INTR, and flush line buffer */ + pci_write_config_byte(pdev, 0x46, 0xe0); + + /* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */ + //pci_write_config_byte(pdev, 0x47, 0x20); + /* enable PCI Delay Transaction, Enable EISA ports 4D0/4D1. + * enable time-out timer + */ + pci_write_config_byte(pdev, 0x47, 0xe6); + + /* enable level trigger on pci irqs: 9,10,11,13 */ + /* important! without this PCI interrupts won't work */ + outb(0x2e, 0x4d1); + + /* 512 K PCI Decode */ + pci_write_config_byte(pdev, 0x48, 0x01); + + /* Wait for PGNT before grant to ISA Master/DMA */ + pci_write_config_byte(pdev, 0x4a, 0x84); + + /* Plug'n'Play */ + /* Parallel DRQ 3, Floppy DRQ 2 (default) */ + pci_write_config_byte(pdev, 0x50, 0x0e); + + /* IRQ Routing for Floppy and Parallel port */ + /* IRQ 6 for floppy, IRQ 7 for parallel port */ + pci_write_config_byte(pdev, 0x51, 0x76); + + /* IRQ Routing for serial ports (take IRQ 3 and 4) */ + pci_write_config_byte(pdev, 0x52, 0x34); + + /* All IRQ's level triggered. */ + pci_write_config_byte(pdev, 0x54, 0x00); + + /* route PIRQA-D irq */ + pci_write_config_byte(pdev, 0x55, 0x90); /* bit 7-4, PIRQA */ + pci_write_config_byte(pdev, 0x56, 0xba); /* bit 7-4, PIRQC; 3-0, PIRQB */ + pci_write_config_byte(pdev, 0x57, 0xd0); /* bit 7-4, PIRQD */ + + /* enable function 5/6, audio/modem */ + pci_read_config_byte(pdev, 0x85, &c); + c &= ~(0x3 << 2); + pci_write_config_byte(pdev, 0x85, c); + + printk(KERN_INFO"via686b fix: ISA bridge done\n"); +} + +static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) +{ + printk(KERN_INFO"via686b fix: IDE\n"); + + /* Modify IDE controller setup */ + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48); + pci_write_config_byte(pdev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + pci_write_config_byte(pdev, 0x40, 0x0b); + /* legacy mode */ + pci_write_config_byte(pdev, 0x42, 0x09); + +#if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */ + /* disable read prefetch/write post buffers */ + pci_write_config_byte(pdev, 0x41, 0x02); + + /* use 3/4 as fifo thresh hold */ + pci_write_config_byte(pdev, 0x43, 0x0a); + pci_write_config_byte(pdev, 0x44, 0x00); + + pci_write_config_byte(pdev, 0x45, 0x00); +#else + pci_write_config_byte(pdev, 0x41, 0xc2); + pci_write_config_byte(pdev, 0x43, 0x35); + pci_write_config_byte(pdev, 0x44, 0x1c); + + pci_write_config_byte(pdev, 0x45, 0x10); +#endif + + printk(KERN_INFO"via686b fix: IDE done\n"); +} + +static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev) +{ + unsigned int val; + unsigned char c; + + /* enable IO */ + pci_write_config_byte(pdev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + pci_read_config_dword(pdev, 0x4, &val); + pci_write_config_dword(pdev, 0x4, val | 1); + + /* route ac97 IRQ */ + pci_write_config_byte(pdev, 0x3c, 9); + pdev->irq = 9; + printk(KERN_INFO"ac97 interrupt = 9\n"); + + pci_read_config_byte(pdev, 0x8, &c); + printk(KERN_INFO"ac97 rev=%d\n", c); + + /* link control: enable link & SGD PCM output */ + pci_write_config_byte(pdev, 0x41, 0xcc); + + /* disable game port, FM, midi, sb, enable write to reg2c-2f */ + pci_write_config_byte(pdev, 0x42, 0x20); + + printk(KERN_INFO"Setting sub-vendor ID & device ID\n"); + + /* we are using Avance logic codec */ + pci_write_config_word(pdev, 0x2c, 0x1005); + pci_write_config_word(pdev, 0x2e, 0x4710); + pci_read_config_dword(pdev, 0x2c, &val); + printk(KERN_INFO"sub vendor-device id=%x\n", val); + + pci_write_config_byte(pdev, 0x42, 0x0); +} + +static void __init loongson2e_fixup_pcimap(struct pci_dev *pdev) +{ + static int first = 1; + + (void)pdev; + if (first) + first = 0; + else + return; + + /* local to PCI mapping: [256M,512M] -> [256M,512M]; differ from pmon */ + /* + * cpu address space [256M,448M] is window for accessing pci space + * we set pcimap_lo[0,1,2] to map it to pci space [256M,448M] + * pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0 + */ + /* 1,00 0110 ,0001 01,00 0000 */ + BONITO_PCIMAP = 0x46140; + //1, 00 0010, 0000,01, 00 0000 + //BONITO_PCIMAP = 0x42040; + + /* + * PCI to local mapping: [2G,2G+256M] -> [0,256M] + */ + BONITO_PCIBASE0 = 0x80000000; + BONITO_PCIBASE1 = 0x00800000; + BONITO_PCIBASE2 = 0x90000000; + +} + +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, loongson2e_fixup_pcimap); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, + loongson2e_686b_func0_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, + loongson2e_686b_func1_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, + loongson2e_686b_func5_fixup); diff --git a/arch/mips/pci/ops-lm2e.c b/arch/mips/pci/ops-lm2e.c new file mode 100644 index 0000000..b868029 --- /dev/null +++ b/arch/mips/pci/ops-lm2e.c @@ -0,0 +1,153 @@ +/* + * ops-lm2e.c + * + * Copyright (C) 2004 ICT CAS + * Author: Li xiaoyu, ICT CAS + * lixy@ict.ac.cn + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include + +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +static inline void bflush(void) +{ + /* flush Bonito register writes */ + (void)BONITO_PCICMD; +} + +static int lm2e_pci_config_access(unsigned char access_type, + struct pci_bus *bus, unsigned int devfn, + int where, u32 *data) +{ + u32 busnum = bus->number; + u32 addr, type; + void *addrp; + int device = PCI_SLOT(devfn); + int function = PCI_FUNC(devfn); + int reg = where & ~3; + + if (busnum == 0) { + /* Type 0 configuration on onboard PCI bus */ + if (device > 20 || function > 7) { + *data = -1; /* device out of range */ + return PCIBIOS_DEVICE_NOT_FOUND; + } + addr = (1 << (device + 11)) | (function << 8) | reg; + type = 0; + } else { + /* Type 1 configuration on offboard PCI bus */ + if (device > 31 || function > 7) { + *data = -1; /* device out of range */ + return PCIBIOS_DEVICE_NOT_FOUND; + } + addr = (busnum << 16) | (device << 11) | (function << 8) | reg; + type = 0x10000; + } + + /* clear aborts */ + BONITO_PCICMD |= BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT; + + BONITO_PCIMAP_CFG = (addr >> 16) | type; + bflush(); + + addrp = (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (addr & 0xffff)); + if (access_type == PCI_ACCESS_WRITE) { + *(volatile unsigned int *)addrp = cpu_to_le32(*data); + } else { + *data = le32_to_cpu(*(volatile unsigned int *)addrp); + } + if (BONITO_PCICMD & (BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT)) { + BONITO_PCICMD |= BONITO_PCICMD_MABORT | BONITO_PCICMD_MTABORT; + *data = -1; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return PCIBIOS_SUCCESSFUL; + +} + +static int lm2e_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + u32 data = 0; + + int ret = lm2e_pci_config_access(PCI_ACCESS_READ, + bus, devfn, where, &data); + + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int lm2e_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data = 0; + int ret; + + if (size == 4) + data = val; + else { + ret = lm2e_pci_config_access(PCI_ACCESS_READ, + bus, devfn, where, &data); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + } + + ret = lm2e_pci_config_access(PCI_ACCESS_WRITE, + bus, devfn, where, &data); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops loongson2e_pci_pci_ops = { + .read = lm2e_pci_pcibios_read, + .write = lm2e_pci_pcibios_write +}; diff --git a/include/asm-mips/mach-lemote/bonito.h b/include/asm-mips/mach-lemote/bonito.h new file mode 100644 index 0000000..83f7ac3 --- /dev/null +++ b/include/asm-mips/mach-lemote/bonito.h @@ -0,0 +1,381 @@ +/* + * Based on Algorithmics header + */ + +#ifndef _BONITO_H +#define _BONITI_H + +#ifdef __ASSEMBLER__ + +/* offsets from base register */ +#define BONITO(x) (x) + +#else /* !__ASSEMBLER */ + +/* offsets from base pointer */ +#define BONITO(x) *(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)) + +#endif /* __ASSEMBLER__ */ + +#define BONITO_BOOT_BASE 0x1fc00000 +#define BONITO_BOOT_SIZE 0x00100000 +#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) +#define BONITO_FLASH_BASE 0x1c000000 +#define BONITO_FLASH_SIZE 0x03000000 +#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) +#define BONITO_SOCKET_BASE 0x1f800000 +#define BONITO_SOCKET_SIZE 0x00400000 +#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) +#define BONITO_REG_BASE 0x1fe00000 +#define BONITO_REG_SIZE 0x00040000 +#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) +#define BONITO_DEV_BASE 0x1ff00000 +#define BONITO_DEV_SIZE 0x00100000 +#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) +#define BONITO_PCILO_BASE 0x10000000 +#define BONITO_PCILO_SIZE 0x0c000000 +#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) +#define BONITO_PCILO0_BASE 0x10000000 +#define BONITO_PCILO1_BASE 0x14000000 +#define BONITO_PCILO2_BASE 0x18000000 +#define BONITO_PCIHI_BASE 0x20000000 +#define BONITO_PCIHI_SIZE 0x20000000 +#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) +#define BONITO_PCIIO_BASE 0x1fd00000 +#define BONITO_PCIIO_SIZE 0x00100000 +#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) +#define BONITO_PCICFG_BASE 0x1fe80000 +#define BONITO_PCICFG_SIZE 0x00080000 +#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) + +/* Bonito Register Bases */ + +#define BONITO_PCICONFIGBASE 0x00 +#define BONITO_REGBASE 0x100 + +/* PCI Configuration Registers */ + +#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) +#define BONITO_PCIDID BONITO_PCI_REG(0x00) +#define BONITO_PCICMD BONITO_PCI_REG(0x04) +#define BONITO_PCICLASS BONITO_PCI_REG(0x08) +#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c) +#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) +#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) +#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) +#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30) +#define BONITO_PCIINT BONITO_PCI_REG(0x3c) + +#define BONITO_PCICMD_PERR 0x80000000 +#define BONITO_PCICMD_SERR 0x40000000 +#define BONITO_PCICMD_MABORT 0x20000000 +#define BONITO_PCICMD_MTABORT 0x10000000 +#define BONITO_PCICMD_TABORT 0x08000000 +#define BONITO_PCICMD_MPERR 0x01000000 +#define BONITO_PCICMD_PERRRESPEN 0x00000040 +#define BONITO_PCICMD_ASTEPEN 0x00000080 +#define BONITO_PCICMD_SERREN 0x00000100 +#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00 +#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8 + +/* 1. Bonito h/w Configuration */ +/* Power on register */ + +#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00) + +#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000 +#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000 +#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000 +#define BONITO_BONPONCFG_CPUBIGEND 0x00004000 +#define BONITO_BONPONCFG_CPUPARITY 0x00002000 +#define BONITO_BONPONCFG_CPUTYPE 0x00000007 +#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0 +#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008 +#define BONITO_BONPONCFG_IS_ARBITER 0x00000010 +#define BONITO_BONPONCFG_ROMBOOT 0x000000c0 +#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6 + +#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) + +#define BONITO_PCIMAP_WINSIZE (1<<26) +#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) +#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) + +/* pcimembaseCfg */ + +#define BONITO_PCIMEMBASECFG_MASK 0xf0000000 +#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f +#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0 +#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0 +#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5 +#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400 +#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800 + +#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000 +#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12 +#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000 +#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17 +#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000 +#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000 + +#define BONITO_PCIMEMBASECFG_ASHIFT 23 +#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff +#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) +#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) + +#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) + +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) +#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) + +#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ + (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ + (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ + ) + +/* PCICmd */ + +#define BONITO_PCICMD_MEMEN 0x00000002 +#define BONITO_PCICMD_MSTREN 0x00000004 + +#define BONITO_IRQ_BASE 32 + +#endif /* !_BONITO_H */ diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h new file mode 100644 index 0000000..9506af4 --- /dev/null +++ b/include/asm-mips/mach-lemote/dma-coherence.h @@ -0,0 +1,43 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Ralf Baechle + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + */ +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H + +struct device; + +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, + size_t size) +{ + return virt_to_phys(addr) | 0x80000000; +} + +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, + struct page *page) +{ + return page_to_phys(page) | 0x80000000; +} + +static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) +{ + return dma_addr & 0x7fffffff; +} + +static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) +{ +} + +static inline int plat_device_is_coherent(struct device *dev) +{ + return 0; +} + +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h new file mode 100644 index 0000000..7850f89 --- /dev/null +++ b/include/asm-mips/mach-lemote/mc146818rtc.h @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * + * RTC routines for PC style attached Dallas chip. + */ +#ifndef __ASM_MACH_GENERIC_MC146818RTC_H +#define __ASM_MACH_GENERIC_MC146818RTC_H + +#include + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ 8 + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + return inb_p(RTC_PORT(1)); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + outb_p(data, RTC_PORT(1)); +} + +#define RTC_ALWAYS_BCD 0 + +#ifndef mc146818_decode_year +#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) +#endif + +#endif /* __ASM_MACH_GENERIC_MC146818RTC_H */ -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:28:40 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:28:47 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:12505 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022644AbXDOP1Y (ORCPT ); Sun, 15 Apr 2007 16:27:24 +0100 Received: (qmail 19425 invoked by uid 511); 15 Apr 2007 15:28:05 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:05 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Subject: lemote-fulong patch update Date: Sun, 15 Apr 2007 23:25:49 +0800 Message-Id: <11766507651736-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14846 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips My boss Fuxin Zhang is busy, and I take the job. It's my first time to submit patch, correct me if I have done anything wrong From tiansm@lemote.com Sun Apr 15 16:29:07 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:29:12 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:12761 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022645AbXDOP1Z (ORCPT ); Sun, 15 Apr 2007 16:27:25 +0100 Received: (qmail 19437 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 3/16] Kconfig update for lemote fulong mini-PC Date: Sun, 15 Apr 2007 23:25:52 +0800 Message-Id: <11766507662638-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507661726-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14847 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- arch/mips/Kconfig | 38 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 38 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 338bfa3..c18a835 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -16,6 +16,27 @@ choice prompt "System type" default SGI_IP22 +config LEMOTE_FULONG + bool "Support for Lemote's fulong mini-PC" + select SYS_HAS_CPU_LOONGSON2 + select DMA_NONCOHERENT + select BOOT_ELF32 + select BOARD_SCACHE + select HW_HAS_PCI + select I8259 + select ISA + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + select GENERIC_HARDIRQS_NO__DO_IRQ + select CPU_HAS_WB + help + Lemote Fulong mini-PC board, which uses Chinese Loongson-2E CPU and a fpga north bridge + + config MIPS_MTX1 bool "4G Systems MTX-1 board" select DMA_NONCOHERENT @@ -1142,6 +1163,13 @@ choice prompt "CPU type" default CPU_R4X00 +config CPU_LOONGSON2 + bool "LOONGSON2" + depends on SYS_HAS_CPU_LOONGSON2 + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -1352,6 +1380,9 @@ config CPU_SB1 endchoice +config SYS_HAS_CPU_LOONGSON2 + bool + config SYS_HAS_CPU_MIPS32_R1 bool @@ -1681,6 +1712,13 @@ config CPU_HAS_SMARTMIPS config CPU_HAS_WB bool +config 64BIT_CONTEXT + bool "Save 64bit integer registers" if CPU_LOONGSON2 && 32BIT + help + Loongson2 CPU is 64bit , when used in 32BIT mode, its integer registers + can still be accessed as 64bit, mainly for multimedia instructions. We must have + all 64bit save/restored to make sure those instructions to get correct result. + # # Vectored interrupt mode is an R2 feature # -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:29:32 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:29:36 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:12249 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022642AbXDOP1Z (ORCPT ); Sun, 15 Apr 2007 16:27:25 +0100 Received: (qmail 19488 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 12/16] cheat for support of more than 256MB memory Date: Sun, 15 Apr 2007 23:26:01 +0800 Message-Id: <1176650766685-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507663039-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <11766507661684-git-send-email-tiansm@lemote.com> <117665076617-git-send-email-tiansm@lemote.com> <1176650766907-git-send-email-tiansm@lemote.com> <11766507663301-git-send-email-tiansm@lemote.com> <11766507663039-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14848 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- arch/mips/kernel/setup.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 4975da0..62ef100 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -509,6 +509,14 @@ static void __init resource_init(void) res->end = end; res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; +#if defined(CONFIG_LEMOTE_FULONG) && defined(CONFIG_64BIT) + /* to keep memory continous, we tell system 0x10000000 - 0x20000000 is reserved + * for memory, in fact it is io region, don't occupy it + * + * SPARSEMEM? + */ + if (boot_mem_map.map[i].type != BOOT_MEM_RESERVED) +#endif request_resource(&iomem_resource, res); /* -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:29:56 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:29:58 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:11737 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022648AbXDOP1Z (ORCPT ); Sun, 15 Apr 2007 16:27:25 +0100 Received: (qmail 19478 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 10/16] make cpu_probe recognize Loongson2 Date: Sun, 15 Apr 2007 23:25:59 +0800 Message-Id: <11766507663301-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <1176650766907-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <11766507661684-git-send-email-tiansm@lemote.com> <117665076617-git-send-email-tiansm@lemote.com> <1176650766907-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14849 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- arch/mips/kernel/cpu-probe.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index ab755ea..c9e3637 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -464,6 +464,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) MIPS_CPU_LLSC; c->tlbsize = 64; break; + case PRID_IMP_LOONGSON2: + c->cputype = CPU_LOONGSON2; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | + MIPS_CPU_FPU | MIPS_CPU_LLSC | + MIPS_CPU_32FPR; + c->tlbsize = 64; + break; } } -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:30:18 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:30:22 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:13017 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022653AbXDOP1Z (ORCPT ); Sun, 15 Apr 2007 16:27:25 +0100 Received: (qmail 19498 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 14/16] tlb handling support for Loongson2 processor Date: Sun, 15 Apr 2007 23:26:03 +0800 Message-Id: <11766507672298-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507661790-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <11766507661684-git-send-email-tiansm@lemote.com> <117665076617-git-send-email-tiansm@lemote.com> <1176650766907-git-send-email-tiansm@lemote.com> <11766507663301-git-send-email-tiansm@lemote.com> <11766507663039-git-send-email-tiansm@lemote.com> <1176650766685-git-send-email-tiansm@lemote.com> <11766507661790-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14850 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- arch/mips/mm/tlb-r4k.c | 23 ++++++++++++++++++++++- arch/mips/mm/tlbex.c | 8 +++++--- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 65160d4..26284bd 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -48,6 +48,22 @@ extern void build_tlb_refill_handler(void); #endif /* CONFIG_MIPS_MT_SMTC */ +#if defined(CONFIG_CPU_LOONGSON2) +/* + * LOONGSON2 has a 4 entry itlb which is a subset of dtlb, + * unfortrunately, itlb is not totally transparent to software. + */ +#define FLUSH_ITLB write_c0_diag(4); + +#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); } + +#else + +#define FLUSH_ITLB +#define FLUSH_ITLB_VM(vma) + +#endif + void local_flush_tlb_all(void) { unsigned long flags; @@ -73,6 +89,7 @@ void local_flush_tlb_all(void) } tlbw_use_hazard(); write_c0_entryhi(old_ctx); + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -136,6 +153,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, } else { drop_mmu_context(mm, cpu); } + FLUSH_ITLB; EXIT_CRITICAL(flags); } } @@ -178,6 +196,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) } else { local_flush_tlb_all(); } + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -210,6 +229,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) finish: write_c0_entryhi(oldpid); + FLUSH_ITLB_VM(vma); EXIT_CRITICAL(flags); } } @@ -241,7 +261,7 @@ void local_flush_tlb_one(unsigned long page) tlbw_use_hazard(); } write_c0_entryhi(oldpid); - + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -293,6 +313,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) else tlb_write_indexed(); tlbw_use_hazard(); + FLUSH_ITLB_VM(vma); EXIT_CRITICAL(flags); } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 492c518..e1a58d9 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -893,6 +893,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, case CPU_4KSC: case CPU_20KC: case CPU_25KF: + case CPU_LOONGSON2: tlbw(p); break; @@ -1276,7 +1277,8 @@ static void __init build_r4000_tlb_refill_handler(void) * need three, with the second nop'ed and the third being * unused. */ -#ifdef CONFIG_32BIT + /* Loongson2 ebase is different than r4k, we have more space */ +#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) if ((p - tlb_handler) > 64) panic("TLB refill handler space exceeded"); #else @@ -1289,7 +1291,7 @@ static void __init build_r4000_tlb_refill_handler(void) /* * Now fold the handler in the TLB refill handler space. */ -#ifdef CONFIG_32BIT +#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) f = final_handler; /* Simplest case, just copy the handler. */ copy_handler(relocs, labels, tlb_handler, p, f); @@ -1336,7 +1338,7 @@ static void __init build_r4000_tlb_refill_handler(void) final_len); f = final_handler; -#ifdef CONFIG_64BIT +#if defined(CONFIG_64BIT) && !defined(CONFIG_CPU_LOONGSON2) if (final_len > 32) final_len = 64; else -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:30:42 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:30:45 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:14041 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022623AbXDOP1Z (ORCPT ); Sun, 15 Apr 2007 16:27:25 +0100 Received: (qmail 19493 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 13/16] define MODULE_PROC_FAMILY for Loongson2 Date: Sun, 15 Apr 2007 23:26:02 +0800 Message-Id: <11766507661790-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <1176650766685-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <11766507661684-git-send-email-tiansm@lemote.com> <117665076617-git-send-email-tiansm@lemote.com> <1176650766907-git-send-email-tiansm@lemote.com> <11766507663301-git-send-email-tiansm@lemote.com> <11766507663039-git-send-email-tiansm@lemote.com> <1176650766685-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14851 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- arch/mips/mm/c-r4k.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 57 insertions(+), 0 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index df04a31..6e6eac6 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -335,6 +335,10 @@ static void r4k_flush_cache_all(void) static inline void local_r4k___flush_cache_all(void * args) { +#if defined(CONFIG_CPU_LOONGSON2) + r4k_blast_scache(); + return; +#endif r4k_blast_dcache(); r4k_blast_icache(); @@ -848,6 +852,26 @@ static void __init probe_pcache(void) c->options |= MIPS_CPU_PREFETCH; break; + case CPU_LOONGSON2: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + if (prid & 0x3) { + c->icache.ways = 4; + } else { + c->icache.ways = 2; + } + c->icache.waybit= 0; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + if (prid & 0x3) { + c->dcache.ways = 4; + } else { + c->dcache.ways = 2; + } + c->dcache.waybit = 0; + break; + default: if (!(config & MIPS_CONF_M)) panic("Don't know how to probe P-caches on this cpu."); @@ -963,6 +987,14 @@ static void __init probe_pcache(void) break; } +#ifdef CONFIG_CPU_LOONGSON2 + /* + * LOONGSON2 has 4 way icache, but when using indexed cache op, + * one op will act on all 4 ways + */ + c->icache.ways = 1; +#endif + printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", icache_size >> 10, cpu_has_vtag_icache ? "virtually tagged" : "physically tagged", @@ -1036,6 +1068,25 @@ static int __init probe_scache(void) return 1; } +#if defined(CONFIG_CPU_LOONGSON2) +static void __init loongson2_sc_init(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + scache_size = 512*1024; + c->scache.linesz = 32; + c->scache.ways = 4; + c->scache.waybit = 0; + c->scache.waysize = scache_size / (c->scache.ways); + c->scache.sets = scache_size /(c->scache.linesz * c->scache.ways); + printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", + scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); + + c->options |= MIPS_CPU_INCLUSIVE_CACHES; + return; +} +#endif + extern int r5k_sc_init(void); extern int rm7k_sc_init(void); extern int mips_sc_init(void); @@ -1085,6 +1136,12 @@ static void __init setup_scache(void) #endif return; +#if defined(CONFIG_CPU_LOONGSON2) + case CPU_LOONGSON2: + loongson2_sc_init(); + return; +#endif + default: if (c->isa_level == MIPS_CPU_ISA_M32R1 || c->isa_level == MIPS_CPU_ISA_M32R2 || -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:31:05 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:31:07 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:14297 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022651AbXDOP1Z (ORCPT ); Sun, 15 Apr 2007 16:27:25 +0100 Received: (qmail 19463 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 7/16] add Loongson processor definitions Date: Sun, 15 Apr 2007 23:25:56 +0800 Message-Id: <11766507661684-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507662650-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14852 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- include/asm-mips/cpu.h | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index d38fdbf..d289359 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -89,6 +89,8 @@ #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 +#define PRID_IMP_LOONGSON1 0x4200 +#define PRID_IMP_LOONGSON2 0x6300 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -200,7 +202,10 @@ #define CPU_SB1A 62 #define CPU_74K 63 #define CPU_R14000 64 -#define CPU_LAST 64 +#define CPU_LOONGSON1 65 +#define CPU_LOONGSON2 66 + +#define CPU_LAST 66 /* * ISA Level encodings -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:31:27 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:31:30 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:13785 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022663AbXDOP11 (ORCPT ); Sun, 15 Apr 2007 16:27:27 +0100 Received: (qmail 19442 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 4/16] TO_PHYS_MASK for loongson2 Date: Sun, 15 Apr 2007 23:25:53 +0800 Message-Id: <11766507661133-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507662638-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14853 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- include/asm-mips/addrspace.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 964c5ed..a4d9a07 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -145,7 +145,7 @@ #define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ #endif -#if defined (CONFIG_CPU_R10000) +#if defined (CONFIG_CPU_R10000) || defined (CONFIG_CPU_LOONGSON2) #define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ #endif -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:31:50 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:31:52 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:13273 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022684AbXDOP1a (ORCPT ); Sun, 15 Apr 2007 16:27:30 +0100 Received: (qmail 19508 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 16/16] alsa sound support for mips Date: Sun, 15 Apr 2007 23:26:05 +0800 Message-Id: <11766507674145-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507672043-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <11766507661684-git-send-email-tiansm@lemote.com> <117665076617-git-send-email-tiansm@lemote.com> <1176650766907-git-send-email-tiansm@lemote.com> <11766507663301-git-send-email-tiansm@lemote.com> <11766507663039-git-send-email-tiansm@lemote.com> <1176650766685-git-send-email-tiansm@lemote.com> <11766507661790-git-send-email-tiansm@lemote.com> <11766507672298-git-send-email-tiansm@lemote.com> <11766507672043-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14854 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- sound/core/pcm_native.c | 10 ++++++++++ sound/core/sgbuf.c | 9 +++++++++ 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index 3e276fc..9005bac 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -3145,7 +3145,11 @@ static struct page *snd_pcm_mmap_data_nopage(struct vm_area_struct *area, return NOPAGE_OOM; /* XXX: is this really due to OOM? */ } else { vaddr = runtime->dma_area + offset; +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) + page = virt_to_page(CAC_ADDR(vaddr)); +#else page = virt_to_page(vaddr); +#endif } get_page(page); if (type) @@ -3261,6 +3265,12 @@ static int snd_pcm_mmap(struct file *file, struct vm_area_struct *area) substream = pcm_file->substream; snd_assert(substream != NULL, return -ENXIO); +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) + /* all mmap using uncached mode */ + area->vm_page_prot = pgprot_noncached(area->vm_page_prot); + area->vm_flags |= ( VM_RESERVED | VM_IO); +#endif + offset = area->vm_pgoff << PAGE_SHIFT; switch (offset) { case SNDRV_PCM_MMAP_OFFSET_STATUS: diff --git a/sound/core/sgbuf.c b/sound/core/sgbuf.c index cefd228..535f0bc 100644 --- a/sound/core/sgbuf.c +++ b/sound/core/sgbuf.c @@ -91,12 +91,21 @@ void *snd_malloc_sgbuf_pages(struct device *device, } sgbuf->table[i].buf = tmpb.area; sgbuf->table[i].addr = tmpb.addr; +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) + sgbuf->page_table[i] = virt_to_page(CAC_ADDR(tmpb.area)); +#else sgbuf->page_table[i] = virt_to_page(tmpb.area); +#endif sgbuf->pages++; } sgbuf->size = size; +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) + /* maybe we should use uncached accelerated mode */ + dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP | VM_IO, pgprot_noncached(PAGE_KERNEL)); +#else dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP, PAGE_KERNEL); +#endif if (! dmab->area) goto _failed; return dmab->area; -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:32:12 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:32:15 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:13529 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022709AbXDOP1i (ORCPT ); Sun, 15 Apr 2007 16:27:38 +0100 Received: (qmail 19458 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 6/16] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 Date: Sun, 15 Apr 2007 23:25:55 +0800 Message-Id: <11766507662650-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <11766507661526-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14855 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- include/asm-mips/cacheops.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index c4a1ec3..df7f2de 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h @@ -20,7 +20,11 @@ #define Index_Load_Tag_D 0x05 #define Index_Store_Tag_I 0x08 #define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else #define Hit_Invalidate_I 0x10 +#endif #define Hit_Invalidate_D 0x11 #define Hit_Writeback_Inv_D 0x15 -- 1.4.4.1 From tiansm@lemote.com Sun Apr 15 16:32:35 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 16:32:37 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:11993 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022738AbXDOP2A (ORCPT ); Sun, 15 Apr 2007 16:28:00 +0100 Received: (qmail 19472 invoked by uid 511); 15 Apr 2007 15:28:06 -0000 Received: from unknown (HELO localhost.localdomain) (192.168.2.197) by lemote.com with SMTP; 15 Apr 2007 15:28:06 -0000 From: tiansm@lemote.com To: linux-mips@linux-mips.org Cc: Fuxin Zhang Subject: [PATCH 9/16] add serial port definition for lemote fulong Date: Sun, 15 Apr 2007 23:25:58 +0800 Message-Id: <1176650766907-git-send-email-tiansm@lemote.com> X-Mailer: git-send-email 1.4.4.1 In-Reply-To: <117665076617-git-send-email-tiansm@lemote.com> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <11766507661684-git-send-email-tiansm@lemote.com> <117665076617-git-send-email-tiansm@lemote.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14856 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips From: Fuxin Zhang Signed-off-by: Fuxin Zhang --- include/asm-mips/serial.h | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index d7a6513..0f78438 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h @@ -204,6 +204,12 @@ #define IP32_SERIAL_PORT_DEFNS #endif /* CONFIG_SGI_IP32 */ +#if defined(CONFIG_LEMOTE_FULONG) +#define LEMOTE_FULONG_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ +#endif + #define SERIAL_PORT_DFNS \ DDB5477_SERIAL_PORT_DEFNS \ EV64120_SERIAL_PORT_DEFNS \ @@ -213,6 +219,7 @@ MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS + MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ + LEMOTE_FULONG_SERIAL_PORT_DEFNS #endif /* _ASM_SERIAL_H */ -- 1.4.4.1 From ths@networkno.de Sun Apr 15 23:31:51 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Apr 2007 23:31:53 +0100 (BST) Received: from phoenix.bawue.net ([193.7.176.60]:46727 "EHLO mail.bawue.net") by ftp.linux-mips.org with ESMTP id S20022957AbXDOWbv (ORCPT ); Sun, 15 Apr 2007 23:31:51 +0100 Received: from lagash (88-106-169-123.dynamic.dsl.as9105.com [88.106.169.123]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bawue.net (Postfix) with ESMTP id D4D7EBBCA3; Mon, 16 Apr 2007 00:28:12 +0200 (CEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1HdDDD-0000Nx-8U; Sun, 15 Apr 2007 23:28:47 +0100 Date: Sun, 15 Apr 2007 23:28:47 +0100 To: tiansm@lemote.com Cc: linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC Message-ID: <20070415222847.GA1402@networkno.de> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <11766507661726-git-send-email-tiansm@lemote.com> User-Agent: Mutt/1.5.13 (2006-08-11) From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14857 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips tiansm@lemote.com wrote: [snip] > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index 92bca6a..2a6742d 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -118,6 +118,7 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap > cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap > cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap > cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap > +cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible, so r5000 / r8000 / r10000 would be better choices. Thiemo From yoichi_yuasa@tripeaks.co.jp Mon Apr 16 06:09:15 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 06:09:19 +0100 (BST) Received: from mo32.po.2iij.net ([210.128.50.17]:56136 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20021898AbXDPFJP (ORCPT ); Mon, 16 Apr 2007 06:09:15 +0100 Received: by mo.po.2iij.net (mo32) id l3G59BQe047736; Mon, 16 Apr 2007 14:09:11 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox33) id l3G59A97089571 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 16 Apr 2007 14:09:10 +0900 (JST) Date: Mon, 16 Apr 2007 14:09:10 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH] remove double config entries in drivers/char/Kconfig Message-Id: <20070416140910.47937dcf.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14858 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has removed double config entries in drivers/char/Kconfig. This problem is only in linux-mips.org tree. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/char/Kconfig mips/drivers/char/Kconfig --- mips-orig/drivers/char/Kconfig 2007-04-14 23:23:32.671598000 +0900 +++ mips/drivers/char/Kconfig 2007-04-15 00:35:22.059197250 +0900 @@ -396,41 +396,6 @@ config SERIAL_DEC kernel: saying N will just cause the configurator to skip all the questions about DECstation serial ports. - If unsure, say Y. - -config SERIAL_DEC_CONSOLE - bool "Support for console on a DECstation serial port" - depends on SERIAL_DEC - default y - help - If you say Y here, it will be possible to use a serial port as the - system console (the system console is the device which receives all - kernel messages and warnings and which allows logins in single user - mode). Note that the firmware uses ttyS0 as the serial console on - the Maxine and ttyS2 on the others. - - If unsure, say Y. - -config ZS - bool "Z85C30 Serial Support" - depends on SERIAL_DEC - default y - help - Documentation on the Zilog 85C350 serial communications controller - is downloadable at . - -config SERIAL_DEC - bool "DECstation serial support" - depends on MACH_DECSTATION - default y - help - This selects whether you want to be asked about drivers for - DECstation serial ports. - - Note that the answer to this question won't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about DECstation serial ports. - config SERIAL_DEC_CONSOLE bool "Support for console on a DECstation serial port" depends on SERIAL_DEC From xfdbse@163.com Mon Apr 16 07:12:05 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 07:12:07 +0100 (BST) Received: from m12-11.163.com ([220.181.12.11]:32714 "HELO m12-11.163.com") by ftp.linux-mips.org with SMTP id S20022244AbXDPGMF (ORCPT ); Mon, 16 Apr 2007 07:12:05 +0100 Received: from 10.0.0.22 (unknown [222.209.176.237]) by smtp12 (Coremail) with SMTP id wKjAC7CrWwJ2EyNGIk0pMg==.62120S2; Mon, 16 Apr 2007 14:11:05 +0800 (CST) From: xfwolf Organization: 30kt To: linux-mips@linux-mips.org Date: Mon, 16 Apr 2007 14:10:56 +0800 User-Agent: KMail/1.5 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200704161410.56670.xfdbse@163.com> X-Coremail-Antispam: 1U3Yxn0WfASr-VFAUDIcSsGvfJ-Yx02cVAKzwAv7VC0I7IYx2 IY67AKxVWUJVWUGwCF72vE52k0Y41lYx0Ex4A2jsIE14v26r1j6r4UMxkIecxEwVAFwVW8 AwAFF20E14v26r1j6r4UM7kC6x804xWl1IIY67AEw4v_Jr0_Jr4l5I8CrVACY4xI64kE6c 02F40Ex7xfM7k0a2IF6F4Un29KB7ZKAUJUUUUUnxnvy29KBjDU0xZFpf9x07jt739UUUUU 129KBjDU= Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14859 Subject: (no subject) X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: xfdbse@163.com Precedence: bulk X-list: linux-mips From tiansm@lemote.com Mon Apr 16 08:38:57 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 08:38:58 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:6892 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022449AbXDPHi5 (ORCPT ); Mon, 16 Apr 2007 08:38:57 +0100 Received: (qmail 4170 invoked by uid 511); 16 Apr 2007 07:39:49 -0000 Received: from unknown (HELO ?192.168.2.197?) (192.168.2.197) by lemote.com with SMTP; 16 Apr 2007 07:39:49 -0000 Message-ID: <462327C3.4020905@lemote.com> Date: Mon, 16 Apr 2007 15:37:39 +0800 From: Tian User-Agent: Icedove 1.5.0.8 (X11/20061116) MIME-Version: 1.0 To: Thiemo Seufer CC: linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <20070415222847.GA1402@networkno.de> In-Reply-To: <20070415222847.GA1402@networkno.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14860 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tiansm@lemote.com Precedence: bulk X-list: linux-mips Thiemo Seufer wrote: > tiansm@lemote.com wrote: > [snip] > >> diff --git a/arch/mips/Makefile b/arch/mips/Makefile >> index 92bca6a..2a6742d 100644 >> --- a/arch/mips/Makefile >> +++ b/arch/mips/Makefile >> @@ -118,6 +118,7 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap >> cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap >> cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap >> cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap >> +cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap >> > > I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible, > so r5000 / r8000 / r10000 would be better choices. > > > Thiemo > > I check the datasheet I have and i don't see loongson2e has implemented mips iv instructions. Songmao From ralf@linux-mips.org Mon Apr 16 09:15:49 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 09:15:51 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:53633 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20022587AbXDPIPt (ORCPT ); Mon, 16 Apr 2007 09:15:49 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3G8FOec026635; Mon, 16 Apr 2007 10:15:25 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3G8FLPj026634; Mon, 16 Apr 2007 09:15:21 +0100 Date: Mon, 16 Apr 2007 09:15:21 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH] remove double config entries in drivers/char/Kconfig Message-ID: <20070416081521.GA26440@linux-mips.org> References: <20070416140910.47937dcf.yoichi_yuasa@tripeaks.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070416140910.47937dcf.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14861 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 16, 2007 at 02:09:10PM +0900, Yoichi Yuasa wrote: > This patch has removed double config entries in drivers/char/Kconfig. > This problem is only in linux-mips.org tree. Thanks, applied. Ralf From fxzhang@ict.ac.cn Mon Apr 16 09:49:52 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 09:49:53 +0100 (BST) Received: from webmail.ict.ac.cn ([159.226.39.7]:27834 "EHLO ict.ac.cn") by ftp.linux-mips.org with ESMTP id S20022616AbXDPItw (ORCPT ); Mon, 16 Apr 2007 09:49:52 +0100 Received: (qmail 10017 invoked by uid 507); 16 Apr 2007 16:52:46 +0800 Received: from unknown (HELO ?192.168.1.63?) (fxzhang@222.92.8.142) by ict.ac.cn with SMTP; 16 Apr 2007 16:52:46 +0800 Message-ID: <46233872.7010206@ict.ac.cn> Date: Mon, 16 Apr 2007 16:48:50 +0800 From: Fuxin Zhang User-Agent: Thunderbird 1.5.0.10 (Windows/20070221) MIME-Version: 1.0 To: Thiemo Seufer CC: tiansm@lemote.com, linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <20070415222847.GA1402@networkno.de> In-Reply-To: <20070415222847.GA1402@networkno.de> X-Enigmail-Version: 0.93.0.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14862 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fxzhang@ict.ac.cn Precedence: bulk X-list: linux-mips >> +cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap > > I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible, > so r5000 / r8000 / r10000 would be better choices. Presently Loongson-2E is nearly MIPS III compatible(with some self-defined extensions), next version will be mips64 release2 compatible. -march=r4600 is inherited from loongson-1, -march=mips3 might be a better choice. > > > Thiemo > > > > From zhangfx@lemote.com Mon Apr 16 09:50:15 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 09:50:18 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:33260 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20022625AbXDPIuP (ORCPT ); Mon, 16 Apr 2007 09:50:15 +0100 Received: (qmail 5338 invoked by uid 511); 16 Apr 2007 08:51:58 -0000 Received: from unknown (HELO ?192.168.1.63?) (222.92.8.142) by lemote.com with SMTP; 16 Apr 2007 08:51:58 -0000 Message-ID: <4623387F.3070905@lemote.com> Date: Mon, 16 Apr 2007 16:49:03 +0800 From: Zhang Fuxin User-Agent: Thunderbird 1.5.0.10 (Windows/20070221) MIME-Version: 1.0 To: Thiemo Seufer CC: tiansm@lemote.com, linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <20070415222847.GA1402@networkno.de> In-Reply-To: <20070415222847.GA1402@networkno.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14863 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips >> +cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap > > I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible, > so r5000 / r8000 / r10000 would be better choices. Presently Loongson-2E is nearly MIPS III compatible(with some self-defined extensions), next version will be mips64 release2 compatible. -march=r4600 is inherited from loongson-1, -march=mips3 might be a better choice. > > > Thiemo > > > > From Fabrice.Aeschbacher@siemens.com Mon Apr 16 10:01:30 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 10:01:36 +0100 (BST) Received: from lizzard.sbs.de ([194.138.37.39]:15941 "EHLO lizzard.sbs.de") by ftp.linux-mips.org with ESMTP id S20022621AbXDPJBa (ORCPT ); Mon, 16 Apr 2007 10:01:30 +0100 Received: from mail2.sbs.de (localhost [127.0.0.1]) by lizzard.sbs.de (8.12.6/8.12.6) with ESMTP id l3G91H45019473 for ; Mon, 16 Apr 2007 11:01:18 +0200 Received: from fthw9xoa.ww002.siemens.net (fthw9xoa.ww002.siemens.net [157.163.133.201]) by mail2.sbs.de (8.12.6/8.12.6) with ESMTP id l3G91HNo016360 for ; Mon, 16 Apr 2007 11:01:17 +0200 Received: from stgw002a.ww002.siemens.net ([141.73.158.150]) by fthw9xoa.ww002.siemens.net with Microsoft SMTPSVC(6.0.3790.1830); Mon, 16 Apr 2007 11:01:17 +0200 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----_=_NextPart_001_01C78005.C4681642" Subject: [PATCH] building compressed kernel (au1000) Date: Mon, 16 Apr 2007 11:01:48 +0200 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH] building compressed kernel (au1000) Thread-Index: AceABd3moMRpkQ1UQiuIV4mRVCVvzg== From: "Aeschbacher, Fabrice" To: X-OriginalArrivalTime: 16 Apr 2007 09:01:17.0272 (UTC) FILETIME=[CB062D80:01C78005] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14864 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Fabrice.Aeschbacher@siemens.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. ------_=_NextPart_001_01C78005.C4681642 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi, Please find enclosed a patch (against 2.6.20.4) for building a compressed kernel image (zImage) for mips / au1000. This patch was only adapted from http://www.freewrt.org/trac/browser/trunk/freewrt/target/linux/au1000-2. 6/patches/003-zImage.patch?rev=3D1 Best regards, Fabrice Aeschbacher ------_=_NextPart_001_01C78005.C4681642 Content-Type: application/octet-stream; name="patch-2.6.20.4-compressed" Content-Transfer-Encoding: base64 Content-Description: patch-2.6.20.4-compressed Content-Disposition: attachment; filename="patch-2.6.20.4-compressed" ZGlmZiAtdXJiTiBsaW51eC0yLjYuMjAuNC1vcmlnL2FyY2gvbWlwcy9ib290L2NvbXByZXNzZWQv YXUxeHh4L2hlYWQuUyBsaW51eC0yLjYuMjAuNC9hcmNoL21pcHMvYm9vdC9jb21wcmVzc2VkL2F1 MXh4eC9oZWFkLlMKLS0tIGxpbnV4LTIuNi4yMC40LW9yaWcvYXJjaC9taXBzL2Jvb3QvY29tcHJl c3NlZC9hdTF4eHgvaGVhZC5TCTE5NzAtMDEtMDEgMDE6MDA6MDAuMDAwMDAwMDAwICswMTAwCisr KyBsaW51eC0yLjYuMjAuNC9hcmNoL21pcHMvYm9vdC9jb21wcmVzc2VkL2F1MXh4eC9oZWFkLlMJ MjAwNy0wNC0xMSAwOTo1OTo0OC4wMDAwMDAwMDAgKzAyMDAKQEAgLTAsMCArMSwxMTkgQEAKKy8q IAorICogYXJjaC9taXBzL2tlcm5lbC9oZWFkLlMgCisgKiAKKyAqIFRoaXMgZmlsZSBpcyBzdWJq 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requested) by mail.bawue.net (Postfix) with ESMTP id 4342EB8AAB; Mon, 16 Apr 2007 14:43:48 +0200 (CEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1HdQZC-0005u9-I5; Mon, 16 Apr 2007 13:44:22 +0100 Date: Mon, 16 Apr 2007 13:44:22 +0100 From: Thiemo Seufer To: Zhang Fuxin Cc: tiansm@lemote.com, linux-mips@linux-mips.org Subject: Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC Message-ID: <20070416124422.GB1402@networkno.de> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <20070415222847.GA1402@networkno.de> <4623387F.3070905@lemote.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4623387F.3070905@lemote.com> User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14865 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Zhang Fuxin wrote: > >> +cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap > > > > I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible, > > so r5000 / r8000 / r10000 would be better choices. > > Presently Loongson-2E is nearly MIPS III compatible(with some > self-defined extensions), next version will be mips64 release2 compatible. I see. > -march=r4600 is inherited from loongson-1, -march=mips3 might be a > better choice. Maybe. The 'mips3' maps to -march=r4000, it would assume more memory latency and a slower integer divider then -march=r4600. Thiemo From ralf@linux-mips.org Mon Apr 16 14:55:22 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 14:55:26 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:44237 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20023275AbXDPNzW (ORCPT ); Mon, 16 Apr 2007 14:55:22 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3GDlAh9030592; Mon, 16 Apr 2007 14:52:30 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3GDlAtI030591; Mon, 16 Apr 2007 14:47:10 +0100 Date: Mon, 16 Apr 2007 14:47:10 +0100 From: Ralf Baechle To: "Aeschbacher, Fabrice" Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] building compressed kernel (au1000) Message-ID: <20070416134710.GA28217@linux-mips.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14866 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 16, 2007 at 11:01:48AM +0200, Aeschbacher, Fabrice wrote: Fabrice, > Please find enclosed a patch (against 2.6.20.4) for building a > compressed kernel image (zImage) for mips / au1000. I see several #include but that file does no longer exist in 2.6.20 which either means that code is dead code or has not been compile tested ... > This patch was only adapted from > http://www.freewrt.org/trac/browser/trunk/freewrt/target/linux/au1000-2. > 6/patches/003-zImage.patch?rev=1 Signed-off-by: ? Ralf From ralf@linux-mips.org Mon Apr 16 15:01:42 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 15:01:44 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:43746 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20023278AbXDPOBm (ORCPT ); Mon, 16 Apr 2007 15:01:42 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3GE1ejI031069; Mon, 16 Apr 2007 15:01:40 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3GE1ck4031068; Mon, 16 Apr 2007 15:01:38 +0100 Date: Mon, 16 Apr 2007 15:01:38 +0100 From: Ralf Baechle To: Thiemo Seufer Cc: Zhang Fuxin , tiansm@lemote.com, linux-mips@linux-mips.org Subject: Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC Message-ID: <20070416140137.GB28217@linux-mips.org> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <20070415222847.GA1402@networkno.de> <4623387F.3070905@lemote.com> <20070416124422.GB1402@networkno.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070416124422.GB1402@networkno.de> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14867 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 16, 2007 at 01:44:22PM +0100, Thiemo Seufer wrote: > Zhang Fuxin wrote: > > >> +cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap > > > > > > I wonder why this is r4600. I heard the Loongson2 is MIPS IV compatible, > > > so r5000 / r8000 / r10000 would be better choices. > > > > Presently Loongson-2E is nearly MIPS III compatible(with some > > self-defined extensions), next version will be mips64 release2 compatible. > > I see. > > > -march=r4600 is inherited from loongson-1, -march=mips3 might be a > > better choice. > > Maybe. The 'mips3' maps to -march=r4000, it would assume more memory > latency and a slower integer divider then -march=r4600. I don't really have an issue with that since I see it as a temporary solution until gcc and binutils know about Loongson 2 specifics. Given the bit I know about the Loognson 2 processor architecture I would not expect a significant performance boost from trying different values for -march with current toolchains. Ralf From anemo@mba.ocn.ne.jp Mon Apr 16 15:21:06 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 15:21:08 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:34271 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20023257AbXDPOVG (ORCPT ); Mon, 16 Apr 2007 15:21:06 +0100 Received: from localhost (p1162-ipad34funabasi.chiba.ocn.ne.jp [124.85.58.162]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id C9EDEA5DE; Mon, 16 Apr 2007 23:19:44 +0900 (JST) Date: Mon, 16 Apr 2007 23:19:44 +0900 (JST) Message-Id: <20070416.231944.41198415.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Retry {save,restore}_fp_context if failed in atomic context. From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14868 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips The save_fp_context()/restore_fp_context() might sleep on accessing user stack and therefore might lose FPU ownership in middle of them. If these function failed due to "in_atomic" test in do_page_fault, touch the sigcontext area in non-atomic context and retry these save/restore operation. This is a replacement of a (broken) fix which was titled "Allow CpU exception in kernel partially". Signed-off-by: Atsushi Nemoto --- This patch depends on: > Subject: Re: [PATCH] Disallow CpU exception in kernel again. > Message-Id: <20070414.023726.128617751.anemo@mba.ocn.ne.jp> arch/mips/kernel/signal-common.h | 9 ++++++ arch/mips/kernel/signal.c | 52 +++++++++++++++++++++++++++++++------ arch/mips/kernel/signal32.c | 52 +++++++++++++++++++++++++++++++------ include/asm-mips/fpu.h | 9 +++++- 4 files changed, 102 insertions(+), 20 deletions(-) diff --git a/arch/mips/kernel/signal-common.h b/arch/mips/kernel/signal-common.h index 297dfcb..c0faabd 100644 --- a/arch/mips/kernel/signal-common.h +++ b/arch/mips/kernel/signal-common.h @@ -34,4 +34,13 @@ extern int install_sigtramp(unsigned int /* Check and clear pending FPU exceptions in saved CSR */ extern int fpcsr_pending(unsigned int __user *fpcsr); +/* Make sure we will not lose FPU ownership */ +#ifdef CONFIG_PREEMPT +#define lock_fpu_owner() preempt_disable() +#define unlock_fpu_owner() preempt_enable() +#else +#define lock_fpu_owner() pagefault_disable() +#define unlock_fpu_owner() pagefault_enable() +#endif + #endif /* __SIGNAL_COMMON_H */ diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index fa58119..07d6730 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -27,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -78,6 +78,46 @@ struct rt_sigframe { /* * Helper routines */ +static int protected_save_fp_context(struct sigcontext __user *sc) +{ + int err; + while (1) { + lock_fpu_owner(); + own_fpu_inatomic(1); + err = save_fp_context(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __put_user(0, &sc->sc_fpregs[0]) | + __put_user(0, &sc->sc_fpregs[31]) | + __put_user(0, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + +static int protected_restore_fp_context(struct sigcontext __user *sc) +{ + int err, tmp; + while (1) { + lock_fpu_owner(); + own_fpu_inatomic(0); + err = restore_fp_context(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __get_user(tmp, &sc->sc_fpregs[0]) | + __get_user(tmp, &sc->sc_fpregs[31]) | + __get_user(tmp, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { int err = 0; @@ -113,10 +153,7 @@ int setup_sigcontext(struct pt_regs *reg * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ - preempt_disable(); - own_fpu(1); - err |= save_fp_context(sc); - preempt_enable(); + err |= protected_save_fp_context(sc); } return err; } @@ -148,10 +185,7 @@ check_and_restore_fp_context(struct sigc err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; - preempt_disable(); - own_fpu(0); - err |= restore_fp_context(sc); - preempt_enable(); + err |= protected_restore_fp_context(sc); return err ?: sig; } diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 53a337c..b9a0144 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -29,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -176,6 +176,46 @@ struct rt_sigframe32 { /* * sigcontext handlers */ +static int protected_save_fp_context32(struct sigcontext32 __user *sc) +{ + int err; + while (1) { + lock_fpu_owner(); + own_fpu_inatomic(1); + err = save_fp_context32(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __put_user(0, &sc->sc_fpregs[0]) | + __put_user(0, &sc->sc_fpregs[31]) | + __put_user(0, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + +static int protected_restore_fp_context32(struct sigcontext32 __user *sc) +{ + int err, tmp; + while (1) { + lock_fpu_owner(); + own_fpu_inatomic(0); + err = restore_fp_context32(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __get_user(tmp, &sc->sc_fpregs[0]) | + __get_user(tmp, &sc->sc_fpregs[31]) | + __get_user(tmp, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + static int setup_sigcontext32(struct pt_regs *regs, struct sigcontext32 __user *sc) { @@ -209,10 +249,7 @@ static int setup_sigcontext32(struct pt_ * Save FPU state to signal context. Signal handler * will "inherit" current FPU state. */ - preempt_disable(); - own_fpu(1); - err |= save_fp_context32(sc); - preempt_enable(); + err |= protected_save_fp_context32(sc); } return err; } @@ -225,10 +262,7 @@ check_and_restore_fp_context32(struct si err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; - preempt_disable(); - own_fpu(0); - err |= restore_fp_context32(sc); - preempt_enable(); + err |= protected_restore_fp_context32(sc); return err ?: sig; } diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 71436f9..b414a7d 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -100,14 +100,19 @@ static inline void __own_fpu(void) set_thread_flag(TIF_USEDFPU); } -static inline void own_fpu(int restore) +static inline void own_fpu_inatomic(int restore) { - preempt_disable(); if (cpu_has_fpu && !__is_fpu_owner()) { __own_fpu(); if (restore) _restore_fp(current); } +} + +static inline void own_fpu(int restore) +{ + preempt_disable(); + own_fpu_inatomic(restore); preempt_enable(); } From anemo@mba.ocn.ne.jp Mon Apr 16 15:32:40 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 15:32:45 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:6345 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20023302AbXDPOck (ORCPT ); Mon, 16 Apr 2007 15:32:40 +0100 Received: from localhost (p1162-ipad34funabasi.chiba.ocn.ne.jp [124.85.58.162]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 435A0B6D3; Mon, 16 Apr 2007 23:32:36 +0900 (JST) Date: Mon, 16 Apr 2007 23:32:35 +0900 (JST) Message-Id: <20070416.233235.75185596.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] Retry {save,restore}_fp_context if failed in atomic context. From: Atsushi Nemoto In-Reply-To: <20070416.231944.41198415.anemo@mba.ocn.ne.jp> References: <20070416.231944.41198415.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14869 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Mon, 16 Apr 2007 23:19:44 +0900 (JST), Atsushi Nemoto wrote: > The save_fp_context()/restore_fp_context() might sleep on accessing > user stack and therefore might lose FPU ownership in middle of them. > > If these function failed due to "in_atomic" test in do_page_fault, > touch the sigcontext area in non-atomic context and retry these > save/restore operation. > > This is a replacement of a (broken) fix which was titled "Allow CpU > exception in kernel partially". > > Signed-off-by: Atsushi Nemoto And this is for 2.6.20-stable. Signed-off-by: Atsushi Nemoto --- This patch depends on: > Subject: Re: [PATCH] Disallow CpU exception in kernel again. > Message-Id: <20070414.024450.07456615.anemo@mba.ocn.ne.jp> arch/mips/kernel/signal-common.h | 59 +++++++++++++++++++++++++++++++----- arch/mips/kernel/signal.c | 2 +- arch/mips/kernel/signal32.c | 61 ++++++++++++++++++++++++++++++++----- arch/mips/kernel/signal_n32.c | 2 +- include/asm-mips/fpu.h | 9 ++++- 5 files changed, 112 insertions(+), 21 deletions(-) diff --git a/arch/mips/kernel/signal-common.h b/arch/mips/kernel/signal-common.h index b625e9c..6e479f6 100644 --- a/arch/mips/kernel/signal-common.h +++ b/arch/mips/kernel/signal-common.h @@ -9,6 +9,55 @@ */ +/* Make sure we will not lose FPU ownership */ +#ifdef CONFIG_PREEMPT +#define lock_fpu_owner() preempt_disable() +#define unlock_fpu_owner() preempt_enable() +#else +#define lock_fpu_owner() pagefault_disable() +#define unlock_fpu_owner() pagefault_enable() +#endif + +static inline int protected_save_fp_context(struct sigcontext __user *sc) +{ + int err; + while (1) { + lock_fpu_owner(); + own_fpu(1); + err = save_fp_context(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __put_user(0, &sc->sc_fpregs[0]) | + __put_user(0, &sc->sc_fpregs[31]) | + __put_user(0, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + +static inline int protected_restore_fp_context(struct sigcontext __user *sc) +{ + int err, tmp; + while (1) { + lock_fpu_owner(); + own_fpu(0); + err = restore_fp_context(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __get_user(tmp, &sc->sc_fpregs[0]) | + __get_user(tmp, &sc->sc_fpregs[31]) | + __get_user(tmp, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + static inline int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { @@ -51,10 +100,7 @@ setup_sigcontext(struct pt_regs *regs, s * Save FPU state to signal context. Signal handler will "inherit" * current FPU state. */ - preempt_disable(); - own_fpu(1); - err |= save_fp_context(sc); - preempt_enable(); + err |= protected_save_fp_context(sc); out: return err; @@ -71,10 +117,7 @@ check_and_restore_fp_context(struct sigc err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; - preempt_disable(); - own_fpu(0); - err |= restore_fp_context(sc); - preempt_enable(); + err |= protected_restore_fp_context(sc); return err ?: sig; } diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 60960f7..95d9585 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -27,7 +28,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 1a3f541..fee8547 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -29,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -137,6 +137,55 @@ struct ucontext32 { /* Check and clear pending FPU exceptions in saved CSR */ extern int fpcsr_pending(unsigned int __user *fpcsr); +/* Make sure we will not lose FPU ownership */ +#ifdef CONFIG_PREEMPT +#define lock_fpu_owner() preempt_disable() +#define unlock_fpu_owner() preempt_enable() +#else +#define lock_fpu_owner() pagefault_disable() +#define unlock_fpu_owner() pagefault_enable() +#endif + +static int protected_save_fp_context32(struct sigcontext32 __user *sc) +{ + int err; + while (1) { + lock_fpu_owner(); + own_fpu(1); + err = save_fp_context32(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __put_user(0, &sc->sc_fpregs[0]) | + __put_user(0, &sc->sc_fpregs[31]) | + __put_user(0, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + +static int protected_restore_fp_context32(struct sigcontext32 __user *sc) +{ + int err, tmp; + while (1) { + lock_fpu_owner(); + own_fpu(0); + err = restore_fp_context32(sc); /* this might fail */ + unlock_fpu_owner(); + if (likely(!err)) + break; + /* touch the sigcontext and try again */ + err = __get_user(tmp, &sc->sc_fpregs[0]) | + __get_user(tmp, &sc->sc_fpregs[31]) | + __get_user(tmp, &sc->sc_fpc_csr); + if (err) + break; /* really bad sigcontext */ + } + return err; +} + static int check_and_restore_fp_context32(struct sigcontext32 __user *sc) { @@ -145,10 +194,7 @@ check_and_restore_fp_context32(struct si err = sig = fpcsr_pending(&sc->sc_fpc_csr); if (err > 0) err = 0; - preempt_disable(); - own_fpu(0); - err |= restore_fp_context32(sc); - preempt_enable(); + err |= protected_restore_fp_context32(sc); return err ?: sig; } @@ -614,10 +660,7 @@ static inline int setup_sigcontext32(str * Save FPU state to signal context. Signal handler will "inherit" * current FPU state. */ - preempt_disable(); - own_fpu(1); - err |= save_fp_context32(sc); - preempt_enable(); + err |= protected_save_fp_context32(sc); out: return err; diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index 617edd9..2279963 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -28,12 +28,12 @@ #include #include #include +#include #include #include #include #include -#include #include #include #include diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 6b9d1bf..f5cdcaa 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -100,14 +100,19 @@ static inline void __own_fpu(void) set_thread_flag(TIF_USEDFPU); } -static inline void own_fpu(int restore) +static inline void own_fpu_inatomic(int restore) { - preempt_disable(); if (cpu_has_fpu && !__is_fpu_owner()) { __own_fpu(); if (restore) _restore_fp(current); } +} + +static inline void own_fpu(int restore) +{ + preempt_disable(); + own_fpu_inatomic(restore); preempt_enable(); } From freddy@dusktilldawn.nl Mon Apr 16 15:47:59 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 15:48:01 +0100 (BST) Received: from tool.snarl.nl ([82.95.241.19]:7126 "EHLO tool.snarl.nl") by ftp.linux-mips.org with ESMTP id S20023318AbXDPOr7 (ORCPT ); Mon, 16 Apr 2007 15:47:59 +0100 Received: from localhost (tool.local.snarl.nl [127.0.0.1]) by tool.snarl.nl (Postfix) with ESMTP id 7A7865DF8D; Mon, 16 Apr 2007 16:47:53 +0200 (CEST) Received: from tool.snarl.nl ([127.0.0.1]) by localhost (tool.local.snarl.nl [127.0.0.1]) (amavisd-new, port 10024) with LMTP id SeHyvO0jy+0I; Mon, 16 Apr 2007 16:47:53 +0200 (CEST) Received: by tool.snarl.nl (Postfix, from userid 1000) id DB24D5DF3D; Mon, 16 Apr 2007 16:47:52 +0200 (CEST) Date: Mon, 16 Apr 2007 16:47:52 +0200 From: Freddy Spierenburg To: Jaroslav Kysela Cc: Marco Braga , Charles Eidsness , linux-mips@linux-mips.org Subject: Re: Trouble with sound/mips/au1x00.c AC97 driver Message-ID: <20070416144752.GT18693@dusktilldawn.nl> References: <20070307104930.GD25248@dusktilldawn.nl> <45F350E9.3020208@cooper-street.com> <45F5DC73.9060004@cooper-street.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Chn8nxio6L/4biUD" Content-Disposition: inline In-Reply-To: <45F5DC73.9060004@cooper-street.com> X-User-Agent-Feature: All mail clients suck. This one just sucks less. X-GPG-Key: http://snarl.nl/~freddy/keys/freddyPublicKey.gpg User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14870 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: freddy@dusktilldawn.nl Precedence: bulk X-list: linux-mips --Chn8nxio6L/4biUD Content-Type: multipart/mixed; boundary="SSJ6yXlPvEk0CmSI" Content-Disposition: inline --SSJ6yXlPvEk0CmSI Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Jaroslav, Please find attached a patch that fixes some known problems currently part of the au1x00 ALSA audio driver. Signed-off-by: Freddy Spierenburg Below is a small time explanation of why the patch is needed. On Mon, Mar 12, 2007 at 07:04:19PM -0400, Charles Eidsness wrote: > I wonder if the AC'97 Controller has to be up for at least one > frame before issuing the cold reset. Each frame is 20.8us, you > could try setting that delay to 25us instead of 500ms. The 10us delay indeed is not enough. 25us gives way better results. Combining it with... > Sergei on the mailing list had a good suggestion as well. You could try= =20 > replacing every udelay with an au_sync_udelay, and each mdelay with an=20 > au_sync_delay. =2E..Sergei his suggestion, and more importantly... > I think that spin_lock_irqsave stuff might fix the problem that Freddy=20 > has =2E..replacing spin_lock() by spin_lock_irqsave() gives me good results. Still not perfectly, but way better than it was. Using the Python audio-script I've attached to this email I've loaded and unloaded the driver 4033 times and it failed 6 times on me. Failing means one control is missing or a control features the wrong settings. If this happens the Python script tries to load the driver again and in all of my tests succeeds right away. --=20 $ cat ~/.signature Freddy Spierenburg http://freddy.snarl.nl/ GnuPG: 0x7941D1E1=3DC948 5851 26D2 FA5C 39F1 E588 6F17 FD5D 7941 D1E1 $ # Please read http://www.ietf.org/rfc/rfc2015.txt before complain! --SSJ6yXlPvEk0CmSI Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="au1x00.patch" Content-Transfer-Encoding: quoted-printable diff -Naur linux-2.6.20.orig/sound/mips/au1x00.c linux-2.6.20/sound/mips/au= 1x00.c --- linux-2.6.20.orig/sound/mips/au1x00.c 2007-02-04 20:22:45.000000000 +00= 00 +++ linux-2.6.20/sound/mips/au1x00.c 2007-04-16 14:04:39.000000000 +0000 @@ -496,8 +496,9 @@ u32 volatile cmd; u16 volatile data; int i; + unsigned long flags; =20 - spin_lock(&au1000->ac97_lock); + spin_lock_irqsave(&au1000->ac97_lock, flags); /* would rather use the interupt than this polling but it works and I can't get the interupt driven case to work efficiently */ for (i =3D 0; i < 0x5000; i++) @@ -520,7 +521,7 @@ } =20 data =3D au1000->ac97_ioport->cmd & 0xffff; - spin_unlock(&au1000->ac97_lock); + spin_unlock_irqrestore(&au1000->ac97_lock, flags); =20 return data; =20 @@ -533,8 +534,9 @@ struct snd_au1000 *au1000 =3D ac97->private_data; u32 cmd; int i; + unsigned long flags; =20 - spin_lock(&au1000->ac97_lock); + spin_lock_irqsave(&au1000->ac97_lock, flags); /* would rather use the interupt than this polling but it works and I can't get the interupt driven case to work efficiently */ for (i =3D 0; i < 0x5000; i++) @@ -547,7 +549,7 @@ cmd &=3D ~AC97C_READ; cmd |=3D ((u32) val << AC97C_WD_BIT); au1000->ac97_ioport->cmd =3D cmd; - spin_unlock(&au1000->ac97_lock); + spin_unlock_irqrestore(&au1000->ac97_lock, flags); } =20 static int __devinit @@ -577,15 +579,15 @@ =20 /* Initialise Au1000's AC'97 Control Block */ au1000->ac97_ioport->cntrl =3D AC97C_RS | AC97C_CE; - udelay(10); + au_sync_udelay(10); au1000->ac97_ioport->cntrl =3D AC97C_CE; - udelay(10); + au_sync_udelay(25); =20 /* Initialise External CODEC -- cold reset */ au1000->ac97_ioport->config =3D AC97C_RESET; - udelay(10); + au_sync_udelay(10); au1000->ac97_ioport->config =3D 0x0; - mdelay(5); + au_sync_delay(5); =20 /* Initialise AC97 middle-layer */ if ((err =3D snd_ac97_bus(au1000->card, 0, &ops, au1000, &pbus)) < 0) --SSJ6yXlPvEk0CmSI Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename=audio Content-Transfer-Encoding: quoted-printable #!/usr/bin/python # # Nice script to load/unload the audio kernel driver. It checks as much # controls as possible. It does this by comparing the configured values to = the # values restored after loading the driver. It reads the configured values = =66rom # /var/lib/alsa/asound.state and tries to load the driver again if any cont= rol # does not hold it's configured value or is even missing. # # Usage: audio start|stop # # Freddy Spierenburg Mon, 16 Apr 2007 16:39:45 +0= 200 import sys, os, re, string, alsaaudio # This is the class definition for the base control type. All derived contr= ols # share this information. class Control: # The class constructor method. def __init__(self, storage): # Get the name for this control. self.name =3D storage['name'].replace('\'', '') # Initialize the value list. self.value =3D [] # Does this control has more than one value? if int(storage['comment.count']) > 1: # Yes, run through all the values. for index in range(int(storage['comment.count'])): # Save every value in our value list. self.value.append(storage['value.' + str(index)]) else: # No, just store this one value in the list. self.value.append(storage['value']) # A nice debug information method. def show(self): # Show the name for this control. print self.name, ':' # Run through all the values for this control. for v in self.value: # Show every value. print 'value =3D', v =09 # This is the class definition for the boolean control type. class BooleanFactory: def Create(self,storage): return Boolean(storage) class Boolean(Control): # The class constructor method. def __init__(self, storage): # Start the constructor for the base class. Control.__init__(self, storage) # The test method to see if the control is initialized correctly. We test = to see # if the current boolean value is equal to the one configured. def error(self): # Get the real name for the control. All control names should be stripped= from the # named strings, except the one holding a '-' character. control =3D self.name if control.count('-') =3D=3D 0: control =3D control.replace('Playback Switch', '').replace('Switch', '') control =3D control.strip() try: # Get a reference to the control mixer =3D alsaaudio.Mixer(control) # Find the mute state for this control. mute =3D mixer.getmute() # Return true if the current boolean value is not equal to the configure= d value. return not ((mute[0] =3D=3D 0 and self.value[0] =3D=3D 'true') or (mute[= 0] =3D=3D 1 and self.value[0] =3D=3D 'false')) except alsaaudio.ALSAAudioError: # An error probably indicates a missing control. This is bad! return True # This is the class definition for the integer control type. class IntegerFactory: def Create(self,storage): return Integer(storage) class Integer(Control): # The class constructor method. def __init__(self, storage): # Start the constructor for the base class. Control.__init__(self, storage) # An integer type holds a range. Split it into a minimum and # maximum field. field =3D string.split(re.sub("'", '', storage['comment.range']), '-') # Save the minimum value. self.minimum =3D int(field[0]) # Save the maximum value. self.maximum =3D int(field[1]) # A nice debug information method. def show(self): # Show the information for the base class. Control.show(self) # Show the configured minimum and maximum value for the range. print 'minimum =3D', self.minimum, 'maximum =3D', self.maximum # The test method to see if the control is initialized correctly. We test = to see # if the range value is like expected and the current volume setting is li= ke it # is configured. def error(self): # Get the real name for the control. control =3D self.name.replace('Playback Volume', '').replace('Volume', ''= ).strip() try: # Get a reference to the control. mixer =3D alsaaudio.Mixer(control) except alsaaudio.ALSAAudioError: # An error indicates a missing control. This is bad! return True # Find the range for this control. rng =3D mixer.getrange() # Check if the current range value is like expected. rangeOK =3D (rng[0] =3D=3D self.minimum and rng[1] =3D=3D self.maximum) # Find the current volume value. volume =3D mixer.getvolume() # Expect this volume value to be good by default. volumeOK =3D True # Run through the found volume values. for index in range(len(volume)): # We get the percentage volume value from the ALSA layer, but # we need the index value. Calculate the index value from the # percentage. volume[index] =3D round(volume[index] * self.maximum / 100.0) # Is the current volume value not equal to the configured value? if volume[index] !=3D int(self.value[index]): # Yes, unfortunately there is something wrong. Set our flag! volumeOK =3D False # And stop checking right away. We're out of luck anyway! break =09 # Return true if the range or volume is not ok! return not (rangeOK and volumeOK) =09 # This is the class definition for the enumerated control type. class EnumeratedFactory: def Create(self,storage): return Enumerated(storage) class Enumerated(Control): # The class constructor method. def __init__(self, storage): # Start the constructor for the base class. Control.__init__(self, storage) =09 # A nice debug information method. def show(self): # Show only the information for the base class. Control.show(self) # The test method to see if the control is initialized correctly. We test = to # see if the current enumerated type value for the control is equal to the # configured value. def error(self): try: # Get a reference to the control. mixer =3D alsaaudio.Mixer(self.name) # Find the enumerated type for this control. enum =3D mixer.getenum() # Return true if the current enumerated type is not equal to the # configured one. return not (enum[0] =3D=3D self.value[0].replace('\'', '')) except alsaaudio.ALSAAudioError: # An error probably indicates a missing control. This is bad! return True # We do not yet do much with the IEC958 control type. class IEC958Factory: def Create(self,storage): return IEC958(storage) class IEC958(Control): def __init__(self, storage): Control.__init__(self, storage) # The factories is a dictionary of control types we recognize and handle. factories =3D { 'BOOLEAN': BooleanFactory(), 'INTEGER': IntegerFactory(), 'ENUMERATED': EnumeratedFactory(), 'IEC958': IEC958Factory() } # The list of all the controls that should be available. If we need to # check them they hold the value true, false if we choose to ignore them. controlsAvailableList =3D { "'Master Playback Switch'": True, "'Master Playback Volume'": True, "'Headphone Playback Switch'": True, "'Headphone Playback Volume'": True, "'Master Mono Playback Switch'": True, "'Master Mono Playback Volume'": True, "'PC Speaker Playback Switch'": True, "'PC Speaker Playback Volume'": True, "'Phone Playback Switch'": True, "'Phone Playback Volume'": True, "'Mic Playback Switch'": True, "'Mic Playback Volume'": True, "'Mic Boost (+20dB)'": True, "'Line Playback Switch'": True, "'Line Playback Volume'": True, "'CD Playback Switch'": True, "'CD Playback Volume'": True, "'Video Playback Switch'": True, "'Aux Playback Switch'": True, "'PCM Playback Switch'": True, "'PCM Playback Volume'": True, "'Capture Source'": False, "'Capture Switch'": False, "'Capture Volume'": True, "'PCM Out Path & Mute'": True, "'3D Control - Switch'": True, "'Mono Output Select'": True, "'Mic Select'": True, "'3D Control - Center'": True, "'3D Control - Depth'": True, "'IEC958 Playback Con Mask'": False, "'IEC958 Playback Pro Mask'": False, "'IEC958 Playback Default'": False, "'IEC958 Playback Switch'": False, "'IEC958 Playback AC97-SPSA'": False, "'Front Playback Volume'": True, "'Front Playback Switch'": True, "'External Amplifier'": True } # The routine to stop the audio driver. def driverStop(): os.system('/sbin/rmmod snd-au1x00 > /dev/null 2>&1') =09 # The routine to start the audio driver. def driverStart(): # The start of a control block is marked by the next reg-exp. start =3D re.compile('control') # The end of a control block is marked by the next reg-exp. end =3D re.compile('\s+}$') # We only add stuff to our storage when we are inside a control block. process =3D False # Initialize our temporary storage to be empty at the start. storage =3D {} # Initialize our list of controls to be empty at the start.. controls =3D [] # Open the ALSA configuration file. file=3Dopen('/var/lib/alsa/asound.state', 'r') # Process every line read from the file. for line in file.readlines(): # What kind of line is this? if start.search(line): # It marks the start of a control block. Start processing. process =3D True # Clear our temporary storage before we begin. storage.clear() elif end.search(line): # It marks the end of a control block. Stop processing. process =3D False # Is this one of the controls we would like to check? if controlsAvailableList.has_key(storage['name']) and controlsAvailableL= ist[storage['name']]: # Yes! Find out by means of the control type, what kind of object to cr= eate. factory =3D factories[storage['comment.type']] # Add the object type to our list of controls. controls.append(factory.Create(storage)) elif process: # We are in the middle of processing and this line is data we need to # store in our object. First split the line in a name and value pair. The # first space is seen as the separator. field =3D string.split(string.strip(line), ' ', 1) # Put the name and value pair inside our temporary storage. storage[field[0]]=3Dfield[1] # Close the file. file.close() # To see if the driver is loaded is marked by the next reg-exp. driver =3D re.compile('^snd_au1x00') # By default we expect our driver not to load. loaded =3D False # Continue to load the driver untill it is loaded. while not loaded: # Run the command to find out which kernel drivers are loaded. stdout =3D os.popen('/bin/lsmod') # Read the output from the previous command. output =3D stdout.read() # Is our driver loaded? if driver.search(output): # Yes, mark that we've loaded the driver. loaded =3D True else: # No, so try to load it ourselves. loaded =3D not os.system('(/sbin/modprobe snd-au1x00 && /etc/init.d/alsa= -utils start) > /dev/null 2>&1') # If we're loaded we are going to check if everything is ok. ok =3D loaded # Is everything ok? if ok: # Yes, run our command to find out how many control we have got. stdout =3D os.popen('/usr/bin/amixer controls') # See if we have all the expected controls. Are we missing some? if len(stdout.readlines()) !=3D len(controlsAvailableList): # Yes, mark that we are not ok anymore. ok =3D False # Is everything still ok? if ok: # Yes, process all the found controls. for control in controls: # Does this control object has a error method? if hasattr(control, 'error'): # Yes, it has. Now run it, to see if an error in the control exist. Do= es it? if control.error(): # Yes, mark that we are not ok anymore. ok =3D False # Stop processing, since it does not make sense anymore break =09 # Did anything go wrong and was the driver loaded? if not ok and loaded: # Yes, so mark that we still have not loaded the driver successfully. loaded =3D False # Stop the driver. driverStop() # A nice usage routine. def usage(): # Write the usage of this program to stdout. print 'Usage: %s {start|stop}' % (sys.argv[0]) # Quit right away. sys.exit(1) # Do we have received enough command line arguments? if len(sys.argv) >=3D 2: # Yes, what was the first argument received? if sys.argv[1] =3D=3D 'start': # It was our command to start the driver. Start it! driverStart() elif sys.argv[1] =3D=3D 'stop': # It was our command to stop the driver. Stop it! driverStop() else: # It was an unknown command. Display our usage message. usage() else: # No, display our usage message. usage() # Exit cleanly. sys.exit(0) --SSJ6yXlPvEk0CmSI-- --Chn8nxio6L/4biUD Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) iD8DBQFGI4yYbxf9XXlB0eERAiN2AJ9tuacSRfHOCK94DhH/QjXORfxw/gCgvNaC 4R2nFbmKcfHjAcVS1RwharE= =XyEI -----END PGP SIGNATURE----- --Chn8nxio6L/4biUD-- From zhangfx@lemote.com Mon Apr 16 16:11:13 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Apr 2007 16:11:15 +0100 (BST) Received: from [222.92.8.141] ([222.92.8.141]:38016 "HELO lemote.com") by ftp.linux-mips.org with SMTP id S20023319AbXDPPLN (ORCPT ); Mon, 16 Apr 2007 16:11:13 +0100 Received: (qmail 8073 invoked by uid 511); 16 Apr 2007 15:13:13 -0000 Received: from unknown (HELO ?192.168.1.63?) (222.92.8.142) by lemote.com with SMTP; 16 Apr 2007 15:13:13 -0000 Message-ID: <462391D5.90707@lemote.com> Date: Mon, 16 Apr 2007 23:10:13 +0800 From: Zhang Fuxin User-Agent: Thunderbird 1.5.0.10 (Windows/20070221) MIME-Version: 1.0 To: Thiemo Seufer , Linux/MIPS Development Subject: Re: [PATCH 2/16] arch related Makefile update for lemote fulong mini-PC References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <20070415222847.GA1402@networkno.de> <4623387F.3070905@lemote.com> <20070416124422.GB1402@networkno.de> In-Reply-To: <20070416124422.GB1402@networkno.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14871 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhangfx@lemote.com Precedence: bulk X-list: linux-mips Thiemo Seufer 写é“: > Maybe. The 'mips3' maps to -march=r4000, it would assume more memory > latency and a slower integer divider then -march=r4600. > Just like Ralf has said, -march might not lead to significant performance difference, but -mtune= may. Two years ago, I found that adding a machine.def to descripe pipeline and resources for loongson2 and -mtune=loongson boost many programs by 2-5%。 > > Thiemo > > > From yoichi_yuasa@tripeaks.co.jp Tue Apr 17 11:16:45 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Apr 2007 11:16:49 +0100 (BST) Received: from mo31.po.2iij.net ([210.128.50.54]:23324 "EHLO mo31.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20023603AbXDQKQp (ORCPT ); Tue, 17 Apr 2007 11:16:45 +0100 Received: by mo.po.2iij.net (mo31) id l3HAFODs040681; Tue, 17 Apr 2007 19:15:24 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox33) id l3HAFMsS091358 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 17 Apr 2007 19:15:22 +0900 (JST) Date: Tue, 17 Apr 2007 19:15:22 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH] fix NEC VR4100 series explanation Message-Id: <20070417191522.6382f086.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14872 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has fixed NEC VR4100 series explanation in arch/mips/Kconfig. This small fix is only for linux-mips.org tree. It's already fixed in linus tree. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Kconfig mips/arch/mips/Kconfig --- mips-orig/arch/mips/Kconfig 2007-04-14 22:14:15.756283750 +0900 +++ mips/arch/mips/Kconfig 2007-04-14 22:15:46.073928250 +0900 @@ -1233,7 +1233,7 @@ config CPU_VR41XX select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL help - The options selects support for the NEC VR41xx series of processors. + The options selects support for the NEC VR4100 series of processors. Only choose this option if you have one of these processors as a kernel built with this option will not run on any other type of processor or vice versa. From ralf@linux-mips.org Wed Apr 18 11:41:28 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 11:41:30 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:27075 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021643AbXDRKl2 (ORCPT ); Wed, 18 Apr 2007 11:41:28 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3IAfRcr004569; Wed, 18 Apr 2007 11:41:28 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3IAfQhZ004568; Wed, 18 Apr 2007 11:41:26 +0100 Date: Wed, 18 Apr 2007 11:41:26 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH] fix NEC VR4100 series explanation Message-ID: <20070418104126.GA3938@linux-mips.org> References: <20070417191522.6382f086.yoichi_yuasa@tripeaks.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070417191522.6382f086.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14873 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Apr 17, 2007 at 07:15:22PM +0900, Yoichi Yuasa wrote: > This patch has fixed NEC VR4100 series explanation in arch/mips/Kconfig. > This small fix is only for linux-mips.org tree. > It's already fixed in linus tree. Thanks, applied. Ralf From ralf@linux-mips.org Wed Apr 18 12:30:49 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 12:30:51 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:54679 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021716AbXDRLat (ORCPT ); Wed, 18 Apr 2007 12:30:49 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3IBUlNR020490; Wed, 18 Apr 2007 12:30:47 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3IBUkYM020488; Wed, 18 Apr 2007 12:30:46 +0100 Date: Wed, 18 Apr 2007 12:30:46 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Retry {save,restore}_fp_context if failed in atomic context. Message-ID: <20070418113046.GC3938@linux-mips.org> References: <20070416.231944.41198415.anemo@mba.ocn.ne.jp> <20070416.233235.75185596.anemo@mba.ocn.ne.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070416.233235.75185596.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14874 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 16, 2007 at 11:32:35PM +0900, Atsushi Nemoto wrote: > > The save_fp_context()/restore_fp_context() might sleep on accessing > > user stack and therefore might lose FPU ownership in middle of them. > > > > If these function failed due to "in_atomic" test in do_page_fault, > > touch the sigcontext area in non-atomic context and retry these > > save/restore operation. > > > > This is a replacement of a (broken) fix which was titled "Allow CpU > > exception in kernel partially". > > > > Signed-off-by: Atsushi Nemoto > > And this is for 2.6.20-stable. Both applied, also to older -stable branches except 2.6.16. In case of 2.6.16 it would have been more time consuming than justifyable and since the bug this patch fixes is comparable to what we had before starting the whole surgery I have no problem to leave 2.6.16 as it is. Anybody still using 2.6.16 should upgrade anyway ... Ralf From ralf@linux-mips.org Wed Apr 18 13:02:43 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 13:02:45 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:62345 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021721AbXDRMCn (ORCPT ); Wed, 18 Apr 2007 13:02:43 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3IC2fOi021083; Wed, 18 Apr 2007 13:02:42 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3IC2eTL021082; Wed, 18 Apr 2007 13:02:40 +0100 Date: Wed, 18 Apr 2007 13:02:40 +0100 From: Ralf Baechle To: tiansm@lemote.com Cc: linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 4/16] TO_PHYS_MASK for loongson2 Message-ID: <20070418120240.GD3938@linux-mips.org> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <11766507661133-git-send-email-tiansm@lemote.com> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14875 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Apr 15, 2007 at 11:25:53PM +0800, tiansm@lemote.com wrote: > diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h > index 964c5ed..a4d9a07 100644 > --- a/include/asm-mips/addrspace.h > +++ b/include/asm-mips/addrspace.h > @@ -145,7 +145,7 @@ > #define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ > #endif > > -#if defined (CONFIG_CPU_R10000) > +#if defined (CONFIG_CPU_R10000) || defined (CONFIG_CPU_LOONGSON2) > #define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ > #endif How about we define TO_PHYS_MASK to 2^57-1 for all processors instead? The use of TO_PHYS_MASK is to strip of the high bits of of a XKPHYS kernel virtual address. Allowing for the top 2 region and 3 cache mode bits that would leave 59 bits. If we also allow for the macro to be used for stripping off the 2 R10000 "uncached attribute" bits we would be down to 57 bits. Not sure if that would be useful - but we got gobs of address space to burn and adding yet another #ifdef for every new 64-bit processor or even variant to addrspace.h isn't really the way to go. Ralf From ralf@linux-mips.org Wed Apr 18 13:06:21 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 13:06:22 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:49888 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021729AbXDRMGV (ORCPT ); Wed, 18 Apr 2007 13:06:21 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3IC6KSl021152; Wed, 18 Apr 2007 13:06:20 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3IC6KY2021151; Wed, 18 Apr 2007 13:06:20 +0100 Date: Wed, 18 Apr 2007 13:06:20 +0100 From: Ralf Baechle To: tiansm@lemote.com Cc: linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC Message-ID: <20070418120620.GE3938@linux-mips.org> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <11766507662638-git-send-email-tiansm@lemote.com> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14876 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Apr 15, 2007 at 11:25:52PM +0800, tiansm@lemote.com wrote: > @@ -1681,6 +1712,13 @@ config CPU_HAS_SMARTMIPS > config CPU_HAS_WB > bool > > +config 64BIT_CONTEXT > + bool "Save 64bit integer registers" if CPU_LOONGSON2 && 32BIT > + help > + Loongson2 CPU is 64bit , when used in 32BIT mode, its integer registers > + can still be accessed as 64bit, mainly for multimedia instructions. We must have > + all 64bit save/restored to make sure those instructions to get correct result. > + Is there anything in implementation of this option Loongson2-specific? If not then I suggest we make this option loook like: bool "Save 64bit integer registers" if CPU_SUPPORTS_64BIT_KERNEL && 32BIT Somebody else might have a use for it! Ralf From ralf@linux-mips.org Wed Apr 18 13:11:42 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 13:11:43 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:60374 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021737AbXDRMLm (ORCPT ); Wed, 18 Apr 2007 13:11:42 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3ICBeBK021244; Wed, 18 Apr 2007 13:11:41 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3ICBd54021243; Wed, 18 Apr 2007 13:11:39 +0100 Date: Wed, 18 Apr 2007 13:11:39 +0100 From: Ralf Baechle To: tiansm@lemote.com Cc: linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 6/16] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 Message-ID: <20070418121139.GF3938@linux-mips.org> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <11766507662650-git-send-email-tiansm@lemote.com> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14877 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Apr 15, 2007 at 11:25:55PM +0800, tiansm@lemote.com wrote: > +#if defined(CONFIG_CPU_LOONGSON2) > +#define Hit_Invalidate_I 0x00 This #ifdef means Index_Invalidate_I and Hit_Invalidate_I will both be defined as zero, is that really correct? (This is the point where I would really like to have a CPU manual ...) > +#else > #define Hit_Invalidate_I 0x10 > +#endif Ralf From fxzhang@ict.ac.cn Wed Apr 18 14:34:10 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 14:34:11 +0100 (BST) Received: from webmail.ict.ac.cn ([159.226.39.7]:1246 "EHLO ict.ac.cn") by ftp.linux-mips.org with ESMTP id S20021797AbXDRNeK (ORCPT ); Wed, 18 Apr 2007 14:34:10 +0100 Received: (qmail 32598 invoked by uid 507); 18 Apr 2007 21:36:22 +0800 Received: from unknown (HELO ?192.168.1.7?) (fxzhang@222.92.8.142) by ict.ac.cn with SMTP; 18 Apr 2007 21:36:22 +0800 Message-ID: <46261DE2.5040908@ict.ac.cn> Date: Wed, 18 Apr 2007 21:32:18 +0800 From: Fuxin Zhang User-Agent: Icedove 1.5.0.8 (X11/20061116) MIME-Version: 1.0 To: Ralf Baechle CC: tiansm@lemote.com, linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <20070418120620.GE3938@linux-mips.org> In-Reply-To: <20070418120620.GE3938@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14878 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fxzhang@ict.ac.cn Precedence: bulk X-list: linux-mips >> + >> > > Is there anything in implementation of this option Loongson2-specific? > Yes. Most 64bit MIPS processors cannot access 64bit content of registers when it is in 32bit mode. Loongson2 has no 32/64 mode bit in fact. And the usage arise from Loongson2's multimedia extension, which is also uniq. > If not then I suggest we make this option loook like: > > bool "Save 64bit integer registers" if CPU_SUPPORTS_64BIT_KERNEL && 32BIT > > Somebody else might have a use for it! > > Ralf > > > > > From fxzhang@ict.ac.cn Wed Apr 18 14:53:46 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 14:53:47 +0100 (BST) Received: from webmail.ict.ac.cn ([159.226.39.7]:57823 "EHLO ict.ac.cn") by ftp.linux-mips.org with ESMTP id S20021824AbXDRNxq (ORCPT ); Wed, 18 Apr 2007 14:53:46 +0100 Received: (qmail 9809 invoked by uid 507); 18 Apr 2007 21:56:03 +0800 Received: from unknown (HELO ?192.168.1.7?) (fxzhang@222.92.8.142) by ict.ac.cn with SMTP; 18 Apr 2007 21:56:03 +0800 Message-ID: <4626227E.4010703@ict.ac.cn> Date: Wed, 18 Apr 2007 21:51:58 +0800 From: Fuxin Zhang User-Agent: Icedove 1.5.0.8 (X11/20061116) MIME-Version: 1.0 To: Ralf Baechle CC: tiansm@lemote.com, linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 6/16] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <20070418121139.GF3938@linux-mips.org> In-Reply-To: <20070418121139.GF3938@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14879 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fxzhang@ict.ac.cn Precedence: bulk X-list: linux-mips Yes, Loongson2 has no Hit_invalidate_I in fact. And although it has 4-way icache, one Index_invalidate_I will invalidate all 4 ways of the same set. The usermanual and datasheet can be downloaded from: http://www.lemote.com/upfiles/godson2e-user-manual-V0.6.pdf Ralf Baechle wrote: > On Sun, Apr 15, 2007 at 11:25:55PM +0800, tiansm@lemote.com wrote: > > >> +#if defined(CONFIG_CPU_LOONGSON2) >> +#define Hit_Invalidate_I 0x00 >> > > This #ifdef means Index_Invalidate_I and Hit_Invalidate_I will both be > defined as zero, is that really correct? > > (This is the point where I would really like to have a CPU manual ...) > > >> +#else >> #define Hit_Invalidate_I 0x10 >> +#endif >> > > Ralf > > > > > From ralf@linux-mips.org Wed Apr 18 14:54:17 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 14:54:18 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:65229 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021840AbXDRNyR (ORCPT ); Wed, 18 Apr 2007 14:54:17 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3IDsE5F023189; Wed, 18 Apr 2007 14:54:15 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3IDsCN8023188; Wed, 18 Apr 2007 14:54:12 +0100 Date: Wed, 18 Apr 2007 14:54:12 +0100 From: Ralf Baechle To: tiansm@lemote.com, perex@suse.cz, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 16/16] alsa sound support for mips Message-ID: <20070418135412.GG3938@linux-mips.org> References: <11766507661684-git-send-email-tiansm@lemote.com> <117665076617-git-send-email-tiansm@lemote.com> <1176650766907-git-send-email-tiansm@lemote.com> <11766507663301-git-send-email-tiansm@lemote.com> <11766507663039-git-send-email-tiansm@lemote.com> <1176650766685-git-send-email-tiansm@lemote.com> <11766507661790-git-send-email-tiansm@lemote.com> <11766507672298-git-send-email-tiansm@lemote.com> <11766507672043-git-send-email-tiansm@lemote.com> <11766507674145-git-send-email-tiansm@lemote.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <11766507674145-git-send-email-tiansm@lemote.com> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14880 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Apr 15, 2007 at 11:26:05PM +0800, tiansm@lemote.com wrote: (Adding a few more people to the cc'list) > sound/core/pcm_native.c | 10 ++++++++++ > sound/core/sgbuf.c | 9 +++++++++ > 2 files changed, 19 insertions(+), 0 deletions(-) > > diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c > index 3e276fc..9005bac 100644 > --- a/sound/core/pcm_native.c > +++ b/sound/core/pcm_native.c > @@ -3145,7 +3145,11 @@ static struct page *snd_pcm_mmap_data_nopage(struct vm_area_struct *area, > return NOPAGE_OOM; /* XXX: is this really due to OOM? */ > } else { > vaddr = runtime->dma_area + offset; > +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) Please use CONFIG_MIPS instead of __mips__ in #if / #ifdefs. The question if #ifdefing is the right approach to solve this problem is something else but I think no, .... > + page = virt_to_page(CAC_ADDR(vaddr)); > +#else > page = virt_to_page(vaddr); > +#endif So this is needed because the MIPS virt_to_page is returning a unsuitable value if vaddress is not a KSEG0 (64-bit: cached XKPHYS) address which is what GFP allocations and the slab will return. So now we have to deciede if a) the MIPS __pa() should be changed to handle uncached addresses. b) the sound code here is simply broken. Some drivers seem to allocate runtime->dma_area from vmalloc, so this whole area in the sound code is looking like built on quicksand ... > } > get_page(page); > if (type) > @@ -3261,6 +3265,12 @@ static int snd_pcm_mmap(struct file *file, struct vm_area_struct *area) > substream = pcm_file->substream; > snd_assert(substream != NULL, return -ENXIO); > > +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) > + /* all mmap using uncached mode */ > + area->vm_page_prot = pgprot_noncached(area->vm_page_prot); > + area->vm_flags |= ( VM_RESERVED | VM_IO); VM_RESERVED will prevent the buffer from being freed. I assume that is another workaround for some kernel subsystem blowing up when being fed a pointer to an uncached RAM address? This smells like a memory leak. > +#endif > + > offset = area->vm_pgoff << PAGE_SHIFT; > switch (offset) { > case SNDRV_PCM_MMAP_OFFSET_STATUS: > diff --git a/sound/core/sgbuf.c b/sound/core/sgbuf.c > index cefd228..535f0bc 100644 > --- a/sound/core/sgbuf.c > +++ b/sound/core/sgbuf.c > @@ -91,12 +91,21 @@ void *snd_malloc_sgbuf_pages(struct device *device, > } > sgbuf->table[i].buf = tmpb.area; > sgbuf->table[i].addr = tmpb.addr; > +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) > + sgbuf->page_table[i] = virt_to_page(CAC_ADDR(tmpb.area)); VM_RESERVED will prevent the buffer from being freed. I assume that is another workaround for some kernel subsystem blowing up when being fed a pointer to an uncached RAM address? This smells like a memory leak. > +#else > sgbuf->page_table[i] = virt_to_page(tmpb.area); > +#endif > sgbuf->pages++; > } > > sgbuf->size = size; > +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) > + /* maybe we should use uncached accelerated mode */ > + dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP | VM_IO, pgprot_noncached(PAGE_KERNEL)); > +#else > dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP, PAGE_KERNEL); > +#endif I would suggest to get rid of this ifdef with a new arch-specific function like vmap_io_buffer which will do whatever a platform seems fit for this case? > if (! dmab->area) > goto _failed; > return dmab->area; Ralf From fxzhang@ict.ac.cn Wed Apr 18 14:56:53 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 14:56:55 +0100 (BST) Received: from webmail.ict.ac.cn ([159.226.39.7]:15072 "EHLO ict.ac.cn") by ftp.linux-mips.org with ESMTP id S20021825AbXDRN4x (ORCPT ); Wed, 18 Apr 2007 14:56:53 +0100 Received: (qmail 12523 invoked by uid 507); 18 Apr 2007 22:00:11 +0800 Received: from unknown (HELO ?192.168.1.7?) (fxzhang@222.92.8.142) by ict.ac.cn with SMTP; 18 Apr 2007 22:00:11 +0800 Message-ID: <46262377.3080406@ict.ac.cn> Date: Wed, 18 Apr 2007 21:56:07 +0800 From: Fuxin Zhang User-Agent: Icedove 1.5.0.8 (X11/20061116) MIME-Version: 1.0 To: Ralf Baechle CC: tiansm@lemote.com, linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 6/16] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <11766507661133-git-send-email-tiansm@lemote.com> <11766507661526-git-send-email-tiansm@lemote.com> <11766507662650-git-send-email-tiansm@lemote.com> <20070418121139.GF3938@linux-mips.org> <4626227E.4010703@ict.ac.cn> In-Reply-To: <4626227E.4010703@ict.ac.cn> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14881 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fxzhang@ict.ac.cn Precedence: bulk X-list: linux-mips Sorry, no english version of datasheet yet. Fuxin Zhang wrote: > Yes, Loongson2 has no Hit_invalidate_I in fact. And although it has > 4-way icache, one Index_invalidate_I will invalidate all 4 ways of the > same set. > > The usermanual and datasheet can be downloaded from: > > http://www.lemote.com/upfiles/godson2e-user-manual-V0.6.pdf > > > Ralf Baechle wrote: >> On Sun, Apr 15, 2007 at 11:25:55PM +0800, tiansm@lemote.com wrote: >> >> >>> +#if defined(CONFIG_CPU_LOONGSON2) >>> +#define Hit_Invalidate_I 0x00 >>> >> >> This #ifdef means Index_Invalidate_I and Hit_Invalidate_I will both be >> defined as zero, is that really correct? >> >> (This is the point where I would really like to have a CPU manual ...) >> >> >>> +#else >>> #define Hit_Invalidate_I 0x10 >>> +#endif >>> >> >> Ralf >> >> >> >> >> > > > > From anemo@mba.ocn.ne.jp Wed Apr 18 15:13:20 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 15:13:21 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:12234 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20021843AbXDRONU (ORCPT ); Wed, 18 Apr 2007 15:13:20 +0100 Received: from localhost (p8009-ipad27funabasi.chiba.ocn.ne.jp [220.107.199.9]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 0F12CA82D; Wed, 18 Apr 2007 23:13:16 +0900 (JST) Date: Wed, 18 Apr 2007 23:13:15 +0900 (JST) Message-Id: <20070418.231315.41198460.anemo@mba.ocn.ne.jp> To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Retry {save,restore}_fp_context if failed in atomic context. From: Atsushi Nemoto In-Reply-To: <20070418113046.GC3938@linux-mips.org> References: <20070416.231944.41198415.anemo@mba.ocn.ne.jp> <20070416.233235.75185596.anemo@mba.ocn.ne.jp> <20070418113046.GC3938@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14882 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Wed, 18 Apr 2007 12:30:46 +0100, Ralf Baechle wrote: > > And this is for 2.6.20-stable. > > Both applied, also to older -stable branches except 2.6.16. In case of > 2.6.16 it would have been more time consuming than justifyable and since > the bug this patch fixes is comparable to what we had before starting the > whole surgery I have no problem to leave 2.6.16 as it is. Anybody still > using 2.6.16 should upgrade anyway ... I agree this patch is not critical for older kernel. But 2.6.16-stable already applied the broken "Allow CpU exception in kernel partially" patch. This should be reverted. Just revert the commit a0d2a152ec0917b0c1b0c84a00fd95d17090a5f8 should be enough. --- Atsushi Nemoto From fxzhang@ict.ac.cn Wed Apr 18 15:13:48 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 15:13:50 +0100 (BST) Received: from webmail.ict.ac.cn ([159.226.39.7]:57313 "EHLO ict.ac.cn") by ftp.linux-mips.org with ESMTP id S20021865AbXDRONs (ORCPT ); Wed, 18 Apr 2007 15:13:48 +0100 Received: (qmail 19814 invoked by uid 507); 18 Apr 2007 22:17:06 +0800 Received: from unknown (HELO ?192.168.1.7?) (fxzhang@222.92.8.142) by ict.ac.cn with SMTP; 18 Apr 2007 22:17:06 +0800 Message-ID: <4626276E.3000303@ict.ac.cn> Date: Wed, 18 Apr 2007 22:13:02 +0800 From: Fuxin Zhang User-Agent: Icedove 1.5.0.8 (X11/20061116) MIME-Version: 1.0 To: Ralf Baechle CC: tiansm@lemote.com, perex@suse.cz, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 16/16] alsa sound support for mips References: <11766507661684-git-send-email-tiansm@lemote.com> <117665076617-git-send-email-tiansm@lemote.com> <1176650766907-git-send-email-tiansm@lemote.com> <11766507663301-git-send-email-tiansm@lemote.com> <11766507663039-git-send-email-tiansm@lemote.com> <1176650766685-git-send-email-tiansm@lemote.com> <11766507661790-git-send-email-tiansm@lemote.com> <11766507672298-git-send-email-tiansm@lemote.com> <11766507672043-git-send-email-tiansm@lemote.com> <11766507674145-git-send-email-tiansm@lemote.com> <20070418135412.GG3938@linux-mips.org> In-Reply-To: <20070418135412.GG3938@linux-mips.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14883 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fxzhang@ict.ac.cn Precedence: bulk X-list: linux-mips >> vaddr = runtime->dma_area + offset; >> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) >> > > Please use CONFIG_MIPS instead of __mips__ in #if / #ifdefs. > > The question if #ifdefing is the right approach to solve this problem is > something else but I think no, .... > I would agree that it is quite ugly, but changing virt_to_page for it does not seem right either. > >> + page = virt_to_page(CAC_ADDR(vaddr)); >> +#else >> page = virt_to_page(vaddr); >> +#endif >> > > So this is needed because the MIPS virt_to_page is returning a unsuitable > value if vaddress is not a KSEG0 (64-bit: cached XKPHYS) address which is > what GFP allocations and the slab will return. So now we have to deciede > if > > a) the MIPS __pa() should be changed to handle uncached addresses. > b) the sound code here is simply broken. > > Some drivers seem to allocate runtime->dma_area from vmalloc, so this > whole area in the sound code is looking like built on quicksand ... > >> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) >> + /* all mmap using uncached mode */ >> + area->vm_page_prot = pgprot_noncached(area->vm_page_prot); >> + area->vm_flags |= ( VM_RESERVED | VM_IO); >> > > VM_RESERVED will prevent the buffer from being freed. I assume that is > another workaround for some kernel subsystem blowing up when being fed a > pointer to an uncached RAM address? This smells like a memory leak. > > Oh, VM_RESERVED should be a memory leak problem, we can remove it. I don't remember any case of other subsystem's problem, just did not think much to add those flags. >> +#endif >> + >> offset = area->vm_pgoff << PAGE_SHIFT; >> switch (offset) { >> case SNDRV_PCM_MMAP_OFFSET_STATUS: >> diff --git a/sound/core/sgbuf.c b/sound/core/sgbuf.c >> index cefd228..535f0bc 100644 >> --- a/sound/core/sgbuf.c >> +++ b/sound/core/sgbuf.c >> @@ -91,12 +91,21 @@ void *snd_malloc_sgbuf_pages(struct device *device, >> } >> sgbuf->table[i].buf = tmpb.area; >> sgbuf->table[i].addr = tmpb.addr; >> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) >> + sgbuf->page_table[i] = virt_to_page(CAC_ADDR(tmpb.area)); >> > > VM_RESERVED will prevent the buffer from being freed. I assume that is > another workaround for some kernel subsystem blowing up when being fed a > pointer to an uncached RAM address? This smells like a memory leak. > > >> +#else >> sgbuf->page_table[i] = virt_to_page(tmpb.area); >> +#endif >> sgbuf->pages++; >> } >> >> sgbuf->size = size; >> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) >> + /* maybe we should use uncached accelerated mode */ >> + dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP | VM_IO, pgprot_noncached(PAGE_KERNEL)); >> +#else >> dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP, PAGE_KERNEL); >> +#endif >> > > I would suggest to get rid of this ifdef with a new arch-specific function > like vmap_io_buffer which will do whatever a platform seems fit for this > case? > I think arch-specific function is the correct way, but don't know what the alsa gods think. > >> if (! dmab->area) >> goto _failed; >> return dmab->area; >> > > Ralf > > > > > From ralf@linux-mips.org Wed Apr 18 15:26:03 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 15:26:05 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:48836 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021840AbXDRO0D (ORCPT ); Wed, 18 Apr 2007 15:26:03 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3IEPs2i024167; Wed, 18 Apr 2007 15:25:54 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3IEPrHL024166; Wed, 18 Apr 2007 15:25:53 +0100 Date: Wed, 18 Apr 2007 15:25:53 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Fix BUG(), BUG_ON() handling Message-ID: <20070418142553.GA24160@linux-mips.org> References: <20070412.200254.128619887.nemoto@toshiba-tops.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070412.200254.128619887.nemoto@toshiba-tops.co.jp> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14884 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Apr 12, 2007 at 08:02:54PM +0900, Atsushi Nemoto wrote: > With commit 63dc68a8cf60cb110b147dab1704d990808b39e2, kernel can not > handle BUG() and BUG_ON() properly since get_user() returns false for > kernel code. Use __get_user() to skip unnecessary access_ok(). This > patch also make BRK_BUG code encoded in the TNE instruction. Thanks, applied to 2.6.20-stable and master. Ralf From djohnson@sw.starentnetworks.com Wed Apr 18 15:40:23 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 15:40:24 +0100 (BST) Received: from newmail.sw.starentnetworks.com ([12.33.234.78]:45461 "EHLO mail.sw.starentnetworks.com") by ftp.linux-mips.org with ESMTP id S20021897AbXDROkX (ORCPT ); Wed, 18 Apr 2007 15:40:23 +0100 Received: from zeus.sw.starentnetworks.com (zeus.sw.starentnetworks.com [12.33.233.46]) by mail.sw.starentnetworks.com (Postfix) with ESMTP id 24BB63E363; Wed, 18 Apr 2007 10:39:42 -0400 (EDT) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <17958.11693.953285.795311@zeus.sw.starentnetworks.com> Date: Wed, 18 Apr 2007 10:39:41 -0400 From: Dave Johnson To: linux-mips@linux-mips.org, Ralf Baechle Subject: [PATCH] Fix wrong checksum for split TCP packets on 64-bit MIPS X-Mailer: VM 7.17 under 21.4 (patch 17) "Jumbo Shrimp" XEmacs Lucid Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14885 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: djohnson+linux-mips@sw.starentnetworks.com Precedence: bulk X-list: linux-mips I've traced down an off-by-one TCP checksum calculation error under the following conditions: 1) The TCP code needs to split a full-sized packet due to a reduced MSS (typically due to the addition of TCP options mid-stream like SACK). _AND_ 2) The checksum of the 2nd fragment is larger than the checksum of the original packet. After subtraction this results in a checksum for the 1st fragment with bits 16..31 set to 1. (this is ok) _AND_ 3) The checksum of the 1st fragment's TCP header plus the previously 32bit checksum of the 1st fragment DOES NOT cause a 32bit overflow when added together. This results in a checksum of the TCP header plus TCP data that still has the upper 16 bits as 1's. _THEN_ 4) The TCP+data checksum is added to the checksum of the pseudo IP header with csum_tcpudp_nofold() incorrectly (the bug). The problem is the checksum of the TCP+data is passed to csum_tcpudp_nofold() as an 32bit unsigned value, however the assembly code acts on it as if it is a 64bit unsigned value. This causes an incorrect 32->64bit extension if the sum has bit 31 set. The resulting checksum is off by one. This problems is data and TCP header dependent due to #2 and #3 above so it doesn't occur on every TCP packet split. Patch below is against 2.6.20, however this problem looks like it's been around since at least Aug 2003 when the 64bit ASM was added to csum_tcpudp_nofold(). Signed-off-by: Dave Johnson --- old/include/asm-mips/checksum.h 2007-01-24 14:23:22 -05:00 +++ new/include/asm-mips/checksum.h 2007-04-18 10:31:27 -04:00 @@ -166,7 +166,7 @@ #else "r" (proto + len), #endif - "r" (sum)); + "r" ((__force unsigned long)sum)); return sum; } From uhler@mips.com Wed Apr 18 16:28:33 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 16:28:36 +0100 (BST) Received: from mx.mips.com ([63.167.95.198]:8592 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S20021950AbXDRP2d convert rfc822-to-8bit (ORCPT ); Wed, 18 Apr 2007 16:28:33 +0100 Received: from mercury.mips.com (mercury [192.168.64.101]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id l3IFScWS003999; Wed, 18 Apr 2007 08:28:39 -0700 (PDT) Received: from exchange.MIPS.COM (exchange [192.168.20.29]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id l3IFS4Cc009995; Wed, 18 Apr 2007 08:28:04 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH 3/16] Kconfig update for lemote fulong mini-PC Date: Wed, 18 Apr 2007 08:28:16 -0700 Message-ID: <692AB3595F5D76428B34B9BEFE20BC1FC1D723@Exchange.mips.com> In-Reply-To: <46261DE2.5040908@ict.ac.cn> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH 3/16] Kconfig update for lemote fulong mini-PC Thread-Index: AceBvmmIjDpfIWciTSiH8NLF84zoUwACUllg References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <20070418120620.GE3938@linux-mips.org> <46261DE2.5040908@ict.ac.cn> From: "Uhler, Mike" To: "Fuxin Zhang" , "Ralf Baechle" Cc: , , "Fuxin Zhang" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14886 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: uhler@mips.com Precedence: bulk X-list: linux-mips > Yes. Most 64bit MIPS processors cannot access 64bit content > of registers when it is in 32bit mode. For clarity, there is no 32/64-bit mode in MIPS processors. There is a mode in which 64-bit OPERATIONS are enabled (that is, those instructions which operate on the full width of the registers) - See the definition of 64-bit Operations Enable in the MIPS64 Architecture for Programmers, volume III. Note that such operations are always enabled while the processor is running in Kernel Mode. The patch is a little short on context, but if you've got a 64-bit kernel, I had always assumed that save/restore of context is always done with LD/SD, not by figuring out whether a process has 64-bit operations enabled, then doing a conditional LD/SD or LW/SW. /gmu --- Michael Uhler, Chief Technology Officer MIPS Technologies, Inc. Email: uhler AT mips.com 1225 Charleston Road Voice: (650)567-5025 FAX: (650)567-5225 Mountain View, CA 94043 > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Fuxin Zhang > Sent: Wednesday, April 18, 2007 6:32 AM > To: Ralf Baechle > Cc: tiansm@lemote.com; linux-mips@linux-mips.org; Fuxin Zhang > Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC > > > >> + > >> > > > > Is there anything in implementation of this option > Loongson2-specific? > > > Yes. Most 64bit MIPS processors cannot access 64bit content > of registers when it is in 32bit mode. > > Loongson2 has no 32/64 mode bit in fact. > > And the usage arise from Loongson2's multimedia extension, > which is also uniq. > > If not then I suggest we make this option loook like: > > > > bool "Save 64bit integer registers" if > CPU_SUPPORTS_64BIT_KERNEL && > > 32BIT > > > > Somebody else might have a use for it! > > > > Ralf > > > > > > > > > > > > From fxzhang@ict.ac.cn Wed Apr 18 16:45:18 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 16:45:20 +0100 (BST) Received: from webmail.ict.ac.cn ([159.226.39.7]:4328 "EHLO ict.ac.cn") by ftp.linux-mips.org with ESMTP id S20021935AbXDRPpS (ORCPT ); Wed, 18 Apr 2007 16:45:18 +0100 Received: (qmail 22252 invoked by uid 507); 18 Apr 2007 23:47:37 +0800 Received: from unknown (HELO ?192.168.1.7?) (fxzhang@222.92.8.142) by ict.ac.cn with SMTP; 18 Apr 2007 23:47:37 +0800 Message-ID: <46263CA5.9080908@ict.ac.cn> Date: Wed, 18 Apr 2007 23:43:33 +0800 From: Fuxin Zhang User-Agent: Icedove 1.5.0.8 (X11/20061116) MIME-Version: 1.0 To: "Uhler, Mike" CC: Ralf Baechle , tiansm@lemote.com, linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <20070418120620.GE3938@linux-mips.org> <46261DE2.5040908@ict.ac.cn> <692AB3595F5D76428B34B9BEFE20BC1FC1D723@Exchange.mips.com> In-Reply-To: <692AB3595F5D76428B34B9BEFE20BC1FC1D723@Exchange.mips.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14887 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fxzhang@ict.ac.cn Precedence: bulk X-list: linux-mips Uhler, Mike wrote: >> Yes. Most 64bit MIPS processors cannot access 64bit content >> of registers when it is in 32bit mode. >> > > For clarity, there is no 32/64-bit mode in MIPS processors. There is a > mode in which 64-bit OPERATIONS are enabled (that is, those instructions > which operate on the full width of the registers) - See the definition > of 64-bit Operations Enable in the MIPS64 Architecture for Programmers, > volume III. Note that such operations are always enabled while the > processor is running in Kernel Mode. > > The patch is a little short on context, but if you've got a 64-bit > kernel, I had always assumed that save/restore of context is always done > with LD/SD, not by figuring out whether a process has 64-bit operations > enabled, then doing a conditional LD/SD or LW/SW. > > This patch for 32bit kernel. We want to save/restore 64bit register content because the high 32bit of register might be used by multimedia programs for loongson processor, such as mplayer. > /gmu > --- > Michael Uhler, Chief Technology Officer > MIPS Technologies, Inc. Email: uhler AT mips.com > 1225 Charleston Road Voice: (650)567-5025 FAX: (650)567-5225 > Mountain View, CA 94043 > > > >> -----Original Message----- >> From: linux-mips-bounce@linux-mips.org >> [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Fuxin Zhang >> Sent: Wednesday, April 18, 2007 6:32 AM >> To: Ralf Baechle >> Cc: tiansm@lemote.com; linux-mips@linux-mips.org; Fuxin Zhang >> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC >> >> >> >>>> + >>>> >>>> >>> Is there anything in implementation of this option >>> >> Loongson2-specific? >> >>> >>> >> Yes. Most 64bit MIPS processors cannot access 64bit content >> of registers when it is in 32bit mode. >> >> Loongson2 has no 32/64 mode bit in fact. >> >> And the usage arise from Loongson2's multimedia extension, >> which is also uniq. >> >>> If not then I suggest we make this option loook like: >>> >>> bool "Save 64bit integer registers" if >>> >> CPU_SUPPORTS_64BIT_KERNEL && >> >>> 32BIT >>> >>> Somebody else might have a use for it! >>> >>> Ralf >>> >>> >>> >>> >>> >>> >> > > > > > From ralf@linux-mips.org Wed Apr 18 17:17:09 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 17:17:11 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:39808 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021726AbXDRQRJ (ORCPT ); Wed, 18 Apr 2007 17:17:09 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3IGH8k9026845; Wed, 18 Apr 2007 17:17:09 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3IGH74Q026844; Wed, 18 Apr 2007 17:17:07 +0100 Date: Wed, 18 Apr 2007 17:17:07 +0100 From: Ralf Baechle To: Dave Johnson Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Fix wrong checksum for split TCP packets on 64-bit MIPS Message-ID: <20070418161707.GB24160@linux-mips.org> References: <17958.11693.953285.795311@zeus.sw.starentnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <17958.11693.953285.795311@zeus.sw.starentnetworks.com> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14888 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 18, 2007 at 10:39:41AM -0400, Dave Johnson wrote: > the following conditions: > > 1) The TCP code needs to split a full-sized packet due to a reduced > MSS (typically due to the addition of TCP options mid-stream like > SACK). > _AND_ > 2) The checksum of the 2nd fragment is larger than the checksum of the > original packet. After subtraction this results in a checksum for > the 1st fragment with bits 16..31 set to 1. (this is ok) > _AND_ > 3) The checksum of the 1st fragment's TCP header plus the previously > 32bit checksum of the 1st fragment DOES NOT cause a 32bit overflow > when added together. This results in a checksum of the TCP header > plus TCP data that still has the upper 16 bits as 1's. > _THEN_ > 4) The TCP+data checksum is added to the checksum of the pseudo IP > header with csum_tcpudp_nofold() incorrectly (the bug). > > The problem is the checksum of the TCP+data is passed to > csum_tcpudp_nofold() as an 32bit unsigned value, however the assembly > code acts on it as if it is a 64bit unsigned value. > > This causes an incorrect 32->64bit extension if the sum has bit 31 > set. The resulting checksum is off by one. Sigh. The second bug of this kind. As clever and apparently elegent as the sign extension stuff happens to look on MIPS as prone to unobvious accidents it is at times. Oh well. Applied & thanks! Ralf From ralf@linux-mips.org Wed Apr 18 17:38:14 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 17:38:16 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:50053 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021892AbXDRQiO (ORCPT ); Wed, 18 Apr 2007 17:38:14 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3IGcBsi027260; Wed, 18 Apr 2007 17:38:11 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3IGc699027259; Wed, 18 Apr 2007 17:38:06 +0100 Date: Wed, 18 Apr 2007 17:38:06 +0100 From: Ralf Baechle To: "Uhler, Mike" Cc: Fuxin Zhang , tiansm@lemote.com, linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC Message-ID: <20070418163806.GA27199@linux-mips.org> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <20070418120620.GE3938@linux-mips.org> <46261DE2.5040908@ict.ac.cn> <692AB3595F5D76428B34B9BEFE20BC1FC1D723@Exchange.mips.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <692AB3595F5D76428B34B9BEFE20BC1FC1D723@Exchange.mips.com> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14889 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 18, 2007 at 08:28:16AM -0700, Uhler, Mike wrote: > > Yes. Most 64bit MIPS processors cannot access 64bit content > > of registers when it is in 32bit mode. > > For clarity, there is no 32/64-bit mode in MIPS processors. There is a > mode in which 64-bit OPERATIONS are enabled (that is, those instructions > which operate on the full width of the registers) - See the definition > of 64-bit Operations Enable in the MIPS64 Architecture for Programmers, > volume III. Note that such operations are always enabled while the > processor is running in Kernel Mode. > > The patch is a little short on context, but if you've got a 64-bit > kernel, I had always assumed that save/restore of context is always done > with LD/SD, not by figuring out whether a process has 64-bit operations > enabled, then doing a conditional LD/SD or LW/SW. Here's a funny one where we have something like a mode. This is a reposting from Bill Earl: [...] One other issue is that UX should always be set, to allow use of MIPS3 instructions, and that XX (bit 31) should be set on R5000 and R10000 processors, to enable MIPS4 instructions. This in turn means that, to avoid various illegal address exceptions, the VM system should not allow a 32-bit user program to map anything into the top 32 KB of the user address space. The problem has to do with some compilers using integer arithmetic to compute a base for some variables in the current stack frame, and then using negative displacements to address the variables, for cases where the stack frame exceeds 32 KB, but is located near the top of memory. The 32-bit unsigned integer add to, say, 0x7fffff00 (64-bit address 0x000000007fffff00) produces a signed 32-bit value such as 0x80000f00, which is the 64-bit value 0xffffffff80000f00, since all 32-bit values, signed or unsigned, are stored as 32-bit signed values sign-extended to 64 bits. When you do a load with a negative offset of, say, -0x1000, you get an address 0xffffffff7fffff00, not 0x000000007fffff00. With UX=0, this would be fine, but, with UX=1 (to enable MIPS3 instructions), the above address is illegal. If the $sp is always at least 32 KB below the top of the address space, this problem does not arise, since any such intermediate pointer generated by the compiler will always be below 0x80000000. [...] The original posting is at http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=14452.59571.970106.514001%40liveoak.engr.sgi.com Ralf From anemo@mba.ocn.ne.jp Wed Apr 18 17:40:29 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 17:40:32 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:14789 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20021844AbXDRQk3 (ORCPT ); Wed, 18 Apr 2007 17:40:29 +0100 Received: from localhost (p8009-ipad27funabasi.chiba.ocn.ne.jp [220.107.199.9]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id C76C3B65E; Thu, 19 Apr 2007 01:40:24 +0900 (JST) Date: Thu, 19 Apr 2007 01:40:24 +0900 (JST) Message-Id: <20070419.014024.07456941.anemo@mba.ocn.ne.jp> To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Retry {save,restore}_fp_context if failed in atomic context. From: Atsushi Nemoto In-Reply-To: <20070418.231315.41198460.anemo@mba.ocn.ne.jp> References: <20070416.233235.75185596.anemo@mba.ocn.ne.jp> <20070418113046.GC3938@linux-mips.org> <20070418.231315.41198460.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14890 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Wed, 18 Apr 2007 23:13:15 +0900 (JST), Atsushi Nemoto wrote: > I agree this patch is not critical for older kernel. But > 2.6.16-stable already applied the broken "Allow CpU exception in > kernel partially" patch. This should be reverted. Just revert the > commit a0d2a152ec0917b0c1b0c84a00fd95d17090a5f8 should be enough. I confirmed the reverse-patch can be cleanly applied on 2.6.16-stable head. --- Atsushi Nemoto From uhler@mips.com Wed Apr 18 23:34:58 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Apr 2007 23:35:00 +0100 (BST) Received: from mx.mips.com ([63.167.95.198]:26264 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S20021834AbXDRWe6 convert rfc822-to-8bit (ORCPT ); Wed, 18 Apr 2007 23:34:58 +0100 Received: from mercury.mips.com (mercury [192.168.64.101]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id l3IMRk9p005510; Wed, 18 Apr 2007 15:27:46 -0700 (PDT) Received: from exchange.MIPS.COM (exchange [192.168.20.29]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id l3IMRA02020482; Wed, 18 Apr 2007 15:27:11 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH 3/16] Kconfig update for lemote fulong mini-PC Date: Wed, 18 Apr 2007 15:27:16 -0700 Message-ID: <692AB3595F5D76428B34B9BEFE20BC1FC1D733@Exchange.mips.com> In-Reply-To: <20070418163806.GA27199@linux-mips.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH 3/16] Kconfig update for lemote fulong mini-PC Thread-Index: AceB1/8Iw6c8qNA6T7u9BLfk1jzPVgAL//TQ References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <20070418120620.GE3938@linux-mips.org> <46261DE2.5040908@ict.ac.cn> <692AB3595F5D76428B34B9BEFE20BC1FC1D723@Exchange.mips.com> <20070418163806.GA27199@linux-mips.org> From: "Uhler, Mike" To: "Ralf Baechle" Cc: "Fuxin Zhang" , , , "Fuxin Zhang" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14891 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: uhler@mips.com Precedence: bulk X-list: linux-mips Note that both of these apply to pre-MIPS64 processors. In a MIPS64 implementation, The Status.PX bit should be used to enable 64-bit operations without enabling 64-bit addressing. The Status.XX bit is gone and can't be set. The addressing boundary condition that Bill mentioned is explicitly address in the Architecture for Programmer's manual, Volume III, section 4.10 as a requirement for hardware in exactly this case. I realize that Loongson is a MIPS III processor where Bill's suggestion may apply, but it's not a general problem moving forward to MIPS64. /gmu --- Michael Uhler, Chief Technology Officer MIPS Technologies, Inc. Email: uhler AT mips.com 1225 Charleston Road Voice: (650)567-5025 FAX: (650)567-5225 Mountain View, CA 94043 > -----Original Message----- > From: Ralf Baechle [mailto:ralf@linux-mips.org] > Sent: Wednesday, April 18, 2007 9:38 AM > To: Uhler, Mike > Cc: Fuxin Zhang; tiansm@lemote.com; > linux-mips@linux-mips.org; Fuxin Zhang > Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC > > On Wed, Apr 18, 2007 at 08:28:16AM -0700, Uhler, Mike wrote: > > > > Yes. Most 64bit MIPS processors cannot access 64bit content of > > > registers when it is in 32bit mode. > > > > For clarity, there is no 32/64-bit mode in MIPS processors. > There is > > a mode in which 64-bit OPERATIONS are enabled (that is, those > > instructions which operate on the full width of the > registers) - See > > the definition of 64-bit Operations Enable in the MIPS64 > Architecture > > for Programmers, volume III. Note that such operations are always > > enabled while the processor is running in Kernel Mode. > > > > The patch is a little short on context, but if you've got a 64-bit > > kernel, I had always assumed that save/restore of context is always > > done with LD/SD, not by figuring out whether a process has 64-bit > > operations enabled, then doing a conditional LD/SD or LW/SW. > > Here's a funny one where we have something like a mode. This > is a reposting from Bill Earl: > > [...] > One other issue is that UX should always be set, to allow use of > MIPS3 instructions, and that XX (bit 31) should be set on > R5000 and R10000 processors, to enable MIPS4 instructions. > This in turn means that, to avoid various illegal address > exceptions, the VM system should not allow a 32-bit user > program to map anything into the top 32 KB of the user address space. > > The problem has to do with some compilers using integer > arithmetic to compute a base for some variables in the > current stack frame, and then using negative displacements to > address the variables, for cases where the stack frame > exceeds 32 KB, but is located near the top of memory. The > 32-bit unsigned integer add to, say, 0x7fffff00 (64-bit > address 0x000000007fffff00) produces a signed 32-bit value > such as 0x80000f00, which is the 64-bit value > 0xffffffff80000f00, since all 32-bit values, signed or > unsigned, are stored as 32-bit signed values sign-extended to > 64 bits. When you do a load with a negative offset of, say, > -0x1000, you get an address 0xffffffff7fffff00, not > 0x000000007fffff00. With UX=0, this would be fine, but, with > UX=1 (to enable MIPS3 instructions), the above address is > illegal. If the $sp is always at least 32 KB below the top > of the address space, this problem does not arise, since any > such intermediate pointer generated by the compiler will > always be below 0x80000000. > [...] > > The original posting is at > http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=1445 2.59571.970106.514001%40liveoak.engr.sgi.com > > Ralf > From ralf@linux-mips.org Thu Apr 19 01:34:42 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Apr 2007 01:34:43 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:12699 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021964AbXDSAem (ORCPT ); Thu, 19 Apr 2007 01:34:42 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3J0YP0J001329; Thu, 19 Apr 2007 01:34:26 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3J0YAPU001328; Thu, 19 Apr 2007 01:34:10 +0100 Date: Thu, 19 Apr 2007 01:34:10 +0100 From: Ralf Baechle To: "Uhler, Mike" Cc: Fuxin Zhang , tiansm@lemote.com, linux-mips@linux-mips.org, Fuxin Zhang Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC Message-ID: <20070419003410.GB30699@linux-mips.org> References: <11766507651736-git-send-email-tiansm@lemote.com> <11766507661317-git-send-email-tiansm@lemote.com> <11766507661726-git-send-email-tiansm@lemote.com> <11766507662638-git-send-email-tiansm@lemote.com> <20070418120620.GE3938@linux-mips.org> <46261DE2.5040908@ict.ac.cn> <692AB3595F5D76428B34B9BEFE20BC1FC1D723@Exchange.mips.com> <20070418163806.GA27199@linux-mips.org> <692AB3595F5D76428B34B9BEFE20BC1FC1D733@Exchange.mips.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <692AB3595F5D76428B34B9BEFE20BC1FC1D733@Exchange.mips.com> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14892 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Apr 18, 2007 at 03:27:16PM -0700, Uhler, Mike wrote: > Note that both of these apply to pre-MIPS64 processors. In a MIPS64 > implementation, The Status.PX bit should be used to enable 64-bit > operations without enabling 64-bit addressing. The Status.XX bit is > gone and can't be set. The addressing boundary condition that Bill > mentioned is explicitly address in the Architecture for Programmer's > manual, Volume III, section 4.10 as a requirement for hardware in > exactly this case. > > I realize that Loongson is a MIPS III processor where Bill's suggestion > may apply, but it's not a general problem moving forward to MIPS64. Linux limits the address space to 0x7fff8000 for 32-bit processes. For sake of simplicity and symmetry we do this on both 32-bit and 64-bit kernels, on all processors. A 64-bit kernel always runs userspace processes with UX=1. Since a 32-bit process cannot create mappings above the low 2GB there isn't an actual need to use PX. (I think there is a small bug in this scheme though, a process that is accessing a 64-bit userspace address that isn't a 32-bit address should be sent a SIGBUS but will actually receive a SIGSEGV. But that's a subtility and also requires extrapolating from an API documents that only covers a strict 32-bit universe.) Ralf From milindchoudhary@gmail.com Thu Apr 19 10:33:51 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Apr 2007 10:33:53 +0100 (BST) Received: from ug-out-1314.google.com ([66.249.92.168]:56863 "EHLO ug-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20021411AbXDSJdv (ORCPT ); Thu, 19 Apr 2007 10:33:51 +0100 Received: by ug-out-1314.google.com with SMTP id 40so549257uga for ; Thu, 19 Apr 2007 02:32:51 -0700 (PDT) DKIM-Signature: a=rsa-sha1; c=relaxed/relaxed; d=gmail.com; s=beta; h=domainkey-signature:received:received:date:from:to:cc:subject:message-id:mime-version:content-type:content-disposition:user-agent; b=i75iwh4QmXnq6O4XlHDO84RlHIJ1WdUoQVhb43+VZ3qzR3S++za0gIvQALa+FEBVrplMFflgZpfD42OS8OsV4+HRmQY3+hdI2Gm0hO0YGbi3d0tAfVGfCuCY217eWsnHm7RMTD4VrvCZLL00wotk/o0p5lWrL3VGVUGz3DbbcvA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=beta; h=received:date:from:to:cc:subject:message-id:mime-version:content-type:content-disposition:user-agent; b=j2dxyVeLS3K61wK4OXQR/uk8RL6igC+nGQMdek9MS394X2c4H0yR+//hjMoJpa5EY7iv1JqSqV1Hv14eyLb6t6LHJ+S7tWAeLFY73S6bFbWI52Euo+49Bk32HSV6832ZMmx+mYPny5TYvbca83+wlMyWLOuScWPQ9sYXvmRoTfQ= Received: by 10.67.10.18 with SMTP id n18mr1926106ugi.1176975170959; Thu, 19 Apr 2007 02:32:50 -0700 (PDT) Received: from localhost ( [59.95.36.145]) by mx.google.com with ESMTP id 34sm2788392uga.2007.04.19.02.32.47; Thu, 19 Apr 2007 02:32:50 -0700 (PDT) Date: Thu, 19 Apr 2007 15:05:16 +0530 From: Milind Arun Choudhary To: Kernel Janitors , MIPS Cc: Andrw Morton , LKML , thomas.koeller@baslerweb.com, ralf@linux-mips.org Subject: [KJ][PATCH]SPIN_LOCK_UNLOCKED cleanup in arch/mips Message-ID: <20070419093516.GA9486@arun.site> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14893 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: milindchoudhary@gmail.com Precedence: bulk X-list: linux-mips SPIN_LOCK_UNLOCKED cleanup,use DEFINE_SPINLOCK instead Signed-off-by: Milind Arun Choudhary --- excite_setup.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c index 42f0eda..2f0e4c0 100644 --- a/arch/mips/basler/excite/excite_setup.c +++ b/arch/mips/basler/excite/excite_setup.c @@ -63,7 +63,7 @@ volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD); volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN); /* Protect access to shared GPI registers */ -spinlock_t titan_lock = SPIN_LOCK_UNLOCKED; +DEFINE_SPINLOCK(titan_lock); int titan_irqflags; -- Milind Arun Choudhary From vagabon.xyz@gmail.com Thu Apr 19 13:25:43 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Apr 2007 13:25:45 +0100 (BST) Received: from ug-out-1314.google.com ([66.249.92.168]:51198 "EHLO ug-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20021638AbXDSMZn (ORCPT ); Thu, 19 Apr 2007 13:25:43 +0100 Received: by ug-out-1314.google.com with SMTP id 40so575416uga for ; Thu, 19 Apr 2007 05:24:42 -0700 (PDT) DKIM-Signature: a=rsa-sha1; c=relaxed/relaxed; d=gmail.com; s=beta; h=domainkey-signature:received:received:message-id:date:reply-to:user-agent:mime-version:to:cc:subject:content-type:content-transfer-encoding:from; b=K+HG7Zshyu23o+xCZ+NDf5pkZH0erbAI3CFJdjH6qhgoYAsJkmhPP2PM2FDvOiksWMBwlk0d7XhgLTVWFpg+TzYSRbyrRwb1KoTTGILGOAf97dRHoNaMr3AH5/UM4KhDk5PSL/TuXBEcvjZUDbUtTnkoIsiXuEF12CaP49Xt2rI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=beta; h=received:message-id:date:reply-to:user-agent:mime-version:to:cc:subject:content-type:content-transfer-encoding:from; b=SlhlqQkCcgAvJt4pIRKSmlZOtJqy8Hf4YRLqTdsb23RgcONJVXxSSO+xoTy0Q4Cl+eE0mseHoLWXVNni6keDwyhIY/lCKZdH/7EmP9pQLRdnYTEGAPIUHmKVskPLKEeKWjgewWvZmvLNOox2N3YkoLLPxVWDChbUowjGoOXQFoU= Received: by 10.82.155.10 with SMTP id c10mr2697969bue.1176985481740; Thu, 19 Apr 2007 05:24:41 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.google.com with ESMTP id b36sm18647ika.2007.04.19.05.24.36; Thu, 19 Apr 2007 05:24:39 -0700 (PDT) Message-ID: <46275F9D.4040408@innova-card.com> Date: Thu, 19 Apr 2007 14:25:01 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: linux-mips , Linux Kernel Mailing List CC: Ralf Baechle Subject: [PATCH] Don't force frame pointers for lockdep on MIPS Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14894 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips From: Franck Bui-Huu Stacktrace support on MIPS doesn't use frame pointers. Since this option considerably increases the size of the kernel code, force lockdep to not use it. Signed-off-by: Franck Bui-Huu --- lib/Kconfig.debug | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 3f3e740..79afd00 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -261,7 +261,7 @@ config LOCKDEP bool depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT select STACKTRACE - select FRAME_POINTER if !X86 + select FRAME_POINTER if !X86 && !MIPS select KALLSYMS select KALLSYMS_ALL -- 1.5.1.1 From hjl@lucon.org Thu Apr 19 18:04:50 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Apr 2007 18:04:54 +0100 (BST) Received: from smtp101.sbc.mail.mud.yahoo.com ([68.142.198.200]:54945 "HELO smtp101.sbc.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20021456AbXDSREu (ORCPT ); Thu, 19 Apr 2007 18:04:50 +0100 Received: (qmail 5219 invoked from network); 19 Apr 2007 17:03:42 -0000 Received: from unknown (HELO lucon.org) (hjjean@sbcglobal.net@75.61.81.46 with login) by smtp101.sbc.mail.mud.yahoo.com with SMTP; 19 Apr 2007 17:03:41 -0000 X-YMail-OSG: xgFMxPAVM1miVK1FOFUzTyFZwOSDaD4l2r2LGlSvCwyMK4SnC5QStBi.vxJGr9KL66i.O7ELr1ehkjth.8dezxC9ovvcjI8l8.BNIPNR2siskAqOWZA- Received: by lucon.org (Postfix, from userid 500) id C414546EEA9; Thu, 19 Apr 2007 10:03:39 -0700 (PDT) Date: Thu, 19 Apr 2007 10:03:39 -0700 From: "H. J. Lu" To: linux-gcc@vger.kernel.org, GNU C Library , gcc@gcc.gnu.org, Mat Hostetter , Warner Losh , linux-mips@linux-mips.org, Ralf Baechle , Linas Vepstas , linux-vax@pergamentum.com Subject: The Linux binutils 2.17.50.0.15 is released Message-ID: <20070419170339.GA14481@lucon.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14895 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hjl@lucon.org Precedence: bulk X-list: linux-mips This is the beta release of binutils 2.17.50.0.15 for Linux, which is based on binutils 2007 0418 in CVS on sourceware.org plus various changes. It is purely for Linux. All relevant patches in patches have been applied to the source tree. You can take a look at patches/README to see what have been applied and in what order they have been applied. Starting from the 2.17.50.0.4 release, the default output section LMA (load memory address) has changed for allocatable sections from being equal to VMA (virtual memory address), to keeping the difference between LMA and VMA the same as the previous output section in the same region. For .data.init_task : { *(.data.init_task) } LMA of .data.init_task section is equal to its VMA with the old linker. With the new linker, it depends on the previous output section. You can use .data.init_task : AT (ADDR(.data.init_task)) { *(.data.init_task) } to ensure that LMA of .data.init_task section is always equal to its VMA. The linker script in the older 2.6 x86-64 kernel depends on the old behavior. You can add AT (ADDR(section)) to force LMA of .data.init_task section equal to its VMA. It will work with both old and new linkers. The x86-64 kernel linker script in kernel 2.6.13 and above is OK. The new x86_64 assembler no longer accepts monitor %eax,%ecx,%edx You should use monitor %rax,%ecx,%edx or monitor which works with both old and new x86_64 assemblers. They should generate the same opcode. The new i386/x86_64 assemblers no longer accept instructions for moving between a segment register and a 32bit memory location, i.e., movl (%eax),%ds movl %ds,(%eax) To generate instructions for moving between a segment register and a 16bit memory location without the 16bit operand size prefix, 0x66, mov (%eax),%ds mov %ds,(%eax) should be used. It will work with both new and old assemblers. The assembler starting from 2.16.90.0.1 will also support movw (%eax),%ds movw %ds,(%eax) without the 0x66 prefix. Patches for 2.4 and 2.6 Linux kernels are available at http://www.kernel.org/pub/linux/devel/binutils/linux-2.4-seg-4.patch http://www.kernel.org/pub/linux/devel/binutils/linux-2.6-seg-5.patch The ia64 assembler is now defaulted to tune for Itanium 2 processors. To build a kernel for Itanium 1 processors, you will need to add ifeq ($(CONFIG_ITANIUM),y) CFLAGS += -Wa,-mtune=itanium1 AFLAGS += -Wa,-mtune=itanium1 endif to arch/ia64/Makefile in your kernel source tree. Please report any bugs related to binutils 2.17.50.0.15 to hjl@lucon.org and http://www.sourceware.org/bugzilla/ Changes from binutils 2.17.50.0.14: 1. Update from binutils 2007 0418. 2. Support Intel SSE4 instructions. 3. Fix linker --fatal-warnings for --warn-shared-textrel. PR 4304. 4. Improve linker error message to identify linker script error location. PR 4090. 5. Fix objcopy to allow removing all sections. PR 4348. 6. Don't print addresses of 32-bit targets as 64-bit values on 64bit host. PR 4292. 7. Improve checking for corrupted input files. PR 4110. 8. Improve alpha linker performance. 9. Add a new linker option, -l:foo. 10. Fix a PPC linker bug. PR 4267. 11. Misc vxworks bug fixes. 12. Misc SH bug fixes. 13. Misc SPU bug fixes. 14. Misc ARM bug fixes. 15. Misc MIPS bug fixes. 16. Misc xtensa bug fixes. Changes from binutils 2.17.50.0.13: 1. Update from binutils 2007 0322. 2. Fix >16byte nop padding regression in x86 assembler. 3. Fix x86-64 disassembler for xchg. PR 4218. 4. Optimize opcode for x86-64 xchg. 5. Allow register operand with x86 nop. 6. Properly handle holes between sections for PE-COFF. PR 4210. 7. Print more PE-COFF info for objdump -p. 8. Report missing matching LO16 relocation for HI16 relocation in mips linker. 9. Use PC-relative relocation for Win64. 10. Fix strip for Solaris. PR 3535. 11. Fix a C++ demangler crash. 12. Some m32c update. 13. Fix misc ARM bugs. Changes from binutils 2.17.50.0.12: 1. Update from binutils 2007 0315. 2. Add EFI/x86-64 support. 3. Fix ELF linker for relocation against STN_UNDEF. PR 3958. 4. Fix ELF linker for SHT_NOBITS section whose VMA > page size. PR 4144. 5. Make assembler and disassembler consistent for "test %eax,%ebx". PR 4027. 6. Fix i386 32bit address wraparound. PR 3966. 7. Allow Linux/i386 linker to read FreeBSD/i386 object files. 8. Fix ELF linker crash upon use of .gnu.warning. sections. PR 3953. 9. Fix ELF linker to issue an error on bad section in segment. PR 4007. 10. Support enabling both x86_64-mingw32 and i386-mingw32. PR 3945. 11. Fix assembler to stabilize .gcc_except_table relaxation. PR 4029. 12. Fix a MIPS linker crash. PR 3852. 13. Fix readelf for h8300-elf. PR 3800. 14. Fix strip for Solaris. PR 3535. 15. Misc xtensa bug fixes. 16. Misc PPC bug fixes. 17. Misc SPU bug fixes. 18. Add support for Toshiba MeP. Changes from binutils 2.17.50.0.11: 1. Update from binutils 2007 0128. 2. Remove duplicate code in x86 assembler. 3. Fix 32bit and 64bit HPPA/ELF. Changes from binutils 2.17.50.0.10: 1. Update from binutils 2007 0125. 2. Support environment variables, LD_SYMBOLIC for -Bsymbolic and LD_SYMBOLIC_FUNCTIONS for -Bsymbolic-functions. 3. Build binutils rpm with LD_SYMBOLIC_FUNCTIONS=1 and reduce PLT relocations in libfd.so by 84%. 4. Enable sharable sections only for ia32, x86-64 and ia64. 5. Properly handle PT_GNU_RELRO segment for objcopy. Changes from binutils 2.17.50.0.9: 1. Update from binutils 2007 0122. 2. Implement sharable section proposal for ia32, x86-64 and ia64: http://groups-beta.google.com/group/generic-abi 3. Implement linker enhancement, -Bsymbolic-functions, --dynamic-list-cpp-new and --dynamic-list-data. PR 3831. 4. Implement new linker switch, --default-script=FILE/-dT FILE. 5. Check EI_OSABI when reading ELF files. PR 3826. 6. Fix x86 assembler error message. PR 3830. 7. Fix a bug in ld testsuite. PR 1283. 8. Don't include archive64.o for 32bit target. PR 3631. 9. Support -z max-page-size and -z common-page-size in user provided linker script. 10. Fix 32bit library support for GNU/kFreeBSD/x86-64. PR 3843. 11. Fix some bugs in Score assembler. PR 3871. 12. Fix various bugs in ARM assembler. PR 3707 and more. 13. Add Fido support. Changes from binutils 2.17.50.0.8: 1. Update from binutils 2007 0103. 2. Fix --wrap linker bug. 3. Improve handling ELF binaries generated by foreign ELF linkers. 4. Various ELF M68K bug fixes. 5. Score bug fixes. 6. Don't read past end of archive elements. PR 3704. 7. Improve .eh_frame_hdr section handling. 8. Fix symbol visibility with comdat/linkonce sections in ELF linker. PR 3666. 9. Fix 4 operand instruction handling in x86 assembler. 10. Properly check the 4th operand in x86 assembler. PR 3712. 11. Fix .cfi_endproc handling in assembler. PR 3607. 12. Various ARM bug fixes. 13. Various PE linker fixes. 14. Improve x86 dissassembler for cmpxchg16b. Changes from binutils 2.17.50.0.7: 1. Update from binutils 2006 1201. 2. Fix "objcopy --only-keep-debug" crash. PR 3609. 3. Fix various ARM ELF bugs. 4. Fix various xtensa bugs. 5. Update x86 disassembler. Changes from binutils 2.17.50.0.6: 1. Update from binutils 2006 1127. 2. Properly set ELF output segment address when the first section in input segment is removed. 3. Better merging of CIEs in linker .eh_frame optimizations. 4. Support .cfi_personality and .cfi_lsda assembler directives. 5. Fix an ARM linker crash. PR 3532. 6. Fix various PPC64 ELF bugs. 7. Mark discarded debug info more thoroughly in linker output. 8. Fix various MIPS ELF bugs. 9. Fix readelf to display program interpreter path > 64 chars. PR 3384. 10. Add support for PowerPC SPU. 11. Properly handle cloned symbols used in relocations in assembler. PR 3469. 12. Update opcode for POPCNT in amdfam10 architecture. Changes from binutils 2.17.50.0.5: 1. Update from binutils 2006 1020. 2. Don't make debug symbol dynamic. PR 3290. 3. Don't page align empty SHF_ALLOC sections, which leads to very large executables. PR 3314. 4. Use a different section index for section relative symbols against removed empty sections. 5. Fix a few ELF EH frame handling bugs. 6. Don't ignore relocation overflow on branches to undefweaks for x86-64. PR 3283. 7. Rename MNI to SSSE3. 8. Properly append symbol list for --dynamic-list. lists. 9. Various ARM ELF fixes. 10. Correct 64bit library search path for Linux/x86 linker with 64bit support. 11. Fix ELF linker to copy OS/PROC specific flags from input section to output section. 12. Fix DW_FORM_ref_addr handling in linker dwarf reader. PR 3191. 13. Fix ELF indirect symbol handling. PR 3351. 14. Fix PT_GNU_RELRO segment handling for SHF_TLS sections. Don't add PT_GNU_RELRO segment when there are no relro sections. PR 3281. 15. Various MIPS ELF fixes. 16. Various Sparc ELF fixes. 17. Various Xtensa ELF fixes. Changes from binutils 2.17.50.0.4: 1. Update from binutils 2006 0927. 2. Fix linker regressions of section address and section relative symbol with empty output section. PR 3223/3267. 3. Fix "strings -T". PR 3257. 4. Fix "objcopy --only-keep-debug". PR 3262. 5. Add Intell iwmmxt2 support. 6. Fix an x86 disassembler bug. PR 3100. Changes from binutils 2.17.50.0.3: 1. Update from binutils 2006 0924. 2. Speed up linker on .o files with debug info on linkonce sections. PR 3111. 3. Added x86-64 PE support. 4. Fix objcopy/strip on .o files with section groups. PR 3181. 5. Fix "ld --hash-style=gnu" crash with gcc 3.4.6. PR 3197. 6. Fix "strip --strip-debug" on .o files generated with "gcc -feliminate-dwarf2-dups". PR 3186. 7. Fix "ld -r" on .o files generated with "gcc -feliminate-dwarf2-dups". PR 3249. 8. Add --dynamic-list to linker to make global symbols dynamic. 9. Fix magic number for EFI ia64. PR 3171. 10. Remove PT_NULL segment for "ld -z relro". PR 3015. 11. Make objcopy to perserve the file formats in archive elements. PR 3110. 12. Optimize x86-64 assembler and fix disassembler for "add32 mov xx,$eax". PR 3235. 13. Improve linker diagnostics. PR 3107. 14. Fix "ld --sort-section name". PR 3009. 15. Updated an x86 disassembler bug. PR 3000. 16. Various updates for PPC, ARM, MIPS, SH, Xtensa. 17. Added Score support. Changes from binutils 2.17.50.0.2: 1. Update from binutils 2006 0715. 2. Add --hash-style to ELF linker with DT_GNU_HASH and SHT_GNU_HASH. 3. Fix a visibility bug in ELF linker (PR 2884). 4. Properly fix the i386 TLS linker bug (PR 2513). 5. Add assembler and dissassembler support for Pentium Pro nops. 6. Optimize x86 nops for Pentium Pro and above. 7. Add -march=/-mtune= to x86 assembler. 8. Fix an ELF linker with TLS common symbols. 9. Improve program header allocation in ELF linker. 10. Improve MIPS, M68K and ARM support. 11. Fix an ELF linker crash when reporting alignment change (PR 2735). 12. Remove unused ELF section symbols (PR 2723). 13. Add --localize-hidden to objcopy. 14. Add AMD SSE4a and ABM new instruction support. 15. Properly handle illegal x86 instructions in group 11 (PR 2829). 16. Add "-z max-page-size=" and "-z common-page-size=" to ELF linker. 17. Fix objcopy for .tbss sections. Changes from binutils 2.17.50.0.1: 1. Update from binutils 2006 0526. 2. Change the x86-64 maximum page size to 2MB. 3. Support --enable-targets=all for 64bit target and host (PR 1485). 4. Properly update CIE/FDE length and align section for .eh_frame section (PR 2655/2657). 5. Properly handle removed ELF section symbols. 6. Fix an ELF linker regression introduced on 2006-04-21. 7. Fix an segfault in PPC ELF linker (PR 2658). 8. Speed up the ELF linker by caching the result of kept section check. 9. Properly create stabs section for ELF. 10. Preserve ELF program header when copying ELF files. 11. Properly handle ELF SHN_LOPROC/SHN_HIOS when checking section index (PR 2607). 12. Misc mips updates. 13. Misc arm updates. 14. Misc xtensa updates. 15. Fix an alpha assembler warning (PR 2598). 16. Fix assembler buffer overflow. 17. Properly disassemble sgdt/sidt for x86-64. Changes from binutils 2.16.91.0.7: 1. Update from binutils 2006 0427. 2. Fix an objcopy regression (PR 2593). 3. Reduce ar memory usage (PR 2467). 4. Allow application specific ELF sections (PR 2537). 5. Fix an i386 TLS linker bug (PR 2513). 6. Speed up ia64 linker by 1300X in some cases (PR 2442). 7. Check illegal immediate register operand in i386 assembler (PR 2533). 8. Fix a strings bug (PR 2584). 9. Better handle corrupted ELF files (PR 2257). 10. Fix a MIPS linker bug (PR 2267). Changes from binutils 2.16.91.0.6: 1. Update from binutils 2006 0317. 2. Support Intel Merom New Instructions in assembler/disassembler. 3. Support Intel new instructions in Montecito. 4. Fix linker "--as-needed" (PR 2434). 5. Fix linker "-s" regression (PR 2462). 6. Fix REP prefix for string instructions in x86 disassembler (PR 2428). 7. Fix the weak undefined symbols in PIE (PR 2218). 8. Fix 2 DWARF reader bugs (PRs 2443, 2338). 9. Improve ELF linker error message (PR 2322). 10. Avoid abort with dynamic symbols in >64K sections (PR 2411). 11. Handle mismatched symbol types for executables (PR 2404). 12. Avoid a linker linkonce regression (PR 2342). Changes from binutils 2.16.91.0.5: 1. Update from binutils 2006 0212. 2. Correct Linux linker search order for DT_NEEDED entries (PR 2290). 3. Fix the x86-64 disassembler for control/debug register moves. 4. Properly handle ELF strip/objcopy with unmodified program header (PR 2258). 5. Improve ELF linker error handling when there are not enough room for program headers (PR 2322). 6. Properly handle weak undefined symbols in PIE (PR 2218). 7. Support new i386/x86-64 TLS relocations. 8. Fix addr2line for linux kernel (PR 2096). 9. Fix an assembler memory leak with --statistics. 10. Avoid an ia64 assembler regression (PR 2117). Changes from binutils 2.16.91.0.4: 1. Update from binutils 2005 1219. 2. Fix a MIPS linker regression (PR 1932). 3. Fix an objcopy bug for ia64 (PR 1991). 4. Fix a linker crash on bad input (PR 2008). 5. Fix 64bit monitor and mwait (PR 1874). Changes from binutils 2.16.91.0.3: 1. Update from binutils 2005 1111. 2. Fix ELF orphan section handling (PR 1467) 3. Fix ELF section attribute handleing (PR 1487). 4. Fix IA64 unwind info dump for relocatable files. (PR 1436). 5. Add DWARF info dump to objdump. 6. Fix SHF_LINK_ORDER handling (PR 1321). 7. Don't allow "ld --just-symbols" on DSO (PR 1263). 8. Fix a "ld -u" crash on TLS symbol (PR 1301). 9. Fix an IA64 linker crash (PR 1247). 10. Fix a MIPS linker bug (PR 1150). 11. Fix a M68K linker bug (PR 1775). 12. Fix an ELF symbol versioning linker bug (PR 1540). 13. Improve linker error handling (PR 1208). 14. Add new SPARC processors to SunOS for objcopy (PR 1472). 15. Add "@file" to read options from a file. 16. Add assembler weakref support. Changes from binutils 2.16.91.0.2: 1. Update from binutils 2005 0821. 2. Support x86-64 medium model. 3. Fix "objdump -S --adjust-vma=xxx" (PR 1179). 4. Reduce R_IA64_NONE relocations from R_IA64_LDXMOV relaxation. 5. Fix x86 linker regression for dosemu. 6. Add "readelf -t/--section-details" to display section details. 7. Fix "as -al=file" regression (PR 1118). Changes from binutils 2.16.91.0.1: 1. Update from binutils 2005 0720. 2. Add Intel VMX support. 3. Add AMD SVME support. 4. Add x86-64 new relocations for medium model. 5. Fix a PIE regression (PR 975). 6. Fix an x86_64 signed 32bit displacement regression. 7. Fix PPC PLT (PR 1004). 8. Improve empty section removal. Changes from binutils 2.16.90.0.3: 1. Update from binutils 2005 0622. 2. Fix a linker versioning bug exposed by gcc 4 (PR 1022/1023/1025). 3. Optimize ia64 br->brl relaxation (PR 834). 4. Improve linker empty section removal. 5. Fix DWARF 2 line number reporting (PR 990). 6. Fix DWARF 2 line number reporting regression on assembly file (PR 1000). Changes from binutils 2.16.90.0.2: 1. Update from binutils 2005 0510. 2. Update ia64 assembler to support comdat group section generated by gcc 4 (PR 940). 3. Fix a linker crash on bad input (PR 939). 4. Fix a sh64 assembler regression (PR 936). 5. Support linker script on executable (PR 882). 6. Fix the linker -pie regression (PR 878). 7. Fix an x86_64 disassembler bug (PR 843). 8. Fix a PPC linker regression. 9. Misc speed up. Changes from binutils 2.16.90.0.1: 1. Update from binutils 2005 0429. 2. Fix an ELF linker regression (PR 815). 3. Fix an empty section removal related bug. 4. Fix an ia64 linker regression (PR 855). 5. Don't allow local symbol to be equated common/undefined symbols (PR 857). 6. Fix the ia64 linker to handle local dynamic symbol error reporting. 7. Make non-debugging reference to discarded section an error (PR 858). 8. Support Sparc/TLS. 9. Support rpm build with newer rpm. 10. Fix an alpha linker regression. 11. Fix the non-gcc build regression. Changes from binutils 2.15.94.0.2.2: 1. Update from binutils 2005 0408. 2. The i386/x86_64 assemblers no longer accept instructions for moving between a segment register and a 32bit memory location. 3. The x86_64 assembler now allows movq between a segment register and a 64bit general purpose register. 4. 20x Speed up linker for input files with >64K sections. 5. Properly report ia64 linker relaxation failures. 6. Support tuning ia64 assembler for Itanium 2 processors. 7. Linker will remove empty unused output sections. 8. Add -N to readelf to display full section names. 9. Fix the ia64 linker to support linkonce text sections without unwind sections. 10. More unwind directive checkings in the ia64 assembler. 11. Speed up linker with wildcard handling. 12. Fix readelf to properly dump .debug_ranges and .debug_loc sections. Changes from binutils 2.15.94.0.2: 1. Fix greater than 64K section support in linker. 2. Properly handle i386 and x86_64 protected symbols in linker. 3. Fix readelf for LEB128 on 64bit hosts. 4. Speed up readelf for section group process. 5. Include ia64 texinfo pages. 6. Change ia64 assembler to check hint.b for Montecito. 7. Improve relaxation failure report in ia64 linker. 8. Fix ia64 linker to allow relax backward branch in the same section. Changes from binutils 2.15.94.0.1: 1. Update from binutils 2004 1220. 2. Fix strip for TLS symbol references. Changes from binutils 2.15.92.0.2: 1. Update from binutils 2004 1121. 2. Put ia64 .ctors/.dtors sections next to small data section for Intel ia64 compiler. 3. Fix -Bdynamic/-Bstatic handling for linker script. 4. Provide more information on relocation overflow. 5. Add --sort-section to linker. 6. Support icc 8.1 unwind info in readelf. 7. Fix the infinite loop bug on bad input in the ia64 assembler. 8. Fix ia64 SECREL relocation in linker. 9. Fix a section group memory leak in readelf. Changes from binutils 2.15.91.0.2: 1. Update from binutils 2004 0927. 2. Work around a section header bug in Intel ia64 compiler. 3. Fix an unwind directive bug in the ia64 assembler. 4. Fix various PPC bugs. 5. Update ARM support. 6. Fix an x86-64 linker warning while building Linux kernel. Changes from binutils 2.15.91.0.1: 1. Update from binutils 2004 0727. 2. Fix the x86_64 linker to prevent non-PIC code in shared library. 3. Fix the ia64 linker to warn the relotable files which can't be relaxed. 4. Fix the comdat group support. Allow mix single-member comdat group with linkonce section. 5. Added --add-needed/--no-add-needed options to linker. 6. Fix the SHF_LINK_ORDER support. 7. Fix the ia64 assembler for multiple sections with the same name and SHT_IA_64_UNWIND sections. 8. Fix the ia64 assembler for merge section and relaxation. Changes from binutils 2.15.90.0.3: 1. Update from binutils 2004 0527. 2. Fix -x auto option in the ia64 assembler. 3. Add the AR check in the ia64 assembler. 4. Fix the section group support. 5. Add a new -z relro linker option. 6. Fix an exception section placement bug in linker. 7. Add .serialize.data and .serialize.instruction to the ia64 assembler. Changes from binutils 2.15.90.0.2: 1. Update from binutils 2004 0415. 2. Fix the linker for weak undefined symbol handling. 3. Fix the ELF/Sparc and ELF/Sparc64 linker for statically linking PIC code. Changes from binutils 2.15.90.0.1.1: 1. Update from binutils 2004 0412. 2. Add --as-needed/--no-as-needed to linker. 3. Fix -z defs in linker. 4. Always reserve the memory for ia64 dynamic linker. 5. Fix a race condition in ia64 lazy binding. Changes from binutils 2.15.90.0.1: 1. Fixed an ia64 assembler bug. 2. Install the assembler man page. Changes from binutils 2.14.90.0.8: 1. Update from binutils 2004 0303. 2. Fixed linker for undefined symbols with non-default visibility. 3. Sped up linker weakdef symbol handling. 4. Fixed mixing ELF32 and ELF64 object files in archive. 5. Added ia64 linker brl optimization. 6. Fixed ia64 linker to disallow invalid dynamic relocations. 7. Fixed DT_TEXTREL handling in ia64 linker. 8. Fixed alignment handling in ia64 assembler. 9. Improved ia64 assembler unwind table handling. Changes from binutils 2.14.90.0.7: 1. Update from binutils 2004 0114. 2. Fixed an ia64 assembler unwind table bug. 3. Better handle IPF linker relaxation overflow. 4. Fixed misc PPC bugs. Changes from binutils 2.14.90.0.6: 1. Update from binutils 2003 1029. 2. Allow type changes for undefined symbols. 3. Fix EH frame optimization. 4. Fix the check for undefined versioned symbol with wildcard. 5. Support generating code for Itanium. 6. Detect and warn bad symbol index. 7. Update IPF assemebler DV check. Changes from binutils 2.14.90.0.5: 1. Update from binutils 2003 0820. 2. No longer use section names for ELF section types nor flags. 3. Fix some ELF/IA64 linker bugs. 4. Fix some ELF/ppc bugs. 5. Add archive support to readelf. Changes from binutils 2.14.90.0.4.1: 1. Update from binutils 2003 0722. 2. Fix an ELF/mips linker bug. 3. Fix an ELF/hpppa linker bug. 4. Fix an ELF/ia64 assembler bug. 5. Fix a linkonce support with C++ debug. 6. A new working C++ demangler. 7. Various alpha, mips, ia64, ... bug fixes. 8. Support for the current gcc and glibc. Changes from binutils 2.14.90.0.4: 1. Fix an ia64 assembler hint@pause bug. 2. Support Intel Prescott New Instructions. Changes from binutils 2.14.90.0.3: 1. Work around the brain dead libtool. Changes from binutils 2.14.90.0.2: 1. Update from binutils 2003 0523. 2. Fix 2 ELF visibility bugs. 3. Fix ELF/ppc linker bugs. Changes from binutils 2.14.90.0.1: 1. Update from binutils 2003 0515. 2. Fix various ELF visibility bugs. 3. Fix some ia64 linker bugs. 4. Add more IAS compatibilities to ia64 assembler. Changes from binutils 2.13.90.0.20: 1. Update from binutils 2003 0505. 2. Fix various ELF visibility bugs. 3. Fix some ia64 linker bugs. 4. Fix some ia64 assembler bugs. 5. Add some IAS compatibilities to ia64 assembler. 6. Fix ELF common symbol alignment. 7. Fix ELF weak symbol handling. Changes from binutils 2.13.90.0.18: 1. Update from binutils 2003 0319. 2. Fix an ia64 linker brl relaxation bug. 3. Fix some ELF/ppc linker bugs. Changes from binutils 2.13.90.0.16: 1. Update from binutils 2003 0121. 2. Fix an ia64 gas bug. 3. Fix some TLS bugs. 4. Fix some ELF/ppc bugs. 5. Fix an ELF/m68k bug. 2. Include /usr/bin/c++filt. Changes from binutils 2.13.90.0.14: 1. Update from binutils 2002 1126. 2. Include /usr/bin/c++filt. 3. Fix "ld -r" with execption handling. Changes from binutils 2.13.90.0.10: 1. Update from binutils 2002 1114. 2. Fix ELF/alpha bugs. 3. Fix an ELF/i386 assembler bug. Changes from binutils 2.13.90.0.4: 1. Update from binutils 2002 1010. 2. More ELF/PPC linker bug fixes. 3. Fix an ELF/alpha linker bug. 4. Fix an ELF/sparc linker bug to support Solaris. 5. More TLS updates. Changes from binutils 2.13.90.0.3: 1. Update from binutils 2002 0814. 2. Fix symbol versioning bugs for gcc 3.2. 3. Fix mips gas. Changes from binutils 2.13.90.0.2: 1. Update from binutils 2002 0809. 2. Fix a mips gas compatibility bug. 3. Fix an x86 TLS bfd bug. 4. Fix an x86 PIC gas bug. 5. Improve symbol versioning support. The file list: 1. binutils-2.17.50.0.15.tar.bz2. Source code. 2. binutils-2.17.50.0.13-2.17.50.0.15.diff.bz2. Patch against the previous beta source code. 3. binutils-2.17.50.0.15.i686.tar.bz2. IA-32 binary tar ball for RedHat EL 4. 4. binutils-2.17.50.0.15.ia64.tar.bz2. IA-64 binary tar ball for RedHat EL 4. 5. binutils-2.17.50.0.15.x86_64.tar.bz2. X64_64 binary tar ball for RedHat EL 4. The primary sites for the beta Linux binutils are: 1. http://www.kernel.org/pub/linux/devel/binutils/ Thanks. H.J. Lu hjl@lucon.org 04/19/2007 From anemo@mba.ocn.ne.jp Fri Apr 20 10:39:31 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Apr 2007 10:39:32 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:714 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20021666AbXDTJjb (ORCPT ); Fri, 20 Apr 2007 10:39:31 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Fri, 20 Apr 2007 18:39:29 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 0F24641BCF; Fri, 20 Apr 2007 18:39:27 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 020F220502; Fri, 20 Apr 2007 18:39:27 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id l3K9dKW0096444; Fri, 20 Apr 2007 18:39:24 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Fri, 20 Apr 2007 18:39:20 +0900 (JST) Message-Id: <20070420.183920.128619859.nemoto@toshiba-tops.co.jp> To: fxzhang@ict.ac.cn Cc: ralf@linux-mips.org, tiansm@lemote.com, perex@suse.cz, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, zhangfx@lemote.com Subject: Re: [PATCH 16/16] alsa sound support for mips From: Atsushi Nemoto In-Reply-To: <4626276E.3000303@ict.ac.cn> References: <11766507674145-git-send-email-tiansm@lemote.com> <20070418135412.GG3938@linux-mips.org> <4626276E.3000303@ict.ac.cn> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14896 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Wed, 18 Apr 2007 22:13:02 +0800, Fuxin Zhang wrote: > >> +#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) > >> + /* all mmap using uncached mode */ > >> + area->vm_page_prot = pgprot_noncached(area->vm_page_prot); > >> + area->vm_flags |= ( VM_RESERVED | VM_IO); > >> > > > > VM_RESERVED will prevent the buffer from being freed. I assume that is > > another workaround for some kernel subsystem blowing up when being fed a > > pointer to an uncached RAM address? This smells like a memory leak. > > > > > Oh, VM_RESERVED should be a memory leak problem, we can remove it. > I don't remember any case of other subsystem's problem, just did not > think much > to add those flags. I think pgprot_noncached() is needed because user mapping for a DMA buffer (runtime->dma_area) should be uncache. If so, doing this in snd_pcm_mmap() looks a bit suspicious. It seems snd_pcm_mmap_data() is a place to do such an adjustment. But for now, both snd_pcm_mmap_status() and snd_pcm_mmap_control() returns -ENXIO for MIPS so this is not a real problem. And I wonder if VM_IO is really needed. The area is a DMA buffer, _not_ a memory mapped IO area, isn't it? > > I would suggest to get rid of this ifdef with a new arch-specific function > > like vmap_io_buffer which will do whatever a platform seems fit for this > > case? > > > I think arch-specific function is the correct way, but don't know what > the alsa gods think. JFYI, there were some discussions on this topic a while ago: http://lkml.org/lkml/2006/1/25/117 and I'v seen MIPS version of dma_mmap_coherent(), etc. somewhere... --- Atsushi Nemoto From alan@lxorguk.ukuu.org.uk Mon Apr 23 15:03:08 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Apr 2007 15:03:12 +0100 (BST) Received: from outpipe-village-512-1.bc.nu ([81.2.110.250]:50397 "EHLO the-village.bc.nu") by ftp.linux-mips.org with ESMTP id S20021675AbXDWODI (ORCPT ); Mon, 23 Apr 2007 15:03:08 +0100 Received: from the-village.bc.nu (localhost.localdomain [127.0.0.1]) by the-village.bc.nu (8.13.8/8.13.8) with ESMTP id l3NE6ewh007881; Mon, 23 Apr 2007 15:06:40 +0100 Date: Mon, 23 Apr 2007 15:06:40 +0100 From: Alan Cox To: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH] IOC3: Switch to pci refcounting safe APIs Message-ID: <20070423150640.1faf693f@the-village.bc.nu> X-Mailer: Claws Mail 2.9.1 (GTK+ 2.10.8; i386-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14897 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alan@lxorguk.ukuu.org.uk Precedence: bulk X-list: linux-mips Untested as I don't have any IOC3 hardware so if someone could give this a check that would be great. Signed-off-by: Alan Cox diff -u --new-file --recursive --exclude-from /usr/src/exclude linux.vanilla-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c linux-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c --- linux.vanilla-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c 2007-04-12 14:15:04.000000000 +0100 +++ linux-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c 2007-04-23 11:49:32.708000752 +0100 @@ -1103,20 +1103,30 @@ * MiniDINs; all other subdevices are left swinging in the wind, leave * them disabled. */ -static inline int ioc3_is_menet(struct pci_dev *pdev) + +static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int dev) +{ + struct pci_dev *dev = pci_get_bus_and_slot(pdev->bus->number, + PCI_DEVFN(dev, 0)); + int ret = 0; + + if (dev) { + if (dev->vendor == PCI_VENDOR_ID_SGI && + dev->device == PCI_DEVICE_ID_SGI_IOC3) + ret = 1; + pci_dev_put(dev); + } + return ret; +} + +static int ioc3_is_menet(struct pci_dev *pdev) { struct pci_dev *dev; - return pdev->bus->parent == NULL - && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(0, 0))) - && dev->vendor == PCI_VENDOR_ID_SGI - && dev->device == PCI_DEVICE_ID_SGI_IOC3 - && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(1, 0))) - && dev->vendor == PCI_VENDOR_ID_SGI - && dev->device == PCI_DEVICE_ID_SGI_IOC3 - && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(2, 0))) - && dev->vendor == PCI_VENDOR_ID_SGI - && dev->device == PCI_DEVICE_ID_SGI_IOC3; + return pdev->bus->parent == NULL && + ioc3_adjacent_is_ioc3(pdev, 0) && + ioc3_adjacent_is_ioc3(pdev, 1) && + ioc3_adjacent_is_ioc3(pdev, 2)); } #ifdef CONFIG_SERIAL_8250 From sshtylyov@ru.mvista.com Mon Apr 23 15:09:31 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Apr 2007 15:09:33 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:63222 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20021652AbXDWOJb (ORCPT ); Mon, 23 Apr 2007 15:09:31 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id BDCE43ECA; Mon, 23 Apr 2007 07:08:58 -0700 (PDT) Message-ID: <462CBE33.2060208@ru.mvista.com> Date: Mon, 23 Apr 2007 18:09:55 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Alan Cox Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] IOC3: Switch to pci refcounting safe APIs References: <20070423150640.1faf693f@the-village.bc.nu> In-Reply-To: <20070423150640.1faf693f@the-village.bc.nu> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14898 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Alan Cox wrote: > Untested as I don't have any IOC3 hardware so if someone could give this > a check that would be great. > Signed-off-by: Alan Cox > diff -u --new-file --recursive --exclude-from /usr/src/exclude linux.vanilla-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c linux-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c > --- linux.vanilla-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c 2007-04-12 14:15:04.000000000 +0100 > +++ linux-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c 2007-04-23 11:49:32.708000752 +0100 > @@ -1103,20 +1103,30 @@ > * MiniDINs; all other subdevices are left swinging in the wind, leave > * them disabled. > */ > -static inline int ioc3_is_menet(struct pci_dev *pdev) > + > +static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int dev) > +{ > + struct pci_dev *dev = pci_get_bus_and_slot(pdev->bus->number, > + PCI_DEVFN(dev, 0)); The same question: isn't pci_get_bus() better in this case? > + int ret = 0; > + > + if (dev) { > + if (dev->vendor == PCI_VENDOR_ID_SGI && > + dev->device == PCI_DEVICE_ID_SGI_IOC3) > + ret = 1; > + pci_dev_put(dev); > + } > + return ret; > +} > + > +static int ioc3_is_menet(struct pci_dev *pdev) > { > struct pci_dev *dev; > > - return pdev->bus->parent == NULL > - && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(0, 0))) > - && dev->vendor == PCI_VENDOR_ID_SGI > - && dev->device == PCI_DEVICE_ID_SGI_IOC3 > - && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(1, 0))) > - && dev->vendor == PCI_VENDOR_ID_SGI > - && dev->device == PCI_DEVICE_ID_SGI_IOC3 > - && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(2, 0))) > - && dev->vendor == PCI_VENDOR_ID_SGI > - && dev->device == PCI_DEVICE_ID_SGI_IOC3; > + return pdev->bus->parent == NULL && > + ioc3_adjacent_is_ioc3(pdev, 0) && > + ioc3_adjacent_is_ioc3(pdev, 1) && > + ioc3_adjacent_is_ioc3(pdev, 2)); > } I don't see the point of using refcounting API in such cases but well... WBR, Sergei From alan@lxorguk.ukuu.org.uk Mon Apr 23 15:15:43 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Apr 2007 15:15:45 +0100 (BST) Received: from outpipe-village-512-1.bc.nu ([81.2.110.250]:61393 "EHLO the-village.bc.nu") by ftp.linux-mips.org with ESMTP id S20021689AbXDWOPn (ORCPT ); Mon, 23 Apr 2007 15:15:43 +0100 Received: from the-village.bc.nu (localhost.localdomain [127.0.0.1]) by the-village.bc.nu (8.13.8/8.13.8) with ESMTP id l3NEJICR007921; Mon, 23 Apr 2007 15:19:18 +0100 Date: Mon, 23 Apr 2007 15:19:18 +0100 From: Alan Cox To: Sergei Shtylyov Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] IOC3: Switch to pci refcounting safe APIs Message-ID: <20070423151918.477ffb6a@the-village.bc.nu> In-Reply-To: <462CBE33.2060208@ru.mvista.com> References: <20070423150640.1faf693f@the-village.bc.nu> <462CBE33.2060208@ru.mvista.com> X-Mailer: Claws Mail 2.9.1 (GTK+ 2.10.8; i386-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14899 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alan@lxorguk.ukuu.org.uk Precedence: bulk X-list: linux-mips > > +static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int dev) > > +{ > > + struct pci_dev *dev = pci_get_bus_and_slot(pdev->bus->number, > > + PCI_DEVFN(dev, 0)); > > The same question: isn't pci_get_bus() better in this case? Makes no real difference, but if you know the MIPS tree never ends up with pdev->bus = NULL for the root bus then its a trivial change > I don't see the point of using refcounting API in such cases but well... Two reasons 1. It makes the entire system more consistent 2. It means we can remove the (usually) unsafe pci_find_slot API (and #3 sort of... it means the pci fake hotplug testing works with this device too) From sshtylyov@ru.mvista.com Mon Apr 23 15:20:37 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Apr 2007 15:20:39 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:13559 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20021703AbXDWOUh (ORCPT ); Mon, 23 Apr 2007 15:20:37 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 8D67D3ECA; Mon, 23 Apr 2007 07:20:35 -0700 (PDT) Message-ID: <462CC0EC.6010600@ru.mvista.com> Date: Mon, 23 Apr 2007 18:21:32 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Alan Cox Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] IOC3: Switch to pci refcounting safe APIs References: <20070423150640.1faf693f@the-village.bc.nu> <462CBE33.2060208@ru.mvista.com> <20070423151918.477ffb6a@the-village.bc.nu> In-Reply-To: <20070423151918.477ffb6a@the-village.bc.nu> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14900 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Alan Cox wrote: >>>+static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int dev) >>>+{ >>>+ struct pci_dev *dev = pci_get_bus_and_slot(pdev->bus->number, >>>+ PCI_DEVFN(dev, 0)); >> >> The same question: isn't pci_get_bus() better in this case? > Makes no real difference, but if you know the MIPS tree never ends up pci_get_bus_and_slot() walks all device tree, pci_get_bus() walks only one bus. > with pdev->bus = NULL for the root bus then its a trivial change You'll get kernel oops in this case anyway as you're dereferencing pdev->bus. >> I don't see the point of using refcounting API in such cases but well... > Two reasons > > 1. It makes the entire system more consistent > 2. It means we can remove the (usually) unsafe pci_find_slot API > (and #3 sort of... it means the pci fake hotplug testing works with this > device too) Ah... Thanks for the explanation. WBR, Sergei From ralf@linux-mips.org Mon Apr 23 15:35:14 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Apr 2007 15:35:16 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:33747 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20021740AbXDWOfO (ORCPT ); Mon, 23 Apr 2007 15:35:14 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3NEZ8fu009766; Mon, 23 Apr 2007 15:35:08 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3NEZ79x009765; Mon, 23 Apr 2007 15:35:07 +0100 Date: Mon, 23 Apr 2007 15:35:07 +0100 From: Ralf Baechle To: Alan Cox Cc: Sergei Shtylyov , linux-mips@linux-mips.org Subject: Re: [PATCH] IOC3: Switch to pci refcounting safe APIs Message-ID: <20070423143507.GA8877@linux-mips.org> References: <20070423150640.1faf693f@the-village.bc.nu> <462CBE33.2060208@ru.mvista.com> <20070423151918.477ffb6a@the-village.bc.nu> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070423151918.477ffb6a@the-village.bc.nu> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14901 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Apr 23, 2007 at 03:19:18PM +0100, Alan Cox wrote: > > > +static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int dev) > > > +{ > > > + struct pci_dev *dev = pci_get_bus_and_slot(pdev->bus->number, > > > + PCI_DEVFN(dev, 0)); > > > > The same question: isn't pci_get_bus() better in this case? > > Makes no real difference, but if you know the MIPS tree never ends up > with pdev->bus = NULL for the root bus then its a trivial change That's the case on MIPS. > > I don't see the point of using refcounting API in such cases but well... > > Two reasons > > 1. It makes the entire system more consistent > 2. It means we can remove the (usually) unsafe pci_find_slot API > > (and #3 sort of... it means the pci fake hotplug testing works with this > device too) The patch looks ok to me: Acked-by: Ralf Baechle Longer term MENET should be handled differently but this patch certainly doesn't make things worse. Ralf From alan@lxorguk.ukuu.org.uk Mon Apr 23 16:15:00 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Apr 2007 16:15:01 +0100 (BST) Received: from outpipe-village-512-1.bc.nu ([81.2.110.250]:28546 "EHLO the-village.bc.nu") by ftp.linux-mips.org with ESMTP id S20021740AbXDWPPA (ORCPT ); Mon, 23 Apr 2007 16:15:00 +0100 Received: from the-village.bc.nu (localhost.localdomain [127.0.0.1]) by the-village.bc.nu (8.13.8/8.13.8) with ESMTP id l3NFIZMM008133; Mon, 23 Apr 2007 16:18:35 +0100 Date: Mon, 23 Apr 2007 16:18:35 +0100 From: Alan Cox To: Ralf Baechle Cc: Sergei Shtylyov , linux-mips@linux-mips.org Subject: Re: [PATCH] IOC3: Switch to pci refcounting safe APIs Message-ID: <20070423161835.4ae29965@the-village.bc.nu> In-Reply-To: <20070423143507.GA8877@linux-mips.org> References: <20070423150640.1faf693f@the-village.bc.nu> <462CBE33.2060208@ru.mvista.com> <20070423151918.477ffb6a@the-village.bc.nu> <20070423143507.GA8877@linux-mips.org> X-Mailer: Claws Mail 2.9.1 (GTK+ 2.10.8; i386-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14902 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alan@lxorguk.ukuu.org.uk Precedence: bulk X-list: linux-mips > > Makes no real difference, but if you know the MIPS tree never ends up > > with pdev->bus = NULL for the root bus then its a trivial change > > That's the case on MIPS. Revised patch then --- Convert the IOC3 driver to use ref counting pci interfaces so that we can obsolete the (usually unsafe) pci_find_{slot/device} interfaces and avoid future authors writing hotplug-unsafe device drivers. Signed-off-by: Alan Cox diff -u --new-file --recursive --exclude-from /usr/src/exclude linux.vanilla-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c linux-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c --- linux.vanilla-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c 2007-04-12 14:15:04.000000000 +0100 +++ linux-2.6.21-rc6-mm1/drivers/net/ioc3-eth.c 2007-04-23 15:58:21.431489816 +0100 @@ -1103,20 +1103,29 @@ * MiniDINs; all other subdevices are left swinging in the wind, leave * them disabled. */ -static inline int ioc3_is_menet(struct pci_dev *pdev) + +static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int dev) +{ + struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(dev, 0)); + int ret = 0; + + if (dev) { + if (dev->vendor == PCI_VENDOR_ID_SGI && + dev->device == PCI_DEVICE_ID_SGI_IOC3) + ret = 1; + pci_dev_put(dev); + } + return ret; +} + +static int ioc3_is_menet(struct pci_dev *pdev) { struct pci_dev *dev; - return pdev->bus->parent == NULL - && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(0, 0))) - && dev->vendor == PCI_VENDOR_ID_SGI - && dev->device == PCI_DEVICE_ID_SGI_IOC3 - && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(1, 0))) - && dev->vendor == PCI_VENDOR_ID_SGI - && dev->device == PCI_DEVICE_ID_SGI_IOC3 - && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(2, 0))) - && dev->vendor == PCI_VENDOR_ID_SGI - && dev->device == PCI_DEVICE_ID_SGI_IOC3; + return pdev->bus->parent == NULL && + ioc3_adjacent_is_ioc3(pdev, 0) && + ioc3_adjacent_is_ioc3(pdev, 1) && + ioc3_adjacent_is_ioc3(pdev, 2)); } #ifdef CONFIG_SERIAL_8250 From anemo@mba.ocn.ne.jp Tue Apr 24 17:54:56 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Apr 2007 17:54:59 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:64250 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20022261AbXDXQy4 (ORCPT ); Tue, 24 Apr 2007 17:54:56 +0100 Received: from localhost (p3087-ipad201funabasi.chiba.ocn.ne.jp [222.146.66.87]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id BA42DA56E; Wed, 25 Apr 2007 01:54:49 +0900 (JST) Date: Wed, 25 Apr 2007 01:54:50 +0900 (JST) Message-Id: <20070425.015450.25909765.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org, jeff@garzik.org, ralf@linux-mips.org, sshtylyov@ru.mvista.com, akpm@linux-foundation.org Subject: [PATCH 1/3] ne: Add platform_driver From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14903 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Currently ne.c has some codes to support RBTX49XX boards but it is not complete. Instead of adding more hacks to fix it, this patch add an generic platform_driver interface to the driver and let RBTX49XX use it. This is a first step. * Add platform_driver interface to ne driver. (Existing legacy ports did not covered by this ne_driver for now) * Make ioaddr 'unsigned long'. * Move a printk down to show dev->name assigned in register_netdev. Signed-off-by: Atsushi Nemoto --- drivers/net/ne.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 95 insertions(+), 8 deletions(-) diff --git a/drivers/net/ne.c b/drivers/net/ne.c index a5c4199..b8a181f 100644 --- a/drivers/net/ne.c +++ b/drivers/net/ne.c @@ -51,6 +51,7 @@ static const char version2[] = #include #include #include +#include #include #include @@ -146,7 +147,7 @@ bad_clone_list[] __initdata = { # define DCR_VAL 0x49 #endif -static int ne_probe1(struct net_device *dev, int ioaddr); +static int ne_probe1(struct net_device *dev, unsigned long ioaddr); static int ne_probe_isapnp(struct net_device *dev); static int ne_open(struct net_device *dev); @@ -184,7 +185,7 @@ static void ne_block_output(struct net_device *dev, const int count, static int __init do_ne_probe(struct net_device *dev) { - unsigned int base_addr = dev->base_addr; + unsigned long base_addr = dev->base_addr; #ifndef MODULE int orig_irq = dev->irq; #endif @@ -285,7 +286,7 @@ static int __init ne_probe_isapnp(struct net_device *dev) return -ENODEV; } -static int __init ne_probe1(struct net_device *dev, int ioaddr) +static int __init ne_probe1(struct net_device *dev, unsigned long ioaddr) { int i; unsigned char SA_prom[32]; @@ -324,7 +325,7 @@ static int __init ne_probe1(struct net_device *dev, int ioaddr) if (ei_debug && version_printed++ == 0) printk(KERN_INFO "%s" KERN_INFO "%s", version1, version2); - printk(KERN_INFO "NE*000 ethercard probe at %#3x:", ioaddr); + printk(KERN_INFO "NE*000 ethercard probe at %#3lx:", ioaddr); /* A user with a poor card that fails to ack the reset, or that does not have a valid 0x57,0x57 signature can still use this @@ -516,8 +517,7 @@ static int __init ne_probe1(struct net_device *dev, int ioaddr) } #endif - printk("\n%s: %s found at %#x, using IRQ %d.\n", - dev->name, name, ioaddr, dev->irq); + printk("\n"); ei_status.name = name; ei_status.tx_start_page = start_page; @@ -547,6 +547,8 @@ static int __init ne_probe1(struct net_device *dev, int ioaddr) ret = register_netdev(dev); if (ret) goto out_irq; + printk(KERN_INFO "%s: %s found at %#lx, using IRQ %d.\n", + dev->name, name, ioaddr, dev->irq); return 0; out_irq: @@ -807,6 +809,86 @@ retry: return; } +static int __init ne_drv_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct resource *res; + int err, irq; + + res = platform_get_resource(pdev, IORESOURCE_IO, 0); + irq = platform_get_irq(pdev, 0); + if (!res || irq < 0) + return -ENODEV; + + dev = alloc_ei_netdev(); + if (!dev) + return -ENOMEM; + dev->irq = irq; + dev->base_addr = res->start; + err = do_ne_probe(dev); + if (err) { + free_netdev(dev); + return err; + } + platform_set_drvdata(pdev, dev); + return 0; +} + +static int __exit ne_drv_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + + unregister_netdev(dev); + free_irq(dev->irq, dev); + release_region(dev->base_addr, NE_IO_EXTENT); + free_netdev(dev); + return 0; +} + +#ifdef CONFIG_PM +static int ne_drv_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct net_device *dev = platform_get_drvdata(pdev); + + if (netif_running(dev)) + netif_device_detach(dev); + return 0; +} + +static int ne_drv_resume(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + + if (netif_running(dev)) { + ne_reset_8390(dev); + NS8390_init(dev, 1); + netif_device_attach(dev); + } + return 0; +} +#endif + +static struct platform_driver ne_driver = { + .remove = __exit_p(ne_drv_remove), +#ifdef CONFIG_PM + .suspend = ne_drv_suspend, + .resume = ne_drv_resume, +#endif + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init ne_init(void) +{ + return platform_driver_probe(&ne_driver, ne_drv_probe); +} + +static void __exit ne_exit(void) +{ + platform_driver_unregister(&ne_driver); +} #ifdef MODULE #define MAX_NE_CARDS 4 /* Max number of NE cards per module */ @@ -832,6 +914,7 @@ ISA device autoprobes on a running machine are not recommended anyway. */ int __init init_module(void) { int this_dev, found = 0; + int plat_found = !ne_init(); for (this_dev = 0; this_dev < MAX_NE_CARDS; this_dev++) { struct net_device *dev = alloc_ei_netdev(); @@ -845,7 +928,7 @@ int __init init_module(void) continue; } free_netdev(dev); - if (found) + if (found || plat_found) break; if (io[this_dev] != 0) printk(KERN_WARNING "ne.c: No NE*000 card found at i/o = %#x\n", io[this_dev]); @@ -853,7 +936,7 @@ int __init init_module(void) printk(KERN_NOTICE "ne.c: You must supply \"io=0xNNN\" value(s) for ISA cards.\n"); return -ENXIO; } - if (found) + if (found || plat_found) return 0; return -ENODEV; } @@ -871,6 +954,7 @@ void __exit cleanup_module(void) { int this_dev; + ne_exit(); for (this_dev = 0; this_dev < MAX_NE_CARDS; this_dev++) { struct net_device *dev = dev_ne[this_dev]; if (dev) { @@ -880,4 +964,7 @@ void __exit cleanup_module(void) } } } +#else /* MODULE */ +module_init(ne_init); +module_exit(ne_exit); #endif /* MODULE */ From anemo@mba.ocn.ne.jp Tue Apr 24 17:55:52 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Apr 2007 17:55:56 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:20421 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20022267AbXDXQzw (ORCPT ); Tue, 24 Apr 2007 17:55:52 +0100 Received: from localhost (p3087-ipad201funabasi.chiba.ocn.ne.jp [222.146.66.87]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 6E2F5A193; Wed, 25 Apr 2007 01:55:48 +0900 (JST) Date: Wed, 25 Apr 2007 01:55:49 +0900 (JST) Message-Id: <20070425.015549.108742168.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org, jeff@garzik.org, ralf@linux-mips.org, sshtylyov@ru.mvista.com, akpm@linux-foundation.org Subject: [PATCH 2/3] ne: MIPS: Use platform_driver for ne on RBTX49XX From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14904 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips This patch lets RBTX49XX boards use generic platform_driver interface for the ne driver. * Use platform_device to pass ioaddr and irq to the ne driver. * Remove unnecessary ifdefs for RBTX49XX from the ne driver. * Make the ne driver selectable on these boards regardless of CONFIG_ISA * Add an ifdef for netcard_portlist[] to avoid unnecessary auto-probe. (I'm not sure M32R needs auto-probe but it is current behavior) Signed-off-by: Atsushi Nemoto --- .../toshiba_rbtx4927/toshiba_rbtx4927_setup.c | 19 +++++++++++++++++++ arch/mips/tx4938/toshiba_rbtx4938/setup.c | 20 ++++++++++++++++++++ drivers/net/Kconfig | 2 +- drivers/net/ne.c | 13 ++++--------- 4 files changed, 44 insertions(+), 10 deletions(-) diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index 0f7576d..7d2c9d0 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -1049,3 +1049,22 @@ static int __init toshiba_rbtx4927_rtc_init(void) return IS_ERR(dev) ? PTR_ERR(dev) : 0; } device_initcall(toshiba_rbtx4927_rtc_init); + +static int __init rbtx4927_ne_init(void) +{ + struct resource res[] = { + { + .start = RBTX4927_RTL_8019_BASE, + .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, + .flags = IORESOURCE_IO, + }, { + .start = RBTX4927_RTL_8019_IRQ, + .flags = IORESOURCE_IRQ, + } + }; + struct platform_device *dev = + platform_device_register_simple("ne", -1, + res, ARRAY_SIZE(res)); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(rbtx4927_ne_init); diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c index 66163ba..f5d1ce7 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -1037,3 +1038,22 @@ static int __init tx4938_spi_proc_setup(void) __initcall(tx4938_spi_proc_setup); #endif + +static int __init rbtx4938_ne_init(void) +{ + struct resource res[] = { + { + .start = RBTX4938_RTL_8019_BASE, + .end = RBTX4938_RTL_8019_BASE + 0x20 - 1, + .flags = IORESOURCE_IO, + }, { + .start = RBTX4938_RTL_8019_IRQ, + .flags = IORESOURCE_IRQ, + } + }; + struct platform_device *dev = + platform_device_register_simple("ne", -1, + res, ARRAY_SIZE(res)); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(rbtx4938_ne_init); diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index aba0d39..a80e8ce 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1088,7 +1088,7 @@ config ETH16I config NE2000 tristate "NE2000/NE1000 support" - depends on NET_ISA || (Q40 && m) || M32R + depends on NET_ISA || (Q40 && m) || M32R || TOSHIBA_RBTX4927 || TOSHIBA_RBTX4938 select CRC32 ---help--- If you have a network (Ethernet) card of this type, say Y and read diff --git a/drivers/net/ne.c b/drivers/net/ne.c index b8a181f..4e99e7a 100644 --- a/drivers/net/ne.c +++ b/drivers/net/ne.c @@ -56,10 +56,6 @@ static const char version2[] = #include #include -#if defined(CONFIG_TOSHIBA_RBTX4927) || defined(CONFIG_TOSHIBA_RBTX4938) -#include -#endif - #include "8390.h" #define DRV_NAME "ne" @@ -81,7 +77,10 @@ static const char version2[] = /* A zero-terminated list of I/O addresses to be probed at boot. */ #ifndef MODULE static unsigned int netcard_portlist[] __initdata = { - 0x300, 0x280, 0x320, 0x340, 0x360, 0x380, 0 +#if defined(CONFIG_ISA) || defined(CONFIG_M32R) + 0x300, 0x280, 0x320, 0x340, 0x360, 0x380, +#endif + 0 }; #endif @@ -227,10 +226,6 @@ struct net_device * __init ne_probe(int unit) sprintf(dev->name, "eth%d", unit); netdev_boot_setup_check(dev); -#ifdef CONFIG_TOSHIBA_RBTX4938 - dev->base_addr = RBTX4938_RTL_8019_BASE; - dev->irq = RBTX4938_RTL_8019_IRQ; -#endif err = do_ne_probe(dev); if (err) goto out; From anemo@mba.ocn.ne.jp Tue Apr 24 17:56:29 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Apr 2007 17:56:31 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:28620 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20021440AbXDXQ43 (ORCPT ); Tue, 24 Apr 2007 17:56:29 +0100 Received: from localhost (p3087-ipad201funabasi.chiba.ocn.ne.jp [222.146.66.87]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id DFEBBAB46; Wed, 25 Apr 2007 01:56:24 +0900 (JST) Date: Wed, 25 Apr 2007 01:56:25 +0900 (JST) Message-Id: <20070425.015625.96686329.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: jeff@garzik.org, ralf@linux-mips.org, sshtylyov@ru.mvista.com, akpm@linux-foundation.org Subject: [PATCH 3/3] MIPS: Drop unnecessary CONFIG_ISA from RBTX49XX From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14905 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Those boards do not need CONFIG_ISA if the ne driver could be selectable without it. Disable it and update a defconfig. Signed-off-by: Atsushi Nemoto --- arch/mips/Kconfig | 2 -- arch/mips/configs/rbhma4500_defconfig | 31 ------------------------------- 2 files changed, 0 insertions(+), 33 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c78b143..e1e08dc 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -786,7 +786,6 @@ config TOSHIBA_RBTX4927 select HAS_TXX9_SERIAL select HW_HAS_PCI select I8259 - select ISA select SWAP_IO_SPACE select SYS_HAS_CPU_TX49XX select SYS_SUPPORTS_32BIT_KERNEL @@ -808,7 +807,6 @@ config TOSHIBA_RBTX4938 select HAS_TXX9_SERIAL select HW_HAS_PCI select I8259 - select ISA select SWAP_IO_SPACE select SYS_HAS_CPU_TX49XX select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig index 29e0df9..7d0f217 100644 --- a/arch/mips/configs/rbhma4500_defconfig +++ b/arch/mips/configs/rbhma4500_defconfig @@ -245,7 +245,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y -CONFIG_ISA=y CONFIG_MMU=y # @@ -573,7 +572,6 @@ CONFIG_MTD_CFI_UTIL=y # # Plug and Play support # -# CONFIG_PNP is not set # CONFIG_PNPACPI is not set # @@ -658,7 +656,6 @@ CONFIG_BLK_DEV_IT8213=m # CONFIG_BLK_DEV_VIA82CXXX is not set CONFIG_BLK_DEV_TC86C001=m # CONFIG_IDE_ARM is not set -# CONFIG_IDE_CHIPSETS is not set CONFIG_BLK_DEV_IDEDMA=y # CONFIG_IDEDMA_IVB is not set # CONFIG_IDEDMA_AUTO is not set @@ -677,11 +674,6 @@ CONFIG_RAID_ATTRS=m # CONFIG_ATA is not set # -# Old CD-ROM drivers (not SCSI, not IDE) -# -# CONFIG_CD_NO_IDESCSI is not set - -# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set @@ -742,37 +734,20 @@ CONFIG_NET_ETHERNET=y # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_SMC is not set # CONFIG_DM9000 is not set -# CONFIG_NET_VENDOR_RACAL is not set # # Tulip family network device support # # CONFIG_NET_TULIP is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set # CONFIG_HP100 is not set -CONFIG_NET_ISA=y -# CONFIG_E2100 is not set -# CONFIG_EWRK3 is not set -# CONFIG_EEXPRESS is not set -# CONFIG_EEXPRESS_PRO is not set -# CONFIG_HPLAN_PLUS is not set -# CONFIG_HPLAN is not set -# CONFIG_LP486E is not set -# CONFIG_ETH16I is not set CONFIG_NE2000=y -# CONFIG_SEEQ8005 is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set # CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_AC3200 is not set -# CONFIG_APRICOT is not set # CONFIG_B44 is not set # CONFIG_FORCEDETH is not set -# CONFIG_CS89x0 is not set # CONFIG_DGRS is not set # CONFIG_EEPRO100 is not set # CONFIG_E100 is not set @@ -833,8 +808,6 @@ CONFIG_NET_RADIO=y # Obsolete Wireless cards support (pre-802.11) # # CONFIG_STRIP is not set -# CONFIG_ARLAN is not set -# CONFIG_WAVELAN is not set # # Wireless 802.11b ISA/PCI cards support @@ -920,9 +893,6 @@ CONFIG_KEYBOARD_ATKBD=y CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y # CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_INPORT is not set -# CONFIG_MOUSE_LOGIBM is not set -# CONFIG_MOUSE_PC110PAD is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -1072,7 +1042,6 @@ CONFIG_FB_ATY_CT=y # CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set -# CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y # CONFIG_FRAMEBUFFER_CONSOLE is not set From anemo@mba.ocn.ne.jp Tue Apr 24 18:03:57 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 24 Apr 2007 18:03:59 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.175.29]:60125 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20021440AbXDXRD5 (ORCPT ); Tue, 24 Apr 2007 18:03:57 +0100 Received: from localhost (p3087-ipad201funabasi.chiba.ocn.ne.jp [222.146.66.87]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 35E95AB65; Wed, 25 Apr 2007 02:03:54 +0900 (JST) Date: Wed, 25 Apr 2007 02:03:55 +0900 (JST) Message-Id: <20070425.020355.70477311.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org, jeff@garzik.org, ralf@linux-mips.org, sshtylyov@ru.mvista.com Subject: Re: [PATCH 2/3] ne: MIPS: Use platform_driver for ne on RBTX49XX From: Atsushi Nemoto In-Reply-To: <20070425.015549.108742168.anemo@mba.ocn.ne.jp> References: <20070425.015549.108742168.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14906 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Wed, 25 Apr 2007 01:55:49 +0900 (JST), Atsushi Nemoto wrote: > This patch lets RBTX49XX boards use generic platform_driver interface > for the ne driver. This patch obsolates a patch I send on 1 Mar. > Subject: [PATCH] Fix broken RBTX4927 support in ne.c > Message-Id: <20070301.012223.129448787.anemo@mba.ocn.ne.jp> > Date: Thu, 01 Mar 2007 01:22:23 +0900 (JST) I revoke this old patch if new patch was acceptable. --- Atsushi Nemoto From akpm@linux-foundation.org Thu Apr 26 03:08:08 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 03:08:10 +0100 (BST) Received: from smtp1.linux-foundation.org ([65.172.181.25]:51391 "EHLO smtp1.linux-foundation.org") by ftp.linux-mips.org with ESMTP id S20023095AbXDZCII (ORCPT ); Thu, 26 Apr 2007 03:08:08 +0100 Received: from shell0.pdx.osdl.net (fw.osdl.org [65.172.181.6]) by smtp1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with ESMTP id l3Q27s25025321 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 25 Apr 2007 19:07:56 -0700 Received: from box (shell0.pdx.osdl.net [10.9.0.31]) by shell0.pdx.osdl.net (8.13.1/8.11.6) with SMTP id l3Q27rKQ018592; Wed, 25 Apr 2007 19:07:54 -0700 Date: Wed, 25 Apr 2007 19:07:53 -0700 From: Andrew Morton To: "Aeschbacher, Fabrice" Cc: "lkml" , linux-mips@linux-mips.org Subject: Re: pcmcia - failed to initialize IDE interface Message-Id: <20070425190753.fb8c272d.akpm@linux-foundation.org> In-Reply-To: References: X-Mailer: Sylpheed version 2.2.7 (GTK+ 2.8.17; x86_64-unknown-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: osdl$Revision: 1.177 $ X-Scanned-By: MIMEDefang 2.53 on 65.172.181.25 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14907 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Wed, 25 Apr 2007 15:27:26 +0200 "Aeschbacher, Fabrice" wrote: > Hi, > > [kernel 2.6.20.7, arch=mips, processor=amd au1550] > > I'm trying to install a 2.6 kernel on an Alchemy au1550, and having > problem with the pcmcia socket, where I plugged a CompactFlash card. The > card seems to be recognized by the kernel, appears in > /sys/bus/pcmcia/devices, but not in /proc/bus/pccard, and I can't access > the device (/dev/hda). > > The relevant console messages: > ---------------------------------------------------------------- > pccard: PCMCIA card inserted into slot 0 > pcmcia: registering new device pcmcia0.0 > hda: SanDisk SDCFB-64, CFA DISK drive > ide0: Disabled unable to get IRQ 35. > ide0: failed to initialize IDE interface > ide0: I/O resource 0x10200E-0x10200E not free. > ide0: ports already in use, skipping probe > ide0: I/O resource 0x10200E-0x10200E not free. > ide0: ports already in use, skipping probe > ide0: I/O resource 0x10200E-0x10200E not free. > ide0: ports already in use, skipping probe > ide0: I/O resource 0x10200E-0x10200E not free. > ide0: ports already in use, skipping probe > ide0: I/O resource 0x10200E-0x10200E not free. > ide0: ports already in use, skipping probe > ide0: I/O resource 0x10200E-0x10200E not free. > ide0: ports already in use, skipping probe > ide0: I/O resource 0x10200E-0x10200E not free. > ide0: ports already in use, skipping probe > ide0: I/O resource 0x10200E-0x10200E not free. > ide0: ports already in use, skipping probe > ide0: I/O resource 0x10200E-0x10200E not free. > ide0: ports already in use, skipping probe > ide-cs: ide_register() at 0x102000 & 0x10200e, irq 35 failed > ---------------------------------------------------------------- > > Here is the relevant part of the kernel config: > CONFIG_IDE=y > CONFIG_IDE_GENERIC=y > CONFIG_BLK_DEV_IDE=y > CONFIG_BLK_DEV_IDECS=y > CONFIG_PCCARD=y > CONFIG_PCMCIA_DEBUG=y > CONFIG_PCMCIA=y > CONFIG_PCMCIA_AU1X00=y > (cc'ed linux-mips) Perhaps /proc/ioports will tell us where the conflict lies. The output of `dmesg -s 1000000' might also be needed. From Fabrice.Aeschbacher@siemens.com Thu Apr 26 09:47:41 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 09:47:48 +0100 (BST) Received: from lizzard.sbs.de ([194.138.37.39]:59986 "EHLO lizzard.sbs.de") by ftp.linux-mips.org with ESMTP id S20023318AbXDZIrl convert rfc822-to-8bit (ORCPT ); Thu, 26 Apr 2007 09:47:41 +0100 Received: from mail2.sbs.de (localhost [127.0.0.1]) by lizzard.sbs.de (8.12.6/8.12.6) with ESMTP id l3Q8lYjT026624; Thu, 26 Apr 2007 10:47:34 +0200 Received: from fthw9xoa.ww002.siemens.net (fthw9xoa.ww002.siemens.net [157.163.133.201]) by mail2.sbs.de (8.12.6/8.12.6) with ESMTP id l3Q8lUpj009234; Thu, 26 Apr 2007 10:47:32 +0200 Received: from stgw002a.ww002.siemens.net ([141.73.158.150]) by fthw9xoa.ww002.siemens.net with Microsoft SMTPSVC(6.0.3790.1830); Thu, 26 Apr 2007 10:47:27 +0200 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: pcmcia - failed to initialize IDE interface Date: Thu, 26 Apr 2007 10:48:09 +0200 Message-ID: In-Reply-To: <20070425190753.fb8c272d.akpm@linux-foundation.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: pcmcia - failed to initialize IDE interface Thread-Index: AceHqEmPYMhqH9+RSm+Ie3xgpMcxxgANhycQ From: "Aeschbacher, Fabrice" To: "lkml" Cc: X-OriginalArrivalTime: 26 Apr 2007 08:47:27.0451 (UTC) FILETIME=[848B0AB0:01C787DF] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14908 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Fabrice.Aeschbacher@siemens.com Precedence: bulk X-list: linux-mips # cat /proc/ioports 00102000-00102007 : ide0 0010200e-0010200e : ide0 500000300-5000fffff : PCI IO space # cat /proc/iomem 10500000-1050ffff : Au1x00 ENET 10520000-10520003 : Au1x00 ENET 11100000-111fffff : serial 11200000-112fffff : serial 14020000-1407ffff : au1xxx-ohci.0 440000000-44fffffff : PCI memory space 440000000-447ffffff : 0000:00:0c.0 448000000-448ffffff : 0000:00:0c.0 449000000-449000fff : 0000:00:0a.0 449000000-449000fff : ohci_hcd 449001000-449001fff : 0000:00:0a.1 449001000-449001fff : ohci_hcd 449002000-4490020ff : 0000:00:0a.2 # dmesg -s 1000000 Linux version 2.6.20.7 (kh1af478@kh1r558d) (gcc version 3.3.4) #67 Wed Apr 25 16:56:40 CEST 2007 CPU revision is: 03030200 Siemens SISTORE CX1 Board (PRId 03030200) @ 324MHZ BCLK switching enabled! Determined physical RAM map: memory: 08000000 @ 00000000 (usable) On node 0 totalpages: 32768 DMA zone: 256 pages used for memmap DMA zone: 0 pages reserved DMA zone: 32512 pages, LIFO batch:7 Normal zone: 0 pages used for memmap __request_resource: new=System RAM[0-7ffffff], root=PCI mem[10000000-fffffffff] __request_resource: new=Kernel code[100000-3ddcff], root=System RAM[0-7ffffff] __request_resource: new=Kernel data[3ddd00-4850bf], root=System RAM[0-7ffffff] Built 1 zonelists. Total pages: 32512 Kernel command line: root=/dev/mtdblock0 rootfstype=jffs2 console=ttyS1,115200 usb_ohci=base:0x14020000,len:0x60000,irq:26 Primary instruction cache 16kB, physically tagged, 4-way, linesize 32 bytes. Primary data cache 16kB, 4-way, linesize 32 bytes. Synthesized TLB refill handler (17 instructions). Synthesized TLB load handler fastpath (34 instructions). Synthesized TLB store handler fastpath (34 instructions). Synthesized TLB modify handler fastpath (33 instructions). PID hash table entries: 512 (order: 9, 2048 bytes) calculating r4koff... 0004f1a0(324000) CPU frequency 324.00 MHz Console: colour dummy device 80x25 Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 124928k/131072k available (2935k kernel code, 6092k reserved, 668k data, 148k init, 0k highmem) Calibrating delay loop... 322.56 BogoMIPS (lpj=161280) Mount-cache hash table entries: 512 NET: Registered protocol family 16 __request_resource: new=au1xxx-ohci.0[14020000-1407ffff], root=PCI mem[10000000-fffffffff] registering PCI controller with io_map_base unset Generic PHY: Registered new driver SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb __request_resource: new=PCI memory space[440000000-44fffffff], root=PCI mem[10000000-fffffffff] __request_resource: new=PCI IO space[500000300-5000fffff], root=PCI IO[1000-fffffffff] PCI: Scanning bus 0000:00 PCI: Found 0000:00:0a.0 [1033/0035] 000c03 00 PCI: Found 0000:00:0a.1 [1033/0035] 000c03 00 PCI: Found 0000:00:0a.2 [1033/00e0] 000c03 00 PCI: Found 0000:00:0c.0 [12d5/1000] 000480 00 PCI: Fixups for bus 0000:00 PCI: Bus scan for 0000:00 returning with max=00 __request_resource: new=0000:00:0c.0[440000000-447ffffff], root=PCI memory space[440000000-44fffffff] got res [440000000:447ffffff] bus [40000000:47ffffff] flags 1208 for BAR 0 of 0000:00:0c.0 PCI: moved device 0000:00:0c.0 resource 0 (1208) to 40000000 __request_resource: new=0000:00:0c.0[448000000-448ffffff], root=PCI memory space[440000000-44fffffff] got res [448000000:448ffffff] bus [48000000:48ffffff] flags 200 for BAR 1 of 0000:00:0c.0 PCI: moved device 0000:00:0c.0 resource 1 (200) to 48000000 __request_resource: new=0000:00:0a.0[449000000-449000fff], root=PCI memory space[440000000-44fffffff] got res [449000000:449000fff] bus [49000000:49000fff] flags 200 for BAR 0 of 0000:00:0a.0 PCI: moved device 0000:00:0a.0 resource 0 (200) to 49000000 __request_resource: new=0000:00:0a.1[449001000-449001fff], root=PCI memory space[440000000-44fffffff] got res [449001000:449001fff] bus [49001000:49001fff] flags 200 for BAR 0 of 0000:00:0a.1 PCI: moved device 0000:00:0a.1 resource 0 (200) to 49001000 __request_resource: new=0000:00:0a.2[449002000-4490020ff], root=PCI memory space[440000000-44fffffff] got res [449002000:4490020ff] bus [49002000:490020ff] flags 200 for BAR 0 of 0000:00:0a.2 PCI: moved device 0000:00:0a.2 resource 0 (200) to 49002000 PCI: fixup irq: (0000:00:0a.0) got 2 PCI: fixup irq: (0000:00:0a.1) got 5 PCI: fixup irq: (0000:00:0a.2) got 6 PCI: fixup irq: (0000:00:0c.0) got 1 NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 4096 (order: 2, 16384 bytes) TCP bind hash table entries: 2048 (order: 1, 8192 bytes) TCP: Hash tables configured (established 4096 bind 2048) TCP reno registered Installing knfsd (copyright (C) 1996 okir@monad.swb.de). JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc. io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered (default) PCI: Calling quirk 8027fe64 for 0000:00:0a.0 PCI: Calling quirk 80312674 for 0000:00:0a.0 PCI: Calling quirk 8027fe64 for 0000:00:0a.1 PCI: Calling quirk 80312674 for 0000:00:0a.1 PCI: Calling quirk 8027fe64 for 0000:00:0a.2 PCI: Calling quirk 80312674 for 0000:00:0a.2 PCI: Calling quirk 8027fe64 for 0000:00:0c.0 PCI: Calling quirk 80312674 for 0000:00:0c.0 Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled __request_resource: new=serial[11100000-111fffff], root=PCI mem[10000000-fffffffff] serial8250.9: ttyS0 at MMIO 0x11100000 (irq = 0) is a 16550A __request_resource: new=serial[11200000-112fffff], root=PCI mem[10000000-fffffffff] serial8250.9: ttyS1 at MMIO 0x11200000 (irq = 8) is a 16550A __request_resource: new=serial[11400000-114fffff], root=PCI mem[10000000-fffffffff] RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize loop: loaded (max 8 devices) nbd: registered device at major 43 __request_resource: new=Au1x00 ENET[10500000-1050ffff], root=PCI mem[10000000-fffffffff] __request_resource: new=Au1x00 ENET[10520000-10520003], root=PCI mem[10000000-fffffffff] au1000_eth version 1.6 Pete Popov eth0: Au1xx0 Ethernet found at 0x10500000, irq 27 au1000_eth_mii: probed eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=0:04, irq=-1) Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx CX1 NOR Flash: probing 16-bit flash bus CX1 NOR Flash: Found 1 x16 devices at 0x0 in 16-bit bank Amd/Fujitsu Extended Query Table at 0x0040 CX1 NOR Flash: CFI does not contain boot bank location. Assuming top. number of CFI chips: 1 cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness. Creating 5 MTD partitions on "CX1 NOR Flash": 0x00000000-0x05000000 : "Root FS" 0x05000000-0x07000000 : "Data FS" 0x07000000-0x07c00000 : "Update FS" 0x07c00000-0x07d00000 : "YAMON" 0x07d00000-0x07fc0000 : "raw kernel" au1x_board_init cx1_socket_init ohci_hcd: 2006 August 04 USB 1.1 'Open' Host Controller (OHCI) Driver (PCI) PCI: Enabling device 0000:00:0a.0 (0000 -> 0002) __request_resource: new=ohci_hcd[449000000-449000fff], root=PCI mem[10000000-fffffffff] __request_resource: new=ohci_hcd[449000000-449000fff], root=PCI memory space[440000000-44fffffff] __request_resource: new=ohci_hcd[449000000-449000fff], root=0000:00:0a.0[449000000-449000fff] PCI: Enabling bus mastering for device 0000:00:0a.0 PCI: Setting latency timer of device 0000:00:0a.0 to 64 ohci_hcd 0000:00:0a.0: OHCI Host Controller ohci_hcd 0000:00:0a.0: new USB bus registered, assigned bus number 1 ohci_hcd 0000:00:0a.0: irq 2, io mem 0x449000000 cx1_pcmcia_configure_socket: bad Vpp 33 usb usb1: configuration #1 chosen from 1 choice hub 1-0:1.0: USB hub found hub 1-0:1.0: 3 ports detected PCI: Enabling device 0000:00:0a.1 (0000 -> 0002) __request_resource: new=ohci_hcd[449001000-449001fff], root=PCI mem[10000000-fffffffff] __request_resource: new=ohci_hcd[449001000-449001fff], root=PCI memory space[440000000-44fffffff] __request_resource: new=ohci_hcd[449001000-449001fff], root=0000:00:0a.1[449001000-449001fff] PCI: Enabling bus mastering for device 0000:00:0a.1 PCI: Setting latency timer of device 0000:00:0a.1 to 64 ohci_hcd 0000:00:0a.1: OHCI Host Controller ohci_hcd 0000:00:0a.1: new USB bus registered, assigned bus number 2 ohci_hcd 0000:00:0a.1: irq 5, io mem 0x449001000 usb usb2: configuration #1 chosen from 1 choice hub 2-0:1.0: USB hub found hub 2-0:1.0: 2 ports detected Initializing USB Mass Storage driver... usbcore: registered new interface driver usb-storage USB Mass Storage support registered. usbcore: registered new interface driver hiddev usbcore: registered new interface driver usbhid drivers/usb/input/hid-core.c: v2.6:USB HID core driver i8042.c: i8042 controller selftest failed. (0xf != 0x55) i8042: probe of i8042 failed with error -5 cx1_pcmcia_configure_socket: bad Vpp 33 cx1_pcmcia_configure_socket: bad Vpp 33 Trying to free nonexistent resource <0000000000000060-000000000000006f> TCP cubic registered NET: Registered protocol family 1 NET: Registered protocol family 17 pcmcia: ide-cs: invalid hash for product string "TS2GCF120": is 0xf54a91c8, should be 0x969aa4f2 pcmcia: see Documentation/pcmcia/devicetable.txt for details Time: MIPS clocksource has been installed. VFS: Mounted root (jffs2 filesystem) readonly. Freeing unused kernel memory: 148k freed pccard: PCMCIA card inserted into slot 0 pcmcia: registering new device pcmcia0.0 ide_attach() ide_config(0x812a4400) __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] __request_resource: new=ide0[102000-102007], root=PCI IO[1000-fffffffff] Probing IDE interface ide0... probing for hda: present=0, media=32, probetype=ATA Algorithmics/MIPS FPU Emulator v1.5 hda: TRANSCEND, CFA DISK drive probing for hdb: present=0, media=32, probetype=ATA probing for hdb: present=0, media=32, probetype=ATAPI calling ide_default_irq(102000) ide0: Disabled unable to get IRQ 35. ide0: failed to initialize IDE interface __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] ide0: I/O resource 0x10200E-0x10200E not free. ide0: ports already in use, skipping probe __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] ide0: I/O resource 0x10200E-0x10200E not free. ide0: ports already in use, skipping probe __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] ide0: I/O resource 0x10200E-0x10200E not free. ide0: ports already in use, skipping probe __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] ide0: I/O resource 0x10200E-0x10200E not free. ide0: ports already in use, skipping probe __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] ide0: I/O resource 0x10200E-0x10200E not free. ide0: ports already in use, skipping probe __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] ide0: I/O resource 0x10200E-0x10200E not free. ide0: ports already in use, skipping probe __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] ide0: I/O resource 0x10200E-0x10200E not free. ide0: ports already in use, skipping probe __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] ide0: I/O resource 0x10200E-0x10200E not free. ide0: ports already in use, skipping probe No module found in object __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] ide0: I/O resource 0x10200E-0x10200E not free. ide0: ports already in use, skipping probe ide-cs: ide_register() at 0x102000 & 0x10200e, irq 35 failed ide_release(0x812a4400) eth0: link up (100/Full) eth0: Pass all multicast ------------------------------------------------------------------------ - I added some printk() only for debugging raisons (for example in __request_resource, as you can see) Best regards, Fabrice Aeschbacher > -----Original Message----- > From: Andrew Morton [mailto:akpm@linux-foundation.org] > Sent: Donnerstag, 26. April 2007 04:08 > To: Aeschbacher, Fabrice > Cc: lkml; linux-mips@linux-mips.org > Subject: Re: pcmcia - failed to initialize IDE interface > > On Wed, 25 Apr 2007 15:27:26 +0200 "Aeschbacher, Fabrice" > wrote: > > > Hi, > > > > [kernel 2.6.20.7, arch=mips, processor=amd au1550] > > > > I'm trying to install a 2.6 kernel on an Alchemy au1550, and having > > problem with the pcmcia socket, where I plugged a > CompactFlash card. > > The card seems to be recognized by the kernel, appears in > > /sys/bus/pcmcia/devices, but not in /proc/bus/pccard, and I can't > > access the device (/dev/hda). > > > > The relevant console messages: > > ---------------------------------------------------------------- > > pccard: PCMCIA card inserted into slot 0 > > pcmcia: registering new device pcmcia0.0 > > hda: SanDisk SDCFB-64, CFA DISK drive > > ide0: Disabled unable to get IRQ 35. > > ide0: failed to initialize IDE interface > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide-cs: ide_register() at 0x102000 & 0x10200e, irq 35 failed > > ---------------------------------------------------------------- > > > > Here is the relevant part of the kernel config: > > CONFIG_IDE=y > > CONFIG_IDE_GENERIC=y > > CONFIG_BLK_DEV_IDE=y > > CONFIG_BLK_DEV_IDECS=y > > CONFIG_PCCARD=y > > CONFIG_PCMCIA_DEBUG=y > > CONFIG_PCMCIA=y > > CONFIG_PCMCIA_AU1X00=y > > > > (cc'ed linux-mips) > > Perhaps /proc/ioports will tell us where the conflict lies. > > The output of `dmesg -s 1000000' might also be needed. > From anemo@mba.ocn.ne.jp Thu Apr 26 09:50:02 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 09:50:04 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:4992 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20023300AbXDZIuC (ORCPT ); Thu, 26 Apr 2007 09:50:02 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Thu, 26 Apr 2007 17:50:01 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 1E4D123CD0; Thu, 26 Apr 2007 17:49:54 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 0B22F20457; Thu, 26 Apr 2007 17:49:54 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id l3Q8nrW0023337; Thu, 26 Apr 2007 17:49:53 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Thu, 26 Apr 2007 17:49:53 +0900 (JST) Message-Id: <20070426.174953.11964712.nemoto@toshiba-tops.co.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [MIPS] Fix kunmap_coherent() usage. From: Atsushi Nemoto In-Reply-To: References: X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14909 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sun, 25 Mar 2007 13:30:46 +0100, linux-mips@linux-mips.org wrote: > Author: Atsushi Nemoto Sun Mar 25 02:10:10 2007 +0900 > Comitter: Ralf Baechle Sun Mar 25 02:06:30 2007 +0100 > Commit: 116e34f274dabaf989e4c1c021c4be49f85294e5 > Gitweb: http://www.linux-mips.org/g/linux/116e34f2 > Branch: master I just found this commit is not exist in Linus's tree. Anyway it is harmless and will be overwritten by an another cleanup in linux-queue tree. --- Atsushi Nemoto From rmk+linux-mips=linux-mips.org@arm.linux.org.uk Thu Apr 26 10:15:54 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 10:15:56 +0100 (BST) Received: from caramon.arm.linux.org.uk ([217.147.92.249]:48913 "EHLO caramon.arm.linux.org.uk") by ftp.linux-mips.org with ESMTP id S20023314AbXDZJPy (ORCPT ); Thu, 26 Apr 2007 10:15:54 +0100 Received: from flint.arm.linux.org.uk ([2002:d993:5cf9:1:201:2ff:fe14:8fad]) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.62) (envelope-from ) id 1Hh01c-0000so-VX; Thu, 26 Apr 2007 10:12:29 +0100 Received: from rmk by flint.arm.linux.org.uk with local (Exim 4.62) (envelope-from ) id 1Hh01Y-0005w9-4v; Thu, 26 Apr 2007 10:12:24 +0100 Date: Thu, 26 Apr 2007 10:12:22 +0100 From: Russell King To: "Aeschbacher, Fabrice" Cc: lkml , linux-mips@linux-mips.org Subject: Re: pcmcia - failed to initialize IDE interface Message-ID: <20070426091222.GA16723@flint.arm.linux.org.uk> Mail-Followup-To: "Aeschbacher, Fabrice" , lkml , linux-mips@linux-mips.org References: <20070425190753.fb8c272d.akpm@linux-foundation.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14910 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmk+lkml@arm.linux.org.uk Precedence: bulk X-list: linux-mips On Thu, Apr 26, 2007 at 10:48:09AM +0200, Aeschbacher, Fabrice wrote: > __request_resource: new=ide0[10200e-10200e], root=PCI IO[1000-fffffffff] > __request_resource: new=ide0[102000-102007], root=PCI IO[1000-fffffffff] > > I added some printk() only for debugging raisons (for example in > __request_resource, as you can see) You might want to also dump the resource flags as well. The two I show above (from the PCMCIA calls in ide_config) should not mark the resources busy. -- Russell King Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/ maintainer of: From mano@roarinelk.homelinux.net Thu Apr 26 10:35:16 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 10:35:18 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:37133 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20023342AbXDZJfQ (ORCPT ); Thu, 26 Apr 2007 10:35:16 +0100 Received: (qmail 26501 invoked by uid 1000); 26 Apr 2007 11:35:15 +0200 Date: Thu, 26 Apr 2007 11:35:15 +0200 From: Manuel Lauss To: linux-mips@linux-mips.org Subject: MIPS ioport_map and Au1xxx PCMCIA Message-ID: <20070426093515.GA26434@roarinelk.homelinux.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14911 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hello, the file arch/mips/lib/iomap.c contains this define #define PIO_MASK 0x0ffffUL which prevents pata_pcmcia with the new devres stuff from attaching to a CF card. (on my Au1200). The ports-to-be-iomap()'ed are in the 0xc0000000 range and the ioport_map() function rejects all attempts of pata_pcmcia to devm_ioport_map() them. What is this mask used for and can it be removed? Thanks, -- Manuel Lauss From yoichi_yuasa@tripeaks.co.jp Thu Apr 26 11:55:58 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 11:56:00 +0100 (BST) Received: from mo32.po.2iij.NET ([210.128.50.17]:8000 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20023370AbXDZKz6 (ORCPT ); Thu, 26 Apr 2007 11:55:58 +0100 Received: by mo.po.2iij.net (mo32) id l3QAttIh051570; Thu, 26 Apr 2007 19:55:55 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox33) id l3QAto68097382 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 26 Apr 2007 19:55:51 +0900 (JST) Message-Id: <200704261055.l3QAto68097382@mbox33.po.2iij.net> Date: Thu, 26 Apr 2007 19:45:09 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH][MIPS] rename VR41XX to VR4100 series Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14912 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf This patch has renamed VR41XX to VR4100 series. That's better. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X vr41xx/Documentation/dontdiff vr41xx-orig/arch/mips/Kconfig vr41xx/arch/mips/Kconfig --- vr41xx-orig/arch/mips/Kconfig 2007-04-26 19:00:53.983294750 +0900 +++ vr41xx/arch/mips/Kconfig 2007-04-26 19:07:27.463885750 +0900 @@ -501,7 +501,7 @@ config DDB5477 ether port USB, AC97, PCI, etc. config MACH_VR41XX - bool "NEC VR41XX-based machines" + bool "NEC VR4100 series based machines" select SYS_HAS_CPU_VR41XX select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL From yoichi_yuasa@tripeaks.co.jp Thu Apr 26 11:57:10 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 11:57:13 +0100 (BST) Received: from mo32.po.2iij.NET ([210.128.50.17]:14896 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20023372AbXDZK5K (ORCPT ); Thu, 26 Apr 2007 11:57:10 +0100 Received: by mo.po.2iij.net (mo32) id l3QAtrfi051556; Thu, 26 Apr 2007 19:55:53 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox31) id l3QAtpai091830 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 26 Apr 2007 19:55:52 +0900 (JST) Message-Id: <200704261055.l3QAtpai091830@mbox31.po.2iij.net> Date: Thu, 26 Apr 2007 19:53:59 +0900 From: Yoichi Yuasa To: ralf@linux-mips.org Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips@linux-mips.org Subject: [PATCH][MIPS] update vr41xx Kconfig Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14913 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has updated vr41xx/Kconfig. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X vr41xx/Documentation/dontdiff vr41xx-orig/arch/mips/vr41xx/Kconfig vr41xx/arch/mips/vr41xx/Kconfig --- vr41xx-orig/arch/mips/vr41xx/Kconfig 2007-04-26 19:00:56.387445000 +0900 +++ vr41xx/arch/mips/vr41xx/Kconfig 2007-04-26 19:28:56.296432750 +0900 @@ -1,6 +1,10 @@ -config CASIO_E55 - bool "Support for CASIO CASSIOPEIA E-10/15/55/65" +choice + prompt "Machine type" depends on MACH_VR41XX + default TANBAC_TB022X + +config CASIO_E55 + bool "CASIO CASSIOPEIA E-10/15/55/65" select DMA_NONCOHERENT select IRQ_CPU select ISA @@ -8,8 +12,7 @@ config CASIO_E55 select SYS_SUPPORTS_LITTLE_ENDIAN config IBM_WORKPAD - bool "Support for IBM WorkPad z50" - depends on MACH_VR41XX + bool "IBM WorkPad z50" select DMA_NONCOHERENT select IRQ_CPU select ISA @@ -17,26 +20,18 @@ config IBM_WORKPAD select SYS_SUPPORTS_LITTLE_ENDIAN config NEC_CMBVR4133 - bool "Support for NEC CMB-VR4133" - depends on MACH_VR41XX + bool "NEC CMB-VR4133" select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN -config ROCKHOPPER - bool "Support for Rockhopper baseboard" - depends on NEC_CMBVR4133 - select I8259 - select HAVE_STD_PC_SERIAL_PORT - config TANBAC_TB022X - bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM" - depends on MACH_VR41XX + bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM" select DMA_NONCOHERENT - select HW_HAS_PCI select IRQ_CPU + select HW_HAS_PCI select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN help @@ -46,40 +41,65 @@ config TANBAC_TB022X Please refer to about VR4131 multichip module and VR4131DIMM. -config TANBAC_TB0226 - bool "Support for TANBAC Mbase(TB0226)" +config VICTOR_MPC30X + bool "Victor MP-C303/304" + select DMA_NONCOHERENT + select IRQ_CPU + select HW_HAS_PCI + select PCI_VR41XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + +config ZAO_CAPCELLA + bool "ZAO Networks Capcella" + select DMA_NONCOHERENT + select IRQ_CPU + select HW_HAS_PCI + select PCI_VR41XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + +endchoice + +config ROCKHOPPER + bool "Support for Rockhopper base board" + depends on NEC_CMBVR4133 + select PCI_VR41XX + select I8259 + select HAVE_STD_PC_SERIAL_PORT + +choice + prompt "Base board type" depends on TANBAC_TB022X + default TANBAC_TB0287 + +config TANBAC_TB0219 + bool "TANBAC DIMM Evaluation Kit(TB0219)" select GPIO_VR41XX + select PCI_VR41XX + help + The TANBAC DIMM Evaluation Kit(TB0219) is a MIPS-based platform + manufactured by TANBAC. + Please refer to about DIMM Evaluation Kit. + +config TANBAC_TB0226 + bool "TANBAC Mbase(TB0226)" + select GPIO_VR41XX + select PCI_VR41XX help The TANBAC Mbase(TB0226) is a MIPS-based platform manufactured by TANBAC. Please refer to about Mbase. config TANBAC_TB0287 - bool "Support for TANBAC Mini-ITX DIMM base(TB0287)" - depends on TANBAC_TB022X + bool "TANBAC Mini-ITX DIMM base(TB0287)" + select PCI_VR41XX help The TANBAC Mini-ITX DIMM base(TB0287) is a MIPS-based platform manufactured by TANBAC. Please refer to about Mini-ITX DIMM base. -config VICTOR_MPC30X - bool "Support for Victor MP-C303/304" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - -config ZAO_CAPCELLA - bool "Support for ZAO Networks Capcella" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN +endchoice config PCI_VR41XX bool "Add PCI control unit support of NEC VR4100 series" From yoichi_yuasa@tripeaks.co.jp Thu Apr 26 11:57:33 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 11:57:36 +0100 (BST) Received: from mo32.po.2iij.NET ([210.128.50.17]:20519 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20023375AbXDZK5M (ORCPT ); Thu, 26 Apr 2007 11:57:12 +0100 Received: by mo.po.2iij.net (mo32) id l3QAttNZ051584; Thu, 26 Apr 2007 19:55:55 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox32) id l3QAtpJ8003441 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 26 Apr 2007 19:55:51 +0900 (JST) Message-Id: <200704261055.l3QAtpJ8003441@mbox32.po.2iij.net> Date: Thu, 26 Apr 2007 19:51:31 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH][MIPS] remove 2 select entries for VR41xx Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14914 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has removed 2 select entries for VR41xx. These entries are selected in arch/mips/vr41xx/Kconfig. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X vr41xx/Documentation/dontdiff vr41xx-orig/arch/mips/Kconfig vr41xx/arch/mips/Kconfig --- vr41xx-orig/arch/mips/Kconfig 2007-04-26 19:14:20.753714750 +0900 +++ vr41xx/arch/mips/Kconfig 2007-04-26 19:15:59.763902500 +0900 @@ -503,8 +503,6 @@ config DDB5477 config MACH_VR41XX bool "NEC VR4100 series based machines" select SYS_HAS_CPU_VR41XX - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL select GENERIC_HARDIRQS_NO__DO_IRQ config PMC_YOSEMITE From ralf@linux-mips.org Thu Apr 26 15:24:12 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 15:24:14 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:41177 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20023430AbXDZOYM (ORCPT ); Thu, 26 Apr 2007 15:24:12 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3QEO6U7017352; Thu, 26 Apr 2007 15:24:06 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3QEO58M017351; Thu, 26 Apr 2007 15:24:05 +0100 Date: Thu, 26 Apr 2007 15:24:04 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH][MIPS] rename VR41XX to VR4100 series Message-ID: <20070426142404.GA11177@linux-mips.org> References: <200704261055.l3QAto68097382@mbox33.po.2iij.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200704261055.l3QAto68097382@mbox33.po.2iij.net> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14915 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Apr 26, 2007 at 07:45:09PM +0900, Yoichi Yuasa wrote: > This patch has renamed VR41XX to VR4100 series. > That's better. Queued, thanks. Ralf From ralf@linux-mips.org Thu Apr 26 15:24:34 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 15:24:36 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:42457 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20023432AbXDZOY2 (ORCPT ); Thu, 26 Apr 2007 15:24:28 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3QEOMM3017358; Thu, 26 Apr 2007 15:24:22 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3QEOMsN017357; Thu, 26 Apr 2007 15:24:22 +0100 Date: Thu, 26 Apr 2007 15:24:22 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH][MIPS] remove 2 select entries for VR41xx Message-ID: <20070426142422.GB11177@linux-mips.org> References: <200704261055.l3QAtpJ8003441@mbox32.po.2iij.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200704261055.l3QAtpJ8003441@mbox32.po.2iij.net> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14916 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Apr 26, 2007 at 07:51:31PM +0900, Yoichi Yuasa wrote: > This patch has removed 2 select entries for VR41xx. > These entries are selected in arch/mips/vr41xx/Kconfig. Queued, thanks. Ralf From ralf@linux-mips.org Thu Apr 26 15:24:56 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 15:24:59 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:11226 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20023433AbXDZOYq (ORCPT ); Thu, 26 Apr 2007 15:24:46 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.8/8.13.8) with ESMTP id l3QEOeoS017371; Thu, 26 Apr 2007 15:24:40 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.8/8.13.8/Submit) id l3QEOenS017370; Thu, 26 Apr 2007 15:24:40 +0100 Date: Thu, 26 Apr 2007 15:24:40 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips@linux-mips.org Subject: Re: [PATCH][MIPS] update vr41xx Kconfig Message-ID: <20070426142440.GC11177@linux-mips.org> References: <200704261055.l3QAtpai091830@mbox31.po.2iij.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200704261055.l3QAtpai091830@mbox31.po.2iij.net> User-Agent: Mutt/1.4.2.2i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14917 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Apr 26, 2007 at 07:53:59PM +0900, Yoichi Yuasa wrote: > This patch has updated vr41xx/Kconfig. Queued, thanks. Ralf From alan@lxorguk.ukuu.org.uk Thu Apr 26 16:51:42 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 16:51:44 +0100 (BST) Received: from outpipe-village-512-1.bc.nu ([81.2.110.250]:16838 "EHLO the-village.bc.nu") by ftp.linux-mips.org with ESMTP id S20023441AbXDZPvm (ORCPT ); Thu, 26 Apr 2007 16:51:42 +0100 Received: from the-village.bc.nu (localhost.localdomain [127.0.0.1]) by the-village.bc.nu (8.13.8/8.13.8) with ESMTP id l3QFtP9a026458; Thu, 26 Apr 2007 16:55:25 +0100 Date: Thu, 26 Apr 2007 16:55:25 +0100 From: Alan Cox To: Manuel Lauss Cc: linux-mips@linux-mips.org Subject: Re: MIPS ioport_map and Au1xxx PCMCIA Message-ID: <20070426165525.27bd8a77@the-village.bc.nu> In-Reply-To: <20070426093515.GA26434@roarinelk.homelinux.net> References: <20070426093515.GA26434@roarinelk.homelinux.net> X-Mailer: Claws Mail 2.9.1 (GTK+ 2.10.8; i386-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14918 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alan@lxorguk.ukuu.org.uk Precedence: bulk X-list: linux-mips On Thu, 26 Apr 2007 11:35:15 +0200 Manuel Lauss wrote: > Hello, > > the file arch/mips/lib/iomap.c contains this define > #define PIO_MASK 0x0ffffUL > > which prevents pata_pcmcia with the new devres stuff > from attaching to a CF card. (on my Au1200). > The ports-to-be-iomap()'ed are in the 0xc0000000 range > and the ioport_map() function rejects all attempts > of pata_pcmcia to devm_ioport_map() them. > > What is this mask used for and can it be removed? iomap uses PIO_MASK to idenfiy ports within the I/O space range. The mips code looks somewhat incomplete in the base kernel which is probably much of the problem. The basic idea is that ioread/iowrite and friends work generically regardless of MMIO v PIO so you can just do pci_iomap(some bar); iowrite(blah); pci_iounmap(blah) and not worry about anything. Now if your platform doesn't have seperate IO space you could probably implement iowrite/ioremap/ioport_map to be pretty much no-ops depending upon how your PCI bars are encoded. Alan From mano@roarinelk.homelinux.net Thu Apr 26 18:46:12 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 18:46:13 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:12559 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20022368AbXDZRqM (ORCPT ); Thu, 26 Apr 2007 18:46:12 +0100 Received: (qmail 27735 invoked by uid 1000); 26 Apr 2007 19:45:08 +0200 Date: Thu, 26 Apr 2007 19:45:08 +0200 From: Manuel Lauss To: Alan Cox Cc: linux-mips@linux-mips.org Subject: Re: MIPS ioport_map and Au1xxx PCMCIA Message-ID: <20070426174508.GB27510@roarinelk.homelinux.net> References: <20070426093515.GA26434@roarinelk.homelinux.net> <20070426165525.27bd8a77@the-village.bc.nu> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070426165525.27bd8a77@the-village.bc.nu> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14919 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips On Thu, Apr 26, 2007 at 04:55:25PM +0100, Alan Cox wrote: > iomap uses PIO_MASK to idenfiy ports within the I/O space range. The mips > code looks somewhat incomplete in the base kernel which is probably much > of the problem. > > The basic idea is that ioread/iowrite and friends work generically > regardless of MMIO v PIO so you can just do > > pci_iomap(some bar); > iowrite(blah); > pci_iounmap(blah) > > and not worry about anything. > > Now if your platform doesn't have seperate IO space you could probably > implement iowrite/ioremap/ioport_map to be pretty much no-ops depending > upon how your PCI bars are encoded. This Au1200 doesn't have PCI; to access the PCMCIA IO space one has to ioremap() a part from the top of the 36bit space. I took the cheap route and simply removed the PIO_MASK check from my local kernel. Thank you, -- Manuel Lauss From Eric.VanTassell@drs-ss.com Thu Apr 26 22:56:58 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 26 Apr 2007 22:57:00 +0100 (BST) Received: from smtp-out.sigp.net ([63.237.78.44]:40685 "EHLO smtp-out.sigp.net") by ftp.linux-mips.org with ESMTP id S20021450AbXDZV46 (ORCPT ); Thu, 26 Apr 2007 22:56:58 +0100 Received: from gamd-ex-001.ss.drs.master (gamd-ex-001.ss.drs.master [172.22.132.94]) by smtp-out.sigp.net (8.14.1/8.14.1) with ESMTP id l3QLnRBt014516 for ; Thu, 26 Apr 2007 17:49:27 -0400 (EDT) X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C7884C.C2CDFC39" Subject: bug in arch/mips/sibyte/cfe/cfe_api.c ? Date: Thu, 26 Apr 2007 17:49:22 -0400 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: bug in arch/mips/sibyte/cfe/cfe_api.c ? Thread-Index: AceITMAja369+xbgTq2GTnEwfJNdOA== From: "van Tassell, Eric" To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14920 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Eric.VanTassell@drs-ss.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. ------_=_NextPart_001_01C7884C.C2CDFC39 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable All, The following change which showed up merging from 2.6.20.1 appears to be a bug. =20 diff -U 3 linux/arch/mips/sibyte/cfe/cfe_api.c linux-2.6.20.1/arch/mips/sibyte/cfe/cfe_api.c --- linux/arch/mips/sibyte/cfe/cfe_api.c 2007-04-25 14:33:46.000000000 -0400 +++ linux-2.6.20.1/arch/mips/sibyte/cfe/cfe_api.c 2007-02-20 19:47:41.000000000 -0500 @@ -135,7 +135,7 @@ { cfe_xiocb_t xiocb; =20 - xiocb.xiocb_fcode =3D CFE_CMD_ENV_ENUM; + xiocb.xiocb_fcode =3D CFE_CMD_ENV_SET; xiocb.xiocb_status =3D 0; xiocb.xiocb_handle =3D 0; xiocb.xiocb_flags =3D 0; =20 =20 - Eric van Tassell =20 DRS Intelligence Technologies Advanced Processing Group 21 Continental Blvd Merrimack, NH 03054 P: 603.424.3750 www.drs-ss.com =20 ------_=_NextPart_001_01C7884C.C2CDFC39 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

All,

         =    The following change which showed up merging from 2.6.20.1 appears to be a bug.

 

diff -U 3 linux/arch/mips/sibyte/cfe/cfe_api.c linux-2.6.20.1/arch/mips/sibyte/cfe/cfe_api.c

--- = linux/arch/mips/sibyte/cfe/cfe_api.c      &= nbsp;    2007-04-25 14:33:46.000000000 -0400

+++ = linux-2.6.20.1/arch/mips/sibyte/cfe/cfe_api.c     = 2007-02-20 19:47:41.000000000 -0500

@@ -135,7 +135,7 @@

 {

         =    cfe_xiocb_t xiocb;

 

-         = ;  xiocb.xiocb_fcode =3D = CFE_CMD_ENV_ENUM;

+         = ; xiocb.xiocb_fcode =3D CFE_CMD_ENV_SET;

         =    xiocb.xiocb_status =3D 0;

         =    xiocb.xiocb_handle =3D 0;

         =    xiocb.xiocb_flags =3D 0;

 

 

-         Eric van = Tassell

 

DRS Intelligence = Technologies

Advanced Processing = Group

21 Continental = Blvd

Merrimack, NH 03054

P: 603.424.3750

www.drs-ss.com

 

------_=_NextPart_001_01C7884C.C2CDFC39-- From stjeanma@pmc-sierra.com Fri Apr 27 01:48:32 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Apr 2007 01:48:37 +0100 (BST) Received: from mother.pmc-sierra.com ([216.241.224.12]:22726 "HELO mother.pmc-sierra.bc.ca") by ftp.linux-mips.org with SMTP id S20021458AbXD0Asc (ORCPT ); Fri, 27 Apr 2007 01:48:32 +0100 Received: (qmail 8063 invoked by uid 101); 27 Apr 2007 00:48:13 -0000 Received: from unknown (HELO pmxedge1.pmc-sierra.bc.ca) (216.241.226.183) by mother.pmc-sierra.com with SMTP; 27 Apr 2007 00:48:13 -0000 Received: from pasqua.pmc-sierra.bc.ca (pasqua.pmc-sierra.bc.ca [134.87.183.161]) by pmxedge1.pmc-sierra.bc.ca (8.13.4/8.12.7) with ESMTP id l3R0mCpg031931; Thu, 26 Apr 2007 17:48:12 -0700 From: Marc St-Jean Received: (from stjeanma@localhost) by pasqua.pmc-sierra.bc.ca (8.13.4/8.12.11) id l3R0m3WV015597; Thu, 26 Apr 2007 18:48:03 -0600 Date: Thu, 26 Apr 2007 18:48:03 -0600 Message-Id: <200704270048.l3R0m3WV015597@pasqua.pmc-sierra.bc.ca> To: netdev@vger.kernel.org Subject: [PATCH 10/12] drivers: PMC MSP71xx ethernet driver Cc: akpm@linux-foundation.org, jgarzik@pobox.com, linux-mips@linux-mips.org Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14921 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stjeanma@pmc-sierra.com Precedence: bulk X-list: linux-mips [PATCH 10/12] drivers: PMC MSP71xx ethernet driver Patch to add an ethernet driver for the PMC-Sierra MSP71xx devices. Patches 1 through 9 were posted to linux-mips@linux-mips.org as well as other sub-system lists/maintainers as appropriate. This patch has some dependencies on the first few patches in the set. If you would like to receive these or the entire set, please email me. Thanks, Marc Signed-off-by: Marc St-Jean --- Changes since last posting: -Major cleanup in style, etc. -Converted to platfrom driver model. -Added iomapping support. -Added dma sync support. -Added NAPI support. -Added skb buffer recycling. arch/mips/pmc-sierra/msp71xx/msp_eth.c | 122 + drivers/net/Kconfig | 20 drivers/net/Makefile | 1 drivers/net/pmcmspeth.c | 3178 +++++++++++++++++++++++++++++++++ drivers/net/pmcmspeth.h | 624 ++++++ 5 files changed, 3945 insertions(+) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 76f98f3..53a7246 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -201,6 +201,26 @@ config MACB source "drivers/net/arm/Kconfig" +config MSPETH + bool "Ethernet for PMC-Sierra MSP" + depends on NET_ETHERNET && PMC_MSP + ---help--- + This adds support for the the MACs found on the PMC-Sierra MSP devices. + +config MSPETH_NAPI + bool "NAPI support" + depends on MSPETH + help + NAPI(New API) is a technique to improve network performance on Linux. + +config MSPETH_SKB_RECYCLE + bool "Socket Buffer recycling support" + depends on MSPETH + help + Reuse the socket buffers used during the transmission of packets for the receive + operation. This improves performance by reducing kmalloc/kfree operations. + + config MACE tristate "MACE (Power Mac ethernet) support" depends on NET_ETHERNET && PPC_PMAC && PPC32 diff --git a/drivers/net/Makefile b/drivers/net/Makefile index c26ba39..cc90aa0 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_SKFP) += skfp/ obj-$(CONFIG_VIA_RHINE) += via-rhine.o obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o +obj-$(CONFIG_MSPETH) += pmcmspeth.o obj-$(CONFIG_RIONET) += rionet.o # diff --git a/drivers/net/pmcmspeth.c b/drivers/net/pmcmspeth.c new file mode 100644 index 0000000..788fa23 --- /dev/null +++ b/drivers/net/pmcmspeth.c @@ -0,0 +1,3178 @@ +/* + * PMC-Sierra MSP EVM ethernet driver for linux + * + * Copyright 2005-2007 PMC-Sierra, Inc + * + * Originally based on mspeth.c driver which contains substantially the + * same hardware. + * Based on skelton.c by Donald Becker. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#include +#include +#include +#include +#include +#include +#include +#include +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +#include +#include +#include +#include +#include +#include +#endif /* LINUX_VERSION_CODE */ + +#include "pmcmspeth.h" + +/************************************************************************** + * The name of the card. Is used for messages and in the requests for + * io regions, irqs and dma channels, versions, etc. Also, various other + * identifying character constants. + */ +static const char cardname[] = "pmcmspeth"; + +/************************************************************************** + * List of PHYs. Each MAC will have a certain number (maybe zero) + * PHYs hanging off the MDIO interface. + */ +static struct mspeth_phy *root_phy_dev = NULL; + +/* Debugging flags */ +static unsigned int mspeth_debug = MSPETH_DEBUG; + +/************************************************************************** + * Function prototypes + */ + +/* Functions that get called by upper layers */ +static int mspeth_open(struct net_device *dev); +static int mspeth_send_packet(struct sk_buff *skb, + struct net_device *dev); +static void mspeth_tx_timeout(struct net_device *dev); +static void mspeth_hard_restart_bh(unsigned long dev_addr); +static int mspeth_close(struct net_device *dev); +static struct net_device_stats *mspeth_get_stats(struct net_device *dev); +static void mspeth_set_multicast_list(struct net_device *dev); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +static irqreturn_t mspeth_interrupt(int irq, void *dev_id); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +static void mspeth_interrupt(int irq, void *dev_id, struct pt_regs *regs); +#endif + +#ifdef CONFIG_MSPETH_NAPI +static int mspeth_poll(struct net_device *dev, int *budget); +inline static void mspeth_txdone(unsigned long dev_addr); +#else +static void mspeth_rx(unsigned long dev_addr); +static void mspeth_txdone(unsigned long dev_addr); +#endif /* CONFIG_MSPETH_NAPI */ + +/* Private utility functions */ +static void mspeth_soft_restart(struct net_device *dev); +static void mspeth_hard_restart(struct net_device *dev); +static void mspeth_mac_reset(struct net_device *dev); +static void mspeth_mac_init(struct net_device *dev); +static void mspeth_phy_init(struct net_device *dev); +static void mspeth_phy_reset(struct net_device *dev); +static int mspeth_proc_info(char *buf, char **buf_loc, off_t off, + int len, int *eof, void *data); +static void mspeth_set_arc_entry(struct net_device *dev, + int index, unsigned char *addr); +static void mspeth_check_tx_stat(struct net_device *dev, int status); +static int mspeth_phyprobe(struct net_device *dev); +static void mspeth_init_phyaddr(struct net_device *dev); +static void mspeth_init_cmdline(struct net_device *dev); +static void mspeth_fatal_error_interrupt(struct net_device *dev, + int status); + +/* + * Define the utility functions used by the the various other actual + * routines here. These should all be inline or macros. + */ + +/************************************************************************ + * flush_memqueue - Ensure all queued memory transactions are + * complete. + */ +#define flush_memqueue() blocking_read_reg32(MEM_CFG1_REG) + +#if defined(CONFIG_DMA_NONCOHERENT) && \ + (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)) +/************************************************************************ + * writeback_buffer - force the cache to write contents of cached buffer + * to memory and invalidate the buffer. Must start on cache line boundary, + * must "own" to next higher cache line boundary from end of buffer + * + * stjeanma, 2006-06-12: + * Use L1_CACHE_ALIGN to cache align the buffer rounding down to + * the next cache line. It is the resposibility of the caller to ensure + * that any partial cache line before the pointer isn't conflicting with + * other memory shared with the controller. + */ +inline static void +writeback_buffer(void *buf_addr, unsigned int length) +{ + unsigned long end = (unsigned long)buf_addr + length; + buf_addr = (void *)((unsigned long)buf_addr & + ~(L1_CACHE_BYTES - 1)); + + while ((unsigned long)buf_addr + UNROLL_INCR < end) { + CACHE_UNROLL(buf_addr, Hit_Writeback_Inv_D); + buf_addr += UNROLL_INCR; + } + + while ((unsigned long)buf_addr < end) { + flush_dcache_line((unsigned long)buf_addr); + buf_addr += L1_CACHE_BYTES; + } +} + +/************************************************************************ + * invalidate_buffer - Invalidate buffer cache + * - must start on cache line boundary + * - must "own" to next higher cache line boundary from end of buffer + * + * stjeanma, 2006-06-12: + * Use L1_CACHE_ALIGN to cache align the buffer rounding down to + * the next cache line. It is the resposibility of the caller to ensure + * that any partial cache line before the pointer isn't conflicting with + * other memory shared with the controller. + */ +inline static void +invalidate_buffer(void *buf_addr, unsigned int length) +{ + unsigned long end = (unsigned long)buf_addr + length; + buf_addr = (void *)((unsigned long)buf_addr & ~(L1_CACHE_BYTES - 1)); + + while ((unsigned long)buf_addr + UNROLL_INCR < end) { + CACHE_UNROLL(buf_addr, Hit_Invalidate_D); + buf_addr += UNROLL_INCR; + } + + while ((unsigned long)buf_addr < end) { + invalidate_dcache_line((unsigned long)buf_addr ); + buf_addr += L1_CACHE_BYTES; + } +} +#else +#define writeback_buffer(a, l) do {} while (0) +#define invalidate_buffer(a, l) do {} while (0) +#endif /* CONFIG_DMA_NONCOHERENT && LINUX_VERSION_CODE */ + +/************************************************************************ + * Read/Write a MSP eth register. + */ +inline static u32 +msp_read(struct mspeth_priv *lp, unsigned int offset) +{ + return __raw_readl(lp->mapaddr + offset); +} + +inline static void +msp_write(struct mspeth_priv *lp, unsigned int offset, u32 val) +{ + __raw_writel(val, lp->mapaddr + offset); +} + +/************************************************************************ + * Read/Write a MDIO register. + */ +static u32 +mspphy_read(struct mspeth_phy *phyptr, int phy_reg) +{ + unsigned long flags; + u32 data; + + if (phyptr == NULL) { + printk(KERN_WARNING "MSPETH(mspphy_read): " + "Cannot read from a NULL PHY!\n"); + return 0x0; + } + + /* protect access with spin lock */ + spin_lock_irqsave(&(phyptr->lock), flags); + + while (__raw_readl(phyptr->memaddr + MSPPHY_MII_CTRL) & + MD_CA_BUSY_BIT) {;} + __raw_writel(MD_CA_BUSY_BIT | phyptr->phyaddr << 5 | phy_reg, + phyptr->memaddr + MSPPHY_MII_CTRL); + while (__raw_readl(phyptr->memaddr + MSPPHY_MII_CTRL) & + MD_CA_BUSY_BIT) {;} + data = __raw_readl(phyptr->memaddr + MSPPHY_MII_DATA); + + /* unlock */ + spin_unlock_irqrestore(&(phyptr->lock), flags); + + return data & 0xffff; +} + +static void +mspphy_write(struct mspeth_phy *phyptr, int phy_reg, u32 data) +{ + unsigned long flags; + + if (phyptr == NULL) { + printk(KERN_WARNING "MSPETH(mspphy_write): " + "Cannot write to a NULL PHY!\n"); + return; + } + + /* protect access with spin lock */ + spin_lock_irqsave(&(phyptr->lock), flags); + + while (__raw_readl(phyptr->memaddr + MSPPHY_MII_CTRL) & + MD_CA_BUSY_BIT) {;} + __raw_writel(data, phyptr->memaddr + MSPPHY_MII_DATA); + __raw_writel(MD_CA_BUSY_BIT | MD_CA_Wr | + phyptr->phyaddr << 5 | phy_reg, + phyptr->memaddr + MSPPHY_MII_CTRL); + while (__raw_readl(phyptr->memaddr + MSPPHY_MII_CTRL) & + MD_CA_BUSY_BIT) {;} + + /* unlock */ + spin_unlock_irqrestore(&(phyptr->lock), flags); +} + +#ifdef CONFIG_MSPETH_SKB_RECYCLE +/* initialise the recycle bin for skb */ +static void +init_skbuff_bin(void) +{ + spin_lock_init(&skb_bin.lock); + skb_bin.recycle_max = RX_BUF_NUM * 4; /* max size of bin */ + skb_bin.recycle_count = 0; + skb_bin.recycle_queue = NULL; + skb_bin.user_count = 0; +} + +/* free the skb's in recycle bin */ +static void +free_skbuff_bin(void) +{ + spin_lock_bh(&skb_bin.lock); + + /* check any skb's are present in the recycle bin */ + if (skb_bin.recycle_count > 0) { + struct sk_buff *skb; + while (skb_bin.recycle_queue != NULL ) { + skb = skb_bin.recycle_queue->next; + dev_kfree_skb_any(skb_bin.recycle_queue); + skb_bin.recycle_queue = skb; + } + } + + /* reset fields */ + skb_bin.recycle_queue = NULL; + skb_bin.recycle_count = 0; + + spin_unlock_bh(&skb_bin.lock); +} + +inline static void +mspeth_skb_headerinit(struct sk_buff *skb) +{ + /* these are essential before init */ + dst_release(skb->dst); +#ifdef CONFIG_XFRM + secpath_put(skb->sp); +#endif +#ifdef CONFIG_NETFILTER + nf_conntrack_put(skb->nfct); +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) + nf_conntrack_put_reasm(skb->nfct_reasm); +#endif +#ifdef CONFIG_BRIDGE_NETFILTER + nf_bridge_put(skb->nf_bridge); +#endif +#endif /* CONFIG_NETFILTER */ + + /* now initialise the skb . . . */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + /* clear the members till skb->truesize */ + memset(skb, 0, offsetof(struct sk_buff, truesize)); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + skb->prev = NULL; + skb->list = NULL; + skb->sk = NULL; + skb->stamp.tv_sec = 0; +#ifdef CONFIG_BRECIS + skb->stamp.tv_usec = 0; +#endif /* CONFIG_BRECIS */ + skb->dev = NULL; + skb->real_dev = NULL; + skb->dst = NULL; + memset(skb->cb, 0, sizeof(skb->cb)); + skb->pkt_type = PACKET_HOST; + skb->priority = 0; + skb->security = 0; + +#ifdef CONFIG_NETFILTER + skb->nfmark = skb->nfcache = 0; + skb->nfct = NULL; +#ifdef CONFIG_NETFILTER_DEBUG + skb->nf_debug = 0; +#endif +#if defined(CONFIG_BRIDGE) || defined(CONFIG_BRIDGE_MODULE) + skb->nf_bridge = NULL; +#endif +#endif /* CONFIG_NETFILTER */ +#ifdef CONFIG_NET_SCHED + skb->tc_index = 0; +#endif +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) + skb->nfct_reasm = NULL; +#endif +#endif /* LINUX_VERSION_CODE */ +} +#endif /* CONFIG_MSPETH_SKB_RECYCLE */ + +/************************************************************************** + * Allocate and align a max length socket buffer for this device + */ +inline static struct sk_buff * +mspeth_alloc_skb(struct net_device *dev) +{ + struct sk_buff *skb = NULL; + +#ifdef CONFIG_MSPETH_SKB_RECYCLE + /* try to get an skb from the recycle bin */ + spin_lock_bh(&skb_bin.lock); + + /* check if the bin si empty */ + if (skb_bin.recycle_queue) { + /* grab an skb from the bin */ + skb = skb_bin.recycle_queue; + skb_bin.recycle_queue = skb->next; + + /* we have taken one, so reduce the count */ + skb_bin.recycle_count--; + skb_bin.recycle_hits++; + spin_unlock_bh(&skb_bin.lock); + + skb->next = NULL; /* must be set to NULL */ + skb->truesize = (skb->end - skb->head) + + sizeof(struct sk_buff); + atomic_set(&skb->users, 1); + + /* reset the payload pointers */ + skb->data = skb->head; + skb->tail = skb->head; + + /* reset shared info fields */ + atomic_set(&(skb_shinfo(skb)->dataref), 1); + skb_shinfo(skb)->nr_frags = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + skb_shinfo(skb)->gso_size = 0; + skb_shinfo(skb)->gso_segs = 0; +#endif + skb_shinfo(skb)->frag_list = NULL; + + /* compliance with __dev_alloc_skb */ + skb_reserve(skb, NET_SKB_PAD); + } else { + /* no skb in bin */ + spin_unlock_bh(&skb_bin.lock); + } +#endif /* CONFIG_MSPETH_SKB_RECYCLE */ + + if (skb == NULL) { + /* + * We need a bit more than an ethernet frame for the + * aligment stuff so preallocate two more. + */ + skb = dev_alloc_skb(MSP_END_BUFSIZE + 2); +#ifdef CONFIG_MSPETH_SKB_RECYCLE + skb_bin.recycle_misses++; +#endif + if (skb == NULL) { + printk(KERN_WARNING "MSPETH(alloc_skb) %s: " + "cannot allocate skb!\n", dev->name); + return NULL; + } + } + + /* + * Align and fill out fields specific to our device. Notice that + * our device is smart about FCS etc ...... + */ + skb_reserve(skb, 2); + skb->dev = dev; + skb->ip_summed = CHECKSUM_NONE; + + return skb; +} + +/************************************************************************** + * Add the used skb to recycle bin or free it + */ +inline static void +mspeth_free_skb(struct sk_buff *skb) +{ +#ifdef CONFIG_MSPETH_SKB_RECYCLE + /* + * First try to recycle the skb. + * Check if the skb can be recycled. + */ + if ((skb->end - skb->head) >= SKBUFF_RECYCLABLE_SIZE && + (!skb->destructor) && + (!skb->cloned) && + (atomic_dec_and_test(&skb->users))) { + /* skb is recyclable */ + spin_lock_bh(&skb_bin.lock); + + /* check the bin has room to add our skb */ + if (likely(skb_bin.recycle_count < skb_bin.recycle_max)) { + /* everything ok; go recycle it */ + /* prerequisite before adding to recycle bin */ + mspeth_skb_headerinit(skb); + + /* now we can add the skb to bin */ + skb->next = skb_bin.recycle_queue; + skb_bin.recycle_queue = skb; + + /* we have one more skb in bin, increase the count */ + skb_bin.recycle_count++; + + spin_unlock_bh(&skb_bin.lock); + return; + } else { + /* bin has no room */ + spin_unlock_bh(&skb_bin.lock); + } + } +#endif /* CONFIG_MSPETH_SKB_RECYCLE */ + + /* Can't add skb to recycle bin, so free it in normal way. */ + dev_kfree_skb_any(skb); +} + +/************************************************************************** + * Error reporting functions -- used for debugging mostly + */ +static void +dump_qdesc(struct q_desc *fd) +{ + printk(KERN_INFO " q_desc(%p): %08x %08x %08x %08x\n", + fd, fd->fd.FDNext, fd->fd.FDSystem, + fd->fd.FDStat, fd->fd.FDCtl); + printk(KERN_INFO " BD: %08x %08x\n", + fd->bd.BuffData, fd->bd.BDCtl); +} + +static void +print_buf(char *add, int length) +{ + int i; + int len = length; + + printk(KERN_INFO "print_buf(%08x)(%x)\n", + (unsigned int)add, length); + + if (len > 100) + len = 100; + for (i = 0; i < len; i++) { + printk(KERN_INFO " %2.2X", (unsigned char)add[i]); + if (!(i % 16)) + printk(KERN_INFO "\n"); + } + printk(KERN_INFO "\n"); +} + +static void +print_eth(int rx, char *add, int len) +{ + int i; + int lentyp; + + if (rx) + printk(KERN_INFO "\n************************** RX packet " + "0x%08x ****************************\n", (u32)add); + else + printk(KERN_INFO "\n************************** TX packet " + "0x%08x ****************************\n", (u32)add); + + printk(KERN_INFO "---- ethernet ----\n"); + printk(KERN_INFO "==> dest: "); + for (i = 0; i < 6; i++) { + printk(KERN_INFO "%02x", (unsigned char)add[i]); + printk((i < 5) ? KERN_INFO ":" : KERN_INFO "\n"); + } + + printk(KERN_INFO "==> src: "); + for (i = 0; i < 6; i++) { + printk(KERN_INFO "%02x", (unsigned char)add[i + 6]); + printk((i < 5) ? KERN_INFO ":" : KERN_INFO "\n"); + } + lentyp = ((unsigned char)add[12] << 8) | (unsigned char)add[13]; + if (lentyp <= 1500) + printk(KERN_INFO "==> len: %d\n", lentyp); + else if (lentyp > 1535) + printk(KERN_INFO "==> type: 0x%04x\n", lentyp); + else + printk(KERN_INFO "==> ltyp: 0x%04x\n", lentyp); + + if (len > 0x100) + len = 0x100; + + for (i = 0; i < ((u32)add & 0x0000000F); i++) + printk(KERN_INFO " "); + for (i = 0; i < len; i++, add++) { + printk(KERN_INFO " %02x", *((unsigned char *)add)); + if (!(((u32)add + 1) % 16)) + printk(KERN_INFO "\n"); + } + printk(KERN_INFO "\n"); +} + +/* + * Used mainly for debugging unusual conditions signalled by a + * fatal error interrupt (eg, IntBLEx). This function stops the transmit + * and receive in an attempt to capture the true state of the queues + * at the time of the interrupt. + */ +#undef MSPETH_DUMP_QUEUES +#ifdef MSPETH_DUMP_QUEUES +static void +dump_blist(struct bl_desc *fd) +{ + int i; + + printk(KERN_INFO " bl_desc(%p): %08x %08x %08x %08x\n", + fd, fd->fd.FDNext, + fd->fd.FDSystem, fd->fd.FDStat, fd->fd.FDCtl); + for (i = 0; i < RX_BUF_NUM << 1; i++) + printk(KERN_INFO " BD #%d: %08x %08x\n", + i, fd->bd[i].BuffData, fd->bd[i].BDCtl); +} + +/* Catalog the received buffers numbers */ +static int rx_bdnums[2][RX_BUF_NUM << 2]; +static int rx_bdnums_ind[2] = {0, 0}; +static inline void +catalog_rx_bdnum(int hwnum, int bdnum) +{ + rx_bdnums_ind[hwnum] = (rx_bdnums_ind[hwnum] + 1) & + ((RX_BUF_NUM << 2) - 1); + rx_bdnums[hwnum][rx_bdnums_ind[hwnum]] = bdnum; +} + +static void +mspeth_dump_queues(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + int unit = lp->unit; + int i; + + /* Halt Xmit and Recv to preserve the state of queues */ + msp_write(lp, MSPETH_Rx_Ctl, msp_read(lp, MSPETH_Rx_Ctl) & ~Rx_RxEn); + msp_write(lp, MSPETH_Tx_Ctl, msp_read(lp, MSPETH_Tx_Ctl) & ~Tx_En); + + /* Print receive queue */ + printk(KERN_INFO "Receive Queue\n"); + printk(KERN_INFO "=============\n\n"); + printk(KERN_INFO "rxfd_base = 0x%08x\n", + (unsigned int) lp->rxfd_base); + printk(KERN_INFO "rxfd_curr = 0x%08x\n", + (unsigned int) lp->rxfd_curr); + for (i = 0; i < RX_BUF_NUM; i++) { + printk(KERN_INFO "%d:", i); + dump_qdesc((struct q_desc *) &lp->rxfd_base[i]); + } + + /* Print transmit queue */ + printk(KERN_INFO "\nTransmit Queue\n"); + printk(KERN_INFO "==============\n"); + printk(KERN_INFO "txfd_base = 0x%08x\n", + (unsigned int) lp->txfd_base); + printk(KERN_INFO "tx_head = %d, tx_tail = %d\n", + lp->tx_head, lp->tx_tail); + for (i = 0; i < TX_BUF_NUM; i++) { + printk(KERN_INFO "%d:", i); + dump_qdesc((struct q_desc *) &lp->txfd_base[i]); + } + + /* Print the free buffer list */ + printk(KERN_INFO "\nFree Buffer List\n"); + printk(KERN_INFO "================\n"); + printk(KERN_INFO "blfd_ptr = 0x%08x\n", (unsigned int) lp->blfd_ptr); + dump_blist(lp->blfd_ptr); + + /* Print the bdnum history and current index as a reference */ + printk(KERN_INFO "\nbdnum history\n"); + printk(KERN_INFO "=============\n"); + for (i = 0; i < RX_BUF_NUM; i++) { + printk(KERN_INFO "\t%d\t%d\t%d\t%d\n", + rx_bdnums[unit][4 * i], + rx_bdnums[unit][4 * i + 1], + rx_bdnums[unit][4 * i + 2], + rx_bdnums[unit][4 * i + 3]); + } + printk(KERN_INFO "Current bdnum index: %d\n", rx_bdnums_ind[unit]); + + /* Re-enable Xmit/Recv */ + msp_write(lp, MSPETH_Rx_Ctl, msp_read(lp, MSPETH_Rx_Ctl) | Rx_RxEn); + msp_write(lp, MSPETH_Tx_Ctl, msp_read(lp, MSPETH_Tx_Ctl) | Tx_En); +} + +static void +mspeth_dump_stats(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + + printk(KERN_INFO "Interface stats:\n"); + printk(KERN_INFO "\ttx_ints: %d\n", lp->lstats.tx_ints); + printk(KERN_INFO "\trx_ints: %d\n", lp->lstats.rx_ints); + printk(KERN_INFO "\ttx_full: %d\n", lp->lstats.tx_full); + printk(KERN_INFO "\tfd_exha: %d\n", lp->lstats.fd_exha); +} +#else +#define mspeth_dump_stats(a) do {} while (0) +#define mspeth_dump_queues(a) do {} while (0) +#define catalog_rx_bdnum(a, b) do {} while (0) +#define dump_blist(a) do {} while (0) +#endif /* MSPETH_DUMP_QUEUES */ + +/* + * Actual functions used in the driver are defined here. They should + * all start with mspeth. + */ + +/************************************************************************** + * Check for an mspeth ethernet device and return 0 if there is one. + * Also a good time to fill out some of the device fields and do some + * preliminary initialization. The mspeth resources are statically + * allocated. + */ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +int mspeth_probe(struct platform_device *pldev) +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +int __init mspeth_probe(struct net_device *dev) +#endif +{ + int unit, hwunit; + int i, err; + u8 macaddr[8]; + struct mspeth_priv *lp; + char tmp_str[128]; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + struct net_device *dev = NULL; + struct resource *res; + void *mapaddr; + unit = pldev->id; +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + sscanf(dev->name, "eth%d", &unit); +#endif + + /* default return value -- no device here */ + err = -ENODEV; + + /* + * Scan the hardware list and associate a logical unit with a + * hardware unit it's important to keep these two straight. + * hwunit is used for accessing the prom and all hardware. + * unit is used when parsing the commandline and any other + * uses that might refer to *all* eth devices (not just mspeth + * devices) in the system. + */ + for (i = 0, hwunit = 0; hwunit < MSPETH_MAX_UNITS; hwunit++) { + if (identify_enet(hwunit) != FEATURE_NOEXIST) + if (i++ == unit) + break; + } + + /* Sanity checks on hardware parameters */ + if (unit < 0 || hwunit >= MSPETH_MAX_UNITS) + goto out_err; + + /* Retrieve the mac address from the PROM */ + snprintf(tmp_str, 128, "ethaddr%d", hwunit); + if (get_ethernet_addr(tmp_str, macaddr)) { + printk(KERN_WARNING "MSPETH(probe): " + "No Mac addr specified for eth%d, hwunit %d\n", + unit, hwunit); + goto out_err; + } + + if (macaddr[0] & 0x01) { + printk(KERN_WARNING "MSPETH(probe): " + "Bad Multicast Mac addr specified for eth%d, " + "hwunit %d %02x:%02x:%02x:%02x:%02x:%02x\n", + unit, hwunit, + macaddr[0], macaddr[1], macaddr[2], + macaddr[3], macaddr[4], macaddr[5]); + goto out_err; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + dev = alloc_etherdev(sizeof(struct mspeth_priv)); + if (!dev) { + err = -ENOMEM; + goto out_err; + } + + SET_MODULE_OWNER(dev); + SET_NETDEV_DEV(dev, &pldev->dev); + dev_set_drvdata(&pldev->dev, dev); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + /* Create & initialize the local device structure */ + if (dev->priv == NULL) { + dev->priv = kmalloc(sizeof(struct mspeth_priv), + GFP_KERNEL); + if (dev->priv == NULL) + goto out_err; + } +#endif + + lp = netdev_priv(dev); + memset(lp, 0, sizeof(struct mspeth_priv)); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + lp->dev = &pldev->dev; + + res = platform_get_resource(pldev, IORESOURCE_MEM, 0); + if (!res) { + printk(KERN_ERR "MSPETH(probe) %s: " + "IOMEM resource not found for eth%d\n", + dev->name, unit); + goto out_netdev; + } + + /* reserve the memory region */ + if (!request_mem_region(res->start, res->end - res->start + 1, + cardname)) { + printk(KERN_ERR "MSPETH(probe) %s: unable to " + "get memory/io address region 0x08%lx\n", + dev->name, dev->base_addr); + goto out_netdev; + } + + /* remap the memory */ + mapaddr = ioremap_nocache(res->start, res->end - res->start + 1); + if (!mapaddr) { + printk(KERN_WARNING "MSPETH(probe) %s: " + "unable to ioremap address 0x%08x\n", + dev->name, res->start); + goto out_unreserve; + } + + lp->mapaddr = mapaddr; + dev->base_addr = res->start; + dev->irq = platform_get_irq(pldev, 0); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + /* + * Dig out the parameters from the defines and do other + * hwunit specific stuff + */ + switch (hwunit) { + case 0: + dev->base_addr = MSP_MAC0_BASE; + dev->irq = MSP_INT_MAC0; + break; + case 1: + dev->base_addr = MSP_MAC1_BASE; + dev->irq = MSP_INT_MAC1; + break; + case 2: + dev->base_addr = MSP_MAC2_BASE; + dev->irq = MSP_INT_MAC2; + break; + default: + printk(KERN_WARNING "MSPETH(probe): " + "Unsupported hardware unit %d\n", hwunit); + goto out_unmap; + } + + /* reserve the memory region */ + if (!request_mem_region(dev->base_addr, MSP_MAC_SIZE, cardname)) { + printk(KERN_ERR "MSPETH(probe) %s: unable to " + "get memory/io address region 0x08%lx\n", + dev->name, dev->base_addr); + goto out_err; + } + + /* remap the memory */ + lp->mapaddr = ioremap_nocache(dev->base_addr, MSP_MAC_SIZE); + if (!lp->mapaddr) { + printk(KERN_ERR "MSPETH(probe) %s: unable to " + "ioremap address 0x%08lx\n", + dev->name, dev->base_addr); + goto out_unreserve; + } +#endif + + /* remap the system reset registers */ + lp->rstaddr = ioremap_nocache(MSP_RST_BASE, MSP_RST_SIZE); + if (!lp->rstaddr) { + printk(KERN_ERR "MSPETH(probe) %s: unable to " + "ioremap address 0x%08x\n", + dev->name, MSP_RST_BASE); + goto out_unmap; + } + + /* set the logical and hardware units */ + lp->unit = unit; + lp->hwunit = hwunit; + + /* probe for PHYS attached to this MACs MDIO interface */ + if (mspeth_phyprobe(dev)) + goto out_unmap; + + /* parse the environment and command line */ + mspeth_init_cmdline(dev); + mspeth_init_phyaddr(dev); + + /* MAC address */ + dev->addr_len = ETH_ALEN; + for (i = 0; i < dev->addr_len; i++) + dev->dev_addr[i] = macaddr[i]; + + /* register the /proc entry */ + snprintf(tmp_str, 128, "pmcmspeth%d", unit); + create_proc_read_entry(tmp_str, 0644, proc_net, + mspeth_proc_info, dev); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)) + ether_setup(dev); +#endif + /* set the various call back functions */ + dev->open = mspeth_open; + dev->stop = mspeth_close; + dev->tx_timeout = mspeth_tx_timeout; + dev->watchdog_timeo = TX_TIMEOUT * HZ; + dev->hard_start_xmit = mspeth_send_packet; + dev->get_stats = mspeth_get_stats; + dev->set_multicast_list = mspeth_set_multicast_list; +#ifdef CONFIG_MSPETH_NAPI + dev->poll = mspeth_poll; + dev->weight = NAPI_WEIGHT; +#endif + + /* debugging output */ + printk(KERN_INFO + "eth%d: found at physical address %lx, irq %d\n", + unit, dev->base_addr, dev->irq); + if (mspeth_debug > 1) { + printk(KERN_INFO "MSPETH(probe) eth%d: " + "associated with hardware unit %d\n", + unit, hwunit); + printk(KERN_INFO "MSPETH(probe) eth%d: assigned " + "MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", + unit, macaddr[0], macaddr[1], macaddr[2], + macaddr[3], macaddr[4], macaddr[5]); + printk(KERN_INFO "MSPETH(probe) eth%d: " + "phytype %c, phyclk %c\n", + unit, identify_enet(hwunit), + identify_enetTxD(hwunit)); + } + +#ifdef CONFIG_MSPETH_SKB_RECYCLE + /* initialize the socket buffer recycle bin */ + init_skbuff_bin(); +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + err = register_netdev(dev); + if (err) { + printk(KERN_WARNING "MSPETH(probe) eth%d: " + "unable to register network device\n", unit); + goto out_unmap; + } +#endif + + return 0; + +out_unmap: + if (lp->rstaddr) + iounmap(lp->rstaddr); + iounmap(lp->mapaddr); + +out_unreserve: +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + release_mem_region(res->start, res->end - res->start + 1); + +out_netdev: + free_netdev(dev); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + release_mem_region(dev->base_addr, MSP_MAC_SIZE); +#endif + +out_err: + return err; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +/************************************************************************** + * Release the mspeth ethernet device and return 0 if there is one. + */ +static int +mspeth_remove(struct platform_device *pldev) +{ + struct net_device *dev = dev_get_drvdata(&pldev->dev); + struct mspeth_priv *lp = netdev_priv(dev); + struct mspeth_phy **tail_pp; + +#ifdef CONFIG_MSPETH_SKB_RECYCLE + skb_bin.user_count--; + if (skb_bin.user_count == 0) { + /* free the recycle bin */ + free_skbuff_bin(); + } +#endif + + for (tail_pp = &root_phy_dev; *tail_pp != NULL; ) { + struct mspeth_phy **next_pp = &((*tail_pp)->next_phy); + kfree(*tail_pp); + tail_pp = next_pp; + } + + unregister_netdev(dev); + + iounmap(lp->rstaddr); + lp->rstaddr = NULL; + iounmap(lp->mapaddr); + lp->mapaddr = NULL; + release_mem_region(dev->base_addr, MSP_MAC_SIZE); + + free_netdev(dev); + + return 0; +} +#endif + +/************************************************************************** + * Probe the hardware and fill out the array of PHY control elements + */ +static int +mspeth_phyprobe(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + u32 reg1; + int phyaddr; + struct mspeth_phy tmp_phy; + struct mspeth_phy **tail_pp; + + tmp_phy.next_phy = NULL; + tmp_phy.hwunit = lp->hwunit; + tmp_phy.phyaddr = 0; + tmp_phy.memaddr = lp->mapaddr + MSPETH_MD_DATA; + tmp_phy.assigned = false; + tmp_phy.linkup = false; + spin_lock_init(&tmp_phy.lock); + + /* find the tail of the phy list */ + for (tail_pp = &root_phy_dev; *tail_pp != NULL; + tail_pp = &((*tail_pp)->next_phy)) {;} + + /* probe the phys and add to list */ + for (phyaddr = 0; phyaddr < MD_MAX_PHY; phyaddr++) { + tmp_phy.phyaddr = phyaddr; + reg1 = mspphy_read(&tmp_phy, MII_BMSR); + + if ((reg1 & BMSR_EXISTS) && + reg1 != 0xffff && reg1 != 0xc000) { + if (mspeth_debug > 1) + printk(KERN_INFO "MSPETH(phyprobe): " + "phyaddr = %d, hwindex = %d has " + "phy status 0x%04x\n", + phyaddr, lp->hwunit, reg1); + + *tail_pp = kmalloc(sizeof(struct mspeth_phy), + GFP_KERNEL); + if (!*tail_pp) { + printk(KERN_WARNING "MSPETH(phyprobe) " + "eth%d: unable to allocate phy\n", + lp->hwunit); + return -1; + } + + **tail_pp = tmp_phy; + spin_lock_init(&((*tail_pp)->lock)); + tail_pp = &((*tail_pp)->next_phy); + } + } + + return 0; +} + +/************************************************************************** + * Scan the environment and fill the phyaddresses + */ +static void +mspeth_init_phyaddr(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + int hwunit; + int phyaddr; + char *phystr; + char name[80]; + + /* defaults */ + lp->phyptr = NULL; + + /* new style enviroment scan to determine the phy addresses */ + sprintf(name, "phyaddr%d", lp->hwunit); + phystr = prom_getenv(name); + + if (mspeth_debug > 0) + printk(KERN_INFO "MSPETH(init_phyaddr): " + "hwunit = %d, phystr prom = \"%s\"\n", + lp->hwunit, phystr); + + if (phystr != NULL && + sscanf(phystr, "%d:%d", &hwunit, &phyaddr) == 2 && + hwunit < MSPETH_MAX_UNITS && + (phyaddr < MD_MAX_PHY || phyaddr == MD_DYNAMIC_PHY)) { + /* + * Look through the phylist and find a phy that matches + * the PROM settings + */ + for (lp->phyptr = root_phy_dev; lp->phyptr != NULL; + lp->phyptr = lp->phyptr->next_phy) { + if (lp->phyptr->phyaddr == phyaddr && + lp->phyptr->hwunit == hwunit) { + if (lp->phyptr->assigned) { + lp->phyptr = NULL; + printk(KERN_WARNING + "MSPETH(init_phyaddr) %s: " + "PROM phyaddress is already " + "in use!\ + phystr prom = \"%s\"\n", + dev->name, phystr); + } else + lp->phyptr->assigned = true; + + break; + } + } + } else { + /* + * No acceptable PROM settings so we have to make + * something up + */ + if (lp->option & MSP_OPT_SWITCH) { + /* + * Commandline set us to a switch so no phy + * settings required. Consider changing this later + * so that we can access the registers in the + * switch through MDIO etc. Could be autoprobed too. + */ + } else { + /* + * Search through the list of phys and use the + * first unassigned one. We need some way of + * determining which phy is connected to which + * MAC other than first come, first serve. + * + * stjeanma, 2006-02-13: + * We must keep all PHYs on a global list for + * boards which have all PHY MDIOs hooked to a + * single MAC. However for boards with PHYs hooked + * up to inidvidual MACs, we must first search the + * list for PHYs belonging to the MAC being + * initialized. + */ + for (lp->phyptr = root_phy_dev; lp->phyptr != NULL; + lp->phyptr = lp->phyptr->next_phy) { + if (!lp->phyptr->assigned && + lp->phyptr->hwunit == lp->hwunit) { + lp->phyptr->assigned = true; + break; + } + } + + if (lp->phyptr == NULL) { + for (lp->phyptr = root_phy_dev; + lp->phyptr != NULL; + lp->phyptr = lp->phyptr->next_phy) { + if (!lp->phyptr->assigned) { + lp->phyptr->assigned = true; + break; + } + } + } + } + + /* rudimentary error checking */ + if (phystr != NULL) + printk(KERN_WARNING "MSPETH(init_phyaddr) " + "eth%d: bad phyaddr value %s\n", + lp->unit, phystr); + } +} + +/************************************************************************** + * Scan the environment to get the kernel command line options + * for ethernet. + */ +static void +mspeth_init_cmdline(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + int index; + int unit; + char c = ' '; + char command_line[COMMAND_LINE_SIZE]; + char *ptr = command_line; + char *ethptr = NULL; + + /* default options */ + lp->option = MSP_OPT_AUTO; + + /* scan the command line looking for static configurations */ + strcpy(command_line, prom_getcmdline()); + while (c != '\0') { + if (c != ' ' || memcmp(ptr, "ip=", 3) != 0) { + c = *ptr++; + continue; + } + + c = *ptr++; + index = 0; + unit = -1; + + while (index < 8) { + c = *ptr++; + + if (c == '\0' || c == ' ') { + if (index == 7) { + index++; + *--ptr = '\0'; + ptr++; + } + break; + } + + if (c == ':') { + index++; + if (index == 5) { + if (memcmp(ptr, "eth", 3) != 0) + break; + + ethptr = &ptr[3]; + ptr = ethptr; + } + + if (index == 6) { + *--ptr = '\0'; + ptr++; + unit = simple_strtol( + ethptr, NULL, 0); + } + + if (index == 7) { + ethptr = ptr; + } + + if (index == 8) { + *--ptr = '\0'; + ptr++; + } + } + } + + if (index < 8 || unit < 0 || unit > MSPETH_MAX_UNITS) + continue; + + /* check to see if this our option and parse them out */ + if (lp->unit == unit) { + if (memcmp(ethptr, "100fs", 5) == 0) + /* 100M full-duplex switch */ + lp->option = MSP_OPT_100M | MSP_OPT_FDUP | + MSP_OPT_SWITCH; + else if (memcmp(ethptr, "100hs", 5) == 0) + /* 100M half-duplex switch */ + lp->option = MSP_OPT_100M | MSP_OPT_HDUP | + MSP_OPT_SWITCH; + else if (memcmp(ethptr, "10fs", 4) == 0) + /* 10M full-duplex switch */ + lp->option = MSP_OPT_10M | MSP_OPT_FDUP | + MSP_OPT_SWITCH; + else if (memcmp(ethptr, "10hs", 4) == 0) + /* 10M half-duplex switch */ + lp->option = MSP_OPT_100M | MSP_OPT_HDUP | + MSP_OPT_SWITCH; + else if (memcmp(ethptr, "100f", 4) == 0) + /* 100M full-duplex */ + lp->option = MSP_OPT_100M | MSP_OPT_FDUP; + else if (memcmp(ethptr, "100h", 4) == 0) + /* 100M half-duplex */ + lp->option = MSP_OPT_100M | MSP_OPT_HDUP; + else if (memcmp(ethptr, "10f", 3) == 0) + /* 10M full-duplex */ + lp->option = MSP_OPT_10M | MSP_OPT_FDUP; + else if (memcmp(ethptr, "10h", 3) == 0) + /* 100M half-duplex */ + lp->option = MSP_OPT_10M | MSP_OPT_HDUP; + } + + if (mspeth_debug > 0) + printk(KERN_INFO "MSPETH(init_cmdline) eth%d: " + "boot = %s, option = %02x\n", + lp->unit, command_line, lp->option); + } +} + +/************************************************************************** + * Reset the phy + */ +static void +mspeth_phy_reset(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + u32 id0, id1; + + if (lp->phyptr == NULL) + return; + + /* reset the phy */ + mspphy_write(lp->phyptr, MII_BMCR, BMCR_RESET); + while ((mspphy_read(lp->phyptr, MII_BMCR) & BMCR_RESET) != 0) + udelay(100); + + if (mspeth_debug > 0) { + id0 = mspphy_read(lp->phyptr, MII_PHYSID1); + id1 = mspphy_read(lp->phyptr, MII_PHYSID2); + printk(KERN_INFO "MSPETH(phy_reset) eth%d: " + "PHY ID %04x %04x\n", lp->unit, id0, id1); + printk(KERN_INFO "MSPETH(phy_reset) eth%d: " + "speed = %d, duplex = %s\n", lp->unit, lp->speed, + ((lp->fullduplex) ? "FULL" : "HALF")); + } +} + +/************************************************************************** + * Initialize the phy -- set the speed and duplex. Wait for + * autonegotiation to complete. If it doesn't then force the + * renegotiation. If *that* fails then reset the phy and try + * again. Finally just make some assumptions. If autonegotiation + * is disabled then just force values. + */ +static void +mspeth_phy_init(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + u32 ctl, neg_result; + int i; + enum {AUTONEG, AUTONEG_FORCE, PHYRESET} auto_status; + char *link_type; + char *link_stat; + + /* check for defaults and autonegotiate */ + if (lp->option == MSP_OPT_AUTO) { + /* + * Make sure the autonegotiation is enabled and then wait + * for the autonegotion to complete. + */ + link_type = "Autoneg"; + for (auto_status = AUTONEG; auto_status <= PHYRESET; + auto_status++) { + /* + * Run through all the various autonegotion methods + * until we fail + */ + switch (auto_status) { + case AUTONEG: + mspphy_write(lp->phyptr, MII_BMCR, + BMCR_ANENABLE); + break; + case AUTONEG_FORCE: + printk(KERN_INFO "MSPETH(phy_init) " + "%s: Forcing autonegotiation\n", + dev->name); + mspphy_write(lp->phyptr, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); + break; + case PHYRESET: + printk(KERN_INFO "MSPETH(phy_init) " + "%s: Resetting phy\n", dev->name); + mspphy_write(lp->phyptr, MII_BMCR, + BMCR_RESET); + while ((mspphy_read(lp->phyptr, MII_BMCR) & + BMCR_RESET) != 0) + udelay(100); + mspphy_write(lp->phyptr, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); + break; + default: + printk(KERN_WARNING "MSPETH(phy_init) " + "%s: Unknown autonegotation mode?\n", + dev->name); + return; + } + + /* + * Autoneg should be underway, so lets loop + * and wait for it to exit. + */ + printk(KERN_INFO + "%s: Auto Negotiation...", dev->name); + + for (i = 0; i < 2000 && + !(mspphy_read(lp->phyptr, MII_BMSR) & + BMSR_ANEGCOMPLETE); i++) { + mdelay(1); + } + + if (i == 2000) { + /* + * Autonegotiation failed to complete so + * go to next level of negotiation. + */ + printk(KERN_INFO " failed.\n"); + continue; + } + + /* must have succeeded so we can set the speed etc */ + printk(KERN_INFO " done.\n"); + neg_result = mspphy_read(lp->phyptr, MII_LPA); + if (neg_result & (LPA_100FULL | LPA_100HALF)) + lp->speed = 100; + else + lp->speed = 10; + + if (neg_result & (LPA_100FULL | LPA_10FULL)) + lp->fullduplex = true; + else + lp->fullduplex = false; + break; + } + + /* + * Check to see if *everything* failed and try to set + * some default values. + */ + if (auto_status > PHYRESET) { + printk(KERN_WARNING "Autonegotion failed. " + "Assuming 10Mbps, half-duplex.\n"); + link_type = "Autoneg (failed)"; + lp->speed = 10; + lp->fullduplex = false; + } + } else { + /* + * If speed and duplex are statically configured then + * set that here. + */ + link_type = "Static"; + ctl = 0; + if (lp->option & MSP_OPT_100M) { + lp->speed = 100; + ctl |= BMCR_SPEED100; + } else { + lp->speed = 10; + ctl &= ~BMCR_SPEED100; + } + + if (lp->option & MSP_OPT_FDUP) { + lp->fullduplex = true; + ctl |= BMCR_FULLDPLX; + } else { + lp->fullduplex = false; + ctl &= ~BMCR_FULLDPLX; + } + + /* stjeanma: Don't write to the PHY for a switch */ + if (!(lp->option & MSP_OPT_SWITCH)) + mspphy_write(lp->phyptr, MII_BMCR, ctl); + } + + if (!(lp->option & MSP_OPT_SWITCH)) { + /* + * Wait for a little bit to see if we've got a carrier + * -- don't go crazy though. + */ + printk(KERN_INFO + "%s: Waiting for carrier ...", dev->name); + for (i = 0; i < 1000 && + !(mspphy_read(lp->phyptr, MII_BMSR) & + BMSR_LSTATUS); i++) { + mdelay(1); + } + + if (i == 1000) { + printk(KERN_INFO " no carrier.\n"); + lp->phyptr->linkup = false; + netif_carrier_off(dev); + link_stat = "Link down"; + } else { + printk(KERN_INFO " carrier detected.\n"); + lp->phyptr->linkup = true; + netif_carrier_on(dev); + link_stat = "Link up"; + } + } else { + + /* + * Assume we're connected. If we're using a switch + * we always will be. + */ + printk(KERN_INFO + "%s: Using internal switch\n", dev->name); + + /* stjeanma: PHY might not be allocated for a switch */ + if (lp->phyptr != NULL) + lp->phyptr->linkup = true; + + /* Turn on the carrier */ + netif_carrier_on(dev); + link_stat = "Link up"; + } + + /* + * Configure the MAC with the duplex setting + * -- it doesn't care about speed. + */ + if (lp->fullduplex) + msp_write(lp, MSPETH_MAC_Ctl, + msp_read(lp, MSPETH_MAC_Ctl) | MAC_FullDup); + else + msp_write(lp, MSPETH_MAC_Ctl, + msp_read(lp, MSPETH_MAC_Ctl) & ~MAC_FullDup); + + printk(KERN_INFO + "%s: %s, %s, linkspeed %dMbps, %s Duplex\n", + dev->name, link_type, link_stat, lp->speed, + (lp->fullduplex) ? "Full" : "Half"); +} + +/************************************************************************** + * Check the link for a carrier when the link check timer expires. + * If the link is down and it has been down for a while (at least 1 + * timer delay) then change the upper layer link state to match. + * Do a soft-restart if we're bringing the link up. Reschedule the + * timer of course. + */ +static void +mspeth_link_check(unsigned long data) +{ + struct net_device *dev = (struct net_device *)data; + struct mspeth_priv *lp = netdev_priv(dev); + enum {LINKGOOD, LINKBAD, LINKUNKNOWN} linkstatus; + + /* check the current link status */ + linkstatus = LINKUNKNOWN; + if (mspphy_read(lp->phyptr, MII_BMSR) & BMSR_LSTATUS) { + if (lp->phyptr->linkup) + linkstatus = LINKGOOD; + lp->phyptr->linkup = true; + } else { + if (!lp->phyptr->linkup) + linkstatus = LINKBAD; + lp->phyptr->linkup = false; + } + + /* check the upper layer status */ + if (netif_carrier_ok(dev)) { + /* + * Upper layer thinks we're ok but the link is bad, so + * take the link down. + */ + if (linkstatus == LINKBAD) { + printk(KERN_INFO "MSPETH(link_check) %s: " + "NO LINK DETECTED\n", dev->name); + netif_stop_queue(dev); + netif_carrier_off(dev); + } + } else { + /* + * Upper layer thinks we're broken but we've recovered so + * do a soft-restart and bring the link back up. + */ + if (linkstatus == LINKGOOD) { + printk(KERN_INFO "MSPETH(link_check) %s: " + "LINK DETECTED\n", dev->name); + mspeth_soft_restart(dev); + netif_carrier_on(dev); + } + } + + /* reschedule the timer */ + lp->link_timer.expires = jiffies + HZ / LINK_DELAY_DIV; + add_timer(&lp->link_timer); +} + +/************************************************************************** + * Reset the hardware and restore defaults. Queues etc must be + * cleared afterwards, although we don't change the pointers so + * they don't need to be reallocated. + */ +static void +mspeth_mac_reset(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + int i; + u32 rstpat; + + /* hardware reset */ + switch (lp->hwunit) { + case 0: + rstpat = MSP_EA_RST; + break; + case 1: + rstpat = MSP_EB_RST; + break; + case 2: + rstpat = MSP_EC_RST; + break; + default: + printk(KERN_WARNING + "MSPETH(mac_reset) %s: Unsupported hwunit %d\n", + dev->name, lp->hwunit); + return; + } + + __raw_writel(rstpat, lp->rstaddr + MSPRST_SET); + mdelay(100); + __raw_writel(rstpat, lp->rstaddr + MSPRST_CLR); + + /* Wait for the MAC to come out of reset */ + for (i = 0; i < 10; i++) { + if ((__raw_readl(lp->rstaddr + MSPRST_STS) & rstpat) == 0) + break; + ndelay(100); + } + + /* initialize registers to default value */ + msp_write(lp, MSPETH_MAC_Ctl, 0); + msp_write(lp, MSPETH_DMA_Ctl, 0); + msp_write(lp, MSPETH_TxThrsh, 0); + msp_write(lp, MSPETH_TxPollCtr, 0); + msp_write(lp, MSPETH_RxFragSize, 0); + msp_write(lp, MSPETH_Int_En, 0); + msp_write(lp, MSPETH_FDA_Bas, 0); + msp_write(lp, MSPETH_FDA_Lim, 0); + msp_write(lp, MSPETH_Int_Src, 0xffffffff); /* Write 1 to clear */ + msp_write(lp, MSPETH_ARC_Ctl, 0); + msp_write(lp, MSPETH_Tx_Ctl, 0); + msp_write(lp, MSPETH_Rx_Ctl, 0); + msp_write(lp, MSPETH_ARC_Ena, 0); + (void)msp_read(lp, MSPETH_Miss_Cnt); /* Read to clear */ +} + +/************************************************************************** + * Initialize the hardware and start the DMA/MAC RX/TX. The queues must + * be setup before this is called. + */ +static void +mspeth_mac_init(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + int flags; + + /* do not interrupt me while I'm configuring the MAC */ + local_irq_save(flags); + + /* configure the BRCTL RMII registers if we're an RMII device */ + if (identify_enet(lp->hwunit) == ENET_RMII) { + u32 brctl = msp_read(lp, MSPETH_BCTRL_Reg) & ~RMII_Reset; + if (identify_enetTxD(lp->hwunit) == ENETTXD_RISING) + brctl |= RMII_ClkRising; + if (identify_enetTxD(lp->hwunit) == ENETTXD_FALLING) + brctl &= ~RMII_ClkRising; + if (lp->speed == 10) + brctl |= RMII_10MBIT; + else + brctl &= ~RMII_10MBIT; + msp_write(lp, MSPETH_BCTRL_Reg, brctl); + } + + /* set some device structure parameters */ + dev->tx_queue_len = TX_BUF_NUM; + + /* load station address to ARC */ + mspeth_set_arc_entry(dev, ARC_ENTRY_SOURCE, dev->dev_addr); + + /* Enable ARC (broadcast and unicast) */ + msp_write(lp, MSPETH_ARC_Ena, ARC_Ena_Bit(ARC_ENTRY_SOURCE)); + msp_write(lp, MSPETH_ARC_Ctl, ARC_CompEn | ARC_BroadAcc); + + /* configure DMA */ + msp_write(lp, MSPETH_DMA_Ctl, DMA_CTL_CMD); + + /* configure the RX/TX mac */ + msp_write(lp, MSPETH_RxFragSize, 0); + msp_write(lp, MSPETH_TxPollCtr, TX_POLL_CNT); + msp_write(lp, MSPETH_TxThrsh, TX_THRESHOLD); + + /* zero and enable the interrupts */ + lp->fatal_icnt = 0; + msp_write(lp, MSPETH_Int_En, INT_EN_CMD); + + /* + * Set queues + * + * hammtrev, 2005-11-25: + * Using the formula used in the old driver, which gives a + * little bit less than (RX_BUF_NUM - 1) << 5, allowing for more + * buffer descriptors attached to a frame descriptor. + */ + msp_write(lp, MSPETH_FDA_Bas, (u32)lp->rxfd_base); + msp_write(lp, MSPETH_FDA_Lim, (RX_BUF_NUM - 1) << 5); + + /* + * Activation method: + * First, enable the MAC Transmitter and the DMA Receive circuits. + * Then enable the DMA Transmitter and the MAC Receive circuits. + */ + /* start DMA receiver */ + msp_write(lp, MSPETH_BLFrmPtr, (u32)lp->blfd_ptr); + /* start MAC receiver */ + msp_write(lp, MSPETH_Rx_Ctl, RX_CTL_CMD); + + /* start the DMA transmitter */ + msp_write(lp, MSPETH_TxFrmPtr, (u32)lp->txfd_base); + +#ifdef CONFIG_MSPETH_NAPI + /* start the MAC transmitter */ + msp_write(lp, MSPETH_Tx_Ctl, TX_CTL_CMD & ~Tx_EnComp); +#else + msp_write(lp, MSPETH_Tx_Ctl, TX_CTL_CMD); +#endif /* CONFIG_MSPETH_NAPI */ + + /* turn the interrupts back on */ + local_irq_restore(flags); +} + +/************************************************************************** + * Start the Address Recognition circuit. It must be initialized with + * address of the device (which can be changed in the PROM). + */ +static void +mspeth_set_arc_entry(struct net_device *dev, int index, unsigned char *addr) +{ + int arc_index = index * 6; + unsigned long arc_data; + unsigned long saved_addr; + struct mspeth_priv *lp = netdev_priv(dev); + + saved_addr = msp_read(lp, MSPETH_ARC_Adr); + + if (mspeth_debug > 1) { + int i; + printk(KERN_INFO "MSPETH(set_arc_entry) %s: " + "arc %d:", dev->name, index); + for (i = 0; i < 6; i++) + printk(KERN_INFO " %02x", addr[i]); + printk(KERN_INFO "\n"); + } + + if (index & 1) { + /* read modify write */ + msp_write(lp, MSPETH_ARC_Adr, arc_index - 2); + arc_data = msp_read(lp, MSPETH_ARC_Data) & 0xffff0000; + arc_data |= addr[0] << 8 | addr[1]; + msp_write(lp, MSPETH_ARC_Data, arc_data); + + /* write whole word */ + msp_write(lp, MSPETH_ARC_Adr, arc_index + 2); + arc_data = (addr[2] << 24) | (addr[3] << 16) | + (addr[4] << 8) | addr[5]; + msp_write(lp, MSPETH_ARC_Data, arc_data); + } else { + /* write whole word */ + msp_write(lp, MSPETH_ARC_Adr, arc_index); + arc_data = (addr[0] << 24) | (addr[1] << 16) | + (addr[2] << 8) | addr[3]; + msp_write(lp, MSPETH_ARC_Data, arc_data); + + /* read modify write */ + msp_write(lp, MSPETH_ARC_Adr, arc_index + 4); + arc_data = msp_read(lp, MSPETH_ARC_Data) & 0x0000ffff; + arc_data |= addr[4] << 24 | (addr[5] << 16); + msp_write(lp, MSPETH_ARC_Data, arc_data); + } + + if (mspeth_debug > 2) { + int i; + for (i = arc_index / 4; i < arc_index / 4 + 2; i++) { + msp_write(lp, MSPETH_ARC_Adr, i * 4); + printk(KERN_INFO "arc 0x%x: %08x\n", + i * 4, msp_read(lp, MSPETH_ARC_Data)); + } + } + msp_write(lp, MSPETH_ARC_Adr, saved_addr); +} + +/************************************************************************** + * Initialize the RX/TX queues and the free buffer list. This routine + * allocates memory and care must be taken to free the memory when it + * is no longer required + */ +static bool +mspeth_init_queues(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + int i, size; + u32 tmp_addr; + struct sk_buff *skb; + dma_addr_t dma_skb; + + /* + * The queue structure allocates individual buffers large enough + * to hold an entire packet. There is no packing so each FD + * requires a single BD. There is one q_desc (an FD and a BD, + * 16-byte aligned) for each packet recieved and the same for + * each packet to transmit. The list of free buffers has one + * FD and an arbitrary number of BDs following it (but even). + * There is one BD for each RX buffer. + */ + + /* + * TODO: Need to add some error checking here for reentry into + * this routine. + */ + /* descriptors for the rx/tx buffers and the buffer list */ + size = (RX_BUF_NUM + TX_BUF_NUM) * sizeof(struct q_desc) + + sizeof(struct bl_desc); + + /* test for allocation requirements */ + if (lp->fd_base == NULL) { + /* add enough margin to align to 16-byte boundary */ + lp->fd_base = kmalloc(size + (L1_CACHE_BYTES - 1), + GFP_KERNEL); + if (lp->fd_base == NULL) { + printk(KERN_ERR "MSPETH(init_queues) %s: " + "Cannot allocate space for descriptors!\n", + dev->name); + return false; + } + + /* + * Move frame descriptors to uncached addresses. This + * prevents spurious IntBLEx interrupts. + */ + lp->fd_base = (void*)KSEG1ADDR((u32)lp->fd_base); + memset(lp->fd_base, 0, size + (L1_CACHE_BYTES - 1)); + + if (mspeth_debug > 1) + printk(KERN_INFO + "MSPETH(init_queues) %s: fd_base = %p\n", + dev->name, lp->fd_base); + } + + /* + * stjeanma, 2006-01-26: + * Add instead of subtract and take into account the + * architecture's cache line size. + */ + tmp_addr = ((u32) lp->fd_base + + (L1_CACHE_BYTES - 1)) & ~(L1_CACHE_BYTES - 1); + + /* allocate the RX queue (aka free descriptor area) */ + lp->rxfd_base = (struct q_desc *)tmp_addr; + lp->rxfd_curr = lp->rxfd_base; + tmp_addr += RX_BUF_NUM * sizeof(struct q_desc); + + /* + * Initialize the RX queue (these values are mostly + * overwritten by the MAC). + */ + for (i = 0; i < RX_BUF_NUM; i++) { + lp->rxfd_base[i].fd0.FDNext = 0x00000000; + lp->rxfd_base[i].fd0.FDSystem = 0x00000000; + lp->rxfd_base[i].fd0.FDStat = 0x00000000; + lp->rxfd_base[i].fd0.FDCtl = FD_CownsFD; + lp->rxfd_base[i].fd1.FDNext = 0x00000000; + lp->rxfd_base[i].fd1.FDSystem = 0x00000000; + lp->rxfd_base[i].fd1.FDStat = 0x00000000; + lp->rxfd_base[i].fd1.FDCtl = FD_CownsFD; + } + + /* initialize the actual TX sk_buff pointers */ + if (lp->txfd_base != NULL) { + for (i = 0; i < TX_BUF_NUM; i++) { + skb = (struct sk_buff *)lp->txfd_base[i].fd.FDSystem; +#if defined(CONFIG_DMA_NONCOHERENT) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + dma_skb = lp->txfd_base[i].fd1.FDStat; + if (dma_skb != 0x00000000) { + lp->txfd_base[i].fd1.FDStat = 0x00000000; + /* unmap any dma pointers */ + dma_unmap_single(lp->dev, dma_skb, + skb->len, DMA_BIDIRECTIONAL); + } +#endif + if (skb != NULL) { + lp->txfd_base[i].fd.FDSystem = 0x00000000; + dev_kfree_skb_any(skb); + } + } + } + + /* allocate the TX queue */ + lp->txfd_base = (struct q_desc *)tmp_addr; + lp->tx_head = lp->tx_tail = 0; + tmp_addr += TX_BUF_NUM * sizeof(struct q_desc); + + /* initialize the TX queue */ + for (i = 0; i < TX_BUF_NUM; i++) { + lp->txfd_base[i].fd.FDNext = (u32)(&lp->txfd_base[i + 1]); + lp->txfd_base[i].fd.FDSystem = 0x00000000; + lp->txfd_base[i].fd.FDStat = 0x00000000; + lp->txfd_base[i].fd.FDCtl = 0x00000000; + } + lp->txfd_base[TX_BUF_NUM - 1].fd.FDNext = (u32)(&lp->txfd_base[0]); + + /* initialize the buffer list FD */ + lp->blfd_ptr = (struct bl_desc *)tmp_addr; + lp->blfd_ptr->fd.FDNext = (u32)lp->blfd_ptr; + lp->blfd_ptr->fd.FDCtl = (RX_BUF_NUM << 1) | FD_CownsFD; + + /* allocate the RX sk_buff array */ + if (lp->rx_skbp == NULL) { + lp->rx_skbp = (struct sk_buff **)kmalloc( + (RX_BUF_NUM << 1) * sizeof(struct sk_buff *), + GFP_KERNEL); + if (lp->rx_skbp == NULL) { + printk(KERN_ERR "MSPETH(init_queues) %s: " + "Cannot allocate the array of " + "sk_buff pointers!\n", dev->name); + return false; + } + + for (i = 0; i < RX_BUF_NUM << 1; i++) + lp->rx_skbp[i] = NULL; + } + + /* initialize the actual RX sk_buff pointers */ + for (i = 0; i < RX_BUF_NUM << 1; i++) { + /* free up old sk_buffs */ + skb = lp->rx_skbp[i]; + if (skb != NULL) { + lp->rx_skbp[i] = NULL; + dev_kfree_skb_any(skb); + } + + /* allocate and align the skb */ + skb = dev_alloc_skb(MSP_END_BUFSIZE + 2); + if (skb == NULL) { + printk(KERN_ERR "MSPETH(init_queues) %s: " + "Cannot allocate the sk_buffs!\n", dev->name); + return false; + } + lp->rx_skbp[i] = skb; + + /* + * Slign and fill out fields specific to our + * device. Notice that our device is smart about + * FCS etc. + */ + skb_reserve(skb, 2); + skb->dev = dev; + skb->ip_summed = CHECKSUM_NONE; + + /* + * Initialize the buffer list entries reserving 2 bytes + * in the skb results in a 16-byte aligned IP header, + * but also puts the skb->data at a 16-bit boundary. + * The hardware requires a 32-bit aligned buffer. So we + * round back two bytes and then instruct the hardware + * to skip forward 2 bytes into the buffer. + */ + lp->blfd_ptr->bd[i].BuffData = (u32)skb->data & + BD_DataAlign_MASK; + lp->blfd_ptr->bd[i].BDCtl = (BD_CownsBD | + (i << BD_RxBDID_SHIFT) | MSP_END_BUFSIZE); + } + + /* allocate the RX dma array */ + if (lp->rx_dma_skbp == NULL) { + lp->rx_dma_skbp = (dma_addr_t *)kmalloc( + (RX_BUF_NUM << 1) * sizeof(dma_addr_t), + GFP_KERNEL); + if (lp->rx_dma_skbp == NULL) { + printk(KERN_ERR "MSPETH(init_queues) %s: " + "Cannot allocate the array of " + "RX dma addresses!\n", dev->name); + return false; + } + + for (i = 0; i < RX_BUF_NUM << 1; i++) + lp->rx_dma_skbp[i] = 0x00000000; + } + + /* initialize the RX dma pointers */ + for (i = 0; i < RX_BUF_NUM << 1; i++) { +#if defined(CONFIG_DMA_NONCOHERENT) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + dma_skb = lp->rx_dma_skbp[i]; + /* unmap any dma pointers */ + if (dma_skb != 0x00000000) { + lp->rx_dma_skbp[i] = 0x00000000; + dma_unmap_single(lp->dev, dma_skb, + MSP_END_BUFSIZE, DMA_BIDIRECTIONAL); + } +#endif + } + + /* configure the queue length and return */ + atomic_set(&lp->tx_qspc, TX_BUF_NUM); + + return true; +} + +/************************************************************************** + * Converse of the mspeth_init_queues routine. This frees all the memory + * associated with the queues. It must be called when closing the device. + */ +static void +mspeth_free_queues(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + struct sk_buff *skb; + dma_addr_t dma_skb; + int i; + + /* free up any TX buffers */ + if (lp->txfd_base != NULL) { + for (i = 0; i < TX_BUF_NUM; i++) { + skb = (struct sk_buff *)lp->txfd_base[i].fd.FDSystem; +#if defined(CONFIG_DMA_NONCOHERENT) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + dma_skb = lp->txfd_base[i].fd1.FDStat; + if (dma_skb != 0x00000000) { + lp->txfd_base[i].fd1.FDStat = 0x00000000; + /* unmap any dma pointers */ + dma_unmap_single(lp->dev, dma_skb, + skb->len, DMA_BIDIRECTIONAL); + } +#endif + if (skb != NULL) { + lp->txfd_base[i].fd.FDSystem = 0x00000000; + dev_kfree_skb_any(skb); + } + } + } + + /* free up the RX sk_buff buffer and array */ + if (lp->rx_skbp != NULL) { + for (i = 0; i < RX_BUF_NUM << 1; i++) { + skb = lp->rx_skbp[i]; + if (skb != NULL) { + dev_kfree_skb_any(skb); + } + } + kfree(lp->rx_skbp); + } + + /* unmap any RX dma pointers and free up the array */ + if (lp->rx_dma_skbp != NULL) { +#if defined(CONFIG_DMA_NONCOHERENT) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + for (i = 0; i < RX_BUF_NUM << 1; i++) { + dma_skb = lp->rx_dma_skbp[i]; + if (dma_skb != 0x00000000) + dma_unmap_single(lp->dev, dma_skb, + MSP_END_BUFSIZE, DMA_BIDIRECTIONAL); + } +#endif + kfree(lp->rx_dma_skbp); + } + + /* + * Free the descriptor area. Move fd_base back to KSEG0 before + * freeing it. + */ + if (lp->fd_base != NULL) + kfree((void*)KSEG0ADDR(lp->fd_base)); + + /* nullify all the pointers and zero out the queue space */ + lp->fd_base = NULL; + lp->rxfd_base = NULL; + lp->rxfd_curr = NULL; + lp->txfd_base = NULL; + lp->blfd_ptr = NULL; + lp->rx_skbp = NULL; + lp->rx_dma_skbp = NULL; + lp->tx_head = lp->tx_tail = 0; + + atomic_set(&lp->tx_qspc, 0); +} + +/************************************************************************** + * Do a safe soft restart of the device. This *will* cause packet loss, + * so it's only used as a recovery mechanism. + */ +static void +mspeth_soft_restart(struct net_device *dev) +{ + int flags; + + printk(KERN_INFO "MSPETH(soft_restart) %s: " + "Soft device restart\n", dev->name); + + netif_stop_queue(dev); + + /* please don't interrupt me while I'm resetting everything */ + local_irq_save(flags); + + /* Try to restart the adaptor. */ + mspeth_mac_reset(dev); + mspeth_init_queues(dev); + mspeth_mac_init(dev); + mspeth_phy_init(dev); + + /* turn back on the interrupts */ + local_irq_restore(flags); + + /* and start up the queue! We should be fixed .... */ + dev->trans_start = jiffies; + netif_wake_queue(dev); +} + +/************************************************************************** + * Do a *hard* restart of the device. This *will* cause packet loss, so + * it's only used as a recovery mechanism + */ +static void +mspeth_hard_restart(struct net_device *dev) +{ + int flags; + + printk(KERN_INFO "MSPETH(hard_restart) %s: " + "Hard device restart\n", dev->name); + + netif_stop_queue(dev); + + /* please don't interrupt me while I'm resetting everything */ + local_irq_save(flags); + + /* Try to restart the adaptor. */ + mspeth_mac_reset(dev); + mspeth_phy_reset(dev); + mspeth_free_queues(dev); + mspeth_init_queues(dev); + mspeth_mac_init(dev); + mspeth_phy_init(dev); + + /* turn back on the interrupts */ + local_irq_restore(flags); + + /* and start up the queue! We should be fixed .... */ + dev->trans_start = jiffies; + netif_wake_queue(dev); +} + +/************************************************************************** + * Open/initialize the board. This is called (in the current kernel) + * sometime after booting when the 'ifconfig' program is run. + * + * This routine should set everything up anew at each open, even + * registers that "should" only need to be set once at boot, so that + * there is non-reboot way to recover if something goes wrong. + */ +static int +mspeth_open(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + int err = -EBUSY; + + /* reset the hardware, disabling/clearing all interrupts */ + mspeth_mac_reset(dev); + mspeth_phy_reset(dev); + + /* determine preset speed and duplex settings */ + if (lp->option & MSP_OPT_10M) + lp->speed = 10; + else + lp->speed = 100; + + if (lp->option & MSP_OPT_FDUP) + lp->fullduplex = true; + else + lp->fullduplex = false; + + /* initialize the queues and the hardware */ + if (!mspeth_init_queues(dev)) { + printk(KERN_ERR "MSPETH(open) %s: " + "Unable to allocate queues\n", dev->name); + goto out_err; + } + + /* allocate and initialize the tasklets */ +#ifndef CONFIG_MSPETH_NAPI + tasklet_init(&lp->rx_tasklet, mspeth_rx, (u32)dev); + tasklet_init(&lp->tx_tasklet, mspeth_txdone, (u32)dev); +#endif + + /* + * hammtrev, 2005/12/08: + * Adding a new BH handler to reset the device in response to BLEx. + */ + tasklet_init(&lp->hard_restart_tasklet, mspeth_hard_restart_bh, + (u32)dev); + + mspeth_mac_init(dev); + mspeth_phy_init(dev); + + /* stjeanma: No need to poll the link status for a switch */ + if (!(lp->option & MSP_OPT_SWITCH)) { + /* initialize the link check timer */ + init_timer(&lp->link_timer); + lp->link_timer.expires = jiffies + HZ / LINK_DELAY_DIV; + lp->link_timer.data = (u32)dev; + lp->link_timer.function = mspeth_link_check; + add_timer(&lp->link_timer); + } + + /* Allocate the IRQ */ + if (request_irq(dev->irq, &mspeth_interrupt, 0, cardname, dev)) { + printk(KERN_ERR + "MSPETH(open) %s: unable to reserve IRQ %d\n", + dev->name, dev->irq); + goto out_err; + } + +#ifdef CONFIG_MSPETH_SKB_RECYCLE + skb_bin.user_count++; +#endif + /* and start up the queue */ + netif_start_queue(dev); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)) + MOD_INC_USE_COUNT; +#endif + return 0; + +out_err: + return err; +} + +/************************************************************************** + * The inverse routine to mspeth_open(). Close the device and clean up + */ +static int +mspeth_close(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + u32 flags; + + /* please don't interrupt me while I'm shutting down everything */ + local_irq_save(flags); + + /* stop the queue & let the world know about it */ + netif_stop_queue(dev); + netif_carrier_off(dev); + + /* kill the tasklets before resetting devices */ +#ifndef CONFIG_MSPETH_NAPI + tasklet_kill(&lp->rx_tasklet); + tasklet_kill(&lp->tx_tasklet); +#endif + tasklet_kill(&lp->hard_restart_tasklet); + + /* smite the link check timers */ + del_timer_sync(&lp->link_timer); + + /* Clean up the adaptor. */ + mspeth_mac_reset(dev); + mspeth_phy_reset(dev); + + /* free the the queue memeory */ + mspeth_free_queues(dev); + + /* free up the resources */ + free_irq(dev->irq, dev); + + /* + * Deassign the phy. + * stjeanma: PHY might not be allocated for a switch. + */ + if (lp->phyptr != NULL) + lp->phyptr->assigned = false; + + /* turn back on the interrupts */ + local_irq_restore(flags); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)) + MOD_DEC_USE_COUNT; +#endif + + return 0; +} + +/************************************************************************** + * The typical workload of the driver: + * Handle the network interface interrupts. + */ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +static irqreturn_t mspeth_interrupt(int irq, void *dev_id) +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +static void mspeth_interrupt(int irq, void *dev_id, struct pt_regs *regs) +#endif +{ + struct net_device *dev = dev_id; + struct mspeth_priv *lp = netdev_priv(dev); + u32 status; + + if (unlikely(dev == NULL)) { + printk(KERN_WARNING "MSPETH(interrupt) %s: " + "irq %d for unknown device.\n", dev->name, irq); + return IRQ_NONE; + } + + /* + * stjeanma, 2006-02-08: + * This read flushes the dma queue in addition to obtaining + * status. + */ + status = msp_read(lp, MSPETH_Int_Src); + + /* acknowledge the interrupts and check for null entry */ + if (unlikely(status == 0)) + return IRQ_HANDLED; + else + msp_write(lp, MSPETH_Int_Src, status); + +#if MSPETH_DEBUG + /* collect debugging stats */ + if (likely(status & IntSrc_MacRx)) + lp->lstats.rx_ints++; + if (status & IntSrc_MacTx) + lp->lstats.tx_ints++; +#endif + +#ifdef CONFIG_MSPETH_NAPI + /* if NAPI is enabled schedule rx jobs */ + if (likely(status == IntSrc_MacRx)) { + if (netif_rx_schedule_prep(dev)) { + msp_write(lp, MSPETH_Rx_Ctl, + RX_CTL_CMD & ~Rx_EnGood); + msp_write(lp, MSPETH_Int_En, + INT_EN_CMD & ~IntEn_FDAEx); + __netif_rx_schedule(dev); + } + return IRQ_HANDLED; + } + + if (status & IntSrc_MacRx) { + /* if NAPI is enabled schedule rx jobs */ + if (netif_rx_schedule_prep(dev)) { + msp_write(lp, MSPETH_Rx_Ctl, + RX_CTL_CMD & ~Rx_EnGood); + msp_write(lp, MSPETH_Int_En, + INT_EN_CMD & ~IntEn_FDAEx); + __netif_rx_schedule(dev); + } + } + + /* + * Workaround for transmission timeouts due to transmit queue + * exhaust even if the queue has room. + */ + if (status & IntSrc_MacTx) { + msp_write(lp, MSPETH_Tx_Ctl, TX_CTL_CMD & ~Tx_EnComp); + netif_wake_queue(dev); + } +#else + /* + * At least for every TXDONE_MAX_PKT one IntSrc_MacTx will be + * generated. + */ + if (likely(status == IntSrc_MacRx)) { + /* disable interrupt and schedule tasklet */ + msp_write(lp, MSPETH_Rx_Ctl, RX_CTL_CMD & ~Rx_EnGood); + tasklet_schedule(&lp->rx_tasklet); + return IRQ_HANDLED; + } + + if (likely(status == IntSrc_MacTx)) { + /* disable interrupt and schedule tasklet */ + msp_write(lp, MSPETH_Tx_Ctl, TX_CTL_CMD & ~Tx_EnComp); + tasklet_schedule(&lp->tx_tasklet); + return IRQ_HANDLED; + } + + if (likely(status == (IntSrc_MacRx | IntSrc_MacTx))) { + /* disable interrupt and schedule tasklet */ + msp_write(lp, MSPETH_Rx_Ctl, RX_CTL_CMD & ~Rx_EnGood); + msp_write(lp, MSPETH_Tx_Ctl, TX_CTL_CMD & ~Tx_EnComp); + tasklet_schedule(&lp->tx_tasklet); + tasklet_schedule(&lp->rx_tasklet); + return IRQ_HANDLED; + } + + if (status & IntSrc_MacRx) { + /* disable interrupt and schedule tasklet */ + msp_write(lp, MSPETH_Rx_Ctl, RX_CTL_CMD & ~Rx_EnGood); + tasklet_schedule(&lp->rx_tasklet); + } + + /* all other combined cases */ + if (status & IntSrc_MacTx) { + /* disable interrupt and schedule tasklet */ + msp_write(lp, MSPETH_Tx_Ctl, TX_CTL_CMD & ~Tx_EnComp); + tasklet_schedule(&lp->tx_tasklet); + } +#endif /* CONFIG_MSPETH_NAPI */ + + /* recoverable errors */ + if (status & IntSrc_FDAEx) { + /* disable FDAEx int. (until we make room...) */ + msp_write(lp, MSPETH_Int_En, INT_EN_CMD & ~IntEn_FDAEx); + lp->lstats.fd_exha++; + lp->stats.rx_dropped++; + } + + /* + * hammtrev, 2005/08/30: + * Some boards generate a link state interrupt on power-up. + * ACK it and it will go away. + */ + if (status & IntSrc_Link_St) + msp_write(lp, MSPETH_MAC_Ctl, + msp_read(lp, MSPETH_MAC_Ctl) | MAC_LnkChg); + + /* + * And now all the unrecoverable fatal error conditions, this + * includes BLEx errors since we can *never* have one -- if we + * do, it indicates that there is some sort of queue corruption. + */ + if (status & FATAL_ERROR_INT) { + /* Disable further interrupts until device reset. */ + msp_write(lp, MSPETH_DMA_Ctl, + msp_read(lp, MSPETH_DMA_Ctl) | DMA_IntMask); + /* this one may be overkill... */ + msp_write(lp, MSPETH_MAC_Ctl, + msp_read(lp, MSPETH_MAC_Ctl) | MAC_HaltImm); + mspeth_fatal_error_interrupt(dev, status); + } + + return IRQ_HANDLED; +} + +/************************************************************************** + * Fatal error interrupts reset the entire device but they don't require + * reallocating the queues, just clearing them + */ +static void +mspeth_fatal_error_interrupt(struct net_device *dev, int status) +{ + struct mspeth_priv *lp = netdev_priv(dev); + + printk(KERN_WARNING + "MSPETH(fatal_error_interrupt) %s: " + "Fatal Error Interrupt (0x%08x):", dev->name, status); + + if (status & IntSrc_DmParErr) + printk(KERN_WARNING " DmParErr"); + if (status & IntSrc_NRAB) + printk(KERN_WARNING " IntNRAB"); + if (status & IntSrc_BLEx) + printk(KERN_WARNING " IntBLEx"); + printk(KERN_WARNING "\n"); + + /* panic if it gets too crazy */ + if (lp->fatal_icnt++ > 100) + panic("MSPETH(fatal_error_interrupt) %s: " + "too many fatal errors.\n", dev->name); + + /* Dump our descriptors, if desired */ + if (mspeth_debug > 0) { + mspeth_dump_queues(dev); + mspeth_dump_stats(dev); + } + + /* + * Try to restart the adaptor. + * + * hammtrev, 2005/12/08: + * This is too much work for a top-half interrupt handler, and + * may result in unexpected race conditions with other tasklets. + * Now deferring the device reset to a bottom-half tasklet, to + * allow any currently-running tasklet to complete without + * unexpected changes to frame/buffer descriptors, etc. + */ + tasklet_schedule(&lp->hard_restart_tasklet); +} + +/************************************************************************** + * Handle deferred processing of the IntBLEx interrupt. + */ +static void +mspeth_hard_restart_bh(unsigned long dev_addr) +{ + struct net_device *dev = (struct net_device *)dev_addr; + + printk(KERN_WARNING "MSPETH(hard_restart_bh) %s: " + "restarting device\n", dev->name); + mspeth_hard_restart(dev); +} + + +/************************************************************************** + * Process a single RX packet, including sending it up the stack and + * reallocating the buffer. Return the next buffer in the RX queue. + * This routine assumes that the current FD pointed to by rxfd_curr + * has been invalidated with the cache and is current with main memory. + * + * Changed __hotnet to inline: slight performance improvement. + */ +inline static struct q_desc * +mspeth_rx_onepkt(struct net_device *dev) { + struct mspeth_priv *lp = netdev_priv(dev); + u32 status; + struct q_desc *next_rxfd; + int bdnum, len; + struct sk_buff *skb; + dma_addr_t dma_skb; + + /* collect all the relevent information */ + status = lp->rxfd_curr->fd.FDStat; + /* Drop the FCS from the length */ + len = (lp->rxfd_curr->bd.BDCtl & BD_BuffLength_MASK) - 4; + bdnum = (lp->rxfd_curr->bd.BDCtl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; + + if (mspeth_debug > 2) + printk(KERN_INFO "MSPETH(rx_onepkt) %s: " + "RxFD.\n", dev->name); + if (mspeth_debug > 3) + dump_qdesc(lp->rxfd_curr); +#ifdef MSPETH_DUMP_QUEUES + if (mspeth_debug > 2 && + (!bdnum && (rx_bdnums[lp->unit][rx_bdnums_ind[lp->unit]] + != ((RX_BUF_NUM << 1) - 1)))) + dump_qdesc(lp->rxfd_curr); + catalog_rx_bdnum(lp->unit, bdnum); +#endif /* MSPETH_DUMP_QUEUES */ + + /* + * The packet has been received correctly so prepare to send + * it up the stack + */ + if (likely(status & Rx_Good)) { + skb = lp->rx_skbp[bdnum]; + dma_skb = lp->rx_dma_skbp[bdnum]; + + /* + * If a replacement buffer can be allocated then send + * the skb up the stack otherwise we drop the packet + * and reuse the existing buffer + */ + lp->rx_skbp[bdnum] = mspeth_alloc_skb(dev); + if (likely(lp->rx_skbp[bdnum] != NULL)) { +#if defined(CONFIG_DMA_NONCOHERENT) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + /* Replacement buffer map and sync for dma */ + lp->rx_dma_skbp[bdnum] = dma_map_single( + lp->dev, lp->rx_skbp[bdnum]->data, + MSP_END_BUFSIZE, DMA_FROM_DEVICE); + + /* + * Replacement buffer has been allocated + * successfully, so sync and un-map original + * buffer. + */ + dma_sync_single_for_cpu(lp->dev, dma_skb, + len, DMA_FROM_DEVICE); + dma_unmap_single(lp->dev, dma_skb, + MSP_END_BUFSIZE, DMA_NONE); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + invalidate_buffer(skb->data, len); +#endif + + /* complete the skb and send it up the stack */ + skb_put(skb, len); + skb->protocol = eth_type_trans(skb, dev); + +#ifdef CONFIG_MSPETH_NAPI + netif_receive_skb(skb); +#else + netif_rx(skb); +#endif /* CONFIG_MSPETH_NAPI */ + dev->last_rx = jiffies; + + lp->stats.rx_packets++; + lp->stats.rx_bytes += len; + + if (mspeth_debug > 4) { + print_eth(1, skb->data, len); + if (mspeth_debug > 5) + print_buf(skb->data, len); + } + } else { + printk(KERN_WARNING "MSPETH(rx_onepkt) %s: " + "Memory squeeze, dropping packet.\n", + dev->name); + lp->rx_skbp[bdnum] = skb; + lp->stats.rx_dropped++; + } + + /* Do the rounding for the 32-bit data alignment */ + lp->blfd_ptr->bd[bdnum].BuffData = + (u32)lp->rx_skbp[bdnum]->data & + BD_DataAlign_MASK; + } else { + lp->stats.rx_errors++; + /* WORKAROUND: LongErr and CRCErr means Overflow. */ + if ((status & Rx_LongErr) && (status & Rx_CRCErr)) { + status &= ~(Rx_LongErr | Rx_CRCErr); + status |= Rx_Over; + } + if (status & Rx_LongErr) + lp->stats.rx_length_errors++; + if (status & Rx_Over) + lp->stats.rx_fifo_errors++; + if (status & Rx_CRCErr) + lp->stats.rx_crc_errors++; + if (status & Rx_Align) + lp->stats.rx_frame_errors++; + } + + /* allocate buffer back to controller */ + lp->blfd_ptr->bd[bdnum].BDCtl = + (BD_CownsBD | (bdnum << BD_RxBDID_SHIFT) | MSP_END_BUFSIZE); + blocking_read_reg32(&lp->blfd_ptr->bd[bdnum].BDCtl); + + /* save next FD before allocating current one to controller */ + next_rxfd = (struct q_desc *)lp->rxfd_curr->fd.FDNext; + + /* + * Return q_desc to the controller. Setting fd0.FDCtl last prevents + * the controller from using this q_desc until we're done. + * + * Writeback the changes back to the RAM so that MAC can see the + * available buffers on a write-through cache this doesn't really + * do anything, but on a writeback cache this is quite important. + * + * stjeanma, 2006-02-08: + * Uncached writes need to be read back to ensure they reach RAM. + */ + lp->rxfd_curr->fd0.FDNext = 0; + lp->rxfd_curr->fd0.FDSystem = 0; + lp->rxfd_curr->fd0.FDStat = 0; + lp->rxfd_curr->fd1.FDNext = 0; + lp->rxfd_curr->fd1.FDSystem = 0; + lp->rxfd_curr->fd1.FDStat = 0; + lp->rxfd_curr->fd1.FDCtl = FD_CownsFD; + lp->rxfd_curr->fd0.FDCtl = FD_CownsFD; + blocking_read_reg32(&lp->rxfd_curr->fd0.FDCtl); + + return next_rxfd; +} + +#ifdef CONFIG_MSPETH_NAPI +/************************************************************************* + * mspeth polling method used by NAPI. + */ +static int __hotnet +mspeth_poll(struct net_device *dev, int *budget) +{ + struct mspeth_priv *lp = netdev_priv(dev); + int work_limit = min(*budget, dev->quota); + int work_done; + int done = 1; + + flush_memqueue(); + + for (work_done = 0; (work_done < work_limit) && + !(lp->rxfd_curr->fd.FDCtl & FD_CownsFD); + work_done++) + lp->rxfd_curr = mspeth_rx_onepkt(dev); + + if (likely(work_done > 0)) { + *budget -= work_done; + dev->quota -= work_done; + done = (work_done < work_limit); + } + + if (done) { + /* + * Reenable rx and FDAEXhaust interrupts since we + * handled all recieved packets. + */ + local_irq_disable(); + __netif_rx_complete(dev); + msp_write(lp, MSPETH_Rx_Ctl, RX_CTL_CMD | Rx_EnGood); + msp_write(lp, MSPETH_Int_En, INT_EN_CMD); + local_irq_enable(); + } + + return !done; +} +#else +/************************************************************************** + * A packet has been received so shove it up the network stack and + * allocate another buffer for reception. Called by the rx_tasklet which + * is scheduled by the interrupt handler. + */ +static void __hotnet +mspeth_rx(unsigned long dev_addr) +{ + struct net_device *dev = (struct net_device *)dev_addr; + struct mspeth_priv *lp = netdev_priv(dev); + u32 status; + int rx_cnt; + + /* + * Make sure the memory queue is flushed and the cache is + * invalidated this is only really important in the case where + * we have a single packet to process otherwise the packet at + * the head of the queue will *certainly* be flushed from the + * memory queue. We don't need to flush the DMA queue since the + * ISR that scheduled this routine will have done it already. + */ + flush_memqueue(); + + /* + * Loop around processing the rx packet queue. + * This should be adjusted to process a maximum number of + * packets, or perhaps insert a call to "schedule" within it + * so that it doesn't monopolize the CPU. + */ + for (rx_cnt = 0; rx_cnt < RX_MAX_PKT && + !(lp->rxfd_curr->fd.FDCtl & FD_CownsFD); rx_cnt++) { + /* + * Process the current packet and move to the next + * frame descriptor. + */ + lp->rxfd_curr = mspeth_rx_onepkt(dev); + } + + /* re-enable FDA Exhausted interupts 'cause there's room now */ + if (rx_cnt > 0) + msp_write(lp, MSPETH_Int_En, INT_EN_CMD); + + /* + * Check to see if there is an unprocessed packet + * -- reschedule if so. + * + * hammtrev, 2005-12-16: + * Flush the memory queue and invalidate the cache + * lines before re-examining the current rxfd. + */ + flush_memqueue(); + + if (!(lp->rxfd_curr->fd.FDCtl & FD_CownsFD)) { + tasklet_schedule(&lp->rx_tasklet); + } else { + /* + * Re-enable the RX completion interrupt and check to see + * if there is an outstanding interrupt. + */ + msp_write(lp, MSPETH_Rx_Ctl, RX_CTL_CMD); + status = msp_read(lp, MSPETH_Int_Src); + + /* + * If there is an outstanding RX interrupt, then reschedule + * the routine + */ + if (status & IntSrc_MacRx) { + /* ack the interrupt, disable it and reschedule */ + msp_write(lp, MSPETH_Int_Src, IntSrc_MacRx); + msp_write(lp, MSPETH_Rx_Ctl, + RX_CTL_CMD & ~Rx_EnGood); + tasklet_schedule(&lp->rx_tasklet); + } + } +} +#endif /* CONFIG_MSPETH_NAPI */ + +/************************************************************************** + * Basic transmit function -- called from the upper network layers + */ +static int __hotnet +mspeth_send_packet(struct sk_buff *skb, struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + struct q_desc *txfd_ptr; + + /* + * NOTE that if we cannot transmit then we must return 1 and + * *not touch* the skb since it doesn't belong to us. The + * networking layer above will take care of it. + */ + +#ifdef CONFIG_MSPETH_NAPI + /* + * We have no txdone interrupt on NAPI. + * Free transmitted buffers here. + */ + mspeth_txdone((unsigned long)dev); +#endif + + /* + * Don't take drastic action right away if the queue is stopped, + * but if its been that way for quite a while we'll attempt to + * restart the adatper. + */ + if (netif_queue_stopped(dev)) { + /* + * If we get here, some higher level has decided we are + * broken. There should really be a "kick me" function + * call instead. + */ + int tickssofar = jiffies - dev->trans_start; + if (tickssofar < 5) { + printk(KERN_WARNING "MSPETH(send_packet) %s: " + "queue stopped ...\n", dev->name); + return 1; + } + + printk(KERN_WARNING "MSPETH(send_packet) %s: " + "transmit timed out, restarting adaptor. " + "TX_Status = %08x\n", + dev->name, msp_read(lp, MSPETH_Tx_Stat)); + + /* do a hard restart and return */ + mspeth_hard_restart(dev); + return 1; + } + + /* + * Protect access to the transmit queue with the atomic queue + * space variable. + */ + if (atomic_read(&lp->tx_qspc) == 0) { + /* no room on queue for another packet */ + netif_stop_queue(dev); +#ifdef CONFIG_MSPETH_NAPI + /* workaround for waking the queue */ + msp_write(lp, MSPETH_Tx_Ctl, TX_CTL_CMD); +#endif + lp->lstats.tx_full++; + return 1; + } + + lp->stats.tx_bytes += skb->len; + + /* we have room, so get the next availabe tx FD */ + txfd_ptr = &(lp->txfd_base[lp->tx_head]); + lp->tx_head = (lp->tx_head + 1) & TX_BUF_MASK; + +#if defined(CONFIG_DMA_NONCOHERENT) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + /* map and sync for dma */ + txfd_ptr->fd1.FDStat = dma_map_single(lp->dev, skb->data, + skb->len, DMA_TO_DEVICE); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + /* writeback the cache and flush the sdram queue */ + writeback_buffer(skb->data, skb->len); +#endif + + /* + * stjeanma, 2006-02-08: + * Uncached writes need to be read back to ensure they reach RAM. + */ + txfd_ptr->bd.BuffData = (u32)skb->data; + txfd_ptr->bd.BDCtl = skb->len; + txfd_ptr->fd.FDSystem = (u32)skb; + txfd_ptr->fd.FDCtl = FD_CownsFD_Set; + blocking_read_reg32(&txfd_ptr->fd.FDCtl); + + /* one more packet on the TX queue */ + atomic_dec(&lp->tx_qspc); + + if (mspeth_debug > 4) { + print_eth(0, (unsigned char *)skb->data, skb->len); + if (mspeth_debug > 5) + print_buf(skb->data, skb->len); + } + + /* wake up the transmitter */ + msp_write(lp, MSPETH_DMA_Ctl, DMA_CTL_CMD | DMA_TxWakeUp); + + dev->trans_start = jiffies; + + return 0; +} + +/************************************************************************** + * Free the buffers which have been transmitted from the transmit queue. + * Called from the tx_tasklet which is scheduled by the interrupt handler + */ +#ifdef CONFIG_MSPETH_NAPI +inline static void +#else +static void __hotnet +#endif +mspeth_txdone(unsigned long dev_addr) +{ + struct net_device *dev = (struct net_device *)dev_addr; + struct mspeth_priv *lp = netdev_priv(dev); + struct q_desc *txfd_ptr; + int num_done = 0; + u32 status; + + /* + * Walk the queue until we come to the end or a buffer we don't + * control we don't worry much about leaving a buffer or two on + * the tx queue; we'll get to them later and if we're busy then + * we'll get to them RSN. + * + * stjeanma, 2006-02-08: + * Flush the memory queue to see the MAC queue updates. + */ + txfd_ptr = &(lp->txfd_base[lp->tx_tail]); + flush_memqueue(); + + while (atomic_read(&lp->tx_qspc) < TXDONE_MAX_PKT && + !(txfd_ptr->fd.FDCtl & FD_CownsFD)) { + struct sk_buff *skb; + dma_addr_t dma_skb; + + status = txfd_ptr->fd.FDStat; + mspeth_check_tx_stat(dev, status); + + if (mspeth_debug > 2) + printk(KERN_INFO "MSPETH(txdone) %s: " + "TxFD done.\n", dev->name); + if (mspeth_debug > 3) + dump_qdesc(txfd_ptr); + + /* + * Free the current socket buffer and change ownership of + * the TX descriptor. + * + * Writeback the change to RAM so that the controller can + * see them. + * + * stjeanma, 2006-02-08: + * Uncached writes need to be read back to ensure they + * reach RAM. + */ + dma_skb = txfd_ptr->fd1.FDStat; + txfd_ptr->fd1.FDStat = 0x00000000; + + skb = (struct sk_buff *)(txfd_ptr->fd.FDSystem); + txfd_ptr->fd.FDSystem = 0x00000000; + txfd_ptr->fd.FDCtl = 0x00000000; + blocking_read_reg32(&txfd_ptr->fd.FDCtl); + +#if defined(CONFIG_DMA_NONCOHERENT) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + /* unmap dma sync */ + if (dma_skb != 0x00000000) + dma_unmap_single(lp->dev, dma_skb, + skb->len, DMA_NONE); +#endif + if (skb != NULL) + mspeth_free_skb(skb); + + /* advance to the next TX descriptor */ + atomic_inc(&lp->tx_qspc); + num_done++; + lp->tx_tail = (lp->tx_tail + 1) & TX_BUF_MASK; + + txfd_ptr = &(lp->txfd_base[lp->tx_tail]); + flush_memqueue(); + } + +#ifndef CONFIG_MSPETH_NAPI + /* + * If we freed at least one buffer and the queue is stopped + * then restart it. + */ + if (num_done > 0 && netif_queue_stopped(dev)) + netif_wake_queue(dev); + + /* re-enable interrupts regardless */ + msp_write(lp, MSPETH_Tx_Ctl, TX_CTL_CMD); + + /* Check for outstanding packets */ + status = msp_read(lp, MSPETH_Int_Src); + + /* If we have an outstanding packet, reschedule the tasklet */ + if (status & IntSrc_MacTx) { + /* ack interrupt, disable it, and reschedule */ + msp_write(lp, MSPETH_Int_Src, IntSrc_MacTx); + msp_write(lp, MSPETH_Tx_Ctl, TX_CTL_CMD & ~Tx_EnComp); + tasklet_schedule(&lp->tx_tasklet); + } +#endif /* CONFIG_MSPETH_NAPI */ +} + +/************************************************************************** + * If there is a timeout we soft restart the entire device + */ +static void +mspeth_tx_timeout(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + printk(KERN_WARNING "MSPETH(tx_timeout) %s: " + "transmit timed out, status 0x%08x\n", + dev->name, msp_read(lp, MSPETH_Tx_Stat)); + + /* try to restart the adaptor */ + mspeth_soft_restart(dev); +} + +/************************************************************************** + * Debugging code to dump out the transmit status register + * + * hammtrev, 2005-11-25: + * The Tx_NCarr condition makes a lot of noise on the PMC RG, but + * doesn't seem to affect the success of transmissions. Removing for now. + */ +#define TX_STA_ERR \ + (Tx_ExColl | Tx_Under | Tx_Defer | Tx_LateColl | Tx_TxPar | Tx_SQErr) +static void +mspeth_check_tx_stat(struct net_device *dev, int status) +{ + struct mspeth_priv *lp = netdev_priv(dev); + const char *msg = NULL; + + /* count collisions */ + if (status & Tx_ExColl) + lp->stats.collisions += 16; + if (status & Tx_TxColl_MASK) + lp->stats.collisions += status & Tx_TxColl_MASK; + + /* WORKAROUND: ignore LostCrS when there is no carrier .... */ + if (!netif_carrier_ok(dev)) + status &= ~Tx_NCarr; + + if (likely(!(status & TX_STA_ERR))) { + /* no error. */ + lp->stats.tx_packets++; + return; + } + + lp->stats.tx_errors++; + if (status & Tx_ExColl) { + lp->stats.tx_aborted_errors++; + msg = "Excessive Collision."; + } + if (status & Tx_Under) { + lp->stats.tx_fifo_errors++; + msg = "Tx FIFO Underrun."; + } + if (status & Tx_Defer) { + lp->stats.tx_fifo_errors++; + msg = "Excessive Deferral."; + } +#if 0 + if (status & Tx_NCarr) { + lp->stats.tx_carrier_errors++; + msg = "Lost Carrier Sense."; + } +#endif + if (status & Tx_LateColl) { + lp->stats.tx_aborted_errors++; + msg = "Late Collision."; + } + if (status & Tx_TxPar) { + lp->stats.tx_fifo_errors++; + msg = "Transmit Parity Error."; + } + if (status & Tx_SQErr) { + lp->stats.tx_heartbeat_errors++; + msg = "Signal Quality Error."; + } + if (msg) + printk(KERN_WARNING + "MSPETH(check_tx_stats) %s: %s (%#x)\n", + dev->name, msg, status); +} + +/* + * Get the current statistics. + * This may be called with the card open or closed. + */ +static struct net_device_stats * +mspeth_get_stats(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + unsigned long flags; + + if (netif_running(dev)) { + local_irq_save(flags); + /* Update the statistics from the device registers. */ + lp->stats.rx_missed_errors = msp_read(lp, MSPETH_Miss_Cnt); + local_irq_restore(flags); + } + + return &lp->stats; +} + +/* + * Set or clear the multicast filter for this adaptor. + * num_addrs == -1 Promiscuous mode, receive all packets + * num_addrs == 0 Normal mode, clear multicast list + * num_addrs > 0 Multicast mode, receive normal and MC packets, + * and do best-effort filtering. + */ +static void +mspeth_set_multicast_list(struct net_device *dev) +{ + struct mspeth_priv *lp = netdev_priv(dev); + + if (dev->flags & IFF_PROMISC) { + /* Enable promiscuous mode */ + msp_write(lp, MSPETH_ARC_Ctl, + ARC_CompEn | ARC_BroadAcc | + ARC_GroupAcc | ARC_StationAcc); + } else if ((dev->flags & IFF_ALLMULTI) || + dev->mc_count > ARC_ENTRY_MAX - 3) { + /* ARC 0, 1, 20 are reserved. */ + /* Disable promiscuous mode, use normal mode. */ + msp_write(lp, MSPETH_ARC_Ctl, + ARC_CompEn | ARC_BroadAcc | ARC_GroupAcc); + } else if (dev->mc_count) { + struct dev_mc_list* cur_addr = dev->mc_list; + int i; + int ena_bits = ARC_Ena_Bit(ARC_ENTRY_SOURCE); + + msp_write(lp, MSPETH_ARC_Ctl, 0); + /* Walk the address list, and load the filter */ + for (i = 0; i < dev->mc_count; i++, + cur_addr = cur_addr->next) { + if (!cur_addr) + break; + + /* entry 0, 1 is reserved. */ + mspeth_set_arc_entry(dev, i + 2, cur_addr->dmi_addr); + ena_bits |= ARC_Ena_Bit(i + 2); + } + msp_write(lp, MSPETH_ARC_Ena, ena_bits); + msp_write(lp, MSPETH_ARC_Ctl, ARC_CompEn | ARC_BroadAcc); + } else { + msp_write(lp, MSPETH_ARC_Ena, ARC_Ena_Bit(ARC_ENTRY_SOURCE)); + msp_write(lp, MSPETH_ARC_Ctl, ARC_CompEn | ARC_BroadAcc); + } +} + +static int +mspeth_proc_info(char *buf, char **bloc, off_t off, + int length, int *eof, void *data) +{ + int len = 0; + int i, cnt; + struct net_device *dev = (struct net_device *)data; + struct mspeth_priv *lp = netdev_priv(dev); + + /* finished reading regardless of anything else */ + if (off > 0) + return 0; + + len += sprintf(buf, "MSPETH hwunit %d statistics:\n", lp->hwunit); + len += sprintf(buf + len, "%s: tx_ints %d, rx_ints %d, " + "max_tx_qlen %d, tx_full %d, fd_exha %d\n", + dev->name, + lp->lstats.tx_ints, + lp->lstats.rx_ints, + lp->lstats.max_tx_qlen, + lp->lstats.tx_full, + lp->lstats.fd_exha); + len += sprintf(buf + len, " fd_base = %p\n\n", lp->fd_base); + len += sprintf(buf + len, " rxfd_base = %p, rxfd_curr = %p\n", + lp->rxfd_base, lp->rxfd_curr); + + if (lp->rxfd_base != NULL) { + cnt = 0; + for (i = 0; i < RX_BUF_NUM; i++) { + if (lp->rxfd_base[i].fd.FDCtl & FD_CownsFD) + cnt++; + } + len += sprintf(buf + len, + " Controller FD count = %d\n\n", cnt); + } + len += sprintf(buf + len, " tx_base = %p, tx_head = %d, " + "tx_tail = %d, qspc = %d\n", + lp->txfd_base, lp->tx_head, lp->tx_tail, + atomic_read(&lp->tx_qspc)); + len += sprintf(buf + len, " blfd_ptr = %p, rx_skbp = %p\n\n", + lp->blfd_ptr, lp->rx_skbp); + if (lp->mapaddr != NULL) + len += sprintf(buf + len, + " pause sent: %d, pause recv: %d\n\n", + msp_read(lp, MSPETH_PauseCnt), + msp_read(lp, MSPETH_RemPauCnt)); +#ifdef CONFIG_MSPETH_NAPI + len += sprintf(buf + len, " NAPI is enabled\n\n"); +#endif +#ifdef CONFIG_MSPETH_SKB_RECYCLE + len += sprintf(buf + len, + " Socket Buffer Recycling is enabled\n"); + len += sprintf(buf + len, + " recycle hits = %lu, recycle misses = %lu\n", + skb_bin.recycle_hits, skb_bin.recycle_misses); + len += sprintf(buf + len, " recycle bin skb count = %lu\n\n", + skb_bin.recycle_count); +#endif + + return len; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +/* platform device stuff for linux 2.6 */ +static char mspeth_string[] = "mspeth"; + +static struct platform_driver mspeth_driver = { + .probe = mspeth_probe, + .remove = __devexit_p(mspeth_remove), + .driver { + .name = mspeth_string, + }, +}; + +/* + * Register the mspeth with the kernel + */ +static int __init mspeth_init_module(void) +{ + printk(KERN_INFO "PMC MSPETH 10/100 Ethernet Driver\n"); + + if (platform_driver_register(&mspeth_driver)) { + printk(KERN_ERR "Driver registration failed\n"); + return -ENOMEM; + } + + return 0; +} + +/* + * Unregister the mspeth from the kernel + */ +static void __exit mspeth_cleanup_module(void) +{ + platform_driver_unregister(&mspeth_driver); +} + +MODULE_DESCRIPTION("PMC MSPETH 10/100 Ethernet Driver"); +MODULE_LICENSE("GPL"); + +module_init(mspeth_init_module); +module_exit(mspeth_cleanup_module); +#endif diff --git a/drivers/net/pmcmspeth.h b/drivers/net/pmcmspeth.h new file mode 100644 index 0000000..f1909aa --- /dev/null +++ b/drivers/net/pmcmspeth.h @@ -0,0 +1,624 @@ +/* + * PMC-Sierra MSP EVM ethernet driver for linux + * + * Copyright 2005-2007 PMC-Sierra, Inc + * + * Originally based on mspeth.c driver which contains substantially the + * same hardware. + * Based on skelton.c by Donald Becker. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' A ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _MSPETH_H_ +#define _MSPETH_H_ + +/************************************************************************** + * Cache size externs and defines + */ +extern int ic_lsize, dc_lsize; /* Primary cache linesize in bytes */ +extern int sc_lsize; /* Secondary cache linesize in bytes */ + /* must be included after the above */ + +/************************************************************************** + * Temporary define to determine cache policy -- at some time in the near + * future, this will get migrated to something in the configuration + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)) +#if !defined(CONFIG_UCLINUX) && \ + (CONF_CM_DEFAULT == CONF_CM_CACHABLE_NONCOHERENT) +#define CONFIG_DMA_NONCOHERENT +#endif +#endif + +/* Get the private data pointer */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)) +#define netdev_priv(dev) ((struct mspeth_priv *)dev->priv) +#endif + +/* Define __hotnet macro for 2.6 */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#define __hotnet +#endif + +/* Define dma_addr_t for 2.4 */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)) +#define dma_addr_t u32 +#endif + +/************************************************************************** + * Device constants for our various types of MSP chips + */ +#define MSPETH_MAX_UNITS 3 +#define STDETH_MAX_UNITS 8 + +/************************************************************************** + * Tuning parameters + */ +#define DMA_BURST_SIZE 32 /* maximum burst size for the DMA transfers */ +#define TX_TIMEOUT 1 /* time (in seconds) for the TX timeout */ + +#if defined(CONFIG_PMC_MSP7120_EVAL) || \ + defined(CONFIG_PMC_MSP7120_GW) || \ + defined(CONFIG_PMC_MSP7120_FPGA) +#define TX_THRESHOLD 100 /* MAC TX fifo depth before we start sending */ +#else +#define TX_THRESHOLD 1000 /* MAC TX fifo depth before we start sending */ +#endif +#define TX_POLL_CNT 0 /* interval for the TX poll mechanism + * -- not used, leave at zero */ +#define LINK_DELAY_DIV 4 /* delay for checking the link status */ +#define RX_MAX_PKT 16 /* maximum number of packet the RX handler */ + /* will process at one time */ + +/* + * Define the RX/TX buffer counts. Notice that they *must* be <= 256 and + * also a power of two. So much so that we test for it at compile time and + * set the order of the queue lengths instead of the numbers directly. + * + * cavanaug 2006-02-21: Changed buffer order from 5 to 6. This prevents + * corruption of the queues on eth1 that were preventing eth1 from working + * without the cable being unplugged and plugged back in. + */ +#define RX_BUF_ORDER 6 /* 64 buffers */ +#define TX_BUF_ORDER 6 /* 64 buffers */ + +/* Use 0 for production, 1 for verification, >2 for debug */ +#ifndef MSPETH_DEBUG +#define MSPETH_DEBUG 0 +#endif + +/************************************************************************** + * Buffer sizes + */ +#define MAX_PKT_SIZE 1532 +#define MSP_END_PREPEND 224 +#define MAX_ETH_BUFFER_SIZE (MAX_PKT_SIZE + MSP_END_PREPEND) +#define MSP_END_BUFSIZE (MAX_ETH_BUFFER_SIZE + 24) + +/************************************************************************** + * Option defines + */ +#define MSP_OPT_AUTO 0x00 +#define MSP_OPT_10M 0x01 +#define MSP_OPT_100M 0x02 +#define MSP_OPT_FDUP 0x04 +#define MSP_OPT_HDUP 0x08 +#define MSP_OPT_SWITCH 0x10 + +/************************************************************************** + * Local error codes etc (mac errors start at 9000) + */ +#define MSP_SUCCESS 0 +#define MSP_FAIL -1 +#define MSP_MAC_MEM_ALLOC_ERROR 9002 +#define MSP_MAC_PHY_ERROR 9006 +#define MSP_MAC_PHY_NO_LINK 9012 + +/************************************************************************** + * Hardware register locations & constants + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)) +#define MSP_MAC0_BASE 0xB8600000 /* Base address to MAC0 Controller */ +#define MSP_MAC1_BASE 0xB8700000 /* Base address to MAC1 Controller */ +#define MSP_MAC2_BASE 0xB8900000 /* Base address to MAC2 Controller */ +#define MSP_RST_BASE SYS_RST_REG /* Base address to system reset */ + +#define MSP_EA_RST MAC0_RST +#define MSP_EB_RST MAC1_RST +#define MSP_EC_RST MAC2_RST + +#define MSP_INT_MAC0 BRECISINT_MAC0 +#define MSP_INT_MAC1 BRECISINT_MAC1 +#define MSP_INT_MAC2 BRECISINT_MAC2 + +#define MEM_CFG1_REG MEM_CNFG1_REG +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#ifndef MSP_INT_MAC2 +#define MSP_INT_MAC2 0 +#endif +#endif + +/************************************************************************** + * Macros & inline functions + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)) +#define IRQ_HANDLED +#define IRQ_NONE +#endif + +/* Select the correct cache flush/invalidate operations */ +#if CONFIG_MIPS_L1_CACHE_SHIFT == 4 +#define CACHE_UNROLL cache16_unroll32 +#define UNROLL_INCR 0x200 +#elif CONFIG_MIPS_L1_CACHE_SHIFT == 5 +#define CACHE_UNROLL cache32_unroll32 +#define UNROLL_INCR 0x400 +#elif CONFIG_MIPS_L1_CACHE_SHIFT == 6 +#define CACHE_UNROLL cache64_unroll32 +#define UNROLL_INCR 0x800 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)) +#define CACHE_UNROLL cache16_unroll32 +#define UNROLL_INCR 0x200 +#endif + +/************************************************************************** + * Register definitions + */ + +/* MAC */ +#define MSPETH_DMA_Ctl 0x00 +#define MSPETH_TxFrmPtr 0x04 +#define MSPETH_TxThrsh 0x08 +#define MSPETH_TxPollCtr 0x0c +#define MSPETH_BLFrmPtr 0x10 +#define MSPETH_RxFragSize 0x14 +#define MSPETH_Int_En 0x18 +#define MSPETH_FDA_Bas 0x1c +#define MSPETH_FDA_Lim 0x20 +#define MSPETH_Int_Src 0x24 +#define MSPETH_PauseCnt 0x30 +#define MSPETH_RemPauCnt 0x34 +#define MSPETH_TxCtlFrmStat 0x38 +#define MSPETH_MAC_Ctl 0x40 +#define MSPETH_ARC_Ctl 0x44 +#define MSPETH_Tx_Ctl 0x48 +#define MSPETH_Tx_Stat 0x4c +#define MSPETH_Rx_Ctl 0x50 +#define MSPETH_Rx_Stat 0x54 +#define MSPETH_MD_DATA 0x58 +#define MSPETH_MD_CA 0x5c +#define MSPETH_ARC_Adr 0x60 +#define MSPETH_ARC_Data 0x64 +#define MSPETH_ARC_Ena 0x68 +#define MSPETH_Miss_Cnt 0x7c +#define MSPETH_BSWE1_Add 0xc0 +#define MSPETH_BSWE2_Add 0xc4 +#define MSPETH_BMWE1_Add 0xc8 +#define MSPETH_BMWE2_Add 0xcc +#define MSPETH_INTBRW_Add 0xd0 +#define MSPETH_BCTRL_Reg 0xd4 + +/* PHY */ +#define MSPPHY_MII_DATA 0x00 +#define MSPPHY_MII_CTRL 0x04 + +/* Reset */ +#define MSPRST_STS 0x00 +#define MSPRST_SET 0x04 +#define MSPRST_CLR 0x08 + +/* + * Bit Assignments + */ + +/* DMA_Ctl (0x00) bit assign -------------------------------------------*/ +#define DMA_RxAlign3 0x00C00000 /* Receive Alignment (skip 3 bytes) */ +#define DMA_RxAlign2 0x00800000 /* Receive Alignment (skip 2 bytes) */ +#define DMA_RxAlign1 0x00400000 /* Receive Alignment (skip 1 byte) */ +/* RESERVED 0x00300000 Not used, must be zero */ +#define DMA_M66EnStat 0x00080000 /* 1:Station clock/30 */ +#define DMA_IntMask 0x00040000 /* 1:Interupt mask */ +#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */ +#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */ +#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */ +#define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */ +#define DMA_TestMode 0x00002000 /* 1:Test Mode */ +#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */ +#define DMA_BRST_Mask 0x000001fc /* DMA Burst size */ +#define DMA_BRST_Shift 2 + +/* RxFragSize (0x14) bit assign --------------------------------------- */ +#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */ +#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */ + +/* + * Int_En (0x18) bit assign ------------------------------------------- + * Since bit 6 of the Int_En register at 0x18 is reserved and even writing + * to this register bit causes random interrupts, take caution when writing + * to this register - always write 0 there. For this reason there are two + * definitions for Enable and Disable and couldn't use the ~ of the Enable + * for Disable, + */ +#define IntEn_NRAB 0x00000800 /* Non-recoverable abort enable */ +#define IntEn_TxCtlCmp 0x00000400 /* Transmit Ctl Complete enable */ +#define IntEn_DmParErr 0x00000200 /* DMA Parity Error enable */ +#define IntEn_DParD 0x00000100 /* Data Parity Detected enable */ +#define IntEn_EarNot 0x00000080 /* Early Rx Notify enable */ +/* RESERVED 0x00000040 Not used, must be zero */ +#define IntEn_SSysErr 0x00000020 /* Signalled System Error enable */ +#define IntEn_RMAB 0x00000010 /* Received Master Abort enable */ +#define IntEn_RTAB 0x00000008 /* Received Target Abort enable */ +#define IntEn_STAB 0x00000004 /* Signaled Target Abort enable */ +#define IntEn_BLEx 0x00000002 /* Buffer List Exhausted enable */ +#define IntEn_FDAEx 0x00000001 /* FDA Exhausted Enable */ + +/* Int_Src (0x24) bit assign ------------------------------------------ */ +#define IntSrc_ExtE 0x00040000 /* External Event int. */ +/* RESERVED 0x00020000 Not used, must be zero */ +#define IntSrc_ExDefer 0x00010000 /* Excessive Tx Deferrals int. */ +#define IntSrc_Link_St 0x00008000 /* Link State Change status */ +#define IntSrc_NRAB 0x00004000 /* Non-recoverable abort int.*/ +#define IntSrc_DmParErr 0x00002000 /* DMA Parity Error int. */ +#define IntSrc_BLEx 0x00001000 /* Buffer List Exhausted int */ +#define IntSrc_FDAEx 0x00000800 /* FDA Exhausted, int. */ +#define IntSrc_NRAB_St 0x00000400 /* Non-recoverable abort status */ +#define IntSrc_Cmp 0x00000200 /* MAC ctrl packet int. */ +#define IntSrc_ExBD 0x00000100 /* Excessive BD status */ +#define IntSrc_DmParErr_St 0x00000080 /* DMA Parity Error status */ +#define IntSrc_EarNot 0x00000040 /* Rx early notify int. */ +#define IntSrc_SWInt_St 0x00000020 /* Software Request status */ +#define IntSrc_BLEx_St 0x00000010 /* Buffer List Exhausted status */ +#define IntSrc_FDAEx_St 0x00000008 /* FDA Exhausted status */ +/* RESERVED 0x00000004 Not used, must be zero */ +#define IntSrc_MacRx 0x00000002 /* Rx packet int. */ +#define IntSrc_MacTx 0x00000001 /* Tx packet int. */ + +/* MAC_Ctl (0x40) bit assign ------------------------------------------ */ +#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */ +/* RESERVED 0x00004000 Not used, must be zero */ +#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */ +#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */ +#define MAC_LnkChg 0x00000100 /* write 1 to clear Int_Link */ +#define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */ +#define MAC_Conn_Auto 0x00000000 /* 00:Connection mode (Automatic) */ +#define MAC_Conn_10M 0x00000020 /* 01:10Mbps endec) */ +#define MAC_Conn_Mll 0x00000040 /* 10:(Mll clock) */ +#define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */ +#define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */ +#define MAC_Reset 0x00000004 /* 1:Software Reset */ +#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */ +#define MAC_HaltReq 0x00000001 /* 1:Halt request */ + + /* ARC_Ctl (0x44) (bit assign ---------------------------------------- */ +#define ARC_CompEn 0x00000010 /* 1:ARC Compare Enable */ +#define ARC_NegCAM 0x00000008 /* 1:Reject packets ARC */ + /* recognizes, accept other */ +#define ARC_BroadAcc 0x00000004 /* 1:Broadcast accept */ +#define ARC_GroupAcc 0x00000002 /* 1:Multicast accept */ +#define ARC_StationAcc 0x00000001 /* 1:unicast accept */ + +/* Tx_Ctl (0x48) bit assign ------------------------------------------- */ +#define Tx_EnComp 0x00004000 /* 1:Enable Completion */ +#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */ +#define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */ +#define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */ +#define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */ +#define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */ +#define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */ +#define Tx_FBack 0x00000010 /* 1:Fast Back-off */ +#define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */ +#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */ +#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */ +#define Tx_En 0x00000001 /* 1:Transmit enable */ + +/* Tx_Stat (0x4C) bit assign ------------------------------------------ */ +#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */ +#define Tx_Halted 0x00008000 /* Tx Halted */ +#define Tx_Comp 0x00004000 /* Completion */ +#define Tx_TxPar 0x00002000 /* Tx Parity Error */ +#define Tx_LateColl 0x00001000 /* Late Collision */ +#define Tx_10Stat 0x00000800 /* 10Mbps Status */ +#define Tx_NCarr 0x00000400 /* No Carrier */ +#define Tx_Defer 0x00000200 /* Deferral */ +#define Tx_Under 0x00000100 /* Underrun */ +#define Tx_IntTx 0x00000080 /* Interrupt on Tx */ +#define Tx_Paused 0x00000040 /* Transmit Paused */ +#define Tx_TXDefer 0x00000020 /* Transmit Defered */ +#define Tx_ExColl 0x00000010 /* Excessive Collision */ +#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */ + +/* + * Rx_Ctl (0x50) bit assign ------------------------------------------- + * EnLenErr is a bit that is NOT defined in the manual but was added + * It indicates the reception of a frame whose protocol id field value + * does not match a length. This interrupt allows us the process IP + * and other packets whose protocol id field is not treated as a length + */ +#define Rx_EnGood 0x00004000 /* 1:Enable Good */ +#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */ +#define Rx_EnLenErr 0x00001000 /* 1:Enable Length Error */ +#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */ +#define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */ +#define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */ +#define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */ +/* RESERVED 0x00000080 Not used, must be zero */ +#define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */ +#define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */ +#define Rx_ShortEn 0x00000008 /* 1:Short Enable */ +#define Rx_LongEn 0x00000004 /* 1:Long Enable */ +#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */ +#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */ + +/* Rx_Stat (0x54) bit assign ------------------------------------------ */ +#define Rx_Halted 0x00008000 /* Rx Halted */ +#define Rx_Good 0x00004000 /* Rx Good */ +#define Rx_RxPar 0x00002000 /* Rx Parity Error */ +/* RESERVED 0x00001000 Not used, must be zero */ +#define Rx_LongErr 0x00000800 /* Rx Long Error */ +#define Rx_Over 0x00000400 /* Rx Overflow */ +#define Rx_CRCErr 0x00000200 /* Rx CRC Error */ +#define Rx_Align 0x00000100 /* Rx Alignment Error */ +#define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */ +#define Rx_IntRx 0x00000040 /* Rx Interrupt */ +#define Rx_CtlRecd 0x00000020 /* Rx Control Receive */ +#define Rx_Stat_Mask 0x0000EFC0 /* Rx All Status Mask */ + +/* MD_CA (0x5C) bit assign -------------------------------------------- */ +#define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */ +#define MD_CA_BUSY_BIT 0x00000800 /* 1:Busy (Start Operation) */ +#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */ +#define MD_CA_PHYADD 0x000003E0 /* bits 9:5 */ +#define MD_CA_PHYREG 0x0000001F /* bits 4:0 */ +#define MD_CA_PhyShift 5 +#define MD_MAX_PHY 32 /* Maximum number of PHY per MII */ +#define MD_UNASSIGNED_PHY 0xFD /* PHY address has not been */ + /* determined yet */ +#define MD_SWITCH_PHY 0xFE /* No PHY exists */ +#define MD_DYNAMIC_PHY 0xFF /* Dynamically find phy */ + +/* ARC_Ena (0x68) bit assign ------------------------------------------ */ +#define ARC_ENTRY_MAX 21 /* ARC Data entry max count */ +#define ARC_Ena_Mask ((1 << ARC_ENTRY_MAX) - 1) + /* ARC Enable bits (Max 21) */ +#define ARC_Ena_Bit(index) (1 << (index)) +#define ARC_ENTRY_DESTINATION 0 +#define ARC_ENTRY_SOURCE 1 +#define ARC_ENTRY_MACCTL 20 + +/* BCTRL_Reg (0xd4) bit assign ---------------------------------------- */ +#define RMII_Reset 0x00000004 /* RMII Reset */ +#define RMII_10MBIT 0x00000002 /* 1 if 10 Mbs, 0 if 100 Mbs */ +#define RMII_ClkRising 0x00000001 /* 0 if TxD generated off */ + /* falling edge, */ + /* 1 if generated off */ + /* rising edge of Tx-CLK */ + +/********************************************************************** + * Data structures + */ + +/* Frame descripter */ +struct f_desc { + volatile u32 FDNext; + volatile u32 FDSystem; + volatile u32 FDStat; + volatile u32 FDCtl; +}; + +/* Buffer descripter */ +struct b_desc { + volatile u32 BuffData; + volatile u32 BDCtl; +}; + +#define FD_ALIGN 16 + +/* Frame Descripter bit assign ---------------------------------------- */ +#define FD_Next_EOL 0x00000001 /* FDNext EOL indicator */ +#define FD_Next_MASK 0xFFFFFFF0 /* FDNext valid pointer */ + +#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */ +#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */ +#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */ +#define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */ +#define FD_FrmOpt_IntTx 0x20000000 /* Tx only */ +#define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */ +#define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */ +#define FD_FrmOpt_Packing 0x04000000 /* Rx only */ +#define FD_CownsFD 0x80000000 /* FD Controller owner bit */ +#define FD_BDCnt_SHIFT 16 +#define FD_CownsFD_Set 0x80010000 /* (FD_CownsFD | */ + /* (1 << FD_BDCnt_SHIFT)) */ + +/* Buffer Descripter bit assign --------------------------------------- */ +#define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */ +#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */ +#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */ +#define BD_CownsBD 0x80000000 /* BD Controller owner bit */ +#define BD_DataAlign_MASK 0xFFFFFFF0 /* Buffer alignment mask */ +#define BD_RxBDID_SHIFT 16 +#define BD_RxBDSeqN_SHIFT 24 + +/* Operational constants */ +#define DMA_CTL_CMD (DMA_M66EnStat | DMA_RxBigE | DMA_TxBigE | \ + DMA_RxAlign2 | (DMA_BURST_SIZE << DMA_BRST_Shift)) + +#define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \ + Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | \ + Tx_EnUnder | Tx_En) + +#define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver | \ + Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) + +#define INT_EN_CMD (IntEn_NRAB | IntEn_DmParErr | IntEn_SSysErr | \ + IntEn_BLEx | IntEn_FDAEx) + +#define FATAL_ERROR_INT (IntSrc_NRAB | IntSrc_DmParErr | IntSrc_BLEx) + +#define BMSR_EXISTS (BMSR_ANEGCAPABLE | BMSR_10HALF | BMSR_10FULL | \ + BMSR_100HALF | BMSR_100FULL) + +/* Error check and calculate constants & masks */ +#if RX_BUF_ORDER > 8 || RX_BUF_ORDER < 0 +#error "RX buffer order out of limits. 0 < ORDER < 9" +#endif + +#if TX_BUF_ORDER > 8 || TX_BUF_ORDER < 0 +#error "TX buffer order out of limits. 0 < ORDER < 9" +#endif + +#define RX_BUF_NUM (1 << RX_BUF_ORDER) +#define RX_BUF_MASK (RX_BUF_NUM - 1) +#define TX_BUF_NUM (1 << TX_BUF_ORDER) +#define TX_BUF_MASK (TX_BUF_NUM - 1) + +#ifdef CONFIG_MSPETH_NAPI +#define TXDONE_MAX_PKT 4 +#define NAPI_WEIGHT 64 /* Number of packets handled at one poll */ +#else +#define TXDONE_MAX_PKT TX_BUF_NUM +#endif /* CONFIG_MSPETH_NAPI */ + +#ifdef CONFIG_MSPETH_SKB_RECYCLE +#define SKBUFF_RECYCLABLE_SIZE (SKB_DATA_ALIGN(MSP_END_BUFSIZE + 2 + 16)) + +/* Handler for skb recycle bin */ +struct { + struct sk_buff *recycle_queue; /* recyclable skbs are queued here */ + unsigned long recycle_max; /* storage capacity in no.of skbs */ + unsigned long recycle_count; /* avilable skbs in bin */ + unsigned long user_count; /* bin usage count */ + unsigned long recycle_hits; /* number of hits */ + unsigned long recycle_misses; /* number of misses */ + spinlock_t lock; /* for mutual exclusion */ +} skb_bin; +#endif /* CONFIG_MSPETH_SKB_RECYCLE */ + +struct q_desc { + union { + struct f_desc fd; + struct f_desc fd0; + }; + union { + struct b_desc bd; + struct f_desc fd1; + }; +}; + +/* + * hammtrev, 2005-11-25: + * Apparently, the MSP Ethernet has a hardware issue which could hang the + * device if a BLEx interrupt comes before a FDAEx, so they should be + * avoided if at all possible. Changing to ensure there are twice as many + * buffer descriptors as frame descriptors. + */ +struct bl_desc { + struct f_desc fd; + struct b_desc bd[RX_BUF_NUM << 1]; +}; + + +/* Structure to define access to each phy (for control purposes) */ +struct mspeth_phy { + struct mspeth_phy *next_phy; + u8 hwunit; + u8 phyaddr; + void *memaddr; + bool assigned; + bool linkup; + spinlock_t lock; +}; + +/* Information that need to be kept for each board. */ +struct mspeth_priv { + /* device configuration & constants */ + u8 unit; /* logical unit number */ + u8 hwunit; /* hardware unit number */ + u8 option; /* option setting from PROM or bootline */ + int speed; /* actual speed, 10 or 100 */ + bool fullduplex; /* actual duplex */ + + /* device object pointer */ + struct device *dev; + + /* phy configuration & control index */ + struct mspeth_phy *phyptr; + + /* ioremapped register access cookie */ + void *mapaddr; + + /* ioremapped system reset registers */ + void *rstaddr; + + /* tasklet queues */ + struct tasklet_struct rx_tasklet; + struct tasklet_struct tx_tasklet; + struct tasklet_struct hard_restart_tasklet; + + /* link monitor timer */ + struct timer_list link_timer; + + /* statistics */ + struct net_device_stats stats; /* statistics */ + int fatal_icnt; + struct { + int max_tx_qlen; + int tx_ints; + int rx_ints; + int tx_full; + int fd_exha; + } lstats; + + /* + * Buffer structures + * + * Transmitting: Batch Mode. + * 1 BD in 1 TxFD + * circular list of FDs + * Receiving: Non-Packing mode + * 1 circular FD for Free Buffer List. + * RX_BUF_NUM BD in Free Buffer FD. + * One Free Buffer BD has preallocated skb data + */ + void *fd_base; + + struct q_desc *rxfd_base; /* RX FD region ptr */ + struct q_desc *rxfd_curr; /* RX FD current ptr */ + struct q_desc *txfd_base; /* TX FD region ptr */ + + u32 tx_head, tx_tail; /* insert/delete for TX queue */ + atomic_t tx_qspc; /* space available on the transmit queue */ + + struct bl_desc *blfd_ptr; /* Free list FD head */ + struct sk_buff **rx_skbp; /* RX skb ptr array */ + dma_addr_t *rx_dma_skbp; /* RX dma map array */ +}; + +#endif /* _MSPETH_H_ */ diff --git a/arch/mips/pmc-sierra/msp71xx/msp_eth.c b/arch/mips/pmc-sierra/msp71xx/msp_eth.c new file mode 100644 index 0000000..8799960 --- /dev/null +++ b/arch/mips/pmc-sierra/msp71xx/msp_eth.c @@ -0,0 +1,122 @@ +/* + * The setup file for ethernet related hardware on PMC-Sierra MSP processors. + * + * Copyright 2005-2006 PMC-Sierra, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +#include +#include + +#if defined(CONFIG_PMC_MSP4200_GW) +#include +#include +#define MSP_ETH_GPIO 9 +#define MSP_ETH_GPIO_MODE_REG GPIO_CFG3_REG +#define MSP_ETH_GPIO_DATA_REG GPIO_DATA3_REG +#elif defined(CONFIG_PMC_MSP7120_GW) +#include +#include +#define MSP_ETH_GPIO 14 +#define MSP_ETH_GPIO_MODE_REG GPIO_CFG4_REG +#define MSP_ETH_GPIO_DATA_REG GPIO_DATA4_REG +#endif + +#define MSP_ETH_ID "mspeth" + +static struct resource msp_eth0_resources[] = { + [0] = { + .start = MSP_MAC0_BASE, + .end = MSP_MAC0_BASE + MSP_MAC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_MAC0, + .end = MSP_INT_MAC0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msp_eth1_resources[] = { + [0] = { + .start = MSP_MAC1_BASE, + .end = MSP_MAC1_BASE + MSP_MAC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSP_INT_MAC1, + .end = MSP_INT_MAC1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device msp_eth_devs[] = { + [0] = { + .name = MSP_ETH_ID, + .id = 0, + .num_resources = ARRAY_SIZE(msp_eth0_resources), + .resource = msp_eth0_resources, + }, + [1] = { + .name = MSP_ETH_ID, + .id = 1, + .num_resources = ARRAY_SIZE(msp_eth1_resources), + .resource = msp_eth1_resources, + }, +}; + +static int __init msp_eth_setup(void) +{ + int i, ret = 0; + +#if defined(CONFIG_PMC_MSP4200_GW) || \ + defined(CONFIG_PMC_MSP7120_GW) + /* Configure the GPIO and take the ethernet PHY out of reset */ + set_value_reg32(MSP_ETH_GPIO_MODE_REG, + BASIC_MODE_MASK(MSP_ETH_GPIO), + BASIC_MODE(MSP_GPIO_OUTPUT, MSP_ETH_GPIO)); + set_reg32(MSP_ETH_GPIO_DATA_REG, + BASIC_DATA_MASK(MSP_ETH_GPIO)); +#endif + + /* Register the ethernet devices and bind the drivers */ + for (i = 0; i < ARRAY_SIZE(msp_eth_devs); i++) { + ret = platform_device_register(&msp_eth_devs[i]); + if (ret) { + while (--i >= 0) + platform_device_unregister(&msp_eth_devs[i]); + break; + } + } + + if (ret) + printk(KERN_WARNING + "Could not initialize MSPETH device structures.\n"); + + return ret; +} + +subsys_initcall(msp_eth_setup); From Fabrice.Aeschbacher@siemens.com Fri Apr 27 08:59:39 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Apr 2007 08:59:43 +0100 (BST) Received: from lizzard.sbs.de ([194.138.37.39]:64089 "EHLO lizzard.sbs.de") by ftp.linux-mips.org with ESMTP id S20021611AbXD0H7j convert rfc822-to-8bit (ORCPT ); Fri, 27 Apr 2007 08:59:39 +0100 Received: from mail2.sbs.de (localhost [127.0.0.1]) by lizzard.sbs.de (8.12.6/8.12.6) with ESMTP id l3R7xT4K015403; Fri, 27 Apr 2007 09:59:29 +0200 Received: from fthw9xoa.ww002.siemens.net (fthw9xoa.ww002.siemens.net [157.163.133.201]) by mail2.sbs.de (8.12.6/8.12.6) with ESMTP id l3R7xMW2006598; Fri, 27 Apr 2007 09:59:28 +0200 Received: from stgw002a.ww002.siemens.net ([141.73.158.150]) by fthw9xoa.ww002.siemens.net with Microsoft SMTPSVC(6.0.3790.1830); Fri, 27 Apr 2007 09:59:24 +0200 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: pcmcia - failed to initialize IDE interface Date: Fri, 27 Apr 2007 10:00:06 +0200 Message-ID: In-Reply-To: <20070425190753.fb8c272d.akpm@linux-foundation.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: pcmcia - failed to initialize IDE interface Thread-Index: AceHqEmPYMhqH9+RSm+Ie3xgpMcxxgA9vZhw From: "Aeschbacher, Fabrice" To: Cc: "lkml" , X-OriginalArrivalTime: 27 Apr 2007 07:59:24.0197 (UTC) FILETIME=[F8672550:01C788A1] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14922 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Fabrice.Aeschbacher@siemens.com Precedence: bulk X-list: linux-mips I think I isolated the problem: in ide-cs.c, ide_config() is calling pcmcia_request_irq(), and this function happens to set irq=35. This irq was not rejected later in ide_probe.c, hwif_init(): ide0: Disabled unable to get IRQ 35 I noticed that the old kernel 2.4.26 used irq=40 here. So I tried to force pcmcia_request_irq() to set irq=40, like follows: --- linux-2.6.20.7-orig/drivers/pcmcia/pcmcia_resource.c 2007-04-15 21:08:02.000000000 +0200 +++ linux-2.6.20.7/drivers/pcmcia/pcmcia_resource.c 2007-04-27 09:20:41.000000000 +0200 @@ -867,6 +867,7 @@ printk(KERN_WARNING "pcmcia: request for exclusive IRQ could not be fulfilled.\n"); printk(KERN_WARNING "pcmcia: the driver needs updating to supported shared IRQ lines.\n"); } + irq = 40; c->irq.Attributes = req->Attributes; s->irq.AssignedIRQ = req->AssignedIRQ = irq; s->irq.Config++; and this happens to work: ide_config() succeeds, and finally I can mount the CF and use it. Other values for irq (i tried 39, 41) won't work either. Which would be the correct way to make pcmcia_request_irq() use the correct value of 40? Fabrice > -----Original Message----- > From: Andrew Morton [mailto:akpm@linux-foundation.org] > Sent: Donnerstag, 26. April 2007 04:08 > To: Aeschbacher, Fabrice > Cc: lkml; linux-mips@linux-mips.org > Subject: Re: pcmcia - failed to initialize IDE interface > > On Wed, 25 Apr 2007 15:27:26 +0200 "Aeschbacher, Fabrice" > wrote: > > > Hi, > > > > [kernel 2.6.20.7, arch=mips, processor=amd au1550] > > > > I'm trying to install a 2.6 kernel on an Alchemy au1550, and having > > problem with the pcmcia socket, where I plugged a > CompactFlash card. > > The card seems to be recognized by the kernel, appears in > > /sys/bus/pcmcia/devices, but not in /proc/bus/pccard, and I can't > > access the device (/dev/hda). > > > > The relevant console messages: > > ---------------------------------------------------------------- > > pccard: PCMCIA card inserted into slot 0 > > pcmcia: registering new device pcmcia0.0 > > hda: SanDisk SDCFB-64, CFA DISK drive > > ide0: Disabled unable to get IRQ 35. > > ide0: failed to initialize IDE interface > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide0: I/O resource 0x10200E-0x10200E not free. > > ide0: ports already in use, skipping probe > > ide-cs: ide_register() at 0x102000 & 0x10200e, irq 35 failed > > ---------------------------------------------------------------- > > > > Here is the relevant part of the kernel config: > > CONFIG_IDE=y > > CONFIG_IDE_GENERIC=y > > CONFIG_BLK_DEV_IDE=y > > CONFIG_BLK_DEV_IDECS=y > > CONFIG_PCCARD=y > > CONFIG_PCMCIA_DEBUG=y > > CONFIG_PCMCIA=y > > CONFIG_PCMCIA_AU1X00=y > > > > (cc'ed linux-mips) > > Perhaps /proc/ioports will tell us where the conflict lies. > > The output of `dmesg -s 1000000' might also be needed. > From Fabrice.Aeschbacher@siemens.com Fri Apr 27 09:41:55 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Apr 2007 09:41:57 +0100 (BST) Received: from gecko.sbs.de ([194.138.37.40]:15951 "EHLO gecko.sbs.de") by ftp.linux-mips.org with ESMTP id S20021616AbXD0Ilz convert rfc822-to-8bit (ORCPT ); Fri, 27 Apr 2007 09:41:55 +0100 Received: from mail2.sbs.de (localhost [127.0.0.1]) by gecko.sbs.de (8.12.6/8.12.6) with ESMTP id l3R8fnAT026886; Fri, 27 Apr 2007 10:41:49 +0200 Received: from fthw9xoa.ww002.siemens.net (fthw9xoa.ww002.siemens.net [157.163.133.201]) by mail2.sbs.de (8.12.6/8.12.6) with ESMTP id l3R8fmxJ019684; Fri, 27 Apr 2007 10:41:48 +0200 Received: from stgw002a.ww002.siemens.net ([141.73.158.150]) by fthw9xoa.ww002.siemens.net with Microsoft SMTPSVC(6.0.3790.1830); Fri, 27 Apr 2007 10:41:48 +0200 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: pcmcia - failed to initialize IDE interface Date: Fri, 27 Apr 2007 10:42:31 +0200 Message-ID: In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: pcmcia - failed to initialize IDE interface Thread-Index: AceHqEmPYMhqH9+RSm+Ie3xgpMcxxgA9vZhwAAIIYDA= From: "Aeschbacher, Fabrice" To: Cc: , "lkml" X-OriginalArrivalTime: 27 Apr 2007 08:41:48.0655 (UTC) FILETIME=[E5049FF0:01C788A7] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14923 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Fabrice.Aeschbacher@siemens.com Precedence: bulk X-list: linux-mips > Which would be the correct way to make pcmcia_request_irq() > use the correct value of 40? This is in drivers/pcmcia/au1000_db1x00.c: db1x00_pcmcia_hw_init(): skt->irq = AU1000_GPIO_8; /* = 40 */ Now the CF is working fine. Fabrice From jan.nikitenko@gmail.com Fri Apr 27 19:43:19 2007 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 27 Apr 2007 19:43:24 +0100 (BST) Received: from ug-out-1314.google.com ([66.249.92.175]:41364 "EHLO ug-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20021450AbXD0SnT (ORCPT ); Fri, 27 Apr 2007 19:43:19 +0100 Received: by ug-out-1314.google.com with SMTP id 40so749654uga for ; Fri, 27 Apr 2007 11:42:18 -0700 (PDT) DKIM-Signature: a=rsa-sha1; c=relaxed/relaxed; d=gmail.com; s=beta; h=domainkey-signature:received:received:message-id:date:from:user-agent:mime-version:to:cc:subject:content-type; b=FvoogL413hfkm2+FlPke6MMMW2x17pqUwiP163dO9zqnjKjGpnVPQbBd21OEAz39peWPPn5ro+q3lWpLeqRmcS9HMw2JvUH27KMdQfVCAaCjUzb9DmDGcJ4/OO42rkrjuvSmADuyhGohiKblgozYsc9TTTjvN6l9bpI6acBuQ5k= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=beta; h=received:message-id:date:from:user-agent:mime-version:to:cc:subject:content-type; b=DiO+bH9RDz3NLsPtRULzY2vdqxLsGg7IOOZZuoAH+9JcKKnA5JDo+yy6q4EPSWwNku4E7MHTk5TrhBX64ebQhFqfUGJlOYw6LahNXuv7TlG0QgjBOwKQ++i0UOHusH4fu9cvtVWH89WkT+5hg2E6VjA5rECGQgiVsyuw0/iGdW8= Received: by 10.82.175.2 with SMTP id x2mr6365371bue.1177699337750; Fri, 27 Apr 2007 11:42:17 -0700 (PDT) Received: from ?194.132.8.27? ( [85.70.229.122]) by mx.google.com with ESMTP id c22sm591760ika.2007.04.27.11.42.15; Fri, 27 Apr 2007 11:42:16 -0700 (PDT) Message-ID: <46324403.4080606@gmail.com> Date: Fri, 27 Apr 2007 20:42:11 +0200 From: Jan Nikitenko User-Agent: Thunderbird 1.5.0.10 (X11/20070327) MIME-Version: 1.0 To: David Brownell CC: spi-devel-general@lists.sourceforge.net, linux-mips@linux-mips.org Subject: spi: Add support for au1550 spi controller Content-Type: multipart/mixed; boundary="------------060606060301060801020402" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 14924 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jan.nikitenko@gmail.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------060606060301060801020402 Content-Type: text/plain; charset=ISO-8859-2; format=flowed Content-Transfer-Encoding: 7bit Here is a patch (for 2.6.21 git as of 2007-04-27) with complete support for alchemy au1550 psc spi controller. It supports dma transfers using alchemy descriptor based dma controller for 4 to 8 bits per spi word transfers. For 9 to 24 bits per spi word transfers, pio irq based mode is used to avoid setup of dma channels from scratch on each number of bits per word change. Tested with au1550, may also work on other mips alchemy cpus, like au1200/au1210/au1250. Used extensively with SD card connected via SPI, handles 8.1MHz spi clock transfers using dma without any problem (the highest spi clock freq possible to get internally with au1550 running on 324MHz). The driver supports sharing of spi bus by multiple devices, all features of alchemy spi controller are supported (all spi modes, msb/lsb first, bits per word in 4 to 24 range). As the spi clock of the controller depends on main input clock that shall be configured externally, platform data structure for au1550 spi controller driver contains mainclk_hz attribute to define the input clock hz - from this value, dividers of the controller for spi clock are set up for required frequency. Jan Signed-off-by: Jan Nikitenko drivers/spi/Kconfig | 11 drivers/spi/Makefile | 1 drivers/spi/au1550_spi.c | 959 ++++++++++++++++++++++++++++++ include/asm-mips/mach-au1x00/au1550_spi.h | 16 4 files changed, 987 insertions(+) --------------060606060301060801020402 Content-Type: text/plain; name="au1550-spi.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="au1550-spi.patch" diff -urN linux-git.orig/drivers/spi/au1550_spi.c linux-git/drivers/spi/au1550_spi.c --- linux-git.orig/drivers/spi/au1550_spi.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-git/drivers/spi/au1550_spi.c 2007-04-27 20:20:32.000000000 +0200 @@ -0,0 +1,959 @@ +/* + * au1550_spi.c - au1550 psc spi controller driver + * may work also with au1200, au1210, au1250 + * will not work on au1000, au1100 and au1500 (no full spi controller there) + * + * Copyright (c) 2006 ATRON electronic GmbH + * Author: Jan Nikitenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static unsigned usedma = 1; +module_param(usedma, uint, 0644); + +/* +#define AU1550_SPI_DEBUG_LOOPBACK +*/ + + +#define AU1550_SPI_DBDMA_DESCRIPTORS 1 +#define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U + +struct au1550_spi { + struct spi_bitbang bitbang; + + volatile psc_spi_t __iomem *regs; + int irq; + unsigned freq_max; + unsigned freq_min; + + unsigned len; + unsigned tx_count; + unsigned rx_count; + const u8 *tx; + u8 *rx; + + void (*rx_word)(struct au1550_spi *hw); + void (*tx_word)(struct au1550_spi *hw); + int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t); + irqreturn_t (*irq_callback)(struct au1550_spi *hw); + + struct completion master_done; + + u32 dma_tx_id; + u32 dma_rx_id; + u32 dma_tx_ch; + u32 dma_rx_ch; + + u8 *dma_rx_tmpbuf; + unsigned dma_rx_tmpbuf_size; + u32 dma_rx_tmpbuf_addr; + + struct spi_master *master; + struct device *dev; + struct au1550_spi_info *pdata; +}; + + +static u64 au1550_spi_dma_mask = ~(u32)0; + +/* we need 8-bit memory device for dma transfers to/from spi fifo */ +static dbdev_tab_t au1550_spi_mem_dbdev = +{ + DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,0,8,0x00000000,0,0 +}; + +static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw); + + +/** + * compute BRG and DIV bits to setup spi clock based on main input clock rate + * that was specified in platform data structure + * according to au1550 datasheet: + * psc_tempclk = psc_mainclk / (2 << DIV) + * spiclk = psc_tempclk / (2 * (BRG + 1)) + * BRG valid range is 4..63 + * DIV valid range is 0..3 + */ +static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz) +{ + u32 mainclk_hz = hw->pdata->mainclk_hz; + u32 div, brg; + + for (div = 0; div < 4; div++) { + brg = mainclk_hz / speed_hz / (4 << div); + /* now we have BRG+1 in brg, so count with that */ + if (brg < (4 + 1)) { + brg = (4 + 1); /* speed_hz too big */ + break; /* set lowest brg (div is == 0) */ + } + if (brg <= (63 + 1)) + break; /* we have valid brg and div */ + } + if (div == 4) { + div = 3; /* speed_hz too small */ + brg = (63 + 1); /* set highest brg and div */ + } + brg--; + return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div); +} + +static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw) +{ + hw->regs->psc_spimsk = + PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO | + PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO | + PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD; + au_sync(); + + hw->regs->psc_spievent = PSC_SPIEVNT_MM | PSC_SPIEVNT_RR + | PSC_SPIEVNT_RO | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR + | PSC_SPIEVNT_TO | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD + | PSC_SPIEVNT_MD; + au_sync(); +} + +static void au1550_spi_reset_fifos(struct au1550_spi *hw) +{ + u32 pcr; + hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC; + au_sync(); + do { + pcr = hw->regs->psc_spipcr; + au_sync(); + } while (pcr != 0); +} + +/* + * dma transfers are used for the most common spi word size of 8-bits + * we cannot easily change already set up dma channels' width, so if we wanted + * dma support for more than 8-bit words (up to 24 bits), we would need to + * setup dma channels from scratch on each spi transfer, based on bits_per_word + * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits + * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode + * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set() + */ +static void au1550_spi_chipsel(struct spi_device *spi, int value) +{ + struct au1550_spi *hw = spi_master_get_devdata(spi->master); + unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; + u32 cfg, stat; + + switch (value) { + case BITBANG_CS_INACTIVE: + if (hw->pdata->deactivate_cs) + hw->pdata->deactivate_cs(hw->pdata, spi->chip_select, + cspol); + break; + + case BITBANG_CS_ACTIVE: + au1550_spi_bits_handlers_set(hw, spi->bits_per_word); + + cfg = hw->regs->psc_spicfg; + au_sync(); + hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; + au_sync(); + + if (spi->mode & SPI_CPOL) + cfg |= PSC_SPICFG_BI; + else + cfg &= ~PSC_SPICFG_BI; + if (spi->mode & SPI_CPHA) + cfg &= ~PSC_SPICFG_CDE; + else + cfg |= PSC_SPICFG_CDE; + + if (spi->mode & SPI_LSB_FIRST) + cfg |= PSC_SPICFG_MLF; + else + cfg &= ~PSC_SPICFG_MLF; + + if (usedma && spi->bits_per_word <= 8) + cfg &= ~PSC_SPICFG_DD_DISABLE; + else + cfg |= PSC_SPICFG_DD_DISABLE; + cfg = PSC_SPICFG_CLR_LEN(cfg); + cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word); + + cfg = PSC_SPICFG_CLR_BAUD(cfg); + cfg &= ~PSC_SPICFG_SET_DIV(3); + cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz); + + hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE; + au_sync(); + do { + stat = hw->regs->psc_spistat; + au_sync(); + } while ((stat & PSC_SPISTAT_DR) == 0); + + if (hw->pdata->activate_cs) + hw->pdata->activate_cs(hw->pdata, spi->chip_select, + cspol); + break; + } +} + +static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t) +{ + struct au1550_spi *hw = spi_master_get_devdata(spi->master); + unsigned bpw, hz; + u32 cfg, stat; + + bpw = t ? t->bits_per_word : spi->bits_per_word; + hz = t ? t->speed_hz : spi->max_speed_hz; + + if (bpw < 4 || bpw > 24) { + dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n", + bpw); + return -EINVAL; + } + if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) { + dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n", + hz); + return -EINVAL; + } + + au1550_spi_bits_handlers_set(hw, spi->bits_per_word); + + cfg = hw->regs->psc_spicfg; + au_sync(); + hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; + au_sync(); + + if (usedma && bpw <= 8) + cfg &= ~PSC_SPICFG_DD_DISABLE; + else + cfg |= PSC_SPICFG_DD_DISABLE; + cfg = PSC_SPICFG_CLR_LEN(cfg); + cfg |= PSC_SPICFG_SET_LEN(bpw); + + cfg = PSC_SPICFG_CLR_BAUD(cfg); + cfg &= ~PSC_SPICFG_SET_DIV(3); + cfg |= au1550_spi_baudcfg(hw, hz); + + hw->regs->psc_spicfg = cfg; + au_sync(); + + if (cfg & PSC_SPICFG_DE_ENABLE) { + do { + stat = hw->regs->psc_spistat; + au_sync(); + } while ((stat & PSC_SPISTAT_DR) == 0); + } + + au1550_spi_reset_fifos(hw); + au1550_spi_mask_ack_all(hw); + return 0; +} + +static int au1550_spi_setup(struct spi_device *spi) +{ + struct au1550_spi *hw = spi_master_get_devdata(spi->master); + + if (spi->bits_per_word == 0) + spi->bits_per_word = 8; + if (spi->bits_per_word < 4 || spi->bits_per_word > 24) { + dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n", + spi->bits_per_word); + return -EINVAL; + } + + if (spi->max_speed_hz == 0) + spi->max_speed_hz = hw->freq_max; + if (spi->max_speed_hz > hw->freq_max + || spi->max_speed_hz < hw->freq_min) + return -EINVAL; + /* + * NOTE: cannot change speed and other hw settings immediately, + * otherwise sharing of spi bus is not possible, + * so do not call setupxfer(spi, NULL) here + */ + return 0; +} + +/* + * for dma spi transfers, we have to setup rx channel, otherwise there is + * no reliable way how to recognize that spi transfer is done + * dma complete callbacks are called before real spi transfer is finished + * and if only tx dma channel is set up (and rx fifo overflow event masked) + * spi master done event irq is not generated unless rx fifo is empty (emptied) + * so we need rx tmp buffer to use for rx dma if user does not provide one + */ +static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size) +{ + hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL); + if (!hw->dma_rx_tmpbuf) + return -ENOMEM; + hw->dma_rx_tmpbuf_size = size; + hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf, + size, DMA_FROM_DEVICE); + if (dma_mapping_error(hw->dma_rx_tmpbuf_addr)) { + kfree(hw->dma_rx_tmpbuf); + hw->dma_rx_tmpbuf = 0; + hw->dma_rx_tmpbuf_size = 0; + return -EFAULT; + } + return 0; +} + +static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw) +{ + dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr, + hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE); + kfree(hw->dma_rx_tmpbuf); + hw->dma_rx_tmpbuf = 0; + hw->dma_rx_tmpbuf_size = 0; +} + +static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t) +{ + struct au1550_spi *hw = spi_master_get_devdata(spi->master); + dma_addr_t dma_tx_addr; + dma_addr_t dma_rx_addr; + u32 res; + + hw->len = t->len; + hw->tx_count = 0; + hw->rx_count = 0; + + hw->tx = t->tx_buf; + hw->rx = t->rx_buf; + dma_tx_addr = t->tx_dma; + dma_rx_addr = t->rx_dma; + + /* + * check if buffers are already dma mapped, map them otherwise + * use rx buffer in place of tx if tx buffer was not provided + * use temp rx buffer (preallocated or realloc to fit) for rx dma + */ + if (t->rx_buf) { + if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ + dma_rx_addr = dma_map_single(hw->dev, + (void *)t->rx_buf, t->len, DMA_FROM_DEVICE); + if (dma_mapping_error(dma_rx_addr)) + dev_err(hw->dev, "rx dma map error\n"); + } + } else { + if (t->len > hw->dma_rx_tmpbuf_size) { + int ret; + au1550_spi_dma_rxtmp_free(hw); + ret = au1550_spi_dma_rxtmp_alloc(hw, + max(t->len, AU1550_SPI_DMA_RXTMP_MINSIZE)); + if (ret < 0) + return ret; + } + hw->rx = hw->dma_rx_tmpbuf; + dma_rx_addr = hw->dma_rx_tmpbuf_addr; + dma_sync_single_for_device(hw->dev, dma_rx_addr, + t->len, DMA_FROM_DEVICE); + } + if (t->tx_buf) { + if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ + dma_tx_addr = dma_map_single(hw->dev, + (void *)t->tx_buf, t->len, DMA_TO_DEVICE); + if (dma_mapping_error(dma_tx_addr)) + dev_err(hw->dev, "tx dma map error\n"); + } + } else { + dma_sync_single_for_device(hw->dev, dma_rx_addr, + t->len, DMA_BIDIRECTIONAL); + hw->tx = hw->rx; + } + + /* put buffers on the ring */ + res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len); + if (!res) + dev_err(hw->dev, "rx dma put dest error\n"); + + res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len); + if (!res) + dev_err(hw->dev, "tx dma put source error\n"); + + au1xxx_dbdma_start(hw->dma_rx_ch); + au1xxx_dbdma_start(hw->dma_tx_ch); + + /* by default enable nearly all events interrupt */ + hw->regs->psc_spimsk = PSC_SPIMSK_SD; + au_sync(); + + /* start the transfer */ + hw->regs->psc_spipcr = PSC_SPIPCR_MS; + au_sync(); + + wait_for_completion(&hw->master_done); + + au1xxx_dbdma_stop(hw->dma_tx_ch); + au1xxx_dbdma_stop(hw->dma_rx_ch); + + if (!t->rx_buf) { + /* using the temporal preallocated and premapped buffer */ + dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len, + DMA_FROM_DEVICE); + } + /* unmap buffers if mapped above */ + if (t->rx_buf && t->rx_dma == 0 ) + dma_unmap_single(hw->dev, dma_rx_addr, t->len, + DMA_FROM_DEVICE); + if (t->tx_buf && t->tx_dma == 0 ) + dma_unmap_single(hw->dev, dma_tx_addr, t->len, + DMA_TO_DEVICE); + + return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count; +} + +static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) +{ + u32 stat, evnt; + + stat = hw->regs->psc_spistat; + evnt = hw->regs->psc_spievent; + au_sync(); + if ((stat & PSC_SPISTAT_DI) == 0) { + dev_err(hw->dev, "Unexpected IRQ!\n"); + return IRQ_NONE; + } + + if ((evnt & + (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO + | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD)) != 0) { + /* + * due to an spi error we consider transfer as done, + * so mask all events until before next transfer start + * and stop the possibly running dma immediatelly + */ + au1550_spi_mask_ack_all(hw); + au1xxx_dbdma_stop(hw->dma_rx_ch); + au1xxx_dbdma_stop(hw->dma_tx_ch); + + /* get number of transfered bytes */ + hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch); + hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch); + + au1xxx_dbdma_reset(hw->dma_rx_ch); + au1xxx_dbdma_reset(hw->dma_tx_ch); + au1550_spi_reset_fifos(hw); + + dev_err(hw->dev, + "Unexpected SPI error: event=0x%x stat=0x%x!\n", + evnt, stat); + + complete(&hw->master_done); + return IRQ_HANDLED; + } + + if ((evnt & PSC_SPIEVNT_MD) != 0) { + /* transfer completed successfully */ + au1550_spi_mask_ack_all(hw); + hw->rx_count = hw->len; + hw->tx_count = hw->len; + complete(&hw->master_done); + } + return IRQ_HANDLED; +} + + +/* routines to handle different word sizes in pio mode */ +#define AU1550_SPI_RX_WORD(size, mask) \ +static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \ +{ \ + u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \ + au_sync(); \ + if (hw->rx) \ + *(u##size *)hw->rx = (u##size)fifoword; \ + hw->rx += (size) / 8; \ + hw->rx_count += (size) / 8; \ +} + +#define AU1550_SPI_TX_WORD(size, mask) \ +static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \ +{ \ + u32 fifoword = 0; \ + if (hw->tx) \ + fifoword = *(u##size *)hw->tx & (u32)(mask); \ + hw->tx += (size) / 8; \ + hw->tx_count += (size) / 8; \ + if (hw->tx_count >= hw->len) \ + fifoword |= PSC_SPITXRX_LC; \ + hw->regs->psc_spitxrx = fifoword; \ + au_sync(); \ +} + +AU1550_SPI_RX_WORD(8,0xff) +AU1550_SPI_RX_WORD(16,0xffff) +AU1550_SPI_RX_WORD(32,0xffffff) +AU1550_SPI_TX_WORD(8,0xff) +AU1550_SPI_TX_WORD(16,0xffff) +AU1550_SPI_TX_WORD(32,0xffffff) + +static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t) +{ + u32 stat, mask; + struct au1550_spi *hw = spi_master_get_devdata(spi->master); + + hw->tx = t->tx_buf; + hw->rx = t->rx_buf; + hw->len = t->len; + hw->tx_count = 0; + hw->rx_count = 0; + + /* by default enable nearly all events after filling tx fifo */ + mask = PSC_SPIMSK_SD; + + /* fill the transmit FIFO */ + while (hw->tx_count < hw->len) { + + hw->tx_word(hw); + + if (hw->tx_count >= hw->len) { + /* mask tx fifo request interrupt as we are done */ + mask |= PSC_SPIMSK_TR; + } + + stat = hw->regs->psc_spistat; + au_sync(); + if (stat & PSC_SPISTAT_TF) + break; + } + + /* enable event interrupts */ + hw->regs->psc_spimsk = mask; + au_sync(); + + /* start the transfer */ + hw->regs->psc_spipcr = PSC_SPIPCR_MS; + au_sync(); + + wait_for_completion(&hw->master_done); + + return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count; +} + +static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) +{ + int busy; + u32 stat, evnt; + + stat = hw->regs->psc_spistat; + evnt = hw->regs->psc_spievent; + au_sync(); + if ((stat & PSC_SPISTAT_DI) == 0) { + dev_err(hw->dev, "Unexpected IRQ!\n"); + return IRQ_NONE; + } + + if ((evnt & + (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO + | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD)) != 0) { + dev_err(hw->dev, + "Unexpected SPI error: event=0x%x stat=0x%x!\n", + evnt, stat); + /* + * due to an error we consider transfer as done, + * so mask all events until before next transfer start + */ + au1550_spi_mask_ack_all(hw); + complete(&hw->master_done); + return IRQ_HANDLED; + } + + /* + * while there is something to read from rx fifo + * or there is a space to write to tx fifo: + */ + do { + busy = 0; + stat = hw->regs->psc_spistat; + au_sync(); + + if ((stat & PSC_SPISTAT_RE) == 0 && hw->rx_count < hw->len) { + hw->rx_word(hw); + /* ack the receive request event */ + hw->regs->psc_spievent = PSC_SPIEVNT_RR; + au_sync(); + busy = 1; + } + + if ((stat & PSC_SPISTAT_TF) == 0 && hw->tx_count < hw->len) { + hw->tx_word(hw); + /* ack the transmit request event */ + hw->regs->psc_spievent = PSC_SPIEVNT_TR; + au_sync(); + busy = 1; + } + } while (busy); + + evnt = hw->regs->psc_spievent; + au_sync(); + + if (hw->rx_count >= hw->len || (evnt & PSC_SPIEVNT_MD) != 0) { + /* transfer completed successfully */ + au1550_spi_mask_ack_all(hw); + complete(&hw->master_done); + } + return IRQ_HANDLED; +} + +static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) +{ + struct au1550_spi *hw = spi_master_get_devdata(spi->master); + return hw->txrx_bufs(spi, t); +} + +static irqreturn_t au1550_spi_irq(int irq, void *dev, struct pt_regs *regs) +{ + struct au1550_spi *hw = dev; + return hw->irq_callback(hw); +} + +static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw) +{ + if (bpw <= 8) { + if (usedma) { + hw->txrx_bufs = &au1550_spi_dma_txrxb; + hw->irq_callback = &au1550_spi_dma_irq_callback; + } else { + hw->rx_word = &au1550_spi_rx_word_8; + hw->tx_word = &au1550_spi_tx_word_8; + hw->txrx_bufs = &au1550_spi_pio_txrxb; + hw->irq_callback = &au1550_spi_pio_irq_callback; + } + } else if (bpw <= 16) { + hw->rx_word = &au1550_spi_rx_word_16; + hw->tx_word = &au1550_spi_tx_word_16; + hw->txrx_bufs = &au1550_spi_pio_txrxb; + hw->irq_callback = &au1550_spi_pio_irq_callback; + } else { + hw->rx_word = &au1550_spi_rx_word_32; + hw->tx_word = &au1550_spi_tx_word_32; + hw->txrx_bufs = &au1550_spi_pio_txrxb; + hw->irq_callback = &au1550_spi_pio_irq_callback; + } +} + +static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) +{ + u32 stat, cfg; + + /* set up the PSC for SPI mode */ + hw->regs->psc_ctrl = PSC_CTRL_DISABLE; + au_sync(); + hw->regs->psc_sel = PSC_SEL_PS_SPIMODE; + au_sync(); + + hw->regs->psc_spicfg = 0; + au_sync(); + + hw->regs->psc_ctrl = PSC_CTRL_ENABLE; + au_sync(); + + do { + stat = hw->regs->psc_spistat; + au_sync(); + } while ((stat & PSC_SPISTAT_SR) == 0); + + + cfg = usedma ? 0 : PSC_SPICFG_DD_DISABLE; + cfg |= PSC_SPICFG_SET_LEN(8); + cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8; + /* use minimal allowed brg and div values as initial setting: */ + cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0); + +#ifdef AU1550_SPI_DEBUG_LOOPBACK + cfg |= PSC_SPICFG_LB; +#endif + + hw->regs->psc_spicfg = cfg; + au_sync(); + + au1550_spi_mask_ack_all(hw); + + hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE; + au_sync(); + + do { + stat = hw->regs->psc_spistat; + au_sync(); + } while ((stat & PSC_SPISTAT_DR) == 0); +} + + +static int au1550_spi_probe(struct platform_device *pdev) +{ + struct au1550_spi *hw; + struct spi_master *master; + int err = 0; + + master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi)); + if (master == NULL) { + dev_err(&pdev->dev, "No memory for spi_master\n"); + err = -ENOMEM; + goto err_nomem; + } + + hw = spi_master_get_devdata(master); + memset(hw, 0, sizeof(struct au1550_spi)); + + hw->master = spi_master_get(master); + hw->pdata = pdev->dev.platform_data; + hw->dev = &pdev->dev; + + if (hw->pdata == NULL) { + dev_err(&pdev->dev, "No platform data supplied\n"); + err = -ENOENT; + goto err_no_pdata; + } + + platform_set_drvdata(pdev, hw); + + init_completion(&hw->master_done); + + hw->bitbang.master = hw->master; + hw->bitbang.setup_transfer = au1550_spi_setupxfer; + hw->bitbang.chipselect = au1550_spi_chipsel; + hw->bitbang.master->setup = au1550_spi_setup; + hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs; + + switch (hw->pdata->bus_num) { + case 0: + hw->irq = AU1550_PSC0_INT; + hw->regs = (volatile psc_spi_t *)PSC0_BASE_ADDR; + hw->dma_rx_id = DSCR_CMD0_PSC0_RX; + hw->dma_tx_id = DSCR_CMD0_PSC0_TX; + break; + case 1: + hw->irq = AU1550_PSC1_INT; + hw->regs = (volatile psc_spi_t *)PSC1_BASE_ADDR; + hw->dma_rx_id = DSCR_CMD0_PSC1_RX; + hw->dma_tx_id = DSCR_CMD0_PSC1_TX; + break; + case 2: + hw->irq = AU1550_PSC2_INT; + hw->regs = (volatile psc_spi_t *)PSC2_BASE_ADDR; + hw->dma_rx_id = DSCR_CMD0_PSC2_RX; + hw->dma_tx_id = DSCR_CMD0_PSC2_TX; + break; + case 3: + hw->irq = AU1550_PSC3_INT; + hw->regs = (volatile psc_spi_t *)PSC3_BASE_ADDR; + hw->dma_rx_id = DSCR_CMD0_PSC3_RX; + hw->dma_tx_id = DSCR_CMD0_PSC3_TX; + break; + default: + dev_err(&pdev->dev, "Wrong bus_num of SPI\n"); + err = -ENOENT; + goto err_no_pdata; + } + + if (request_mem_region((unsigned long)hw->regs, sizeof(psc_spi_t), + pdev->name) == NULL) { + dev_err(&pdev->dev, "Cannot reserve iomem region\n"); + err = -ENXIO; + goto err_no_iores; + } + + + if (usedma) { + /* + * create memory device with 8 bits dev_devwidth + * needed for proper byte ordering to spi fifo + */ + int memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev); + if (!memid) { + dev_err(&pdev->dev, + "Cannot create dma 8 bit mem device\n"); + err = -ENXIO; + goto err_dma_add_dev; + } + + hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(memid, + hw->dma_tx_id, NULL, (void *)hw); + if (hw->dma_tx_ch == 0) { + dev_err(&pdev->dev, + "Cannot allocate tx dma channel\n"); + err = -ENXIO; + goto err_no_txdma; + } + au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8); + if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch, + AU1550_SPI_DBDMA_DESCRIPTORS) == 0) { + dev_err(&pdev->dev, + "Cannot allocate tx dma descriptors\n"); + err = -ENXIO; + goto err_no_txdma_descr; + } + + + hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id, + memid, NULL, (void *)hw); + if (hw->dma_rx_ch == 0) { + dev_err(&pdev->dev, + "Cannot allocate rx dma channel\n"); + err = -ENXIO; + goto err_no_rxdma; + } + au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8); + if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch, + AU1550_SPI_DBDMA_DESCRIPTORS) == 0) { + dev_err(&pdev->dev, + "Cannot allocate rx dma descriptors\n"); + err = -ENXIO; + goto err_no_rxdma_descr; + } + + e