From yoichi_yuasa@tripeaks.co.jp Sun Oct 1 11:48:58 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Oct 2006 11:49:00 +0100 (BST) Received: from mo32.po.2iij.net ([210.128.50.17]:61709 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20037591AbWJAKs6 (ORCPT ); Sun, 1 Oct 2006 11:48:58 +0100 Received: by mo.po.2iij.net (mo32) id k91AmsUY014903; Sun, 1 Oct 2006 19:48:54 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox30) id k91Amq4c090868 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sun, 1 Oct 2006 19:48:52 +0900 (JST) Date: Sun, 1 Oct 2006 19:43:27 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH 2/3] rename SERIAL_PORT_DEFNS for EV64120 Message-Id: <20061001194327.02fceb06.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20061001193528.003d01d8.yoichi_yuasa@tripeaks.co.jp> References: <20061001193528.003d01d8.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12751 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has renamed serial ports definition for EV64120. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/serial.h mips/include/asm-mips/serial.h --- mips-orig/include/asm-mips/serial.h 2006-10-01 16:12:38.497543500 +0900 +++ mips/include/asm-mips/serial.h 2006-10-01 16:30:18.963818500 +0900 @@ -55,19 +55,18 @@ * Galileo EV64120 evaluation board */ #ifdef CONFIG_MIPS_EV64120 -#include -#include -#define EV96100_SERIAL_PORT_DEFNS \ - { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \ +#include +#define EV64120_SERIAL_PORT_DEFNS \ + { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \ .flags = STD_COM_FLAGS, \ - .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \ + .iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \ .io_type = SERIAL_IO_MEM }, \ - { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \ + { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \ .flags = STD_COM_FLAGS, \ - .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \ + .iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \ .io_type = SERIAL_IO_MEM }, #else -#define EV96100_SERIAL_PORT_DEFNS +#define EV64120_SERIAL_PORT_DEFNS #endif #ifdef CONFIG_MIPS_ITE8172 @@ -239,7 +238,7 @@ #define SERIAL_PORT_DFNS \ DDB5477_SERIAL_PORT_DEFNS \ - EV96100_SERIAL_PORT_DEFNS \ + EV64120_SERIAL_PORT_DEFNS \ IP32_SERIAL_PORT_DEFNS \ ITE_SERIAL_PORT_DEFNS \ IVR_SERIAL_PORT_DEFNS \ From yoichi_yuasa@tripeaks.co.jp Sun Oct 1 11:49:24 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Oct 2006 11:49:26 +0100 (BST) Received: from mo32.po.2iij.net ([210.128.50.17]:25652 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20037592AbWJAKs7 (ORCPT ); Sun, 1 Oct 2006 11:48:59 +0100 Received: by mo.po.2iij.net (mo32) id k91AmvPX014906; Sun, 1 Oct 2006 19:48:57 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox30) id k91AmoO8090851 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sun, 1 Oct 2006 19:48:50 +0900 (JST) Date: Sun, 1 Oct 2006 19:35:28 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH 1/3] add UART IRQ number for EV64120 Message-Id: <20061001193528.003d01d8.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12752 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has added UART IRQ number for EV64120. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/mach-ev64120/mach-gt64120.h mips/include/asm-mips/mach-ev64120/mach-gt64120.h --- mips-orig/include/asm-mips/mach-ev64120/mach-gt64120.h 2006-10-01 16:12:37.741496250 +0900 +++ mips/include/asm-mips/mach-ev64120/mach-gt64120.h 2006-10-01 16:14:24.228151250 +0900 @@ -42,6 +42,7 @@ extern unsigned long gt64120_base; #define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR)) #define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR)) #define EV64120_BASE_BAUD ( 3686400 / 16 ) +#define EV64120_UART_IRQ 6 /* * PCI interrupts will come in on either the INTA or INTD interrups lines, From yoichi_yuasa@tripeaks.co.jp Sun Oct 1 11:49:49 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Oct 2006 11:49:52 +0100 (BST) Received: from mo30.po.2iij.net ([210.128.50.53]:60168 "EHLO mo30.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20037784AbWJAKs7 (ORCPT ); Sun, 1 Oct 2006 11:48:59 +0100 Received: by mo.po.2iij.net (mo30) id k91Amvd8011953; Sun, 1 Oct 2006 19:48:57 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox30) id k91Amr4F090877 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sun, 1 Oct 2006 19:48:53 +0900 (JST) Date: Sun, 1 Oct 2006 19:47:08 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH 3/3] remove unused galileo-boars header files Message-Id: <20061001194708.23bc7991.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20061001194327.02fceb06.yoichi_yuasa@tripeaks.co.jp> References: <20061001193528.003d01d8.yoichi_yuasa@tripeaks.co.jp> <20061001194327.02fceb06.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12753 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has removed unused galileo-boards header files. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/galileo-boards/ev96100.h mips/include/asm-mips/galileo-boards/ev96100.h --- mips-orig/include/asm-mips/galileo-boards/ev96100.h 2006-10-01 16:12:37.713494500 +0900 +++ mips/include/asm-mips/galileo-boards/ev96100.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,55 +0,0 @@ -/* - * - */ -#ifndef _MIPS_EV96100_H -#define _MIPS_EV96100_H - -#include - -/* - * GT64120 config space base address - */ -#define GT64120_BASE (KSEG1ADDR(0x14000000)) -#define MIPS_GT_BASE GT64120_BASE - -/* - * PCI Bus allocation - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - -/* - * Duart I/O ports. - */ -#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20) -#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00) - - -/* - * EV96100 interrupt controller register base. - */ -#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) - -/* - * EV96100 UART register base. - */ -#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR -#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR -#define EV96100_BASE_BAUD ( 3686400 / 16 ) - - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. - */ -#define __GT_READ(ofs) \ - (*(volatile u32 *)(GT64120_BASE+(ofs))) -#define __GT_WRITE(ofs, data) \ - do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) -#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) -#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) - -#endif /* !(_MIPS_EV96100_H) */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/galileo-boards/ev96100int.h mips/include/asm-mips/galileo-boards/ev96100int.h --- mips-orig/include/asm-mips/galileo-boards/ev96100int.h 2006-10-01 16:12:37.713494500 +0900 +++ mips/include/asm-mips/galileo-boards/ev96100int.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,12 +0,0 @@ -/* - * - */ -#ifndef _MIPS_EV96100INT_H -#define _MIPS_EV96100INT_H - -#define EV96100INT_UART_0 6 /* IP 6 */ -#define EV96100INT_TIMER 7 /* IP 7 */ - -extern void ev96100int_init(void); - -#endif /* !(_MIPS_EV96100_H) */ From anemo@mba.ocn.ne.jp Sun Oct 1 15:31:01 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Oct 2006 15:31:02 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:29126 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20037855AbWJAObB (ORCPT ); Sun, 1 Oct 2006 15:31:01 +0100 Received: from localhost (p3194-ipad03funabasi.chiba.ocn.ne.jp [219.160.83.194]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id ED740A675; Sun, 1 Oct 2006 23:30:54 +0900 (JST) Date: Sun, 01 Oct 2006 23:33:06 +0900 (JST) Message-Id: <20061001.233306.126574447.anemo@mba.ocn.ne.jp> To: girishvg@gmail.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, clameter@sgi.com Subject: Re: [PATCH] fix size of zones_size and zholes_size array From: Atsushi Nemoto In-Reply-To: References: <20060930.033406.104030456.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12754 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips CC-d to Christoph Lameter. On Sat, 30 Sep 2006 03:41:39 +0900, girish wrote: > On Sep 30, 2006, at 3:34 AM, Atsushi Nemoto wrote: > > > The commit f06a96844a577c43249fce25809a4fae07407f46 broke mips. > > > > Signed-off-by: Atsushi Nemoto > > > > diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c > > index a624778..2f346d1 100644 > > --- a/arch/mips/mm/init.c > > +++ b/arch/mips/mm/init.c > > @@ -357,10 +357,10 @@ static int __init page_is_ram(unsigned l > > > > void __init paging_init(void) > > { > > - unsigned long zones_size[] = { 0, }; > > + unsigned long zones_size[MAX_NR_ZONES] = { 0, }; > > unsigned long max_dma, high, low; > > #ifndef CONFIG_FLATMEM > > - unsigned long zholes_size[] = { 0, }; > > + unsigned long zholes_size[MAX_NR_ZONES] = { 0, }; > > unsigned long i, j, pfn; > > #endif > > Nemoto~san, this was your patch earlier. > > void __init paging_init(void) > { > - unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0}; > + unsigned long zones_size[] = { [0 ... MAX_NR_ZONES - 1] = 0 }; > unsigned long max_dma, high, low; > +#ifdef CONFIG_SPARSEMEM > + unsigned long zholes_size[] = { [0 ... MAX_NR_ZONES - 1] = 0 }; > + unsigned long i, j, pfn; > +#endif Yes. This is correct. And then there was a conflict on this commit. > commit f06a96844a577c43249fce25809a4fae07407f46 > Author: Christoph Lameter > Date: Mon Sep 25 23:31:10 2006 -0700 > [PATCH] reduce MAX_NR_ZONES: fix MAX_NR_ZONES array initializations Perhaps his original patch was: - unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0}; + unsigned long zones_size[MAX_NR_ZONES] = {0, }; This conflicted with my change. Unfortunately the conflict was resolved in wrong way, thus now we have this line: unsigned long zones_size[] = { 0, }; This time my patch is trying to get the original target. --- Atsushi Nemoto From anemo@mba.ocn.ne.jp Sun Oct 1 15:50:47 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Oct 2006 15:50:49 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:23259 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20037863AbWJAOur (ORCPT ); Sun, 1 Oct 2006 15:50:47 +0100 Received: from localhost (p3194-ipad03funabasi.chiba.ocn.ne.jp [219.160.83.194]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id DE5669C55; Sun, 1 Oct 2006 23:50:43 +0900 (JST) Date: Sun, 01 Oct 2006 23:52:54 +0900 (JST) Message-Id: <20061001.235254.126142488.anemo@mba.ocn.ne.jp> To: girishvg@gmail.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: PATCH] cleanup hardcoding __pa/__va macros etc. (take-5) From: Atsushi Nemoto In-Reply-To: <8D501155-BC7A-471A-9374-9EB8D48BE307@gmail.com> References: <20060930.025956.108739154.anemo@mba.ocn.ne.jp> <8D501155-BC7A-471A-9374-9EB8D48BE307@gmail.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12755 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sat, 30 Sep 2006 03:33:01 +0900, girish wrote: > > Looks good to me, except for page.h part. > > I agree, but as of now, I do not have any better solution. If & when > I will implement kernel page table for memory above 2000_0000, I plan > to give it a through mapping. That is to say, 4000_0000 physical > mapped to 4000_0000 virtual. In that case the page.h __pa/__va macros > stand a chance (^_^;) No. 4000_0000 physical is never mapped to 4000_0000 virtual. The low 2GB of virtual address space are used for user mapping. > If somebody has already done kernel page table implementation, could > you please pass on the relevant patch? Thanks. If you have a 64-bit CPU, you can use a 64-bit kernel which gives you large XKPHYS area. If not, and your CPU does not have D-cache aliasing, you can use CONFIG_HIGHMEM which are using kernel page table already. Otherwise you are out of luck for now unfortunately. Anyway, you do not have to change __pa() and __va(). --- Atsushi Nemoto From girishvg@gmail.com Sun Oct 1 15:56:46 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Oct 2006 15:56:48 +0100 (BST) Received: from py-out-1112.google.com ([64.233.166.176]:25666 "EHLO py-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S20037872AbWJAO4q (ORCPT ); Sun, 1 Oct 2006 15:56:46 +0100 Received: by py-out-1112.google.com with SMTP id i49so632812pyi for ; Sun, 01 Oct 2006 07:56:45 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:in-reply-to:references:mime-version:content-type:message-id:cc:content-transfer-encoding:from:subject:date:to:x-mailer; b=KdZkbVNHeCgPvv5DbAl32/JtnHYuOYATo8MVmZ4No6i1zjmmhJx7QG+PNprb6pwcUPsEBOsDs87+qagxqpn81Gn78tAWga0VVMyhQbaaqumdexuRtivwYCcl3n2AwAr0jlY13zLNSLcauLWFDF85Q8Vu0mIl/VHa+LRBLoKmjNo= Received: by 10.65.237.1 with SMTP id o1mr5673869qbr; Sun, 01 Oct 2006 07:56:45 -0700 (PDT) Received: from ?192.168.1.3? ( [61.125.212.22]) by mx.gmail.com with ESMTP id 38sm4599910nzf.2006.10.01.07.56.43; Sun, 01 Oct 2006 07:56:44 -0700 (PDT) In-Reply-To: <20061001.235254.126142488.anemo@mba.ocn.ne.jp> References: <20060930.025956.108739154.anemo@mba.ocn.ne.jp> <8D501155-BC7A-471A-9374-9EB8D48BE307@gmail.com> <20061001.235254.126142488.anemo@mba.ocn.ne.jp> Mime-Version: 1.0 (Apple Message framework v749) Content-Type: text/plain; charset=US-ASCII; delsp=yes; format=flowed Message-Id: <105ACD1A-F259-46BE-BB1C-CE4075AF9290@gmail.com> Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Transfer-Encoding: 7bit From: girish Subject: Re: PATCH] cleanup hardcoding __pa/__va macros etc. (take-5) Date: Sun, 1 Oct 2006 23:57:03 +0900 To: Atsushi Nemoto X-Mailer: Apple Mail (2.749) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12756 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: girishvg@gmail.com Precedence: bulk X-list: linux-mips On Oct 1, 2006, at 11:52 PM, Atsushi Nemoto wrote: > On Sat, 30 Sep 2006 03:33:01 +0900, girish wrote: >>> Looks good to me, except for page.h part. >> >> I agree, but as of now, I do not have any better solution. If & when >> I will implement kernel page table for memory above 2000_0000, I plan >> to give it a through mapping. That is to say, 4000_0000 physical >> mapped to 4000_0000 virtual. In that case the page.h __pa/__va macros >> stand a chance (^_^;) > > No. 4000_0000 physical is never mapped to 4000_0000 virtual. The low > 2GB of virtual address space are used for user mapping. Can't I provide Kernel mapping via swapper_pg_dir to 4000_0000? > >> If somebody has already done kernel page table implementation, could >> you please pass on the relevant patch? Thanks. > > If you have a 64-bit CPU, you can use a 64-bit kernel which gives you > large XKPHYS area. If not, and your CPU does not have D-cache > aliasing, you can use CONFIG_HIGHMEM which are using kernel page table > already. Otherwise you are out of luck for now unfortunately. We poor 32bit users! I have, to some extent, already incorporated highmem (1GB) through HIGHMEM + SPARSEMEM combination. > Anyway, you do not have to change __pa() and __va(). > > --- > Atsushi Nemoto From anemo@mba.ocn.ne.jp Sun Oct 1 16:07:00 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Oct 2006 16:07:02 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:53725 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20037887AbWJAPHA (ORCPT ); Sun, 1 Oct 2006 16:07:00 +0100 Received: from localhost (p3194-ipad03funabasi.chiba.ocn.ne.jp [219.160.83.194]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 1BC29A6E3; Mon, 2 Oct 2006 00:06:56 +0900 (JST) Date: Mon, 02 Oct 2006 00:09:07 +0900 (JST) Message-Id: <20061002.000907.130240123.anemo@mba.ocn.ne.jp> To: girishvg@gmail.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: PATCH] cleanup hardcoding __pa/__va macros etc. (take-5) From: Atsushi Nemoto In-Reply-To: <105ACD1A-F259-46BE-BB1C-CE4075AF9290@gmail.com> References: <8D501155-BC7A-471A-9374-9EB8D48BE307@gmail.com> <20061001.235254.126142488.anemo@mba.ocn.ne.jp> <105ACD1A-F259-46BE-BB1C-CE4075AF9290@gmail.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12757 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sun, 1 Oct 2006 23:57:03 +0900, girish wrote: > > No. 4000_0000 physical is never mapped to 4000_0000 virtual. The low > > 2GB of virtual address space are used for user mapping. > > Can't I provide Kernel mapping via swapper_pg_dir to 4000_0000? Yes. I do not think it is possible. > I have, to some extent, already incorporated highmem (1GB) through > HIGHMEM + SPARSEMEM combination. So using __pa() and __va() for HIGHMEM page is wrong. If there were such usages, please fix them instead. --- Atsushi Nemoto From receive4me@gmail.com Sun Oct 1 18:29:51 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Oct 2006 18:29:53 +0100 (BST) Received: from wx-out-0506.google.com ([66.249.82.238]:62341 "EHLO wx-out-0506.google.com") by ftp.linux-mips.org with ESMTP id S20038653AbWJAR3v (ORCPT ); Sun, 1 Oct 2006 18:29:51 +0100 Received: by wx-out-0506.google.com with SMTP id h30so1612313wxd for ; Sun, 01 Oct 2006 10:29:50 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type; b=HdH+jmK7b9bbe7VfRh51OCmgmfpUpZGBxwChATbFbN8/n8ukVhVRHFlqH/0XU9V2TQye7+z+ZxQAe4AGEH5RCOFNTqRGLMfZZ9oqbb6ObkjnGBbTRJ5WXbjc6uxQXENPTX3BF2ajHMkBHBZ8RbiBmq0SKR1kn+cCmsWzPx/EDRk= Received: by 10.90.72.10 with SMTP id u10mr2496533aga; Sun, 01 Oct 2006 10:29:49 -0700 (PDT) Received: by 10.90.31.10 with HTTP; Sun, 1 Oct 2006 10:29:49 -0700 (PDT) Message-ID: <5ee285ba0610011029y13932410ueb27669000086a65@mail.gmail.com> Date: Mon, 2 Oct 2006 01:29:49 +0800 From: "David Lee" To: linux-mips@linux-mips.org Subject: depmod: Segmentation Fault MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_32989_26988842.1159723789504" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12758 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: receive4me@gmail.com Precedence: bulk X-list: linux-mips ------=_Part_32989_26988842.1159723789504 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi, I downloaded modutils-2.4.27 and compiled it with no error on my mipsel linux-2.4.30. lsmod works fine. However, running depmod -v shown the following errors: # ./depmod -v xftw starting at /lib/modules/boot lstat on /lib/modules/boot failed xftw starting at /lib/modules/2.4.30 xftw_readdir /lib/modules/2.4.30 pruned build type 2 /lib/modules/2.4.30/kernel xftw_readdir /lib/modules/2.4.30/kernel user function /lib/modules/2.4.30/kernel type 2 /lib/modules/2.4.30/kernel/crypto xftw_readdir /lib/modules/2.4.30/kernel/crypto user function /lib/modules/2.4.30/kernel/crypto user function /lib/modules/2.4.30/kernel/crypto/aes.o user function /lib/modules/2.4.30/kernel/crypto/arc4.o user function /lib/modules/2.4.30/kernel/crypto/deflate.o ................. ................. xftw starting at /lib/modules/2.4 lstat on /lib/modules/2.4 failed xftw starting at /lib/modules/kernel lstat on /lib/modules/kernel failed xftw starting at /lib/modules/fs lstat on /lib/modules/fs failed xftw starting at /lib/modules/net lstat on /lib/modules/net failed xftw starting at /lib/modules/scsi lstat on /lib/modules/scsi failed xftw starting at /lib/modules/block lstat on /lib/modules/block failed xftw starting at /lib/modules/cdrom lstat on /lib/modules/cdrom failed xftw starting at /lib/modules/ipv4 lstat on /lib/modules/ipv4 failed xftw starting at /lib/modules/ipv6 lstat on /lib/modules/ipv6 failed xftw starting at /lib/modules/sound lstat on /lib/modules/sound failed xftw starting at /lib/modules/fc4 lstat on /lib/modules/fc4 failed xftw starting at /lib/modules/video lstat on /lib/modules/video failed xftw starting at /lib/modules/misc lstat on /lib/modules/misc failed xftw starting at /lib/modules/pcmcia lstat on /lib/modules/pcmcia failed xftw starting at /lib/modules/atm lstat on /lib/modules/atm failed xftw starting at /lib/modules/usb lstat on /lib/modules/usb failed xftw starting at /lib/modules/ide lstat on /lib/modules/ide failed xftw starting at /lib/modules/ieee1394 lstat on /lib/modules/ieee1394 failed xftw starting at /lib/modules/mtd lstat on /lib/modules/mtd failed xftw starting at /lib/modules/boot lstat on /lib/modules/boot failed Segmentation fault Kernel was compiled with kmod. I could load modules by busybox. Please help. Thanks. David ------=_Part_32989_26988842.1159723789504 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline
Hi,
 
I downloaded modutils-2.4.27 and compiled it with no error on my mipsel linux-2.4.30. lsmod works fine. However, running depmod -v shown the following errors:
 
# ./depmod -v
xftw starting at /lib/modules/boot lstat on /lib/modules/boot failed
xftw starting at /lib/modules/2.4.30
xftw_readdir /lib/modules/2.4.30
pruned build
type 2 /lib/modules/2.4.30/kernel
xftw_readdir /lib/modules/2.4.30/kernel
user function /lib/modules/2.4.30/kernel
type 2 /lib/modules/2.4.30/kernel/crypto
xftw_readdir /lib/modules/2.4.30/kernel/crypto
user function /lib/modules/2.4.30/kernel/crypto
user function /lib/modules/2.4.30/kernel/crypto/aes.o
user function /lib/modules/2.4.30/kernel/crypto/arc4.o
user function /lib/modules/2.4.30/kernel/crypto/deflate.o
.................
.................
xftw starting at /lib/modules/2.4 lstat on /lib/modules/2.4 failed
xftw starting at /lib/modules/kernel lstat on /lib/modules/kernel failed
xftw starting at /lib/modules/fs lstat on /lib/modules/fs failed
xftw starting at /lib/modules/net lstat on /lib/modules/net failed
xftw starting at /lib/modules/scsi lstat on /lib/modules/scsi failed
xftw starting at /lib/modules/block lstat on /lib/modules/block failed
xftw starting at /lib/modules/cdrom lstat on /lib/modules/cdrom failed
xftw starting at /lib/modules/ipv4 lstat on /lib/modules/ipv4 failed
xftw starting at /lib/modules/ipv6 lstat on /lib/modules/ipv6 failed
xftw starting at /lib/modules/sound lstat on /lib/modules/sound failed
xftw starting at /lib/modules/fc4 lstat on /lib/modules/fc4 failed
xftw starting at /lib/modules/video lstat on /lib/modules/video failed
xftw starting at /lib/modules/misc lstat on /lib/modules/misc failed
xftw starting at /lib/modules/pcmcia lstat on /lib/modules/pcmcia failed
xftw starting at /lib/modules/atm lstat on /lib/modules/atm failed
xftw starting at /lib/modules/usb lstat on /lib/modules/usb failed
xftw starting at /lib/modules/ide lstat on /lib/modules/ide failed
xftw starting at /lib/modules/ieee1394 lstat on /lib/modules/ieee1394 failed
xftw starting at /lib/modules/mtd lstat on /lib/modules/mtd failed
xftw starting at /lib/modules/boot lstat on /lib/modules/boot failed
Segmentation fault
 
Kernel was compiled with kmod. I could load modules by busybox.
 
Please help. Thanks.
 
David
 
------=_Part_32989_26988842.1159723789504-- From ralf@linux-mips.org Sun Oct 1 20:43:22 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Oct 2006 20:43:51 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:37801 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20038678AbWJATnW (ORCPT ); Sun, 1 Oct 2006 20:43:22 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k91JiCnI006367; Sun, 1 Oct 2006 20:44:13 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k91Ji9Tm006366; Sun, 1 Oct 2006 20:44:09 +0100 Date: Sun, 1 Oct 2006 20:44:09 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH 1/3] add UART IRQ number for EV64120 Message-ID: <20061001194409.GA6347@linux-mips.org> References: <20061001193528.003d01d8.yoichi_yuasa@tripeaks.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20061001193528.003d01d8.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12759 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips All three applied. That said I'm wondering if anybody is still using the EV64120 or if it would make another candidate for deletion. Ralf From pak.woon@nec.com.au Mon Oct 2 02:39:27 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Oct 2006 02:39:29 +0100 (BST) Received: from ns2.nec.com.au ([147.76.180.2]:22725 "EHLO ns2.nec.com.au") by ftp.linux-mips.org with ESMTP id S20040343AbWJBBj1 (ORCPT ); Mon, 2 Oct 2006 02:39:27 +0100 Received: from smtp1.nec.com.au (unknown [172.31.8.18]) by ns2.nec.com.au (Postfix) with ESMTP id B979C3B6A7 for ; Mon, 2 Oct 2006 11:39:16 +1000 (EST) Received: from [147.76.208.162] ([147.76.208.162]) by tns.neca.nec.com.au (8.12.8/8.12.8) with ESMTP id k921ipZl001952; Mon, 2 Oct 2006 11:44:52 +1000 Message-ID: <45206D4C.1040005@nec.com.au> Date: Mon, 02 Oct 2006 11:37:16 +1000 From: Pak Woon User-Agent: Mozilla Thunderbird 1.0.2 (Windows/20050317) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Andrew Sharp Cc: linux-mips@linux-mips.org Subject: Re: Introduction and problems cloning repository References: <451C7CE7.8040909@nec.com.au> <20060929094944.GA10597@linux-mips.org> <20060929105241.423a1ade@ripper> In-Reply-To: <20060929105241.423a1ade@ripper> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12760 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pak.woon@nec.com.au Precedence: bulk X-list: linux-mips >>>First time poster to this mailing list so if I am not following the >>>correct protocol please let me know. >>> >>>Introduction. I am a firmware developer working for NEC Australia. >>>We are currently developing a MIPS SOC device made by Wintegra. >>> >>>I am trying to clone the linux-malta.git repository using the >>>command "git clone http://ftp.linux-mips.org/pub/scm/linux-malta.git >>> >>>./linux-malta.git" but I receieve an "error: Can't lock ref". I have >>>to use http because I am sure port 9418 is blocked by the sysadmin >> >>An good old access permission problem on the web server but I won't >>have time to sort it out now. > > > I had this same problem. Turns out that for the http method of git, you > have to use the name 'www.linux-mips.org'. So it would be > > git clone http://www.linux-mips.org/pub/scm/linux-malta.git linux-malta.git > > >> cvs -d :pserver:anonymous@git.linux-mips.org:/pub/scm/linux.git co >> -d linux-malta -P >> >>Where is one of linux-2.0, linux-2.2, linux-2.4, >>MaltaRef_2_4, MaltaRef_2_6 and master - if your firewall allows port >>2401 that is ... >> >>But why are you still using the linux-malta repository? Since ~ 5 >>months it is no longer being updated and has effectivly been replaced >>with linux.git repository. Of this repository there are also >>snapshots of all tagged versions available. > > > Good point. Probably because on http://www.linux-mips.org/wiki/Getting_the_kernel it mentions MIPS technologies is maintaining "a stable and tested kernel with focus on hardware support for ... the Malta Eval board" and I thought it would be quicker to develop with. Are they no longer doing the maintainace? Regards, Pak From yoichi_yuasa@tripeaks.co.jp Mon Oct 2 03:59:34 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Oct 2006 03:59:38 +0100 (BST) Received: from mo30.po.2iij.net ([210.128.50.53]:14909 "EHLO mo30.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20040610AbWJBC7e (ORCPT ); Mon, 2 Oct 2006 03:59:34 +0100 Received: by mo.po.2iij.net (mo30) id k922xTRM078637; Mon, 2 Oct 2006 11:59:30 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox32) id k922xQxK056549 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 2 Oct 2006 11:59:26 +0900 (JST) Date: Mon, 2 Oct 2006 11:59:26 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips@linux-mips.org Subject: Re: [PATCH 1/3] add UART IRQ number for EV64120 Message-Id: <20061002115926.3178aa52.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20061001194409.GA6347@linux-mips.org> References: <20061001193528.003d01d8.yoichi_yuasa@tripeaks.co.jp> <20061001194409.GA6347@linux-mips.org> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12761 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, On Sun, 1 Oct 2006 20:44:09 +0100 Ralf Baechle wrote: > All three applied. Thanks. > That said I'm wondering if anybody is still using the EV64120 or if it > would make another candidate for deletion. I agree, if you add EV64120 to the deletion list. Yoichi From manoje@broadcom.com Mon Oct 2 04:19:54 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Oct 2006 04:19:56 +0100 (BST) Received: from mms1.broadcom.com ([216.31.210.17]:50951 "EHLO mms1.broadcom.com") by ftp.linux-mips.org with ESMTP id S20040639AbWJBDTy convert rfc822-to-8bit (ORCPT ); Mon, 2 Oct 2006 04:19:54 +0100 Received: from 10.10.64.154 by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.2.2)); Sun, 01 Oct 2006 20:19:38 -0700 X-Server-Uuid: 8BFFF8BB-6D19-4612-8F54-AA4CE9D0539E Received: by mail-irva-10.broadcom.com (Postfix, from userid 47) id 44F092AF; Sun, 1 Oct 2006 20:19:38 -0700 (PDT) Received: from mail-irva-8.broadcom.com (mail-irva-8 [10.10.64.221]) by mail-irva-10.broadcom.com (Postfix) with ESMTP id 197BA2AE; Sun, 1 Oct 2006 20:19:38 -0700 (PDT) Received: from mail-sj1-12.sj.broadcom.com (mail-sj1-12.sj.broadcom.com [10.16.128.215]) by mail-irva-8.broadcom.com (MOS 3.7.5a-GA) with ESMTP id EGI25095; Sun, 1 Oct 2006 20:19:37 -0700 (PDT) Received: from NT-SJCA-0751.brcm.ad.broadcom.com (nt-sjca-0751 [10.16.192.221]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id A09DF20501; Sun, 1 Oct 2006 20:19:37 -0700 (PDT) Received: from NT-SJCA-0752.brcm.ad.broadcom.com ([10.16.192.222]) by NT-SJCA-0751.brcm.ad.broadcom.com with Microsoft SMTPSVC(6.0.3790.1830); Sun, 1 Oct 2006 20:19:37 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Subject: RE: [MIPS] SB1: Build fix: delete initialization of flush_icache_page pointer. Date: Sun, 1 Oct 2006 20:17:35 -0700 Message-ID: <710F16C36810444CA2F5821E5EAB7F23BB0E@NT-SJCA-0752.brcm.ad.broadcom.com> Thread-Topic: [MIPS] SB1: Build fix: delete initialization of flush_icache_page pointer. Thread-Index: AcbitmP3HSNOWKknTka25vlIjnmtMgDGupR2 References: <20060927.235804.95064004.anemo@mba.ocn.ne.jp> <710F16C36810444CA2F5821E5EAB7F230A0E91@NT-SJCA-0752.brcm.ad.broadcom.com> <20060928.132712.47915433.nemoto@toshiba-tops.co.jp> From: "Manoj Ekbote" To: "Atsushi Nemoto" cc: linux-mips@linux-mips.org, ralf@linux-mips.org, "Mark E Mason" X-OriginalArrivalTime: 02 Oct 2006 03:19:37.0576 (UTC) FILETIME=[9749CE80:01C6E5D1] X-TMWD-Spam-Summary: TS=20061002031940; SEV=2.0.2; DFV=A2006100110; IFV=2.0.4,4.0-8; RPD=4.00.0004; ENG=IBF; RPDID=303030312E30413031303230352E34353230383532362E303032392D412D; CAT=NONE; CON=NONE X-MMS-Spam-Filter-ID: A2006100110_4.00.0004_4.0-8 X-WSS-ID: 693E5AC009W533065-01-01 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12762 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manoje@broadcom.com Precedence: bulk X-list: linux-mips -----Original Message----- From: Atsushi Nemoto [mailto:anemo@mba.ocn.ne.jp] Sent: Wed 9/27/2006 9:27 PM To: Manoj Ekbote Cc: linux-mips@linux-mips.org; ralf@linux-mips.org; Mark E Mason Subject: Re: [MIPS] SB1: Build fix: delete initialization of flush_icache_page pointer. On Wed, 27 Sep 2006 19:17:16 -0700, "Manoj Ekbote" wrote: > I added a line that initializes the flush_icache_page pointer in > sb1_cache_init. > The below method worked. The SMP kernel boots fine now. Removing parts > of local_sb1_flush_icache_page doesn't help. It looks like > flush_icache_page in mm/memory.c:do_no_page is needed. Removing it will > fail the boot process. Thank you for testing. Now I'm wondering why do_no_page() works on SMP. if (pte_none(*page_table)) { flush_icache_page(vma, new_page); entry = mk_pte(new_page, vma->vm_page_prot); if (write_access) entry = maybe_mkwrite(pte_mkdirty(entry), vma); set_pte_at(mm, address, page_table, entry); ... } else { /* One of our sibling threads was faster, back out. */ page_cache_release(new_page); goto unlock; } /* no need to invalidate: a not-present page shouldn't be cached */ update_mmu_cache(vma, address, entry); Other CPU might be able to load new pte value just after set_ste_at(), but dcache is not flushed until update_mmu_cache(). Maybe I missed something... It looks like the page with instructions has to be invalidated.I did a flush_cache_page in __update_cache.That seems to help too. > I am wondering if people have booted the latest tree on non-Broadcom > boards...curious to know if the removal of flush_icache_page has > affected them. Yes, Ralf and Thiemo said even some SB1 boards can work fine without flush_icache_page. --- Atsushi Nemoto From macro@linux-mips.org Mon Oct 2 12:55:12 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Oct 2006 12:55:18 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:54544 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038745AbWJBLzM (ORCPT ); Mon, 2 Oct 2006 12:55:12 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id B3346F5EC1; Mon, 2 Oct 2006 13:55:06 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OObclvLcQDeV; Mon, 2 Oct 2006 13:55:06 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 579DCE1CB2; Mon, 2 Oct 2006 13:55:06 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k92BtCt3027483; Mon, 2 Oct 2006 13:55:12 +0200 Date: Mon, 2 Oct 2006 12:55:09 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: linux-mips@linux-mips.org Subject: [patch] 2.6.18: TRDY timeout tweaks for Broadcom SiByte systems Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1965/Mon Oct 2 11:52:42 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12763 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Hello, It was obesrved that at least one older PCI card predating the requirement for the TRDY signal to respond within 16 clock ticks actually does not meet this rule nor even the power-on defaults of the PCI bridges found in development systems built around the Broadcom SiByte SOCs. Here is a patch that bumps up the timeout to the highest finite value supported by these chips, which is 255 clock ticks. The bridges affected are the SiByte SOC itself and the SP1011. This change does not effectively affect systems only having PCI option cards installed that meet the TRDY requirement of the current PCI spec. The rule was introduced with PCI 2.1, so any older card may make the system affected. If this is the case, performance of the system will suffer in return for the card working at all. If this is a concern, then the solution is not to use such cards. Please apply the change. Maciej Signed-off-by: Maciej W. Rozycki patch-mips-2.6.15-20060124-sb1250-retry-3 diff -up --recursive --new-file linux-mips-2.6.15-20060124.macro/arch/mips/pci/fixup-sb1250.c linux-mips-2.6.15-20060124/arch/mips/pci/fixup-sb1250.c --- linux-mips-2.6.15-20060124.macro/arch/mips/pci/fixup-sb1250.c 2004-12-18 22:28:20.000000000 +0000 +++ linux-mips-2.6.15-20060124/arch/mips/pci/fixup-sb1250.c 2006-09-20 01:36:46.000000000 +0000 @@ -1,7 +1,7 @@ /* * arch/mips/pci/fixup-sb1250.c * - * Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2004, 2006 MIPS Technologies, Inc. All rights reserved. * Author: Maciej W. Rozycki * * This program is free software; you can redistribute it and/or @@ -14,6 +14,17 @@ #include /* + * Set the the BCM1250, etc. PCI host bridge's TRDY timeout + * to the finite max. + */ +static void __init quirk_sb1250_pci(struct pci_dev *dev) +{ + pci_write_config_byte(dev, 0x40, 0xff); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI, + quirk_sb1250_pci); + +/* * The BCM1250, etc. PCI/HT bridge reports as a host bridge. */ static void __init quirk_sb1250_ht(struct pci_dev *dev) @@ -22,3 +33,13 @@ static void __init quirk_sb1250_ht(struc } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT, quirk_sb1250_ht); + +/* + * Set the the SP1011 HT/PCI bridge's TRDY timeout to the finite max. + */ +static void __init quirk_sp1011(struct pci_dev *dev) +{ + pci_write_config_byte(dev, 0x64, 0xff); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIPACKETS, PCI_DEVICE_ID_SP1011, + quirk_sp1011); diff -up --recursive --new-file linux-mips-2.6.15-20060124.macro/include/linux/pci_ids.h linux-mips-2.6.15-20060124/include/linux/pci_ids.h --- linux-mips-2.6.15-20060124.macro/include/linux/pci_ids.h 2006-01-12 06:00:39.000000000 +0000 +++ linux-mips-2.6.15-20060124/include/linux/pci_ids.h 2006-09-20 00:44:52.000000000 +0000 @@ -1834,6 +1834,8 @@ #define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 #define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 +#define PCI_VENDOR_ID_SIPACKETS 0x14d9 +#define PCI_DEVICE_ID_SP1011 0x0010 #define PCI_VENDOR_ID_AFAVLAB 0x14db #define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 @@ -1933,6 +1935,7 @@ #define PCI_DEVICE_ID_FARSITE_TE1C 0x1612 #define PCI_VENDOR_ID_SIBYTE 0x166d +#define PCI_DEVICE_ID_BCM1250_PCI 0x0001 #define PCI_DEVICE_ID_BCM1250_HT 0x0002 #define PCI_VENDOR_ID_NETCELL 0x169c From yoichi_yuasa@tripeaks.co.jp Mon Oct 2 15:20:05 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Oct 2006 15:20:11 +0100 (BST) Received: from mo31.po.2iij.net ([210.128.50.54]:54791 "EHLO mo31.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20038771AbWJBOUF (ORCPT ); Mon, 2 Oct 2006 15:20:05 +0100 Received: by mo.po.2iij.net (mo31) id k92EK1Bq039179; Mon, 2 Oct 2006 23:20:01 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox33) id k92EJt8t030391 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 2 Oct 2006 23:19:55 +0900 (JST) Date: Mon, 2 Oct 2006 23:14:32 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH] remove Momentum / PMC-Sierra Jaguar ATX evaluation board Message-Id: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12764 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has removed Momentum / PMC-Sierra Jaguar ATX evaluation board support. It was scheduled to be removed after 2.6.18 released. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/Documentation/feature-removal-schedule.txt mips/Documentation/feature-removal-schedule.txt --- mips-orig/Documentation/feature-removal-schedule.txt 2006-10-02 22:34:28.501152500 +0900 +++ mips/Documentation/feature-removal-schedule.txt 2006-10-02 22:32:30.225760750 +0900 @@ -220,16 +220,6 @@ Who: Nick Piggin --------------------------- -What: Support for the Momentum / PMC-Sierra Jaguar ATX evaluation board -When: September 2006 -Why: Does no longer build since quite some time, and was never popular, - due to the platform being replaced by successor models. Apparently - no user base left. It also is one of the last users of - WANT_PAGE_VIRTUAL. -Who: Ralf Baechle - ---------------------------- - What: Support for the Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G When: September 2006 Why: Some do no longer build and apparently there is no user base left diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Kconfig mips/arch/mips/Kconfig --- mips-orig/arch/mips/Kconfig 2006-10-02 22:34:28.501152500 +0900 +++ mips/arch/mips/Kconfig 2006-10-02 22:32:30.229761000 +0900 @@ -374,26 +374,6 @@ config MIPS_SIM This option enables support for MIPS Technologies MIPSsim software emulator. -config MOMENCO_JAGUAR_ATX - bool "Momentum Jaguar board" - select BOOT_ELF32 - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select IRQ_CPU_RM7K - select IRQ_MV64340 - select LIMITED_DMA - select PCI_MARVELL - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_RM9000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer . - config MOMENCO_OCELOT bool "Momentum Ocelot board" select DMA_NONCOHERENT @@ -804,7 +784,6 @@ source "arch/mips/gt64120/ev64120/Kconfi source "arch/mips/jazz/Kconfig" source "arch/mips/ite-boards/Kconfig" source "arch/mips/lasat/Kconfig" -source "arch/mips/momentum/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" @@ -877,11 +856,6 @@ config GENERIC_ISA_DMA config I8259 bool -config LIMITED_DMA - bool - select HIGHMEM - select SYS_SUPPORTS_HIGHMEM - config MIPS_BONITO64 bool diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Makefile mips/arch/mips/Makefile --- mips-orig/arch/mips/Makefile 2006-10-02 22:34:28.501152500 +0900 +++ mips/arch/mips/Makefile 2006-10-02 22:32:30.229761000 +0900 @@ -390,17 +390,6 @@ cflags-$(CONFIG_BASLER_EXCITE) += -Iincl load-$(CONFIG_BASLER_EXCITE) += 0x80100000 # -# Momentum Jaguar ATX -# -core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/ -cflags-$(CONFIG_MOMENCO_JAGUAR_ATX) += -Iinclude/asm-mips/mach-ja -#ifdef CONFIG_JAGUAR_DMALOW -#load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff88000000 -#else -load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff80100000 -#endif - -# # NEC DDB # core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/jaguar-atx_defconfig mips/arch/mips/configs/jaguar-atx_defconfig --- mips-orig/arch/mips/configs/jaguar-atx_defconfig 2006-10-02 22:34:28.501152500 +0900 +++ mips/arch/mips/configs/jaguar-atx_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,839 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:12 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MOMENCO_JAGUAR_ATX=y -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_JAGUAR_DMALOW=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_LIMITED_DMA=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_CPU_RM7K=y -CONFIG_IRQ_MV64340=y -CONFIG_PCI_MARVELL=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_BOOT_ELF32=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -CONFIG_CPU_RM9000=y -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM9000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_HIGHMEM=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -# CONFIG_PACKET is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -CONFIG_IPV6=m -CONFIG_IPV6_PRIVACY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_IPV6_TUNNEL=m -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=m - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_LXT_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_SMSC_PHY=m - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -CONFIG_EEPRO100=y -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_MV643XX_ETH=y -CONFIG_MV643XX_ETH_0=y -CONFIG_MV643XX_ETH_1=y -CONFIG_MV643XX_ETH_2=y - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=m - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_HFSPLUS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=m -CONFIG_CRC32=m -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/mm/highmem.c mips/arch/mips/mm/highmem.c --- mips-orig/arch/mips/mm/highmem.c 2006-10-02 22:34:28.501152500 +0900 +++ mips/arch/mips/mm/highmem.c 2006-10-02 22:32:30.233761250 +0900 @@ -82,7 +82,6 @@ void __kunmap_atomic(void *kvaddr, enum preempt_check_resched(); } -#ifndef CONFIG_LIMITED_DMA /* * This is the same as kmap_atomic() but can map memory that doesn't * have a struct page associated with it. @@ -101,7 +100,6 @@ void *kmap_atomic_pfn(unsigned long pfn, return (void*) vaddr; } -#endif /* CONFIG_LIMITED_DMA */ struct page *__kmap_atomic_to_page(void *ptr) { diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/mm/init.c mips/arch/mips/mm/init.c --- mips-orig/arch/mips/mm/init.c 2006-10-02 22:34:28.501152500 +0900 +++ mips/arch/mips/mm/init.c 2006-10-02 22:32:30.233761250 +0900 @@ -448,9 +448,6 @@ void __init mem_init(void) continue; } ClearPageReserved(page); -#ifdef CONFIG_LIMITED_DMA - set_page_address(page, lowmem_page_address(page)); -#endif init_page_count(page); __free_page(page); totalhigh_pages++; diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/Kconfig mips/arch/mips/momentum/Kconfig --- mips-orig/arch/mips/momentum/Kconfig 2006-10-02 22:34:28.501152500 +0900 +++ mips/arch/mips/momentum/Kconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,6 +0,0 @@ -config JAGUAR_DMALOW - bool "Low DMA Mode" - depends on MOMENCO_JAGUAR_ATX - help - Select to Y if jump JP5 is set on your board, N otherwise. Normally - the jumper is set, so if you feel unsafe, just say Y. diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/Makefile mips/arch/mips/momentum/jaguar_atx/Makefile --- mips-orig/arch/mips/momentum/jaguar_atx/Makefile 2006-10-02 22:34:28.505152750 +0900 +++ mips/arch/mips/momentum/jaguar_atx/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,12 +0,0 @@ -# -# Makefile for Momentum Computer's Jaguar-ATX board. -# -# Note! Dependencies are done automagically by 'make dep', which also -# removes any old dependencies. DON'T put your own dependencies here -# unless it's something special (ie not a .c file). -# - -obj-y += irq.o prom.o reset.o setup.o - -obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o -obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/dbg_io.c mips/arch/mips/momentum/jaguar_atx/dbg_io.c --- mips-orig/arch/mips/momentum/jaguar_atx/dbg_io.c 2006-10-02 22:34:28.505152750 +0900 +++ mips/arch/mips/momentum/jaguar_atx/dbg_io.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,125 +0,0 @@ - -#if defined(CONFIG_REMOTE_DEBUG) - -#include /* For the serial port location and base baud */ - -/* --- CONFIG --- */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE OCELOT_SERIAL1_BASE -#define MAX_BAUD OCELOT_BASE_BAUD - -/* === END OF CONFIG === */ - -#define REG_OFFSET 4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/irq.c mips/arch/mips/momentum/jaguar_atx/irq.c --- mips-orig/arch/mips/momentum/jaguar_atx/irq.c 2006-10-02 22:34:28.505152750 +0900 +++ mips/arch/mips/momentum/jaguar_atx/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,94 +0,0 @@ -/* - * Copyright (C) 2002 Momentum Computer, Inc. - * Author: Matthew Dharm, mdharm@momenco.com - * - * Based on work by: - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP0) - do_IRQ(0, regs); - else if (pending & STATUSF_IP1) - do_IRQ(1, regs); - else if (pending & STATUSF_IP2) - do_IRQ(2, regs); - else if (pending & STATUSF_IP3) - do_IRQ(3, regs); - else if (pending & STATUSF_IP4) - do_IRQ(4, regs); - else if (pending & STATUSF_IP5) - do_IRQ(5, regs); - else if (pending & STATUSF_IP6) - do_IRQ(6, regs); - else if (pending & STATUSF_IP7) - ll_timer_interrupt(7, regs); - else { - /* - * Now look at the extended interrupts - */ - pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; - if (pending & STATUSF_IP8) - ll_mv64340_irq(regs); - } -} - -static struct irqaction cascade_mv64340 = { - no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL -}; - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM); - - mips_cpu_irq_init(0); - rm7k_cpu_irq_init(8); - - /* set up the cascading interrupts */ - setup_irq(8, &cascade_mv64340); - - mv64340_irq_init(16); - - set_c0_status(ST0_IM); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/ja-console.c mips/arch/mips/momentum/jaguar_atx/ja-console.c --- mips-orig/arch/mips/momentum/jaguar_atx/ja-console.c 2006-10-02 22:34:28.505152750 +0900 +++ mips/arch/mips/momentum/jaguar_atx/ja-console.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,106 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001, 2002, 2004 Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/* SUPERIO uart register map */ -struct ja_uartregs { - union { - volatile u8 pad0[3]; - volatile u8 rbr; /* read only, DLAB == 0 */ - volatile u8 pad1[3]; - volatile u8 thr; /* write only, DLAB == 0 */ - volatile u8 pad2[3]; - volatile u8 dll; /* DLAB == 1 */ - } u1; - union { - volatile u8 pad0[3]; - volatile u8 ier; /* DLAB == 0 */ - volatile u8 pad1[3]; - volatile u8 dlm; /* DLAB == 1 */ - } u2; - union { - volatile u8 pad0[3]; - volatile u8 iir; /* read only */ - volatile u8 pad1[3]; - volatile u8 fcr; /* write only */ - } u3; - volatile u8 pad0[3]; - volatile u8 iu_lcr; - volatile u8 pad1[3]; - volatile u8 iu_mcr; - volatile u8 pad2[3]; - volatile u8 iu_lsr; - volatile u8 pad3[3]; - volatile u8 iu_msr; - volatile u8 pad4[3]; - volatile u8 iu_scr; -} ja_uregs_t; - -#define iu_rbr u1.rbr -#define iu_thr u1.thr -#define iu_dll u1.dll -#define iu_ier u2.ier -#define iu_dlm u2.dlm -#define iu_iir u3.iir -#define iu_fcr u3.fcr - -extern unsigned long uart_base; - -static inline struct ja_uartregs *console_uart(void) -{ - return (struct ja_uartregs *) (uart_base + 0x23UL); -} - -void prom_putchar(char c) -{ - struct ja_uartregs *uart = console_uart(); - - while ((uart->iu_lsr & 0x20) == 0); - uart->iu_thr = c; -} - -char __init prom_getchar(void) -{ - return 0; -} - -static void inline ja_console_probe(void) -{ - struct uart_port up; - - /* - * Register to interrupt zero because we share the interrupt with - * the serial driver which we don't properly support yet. - */ - memset(&up, 0, sizeof(up)); - up.membase = (unsigned char *) uart_base + 0x23UL; - up.irq = JAGUAR_ATX_SERIAL1_IRQ; - up.uartclk = JAGUAR_ATX_UART_CLK; - up.regshift = 2; - up.iotype = UPIO_MEM; - up.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - up.line = 0; - - if (early_serial_setup(&up)) - printk(KERN_ERR "Early serial init of port 0 failed\n"); -} - -__init void ja_setup_console(void) -{ - ja_console_probe(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h mips/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h --- mips-orig/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h 2006-10-02 22:34:28.505152750 +0900 +++ mips/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,52 +0,0 @@ -/* - * Jaguar-ATX Board Register Definitions - * - * (C) 2002 Momentum Computer Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __JAGUAR_ATX_FPGA_H__ -#define __JAGUAR_ATX_FPGA_H__ - -#define JAGUAR_ATX_REG_BOARDREV 0x0 -#define JAGUAR_ATX_REG_FPGA_REV 0x1 -#define JAGUAR_ATX_REG_FPGA_TYPE 0x2 -#define JAGUAR_ATX_REG_RESET_STATUS 0x3 -#define JAGUAR_ATX_REG_BOARD_STATUS 0x4 -#define JAGUAR_ATX_REG_RESERVED1 0x5 -#define JAGUAR_ATX_REG_SET 0x6 -#define JAGUAR_ATX_REG_CLR 0x7 -#define JAGUAR_ATX_REG_EEPROM_MODE 0x9 -#define JAGUAR_ATX_REG_RESERVED2 0xa -#define JAGUAR_ATX_REG_RESERVED3 0xb -#define JAGUAR_ATX_REG_RESERVED4 0xc -#define JAGUAR_ATX_REG_PHY_INTSTAT 0xd -#define JAGUAR_ATX_REG_RESERVED5 0xe -#define JAGUAR_ATX_REG_RESERVED6 0xf - -#define JAGUAR_ATX_CS0_ADDR 0xfc000000L - -extern unsigned long ja_fpga_base; - -#define JAGUAR_FPGA_WRITE(x,y) writeb(x, ja_fpga_base + JAGUAR_ATX_REG_##y) -#define JAGUAR_FPGA_READ(x) readb(ja_fpga_base + JAGUAR_ATX_REG_##x) - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/prom.c mips/arch/mips/momentum/jaguar_atx/prom.c --- mips-orig/arch/mips/momentum/jaguar_atx/prom.c 2006-10-02 22:34:28.505152750 +0900 +++ mips/arch/mips/momentum/jaguar_atx/prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,266 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Added changes for SMP - Manish Lachwani (lachwani@pmc-sierra.com) - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "jaguar_atx_fpga.h" - -extern void ja_setup_console(void); - -struct callvectors *debug_vectors; - -extern unsigned long cpu_clock; - -const char *get_system_type(void) -{ - return "Momentum Jaguar-ATX"; -} - -#ifdef CONFIG_MV643XX_ETH -extern unsigned char prom_mac_addr_base[6]; - -static void burn_clocks(void) -{ - int i; - - /* this loop should burn at least 1us -- this should be plenty */ - for (i = 0; i < 0x10000; i++) - ; -} - -static u8 exchange_bit(u8 val, u8 cs) -{ - /* place the data */ - JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE); - burn_clocks(); - - /* turn the clock on */ - JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE); - burn_clocks(); - - /* turn the clock off and read-strobe */ - JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - - /* return the data */ - return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); -} - -void get_mac(char dest[6]) -{ - u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int i,j; - - for (i = 0; i < 12; i++) - exchange_bit(read_opcode[i], 1); - - for (j = 0; j < 6; j++) { - dest[j] = 0; - for (i = 0; i < 8; i++) { - dest[j] <<= 1; - dest[j] |= exchange_bit(0, 1); - } - } - - /* turn off CS */ - exchange_bit(0,0); -} -#endif - -#ifdef CONFIG_64BIT - -unsigned long signext(unsigned long addr) -{ - addr &= 0xffffffff; - return (unsigned long)((int)addr); -} - -void *get_arg(unsigned long args, int arc) -{ - unsigned long ul; - unsigned char *puc, uc; - - args += (arc * 4); - ul = (unsigned long)signext(args); - puc = (unsigned char *)ul; - if (puc == 0) - return (void *)0; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - uc = *puc++; - l = (unsigned long)uc; - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 24); -#else - uc = *puc++; - ul = ((unsigned long)uc) << 24; - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= ((unsigned long)uc); -#endif - ul = signext(ul); - - return (void *)ul; -} - -char *arg64(unsigned long addrin, int arg_index) -{ - unsigned long args; - char *p; - - args = signext(addrin); - p = (char *)get_arg(args, arg_index); - - return p; -} -#endif /* CONFIG_64BIT */ - -/* PMON passes arguments in C main() style */ -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - int i; - -#ifdef CONFIG_SERIAL_8250_CONSOLE -// ja_setup_console(); /* The very first thing. */ -#endif - -#ifdef CONFIG_64BIT - char *ptr; - - printk("Mips64 Jaguar-ATX\n"); - /* save the PROM vectors for debugging use */ - debug_vectors = (struct callvectors *)signext((unsigned long)cv); - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - - for (i = 1; i < argc; i++) { - ptr = (char *)arg64((unsigned long)arg, i); - if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >= - sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ptr); - strcat(arcs_cmdline, " "); - } - - i = 0; - while (1) { - ptr = (char *)arg64((unsigned long)env, i); - if (! ptr) - break; - - if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(ptr + strlen("gtbase="), - NULL, 16); - - if ((marvell_base & 0xffffffff00000000) == 0) - marvell_base |= 0xffffffff00000000; - - printk("marvell_base set to 0x%016lx\n", marvell_base); - } - if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(ptr + strlen("cpuclock="), - NULL, 10); - printk("cpu_clock set to %d\n", cpu_clock); - } - i++; - } - printk("arcs_cmdline: %s\n", arcs_cmdline); - -#else /* CONFIG_64BIT */ - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - while (*env) { - if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - } - if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(*env + strlen("cpuclock="), - NULL, 10); - } - env++; - } -#endif /* CONFIG_64BIT */ - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_JAGUAR_ATX; - -#ifdef CONFIG_MV643XX_ETH - /* get the base MAC address for on-board ethernet ports */ - get_mac(prom_mac_addr_base); -#endif -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} - -void __init prom_fixup_mem_map(unsigned long start, unsigned long end) -{ -} - -int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp) -{ - /* Clear the semaphore */ - *(volatile uint32_t *)(0xbb000a68) = 0x80000000; - - return 1; -} - -void prom_init_secondary(void) -{ - clear_c0_config(CONF_CM_CMASK); - set_c0_config(0x2); - - clear_c0_status(ST0_IM); - set_c0_status(0x1ffff); -} - -void prom_smp_finish(void) -{ -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/reset.c mips/arch/mips/momentum/jaguar_atx/reset.c --- mips-orig/arch/mips/momentum/jaguar_atx/reset.c 2006-10-02 22:34:28.505152750 +0900 +++ mips/arch/mips/momentum/jaguar_atx/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,56 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - */ -#include -#include -#include -#include -#include -#include -#include -#include - -void momenco_jaguar_restart(char *command) -{ - /* base address of timekeeper portion of part */ -#ifdef CONFIG_64BIT - void *nvram = (void*) 0xfffffffffc807000; -#else - void *nvram = (void*) 0xfc807000; -#endif - /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ - writeb(0x84, nvram + 0xff7); - - /* wait for the watchdog to go off */ - mdelay(100+(1000/16)); - - /* if the watchdog fails for some reason, let people know */ - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_jaguar_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_jaguar_power_off(void) -{ - momenco_jaguar_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/setup.c mips/arch/mips/momentum/jaguar_atx/setup.c --- mips-orig/arch/mips/momentum/jaguar_atx/setup.c 2006-10-02 22:34:28.505152750 +0900 +++ mips/arch/mips/momentum/jaguar_atx/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,476 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Momentum Computer Jaguar-ATX board dependent boot routines - * - * Copyright (C) 1996, 1997, 2001, 04, 06 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: Matthew Dharm, Momentum Computer - * mdharm@momenco.com - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "jaguar_atx_fpga.h" - -extern unsigned long mv64340_sram_base; -unsigned long cpu_clock; - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_jaguar_restart(char *command); -extern void momenco_jaguar_halt(void); -extern void momenco_jaguar_power_off(void); - -void momenco_time_init(void); - -static char reset_reason; - -static inline unsigned long ENTRYLO(unsigned long paddr) -{ - return ((paddr & PAGE_MASK) | - (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | - _CACHE_UNCACHED)) >> 6; -} - -void __init bus_error_init(void) { /* nothing */ } - -/* - * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going - * to be hit on every IRQ anyway - there's absolutely no point in letting it be - * a random TLB entry, as it'll just cause needless churning of the TLB. And we - * use the other half for the serial port, which is just a PITA otherwise :) - * - * Device Physical Virtual - * MV64340 Internal Regs 0xf4000000 0xf4000000 - * Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000 - * NVRAM (CS1) 0xfc800000 0xfc800000 - * UARTs (CS2) 0xfd000000 0xfd000000 - * Internal SRAM 0xfe000000 0xfe000000 - * M-Systems DOC (CS3) 0xff000000 0xff000000 - */ - -static __init void wire_stupidity_into_tlb(void) -{ -#ifdef CONFIG_32BIT - write_c0_wired(0); - local_flush_tlb_all(); - - /* marvell and extra space */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), - 0xf4000000UL, PM_64K); - /* fpga, rtc, and uart */ - add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), - 0xfc000000UL, PM_16M); -// /* m-sys and internal SRAM */ -// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), -// 0xfe000000UL, PM_16M); - - marvell_base = 0xf4000000; - //mv64340_sram_base = 0xfe000000; /* Currently unused */ -#endif -} - -unsigned long marvell_base = 0xf4000000L; -unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR; -unsigned long uart_base = 0xfd000000L; -static unsigned char *rtc_base = (unsigned char*) 0xfc800000L; - -EXPORT_SYMBOL(marvell_base); - -static __init int per_cpu_mappings(void) -{ - marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000); - ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000); - uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000); - rtc_base = ioremap(0xfc000000UL, 0x8000); - // ioremap(0xfe000000, 32 << 20); - write_c0_wired(0); - local_flush_tlb_all(); - ja_setup_console(); - - return 0; -} -arch_initcall(per_cpu_mappings); - -unsigned long m48t37y_get_time(void) -{ - unsigned int year, month, day, hour, min, sec; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - /* stop the update */ - rtc_base[0x7ff8] = 0x40; - - year = BCD2BIN(rtc_base[0x7fff]); - year += BCD2BIN(rtc_base[0x7ff1]) * 100; - - month = BCD2BIN(rtc_base[0x7ffe]); - - day = BCD2BIN(rtc_base[0x7ffd]); - - hour = BCD2BIN(rtc_base[0x7ffb]); - min = BCD2BIN(rtc_base[0x7ffa]); - sec = BCD2BIN(rtc_base[0x7ff9]); - - /* start the update */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return mktime(year, month, day, hour, min, sec); -} - -int m48t37y_set_time(unsigned long sec) -{ - struct rtc_time tm; - unsigned long flags; - - /* convert to a more useful format -- note months count from 0 */ - to_tm(sec, &tm); - tm.tm_mon += 1; - - spin_lock_irqsave(&rtc_lock, flags); - /* enable writing */ - rtc_base[0x7ff8] = 0x80; - - /* year */ - rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100); - rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100); - - /* month */ - rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon); - - /* day */ - rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday); - - /* hour/min/sec */ - rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour); - rtc_base[0x7ffa] = BIN2BCD(tm.tm_min); - rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec); - - /* day of week -- not really used, but let's keep it up-to-date */ - rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1); - - /* disable writing */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - -void __init plat_timer_setup(struct irqaction *irq) -{ - setup_irq(8, irq); -} - -/* - * Ugly but the least of all evils. TLB initialization did flush the TLB so - * We need to setup mappings again before we can touch the RTC. - */ -void momenco_time_init(void) -{ - wire_stupidity_into_tlb(); - - mips_hpt_frequency = cpu_clock / 2; - - rtc_mips_get_time = m48t37y_get_time; - rtc_mips_set_time = m48t37y_set_time; -} - -static struct resource mv_pci_io_mem0_resource = { - .name = "MV64340 PCI0 IO MEM", - .flags = IORESOURCE_IO -}; - -static struct resource mv_pci_mem0_resource = { - .name = "MV64340 PCI0 MEM", - .flags = IORESOURCE_MEM -}; - -static struct mv_pci_controller mv_bus0_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem0_resource, - .io_resource = &mv_pci_io_mem0_resource, - }, - .config_addr = MV64340_PCI_0_CONFIG_ADDR, - .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, -}; - -static uint32_t mv_io_base, mv_io_size; - -static void ja_pci0_init(void) -{ - uint32_t mem0_base, mem0_size; - uint32_t io_base, io_size; - - io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16; - io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16; - mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16; - mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16; - - mv_pci_io_mem0_resource.start = 0; - mv_pci_io_mem0_resource.end = io_size - 1; - mv_pci_mem0_resource.start = mem0_base; - mv_pci_mem0_resource.end = mem0_base + mem0_size - 1; - mv_bus0_controller.pcic.mem_offset = mem0_base; - mv_bus0_controller.pcic.io_offset = 0; - - ioport_resource.end = io_size - 1; - - register_pci_controller(&mv_bus0_controller.pcic); - - mv_io_base = io_base; - mv_io_size = io_size; -} - -static struct resource mv_pci_io_mem1_resource = { - .name = "MV64340 PCI1 IO MEM", - .flags = IORESOURCE_IO -}; - -static struct resource mv_pci_mem1_resource = { - .name = "MV64340 PCI1 MEM", - .flags = IORESOURCE_MEM -}; - -static struct mv_pci_controller mv_bus1_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem1_resource, - .io_resource = &mv_pci_io_mem1_resource, - }, - .config_addr = MV64340_PCI_1_CONFIG_ADDR, - .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, -}; - -static __init void ja_pci1_init(void) -{ - uint32_t mem0_base, mem0_size; - uint32_t io_base, io_size; - - io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16; - io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16; - mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16; - mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16; - - /* - * Here we assume the I/O window of second bus to be contiguous with - * the first. A gap is no problem but would waste address space for - * remapping the port space. - */ - mv_pci_io_mem1_resource.start = mv_io_size; - mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1; - mv_pci_mem1_resource.start = mem0_base; - mv_pci_mem1_resource.end = mem0_base + mem0_size - 1; - mv_bus1_controller.pcic.mem_offset = mem0_base; - mv_bus1_controller.pcic.io_offset = 0; - - ioport_resource.end = io_base + io_size -mv_io_base - 1; - - register_pci_controller(&mv_bus1_controller.pcic); - - mv_io_size = io_base + io_size - mv_io_base; -} - -static __init int __init ja_pci_init(void) -{ - unsigned long io_v_base; - uint32_t enable; - - enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE); - - /* - * We require at least one enabled I/O or PCI memory window or we - * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3. - */ - if (enable & (0x01 << 9) || enable & (0x01 << 10)) - ja_pci0_init(); - - if (enable & (0x01 << 14) || enable & (0x01 << 15)) - ja_pci1_init(); - - if (mv_io_size) { - io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size); - if (!io_v_base) - panic("Could not ioremap I/O port range"); - - set_io_port_base(io_v_base); - } - - return 0; -} - -arch_initcall(ja_pci_init); - -void __init plat_mem_setup(void) -{ - unsigned int tmpword; - - board_time_init = momenco_time_init; - - _machine_restart = momenco_jaguar_restart; - _machine_halt = momenco_jaguar_halt; - pm_power_off = momenco_jaguar_power_off; - - /* - * initrd_start = (unsigned long)jaguar_initrd_start; - * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size; - * initrd_below_start_ok = 1; - */ - - wire_stupidity_into_tlb(); - - /* - * shut down ethernet ports, just to be sure our memory doesn't get - * corrupted by random ethernet traffic. - */ - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8); - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff); - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1); - - /* Turn off the Bit-Error LED */ - JAGUAR_FPGA_WRITE(0x80, CLR); - - tmpword = JAGUAR_FPGA_READ(BOARDREV); - if (tmpword < 26) - printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n", - 'A'+tmpword); - else - printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n", - tmpword); - - tmpword = JAGUAR_FPGA_READ(FPGA_REV); - printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = JAGUAR_FPGA_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - switch (tmpword) { - case 0x1: - printk(" - Power-up reset\n"); - break; - case 0x2: - printk(" - Push-button reset\n"); - break; - case 0x8: - printk(" - Watchdog reset\n"); - break; - case 0x10: - printk(" - JTAG reset\n"); - break; - default: - printk(" - Unknown reset cause\n"); - } - reset_reason = tmpword; - JAGUAR_FPGA_WRITE(0xff, RESET_STATUS); - - tmpword = JAGUAR_FPGA_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - - /* 256MiB of RM9000x2 DDR */ -// add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM); - - /* 128MiB of MV-64340 DDR */ -// add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM); - - /* XXX Memory configuration should be picked up from PMON2k */ -#ifdef CONFIG_JAGUAR_DMALOW - printk("Jaguar ATX DMA-low mode set\n"); - add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM); - add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM); -#else - /* 128MiB of MV-64340 DDR RAM */ - printk("Jaguar ATX DMA-low mode is not set\n"); - add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM); -#endif - -#ifdef GEMDEBUG_TRACEBUFFER - { - unsigned int tbControl; - tbControl = - 0 << 26 | /* post trigger delay 0 */ - 0x2 << 16 | /* sequential trace mode */ - // 0x0 << 16 | /* non-sequential trace mode */ - // 0xf << 4 | /* watchpoints disabled */ - 2 << 2 | /* armed */ - 2 ; /* interrupt disabled */ - printk ("setting tbControl = %08lx\n", tbControl); - write_32bit_cp0_set1_register($22, tbControl); - __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t"); - - } -#endif -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/Makefile mips/arch/mips/pci/Makefile --- mips-orig/arch/mips/pci/Makefile 2006-10-02 22:34:28.537154750 +0900 +++ mips/arch/mips/pci/Makefile 2006-10-02 22:32:30.233761250 +0900 @@ -34,7 +34,6 @@ obj-$(CONFIG_SOC_AU1500) += fixup-au1000 obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o -obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-jaguar.c mips/arch/mips/pci/fixup-jaguar.c --- mips-orig/arch/mips/pci/fixup-jaguar.c 2006-10-02 22:34:28.541155000 +0900 +++ mips/arch/mips/pci/fixup-jaguar.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,43 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Marvell MV64340 interrupt fixup code. - * - * Marvell wants an NDA for their docs so this was written without - * documentation. You've been warned. - * - * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) - */ -#include -#include -#include - -#include - -/* - * WARNING: Example of how _NOT_ to do it. - */ -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) - return 3; /* PCI-X A */ - if (bus == 0 && slot == 2) - return 4; /* PCI-X B */ - if (bus == 1 && slot == 1) - return 5; /* PCI A */ - if (bus == 1 && slot == 2) - return 6; /* PCI B */ - -return 0; - panic("Whooops in pcibios_map_irq"); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/bootinfo.h mips/include/asm-mips/bootinfo.h --- mips-orig/include/asm-mips/bootinfo.h 2006-10-02 22:34:28.541155000 +0900 +++ mips/include/asm-mips/bootinfo.h 2006-10-02 22:32:30.237761500 +0900 @@ -121,7 +121,6 @@ #define MACH_MOMENCO_OCELOT 0 #define MACH_MOMENCO_OCELOT_G 1 #define MACH_MOMENCO_OCELOT_C 2 -#define MACH_MOMENCO_JAGUAR_ATX 3 #define MACH_MOMENCO_OCELOT_3 4 /* diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/highmem.h mips/include/asm-mips/highmem.h --- mips-orig/include/asm-mips/highmem.h 2006-10-02 22:34:28.541155000 +0900 +++ mips/include/asm-mips/highmem.h 2006-10-02 22:32:30.237761500 +0900 @@ -47,41 +47,6 @@ extern pte_t *pkmap_page_table; extern void * kmap_high(struct page *page); extern void kunmap_high(struct page *page); -/* - * CONFIG_LIMITED_DMA is for systems with DMA limitations such as Momentum's - * Jaguar ATX. This option exploits the highmem code in the kernel so is - * always enabled together with CONFIG_HIGHMEM but at this time doesn't - * actually add highmem functionality. - */ - -#ifdef CONFIG_LIMITED_DMA - -/* - * These are the default functions for the no-highmem case from - * - */ -static inline void *kmap(struct page *page) -{ - might_sleep(); - return page_address(page); -} - -#define kunmap(page) do { (void) (page); } while (0) - -static inline void *kmap_atomic(struct page *page, enum km_type type) -{ - return page_address(page); -} - -static inline void kunmap_atomic(void *kvaddr, enum km_type type) { } -#define kmap_atomic_pfn(pfn, idx) page_address(pfn_to_page(pfn)) - -#define kmap_atomic_to_page(ptr) virt_to_page(ptr) - -#define flush_cache_kmaps() do { } while (0) - -#else /* LIMITED_DMA */ - extern void *__kmap(struct page *page); extern void __kunmap(struct page *page); extern void *__kmap_atomic(struct page *page, enum km_type type); @@ -97,8 +62,6 @@ extern struct page *__kmap_atomic_to_pag #define flush_cache_kmaps() flush_cache_all() -#endif /* LIMITED_DMA */ - #endif /* __KERNEL__ */ #endif /* _ASM_HIGHMEM_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/mach-ja/cpu-feature-overrides.h mips/include/asm-mips/mach-ja/cpu-feature-overrides.h --- mips-orig/include/asm-mips/mach-ja/cpu-feature-overrides.h 2006-10-02 22:34:28.541155000 +0900 +++ mips/include/asm-mips/mach-ja/cpu-feature-overrides.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,45 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Ralf Baechle - */ -#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H - -/* - * Momentum Jaguar ATX always has the RM9000 processor. - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_icache_snoops_remote_store 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 32 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/mach-ja/spaces.h mips/include/asm-mips/mach-ja/spaces.h --- mips-orig/include/asm-mips/mach-ja/spaces.h 2006-10-02 22:34:28.541155000 +0900 +++ mips/include/asm-mips/mach-ja/spaces.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,20 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef __ASM_MACH_JA_SPACES_H -#define __ASM_MACH_JA_SPACES_H - -/* - * Memory above this physical address will be considered highmem. - */ -#define HIGHMEM_START 0x08000000UL - -#include_next - -#endif /* __ASM_MACH_JA_SPACES_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/page.h mips/include/asm-mips/page.h --- mips-orig/include/asm-mips/page.h 2006-10-02 22:34:28.541155000 +0900 +++ mips/include/asm-mips/page.h 2006-10-02 22:32:30.245762000 +0900 @@ -166,10 +166,6 @@ typedef struct { unsigned long pgprot; } #define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) #define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) -#ifdef CONFIG_LIMITED_DMA -#define WANT_PAGE_VIRTUAL -#endif - #include #include diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/serial.h mips/include/asm-mips/serial.h --- mips-orig/include/asm-mips/serial.h 2006-10-02 22:34:28.541155000 +0900 +++ mips/include/asm-mips/serial.h 2006-10-02 22:32:30.245762000 +0900 @@ -113,25 +113,6 @@ #define STD_SERIAL_PORT_DEFNS #endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ -#ifdef CONFIG_MOMENCO_JAGUAR_ATX -/* Ordinary NS16552 duart with a 20MHz crystal. */ -#define JAGUAR_ATX_UART_CLK 20000000 -#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16) - -#define JAGUAR_ATX_SERIAL1_IRQ 6 -#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L - -#define _JAGUAR_ATX_SERIAL_INIT(int, base) \ - { .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \ - .flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - .iomem_base = (u8 *) base, iomem_reg_shift: 2, \ - io_type: SERIAL_IO_MEM } -#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \ - _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE) -#else -#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS -#endif - #ifdef CONFIG_MOMENCO_OCELOT_3 #define OCELOT_3_BASE_BAUD ( 20000000 / 16 ) #define OCELOT_3_SERIAL_IRQ 6 diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/war.h mips/include/asm-mips/war.h --- mips-orig/include/asm-mips/war.h 2006-10-02 22:34:28.541155000 +0900 +++ mips/include/asm-mips/war.h 2006-10-02 22:32:30.245762000 +0900 @@ -171,8 +171,7 @@ * On the RM9000 there is a problem which makes the CreateDirtyExclusive * cache operation unusable on SMP systems. */ -#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \ - defined(CONFIG_BASLER_EXCITE) +#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) #define RM9000_CDEX_SMP_WAR 1 #endif @@ -181,8 +180,8 @@ * where invalid instructions in the same I-cache line worth of instructions * being fetched may case spurious exceptions. */ -#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ - defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) +#if defined(CONFIG_MOMENCO_OCELOT_3) || defined(CONFIG_PMC_YOSEMITE) || \ + defined(CONFIG_BASLER_EXCITE) #define ICACHE_REFILLS_WORKAROUND_WAR 1 #endif From yoichi_yuasa@tripeaks.co.jp Mon Oct 2 15:20:36 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Oct 2006 15:20:44 +0100 (BST) Received: from mo31.po.2iij.net ([210.128.50.54]:7958 "EHLO mo31.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20038773AbWJBOUL (ORCPT ); Mon, 2 Oct 2006 15:20:11 +0100 Received: by mo.po.2iij.net (mo31) id k92EK5ln039189; Mon, 2 Oct 2006 23:20:05 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox33) id k92EJvYs030409 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 2 Oct 2006 23:19:57 +0900 (JST) Date: Mon, 2 Oct 2006 23:17:00 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH] remove Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G support Message-Id: <20061002231700.398b5836.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12765 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has removed Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G support. It was scheduled to be removed after 2.6.18 released. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/Documentation/feature-removal-schedule.txt mips/Documentation/feature-removal-schedule.txt --- mips-orig/Documentation/feature-removal-schedule.txt 2006-10-02 22:40:23.595344500 +0900 +++ mips/Documentation/feature-removal-schedule.txt 2006-10-02 22:40:29.383706250 +0900 @@ -220,14 +220,6 @@ Who: Nick Piggin --------------------------- -What: Support for the Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G -When: September 2006 -Why: Some do no longer build and apparently there is no user base left - for these platforms. -Who: Ralf Baechle - ---------------------------- - What: Support for MIPS Technologies' Altas and SEAD evaluation board When: September 2006 Why: Some do no longer build and apparently there is no user base left diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Kconfig mips/arch/mips/Kconfig --- mips-orig/arch/mips/Kconfig 2006-10-02 22:40:23.595344500 +0900 +++ mips/arch/mips/Kconfig 2006-10-02 22:40:29.387706500 +0900 @@ -374,76 +374,6 @@ config MIPS_SIM This option enables support for MIPS Technologies MIPSsim software emulator. -config MOMENCO_OCELOT - bool "Momentum Ocelot board" - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select IRQ_CPU_RM7K - select MIPS_GT64120 - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - The Ocelot is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer . - -config MOMENCO_OCELOT_3 - bool "Momentum Ocelot-3 board" - select BOOT_ELF32 - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select IRQ_CPU_RM7K - select IRQ_MV64340 - select PCI_MARVELL - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_RM9000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - The Ocelot-3 is based off Discovery III System Controller and - PMC-Sierra Rm79000 core. - -config MOMENCO_OCELOT_C - bool "Momentum Ocelot-C board" - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select IRQ_MV64340 - select PCI_MARVELL - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - The Ocelot is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer . - -config MOMENCO_OCELOT_G - bool "Momentum Ocelot-G board" - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select IRQ_CPU_RM7K - select PCI_MARVELL - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - The Ocelot is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer . - config MIPS_XXS1500 bool "MyCable XXS1500 board" select DMA_NONCOHERENT @@ -908,9 +838,6 @@ config IRQ_CPU_RM7K config IRQ_CPU_RM9K bool -config IRQ_MV64340 - bool - config DDB5XXX_COMMON bool @@ -999,9 +926,8 @@ config WDT_RM9000 choice prompt "Galileo Chip Clock" #default SYSCLK_83 if MIPS_EV64120 - depends on MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G + depends on MIPS_EV64120 default SYSCLK_83 if MIPS_EV64120 - default SYSCLK_100 if MOMENCO_OCELOT || MOMENCO_OCELOT_G config SYSCLK_75 bool "75" if MIPS_EV64120 @@ -1010,7 +936,7 @@ config SYSCLK_83 bool "83.3" if MIPS_EV64120 config SYSCLK_100 - bool "100" if MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G + bool "100" if MIPS_EV64120 endchoice diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Makefile mips/arch/mips/Makefile --- mips-orig/arch/mips/Makefile 2006-10-02 22:40:23.595344500 +0900 +++ mips/arch/mips/Makefile 2006-10-02 22:40:29.387706500 +0900 @@ -334,34 +334,6 @@ cflags-$(CONFIG_MIPS_SIM) += -Iinclude/a load-$(CONFIG_MIPS_SIM) += 0x80100000 # -# Momentum Ocelot board -# -# The Ocelot setup.o must be linked early - it does the ioremap() for the -# mips_io_port_base. -# -core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \ - arch/mips/gt64120/momenco_ocelot/ -cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot -load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000 - -# -# Momentum Ocelot-G board -# -# The Ocelot-G setup.o must be linked early - it does the ioremap() for the -# mips_io_port_base. -# -core-$(CONFIG_MOMENCO_OCELOT_G) += arch/mips/momentum/ocelot_g/ -load-$(CONFIG_MOMENCO_OCELOT_G) += 0xffffffff80100000 - -# -# Momentum Ocelot-C and -CS boards -# -# The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the -# mips_io_port_base. -core-$(CONFIG_MOMENCO_OCELOT_C) += arch/mips/momentum/ocelot_c/ -load-$(CONFIG_MOMENCO_OCELOT_C) += 0xffffffff80100000 - -# # PMC-Sierra Yosemite # core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ @@ -376,13 +348,6 @@ cflags-$(CONFIG_QEMU) += -Iinclude/asm- load-$(CONFIG_QEMU) += 0xffffffff80010000 # -# Momentum Ocelot-3 -# -core-$(CONFIG_MOMENCO_OCELOT_3) += arch/mips/momentum/ocelot_3/ -cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3 -load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000 - -# # Basler eXcite # core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/ocelot_3_defconfig mips/arch/mips/configs/ocelot_3_defconfig --- mips-orig/arch/mips/configs/ocelot_3_defconfig 2006-10-02 22:32:45.834736250 +0900 +++ mips/arch/mips/configs/ocelot_3_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,1158 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:15 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -CONFIG_MOMENCO_OCELOT_3=y -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_CPU_RM7K=y -CONFIG_IRQ_MV64340=y -CONFIG_PCI_MARVELL=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_BOOT_ELF32=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -CONFIG_CPU_RM9000=y -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM9000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Block layer -# -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -# CONFIG_IPV6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -# CONFIG_NF_CONNTRACK is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set - -# -# IPv6: Netfilter Configuration (EXPERIMENTAL) -# -# CONFIG_IP6_NF_QUEUE is not set -# CONFIG_IP6_NF_IPTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_CDROM_PKTCDVD is not set -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=m -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -# CONFIG_BLK_DEV_SD is not set -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI Transport Attributes -# -# CONFIG_SCSI_SPI_ATTRS is not set -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_ISCSI_ATTRS=m -CONFIG_SCSI_SAS_ATTRS=m - -# -# SCSI low-level drivers -# -CONFIG_ISCSI_TCP=m -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -CONFIG_TUN=m - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=m - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_LXT_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_SMSC_PHY=m - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -CONFIG_E100=y -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_LAN_SAA9730 is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_MV643XX_ETH=y -CONFIG_MV643XX_ETH_0=y -CONFIG_MV643XX_ETH_1=y -CONFIG_MV643XX_ETH_2=y - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PPP=m -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -# CONFIG_PPP_BSDCOMP is not set -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -CONFIG_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FB=y -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_TILEBLITTING is not set -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_SMIVGX is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_VIRTUAL is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y - -# -# Logo configuration -# -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=m -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=m -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set -# CONFIG_REISERFS_FS_XATTR is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -CONFIG_XFS_FS=m -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_SECURITY is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=m - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_EFS_FS=y -CONFIG_CRAMFS=y -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -# CONFIG_NFSD_V3_ACL is not set -# CONFIG_NFSD_V4 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=m -# CONFIG_SMB_NLS_DEFAULT is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=m -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="ip=any root=nfs" - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -CONFIG_CRC_CCITT=m -CONFIG_CRC16=m -CONFIG_CRC32=y -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=m -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/ocelot_c_defconfig mips/arch/mips/configs/ocelot_c_defconfig --- mips-orig/arch/mips/configs/ocelot_c_defconfig 2006-10-02 22:32:45.834736250 +0900 +++ mips/arch/mips/configs/ocelot_c_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,903 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:16 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -CONFIG_MOMENCO_OCELOT_C=y -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_MV64340=y -CONFIG_PCI_MARVELL=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -CONFIG_CPU_RM7000=y -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -# CONFIG_32BIT is not set -CONFIG_64BIT=y -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_RESOURCES_64BIT=y -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# -# CONFIG_BLK_DEV_IO_TRACE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_BUILD_ELF64 is not set -CONFIG_MIPS32_COMPAT=y -CONFIG_COMPAT=y -CONFIG_MIPS32_O32=y -CONFIG_MIPS32_N32=y -CONFIG_BINFMT_ELF32=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -# CONFIG_PACKET is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_SOFTMAC=y -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=y - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=y -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -# CONFIG_MV643XX_ETH is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -# CONFIG_UNWIND_INFO is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -CONFIG_CRC32=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/ocelot_defconfig mips/arch/mips/configs/ocelot_defconfig --- mips-orig/arch/mips/configs/ocelot_defconfig 2006-10-02 22:32:45.834736250 +0900 +++ mips/arch/mips/configs/ocelot_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,852 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:16 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -CONFIG_MOMENCO_OCELOT=y -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_CPU_RM7K=y -CONFIG_MIPS_GT64120=y -CONFIG_SWAP_IO_SPACE=y -# CONFIG_SYSCLK_75 is not set -# CONFIG_SYSCLK_83 is not set -CONFIG_SYSCLK_100=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -CONFIG_CPU_RM7000=y -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_HOTPLUG is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -# CONFIG_PCI is not set -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -# CONFIG_PACKET is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_SOFTMAC=y -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=y - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=y -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# PHY device support -# -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_DM9000 is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -# CONFIG_UNWIND_INFO is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -CONFIG_CRC32=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/ocelot_g_defconfig mips/arch/mips/configs/ocelot_g_defconfig --- mips-orig/arch/mips/configs/ocelot_g_defconfig 2006-10-02 22:32:45.834736250 +0900 +++ mips/arch/mips/configs/ocelot_g_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,906 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:16 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -CONFIG_MOMENCO_OCELOT_G=y -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_CPU_RM7K=y -CONFIG_PCI_MARVELL=y -CONFIG_SWAP_IO_SPACE=y -# CONFIG_SYSCLK_75 is not set -# CONFIG_SYSCLK_83 is not set -CONFIG_SYSCLK_100=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -CONFIG_CPU_RM7000=y -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -# CONFIG_32BIT is not set -CONFIG_64BIT=y -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_RESOURCES_64BIT=y -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# -# CONFIG_BLK_DEV_IO_TRACE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_BUILD_ELF64 is not set -CONFIG_MIPS32_COMPAT=y -CONFIG_COMPAT=y -CONFIG_MIPS32_O32=y -CONFIG_MIPS32_N32=y -CONFIG_BINFMT_ELF32=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -# CONFIG_PACKET is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_SOFTMAC=y -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=y - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=y -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_GALILEO_64240_ETH=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -# CONFIG_UNWIND_INFO is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -CONFIG_CRC32=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/Makefile mips/arch/mips/gt64120/momenco_ocelot/Makefile --- mips-orig/arch/mips/gt64120/momenco_ocelot/Makefile 2006-10-02 22:32:45.894740000 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,9 +0,0 @@ -# -# Makefile for Momentum's Ocelot board. -# - -obj-y += irq.o prom.o reset.o setup.o - -obj-$(CONFIG_KGDB) += dbg_io.o - -EXTRA_AFLAGS := $(CFLAGS) diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/dbg_io.c mips/arch/mips/gt64120/momenco_ocelot/dbg_io.c --- mips-orig/arch/mips/gt64120/momenco_ocelot/dbg_io.c 2006-10-02 22:32:45.894740000 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/dbg_io.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,125 +0,0 @@ - -#ifdef CONFIG_KGDB - -#include /* For the serial port location and base baud */ - -/* --- CONFIG --- */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE OCELOT_SERIAL1_BASE -#define MAX_BAUD OCELOT_BASE_BAUD - -/* === END OF CONFIG === */ - -#define REG_OFFSET 4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/irq.c mips/arch/mips/gt64120/momenco_ocelot/irq.c --- mips-orig/arch/mips/gt64120/momenco_ocelot/irq.c 2006-10-02 22:32:45.894740000 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,95 +0,0 @@ -/* - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_status() & read_c0_cause(); - - if (pending & STATUSF_IP2) /* int0 hardware line */ - do_IRQ(2, regs); - else if (pending & STATUSF_IP3) /* int1 hardware line */ - do_IRQ(3, regs); - else if (pending & STATUSF_IP4) /* int2 hardware line */ - do_IRQ(4, regs); - else if (pending & STATUSF_IP5) /* int3 hardware line */ - do_IRQ(5, regs); - else if (pending & STATUSF_IP6) /* int4 hardware line */ - do_IRQ(6, regs); - else if (pending & STATUSF_IP7) /* cpu timer */ - do_IRQ(7, regs); - else { - /* - * Now look at the extended interrupts - */ - pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; - - if (pending & STATUSF_IP8) /* int6 hardware line */ - do_IRQ(8, regs); - else if (pending & STATUSF_IP9) /* int7 hardware line */ - do_IRQ(9, regs); - else if (pending & STATUSF_IP10) /* int8 hardware line */ - do_IRQ(10, regs); - else if (pending & STATUSF_IP11) /* int9 hardware line */ - do_IRQ(11, regs); - } -} - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM); - local_irq_disable(); - - mips_cpu_irq_init(0); - rm7k_cpu_irq_init(8); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h mips/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h --- mips-orig/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h 2006-10-02 22:32:45.894740000 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,30 +0,0 @@ -/* - * Ocelot Board Register Definitions - * - * (C) 2001 Red Hat, Inc. - * - * GPL'd - */ -#ifndef __MOMENCO_OCELOT_PLD_H__ -#define __MOMENCO_OCELOT_PLD_H__ - -#define OCELOT_CS0_ADDR (0xe0020000) - -#define OCELOT_REG_BOARDREV (0) -#define OCELOT_REG_PLD1_ID (1) -#define OCELOT_REG_PLD2_ID (2) -#define OCELOT_REG_RESET_STATUS (3) -#define OCELOT_REG_BOARD_STATUS (4) -#define OCELOT_REG_CPCI_ID (5) -#define OCELOT_REG_I2C_CTRL (8) -#define OCELOT_REG_EEPROM_MODE (9) -#define OCELOT_REG_INTMASK (10) -#define OCELOT_REG_INTSTATUS (11) -#define OCELOT_REG_INTSET (12) -#define OCELOT_REG_INTCLR (13) - -#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y) -#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x) - - -#endif /* __MOMENCO_OCELOT_PLD_H__ */ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/prom.c mips/arch/mips/gt64120/momenco_ocelot/prom.c --- mips-orig/arch/mips/gt64120/momenco_ocelot/prom.c 2006-10-02 22:32:45.894740000 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,73 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include - -#include -#include -#include - -struct callvectors* debug_vectors; - -extern unsigned long gt64120_base; - -const char *get_system_type(void) -{ - return "Momentum Ocelot"; -} - -/* [jsun@junsun.net] PMON passes arguments in C main() style */ -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - uint32_t tmp; - int i; - - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_OCELOT; - - while (*env) { - if (strncmp("gtbase", *env, 6) == 0) { - gt64120_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - break; - } - *env++; - } - - debug_vectors->printf("Booting Linux kernel...\n"); - - /* All the boards have at least 64MiB. If there's more, we - detect and register it later */ - add_memory_region(0, 64 << 20, BOOT_MEM_RAM); -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/reset.c mips/arch/mips/gt64120/momenco_ocelot/reset.c --- mips-orig/arch/mips/gt64120/momenco_ocelot/reset.c 2006-10-02 22:32:45.894740000 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,47 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - */ -#include -#include -#include -#include -#include -#include -#include -#include - -void momenco_ocelot_restart(char *command) -{ - void *nvram = ioremap_nocache(0x2c807000, 0x1000); - - if (!nvram) { - printk(KERN_NOTICE "ioremap of reset register failed\n"); - return; - } - writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to - assert reset in 1/16 second */ - mdelay(10+(1000/16)); - iounmap(nvram); - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_ocelot_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_ocelot_power_off(void) -{ - momenco_ocelot_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/setup.c mips/arch/mips/gt64120/momenco_ocelot/setup.c --- mips-orig/arch/mips/gt64120/momenco_ocelot/setup.c 2006-10-02 22:32:45.894740000 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,369 +0,0 @@ -/* - * setup.c - * - * BRIEF MODULE DESCRIPTION - * Momentum Computer Ocelot (CP7000) - board dependent boot routines - * - * Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ocelot_pld.h" - -unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE); - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_ocelot_restart(char *command); -extern void momenco_ocelot_halt(void); -extern void momenco_ocelot_power_off(void); - -extern void gt64120_time_init(void); -extern void momenco_ocelot_irq_setup(void); - -static char reset_reason; - -#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1) - -static void __init setup_l3cache(unsigned long size); - -/* setup code for a handoff from a version 1 PMON 2000 PROM */ -void PMON_v1_setup() -{ - /* A wired TLB entry for the GT64120A and the serial port. The - GT64120A is going to be hit on every IRQ anyway - there's - absolutely no point in letting it be a random TLB entry, as - it'll just cause needless churning of the TLB. And we use - the other half for the serial port, which is just a PITA - otherwise :) - - Device Physical Virtual - GT64120 Internal Regs 0x24000000 0xe0000000 - UARTs (CS2) 0x2d000000 0xe0001000 - */ - add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K); - - /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM - in the CS[012] region. We can't use ioremap() yet. The NVRAM - is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. - - Ocelot PLD (CS0) 0x2c000000 0xe0020000 - NVRAM 0x2c800000 0xe0030000 - */ - - add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K); - - /* Relocate the CS3/BootCS region */ - GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21); - - /* Relocate CS[012] */ - GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21); - - /* Relocate the GT64120A itself... */ - GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21); - mb(); - gt64120_base = 0xe0000000; - - /* ...and the PCI0 view of it. */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000); - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001); -} - -/* setup code for a handoff from a version 2 PMON 2000 PROM */ -void PMON_v2_setup() -{ - /* A wired TLB entry for the GT64120A and the serial port. The - GT64120A is going to be hit on every IRQ anyway - there's - absolutely no point in letting it be a random TLB entry, as - it'll just cause needless churning of the TLB. And we use - the other half for the serial port, which is just a PITA - otherwise :) - - Device Physical Virtual - GT64120 Internal Regs 0xf4000000 0xe0000000 - UARTs (CS2) 0xfd000000 0xe0001000 - */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K); - - /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM - in the CS[012] region. We can't use ioremap() yet. The NVRAM - is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. - - Ocelot PLD (CS0) 0xfc000000 0xe0020000 - NVRAM 0xfc800000 0xe0030000 - */ - add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K); - - gt64120_base = 0xe0000000; -} - -void __init plat_mem_setup(void) -{ - void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); - unsigned int tmpword; - - board_time_init = gt64120_time_init; - - _machine_restart = momenco_ocelot_restart; - _machine_halt = momenco_ocelot_halt; - pm_power_off = momenco_ocelot_power_off; - - /* - * initrd_start = (unsigned long)ocelot_initrd_start; - * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; - * initrd_below_start_ok = 1; - */ - - /* do handoff reconfiguration */ - if (gt64120_base == KSEG1ADDR(GT_DEF_BASE)) - PMON_v1_setup(); - else - PMON_v2_setup(); - - /* Turn off the Bit-Error LED */ - OCELOT_PLD_WRITE(0x80, INTCLR); - - /* Relocate all the PCI1 stuff, not that we use it */ - GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21); - GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21); - GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21); - - /* Relocate PCI0 I/O and Mem0 */ - GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21); - GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21); - - /* Relocate PCI0 Mem1 */ - GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21); - - /* For the initial programming, we assume 512MB configuration */ - /* Relocate the CPU's view of the RAM... */ - GT_WRITE(GT_SCS10LD_OFS, 0); - GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21); - - GT_WRITE(GT_SCS1LD_OFS, 0xff); - GT_WRITE(GT_SCS1HD_OFS, 0x00); - GT_WRITE(GT_SCS0LD_OFS, 0); - GT_WRITE(GT_SCS0HD_OFS, 0xff); - GT_WRITE(GT_SCS3LD_OFS, 0xff); - GT_WRITE(GT_SCS3HD_OFS, 0x00); - GT_WRITE(GT_SCS2LD_OFS, 0); - GT_WRITE(GT_SCS2HD_OFS, 0xff); - - /* ...and the PCI0 view of it. */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000); - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000); - - tmpword = OCELOT_PLD_READ(BOARDREV); - if (tmpword < 26) - printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword); - else - printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword); - - tmpword = OCELOT_PLD_READ(PLD1_ID); - printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_PLD_READ(PLD2_ID); - printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_PLD_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - reset_reason = tmpword; - OCELOT_PLD_WRITE(0xff, RESET_STATUS); - - tmpword = OCELOT_PLD_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not"); - printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); - printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); - - if (tmpword&12) - l3func((1<<(((tmpword&12) >> 2)+20))); - - switch(tmpword &3) { - case 3: - /* 512MiB */ - /* Decoders are allready set -- just add the - * appropriate region */ - add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM); - add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM); - break; - case 2: - /* 256MiB -- two banks of 128MiB */ - GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21); - - GT_WRITE(GT_SCS0HD_OFS, 0x7f); - GT_WRITE(GT_SCS2LD_OFS, 0x80); - GT_WRITE(GT_SCS2HD_OFS, 0xff); - - /* reconfigure the PCI0 interface view of memory */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000); - - add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); - add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM); - break; - case 1: - /* 128MiB -- 64MiB per bank */ - GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21); - - GT_WRITE(GT_SCS0HD_OFS, 0x3f); - GT_WRITE(GT_SCS2LD_OFS, 0x40); - GT_WRITE(GT_SCS2HD_OFS, 0x7f); - - /* reconfigure the PCI0 interface view of memory */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000); - - /* add the appropriate region */ - add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); - break; - case 0: - /* 64MiB */ - GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21); - - GT_WRITE(GT_SCS0HD_OFS, 0x1f); - GT_WRITE(GT_SCS2LD_OFS, 0x20); - GT_WRITE(GT_SCS2HD_OFS, 0x3f); - - /* reconfigure the PCI0 interface view of memory */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000); - - break; - } - - /* Fix up the DiskOnChip mapping */ - GT_WRITE(GT_DEV_B3_OFS, 0xfef73); -} - -extern int rm7k_tcache_enabled; -/* - * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() - */ -#define Page_Invalidate_T 0x16 -static void __init setup_l3cache(unsigned long size) -{ - int register i; - unsigned long tmp; - - printk("Enabling L3 cache..."); - - /* Enable the L3 cache in the GT64120A's CPU Configuration register */ - tmp = GT_READ(GT_CPU_OFS); - GT_WRITE(GT_CPU_OFS, tmp | (1<<14)); - - /* Enable the L3 cache in the CPU */ - set_c0_config(1<<12 /* CONF_TE */); - - /* Clear the cache */ - write_c0_taglo(0); - write_c0_taghi(0); - - for (i=0; i < size; i+= 4096) { - __asm__ __volatile__ ( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (KSEG0ADDR(i)), - "i" (Page_Invalidate_T)); - } - - /* Let the RM7000 MM code know that the tertiary cache is enabled */ - rm7k_tcache_enabled = 1; - - printk("Done\n"); -} - - -/* This needs to be one of the first initcalls, because no I/O port access - can work before this */ - -static int io_base_ioremap(void) -{ - void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE); - - if (!io_remap_range) { - panic("Could not ioremap I/O port range"); - } - set_io_port_base(io_remap_range - GT_PCI_IO_BASE); - - return 0; -} - -module_init(io_base_ioremap); diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/kernel/Makefile mips/arch/mips/kernel/Makefile --- mips-orig/arch/mips/kernel/Makefile 2006-10-02 22:32:45.906740750 +0900 +++ mips/arch/mips/kernel/Makefile 2006-10-02 22:40:29.399707250 +0900 @@ -50,7 +50,6 @@ obj-$(CONFIG_I8259) += i8259.o obj-$(CONFIG_IRQ_CPU) += irq_cpu.o obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o -obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o obj-$(CONFIG_32BIT) += scall32-o32.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/kernel/irq-mv6434x.c mips/arch/mips/kernel/irq-mv6434x.c --- mips-orig/arch/mips/kernel/irq-mv6434x.c 2006-10-02 22:32:45.910741000 +0900 +++ mips/arch/mips/kernel/irq-mv6434x.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,162 +0,0 @@ -/* - * Copyright 2002 Momentum Computer - * Author: mdharm@momenco.com - * Copyright (C) 2004 Ralf Baechle - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -static unsigned int irq_base; - -static inline int ls1bit32(unsigned int x) -{ - int b = 31, s; - - s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; - s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; - s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; - s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; - s = 1; if (x << 1 == 0) s = 0; b -= s; - - return b; -} - -/* mask off an interrupt -- 1 is enable, 0 is disable */ -static inline void mask_mv64340_irq(unsigned int irq) -{ - uint32_t value; - - if (irq < (irq_base + 32)) { - value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); - value &= ~(1 << (irq - irq_base)); - MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value); - } else { - value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); - value &= ~(1 << (irq - irq_base - 32)); - MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value); - } -} - -/* unmask an interrupt -- 1 is enable, 0 is disable */ -static inline void unmask_mv64340_irq(unsigned int irq) -{ - uint32_t value; - - if (irq < (irq_base + 32)) { - value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); - value |= 1 << (irq - irq_base); - MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value); - } else { - value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); - value |= 1 << (irq - irq_base - 32); - MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value); - } -} - -/* - * Enables the IRQ on Marvell Chip - */ -static void enable_mv64340_irq(unsigned int irq) -{ - unmask_mv64340_irq(irq); -} - -/* - * Initialize the IRQ on Marvell Chip - */ -static unsigned int startup_mv64340_irq(unsigned int irq) -{ - unmask_mv64340_irq(irq); - return 0; -} - -/* - * Disables the IRQ on Marvell Chip - */ -static void disable_mv64340_irq(unsigned int irq) -{ - mask_mv64340_irq(irq); -} - -/* - * Masks and ACKs an IRQ - */ -static void mask_and_ack_mv64340_irq(unsigned int irq) -{ - mask_mv64340_irq(irq); -} - -/* - * End IRQ processing - */ -static void end_mv64340_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - unmask_mv64340_irq(irq); -} - -/* - * Interrupt handler for interrupts coming from the Marvell chip. - * It could be built in ethernet ports etc... - */ -void ll_mv64340_irq(struct pt_regs *regs) -{ - unsigned int irq_src_low, irq_src_high; - unsigned int irq_mask_low, irq_mask_high; - - /* read the interrupt status registers */ - irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); - irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); - irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW); - irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH); - - /* mask for just the interrupts we want */ - irq_src_low &= irq_mask_low; - irq_src_high &= irq_mask_high; - - if (irq_src_low) - do_IRQ(ls1bit32(irq_src_low) + irq_base, regs); - else - do_IRQ(ls1bit32(irq_src_high) + irq_base + 32, regs); -} - -#define shutdown_mv64340_irq disable_mv64340_irq - -struct irq_chip mv64340_irq_type = { - .typename = "MV-64340", - .startup = startup_mv64340_irq, - .shutdown = shutdown_mv64340_irq, - .enable = enable_mv64340_irq, - .disable = disable_mv64340_irq, - .ack = mask_and_ack_mv64340_irq, - .end = end_mv64340_irq, -}; - -void __init mv64340_irq_init(unsigned int base) -{ - int i; - - /* Reset irq handlers pointers to NULL */ - for (i = base; i < base + 64; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 2; - irq_desc[i].chip = &mv64340_irq_type; - } - - irq_base = base; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/Makefile mips/arch/mips/momentum/ocelot_3/Makefile --- mips-orig/arch/mips/momentum/ocelot_3/Makefile 2006-10-02 22:32:46.170757250 +0900 +++ mips/arch/mips/momentum/ocelot_3/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,8 +0,0 @@ -# -# Makefile for Momentum Computer's Ocelot-3 board. -# -# Note! Dependencies are done automagically by 'make dep', which also -# removes any old dependencies. DON'T put your own dependencies here -# unless it's something special (ie not a .c file). -# -obj-y += irq.o prom.o reset.o setup.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/irq.c mips/arch/mips/momentum/ocelot_3/irq.c --- mips-orig/arch/mips/momentum/ocelot_3/irq.c 2006-10-02 22:32:46.170757250 +0900 +++ mips/arch/mips/momentum/ocelot_3/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,109 +0,0 @@ -/* - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) - * - * Copyright 2004 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct irqaction cascade_mv64340 = { - no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL -}; - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM | ST0_BEV); - - rm7k_cpu_irq_init(8); - - /* set up the cascading interrupts */ - setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */ - mv64340_irq_init(16); - - set_c0_status(ST0_IM); /* IE in the status register */ - -} - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP0) - do_IRQ(0, regs); - else if (pending & STATUSF_IP1) - do_IRQ(1, regs); - else if (pending & STATUSF_IP2) - do_IRQ(2, regs); - else if (pending & STATUSF_IP3) - do_IRQ(3, regs); - else if (pending & STATUSF_IP4) - do_IRQ(4, regs); - else if (pending & STATUSF_IP5) - do_IRQ(5, regs); - else if (pending & STATUSF_IP6) - do_IRQ(6, regs); - else if (pending & STATUSF_IP7) - do_IRQ(7, regs); - else { - /* - * Now look at the extended interrupts - */ - pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; - - if (pending & STATUSF_IP8) - ll_mv64340_irq(regs); - else - spurious_interrupt(regs); - } -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h mips/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h --- mips-orig/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h 2006-10-02 22:32:46.170757250 +0900 +++ mips/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,57 +0,0 @@ -/* - * Ocelot-3 Board Register Definitions - * - * (C) 2002 Momentum Computer Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - */ - -#ifndef __OCELOT_3_FPGA_H__ -#define __OCELOT_3_FPGA_H__ - -#define OCELOT_3_REG_BOARDREV 0x0 -#define OCELOT_3_REG_FPGA_REV 0x1 -#define OCELOT_3_REG_FPGA_TYPE 0x2 -#define OCELOT_3_REG_RESET_STATUS 0x3 -#define OCELOT_3_REG_BOARD_STATUS 0x4 -#define OCELOT_3_REG_CPCI_ID 0x5 -#define OCELOT_3_REG_SET 0x6 -#define OCELOT_3_REG_CLR 0x7 -#define OCELOT_3_REG_EEPROM_MODE 0x9 -#define OCELOT_3_REG_INTMASK 0xa -#define OCELOT_3_REG_INTSTAT 0xb -#define OCELOT_3_REG_UART_INTMASK 0xc -#define OCELOT_3_REG_UART_INTSTAT 0xd -#define OCELOT_3_REG_INTSET 0xe -#define OCELOT_3_REG_INTCLR 0xf - -extern unsigned long ocelot_fpga_base; - -#define OCELOT_FPGA_WRITE(x, y) writeb(x, ocelot_fpga_base + OCELOT_3_REG_##y) -#define OCELOT_FPGA_READ(x) readb(ocelot_fpga_base + OCELOT_3_REG_##x) - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/prom.c mips/arch/mips/momentum/ocelot_3/prom.c --- mips-orig/arch/mips/momentum/ocelot_3/prom.c 2006-10-02 22:32:46.170757250 +0900 +++ mips/arch/mips/momentum/ocelot_3/prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,248 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Copyright 2004 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - */ -#include -#include -#include - -#include -#include -#include -#include "ocelot_3_fpga.h" - -struct callvectors* debug_vectors; -extern unsigned long marvell_base; -extern unsigned long cpu_clock; - -#ifdef CONFIG_MV643XX_ETH -extern unsigned char prom_mac_addr_base[6]; -#endif - -const char *get_system_type(void) -{ - return "Momentum Ocelot-3"; -} - -#ifdef CONFIG_MV643XX_ETH -void burn_clocks(void) -{ - int i; - - /* this loop should burn at least 1us -- this should be plenty */ - for (i = 0; i < 0x10000; i++) - ; -} - -u8 exchange_bit(u8 val, u8 cs) -{ - /* place the data */ - OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE); - burn_clocks(); - - /* turn the clock on */ - OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE); - burn_clocks(); - - /* turn the clock off and read-strobe */ - OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - - /* return the data */ - return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); -} - -void get_mac(char dest[6]) -{ - u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int i,j; - - for (i = 0; i < 12; i++) - exchange_bit(read_opcode[i], 1); - - for (j = 0; j < 6; j++) { - dest[j] = 0; - for (i = 0; i < 8; i++) { - dest[j] <<= 1; - dest[j] |= exchange_bit(0, 1); - } - } - - /* turn off CS */ - exchange_bit(0,0); -} -#endif - - -#ifdef CONFIG_64BIT - -unsigned long signext(unsigned long addr) -{ - addr &= 0xffffffff; - return (unsigned long)((int)addr); -} - -void *get_arg(unsigned long args, int arc) -{ - unsigned long ul; - unsigned char *puc, uc; - - args += (arc * 4); - ul = (unsigned long)signext(args); - puc = (unsigned char *)ul; - if (puc == 0) - return (void *)0; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - uc = *puc++; - ul = (unsigned long)uc; - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 24); -#else /* CONFIG_CPU_LITTLE_ENDIAN */ - uc = *puc++; - ul = ((unsigned long)uc) << 24; - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= ((unsigned long)uc); -#endif /* CONFIG_CPU_LITTLE_ENDIAN */ - ul = signext(ul); - return (void *)ul; -} - -char *arg64(unsigned long addrin, int arg_index) -{ - unsigned long args; - char *p; - - args = signext(addrin); - p = (char *)get_arg(args, arg_index); - - return p; -} -#endif /* CONFIG_64BIT */ - -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - int i; - -#ifdef CONFIG_64BIT - char *ptr; - printk("prom_init - MIPS64\n"); - - /* save the PROM vectors for debugging use */ - debug_vectors = (struct callvectors *)signext((unsigned long)cv); - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - - for (i = 1; i < argc; i++) { - ptr = (char *)arg64((unsigned long)arg, i); - if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >= - sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ptr); - strcat(arcs_cmdline, " "); - } - i = 0; - - while (1) { - ptr = (char *)arg64((unsigned long)env, i); - if (! ptr) - break; - - if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(ptr + strlen("gtbase="), - NULL, 16); - - if ((marvell_base & 0xffffffff00000000) == 0) - marvell_base |= 0xffffffff00000000; - - printk("marvell_base set to 0x%016lx\n", marvell_base); - } - if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(ptr + strlen("cpuclock="), - NULL, 10); - printk("cpu_clock set to %d\n", cpu_clock); - } - i++; - } - printk("arcs_cmdline: %s\n", arcs_cmdline); - -#else /* CONFIG_64BIT */ - - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - while (*env) { - if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - } - if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(*env + strlen("cpuclock="), - NULL, 10); - } - env++; - } -#endif /* CONFIG_64BIT */ - - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_OCELOT_3; - -#ifdef CONFIG_MV643XX_ETH - /* get the base MAC address for on-board ethernet ports */ - get_mac(prom_mac_addr_base); -#endif - -#ifndef CONFIG_64BIT - debug_vectors->printf("Booting Linux kernel...\n"); -#endif -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} - -void __init prom_fixup_mem_map(unsigned long start, unsigned long end) -{ -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/reset.c mips/arch/mips/momentum/ocelot_3/reset.c --- mips-orig/arch/mips/momentum/ocelot_3/reset.c 2006-10-02 22:32:46.170757250 +0900 +++ mips/arch/mips/momentum/ocelot_3/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,59 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 01, 05 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Copyright 2004 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - */ -#include -#include -#include -#include -#include -#include -#include -#include - -void momenco_ocelot_restart(char *command) -{ - /* base address of timekeeper portion of part */ - void *nvram = (void *) 0xfc807000L; - - /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ - writeb(0x84, nvram + 0xff7); - - /* wait for the watchdog to go off */ - mdelay(100+(1000/16)); - - /* if the watchdog fails for some reason, let people know */ - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_ocelot_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_ocelot_power_off(void) -{ - momenco_ocelot_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/setup.c mips/arch/mips/momentum/ocelot_3/setup.c --- mips-orig/arch/mips/momentum/ocelot_3/setup.c 2006-10-02 22:32:46.170757250 +0900 +++ mips/arch/mips/momentum/ocelot_3/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,399 +0,0 @@ -/* - * setup.c - * - * BRIEF MODULE DESCRIPTION - * Momentum Computer Ocelot-3 board dependent boot routines - * - * Copyright (C) 1996, 1997, 01, 05 Ralf Baechle - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: Matthew Dharm, Momentum Computer - * mdharm@momenco.com - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2004 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ocelot_3_fpga.h" - -/* Marvell Discovery Register Base */ -unsigned long marvell_base = (signed)0xf4000000; - -/* CPU clock */ -unsigned long cpu_clock; - -/* RTC/NVRAM */ -unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000; - -/* FPGA Base */ -unsigned long ocelot_fpga_base = (signed)0xfc000000; - -/* Serial base */ -unsigned long uart_base = (signed)0xfd000000; - -/* - * Marvell Discovery SRAM. This is one place where Ethernet - * Tx and Rx descriptors can be placed to improve performance - */ -extern unsigned long mv64340_sram_base; - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_ocelot_restart(char *command); -extern void momenco_ocelot_halt(void); -extern void momenco_ocelot_power_off(void); - -void momenco_time_init(void); -static char reset_reason; - -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask); - -static inline unsigned long ENTRYLO(unsigned long paddr) -{ - return ((paddr & PAGE_MASK) | - (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | - _CACHE_UNCACHED)) >> 6; -} - -void __init bus_error_init(void) -{ - /* nothing */ -} - -/* - * setup code for a handoff from a version 2 PMON 2000 PROM - */ -void setup_wired_tlb_entries(void) -{ - write_c0_wired(0); - local_flush_tlb_all(); - - /* marvell and extra space */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K); - - /* fpga, rtc, and uart */ - add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M); -} - -unsigned long m48t37y_get_time(void) -{ - unsigned int year, month, day, hour, min, sec; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - /* stop the update */ - rtc_base[0x7ff8] = 0x40; - - year = BCD2BIN(rtc_base[0x7fff]); - year += BCD2BIN(rtc_base[0x7ff1]) * 100; - - month = BCD2BIN(rtc_base[0x7ffe]); - - day = BCD2BIN(rtc_base[0x7ffd]); - - hour = BCD2BIN(rtc_base[0x7ffb]); - min = BCD2BIN(rtc_base[0x7ffa]); - sec = BCD2BIN(rtc_base[0x7ff9]); - - /* start the update */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return mktime(year, month, day, hour, min, sec); -} - -int m48t37y_set_time(unsigned long sec) -{ - struct rtc_time tm; - unsigned long flags; - - /* convert to a more useful format -- note months count from 0 */ - to_tm(sec, &tm); - tm.tm_mon += 1; - - spin_lock_irqsave(&rtc_lock, flags); - /* enable writing */ - rtc_base[0x7ff8] = 0x80; - - /* year */ - rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100); - rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100); - - /* month */ - rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon); - - /* day */ - rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday); - - /* hour/min/sec */ - rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour); - rtc_base[0x7ffa] = BIN2BCD(tm.tm_min); - rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec); - - /* day of week -- not really used, but let's keep it up-to-date */ - rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1); - - /* disable writing */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - -void __init plat_timer_setup(struct irqaction *irq) -{ - setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */ -} - -void momenco_time_init(void) -{ - setup_wired_tlb_entries(); - - /* - * Ocelot-3 board has been built with both - * the Rm7900 and the Rm7065C - */ - mips_hpt_frequency = cpu_clock / 2; - - rtc_mips_get_time = m48t37y_get_time; - rtc_mips_set_time = m48t37y_set_time; -} - -/* - * PCI Support for Ocelot-3 - */ - -/* Bus #0 IO and MEM space */ -#define OCELOT_3_PCI_IO_0_START 0xe0000000 -#define OCELOT_3_PCI_IO_0_SIZE 0x08000000 -#define OCELOT_3_PCI_MEM_0_START 0xc0000000 -#define OCELOT_3_PCI_MEM_0_SIZE 0x10000000 - -/* Bus #1 IO and MEM space */ -#define OCELOT_3_PCI_IO_1_START 0xe8000000 -#define OCELOT_3_PCI_IO_1_SIZE 0x08000000 -#define OCELOT_3_PCI_MEM_1_START 0xd0000000 -#define OCELOT_3_PCI_MEM_1_SIZE 0x10000000 - -static struct resource mv_pci_io_mem0_resource = { - .name = "MV64340 PCI0 IO MEM", - .start = OCELOT_3_PCI_IO_0_START, - .end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE - 1, - .flags = IORESOURCE_IO, -}; - -static struct resource mv_pci_io_mem1_resource = { - .name = "MV64340 PCI1 IO MEM", - .start = OCELOT_3_PCI_IO_1_START, - .end = OCELOT_3_PCI_IO_1_START + OCELOT_3_PCI_IO_1_SIZE - 1, - .flags = IORESOURCE_IO, -}; - -static struct resource mv_pci_mem0_resource = { - .name = "MV64340 PCI0 MEM", - .start = OCELOT_3_PCI_MEM_0_START, - .end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct resource mv_pci_mem1_resource = { - .name = "MV64340 PCI1 MEM", - .start = OCELOT_3_PCI_MEM_1_START, - .end = OCELOT_3_PCI_MEM_1_START + OCELOT_3_PCI_MEM_1_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct mv_pci_controller mv_bus0_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem0_resource, - .io_resource = &mv_pci_io_mem0_resource, - }, - .config_addr = MV64340_PCI_0_CONFIG_ADDR, - .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, -}; - -static struct mv_pci_controller mv_bus1_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem1_resource, - .io_resource = &mv_pci_io_mem1_resource, - }, - .config_addr = MV64340_PCI_1_CONFIG_ADDR, - .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, -}; - -static __init int __init ja_pci_init(void) -{ - uint32_t enable; - extern int pci_probe_only; - - /* PMON will assign PCI resources */ - pci_probe_only = 1; - - enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE); - /* - * We require at least one enabled I/O or PCI memory window or we - * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3. - */ - if (enable & (0x01 << 9) || enable & (0x01 << 10)) - register_pci_controller(&mv_bus0_controller.pcic); - - if (enable & (0x01 << 14) || enable & (0x01 << 15)) - register_pci_controller(&mv_bus1_controller.pcic); - - ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE + - OCELOT_3_PCI_IO_1_SIZE - 1; - - iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE + - OCELOT_3_PCI_MEM_1_SIZE - 1; - - set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */ - - return 0; -} - -arch_initcall(ja_pci_init); - -void __init plat_mem_setup(void) -{ - unsigned int tmpword; - - board_time_init = momenco_time_init; - - _machine_restart = momenco_ocelot_restart; - _machine_halt = momenco_ocelot_halt; - pm_power_off = momenco_ocelot_power_off; - - /* Wired TLB entries */ - setup_wired_tlb_entries(); - - /* shut down ethernet ports, just to be sure our memory doesn't get - * corrupted by random ethernet traffic. - */ - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); - do {} - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); - - /* Turn off the Bit-Error LED */ - OCELOT_FPGA_WRITE(0x80, CLR); - - tmpword = OCELOT_FPGA_READ(BOARDREV); - if (tmpword < 26) - printk("Momenco Ocelot-3: Board Assembly Rev. %c\n", - 'A'+tmpword); - else - printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n", - tmpword); - - tmpword = OCELOT_FPGA_READ(FPGA_REV); - printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_FPGA_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - switch (tmpword) { - case 0x1: - printk(" - Power-up reset\n"); - break; - case 0x2: - printk(" - Push-button reset\n"); - break; - case 0x4: - printk(" - cPCI bus reset\n"); - break; - case 0x8: - printk(" - Watchdog reset\n"); - break; - case 0x10: - printk(" - Software reset\n"); - break; - default: - printk(" - Unknown reset cause\n"); - } - reset_reason = tmpword; - OCELOT_FPGA_WRITE(0xff, RESET_STATUS); - - tmpword = OCELOT_FPGA_READ(CPCI_ID); - printk("cPCI ID register: 0x%02x\n", tmpword); - printk(" - Slot number: %d\n", tmpword & 0x1f); - printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); - printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); - - tmpword = OCELOT_FPGA_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1); - - /* Support for 128 MB memory */ - add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/Makefile mips/arch/mips/momentum/ocelot_c/Makefile --- mips-orig/arch/mips/momentum/ocelot_c/Makefile 2006-10-02 22:32:46.170757250 +0900 +++ mips/arch/mips/momentum/ocelot_c/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,8 +0,0 @@ -# -# Makefile for Momentum Computer's Ocelot-C and -CS boards. -# - -obj-y += cpci-irq.o irq.o prom.o reset.o \ - setup.o uart-irq.o - -obj-$(CONFIG_KGDB) += dbg_io.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/cpci-irq.c mips/arch/mips/momentum/ocelot_c/cpci-irq.c --- mips-orig/arch/mips/momentum/ocelot_c/cpci-irq.c 2006-10-02 22:32:46.170757250 +0900 +++ mips/arch/mips/momentum/ocelot_c/cpci-irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,152 +0,0 @@ -/* - * Copyright 2002 Momentum Computer - * Author: mdharm@momenco.com - * - * arch/mips/momentum/ocelot_c/cpci-irq.c - * Interrupt routines for cpci. Interrupt numbers are assigned from - * CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources). - * - * Note that the high-level software will need to be careful about using - * these interrupts. If this board is asserting a cPCI interrupt, it will - * also see the asserted interrupt. Care must be taken to avoid an - * interrupt flood. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "ocelot_c_fpga.h" - -#define CPCI_IRQ_BASE 8 - -static inline int ls1bit8(unsigned int x) -{ - int b = 7, s; - - s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s; - s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s; - s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s; - - return b; -} - -/* mask off an interrupt -- 0 is enable, 1 is disable */ -static inline void mask_cpci_irq(unsigned int irq) -{ - uint32_t value; - - value = OCELOT_FPGA_READ(INTMASK); - value |= 1 << (irq - CPCI_IRQ_BASE); - OCELOT_FPGA_WRITE(value, INTMASK); - - /* read the value back to assure that it's really been written */ - value = OCELOT_FPGA_READ(INTMASK); -} - -/* unmask an interrupt -- 0 is enable, 1 is disable */ -static inline void unmask_cpci_irq(unsigned int irq) -{ - uint32_t value; - - value = OCELOT_FPGA_READ(INTMASK); - value &= ~(1 << (irq - CPCI_IRQ_BASE)); - OCELOT_FPGA_WRITE(value, INTMASK); - - /* read the value back to assure that it's really been written */ - value = OCELOT_FPGA_READ(INTMASK); -} - -/* - * Enables the IRQ in the FPGA - */ -static void enable_cpci_irq(unsigned int irq) -{ - unmask_cpci_irq(irq); -} - -/* - * Initialize the IRQ in the FPGA - */ -static unsigned int startup_cpci_irq(unsigned int irq) -{ - unmask_cpci_irq(irq); - return 0; -} - -/* - * Disables the IRQ in the FPGA - */ -static void disable_cpci_irq(unsigned int irq) -{ - mask_cpci_irq(irq); -} - -/* - * Masks and ACKs an IRQ - */ -static void mask_and_ack_cpci_irq(unsigned int irq) -{ - mask_cpci_irq(irq); -} - -/* - * End IRQ processing - */ -static void end_cpci_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - unmask_cpci_irq(irq); -} - -/* - * Interrupt handler for interrupts coming from the FPGA chip. - * It could be built in ethernet ports etc... - */ -void ll_cpci_irq(struct pt_regs *regs) -{ - unsigned int irq_src, irq_mask; - - /* read the interrupt status registers */ - irq_src = OCELOT_FPGA_READ(INTSTAT); - irq_mask = OCELOT_FPGA_READ(INTMASK); - - /* mask for just the interrupts we want */ - irq_src &= ~irq_mask; - - do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs); -} - -#define shutdown_cpci_irq disable_cpci_irq - -struct irq_chip cpci_irq_type = { - .typename = "CPCI/FPGA", - .startup = startup_cpci_irq, - .shutdown = shutdown_cpci_irq, - .enable = enable_cpci_irq, - .disable = disable_cpci_irq, - .ack = mask_and_ack_cpci_irq, - .end = end_cpci_irq, -}; - -void cpci_irq_init(void) -{ - int i; - - /* Reset irq handlers pointers to NULL */ - for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 2; - irq_desc[i].chip = &cpci_irq_type; - } -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/dbg_io.c mips/arch/mips/momentum/ocelot_c/dbg_io.c --- mips-orig/arch/mips/momentum/ocelot_c/dbg_io.c 2006-10-02 22:32:46.170757250 +0900 +++ mips/arch/mips/momentum/ocelot_c/dbg_io.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,125 +0,0 @@ - -#ifdef CONFIG_KGDB - -#include /* For the serial port location and base baud */ - -/* --- CONFIG --- */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE OCELOT_SERIAL1_BASE -#define MAX_BAUD OCELOT_BASE_BAUD - -/* === END OF CONFIG === */ - -#define REG_OFFSET 4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/irq.c mips/arch/mips/momentum/ocelot_c/irq.c --- mips-orig/arch/mips/momentum/ocelot_c/irq.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_c/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,107 +0,0 @@ -/* - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void uart_irq_init(void); -extern void cpci_irq_init(void); - -static struct irqaction cascade_fpga = { - no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL -}; - -static struct irqaction cascade_mv64340 = { - no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL -}; - -extern void ll_uart_irq(struct pt_regs *regs); -extern void ll_cpci_irq(struct pt_regs *regs); - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP0) - do_IRQ(0, regs); - else if (pending & STATUSF_IP1) - do_IRQ(1, regs); - else if (pending & STATUSF_IP2) - do_IRQ(2, regs); - else if (pending & STATUSF_IP3) - ll_uart_irq(regs); - else if (pending & STATUSF_IP4) - do_IRQ(4, regs); - else if (pending & STATUSF_IP5) - ll_cpci_irq(regs); - else if (pending & STATUSF_IP6) - ll_mv64340_irq(regs); - else if (pending & STATUSF_IP7) - do_IRQ(7, regs); - else - spurious_interrupt(regs); -} - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM); - - mips_cpu_irq_init(0); - - /* set up the cascading interrupts */ - setup_irq(3, &cascade_fpga); - setup_irq(5, &cascade_fpga); - setup_irq(6, &cascade_mv64340); - - mv64340_irq_init(16); - uart_irq_init(); - cpci_irq_init(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h mips/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h --- mips-orig/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,59 +0,0 @@ -/* - * Ocelot-C Board Register Definitions - * - * (C) 2002 Momentum Computer Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - */ - -#ifndef __OCELOT_C_FPGA_H__ -#define __OCELOT_C_FPGA_H__ - - -#ifdef CONFIG_64BIT -#define OCELOT_C_CS0_ADDR (0xfffffffffc000000) -#else -#define OCELOT_C_CS0_ADDR (0xfc000000) -#endif - -#define OCELOT_C_REG_BOARDREV 0x0 -#define OCELOT_C_REG_FPGA_REV 0x1 -#define OCELOT_C_REG_FPGA_TYPE 0x2 -#define OCELOT_C_REG_RESET_STATUS 0x3 -#define OCELOT_C_REG_BOARD_STATUS 0x4 -#define OCELOT_C_REG_CPCI_ID 0x5 -#define OCELOT_C_REG_SET 0x6 -#define OCELOT_C_REG_CLR 0x7 -#define OCELOT_C_REG_EEPROM_MODE 0x9 -#define OCELOT_C_REG_INTMASK 0xa -#define OCELOT_C_REG_INTSTAT 0xb -#define OCELOT_C_REG_UART_INTMASK 0xc -#define OCELOT_C_REG_UART_INTSTAT 0xd -#define OCELOT_C_REG_INTSET 0xe -#define OCELOT_C_REG_INTCLR 0xf - -#define OCELOT_FPGA_WRITE(x, y) writeb(x, OCELOT_C_CS0_ADDR + OCELOT_C_REG_##y) -#define OCELOT_FPGA_READ(x) readb(OCELOT_C_CS0_ADDR + OCELOT_C_REG_##x) - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/prom.c mips/arch/mips/momentum/ocelot_c/prom.c --- mips-orig/arch/mips/momentum/ocelot_c/prom.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_c/prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,242 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "ocelot_c_fpga.h" - -struct callvectors* debug_vectors; - -extern unsigned long marvell_base; -extern unsigned long cpu_clock; - -#ifdef CONFIG_MV643XX_ETH -extern unsigned char prom_mac_addr_base[6]; -#endif - -const char *get_system_type(void) -{ -#ifdef CONFIG_CPU_SR71000 - return "Momentum Ocelot-CS"; -#else - return "Momentum Ocelot-C"; -#endif -} - -#ifdef CONFIG_MV643XX_ETH -static void burn_clocks(void) -{ - int i; - - /* this loop should burn at least 1us -- this should be plenty */ - for (i = 0; i < 0x10000; i++) - ; -} - -static u8 exchange_bit(u8 val, u8 cs) -{ - /* place the data */ - OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE); - burn_clocks(); - - /* turn the clock on */ - OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE); - burn_clocks(); - - /* turn the clock off and read-strobe */ - OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - - /* return the data */ - return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); -} - -void get_mac(char dest[6]) -{ - u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int i,j; - - for (i = 0; i < 12; i++) - exchange_bit(read_opcode[i], 1); - - for (j = 0; j < 6; j++) { - dest[j] = 0; - for (i = 0; i < 8; i++) { - dest[j] <<= 1; - dest[j] |= exchange_bit(0, 1); - } - } - - /* turn off CS */ - exchange_bit(0,0); -} -#endif - - -#ifdef CONFIG_64BIT - -unsigned long signext(unsigned long addr) -{ - addr &= 0xffffffff; - return (unsigned long)((int)addr); -} - -void *get_arg(unsigned long args, int arc) -{ - unsigned long ul; - unsigned char *puc, uc; - - args += (arc * 4); - ul = (unsigned long)signext(args); - puc = (unsigned char *)ul; - if (puc == 0) - return (void *)0; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - uc = *puc++; - ul = (unsigned long)uc; - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 24); -#else /* CONFIG_CPU_LITTLE_ENDIAN */ - uc = *puc++; - ul = ((unsigned long)uc) << 24; - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= ((unsigned long)uc); -#endif /* CONFIG_CPU_LITTLE_ENDIAN */ - ul = signext(ul); - return (void *)ul; -} - -char *arg64(unsigned long addrin, int arg_index) -{ - unsigned long args; - char *p; - args = signext(addrin); - p = (char *)get_arg(args, arg_index); - return p; -} -#endif /* CONFIG_64BIT */ - - -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - int i; - -#ifdef CONFIG_64BIT - char *ptr; - - printk("prom_init - MIPS64\n"); - /* save the PROM vectors for debugging use */ - debug_vectors = (struct callvectors *)signext((unsigned long)cv); - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - - for (i = 1; i < argc; i++) { - ptr = (char *)arg64((unsigned long)arg, i); - if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >= - sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ptr); - strcat(arcs_cmdline, " "); - } - i = 0; - while (1) { - ptr = (char *)arg64((unsigned long)env, i); - if (! ptr) - break; - - if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(ptr + strlen("gtbase="), - NULL, 16); - - if ((marvell_base & 0xffffffff00000000) == 0) - marvell_base |= 0xffffffff00000000; - - printk("marvell_base set to 0x%016lx\n", marvell_base); - } - if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(ptr + strlen("cpuclock="), - NULL, 10); - printk("cpu_clock set to %d\n", cpu_clock); - } - i++; - } - printk("arcs_cmdline: %s\n", arcs_cmdline); - -#else /* CONFIG_64BIT */ - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - while (*env) { - if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - } - if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(*env + strlen("cpuclock="), - NULL, 10); - } - env++; - } -#endif /* CONFIG_64BIT */ - - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_OCELOT_C; - -#ifdef CONFIG_MV643XX_ETH - /* get the base MAC address for on-board ethernet ports */ - get_mac(prom_mac_addr_base); -#endif - -#ifndef CONFIG_64BIT - debug_vectors->printf("Booting Linux kernel...\n"); -#endif -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/reset.c mips/arch/mips/momentum/ocelot_c/reset.c --- mips-orig/arch/mips/momentum/ocelot_c/reset.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_c/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,58 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - */ -#include -#include -#include -#include -#include -#include -#include -#include - -void momenco_ocelot_restart(char *command) -{ - /* base address of timekeeper portion of part */ - void *nvram = (void *) -#ifdef CONFIG_64BIT - 0xfffffffffc807000; -#else - 0xfc807000; -#endif - - /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ - writeb(0x84, nvram + 0xff7); - - /* wait for the watchdog to go off */ - mdelay(100+(1000/16)); - - /* if the watchdog fails for some reason, let people know */ - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_ocelot_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_ocelot_power_off(void) -{ - momenco_ocelot_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/setup.c mips/arch/mips/momentum/ocelot_c/setup.c --- mips-orig/arch/mips/momentum/ocelot_c/setup.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_c/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,368 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Momentum Computer Ocelot-C and -CS board dependent boot routines - * - * Copyright (C) 1996, 1997, 2001 Ralf Baechle - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: Matthew Dharm, Momentum Computer - * mdharm@momenco.com - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ocelot_c_fpga.h" - -unsigned long marvell_base; -extern unsigned long mv64340_sram_base; -unsigned long cpu_clock; - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_ocelot_restart(char *command); -extern void momenco_ocelot_halt(void); -extern void momenco_ocelot_power_off(void); - -void momenco_time_init(void); - -static char reset_reason; - -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask); - -static unsigned long ENTRYLO(unsigned long paddr) -{ - return ((paddr & PAGE_MASK) | - (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | - _CACHE_UNCACHED)) >> 6; -} - -/* setup code for a handoff from a version 2 PMON 2000 PROM */ -void PMON_v2_setup(void) -{ - /* Some wired TLB entries for the MV64340 and perhiperals. The - MV64340 is going to be hit on every IRQ anyway - there's - absolutely no point in letting it be a random TLB entry, as - it'll just cause needless churning of the TLB. And we use - the other half for the serial port, which is just a PITA - otherwise :) - - Device Physical Virtual - MV64340 Internal Regs 0xf4000000 0xf4000000 - Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000 - NVRAM (CS1) 0xfc800000 0xfc800000 - UARTs (CS2) 0xfd000000 0xfd000000 - Internal SRAM 0xfe000000 0xfe000000 - M-Systems DOC (CS3) 0xff000000 0xff000000 - */ - printk("PMON_v2_setup\n"); - -#ifdef CONFIG_64BIT - /* marvell and extra space */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K); - /* fpga, rtc, and uart */ - add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M); - /* m-sys and internal SRAM */ - add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M); - - marvell_base = 0xfffffffff4000000; - mv64340_sram_base = 0xfffffffffe000000; -#else - /* marvell and extra space */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K); - /* fpga, rtc, and uart */ - add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M); - /* m-sys and internal SRAM */ - add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M); - - marvell_base = 0xf4000000; - mv64340_sram_base = 0xfe000000; -#endif -} - -unsigned long m48t37y_get_time(void) -{ -#ifdef CONFIG_64BIT - unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000; -#else - unsigned char* rtc_base = (unsigned char*)0xfc800000; -#endif - unsigned int year, month, day, hour, min, sec; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - /* stop the update */ - rtc_base[0x7ff8] = 0x40; - - year = BCD2BIN(rtc_base[0x7fff]); - year += BCD2BIN(rtc_base[0x7ff1]) * 100; - - month = BCD2BIN(rtc_base[0x7ffe]); - - day = BCD2BIN(rtc_base[0x7ffd]); - - hour = BCD2BIN(rtc_base[0x7ffb]); - min = BCD2BIN(rtc_base[0x7ffa]); - sec = BCD2BIN(rtc_base[0x7ff9]); - - /* start the update */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return mktime(year, month, day, hour, min, sec); -} - -int m48t37y_set_time(unsigned long sec) -{ -#ifdef CONFIG_64BIT - unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000; -#else - unsigned char* rtc_base = (unsigned char*)0xfc800000; -#endif - struct rtc_time tm; - unsigned long flags; - - /* convert to a more useful format -- note months count from 0 */ - to_tm(sec, &tm); - tm.tm_mon += 1; - - spin_lock_irqsave(&rtc_lock, flags); - /* enable writing */ - rtc_base[0x7ff8] = 0x80; - - /* year */ - rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100); - rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100); - - /* month */ - rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon); - - /* day */ - rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday); - - /* hour/min/sec */ - rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour); - rtc_base[0x7ffa] = BIN2BCD(tm.tm_min); - rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec); - - /* day of week -- not really used, but let's keep it up-to-date */ - rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1); - - /* disable writing */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - -void __init plat_timer_setup(struct irqaction *irq) -{ - setup_irq(7, irq); -} - -void momenco_time_init(void) -{ -#ifdef CONFIG_CPU_SR71000 - mips_hpt_frequency = cpu_clock; -#elif defined(CONFIG_CPU_RM7000) - mips_hpt_frequency = cpu_clock / 2; -#else -#error Unknown CPU for this board -#endif - printk("momenco_time_init cpu_clock=%d\n", cpu_clock); - - rtc_mips_get_time = m48t37y_get_time; - rtc_mips_set_time = m48t37y_set_time; -} - -void __init plat_mem_setup(void) -{ - unsigned int tmpword; - - board_time_init = momenco_time_init; - - _machine_restart = momenco_ocelot_restart; - _machine_halt = momenco_ocelot_halt; - pm_power_off = momenco_ocelot_power_off; - - /* - * initrd_start = (unsigned long)ocelot_initrd_start; - * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; - * initrd_below_start_ok = 1; - */ - - /* do handoff reconfiguration */ - PMON_v2_setup(); - - /* shut down ethernet ports, just to be sure our memory doesn't get - * corrupted by random ethernet traffic. - */ - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); - do {} - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); - - /* Turn off the Bit-Error LED */ - OCELOT_FPGA_WRITE(0x80, CLR); - - tmpword = OCELOT_FPGA_READ(BOARDREV); -#ifdef CONFIG_CPU_SR71000 - if (tmpword < 26) - printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n", - 'A'+tmpword); - else - printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n", - tmpword); -#else - if (tmpword < 26) - printk("Momenco Ocelot-C: Board Assembly Rev. %c\n", - 'A'+tmpword); - else - printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n", - tmpword); -#endif - - tmpword = OCELOT_FPGA_READ(FPGA_REV); - printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_FPGA_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - switch (tmpword) { - case 0x1: - printk(" - Power-up reset\n"); - break; - case 0x2: - printk(" - Push-button reset\n"); - break; - case 0x4: - printk(" - cPCI bus reset\n"); - break; - case 0x8: - printk(" - Watchdog reset\n"); - break; - case 0x10: - printk(" - Software reset\n"); - break; - default: - printk(" - Unknown reset cause\n"); - } - reset_reason = tmpword; - OCELOT_FPGA_WRITE(0xff, RESET_STATUS); - - tmpword = OCELOT_FPGA_READ(CPCI_ID); - printk("cPCI ID register: 0x%02x\n", tmpword); - printk(" - Slot number: %d\n", tmpword & 0x1f); - printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); - printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); - - tmpword = OCELOT_FPGA_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); - printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); - - switch(tmpword &3) { - case 3: - /* 512MiB */ - add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM); - break; - case 2: - /* 256MiB */ - add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM); - break; - case 1: - /* 128MiB */ - add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM); - break; - case 0: - /* 1GiB -- needs CONFIG_HIGHMEM */ - add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM); - break; - } -} - -#ifndef CONFIG_64BIT -/* This needs to be one of the first initcalls, because no I/O port access - can work before this */ -static int io_base_ioremap(void) -{ - /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */ - void *io_remap_range = ioremap(0xc0000000, 0x30000000); - - if (!io_remap_range) { - panic("Could not ioremap I/O port range"); - } - printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range); - set_io_port_base(io_remap_range - 0xc0000000); - - return 0; -} - -module_init(io_base_ioremap); -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/uart-irq.c mips/arch/mips/momentum/ocelot_c/uart-irq.c --- mips-orig/arch/mips/momentum/ocelot_c/uart-irq.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_c/uart-irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,146 +0,0 @@ -/* - * Copyright 2002 Momentum Computer - * Author: mdharm@momenco.com - * - * arch/mips/momentum/ocelot_c/uart-irq.c - * Interrupt routines for UARTs. Interrupt numbers are assigned from - * 80 to 81 (2 interrupt sources). - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ocelot_c_fpga.h" - -static inline int ls1bit8(unsigned int x) -{ - int b = 7, s; - - s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s; - s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s; - s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s; - - return b; -} - -/* mask off an interrupt -- 0 is enable, 1 is disable */ -static inline void mask_uart_irq(unsigned int irq) -{ - uint8_t value; - - value = OCELOT_FPGA_READ(UART_INTMASK); - value |= 1 << (irq - 74); - OCELOT_FPGA_WRITE(value, UART_INTMASK); - - /* read the value back to assure that it's really been written */ - value = OCELOT_FPGA_READ(UART_INTMASK); -} - -/* unmask an interrupt -- 0 is enable, 1 is disable */ -static inline void unmask_uart_irq(unsigned int irq) -{ - uint8_t value; - - value = OCELOT_FPGA_READ(UART_INTMASK); - value &= ~(1 << (irq - 74)); - OCELOT_FPGA_WRITE(value, UART_INTMASK); - - /* read the value back to assure that it's really been written */ - value = OCELOT_FPGA_READ(UART_INTMASK); -} - -/* - * Enables the IRQ in the FPGA - */ -static void enable_uart_irq(unsigned int irq) -{ - unmask_uart_irq(irq); -} - -/* - * Initialize the IRQ in the FPGA - */ -static unsigned int startup_uart_irq(unsigned int irq) -{ - unmask_uart_irq(irq); - return 0; -} - -/* - * Disables the IRQ in the FPGA - */ -static void disable_uart_irq(unsigned int irq) -{ - mask_uart_irq(irq); -} - -/* - * Masks and ACKs an IRQ - */ -static void mask_and_ack_uart_irq(unsigned int irq) -{ - mask_uart_irq(irq); -} - -/* - * End IRQ processing - */ -static void end_uart_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - unmask_uart_irq(irq); -} - -/* - * Interrupt handler for interrupts coming from the FPGA chip. - */ -void ll_uart_irq(struct pt_regs *regs) -{ - unsigned int irq_src, irq_mask; - - /* read the interrupt status registers */ - irq_src = OCELOT_FPGA_READ(UART_INTSTAT); - irq_mask = OCELOT_FPGA_READ(UART_INTMASK); - - /* mask for just the interrupts we want */ - irq_src &= ~irq_mask; - - do_IRQ(ls1bit8(irq_src) + 74, regs); -} - -#define shutdown_uart_irq disable_uart_irq - -struct irq_chip uart_irq_type = { - .typename = "UART/FPGA", - .startup = startup_uart_irq, - .shutdown = shutdown_uart_irq, - .enable = enable_uart_irq, - .disable = disable_uart_irq, - .ack = mask_and_ack_uart_irq, - .end = end_uart_irq, -}; - -void uart_irq_init(void) -{ - /* Reset irq handlers pointers to NULL */ - irq_desc[80].status = IRQ_DISABLED; - irq_desc[80].action = 0; - irq_desc[80].depth = 2; - irq_desc[80].chip = &uart_irq_type; - - irq_desc[81].status = IRQ_DISABLED; - irq_desc[81].action = 0; - irq_desc[81].depth = 2; - irq_desc[81].chip = &uart_irq_type; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/Makefile mips/arch/mips/momentum/ocelot_g/Makefile --- mips-orig/arch/mips/momentum/ocelot_g/Makefile 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_g/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,8 +0,0 @@ -# -# Makefile for Momentum Computer's Ocelot-G board. -# - -obj-y += irq.o gt-irq.o prom.o reset.o setup.o -obj-$(CONFIG_KGDB) += dbg_io.o - -EXTRA_AFLAGS := $(CFLAGS) diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/dbg_io.c mips/arch/mips/momentum/ocelot_g/dbg_io.c --- mips-orig/arch/mips/momentum/ocelot_g/dbg_io.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_g/dbg_io.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,125 +0,0 @@ - -#ifdef CONFIG_KGDB - -#include /* For the serial port location and base baud */ - -/* --- CONFIG --- */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE OCELOT_SERIAL1_BASE -#define MAX_BAUD OCELOT_BASE_BAUD - -/* === END OF CONFIG === */ - -#define REG_OFFSET 4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/gt-irq.c mips/arch/mips/momentum/ocelot_g/gt-irq.c --- mips-orig/arch/mips/momentum/ocelot_g/gt-irq.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_g/gt-irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,213 +0,0 @@ -/* - * - * Copyright 2002 Momentum Computer - * Author: mdharm@momenco.com - * - * arch/mips/momentum/ocelot_g/gt_irq.c - * Interrupt routines for gt64240. Currently it only handles timer irq. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -unsigned long bus_clock; - -/* - * These are interrupt handlers for the GT on-chip interrupts. They - * all come in to the MIPS on a single interrupt line, and have to - * be handled and ack'ed differently than other MIPS interrupts. - */ - -#if CURRENTLY_UNUSED - -struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH]; -void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr); - -/* - * Hooks IRQ handler to the system. When the system is interrupted - * the interrupt service routine is called. - * - * Inputs : - * int_cause - The interrupt cause number. In EVB64120 two parameters - * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. - * bit_num - Indicates which bit number in the cause register - * isr_ptr - Pointer to the interrupt service routine - */ -void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr) -{ - irq_handlers[int_cause][bit_num].routine = isr_ptr; -} - - -/* - * Enables the IRQ on Galileo Chip - * - * Inputs : - * int_cause - The interrupt cause number. In EVB64120 two parameters - * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. - * bit_num - Indicates which bit number in the cause register - * - * Outputs : - * 1 if successful, 0 if failure - */ -int enable_galileo_irq(int int_cause, int bit_num) -{ - if (int_cause == INT_CAUSE_MAIN) - SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num)); - else if (int_cause == INT_CAUSE_HIGH) - SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER, - (1 << bit_num)); - else - return 0; - - return 1; -} - -/* - * Disables the IRQ on Galileo Chip - * - * Inputs : - * int_cause - The interrupt cause number. In EVB64120 two parameters - * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. - * bit_num - Indicates which bit number in the cause register - * - * Outputs : - * 1 if successful, 0 if failure - */ -int disable_galileo_irq(int int_cause, int bit_num) -{ - if (int_cause == INT_CAUSE_MAIN) - RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, - (1 << bit_num)); - else if (int_cause == INT_CAUSE_HIGH) - RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER, - (1 << bit_num)); - else - return 0; - return 1; -} -#endif /* UNUSED */ - -/* - * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#. - * - * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this - * routine can handle, for now. - * - * In the future, we'll route more interrupts to this pin, and that's why - * we keep this particular structure in the function. - */ - -static irqreturn_t gt64240_p0int_irq(int irq, void *dev, struct pt_regs *regs) -{ - uint32_t irq_src, irq_src_mask; - int handled; - - /* get the low interrupt cause register */ - irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER); - - /* get the mask register for this pin */ - irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW); - - /* mask off only the interrupts we're interested in */ - irq_src = irq_src & irq_src_mask; - - handled = IRQ_NONE; - - /* Check for timer interrupt */ - if (irq_src & 0x00000100) { - handled = IRQ_HANDLED; - irq_src &= ~0x00000100; - - /* Clear any pending cause bits */ - MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); - - /* handle the timer call */ - do_timer(1); -#ifndef CONFIG_SMP - update_process_times(user_mode(regs)); -#endif - } - - if (irq_src) { - printk(KERN_INFO - "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n", - irq_src); - } - - return handled; -} - -/* - * Initializes timer using galileo's built in timer. - */ - -/* - * This will ignore the standard MIPS timer interrupt handler - * that is passed in as *irq (=irq0 in ../kernel/time.c). - * We will do our own timer interrupt handling. - */ -void gt64240_time_init(void) -{ - static struct irqaction timer; - - /* Stop the timer -- we'll use timer #0 */ - MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0); - - /* Load timer value for 100 Hz */ - MV_WRITE(TIMER_COUNTER0, bus_clock / 100); - - /* - * Create the IRQ structure entry for the timer. Since we're too early - * in the boot process to use the "request_irq()" call, we'll hard-code - * the values to the correct interrupt line. - */ - timer.handler = >64240_p0int_irq; - timer.flags = IRQF_SHARED | IRQF_DISABLED; - timer.name = "timer"; - timer.dev_id = NULL; - timer.next = NULL; - timer.mask = CPU_MASK_NONE; - irq_desc[6].action = &timer; - - enable_irq(6); - - /* Clear any pending cause bits */ - MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); - - /* Enable the interrupt for timer 0 */ - MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1); - - /* Enable the timer interrupt for GT-64240 pin P0_INT# */ - MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100); - - /* Configure and start the timer */ - MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3); -} - -void gt64240_irq_init(void) -{ -#if CURRENTLY_UNUSED - int i, j; - - /* Reset irq handlers pointers to NULL */ - for (i = 0; i < MAX_CAUSE_REGS; i++) { - for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) { - irq_handlers[i][j].next = NULL; - irq_handlers[i][j].sync = 0; - irq_handlers[i][j].routine = NULL; - irq_handlers[i][j].data = NULL; - } - } -#endif -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/irq.c mips/arch/mips/momentum/ocelot_g/irq.c --- mips-orig/arch/mips/momentum/ocelot_g/irq.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_g/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP2) - do_IRQ(2, regs); - else if (pending & STATUSF_IP3) - do_IRQ(3, regs); - else if (pending & STATUSF_IP4) - do_IRQ(4, regs); - else if (pending & STATUSF_IP5) - do_IRQ(5, regs); - else if (pending & STATUSF_IP6) - do_IRQ(6, regs); - else if (pending & STATUSF_IP7) - do_IRQ(7, regs); - else { - /* - * Now look at the extended interrupts - */ - pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; - - if (pending & STATUSF_IP8) - do_IRQ(8, regs); - else if (pending & STATUSF_IP9) - do_IRQ(9, regs); - else if (pending & STATUSF_IP10) - do_IRQ(10, regs); - else if (pending & STATUSF_IP11) - do_IRQ(11, regs); - else - spurious_interrupt(regs); - } -} - -extern void gt64240_irq_init(void); - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM); - local_irq_disable(); - - mips_cpu_irq_init(0); - rm7k_cpu_irq_init(8); - - gt64240_irq_init(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/ocelot_pld.h mips/arch/mips/momentum/ocelot_g/ocelot_pld.h --- mips-orig/arch/mips/momentum/ocelot_g/ocelot_pld.h 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_g/ocelot_pld.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,30 +0,0 @@ -/* - * Ocelot Board Register Definitions - * - * (C) 2001 Red Hat, Inc. - * - * GPL'd - */ -#ifndef __MOMENCO_OCELOT_PLD_H__ -#define __MOMENCO_OCELOT_PLD_H__ - -#define OCELOT_CS0_ADDR (0xfc000000) - -#define OCELOT_REG_BOARDREV (0) -#define OCELOT_REG_PLD1_ID (1) -#define OCELOT_REG_PLD2_ID (2) -#define OCELOT_REG_RESET_STATUS (3) -#define OCELOT_REG_BOARD_STATUS (4) -#define OCELOT_REG_CPCI_ID (5) -#define OCELOT_REG_I2C_CTRL (8) -#define OCELOT_REG_EEPROM_MODE (9) -#define OCELOT_REG_INTMASK (10) -#define OCELOT_REG_INTSTATUS (11) -#define OCELOT_REG_INTSET (12) -#define OCELOT_REG_INTCLR (13) - -#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y) -#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x) - - -#endif /* __MOMENCO_OCELOT_PLD_H__ */ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/prom.c mips/arch/mips/momentum/ocelot_g/prom.c --- mips-orig/arch/mips/momentum/ocelot_g/prom.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_g/prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,85 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "ocelot_pld.h" - -struct callvectors* debug_vectors; - -extern unsigned long marvell_base; -extern unsigned long bus_clock; - -#ifdef CONFIG_GALILLEO_GT64240_ETH -extern unsigned char prom_mac_addr_base[6]; -#endif - -const char *get_system_type(void) -{ - return "Momentum Ocelot"; -} - -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - int i; - - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_OCELOT_G; - -#ifdef CONFIG_GALILLEO_GT64240_ETH - /* get the base MAC address for on-board ethernet ports */ - memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6); -#endif - - while (*env) { - if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - } - if (strncmp("busclock", *env, strlen("busclock")) == 0) { - bus_clock = simple_strtol(*env + strlen("busclock="), - NULL, 10); - } - env++; - } -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/reset.c mips/arch/mips/momentum/ocelot_g/reset.c --- mips-orig/arch/mips/momentum/ocelot_g/reset.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_g/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,47 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - */ -#include -#include -#include -#include -#include -#include -#include -#include - -void momenco_ocelot_restart(char *command) -{ - void *nvram = ioremap_nocache(0x2c807000, 0x1000); - - if (!nvram) { - printk(KERN_NOTICE "ioremap of reset register failed\n"); - return; - } - writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to - assert reset in 1/16 second */ - mdelay(10+(1000/16)); - iounmap(nvram); - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_ocelot_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_ocelot_power_off(void) -{ - momenco_ocelot_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/setup.c mips/arch/mips/momentum/ocelot_g/setup.c --- mips-orig/arch/mips/momentum/ocelot_g/setup.c 2006-10-02 22:32:46.174757500 +0900 +++ mips/arch/mips/momentum/ocelot_g/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,263 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines - * - * Copyright (C) 1996, 1997, 2001 Ralf Baechle - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: Matthew Dharm, Momentum Computer - * mdharm@momenco.com - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ocelot_pld.h" - -#ifdef CONFIG_GALILLEO_GT64240_ETH -extern unsigned char prom_mac_addr_base[6]; -#endif - -unsigned long marvell_base; - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_ocelot_restart(char *command); -extern void momenco_ocelot_halt(void); -extern void momenco_ocelot_power_off(void); - -extern void gt64240_time_init(void); -extern void momenco_ocelot_irq_setup(void); - -static char reset_reason; - -static unsigned long ENTRYLO(unsigned long paddr) -{ - return ((paddr & PAGE_MASK) | - (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | - _CACHE_UNCACHED)) >> 6; -} - -/* setup code for a handoff from a version 2 PMON 2000 PROM */ -void PMON_v2_setup(void) -{ - /* A wired TLB entry for the GT64240 and the serial port. The - GT64240 is going to be hit on every IRQ anyway - there's - absolutely no point in letting it be a random TLB entry, as - it'll just cause needless churning of the TLB. And we use - the other half for the serial port, which is just a PITA - otherwise :) - - Device Physical Virtual - GT64240 Internal Regs 0xf4000000 0xe0000000 - UARTs (CS2) 0xfd000000 0xe0001000 - */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), - 0xf4000000, PM_64K); - add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000), - 0xfd000000, PM_4K); - - /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM - in the CS[012] region. We can't use ioremap() yet. The NVRAM - is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. - - Ocelot PLD (CS0) 0xfc000000 0xe0020000 - NVRAM (CS1) 0xfc800000 0xe0030000 - */ - add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000), - 0xfc000000, PM_64K); - add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000), - 0xfc800000, PM_64K); - - marvell_base = 0xf4000000; -} - -extern int rm7k_tcache_enabled; - -/* - * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() - */ -#define Page_Invalidate_T 0x16 -static void __init setup_l3cache(unsigned long size) -{ - int register i; - - printk("Enabling L3 cache..."); - - /* Enable the L3 cache in the GT64120A's CPU Configuration register */ - MV_WRITE(0, MV_READ(0) | (1<<14)); - - /* Enable the L3 cache in the CPU */ - set_c0_config(1<<12 /* CONF_TE */); - - /* Clear the cache */ - write_c0_taglo(0); - write_c0_taghi(0); - - for (i=0; i < size; i+= 4096) { - __asm__ __volatile__ ( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (KSEG0ADDR(i)), - "i" (Page_Invalidate_T)); - } - - /* Let the RM7000 MM code know that the tertiary cache is enabled */ - rm7k_tcache_enabled = 1; - - printk("Done\n"); -} - -void __init plat_mem_setup(void) -{ - void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache); - unsigned int tmpword; - - board_time_init = gt64240_time_init; - - _machine_restart = momenco_ocelot_restart; - _machine_halt = momenco_ocelot_halt; - pm_power_off = momenco_ocelot_power_off; - - /* - * initrd_start = (unsigned long)ocelot_initrd_start; - * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; - * initrd_below_start_ok = 1; - */ - - /* do handoff reconfiguration */ - PMON_v2_setup(); - -#ifdef CONFIG_GALILLEO_GT64240_ETH - /* get the mac addr */ - memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6); -#endif - - /* Turn off the Bit-Error LED */ - OCELOT_PLD_WRITE(0x80, INTCLR); - - tmpword = OCELOT_PLD_READ(BOARDREV); - if (tmpword < 26) - printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword); - else - printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword); - - tmpword = OCELOT_PLD_READ(PLD1_ID); - printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_PLD_READ(PLD2_ID); - printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_PLD_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - reset_reason = tmpword; - OCELOT_PLD_WRITE(0xff, RESET_STATUS); - - tmpword = OCELOT_PLD_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not"); - printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); - printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); - - if (tmpword&12) - l3func((1<<(((tmpword&12) >> 2)+20))); - - switch(tmpword &3) { - case 3: - /* 512MiB -- two banks of 256MiB */ - add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM); -/* - add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM); -*/ - break; - case 2: - /* 256MiB -- two banks of 128MiB */ - add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM); - add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM); - break; - case 1: - /* 128MiB -- 64MiB per bank */ - add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM); - add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); - break; - case 0: - /* 64MiB */ - add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM); - break; - } - - /* FIXME: Fix up the DiskOnChip mapping */ - MV_WRITE(0x468, 0xfef73); -} - -/* This needs to be one of the first initcalls, because no I/O port access - can work before this */ - -static int io_base_ioremap(void) -{ - /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */ - unsigned long io_remap_range; - - io_remap_range = (unsigned long) ioremap(0xc0000000, 0x30000000); - if (!io_remap_range) - panic("Could not ioremap I/O port range"); - - set_io_port_base(io_remap_range - 0xc0000000); - - return 0; -} - -module_init(io_base_ioremap); diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/Makefile mips/arch/mips/pci/Makefile --- mips-orig/arch/mips/pci/Makefile 2006-10-02 22:40:23.607345250 +0900 +++ mips/arch/mips/pci/Makefile 2006-10-02 22:40:29.423708750 +0900 @@ -11,7 +11,6 @@ obj-$(CONFIG_ITE_BOARD_GEN) += ops-it817 obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o -obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o obj-$(CONFIG_MIPS_MSC) += ops-msc.o obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o @@ -34,10 +33,6 @@ obj-$(CONFIG_SOC_AU1500) += fixup-au1000 obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o -obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o -obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o -obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o -obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ pci-yosemite.o obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ocelot-c.c mips/arch/mips/pci/fixup-ocelot-c.c --- mips-orig/arch/mips/pci/fixup-ocelot-c.c 2006-10-02 22:32:46.178757750 +0900 +++ mips/arch/mips/pci/fixup-ocelot-c.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,41 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Based on work for the Linux port to the Ocelot board, which is - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/momentum/ocelot_g/pci.c - * Board-specific PCI routines for mv64340 controller. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) - return 2; /* PCI-X A */ - if (bus == 1 && slot == 1) - return 12; /* PCI-X B */ - if (bus == 1 && slot == 2) - return 4; /* PCI B */ - -return 0; - panic("Whooops in pcibios_map_irq"); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ocelot-g.c mips/arch/mips/pci/fixup-ocelot-g.c --- mips-orig/arch/mips/pci/fixup-ocelot-g.c 2006-10-02 22:32:46.178757750 +0900 +++ mips/arch/mips/pci/fixup-ocelot-g.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,37 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) - */ -#include -#include -#include -#include - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) /* Intel 82543 Gigabit MAC */ - return 2; /* irq_nr is 2 for INT0 */ - - if (bus == 0 && slot == 2) /* Intel 82543 Gigabit MAC */ - return 3; /* irq_nr is 3 for INT1 */ - - if (bus == 1 && slot == 3) /* Intel 21555 bridge */ - return 5; /* irq_nr is 8 for INT6 */ - - if (bus == 1 && slot == 4) /* PMC Slot */ - return 9; /* irq_nr is 9 for INT7 */ - - return -1; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ocelot.c mips/arch/mips/pci/fixup-ocelot.c --- mips-orig/arch/mips/pci/fixup-ocelot.c 2006-10-02 22:32:46.178757750 +0900 +++ mips/arch/mips/pci/fixup-ocelot.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,75 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/gt64120/momenco_ocelot/pci.c - * Board-specific PCI routines for gt64120 controller. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include - - -void __devinit pcibios_fixup_bus(struct pci_bus *bus) -{ - struct pci_bus *current_bus = bus; - struct pci_dev *devices; - struct list_head *devices_link; - u16 cmd; - - list_for_each(devices_link, &(current_bus->devices)) { - - devices = pci_dev_b(devices_link); - if (devices == NULL) - continue; - - if (PCI_SLOT(devices->devfn) == 1) { - /* - * Slot 1 is primary ether port, i82559 - * we double-check against that assumption - */ - if ((devices->vendor != 0x8086) || - (devices->device != 0x1209)) { - panic("pcibios_fixup_bus: found " - "unexpected PCI device in slot 1."); - } - devices->irq = 2; /* irq_nr is 2 for INT0 */ - } else if (PCI_SLOT(devices->devfn) == 2) { - /* - * Slot 2 is secondary ether port, i21143 - * we double-check against that assumption - */ - if ((devices->vendor != 0x1011) || - (devices->device != 0x19)) { - panic("galileo_pcibios_fixup_bus: " - "found unexpected PCI device in slot 2."); - } - devices->irq = 3; /* irq_nr is 3 for INT1 */ - } else if (PCI_SLOT(devices->devfn) == 4) { - /* PMC Slot 1 */ - devices->irq = 8; /* irq_nr is 8 for INT6 */ - } else if (PCI_SLOT(devices->devfn) == 5) { - /* PMC Slot 1 */ - devices->irq = 9; /* irq_nr is 9 for INT7 */ - } else { - /* We don't have assign interrupts for other devices. */ - devices->irq = 0xff; - } - - /* Assign an interrupt number for the device */ - bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, - devices->irq); - - /* enable master */ - bus->ops->read_word(devices, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_MASTER; - bus->ops->write_word(devices, PCI_COMMAND, cmd); - } -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ocelot3.c mips/arch/mips/pci/fixup-ocelot3.c --- mips-orig/arch/mips/pci/fixup-ocelot3.c 2006-10-02 22:32:46.178757750 +0900 +++ mips/arch/mips/pci/fixup-ocelot3.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,41 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 Montavista Software Inc. - * Author: Manish Lachwani (mlachwani@mvista.com) - * - * Looking at the schematics for the Ocelot-3 board, there are - * two PCI busses and each bus has two PCI slots. - */ -#include -#include -#include -#include - -/* - * Do platform specific device initialization at - * pci_enable_device() time - */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) - return 2; /* PCI-X A */ - if (bus == 0 && slot == 2) - return 3; /* PCI-X B */ - if (bus == 1 && slot == 1) - return 4; /* PCI A */ - if (bus == 1 && slot == 2) - return 5; /* PCI B */ - -return 0; - panic("Whooops in pcibios_map_irq"); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/ops-marvell.c mips/arch/mips/pci/ops-marvell.c --- mips-orig/arch/mips/pci/ops-marvell.c 2006-10-02 22:32:46.210759750 +0900 +++ mips/arch/mips/pci/ops-marvell.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,93 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) - */ -#include -#include -#include - -#include - -static int mv_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - struct mv_pci_controller *mvbc = bus->sysdata; - unsigned long address_reg, data_reg; - u32 address; - - address_reg = mvbc->config_addr; - data_reg = mvbc->config_vreg; - - /* Accessing device 31 crashes those Marvells. Since years. - Will they ever make sane controllers ... */ - if (PCI_SLOT(devfn) == 31) - return PCIBIOS_DEVICE_NOT_FOUND; - - address = (bus->number << 16) | (devfn << 8) | - (where & 0xfc) | 0x80000000; - - /* start the configuration cycle */ - MV_WRITE(address_reg, address); - - switch (size) { - case 1: - *val = MV_READ_8(data_reg + (where & 0x3)); - break; - - case 2: - *val = MV_READ_16(data_reg + (where & 0x3)); - break; - - case 4: - *val = MV_READ(data_reg); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int mv_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - struct mv_pci_controller *mvbc = bus->sysdata; - unsigned long address_reg, data_reg; - u32 address; - - address_reg = mvbc->config_addr; - data_reg = mvbc->config_vreg; - - /* Accessing device 31 crashes those Marvells. Since years. - Will they ever make sane controllers ... */ - if (PCI_SLOT(devfn) == 31) - return PCIBIOS_DEVICE_NOT_FOUND; - - address = (bus->number << 16) | (devfn << 8) | - (where & 0xfc) | 0x80000000; - - /* start the configuration cycle */ - MV_WRITE(address_reg, address); - - switch (size) { - case 1: - MV_WRITE_8(data_reg + (where & 0x3), val); - break; - - case 2: - MV_WRITE_16(data_reg + (where & 0x3), val); - break; - - case 4: - MV_WRITE(data_reg, val); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops mv_pci_ops = { - .read = mv_read_config, - .write = mv_write_config -}; diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/pci-ocelot-c.c mips/arch/mips/pci/pci-ocelot-c.c --- mips-orig/arch/mips/pci/pci-ocelot-c.c 2006-10-02 22:32:46.214760000 +0900 +++ mips/arch/mips/pci/pci-ocelot-c.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,145 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004, 06 by Ralf Baechle (ralf@linux-mips.org) - */ - -#include -#include -#include - -#include - -#include - -/* - * We assume the address ranges have already been setup appropriately by - * the firmware. PMON in case of the Ocelot C does that. - */ -static struct resource mv_pci_io_mem0_resource = { - .name = "MV64340 PCI0 IO MEM", - .flags = IORESOURCE_IO -}; - -static struct resource mv_pci_mem0_resource = { - .name = "MV64340 PCI0 MEM", - .flags = IORESOURCE_MEM -}; - -static struct mv_pci_controller mv_bus0_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem0_resource, - .io_resource = &mv_pci_io_mem0_resource, - }, - .config_addr = MV64340_PCI_0_CONFIG_ADDR, - .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, -}; - -static uint32_t mv_io_base, mv_io_size; - -static void mv64340_pci0_init(void) -{ - uint32_t mem0_base, mem0_size; - uint32_t io_base, io_size; - - io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16; - io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16; - mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16; - mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16; - - mv_pci_io_mem0_resource.start = 0; - mv_pci_io_mem0_resource.end = io_size - 1; - mv_pci_mem0_resource.start = mem0_base; - mv_pci_mem0_resource.end = mem0_base + mem0_size - 1; - mv_bus0_controller.pcic.mem_offset = mem0_base; - mv_bus0_controller.pcic.io_offset = 0; - - ioport_resource.end = io_size - 1; - - register_pci_controller(&mv_bus0_controller.pcic); - - mv_io_base = io_base; - mv_io_size = io_size; -} - -static struct resource mv_pci_io_mem1_resource = { - .name = "MV64340 PCI1 IO MEM", - .flags = IORESOURCE_IO -}; - -static struct resource mv_pci_mem1_resource = { - .name = "MV64340 PCI1 MEM", - .flags = IORESOURCE_MEM -}; - -static struct mv_pci_controller mv_bus1_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem1_resource, - .io_resource = &mv_pci_io_mem1_resource, - }, - .config_addr = MV64340_PCI_1_CONFIG_ADDR, - .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, -}; - -static __init void mv64340_pci1_init(void) -{ - uint32_t mem0_base, mem0_size; - uint32_t io_base, io_size; - - io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16; - io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16; - mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16; - mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16; - - /* - * Here we assume the I/O window of second bus to be contiguous with - * the first. A gap is no problem but would waste address space for - * remapping the port space. - */ - mv_pci_io_mem1_resource.start = mv_io_size; - mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1; - mv_pci_mem1_resource.start = mem0_base; - mv_pci_mem1_resource.end = mem0_base + mem0_size - 1; - mv_bus1_controller.pcic.mem_offset = mem0_base; - mv_bus1_controller.pcic.io_offset = 0; - - ioport_resource.end = io_base + io_size -mv_io_base - 1; - - register_pci_controller(&mv_bus1_controller.pcic); - - mv_io_size = io_base + io_size - mv_io_base; -} - -static __init int __init ocelot_c_pci_init(void) -{ - unsigned long io_v_base; - uint32_t enable; - - enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE); - - /* - * We require at least one enabled I/O or PCI memory window or we - * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3. - */ - if (enable & (0x01 << 9) || enable & (0x01 << 10)) - mv64340_pci0_init(); - - if (enable & (0x01 << 14) || enable & (0x01 << 15)) - mv64340_pci1_init(); - - if (mv_io_size) { - io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size); - if (!io_v_base) - panic("Could not ioremap I/O port range"); - - set_io_port_base(io_v_base); - } - - return 0; -} - -arch_initcall(ocelot_c_pci_init); diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/pci-ocelot-g.c mips/arch/mips/pci/pci-ocelot-g.c --- mips-orig/arch/mips/pci/pci-ocelot-g.c 2006-10-02 22:32:46.214760000 +0900 +++ mips/arch/mips/pci/pci-ocelot-g.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,97 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This doesn't really fly - but I don't have a GT64240 system for testing. - */ -#include -#include -#include -#include -#include - -/* - * We assume these address ranges have been programmed into the GT-64240 by - * the firmware. PMON in case of the Ocelot G does that. Note the size of - * the I/O range is completly stupid; I/O mappings are limited to at most - * 256 bytes by the PCI spec and deprecated; and just to make things worse - * apparently many devices don't decode more than 64k of I/O space. - */ - -#define gt_io_size 0x20000000UL -#define gt_io_base 0xe0000000UL - -static struct resource gt_pci_mem0_resource = { - .name = "MV64240 PCI0 MEM", - .start = 0xc0000000UL, - .end = 0xcfffffffUL, - .flags = IORESOURCE_MEM -}; - -static struct resource gt_pci_io_mem0_resource = { - .name = "MV64240 PCI0 IO MEM", - .start = 0xe0000000UL, - .end = 0xefffffffUL, - .flags = IORESOURCE_IO -}; - -static struct mv_pci_controller gt_bus0_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = >_pci_mem0_resource, - .mem_offset = 0xc0000000UL, - .io_resource = >_pci_io_mem0_resource, - .io_offset = 0x00000000UL - }, - .config_addr = PCI_0CONFIGURATION_ADDRESS, - .config_vreg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, -}; - -static struct resource gt_pci_mem1_resource = { - .name = "MV64240 PCI1 MEM", - .start = 0xd0000000UL, - .end = 0xdfffffffUL, - .flags = IORESOURCE_MEM -}; - -static struct resource gt_pci_io_mem1_resource = { - .name = "MV64240 PCI1 IO MEM", - .start = 0xf0000000UL, - .end = 0xffffffffUL, - .flags = IORESOURCE_IO -}; - -static struct mv_pci_controller gt_bus1_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = >_pci_mem1_resource, - .mem_offset = 0xd0000000UL, - .io_resource = >_pci_io_mem1_resource, - .io_offset = 0x10000000UL - }, - .config_addr = PCI_1CONFIGURATION_ADDRESS, - .config_vreg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, -}; - -static __init int __init ocelot_g_pci_init(void) -{ - unsigned long io_v_base; - - if (gt_io_size) { - io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size); - if (!io_v_base) - panic("Could not ioremap I/O port range"); - - set_io_port_base(io_v_base); - } - - register_pci_controller(>_bus0_controller.pcic); - register_pci_controller(>_bus1_controller.pcic); - - return 0; -} - -arch_initcall(ocelot_g_pci_init); diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/pci-ocelot.c mips/arch/mips/pci/pci-ocelot.c --- mips-orig/arch/mips/pci/pci-ocelot.c 2006-10-02 22:32:46.214760000 +0900 +++ mips/arch/mips/pci/pci-ocelot.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,107 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Galileo Evaluation Boards PCI support. - * - * The general-purpose functions to read/write and configure the GT64120A's - * PCI registers (function names start with pci0 or pci1) are either direct - * copies of functions written by Galileo Technology, or are modifications - * of their functions to work with Linux 2.4 vs Linux 2.2. These functions - * are Copyright - Galileo Technology. - * - * Other functions are derived from other MIPS PCI implementations, or were - * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static inline unsigned int pci0ReadConfigReg(unsigned int offset) -{ - unsigned int DataForRegCf8; - unsigned int data; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - GT_READ(GT_PCI0_CFGDATA_OFS, &data); - - return data; -} - -static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data) -{ - unsigned int DataForRegCf8; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - GT_WRITE(GT_PCI0_CFGDATA_OFS, data); -} - -static struct resource ocelot_mem_resource = { - start = GT_PCI_MEM_BASE; - end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1; -}; - -static struct resource ocelot_io_resource = { - start = GT_PCI_IO_BASE; - end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; -}; - -static struct pci_controller ocelot_pci_controller = { - .pci_ops = gt64120_pci_ops; - .mem_resource = &ocelot_mem_resource; - .io_resource = &ocelot_io_resource; -}; - -static int __init ocelot_pcibios_init(void) -{ - u32 tmp; - - GT_READ(GT_PCI0_CMD_OFS, &tmp); - GT_READ(GT_PCI0_BARE_OFS, &tmp); - - /* - * You have to enable bus mastering to configure any other - * card on the bus. - */ - tmp = pci0ReadConfigReg(PCI_COMMAND); - tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - pci0WriteConfigReg(PCI_COMMAND, tmp); - - register_pci_controller(&ocelot_pci_controller); -} - -arch_initcall(ocelot_pcibios_init); diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/bootinfo.h mips/include/asm-mips/bootinfo.h --- mips-orig/include/asm-mips/bootinfo.h 2006-10-02 22:40:23.607345250 +0900 +++ mips/include/asm-mips/bootinfo.h 2006-10-02 22:40:29.427709000 +0900 @@ -115,15 +115,6 @@ #define MACH_EV64120A 0 /* EV64120A */ /* - * Valid machtype for group MOMENCO - */ -#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ -#define MACH_MOMENCO_OCELOT 0 -#define MACH_MOMENCO_OCELOT_G 1 -#define MACH_MOMENCO_OCELOT_C 2 -#define MACH_MOMENCO_OCELOT_3 4 - -/* * Valid machtype for group ITE */ #define MACH_GROUP_ITE 13 /* ITE Semi Eval Boards */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h mips/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h --- mips-orig/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h 2006-10-02 22:33:09.484214250 +0900 +++ mips/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,48 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * Copyright (C) 2004 Ralf Baechle - */ -#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H - -/* - * Momentum Ocelot-3 is based on Rm7900 processor which - * is based on the E9000 core. - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_icache_snoops_remote_store 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 32 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/marvell.h mips/include/asm-mips/marvell.h --- mips-orig/include/asm-mips/marvell.h 2006-10-02 22:33:09.492214750 +0900 +++ mips/include/asm-mips/marvell.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,58 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MARVELL_H -#define __ASM_MIPS_MARVELL_H - -#include - -#include - -extern unsigned long marvell_base; - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. - */ -#define __MV_READ(ofs) \ - (*(volatile u32 *)(marvell_base+(ofs))) -#define __MV_WRITE(ofs, data) \ - do { *(volatile u32 *)(marvell_base+(ofs)) = (data); } while (0) - -#define MV_READ(ofs) le32_to_cpu(__MV_READ(ofs)) -#define MV_WRITE(ofs, data) __MV_WRITE(ofs, cpu_to_le32(data)) - -#define MV_READ_16(ofs) \ - le16_to_cpu(*(volatile u16 *)(marvell_base+(ofs))) -#define MV_WRITE_16(ofs, data) \ - *(volatile u16 *)(marvell_base+(ofs)) = cpu_to_le16(data) - -#define MV_READ_8(ofs) \ - *(volatile u8 *)(marvell_base+(ofs)) -#define MV_WRITE_8(ofs, data) \ - *(volatile u8 *)(marvell_base+(ofs)) = data - -#define MV_SET_REG_BITS(ofs, bits) \ - (*((volatile u32 *)(marvell_base + (ofs)))) |= ((u32)cpu_to_le32(bits)) -#define MV_RESET_REG_BITS(ofs, bits) \ - (*((volatile u32 *)(marvell_base + (ofs)))) &= ~((u32)cpu_to_le32(bits)) - -extern struct pci_ops mv_pci_ops; - -struct mv_pci_controller { - struct pci_controller pcic; - - /* - * GT-64240/MV-64340 specific, per host bus information - */ - unsigned long config_addr; - unsigned long config_vreg; -}; - -extern void ll_mv64340_irq(struct pt_regs *regs); - -#endif /* __ASM_MIPS_MARVELL_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/serial.h mips/include/asm-mips/serial.h --- mips-orig/include/asm-mips/serial.h 2006-10-02 22:40:23.743353750 +0900 +++ mips/include/asm-mips/serial.h 2006-10-02 22:40:29.439709750 +0900 @@ -113,86 +113,6 @@ #define STD_SERIAL_PORT_DEFNS #endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ -#ifdef CONFIG_MOMENCO_OCELOT_3 -#define OCELOT_3_BASE_BAUD ( 20000000 / 16 ) -#define OCELOT_3_SERIAL_IRQ 6 -#define OCELOT_3_SERIAL_BASE (signed)0xfd000020 - -#define _OCELOT_3_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, iomem_reg_shift: 2, \ - io_type: SERIAL_IO_MEM } - -#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ - _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE) -#else -#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_MOMENCO_OCELOT -/* Ordinary NS16552 duart with a 20MHz crystal. */ -#define OCELOT_BASE_BAUD ( 20000000 / 16 ) - -#define OCELOT_SERIAL1_IRQ 4 -#define OCELOT_SERIAL1_BASE 0xe0001020 - -#define _OCELOT_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM } -#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ - _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE) -#else -#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_MOMENCO_OCELOT_G -/* Ordinary NS16552 duart with a 20MHz crystal. */ -#define OCELOT_G_BASE_BAUD ( 20000000 / 16 ) - -#define OCELOT_G_SERIAL1_IRQ 4 -#if 0 -#define OCELOT_G_SERIAL1_BASE 0xe0001020 -#else -#define OCELOT_G_SERIAL1_BASE 0xfd000020 -#endif - -#define _OCELOT_G_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\ - .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM } -#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ - _OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE) -#else -#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_MOMENCO_OCELOT_C -/* Ordinary NS16552 duart with a 20MHz crystal. */ -#define OCELOT_C_BASE_BAUD ( 20000000 / 16 ) - -#define OCELOT_C_SERIAL1_IRQ 80 -#define OCELOT_C_SERIAL1_BASE 0xfd000020 - -#define OCELOT_C_SERIAL2_IRQ 81 -#define OCELOT_C_SERIAL2_BASE 0xfd000000 - -#define _OCELOT_C_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_C_BASE_BAUD, \ - .irq = (int), \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM \ - } -#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ - _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \ - _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE) -#else -#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS -#endif - #ifdef CONFIG_DDB5477 #include #define DDB5477_SERIAL_PORT_DEFNS \ @@ -224,10 +144,6 @@ ITE_SERIAL_PORT_DEFNS \ IVR_SERIAL_PORT_DEFNS \ JAZZ_SERIAL_PORT_DEFNS \ - STD_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS + STD_SERIAL_PORT_DEFNS #endif /* _ASM_SERIAL_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/war.h mips/include/asm-mips/war.h --- mips-orig/include/asm-mips/war.h 2006-10-02 22:40:23.743353750 +0900 +++ mips/include/asm-mips/war.h 2006-10-02 22:40:29.439709750 +0900 @@ -180,8 +180,7 @@ * where invalid instructions in the same I-cache line worth of instructions * being fetched may case spurious exceptions. */ -#if defined(CONFIG_MOMENCO_OCELOT_3) || defined(CONFIG_PMC_YOSEMITE) || \ - defined(CONFIG_BASLER_EXCITE) +#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) #define ICACHE_REFILLS_WORKAROUND_WAR 1 #endif From yoichi_yuasa@tripeaks.co.jp Mon Oct 2 15:21:07 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Oct 2006 15:21:13 +0100 (BST) Received: from mo31.po.2iij.net ([210.128.50.54]:55372 "EHLO mo31.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20038778AbWJBOUM (ORCPT ); Mon, 2 Oct 2006 15:20:12 +0100 Received: by mo.po.2iij.net (mo31) id k92EK89B039210; Mon, 2 Oct 2006 23:20:08 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox33) id k92EK2g9030463 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 2 Oct 2006 23:20:03 +0900 (JST) Date: Mon, 2 Oct 2006 23:19:00 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH] remove IT8172-based platforms, ITE 8172G and Globespan IVR support Message-Id: <20061002231900.6c6b51a3.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12766 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, This patch has removed IT8172-based platforms, ITE 8172G and Globespan IVR support. It was scheduled to be removed after 2.6.18 released. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/Documentation/feature-removal-schedule.txt mips/Documentation/feature-removal-schedule.txt --- mips-orig/Documentation/feature-removal-schedule.txt 2006-10-02 22:43:55.348578250 +0900 +++ mips/Documentation/feature-removal-schedule.txt 2006-10-02 22:44:01.296950000 +0900 @@ -228,16 +228,6 @@ Who: Ralf Baechle --------------------------- -What: Support for the IT8172-based platforms, ITE 8172G and Globespan IVR -When: September 2006 -Why: Code does no longer build since at least 2.6.0, apparently there is - no user base left for these platforms. Hardware out of production - since several years and hardly a trace of the manufacturer left on - the net. -Who: Ralf Baechle - ---------------------------- - What: Interrupt only SA_* flags When: Januar 2007 Why: The interrupt related SA_* flags are replaced by IRQF_* to move them diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Kconfig mips/arch/mips/Kconfig --- mips-orig/arch/mips/Kconfig 2006-10-02 22:43:55.348578250 +0900 +++ mips/arch/mips/Kconfig 2006-10-02 22:44:01.296950000 +0900 @@ -203,39 +203,6 @@ config MIPS_EV64120 . Say Y here if you wish to build a kernel for this platform. -config MIPS_IVR - bool "Globespan IVR board" - select DMA_NONCOHERENT - select HW_HAS_PCI - select ITE_BOARD_GEN - select SYS_HAS_CPU_NEVADA - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_LITTLE_ENDIAN - help - This is an evaluation board built by Globespan to showcase thir - iVR (Internet Video Recorder) design. It utilizes a QED RM5231 - R5000 MIPS core. More information can be found out their website - located at . Say Y here if you wish to - build a kernel for this platform. - -config MIPS_ITE8172 - bool "ITE 8172G board" - select DMA_NONCOHERENT - select HW_HAS_PCI - select ITE_BOARD_GEN - select SYS_HAS_CPU_R5432 - select SYS_HAS_CPU_NEVADA - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_LITTLE_ENDIAN - help - Ths is an evaluation board made by ITE - with ATX form factor that utilizes a MIPS R5000 to work with its - ITE8172G companion internet appliance chip. The MIPS core can be - either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build - a kernel for this platform. - config MACH_JAZZ bool "Jazz family of machines" select ARC @@ -712,7 +679,6 @@ endchoice source "arch/mips/ddb5xxx/Kconfig" source "arch/mips/gt64120/ev64120/Kconfig" source "arch/mips/jazz/Kconfig" -source "arch/mips/ite-boards/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/sgi-ip27/Kconfig" @@ -863,9 +829,6 @@ config MIPS_RM9122 config PCI_MARVELL bool -config ITE_BOARD_GEN - bool - config SOC_AU1000 bool select SOC_AU1X00 @@ -948,16 +911,6 @@ config AU1X00_USB_DEVICE depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 default n -config IT8172_CIR - bool - depends on MIPS_ITE8172 || MIPS_IVR - default y - -config IT8712 - bool - depends on MIPS_ITE8172 - default y - config BOOT_ELF32 bool diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Makefile mips/arch/mips/Makefile --- mips-orig/arch/mips/Makefile 2006-10-02 22:43:55.348578250 +0900 +++ mips/arch/mips/Makefile 2006-10-02 22:44:01.296950000 +0900 @@ -287,19 +287,6 @@ cflags-$(CONFIG_WR_PPMC) += -Iinclude/a load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 # -# Globespan IVR eval board with QED 5231 CPU -# -core-$(CONFIG_ITE_BOARD_GEN) += arch/mips/ite-boards/generic/ -core-$(CONFIG_MIPS_IVR) += arch/mips/ite-boards/ivr/ -load-$(CONFIG_MIPS_IVR) += 0xffffffff80100000 - -# -# ITE 8172 eval board with QED 5231 CPU -# -core-$(CONFIG_MIPS_ITE8172) += arch/mips/ite-boards/qed-4n-s01b/ -load-$(CONFIG_MIPS_ITE8172) += 0xffffffff80100000 - -# # For all MIPS, Inc. eval boards # core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/it8172_defconfig mips/arch/mips/configs/it8172_defconfig --- mips-orig/arch/mips/configs/it8172_defconfig 2006-10-02 22:32:45.826735750 +0900 +++ mips/arch/mips/configs/it8172_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,964 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:11 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_IVR is not set -CONFIG_MIPS_ITE8172=y -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -# CONFIG_IT8172_REVC is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_ITE_BOARD_GEN=y -CONFIG_IT8172_CIR=y -CONFIG_IT8712=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -CONFIG_CPU_NEVADA=y -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_R5432=y -CONFIG_SYS_HAS_CPU_NEVADA=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_HOTPLUG is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -# CONFIG_PCI is not set -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_PARTITIONS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -# CONFIG_MTD_BLOCK is not set -# CONFIG_MTD_BLOCK_RO is not set -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0x8000000 -CONFIG_MTD_PHYSMAP_LEN=0x2000000 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set - -# -# OneNAND Flash Device Drivers -# -# CONFIG_MTD_ONENAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_IDE_ARM is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# PHY device support -# -CONFIG_PHYLIB=m - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_LXT_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_SMSC_PHY=m - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_DM9000 is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_QTRONIX_KEYBOARD is not set -# CONFIG_IT8172_SCR0 is not set -# CONFIG_IT8172_SCR1 is not set -# CONFIG_ITE_GPIO is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -CONFIG_SOUND=y - -# -# Advanced Linux Sound Architecture -# -# CONFIG_SND is not set - -# -# Open Sound System -# -CONFIG_SOUND_PRIME=y -CONFIG_SOUND_IT8172=y -# CONFIG_SOUND_MSNDCLAS is not set -# CONFIG_SOUND_MSNDPIN is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=m - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=m -CONFIG_CRC32=m -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/ivr_defconfig mips/arch/mips/configs/ivr_defconfig --- mips-orig/arch/mips/configs/ivr_defconfig 2006-10-02 22:32:45.826735750 +0900 +++ mips/arch/mips/configs/ivr_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,920 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:12 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -CONFIG_MIPS_IVR=y -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_ITE_BOARD_GEN=y -CONFIG_IT8172_CIR=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -CONFIG_CPU_NEVADA=y -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_NEVADA=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_BLK_DEV_IDEPCI is not set -# CONFIG_IDE_ARM is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=m - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_LXT_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_SMSC_PHY=m - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_QTRONIX_KEYBOARD=y -CONFIG_IT8172_SCR0=y -CONFIG_IT8172_SCR1=y - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -CONFIG_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=m - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=m -CONFIG_CRC32=m -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/Kconfig mips/arch/mips/ite-boards/Kconfig --- mips-orig/arch/mips/ite-boards/Kconfig 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/Kconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,8 +0,0 @@ -config IT8172_REVC - bool "Support for older IT8172 (Rev C)" - depends on MIPS_ITE8172 - help - Say Y here to support the older, Revision C version of the Integrated - Technology Express, Inc. ITE8172 SBC. Vendor page at - ; picture of the - board at . diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/generic/Makefile mips/arch/mips/ite-boards/generic/Makefile --- mips-orig/arch/mips/ite-boards/generic/Makefile 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/generic/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,15 +0,0 @@ -# -# Copyright 2000 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# ppopov@mvista.com or source@mvista.com -# -# Makefile for the ITE 8172 (qed-4n-s01b) board, generic files. -# - -obj-y += it8172_setup.o irq.o pmon_prom.o \ - time.o lpc.o puts.o reset.o - -obj-$(CONFIG_IT8172_CIR)+= it8172_cir.o -obj-$(CONFIG_KGDB) += dbg_io.o - -EXTRA_AFLAGS := $(CFLAGS) diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/generic/dbg_io.c mips/arch/mips/ite-boards/generic/dbg_io.c --- mips-orig/arch/mips/ite-boards/generic/dbg_io.c 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/generic/dbg_io.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,124 +0,0 @@ - - -#ifdef CONFIG_KGDB - -/* --- CONFIG --- */ - -/* we need uint32 uint8 */ -/* #include "types.h" */ -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [stevel] we use the IT8712 serial port for kgdb */ -#define DEBUG_BASE 0xB40003F8 /* 8712 serial port 1 base address */ -#define MAX_BAUD 115200 - -/* === END OF CONFIG === */ - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE 1 -#define OFS_INTR_ID 2 -#define OFS_DATA_FORMAT 3 -#define OFS_LINE_CONTROL 3 -#define OFS_MODEM_CONTROL 4 -#define OFS_RS232_OUTPUT 4 -#define OFS_LINE_STATUS 5 -#define OFS_MODEM_STATUS 6 -#define OFS_RS232_INPUT 6 -#define OFS_SCRATCH_PAD 7 - -#define OFS_DIVISOR_LSB 0 -#define OFS_DIVISOR_MSB 1 - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(DEBUG_BASE + y))) -#define UART16550_WRITE(y,z) ((*((volatile uint8*)(DEBUG_BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_115200, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_115200, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/generic/irq.c mips/arch/mips/ite-boards/generic/irq.c --- mips-orig/arch/mips/ite-boards/generic/irq.c 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/generic/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,308 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * ITE 8172G interrupt/setup routines. - * - * Copyright 2000,2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * Part of this file was derived from Carsten Langgaard's - * arch/mips/mips-boards/atlas/atlas_int.c. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/* revisit */ -#define EXT_IRQ0_TO_IP 2 /* IP 2 */ -#define EXT_IRQ5_TO_IP 7 /* IP 7 */ - -#define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) - -extern void set_debug_traps(void); -extern void mips_timer_interrupt(int irq, struct pt_regs *regs); - -struct it8172_intc_regs volatile *it8172_hw0_icregs = - (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE)); - -static void disable_it8172_irq(unsigned int irq_nr) -{ - if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) { - /* LPC interrupt */ - it8172_hw0_icregs->lpc_mask |= - (1 << (irq_nr - IT8172_LPC_IRQ_BASE)); - } else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) { - /* Local Bus interrupt */ - it8172_hw0_icregs->lb_mask |= - (1 << (irq_nr - IT8172_LB_IRQ_BASE)); - } else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) { - /* PCI and other interrupts */ - it8172_hw0_icregs->pci_mask |= - (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE)); - } else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) { - /* NMI interrupts */ - it8172_hw0_icregs->nmi_mask |= - (1 << (irq_nr - IT8172_NMI_IRQ_BASE)); - } else { - panic("disable_it8172_irq: bad irq %d", irq_nr); - } -} - -static void enable_it8172_irq(unsigned int irq_nr) -{ - if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) { - /* LPC interrupt */ - it8172_hw0_icregs->lpc_mask &= - ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE)); - } - else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) { - /* Local Bus interrupt */ - it8172_hw0_icregs->lb_mask &= - ~(1 << (irq_nr - IT8172_LB_IRQ_BASE)); - } - else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) { - /* PCI and other interrupts */ - it8172_hw0_icregs->pci_mask &= - ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE)); - } - else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) { - /* NMI interrupts */ - it8172_hw0_icregs->nmi_mask &= - ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE)); - } - else { - panic("enable_it8172_irq: bad irq %d", irq_nr); - } -} - -static unsigned int startup_ite_irq(unsigned int irq) -{ - enable_it8172_irq(irq); - return 0; -} - -#define shutdown_ite_irq disable_it8172_irq -#define mask_and_ack_ite_irq disable_it8172_irq - -static void end_ite_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_it8172_irq(irq); -} - -static struct irq_chip it8172_irq_type = { - .typename = "ITE8172", - .startup = startup_ite_irq, - .shutdown = shutdown_ite_irq, - .enable = enable_it8172_irq, - .disable = disable_it8172_irq, - .ack = mask_and_ack_ite_irq, - .end = end_ite_irq, -}; - - -static void enable_none(unsigned int irq) { } -static unsigned int startup_none(unsigned int irq) { return 0; } -static void disable_none(unsigned int irq) { } -static void ack_none(unsigned int irq) { } - -/* startup is the same as "enable", shutdown is same as "disable" */ -#define shutdown_none disable_none -#define end_none enable_none - -static struct irq_chip cp0_irq_type = { - .typename = "CP0 Count", - .startup = startup_none, - .shutdown = shutdown_none, - .enable = enable_none, - .disable = disable_none, - .ack = ack_none, - .end = end_none -}; - -void enable_cpu_timer(void) -{ - unsigned long flags; - - local_irq_save(flags); - set_c0_status(0x100 << EXT_IRQ5_TO_IP); - local_irq_restore(flags); -} - -void __init arch_init_irq(void) -{ - int i; - unsigned long flags; - - /* mask all interrupts */ - it8172_hw0_icregs->lb_mask = 0xffff; - it8172_hw0_icregs->lpc_mask = 0xffff; - it8172_hw0_icregs->pci_mask = 0xffff; - it8172_hw0_icregs->nmi_mask = 0xffff; - - /* make all interrupts level triggered */ - it8172_hw0_icregs->lb_trigger = 0; - it8172_hw0_icregs->lpc_trigger = 0; - it8172_hw0_icregs->pci_trigger = 0; - it8172_hw0_icregs->nmi_trigger = 0; - - /* active level setting */ - /* uart, keyboard, and mouse are active high */ - it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000); - it8172_hw0_icregs->lb_level |= 0x20; - - /* keyboard and mouse are edge triggered */ - it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000); - - -#if 0 - // Enable this piece of code to make internal USB interrupt - // edge triggered. - it8172_hw0_icregs->pci_trigger |= - (1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE)); - it8172_hw0_icregs->pci_level &= - ~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE)); -#endif - - for (i = 0; i <= IT8172_LAST_IRQ; i++) { - irq_desc[i].chip = &it8172_irq_type; - spin_lock_init(&irq_desc[i].lock); - } - irq_desc[MIPS_CPU_TIMER_IRQ].chip = &cp0_irq_type; - set_c0_status(ALLINTS_NOTIMER); -} - -void mips_spurious_interrupt(struct pt_regs *regs) -{ -#if 1 - return; -#else - unsigned long status, cause; - - printk("got spurious interrupt\n"); - status = read_c0_status(); - cause = read_c0_cause(); - printk("status %x cause %x\n", status, cause); - printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr); -#endif -} - -void it8172_hw0_irqdispatch(struct pt_regs *regs) -{ - int irq; - unsigned short intstatus = 0, status = 0; - - intstatus = it8172_hw0_icregs->intstatus; - if (intstatus & 0x8) { - panic("Got NMI interrupt"); - } else if (intstatus & 0x4) { - /* PCI interrupt */ - irq = 0; - status |= it8172_hw0_icregs->pci_req; - while (!(status & 0x1)) { - irq++; - status >>= 1; - } - irq += IT8172_PCI_DEV_IRQ_BASE; - } else if (intstatus & 0x1) { - /* Local Bus interrupt */ - irq = 0; - status |= it8172_hw0_icregs->lb_req; - while (!(status & 0x1)) { - irq++; - status >>= 1; - } - irq += IT8172_LB_IRQ_BASE; - } else if (intstatus & 0x2) { - /* LPC interrupt */ - /* Since some lpc interrupts are edge triggered, - * we could lose an interrupt this way because - * we acknowledge all ints at onces. Revisit. - */ - status |= it8172_hw0_icregs->lpc_req; - it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */ - irq = 0; - while (!(status & 0x1)) { - irq++; - status >>= 1; - } - irq += IT8172_LPC_IRQ_BASE; - } else - return; - - do_IRQ(irq, regs); -} - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - - if (!pending) - mips_spurious_interrupt(regs); - else if (pending & CAUSEF_IP7) - ll_timer_interrupt(127, regs); - else if (pending & CAUSEF_IP2) - it8172_hw0_irqdispatch(regs); -} - -void show_pending_irqs(void) -{ - fputs("intstatus: "); - put32(it8172_hw0_icregs->intstatus); - puts(""); - - fputs("pci_req: "); - put32(it8172_hw0_icregs->pci_req); - puts(""); - - fputs("lb_req: "); - put32(it8172_hw0_icregs->lb_req); - puts(""); - - fputs("lpc_req: "); - put32(it8172_hw0_icregs->lpc_req); - puts(""); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/generic/it8172_cir.c mips/arch/mips/ite-boards/generic/it8172_cir.c --- mips-orig/arch/mips/ite-boards/generic/it8172_cir.c 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/generic/it8172_cir.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,170 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * IT8172 Consumer IR port generic routines. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - - -#ifdef CONFIG_IT8172_CIR - -#include -#include -#include -#include - -#include -#include - - -volatile struct it8172_cir_regs *cir_regs[NUM_CIR_PORTS] = { - (volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR0_BASE)), - (volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR1_BASE))}; - - -/* - * Initialize Consumer IR Port. - */ -int cir_port_init(struct cir_port *cir) -{ - int port = cir->port; - unsigned char data; - - /* set baud rate */ - cir_regs[port]->bdlr = cir->baud_rate & 0xff; - cir_regs[port]->bdhr = (cir->baud_rate >> 8) & 0xff; - - /* set receiver control register */ - cir_regs[port]->rcr = (CIR_SET_RDWOS(cir->rdwos) | CIR_SET_RXDCR(cir->rxdcr)); - - /* set carrier frequency register */ - cir_regs[port]->cfr = (CIR_SET_CF(cir->cfq) | CIR_SET_HS(cir->hcfs)); - - /* set fifo threshold */ - data = cir_regs[port]->mstcr & 0xf3; - data |= CIR_SET_FIFO_TL(cir->fifo_tl); - cir_regs[port]->mstcr = data; - - clear_fifo(cir); - enable_receiver(cir); - disable_rx_demodulation(cir); - - set_rx_active(cir); - int_enable(cir); - rx_int_enable(cir); - - return 0; -} - - -void clear_fifo(struct cir_port *cir) -{ - cir_regs[cir->port]->mstcr |= CIR_FIFO_CLEAR; -} - -void enable_receiver(struct cir_port *cir) -{ - cir_regs[cir->port]->rcr |= CIR_RXEN; -} - -void disable_receiver(struct cir_port *cir) -{ - cir_regs[cir->port]->rcr &= ~CIR_RXEN; -} - -void enable_rx_demodulation(struct cir_port *cir) -{ - cir_regs[cir->port]->rcr |= CIR_RXEND; -} - -void disable_rx_demodulation(struct cir_port *cir) -{ - cir_regs[cir->port]->rcr &= ~CIR_RXEND; -} - -void set_rx_active(struct cir_port *cir) -{ - cir_regs[cir->port]->rcr |= CIR_RXACT; -} - -void int_enable(struct cir_port *cir) -{ - cir_regs[cir->port]->ier |= CIR_IEC; -} - -void rx_int_enable(struct cir_port *cir) -{ - cir_regs[cir->port]->ier |= CIR_RDAIE; -} - -void dump_regs(struct cir_port *cir) -{ - printk("mstcr %x ier %x iir %x cfr %x rcr %x tcr %x tfsr %x rfsr %x\n", - cir_regs[cir->port]->mstcr, - cir_regs[cir->port]->ier, - cir_regs[cir->port]->iir, - cir_regs[cir->port]->cfr, - cir_regs[cir->port]->rcr, - cir_regs[cir->port]->tcr, - cir_regs[cir->port]->tfsr, - cir_regs[cir->port]->rfsr); - - while (cir_regs[cir->port]->iir & CIR_RDAI) { - printk("data %x\n", cir_regs[cir->port]->dr); - } -} - -void dump_reg_addr(struct cir_port *cir) -{ - printk("dr %x mstcr %x ier %x iir %x cfr %x rcr %x tcr %x bdlr %x bdhr %x tfsr %x rfsr %x\n", - (unsigned)&cir_regs[cir->port]->dr, - (unsigned)&cir_regs[cir->port]->mstcr, - (unsigned)&cir_regs[cir->port]->ier, - (unsigned)&cir_regs[cir->port]->iir, - (unsigned)&cir_regs[cir->port]->cfr, - (unsigned)&cir_regs[cir->port]->rcr, - (unsigned)&cir_regs[cir->port]->tcr, - (unsigned)&cir_regs[cir->port]->bdlr, - (unsigned)&cir_regs[cir->port]->bdhr, - (unsigned)&cir_regs[cir->port]->tfsr, - (unsigned)&cir_regs[cir->port]->rfsr); -} - -int cir_get_rx_count(struct cir_port *cir) -{ - return cir_regs[cir->port]->rfsr & CIR_RXFBC_MASK; -} - -char cir_read_data(struct cir_port *cir) -{ - return cir_regs[cir->port]->dr; -} - -char get_int_status(struct cir_port *cir) -{ - return cir_regs[cir->port]->iir; -} -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/generic/it8172_setup.c mips/arch/mips/ite-boards/generic/it8172_setup.c --- mips-orig/arch/mips/ite-boards/generic/it8172_setup.c 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/generic/it8172_setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,352 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * IT8172/QED5231 board setup. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern struct resource ioport_resource; -#ifdef CONFIG_SERIO_I8042 -int init_8712_keyboard(void); -#endif - -extern int SearchIT8712(void); -extern void InitLPCInterface(void); -extern char * __init prom_getcmdline(void); -extern void it8172_restart(char *command); -extern void it8172_halt(void); -extern void it8172_power_off(void); - -extern void it8172_time_init(void); - -#ifdef CONFIG_IT8172_REVC -struct { - struct resource ram; - struct resource pci_mem; - struct resource pci_io; - struct resource flash; - struct resource boot; -} it8172_resources = { - { - .start = 0, /* to be initted */ - .end = 0, - .name = "RAM", - .flags = IORESOURCE_MEM - }, { - .start = 0x10000000, - .end = 0x13FFFFFF, - .name = "PCI Mem", - .flags = IORESOURCE_MEM - }, { - .start = 0x14000000, - .end = 0x17FFFFFF - .name = "PCI I/O", - }, { - .start = 0x08000000, - .end = 0x0CFFFFFF - .name = "Flash", - }, { - .start = 0x1FC00000, - .end = 0x1FFFFFFF - .name = "Boot ROM", - } -}; -#else -struct { - struct resource ram; - struct resource pci_mem0; - struct resource pci_mem1; - struct resource pci_io; - struct resource pci_mem2; - struct resource pci_mem3; - struct resource flash; - struct resource boot; -} it8172_resources = { - { - .start = 0, /* to be initted */ - .end = 0, - .name = "RAM", - .flags = IORESOURCE_MEM - }, { - .start = 0x0C000000, - .end = 0x0FFFFFFF, - .name = "PCI Mem0", - .flags = IORESOURCE_MEM - }, { - .start = 0x10000000, - .end = 0x13FFFFFF, - .name = "PCI Mem1", - .flags = IORESOURCE_MEM - }, { - .start = 0x14000000, - .end = 0x17FFFFFF - .name = "PCI I/O", - }, { - .start = 0x1A000000, - .end = 0x1BFFFFFF, - .name = "PCI Mem2", - .flags = IORESOURCE_MEM - }, { - .start = 0x1C000000, - .end = 0x1FBFFFFF, - .name = "PCI Mem3", - .flags = IORESOURCE_MEM - }, { - .start = 0x08000000, - .end = 0x0CFFFFFF - .name = "Flash", - }, { - .start = 0x1FC00000, - .end = 0x1FFFFFFF - .name = "Boot ROM", - } -}; -#endif - - -void __init it8172_init_ram_resource(unsigned long memsize) -{ - it8172_resources.ram.end = memsize; -} - -void __init plat_mem_setup(void) -{ - unsigned short dsr; - char *argptr; - - argptr = prom_getcmdline(); -#ifdef CONFIG_SERIAL_CONSOLE - if ((argptr = strstr(argptr, "console=")) == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS0,115200"); - } -#endif - - clear_c0_status(ST0_FR); - - board_time_init = it8172_time_init; - - _machine_restart = it8172_restart; - _machine_halt = it8172_halt; - pm_power_off = it8172_power_off; - - /* - * IO/MEM resources. - * - * revisit this area. - */ - set_io_port_base(KSEG1); - ioport_resource.start = it8172_resources.pci_io.start; - ioport_resource.end = it8172_resources.pci_io.end; -#ifdef CONFIG_IT8172_REVC - iomem_resource.start = it8172_resources.pci_mem.start; - iomem_resource.end = it8172_resources.pci_mem.end; -#else - iomem_resource.start = it8172_resources.pci_mem0.start; - iomem_resource.end = it8172_resources.pci_mem3.end; -#endif - -#ifdef CONFIG_BLK_DEV_INITRD - ROOT_DEV = Root_RAM0; -#endif - - /* - * Pull enabled devices out of standby - */ - IT_IO_READ16(IT_PM_DSR, dsr); - - /* - * Fixme: This breaks when these drivers are modules!!! - */ -#ifdef CONFIG_SOUND_IT8172 - dsr &= ~IT_PM_DSR_ACSB; -#else - dsr |= IT_PM_DSR_ACSB; -#endif -#ifdef CONFIG_BLK_DEV_IT8172 - dsr &= ~IT_PM_DSR_IDESB; -#else - dsr |= IT_PM_DSR_IDESB; -#endif - IT_IO_WRITE16(IT_PM_DSR, dsr); - - InitLPCInterface(); - -#ifdef CONFIG_MIPS_ITE8172 - if (SearchIT8712()) { - printk("Found IT8712 Super IO\n"); - /* enable IT8712 serial port */ - LPCSetConfig(LDN_SERIAL1, 0x30, 0x01); /* enable */ - LPCSetConfig(LDN_SERIAL1, 0x23, 0x01); /* clock selection */ -#ifdef CONFIG_SERIO_I8042 - if (init_8712_keyboard()) { - printk("Unable to initialize keyboard\n"); - LPCSetConfig(LDN_KEYBOARD, 0x30, 0x0); /* disable keyboard */ - } else { - LPCSetConfig(LDN_KEYBOARD, 0x30, 0x1); /* enable keyboard */ - LPCSetConfig(LDN_KEYBOARD, 0xf0, 0x2); - LPCSetConfig(LDN_KEYBOARD, 0x71, 0x3); - - LPCSetConfig(LDN_MOUSE, 0x30, 0x1); /* enable mouse */ - - LPCSetConfig(0x4, 0x30, 0x1); - LPCSetConfig(0x4, 0xf4, LPCGetConfig(0x4, 0xf4) | 0x80); - - if ((LPCGetConfig(LDN_KEYBOARD, 0x30) == 0) || - (LPCGetConfig(LDN_MOUSE, 0x30) == 0)) - printk("Error: keyboard or mouse not enabled\n"); - - } -#endif - } - else { - printk("IT8712 Super IO not found\n"); - } -#endif - -#ifdef CONFIG_IT8172_CIR - { - unsigned long data; - //printk("Enabling CIR0\n"); - IT_IO_READ16(IT_PM_DSR, data); - data &= ~IT_PM_DSR_CIR0SB; - IT_IO_WRITE16(IT_PM_DSR, data); - //printk("DSR register: %x\n", (unsigned)IT_IO_READ16(IT_PM_DSR, data)); - } -#endif -#ifdef CONFIG_IT8172_SCR0 - { - unsigned i; - /* Enable Smart Card Reader 0 */ - /* First power it up */ - IT_IO_READ16(IT_PM_DSR, i); - i &= ~IT_PM_DSR_SCR0SB; - IT_IO_WRITE16(IT_PM_DSR, i); - /* Then initialize its registers */ - outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT - |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT - |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT - |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT - |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT), - IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SFR); - outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT, - IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SCDR); - } -#endif /* CONFIG_IT8172_SCR0 */ -#ifdef CONFIG_IT8172_SCR1 - { - unsigned i; - /* Enable Smart Card Reader 1 */ - /* First power it up */ - IT_IO_READ16(IT_PM_DSR, i); - i &= ~IT_PM_DSR_SCR1SB; - IT_IO_WRITE16(IT_PM_DSR, i); - /* Then initialize its registers */ - outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT - |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT - |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT - |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT - |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT), - IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SFR); - outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT, - IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SCDR); - } -#endif /* CONFIG_IT8172_SCR1 */ -} - -#ifdef CONFIG_SERIO_I8042 -/* - * According to the ITE Special BIOS Note for waking up the - * keyboard controller... - */ -static int init_8712_keyboard(void) -{ - unsigned int cmd_port = 0x14000064; - unsigned int data_port = 0x14000060; - ^^^^^^^^^^^ - Somebody here doesn't grok the concept of io ports. - - unsigned char data; - int i; - - outb(0xaa, cmd_port); /* send self-test cmd */ - i = 0; - while (!(inb(cmd_port) & 0x1)) { /* wait output buffer full */ - i++; - if (i > 0xffffff) - return 1; - } - - data = inb(data_port); - outb(0xcb, cmd_port); /* set ps2 mode */ - while (inb(cmd_port) & 0x2) { /* wait while input buffer full */ - i++; - if (i > 0xffffff) - return 1; - } - outb(0x01, data_port); - while (inb(cmd_port) & 0x2) { /* wait while input buffer full */ - i++; - if (i > 0xffffff) - return 1; - } - - outb(0x60, cmd_port); /* write 8042 command byte */ - while (inb(cmd_port) & 0x2) { /* wait while input buffer full */ - i++; - if (i > 0xffffff) - return 1; - } - outb(0x45, data_port); /* at interface, keyboard enabled, system flag */ - while (inb(cmd_port) & 0x2) { /* wait while input buffer full */ - i++; - if (i > 0xffffff) - return 1; - } - - outb(0xae, cmd_port); /* enable interface */ - return 0; -} -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/generic/lpc.c mips/arch/mips/ite-boards/generic/lpc.c --- mips-orig/arch/mips/ite-boards/generic/lpc.c 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/generic/lpc.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,144 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * ITE Semi IT8712 Super I/O functions. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -void LPCEnterMBPnP(void) -{ - int i; - unsigned char key[4] = {0x87, 0x01, 0x55, 0x55}; - - for (i = 0; i<4; i++) - outb(key[i], LPC_KEY_ADDR); - -} - -void LPCExitMBPnP(void) -{ - outb(0x02, LPC_KEY_ADDR); - outb(0x02, LPC_DATA_ADDR); -} - -void LPCSetConfig(char LdnNumber, char Index, char data) -{ - LPCEnterMBPnP(); // Enter IT8712 MB PnP mode - outb(0x07, LPC_KEY_ADDR); - outb(LdnNumber, LPC_DATA_ADDR); - outb(Index, LPC_KEY_ADDR); - outb(data, LPC_DATA_ADDR); - LPCExitMBPnP(); -} - -char LPCGetConfig(char LdnNumber, char Index) -{ - char rtn; - - LPCEnterMBPnP(); // Enter IT8712 MB PnP mode - outb(0x07, LPC_KEY_ADDR); - outb(LdnNumber, LPC_DATA_ADDR); - outb(Index, LPC_KEY_ADDR); - rtn = inb(LPC_DATA_ADDR); - LPCExitMBPnP(); - return rtn; -} - -int SearchIT8712(void) -{ - unsigned char Id1, Id2; - unsigned short Id; - - LPCEnterMBPnP(); - outb(0x20, LPC_KEY_ADDR); /* chip id byte 1 */ - Id1 = inb(LPC_DATA_ADDR); - outb(0x21, LPC_KEY_ADDR); /* chip id byte 2 */ - Id2 = inb(LPC_DATA_ADDR); - Id = (Id1 << 8) | Id2; - LPCExitMBPnP(); - if (Id == 0x8712) - return TRUE; - else - return FALSE; -} - -void InitLPCInterface(void) -{ - unsigned char bus, dev_fn; - unsigned long data; - - bus = 0; - dev_fn = 1<<3 | 4; - - - /* pci cmd, SERR# Enable */ - IT_WRITE(IT_CONFADDR, - (bus << IT_BUSNUM_SHF) | - (dev_fn << IT_FUNCNUM_SHF) | - ((0x4 / 4) << IT_REGNUM_SHF)); - IT_READ(IT_CONFDATA, data); - data |= 0x0100; - IT_WRITE(IT_CONFADDR, - (bus << IT_BUSNUM_SHF) | - (dev_fn << IT_FUNCNUM_SHF) | - ((0x4 / 4) << IT_REGNUM_SHF)); - IT_WRITE(IT_CONFDATA, data); - - /* setup serial irq control register */ - IT_WRITE(IT_CONFADDR, - (bus << IT_BUSNUM_SHF) | - (dev_fn << IT_FUNCNUM_SHF) | - ((0x48 / 4) << IT_REGNUM_SHF)); - IT_READ(IT_CONFDATA, data); - data = (data & 0xffff00ff) | 0xc400; - IT_WRITE(IT_CONFADDR, - (bus << IT_BUSNUM_SHF) | - (dev_fn << IT_FUNCNUM_SHF) | - ((0x48 / 4) << IT_REGNUM_SHF)); - IT_WRITE(IT_CONFDATA, data); - - - /* Enable I/O Space Subtractive Decode */ - /* default 0x4C is 0x3f220000 */ - IT_WRITE(IT_CONFADDR, - (bus << IT_BUSNUM_SHF) | - (dev_fn << IT_FUNCNUM_SHF) | - ((0x4C / 4) << IT_REGNUM_SHF)); - IT_WRITE(IT_CONFDATA, 0x3f2200f3); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/generic/pmon_prom.c mips/arch/mips/ite-boards/generic/pmon_prom.c --- mips-orig/arch/mips/ite-boards/generic/pmon_prom.c 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/generic/pmon_prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,135 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * PROM library initialisation code, assuming a version of - * pmon is the boot code. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/xx files. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include - -#include - -extern int prom_argc; -extern char **prom_argv, **prom_envp; - -typedef struct -{ - char *name; -/* char *val; */ -}t_env_var; - - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; - -} - - -char *prom_getenv(char *envname) -{ - /* - * Return a pointer to the given environment variable. - * Environment variables are stored in the form of "memsize=64". - */ - - t_env_var *env = (t_env_var *)prom_envp; - int i; - - i = strlen(envname); - - while(env->name) { - if(strncmp(envname, env->name, i) == 0) { - return(env->name + strlen(envname) + 1); - } - env++; - } - return(NULL); -} - -static inline unsigned char str2hexnum(unsigned char c) -{ - if(c >= '0' && c <= '9') - return c - '0'; - if(c >= 'a' && c <= 'f') - return c - 'a' + 10; - return 0; /* foo */ -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} - -unsigned long __init prom_get_memsize(void) -{ - char *memsize_str; - unsigned int memsize; - - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { -#ifdef CONFIG_MIPS_ITE8172 - memsize = 32; -#elif defined(CONFIG_MIPS_IVR) - memsize = 64; -#else - memsize = 8; -#endif - printk("memsize unknown: setting to %dMB\n", memsize); - } else { - printk("memsize: %s\n", memsize_str); - memsize = simple_strtol(memsize_str, NULL, 0); - } - return memsize; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/generic/puts.c mips/arch/mips/ite-boards/generic/puts.c --- mips-orig/arch/mips/ite-boards/generic/puts.c 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/generic/puts.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,139 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Low level uart routines to directly access a 16550 uart. - * - * Copyright 2000,2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include - -#define SERIAL_BASE 0xB4011800 /* it8172 */ -#define SER_CMD 5 -#define SER_DATA 0x00 -#define TX_BUSY 0x20 - -#define TIMEOUT 0xffff -#undef SLOW_DOWN - -static const char digits[16] = "0123456789abcdef"; -static volatile unsigned char *const com1 = (unsigned char *) SERIAL_BASE; - - -#ifdef SLOW_DOWN -static inline void slow_down() -{ - int k; - for (k = 0; k < 10000; k++); -} -#else -#define slow_down() -#endif - -void putch(const unsigned char c) -{ - unsigned char ch; - int i = 0; - - do { - ch = com1[SER_CMD]; - slow_down(); - i++; - if (i > TIMEOUT) { - break; - } - } while (0 == (ch & TX_BUSY)); - com1[SER_DATA] = c; -} - -void puts(unsigned char *cp) -{ - unsigned char ch; - int i = 0; - - while (*cp) { - do { - ch = com1[SER_CMD]; - slow_down(); - i++; - if (i > TIMEOUT) { - break; - } - } while (0 == (ch & TX_BUSY)); - com1[SER_DATA] = *cp++; - } - putch('\r'); - putch('\n'); -} - -void fputs(unsigned char *cp) -{ - unsigned char ch; - int i = 0; - - while (*cp) { - - do { - ch = com1[SER_CMD]; - slow_down(); - i++; - if (i > TIMEOUT) { - break; - } - } while (0 == (ch & TX_BUSY)); - com1[SER_DATA] = *cp++; - } -} - - -void put64(uint64_t ul) -{ - int cnt; - unsigned ch; - - cnt = 16; /* 16 nibbles in a 64 bit long */ - putch('0'); - putch('x'); - do { - cnt--; - ch = (unsigned char) (ul >> cnt * 4) & 0x0F; - putch(digits[ch]); - } while (cnt > 0); -} - -void put32(unsigned u) -{ - int cnt; - unsigned ch; - - cnt = 8; /* 8 nibbles in a 32 bit long */ - putch('0'); - putch('x'); - do { - cnt--; - ch = (unsigned char) (u >> cnt * 4) & 0x0F; - putch(digits[ch]); - } while (cnt > 0); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/generic/reset.c mips/arch/mips/ite-boards/generic/reset.c --- mips-orig/arch/mips/ite-boards/generic/reset.c 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/generic/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,60 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * ITE 8172 reset routines. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include - -void it8172_restart() -{ - set_c0_status(ST0_BEV | ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -void it8172_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void it8172_power_off(void) -{ - it8172_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/generic/time.c mips/arch/mips/ite-boards/generic/time.c --- mips-orig/arch/mips/ite-boards/generic/time.c 2006-10-02 22:32:45.898740250 +0900 +++ mips/arch/mips/ite-boards/generic/time.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,249 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * Copyright (C) 2003 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Setting up the clock on the MIPS boards. - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define IT8172_RTC_ADR_REG (IT8172_PCI_IO_BASE + IT_RTC_BASE) -#define IT8172_RTC_DAT_REG (IT8172_RTC_ADR_REG + 1) -#define IT8172_RTC_CENTURY_REG (IT8172_PCI_IO_BASE + IT_RTC_CENTURY) - -static volatile char *rtc_adr_reg = (char*)KSEG1ADDR(IT8172_RTC_ADR_REG); -static volatile char *rtc_dat_reg = (char*)KSEG1ADDR(IT8172_RTC_DAT_REG); -static volatile char *rtc_century_reg = (char*)KSEG1ADDR(IT8172_RTC_CENTURY_REG); - -unsigned char it8172_rtc_read_data(unsigned long addr) -{ - unsigned char retval; - - *rtc_adr_reg = addr; - retval = *rtc_dat_reg; - return retval; -} - -void it8172_rtc_write_data(unsigned char data, unsigned long addr) -{ - *rtc_adr_reg = addr; - *rtc_dat_reg = data; -} - -#undef CMOS_READ -#undef CMOS_WRITE -#define CMOS_READ(addr) it8172_rtc_read_data(addr) -#define CMOS_WRITE(data, addr) it8172_rtc_write_data(data, addr) - -static unsigned char saved_control; /* remember rtc control reg */ -static inline int rtc_24h(void) { return saved_control & RTC_24H; } -static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; } - -static inline unsigned char -bin_to_hw(unsigned char c) -{ - if (rtc_dm_binary()) - return c; - else - return ((c/10) << 4) + (c%10); -} - -static inline unsigned char -hw_to_bin(unsigned char c) -{ - if (rtc_dm_binary()) - return c; - else - return (c>>4)*10 + (c &0xf); -} - -/* 0x80 bit indicates pm in 12-hour format */ -static inline unsigned char -hour_bin_to_hw(unsigned char c) -{ - if (rtc_24h()) - return bin_to_hw(c); - if (c >= 12) - return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */ - else - return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */ -} - -static inline unsigned char -hour_hw_to_bin(unsigned char c) -{ - unsigned char tmp = hw_to_bin(c&0x3f); - if (rtc_24h()) - return tmp; - if (c & 0x80) - return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */ - else - return (tmp==12)?0:tmp; /* 12am is 0 */ -} - -static unsigned long r4k_offset; /* Amount to increment compare reg each time */ -static unsigned long r4k_cur; /* What counter should be at next timer irq */ -extern unsigned int mips_hpt_frequency; - -/* - * Figure out the r4k offset, the amount to increment the compare - * register for each time tick. - * Use the RTC to calculate offset. - */ -static unsigned long __init cal_r4koff(void) -{ - unsigned int flags; - - local_irq_save(flags); - - /* Start counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - /* Start r4k counter. */ - write_c0_count(0); - - /* Read counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - mips_hpt_frequency = read_c0_count(); - - /* restore interrupts */ - local_irq_restore(flags); - - return (mips_hpt_frequency / HZ); -} - -static unsigned long -it8172_rtc_get_time(void) -{ - unsigned int year, mon, day, hour, min, sec; - unsigned int flags; - - /* avoid update-in-progress. */ - for (;;) { - local_irq_save(flags); - if (! (CMOS_READ(RTC_REG_A) & RTC_UIP)) - break; - /* don't hold intr closed all the time */ - local_irq_restore(flags); - } - - /* Read regs. */ - sec = hw_to_bin(CMOS_READ(RTC_SECONDS)); - min = hw_to_bin(CMOS_READ(RTC_MINUTES)); - hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS)); - day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH)); - mon = hw_to_bin(CMOS_READ(RTC_MONTH)); - year = hw_to_bin(CMOS_READ(RTC_YEAR)) + - hw_to_bin(*rtc_century_reg) * 100; - - /* restore interrupts */ - local_irq_restore(flags); - - return mktime(year, mon, day, hour, min, sec); -} - -static int -it8172_rtc_set_time(unsigned long t) -{ - struct rtc_time tm; - unsigned int flags; - - /* convert */ - to_tm(t, &tm); - - /* avoid update-in-progress. */ - for (;;) { - local_irq_save(flags); - if (! (CMOS_READ(RTC_REG_A) & RTC_UIP)) - break; - /* don't hold intr closed all the time */ - local_irq_restore(flags); - } - - *rtc_century_reg = bin_to_hw(tm.tm_year/100); - CMOS_WRITE(bin_to_hw(tm.tm_sec), RTC_SECONDS); - CMOS_WRITE(bin_to_hw(tm.tm_min), RTC_MINUTES); - CMOS_WRITE(hour_bin_to_hw(tm.tm_hour), RTC_HOURS); - CMOS_WRITE(bin_to_hw(tm.tm_mday), RTC_DAY_OF_MONTH); - CMOS_WRITE(bin_to_hw(tm.tm_mon+1), RTC_MONTH); /* tm_mon starts from 0 */ - CMOS_WRITE(bin_to_hw(tm.tm_year%100), RTC_YEAR); - - /* restore interrupts */ - local_irq_restore(flags); - - return 0; -} - -void __init it8172_time_init(void) -{ - unsigned int est_freq, flags; - - local_irq_save(flags); - - saved_control = CMOS_READ(RTC_CONTROL); - - printk("calculating r4koff... "); - r4k_offset = cal_r4koff(); - printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); - - est_freq = 2*r4k_offset*HZ; - est_freq += 5000; /* round */ - est_freq -= est_freq%10000; - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, - (est_freq%1000000)*100/1000000); - - local_irq_restore(flags); - - rtc_mips_get_time = it8172_rtc_get_time; - rtc_mips_set_time = it8172_rtc_set_time; -} - -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) - -void __init plat_timer_setup(struct irqaction *irq) -{ - puts("timer_setup\n"); - put32(NR_IRQS); - puts(""); - /* we are using the cpu counter for timer interrupts */ - setup_irq(MIPS_CPU_TIMER_IRQ, irq); - - /* to generate the first timer interrupt */ - r4k_cur = (read_c0_count() + r4k_offset); - write_c0_compare(r4k_cur); - set_c0_status(ALLINTS); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/ivr/Makefile mips/arch/mips/ite-boards/ivr/Makefile --- mips-orig/arch/mips/ite-boards/ivr/Makefile 2006-10-02 22:32:45.902740500 +0900 +++ mips/arch/mips/ite-boards/ivr/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,10 +0,0 @@ -# -# Copyright 2000 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# ppopov@mvista.com or source@mvista.com -# -# Makefile for the Globespan IVR board, -# board-specific files. -# - -obj-y += init.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/ivr/README mips/arch/mips/ite-boards/ivr/README --- mips-orig/arch/mips/ite-boards/ivr/README 2006-10-02 22:32:45.902740500 +0900 +++ mips/arch/mips/ite-boards/ivr/README 1970-01-01 09:00:00.000000000 +0900 @@ -1,3 +0,0 @@ -This is not really a board made by ITE Semi, but it's very -similar to the ITE QED-4N-S01B board. The IVR board is made -by Globespan and it's a reference board for the PVR chip. diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/ivr/init.c mips/arch/mips/ite-boards/ivr/init.c --- mips-orig/arch/mips/ite-boards/ivr/init.c 2006-10-02 22:32:45.902740500 +0900 +++ mips/arch/mips/ite-boards/ivr/init.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,81 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * IVR board setup. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int prom_argc; -char **prom_argv, **prom_envp; - -extern void __init prom_init_cmdline(void); -extern unsigned long __init prom_get_memsize(void); -extern void __init it8172_init_ram_resource(unsigned long memsize); - -const char *get_system_type(void) -{ - return "Globespan IVR"; -} - -void __init prom_init(void) -{ - unsigned long mem_size; - unsigned long pcicr; - - prom_argc = fw_arg0; - prom_argv = (char **) fw_arg1; - prom_envp = (int *) fw_arg3; - - mips_machgroup = MACH_GROUP_GLOBESPAN; - mips_machtype = MACH_IVR; /* Globespan's iTVC15 reference board */ - - prom_init_cmdline(); - - /* pmon does not set memsize */ - mem_size = prom_get_memsize(); - mem_size = mem_size << 20; - - /* - * make the entire physical memory visible to pci bus masters - */ - IT_READ(IT_MC_PCICR, pcicr); - pcicr &= ~0x1f; - pcicr |= (mem_size - 1) >> 22; - IT_WRITE(IT_MC_PCICR, pcicr); - - it8172_init_ram_resource(mem_size); - add_memory_region(0, mem_size, BOOT_MEM_RAM); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/qed-4n-s01b/Makefile mips/arch/mips/ite-boards/qed-4n-s01b/Makefile --- mips-orig/arch/mips/ite-boards/qed-4n-s01b/Makefile 2006-10-02 22:32:45.902740500 +0900 +++ mips/arch/mips/ite-boards/qed-4n-s01b/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,10 +0,0 @@ -# -# Copyright 2000 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# ppopov@mvista.com or source@mvista.com -# -# Makefile for the ITE 8172 (qed-4n-s01b) board, board -# specific files. -# - -obj-y := init.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/qed-4n-s01b/README mips/arch/mips/ite-boards/qed-4n-s01b/README --- mips-orig/arch/mips/ite-boards/qed-4n-s01b/README 2006-10-02 22:32:45.902740500 +0900 +++ mips/arch/mips/ite-boards/qed-4n-s01b/README 1970-01-01 09:00:00.000000000 +0900 @@ -1,2 +0,0 @@ -This is an ITE (www.iteusa.com) eval board for the ITE 8172G -system controller, with a QED 5231 CPU. diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/ite-boards/qed-4n-s01b/init.c mips/arch/mips/ite-boards/qed-4n-s01b/init.c --- mips-orig/arch/mips/ite-boards/qed-4n-s01b/init.c 2006-10-02 22:32:45.902740500 +0900 +++ mips/arch/mips/ite-boards/qed-4n-s01b/init.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,82 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * IT8172/QED5231 board setup. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int prom_argc; -char **prom_argv, **prom_envp; - -extern void __init prom_init_cmdline(void); -extern unsigned long __init prom_get_memsize(void); -extern void __init it8172_init_ram_resource(unsigned long memsize); - -const char *get_system_type(void) -{ - return "ITE QED-4N-S01B"; -} - -void __init prom_init(void) -{ - unsigned long mem_size; - unsigned long pcicr; - - prom_argc = fw_arg0; - prom_argv = (char **) fw_arg1; - prom_envp = (int *) fw_arg3; - - mips_machgroup = MACH_GROUP_ITE; - mips_machtype = MACH_QED_4N_S01B; /* ITE board name/number */ - - prom_init_cmdline(); - mem_size = prom_get_memsize(); - - printk("Memory size: %dMB\n", (unsigned)mem_size); - - mem_size <<= 20; /* MB */ - - /* - * make the entire physical memory visible to pci bus masters - */ - IT_READ(IT_MC_PCICR, pcicr); - pcicr &= ~0x1f; - pcicr |= (mem_size - 1) >> 22; - IT_WRITE(IT_MC_PCICR, pcicr); - - it8172_init_ram_resource(mem_size); - add_memory_region(0, mem_size, BOOT_MEM_RAM); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/Makefile mips/arch/mips/pci/Makefile --- mips-orig/arch/mips/pci/Makefile 2006-10-02 22:43:55.396581250 +0900 +++ mips/arch/mips/pci/Makefile 2006-10-02 22:44:01.312951000 +0900 @@ -7,7 +7,6 @@ obj-y += pci.o # # PCI bus host bridge specific code # -obj-$(CONFIG_ITE_BOARD_GEN) += ops-it8172.o obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o @@ -27,8 +26,6 @@ obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_MIPS_EV64120) += fixup-ev64120.o -obj-$(CONFIG_MIPS_ITE8172) += fixup-ite8172g.o -obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ite8172g.c mips/arch/mips/pci/fixup-ite8172g.c --- mips-orig/arch/mips/pci/fixup-ite8172g.c 2006-10-02 22:32:46.178757750 +0900 +++ mips/arch/mips/pci/fixup-ite8172g.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,80 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Board specific pci fixups. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -#include -#include -#include - -/* - * Shortcuts - */ -#define INTA IT8172_PCI_INTA_IRQ -#define INTB IT8172_PCI_INTB_IRQ -#define INTC IT8172_PCI_INTC_IRQ -#define INTD IT8172_PCI_INTD_IRQ - -static const int internal_func_irqs[7] __initdata = { - IT8172_AC97_IRQ, - IT8172_DMA_IRQ, - IT8172_CDMA_IRQ, - IT8172_USB_IRQ, - IT8172_BRIDGE_MASTER_IRQ, - IT8172_IDE_IRQ, - IT8172_MC68K_IRQ -}; - -static char irq_tab_ite8172g[][5] __initdata = { - [0x10] = { 0, INTA, INTB, INTC, INTD }, - [0x11] = { 0, INTA, INTB, INTC, INTD }, - [0x12] = { 0, INTB, INTC, INTD, INTA }, - [0x13] = { 0, INTC, INTD, INTA, INTB }, - [0x14] = { 0, INTD, INTA, INTB, INTC }, -}; - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - /* - * Internal device 1 is actually 7 different internal devices on the - * IT8172G (a multifunction device). - */ - if (slot == 1) - return internal_func_irqs[PCI_FUNC(dev->devfn)]; - - return irq_tab_ite8172g[slot][pin]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ivr.c mips/arch/mips/pci/fixup-ivr.c --- mips-orig/arch/mips/pci/fixup-ivr.c 2006-10-02 22:32:46.178757750 +0900 +++ mips/arch/mips/pci/fixup-ivr.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,75 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Globespan IVR board-specific pci fixups. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -#include -#include -#include - -/* - * Shortcuts - */ -#define INTA IT8172_PCI_INTA_IRQ -#define INTB IT8172_PCI_INTB_IRQ -#define INTC IT8172_PCI_INTC_IRQ -#define INTD IT8172_PCI_INTD_IRQ - -static const int internal_func_irqs[7] __initdata = { - IT8172_AC97_IRQ, - IT8172_DMA_IRQ, - IT8172_CDMA_IRQ, - IT8172_USB_IRQ, - IT8172_BRIDGE_MASTER_IRQ, - IT8172_IDE_IRQ, - IT8172_MC68K_IRQ -}; - -static char irq_tab_ivr[][5] __initdata = { - [0x11] = { INTC, INTC, INTD, INTA, INTB }, /* Realtek RTL-8139 */ - [0x12] = { INTB, INTB, INTB, INTC, INTC }, /* IVR slot */ - [0x13] = { INTA, INTA, INTB, INTC, INTD } /* Expansion slot */ -}; - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - if (slot == 1) - return internal_func_irqs[PCI_FUNC(dev->devfn)]; - - return irq_tab_ivr[slot][pin]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/ops-it8172.c mips/arch/mips/pci/ops-it8172.c --- mips-orig/arch/mips/pci/ops-it8172.c 2006-10-02 22:32:46.206759500 +0900 +++ mips/arch/mips/pci/ops-it8172.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,213 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * IT8172 system controller specific pci support. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -#include -#include - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -#undef DEBUG -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -static struct resource pci_mem_resource_1; - -static struct resource pci_io_resource = { - .start = 0x14018000, - .end = 0x17FFFFFF, - .name = "io pci IO space", - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource_0 = { - .start = 0x10101000, - .end = 0x13FFFFFF, - .name = "ext pci memory space 0/1", - .flags = IORESOURCE_MEM, - .parent = &pci_mem_resource_0, - .sibling = NULL, - .child = &pci_mem_resource_1 -}; - -static struct resource pci_mem_resource_1 = { - .start = 0x1A000000, - .end = 0x1FBFFFFF, - .name = "ext pci memory space 2/3", - .flags = IORESOURCE_MEM, - .parent = &pci_mem_resource_0 -}; - -extern struct pci_ops it8172_pci_ops; - -struct pci_controller it8172_controller = { - .pci_ops = &it8172_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource_0, -}; - -static int it8172_pcibios_config_access(unsigned char access_type, - struct pci_bus *bus, - unsigned int devfn, int where, - u32 * data) -{ - /* - * config cycles are on 4 byte boundary only - */ - - /* Setup address */ - IT_WRITE(IT_CONFADDR, (bus->number << IT_BUSNUM_SHF) | - (devfn << IT_FUNCNUM_SHF) | (where & ~0x3)); - - if (access_type == PCI_ACCESS_WRITE) { - IT_WRITE(IT_CONFDATA, *data); - } else { - IT_READ(IT_CONFDATA, *data); - } - - /* - * Revisit: check for master or target abort. - */ - return 0; -} - - -/* - * We can't address 8 and 16 bit words directly. Instead we have to - * read/write a 32bit word and mask/modify the data we actually want. - */ -static write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - u32 data = 0; - - switch (size) { - case 1: - if (it8172_pcibios_config_access - (PCI_ACCESS_READ, dev, where, &data)) - return -1; - - *val = (data >> ((where & 3) << 3)) & 0xff; - - return PCIBIOS_SUCCESSFUL; - - case 2: - - if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (it8172_pcibios_config_access - (PCI_ACCESS_READ, dev, where, &data)) - return -1; - - *val = (data >> ((where & 3) << 3)) & 0xffff; - DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n", - dev->bus->number, dev->devfn, where, *val); - - return PCIBIOS_SUCCESSFUL; - - case 4: - - if (where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (it8172_pcibios_config_access - (PCI_ACCESS_READ, dev, where, &data)) - return -1; - - *val = data; - - return PCIBIOS_SUCCESSFUL; - } -} - - -static write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - u32 data = 0; - - switch (size) { - case 1: - if (it8172_pcibios_config_access - (PCI_ACCESS_READ, dev, where, &data)) - return -1; - - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (it8172_pcibios_config_access - (PCI_ACCESS_WRITE, dev, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; - - case 2: - if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (it8172_pcibios_config_access - (PCI_ACCESS_READ, dev, where, &data)) - eturn - 1; - - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (it8172_pcibios_config_access - (PCI_ACCESS_WRITE, dev, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; - - case 4: - if (where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (it8172_pcibios_config_access - (PCI_ACCESS_WRITE, dev, where, &val)) - return -1; - - return PCIBIOS_SUCCESSFUL; - } -} - -struct pci_ops it8172_pci_ops = { - .read = read_config, - .write = write_config, -}; diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/bootinfo.h mips/include/asm-mips/bootinfo.h --- mips-orig/include/asm-mips/bootinfo.h 2006-10-02 22:43:55.400581500 +0900 +++ mips/include/asm-mips/bootinfo.h 2006-10-02 22:44:01.316951250 +0900 @@ -115,12 +115,6 @@ #define MACH_EV64120A 0 /* EV64120A */ /* - * Valid machtype for group ITE - */ -#define MACH_GROUP_ITE 13 /* ITE Semi Eval Boards */ -#define MACH_QED_4N_S01B 0 /* ITE8172 based eval board */ - -/* * Valid machtype for group PHILIPS */ #define MACH_GROUP_PHILIPS 14 @@ -129,12 +123,6 @@ #define MACH_PHILIPS_JBS 2 /* JBS */ /* - * Valid machtype for group Globespan - */ -#define MACH_GROUP_GLOBESPAN 15 /* Globespan */ -#define MACH_IVR 0 /* IVR eval board */ - -/* * Valid machtype for group SIBYTE */ #define MACH_GROUP_SIBYTE 16 /* Sibyte / Broadcom */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/it8172/it8172.h mips/include/asm-mips/it8172/it8172.h --- mips-orig/include/asm-mips/it8172/it8172.h 2006-10-02 22:33:08.584158000 +0900 +++ mips/include/asm-mips/it8172/it8172.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,348 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * IT8172 system controller defines. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __IT8172__H__ -#define __IT8172__H__ - -#include - -#define IT8172_BASE 0x18000000 -#define IT8172_PCI_IO_BASE 0x14000000 -#define IT8172_PCI_MEM_BASE 0x10000000 - -// System registers offsets from IT8172_BASE -#define IT_CMFPCR 0x0 -#define IT_DSRR 0x2 -#define IT_PCDCR 0x4 -#define IT_SPLLCR 0x6 -#define IT_CIDR 0x10 -#define IT_CRNR 0x12 -#define IT_CPUTR 0x14 -#define IT_CTCR 0x16 -#define IT_SDPR 0xF0 - -// Power management register offset from IT8172_PCI_IO_BASE -// Power Management Device Standby Register -#define IT_PM_DSR 0x15800 - -#define IT_PM_DSR_TMR0SB 0x0001 -#define IT_PM_DSR_TMR1SB 0x0002 -#define IT_PM_DSR_CIR0SB 0x0004 -#define IT_PM_DSR_CIR1SB 0x0008 -#define IT_PM_DSR_SCR0SB 0x0010 -#define IT_PM_DSR_SCR1SB 0x0020 -#define IT_PM_DSR_PPSB 0x0040 -#define IT_PM_DSR_I2CSB 0x0080 -#define IT_PM_DSR_UARTSB 0x0100 -#define IT_PM_DSR_IDESB 0x0200 -#define IT_PM_DSR_ACSB 0x0400 -#define IT_PM_DSR_M68KSB 0x0800 - -// Power Management PCI Device Software Reset Register -#define IT_PM_PCISR 0x15802 - -#define IT_PM_PCISR_IDESR 0x0001 -#define IT_PM_PCISR_CDMASR 0x0002 -#define IT_PM_PCISR_USBSR 0x0004 -#define IT_PM_PCISR_DMASR 0x0008 -#define IT_PM_PCISR_ACSR 0x0010 -#define IT_PM_PCISR_MEMSR 0x0020 -#define IT_PM_PCISR_68KSR 0x0040 - - -// PCI Configuration address and data register offsets -// from IT8172_BASE -#define IT_CONFADDR 0x4000 -#define IT_BUSNUM_SHF 16 -#define IT_DEVNUM_SHF 11 -#define IT_FUNCNUM_SHF 8 -#define IT_REGNUM_SHF 2 - -#define IT_CONFDATA 0x4004 - -// PCI configuration header common register offsets -#define IT_VID 0x00 -#define IT_DID 0x02 -#define IT_PCICMD 0x04 -#define IT_PCISTS 0x06 -#define IT_RID 0x08 -#define IT_CLASSC 0x09 -#define IT_HEADT 0x0E -#define IT_SERIRQC 0x49 - -// PCI to Internal/LPC Bus Bridge configuration header register offset -#define IT_P2I_BCR 0x4C -#define IT_P2I_D0IOSC 0x50 -#define IT_P2I_D1IOSC 0x54 -#define IT_P2I_D2IOSC 0x58 -#define IT_P2I_D3IOSC 0x5C -#define IT_P2I_D4IOSC 0x60 -#define IT_P2I_D5IOSC 0x64 -#define IT_P2I_D6IOSC 0x68 -#define IT_P2I_D7IOSC 0x6C -#define IT_P2I_D8IOSC 0x70 -#define IT_P2I_D9IOSC 0x74 -#define IT_P2I_D10IOSC 0x78 -#define IT_P2I_D11IOSC 0x7C - -// Memory controller register offsets from IT8172_BASE -#define IT_MC_SDRMR 0x1000 -#define IT_MC_SDRTR 0x1004 -#define IT_MC_MCR 0x1008 -#define IT_MC_SDTYPE 0x100C -#define IT_MC_WPBA 0x1010 -#define IT_MC_WPTA 0x1014 -#define IT_MC_HATR 0x1018 -#define IT_MC_PCICR 0x101C - -// Flash/ROM control register offsets from IT8172_BASE -#define IT_FC_BRCR 0x2000 -#define IT_FC_FCR 0x2004 -#define IT_FC_DCR 0x2008 - -// M68K interface bridge configuration header register offset -#define IT_M68K_MBCSR 0x54 -#define IT_M68K_TMR 0x58 -#define IT_M68K_BCR 0x5C -#define IT_M68K_BSR 0x5D -#define IT_M68K_DTR 0x5F - -// Register offset from IT8172_PCI_IO_BASE -// These registers are accessible through 8172 PCI IO window. - -// INTC -#define IT_INTC_BASE 0x10000 -#define IT_INTC_LBDNIRR 0x10000 -#define IT_INTC_LBDNIMR 0x10002 -#define IT_INTC_LBDNITR 0x10004 -#define IT_INTC_LBDNIAR 0x10006 -#define IT_INTC_LPCNIRR 0x10010 -#define IT_INTC_LPCNIMR 0x10012 -#define IT_INTC_LPCNITR 0x10014 -#define IT_INTC_LPCNIAR 0x10016 -#define IT_INTC_PDNIRR 0x10020 -#define IT_INTC_PDNIMR 0x10022 -#define IT_INTC_PDNITR 0x10024 -#define IT_INTC_PDNIAR 0x10026 -#define IT_INTC_UMNIRR 0x10030 -#define IT_INTC_UMNITR 0x10034 -#define IT_INTC_UMNIAR 0x10036 -#define IT_INTC_TYPER 0x107FE - -// IT8172 PCI device number -#define IT_C2P_DEVICE 0 -#define IT_AUDIO_DEVICE 1 -#define IT_DMAC_DEVICE 1 -#define IT_CDMAC_DEVICE 1 -#define IT_USB_DEVICE 1 -#define IT_P2I_DEVICE 1 -#define IT_IDE_DEVICE 1 -#define IT_M68K_DEVICE 1 - -// IT8172 PCI function number -#define IT_C2P_FUNCION 0 -#define IT_AUDIO_FUNCTION 0 -#define IT_DMAC_FUNCTION 1 -#define IT_CDMAC_FUNCTION 2 -#define IT_USB_FUNCTION 3 -#define IT_P2I_FUNCTION 4 -#define IT_IDE_FUNCTION 5 -#define IT_M68K_FUNCTION 6 - -// IT8172 GPIO -#define IT_GPADR 0x13800 -#define IT_GPBDR 0x13808 -#define IT_GPCDR 0x13810 -#define IT_GPACR 0x13802 -#define IT_GPBCR 0x1380A -#define IT_GPCCR 0x13812 -#define IT_GPAICR 0x13804 -#define IT_GPBICR 0x1380C -#define IT_GPCICR 0x13814 -#define IT_GPAISR 0x13806 -#define IT_GPBISR 0x1380E -#define IT_GPCISR 0x13816 -#define IT_GCR 0x13818 - -// IT8172 RTC -#define IT_RTC_BASE 0x14800 -#define IT_RTC_CENTURY 0x14808 - -#define IT_RTC_RIR0 0x00 -#define IT_RTC_RTR0 0x01 -#define IT_RTC_RIR1 0x02 -#define IT_RTC_RTR1 0x03 -#define IT_RTC_RIR2 0x04 -#define IT_RTC_RTR2 0x05 -#define IT_RTC_RCTR 0x08 -#define IT_RTC_RA 0x0A -#define IT_RTC_RB 0x0B -#define IT_RTC_RC 0x0C -#define IT_RTC_RD 0x0D - -#define RTC_SEC_INDEX 0x00 -#define RTC_MIN_INDEX 0x02 -#define RTC_HOUR_INDEX 0x04 -#define RTC_DAY_INDEX 0x06 -#define RTC_DATE_INDEX 0x07 -#define RTC_MONTH_INDEX 0x08 -#define RTC_YEAR_INDEX 0x09 - -// IT8172 internal device registers -#define IT_TIMER_BASE 0x10800 -#define IT_CIR0_BASE 0x11000 -#define IT_UART_BASE 0x11800 -#define IT_SCR0_BASE 0x12000 -#define IT_SCR1_BASE 0x12800 -#define IT_PP_BASE 0x13000 -#define IT_I2C_BASE 0x14000 -#define IT_CIR1_BASE 0x15000 - -// IT8172 Smart Card Reader offsets from IT_SCR*_BASE -#define IT_SCR_SFR 0x08 -#define IT_SCR_SCDR 0x09 - -// IT8172 IT_SCR_SFR bit definition & mask -#define IT_SCR_SFR_GATE_UART 0x40 -#define IT_SCR_SFR_GATE_UART_BIT 6 -#define IT_SCR_SFR_GATE_UART_OFF 0 -#define IT_SCR_SFR_GATE_UART_ON 1 -#define IT_SCR_SFR_FET_CHARGE 0x30 -#define IT_SCR_SFR_FET_CHARGE_BIT 4 -#define IT_SCR_SFR_FET_CHARGE_3_3_US 3 -#define IT_SCR_SFR_FET_CHARGE_13_US 2 -#define IT_SCR_SFR_FET_CHARGE_53_US 1 -#define IT_SCR_SFR_FET_CHARGE_213_US 0 -#define IT_SCR_SFR_CARD_FREQ 0x0C -#define IT_SCR_SFR_CARD_FREQ_BIT 2 -#define IT_SCR_SFR_CARD_FREQ_STOP 3 -#define IT_SCR_SFR_CARD_FREQ_3_5_MHZ 0 -#define IT_SCR_SFR_CARD_FREQ_7_1_MHZ 2 -#define IT_SCR_SFR_CARD_FREQ_96_DIV_MHZ 1 -#define IT_SCR_SFR_FET_ACTIVE 0x02 -#define IT_SCR_SFR_FET_ACTIVE_BIT 1 -#define IT_SCR_SFR_FET_ACTIVE_INVERT 0 -#define IT_SCR_SFR_FET_ACTIVE_NONINVERT 1 -#define IT_SCR_SFR_ENABLE 0x01 -#define IT_SCR_SFR_ENABLE_BIT 0 -#define IT_SCR_SFR_ENABLE_OFF 0 -#define IT_SCR_SFR_ENABLE_ON 1 - -// IT8172 IT_SCR_SCDR bit definition & mask -#define IT_SCR_SCDR_RESET_MODE 0x80 -#define IT_SCR_SCDR_RESET_MODE_BIT 7 -#define IT_SCR_SCDR_RESET_MODE_ASYNC 0 -#define IT_SCR_SCDR_RESET_MODE_SYNC 1 -#define IT_SCR_SCDR_DIVISOR 0x7F -#define IT_SCR_SCDR_DIVISOR_BIT 0 -#define IT_SCR_SCDR_DIVISOR_STOP_VAL_1 0x00 -#define IT_SCR_SCDR_DIVISOR_STOP_VAL_2 0x01 -#define IT_SCR_SCDR_DIVISOR_STOP_VAL_3 0x7F - -// IT8172 DMA -#define IT_DMAC_BASE 0x16000 -#define IT_DMAC_BCAR0 0x00 -#define IT_DMAC_BCAR1 0x04 -#define IT_DMAC_BCAR2 0x08 -#define IT_DMAC_BCAR3 0x0C -#define IT_DMAC_BCCR0 0x02 -#define IT_DMAC_BCCR1 0x06 -#define IT_DMAC_BCCR2 0x0a -#define IT_DMAC_BCCR3 0x0e -#define IT_DMAC_CR 0x10 -#define IT_DMAC_SR 0x12 -#define IT_DMAC_ESR 0x13 -#define IT_DMAC_RQR 0x14 -#define IT_DMAC_MR 0x16 -#define IT_DMAC_EMR 0x17 -#define IT_DMAC_MKR 0x18 -#define IT_DMAC_PAR0 0x20 -#define IT_DMAC_PAR1 0x22 -#define IT_DMAC_PAR2 0x24 -#define IT_DMAC_PAR3 0x26 - -// IT8172 IDE -#define IT_IDE_BASE 0x17800 -#define IT_IDE_STATUS 0x1F7 - -// IT8172 Audio Controller -#define IT_AC_BASE 0x17000 -#define IT_AC_PCMOV 0x00 -#define IT_AC_FMOV 0x02 -#define IT_AC_I2SV 0x04 -#define IT_AC_DRSS 0x06 -#define IT_AC_PCC 0x08 -#define IT_AC_PCDL 0x0A -#define IT_AC_PCB1STA 0x0C -#define IT_AC_PCB2STA 0x10 -#define IT_AC_CAPCC 0x14 -#define IT_AC_CAPCDL 0x16 -#define IT_AC_CAPB1STA 0x18 -#define IT_AC_CAPB2STA 0x1C -#define IT_AC_CODECC 0x22 -#define IT_AC_I2SMC 0x24 -#define IT_AC_VS 0x26 -#define IT_AC_SRCS 0x28 -#define IT_AC_CIRCP 0x2A -#define IT_AC_CIRDP 0x2C -#define IT_AC_TM 0x4A -#define IT_AC_PFDP 0x4C -#define IT_AC_GC 0x54 -#define IT_AC_IMC 0x56 -#define IT_AC_ISC 0x5B -#define IT_AC_OPL3SR 0x68 -#define IT_AC_OPL3DWDR 0x69 -#define IT_AC_OPL3AB1W 0x6A -#define IT_AC_OPL3DW 0x6B -#define IT_AC_BPDC 0x70 - - -// IT8172 Timer -#define IT_TIMER_BASE 0x10800 -#define TIMER_TCVR0 0x00 -#define TIMER_TRVR0 0x02 -#define TIMER_TCR0 0x04 -#define TIMER_TIRR 0x06 -#define TIMER_TCVR1 0x08 -#define TIMER_TRVR1 0x0A -#define TIMER_TCR1 0x0C -#define TIMER_TIDR 0x0E - - -#define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data -#define IT_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) - -#define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data -#define IT_IO_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) - -#define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data -#define IT_IO_READ16(ofs, data) data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/it8172/it8172_cir.h mips/include/asm-mips/it8172/it8172_cir.h --- mips-orig/include/asm-mips/it8172/it8172_cir.h 2006-10-02 22:33:08.584158000 +0900 +++ mips/include/asm-mips/it8172/it8172_cir.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,140 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * IT8172 Consumer IR port defines. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#define NUM_CIR_PORTS 2 - -/* Master Control Register */ -#define CIR_RESET 0x1 -#define CIR_FIFO_CLEAR 0x2 -#define CIR_SET_FIFO_TL(x) (((x)&0x3)<<2) -#define CIR_ILE 0x10 -#define CIR_ILSEL 0x20 - -/* Interrupt Enable Register */ -#define CIR_TLDLIE 0x1 -#define CIR_RDAIE 0x2 -#define CIR_RFOIE 0x4 -#define CIR_IEC 0x80 - -/* Interrupt Identification Register */ -#define CIR_TLDLI 0x1 -#define CIR_RDAI 0x2 -#define CIR_RFOI 0x4 -#define CIR_NIP 0x80 - -/* Carrier Frequency Register */ -#define CIR_SET_CF(x) ((x)&0x1f) - #define CFQ_38_480 0xB /* 38 KHz low, 480 KHz high */ -#define CIR_HCFS 0x20 - #define CIR_SET_HS(x) (((x)&0x1)<<5) - - -/* Receiver Control Register */ -#define CIR_SET_RXDCR(x) ((x)&0x7) -#define CIR_RXACT 0x8 -#define CIR_RXEND 0x10 -#define CIR_RDWOS 0x20 - #define CIR_SET_RDWOS(x) (((x)&0x1)<<5) -#define CIR_RXEN 0x80 - -/* Transmitter Control Register */ -#define CIR_SET_TXMPW(x) ((x)&0x7) -#define CIR_SET_TXMPM(x) (((x)&0x3)<<3) -#define CIR_TXENDF 0x20 -#define CIR_TXRLE 0x40 - -/* Receiver FIFO Status Register */ -#define CIR_RXFBC_MASK 0x3f -#define CIR_RXFTO 0x80 - -/* Wakeup Code Length Register */ -#define CIR_SET_WCL ((x)&0x3f) -#define CIR_WCL_MASK(x) ((x)&0x3f) - -/* Wakeup Power Control/Status Register */ -#define CIR_BTMON 0x2 -#define CIR_CIRON 0x4 -#define CIR_RCRST 0x10 -#define CIR_WCRST 0x20 - -struct cir_port { - int port; - unsigned short baud_rate; - unsigned char fifo_tl; - unsigned char cfq; - unsigned char hcfs; - unsigned char rdwos; - unsigned char rxdcr; -}; - -struct it8172_cir_regs { - unsigned char dr; /* data */ - char pad; - unsigned char mstcr; /* master control */ - char pad1; - unsigned char ier; /* interrupt enable */ - char pad2; - unsigned char iir; /* interrupt identification */ - char pad3; - unsigned char cfr; /* carrier frequency */ - char pad4; - unsigned char rcr; /* receiver control */ - char pad5; - unsigned char tcr; /* transmitter control */ - char pad6; - char pad7; - char pad8; - unsigned char bdlr; /* baud rate divisor low byte */ - char pad9; - unsigned char bdhr; /* baud rate divisor high byte */ - char pad10; - unsigned char tfsr; /* tx fifo byte count */ - char pad11; - unsigned char rfsr; /* rx fifo status */ - char pad12; - unsigned char wcl; /* wakeup code length */ - char pad13; - unsigned char wcr; /* wakeup code read/write */ - char pad14; - unsigned char wps; /* wakeup power control/status */ -}; - -int cir_port_init(struct cir_port *cir); -extern void clear_fifo(struct cir_port *cir); -extern void enable_receiver(struct cir_port *cir); -extern void disable_receiver(struct cir_port *cir); -extern void enable_rx_demodulation(struct cir_port *cir); -extern void disable_rx_demodulation(struct cir_port *cir); -extern void set_rx_active(struct cir_port *cir); -extern void int_enable(struct cir_port *cir); -extern void rx_int_enable(struct cir_port *cir); -extern char get_int_status(struct cir_port *cir); -extern int cir_get_rx_count(struct cir_port *cir); -extern char cir_read_data(struct cir_port *cir); diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/it8172/it8172_dbg.h mips/include/asm-mips/it8172/it8172_dbg.h --- mips-orig/include/asm-mips/it8172/it8172_dbg.h 2006-10-02 22:33:08.584158000 +0900 +++ mips/include/asm-mips/it8172/it8172_dbg.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,38 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Function prototypes for low level uart routines to - * directly access a 16550 uart. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include - -extern void putch(const unsigned char c); -extern void puts(unsigned char *cp); -extern void fputs(unsigned char *cp); -extern void put64(uint64_t ul); -extern void put32(unsigned u); diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/it8172/it8172_int.h mips/include/asm-mips/it8172/it8172_int.h --- mips-orig/include/asm-mips/it8172/it8172_int.h 2006-10-02 22:33:08.588158250 +0900 +++ mips/include/asm-mips/it8172/it8172_int.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,144 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * ITE 8172 Interrupt Numbering - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _MIPS_ITEINT_H -#define _MIPS_ITEINT_H - -/* - * Here's the "strategy": - * We number the LPC serial irqs from 0 to 15, - * the local bus irqs from 16 to 31, - * the pci dev register interrupts from 32 to 47, - * and the non-maskable ints from 48 to 53. - */ - -#define IT8172_LPC_IRQ_BASE 0 /* first LPC int number */ -#define IT8172_SERIRQ_0 (IT8172_LPC_IRQ_BASE + 0) -#define IT8172_SERIRQ_1 (IT8172_LPC_IRQ_BASE + 1) -#define IT8172_SERIRQ_2 (IT8172_LPC_IRQ_BASE + 2) -#define IT8172_SERIRQ_3 (IT8172_LPC_IRQ_BASE + 3) -#define IT8172_SERIRQ_4 (IT8172_LPC_IRQ_BASE + 4) -#define IT8172_SERIRQ_5 (IT8172_LPC_IRQ_BASE + 5) -#define IT8172_SERIRQ_6 (IT8172_LPC_IRQ_BASE + 6) -#define IT8172_SERIRQ_7 (IT8172_LPC_IRQ_BASE + 7) -#define IT8172_SERIRQ_8 (IT8172_LPC_IRQ_BASE + 8) -#define IT8172_SERIRQ_9 (IT8172_LPC_IRQ_BASE + 9) -#define IT8172_SERIRQ_10 (IT8172_LPC_IRQ_BASE + 10) -#define IT8172_SERIRQ_11 (IT8172_LPC_IRQ_BASE + 11) -#define IT8172_SERIRQ_12 (IT8172_LPC_IRQ_BASE + 12) -#define IT8172_SERIRQ_13 (IT8172_LPC_IRQ_BASE + 13) -#define IT8172_SERIRQ_14 (IT8172_LPC_IRQ_BASE + 14) -#define IT8172_SERIRQ_15 (IT8172_LPC_IRQ_BASE + 15) - -#define IT8172_LB_IRQ_BASE 16 /* first local bus int number */ -#define IT8172_PPR_IRQ (IT8172_LB_IRQ_BASE + 0) /* parallel port */ -#define IT8172_TIMER0_IRQ (IT8172_LB_IRQ_BASE + 1) -#define IT8172_TIMER1_IRQ (IT8172_LB_IRQ_BASE + 2) -#define IT8172_I2C_IRQ (IT8172_LB_IRQ_BASE + 3) -#define IT8172_GPIO_IRQ (IT8172_LB_IRQ_BASE + 4) -#define IT8172_CIR0_IRQ (IT8172_LB_IRQ_BASE + 5) -#define IT8172_CIR1_IRQ (IT8172_LB_IRQ_BASE + 6) -#define IT8172_UART_IRQ (IT8172_LB_IRQ_BASE + 7) -#define IT8172_SCR0_IRQ (IT8172_LB_IRQ_BASE + 8) -#define IT8172_SCR1_IRQ (IT8172_LB_IRQ_BASE + 9) -#define IT8172_RTC_IRQ (IT8172_LB_IRQ_BASE + 10) -#define IT8172_IOCHK_IRQ (IT8172_LB_IRQ_BASE + 11) -/* 12 - 15 reserved */ - -/* - * Note here that the pci dev registers includes bits for more than - * just the pci devices. - */ -#define IT8172_PCI_DEV_IRQ_BASE 32 /* first pci dev irq */ -#define IT8172_AC97_IRQ (IT8172_PCI_DEV_IRQ_BASE + 0) -#define IT8172_MC68K_IRQ (IT8172_PCI_DEV_IRQ_BASE + 1) -#define IT8172_IDE_IRQ (IT8172_PCI_DEV_IRQ_BASE + 2) -#define IT8172_USB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 3) -#define IT8172_BRIDGE_MASTER_IRQ (IT8172_PCI_DEV_IRQ_BASE + 4) -#define IT8172_BRIDGE_TARGET_IRQ (IT8172_PCI_DEV_IRQ_BASE + 5) -#define IT8172_PCI_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 6) -#define IT8172_PCI_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 7) -#define IT8172_PCI_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 8) -#define IT8172_PCI_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 9) -#define IT8172_S_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 10) -#define IT8172_S_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 11) -#define IT8172_S_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 12) -#define IT8172_S_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 13) -#define IT8172_CDMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 14) -#define IT8172_DMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 15) - -#define IT8172_NMI_IRQ_BASE 48 -#define IT8172_SER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 0) -#define IT8172_PCI_NMI_IRQ (IT8172_NMI_IRQ_BASE + 1) -#define IT8172_RTC_NMI_IRQ (IT8172_NMI_IRQ_BASE + 2) -#define IT8172_CPUIF_NMI_IRQ (IT8172_NMI_IRQ_BASE + 3) -#define IT8172_PMER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 4) -#define IT8172_POWER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 5) - -#define IT8172_LAST_IRQ (IT8172_POWER_NMI_IRQ) -/* Finally, let's move over here the mips cpu timer interrupt. - */ -#define MIPS_CPU_TIMER_IRQ (NR_IRQS-1) - -/* - * IT8172 Interrupt Controller Registers - */ -struct it8172_intc_regs { - volatile unsigned short lb_req; /* offset 0 */ - volatile unsigned short lb_mask; - volatile unsigned short lb_trigger; - volatile unsigned short lb_level; - unsigned char pad0[8]; - - volatile unsigned short lpc_req; /* offset 0x10 */ - volatile unsigned short lpc_mask; - volatile unsigned short lpc_trigger; - volatile unsigned short lpc_level; - unsigned char pad1[8]; - - volatile unsigned short pci_req; /* offset 0x20 */ - volatile unsigned short pci_mask; - volatile unsigned short pci_trigger; - volatile unsigned short pci_level; - unsigned char pad2[8]; - - volatile unsigned short nmi_req; /* offset 0x30 */ - volatile unsigned short nmi_mask; - volatile unsigned short nmi_trigger; - volatile unsigned short nmi_level; - unsigned char pad3[6]; - - volatile unsigned short nmi_redir; /* offset 0x3E */ - unsigned char pad4[0xBE]; - - volatile unsigned short intstatus; /* offset 0xFE */ -}; - -#endif /* _MIPS_ITEINT_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/it8172/it8172_pci.h mips/include/asm-mips/it8172/it8172_pci.h --- mips-orig/include/asm-mips/it8172/it8172_pci.h 2006-10-02 22:33:08.588158250 +0900 +++ mips/include/asm-mips/it8172/it8172_pci.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,108 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * IT8172 system controller specific pci defines. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _8172PCI_H_ -#define _8172PCI_H_ - -// PCI configuration space Type0 -#define PCI_IDREG 0x00 -#define PCI_CMDSTSREG 0x04 -#define PCI_CLASSREG 0x08 -#define PCI_BHLCREG 0x0C -#define PCI_BASE1REG 0x10 -#define PCI_BASE2REG 0x14 -#define PCI_BASE3REG 0x18 -#define PCI_BASE4REG 0x1C -#define PCI_BASE5REG 0x20 -#define PCI_BASE6REG 0x24 -#define PCI_ROMBASEREG 0x30 -#define PCI_INTRREG 0x3C - -// PCI configuration space Type1 -#define PCI_BUSNOREG 0x18 - -#define IT_PCI_VENDORID(x) ((x) & 0xFFFF) -#define IT_PCI_DEVICEID(x) (((x)>>16) & 0xFFFF) - -// Command register -#define PCI_CMD_IOEN 0x00000001 -#define PCI_CMD_MEMEN 0x00000002 -#define PCI_CMD_BUSMASTER 0x00000004 -#define PCI_CMD_SPCYCLE 0x00000008 -#define PCI_CMD_WRINV 0x00000010 -#define PCI_CMD_VGASNOOP 0x00000020 -#define PCI_CMD_PERR 0x00000040 -#define PCI_CMD_WAITCTRL 0x00000080 -#define PCI_CMD_SERR 0x00000100 -#define PCI_CMD_FAST_BACKTOBACK 0x00000200 - -// Status register -#define PCI_STS_66MHZ 0x00200000 -#define PCI_STS_SUPPORT_UDF 0x00400000 -#define PCI_STS_FAST_BACKTOBACK 0x00800000 -#define PCI_STS_DATA_PERR 0x01000000 -#define PCI_STS_DEVSEL0 0x02000000 -#define PCI_STS_DEVSEL1 0x04000000 -#define PCI_STS_SIG_TGTABORT 0x08000000 -#define PCI_STS_RCV_TGTABORT 0x10000000 -#define PCI_STS_RCV_MSTABORT 0x20000000 -#define PCI_STS_SYSERR 0x40000000 -#define PCI_STS_DETCT_PERR 0x80000000 - -#define IT_PCI_CLASS(x) (((x)>>24) & 0xFF) -#define IT_PCI_SUBCLASS(x) (((x)>>16) & 0xFF) -#define IT_PCI_INTERFACE(x) (((x)>>8) & 0xFF) -#define IT_PCI_REVISION(x) ((x) & 0xFF) - -// PCI class code -#define PCI_CLASS_BRIDGE 0x06 - -// bridge subclass -#define PCI_SUBCLASS_BRIDGE_HOST 0x00 -#define PCI_SUBCLASS_BRIDGE_PCI 0x04 - -// BHLCREG -#define IT_PCI_BIST(x) (((x)>>24) & 0xFF) -#define IT_PCI_HEADERTYPE(x) (((x)>>16) & 0xFF) -#define IT_PCI_LATENCYTIMER(x) (((x)>>8) & 0xFF) -#define IT_PCI_CACHELINESIZE(x) ((x) & 0xFF) - -#define PCI_MULTIFUNC 0x80 - -// INTRREG -#define IT_PCI_MAXLAT(x) (((x)>>24) & 0xFF) -#define IT_PCI_MINGNT(x) (((x)>>16) & 0xFF) -#define IT_PCI_INTRPIN(x) (((x)>>8) & 0xFF) -#define IT_PCI_INTRLINE(x) ((x) & 0xFF) - -#define PCI_VENDOR_NEC 0x1033 -#define PCI_VENDOR_DEC 0x1101 - -#endif // _8172PCI_H_ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/it8712.h mips/include/asm-mips/it8712.h --- mips-orig/include/asm-mips/it8712.h 2006-10-02 22:33:08.588158250 +0900 +++ mips/include/asm-mips/it8712.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,28 +0,0 @@ - -#ifndef __IT8712_H__ -#define __IT8712_H__ - -#define LPC_BASE_ADDR 0x14000000 - -// MB PnP configuration register -#define LPC_KEY_ADDR 0x1400002E -#define LPC_DATA_ADDR 0x1400002F - -// Device LDN -#define LDN_SERIAL1 0x01 -#define LDN_SERIAL2 0x02 -#define LDN_PARALLEL 0x03 -#define LDN_KEYBOARD 0x05 -#define LDN_MOUSE 0x06 - -#define IT8712_UART1_PORT 0x3F8 -#define IT8712_UART2_PORT 0x2F8 - -#ifndef ASM_ONLY - -void LPCSetConfig(char LdnNumber, char Index, char data); -char LPCGetConfig(char LdnNumber, char Index); - -#endif - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/serial.h mips/include/asm-mips/serial.h --- mips-orig/include/asm-mips/serial.h 2006-10-02 22:43:55.408582000 +0900 +++ mips/include/asm-mips/serial.h 2006-10-02 22:44:01.324951750 +0900 @@ -69,38 +69,6 @@ #define EV64120_SERIAL_PORT_DEFNS #endif -#ifdef CONFIG_MIPS_ITE8172 -#include -#include -#include -#define ITE_SERIAL_PORT_DEFNS \ - { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \ - .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \ - { .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \ - .irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \ - /* Smart Card Reader 0 */ \ - { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \ - .irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \ - /* Smart Card Reader 1 */ \ - { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \ - .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, -#else -#define ITE_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_MIPS_IVR -#include -#include -#define IVR_SERIAL_PORT_DEFNS \ - { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \ - .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \ - /* Smart Card Reader 1 */ \ - { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \ - .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, -#else -#define IVR_SERIAL_PORT_DEFNS -#endif - #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT #define STD_SERIAL_PORT_DEFNS \ /* UART CLK PORT IRQ FLAGS */ \ @@ -141,8 +109,6 @@ DDB5477_SERIAL_PORT_DEFNS \ EV64120_SERIAL_PORT_DEFNS \ IP32_SERIAL_PORT_DEFNS \ - ITE_SERIAL_PORT_DEFNS \ - IVR_SERIAL_PORT_DEFNS \ JAZZ_SERIAL_PORT_DEFNS \ STD_SERIAL_PORT_DEFNS From christoph@schroedinger.engr.sgi.com Mon Oct 2 17:00:48 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Oct 2006 17:00:50 +0100 (BST) Received: from omx1-ext.sgi.com ([192.48.179.11]:13959 "EHLO omx1.americas.sgi.com") by ftp.linux-mips.org with ESMTP id S20038834AbWJBQAs (ORCPT ); Mon, 2 Oct 2006 17:00:48 +0100 Received: from imr2.americas.sgi.com (imr2.americas.sgi.com [198.149.16.18]) by omx1.americas.sgi.com (8.12.10/8.12.9/linux-outbound_gateway-1.1) with ESMTP id k92G0inx022557; Mon, 2 Oct 2006 11:00:44 -0500 Received: from spindle.corp.sgi.com (spindle.corp.sgi.com [198.29.75.13]) by imr2.americas.sgi.com (8.12.9/8.12.10/SGI_generic_relay-1.2) with ESMTP id k92FtTDu57879940; Mon, 2 Oct 2006 08:55:29 -0700 (PDT) Received: from schroedinger.engr.sgi.com (schroedinger.engr.sgi.com [163.154.5.55]) by spindle.corp.sgi.com (SGI-8.12.5/8.12.9/generic_config-1.2) with ESMTP id k92G0hnB59520631; Mon, 2 Oct 2006 09:00:43 -0700 (PDT) Received: from christoph (helo=localhost) by schroedinger.engr.sgi.com with local-esmtp (Exim 3.36 #1 (Debian)) id 1GUQDj-0003CC-00; Mon, 02 Oct 2006 09:00:43 -0700 Date: Mon, 2 Oct 2006 09:00:43 -0700 (PDT) From: Christoph Lameter To: Atsushi Nemoto cc: girishvg@gmail.com, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] fix size of zones_size and zholes_size array In-Reply-To: <20061001.233306.126574447.anemo@mba.ocn.ne.jp> Message-ID: References: <20060930.033406.104030456.anemo@mba.ocn.ne.jp> <20061001.233306.126574447.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12767 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: clameter@sgi.com Precedence: bulk X-list: linux-mips On Sun, 1 Oct 2006, Atsushi Nemoto wrote: > > Nemoto~san, this was your patch earlier. > > > > void __init paging_init(void) > > { > > - unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0}; > > + unsigned long zones_size[] = { [0 ... MAX_NR_ZONES - 1] = 0 }; > > unsigned long max_dma, high, low; > > +#ifdef CONFIG_SPARSEMEM > > + unsigned long zholes_size[] = { [0 ... MAX_NR_ZONES - 1] = 0 }; > > + unsigned long i, j, pfn; > > +#endif > > Yes. This is correct. And then there was a conflict on this commit. Looks fine to me too. In that case you can drop the piece of my patch. From ralf@linux-mips.org Tue Oct 3 00:34:43 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 00:34:45 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:58058 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20038685AbWJBXen (ORCPT ); Tue, 3 Oct 2006 00:34:43 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k92FI1oI025416; Mon, 2 Oct 2006 16:19:21 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k92FI0cW025415; Mon, 2 Oct 2006 16:18:00 +0100 Date: Mon, 2 Oct 2006 16:18:00 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH] remove Momentum / PMC-Sierra Jaguar ATX evaluation board Message-ID: <20061002151800.GA25180@linux-mips.org> References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12768 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Oct 02, 2006 at 11:14:32PM +0900, Yoichi Yuasa wrote: > This patch has removed Momentum / PMC-Sierra Jaguar ATX evaluation board support. > It was scheduled to be removed after 2.6.18 released. Stanislaw Skowronek raised his hand to take care of all the Jaguar / Ocelot boards, so I'll remove them from the list for now. Ralf From yoichi_yuasa@tripeaks.co.jp Tue Oct 3 02:44:14 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 02:44:17 +0100 (BST) Received: from mo30.po.2iij.net ([210.128.50.53]:36356 "EHLO mo30.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20038837AbWJCBoO (ORCPT ); Tue, 3 Oct 2006 02:44:14 +0100 Received: by mo.po.2iij.net (mo30) id k931iAwG006033; Tue, 3 Oct 2006 10:44:10 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox32) id k931i4TD002658 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 3 Oct 2006 10:44:04 +0900 (JST) Message-Id: <200610030144.k931i4TD002658@mbox32.po.2iij.net> Date: Tue, 3 Oct 2006 10:44:04 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips@linux-mips.org Subject: Re: [PATCH] remove Momentum / PMC-Sierra Jaguar ATX evaluation board In-Reply-To: <20061002151800.GA25180@linux-mips.org> References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12769 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, On Mon, 2 Oct 2006 16:18:00 +0100 Ralf Baechle wrote: > On Mon, Oct 02, 2006 at 11:14:32PM +0900, Yoichi Yuasa wrote: > > > This patch has removed Momentum / PMC-Sierra Jaguar ATX evaluation board support. > > It was scheduled to be removed after 2.6.18 released. > > Stanislaw Skowronek raised his hand to take care of all the Jaguar / > Ocelot boards, so I'll remove them from the list for now. OK. How about MIPS Technologies boards on the list? Yoichi From pak.woon@nec.com.au Tue Oct 3 08:57:16 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 08:57:20 +0100 (BST) Received: from ns2.nec.com.au ([147.76.180.2]:4266 "EHLO ns2.nec.com.au") by ftp.linux-mips.org with ESMTP id S20037761AbWJCH5Q (ORCPT ); Tue, 3 Oct 2006 08:57:16 +0100 Received: from smtp1.nec.com.au (unknown [172.31.8.18]) by ns2.nec.com.au (Postfix) with ESMTP id 70CD33B6B6 for ; Tue, 3 Oct 2006 17:57:04 +1000 (EST) Received: from [147.76.208.162] ([147.76.208.162]) by tns.neca.nec.com.au (8.12.8/8.12.8) with ESMTP id k9382jZl030035 for ; Tue, 3 Oct 2006 18:02:48 +1000 Message-ID: <4522175B.80901@nec.com.au> Date: Tue, 03 Oct 2006 17:55:07 +1000 From: Pak Woon User-Agent: Mozilla Thunderbird 1.0.2 (Windows/20050317) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Roll-your-own Toolchain Builds References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> In-Reply-To: <200610030144.k931i4TD002658@mbox32.po.2iij.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12770 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pak.woon@nec.com.au Precedence: bulk X-list: linux-mips Hi all, I am trying to roll-my-own toolchain by following the instructions outlined in http://www.linux-mips.org/wiki/Toolchains. I have encountered the "cannot create executables" / "crt01.o: No such file" problem. There are a lot of people who see the same thing, but there does not seem to be a definative answer. FYI, my packages are:- binutils-2.16.91.0.6-5 gcc-4.1.1-1.fc5 lib-gcc-4.1.1-1.fc5 gcc-gfortran-4.1.1-1.fc5 gcc-g++-4.1.1-1.fc5 Regards, Pak From yoichi_yuasa@tripeaks.co.jp Tue Oct 3 09:33:10 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 09:33:11 +0100 (BST) Received: from mo32.po.2iij.net ([210.128.50.17]:22589 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20037845AbWJCIdK (ORCPT ); Tue, 3 Oct 2006 09:33:10 +0100 Received: by mo.po.2iij.net (mo32) id k938X6Xb009831; Tue, 3 Oct 2006 17:33:06 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox32) id k938X4UJ011881 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 3 Oct 2006 17:33:04 +0900 (JST) Date: Tue, 3 Oct 2006 17:33:04 +0900 From: Yoichi Yuasa To: Pak Woon Cc: linux-mips@linux-mips.org Subject: Re: Roll-your-own Toolchain Builds Message-Id: <20061003173304.04e8b907.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <4522175B.80901@nec.com.au> References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> <4522175B.80901@nec.com.au> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12771 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips On Tue, 03 Oct 2006 17:55:07 +1000 Pak Woon wrote: > Hi all, > > I am trying to roll-my-own toolchain by following the instructions > outlined in http://www.linux-mips.org/wiki/Toolchains. I have > encountered the "cannot create executables" / "crt01.o: No such file" > problem. There are a lot of people who see the same thing, but there > does not seem to be a definative answer. When did you get the message? building toolchain or ... > FYI, my packages are:- > binutils-2.16.91.0.6-5 > gcc-4.1.1-1.fc5 > lib-gcc-4.1.1-1.fc5 > gcc-gfortran-4.1.1-1.fc5 > gcc-g++-4.1.1-1.fc5 Did you install glibc-devel package? Yoichi From daniel@haxx.se Tue Oct 3 09:37:23 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 09:37:26 +0100 (BST) Received: from kluster2.contactor.se ([193.15.23.26]:4544 "EHLO kluster2.contactor.se") by ftp.linux-mips.org with ESMTP id S20037815AbWJCIhX (ORCPT ); Tue, 3 Oct 2006 09:37:23 +0100 Received: from linux3.contactor.se (linux3.contactor.se [193.15.23.23]) by kluster2.contactor.se (8.13.4/8.13.4/Debian-3sarge3) with ESMTP id k938bGtr004335; Tue, 3 Oct 2006 10:37:16 +0200 Date: Tue, 3 Oct 2006 10:37:16 +0200 (CEST) From: Daniel Stenberg X-X-Sender: dast@linux3.contactor.se To: Pak Woon cc: linux-mips@linux-mips.org Subject: Re: Roll-your-own Toolchain Builds In-Reply-To: <4522175B.80901@nec.com.au> Message-ID: References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> <4522175B.80901@nec.com.au> X-fromdanielhimself: yes MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed X-Virus-Scanned: ClamAV version 0.84, clamav-milter version 0.84e on kluster2.contactor.se X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12772 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: daniel@haxx.se Precedence: bulk X-list: linux-mips On Tue, 3 Oct 2006, Pak Woon wrote: > I am trying to roll-my-own toolchain by following the instructions outlined > in http://www.linux-mips.org/wiki/Toolchains. > binutils-2.16.91.0.6-5 > gcc-4.1.1-1.fc5 Funny, since that page says that the recommended gcc version is 3.4.4 and binutils 2.16.1... (even though I've had no problems with 3.4.6 myself) From pak.woon@nec.com.au Tue Oct 3 09:52:39 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 09:52:41 +0100 (BST) Received: from ns2.nec.com.au ([147.76.180.2]:37295 "EHLO ns2.nec.com.au") by ftp.linux-mips.org with ESMTP id S20037889AbWJCIwj (ORCPT ); Tue, 3 Oct 2006 09:52:39 +0100 Received: from smtp1.nec.com.au (unknown [172.31.8.18]) by ns2.nec.com.au (Postfix) with ESMTP id 4021C3B6A7 for ; Tue, 3 Oct 2006 18:52:32 +1000 (EST) Received: from [147.76.208.162] ([147.76.208.162]) by tns.neca.nec.com.au (8.12.8/8.12.8) with ESMTP id k938wFZl031204; Tue, 3 Oct 2006 18:58:16 +1000 Message-ID: <4522245D.4020801@nec.com.au> Date: Tue, 03 Oct 2006 18:50:37 +1000 From: Pak Woon User-Agent: Mozilla Thunderbird 1.0.2 (Windows/20050317) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Yoichi Yuasa Cc: linux-mips@linux-mips.org Subject: Re: Roll-your-own Toolchain Builds References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> <4522175B.80901@nec.com.au> <20061003173304.04e8b907.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20061003173304.04e8b907.yoichi_yuasa@tripeaks.co.jp> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12773 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pak.woon@nec.com.au Precedence: bulk X-list: linux-mips >>I am trying to roll-my-own toolchain by following the instructions >>outlined in http://www.linux-mips.org/wiki/Toolchains. I have >>encountered the "cannot create executables" / "crt01.o: No such file" >>problem. There are a lot of people who see the same thing, but there >>does not seem to be a definative answer. > > > When did you get the message? During the "make -j2" command when building gcc > building toolchain or ... > > >>FYI, my packages are:- >>binutils-2.16.91.0.6-5 >>gcc-4.1.1-1.fc5 >>lib-gcc-4.1.1-1.fc5 >>gcc-gfortran-4.1.1-1.fc5 >>gcc-g++-4.1.1-1.fc5 > > > Did you install glibc-devel package? I have glibc-devel-2.4-11 > Yoichi > From macro@linux-mips.org Tue Oct 3 10:45:28 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 10:45:32 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:40972 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038330AbWJCJp2 (ORCPT ); Tue, 3 Oct 2006 10:45:28 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 1530CF61A3; Tue, 3 Oct 2006 11:45:24 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VtHde4pR2Z0a; Tue, 3 Oct 2006 11:45:23 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id B5308F619C; Tue, 3 Oct 2006 11:45:23 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k939jRRq012181; Tue, 3 Oct 2006 11:45:27 +0200 Date: Tue, 3 Oct 2006 10:45:24 +0100 (BST) From: "Maciej W. Rozycki" To: Yoichi Yuasa cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] remove Momentum / PMC-Sierra Jaguar ATX evaluation board In-Reply-To: <200610030144.k931i4TD002658@mbox32.po.2iij.net> Message-ID: References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1982/Tue Oct 3 07:04:49 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12774 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, 3 Oct 2006, Yoichi Yuasa wrote: > How about MIPS Technologies boards on the list? Both configurations affected build just fine now. The Atlas board needs an update for its serial driver that I have to send through RMK (which I'll try to do shortly) and the driver for the onboard 53c810 requires the missing iomap support. Otherwise it works fine with core cards using the Galileo system controller (others may have issues, which may or may not eventually be resolved). The SEAD board requires an update to its interrupt handler, which I'll code as soon as I find a couple of minutes to spare. It's nothing complicated, but I want to test it a little bit before committing. I need to find a useful way of running Linux on it though. ;-) Maciej From vitalywool@gmail.com Tue Oct 3 12:35:48 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 12:35:53 +0100 (BST) Received: from rtsoft2.corbina.net ([85.21.88.2]:24555 "HELO mail.dev.rtsoft.ru") by ftp.linux-mips.org with SMTP id S20038651AbWJCLfs (ORCPT ); Tue, 3 Oct 2006 12:35:48 +0100 Received: (qmail 27425 invoked from network); 3 Oct 2006 11:36:05 -0000 Received: from laja.dev.rtsoft.ru.dev.rtsoft.ru (HELO dev.rtsoft.ru.) (192.168.1.205) by mail.dev.rtsoft.ru with SMTP; 3 Oct 2006 11:36:05 -0000 Date: Tue, 3 Oct 2006 15:36:11 +0400 From: Vitaly Wool To: linux-mips@linux-mips.org Subject: [PATCH] add TV810 board support Message-Id: <20061003153611.def3118f.vitalywool@gmail.com> X-Mailer: Sylpheed version 2.2.6 (GTK+ 2.8.13; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12775 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vitalywool@gmail.com Precedence: bulk X-list: linux-mips Hello folks, inlined is the patch that adds support for TV810 board which is a small deviation :) from PNX8550 platform. arch/mips/Kconfig | 5 arch/mips/Makefile | 5 arch/mips/configs/pnx8550-stb810_defconfig | 1219 +++++++++++++++++++++++++ arch/mips/kernel/head.S | 2 arch/mips/philips/pnx8550/common/prom.c | 20 arch/mips/philips/pnx8550/stb810/Makefile | 4 arch/mips/philips/pnx8550/stb810/board_setup.c | 56 + arch/mips/philips/pnx8550/stb810/irqmap.c | 23 arch/mips/philips/pnx8550/stb810/prom_init.c | 49 + include/asm-mips/bootinfo.h | 1 10 files changed, 1369 insertions(+), 15 deletions(-) Signed-off-by: Vitaly Wool Signed-off-by: Vladimir Barinov Index: linux-mips.git/arch/mips/philips/pnx8550/stb810/Makefile =================================================================== --- /dev/null +++ linux-mips.git/arch/mips/philips/pnx8550/stb810/Makefile @@ -0,0 +1,4 @@ + +# Makefile for the Philips STB810 Board. + +lib-y := prom_init.o board_setup.o irqmap.o Index: linux-mips.git/arch/mips/philips/pnx8550/stb810/board_setup.c =================================================================== --- /dev/null +++ linux-mips.git/arch/mips/philips/pnx8550/stb810/board_setup.c @@ -0,0 +1,56 @@ +/* + * STB810 specific board startup routines. + * + * Based on the arch/mips/philips/pnx8550/jbs/board_setup.c + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +/* CP0 hazard avoidance. */ +#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +void __init board_setup(void) +{ + unsigned long config0, configpr; + + config0 = read_c0_config(); + + /* clear all three cache coherency fields */ + config0 &= ~(0x7 | (7<<25) | (7<<28)); + config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | + (CONF_CM_DEFAULT<<28)); + write_c0_config(config0); + BARRIER; + + configpr = read_c0_config7(); + configpr |= (1<<19); /* enable tlb */ + write_c0_config7(configpr); + BARRIER; +} Index: linux-mips.git/arch/mips/philips/pnx8550/stb810/irqmap.c =================================================================== --- /dev/null +++ linux-mips.git/arch/mips/philips/pnx8550/stb810/irqmap.c @@ -0,0 +1,23 @@ +/* + * Philips STB810 board irqmap. + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +char irq_tab_jbs[][5] __initdata = { + [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, + [10] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, +}; + Index: linux-mips.git/arch/mips/philips/pnx8550/stb810/prom_init.c =================================================================== --- /dev/null +++ linux-mips.git/arch/mips/philips/pnx8550/stb810/prom_init.c @@ -0,0 +1,49 @@ +/* + * STB810 specific prom routines + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "Philips PNX8550/STB810"; +} + +void __init prom_init(void) +{ + + unsigned long memsize; + prom_argc = (int) fw_arg0; + prom_argv = (char **) fw_arg1; + prom_envp = (char **) fw_arg2; + + prom_init_cmdline(); + + mips_machgroup = MACH_GROUP_PHILIPS; + mips_machtype = MACH_PHILIPS_STB810; + + memsize = 0x08000000; /* Trimedia uses memory above */ + add_memory_region(0, memsize, BOOT_MEM_RAM); +} Index: linux-mips.git/include/asm-mips/bootinfo.h =================================================================== --- linux-mips.git.orig/include/asm-mips/bootinfo.h +++ linux-mips.git/include/asm-mips/bootinfo.h @@ -137,6 +137,7 @@ #define MACH_PHILIPS_NINO 0 /* Nino */ #define MACH_PHILIPS_VELO 1 /* Velo */ #define MACH_PHILIPS_JBS 2 /* JBS */ +#define MACH_PHILIPS_STB810 3 /* STB810 */ /* * Valid machtype for group Globespan Index: linux-mips.git/arch/mips/philips/pnx8550/common/prom.c =================================================================== --- linux-mips.git.orig/arch/mips/philips/pnx8550/common/prom.c +++ linux-mips.git/arch/mips/philips/pnx8550/common/prom.c @@ -35,23 +35,15 @@ char * prom_getcmdline(void) return &(arcs_cmdline[0]); } -void prom_init_cmdline(void) +void __init prom_init_cmdline(void) { - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ + int i; - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; + arcs_cmdline[0] = '\0'; + for (i = 0; i < prom_argc; i++) { + strcat(arcs_cmdline, prom_argv[i]); + strcat(arcs_cmdline, " "); } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; } char *prom_getenv(char *envname) Index: linux-mips.git/arch/mips/kernel/head.S =================================================================== --- linux-mips.git.orig/arch/mips/kernel/head.S +++ linux-mips.git/arch/mips/kernel/head.S @@ -138,7 +138,7 @@ EXPORT(stext) # used for profiling EXPORT(_stext) -#if defined(CONFIG_QEMU) || defined(CONFIG_MIPS_SIM) +#if defined(CONFIG_QEMU) || defined(CONFIG_MIPS_SIM) || defined(CONFIG_PNX8550_STB810) /* * Give us a fighting chance of running if execution beings at the * kernel load address. This is needed because this platform does Index: linux-mips.git/arch/mips/configs/pnx8550-stb810_defconfig =================================================================== --- /dev/null +++ linux-mips.git/arch/mips/configs/pnx8550-stb810_defconfig @@ -0,0 +1,1219 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.18 +# Tue Oct 3 15:10:36 2006 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_WR_PPMC is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +CONFIG_PNX8550_STB810=y +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_MARKEINS is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_PNX8550=y +CONFIG_SOC_PNX8550=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMTC is not set +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_VPE_LOADER is not set +# CONFIG_64BIT_PHYS_ADDR is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_RELAY is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_HOTPLUG is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_SLAB=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODULE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +# CONFIG_PCI_MULTITHREAD_PROBE is not set +# CONFIG_PCI_DEBUG is not set +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# + +# +# PCI Hotplug Support +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECD=m +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +CONFIG_BLK_DEV_IDESCSI=y +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_IDEPCI_SHARE_IRQ=y +CONFIG_BLK_DEV_OFFBOARD=y +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +# CONFIG_IDEDMA_PCI_AUTO is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +CONFIG_BLK_DEV_HPT366=y +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_IDE_ARM is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_IVB is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set + +# +# SCSI low-level drivers +# +CONFIG_ISCSI_TCP=m +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Serial ATA (prod) and Parallel ATA (experimental) drivers +# +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +CONFIG_NATSEMI=y +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_LAN_SAA9730 is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_PNX8XXX is not set +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# + +# +# Hardware Monitoring support +# +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +CONFIG_VIDEO_V4L2=y + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_TOUCHSCREEN is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_ATI_REMOTE2 is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set +# CONFIG_USB_TRANCEVIBRATOR is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=m +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +CONFIG_DEBUG_SLAB=y +# CONFIG_DEBUG_SLAB_LEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB is not set +# CONFIG_RUNTIME_DEBUG is not set +# CONFIG_MIPS_UNCACHED is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=m +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +CONFIG_LIBCRC32C=m +CONFIG_PLIST=y Index: linux-mips.git/arch/mips/Kconfig =================================================================== --- linux-mips.git.orig/arch/mips/Kconfig +++ linux-mips.git/arch/mips/Kconfig @@ -480,6 +480,11 @@ config PNX8550_JBS select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN +config PNX8550_STB810 + bool "Support for Philips PNX8550 based STB810 board" + select PNX8550 + select SYS_SUPPORTS_LITTLE_ENDIAN + config DDB5477 bool "NEC DDB Vrc-5477" select DDB5XXX_COMMON Index: linux-mips.git/arch/mips/Makefile =================================================================== --- linux-mips.git.orig/arch/mips/Makefile +++ linux-mips.git/arch/mips/Makefile @@ -467,6 +467,11 @@ libs-$(CONFIG_PNX8550_JBS) += arch/mips/ #cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550 load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 +# Philips PNX8550 STB810 board +# +libs-$(CONFIG_PNX8550_STB810) += arch/mips/philips/pnx8550/stb810/ +load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000 + # NEC EMMA2RH boards # core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/ From ths@networkno.de Tue Oct 3 13:53:20 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 13:53:21 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:62169 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20038706AbWJCMxT (ORCPT ); Tue, 3 Oct 2006 13:53:19 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id CC1BB462C6; Tue, 3 Oct 2006 14:53:18 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GUicV-0001Kn-Ml; Tue, 03 Oct 2006 12:39:31 +0100 Date: Tue, 3 Oct 2006 12:39:31 +0100 To: Vitaly Wool Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] add TV810 board support Message-ID: <20061003113931.GE30302@networkno.de> References: <20061003153611.def3118f.vitalywool@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20061003153611.def3118f.vitalywool@gmail.com> User-Agent: Mutt/1.5.13 (2006-08-11) From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12776 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Vitaly Wool wrote: [snip] > +/* CP0 hazard avoidance. */ > +#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ > + "nop; nop; nop; nop; nop; nop;\n\t" \ > + ".set reorder\n\t") Didn't we just get rid of that BARRIER stuff? Thiemo From sathesh_edara2003@yahoo.co.in Tue Oct 3 15:35:52 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 15:35:59 +0100 (BST) Received: from web7913.mail.in.yahoo.com ([202.86.4.89]:56987 "HELO web7913.mail.in.yahoo.com") by ftp.linux-mips.org with SMTP id S20038873AbWJCOfw (ORCPT ); Tue, 3 Oct 2006 15:35:52 +0100 Received: (qmail 37397 invoked by uid 60001); 3 Oct 2006 14:35:45 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.co.in; h=Message-ID:Received:Date:From:Subject:To:Cc:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=MY9tr2kuW6EfQZedwCAhtDSFt7DUQXuxVssnTZ1TzQvfbFdumxondJFp5ZVV01YwXahHsuBa+MgfCOKuJICDvYBNKTf2DHwlHCiZpCWFxEJ6C2zin49giS6ToJwKVYcxFY1HtPAii+xw9kkmaHlXZZrM+gZLyGjNTp0/0LmXjO0= ; Message-ID: <20061003143545.37395.qmail@web7913.mail.in.yahoo.com> Received: from [61.246.223.98] by web7913.mail.in.yahoo.com via HTTP; Tue, 03 Oct 2006 15:35:44 BST Date: Tue, 3 Oct 2006 15:35:44 +0100 (BST) From: sathesh babu Subject: Re: linux-libc-headers-2.6.17 To: Jim Gifford , Jim Wilson Cc: sathesh babu , linux-mips@linux-mips.org In-Reply-To: <4512134B.40006@jg555.com> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="0-1092621611-1159886144=:35963" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12777 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sathesh_edara2003@yahoo.co.in Precedence: bulk X-list: linux-mips --0-1092621611-1159886144=:35963 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi Jim, I have downloaded 2.6.18 sanitized headers from the following link which was suggested by you. http://ftp.jg555.com/headers I am trying to build the toolchain for MIPS for linux-2.6.18 kernel using these headers and uClibc-0.9.28 and gcc-3.4.3. When i tried to compile busybox-1.00 i get the following error "undefined reference to `getpageshift' ". Then i searched in the mailing list and found your article http://linuxfromscratch.org/pipermail/lfs-dev/2006-July/057591.html I added the following definition for getpageshift(), suggested in the above link in the asm-mips/page.h file Here is a santized version > #define PAGE_SIZE (getpagesize()) > static __inline__ int getpageshift() > { > int pagesize = getpagesize(); > return (__builtin_clz(pagesize) ^ 31); > } I am not able to find definition for getpagesize().Can you please help me finding the definition for same. Is it in kernel or in userland?. BTW: I tried the same thing on Linux-2.6.17.13. I could build the toolchain by modifying the page.h as mentioned above. I could build the images for both Linux-2.6.17.13 and root file system for MIPS processor.But when i tried to execute any command pointing to busybox i was getting kernel crash. When i tried to debug this issue i found that "asm/page.h" file is included in some of the files in the busybox. Is this crash because of getpageshift() which is defined in asm-mips/page.h.?. What is the expected output of getpagesize()?. Could you advise a solution for this?. Regards, Sathesh Jim Gifford wrote: Jim Wilson wrote: > I'd suggest looking at Dan Kegel's crosstool package, which provides > scripts showing how to do a build from scratch. There is a pointer to > it on the www.linux-mips.org wiki. See > http://www.linux-mips.org/wiki/Toolchains > Actually my Cross-LFS team has created a sanitation script to clean the headers, you can get the script from http://headers.cross-lfs.org, or you can download a bundle from http://ftp.jg555.com/headers --------------------------------- Find out what India is talking about on - Yahoo! Answers India Send FREE SMS to your friend's mobile from Yahoo! Messenger Version 8. Get it NOW --0-1092621611-1159886144=:35963 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit
Hi Jim,
   
I have downloaded 2.6.18 sanitized headers from the following link which was suggested by you.
 
I am trying to build the toolchain for MIPS for linux-2.6.18 kernel using these headers and uClibc-0.9.28 and gcc-3.4.3.
When i tried to compile busybox-1.00 i get the following error
"undefined reference to `getpageshift' ".
 
Then i searched in the mailing list and found your article
 
I added the following definition for getpageshift(), suggested in the above link in the asm-mips/page.h file
 
 Here is a santized version
> #define PAGE_SIZE       (getpagesize())
> static __inline__ int getpageshift()
> {
>     int pagesize = getpagesize();
>     return (__builtin_clz(pagesize) ^ 31);
> }
I am not able to find definition for getpagesize().Can you please help me finding the definition for same. Is it in kernel or in userland?.
 
BTW:
 
  I tried the same thing on Linux-2.6.17.13. I could build the toolchain by modifying the page.h as mentioned above. I could build the images for both Linux-2.6.17.13 and root file system for MIPS processor.But when i tried to execute any command pointing to busybox i was getting kernel crash.
 
When i tried to debug this issue i found that "asm/page.h" file is included in some of the files in the busybox.
 
Is this crash because of getpageshift() which is defined in asm-mips/page.h.?.
 
What is the expected output of getpagesize()?.
 
Could you advise a solution for this?.
 
 
Regards,
Sathesh
 
 

Jim Gifford <maillist@jg555.com> wrote:
Jim Wilson wrote:
> I'd suggest looking at Dan Kegel's crosstool package, which provides
> scripts showing how to do a build from scratch. There is a pointer to
> it on the www.linux-mips.org wiki. See
> http://www.linux-mips.org/wiki/Toolchains
>
Actually my Cross-LFS team has created a sanitation script to clean the
headers, you can get the script from http://headers.cross-lfs.org, or
you can download a bundle from http://ftp.jg555.com/headers



Find out what India is talking about on - Yahoo! Answers India
Send FREE SMS to your friend's mobile from Yahoo! Messenger Version 8. Get it NOW --0-1092621611-1159886144=:35963-- From vagabon.xyz@gmail.com Tue Oct 3 15:43:52 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 15:43:54 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.185]:38023 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20037823AbWJCOnw (ORCPT ); Tue, 3 Oct 2006 15:43:52 +0100 Received: by nf-out-0910.google.com with SMTP id l23so184193nfc for ; Tue, 03 Oct 2006 07:43:51 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:reply-to:user-agent:mime-version:to:subject:content-type:content-transfer-encoding:from; b=WzLNzRcMG7pvK/Y1uy1mNxYojweL20ud4XJiNtdsHt/E5Fw/tsKRJrG8ONFKKNjjFxjf7RjUymRhcq5fDWWHzb75IzS79YmgxuZakRLm9dC1+MzYilWA1gy6+3z5SUNCBHowHpDQLTGnR1PmE+uXxs9I0wfPyedJLAknc3B53JA= Received: by 10.48.48.15 with SMTP id v15mr924082nfv; Tue, 03 Oct 2006 07:43:51 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.gmail.com with ESMTP id l32sm1218693nfa.2006.10.03.07.43.50; Tue, 03 Oct 2006 07:43:50 -0700 (PDT) Message-ID: <45227762.8090207@innova-card.com> Date: Tue, 03 Oct 2006 16:44:50 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: [RFC] setup.c: get ride of CPHYSADDR() Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12778 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips Hi, The following patch is an attempt to remove this macro in setup.c. I'm not sure about why sometimes it is used and sometimes it is not. By sending this RFC, I hope to get some feedbacks that will shed some light on this obscure macro... The reason why I'm trying to kick out this macro is that we should rely on __pa() for address convertions instead of having several helpers that do the same thing but differently. Futermore if some tricks are needed for these conversions, they should be done in one place. Thanks Franck -- >8 -- diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index fdbb508..00d62bd 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -204,12 +204,12 @@ static void __init finalize_initrd(void) printk(KERN_INFO "Initrd not found or empty"); goto disable; } - if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { + if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) { printk("Initrd extends beyond end of memory"); goto disable; } - reserve_bootmem(CPHYSADDR(initrd_start), size); + reserve_bootmem(__pa(initrd_start), size); initrd_below_start_ok = 1; printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", @@ -256,7 +256,7 @@ static void __init bootmem_init(void) * of usable memory. */ reserved_end = init_initrd(); - reserved_end = PFN_UP(CPHYSADDR(max(reserved_end, (unsigned long)&_end))); + reserved_end = PFN_UP(__pa(max(reserved_end, (unsigned long)&_end))); /* * Find the highest page frame number we have available. From macro@linux-mips.org Tue Oct 3 16:16:32 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 16:16:35 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:12037 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038706AbWJCPQc (ORCPT ); Tue, 3 Oct 2006 16:16:32 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 13420F62CC; Tue, 3 Oct 2006 17:16:28 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id i91M76rkR9YG; Tue, 3 Oct 2006 17:16:27 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id C2374F5BB4; Tue, 3 Oct 2006 17:16:27 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k93FGZEr004033; Tue, 3 Oct 2006 17:16:35 +0200 Date: Tue, 3 Oct 2006 16:16:30 +0100 (BST) From: "Maciej W. Rozycki" To: Franck Bui-Huu cc: linux-mips@linux-mips.org Subject: Re: [RFC] setup.c: get ride of CPHYSADDR() In-Reply-To: <45227762.8090207@innova-card.com> Message-ID: References: <45227762.8090207@innova-card.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1984/Tue Oct 3 12:01:28 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12779 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Franck, > The following patch is an attempt to remove this macro in setup.c. > I'm not sure about why sometimes it is used and sometimes it is > not. By sending this RFC, I hope to get some feedbacks that will shed > some light on this obscure macro... > > The reason why I'm trying to kick out this macro is that we should > rely on __pa() for address convertions instead of having several > helpers that do the same thing but differently. Futermore if some > tricks are needed for these conversions, they should be done in > one place. Have you verified it works correctly for 64-bit kernels linked at a KSEG0 address? Maciej From macro@linux-mips.org Tue Oct 3 16:18:01 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 16:18:02 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:30981 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038850AbWJCPSB (ORCPT ); Tue, 3 Oct 2006 16:18:01 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 3B49EF62E0; Tue, 3 Oct 2006 17:17:56 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nfNNYqXi6Zpm; Tue, 3 Oct 2006 17:17:55 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id C933EF62DF; Tue, 3 Oct 2006 17:17:55 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k93FI2pv004643; Tue, 3 Oct 2006 17:18:02 +0200 Date: Tue, 3 Oct 2006 16:17:57 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton , Jeff Garzik , Ralf Baechle , Andy Fleming cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: [patch 0/6] 2.6.18: sb1250-mac: Driver model & phylib update Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1984/Tue Oct 3 12:01:28 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12780 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Hello, Here is a set of patches that update the sb1250-mac driver used for the onchip Gigabit Ethernet interfaces of the Broadcom SiByte family of SOCs including the BCM1250 and a couple of other members. These are used, among others, on various Broadcom evaluation boards together with Broadcom Gigabit Ethernet PHY chips. Changes include porting the driver to the driver model as a platform device, support for phylib, including the BCM54xx PHYs in the interrupt mode, proper resource managment and a couple of minor clean-ups. Apart from changes to networking code, there are a few required in the architecture-specific areas and therefore I am sending these changes to Ralf and the linux-mips list as well. It might also involve a few more interested parties in the discussion. The changes were tested with a Broadcom SWARM board, which includes a BCM1250 part which has 3 MAC units on chip, of which 2 are usable, with BCM5421 PHY chips attached (both wired to the same interrupt line, which made testing whether IRQ sharing works properly in phylib possible). Link partners included a 1000base and a 100base interface doing autonegotiation as well as a 10base one doing none. Other Broadcom boards that I know of may have these or BCM5411 or BCM5461 chips. The lack of documentation or at least actual pieces of hardware makes the use of interrupts impossible for all but the SWARM, the Sentosa and the Shorty (with the latter unsupported by Linux). Maciej From macro@linux-mips.org Tue Oct 3 16:18:26 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 16:18:29 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:36357 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038883AbWJCPSP (ORCPT ); Tue, 3 Oct 2006 16:18:15 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id EE402F62DF; Tue, 3 Oct 2006 17:18:10 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id x3LQp-tkoyEA; Tue, 3 Oct 2006 17:18:10 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 3D84FF62DA; Tue, 3 Oct 2006 17:18:10 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k93FIHpk004728; Tue, 3 Oct 2006 17:18:17 +0200 Date: Tue, 3 Oct 2006 16:18:13 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton , Jeff Garzik , Ralf Baechle , Andy Fleming cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: [patch 1/6] 2.6.18: sb1250-mac: Broadcom PHY support Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1984/Tue Oct 3 12:01:28 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12781 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Hello, This patch adds support for interrupt-driven operation of the Broadcom Gigabit Ethernet PHYs. I have included device IDs for the parts used on Broadcom SiByte evaluation boards; more can be added as a need arises. They are apparently generally software-compatible with one another. Please consider. Maciej Signed-off-by: Maciej W. Rozycki patch-mips-2.6.18-20060920-broadcom-phy-15 diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/drivers/net/phy/Kconfig linux-mips-2.6.18-20060920/drivers/net/phy/Kconfig --- linux-mips-2.6.18-20060920.macro/drivers/net/phy/Kconfig 2006-09-20 20:50:26.000000000 +0000 +++ linux-mips-2.6.18-20060920/drivers/net/phy/Kconfig 2006-09-23 14:39:08.000000000 +0000 @@ -56,6 +56,12 @@ config SMSC_PHY ---help--- Currently supports the LAN83C185 PHY +config BROADCOM_PHY + tristate "Drivers for Broadcom PHYs" + depends on PHYLIB + ---help--- + Currently supports the BCM5411, BCM5421 and BCM5461 PHYs. + config FIXED_PHY tristate "Drivers for PHY emulation on fixed speed/link" depends on PHYLIB diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/drivers/net/phy/Makefile linux-mips-2.6.18-20060920/drivers/net/phy/Makefile --- linux-mips-2.6.18-20060920.macro/drivers/net/phy/Makefile 2006-09-20 20:50:26.000000000 +0000 +++ linux-mips-2.6.18-20060920/drivers/net/phy/Makefile 2006-09-22 22:55:37.000000000 +0000 @@ -10,4 +10,5 @@ obj-$(CONFIG_LXT_PHY) += lxt.o obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_SMSC_PHY) += smsc.o obj-$(CONFIG_VITESSE_PHY) += vitesse.o +obj-$(CONFIG_BROADCOM_PHY) += broadcom.o obj-$(CONFIG_FIXED_PHY) += fixed.o diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/drivers/net/phy/broadcom.c linux-mips-2.6.18-20060920/drivers/net/phy/broadcom.c --- linux-mips-2.6.18-20060920.macro/drivers/net/phy/broadcom.c 1970-01-01 00:00:00.000000000 +0000 +++ linux-mips-2.6.18-20060920/drivers/net/phy/broadcom.c 2006-09-28 01:47:11.000000000 +0000 @@ -0,0 +1,175 @@ +/* + * drivers/net/phy/broadcom.c + * + * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet + * transceivers. + * + * Copyright (c) 2006 Maciej W. Rozycki + * + * Inspired by code written by Amy Fong. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include + +#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */ +#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */ +#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */ + +#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */ +#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */ + +#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */ +#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */ +#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */ +#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */ +#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */ +#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */ +#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */ +#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */ +#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */ +#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */ +#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */ +#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */ +#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */ +#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */ +#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */ +#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */ +#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */ + +MODULE_DESCRIPTION("Broadcom PHY driver"); +MODULE_AUTHOR("Maciej W. Rozycki"); +MODULE_LICENSE("GPL"); + +static int bcm54xx_config_init(struct phy_device *phydev) +{ + int reg, err; + + reg = phy_read(phydev, MII_BCM54XX_ECR); + if (reg < 0) + return reg; + + /* Mask interrupts globally. */ + reg |= MII_BCM54XX_ECR_IM; + err = phy_write(phydev, MII_BCM54XX_ECR, reg); + if (err < 0) + return err; + + /* Unmask events we are interested in. */ + reg = ~(MII_BCM54XX_INT_DUPLEX | + MII_BCM54XX_INT_SPEED | + MII_BCM54XX_INT_LINK); + err = phy_write(phydev, MII_BCM54XX_IMR, reg); + if (err < 0) + return err; + return 0; +} + +static int bcm54xx_ack_interrupt(struct phy_device *phydev) +{ + int reg; + + /* Clear pending interrupts. */ + reg = phy_read(phydev, MII_BCM54XX_ISR); + if (reg < 0) + return reg; + + return 0; +} + +static int bcm54xx_config_intr(struct phy_device *phydev) +{ + int reg, err; + + reg = phy_read(phydev, MII_BCM54XX_ECR); + if (reg < 0) + return reg; + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) + reg &= ~MII_BCM54XX_ECR_IM; + else + reg |= MII_BCM54XX_ECR_IM; + + err = phy_write(phydev, MII_BCM54XX_ECR, reg); + return err; +} + +static struct phy_driver bcm5411_driver = { + .phy_id = 0x00206070, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM5411", + .features = PHY_GBIT_FEATURES, + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, + .config_init = bcm54xx_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = bcm54xx_ack_interrupt, + .config_intr = bcm54xx_config_intr, + .driver = { .owner = THIS_MODULE }, +}; + +static struct phy_driver bcm5421_driver = { + .phy_id = 0x002060e0, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM5421", + .features = PHY_GBIT_FEATURES, + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, + .config_init = bcm54xx_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = bcm54xx_ack_interrupt, + .config_intr = bcm54xx_config_intr, + .driver = { .owner = THIS_MODULE }, +}; + +static struct phy_driver bcm5461_driver = { + .phy_id = 0x002060c0, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM5461", + .features = PHY_GBIT_FEATURES, + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, + .config_init = bcm54xx_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = bcm54xx_ack_interrupt, + .config_intr = bcm54xx_config_intr, + .driver = { .owner = THIS_MODULE }, +}; + +static int __init broadcom_init(void) +{ + int ret; + + ret = phy_driver_register(&bcm5411_driver); + if (ret) + goto out_5411; + ret = phy_driver_register(&bcm5421_driver); + if (ret) + goto out_5421; + ret = phy_driver_register(&bcm5461_driver); + if (ret) + goto out_5461; + return ret; + +out_5461: + phy_driver_unregister(&bcm5421_driver); +out_5421: + phy_driver_unregister(&bcm5411_driver); +out_5411: + return ret; +} + +static void __exit broadcom_exit(void) +{ + phy_driver_unregister(&bcm5461_driver); + phy_driver_unregister(&bcm5421_driver); + phy_driver_unregister(&bcm5411_driver); +} + +module_init(broadcom_init); +module_exit(broadcom_exit); From macro@linux-mips.org Tue Oct 3 16:18:52 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 16:18:55 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:41221 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038880AbWJCPS3 (ORCPT ); Tue, 3 Oct 2006 16:18:29 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 87F6CF62EB; Tue, 3 Oct 2006 17:18:25 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XXWpFC5-Ohe3; Tue, 3 Oct 2006 17:18:25 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 2AF6FF62DA; Tue, 3 Oct 2006 17:18:25 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k93FIWv6005071; Tue, 3 Oct 2006 17:18:32 +0200 Date: Tue, 3 Oct 2006 16:18:28 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton , Jeff Garzik , Ralf Baechle , Andy Fleming cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: [patch 2/6] 2.6.18: sb1250-mac: Missing inclusions from Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1984/Tue Oct 3 12:01:28 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12782 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Hello, The uses some types and macros defined in , , and , but fails to include these headers. Please consider. Maciej Signed-off-by: Maciej W. Rozycki patch-mips-2.6.18-20060920-include-phy-16 diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/include/linux/phy.h linux-mips-2.6.18-20060920/include/linux/phy.h --- linux-mips-2.6.18-20060920.macro/include/linux/phy.h 2006-08-29 04:58:59.000000000 +0000 +++ linux-mips-2.6.18-20060920/include/linux/phy.h 2006-10-03 14:18:05.000000000 +0000 @@ -20,6 +20,10 @@ #include #include +#include +#include +#include +#include #define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ SUPPORTED_10baseT_Full | \ From macro@linux-mips.org Tue Oct 3 16:19:17 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 16:19:20 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:44037 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038886AbWJCPSg (ORCPT ); Tue, 3 Oct 2006 16:18:36 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 689F3F62EC; Tue, 3 Oct 2006 17:18:32 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id z1kukOOnVuFR; Tue, 3 Oct 2006 17:18:32 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 07F78F62DA; Tue, 3 Oct 2006 17:18:32 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k93FIdHH005100; Tue, 3 Oct 2006 17:18:39 +0200 Date: Tue, 3 Oct 2006 16:18:35 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton , Jeff Garzik , Ralf Baechle , Andy Fleming cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: [patch 3/6] 2.6.18: sb1250-mac: Phylib IRQ handling fixes Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1984/Tue Oct 3 12:01:28 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12783 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Hello, This patch fixes a couple of problems discovered with interrupt handling in the phylib core, namely: 1. The driver uses timer and workqueue calls, but does not include nor . 2. The driver uses schedule_work() for handling interrupts, but does not make sure any pending work scheduled thus has been completed before driver's structures get freed from memory. This is especially important as interrupts may keep arriving if the line is shared with another PHY. The solution is to ignore phy_interrupt() calls if the reported device has already been halted and calling flush_scheduled_work() from phy_stop_interrupts() (but guarded with current_is_keventd() in case the function has been called through keventd from the MAC device's close call to avoid a deadlock on the netlink lock). Please consider. Maciej Signed-off-by: Maciej W. Rozycki patch-mips-2.6.18-20060920-phy-irq-16 diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/drivers/net/phy/phy.c linux-mips-2.6.18-20060920/drivers/net/phy/phy.c --- linux-mips-2.6.18-20060920.macro/drivers/net/phy/phy.c 2006-08-05 04:58:46.000000000 +0000 +++ linux-mips-2.6.18-20060920/drivers/net/phy/phy.c 2006-10-03 14:19:21.000000000 +0000 @@ -7,6 +7,7 @@ * Author: Andy Fleming * * Copyright (c) 2004 Freescale Semiconductor, Inc. + * Copyright (c) 2006 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -32,6 +33,8 @@ #include #include #include +#include +#include #include #include @@ -484,6 +487,9 @@ static irqreturn_t phy_interrupt(int irq { struct phy_device *phydev = phy_dat; + if (PHY_HALTED == phydev->state) + return IRQ_NONE; /* It can't be ours. */ + /* The MDIO bus is not allowed to be written in interrupt * context, so we need to disable the irq here. A work * queue will write the PHY to disable and clear the @@ -577,6 +583,13 @@ int phy_stop_interrupts(struct phy_devic if (err) phy_error(phydev); + /* + * Finish any pending work; we might have been scheduled + * to be called from keventd ourselves, though. + */ + if (!current_is_keventd()) + flush_scheduled_work(); + free_irq(phydev->irq, phydev); return err; @@ -603,7 +616,8 @@ static void phy_change(void *data) enable_irq(phydev->irq); /* Reenable interrupts */ - err = phy_config_interrupt(phydev, PHY_INTERRUPT_ENABLED); + if (PHY_HALTED != phydev->state) + err = phy_config_interrupt(phydev, PHY_INTERRUPT_ENABLED); if (err) goto irq_enable_err; @@ -624,18 +638,24 @@ void phy_stop(struct phy_device *phydev) if (PHY_HALTED == phydev->state) goto out_unlock; - if (phydev->irq != PHY_POLL) { - /* Clear any pending interrupts */ - phy_clear_interrupt(phydev); + phydev->state = PHY_HALTED; + if (phydev->irq != PHY_POLL) { /* Disable PHY Interrupts */ phy_config_interrupt(phydev, PHY_INTERRUPT_DISABLED); - } - phydev->state = PHY_HALTED; + /* Clear any pending interrupts */ + phy_clear_interrupt(phydev); + } out_unlock: spin_unlock(&phydev->lock); + + /* + * Cannot call flush_scheduled_work() here as desired because + * of rtnl_lock(), but PHY_HALTED shall guarantee phy_change() + * will not reenable interrupts. + */ } From macro@linux-mips.org Tue Oct 3 16:19:44 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 16:19:49 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:51461 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038889AbWJCPSr (ORCPT ); Tue, 3 Oct 2006 16:18:47 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 83911F62DA; Tue, 3 Oct 2006 17:18:42 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2AqXVgSim7C5; Tue, 3 Oct 2006 17:18:41 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id CEE19F5BB4; Tue, 3 Oct 2006 17:18:41 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k93FIntC005136; Tue, 3 Oct 2006 17:18:49 +0200 Date: Tue, 3 Oct 2006 16:18:44 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton , Jeff Garzik , Ralf Baechle , Andy Fleming cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: [patch 4/6] 2.6.18: sb1250-mac: The actual driver update Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1984/Tue Oct 3 12:01:28 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12784 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Hello, This is the actual driver update. It includes the following changes: 1. Some help text for Kconfig. 2. Removal of unused module options. 3. Phylib support and the resulting removal of generic bits for handling the PHY. 4. Proper reserving of device resources and using ioremap()ped handles to access MAC registers rather than platform-specific macros. 5. Handling of the device using the driver model. Please consider. Maciej Signed-off-by: Maciej W. Rozycki patch-mips-2.6.18-20060920-sb1250-mac-15 diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/drivers/net/Kconfig linux-mips-2.6.18-20060920/drivers/net/Kconfig --- linux-mips-2.6.18-20060920.macro/drivers/net/Kconfig 2006-09-10 04:55:24.000000000 +0000 +++ linux-mips-2.6.18-20060920/drivers/net/Kconfig 2006-09-28 02:35:44.000000000 +0000 @@ -2030,6 +2030,15 @@ config R8169_NAPI config NET_SB1250_MAC tristate "SB1250 Ethernet support" depends on SIBYTE_SB1xxx_SOC + select PHYLIB + ---help--- + This driver supports gigabit Ethernet interfaces based on the + Broadcom SiByte family of System-On-a-Chip parts. They include + the BCM1120, BCM1125, BCM1125H, BCM1250, BCM1255, BCM1280, BCM1455 + and BCM1480 chips. + + To compile this driver as a module, choose M here: the module + will be called sb1250-mac. config R8169_VLAN bool "VLAN support" diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/drivers/net/sb1250-mac.c linux-mips-2.6.18-20060920/drivers/net/sb1250-mac.c --- linux-mips-2.6.18-20060920.macro/drivers/net/sb1250-mac.c 2006-09-20 20:50:26.000000000 +0000 +++ linux-mips-2.6.18-20060920/drivers/net/sb1250-mac.c 2006-09-28 02:51:29.000000000 +0000 @@ -1,5 +1,6 @@ /* * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation + * Copyright (c) 2006 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -18,7 +19,11 @@ * * This driver is designed for the Broadcom SiByte SOC built-in * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp. + * + * Updated to the driver model and the PHY abstraction layer + * by Maciej W. Rozycki. */ + #include #include #include @@ -32,9 +37,18 @@ #include #include #include -#include /* Processor type for cache alignment. */ -#include +#include +#include +#include +#include +#include +#include +#include + +#include #include +#include +#include /* Processor type for cache alignment. */ /* This is only here until the firmware is ready. In that case, the firmware leaves the ethernet address in the register for us. */ @@ -48,7 +62,7 @@ /* These identify the driver base version and may not be removed. */ #if 0 -static char version1[] __devinitdata = +static char version1[] __initdata = "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n"; #endif @@ -57,8 +71,6 @@ static char version1[] __devinitdata = #define CONFIG_SBMAC_COALESCE -#define MAX_UNITS 4 /* More are supported, limit only on options */ - /* Time in jiffies before concluding the transmitter is hung. */ #define TX_TIMEOUT (2*HZ) @@ -74,26 +86,6 @@ static int debug = 1; module_param(debug, int, S_IRUGO); MODULE_PARM_DESC(debug, "Debug messages"); -/* mii status msgs */ -static int noisy_mii = 1; -module_param(noisy_mii, int, S_IRUGO); -MODULE_PARM_DESC(noisy_mii, "MII status messages"); - -/* Used to pass the media type, etc. - Both 'options[]' and 'full_duplex[]' should exist for driver - interoperability. - The media type is usually passed in 'options[]'. -*/ -#ifdef MODULE -static int options[MAX_UNITS] = {-1, -1, -1, -1}; -module_param_array(options, int, NULL, S_IRUGO); -MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS)); - -static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1}; -module_param_array(full_duplex, int, NULL, S_IRUGO); -MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS)); -#endif - #ifdef CONFIG_SBMAC_COALESCE static int int_pktcnt = 0; module_param(int_pktcnt, int, S_IRUGO); @@ -104,6 +96,7 @@ module_param(int_timeout, int, S_IRUGO); MODULE_PARM_DESC(int_timeout, "Timeout value"); #endif +#include #include #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #include @@ -126,22 +119,43 @@ MODULE_PARM_DESC(int_timeout, "Timeout v #error invalid SiByte MAC configuation #endif +#ifdef K_INT_PHY +#define SBMAC_PHY_INT K_INT_PHY +#else +#define SBMAC_PHY_INT PHY_POLL +#endif + /********************************************************************** * Simple types ********************************************************************* */ - -typedef enum { sbmac_speed_auto, sbmac_speed_10, - sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; - -typedef enum { sbmac_duplex_auto, sbmac_duplex_half, - sbmac_duplex_full } sbmac_duplex_t; - -typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, - sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; - -typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, - sbmac_state_broken } sbmac_state_t; +typedef enum { + sbmac_speed_none = 0, + sbmac_speed_10 = SPEED_10, + sbmac_speed_100 = SPEED_100, + sbmac_speed_1000 = SPEED_1000, +} sbmac_speed_t; + +typedef enum { + sbmac_duplex_none = -1, + sbmac_duplex_half = DUPLEX_HALF, + sbmac_duplex_full = DUPLEX_FULL, +} sbmac_duplex_t; + +typedef enum { + sbmac_fc_none, + sbmac_fc_disabled, + sbmac_fc_frame, + sbmac_fc_collision, + sbmac_fc_carrier, +} sbmac_fc_t; + +typedef enum { + sbmac_state_uninit, + sbmac_state_off, + sbmac_state_on, + sbmac_state_broken, +} sbmac_state_t; /********************************************************************** @@ -225,46 +239,46 @@ struct sbmac_softc { * Linux-specific things */ - struct net_device *sbm_dev; /* pointer to linux device */ - spinlock_t sbm_lock; /* spin lock */ - struct timer_list sbm_timer; /* for monitoring MII */ - struct net_device_stats sbm_stats; - int sbm_devflags; /* current device flags */ - - int sbm_phy_oldbmsr; - int sbm_phy_oldanlpar; - int sbm_phy_oldk1stsr; - int sbm_phy_oldlinkstat; - int sbm_buffersize; + struct net_device *sbm_dev; /* pointer to linux device */ + struct phy_device *phy_dev; /* the associated PHY device */ + struct mii_bus mii_bus; /* the MII bus */ + int phy_irq[PHY_MAX_ADDR]; + struct work_struct sbm_queue; /* used for the PHY */ + spinlock_t sbm_lock; /* spin lock */ + struct net_device_stats sbm_stats; + int sbm_devflags; /* current device flags */ - unsigned char sbm_phys[2]; + int sbm_buffersize; /* * Controller-specific things */ - volatile void __iomem *sbm_base; /* MAC's base address */ - sbmac_state_t sbm_state; /* current state */ + volatile void __iomem *sbm_base; /* MAC's base address */ + sbmac_state_t sbm_state; /* current state */ volatile void __iomem *sbm_macenable; /* MAC Enable Register */ - volatile void __iomem *sbm_maccfg; /* MAC Configuration Register */ - volatile void __iomem *sbm_fifocfg; /* FIFO configuration register */ - volatile void __iomem *sbm_framecfg; /* Frame configuration register */ - volatile void __iomem *sbm_rxfilter; /* receive filter register */ - volatile void __iomem *sbm_isr; /* Interrupt status register */ - volatile void __iomem *sbm_imr; /* Interrupt mask register */ - volatile void __iomem *sbm_mdio; /* MDIO register */ - - sbmac_speed_t sbm_speed; /* current speed */ - sbmac_duplex_t sbm_duplex; /* current duplex */ - sbmac_fc_t sbm_fc; /* current flow control setting */ - - unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; - - sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ - sbmacdma_t sbm_rxdma; - int rx_hw_checksum; - int sbe_idx; + volatile void __iomem *sbm_maccfg; /* MAC Config Register */ + volatile void __iomem *sbm_fifocfg; /* FIFO Config Register */ + volatile void __iomem *sbm_framecfg; /* Frame Config Register */ + volatile void __iomem *sbm_rxfilter; /* Receive Filter Register */ + volatile void __iomem *sbm_isr; /* Interrupt Status Register */ + volatile void __iomem *sbm_imr; /* Interrupt Mask Register */ + volatile void __iomem *sbm_mdio; /* MDIO Register */ + + + sbmac_speed_t sbm_speed; /* current speed */ + sbmac_duplex_t sbm_duplex; /* current duplex */ + sbmac_fc_t sbm_fc; /* cur. flow control setting */ + int sbm_pause; /* current pause setting */ + int sbm_link; /* current link state */ + + unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; + + sbmacdma_t sbm_txdma; /* only channel 0 for now */ + sbmacdma_t sbm_rxdma; + int rx_hw_checksum; + int sbe_idx; }; @@ -297,32 +311,36 @@ static uint64_t sbmac_addr2reg(unsigned static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs); static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); static void sbmac_setmulti(struct sbmac_softc *sc); -static int sbmac_init(struct net_device *dev, int idx); +static int sbmac_init(struct platform_device *pldev, long long base); static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed); static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc); static int sbmac_open(struct net_device *dev); -static void sbmac_timer(unsigned long data); static void sbmac_tx_timeout (struct net_device *dev); static struct net_device_stats *sbmac_get_stats(struct net_device *dev); static void sbmac_set_rx_mode(struct net_device *dev); static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +static void sbmac_phy_disconnect(void *data); static int sbmac_close(struct net_device *dev); -static int sbmac_mii_poll(struct sbmac_softc *s,int noisy); +static void sbmac_mii_poll(struct net_device *dev); static int sbmac_mii_probe(struct net_device *dev); -static void sbmac_mii_sync(struct sbmac_softc *s); -static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt); -static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx); -static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx, - unsigned int regval); +static void sbmac_mii_sync(volatile void __iomem *sbm_mdio); +static void sbmac_mii_senddata(volatile void __iomem *sbm_mdio, + unsigned int data, int bitcnt); +static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx); +static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, + u16 val); /********************************************************************** * Globals ********************************************************************* */ -static uint64_t sbmac_orig_hwaddr[MAX_UNITS]; +static char sbmac_string[] = "sb1250-mac"; +static char sbmac_pretty[] = "SB1250 MAC"; + +static char sbmac_mdio_string[] = "sb1250-mac-mdio"; /********************************************************************** @@ -334,185 +352,66 @@ static uint64_t sbmac_orig_hwaddr[MAX_UN #define MII_COMMAND_WRITE 0x01 #define MII_COMMAND_ACK 0x02 -#define BMCR_RESET 0x8000 -#define BMCR_LOOPBACK 0x4000 -#define BMCR_SPEED0 0x2000 -#define BMCR_ANENABLE 0x1000 -#define BMCR_POWERDOWN 0x0800 -#define BMCR_ISOLATE 0x0400 -#define BMCR_RESTARTAN 0x0200 -#define BMCR_DUPLEX 0x0100 -#define BMCR_COLTEST 0x0080 -#define BMCR_SPEED1 0x0040 -#define BMCR_SPEED1000 BMCR_SPEED1 -#define BMCR_SPEED100 BMCR_SPEED0 -#define BMCR_SPEED10 0 - -#define BMSR_100BT4 0x8000 -#define BMSR_100BT_FDX 0x4000 -#define BMSR_100BT_HDX 0x2000 -#define BMSR_10BT_FDX 0x1000 -#define BMSR_10BT_HDX 0x0800 -#define BMSR_100BT2_FDX 0x0400 -#define BMSR_100BT2_HDX 0x0200 -#define BMSR_1000BT_XSR 0x0100 -#define BMSR_PRESUP 0x0040 -#define BMSR_ANCOMPLT 0x0020 -#define BMSR_REMFAULT 0x0010 -#define BMSR_AUTONEG 0x0008 -#define BMSR_LINKSTAT 0x0004 -#define BMSR_JABDETECT 0x0002 -#define BMSR_EXTCAPAB 0x0001 - -#define PHYIDR1 0x2000 -#define PHYIDR2 0x5C60 - -#define ANAR_NP 0x8000 -#define ANAR_RF 0x2000 -#define ANAR_ASYPAUSE 0x0800 -#define ANAR_PAUSE 0x0400 -#define ANAR_T4 0x0200 -#define ANAR_TXFD 0x0100 -#define ANAR_TXHD 0x0080 -#define ANAR_10FD 0x0040 -#define ANAR_10HD 0x0020 -#define ANAR_PSB 0x0001 - -#define ANLPAR_NP 0x8000 -#define ANLPAR_ACK 0x4000 -#define ANLPAR_RF 0x2000 -#define ANLPAR_ASYPAUSE 0x0800 -#define ANLPAR_PAUSE 0x0400 -#define ANLPAR_T4 0x0200 -#define ANLPAR_TXFD 0x0100 -#define ANLPAR_TXHD 0x0080 -#define ANLPAR_10FD 0x0040 -#define ANLPAR_10HD 0x0020 -#define ANLPAR_PSB 0x0001 /* 802.3 */ - -#define ANER_PDF 0x0010 -#define ANER_LPNPABLE 0x0008 -#define ANER_NPABLE 0x0004 -#define ANER_PAGERX 0x0002 -#define ANER_LPANABLE 0x0001 - -#define ANNPTR_NP 0x8000 -#define ANNPTR_MP 0x2000 -#define ANNPTR_ACK2 0x1000 -#define ANNPTR_TOGTX 0x0800 -#define ANNPTR_CODE 0x0008 - -#define ANNPRR_NP 0x8000 -#define ANNPRR_MP 0x2000 -#define ANNPRR_ACK3 0x1000 -#define ANNPRR_TOGTX 0x0800 -#define ANNPRR_CODE 0x0008 - -#define K1TCR_TESTMODE 0x0000 -#define K1TCR_MSMCE 0x1000 -#define K1TCR_MSCV 0x0800 -#define K1TCR_RPTR 0x0400 -#define K1TCR_1000BT_FDX 0x200 -#define K1TCR_1000BT_HDX 0x100 - -#define K1STSR_MSMCFLT 0x8000 -#define K1STSR_MSCFGRES 0x4000 -#define K1STSR_LRSTAT 0x2000 -#define K1STSR_RRSTAT 0x1000 -#define K1STSR_LP1KFD 0x0800 -#define K1STSR_LP1KHD 0x0400 -#define K1STSR_LPASMDIR 0x0200 - -#define K1SCR_1KX_FDX 0x8000 -#define K1SCR_1KX_HDX 0x4000 -#define K1SCR_1KT_FDX 0x2000 -#define K1SCR_1KT_HDX 0x1000 - -#define STRAP_PHY1 0x0800 -#define STRAP_NCMODE 0x0400 -#define STRAP_MANMSCFG 0x0200 -#define STRAP_ANENABLE 0x0100 -#define STRAP_MSVAL 0x0080 -#define STRAP_1KHDXADV 0x0010 -#define STRAP_1KFDXADV 0x0008 -#define STRAP_100ADV 0x0004 -#define STRAP_SPEEDSEL 0x0000 -#define STRAP_SPEED100 0x0001 - -#define PHYSUP_SPEED1000 0x10 -#define PHYSUP_SPEED100 0x08 -#define PHYSUP_SPEED10 0x00 -#define PHYSUP_LINKUP 0x04 -#define PHYSUP_FDX 0x02 - -#define MII_BMCR 0x00 /* Basic mode control register (rw) */ -#define MII_BMSR 0x01 /* Basic mode status register (ro) */ -#define MII_PHYIDR1 0x02 -#define MII_PHYIDR2 0x03 - -#define MII_K1STSR 0x0A /* 1K Status Register (ro) */ -#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ - - #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ #define ENABLE 1 #define DISABLE 0 /********************************************************************** - * SBMAC_MII_SYNC(s) + * SBMAC_MII_SYNC(sbm_mdio) * * Synchronize with the MII - send a pattern of bits to the MII * that will guarantee that it is ready to accept a command. * * Input parameters: - * s - sbmac structure + * sbm_mdio - address of the MAC's MDIO register * * Return value: * nothing ********************************************************************* */ -static void sbmac_mii_sync(struct sbmac_softc *s) +static void sbmac_mii_sync(volatile void __iomem *sbm_mdio) { int cnt; uint64_t bits; int mac_mdio_genc; - mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; + mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; - __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(bits | mac_mdio_genc, sbm_mdio); for (cnt = 0; cnt < 32; cnt++) { - __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); + __raw_writeq(bits | mac_mdio_genc, sbm_mdio); } } /********************************************************************** - * SBMAC_MII_SENDDATA(s,data,bitcnt) + * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt) * * Send some bits to the MII. The bits to be sent are right- * justified in the 'data' parameter. * * Input parameters: - * s - sbmac structure - * data - data to send - * bitcnt - number of bits to send + * sbm_mdio - address of the MAC's MDIO register + * data - data to send + * bitcnt - number of bits to send ********************************************************************* */ -static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt) +static void sbmac_mii_senddata(volatile void __iomem *sbm_mdio, + unsigned int data, int bitcnt) { int i; uint64_t bits; unsigned int curmask; int mac_mdio_genc; - mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; + mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; bits = M_MAC_MDIO_DIR_OUTPUT; - __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(bits | mac_mdio_genc, sbm_mdio); curmask = 1 << (bitcnt - 1); @@ -520,9 +419,9 @@ static void sbmac_mii_senddata(struct sb if (data & curmask) bits |= M_MAC_MDIO_OUT; else bits &= ~M_MAC_MDIO_OUT; - __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(bits | mac_mdio_genc, sbm_mdio); + __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); + __raw_writeq(bits | mac_mdio_genc, sbm_mdio); curmask >>= 1; } } @@ -530,21 +429,22 @@ static void sbmac_mii_senddata(struct sb /********************************************************************** - * SBMAC_MII_READ(s,phyaddr,regidx) - * + * SBMAC_MII_READ(bus, phyaddr, regidx) * Read a PHY register. * * Input parameters: - * s - sbmac structure + * bus - MDIO bus handle * phyaddr - PHY's address - * regidx = index of register to read + * regnum - index of register to read * * Return value: - * value read, or 0 if an error occurred. + * value read, or 0xffff if an error occurred. ********************************************************************* */ -static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx) +static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx) { + struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; + volatile void __iomem *sbm_mdio = sc->sbm_mdio; int idx; int error; int regval; @@ -554,8 +454,7 @@ static unsigned int sbmac_mii_read(struc * Synchronize ourselves so that the PHY knows the next * thing coming down is a command */ - - sbmac_mii_sync(s); + sbmac_mii_sync(sbm_mdio); /* * Send the data to the PHY. The sequence is @@ -564,37 +463,37 @@ static unsigned int sbmac_mii_read(struc * the PHY addr (5 bits) * the register index (5 bits) */ + sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); + sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2); + sbmac_mii_senddata(sbm_mdio, phyaddr, 5); + sbmac_mii_senddata(sbm_mdio, regidx, 5); - sbmac_mii_senddata(s,MII_COMMAND_START, 2); - sbmac_mii_senddata(s,MII_COMMAND_READ, 2); - sbmac_mii_senddata(s,phyaddr, 5); - sbmac_mii_senddata(s,regidx, 5); - - mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; + mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; /* * Switch the port around without a clock transition. */ - __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); /* * Send out a clock pulse to signal we want the status */ - - __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, + sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); /* * If an error occurred, the PHY will signal '1' back */ - error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN; + error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN; /* * Issue an 'idle' clock pulse, but keep the direction * the same. */ - __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, + sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); regval = 0; @@ -602,55 +501,60 @@ static unsigned int sbmac_mii_read(struc regval <<= 1; if (error == 0) { - if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN) + if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN) regval |= 1; } - __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, + sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); } /* Switch back to output */ - __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); if (error == 0) return regval; - return 0; + return 0xffff; } /********************************************************************** - * SBMAC_MII_WRITE(s,phyaddr,regidx,regval) + * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval) * * Write a value to a PHY register. * * Input parameters: - * s - sbmac structure + * bus - MDIO bus handle * phyaddr - PHY to use - * regidx - register within the PHY - * regval - data to write to register + * regidx - register within the PHY + * regval - data to write to register * * Return value: - * nothing + * 0 for success ********************************************************************* */ -static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx, - unsigned int regval) +static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, + u16 regval) { + struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; + volatile void __iomem *sbm_mdio = sc->sbm_mdio; int mac_mdio_genc; - sbmac_mii_sync(s); + sbmac_mii_sync(sbm_mdio); + + sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); + sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2); + sbmac_mii_senddata(sbm_mdio, phyaddr, 5); + sbmac_mii_senddata(sbm_mdio, regidx, 5); + sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2); + sbmac_mii_senddata(sbm_mdio, regval, 16); - sbmac_mii_senddata(s,MII_COMMAND_START,2); - sbmac_mii_senddata(s,MII_COMMAND_WRITE,2); - sbmac_mii_senddata(s,phyaddr, 5); - sbmac_mii_senddata(s,regidx, 5); - sbmac_mii_senddata(s,MII_COMMAND_ACK,2); - sbmac_mii_senddata(s,regval,16); + mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; - mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; + __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); - __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio); + return 0; } @@ -692,27 +596,27 @@ static void sbdma_initctx(sbmacdma_t *d, s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; #endif - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR))); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR); /* * initialize register pointers @@ -927,7 +831,7 @@ static int sbdma_add_rcvbuffer(sbmacdma_ if (sb == NULL) { sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN); if (sb_new == NULL) { - printk(KERN_INFO "%s: sk_buff allocation failed\n", + pr_info("%s: sk_buff allocation failed\n", d->sbdma_eth->sbm_dev->name); return -ENOBUFS; } @@ -1379,14 +1283,6 @@ static int sbmac_initctx(struct sbmac_so s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; s->sbm_mdio = s->sbm_base + R_MAC_MDIO; - s->sbm_phys[0] = 1; - s->sbm_phys[1] = 0; - - s->sbm_phy_oldbmsr = 0; - s->sbm_phy_oldanlpar = 0; - s->sbm_phy_oldk1stsr = 0; - s->sbm_phy_oldlinkstat = 0; - /* * Initialize the DMA channels. Right now, only one per MAC is used * Note: Only do this _once_, as it allocates memory from the kernel! @@ -1401,14 +1297,6 @@ static int sbmac_initctx(struct sbmac_so s->sbm_state = sbmac_state_off; - /* - * Initial speed is (XXX TEMP) 10MBit/s HDX no FC - */ - - s->sbm_speed = sbmac_speed_10; - s->sbm_duplex = sbmac_duplex_half; - s->sbm_fc = sbmac_fc_disabled; - return 0; } @@ -1921,8 +1809,6 @@ static int sbmac_set_speed(struct sbmac_ cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; break; - case sbmac_speed_auto: /* XXX not implemented */ - /* fall through */ default: return 0; } @@ -1995,8 +1881,6 @@ static int sbmac_set_duplex(struct sbmac cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; break; - case sbmac_fc_auto: /* XXX not implemented */ - /* fall through */ case sbmac_fc_frame: /* not valid in half duplex */ default: /* invalid selection */ return 0; @@ -2015,15 +1899,12 @@ static int sbmac_set_duplex(struct sbmac case sbmac_fc_collision: /* not valid in full duplex */ case sbmac_fc_carrier: /* not valid in full duplex */ - case sbmac_fc_auto: /* XXX not implemented */ - /* fall through */ default: return 0; } break; - case sbmac_duplex_auto: - /* XXX not implemented */ - break; + default: + return 0; } /* @@ -2322,7 +2203,7 @@ static int sb1250_change_mtu(struct net_ if (new_mtu > ENET_PACKET_SIZE) return -EINVAL; _dev->mtu = new_mtu; - printk(KERN_INFO "changing the mtu to %d\n", new_mtu); + pr_info("changing the mtu to %d\n", new_mtu); return 0; } @@ -2338,19 +2219,16 @@ static int sb1250_change_mtu(struct net_ * status ********************************************************************* */ -static int sbmac_init(struct net_device *dev, int idx) +static int sbmac_init(struct platform_device *pldev, long long base) { - struct sbmac_softc *sc; + struct net_device *dev = pldev->dev.driver_data; + int idx = pldev->id; + struct sbmac_softc *sc = netdev_priv(dev); unsigned char *eaddr; uint64_t ea_reg; int i; int err; - sc = netdev_priv(dev); - - /* Determine controller base address */ - - sc->sbm_base = IOADDR(dev->base_addr); sc->sbm_dev = dev; sc->sbe_idx = idx; @@ -2403,45 +2281,57 @@ static int sbmac_init(struct net_device dev->change_mtu = sb1250_change_mtu; + dev->irq = UNIT_INT(idx); + /* This is needed for PASS2 for Rx H/W checksum feature */ sbmac_set_iphdr_offset(sc); err = register_netdev(dev); - if (err) - goto out_uninit; - - if (sc->rx_hw_checksum == ENABLE) { - printk(KERN_INFO "%s: enabling TCP rcv checksum\n", - sc->sbm_dev->name); + if (err) { + printk(KERN_ERR "%s.%d: unable to register netdev\n", + sbmac_string, idx); + sbmac_uninitctx(sc); + return err; } + pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name); + + if (sc->rx_hw_checksum == ENABLE) + pr_info("%s: enabling TCP rcv checksum\n", dev->name); + /* * Display Ethernet address (this is called during the config * process so we need to finish off the config message that * was being displayed) */ - printk(KERN_INFO - "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n", - dev->name, dev->base_addr, - eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]); + pr_info("%s: SiByte Ethernet at 0x%08Lx, " + "address: %02X:%02X:%02X:%02X:%02X:%02X\n", + dev->name, base, + eaddr[0], eaddr[1], eaddr[2], eaddr[3], eaddr[4], eaddr[5]); + + sc->mii_bus.name = sbmac_mdio_string; + sc->mii_bus.id = idx; + sc->mii_bus.priv = sc; + sc->mii_bus.read = sbmac_mii_read; + sc->mii_bus.write = sbmac_mii_write; + sc->mii_bus.irq = sc->phy_irq; + for (i = 0; i < PHY_MAX_ADDR; ++i) + sc->mii_bus.irq[i] = SBMAC_PHY_INT; + sc->mii_bus.dev = &pldev->dev; + dev_set_drvdata(&pldev->dev, &sc->mii_bus); return 0; - -out_uninit: - sbmac_uninitctx(sc); - - return err; } static int sbmac_open(struct net_device *dev) { struct sbmac_softc *sc = netdev_priv(dev); + int err; - if (debug > 1) { - printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq); - } + if (debug > 1) + pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq); /* * map/route interrupt (clear status first, in case something @@ -2450,224 +2340,177 @@ static int sbmac_open(struct net_device */ __raw_readq(sc->sbm_isr); - if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev)) - return -EBUSY; + err = request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev); + if (err) { + printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name, + dev->irq); + goto out_err; + } /* - * Probe phy address + * Sanity check whether a possible previous call + * to sbmac_close() has fully concluded. */ - - if(sbmac_mii_probe(dev) == -1) { - printk("%s: failed to probe PHY.\n", dev->name); - return -EINVAL; + if (sc->phy_dev) { + printk(KERN_ERR "%s: PHY still in use\n", dev->name); + return -EBUSY; } /* - * Configure default speed + * Probe PHY address */ + err = mdiobus_register(&sc->mii_bus); + if (err) { + printk(KERN_ERR "%s: unable to register MDIO bus\n", + dev->name); + goto out_unirq; + } - sbmac_mii_poll(sc,noisy_mii); + sc->sbm_speed = sbmac_speed_none; + sc->sbm_duplex = sbmac_duplex_none; + sc->sbm_fc = sbmac_fc_none; + sc->sbm_pause = -1; + sc->sbm_link = 0; /* - * Turn on the channel + * Attach to the PHY */ - - sbmac_set_channel_state(sc,sbmac_state_on); + err = sbmac_mii_probe(dev); + if (err) + goto out_unregister; /* - * XXX Station address is in dev->dev_addr + * Turn on the channel */ - if (dev->if_port == 0) - dev->if_port = 0; + sbmac_set_channel_state(sc,sbmac_state_on); netif_start_queue(dev); sbmac_set_rx_mode(dev); - /* Set the timer to check for link beat. */ - init_timer(&sc->sbm_timer); - sc->sbm_timer.expires = jiffies + 2 * HZ/100; - sc->sbm_timer.data = (unsigned long)dev; - sc->sbm_timer.function = &sbmac_timer; - add_timer(&sc->sbm_timer); + phy_start(sc->phy_dev); return 0; + +out_unregister: + mdiobus_unregister(&sc->mii_bus); + +out_unirq: + free_irq(dev->irq, dev); + +out_err: + return err; } static int sbmac_mii_probe(struct net_device *dev) { + struct sbmac_softc *sc = netdev_priv(dev); + struct phy_device *phy_dev; int i; - struct sbmac_softc *s = netdev_priv(dev); - u16 bmsr, id1, id2; - u32 vendor, device; - - for (i=1; i<31; i++) { - bmsr = sbmac_mii_read(s, i, MII_BMSR); - if (bmsr != 0) { - s->sbm_phys[0] = i; - id1 = sbmac_mii_read(s, i, MII_PHYIDR1); - id2 = sbmac_mii_read(s, i, MII_PHYIDR2); - vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f); - device = (id2 >> 4) & 0x3f; - - printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n", - dev->name, i, vendor, device); - return i; - } - } - return -1; -} + INIT_WORK(&sc->sbm_queue, sbmac_phy_disconnect, sc); -static int sbmac_mii_poll(struct sbmac_softc *s,int noisy) -{ - int bmsr,bmcr,k1stsr,anlpar; - int chg; - char buffer[100]; - char *p = buffer; - - /* Read the mode status and mode control registers. */ - bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR); - bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR); - - /* get the link partner status */ - anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR); - - /* if supported, read the 1000baseT register */ - if (bmsr & BMSR_1000BT_XSR) { - k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR); - } - else { - k1stsr = 0; + for (i = 0; i < PHY_MAX_ADDR; i++) { + phy_dev = sc->mii_bus.phy_map[i]; + if (phy_dev) + break; } + if (!phy_dev) { + printk(KERN_ERR "%s: no PHY found\n", dev->name); + return -ENXIO; + } + + phy_dev = phy_connect(dev, phy_dev->dev.bus_id, &sbmac_mii_poll, 0); + if (IS_ERR(phy_dev)) { + printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); + return PTR_ERR(phy_dev); + } + + /* Remove any features not supported by the controller */ + phy_dev->supported &= SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full | + SUPPORTED_Autoneg | + SUPPORTED_MII | + SUPPORTED_Pause | + SUPPORTED_Asym_Pause; + phy_dev->advertising = phy_dev->supported; + + pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", + dev->name, phy_dev->drv->name, + phy_dev->dev.bus_id, phy_dev->irq); - chg = 0; + sc->phy_dev = phy_dev; - if ((bmsr & BMSR_LINKSTAT) == 0) { - /* - * If link status is down, clear out old info so that when - * it comes back up it will force us to reconfigure speed - */ - s->sbm_phy_oldbmsr = 0; - s->sbm_phy_oldanlpar = 0; - s->sbm_phy_oldk1stsr = 0; return 0; - } - - if ((s->sbm_phy_oldbmsr != bmsr) || - (s->sbm_phy_oldanlpar != anlpar) || - (s->sbm_phy_oldk1stsr != k1stsr)) { - if (debug > 1) { - printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n", - s->sbm_dev->name, - s->sbm_phy_oldbmsr,bmsr, - s->sbm_phy_oldanlpar,anlpar, - s->sbm_phy_oldk1stsr,k1stsr); - } - s->sbm_phy_oldbmsr = bmsr; - s->sbm_phy_oldanlpar = anlpar; - s->sbm_phy_oldk1stsr = k1stsr; - chg = 1; - } - - if (chg == 0) - return 0; - - p += sprintf(p,"Link speed: "); - - if (k1stsr & K1STSR_LP1KFD) { - s->sbm_speed = sbmac_speed_1000; - s->sbm_duplex = sbmac_duplex_full; - s->sbm_fc = sbmac_fc_frame; - p += sprintf(p,"1000BaseT FDX"); - } - else if (k1stsr & K1STSR_LP1KHD) { - s->sbm_speed = sbmac_speed_1000; - s->sbm_duplex = sbmac_duplex_half; - s->sbm_fc = sbmac_fc_disabled; - p += sprintf(p,"1000BaseT HDX"); - } - else if (anlpar & ANLPAR_TXFD) { - s->sbm_speed = sbmac_speed_100; - s->sbm_duplex = sbmac_duplex_full; - s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled; - p += sprintf(p,"100BaseT FDX"); - } - else if (anlpar & ANLPAR_TXHD) { - s->sbm_speed = sbmac_speed_100; - s->sbm_duplex = sbmac_duplex_half; - s->sbm_fc = sbmac_fc_disabled; - p += sprintf(p,"100BaseT HDX"); - } - else if (anlpar & ANLPAR_10FD) { - s->sbm_speed = sbmac_speed_10; - s->sbm_duplex = sbmac_duplex_full; - s->sbm_fc = sbmac_fc_frame; - p += sprintf(p,"10BaseT FDX"); - } - else if (anlpar & ANLPAR_10HD) { - s->sbm_speed = sbmac_speed_10; - s->sbm_duplex = sbmac_duplex_half; - s->sbm_fc = sbmac_fc_collision; - p += sprintf(p,"10BaseT HDX"); - } - else { - p += sprintf(p,"Unknown"); - } - - if (noisy) { - printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer); - } - - return 1; } -static void sbmac_timer(unsigned long data) +static void sbmac_mii_poll(struct net_device *dev) { - struct net_device *dev = (struct net_device *)data; struct sbmac_softc *sc = netdev_priv(dev); - int next_tick = HZ; - int mii_status; - - spin_lock_irq (&sc->sbm_lock); - - /* make IFF_RUNNING follow the MII status bit "Link established" */ - mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR); + struct phy_device *phy_dev = sc->phy_dev; + unsigned long flags; + sbmac_fc_t fc; + int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg; - if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) { - sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT; - if (mii_status & BMSR_LINKSTAT) { - netif_carrier_on(dev); - } - else { - netif_carrier_off(dev); + link_chg = (sc->sbm_link != phy_dev->link); + speed_chg = (sc->sbm_speed != phy_dev->speed); + duplex_chg = (sc->sbm_duplex != phy_dev->duplex); + pause_chg = (sc->sbm_pause != phy_dev->pause); + + if (!link_chg && !speed_chg && !duplex_chg && !pause_chg) + return; /* Hmmm... */ + + if (!phy_dev->link) { + if (link_chg) { + sc->sbm_link = phy_dev->link; + sc->sbm_speed = sbmac_speed_none; + sc->sbm_duplex = sbmac_duplex_none; + sc->sbm_fc = sbmac_fc_disabled; + sc->sbm_pause = -1; + pr_info("%s: link unavailable\n", dev->name); } + return; } - /* - * Poll the PHY to see what speed we should be running at - */ + if (phy_dev->duplex == DUPLEX_FULL) { + if (phy_dev->pause) + fc = sbmac_fc_frame; + else + fc = sbmac_fc_disabled; + } else + fc = sbmac_fc_collision; + fc_chg = (sc->sbm_fc != fc); - if (sbmac_mii_poll(sc,noisy_mii)) { - if (sc->sbm_state != sbmac_state_off) { - /* - * something changed, restart the channel - */ - if (debug > 1) { - printk("%s: restarting channel because speed changed\n", - sc->sbm_dev->name); - } - sbmac_channel_stop(sc); - sbmac_channel_start(sc); - } - } + pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed, + phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H'); - spin_unlock_irq (&sc->sbm_lock); + spin_lock_irqsave(&sc->sbm_lock, flags); + + sc->sbm_speed = phy_dev->speed; + sc->sbm_duplex = phy_dev->duplex; + sc->sbm_fc = fc; + sc->sbm_pause = phy_dev->pause; + sc->sbm_link = phy_dev->link; - sc->sbm_timer.expires = jiffies + next_tick; - add_timer(&sc->sbm_timer); + if ((speed_chg || duplex_chg || fc_chg) && + sc->sbm_state != sbmac_state_off) { + /* + * something changed, restart the channel + */ + if (debug > 1) + pr_debug("%s: restarting channel " + "because PHY state changed\n", dev->name); + sbmac_channel_stop(sc); + sbmac_channel_start(sc); + } + + spin_unlock_irqrestore(&sc->sbm_lock, flags); } @@ -2745,62 +2588,39 @@ static void sbmac_set_rx_mode(struct net static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { struct sbmac_softc *sc = netdev_priv(dev); - u16 *data = (u16 *)&rq->ifr_ifru; - unsigned long flags; - int retval; - spin_lock_irqsave(&sc->sbm_lock, flags); - retval = 0; + if (!netif_running(dev) || !sc->phy_dev) + return -EINVAL; - switch(cmd) { - case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */ - data[0] = sc->sbm_phys[0] & 0x1f; - /* Fall Through */ - case SIOCDEVPRIVATE+1: /* Read the specified MII register. */ - data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f); - break; - case SIOCDEVPRIVATE+2: /* Write the specified MII register */ - if (!capable(CAP_NET_ADMIN)) { - retval = -EPERM; - break; - } - if (debug > 1) { - printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name, - data[0],data[1],data[2]); - } - sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]); - break; - default: - retval = -EOPNOTSUPP; - } + return phy_mii_ioctl(sc->phy_dev, if_mii(rq), cmd); +} - spin_unlock_irqrestore(&sc->sbm_lock, flags); - return retval; +static void sbmac_phy_disconnect(void *data) +{ + struct sbmac_softc *sc = data; + + phy_disconnect(sc->phy_dev); + mdiobus_unregister(&sc->mii_bus); + sc->phy_dev = NULL; } static int sbmac_close(struct net_device *dev) { struct sbmac_softc *sc = netdev_priv(dev); - unsigned long flags; - int irq; - sbmac_set_channel_state(sc,sbmac_state_off); + phy_stop(sc->phy_dev); - del_timer_sync(&sc->sbm_timer); - - spin_lock_irqsave(&sc->sbm_lock, flags); + sbmac_set_channel_state(sc, sbmac_state_off); netif_stop_queue(dev); - if (debug > 1) { - printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name); - } + if (debug > 1) + pr_debug("%s: Shutting down ethercard\n",dev->name); - spin_unlock_irqrestore(&sc->sbm_lock, flags); + /* Cannot call phy_disconnect() here because of rtnl_lock(). */ + schedule_work(&sc->sbm_queue); - irq = dev->irq; - synchronize_irq(irq); - free_irq(irq, dev); + free_irq(dev->irq, dev); sbdma_emptyring(&(sc->sbm_txdma)); sbdma_emptyring(&(sc->sbm_rxdma)); @@ -2809,55 +2629,195 @@ static int sbmac_close(struct net_device } +static int __init sbmac_probe(struct platform_device *pldev) +{ + struct net_device *dev; + struct sbmac_softc *sc; + volatile void __iomem *sbm_base; + struct resource *res; + u64 sbmac_orig_hwaddr; + int err; + + res = platform_get_resource(pldev, IORESOURCE_MEM, 0); + BUG_ON(!res); + sbm_base = ioremap_nocache(res->start, res->end - res->start + 1); + if (!sbm_base) { + printk(KERN_ERR "%s: unable to map device registers\n", + pldev->dev.bus_id); + err = -ENOMEM; + goto out_out; + } + + /* + * The R_MAC_ETHERNET_ADDR register will be set to some nonzero + * value for us by the firmware if we're going to use this MAC. + * If we find a zero, skip this MAC. + */ + sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR); + pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", pldev->dev.bus_id, + sbmac_orig_hwaddr ? "" : "not ", (long long)res->start); + if (sbmac_orig_hwaddr == 0) { + err = 0; + goto out_unmap; + } + + /* + * Okay, cool. Initialize this MAC. + */ + dev = alloc_etherdev(sizeof(struct sbmac_softc)); + if (!dev) { + printk(KERN_ERR "%s: unable to allocate etherdev\n", + pldev->dev.bus_id); + err = -ENOMEM; + goto out_unmap; + } + + pldev->dev.driver_data = dev; + SET_NETDEV_DEV(dev, &pldev->dev); + + sc = netdev_priv(dev); + sc->sbm_base = sbm_base; + + err = sbmac_init(pldev, res->start); + if (err) + goto out_kfree; + + return 0; + +out_kfree: + free_netdev(dev); + __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR); + +out_unmap: + iounmap(sbm_base); + +out_out: + return err; +} + +static int __exit sbmac_remove(struct platform_device *pldev) +{ + struct net_device *dev = pldev->dev.driver_data; + struct sbmac_softc *sc = netdev_priv(dev); + + unregister_netdev(dev); + flush_scheduled_work(); /* Finish any pending work. */ + sbmac_uninitctx(sc); + iounmap(sc->sbm_base); + free_netdev(dev); + + return 0; +} + + +static struct platform_device **sbmac_pldev; +static int sbmac_max_units __initdata; #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR) -static void -sbmac_setup_hwaddr(int chan,char *addr) +static void sbmac_setup_hwaddr(int idx, char *addr) { + volatile void __iomem *sbm_base; + unsigned long start, end; uint8_t eaddr[6]; uint64_t val; - unsigned long port; - port = A_MAC_CHANNEL_BASE(chan); - sbmac_parse_hwaddr(addr,eaddr); + if (idx >= sbmac_max_units) + return; + + start = A_MAC_CHANNEL_BASE(idx); + end = A_MAC_CHANNEL_BASE(idx + 1) - 1; + + sbm_base = ioremap_nocache(start, end - start + 1); + if (!sbm_base) { + printk(KERN_ERR "%s: unable to map device registers\n", + sbmac_string); + return + } + + sbmac_parse_hwaddr(addr, eaddr); val = sbmac_addr2reg(eaddr); - __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR)); - val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR)); + __raw_writeq(val, sbm_base + R_MAC_ETHERNET_ADDR); + val = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR); + + iounmap(sbm_base); } #endif -static struct net_device *dev_sbmac[MAX_UNITS]; +static int __init sbmac_platform_probe_one(int idx) +{ + struct platform_device *pldev; + struct { + struct resource r; + char name[strlen(sbmac_pretty) + 4]; + } *res; + int err; + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) { + printk(KERN_ERR "%s.%d: unable to allocate memory\n", + sbmac_string, idx); + err = -ENOMEM; + goto out_err; + } + + /* + * This is the base address of the MAC. + */ + snprintf(res->name, sizeof(res->name), "%s %d", sbmac_pretty, idx); + res->r.name = res->name; + res->r.flags = IORESOURCE_MEM; + res->r.start = A_MAC_CHANNEL_BASE(idx); + res->r.end = A_MAC_CHANNEL_BASE(idx + 1) - 1; + + pldev = platform_device_register_simple(sbmac_string, idx, &res->r, 1); + if (IS_ERR(pldev)) { + printk(KERN_ERR "%s.%d: unable to register platform device\n", + sbmac_string, idx); + err = PTR_ERR(pldev); + goto out_kfree; + } + + if (!pldev->dev.driver) { + err = 0; /* No hardware at this address. */ + goto out_unregister; + } + + sbmac_pldev[idx] = pldev; + return 0; + +out_unregister: + platform_device_unregister(pldev); + +out_kfree: + kfree(res); + +out_err: + return err; +} -static int __init -sbmac_init_module(void) +static void __init sbmac_platform_probe(void) { - int idx; - struct net_device *dev; - unsigned long port; - int chip_max_units; + int i; /* Set the number of available units based on the SOC type. */ switch (soc_type) { case K_SYS_SOC_TYPE_BCM1250: case K_SYS_SOC_TYPE_BCM1250_ALT: - chip_max_units = 3; + sbmac_max_units = 3; break; case K_SYS_SOC_TYPE_BCM1120: case K_SYS_SOC_TYPE_BCM1125: case K_SYS_SOC_TYPE_BCM1125H: - case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ - chip_max_units = 2; + case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ + sbmac_max_units = 2; break; case K_SYS_SOC_TYPE_BCM1x55: case K_SYS_SOC_TYPE_BCM1x80: - chip_max_units = 4; + sbmac_max_units = 4; break; default: - chip_max_units = 0; - break; + return; /* none */ } - if (chip_max_units > MAX_UNITS) - chip_max_units = MAX_UNITS; /* * For bringup when not using the firmware, we can pre-fill @@ -2865,89 +2825,70 @@ sbmac_init_module(void) * specified in this file (or maybe from the config file?) */ #ifdef SBMAC_ETH0_HWADDR - if (chip_max_units > 0) - sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR); + sbmac_setup_hwaddr(0, SBMAC_ETH0_HWADDR); #endif #ifdef SBMAC_ETH1_HWADDR - if (chip_max_units > 1) - sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR); + sbmac_setup_hwaddr(1, SBMAC_ETH1_HWADDR); #endif #ifdef SBMAC_ETH2_HWADDR - if (chip_max_units > 2) - sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR); + sbmac_setup_hwaddr(2, SBMAC_ETH2_HWADDR); #endif #ifdef SBMAC_ETH3_HWADDR - if (chip_max_units > 3) - sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR); + sbmac_setup_hwaddr(3, SBMAC_ETH3_HWADDR); #endif + sbmac_pldev = kzalloc(sbmac_max_units * sizeof(*sbmac_pldev), + GFP_KERNEL); + if (!sbmac_pldev) { + printk(KERN_ERR "%s: unable to allocate memory\n", + sbmac_string); + return; + } + /* * Walk through the Ethernet controllers and find * those who have their MAC addresses set. */ - for (idx = 0; idx < chip_max_units; idx++) { + for (i = 0; i < sbmac_max_units; i++) + if (sbmac_platform_probe_one(i)) + break; +} - /* - * This is the base address of the MAC. - */ - port = A_MAC_CHANNEL_BASE(idx); +static void __exit sbmac_platform_cleanup(void) +{ + int i; - /* - * The R_MAC_ETHERNET_ADDR register will be set to some nonzero - * value for us by the firmware if we're going to use this MAC. - * If we find a zero, skip this MAC. - */ + for (i = 0; i < sbmac_max_units; i++) + platform_device_unregister(sbmac_pldev[i]); +} - sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR)); - if (sbmac_orig_hwaddr[idx] == 0) { - printk(KERN_DEBUG "sbmac: not configuring MAC at " - "%lx\n", port); - continue; - } - /* - * Okay, cool. Initialize this MAC. - */ +static struct platform_driver sbmac_driver = { + .probe = sbmac_probe, + .remove = __exit_p(sbmac_remove), + .driver = { + .name = sbmac_string, + }, +}; - dev = alloc_etherdev(sizeof(struct sbmac_softc)); - if (!dev) - return -ENOMEM; /* return ENOMEM */ - - printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port); - - dev->irq = UNIT_INT(idx); - dev->base_addr = port; - dev->mem_end = 0; - if (sbmac_init(dev, idx)) { - port = A_MAC_CHANNEL_BASE(idx); - __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR)); - free_netdev(dev); - continue; - } - dev_sbmac[idx] = dev; - } - return 0; -} +static int __init sbmac_init_module(void) +{ + int err; + err = platform_driver_register(&sbmac_driver); + if (err) + return err; -static void __exit -sbmac_cleanup_module(void) -{ - struct net_device *dev; - int idx; + sbmac_platform_probe(); - for (idx = 0; idx < MAX_UNITS; idx++) { - struct sbmac_softc *sc; - dev = dev_sbmac[idx]; - if (!dev) - continue; + return err; +} - sc = netdev_priv(dev); - unregister_netdev(dev); - sbmac_uninitctx(sc); - free_netdev(dev); - } +static void __exit sbmac_cleanup_module(void) +{ + sbmac_platform_cleanup(); + platform_driver_unregister(&sbmac_driver); } module_init(sbmac_init_module); From macro@linux-mips.org Tue Oct 3 16:20:11 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 16:20:16 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:57093 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038893AbWJCPTA (ORCPT ); Tue, 3 Oct 2006 16:19:00 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id D84B6F62F5; Tue, 3 Oct 2006 17:18:53 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id psjVJwuej2BF; Tue, 3 Oct 2006 17:18:52 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id B455DF62F0; Tue, 3 Oct 2006 17:18:52 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k93FJ0CF005160; Tue, 3 Oct 2006 17:19:00 +0200 Date: Tue, 3 Oct 2006 16:18:55 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton , Jeff Garzik , Ralf Baechle , Andy Fleming cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: [patch 5/6] 2.6.18: sb1250-mac: Interrupt wiring for PHYs Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1984/Tue Oct 3 12:01:28 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12785 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Hello, This patch defines the wiring for the PHY interrupt lines for the supported Broadcom SiByte boards for which documentation is available. Please consider. Maciej Signed-off-by: Maciej W. Rozycki patch-mips-2.6.18-20060920-sibyte-phy-irq-15 diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/include/asm-mips/sibyte/sentosa.h linux-mips-2.6.18-20060920/include/asm-mips/sibyte/sentosa.h --- linux-mips-2.6.18-20060920.macro/include/asm-mips/sibyte/sentosa.h 2006-09-20 20:51:12.000000000 +0000 +++ linux-mips-2.6.18-20060920/include/asm-mips/sibyte/sentosa.h 2006-09-25 21:08:37.000000000 +0000 @@ -37,4 +37,8 @@ /* GPIOs */ #define K_GPIO_DBG_LED 0 +#ifdef CONFIG_SIBYTE_SENTOSA +#define K_INT_PHY K_INT_PCI_INTD +#endif + #endif /* __ASM_SIBYTE_SENTOSA_H */ diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/include/asm-mips/sibyte/swarm.h linux-mips-2.6.18-20060920/include/asm-mips/sibyte/swarm.h --- linux-mips-2.6.18-20060920.macro/include/asm-mips/sibyte/swarm.h 2006-09-20 20:51:12.000000000 +0000 +++ linux-mips-2.6.18-20060920/include/asm-mips/sibyte/swarm.h 2006-09-25 21:56:49.000000000 +0000 @@ -67,4 +67,9 @@ #define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) #endif +#ifdef CONFIG_SIBYTE_SWARM +#define K_GPIO_PHY 2 +#define K_INT_PHY (K_INT_GPIO_0 + K_GPIO_PHY) +#endif + #endif /* __ASM_SIBYTE_SWARM_H */ From macro@linux-mips.org Tue Oct 3 16:20:38 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 16:20:44 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:774 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038891AbWJCPTQ (ORCPT ); Tue, 3 Oct 2006 16:19:16 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 120DBF62EE; Tue, 3 Oct 2006 17:19:10 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TPRCghgBWeWx; Tue, 3 Oct 2006 17:19:09 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id B9374F62E0; Tue, 3 Oct 2006 17:19:09 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k93FJHRo005257; Tue, 3 Oct 2006 17:19:17 +0200 Date: Tue, 3 Oct 2006 16:19:12 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton , Jeff Garzik , Ralf Baechle , Andy Fleming cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: [patch 6/6] 2.6.18: sb1250-mac: PHY interrupt polarity fixup Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1984/Tue Oct 3 12:01:28 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12786 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Hello, This change makes the PHY interrupt actually work as intended on the SWARM board, where the CFE firmware leaves the GPIO line at the power-on polarity, which is suitable for active-high interrupts, but not quite so for this one (the "interrupt force" bit in the PHY works much better for stress-testing interrupt handling; use that one instead if needed). Please consider. Maciej Signed-off-by: Maciej W. Rozycki patch-mips-2.6.18-20060920-swarm-setup-15 diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/arch/mips/sibyte/swarm/setup.c linux-mips-2.6.18-20060920/arch/mips/sibyte/swarm/setup.c --- linux-mips-2.6.18-20060920.macro/arch/mips/sibyte/swarm/setup.c 2006-07-12 04:59:56.000000000 +0000 +++ linux-mips-2.6.18-20060920/arch/mips/sibyte/swarm/setup.c 2006-09-28 02:37:31.000000000 +0000 @@ -1,6 +1,7 @@ /* * Copyright (C) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * Copyright (c) 2006 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -106,6 +107,8 @@ int swarm_be_handler(struct pt_regs *reg void __init plat_mem_setup(void) { + u64 invert; + #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) bcm1480_setup(); #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) @@ -114,6 +117,16 @@ void __init plat_mem_setup(void) #error invalid SiByte board configuation #endif + /* + * The PHY interrupt on the SWARM is active low, + * but CFE gets it wrong (or not at all, probably). + */ +#ifdef K_GPIO_PHY + invert = __raw_readq(IOADDR(A_GPIO_INPUT_INVERT)); + invert |= 1 << K_GPIO_PHY; + __raw_writeq(invert, IOADDR(A_GPIO_INPUT_INVERT)); +#endif + panic_timeout = 5; /* For debug. */ board_time_init = swarm_time_init; From vagabon.xyz@gmail.com Tue Oct 3 16:33:57 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 16:33:59 +0100 (BST) Received: from ug-out-1314.google.com ([66.249.92.174]:19268 "EHLO ug-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20038895AbWJCPd5 (ORCPT ); Tue, 3 Oct 2006 16:33:57 +0100 Received: by ug-out-1314.google.com with SMTP id z27so580450ugc for ; Tue, 03 Oct 2006 08:33:57 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:reply-to:user-agent:mime-version:to:cc:subject:references:in-reply-to:content-type:content-transfer-encoding:from; b=rfhAfUelVzOqtwamRjFBYfYpQQS2ugSDX7U1rRmHp5wTBOGl8fy8wyapEBYPBd8rcTeazv/nqC31eUUR5mprfJImolcSRHvpFysxSrfSrV9vWPlBDW2IjhL0INcRdIQUnj8MdWobP2NxbJEDRMOQwy1HFvJ7zXjABGUhQrV0aqk= Received: by 10.49.43.2 with SMTP id v2mr963135nfj; Tue, 03 Oct 2006 08:33:57 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.gmail.com with ESMTP id r34sm1298847nfc.2006.10.03.08.33.56; Tue, 03 Oct 2006 08:33:56 -0700 (PDT) Message-ID: <45228320.2070809@innova-card.com> Date: Tue, 03 Oct 2006 17:34:56 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: Franck Bui-Huu , linux-mips@linux-mips.org Subject: Re: [RFC] setup.c: get ride of CPHYSADDR() References: <45227762.8090207@innova-card.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12787 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips Maciej W. Rozycki wrote: > Franck, >> >> The reason why I'm trying to kick out this macro is that we should >> rely on __pa() for address convertions instead of having several >> helpers that do the same thing but differently. Futermore if some >> tricks are needed for these conversions, they should be done in >> one place. > > Have you verified it works correctly for 64-bit kernels linked at a KSEG0 > address? > Of course not ;). More seriously, I'm working on a 32 bits kernel. I'm not familiar with MIPS 64 bits world and all tricks needed to compile them, and that's the reason why I make this thread an RFC one. I was suspecting something related to 64 bits kernels. Do you mean that this macro exists because of a linker issue ? Futhermore I noticed that some part of the code in setup.c do no rely on this macro for address convertions. See for example in resource_init(): code_resource.start = virt_to_phys(&_text); code_resource.end = virt_to_phys(&_etext) - 1; data_resource.start = virt_to_phys(&_etext); data_resource.end = virt_to_phys(&_edata) - 1; Why in that case we compute address converstion differently ? Thanks Franck From kaz@zeugmasystems.com Tue Oct 3 18:45:17 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 18:45:19 +0100 (BST) Received: from mail.zeugmasystems.com ([192.139.122.66]:27024 "EHLO zeugmasystems.com") by ftp.linux-mips.org with ESMTP id S20038857AbWJCRpR convert rfc822-to-8bit (ORCPT ); Tue, 3 Oct 2006 18:45:17 +0100 Content-class: urn:content-classes:message Subject: RE: Roll-your-own Toolchain Builds MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Date: Tue, 3 Oct 2006 10:45:12 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Message-ID: <66910A579C9312469A7DF9ADB54A8B7D3E6D9E@exchange.ZeugmaSystems.local> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Roll-your-own Toolchain Builds thread-index: AcbmxqvYZrrljagrS1iCAgNkhmYUXgASKKZQ From: "Kaz Kylheku" To: "Yoichi Yuasa" , "Pak Woon" Cc: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12788 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kaz@zeugmasystems.com Precedence: bulk X-list: linux-mips > Yoichi Yuasa wrote: > Pak Woon wrote: > > > Hi all, > > > > I am trying to roll-my-own toolchain by following the instructions > > outlined in http://www.linux-mips.org/wiki/Toolchains. I have > > encountered the "cannot create executables" / "crt01.o: No > such file" > > problem. There are a lot of people who see the same thing, > but there > > does not seem to be a definative answer. > > When did you get the message? > building toolchain or ... > > > FYI, my packages are:- > > binutils-2.16.91.0.6-5 > > gcc-4.1.1-1.fc5 > > lib-gcc-4.1.1-1.fc5 > > gcc-gfortran-4.1.1-1.fc5 > > gcc-g++-4.1.1-1.fc5 > > Did you install glibc-devel package? The "compiler cannot create executables" is spit out by the Autoconf-generated configure script when it tries to compile a feature-test program using a some compiler that has no library. That could mean that the development packages are not installed on the host machine for compiling programs against glibc. But it could also possibly mean that the wrong compiler is being run, i.e. a bootstrapping compiler with no library. Use a clean path when building stuff. Before you do anything else: PATH=/bin:/usr/bin Otherwise who knows what will get picked up for execution when all those mountains of scriptology are executing. From manoje@broadcom.com Tue Oct 3 20:15:24 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 20:15:25 +0100 (BST) Received: from mms2.broadcom.com ([216.31.210.18]:30992 "EHLO mms2.broadcom.com") by ftp.linux-mips.org with ESMTP id S20038886AbWJCTPY convert rfc822-to-8bit (ORCPT ); Tue, 3 Oct 2006 20:15:24 +0100 Received: from 10.10.64.154 by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.2.2)); Tue, 03 Oct 2006 12:15:11 -0700 X-Server-Uuid: 79DB55DB-3CB4-423E-BEDB-D0F268247E63 Received: by mail-irva-10.broadcom.com (Postfix, from userid 47) id 933AD2B0; Tue, 3 Oct 2006 12:15:11 -0700 (PDT) Received: from mail-irva-8.broadcom.com (mail-irva-8 [10.10.64.221]) by mail-irva-10.broadcom.com (Postfix) with ESMTP id 6A55E2AE for ; Tue, 3 Oct 2006 12:15:11 -0700 (PDT) Received: from mail-sj1-12.sj.broadcom.com (mail-sj1-12.sj.broadcom.com [10.16.128.215]) by mail-irva-8.broadcom.com (MOS 3.7.5a-GA) with ESMTP id EGL94526; Tue, 3 Oct 2006 12:15:11 -0700 (PDT) Received: from NT-SJCA-0750.brcm.ad.broadcom.com (nt-sjca-0750 [10.16.192.220]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 174CF20501 for ; Tue, 3 Oct 2006 12:15:11 -0700 (PDT) Received: from NT-SJCA-0752.brcm.ad.broadcom.com ([10.16.192.222]) by NT-SJCA-0750.brcm.ad.broadcom.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 3 Oct 2006 12:15:10 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Subject: Build error Date: Tue, 3 Oct 2006 12:15:09 -0700 Message-ID: <710F16C36810444CA2F5821E5EAB7F230A0FB6@NT-SJCA-0752.brcm.ad.broadcom.com> Thread-Topic: Build error Thread-Index: AcbnID4nsYv0X9gERxaKGlGLzCI2Ew== From: "Manoj Ekbote" To: linux-mips@linux-mips.org X-OriginalArrivalTime: 03 Oct 2006 19:15:10.0934 (UTC) FILETIME=[3F0BB760:01C6E720] X-TMWD-Spam-Summary: TS=20061003191512; SEV=2.0.2; DFV=A2006100307; IFV=2.0.4,4.0-8; RPD=4.00.0004; ENG=IBF; RPDID=303030312E30413031303230352E34353232423638422E303037332D412D; CAT=NONE; CON=NONE X-MMS-Spam-Filter-ID: A2006100307_4.00.0004_4.0-8 X-WSS-ID: 693C69352I0973040-01-01 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12789 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manoje@broadcom.com Precedence: bulk X-list: linux-mips Hi, I see this error while compiling the latest sources: CC init/version.o LD init/built-in.o LD .tmp_vmlinux1 arch/mips/kernel/built-in.o: In function `do_gettimeofday': : undefined reference to `tickadj' arch/mips/kernel/built-in.o: In function `do_gettimeofday': : undefined reference to `tickadj' make: *** [.tmp_vmlinux1] Error 1 There is no definition of tickadj anywhere in the tree. Is it supposed to be in kernel/time/ntp.c? /manoj From mlachwani@mvista.com Tue Oct 3 20:28:23 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 20:28:26 +0100 (BST) Received: from gateway-1237.mvista.com ([63.81.120.158]:7479 "EHLO gateway-1237.mvista.com") by ftp.linux-mips.org with ESMTP id S20038884AbWJCT2X (ORCPT ); Tue, 3 Oct 2006 20:28:23 +0100 Received: from [10.0.0.139] (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 711F31BB52; Tue, 3 Oct 2006 12:28:14 -0700 (PDT) Message-ID: <4522B9CE.8060502@mvista.com> Date: Tue, 03 Oct 2006 12:28:14 -0700 From: mlachwani User-Agent: Thunderbird 1.5.0.7 (X11/20060909) MIME-Version: 1.0 To: Manoj Ekbote Cc: linux-mips@linux-mips.org Subject: Re: Build error References: <710F16C36810444CA2F5821E5EAB7F230A0FB6@NT-SJCA-0752.brcm.ad.broadcom.com> In-Reply-To: <710F16C36810444CA2F5821E5EAB7F230A0FB6@NT-SJCA-0752.brcm.ad.broadcom.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12790 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Manoj Ekbote wrote: > Hi, > > I see this error while compiling the latest sources: > > CC init/version.o > LD init/built-in.o > LD .tmp_vmlinux1 > arch/mips/kernel/built-in.o: In function `do_gettimeofday': > : undefined reference to `tickadj' > arch/mips/kernel/built-in.o: In function `do_gettimeofday': > : undefined reference to `tickadj' > make: *** [.tmp_vmlinux1] Error 1 > > There is no definition of tickadj anywhere in the tree. Is it supposed > to be in kernel/time/ntp.c? > > > /manoj > > > > I think you would need the GENERIC_TIME support enabled. Thanks Manish Lachwani From sshtylyov@ru.mvista.com Tue Oct 3 20:46:18 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 20:46:20 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:13736 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20038883AbWJCTqS (ORCPT ); Tue, 3 Oct 2006 20:46:18 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 28CF43ED3; Tue, 3 Oct 2006 12:46:01 -0700 (PDT) Message-ID: <4522BDFC.5040701@ru.mvista.com> Date: Tue, 03 Oct 2006 23:46:04 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [MIPS] Fix wreckage after removal of tickadj; convert to GENERIC_TIME. References: In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12791 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. linux-mips@linux-mips.org wrote: > Author: Ralf Baechle Mon Oct 2 16:54:48 2006 +0100 > Commit: 452dce20d066a17a85bc3fb5a9d1c9fed610e328 > Gitweb: http://www.linux-mips.org/g/linux/452dce20 > Branch: master > Signed-off-by: Ralf Baechle > --- > arch/mips/Kconfig | 4 +++ > arch/mips/dec/time.c | 2 - > arch/mips/kernel/time.c | 74 ----------------------------------------------- > 3 files changed, 4 insertions(+), 76 deletions(-) Well, be forewarned that with this patch, MIPS kernel now only has jiffy-precise time resolution. I.e. you could have killed all gettimeoffset handlers I suppose since there's nothing to call them from anymore. We need a clocksource patch added now to restore the old functionality (it's currently a part of the RT patch)... WBR, Sergei From ralf@linux-mips.org Tue Oct 3 21:13:22 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 21:13:23 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:59280 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20038894AbWJCUNW (ORCPT ); Tue, 3 Oct 2006 21:13:22 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k93KDMva006329; Tue, 3 Oct 2006 21:13:22 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k93KDLJH006328; Tue, 3 Oct 2006 21:13:21 +0100 Date: Tue, 3 Oct 2006 21:13:21 +0100 From: Ralf Baechle To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Subject: Re: [MIPS] Fix wreckage after removal of tickadj; convert to GENERIC_TIME. Message-ID: <20061003201320.GB4934@linux-mips.org> References: <4522BDFC.5040701@ru.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4522BDFC.5040701@ru.mvista.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12792 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Oct 03, 2006 at 11:46:04PM +0400, Sergei Shtylyov wrote: > Well, be forewarned that with this patch, MIPS kernel now only has > jiffy-precise time resolution. I.e. you could have killed all gettimeoffset > handlers I suppose since there's nothing to call them from anymore. We need > a clocksource patch added now to restore the old functionality (it's > currently a part of the RT patch)... After the other broken time patch it was most important to get the kernel buildable again. We can still sort out the clock source. Ralf From wilson@specifix.com Tue Oct 3 21:26:44 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Oct 2006 21:26:48 +0100 (BST) Received: from w099.z064220152.sjc-ca.dsl.cnc.net ([64.220.152.99]:60806 "EHLO bluesmobile.corp.specifix.com") by ftp.linux-mips.org with ESMTP id S20038916AbWJCU0o (ORCPT ); Tue, 3 Oct 2006 21:26:44 +0100 Received: from localhost.localdomain (bluesmobile.specifix.com [64.220.152.99]) by bluesmobile.corp.specifix.com (Postfix) with ESMTP id 203DB3B8FE; Tue, 3 Oct 2006 13:20:58 -0700 (PDT) Subject: Re: Roll-your-own Toolchain Builds From: Jim Wilson To: Pak Woon Cc: linux-mips@linux-mips.org In-Reply-To: <4522175B.80901@nec.com.au> References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> <4522175B.80901@nec.com.au> Content-Type: text/plain Date: Tue, 03 Oct 2006 13:25:47 -0700 Message-Id: <1159907147.23111.14.camel@dhcp-128-107-166-62.cisco.com> Mime-Version: 1.0 X-Mailer: Evolution 2.6.3 (2.6.3-1.fc5.5) Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12793 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilson@specifix.com Precedence: bulk X-list: linux-mips On Tue, 2006-10-03 at 17:55 +1000, Pak Woon wrote: > I am trying to roll-my-own toolchain by following the instructions > outlined in http://www.linux-mips.org/wiki/Toolchains. I have > encountered the "cannot create executables" / "crt01.o: No such file" This is lacking the details and context necessary to understand what is going on. What exactly command did you type? What exactly was the error you got? What was the make output leading up to the error? Thinking about this a bit, I think the problem you ran into here is that the instructions given on the web site are for building a kernel only compiler. This is not a compiler that you can use for building applications, as there is no glibc. This is also not a compiler that you can use for building gcc libraries. So the problem here is that gcc-4.x contains more libraries than gcc-3.x, including some written in C. The instructions say to use --enable-languages=c when configuring, and then type make all. This will work in gcc-3.x as there are no libraries for the C front end. This will not work for gcc-4.x, as there is at least one library for the C front end, namely mudflap. So I am guessing you got the error while configuring libmudflap. The solution is to use "make all-gcc" instead of "make all" when building gcc. This will build only the compiler (and libgcc), without any of the target libraries, that are unneeded for a kernel compiler. If this works, perhaps the instructions on the wiki should be changed. Using "make all-gcc" should work for all gcc versions. -- Jim Wilson, GNU Tools Support, http://www.specifix.com From akpm@osdl.org Wed Oct 4 02:02:11 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Oct 2006 02:02:15 +0100 (BST) Received: from p549F5BCD.dip.t-dialin.net ([84.159.91.205]:21705 "EHLO p549F5BCD.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20038942AbWJDBCL (ORCPT ); Wed, 4 Oct 2006 02:02:11 +0100 Received: from smtp.osdl.org ([65.172.181.4]:63887 "EHLO smtp.osdl.org") by lappi.linux-mips.net with ESMTP id S1100430AbWJCXqR (ORCPT + 1 other); Wed, 4 Oct 2006 01:46:17 +0200 Received: from shell0.pdx.osdl.net (fw.osdl.org [65.172.181.6]) by smtp.osdl.org (8.12.8/8.12.8) with ESMTP id k93NgsaX021601 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Tue, 3 Oct 2006 16:42:56 -0700 Received: from akpm.corp.google.com (shell0.pdx.osdl.net [10.9.0.31]) by shell0.pdx.osdl.net (8.13.1/8.11.6) with SMTP id k93NgrP8017346; Tue, 3 Oct 2006 16:42:54 -0700 Date: Tue, 3 Oct 2006 16:42:53 -0700 From: Andrew Morton To: "Maciej W. Rozycki" Cc: Jeff Garzik , Ralf Baechle , Andy Fleming , netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [patch 4/6] 2.6.18: sb1250-mac: The actual driver update Message-Id: <20061003164253.62f9d5a3.akpm@osdl.org> In-Reply-To: References: X-Mailer: Sylpheed version 2.2.7 (GTK+ 2.8.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: osdl$Revision: 1.155 $ X-Scanned-By: MIMEDefang 2.36 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12794 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@osdl.org Precedence: bulk X-list: linux-mips On Tue, 3 Oct 2006 16:18:44 +0100 (BST) "Maciej W. Rozycki" wrote: > + sbmac_state_t sbm_state; /* current state */ argh. The reader looks at this and doesn't know if it's an integer, a void*, a struct usb_ac_header_descriptor** or what. enum sbmac_state smb_state; is nicer. It has information. From ralf@linux-mips.org Wed Oct 4 02:10:56 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Oct 2006 02:10:58 +0100 (BST) Received: from p549F5BCD.dip.t-dialin.net ([84.159.91.205]:18644 "EHLO p549F5BCD.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20038954AbWJDBK4 (ORCPT ); Wed, 4 Oct 2006 02:10:56 +0100 Received: from localhost ([127.0.0.1]:33731 "EHLO dl5rb.ham-radio-op.net") by lappi.linux-mips.net with ESMTP id S1100411AbWJDBKy (ORCPT + 1 other); Wed, 4 Oct 2006 03:10:54 +0200 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k941AoAD010443; Wed, 4 Oct 2006 02:10:50 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k941Akha010441; Wed, 4 Oct 2006 02:10:46 +0100 Date: Wed, 4 Oct 2006 02:10:46 +0100 From: Ralf Baechle To: Andrew Morton Cc: "Maciej W. Rozycki" , Jeff Garzik , Andy Fleming , netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [patch 4/6] 2.6.18: sb1250-mac: The actual driver update Message-ID: <20061004011046.GA10247@linux-mips.org> References: <20061003164253.62f9d5a3.akpm@osdl.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20061003164253.62f9d5a3.akpm@osdl.org> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12795 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Oct 03, 2006 at 04:42:53PM -0700, Andrew Morton wrote: > On Tue, 3 Oct 2006 16:18:44 +0100 (BST) > "Maciej W. Rozycki" wrote: > > > + sbmac_state_t sbm_state; /* current state */ > > argh. > > The reader looks at this and doesn't know if it's an integer, a void*, a > struct usb_ac_header_descriptor** or what. > > enum sbmac_state smb_state; > > is nicer. It has information. De-typedef-ing would be a separate project for this driver which makes quite generous use of typedefs. Ralf From anemo@mba.ocn.ne.jp Wed Oct 4 02:31:03 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Oct 2006 02:31:05 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:2861 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20038977AbWJDBbD (ORCPT ); Wed, 4 Oct 2006 02:31:03 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Wed, 4 Oct 2006 10:31:01 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 8065F41823; Wed, 4 Oct 2006 10:30:59 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 6D74C3D392; Wed, 4 Oct 2006 10:30:59 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k941UwW0099258; Wed, 4 Oct 2006 10:30:59 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Wed, 04 Oct 2006 10:30:58 +0900 (JST) Message-Id: <20061004.103058.25910611.nemoto@toshiba-tops.co.jp> To: ralf@linux-mips.org Cc: sshtylyov@ru.mvista.com, linux-mips@linux-mips.org Subject: Re: [MIPS] Fix wreckage after removal of tickadj; convert to GENERIC_TIME. From: Atsushi Nemoto In-Reply-To: <20061003201320.GB4934@linux-mips.org> References: <4522BDFC.5040701@ru.mvista.com> <20061003201320.GB4934@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12796 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Tue, 3 Oct 2006 21:13:21 +0100, Ralf Baechle wrote: > > Well, be forewarned that with this patch, MIPS kernel now only has > > jiffy-precise time resolution. I.e. you could have killed all gettimeoffset > > handlers I suppose since there's nothing to call them from anymore. We need > > a clocksource patch added now to restore the old functionality (it's > > currently a part of the RT patch)... > > After the other broken time patch it was most important to get the > kernel buildable again. We can still sort out the clock source. This topic was raised on LKML a month ago. http://lkml.org/lkml/2006/8/31/141 If you just wanted to fix the "undefined reference problem", replacing "tickadj" with 500 (max ntp adjustment time) would be enough. Of course, MIPS clock source would be preferred if it is available soon. --- Atsushi Nemoto From deepfire@elvees.com Wed Oct 4 13:36:01 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Oct 2006 13:36:05 +0100 (BST) Received: from 209-100-st.zelcom.ru ([80.92.102.209]:45003 "EHLO mail.elvees.com") by ftp.linux-mips.org with ESMTP id S20038546AbWJDMgB (ORCPT ); Wed, 4 Oct 2006 13:36:01 +0100 Received: from (IP:80.92.102.210) (authenticated with LOGIN user mail-deepfire) by mail.elvees.com with ESMTP id k94Capgn059136; Wed, 4 Oct 2006 16:36:51 +0400 (MSD) (envelope-from deepfire@elvees.com) From: Samium Gromoff To: Peter Watkins Subject: Re: 16KB PAGE_SIZE on r4k Date: Wed, 4 Oct 2006 16:35:13 +0400 User-Agent: KMail/1.9.1 References: <200609221906.30516.deepfire@elvees.com> <451AD9C1.6080608@gmail.com> In-Reply-To: <451AD9C1.6080608@gmail.com> Cc: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset="koi8-r" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200610041635.13622.deepfire@elvees.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12797 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: deepfire@elvees.com Precedence: bulk X-list: linux-mips On Thursday 28 September 2006 00:06, you wrote: > Samium Gromoff wrote: > > How reliable is 16KB PAGE_SIZE on r4k-likes in kernels around 2.6.17? > > > > Is it known to work? > > > > regards, Samium Gromoff > > > > > > You might want to look at: > > http://www.linux-mips.org/archives/linux-mips/2006-08/msg00294.html > http://www.linux-mips.org/archives/linux-mips/2006-08/msg00244.html > Thanks, looks daunting enough... :-| regards, Samium Gromoff From pak.woon@nec.com.au Thu Oct 5 07:04:25 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 07:04:29 +0100 (BST) Received: from ns2.nec.com.au ([147.76.180.2]:51605 "EHLO ns2.nec.com.au") by ftp.linux-mips.org with ESMTP id S20037647AbWJEGEZ (ORCPT ); Thu, 5 Oct 2006 07:04:25 +0100 Received: from smtp1.nec.com.au (unknown [172.31.8.18]) by ns2.nec.com.au (Postfix) with ESMTP id 332DE3B6A2 for ; Thu, 5 Oct 2006 16:04:15 +1000 (EST) Received: from [147.76.208.162] ([147.76.208.162]) by tns.neca.nec.com.au (8.12.8/8.12.8) with ESMTP id k956A9Zl012216 for ; Thu, 5 Oct 2006 16:10:11 +1000 Message-ID: <45249FE6.8080800@nec.com.au> Date: Thu, 05 Oct 2006 16:02:14 +1000 From: Pak Woon User-Agent: Mozilla Thunderbird 1.0.2 (Windows/20050317) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: Roll-your-own Toolchain Builds References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> <4522175B.80901@nec.com.au> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12798 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pak.woon@nec.com.au Precedence: bulk X-list: linux-mips Daniel Stenberg wrote: > On Tue, 3 Oct 2006, Pak Woon wrote: > >> I am trying to roll-my-own toolchain by following the instructions >> outlined in http://www.linux-mips.org/wiki/Toolchains. > > >> binutils-2.16.91.0.6-5 >> gcc-4.1.1-1.fc5 > > > Funny, since that page says that the recommended gcc version is 3.4.4 > and binutils 2.16.1... (even though I've had no problems with 3.4.6 myself) First of all, thank you all for your suggestions. I have successfully built my own toolchain (using binutils-2.16.1 and gcc-3.4.4). I have also successfully built the kernel for the target board. (with git checkout linux-2.16.18-stable) [ltu@PAKW-FEDORA linux.git]$ readelf -h vmlinux ELF Header: Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, little endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: EXEC (Executable file) Machine: MIPS R3000 Version: 0x1 Entry point address: 0x803c3000 Start of program headers: 52 (bytes into file) Start of section headers: 3056172 (bytes into file) Flags: 0x70001001, noreorder, o32, mips32r2 Size of this header: 52 (bytes) Size of program headers: 32 (bytes) Number of program headers: 1 Size of section headers: 40 (bytes) Number of section headers: 34 Section header string table index: 31 I am now trying to build a simple program with my new toolchain and I've come across the "can't find crt1.o" problem again. I am struggling with this. [ltu@PAKW-FEDORA tmp]$ mips-unknown-linux-gnu-gcc -v hello.c Using built-in specs. Configured with: ../gcc-3.4.4/configure --target=mips-unknown-linux-gnu --prefix=/home/ltu/development/mips-linux-toolchain --enable-languages=c --without-headers --with-gnu-ld --with-gnu-as --disable-shared --disable-threads Thread model: single gcc version 3.4.4 /home/ltu/development/mips-linux-toolchain/libexec/gcc/mips-unknown-linux-gnu/3.4.4/cc1 -quiet -v hello.c -quiet -dumpbase hello.c -auxbase hello -version -o /tmp/ccETB2Cl.s ignoring nonexistent directory "/home/ltu/development/mips-linux-toolchain/lib/gcc/mips-unknown-linux-gnu/3.4.4/../../../../mips-unknown-linux-gnu/sys-include" ignoring nonexistent directory "/home/ltu/development/mips-linux-toolchain/lib/gcc/mips-unknown-linux-gnu/3.4.4/../../../../mips-unknown-linux-gnu/include" #include "..." search starts here: #include <...> search starts here: /home/ltu/development/mips-linux-toolchain/lib/gcc/mips-unknown-linux-gnu/3.4.4/include End of search list. GNU C version 3.4.4 (mips-unknown-linux-gnu) compiled by GNU C version 4.1.1 20060525 (Red Hat 4.1.1-1). GGC heuristics: --param ggc-min-expand=64 --param ggc-min-heapsize=64461 hello.c: In function `main': hello.c:2: warning: return type of 'main' is not `int' /home/ltu/development/mips-linux-toolchain/lib/gcc/mips-unknown-linux-gnu/3.4.4/../../../../mips-unknown-linux-gnu/bin/as -EB -no-mdebug -32 -v -KPIC -o /tmp/ccoPzQTv.o /tmp/ccETB2Cl.s GNU assembler version 2.16.1 (mips-unknown-linux-gnu) using BFD version 2.16.1 /home/ltu/development/mips-linux-toolchain/libexec/gcc/mips-unknown-linux-gnu/3.4.4/collect2 --eh-frame-hdr -EB -dynamic-linker /lib/ld.so.1 crt1.o crti.o /home/ltu/development/mips-linux-toolchain/lib/gcc/mips-unknown-linux-gnu/3.4.4/crtbegin.o -L/home/ltu/development/mips-linux-toolchain/lib/gcc/mips-unknown-linux-gnu/3.4.4 -L/home/ltu/development/mips-linux-toolchain/lib/gcc/mips-unknown-linux-gnu/3.4.4/../../../../mips-unknown-linux-gnu/lib /tmp/ccoPzQTv.o -lgcc -rpath-link /lib:/usr/lib -lc -lgcc /home/ltu/development/mips-linux-toolchain/lib/gcc/mips-unknown-linux-gnu/3.4.4/crtend.o crtn.o /home/ltu/development/mips-linux-toolchain/lib/gcc/mips-unknown-linux-gnu/3.4.4/../../../../mips-unknown-linux-gnu/bin/ld: crt1.o: No such file: No such file or directory collect2: ld returned 1 exit status [ltu@PAKW-FEDORA tmp]$ echo $PATH /home/ltu/development/mips-linux-toolchain/bin:/bin:/usr/bin [ltu@PAKW-FEDORA tmp]$ From my understanding, to compile code for my MIPS target, I need to use mips-unknown-linux-gnu-gcc (which, I assume is the same as /mips-linux-toolchain/mips-unknwn-linux-gnu/bin/gcc). I have ensured my $PATH is the bare minimum. This is the same problem as I was getting when I was trying to build a gcc-4.1.1-1.fc5 based cross compiler. I am really stuck. FYI, my hello.c is: void main ( void ) { volatile int i,j,k; i = 2; j = 1; k = i + j; } Thanks in advance Regards, Pak From yoichi_yuasa@tripeaks.co.jp Thu Oct 5 07:18:02 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 07:18:03 +0100 (BST) Received: from mo30.po.2iij.net ([210.128.50.53]:20509 "EHLO mo30.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20037651AbWJEGSC (ORCPT ); Thu, 5 Oct 2006 07:18:02 +0100 Received: by mo.po.2iij.net (mo30) id k956Hxpk088002; Thu, 5 Oct 2006 15:17:59 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox30) id k956HuvD067996 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 5 Oct 2006 15:17:56 +0900 (JST) Date: Thu, 5 Oct 2006 15:17:56 +0900 From: Yoichi Yuasa To: Pak Woon Cc: linux-mips@linux-mips.org Subject: Re: Roll-your-own Toolchain Builds Message-Id: <20061005151756.6911f9de.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <45249FE6.8080800@nec.com.au> References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> <4522175B.80901@nec.com.au> <45249FE6.8080800@nec.com.au> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12799 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Pak, On Thu, 05 Oct 2006 16:02:14 +1000 Pak Woon wrote: > I am now trying to build a simple program with my new toolchain and I've > come across the "can't find crt1.o" problem again. I am struggling with > this. You need glibc or uClibc for MIPS target. If you want to use uClibc, see buildroot link in http://www.linux-mips.org/wiki/Toolchains . Yoichi From pak.woon@nec.com.au Thu Oct 5 07:53:28 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 07:53:30 +0100 (BST) Received: from ns2.nec.com.au ([147.76.180.2]:62368 "EHLO ns2.nec.com.au") by ftp.linux-mips.org with ESMTP id S20037758AbWJEGx2 (ORCPT ); Thu, 5 Oct 2006 07:53:28 +0100 Received: from smtp1.nec.com.au (unknown [172.31.8.18]) by ns2.nec.com.au (Postfix) with ESMTP id BB6CD3B6A9 for ; Thu, 5 Oct 2006 16:53:20 +1000 (EST) Received: from [147.76.208.162] ([147.76.208.162]) by tns.neca.nec.com.au (8.12.8/8.12.8) with ESMTP id k956xGZl014904; Thu, 5 Oct 2006 16:59:16 +1000 Message-ID: <4524AB69.4040802@nec.com.au> Date: Thu, 05 Oct 2006 16:51:21 +1000 From: Pak Woon User-Agent: Mozilla Thunderbird 1.0.2 (Windows/20050317) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Yoichi Yuasa Cc: linux-mips@linux-mips.org Subject: Re: Roll-your-own Toolchain Builds References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> <4522175B.80901@nec.com.au> <45249FE6.8080800@nec.com.au> <20061005151756.6911f9de.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20061005151756.6911f9de.yoichi_yuasa@tripeaks.co.jp> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12800 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pak.woon@nec.com.au Precedence: bulk X-list: linux-mips >>I am now trying to build a simple program with my new toolchain and I've >>come across the "can't find crt1.o" problem again. I am struggling with >>this. > > > You need glibc or uClibc for MIPS target. > > If you want to use uClibc, see buildroot link in > http://www.linux-mips.org/wiki/Toolchains . Okay, this is going to be a stupid question, but when I built the kernel for the MIPS target, I had no issues or a need for those libs. I assumed that for such a simple hello.c program, I would not need glibc or uClibc either. Pak From yoichi_yuasa@tripeaks.co.jp Thu Oct 5 08:10:34 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 08:10:36 +0100 (BST) Received: from mo32.po.2iij.net ([210.128.50.17]:46665 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20038505AbWJEHKe (ORCPT ); Thu, 5 Oct 2006 08:10:34 +0100 Received: by mo.po.2iij.net (mo32) id k957AW06012695; Thu, 5 Oct 2006 16:10:32 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox33) id k957AVKf040935 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 5 Oct 2006 16:10:31 +0900 (JST) Message-Id: <200610050710.k957AVKf040935@mbox33.po.2iij.net> Date: Thu, 5 Oct 2006 16:10:31 +0900 From: Yoichi Yuasa To: Pak Woon Cc: linux-mips@linux-mips.org Subject: Re: Roll-your-own Toolchain Builds In-Reply-To: <4524AB69.4040802@nec.com.au> References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> <4522175B.80901@nec.com.au> <45249FE6.8080800@nec.com.au> <20061005151756.6911f9de.yoichi_yuasa@tripeaks.co.jp> <4524AB69.4040802@nec.com.au> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12801 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Pak, On Thu, 05 Oct 2006 16:51:21 +1000 Pak Woon wrote: > >>I am now trying to build a simple program with my new toolchain and I've > >>come across the "can't find crt1.o" problem again. I am struggling with > >>this. > > > > > > You need glibc or uClibc for MIPS target. > > > > If you want to use uClibc, see buildroot link in > > http://www.linux-mips.org/wiki/Toolchains . > > Okay, this is going to be a stupid question, but when I built the kernel > for the MIPS target, I had no issues or a need for those libs. I assumed > that for such a simple hello.c program, I would not need glibc or uClibc > either. kernel doesn't need glibc, uClibc and others. If it's standard hello.c, C library is necessary for it ;) Yoichi From yoichi_yuasa@tripeaks.co.jp Thu Oct 5 08:39:22 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 08:39:25 +0100 (BST) Received: from mo31.po.2iij.net ([210.128.50.54]:25128 "EHLO mo31.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20038966AbWJEHjV (ORCPT ); Thu, 5 Oct 2006 08:39:21 +0100 Received: by mo.po.2iij.net (mo31) id k957dJKj077360; Thu, 5 Oct 2006 16:39:19 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox33) id k957dHLU006916 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT) for ; Thu, 5 Oct 2006 16:39:18 +0900 (JST) Date: Thu, 5 Oct 2006 16:39:17 +0900 From: Yoichi Yuasa To: linux-mips@linux-mips.org Subject: Re: Roll-your-own Toolchain Builds Message-Id: <20061005163917.1a6480e4.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <200610050710.k957AVKf040935@mbox33.po.2iij.net> References: <20061002231432.733374f7.yoichi_yuasa@tripeaks.co.jp> <20061002151800.GA25180@linux-mips.org> <200610030144.k931i4TD002658@mbox32.po.2iij.net> <4522175B.80901@nec.com.au> <45249FE6.8080800@nec.com.au> <20061005151756.6911f9de.yoichi_yuasa@tripeaks.co.jp> <4524AB69.4040802@nec.com.au> <200610050710.k957AVKf040935@mbox33.po.2iij.net> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12802 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Pak, I received error mail from your mail server. On Thu, 05 Oct 2006 17:15:55 +1000 Pak Woon wrote: > > My hello.c is:- > void main ( void ) > { > volatile int i,j,k; > > i = 2; > j = 1; > k = i + j; > } main() needs C library. Yoichi From zzh.hust@gmail.com Thu Oct 5 09:55:31 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 09:55:34 +0100 (BST) Received: from ug-out-1314.google.com ([66.249.92.172]:1058 "EHLO ug-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20038986AbWJEIzb (ORCPT ); Thu, 5 Oct 2006 09:55:31 +0100 Received: by ug-out-1314.google.com with SMTP id 40so185156uga for ; Thu, 05 Oct 2006 01:55:31 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=tap3BwvqW+3Bm2LPzMHCzpjfJk5E7vD1jd6z3JZDE2IPEY40+BVrheeIJS1QiE1jcSbGt8mK6SqNaQIcwCi8yg/dRbhn5jprpf6jZ88vAHDu5apBh38a7ifdjcLsvJ5fbcKyerMEd85/h8s2bbNXNMgGpE3ZLfNOwLLfefCsjCE= Received: by 10.67.101.10 with SMTP id d10mr1623899ugm; Thu, 05 Oct 2006 01:55:30 -0700 (PDT) Received: by 10.66.241.3 with HTTP; Thu, 5 Oct 2006 01:55:30 -0700 (PDT) Message-ID: <50c9a2250610050155r9928a24rf41cf58a73e7a89c@mail.gmail.com> Date: Thu, 5 Oct 2006 16:55:30 +0800 From: zhuzhenhua To: linux-mips Subject: how to do a fast checksum for ext2fs? MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12803 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zzh.hust@gmail.com Precedence: bulk X-list: linux-mips on my board, i use the ext2fs as rootfs on a DOC device, and i want do a fast checksum for the rootfs, is there only one way to use fsck? thanks for any hints Best Regards zhuzhenhua From Ramgopal.Kota@analog.com Thu Oct 5 11:09:23 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 11:09:25 +0100 (BST) Received: from nwd2mail11.analog.com ([137.71.25.57]:22368 "EHLO nwd2mail11.analog.com") by ftp.linux-mips.org with ESMTP id S20038488AbWJEKJX convert rfc822-to-8bit (ORCPT ); Thu, 5 Oct 2006 11:09:23 +0100 Received: from nwd2mhb2.analog.com ([137.71.6.12]) by nwd2mail11.analog.com with ESMTP; 05 Oct 2006 06:06:11 -0400 X-IronPort-AV: i="4.09,262,1157342400"; d="scan'208"; a="10930511:sNHT21344141" Received: from nwd2exm4.ad.analog.com (nwd2exm4.ad.analog.com [10.64.53.123]) by nwd2mhb2.analog.com (8.9.3 (PHNE_28810+JAGae91741)/8.9.3) with ESMTP id GAA18664 for ; Thu, 5 Oct 2006 06:09:24 -0400 (EDT) Received: from nwd2exm5.ad.analog.com ([10.64.51.20]) by nwd2exm4.ad.analog.com with Microsoft SMTPSVC(6.0.3790.211); Thu, 5 Oct 2006 06:09:22 -0400 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: R300 Mips Question Date: Thu, 5 Oct 2006 06:09:19 -0400 Message-ID: <7D453D0504B6A2429F98F4D72CBEDE490D7D8795@nwd2exm5.ad.analog.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: R300 Mips Question Thread-Index: AcboZlJ231HtYJLvR06W36U1NH9K6Q== From: "Kota, Ramgopal" To: X-OriginalArrivalTime: 05 Oct 2006 10:09:22.0100 (UTC) FILETIME=[540BB740:01C6E866] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12804 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Ramgopal.Kota@analog.com Precedence: bulk X-list: linux-mips Content-Length: 1471 Lines: 50 Hi, I am new to MIPS and uclinux port.I am getting familiarised with 2.6.18 linux code. I see the following code in asm/mips/kernel/genex.S & asm/mips/kernel/traps.c ++++++++++++ Genex.S +++++++++++++ NESTED(except_vec3_generic, 0, sp) .set push .set noat #if R5432_CP0_INTERRUPT_WAR mfc0 k0, CP0_INDEX #endif mfc0 k1, CP0_CAUSE andi k1, k1, 0x7c #ifdef CONFIG_64BIT dsll k1, k1, 1 #endif PTR_L k0, exception_handlers(k1) jr k0 .set pop END(except_vec3_generic) +++++++++++++ traps.c +++++++++++++++ set_except_vector(0, handle_int); set_except_vector(1, handle_tlbm); set_except_vector(2, handle_tlbl); set_except_vector(3, handle_tlbs); set_except_vector(4, handle_adel); set_except_vector(5, handle_ades); set_except_vector(6, handle_ibe); set_except_vector(7, handle_dbe); set_except_vector(8, handle_sys); set_except_vector(9, handle_bp); set_except_vector(10, handle_ri); set_except_vector(11, handle_cpu); set_except_vector(12, handle_ov); set_except_vector(13, handle_tr); In R3000 manual , bits 2-6 indicate exception code value. In genex.S , the cause register is anded with 0x7c to extract 2-6 bits. I am not able to understand why it is not shifted the last 2 bits. Please try to educate me why this is not done. Ramgopal Kota From jgarzik@pobox.com Thu Oct 5 12:00:17 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 12:00:18 +0100 (BST) Received: from srv5.dvmed.net ([207.36.208.214]:33244 "EHLO mail.dvmed.net") by ftp.linux-mips.org with ESMTP id S20039152AbWJELAR (ORCPT ); Thu, 5 Oct 2006 12:00:17 +0100 Received: from cpe-065-190-194-075.nc.res.rr.com ([65.190.194.75] helo=[10.10.10.99]) by mail.dvmed.net with esmtpsa (Exim 4.62 #1 (Red Hat Linux)) id 1GVQxa-0005ql-HY; Thu, 05 Oct 2006 11:00:15 +0000 Message-ID: <4524E5BD.1040000@pobox.com> Date: Thu, 05 Oct 2006 07:00:13 -0400 From: Jeff Garzik User-Agent: Thunderbird 1.5.0.7 (X11/20060913) MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: Andrew Morton , Ralf Baechle , Andy Fleming , netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [patch 1/6] 2.6.18: sb1250-mac: Broadcom PHY support References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12805 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jgarzik@pobox.com Precedence: bulk X-list: linux-mips Content-Length: 369 Lines: 15 Maciej W. Rozycki wrote: > Hello, [...] > Please consider. > > Maciej Please don't include this in the patch description. It must be hand-edited out, before applying with git-applymbox. All comments should be placed AFTER the "---" separator, which terminates the patch description. Applied patches 1-3, patch #4 failed due to drivers/net/Kconfig breakage From jeff@garzik.org Thu Oct 5 12:02:39 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 12:02:41 +0100 (BST) Received: from srv5.dvmed.net ([207.36.208.214]:57052 "EHLO mail.dvmed.net") by ftp.linux-mips.org with ESMTP id S20039161AbWJELCj (ORCPT ); Thu, 5 Oct 2006 12:02:39 +0100 Received: from cpe-065-190-194-075.nc.res.rr.com ([65.190.194.75] helo=[10.10.10.99]) by mail.dvmed.net with esmtpsa (Exim 4.62 #1 (Red Hat Linux)) id 1GVQzp-0005rz-B6; Thu, 05 Oct 2006 11:02:34 +0000 Message-ID: <4524E648.2000706@garzik.org> Date: Thu, 05 Oct 2006 07:02:32 -0400 From: Jeff Garzik User-Agent: Thunderbird 1.5.0.7 (X11/20060913) MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: Andrew Morton , Ralf Baechle , Andy Fleming , netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [patch 1/6] 2.6.18: sb1250-mac: Broadcom PHY support References: <4524E5BD.1040000@pobox.com> In-Reply-To: <4524E5BD.1040000@pobox.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12806 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jeff@garzik.org Precedence: bulk X-list: linux-mips Content-Length: 624 Lines: 24 Jeff Garzik wrote: > Maciej W. Rozycki wrote: >> Hello, > [...] >> Please consider. >> >> Maciej > > > Please don't include this in the patch description. It must be > hand-edited out, before applying with git-applymbox. All comments > should be placed AFTER the "---" separator, which terminates the patch > description. > > Applied patches 1-3, patch #4 failed due to drivers/net/Kconfig breakage Also, in your email subject line, the kernel version should be included in the [PATCH...] brackets. Please see http://linux.yyz.us/patch-format.html and Documentation/SubmittingPatches for more info. Jeff From geert@linux-m68k.org Thu Oct 5 12:14:26 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 12:14:31 +0100 (BST) Received: from witte.sonytel.be ([80.88.33.193]:46758 "EHLO witte.sonytel.be") by ftp.linux-mips.org with ESMTP id S20039152AbWJELO0 (ORCPT ); Thu, 5 Oct 2006 12:14:26 +0100 Received: from pademelon.sonytel.be (mail.sonytel.be [43.221.60.197]) by witte.sonytel.be (8.12.10/8.12.10) with ESMTP id k95BEMQe012566; Thu, 5 Oct 2006 13:14:22 +0200 (MEST) Date: Thu, 5 Oct 2006 13:14:21 +0200 (CEST) From: Geert Uytterhoeven To: "Kota, Ramgopal" cc: Linux/MIPS Development Subject: Re: R300 Mips Question In-Reply-To: <7D453D0504B6A2429F98F4D72CBEDE490D7D8795@nwd2exm5.ad.analog.com> Message-ID: References: <7D453D0504B6A2429F98F4D72CBEDE490D7D8795@nwd2exm5.ad.analog.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12807 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Content-Length: 2335 Lines: 67 On Thu, 5 Oct 2006, Kota, Ramgopal wrote: > I am new to MIPS and uclinux port.I am getting familiarised with 2.6.18 > linux code. > I see the following code in asm/mips/kernel/genex.S & > asm/mips/kernel/traps.c > > ++++++++++++ Genex.S +++++++++++++ > NESTED(except_vec3_generic, 0, sp) > .set push > .set noat > #if R5432_CP0_INTERRUPT_WAR > mfc0 k0, CP0_INDEX > #endif > mfc0 k1, CP0_CAUSE > andi k1, k1, 0x7c > #ifdef CONFIG_64BIT > dsll k1, k1, 1 > #endif > PTR_L k0, exception_handlers(k1) > jr k0 > .set pop > END(except_vec3_generic) > > +++++++++++++ traps.c +++++++++++++++ > set_except_vector(0, handle_int); > set_except_vector(1, handle_tlbm); > set_except_vector(2, handle_tlbl); > set_except_vector(3, handle_tlbs); > > set_except_vector(4, handle_adel); > set_except_vector(5, handle_ades); > > set_except_vector(6, handle_ibe); > set_except_vector(7, handle_dbe); > > set_except_vector(8, handle_sys); > set_except_vector(9, handle_bp); > set_except_vector(10, handle_ri); > set_except_vector(11, handle_cpu); > set_except_vector(12, handle_ov); > set_except_vector(13, handle_tr); > > In R3000 manual , bits 2-6 indicate exception code value. In genex.S , > the cause register is anded with 0x7c to extract 2-6 bits. > I am not able to understand why it is not shifted the last 2 bits. > > Please try to educate me why this is not done. The exception code value is used to obtain a pointer from the exception_handlers array. Since pointers are 32 bit, you have to convert the index into the array to an offset for the array by multiplying by 4. This nullifies the shift. On 64-bit platforms, pointers are 64 bit and the index is converted to an offset by multiplying by 8. Since the value is already shifted 2 positions to the left, only 1 shift remains to be done (cfr. the dsll). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From macro@linux-mips.org Thu Oct 5 17:04:19 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 17:04:25 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:15878 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20039279AbWJEQET (ORCPT ); Thu, 5 Oct 2006 17:04:19 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id E9775F65F5; Thu, 5 Oct 2006 18:04:07 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id h+CquEeJi9Mt; Thu, 5 Oct 2006 18:04:07 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 4AB6EF60DB; Thu, 5 Oct 2006 18:04:07 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k95G4Grc025516; Thu, 5 Oct 2006 18:04:16 +0200 Date: Thu, 5 Oct 2006 17:04:11 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton , Jeff Garzik , Ralf Baechle , Andy Fleming cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: [PATCH 2.6.18 4/6]: sb1250-mac: Driver model & phylib support Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1997/Wed Oct 4 17:20:43 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12808 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 50973 Lines: 1721 This is an update including the following changes: 1. Some help text for Kconfig. 2. Removal of unused module options. 3. Phylib support and the resulting removal of generic bits for handling the PHY. 4. Proper reserving of device resources and using ioremap()ped handles to access MAC registers rather than platform-specific macros. 5. Handling of the device using the driver model. Signed-off-by: Maciej W. Rozycki --- This revision fixes the problem with drivers/net/Kconfig. Please consider. Maciej patch-2.6.18-sb1250-mac-16 diff -up --recursive --new-file linux-2.6.18.macro/drivers/net/Kconfig linux-2.6.18/drivers/net/Kconfig --- linux-2.6.18.macro/drivers/net/Kconfig 2006-09-20 03:42:06.000000000 +0000 +++ linux-2.6.18/drivers/net/Kconfig 2006-10-05 15:50:20.000000000 +0000 @@ -456,6 +456,15 @@ config MIPS_AU1X00_ENET config NET_SB1250_MAC tristate "SB1250 Ethernet support" depends on NET_ETHERNET && SIBYTE_SB1xxx_SOC + select PHYLIB + ---help--- + This driver supports gigabit Ethernet interfaces based on the + Broadcom SiByte family of System-On-a-Chip parts. They include + the BCM1120, BCM1125, BCM1125H, BCM1250, BCM1255, BCM1280, BCM1455 + and BCM1480 chips. + + To compile this driver as a module, choose M here: the module + will be called sb1250-mac. config SGI_IOC3_ETH bool "SGI IOC3 Ethernet" diff -up --recursive --new-file linux-2.6.18.macro/drivers/net/sb1250-mac.c linux-2.6.18/drivers/net/sb1250-mac.c --- linux-2.6.18.macro/drivers/net/sb1250-mac.c 2006-09-20 03:42:06.000000000 +0000 +++ linux-2.6.18/drivers/net/sb1250-mac.c 2006-10-05 15:48:50.000000000 +0000 @@ -1,5 +1,6 @@ /* * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation + * Copyright (c) 2006 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -18,7 +19,11 @@ * * This driver is designed for the Broadcom SiByte SOC built-in * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp. + * + * Updated to the driver model and the PHY abstraction layer + * by Maciej W. Rozycki. */ + #include #include #include @@ -32,9 +37,18 @@ #include #include #include -#include /* Processor type for cache alignment. */ -#include +#include +#include +#include +#include +#include +#include +#include + +#include #include +#include +#include /* Processor type for cache alignment. */ /* This is only here until the firmware is ready. In that case, the firmware leaves the ethernet address in the register for us. */ @@ -48,7 +62,7 @@ /* These identify the driver base version and may not be removed. */ #if 0 -static char version1[] __devinitdata = +static char version1[] __initdata = "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n"; #endif @@ -57,8 +71,6 @@ static char version1[] __devinitdata = #define CONFIG_SBMAC_COALESCE -#define MAX_UNITS 4 /* More are supported, limit only on options */ - /* Time in jiffies before concluding the transmitter is hung. */ #define TX_TIMEOUT (2*HZ) @@ -74,26 +86,6 @@ static int debug = 1; module_param(debug, int, S_IRUGO); MODULE_PARM_DESC(debug, "Debug messages"); -/* mii status msgs */ -static int noisy_mii = 1; -module_param(noisy_mii, int, S_IRUGO); -MODULE_PARM_DESC(noisy_mii, "MII status messages"); - -/* Used to pass the media type, etc. - Both 'options[]' and 'full_duplex[]' should exist for driver - interoperability. - The media type is usually passed in 'options[]'. -*/ -#ifdef MODULE -static int options[MAX_UNITS] = {-1, -1, -1, -1}; -module_param_array(options, int, NULL, S_IRUGO); -MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS)); - -static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1}; -module_param_array(full_duplex, int, NULL, S_IRUGO); -MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS)); -#endif - #ifdef CONFIG_SBMAC_COALESCE static int int_pktcnt = 0; module_param(int_pktcnt, int, S_IRUGO); @@ -104,6 +96,7 @@ module_param(int_timeout, int, S_IRUGO); MODULE_PARM_DESC(int_timeout, "Timeout value"); #endif +#include #include #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #include @@ -126,22 +119,43 @@ MODULE_PARM_DESC(int_timeout, "Timeout v #error invalid SiByte MAC configuation #endif +#ifdef K_INT_PHY +#define SBMAC_PHY_INT K_INT_PHY +#else +#define SBMAC_PHY_INT PHY_POLL +#endif + /********************************************************************** * Simple types ********************************************************************* */ - -typedef enum { sbmac_speed_auto, sbmac_speed_10, - sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; - -typedef enum { sbmac_duplex_auto, sbmac_duplex_half, - sbmac_duplex_full } sbmac_duplex_t; - -typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, - sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; - -typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, - sbmac_state_broken } sbmac_state_t; +typedef enum { + sbmac_speed_none = 0, + sbmac_speed_10 = SPEED_10, + sbmac_speed_100 = SPEED_100, + sbmac_speed_1000 = SPEED_1000, +} sbmac_speed_t; + +typedef enum { + sbmac_duplex_none = -1, + sbmac_duplex_half = DUPLEX_HALF, + sbmac_duplex_full = DUPLEX_FULL, +} sbmac_duplex_t; + +typedef enum { + sbmac_fc_none, + sbmac_fc_disabled, + sbmac_fc_frame, + sbmac_fc_collision, + sbmac_fc_carrier, +} sbmac_fc_t; + +typedef enum { + sbmac_state_uninit, + sbmac_state_off, + sbmac_state_on, + sbmac_state_broken, +} sbmac_state_t; /********************************************************************** @@ -225,46 +239,46 @@ struct sbmac_softc { * Linux-specific things */ - struct net_device *sbm_dev; /* pointer to linux device */ - spinlock_t sbm_lock; /* spin lock */ - struct timer_list sbm_timer; /* for monitoring MII */ - struct net_device_stats sbm_stats; - int sbm_devflags; /* current device flags */ - - int sbm_phy_oldbmsr; - int sbm_phy_oldanlpar; - int sbm_phy_oldk1stsr; - int sbm_phy_oldlinkstat; - int sbm_buffersize; + struct net_device *sbm_dev; /* pointer to linux device */ + struct phy_device *phy_dev; /* the associated PHY device */ + struct mii_bus mii_bus; /* the MII bus */ + int phy_irq[PHY_MAX_ADDR]; + struct work_struct sbm_queue; /* used for the PHY */ + spinlock_t sbm_lock; /* spin lock */ + struct net_device_stats sbm_stats; + int sbm_devflags; /* current device flags */ - unsigned char sbm_phys[2]; + int sbm_buffersize; /* * Controller-specific things */ - volatile void __iomem *sbm_base; /* MAC's base address */ - sbmac_state_t sbm_state; /* current state */ + volatile void __iomem *sbm_base; /* MAC's base address */ + sbmac_state_t sbm_state; /* current state */ volatile void __iomem *sbm_macenable; /* MAC Enable Register */ - volatile void __iomem *sbm_maccfg; /* MAC Configuration Register */ - volatile void __iomem *sbm_fifocfg; /* FIFO configuration register */ - volatile void __iomem *sbm_framecfg; /* Frame configuration register */ - volatile void __iomem *sbm_rxfilter; /* receive filter register */ - volatile void __iomem *sbm_isr; /* Interrupt status register */ - volatile void __iomem *sbm_imr; /* Interrupt mask register */ - volatile void __iomem *sbm_mdio; /* MDIO register */ - - sbmac_speed_t sbm_speed; /* current speed */ - sbmac_duplex_t sbm_duplex; /* current duplex */ - sbmac_fc_t sbm_fc; /* current flow control setting */ - - unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; - - sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ - sbmacdma_t sbm_rxdma; - int rx_hw_checksum; - int sbe_idx; + volatile void __iomem *sbm_maccfg; /* MAC Config Register */ + volatile void __iomem *sbm_fifocfg; /* FIFO Config Register */ + volatile void __iomem *sbm_framecfg; /* Frame Config Register */ + volatile void __iomem *sbm_rxfilter; /* Receive Filter Register */ + volatile void __iomem *sbm_isr; /* Interrupt Status Register */ + volatile void __iomem *sbm_imr; /* Interrupt Mask Register */ + volatile void __iomem *sbm_mdio; /* MDIO Register */ + + + sbmac_speed_t sbm_speed; /* current speed */ + sbmac_duplex_t sbm_duplex; /* current duplex */ + sbmac_fc_t sbm_fc; /* cur. flow control setting */ + int sbm_pause; /* current pause setting */ + int sbm_link; /* current link state */ + + unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; + + sbmacdma_t sbm_txdma; /* only channel 0 for now */ + sbmacdma_t sbm_rxdma; + int rx_hw_checksum; + int sbe_idx; }; @@ -297,32 +311,36 @@ static uint64_t sbmac_addr2reg(unsigned static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs); static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); static void sbmac_setmulti(struct sbmac_softc *sc); -static int sbmac_init(struct net_device *dev, int idx); +static int sbmac_init(struct platform_device *pldev, long long base); static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed); static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc); static int sbmac_open(struct net_device *dev); -static void sbmac_timer(unsigned long data); static void sbmac_tx_timeout (struct net_device *dev); static struct net_device_stats *sbmac_get_stats(struct net_device *dev); static void sbmac_set_rx_mode(struct net_device *dev); static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +static void sbmac_phy_disconnect(void *data); static int sbmac_close(struct net_device *dev); -static int sbmac_mii_poll(struct sbmac_softc *s,int noisy); +static void sbmac_mii_poll(struct net_device *dev); static int sbmac_mii_probe(struct net_device *dev); -static void sbmac_mii_sync(struct sbmac_softc *s); -static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt); -static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx); -static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx, - unsigned int regval); +static void sbmac_mii_sync(volatile void __iomem *sbm_mdio); +static void sbmac_mii_senddata(volatile void __iomem *sbm_mdio, + unsigned int data, int bitcnt); +static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx); +static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, + u16 val); /********************************************************************** * Globals ********************************************************************* */ -static uint64_t sbmac_orig_hwaddr[MAX_UNITS]; +static char sbmac_string[] = "sb1250-mac"; +static char sbmac_pretty[] = "SB1250 MAC"; + +static char sbmac_mdio_string[] = "sb1250-mac-mdio"; /********************************************************************** @@ -334,185 +352,66 @@ static uint64_t sbmac_orig_hwaddr[MAX_UN #define MII_COMMAND_WRITE 0x01 #define MII_COMMAND_ACK 0x02 -#define BMCR_RESET 0x8000 -#define BMCR_LOOPBACK 0x4000 -#define BMCR_SPEED0 0x2000 -#define BMCR_ANENABLE 0x1000 -#define BMCR_POWERDOWN 0x0800 -#define BMCR_ISOLATE 0x0400 -#define BMCR_RESTARTAN 0x0200 -#define BMCR_DUPLEX 0x0100 -#define BMCR_COLTEST 0x0080 -#define BMCR_SPEED1 0x0040 -#define BMCR_SPEED1000 BMCR_SPEED1 -#define BMCR_SPEED100 BMCR_SPEED0 -#define BMCR_SPEED10 0 - -#define BMSR_100BT4 0x8000 -#define BMSR_100BT_FDX 0x4000 -#define BMSR_100BT_HDX 0x2000 -#define BMSR_10BT_FDX 0x1000 -#define BMSR_10BT_HDX 0x0800 -#define BMSR_100BT2_FDX 0x0400 -#define BMSR_100BT2_HDX 0x0200 -#define BMSR_1000BT_XSR 0x0100 -#define BMSR_PRESUP 0x0040 -#define BMSR_ANCOMPLT 0x0020 -#define BMSR_REMFAULT 0x0010 -#define BMSR_AUTONEG 0x0008 -#define BMSR_LINKSTAT 0x0004 -#define BMSR_JABDETECT 0x0002 -#define BMSR_EXTCAPAB 0x0001 - -#define PHYIDR1 0x2000 -#define PHYIDR2 0x5C60 - -#define ANAR_NP 0x8000 -#define ANAR_RF 0x2000 -#define ANAR_ASYPAUSE 0x0800 -#define ANAR_PAUSE 0x0400 -#define ANAR_T4 0x0200 -#define ANAR_TXFD 0x0100 -#define ANAR_TXHD 0x0080 -#define ANAR_10FD 0x0040 -#define ANAR_10HD 0x0020 -#define ANAR_PSB 0x0001 - -#define ANLPAR_NP 0x8000 -#define ANLPAR_ACK 0x4000 -#define ANLPAR_RF 0x2000 -#define ANLPAR_ASYPAUSE 0x0800 -#define ANLPAR_PAUSE 0x0400 -#define ANLPAR_T4 0x0200 -#define ANLPAR_TXFD 0x0100 -#define ANLPAR_TXHD 0x0080 -#define ANLPAR_10FD 0x0040 -#define ANLPAR_10HD 0x0020 -#define ANLPAR_PSB 0x0001 /* 802.3 */ - -#define ANER_PDF 0x0010 -#define ANER_LPNPABLE 0x0008 -#define ANER_NPABLE 0x0004 -#define ANER_PAGERX 0x0002 -#define ANER_LPANABLE 0x0001 - -#define ANNPTR_NP 0x8000 -#define ANNPTR_MP 0x2000 -#define ANNPTR_ACK2 0x1000 -#define ANNPTR_TOGTX 0x0800 -#define ANNPTR_CODE 0x0008 - -#define ANNPRR_NP 0x8000 -#define ANNPRR_MP 0x2000 -#define ANNPRR_ACK3 0x1000 -#define ANNPRR_TOGTX 0x0800 -#define ANNPRR_CODE 0x0008 - -#define K1TCR_TESTMODE 0x0000 -#define K1TCR_MSMCE 0x1000 -#define K1TCR_MSCV 0x0800 -#define K1TCR_RPTR 0x0400 -#define K1TCR_1000BT_FDX 0x200 -#define K1TCR_1000BT_HDX 0x100 - -#define K1STSR_MSMCFLT 0x8000 -#define K1STSR_MSCFGRES 0x4000 -#define K1STSR_LRSTAT 0x2000 -#define K1STSR_RRSTAT 0x1000 -#define K1STSR_LP1KFD 0x0800 -#define K1STSR_LP1KHD 0x0400 -#define K1STSR_LPASMDIR 0x0200 - -#define K1SCR_1KX_FDX 0x8000 -#define K1SCR_1KX_HDX 0x4000 -#define K1SCR_1KT_FDX 0x2000 -#define K1SCR_1KT_HDX 0x1000 - -#define STRAP_PHY1 0x0800 -#define STRAP_NCMODE 0x0400 -#define STRAP_MANMSCFG 0x0200 -#define STRAP_ANENABLE 0x0100 -#define STRAP_MSVAL 0x0080 -#define STRAP_1KHDXADV 0x0010 -#define STRAP_1KFDXADV 0x0008 -#define STRAP_100ADV 0x0004 -#define STRAP_SPEEDSEL 0x0000 -#define STRAP_SPEED100 0x0001 - -#define PHYSUP_SPEED1000 0x10 -#define PHYSUP_SPEED100 0x08 -#define PHYSUP_SPEED10 0x00 -#define PHYSUP_LINKUP 0x04 -#define PHYSUP_FDX 0x02 - -#define MII_BMCR 0x00 /* Basic mode control register (rw) */ -#define MII_BMSR 0x01 /* Basic mode status register (ro) */ -#define MII_PHYIDR1 0x02 -#define MII_PHYIDR2 0x03 - -#define MII_K1STSR 0x0A /* 1K Status Register (ro) */ -#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ - - #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ #define ENABLE 1 #define DISABLE 0 /********************************************************************** - * SBMAC_MII_SYNC(s) + * SBMAC_MII_SYNC(sbm_mdio) * * Synchronize with the MII - send a pattern of bits to the MII * that will guarantee that it is ready to accept a command. * * Input parameters: - * s - sbmac structure + * sbm_mdio - address of the MAC's MDIO register * * Return value: * nothing ********************************************************************* */ -static void sbmac_mii_sync(struct sbmac_softc *s) +static void sbmac_mii_sync(volatile void __iomem *sbm_mdio) { int cnt; uint64_t bits; int mac_mdio_genc; - mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; + mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; - __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(bits | mac_mdio_genc, sbm_mdio); for (cnt = 0; cnt < 32; cnt++) { - __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); + __raw_writeq(bits | mac_mdio_genc, sbm_mdio); } } /********************************************************************** - * SBMAC_MII_SENDDATA(s,data,bitcnt) + * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt) * * Send some bits to the MII. The bits to be sent are right- * justified in the 'data' parameter. * * Input parameters: - * s - sbmac structure - * data - data to send - * bitcnt - number of bits to send + * sbm_mdio - address of the MAC's MDIO register + * data - data to send + * bitcnt - number of bits to send ********************************************************************* */ -static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt) +static void sbmac_mii_senddata(volatile void __iomem *sbm_mdio, + unsigned int data, int bitcnt) { int i; uint64_t bits; unsigned int curmask; int mac_mdio_genc; - mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; + mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; bits = M_MAC_MDIO_DIR_OUTPUT; - __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(bits | mac_mdio_genc, sbm_mdio); curmask = 1 << (bitcnt - 1); @@ -520,9 +419,9 @@ static void sbmac_mii_senddata(struct sb if (data & curmask) bits |= M_MAC_MDIO_OUT; else bits &= ~M_MAC_MDIO_OUT; - __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(bits | mac_mdio_genc, sbm_mdio); + __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); + __raw_writeq(bits | mac_mdio_genc, sbm_mdio); curmask >>= 1; } } @@ -530,21 +429,22 @@ static void sbmac_mii_senddata(struct sb /********************************************************************** - * SBMAC_MII_READ(s,phyaddr,regidx) - * + * SBMAC_MII_READ(bus, phyaddr, regidx) * Read a PHY register. * * Input parameters: - * s - sbmac structure + * bus - MDIO bus handle * phyaddr - PHY's address - * regidx = index of register to read + * regnum - index of register to read * * Return value: - * value read, or 0 if an error occurred. + * value read, or 0xffff if an error occurred. ********************************************************************* */ -static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx) +static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx) { + struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; + volatile void __iomem *sbm_mdio = sc->sbm_mdio; int idx; int error; int regval; @@ -554,8 +454,7 @@ static unsigned int sbmac_mii_read(struc * Synchronize ourselves so that the PHY knows the next * thing coming down is a command */ - - sbmac_mii_sync(s); + sbmac_mii_sync(sbm_mdio); /* * Send the data to the PHY. The sequence is @@ -564,37 +463,37 @@ static unsigned int sbmac_mii_read(struc * the PHY addr (5 bits) * the register index (5 bits) */ + sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); + sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2); + sbmac_mii_senddata(sbm_mdio, phyaddr, 5); + sbmac_mii_senddata(sbm_mdio, regidx, 5); - sbmac_mii_senddata(s,MII_COMMAND_START, 2); - sbmac_mii_senddata(s,MII_COMMAND_READ, 2); - sbmac_mii_senddata(s,phyaddr, 5); - sbmac_mii_senddata(s,regidx, 5); - - mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; + mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; /* * Switch the port around without a clock transition. */ - __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); /* * Send out a clock pulse to signal we want the status */ - - __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, + sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); /* * If an error occurred, the PHY will signal '1' back */ - error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN; + error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN; /* * Issue an 'idle' clock pulse, but keep the direction * the same. */ - __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, + sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); regval = 0; @@ -602,55 +501,60 @@ static unsigned int sbmac_mii_read(struc regval <<= 1; if (error == 0) { - if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN) + if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN) regval |= 1; } - __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); - __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, + sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); } /* Switch back to output */ - __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio); + __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); if (error == 0) return regval; - return 0; + return 0xffff; } /********************************************************************** - * SBMAC_MII_WRITE(s,phyaddr,regidx,regval) + * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval) * * Write a value to a PHY register. * * Input parameters: - * s - sbmac structure + * bus - MDIO bus handle * phyaddr - PHY to use - * regidx - register within the PHY - * regval - data to write to register + * regidx - register within the PHY + * regval - data to write to register * * Return value: - * nothing + * 0 for success ********************************************************************* */ -static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx, - unsigned int regval) +static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, + u16 regval) { + struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; + volatile void __iomem *sbm_mdio = sc->sbm_mdio; int mac_mdio_genc; - sbmac_mii_sync(s); + sbmac_mii_sync(sbm_mdio); + + sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); + sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2); + sbmac_mii_senddata(sbm_mdio, phyaddr, 5); + sbmac_mii_senddata(sbm_mdio, regidx, 5); + sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2); + sbmac_mii_senddata(sbm_mdio, regval, 16); - sbmac_mii_senddata(s,MII_COMMAND_START,2); - sbmac_mii_senddata(s,MII_COMMAND_WRITE,2); - sbmac_mii_senddata(s,phyaddr, 5); - sbmac_mii_senddata(s,regidx, 5); - sbmac_mii_senddata(s,MII_COMMAND_ACK,2); - sbmac_mii_senddata(s,regval,16); + mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; - mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; + __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); - __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio); + return 0; } @@ -692,27 +596,27 @@ static void sbdma_initctx(sbmacdma_t *d, s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; #endif - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR))); - __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR))); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR); + __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR); /* * initialize register pointers @@ -927,7 +831,7 @@ static int sbdma_add_rcvbuffer(sbmacdma_ if (sb == NULL) { sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN); if (sb_new == NULL) { - printk(KERN_INFO "%s: sk_buff allocation failed\n", + pr_info("%s: sk_buff allocation failed\n", d->sbdma_eth->sbm_dev->name); return -ENOBUFS; } @@ -1379,14 +1283,6 @@ static int sbmac_initctx(struct sbmac_so s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; s->sbm_mdio = s->sbm_base + R_MAC_MDIO; - s->sbm_phys[0] = 1; - s->sbm_phys[1] = 0; - - s->sbm_phy_oldbmsr = 0; - s->sbm_phy_oldanlpar = 0; - s->sbm_phy_oldk1stsr = 0; - s->sbm_phy_oldlinkstat = 0; - /* * Initialize the DMA channels. Right now, only one per MAC is used * Note: Only do this _once_, as it allocates memory from the kernel! @@ -1401,14 +1297,6 @@ static int sbmac_initctx(struct sbmac_so s->sbm_state = sbmac_state_off; - /* - * Initial speed is (XXX TEMP) 10MBit/s HDX no FC - */ - - s->sbm_speed = sbmac_speed_10; - s->sbm_duplex = sbmac_duplex_half; - s->sbm_fc = sbmac_fc_disabled; - return 0; } @@ -1921,8 +1809,6 @@ static int sbmac_set_speed(struct sbmac_ cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; break; - case sbmac_speed_auto: /* XXX not implemented */ - /* fall through */ default: return 0; } @@ -1995,8 +1881,6 @@ static int sbmac_set_duplex(struct sbmac cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; break; - case sbmac_fc_auto: /* XXX not implemented */ - /* fall through */ case sbmac_fc_frame: /* not valid in half duplex */ default: /* invalid selection */ return 0; @@ -2015,15 +1899,12 @@ static int sbmac_set_duplex(struct sbmac case sbmac_fc_collision: /* not valid in full duplex */ case sbmac_fc_carrier: /* not valid in full duplex */ - case sbmac_fc_auto: /* XXX not implemented */ - /* fall through */ default: return 0; } break; - case sbmac_duplex_auto: - /* XXX not implemented */ - break; + default: + return 0; } /* @@ -2322,7 +2203,7 @@ static int sb1250_change_mtu(struct net_ if (new_mtu > ENET_PACKET_SIZE) return -EINVAL; _dev->mtu = new_mtu; - printk(KERN_INFO "changing the mtu to %d\n", new_mtu); + pr_info("changing the mtu to %d\n", new_mtu); return 0; } @@ -2338,19 +2219,16 @@ static int sb1250_change_mtu(struct net_ * status ********************************************************************* */ -static int sbmac_init(struct net_device *dev, int idx) +static int sbmac_init(struct platform_device *pldev, long long base) { - struct sbmac_softc *sc; + struct net_device *dev = pldev->dev.driver_data; + int idx = pldev->id; + struct sbmac_softc *sc = netdev_priv(dev); unsigned char *eaddr; uint64_t ea_reg; int i; int err; - sc = netdev_priv(dev); - - /* Determine controller base address */ - - sc->sbm_base = IOADDR(dev->base_addr); sc->sbm_dev = dev; sc->sbe_idx = idx; @@ -2403,45 +2281,57 @@ static int sbmac_init(struct net_device dev->change_mtu = sb1250_change_mtu; + dev->irq = UNIT_INT(idx); + /* This is needed for PASS2 for Rx H/W checksum feature */ sbmac_set_iphdr_offset(sc); err = register_netdev(dev); - if (err) - goto out_uninit; - - if (sc->rx_hw_checksum == ENABLE) { - printk(KERN_INFO "%s: enabling TCP rcv checksum\n", - sc->sbm_dev->name); + if (err) { + printk(KERN_ERR "%s.%d: unable to register netdev\n", + sbmac_string, idx); + sbmac_uninitctx(sc); + return err; } + pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name); + + if (sc->rx_hw_checksum == ENABLE) + pr_info("%s: enabling TCP rcv checksum\n", dev->name); + /* * Display Ethernet address (this is called during the config * process so we need to finish off the config message that * was being displayed) */ - printk(KERN_INFO - "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n", - dev->name, dev->base_addr, - eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]); + pr_info("%s: SiByte Ethernet at 0x%08Lx, " + "address: %02X:%02X:%02X:%02X:%02X:%02X\n", + dev->name, base, + eaddr[0], eaddr[1], eaddr[2], eaddr[3], eaddr[4], eaddr[5]); + + sc->mii_bus.name = sbmac_mdio_string; + sc->mii_bus.id = idx; + sc->mii_bus.priv = sc; + sc->mii_bus.read = sbmac_mii_read; + sc->mii_bus.write = sbmac_mii_write; + sc->mii_bus.irq = sc->phy_irq; + for (i = 0; i < PHY_MAX_ADDR; ++i) + sc->mii_bus.irq[i] = SBMAC_PHY_INT; + sc->mii_bus.dev = &pldev->dev; + dev_set_drvdata(&pldev->dev, &sc->mii_bus); return 0; - -out_uninit: - sbmac_uninitctx(sc); - - return err; } static int sbmac_open(struct net_device *dev) { struct sbmac_softc *sc = netdev_priv(dev); + int err; - if (debug > 1) { - printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq); - } + if (debug > 1) + pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq); /* * map/route interrupt (clear status first, in case something @@ -2450,224 +2340,177 @@ static int sbmac_open(struct net_device */ __raw_readq(sc->sbm_isr); - if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev)) - return -EBUSY; + err = request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev); + if (err) { + printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name, + dev->irq); + goto out_err; + } /* - * Probe phy address + * Sanity check whether a possible previous call + * to sbmac_close() has fully concluded. */ - - if(sbmac_mii_probe(dev) == -1) { - printk("%s: failed to probe PHY.\n", dev->name); - return -EINVAL; + if (sc->phy_dev) { + printk(KERN_ERR "%s: PHY still in use\n", dev->name); + return -EBUSY; } /* - * Configure default speed + * Probe PHY address */ + err = mdiobus_register(&sc->mii_bus); + if (err) { + printk(KERN_ERR "%s: unable to register MDIO bus\n", + dev->name); + goto out_unirq; + } - sbmac_mii_poll(sc,noisy_mii); + sc->sbm_speed = sbmac_speed_none; + sc->sbm_duplex = sbmac_duplex_none; + sc->sbm_fc = sbmac_fc_none; + sc->sbm_pause = -1; + sc->sbm_link = 0; /* - * Turn on the channel + * Attach to the PHY */ - - sbmac_set_channel_state(sc,sbmac_state_on); + err = sbmac_mii_probe(dev); + if (err) + goto out_unregister; /* - * XXX Station address is in dev->dev_addr + * Turn on the channel */ - if (dev->if_port == 0) - dev->if_port = 0; + sbmac_set_channel_state(sc,sbmac_state_on); netif_start_queue(dev); sbmac_set_rx_mode(dev); - /* Set the timer to check for link beat. */ - init_timer(&sc->sbm_timer); - sc->sbm_timer.expires = jiffies + 2 * HZ/100; - sc->sbm_timer.data = (unsigned long)dev; - sc->sbm_timer.function = &sbmac_timer; - add_timer(&sc->sbm_timer); + phy_start(sc->phy_dev); return 0; + +out_unregister: + mdiobus_unregister(&sc->mii_bus); + +out_unirq: + free_irq(dev->irq, dev); + +out_err: + return err; } static int sbmac_mii_probe(struct net_device *dev) { + struct sbmac_softc *sc = netdev_priv(dev); + struct phy_device *phy_dev; int i; - struct sbmac_softc *s = netdev_priv(dev); - u16 bmsr, id1, id2; - u32 vendor, device; - - for (i=1; i<31; i++) { - bmsr = sbmac_mii_read(s, i, MII_BMSR); - if (bmsr != 0) { - s->sbm_phys[0] = i; - id1 = sbmac_mii_read(s, i, MII_PHYIDR1); - id2 = sbmac_mii_read(s, i, MII_PHYIDR2); - vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f); - device = (id2 >> 4) & 0x3f; - - printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n", - dev->name, i, vendor, device); - return i; - } - } - return -1; -} + INIT_WORK(&sc->sbm_queue, sbmac_phy_disconnect, sc); -static int sbmac_mii_poll(struct sbmac_softc *s,int noisy) -{ - int bmsr,bmcr,k1stsr,anlpar; - int chg; - char buffer[100]; - char *p = buffer; - - /* Read the mode status and mode control registers. */ - bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR); - bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR); - - /* get the link partner status */ - anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR); - - /* if supported, read the 1000baseT register */ - if (bmsr & BMSR_1000BT_XSR) { - k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR); - } - else { - k1stsr = 0; + for (i = 0; i < PHY_MAX_ADDR; i++) { + phy_dev = sc->mii_bus.phy_map[i]; + if (phy_dev) + break; } + if (!phy_dev) { + printk(KERN_ERR "%s: no PHY found\n", dev->name); + return -ENXIO; + } + + phy_dev = phy_connect(dev, phy_dev->dev.bus_id, &sbmac_mii_poll, 0); + if (IS_ERR(phy_dev)) { + printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); + return PTR_ERR(phy_dev); + } + + /* Remove any features not supported by the controller */ + phy_dev->supported &= SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full | + SUPPORTED_Autoneg | + SUPPORTED_MII | + SUPPORTED_Pause | + SUPPORTED_Asym_Pause; + phy_dev->advertising = phy_dev->supported; + + pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", + dev->name, phy_dev->drv->name, + phy_dev->dev.bus_id, phy_dev->irq); - chg = 0; + sc->phy_dev = phy_dev; - if ((bmsr & BMSR_LINKSTAT) == 0) { - /* - * If link status is down, clear out old info so that when - * it comes back up it will force us to reconfigure speed - */ - s->sbm_phy_oldbmsr = 0; - s->sbm_phy_oldanlpar = 0; - s->sbm_phy_oldk1stsr = 0; return 0; - } - - if ((s->sbm_phy_oldbmsr != bmsr) || - (s->sbm_phy_oldanlpar != anlpar) || - (s->sbm_phy_oldk1stsr != k1stsr)) { - if (debug > 1) { - printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n", - s->sbm_dev->name, - s->sbm_phy_oldbmsr,bmsr, - s->sbm_phy_oldanlpar,anlpar, - s->sbm_phy_oldk1stsr,k1stsr); - } - s->sbm_phy_oldbmsr = bmsr; - s->sbm_phy_oldanlpar = anlpar; - s->sbm_phy_oldk1stsr = k1stsr; - chg = 1; - } - - if (chg == 0) - return 0; - - p += sprintf(p,"Link speed: "); - - if (k1stsr & K1STSR_LP1KFD) { - s->sbm_speed = sbmac_speed_1000; - s->sbm_duplex = sbmac_duplex_full; - s->sbm_fc = sbmac_fc_frame; - p += sprintf(p,"1000BaseT FDX"); - } - else if (k1stsr & K1STSR_LP1KHD) { - s->sbm_speed = sbmac_speed_1000; - s->sbm_duplex = sbmac_duplex_half; - s->sbm_fc = sbmac_fc_disabled; - p += sprintf(p,"1000BaseT HDX"); - } - else if (anlpar & ANLPAR_TXFD) { - s->sbm_speed = sbmac_speed_100; - s->sbm_duplex = sbmac_duplex_full; - s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled; - p += sprintf(p,"100BaseT FDX"); - } - else if (anlpar & ANLPAR_TXHD) { - s->sbm_speed = sbmac_speed_100; - s->sbm_duplex = sbmac_duplex_half; - s->sbm_fc = sbmac_fc_disabled; - p += sprintf(p,"100BaseT HDX"); - } - else if (anlpar & ANLPAR_10FD) { - s->sbm_speed = sbmac_speed_10; - s->sbm_duplex = sbmac_duplex_full; - s->sbm_fc = sbmac_fc_frame; - p += sprintf(p,"10BaseT FDX"); - } - else if (anlpar & ANLPAR_10HD) { - s->sbm_speed = sbmac_speed_10; - s->sbm_duplex = sbmac_duplex_half; - s->sbm_fc = sbmac_fc_collision; - p += sprintf(p,"10BaseT HDX"); - } - else { - p += sprintf(p,"Unknown"); - } - - if (noisy) { - printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer); - } - - return 1; } -static void sbmac_timer(unsigned long data) +static void sbmac_mii_poll(struct net_device *dev) { - struct net_device *dev = (struct net_device *)data; struct sbmac_softc *sc = netdev_priv(dev); - int next_tick = HZ; - int mii_status; - - spin_lock_irq (&sc->sbm_lock); - - /* make IFF_RUNNING follow the MII status bit "Link established" */ - mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR); + struct phy_device *phy_dev = sc->phy_dev; + unsigned long flags; + sbmac_fc_t fc; + int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg; - if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) { - sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT; - if (mii_status & BMSR_LINKSTAT) { - netif_carrier_on(dev); - } - else { - netif_carrier_off(dev); + link_chg = (sc->sbm_link != phy_dev->link); + speed_chg = (sc->sbm_speed != phy_dev->speed); + duplex_chg = (sc->sbm_duplex != phy_dev->duplex); + pause_chg = (sc->sbm_pause != phy_dev->pause); + + if (!link_chg && !speed_chg && !duplex_chg && !pause_chg) + return; /* Hmmm... */ + + if (!phy_dev->link) { + if (link_chg) { + sc->sbm_link = phy_dev->link; + sc->sbm_speed = sbmac_speed_none; + sc->sbm_duplex = sbmac_duplex_none; + sc->sbm_fc = sbmac_fc_disabled; + sc->sbm_pause = -1; + pr_info("%s: link unavailable\n", dev->name); } + return; } - /* - * Poll the PHY to see what speed we should be running at - */ + if (phy_dev->duplex == DUPLEX_FULL) { + if (phy_dev->pause) + fc = sbmac_fc_frame; + else + fc = sbmac_fc_disabled; + } else + fc = sbmac_fc_collision; + fc_chg = (sc->sbm_fc != fc); - if (sbmac_mii_poll(sc,noisy_mii)) { - if (sc->sbm_state != sbmac_state_off) { - /* - * something changed, restart the channel - */ - if (debug > 1) { - printk("%s: restarting channel because speed changed\n", - sc->sbm_dev->name); - } - sbmac_channel_stop(sc); - sbmac_channel_start(sc); - } - } + pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed, + phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H'); - spin_unlock_irq (&sc->sbm_lock); + spin_lock_irqsave(&sc->sbm_lock, flags); + + sc->sbm_speed = phy_dev->speed; + sc->sbm_duplex = phy_dev->duplex; + sc->sbm_fc = fc; + sc->sbm_pause = phy_dev->pause; + sc->sbm_link = phy_dev->link; - sc->sbm_timer.expires = jiffies + next_tick; - add_timer(&sc->sbm_timer); + if ((speed_chg || duplex_chg || fc_chg) && + sc->sbm_state != sbmac_state_off) { + /* + * something changed, restart the channel + */ + if (debug > 1) + pr_debug("%s: restarting channel " + "because PHY state changed\n", dev->name); + sbmac_channel_stop(sc); + sbmac_channel_start(sc); + } + + spin_unlock_irqrestore(&sc->sbm_lock, flags); } @@ -2745,62 +2588,39 @@ static void sbmac_set_rx_mode(struct net static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { struct sbmac_softc *sc = netdev_priv(dev); - u16 *data = (u16 *)&rq->ifr_ifru; - unsigned long flags; - int retval; - spin_lock_irqsave(&sc->sbm_lock, flags); - retval = 0; + if (!netif_running(dev) || !sc->phy_dev) + return -EINVAL; - switch(cmd) { - case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */ - data[0] = sc->sbm_phys[0] & 0x1f; - /* Fall Through */ - case SIOCDEVPRIVATE+1: /* Read the specified MII register. */ - data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f); - break; - case SIOCDEVPRIVATE+2: /* Write the specified MII register */ - if (!capable(CAP_NET_ADMIN)) { - retval = -EPERM; - break; - } - if (debug > 1) { - printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name, - data[0],data[1],data[2]); - } - sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]); - break; - default: - retval = -EOPNOTSUPP; - } + return phy_mii_ioctl(sc->phy_dev, if_mii(rq), cmd); +} - spin_unlock_irqrestore(&sc->sbm_lock, flags); - return retval; +static void sbmac_phy_disconnect(void *data) +{ + struct sbmac_softc *sc = data; + + phy_disconnect(sc->phy_dev); + mdiobus_unregister(&sc->mii_bus); + sc->phy_dev = NULL; } static int sbmac_close(struct net_device *dev) { struct sbmac_softc *sc = netdev_priv(dev); - unsigned long flags; - int irq; - sbmac_set_channel_state(sc,sbmac_state_off); + phy_stop(sc->phy_dev); - del_timer_sync(&sc->sbm_timer); - - spin_lock_irqsave(&sc->sbm_lock, flags); + sbmac_set_channel_state(sc, sbmac_state_off); netif_stop_queue(dev); - if (debug > 1) { - printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name); - } + if (debug > 1) + pr_debug("%s: Shutting down ethercard\n",dev->name); - spin_unlock_irqrestore(&sc->sbm_lock, flags); + /* Cannot call phy_disconnect() here because of rtnl_lock(). */ + schedule_work(&sc->sbm_queue); - irq = dev->irq; - synchronize_irq(irq); - free_irq(irq, dev); + free_irq(dev->irq, dev); sbdma_emptyring(&(sc->sbm_txdma)); sbdma_emptyring(&(sc->sbm_rxdma)); @@ -2809,55 +2629,195 @@ static int sbmac_close(struct net_device } +static int __init sbmac_probe(struct platform_device *pldev) +{ + struct net_device *dev; + struct sbmac_softc *sc; + volatile void __iomem *sbm_base; + struct resource *res; + u64 sbmac_orig_hwaddr; + int err; + + res = platform_get_resource(pldev, IORESOURCE_MEM, 0); + BUG_ON(!res); + sbm_base = ioremap_nocache(res->start, res->end - res->start + 1); + if (!sbm_base) { + printk(KERN_ERR "%s: unable to map device registers\n", + pldev->dev.bus_id); + err = -ENOMEM; + goto out_out; + } + + /* + * The R_MAC_ETHERNET_ADDR register will be set to some nonzero + * value for us by the firmware if we're going to use this MAC. + * If we find a zero, skip this MAC. + */ + sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR); + pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", pldev->dev.bus_id, + sbmac_orig_hwaddr ? "" : "not ", (long long)res->start); + if (sbmac_orig_hwaddr == 0) { + err = 0; + goto out_unmap; + } + + /* + * Okay, cool. Initialize this MAC. + */ + dev = alloc_etherdev(sizeof(struct sbmac_softc)); + if (!dev) { + printk(KERN_ERR "%s: unable to allocate etherdev\n", + pldev->dev.bus_id); + err = -ENOMEM; + goto out_unmap; + } + + pldev->dev.driver_data = dev; + SET_NETDEV_DEV(dev, &pldev->dev); + + sc = netdev_priv(dev); + sc->sbm_base = sbm_base; + + err = sbmac_init(pldev, res->start); + if (err) + goto out_kfree; + + return 0; + +out_kfree: + free_netdev(dev); + __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR); + +out_unmap: + iounmap(sbm_base); + +out_out: + return err; +} + +static int __exit sbmac_remove(struct platform_device *pldev) +{ + struct net_device *dev = pldev->dev.driver_data; + struct sbmac_softc *sc = netdev_priv(dev); + + unregister_netdev(dev); + flush_scheduled_work(); /* Finish any pending work. */ + sbmac_uninitctx(sc); + iounmap(sc->sbm_base); + free_netdev(dev); + + return 0; +} + + +static struct platform_device **sbmac_pldev; +static int sbmac_max_units __initdata; #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR) -static void -sbmac_setup_hwaddr(int chan,char *addr) +static void sbmac_setup_hwaddr(int idx, char *addr) { + volatile void __iomem *sbm_base; + unsigned long start, end; uint8_t eaddr[6]; uint64_t val; - unsigned long port; - port = A_MAC_CHANNEL_BASE(chan); - sbmac_parse_hwaddr(addr,eaddr); + if (idx >= sbmac_max_units) + return; + + start = A_MAC_CHANNEL_BASE(idx); + end = A_MAC_CHANNEL_BASE(idx + 1) - 1; + + sbm_base = ioremap_nocache(start, end - start + 1); + if (!sbm_base) { + printk(KERN_ERR "%s: unable to map device registers\n", + sbmac_string); + return + } + + sbmac_parse_hwaddr(addr, eaddr); val = sbmac_addr2reg(eaddr); - __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR)); - val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR)); + __raw_writeq(val, sbm_base + R_MAC_ETHERNET_ADDR); + val = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR); + + iounmap(sbm_base); } #endif -static struct net_device *dev_sbmac[MAX_UNITS]; +static int __init sbmac_platform_probe_one(int idx) +{ + struct platform_device *pldev; + struct { + struct resource r; + char name[strlen(sbmac_pretty) + 4]; + } *res; + int err; + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) { + printk(KERN_ERR "%s.%d: unable to allocate memory\n", + sbmac_string, idx); + err = -ENOMEM; + goto out_err; + } + + /* + * This is the base address of the MAC. + */ + snprintf(res->name, sizeof(res->name), "%s %d", sbmac_pretty, idx); + res->r.name = res->name; + res->r.flags = IORESOURCE_MEM; + res->r.start = A_MAC_CHANNEL_BASE(idx); + res->r.end = A_MAC_CHANNEL_BASE(idx + 1) - 1; + + pldev = platform_device_register_simple(sbmac_string, idx, &res->r, 1); + if (IS_ERR(pldev)) { + printk(KERN_ERR "%s.%d: unable to register platform device\n", + sbmac_string, idx); + err = PTR_ERR(pldev); + goto out_kfree; + } + + if (!pldev->dev.driver) { + err = 0; /* No hardware at this address. */ + goto out_unregister; + } + + sbmac_pldev[idx] = pldev; + return 0; + +out_unregister: + platform_device_unregister(pldev); + +out_kfree: + kfree(res); + +out_err: + return err; +} -static int __init -sbmac_init_module(void) +static void __init sbmac_platform_probe(void) { - int idx; - struct net_device *dev; - unsigned long port; - int chip_max_units; + int i; /* Set the number of available units based on the SOC type. */ switch (soc_type) { case K_SYS_SOC_TYPE_BCM1250: case K_SYS_SOC_TYPE_BCM1250_ALT: - chip_max_units = 3; + sbmac_max_units = 3; break; case K_SYS_SOC_TYPE_BCM1120: case K_SYS_SOC_TYPE_BCM1125: case K_SYS_SOC_TYPE_BCM1125H: - case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ - chip_max_units = 2; + case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ + sbmac_max_units = 2; break; case K_SYS_SOC_TYPE_BCM1x55: case K_SYS_SOC_TYPE_BCM1x80: - chip_max_units = 4; + sbmac_max_units = 4; break; default: - chip_max_units = 0; - break; + return; /* none */ } - if (chip_max_units > MAX_UNITS) - chip_max_units = MAX_UNITS; /* * For bringup when not using the firmware, we can pre-fill @@ -2865,89 +2825,70 @@ sbmac_init_module(void) * specified in this file (or maybe from the config file?) */ #ifdef SBMAC_ETH0_HWADDR - if (chip_max_units > 0) - sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR); + sbmac_setup_hwaddr(0, SBMAC_ETH0_HWADDR); #endif #ifdef SBMAC_ETH1_HWADDR - if (chip_max_units > 1) - sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR); + sbmac_setup_hwaddr(1, SBMAC_ETH1_HWADDR); #endif #ifdef SBMAC_ETH2_HWADDR - if (chip_max_units > 2) - sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR); + sbmac_setup_hwaddr(2, SBMAC_ETH2_HWADDR); #endif #ifdef SBMAC_ETH3_HWADDR - if (chip_max_units > 3) - sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR); + sbmac_setup_hwaddr(3, SBMAC_ETH3_HWADDR); #endif + sbmac_pldev = kzalloc(sbmac_max_units * sizeof(*sbmac_pldev), + GFP_KERNEL); + if (!sbmac_pldev) { + printk(KERN_ERR "%s: unable to allocate memory\n", + sbmac_string); + return; + } + /* * Walk through the Ethernet controllers and find * those who have their MAC addresses set. */ - for (idx = 0; idx < chip_max_units; idx++) { + for (i = 0; i < sbmac_max_units; i++) + if (sbmac_platform_probe_one(i)) + break; +} - /* - * This is the base address of the MAC. - */ - port = A_MAC_CHANNEL_BASE(idx); +static void __exit sbmac_platform_cleanup(void) +{ + int i; - /* - * The R_MAC_ETHERNET_ADDR register will be set to some nonzero - * value for us by the firmware if we're going to use this MAC. - * If we find a zero, skip this MAC. - */ + for (i = 0; i < sbmac_max_units; i++) + platform_device_unregister(sbmac_pldev[i]); +} - sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR)); - if (sbmac_orig_hwaddr[idx] == 0) { - printk(KERN_DEBUG "sbmac: not configuring MAC at " - "%lx\n", port); - continue; - } - /* - * Okay, cool. Initialize this MAC. - */ +static struct platform_driver sbmac_driver = { + .probe = sbmac_probe, + .remove = __exit_p(sbmac_remove), + .driver = { + .name = sbmac_string, + }, +}; - dev = alloc_etherdev(sizeof(struct sbmac_softc)); - if (!dev) - return -ENOMEM; /* return ENOMEM */ - - printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port); - - dev->irq = UNIT_INT(idx); - dev->base_addr = port; - dev->mem_end = 0; - if (sbmac_init(dev, idx)) { - port = A_MAC_CHANNEL_BASE(idx); - __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR)); - free_netdev(dev); - continue; - } - dev_sbmac[idx] = dev; - } - return 0; -} +static int __init sbmac_init_module(void) +{ + int err; + err = platform_driver_register(&sbmac_driver); + if (err) + return err; -static void __exit -sbmac_cleanup_module(void) -{ - struct net_device *dev; - int idx; + sbmac_platform_probe(); - for (idx = 0; idx < MAX_UNITS; idx++) { - struct sbmac_softc *sc; - dev = dev_sbmac[idx]; - if (!dev) - continue; + return err; +} - sc = netdev_priv(dev); - unregister_netdev(dev); - sbmac_uninitctx(sc); - free_netdev(dev); - } +static void __exit sbmac_cleanup_module(void) +{ + sbmac_platform_cleanup(); + platform_driver_unregister(&sbmac_driver); } module_init(sbmac_init_module); From macro@linux-mips.org Thu Oct 5 17:28:57 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 17:29:02 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:35594 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20039276AbWJEQ25 (ORCPT ); Thu, 5 Oct 2006 17:28:57 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 4D4FBF667B; Thu, 5 Oct 2006 18:28:46 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DBxunX22KgjY; Thu, 5 Oct 2006 18:28:45 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id CE043F661D; Thu, 5 Oct 2006 18:28:45 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k95GSuml005135; Thu, 5 Oct 2006 18:28:56 +0200 Date: Thu, 5 Oct 2006 17:28:50 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton , Jeff Garzik , Ralf Baechle cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: [PATCH 2.6.18 7/6]: sb1250-mac: Remove "typedef" obfuscation Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1997/Wed Oct 4 17:20:43 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12809 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 17209 Lines: 483 This is a set of changes to remove unneeded type definitions that only make code less obvious. It applies to all "enum" and "struct" types as well as to potentially unsafe use of them within sizeof(). Signed-off-by: Maciej W. Rozycki --- This applies on top of 4/6. Please consider. Maciej patch-mips-2.6.18-20060920-sb1250-mac-typedef-3 diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/drivers/net/sb1250-mac.c linux-mips-2.6.18-20060920/drivers/net/sb1250-mac.c --- linux-mips-2.6.18-20060920.macro/drivers/net/sb1250-mac.c 2006-09-28 02:51:29.000000000 +0000 +++ linux-mips-2.6.18-20060920/drivers/net/sb1250-mac.c 2006-10-05 16:18:41.000000000 +0000 @@ -129,33 +129,33 @@ MODULE_PARM_DESC(int_timeout, "Timeout v * Simple types ********************************************************************* */ -typedef enum { +enum sbmac_speed { sbmac_speed_none = 0, sbmac_speed_10 = SPEED_10, sbmac_speed_100 = SPEED_100, sbmac_speed_1000 = SPEED_1000, -} sbmac_speed_t; +}; -typedef enum { +enum sbmac_duplex { sbmac_duplex_none = -1, sbmac_duplex_half = DUPLEX_HALF, sbmac_duplex_full = DUPLEX_FULL, -} sbmac_duplex_t; +}; -typedef enum { +enum sbmac_fc { sbmac_fc_none, sbmac_fc_disabled, sbmac_fc_frame, sbmac_fc_collision, sbmac_fc_carrier, -} sbmac_fc_t; +}; -typedef enum { +enum sbmac_state { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, sbmac_state_broken, -} sbmac_state_t; +}; /********************************************************************** @@ -181,52 +181,58 @@ typedef enum { * DMA Descriptor structure ********************************************************************* */ -typedef struct sbdmadscr_s { +struct sbdmadscr { uint64_t dscr_a; uint64_t dscr_b; -} sbdmadscr_t; - -typedef unsigned long paddr_t; +}; /********************************************************************** * DMA Controller structure ********************************************************************* */ -typedef struct sbmacdma_s { +struct sbmacdma { /* * This stuff is used to identify the channel and the registers * associated with it. */ - - struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ - int sbdma_channel; /* channel number */ - int sbdma_txdir; /* direction (1=transmit) */ - int sbdma_maxdescr; /* total # of descriptors in ring */ + struct sbmac_softc *sbdma_eth; /* back pointer to associated + MAC */ + int sbdma_channel; /* channel number */ + int sbdma_txdir; /* direction (1=transmit) */ + int sbdma_maxdescr; /* total # of descriptors + in ring */ #ifdef CONFIG_SBMAC_COALESCE - int sbdma_int_pktcnt; /* # descriptors rx/tx before interrupt*/ - int sbdma_int_timeout; /* # usec rx/tx interrupt */ + int sbdma_int_pktcnt; + /* # descriptors rx/tx + before interrupt */ + int sbdma_int_timeout; + /* # usec rx/tx interrupt */ #endif - - volatile void __iomem *sbdma_config0; /* DMA config register 0 */ - volatile void __iomem *sbdma_config1; /* DMA config register 1 */ - volatile void __iomem *sbdma_dscrbase; /* Descriptor base address */ - volatile void __iomem *sbdma_dscrcnt; /* Descriptor count register */ - volatile void __iomem *sbdma_curdscr; /* current descriptor address */ + volatile void __iomem *sbdma_config0; /* DMA config register 0 */ + volatile void __iomem *sbdma_config1; /* DMA config register 1 */ + volatile void __iomem *sbdma_dscrbase; + /* descriptor base address */ + volatile void __iomem *sbdma_dscrcnt; /* descriptor count register */ + volatile void __iomem *sbdma_curdscr; /* current descriptor + address */ /* * This stuff is for maintenance of the ring */ - - sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */ - sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */ - - struct sk_buff **sbdma_ctxtable; /* context table, one per descr */ - - paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ - sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ - sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ -} sbmacdma_t; + struct sbdmadscr *sbdma_dscrtable; + /* base of descriptor table */ + struct sbdmadscr *sbdma_dscrtable_end; + /* end of descriptor table */ + struct sk_buff **sbdma_ctxtable; + /* context table, one + per descr */ + dma_addr_t sbdma_dscrtable_phys; + /* and also the phys addr */ + struct sbdmadscr *sbdma_addptr; /* next dscr for sw to add */ + struct sbdmadscr *sbdma_remptr; /* next dscr for sw + to remove */ +}; /********************************************************************** @@ -238,7 +244,6 @@ struct sbmac_softc { /* * Linux-specific things */ - struct net_device *sbm_dev; /* pointer to linux device */ struct phy_device *phy_dev; /* the associated PHY device */ struct mii_bus mii_bus; /* the MII bus */ @@ -253,9 +258,8 @@ struct sbmac_softc { /* * Controller-specific things */ - volatile void __iomem *sbm_base; /* MAC's base address */ - sbmac_state_t sbm_state; /* current state */ + enum sbmac_state sbm_state; /* current state */ volatile void __iomem *sbm_macenable; /* MAC Enable Register */ volatile void __iomem *sbm_maccfg; /* MAC Config Register */ @@ -267,16 +271,16 @@ struct sbmac_softc { volatile void __iomem *sbm_mdio; /* MDIO Register */ - sbmac_speed_t sbm_speed; /* current speed */ - sbmac_duplex_t sbm_duplex; /* current duplex */ - sbmac_fc_t sbm_fc; /* cur. flow control setting */ + enum sbmac_speed sbm_speed; /* current speed */ + enum sbmac_duplex sbm_duplex; /* current duplex */ + enum sbmac_fc sbm_fc; /* cur. flow control setting */ int sbm_pause; /* current pause setting */ int sbm_link; /* current link state */ unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; - sbmacdma_t sbm_txdma; /* only channel 0 for now */ - sbmacdma_t sbm_rxdma; + struct sbmacdma sbm_txdma; /* only channel 0 for now */ + struct sbmacdma sbm_rxdma; int rx_hw_checksum; int sbe_idx; }; @@ -290,30 +294,30 @@ struct sbmac_softc { * Prototypes ********************************************************************* */ -static void sbdma_initctx(sbmacdma_t *d, - struct sbmac_softc *s, - int chan, - int txrx, - int maxdescr); -static void sbdma_channel_start(sbmacdma_t *d, int rxtx); -static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m); -static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m); -static void sbdma_emptyring(sbmacdma_t *d); -static void sbdma_fillring(sbmacdma_t *d); -static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d); -static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d); +static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, + int txrx, int maxdescr); +static void sbdma_channel_start(struct sbmacdma *d, int rxtx); +static int sbdma_add_rcvbuffer(struct sbmacdma *d, struct sk_buff *m); +static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m); +static void sbdma_emptyring(struct sbmacdma *d); +static void sbdma_fillring(struct sbmacdma *d); +static void sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d); +static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d); static int sbmac_initctx(struct sbmac_softc *s); static void sbmac_channel_start(struct sbmac_softc *s); static void sbmac_channel_stop(struct sbmac_softc *s); -static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t); -static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff); +static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *, + enum sbmac_state); +static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); static uint64_t sbmac_addr2reg(unsigned char *ptr); -static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs); +static irqreturn_t sbmac_intr(int irq, void *dev_instance, + struct pt_regs *rgs); static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); static void sbmac_setmulti(struct sbmac_softc *sc); static int sbmac_init(struct platform_device *pldev, long long base); -static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed); -static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc); +static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed); +static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, + enum sbmac_fc fc); static int sbmac_open(struct net_device *dev); static void sbmac_tx_timeout (struct net_device *dev); @@ -567,8 +571,8 @@ static int sbmac_mii_write(struct mii_bu * way. * * Input parameters: - * d - sbmacdma_t structure (DMA channel context) - * s - sbmac_softc structure (pointer to a MAC) + * d - struct sbmacdma (DMA channel context) + * s - struct sbmac_softc (pointer to a MAC) * chan - channel number (0..1 right now) * txrx - Identifies DMA_TX or DMA_RX for channel direction * maxdescr - number of descriptors @@ -577,11 +581,8 @@ static int sbmac_mii_write(struct mii_bu * nothing ********************************************************************* */ -static void sbdma_initctx(sbmacdma_t *d, - struct sbmac_softc *s, - int chan, - int txrx, - int maxdescr) +static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, + int txrx, int maxdescr) { /* * Save away interesting stuff in the structure @@ -639,17 +640,19 @@ static void sbdma_initctx(sbmacdma_t *d, d->sbdma_maxdescr = maxdescr; - d->sbdma_dscrtable = (sbdmadscr_t *) - kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL); + d->sbdma_dscrtable = kmalloc((d->sbdma_maxdescr + 1) * + sizeof(*d->sbdma_dscrtable), GFP_KERNEL); /* * The descriptor table must be aligned to at least 16 bytes or the * MAC will corrupt it. */ - d->sbdma_dscrtable = (sbdmadscr_t *) - ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t)); + d->sbdma_dscrtable = (struct sbdmadscr *) + ALIGN((unsigned long)d->sbdma_dscrtable, + sizeof(*d->sbdma_dscrtable)); - memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t)); + memset(d->sbdma_dscrtable, 0, + d->sbdma_maxdescr * sizeof(*d->sbdma_dscrtable)); d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; @@ -659,10 +662,11 @@ static void sbdma_initctx(sbmacdma_t *d, * And context table */ - d->sbdma_ctxtable = (struct sk_buff **) - kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL); + d->sbdma_ctxtable = kmalloc(d->sbdma_maxdescr * + sizeof(*d->sbdma_ctxtable), GFP_KERNEL); - memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *)); + memset(d->sbdma_ctxtable, 0, + d->sbdma_maxdescr * sizeof(*d->sbdma_ctxtable)); #ifdef CONFIG_SBMAC_COALESCE /* @@ -697,7 +701,7 @@ static void sbdma_initctx(sbmacdma_t *d, * nothing ********************************************************************* */ -static void sbdma_channel_start(sbmacdma_t *d, int rxtx ) +static void sbdma_channel_start(struct sbmacdma *d, int rxtx) { /* * Turn on the DMA channel @@ -738,7 +742,7 @@ static void sbdma_channel_start(sbmacdma * nothing ********************************************************************* */ -static void sbdma_channel_stop(sbmacdma_t *d) +static void sbdma_channel_stop(struct sbmacdma *d) { /* * Turn off the DMA channel @@ -787,10 +791,10 @@ static void sbdma_align_skb(struct sk_bu ********************************************************************* */ -static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb) +static int sbdma_add_rcvbuffer(struct sbmacdma *d, struct sk_buff *sb) { - sbdmadscr_t *dsc; - sbdmadscr_t *nextdsc; + struct sbdmadscr *dsc; + struct sbdmadscr *nextdsc; struct sk_buff *sb_new = NULL; int pktsize = ENET_PACKET_SIZE; @@ -905,10 +909,10 @@ static int sbdma_add_rcvbuffer(sbmacdma_ ********************************************************************* */ -static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb) +static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb) { - sbdmadscr_t *dsc; - sbdmadscr_t *nextdsc; + struct sbdmadscr *dsc; + struct sbdmadscr *nextdsc; uint64_t phys; uint64_t ncb; int length; @@ -994,7 +998,7 @@ static int sbdma_add_txbuffer(sbmacdma_t * nothing ********************************************************************* */ -static void sbdma_emptyring(sbmacdma_t *d) +static void sbdma_emptyring(struct sbmacdma *d) { int idx; struct sk_buff *sb; @@ -1022,7 +1026,7 @@ static void sbdma_emptyring(sbmacdma_t * * nothing ********************************************************************* */ -static void sbdma_fillring(sbmacdma_t *d) +static void sbdma_fillring(struct sbmacdma *d) { int idx; @@ -1049,11 +1053,11 @@ static void sbdma_fillring(sbmacdma_t *d * nothing ********************************************************************* */ -static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d) +static void sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d) { int curidx; int hwidx; - sbdmadscr_t *dsc; + struct sbdmadscr *dsc; struct sk_buff *sb; int len; @@ -1070,8 +1074,9 @@ static void sbdma_rx_process(struct sbma */ curidx = d->sbdma_remptr - d->sbdma_dscrtable; - hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - - d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); + hwidx = ((__raw_readq(d->sbdma_curdscr) & + M_DMA_CURDSCR_ADDR) - d->sbdma_dscrtable_phys) / + sizeof(*d->sbdma_dscrtable); /* * If they're the same, that means we've processed all @@ -1174,11 +1179,11 @@ static void sbdma_rx_process(struct sbma * nothing ********************************************************************* */ -static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d) +static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d) { int curidx; int hwidx; - sbdmadscr_t *dsc; + struct sbdmadscr *dsc; struct sk_buff *sb; unsigned long flags; @@ -1197,8 +1202,9 @@ static void sbdma_tx_process(struct sbma */ curidx = d->sbdma_remptr - d->sbdma_dscrtable; - hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - - d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); + hwidx = ((__raw_readq(d->sbdma_curdscr) & + M_DMA_CURDSCR_ADDR) - d->sbdma_dscrtable_phys) / + sizeof(*d->sbdma_dscrtable); /* * If they're the same, that means we've processed all @@ -1301,7 +1307,7 @@ static int sbmac_initctx(struct sbmac_so } -static void sbdma_uninitctx(struct sbmacdma_s *d) +static void sbdma_uninitctx(struct sbmacdma *d) { if (d->sbdma_dscrtable) { kfree(d->sbdma_dscrtable); @@ -1606,10 +1612,10 @@ static void sbmac_channel_stop(struct sb * Return value: * old state ********************************************************************* */ -static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc, - sbmac_state_t state) +static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc, + enum sbmac_state state) { - sbmac_state_t oldstate = sc->sbm_state; + enum sbmac_state oldstate = sc->sbm_state; /* * If same as previous state, return @@ -1744,14 +1750,14 @@ static uint64_t sbmac_addr2reg(unsigned * * Input parameters: * s - sbmac structure - * speed - speed to set MAC to (see sbmac_speed_t enum) + * speed - speed to set MAC to (see enum sbmac_speed) * * Return value: * 1 if successful * 0 indicates invalid parameters ********************************************************************* */ -static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed) +static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed) { uint64_t cfg; uint64_t framecfg; @@ -1831,15 +1837,16 @@ static int sbmac_set_speed(struct sbmac_ * * Input parameters: * s - sbmac structure - * duplex - duplex setting (see sbmac_duplex_t) - * fc - flow control setting (see sbmac_fc_t) + * duplex - duplex setting (see enum sbmac_duplex) + * fc - flow control setting (see enum sbmac_fc) * * Return value: * 1 if ok * 0 if an invalid parameter combination was specified ********************************************************************* */ -static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc) +static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, + enum sbmac_fc fc) { uint64_t cfg; @@ -2455,7 +2462,7 @@ static void sbmac_mii_poll(struct net_de struct sbmac_softc *sc = netdev_priv(dev); struct phy_device *phy_dev = sc->phy_dev; unsigned long flags; - sbmac_fc_t fc; + enum sbmac_fc fc; int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg; link_chg = (sc->sbm_link != phy_dev->link); From macro@linux-mips.org Thu Oct 5 17:34:36 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Oct 2006 17:34:42 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:24331 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20039276AbWJEQeg (ORCPT ); Thu, 5 Oct 2006 17:34:36 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id A79A8F5FDD; Thu, 5 Oct 2006 18:34:22 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id s-qvGSfezdBL; Thu, 5 Oct 2006 18:34:22 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 433ABF5B22; Thu, 5 Oct 2006 18:34:22 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k95GYWsF007564; Thu, 5 Oct 2006 18:34:32 +0200 Date: Thu, 5 Oct 2006 17:34:27 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton , Jeff Garzik , Ralf Baechle cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: [PATCH 2.6.18 8/6]: sb1250-mac: Fix an incorrect use of kfree() Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1997/Wed Oct 4 17:20:43 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12810 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 2074 Lines: 58 The pointer obtained by kmalloc() is treated with ALIGN() before passing it to kfree(). This may or may not cause problems depending on the minimum alignment enforced by kmalloc() and is ugly anyway. This change records the original pointer returned by kmalloc() so that kfree() may safely use it. Signed-off-by: Maciej W. Rozycki --- This applies on top of the "typedef" change (7/6). Please consider. Maciej patch-mips-2.6.18-20060920-sb1250-mac-kfree-0 diff -up --recursive --new-file linux-mips-2.6.18-20060920.macro/drivers/net/sb1250-mac.c linux-mips-2.6.18-20060920/drivers/net/sb1250-mac.c --- linux-mips-2.6.18-20060920.macro/drivers/net/sb1250-mac.c 2006-10-05 16:18:41.000000000 +0000 +++ linux-mips-2.6.18-20060920/drivers/net/sb1250-mac.c 2006-10-04 23:07:27.000000000 +0000 @@ -220,6 +220,7 @@ struct sbmacdma { /* * This stuff is for maintenance of the ring */ + void *sbdma_dscrtable_un; struct sbdmadscr *sbdma_dscrtable; /* base of descriptor table */ struct sbdmadscr *sbdma_dscrtable_end; @@ -640,15 +641,16 @@ static void sbdma_initctx(struct sbmacdm d->sbdma_maxdescr = maxdescr; - d->sbdma_dscrtable = kmalloc((d->sbdma_maxdescr + 1) * - sizeof(*d->sbdma_dscrtable), GFP_KERNEL); + d->sbdma_dscrtable_un = kmalloc((d->sbdma_maxdescr + 1) * + sizeof(*d->sbdma_dscrtable), + GFP_KERNEL); /* * The descriptor table must be aligned to at least 16 bytes or the * MAC will corrupt it. */ d->sbdma_dscrtable = (struct sbdmadscr *) - ALIGN((unsigned long)d->sbdma_dscrtable, + ALIGN((unsigned long)d->sbdma_dscrtable_un, sizeof(*d->sbdma_dscrtable)); memset(d->sbdma_dscrtable, 0, @@ -1309,9 +1311,9 @@ static int sbmac_initctx(struct sbmac_so static void sbdma_uninitctx(struct sbmacdma *d) { - if (d->sbdma_dscrtable) { - kfree(d->sbdma_dscrtable); - d->sbdma_dscrtable = NULL; + if (d->sbdma_dscrtable_un) { + kfree(d->sbdma_dscrtable_un); + d->sbdma_dscrtable = d->sbdma_dscrtable_un = NULL; } if (d->sbdma_ctxtable) { From akpm@osdl.org Fri Oct 6 07:43:22 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 07:43:23 +0100 (BST) Received: from smtp.osdl.org ([65.172.181.4]:48056 "EHLO smtp.osdl.org") by ftp.linux-mips.org with ESMTP id S20038416AbWJFGnW (ORCPT ); Fri, 6 Oct 2006 07:43:22 +0100 Received: from shell0.pdx.osdl.net (fw.osdl.org [65.172.181.6]) by smtp.osdl.org (8.12.8/8.12.8) with ESMTP id k966hBaX011229 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Thu, 5 Oct 2006 23:43:12 -0700 Received: from box (shell0.pdx.osdl.net [10.9.0.31]) by shell0.pdx.osdl.net (8.13.1/8.11.6) with SMTP id k966hA1G020591; Thu, 5 Oct 2006 23:43:11 -0700 Date: Thu, 5 Oct 2006 23:43:10 -0700 From: Andrew Morton To: "Maciej W. Rozycki" Cc: Jeff Garzik , Ralf Baechle , Andy Fleming , netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [patch 3/6] 2.6.18: sb1250-mac: Phylib IRQ handling fixes Message-Id: <20061005234310.6c8042b5.akpm@osdl.org> In-Reply-To: References: X-Mailer: Sylpheed version 2.2.7 (GTK+ 2.8.17; x86_64-unknown-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: osdl$Revision: 1.155 $ X-Scanned-By: MIMEDefang 2.36 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12811 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@osdl.org Precedence: bulk X-list: linux-mips Content-Length: 1139 Lines: 35 On Tue, 3 Oct 2006 16:18:35 +0100 (BST) "Maciej W. Rozycki" wrote: > > 2. The driver uses schedule_work() for handling interrupts, but does not > make sure any pending work scheduled thus has been completed before > driver's structures get freed from memory. This is especially > important as interrupts may keep arriving if the line is shared with > another PHY. > > The solution is to ignore phy_interrupt() calls if the reported device > has already been halted and calling flush_scheduled_work() from > phy_stop_interrupts() (but guarded with current_is_keventd() in case > the function has been called through keventd from the MAC device's > close call to avoid a deadlock on the netlink lock). > eww, hack. Also not module-friendly: WARNING: "current_is_keventd" [drivers/net/phy/libphy.ko] undefined! Does this static void flush_cpu_workqueue(struct cpu_workqueue_struct *cwq) { if (cwq->thread == current) { /* * Probably keventd trying to flush its own queue. So simply run * it by hand rather than deadlocking. */ run_workqueue(cwq); not work??? From vagabon.xyz@gmail.com Fri Oct 6 12:06:53 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 12:06:59 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.188]:40862 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20039011AbWJFLGx (ORCPT ); Fri, 6 Oct 2006 12:06:53 +0100 Received: by nf-out-0910.google.com with SMTP id l23so1132415nfc for ; Fri, 06 Oct 2006 04:06:51 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:reply-to:user-agent:mime-version:to:subject:content-type:content-transfer-encoding:from; b=RSFxg7tNBFQtJyNi8lb76QsjdBUd6PQgBgLq29/SrVg//js1dvVah6IpTPE3CAtXfsnfX65fhLU0wB2KYBjnexY200R0Qc0jxA/OKRN92dVow3hR0lzGCOPCrGxb7M6hEWjHXGfZJjpi5LT5KuZaXXe9Lchi9cgIsNzC1y6xUuY= Received: by 10.49.8.15 with SMTP id l15mr5281300nfi; Fri, 06 Oct 2006 04:06:51 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.google.com with ESMTP id k23sm2587202nfc.2006.10.06.04.06.51; Fri, 06 Oct 2006 04:06:51 -0700 (PDT) Message-ID: <4526390D.7070009@innova-card.com> Date: Fri, 06 Oct 2006 13:07:57 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: Ralf Baechle , linux-mips@linux-mips.org Subject: [PATCH] Use kallsyms_lookup_size_offset() instead of kallsyms_lookup() Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12812 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1429 Lines: 48 From: Franck Bui-Huu This new routine doesn't lookup symbol names. So we needn't to pass any char buffers or pointer since we don't care about names. Signed-off-by: Franck Bui-Huu --- arch/mips/kernel/process.c | 8 ++------ 1 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 045d987..cace1ba 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -358,10 +358,8 @@ static int __init frame_info_init(void) unsigned long size = 0; #ifdef CONFIG_KALLSYMS unsigned long ofs; - char *modname; - char namebuf[KSYM_NAME_LEN + 1]; - kallsyms_lookup((unsigned long)schedule, &size, &ofs, &modname, namebuf); + kallsyms_lookup_size_offset((unsigned long)schedule, &size, &ofs); #endif schedule_mfi.func = schedule; schedule_mfi.func_size = size; @@ -403,8 +401,6 @@ unsigned long unwind_stack(struct task_s { unsigned long stack_page; struct mips_frame_info info; - char *modname; - char namebuf[KSYM_NAME_LEN + 1]; unsigned long size, ofs; int leaf; extern void ret_from_irq(void); @@ -433,7 +429,7 @@ unsigned long unwind_stack(struct task_s } return 0; } - if (!kallsyms_lookup(pc, &size, &ofs, &modname, namebuf)) + if (!kallsyms_lookup_size_offset(pc, &size, &ofs)) return 0; /* * Return ra if an exception occured at the first instruction -- 1.4.2.3 From macro@linux-mips.org Fri Oct 6 12:26:46 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 12:26:52 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:5900 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20039021AbWJFL0q (ORCPT ); Fri, 6 Oct 2006 12:26:46 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 25875F59DD; Fri, 6 Oct 2006 13:26:21 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZMVGRJZ+l6Ie; Fri, 6 Oct 2006 13:26:20 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id ADA48E1C66; Fri, 6 Oct 2006 13:26:20 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k96BQPVc016697; Fri, 6 Oct 2006 13:26:25 +0200 Date: Fri, 6 Oct 2006 12:26:22 +0100 (BST) From: "Maciej W. Rozycki" To: Andrew Morton cc: Jeff Garzik , Ralf Baechle , Andy Fleming , netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [patch 3/6] 2.6.18: sb1250-mac: Phylib IRQ handling fixes In-Reply-To: <20061005234310.6c8042b5.akpm@osdl.org> Message-ID: References: <20061005234310.6c8042b5.akpm@osdl.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1999/Thu Oct 5 19:35:38 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12813 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 2086 Lines: 55 On Thu, 5 Oct 2006, Andrew Morton wrote: > > 2. The driver uses schedule_work() for handling interrupts, but does not > > make sure any pending work scheduled thus has been completed before > > driver's structures get freed from memory. This is especially > > important as interrupts may keep arriving if the line is shared with > > another PHY. > > > > The solution is to ignore phy_interrupt() calls if the reported device > > has already been halted and calling flush_scheduled_work() from > > phy_stop_interrupts() (but guarded with current_is_keventd() in case > > the function has been called through keventd from the MAC device's > > close call to avoid a deadlock on the netlink lock). > > > > eww, hack. > > Also not module-friendly: > > WARNING: "current_is_keventd" [drivers/net/phy/libphy.ko] undefined! > > Does this > > static void flush_cpu_workqueue(struct cpu_workqueue_struct *cwq) > { > if (cwq->thread == current) { > /* > * Probably keventd trying to flush its own queue. So simply run > * it by hand rather than deadlocking. > */ > run_workqueue(cwq); > > not work??? It does, too well even! -- in the case I am trying to take care of we are run with "rtnl_mutex" held as a result of rtnl_lock() called from unregister_netdev() and there is some work already in the workqueue (linkwatch_event(), apparently) wanting to acquire the same lock. Hence a deadlock. It seems problematic elsewhere as well -- see tg3.c -- but a different way to deal with it has been found there. I am not that fond of this solution, but at least it works, unlike calling flush_scheduled_work() here, which deadlocks the current CPU in my system instantly. Any suggestions as to how to do this differently? Perhaps linkwatch_event() should be scheduled differently (using a separate workqueue?)... Or does dev_close() have to be called under this lock from unregister_netdevice()? Perhaps code like this would do: while (dev->flags & IFF_UP) { rtnl_unlock(); dev_close(dev); rtnl_lock(); } Maciej From creideiki+linux-mips@ferretporn.se Fri Oct 6 13:33:49 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 13:33:54 +0100 (BST) Received: from pne-smtpout1-sn2.hy.skanova.net ([81.228.8.83]:46591 "EHLO pne-smtpout1-sn2.hy.skanova.net") by ftp.linux-mips.org with ESMTP id S20037810AbWJFMdt (ORCPT ); Fri, 6 Oct 2006 13:33:49 +0100 Received: from mail.ferretporn.se (83.250.8.219) by pne-smtpout1-sn2.hy.skanova.net (7.2.075) id 4516FC4100327629 for linux-mips@linux-mips.org; Fri, 6 Oct 2006 14:33:44 +0200 Received: from www.ferretporn.se (unknown [192.168.0.3]) by mail.ferretporn.se (Postfix) with ESMTP id 7399CCADC for ; Fri, 6 Oct 2006 14:33:43 +0200 (CEST) Received: from 136.163.203.3 (SquirrelMail authenticated user creideiki) by www.ferretporn.se with HTTP; Fri, 6 Oct 2006 14:33:43 +0200 (CEST) Message-ID: <34353.136.163.203.3.1160138023.squirrel@www.ferretporn.se> Date: Fri, 6 Oct 2006 14:33:43 +0200 (CEST) Subject: /proc/cpuinfo makes false assumptions of uniformity on IP27 From: "Karl-Johan Karlsson" To: linux-mips@linux-mips.org User-Agent: SquirrelMail/1.4.8 MIME-Version: 1.0 Content-Type: text/plain;charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Priority: 3 (Normal) Importance: Normal Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12814 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: creideiki+linux-mips@ferretporn.se Precedence: bulk X-list: linux-mips Content-Length: 1264 Lines: 33 The code in arch/mips/kernel/proc.c:show_cpuinfo() for showing /proc/cpuinfo makes the assumption that all CPU:s are equal, and show NR_CPUS copies of the information for whatever CPU we happen to be running on. This leads to confusing output on SGI Origin 2000, since it can have CPU:s of different types. Here's a sample of what it looks like on my Origin 2000 with 16 R12000 and 16 R10000 CPU:s: creideiki@viggen ~ $ for i in `seq 0 2`; do echo -n "$i: "; grep ^cpu < /proc/cpuinfo | uniq; done 0: cpu model : R12000 V2.3 FPU V0.0 1: cpu model : R10000 V3.4 FPU V0.0 2: cpu model : R12000 V2.3 FPU V0.0 The obvious fix would be to change "current_cpu_data" to "cpu_data[n]" in arch/mips/kernel/proc.c:show_cpuinfo(), but two things remain: 0. I haven't actually tried it yet, since the only Origin 2000 I have is in production. I should be able to reboot to a patched kernel sometime during this weekend. 1. What about the CPU feature test macros in include/asm-mips/cpu-features.h? They claim /* * SMP assumption: Options of CPU 0 are a superset of all processors. * This is true for all known MIPS systems. */ but is that really true, even on a mixed R12k/R10k system? -- Karl-Johan Karlsson From vagabon.xyz@gmail.com Fri Oct 6 14:35:45 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 14:35:50 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.190]:65078 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20039042AbWJFNfp (ORCPT ); Fri, 6 Oct 2006 14:35:45 +0100 Received: by nf-out-0910.google.com with SMTP id l23so1172375nfc for ; Fri, 06 Oct 2006 06:35:44 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:reply-to:user-agent:mime-version:to:cc:subject:content-type:content-transfer-encoding:from; b=PUvzbMO2DBl/JUa7hfo3xhNZhiGRA7+Ybjbrr6CCezfpgPZP6scjW2ByiO6Ept6Wrh4g3dKoV4zHaWPlf2x29GJ7lOjdqInxUFnIWSrrwNmDfMBblPbmPvn+dosI3ZVW6gefS1I9QVMeS4M1QiEh7X8kWG851Dc92LVwf7ha+J8= Received: by 10.49.8.1 with SMTP id l1mr5483971nfi; Fri, 06 Oct 2006 06:35:44 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.google.com with ESMTP id l38sm3589587nfc.2006.10.06.06.35.43; Fri, 06 Oct 2006 06:35:43 -0700 (PDT) Message-ID: <45265BF0.8080103@innova-card.com> Date: Fri, 06 Oct 2006 15:36:48 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org Subject: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12815 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 2782 Lines: 80 From: Franck Bui-Huu This patch introduces __pa_symbol() macro which should be used to calculate the physical address of kernel symbols. We should fix any linker issues in this macro, if any, but more importantly __pa_symbol() uses __pa() to do the real conversion. One resulting thing is that we can see that most of CPHYSADDR() uses weren't needed. It also rely on RELOC_HIDE() to avoid any compiler's oddities when doing arithmetics on symbols. Signed-off-by: Franck Bui-Huu --- arch/mips/kernel/setup.c | 17 ++++++++++------- include/asm-mips/page.h | 1 + 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index fdbb508..cccccd5 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -204,12 +204,12 @@ static void __init finalize_initrd(void) printk(KERN_INFO "Initrd not found or empty"); goto disable; } - if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { + if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) { printk("Initrd extends beyond end of memory"); goto disable; } - reserve_bootmem(CPHYSADDR(initrd_start), size); + reserve_bootmem(__pa(initrd_start), size); initrd_below_start_ok = 1; printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", @@ -256,7 +256,10 @@ static void __init bootmem_init(void) * of usable memory. */ reserved_end = init_initrd(); - reserved_end = PFN_UP(CPHYSADDR(max(reserved_end, (unsigned long)&_end))); + if (reserved_end > (unsigned long)&_end) + reserved_end = PFN_UP(__pa(reserved_end)); + else + reserved_end = PFN_UP(__pa_symbol(&_end)); /* * Find the highest page frame number we have available. @@ -428,10 +431,10 @@ static void __init resource_init(void) if (UNCAC_BASE != IO_BASE) return; - code_resource.start = virt_to_phys(&_text); - code_resource.end = virt_to_phys(&_etext) - 1; - data_resource.start = virt_to_phys(&_etext); - data_resource.end = virt_to_phys(&_edata) - 1; + code_resource.start = __pa_symbol(&_text); + code_resource.end = __pa_symbol(&_etext) - 1; + data_resource.start = __pa_symbol(&_etext); + data_resource.end = __pa_symbol(&_edata) - 1; /* * Request address space for all standard RAM. diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 32e5625..1d5f4a3 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -132,6 +132,7 @@ #endif /* !__ASSEMBLY__ */ #define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) +#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) -- 1.4.2.3 From ilya@total-knowledge.com Fri Oct 6 15:34:19 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 15:34:25 +0100 (BST) Received: from alpha.total-knowledge.com ([205.217.158.170]:7828 "EHLO total-knowledge.com") by ftp.linux-mips.org with ESMTP id S20039066AbWJFOeT (ORCPT ); Fri, 6 Oct 2006 15:34:19 +0100 Received: (qmail 25494 invoked from network); 6 Oct 2006 07:34:15 -0700 Received: from unknown (HELO ?192.168.0.236?) (ilya@209.157.142.202) by alpha.total-knowledge.com with ESMTPA; 6 Oct 2006 07:34:15 -0700 Message-ID: <4526695E.5030702@total-knowledge.com> Date: Fri, 06 Oct 2006 07:34:06 -0700 From: "Ilya A. Volynets-Evenbakh" Organization: Total Knowledge User-Agent: Thunderbird 1.5.0.7 (X11/20060918) MIME-Version: 1.0 To: Karl-Johan Karlsson CC: linux-mips@linux-mips.org Subject: Re: /proc/cpuinfo makes false assumptions of uniformity on IP27 References: <34353.136.163.203.3.1160138023.squirrel@www.ferretporn.se> In-Reply-To: <34353.136.163.203.3.1160138023.squirrel@www.ferretporn.se> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12816 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ilya@total-knowledge.com Precedence: bulk X-list: linux-mips Content-Length: 483 Lines: 18 Try starting your O2K with R10K rack as primary, and you'll find out ;-) Karl-Johan Karlsson wrote: > 1. What about the CPU feature test macros in > include/asm-mips/cpu-features.h? They claim > /* > * SMP assumption: Options of CPU 0 are a superset of all processors. > * This is true for all known MIPS systems. > */ > but is that really true, even on a mixed R12k/R10k system? > > -- Ilya A. Volynets-Evenbakh Total Knowledge. CTO http://www.total-knowledge.com From akpm@osdl.org Fri Oct 6 16:03:35 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 16:03:40 +0100 (BST) Received: from smtp.osdl.org ([65.172.181.4]:3538 "EHLO smtp.osdl.org") by ftp.linux-mips.org with ESMTP id S20039463AbWJFPDf (ORCPT ); Fri, 6 Oct 2006 16:03:35 +0100 Received: from shell0.pdx.osdl.net (fw.osdl.org [65.172.181.6]) by smtp.osdl.org (8.12.8/8.12.8) with ESMTP id k96F3OaX003408 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Fri, 6 Oct 2006 08:03:25 -0700 Received: from box (shell0.pdx.osdl.net [10.9.0.31]) by shell0.pdx.osdl.net (8.13.1/8.11.6) with SMTP id k96F3NHS000397; Fri, 6 Oct 2006 08:03:24 -0700 Date: Fri, 6 Oct 2006 08:03:23 -0700 From: Andrew Morton To: "Maciej W. Rozycki" Cc: Jeff Garzik , Ralf Baechle , Andy Fleming , netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [patch 3/6] 2.6.18: sb1250-mac: Phylib IRQ handling fixes Message-Id: <20061006080323.185f2b58.akpm@osdl.org> In-Reply-To: References: <20061005234310.6c8042b5.akpm@osdl.org> X-Mailer: Sylpheed version 2.2.7 (GTK+ 2.8.17; x86_64-unknown-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: osdl$Revision: 1.155 $ X-Scanned-By: MIMEDefang 2.36 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12817 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@osdl.org Precedence: bulk X-list: linux-mips Content-Length: 2469 Lines: 67 On Fri, 6 Oct 2006 12:26:22 +0100 (BST) "Maciej W. Rozycki" wrote: > On Thu, 5 Oct 2006, Andrew Morton wrote: > > > > 2. The driver uses schedule_work() for handling interrupts, but does not > > > make sure any pending work scheduled thus has been completed before > > > driver's structures get freed from memory. This is especially > > > important as interrupts may keep arriving if the line is shared with > > > another PHY. > > > > > > The solution is to ignore phy_interrupt() calls if the reported device > > > has already been halted and calling flush_scheduled_work() from > > > phy_stop_interrupts() (but guarded with current_is_keventd() in case > > > the function has been called through keventd from the MAC device's > > > close call to avoid a deadlock on the netlink lock). > > > > > > > eww, hack. > > > > Also not module-friendly: > > > > WARNING: "current_is_keventd" [drivers/net/phy/libphy.ko] undefined! > > > > Does this > > > > static void flush_cpu_workqueue(struct cpu_workqueue_struct *cwq) > > { > > if (cwq->thread == current) { > > /* > > * Probably keventd trying to flush its own queue. So simply run > > * it by hand rather than deadlocking. > > */ > > run_workqueue(cwq); > > > > not work??? > > It does, too well even! -- in the case I am trying to take care of we are > run with "rtnl_mutex" held as a result of rtnl_lock() called from > unregister_netdev() and there is some work already in the workqueue > (linkwatch_event(), apparently) wanting to acquire the same lock. Hence a > deadlock. I don't get it. If some code does rtnl_lock(); flush_scheduled_work(); and there's some work scheduled which does rtnl_lock() then it'll deadlock. But it'll deadlock whether or not the caller of flush_scheduled_work() is keventd. Calling flush_scheduled_work() under locks is generally a bad idea. > It seems problematic elsewhere as well -- see tg3.c -- but a > different way to deal with it has been found there. > > I am not that fond of this solution, but at least it works, unlike > calling flush_scheduled_work() here, which deadlocks the current CPU in my > system instantly. Any suggestions as to how to do this differently? > Perhaps linkwatch_event() should be scheduled differently (using a > separate workqueue?)... I'd have thought that was still deadlockable. Could you describe the deadlock more completely please? From yoichi_yuasa@tripeaks.co.jp Fri Oct 6 16:35:30 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 16:35:35 +0100 (BST) Received: from mo30.po.2iij.net ([210.128.50.53]:25610 "EHLO mo30.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20039472AbWJFPfa (ORCPT ); Fri, 6 Oct 2006 16:35:30 +0100 Received: by mo.po.2iij.net (mo30) id k96FZQe9028474; Sat, 7 Oct 2006 00:35:26 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox33) id k96FZHLf031391 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sat, 7 Oct 2006 00:35:18 +0900 (JST) Date: Sat, 7 Oct 2006 00:35:16 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH] fix build errors by IRQ hander change Message-Id: <20061007003516.5eec677e.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12818 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 5531 Lines: 171 Hi Ralf, This patch has fixed build errors by the IRQ handler change. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/kernel/smtc.c mips/arch/mips/kernel/smtc.c --- mips-orig/arch/mips/kernel/smtc.c 2006-10-06 23:19:07.909029750 +0900 +++ mips/arch/mips/kernel/smtc.c 2006-10-06 23:25:16.796083750 +0900 @@ -846,7 +846,7 @@ void ipi_decode(struct pt_regs *regs, st #ifdef SMTC_IDLE_HOOK_DEBUG clock_hang_reported[dest_copy] = 0; #endif /* SMTC_IDLE_HOOK_DEBUG */ - local_timer_interrupt(0, NULL, regs); + local_timer_interrupt(0, NULL); break; case LINUX_SMP_IPI: switch ((int)arg_copy) { diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/mips-boards/generic/time.c mips/arch/mips/mips-boards/generic/time.c --- mips-orig/arch/mips/mips-boards/generic/time.c 2006-10-06 23:19:07.981034250 +0900 +++ mips/arch/mips/mips-boards/generic/time.c 2006-10-06 23:25:16.816085000 +0900 @@ -94,7 +94,7 @@ extern int null_perf_irq(struct pt_regs extern int (*perf_irq)(struct pt_regs *regs); -irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +irqreturn_t mips_timer_interrupt(int irq, void *dev_id) { int cpu = smp_processor_id(); @@ -119,7 +119,7 @@ irqreturn_t mips_timer_interrupt(int irq * perf counter overflow, or both. */ if (read_c0_cause() & (1 << 26)) - perf_irq(regs); + perf_irq(get_irq_regs()); if (read_c0_cause() & (1 << 30)) { /* If timer interrupt, make it de-assert */ @@ -139,13 +139,13 @@ irqreturn_t mips_timer_interrupt(int irq * the tick on VPE 0 to run the full timer_interrupt(). */ if (cpu_data[cpu].vpe_id == 0) { - timer_interrupt(irq, NULL, regs); + timer_interrupt(irq, NULL); smtc_timer_broadcast(cpu_data[cpu].vpe_id); scroll_display_message(); } else { write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); - local_timer_interrupt(irq, dev_id, regs); + local_timer_interrupt(irq, dev_id); smtc_timer_broadcast(cpu_data[cpu].vpe_id); } } @@ -159,12 +159,12 @@ irqreturn_t mips_timer_interrupt(int irq * timer int. */ if (!r2 || (read_c0_cause() & (1 << 26))) - if (perf_irq(regs)) + if (perf_irq(get_irq_regs())) goto out; /* we keep interrupt disabled all the time */ if (!r2 || (read_c0_cause() & (1 << 30))) - timer_interrupt(irq, NULL, regs); + timer_interrupt(irq, NULL); scroll_display_message(); } else { @@ -180,7 +180,7 @@ irqreturn_t mips_timer_interrupt(int irq /* * Other CPUs should do profiling and process accounting */ - local_timer_interrupt(irq, dev_id, regs); + local_timer_interrupt(irq, dev_id); } out: #endif /* CONFIG_MIPS_MT_SMTC */ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/mips-boards/sim/sim_time.c mips/arch/mips/mips-boards/sim/sim_time.c --- mips-orig/arch/mips/mips-boards/sim/sim_time.c 2006-10-06 23:19:07.985034500 +0900 +++ mips/arch/mips/mips-boards/sim/sim_time.c 2006-10-06 23:25:16.848087000 +0900 @@ -33,7 +33,7 @@ unsigned long cpu_khz; -irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +irqreturn_t sim_timer_interrupt(int irq, void *dev_id) { #ifdef CONFIG_SMP int cpu = smp_processor_id(); @@ -44,7 +44,7 @@ irqreturn_t sim_timer_interrupt(int irq, */ #ifndef CONFIG_MIPS_MT_SMTC if (cpu == 0) { - timer_interrupt(irq, dev_id, regs); + timer_interrupt(irq, dev_id); } else { /* Everyone else needs to reset the timer int here as @@ -84,7 +84,7 @@ irqreturn_t sim_timer_interrupt(int irq, irq_enable_hazard(); evpe(vpflags); - if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id, regs); + if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id); else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ)); smtc_timer_broadcast(cpu_data[cpu].vpe_id); @@ -93,10 +93,10 @@ irqreturn_t sim_timer_interrupt(int irq, /* * every CPU should do profiling and process accounting */ - local_timer_interrupt (irq, dev_id, regs); + local_timer_interrupt (irq, dev_id); return IRQ_HANDLED; #else - return timer_interrupt (irq, dev_id, regs); + return timer_interrupt (irq, dev_id); #endif } diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/sgi-ip27/ip27-timer.c mips/arch/mips/sgi-ip27/ip27-timer.c --- mips-orig/arch/mips/sgi-ip27/ip27-timer.c 2006-10-06 23:19:08.065039500 +0900 +++ mips/arch/mips/sgi-ip27/ip27-timer.c 2006-10-06 23:25:16.856087500 +0900 @@ -87,15 +87,11 @@ static int set_rtc_mmss(unsigned long no } #endif -static unsigned int rt_timer_irq; - -void ip27_rt_timer_interrupt(struct pt_regs *regs) +irqreturn_t ip27_rt_timer_interrupt(int irq, void *dev_id) { int cpu = smp_processor_id(); int cpuA = cputoslice(cpu) == 0; - unsigned int irq = rt_timer_irq; - irq_enter(); write_seqlock(&xtime_lock); again: @@ -111,7 +107,7 @@ again: if (cpu == 0) do_timer(1); - update_process_times(user_mode(regs)); + update_process_times(user_mode(get_irq_regs())); /* * If we have an externally synchronized Linux clock, then update @@ -131,7 +127,8 @@ again: } write_sequnlock(&xtime_lock); - irq_exit(); + + return IRQ_HANDLED; } unsigned long ip27_do_gettimeoffset(void) @@ -241,7 +238,6 @@ void __init plat_timer_setup(struct irqa /* setup irqaction */ irq_desc[irqno].status |= IRQ_PER_CPU; - rt_timer_irq = irqno; /* * Only needed to get /proc/interrupt to display timer irq stats */ From yoichi_yuasa@tripeaks.co.jp Fri Oct 6 16:55:02 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 16:55:08 +0100 (BST) Received: from mo30.po.2iij.net ([210.128.50.53]:58637 "EHLO mo30.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20039470AbWJFPzC (ORCPT ); Fri, 6 Oct 2006 16:55:02 +0100 Received: by mo.po.2iij.net (mo30) id k96Ft0Mi030615; Sat, 7 Oct 2006 00:55:00 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox33) id k96FsrRb036290 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sat, 7 Oct 2006 00:54:54 +0900 (JST) Date: Sat, 7 Oct 2006 00:54:52 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH] add "depends on BROKEN" to broken boards support Message-Id: <20061007005452.45b50d8c.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12819 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 2510 Lines: 101 Hi Ralf, This patch has added "depends on BROKEN" to broken boards support. These boards cannot build now. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Kconfig mips/arch/mips/Kconfig --- mips-orig/arch/mips/Kconfig 2006-10-05 22:29:18.893785250 +0900 +++ mips/arch/mips/Kconfig 2006-10-05 22:30:34.042481750 +0900 @@ -121,6 +121,7 @@ config MIPS_MIRAGE config BASLER_EXCITE bool "Basler eXcite smart camera support" + depends on BROKEN select DMA_COHERENT select HW_HAS_PCI select IRQ_CPU @@ -188,7 +189,7 @@ config MACH_DECSTATION config MIPS_EV64120 bool "Galileo EV64120 Evaluation board (EXPERIMENTAL)" - depends on EXPERIMENTAL + depends on BROKEN select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_GT64120 @@ -343,6 +344,7 @@ config MIPS_SIM config MOMENCO_JAGUAR_ATX bool "Momentum Jaguar board" + depends on BROKEN select BOOT_ELF32 select DMA_NONCOHERENT select HW_HAS_PCI @@ -363,6 +365,7 @@ config MOMENCO_JAGUAR_ATX config MOMENCO_OCELOT bool "Momentum Ocelot board" + depends on BROKEN select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU @@ -380,6 +383,7 @@ config MOMENCO_OCELOT config MOMENCO_OCELOT_3 bool "Momentum Ocelot-3 board" + depends on BROKEN select BOOT_ELF32 select DMA_NONCOHERENT select HW_HAS_PCI @@ -399,6 +403,7 @@ config MOMENCO_OCELOT_3 config MOMENCO_OCELOT_C bool "Momentum Ocelot-C board" + depends on BROKEN select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU @@ -416,6 +421,7 @@ config MOMENCO_OCELOT_C config MOMENCO_OCELOT_G bool "Momentum Ocelot-G board" + depends on BROKEN select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU @@ -511,6 +517,7 @@ config QEMU config MARKEINS bool "Support for NEC EMMA2RH Mark-eins" + depends on BROKEN select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU @@ -717,6 +724,7 @@ config SNI_RM200_PCI config TOSHIBA_JMR3927 bool "Toshiba JMR-TX3927 board" + depends on BROKEN select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_TX3927 @@ -728,6 +736,7 @@ config TOSHIBA_JMR3927 config TOSHIBA_RBTX4927 bool "Toshiba TBTX49[23]7 board" + depends on BROKEN select DMA_NONCOHERENT select HAS_TXX9_SERIAL select HW_HAS_PCI @@ -745,6 +754,7 @@ config TOSHIBA_RBTX4927 config TOSHIBA_RBTX4938 bool "Toshiba RBTX4938 board" + depends on BROKEN select HAVE_STD_PC_SERIAL_PORT select DMA_NONCOHERENT select GENERIC_ISA_DMA From scott.ashcroft@talk21.com Fri Oct 6 16:55:32 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 16:55:36 +0100 (BST) Received: from userbg049.dsl.pipex.com ([62.190.246.49]:46341 "EHLO homer.intra.qzxyz.com") by ftp.linux-mips.org with ESMTP id S20039474AbWJFPzC (ORCPT ); Fri, 6 Oct 2006 16:55:02 +0100 Received: from lisa.intra.qzxyz.com ([192.168.42.132]) by homer.intra.qzxyz.com with esmtp (Exim 3.36 #1 (Debian)) id 1GVs2J-0003N9-00 for ; Fri, 06 Oct 2006 16:54:55 +0100 Message-ID: <45267C4E.8090101@talk21.com> Date: Fri, 06 Oct 2006 16:54:54 +0100 From: Scott Ashcroft User-Agent: Thunderbird 1.5.0.7 (X11/20060928) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: [PATCH] Time runs too quickly on Cobalt Content-Type: multipart/mixed; boundary="------------070103080007020100050900" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12820 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: scott.ashcroft@talk21.com Precedence: bulk X-list: linux-mips Content-Length: 1177 Lines: 38 This is a multi-part message in MIME format. --------------070103080007020100050900 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit If I build a kernel with HZ==250 then time runs about 4 four times too quickly on my Cobalt RaQ2. The following patch seems to fix it but I'm not sure this is the correct thing to do. Signed-off-by: Scott Ashcroft --------------070103080007020100050900 Content-Type: text/plain; name="patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="patch" diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index c01a017..f7c6eb2 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -51,8 +51,8 @@ const char *get_system_type(void) void __init plat_timer_setup(struct irqaction *irq) { - /* Load timer value for 1KHz (TCLK is 50MHz) */ - GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS); + /* Load timer value for HZ (TCLK is 50MHz) */ + GALILEO_OUTL(50*1000*1000 / HZ, GT_TC0_OFS); /* Enable timer */ GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); --------------070103080007020100050900-- From ths@networkno.de Fri Oct 6 18:21:54 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 18:22:00 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:60884 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20039482AbWJFRVy (ORCPT ); Fri, 6 Oct 2006 18:21:54 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 3BD66455A7; Fri, 6 Oct 2006 19:21:51 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GVtOT-0006QZ-3S; Fri, 06 Oct 2006 18:21:53 +0100 Date: Fri, 6 Oct 2006 18:21:53 +0100 To: Franck Bui-Huu Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() Message-ID: <20061006172153.GB4456@networkno.de> References: <45265BF0.8080103@innova-card.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <45265BF0.8080103@innova-card.com> User-Agent: Mutt/1.5.13 (2006-08-11) From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12821 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Content-Length: 1251 Lines: 36 Franck Bui-Huu wrote: > From: Franck Bui-Huu > > This patch introduces __pa_symbol() macro which should be used to > calculate the physical address of kernel symbols. We should fix any > linker issues in this macro, if any, but more importantly > __pa_symbol() uses __pa() to do the real conversion. > > One resulting thing is that we can see that most of CPHYSADDR() uses > weren't needed. > > It also rely on RELOC_HIDE() to avoid any compiler's oddities when > doing arithmetics on symbols. > > Signed-off-by: Franck Bui-Huu > --- > arch/mips/kernel/setup.c | 17 ++++++++++------- > include/asm-mips/page.h | 1 + > 2 files changed, 11 insertions(+), 7 deletions(-) > > diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c > index fdbb508..cccccd5 100644 > --- a/arch/mips/kernel/setup.c > +++ b/arch/mips/kernel/setup.c > @@ -204,12 +204,12 @@ static void __init finalize_initrd(void) > printk(KERN_INFO "Initrd not found or empty"); > goto disable; > } > - if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { > + if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) { ISTR this failed on O2, where kernel+initrd are loaded into KSEG0 but the PAGE_OFFSET is for XKPHYS. Thiemo From sshtylyov@ru.mvista.com Fri Oct 6 19:31:45 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Oct 2006 19:31:49 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:59883 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20039484AbWJFSbp (ORCPT ); Fri, 6 Oct 2006 19:31:45 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id F15213ECA; Fri, 6 Oct 2006 11:31:18 -0700 (PDT) Message-ID: <4526A0F3.5090202@ru.mvista.com> Date: Fri, 06 Oct 2006 22:31:15 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Yoichi Yuasa Cc: Ralf Baechle , linux-mips Subject: Re: [PATCH] add "depends on BROKEN" to broken boards support References: <20061007005452.45b50d8c.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20061007005452.45b50d8c.yoichi_yuasa@tripeaks.co.jp> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12822 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1178 Lines: 54 Hello. Yoichi Yuasa wrote: > This patch has added "depends on BROKEN" to broken boards support. > These boards cannot build now. > Yoichi > Signed-off-by: Yoichi Yuasa > @@ -511,6 +517,7 @@ config QEMU > > config MARKEINS > bool "Support for NEC EMMA2RH Mark-eins" > + depends on BROKEN > select DMA_NONCOHERENT > select HW_HAS_PCI > select IRQ_CPU What's broken about this board? > @@ -717,6 +724,7 @@ config SNI_RM200_PCI > > config TOSHIBA_JMR3927 > bool "Toshiba JMR-TX3927 board" > + depends on BROKEN > select DMA_NONCOHERENT > select HW_HAS_PCI > select MIPS_TX3927 > @@ -728,6 +736,7 @@ config TOSHIBA_JMR3927 > > config TOSHIBA_RBTX4927 > bool "Toshiba TBTX49[23]7 board" > + depends on BROKEN > select DMA_NONCOHERENT > select HAS_TXX9_SERIAL > select HW_HAS_PCI ... and this one? > @@ -745,6 +754,7 @@ config TOSHIBA_RBTX4927 > > config TOSHIBA_RBTX4938 > bool "Toshiba RBTX4938 board" > + depends on BROKEN > select HAVE_STD_PC_SERIAL_PORT > select DMA_NONCOHERENT > select GENERIC_ISA_DMA There's a patch from Atsushi Nemoto still pending commit, IIRC... WBR, Sergei From kaz@zeugmasystems.com Sat Oct 7 01:02:14 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Oct 2006 01:02:18 +0100 (BST) Received: from mail.zeugmasystems.com ([192.139.122.66]:9315 "EHLO zeugmasystems.com") by ftp.linux-mips.org with ESMTP id S20039501AbWJGACO convert rfc822-to-8bit (ORCPT ); Sat, 7 Oct 2006 01:02:14 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: CFE problem: starting secondary CPU. Date: Fri, 6 Oct 2006 16:58:37 -0700 Message-ID: <66910A579C9312469A7DF9ADB54A8B7D3E7324@exchange.ZeugmaSystems.local> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: CFE problem: starting secondary CPU. thread-index: Acbpo1bBhY91FwuRSxSoPT5JCpbUyw== From: "Kaz Kylheku" To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12823 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kaz@zeugmasystems.com Precedence: bulk X-list: linux-mips Content-Length: 902 Lines: 34 Anyone seen a problem like this? cfe_cpu_start() works fine on a 32 bit kernel, but not on 64. I added a function to cfe/smp.c: static asmlinkage void dummy() { prom_printf("dummy called\n"); } This serves as the simplest possible "hello world". If I substitute this for the function passed to cfe_cpu_start(), on a 32 bit kernel, the slave CPU calls the function and the message is printed on the serial console. On a 64 bit kernel, the function is never reached. The API call returns, but the secondary CPU never calls in. The sign-extension of the address looks good. The function pointer looks like FFFFFFFF8XXXXXXX. This is cast to long before being assigned into the right field of the CFE request structure, where it is converted to 64 bit unsigned. Inside CFE, the CPU is just looping around waiting for the address to call with a direct jump. So it's a puzzling problem. From imipak@yahoo.com Sat Oct 7 03:15:33 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Oct 2006 03:15:36 +0100 (BST) Received: from web31512.mail.mud.yahoo.com ([68.142.198.141]:44198 "HELO web31512.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20039510AbWJGCPd (ORCPT ); Sat, 7 Oct 2006 03:15:33 +0100 Received: (qmail 38256 invoked by uid 60001); 7 Oct 2006 02:15:23 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=R1K3NnMHzeHJwfOUax5rd9FYokPBFcfUEypBmy2cYOLRo0xLpIUiW+w6vr1kLlVM5GZvac6YBkLdUVmjAzYII/GwI/KfMjtn1UtKp/npmHWvF+HXi6npwVLIvtBpPuCbQsURLeIjAdsViZNxIOiDL75JMyANBNmPw4vepxZNblc= ; Message-ID: <20061007021523.38254.qmail@web31512.mail.mud.yahoo.com> Received: from [65.102.5.19] by web31512.mail.mud.yahoo.com via HTTP; Fri, 06 Oct 2006 19:15:23 PDT Date: Fri, 6 Oct 2006 19:15:23 -0700 (PDT) From: Jonathan Day Subject: Re: CFE problem: starting secondary CPU. To: Kaz Kylheku , linux-mips@linux-mips.org In-Reply-To: <66910A579C9312469A7DF9ADB54A8B7D3E7324@exchange.ZeugmaSystems.local> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12824 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips Content-Length: 1587 Lines: 62 I've seen the case where the second CPU did not start on a Broadcom 1250 running a 64-bit kernel, but I don't know if anyone has a good solution. I just rigged the values in the Linux kernel so that it knows about the second CPU. It's a godawful hack, but I needed something quick at the time. Personally, I am not a fan of CFE and would love to know if there's a better way to bootstrap. --- Kaz Kylheku wrote: > Anyone seen a problem like this? cfe_cpu_start() > works fine on a > 32 bit kernel, but not on 64. > > I added a function to cfe/smp.c: > > static asmlinkage void dummy() > { > prom_printf("dummy called\n"); > } > > This serves as the simplest possible "hello world". > > If I substitute this for the function passed to > cfe_cpu_start(), > on a 32 bit kernel, the slave CPU calls the function > and the > message is printed on the serial console. > > On a 64 bit kernel, the function is never reached. > The API call returns, > but the > secondary CPU never calls in. > > The sign-extension of the address looks good. The > function pointer looks > like > FFFFFFFF8XXXXXXX. This is cast to long before being > assigned into the > right field > of the CFE request structure, where it is converted > to 64 bit unsigned. > > Inside CFE, the CPU is just looping around waiting > for the address to > call with > a direct jump. > > So it's a puzzling problem. > > > > > __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From yoichi_yuasa@tripeaks.co.jp Sat Oct 7 07:26:47 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Oct 2006 07:26:49 +0100 (BST) Received: from mo32.po.2iij.net ([210.128.50.17]:53257 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20037733AbWJGG0r (ORCPT ); Sat, 7 Oct 2006 07:26:47 +0100 Received: by mo.po.2iij.net (mo32) id k976QhP8008163; Sat, 7 Oct 2006 15:26:43 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox33) id k976QZdb064253 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sat, 7 Oct 2006 15:26:36 +0900 (JST) Date: Sat, 7 Oct 2006 06:48:05 +0900 From: Yoichi Yuasa To: Sergei Shtylyov Cc: yoichi_yuasa@tripeaks.co.jp, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] add "depends on BROKEN" to broken boards support Message-Id: <20061007064805.5b656556.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <4526A0F3.5090202@ru.mvista.com> References: <20061007005452.45b50d8c.yoichi_yuasa@tripeaks.co.jp> <4526A0F3.5090202@ru.mvista.com> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12825 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 5727 Lines: 125 Hello Sergei, On Fri, 06 Oct 2006 22:31:15 +0400 Sergei Shtylyov wrote: > Hello. > > Yoichi Yuasa wrote: > > > This patch has added "depends on BROKEN" to broken boards support. > > These boards cannot build now. > > > Yoichi > > > Signed-off-by: Yoichi Yuasa > > > @@ -511,6 +517,7 @@ config QEMU > > > > config MARKEINS > > bool "Support for NEC EMMA2RH Mark-eins" > > + depends on BROKEN > > select DMA_NONCOHERENT > > select HW_HAS_PCI > > select IRQ_CPU > > What's broken about this board? I got build error under arch/mips/emma2rh . This board support cannot be built for three months or more. CC arch/mips/emma2rh/common/irq.o arch/mips/emma2rh/common/irq.c: In function `emma2rh_irq_dispatch': arch/mips/emma2rh/common/irq.c:59: error: too many arguments to function `__do_IRQ' arch/mips/emma2rh/common/irq.c:68: error: too many arguments to function `__do_IRQ' arch/mips/emma2rh/common/irq.c:84: error: too many arguments to function `__do_IRQ' arch/mips/emma2rh/common/irq.c:93: error: too many arguments to function `__do_IRQ' arch/mips/emma2rh/common/irq.c:103: error: too many arguments to function `__do_IRQ' make[1]: *** [arch/mips/emma2rh/common/irq.o] Error 1 make: *** [arch/mips/emma2rh/common] Error 2 > > > @@ -717,6 +724,7 @@ config SNI_RM200_PCI > > > > config TOSHIBA_JMR3927 > > bool "Toshiba JMR-TX3927 board" > > + depends on BROKEN > > select DMA_NONCOHERENT > > select HW_HAS_PCI > > select MIPS_TX3927 > > @@ -728,6 +736,7 @@ config TOSHIBA_JMR3927 > > > > config TOSHIBA_RBTX4927 > > bool "Toshiba TBTX49[23]7 board" > > + depends on BROKEN > > select DMA_NONCOHERENT > > select HAS_TXX9_SERIAL > > select HW_HAS_PCI > > ... and this one? Also, this board support cannot be built for three months or more. CC arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.o CC arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.o arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c: In function `tx4927_pcibios_init': arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c:274: warning: unused variable `s' arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c:359: warning: unused variable `s' arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c: In function `toshiba_rbtx4927_setup': arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c:1003: warning: implicit declaration of function `prom_getcmdline' arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c:1003: warning: assignment makes pointer from integer without a cast arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c:1011: warning: assignment makes pointer from integer without a cast arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c: In function `toshiba_rbtx4927_time_init': arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c:1031: warning: unused variable `c1' arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c:1032: warning: unused variable `c2' arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c: At top level: arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c:165: warning: 'tx4927_pcierr_interrupt' defined but not used arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c:244: warning: 'early_read_config_word' defined but not used arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c:247: warning: 'early_write_config_word' defined but not used CC arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.o arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c: In function `toshiba_rbtx4927_irq_ioc_enable': arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c:434: warning: implicit declaration of function `wbflush' LD arch/mips/tx4927/toshiba_rbtx4927/built-in.o CC arch/mips/tx4927/common/tx4927_prom.o CC arch/mips/tx4927/common/tx4927_setup.o CC arch/mips/tx4927/common/tx4927_irq.o arch/mips/tx4927/common/tx4927_irq.c: In function `tx4927_irq_nested': arch/mips/tx4927/common/tx4927_irq.c:563: warning: implicit declaration of function `toshiba_rbtx4927_irq_nested' make[1]: *** No rule to make target `arch/mips/tx4927/common/smsc_fdc37m81x.o', needed by `arch/mips/tx4927/common/built-in.o'. Stop. make: *** [arch/mips/tx4927/common] Error 2 > > @@ -745,6 +754,7 @@ config TOSHIBA_RBTX4927 > > > > config TOSHIBA_RBTX4938 > > bool "Toshiba RBTX4938 board" > > + depends on BROKEN > > select HAVE_STD_PC_SERIAL_PORT > > select DMA_NONCOHERENT > > select GENERIC_ISA_DMA > > There's a patch from Atsushi Nemoto still pending commit, IIRC... Is it fixed these errors. LD .tmp_vmlinux1 arch/mips/tx4938/toshiba_rbtx4938/built-in.o: In function `toshiba_rbtx4938_irq_nested': : undefined reference to `wbflush' arch/mips/tx4938/toshiba_rbtx4938/built-in.o: In function `toshiba_rbtx4938_irq_nested': : relocation truncated to fit: R_MIPS_26 against `wbflush' arch/mips/tx4938/toshiba_rbtx4938/built-in.o: In function `arch_init_irq': : undefined reference to `wbflush' arch/mips/tx4938/toshiba_rbtx4938/built-in.o: In function `arch_init_irq': : relocation truncated to fit: R_MIPS_26 against `wbflush' arch/mips/tx4938/toshiba_rbtx4938/built-in.o: In function `arch_init_irq': : undefined reference to `wbflush' arch/mips/tx4938/toshiba_rbtx4938/built-in.o: In function `arch_init_irq': : relocation truncated to fit: R_MIPS_26 against `wbflush' arch/mips/tx4938/common/built-in.o: In function `tx4938_irq_nested': : undefined reference to `wbflush' arch/mips/tx4938/common/built-in.o: In function `tx4938_irq_nested': : relocation truncated to fit: R_MIPS_26 against `wbflush' make: *** [.tmp_vmlinux1] Error 1 Yoichi From ralf@linux-mips.org Sat Oct 7 11:54:22 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Oct 2006 11:54:24 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:49071 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20038709AbWJGKyW (ORCPT ); Sat, 7 Oct 2006 11:54:22 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k97ArxDM000764; Sat, 7 Oct 2006 11:54:01 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k97ArcL9000763; Sat, 7 Oct 2006 11:53:38 +0100 Date: Sat, 7 Oct 2006 11:53:38 +0100 From: Ralf Baechle To: Jonathan Day Cc: Kaz Kylheku , linux-mips@linux-mips.org Subject: Re: CFE problem: starting secondary CPU. Message-ID: <20061007105338.GA571@linux-mips.org> References: <66910A579C9312469A7DF9ADB54A8B7D3E7324@exchange.ZeugmaSystems.local> <20061007021523.38254.qmail@web31512.mail.mud.yahoo.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20061007021523.38254.qmail@web31512.mail.mud.yahoo.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12826 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 657 Lines: 17 On Fri, Oct 06, 2006 at 07:15:23PM -0700, Jonathan Day wrote: > I've seen the case where the second CPU did not start > on a Broadcom 1250 running a 64-bit kernel, but I > don't know if anyone has a good solution. I just > rigged the values in the Linux kernel so that it knows > about the second CPU. It's a godawful hack, but I > needed something quick at the time. > > Personally, I am not a fan of CFE and would love to > know if there's a better way to bootstrap. Firmware is a stepchild and all implementations have in common that they're hated by they're users. And my grief is there are way to many different firmwares for MIPS systems. Ralf From anemo@mba.ocn.ne.jp Sat Oct 7 14:53:01 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Oct 2006 14:53:03 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:25566 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20039147AbWJGNxB (ORCPT ); Sat, 7 Oct 2006 14:53:01 +0100 Received: from localhost (p8091-ipad29funabasi.chiba.ocn.ne.jp [221.184.75.91]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 48476A737; Sat, 7 Oct 2006 22:52:53 +0900 (JST) Date: Sat, 07 Oct 2006 22:55:07 +0900 (JST) Message-Id: <20061007.225507.41198174.anemo@mba.ocn.ne.jp> To: yoichi_yuasa@tripeaks.co.jp Cc: sshtylyov@ru.mvista.com, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] add "depends on BROKEN" to broken boards support From: Atsushi Nemoto In-Reply-To: <20061007064805.5b656556.yoichi_yuasa@tripeaks.co.jp> References: <20061007005452.45b50d8c.yoichi_yuasa@tripeaks.co.jp> <4526A0F3.5090202@ru.mvista.com> <20061007064805.5b656556.yoichi_yuasa@tripeaks.co.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12827 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 614 Lines: 17 On Sat, 7 Oct 2006 06:48:05 +0900, Yoichi Yuasa wrote: > > There's a patch from Atsushi Nemoto still pending commit, IIRC... > > Is it fixed these errors. > > LD .tmp_vmlinux1 > arch/mips/tx4938/toshiba_rbtx4938/built-in.o: In function `toshiba_rbtx4938_irq_nested': > : undefined reference to `wbflush' > arch/mips/tx4938/toshiba_rbtx4938/built-in.o: In function `toshiba_rbtx4938_irq_nested': > : relocation truncated to fit: R_MIPS_26 against `wbflush' Yes. The patch is here. http://www.linux-mips.org/archives/linux-mips/2006-08/msg00204.html --- Atsushi Nemoto From yoichi_yuasa@tripeaks.co.jp Sat Oct 7 15:25:36 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Oct 2006 15:25:38 +0100 (BST) Received: from mo30.po.2iij.net ([210.128.50.53]:33287 "EHLO mo30.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20039151AbWJGOZg (ORCPT ); Sat, 7 Oct 2006 15:25:36 +0100 Received: by mo.po.2iij.net (mo30) id k97EPXRq051059; Sat, 7 Oct 2006 23:25:33 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox32) id k97EPSZn086788 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sat, 7 Oct 2006 23:25:28 +0900 (JST) Date: Sat, 7 Oct 2006 13:02:27 +0900 From: Yoichi Yuasa To: Atsushi Nemoto Cc: yoichi_yuasa@tripeaks.co.jp, sshtylyov@ru.mvista.com, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] add "depends on BROKEN" to broken boards support Message-Id: <20061007130227.0790b206.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20061007.225507.41198174.anemo@mba.ocn.ne.jp> References: <20061007005452.45b50d8c.yoichi_yuasa@tripeaks.co.jp> <4526A0F3.5090202@ru.mvista.com> <20061007064805.5b656556.yoichi_yuasa@tripeaks.co.jp> <20061007.225507.41198174.anemo@mba.ocn.ne.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12828 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 772 Lines: 22 On Sat, 07 Oct 2006 22:55:07 +0900 (JST) Atsushi Nemoto wrote: > On Sat, 7 Oct 2006 06:48:05 +0900, Yoichi Yuasa wrote: > > > There's a patch from Atsushi Nemoto still pending commit, IIRC... > > > > Is it fixed these errors. > > > > LD .tmp_vmlinux1 > > arch/mips/tx4938/toshiba_rbtx4938/built-in.o: In function `toshiba_rbtx4938_irq_nested': > > : undefined reference to `wbflush' > > arch/mips/tx4938/toshiba_rbtx4938/built-in.o: In function `toshiba_rbtx4938_irq_nested': > > : relocation truncated to fit: R_MIPS_26 against `wbflush' > > Yes. The patch is here. > > http://www.linux-mips.org/archives/linux-mips/2006-08/msg00204.html OK, It's fixed rbhma4500 errors. I'll update my patch. Yoichi From yoichi_yuasa@tripeaks.co.jp Sat Oct 7 16:05:00 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Oct 2006 16:05:01 +0100 (BST) Received: from mo32.po.2iij.net ([210.128.50.17]:22835 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20039183AbWJGPFA (ORCPT ); Sat, 7 Oct 2006 16:05:00 +0100 Received: by mo.po.2iij.net (mo32) id k97F4vYV054737; Sun, 8 Oct 2006 00:04:57 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox33) id k97F4qHK067300 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sun, 8 Oct 2006 00:04:52 +0900 (JST) Date: Sat, 7 Oct 2006 13:41:51 +0900 From: Yoichi Yuasa To: ralf@linux-mips.org Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips@linux-mips.org Subject: [PATCH] fix DECserial build error by IRQ hander change Message-Id: <20061007134151.27c09f49.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20061007003516.5eec677e.yoichi_yuasa@tripeaks.co.jp> References: <20061007003516.5eec677e.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12829 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 577 Lines: 21 Hi Ralf, One more fix for zs.c . Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/tc/zs.c mips/drivers/tc/zs.c --- mips-orig/drivers/tc/zs.c 2006-10-07 23:51:44.882996750 +0900 +++ mips/drivers/tc/zs.c 2006-10-07 23:55:33.909310000 +0900 @@ -389,7 +389,7 @@ static void receive_chars(struct dec_ser if (ch == 0) continue; if (time_before(jiffies, break_pressed + HZ * 5)) { - handle_sysrq(ch, regs, NULL); + handle_sysrq(ch, NULL); break_pressed = 0; continue; } From girishvg@gmail.com Sat Oct 7 23:10:23 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Oct 2006 23:10:25 +0100 (BST) Received: from py-out-1112.google.com ([64.233.166.181]:63376 "EHLO py-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S20039559AbWJGWKX (ORCPT ); Sat, 7 Oct 2006 23:10:23 +0100 Received: by py-out-1112.google.com with SMTP id i49so1395863pyi for ; Sat, 07 Oct 2006 15:10:22 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:in-reply-to:references:mime-version:content-type:message-id:cc:content-transfer-encoding:from:subject:date:to:x-mailer; b=T+teVh8eWdSnOMWJ81xUdYR2aVBuXK3cLo3r3U6IbDTx9pmeZs9CMgP9Eeon6qxzYgH89cHQWWzZaLLRB+92KFNjPZVmmmxppGBUxm5mHCg1c0eyTjz3wug6turXpMBVGOnRU6Owh5NT85vum+6EHdla23yKlLAZUJn7FyLm22I= Received: by 10.35.10.17 with SMTP id n17mr9056408pyi; Sat, 07 Oct 2006 15:10:22 -0700 (PDT) Received: from ?192.168.1.3? ( [61.125.212.22]) by mx.google.com with ESMTP id q71sm1563852pyg.2006.10.07.15.10.20; Sat, 07 Oct 2006 15:10:21 -0700 (PDT) In-Reply-To: <20061007105338.GA571@linux-mips.org> References: <66910A579C9312469A7DF9ADB54A8B7D3E7324@exchange.ZeugmaSystems.local> <20061007021523.38254.qmail@web31512.mail.mud.yahoo.com> <20061007105338.GA571@linux-mips.org> Mime-Version: 1.0 (Apple Message framework v749) Content-Type: text/plain; charset=US-ASCII; delsp=yes; format=flowed Message-Id: <9D189830-9D85-4360-BEEE-72A3D5510D77@gmail.com> Cc: Jonathan Day , Kaz Kylheku , linux-mips@linux-mips.org Content-Transfer-Encoding: 7bit From: girish Subject: Re: CFE problem: starting secondary CPU. Date: Sun, 8 Oct 2006 07:10:40 +0900 To: Ralf Baechle X-Mailer: Apple Mail (2.749) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12830 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: girishvg@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 887 Lines: 27 On Oct 7, 2006, at 7:53 PM, Ralf Baechle wrote: > On Fri, Oct 06, 2006 at 07:15:23PM -0700, Jonathan Day wrote: > >> I've seen the case where the second CPU did not start >> on a Broadcom 1250 running a 64-bit kernel, but I >> don't know if anyone has a good solution. I just >> rigged the values in the Linux kernel so that it knows >> about the second CPU. It's a godawful hack, but I >> needed something quick at the time. >> >> Personally, I am not a fan of CFE and would love to >> know if there's a better way to bootstrap. > > Firmware is a stepchild and all implementations have in common that > they're > hated by they're users. And my grief is there are way to many > different > firmwares for MIPS systems. > > Ralf > would it be reasonable to choose couple of bootmonitors and support them under MIPS/Linux umbrella. even bootable linux would be a good choice. From creideiki+linux-mips@ferretporn.se Sun Oct 8 00:15:21 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Oct 2006 00:15:23 +0100 (BST) Received: from pne-smtpout1-sn2.hy.skanova.net ([81.228.8.83]:44251 "EHLO pne-smtpout1-sn2.hy.skanova.net") by ftp.linux-mips.org with ESMTP id S20039566AbWJGXPV (ORCPT ); Sun, 8 Oct 2006 00:15:21 +0100 Received: from mail.ferretporn.se (83.250.8.219) by pne-smtpout1-sn2.hy.skanova.net (7.2.075) id 4516FC4100369BD4 for linux-mips@linux-mips.org; Sun, 8 Oct 2006 01:15:15 +0200 Received: from peepoe.ferretporn.se (peepoe.ferretporn.se [192.168.0.7]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.ferretporn.se (Postfix) with ESMTP id 6E88DCBF4 for ; Sun, 8 Oct 2006 01:15:14 +0200 (CEST) From: Karl-Johan Karlsson To: linux-mips@linux-mips.org Subject: [PATCH] Show actual CPU information in /proc/cpuinfo Date: Sun, 8 Oct 2006 01:15:02 +0200 User-Agent: KMail/1.9.4 X-Eric-Conspiracy: There is no conspiracy MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200610080115.12452.creideiki+linux-mips@ferretporn.se> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12831 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: creideiki+linux-mips@ferretporn.se Precedence: bulk X-list: linux-mips Content-Length: 1952 Lines: 43 Currently, /proc/cpuinfo contains several copies of the information for whatever processor we happen to be scheduled on. This patch makes it contain the proper information for each CPU, which is particularly useful on mixed R12k/R10k IP27 machines. Signed-off-by: Karl-Johan Karlsson --- diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index d8beef1..46ee5a6 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -89,9 +89,9 @@ static const char *cpu_name[] = { static int show_cpuinfo(struct seq_file *m, void *v) { - unsigned int version = current_cpu_data.processor_id; - unsigned int fp_vers = current_cpu_data.fpu_id; unsigned long n = (unsigned long) v - 1; + unsigned int version = cpu_data[n].processor_id; + unsigned int fp_vers = cpu_data[n].fpu_id; char fmt [64]; #ifdef CONFIG_SMP @@ -108,8 +108,8 @@ #endif seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", cpu_has_fpu ? " FPU V%d.%d" : ""); - seq_printf(m, fmt, cpu_name[current_cpu_data.cputype <= CPU_LAST ? - current_cpu_data.cputype : CPU_UNKNOWN], + seq_printf(m, fmt, cpu_name[cpu_data[n].cputype <= CPU_LAST ? + cpu_data[n].cputype : CPU_UNKNOWN], (version >> 4) & 0x0f, version & 0x0f, (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", @@ -118,7 +118,7 @@ #endif seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); seq_printf(m, "microsecond timers\t: %s\n", cpu_has_counter ? "yes" : "no"); - seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize); + seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); seq_printf(m, "extra interrupt vector\t: %s\n", cpu_has_divec ? "yes" : "no"); seq_printf(m, "hardware watchpoint\t: %s\n", From ralf@linux-mips.org Sun Oct 8 00:25:25 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Oct 2006 00:25:26 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:64910 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20039571AbWJGXZZ (ORCPT ); Sun, 8 Oct 2006 00:25:25 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k97NPQkH031447; Sun, 8 Oct 2006 00:25:26 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k97NPK5u031446; Sun, 8 Oct 2006 00:25:20 +0100 Date: Sun, 8 Oct 2006 00:25:20 +0100 From: Ralf Baechle To: Karl-Johan Karlsson Cc: linux-mips@linux-mips.org Subject: Re: /proc/cpuinfo makes false assumptions of uniformity on IP27 Message-ID: <20061007232520.GA23815@linux-mips.org> References: <34353.136.163.203.3.1160138023.squirrel@www.ferretporn.se> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <34353.136.163.203.3.1160138023.squirrel@www.ferretporn.se> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12832 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 745 Lines: 18 On Fri, Oct 06, 2006 at 02:33:43PM +0200, Karl-Johan Karlsson wrote: > 1. What about the CPU feature test macros in > include/asm-mips/cpu-features.h? They claim > /* > * SMP assumption: Options of CPU 0 are a superset of all processors. > * This is true for all known MIPS systems. > */ > but is that really true, even on a mixed R12k/R10k system? To the degree that is actually matters, yes. For cache managment on Origins the size of the S-cache doesn't matter, that is it is not relevant if scache_size(cpu 0) > or < scache_size(cpu 1). It gets a little hairy for stuff like performance counters where the R10000 supports a different set of events than its successors; that is not something oprofile can deal with ... Ralf From ralf@linux-mips.org Sun Oct 8 00:32:15 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Oct 2006 00:32:17 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:35499 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20039572AbWJGXcP (ORCPT ); Sun, 8 Oct 2006 00:32:15 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k97NWK4v031559; Sun, 8 Oct 2006 00:32:20 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k97NWJMa031558; Sun, 8 Oct 2006 00:32:19 +0100 Date: Sun, 8 Oct 2006 00:32:19 +0100 From: Ralf Baechle To: Scott Ashcroft Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Time runs too quickly on Cobalt Message-ID: <20061007233219.GB31472@linux-mips.org> References: <45267C4E.8090101@talk21.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <45267C4E.8090101@talk21.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12833 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 282 Lines: 9 On Fri, Oct 06, 2006 at 04:54:54PM +0100, Scott Ashcroft wrote: > If I build a kernel with HZ==250 then time runs about 4 four times too > quickly on my Cobalt RaQ2. > > The following patch seems to fix it but I'm not sure this is the correct > thing to do. Looks right to me. From ralf@linux-mips.org Sun Oct 8 02:17:44 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Oct 2006 02:17:46 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:18631 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20038822AbWJHBRo (ORCPT ); Sun, 8 Oct 2006 02:17:44 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k981Hn1w024503; Sun, 8 Oct 2006 02:17:50 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k981HmSv024502; Sun, 8 Oct 2006 02:17:48 +0100 Date: Sun, 8 Oct 2006 02:17:48 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH] fix build errors by IRQ hander change Message-ID: <20061008011747.GA20330@linux-mips.org> References: <20061007003516.5eec677e.yoichi_yuasa@tripeaks.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20061007003516.5eec677e.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12834 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 549 Lines: 14 On Sat, Oct 07, 2006 at 12:35:16AM +0900, Yoichi Yuasa wrote: > Hi Ralf, > > This patch has fixed build errors by the IRQ handler change. I didn't like David Howell's MIPS patch which left alot of the pt_regs passing in the MIPS code still alive. So I went for a much larger and intrusive solution which I've pushed just so at least some configurations are usable again. I've tested Malta without multithreading (OK), Malta VSMP (hangs), Malta SMTC (hangs), Qemu (OK) so it seems there is something still broken with SMP, I guess IPIs. Ralf From daniel@caiaq.de Sun Oct 8 14:59:20 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Oct 2006 14:59:22 +0100 (BST) Received: from buzzloop.caiaq.de ([212.112.241.133]:15122 "EHLO buzzloop.caiaq.de") by ftp.linux-mips.org with ESMTP id S20039345AbWJHN7T (ORCPT ); Sun, 8 Oct 2006 14:59:19 +0100 Received: from localhost (localhost [127.0.0.1]) by buzzloop.caiaq.de (Postfix) with ESMTP id EF4A67F403A for ; Sun, 8 Oct 2006 15:59:12 +0200 (CEST) Received: from buzzloop.caiaq.de ([127.0.0.1]) by localhost (buzzloop [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 29439-08 for ; Sun, 8 Oct 2006 15:59:12 +0200 (CEST) Received: by buzzloop.caiaq.de (Postfix, from userid 1000) id C8AF97F4026; Sun, 8 Oct 2006 15:59:12 +0200 (CEST) Date: Sun, 8 Oct 2006 15:59:12 +0200 From: Daniel Mack To: linux-mips@linux-mips.org Subject: [PATCH] make au1xxx_ide compile Message-ID: <20061008135912.GA368@ipxXXXXX> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12835 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: daniel@caiaq.de Precedence: bulk X-list: linux-mips Content-Length: 974 Lines: 23 Hi all, This makes the DMA part of the au1xxx driver compile again. Daniel Signed-off-by: Daniel Mack --- a/include/asm-mips/mach-au1x00/au1xxx_ide.h +++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h @@ -171,10 +171,8 @@ #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_D static int auide_dma_host_on(ide_drive_t *drive); static int auide_dma_lostirq(ide_drive_t *drive); static int auide_dma_on(ide_drive_t *drive); - static void auide_ddma_tx_callback(int irq, void *param, - struct pt_regs *regs); - static void auide_ddma_rx_callback(int irq, void *param, - struct pt_regs *regs); + static void auide_ddma_tx_callback(int irq, void *param); + static void auide_ddma_rx_callback(int irq, void *param); static int auide_dma_off_quietly(ide_drive_t *drive); #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ From anemo@mba.ocn.ne.jp Sun Oct 8 16:07:53 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Oct 2006 16:07:55 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:36301 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20038870AbWJHPHx (ORCPT ); Sun, 8 Oct 2006 16:07:53 +0100 Received: from localhost (p7241-ipad29funabasi.chiba.ocn.ne.jp [221.184.74.241]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 4D55BAAC7; Mon, 9 Oct 2006 00:07:47 +0900 (JST) Date: Mon, 09 Oct 2006 00:10:01 +0900 (JST) Message-Id: <20061009.001001.74753036.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, mlachwani@mvista.com Subject: [PATCH] Make sure cpu_has_fpu is used only in atomic context From: Atsushi Nemoto In-Reply-To: <20060901.170817.118968734.nemoto@toshiba-tops.co.jp> References: <44F715F2.7050305@mvista.com> <20060901.122527.63741495.nemoto@toshiba-tops.co.jp> <20060901.170817.118968734.nemoto@toshiba-tops.co.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12836 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 6140 Lines: 214 Make sure cpu_has_fpu (which uses smp_processor_id()) is used only in atomic context. Signed-off-by: Atsushi Nemoto arch/mips/kernel/proc.c | 2 +- arch/mips/kernel/process.c | 2 +- arch/mips/kernel/ptrace.c | 18 ++++++++++-------- arch/mips/kernel/ptrace32.c | 3 ++- arch/mips/kernel/traps.c | 16 +++++++++------- arch/mips/math-emu/cp1emu.c | 7 +++---- include/asm-mips/fpu.h | 6 ++++-- 7 files changed, 30 insertions(+), 24 deletions(-) diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 46ee5a6..4ed37ba 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -107,7 +107,7 @@ #endif seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", - cpu_has_fpu ? " FPU V%d.%d" : ""); + cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); seq_printf(m, fmt, cpu_name[cpu_data[n].cputype <= CPU_LAST ? cpu_data[n].cputype : CPU_UNKNOWN], (version >> 4) & 0x0f, version & 0x0f, diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 045d987..9f307eb 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -115,7 +115,7 @@ #endif status |= KU_USER; regs->cp0_status = status; clear_used_math(); - lose_fpu(); + clear_fpu_owner(); if (cpu_has_dsp) __init_dsp(); regs->cp0_epc = pc; diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 9c3b5fc..1fd705a 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -106,6 +106,7 @@ int ptrace_setregs (struct task_struct * int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) { int i; + unsigned int tmp; if (!access_ok(VERIFY_WRITE, data, 33 * 8)) return -EIO; @@ -121,10 +122,10 @@ int ptrace_getfpregs (struct task_struct __put_user (child->thread.fpu.fcr31, data + 64); + preempt_disable(); if (cpu_has_fpu) { - unsigned int flags, tmp; + unsigned int flags; - preempt_disable(); if (cpu_has_mipsmt) { unsigned int vpflags = dvpe(); flags = read_c0_status(); @@ -138,11 +139,11 @@ int ptrace_getfpregs (struct task_struct __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); write_c0_status(flags); } - preempt_enable(); - __put_user (tmp, data + 65); } else { - __put_user ((__u32) 0, data + 65); + tmp = 0; } + preempt_enable(); + __put_user (tmp, data + 65); return 0; } @@ -245,16 +246,17 @@ #ifdef CONFIG_MIPS_MT_SMTC unsigned int mtflags; #endif /* CONFIG_MIPS_MT_SMTC */ - if (!cpu_has_fpu) + preempt_disable(); + if (!cpu_has_fpu) { + preempt_enable(); break; + } #ifdef CONFIG_MIPS_MT_SMTC /* Read-modify-write of Status must be atomic */ local_irq_save(irqflags); mtflags = dmt(); #endif /* CONFIG_MIPS_MT_SMTC */ - - preempt_disable(); if (cpu_has_mipsmt) { unsigned int vpflags = dvpe(); flags = read_c0_status(); diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index f40ecd8..d9a39c1 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -175,7 +175,9 @@ #ifdef CONFIG_MIPS_MT_SMTC unsigned int mtflags; #endif /* CONFIG_MIPS_MT_SMTC */ + preempt_disable(); if (!cpu_has_fpu) { + preempt_enable(); tmp = 0; break; } @@ -186,7 +188,6 @@ #ifdef CONFIG_MIPS_MT_SMTC mtflags = dmt(); #endif /* CONFIG_MIPS_MT_SMTC */ - preempt_disable(); if (cpu_has_mipsmt) { unsigned int vpflags = dvpe(); flags = read_c0_status(); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b7292a5..cce8313 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -66,7 +66,7 @@ extern asmlinkage void handle_mcheck(voi extern asmlinkage void handle_reserved(void); extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, - struct mips_fpu_struct *ctx); + struct mips_fpu_struct *ctx, int has_fpu); void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); @@ -641,7 +641,7 @@ #endif preempt_enable(); /* Run the emulator */ - sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu); + sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1); preempt_disable(); @@ -791,11 +791,13 @@ asmlinkage void do_cpu(struct pt_regs *r set_used_math(); } - preempt_enable(); - - if (!cpu_has_fpu) { - int sig = fpu_emulator_cop1Handler(regs, - ¤t->thread.fpu); + if (cpu_has_fpu) { + preempt_enable(); + } else { + int sig; + preempt_enable(); + sig = fpu_emulator_cop1Handler(regs, + ¤t->thread.fpu, 0); if (sig) force_sig(sig, current); #ifdef CONFIG_MIPS_MT_FPAFF diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 3f0d5d2..80531b3 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -38,8 +38,6 @@ #include #include #include -#include -#include #include #include #include @@ -1233,7 +1231,8 @@ #endif return 0; } -int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx) +int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, + int has_fpu) { unsigned long oldepc, prevepc; mips_instruction insn; @@ -1263,7 +1262,7 @@ int fpu_emulator_cop1Handler(struct pt_r ieee754_csr.rm = mips_rm[ieee754_csr.rm]; } - if (cpu_has_fpu) + if (has_fpu) break; if (sig) break; diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 58c561a..efef843 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -134,9 +134,11 @@ static inline void restore_fp(struct tas static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) { - if (cpu_has_fpu) { - if ((tsk == current) && __is_fpu_owner()) + if (tsk == current) { + preempt_disable(); + if (is_fpu_owner()) _save_fp(current); + preempt_enable(); } return tsk->thread.fpu.fpr; From anemo@mba.ocn.ne.jp Sun Oct 8 17:22:13 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Oct 2006 17:22:15 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:48857 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20039406AbWJHQWN (ORCPT ); Sun, 8 Oct 2006 17:22:13 +0100 Received: from localhost (p7241-ipad29funabasi.chiba.ocn.ne.jp [221.184.74.241]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 91309A614; Mon, 9 Oct 2006 01:22:08 +0900 (JST) Date: Mon, 09 Oct 2006 01:24:23 +0900 (JST) Message-Id: <20061009.012423.59032950.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] ret_from_irq adjustment From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12837 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 3019 Lines: 128 Make sure that RA on top of interrupt stack is an address of ret_from_irq, so that dump_stack etc. can trace info interrupted context. Also this patch fixes except_vec_vi_handler and __smtc_ipi_vector which seems broken. Signed-off-by: Atsushi Nemoto dec/int-handler.S | 11 ++++------- kernel/entry.S | 14 +++++++++----- kernel/genex.S | 8 +++----- kernel/smtc-asm.S | 9 +++------ 4 files changed, 19 insertions(+), 23 deletions(-) diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S index 55d60d5..31dd47d 100644 --- a/arch/mips/dec/int-handler.S +++ b/arch/mips/dec/int-handler.S @@ -266,10 +266,8 @@ #endif handle_it: LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) - jal do_IRQ - LONG_S s0, TI_REGS($28) - - j ret_from_irq + PTR_LA ra, ret_from_irq + j do_IRQ nop #ifdef CONFIG_32BIT @@ -279,9 +277,8 @@ fpu: #endif spurious: - jal spurious_interrupt - nop - j ret_from_irq + PTR_LA ra, _ret_from_irq + j spurious_interrupt nop END(plat_irq_dispatch) diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index e93e43e..417c08a 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -20,10 +20,7 @@ #ifdef CONFIG_MIPS_MT_SMTC #include #endif -#ifdef CONFIG_PREEMPT - .macro preempt_stop - .endm -#else +#ifndef CONFIG_PREEMPT .macro preempt_stop local_irq_disable .endm @@ -32,9 +29,16 @@ #endif .text .align 5 +FEXPORT(ret_from_irq) + LONG_S s0, TI_REGS($28) +#ifdef CONFIG_PREEMPT +FEXPORT(ret_from_exception) +#else + b _ret_from_irq FEXPORT(ret_from_exception) preempt_stop -FEXPORT(ret_from_irq) +#endif +FEXPORT(_ret_from_irq) LONG_L t0, PT_STATUS(sp) # returning to kernel mode? andi t0, t0, KU_USER beqz t0, resume_kernel diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 50ed772..5baca16 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -133,9 +133,8 @@ NESTED(handle_int, PT_SIZE, sp) LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) - jal plat_irq_dispatch - LONG_S s0, TI_REGS($28) - j ret_from_irq + PTR_LA ra, ret_from_irq + j plat_irq_dispatch END(handle_int) __INIT @@ -224,9 +223,8 @@ #endif /* CONFIG_MIPS_MT_SMTC */ LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) - jalr v0 - LONG_S s0, TI_REGS($28) PTR_LA ra, ret_from_irq + jr v0 END(except_vec_vi_handler) /* diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index 76cb31d..1cb9441 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S @@ -97,15 +97,12 @@ FEXPORT(__smtc_ipi_vector) SAVE_ALL CLI TRACE_IRQS_OFF - move a0,sp /* Function to be invoked passed stack pad slot 5 */ lw t0,PT_PADSLOT5(sp) /* Argument from sender passed in stack pad slot 4 */ - lw a1,PT_PADSLOT4(sp) - jalr t0 - nop - j ret_from_irq - nop + lw a0,PT_PADSLOT4(sp) + PTR_LA ra, _ret_from_irq + jr t0 /* * Called from idle loop to provoke processing of queued IPIs From KevinK@mips.com Sun Oct 8 19:25:37 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Oct 2006 19:25:41 +0100 (BST) Received: from mx.mips.com ([63.167.95.198]:710 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S20038875AbWJHSZh (ORCPT ); Sun, 8 Oct 2006 19:25:37 +0100 Received: from mercury.mips.com (mercury [192.168.64.101]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id k98IOwpT007413; Sun, 8 Oct 2006 11:25:02 -0700 (PDT) Received: from Ulysses ([192.168.3.128]) by mercury.mips.com (8.13.5/8.13.5) with SMTP id k98IPLZn022882; Sun, 8 Oct 2006 11:25:21 -0700 (PDT) Message-ID: <006501c6eb07$4fbf66c0$8003a8c0@Ulysses> From: "Kevin D. Kissell" To: , "Atsushi Nemoto" Cc: References: <20061009.012423.59032950.anemo@mba.ocn.ne.jp> Subject: Re: [PATCH] ret_from_irq adjustment Date: Sun, 8 Oct 2006 20:26:44 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1807 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1807 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12838 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: KevinK@mips.com Precedence: bulk X-list: linux-mips Content-Length: 1221 Lines: 39 While setting up ra "by hand" and transferring control via the jr is a reasonable optimization, you're otherwise breaking things for SMTC. While the comments are misleading (they accurately described an earlier version of the code), the function being called here is ipi_decode(), which needs a pt_regs * in the first argument (hence the copy of the sp), and the pointer to the IPI message descriptor in the second. Do you have access to a 34K to test changes to SMTC? I'd have expected this one to have been pretty quickly fatal. Regards, Kevin K. > diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S > index 76cb31d..1cb9441 100644 > --- a/arch/mips/kernel/smtc-asm.S > +++ b/arch/mips/kernel/smtc-asm.S > @@ -97,15 +97,12 @@ FEXPORT(__smtc_ipi_vector) > SAVE_ALL > CLI > TRACE_IRQS_OFF > - move a0,sp > /* Function to be invoked passed stack pad slot 5 */ > lw t0,PT_PADSLOT5(sp) > /* Argument from sender passed in stack pad slot 4 */ > - lw a1,PT_PADSLOT4(sp) > - jalr t0 > - nop > - j ret_from_irq > - nop > + lw a0,PT_PADSLOT4(sp) > + PTR_LA ra, _ret_from_irq > + jr t0 > > /* > * Called from idle loop to provoke processing of queued IPIs > > From imipak@yahoo.com Sun Oct 8 22:35:50 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Oct 2006 22:35:53 +0100 (BST) Received: from web31502.mail.mud.yahoo.com ([68.142.198.131]:52849 "HELO web31502.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20039657AbWJHVft (ORCPT ); Sun, 8 Oct 2006 22:35:49 +0100 Received: (qmail 84377 invoked by uid 60001); 8 Oct 2006 21:35:38 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:Cc:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=F6+WsDKojuSCM1VKIXBoDNg57wVGXgl5jR7reDRqJHVZhySdX3Mt865+ExGY/h9GtVM6KNJoBbsIDwA9ovMkjhMsgi7dmSygAU6QgqcNNzT0ZzRJ3vepU/PZwUjCQy9DoDBugdOINyly0AB+RLLGMQm0Bf6AXdNLaK+7hJZvlDI= ; Message-ID: <20061008213538.84372.qmail@web31502.mail.mud.yahoo.com> Received: from [65.102.0.10] by web31502.mail.mud.yahoo.com via HTTP; Sun, 08 Oct 2006 14:35:37 PDT Date: Sun, 8 Oct 2006 14:35:37 -0700 (PDT) From: Jonathan Day Subject: Re: CFE problem: starting secondary CPU. To: girish , Ralf Baechle Cc: Jonathan Day , Kaz Kylheku , linux-mips@linux-mips.org In-Reply-To: <9D189830-9D85-4360-BEEE-72A3D5510D77@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12839 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips Content-Length: 1171 Lines: 32 --- girish wrote: > would it be reasonable to choose couple of > bootmonitors and support > them under MIPS/Linux umbrella. even bootable linux > would be a good > choice. I can't see why not. For that matter, I can't imagine it would be too hard to write the necessary flash support to get LinuxBIOS working. It does puzzle me, though, that the kernel seems to get a lot of data from CFE rather than using the probes it already has. Whether it's a built-in BIOS (as on the PC), ACPI, CFE, or some other external table of what is present, the one thing experience has taught is that these tables cannot (and should not) be trusted. Kernel discovery, although unsafe for some hardware*, generally produces more accurate and reliable results. *Of course, that's a killer. There is an unfortunately large amount of hardware in the world that cannot be used safely in conjunction with probes. Other hardware will respond incorrectly, screw up the machine, play all your MP3's backwards, ... __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From ralf@linux-mips.org Sun Oct 8 22:44:42 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Oct 2006 22:44:44 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:34245 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20039656AbWJHVom (ORCPT ); Sun, 8 Oct 2006 22:44:42 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k98LimlP010070; Sun, 8 Oct 2006 22:44:48 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k98Lii7Y010059; Sun, 8 Oct 2006 22:44:44 +0100 Date: Sun, 8 Oct 2006 22:44:43 +0100 From: Ralf Baechle To: "Kevin D. Kissell" Cc: linux-mips@linux-mips.org, Atsushi Nemoto Subject: Re: [PATCH] ret_from_irq adjustment Message-ID: <20061008214443.GA6254@linux-mips.org> References: <20061009.012423.59032950.anemo@mba.ocn.ne.jp> <006501c6eb07$4fbf66c0$8003a8c0@Ulysses> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <006501c6eb07$4fbf66c0$8003a8c0@Ulysses> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12840 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 852 Lines: 18 On Sun, Oct 08, 2006 at 08:26:44PM +0200, Kevin D. Kissell wrote: > While setting up ra "by hand" and transferring control via the jr > is a reasonable optimization, you're otherwise breaking things for SMTC. > While the comments are misleading (they accurately described an earlier > version of the code), the function being called here is ipi_decode(), which > needs a pt_regs * in the first argument (hence the copy of the sp), and > the pointer to the IPI message descriptor in the second. > > Do you have access to a 34K to test changes to SMTC? I'd have > expected this one to have been pretty quickly fatal. The shakeup of the code by the recent series of pt_regs related cleanups is pretty massive. As of last night I only had uniprocessor support working again. VSMP and SMTC were broken; actual multi-core CPU not tested yet. Ralf From kaz@zeugmasystems.com Mon Oct 9 03:10:09 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 03:10:12 +0100 (BST) Received: from mail.zeugmasystems.com ([192.139.122.66]:41957 "EHLO zeugmasystems.com") by ftp.linux-mips.org with ESMTP id S20038960AbWJICKJ convert rfc822-to-8bit (ORCPT ); Mon, 9 Oct 2006 03:10:09 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: CFE problem: starting secondary CPU. Date: Sun, 8 Oct 2006 19:10:05 -0700 Message-ID: <66910A579C9312469A7DF9ADB54A8B7D3E7352@exchange.ZeugmaSystems.local> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: CFE problem: starting secondary CPU. thread-index: AcbptnK09wiGicUZQwSJalVBZNRNVQBjFPJg From: "Kaz Kylheku" To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12841 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kaz@zeugmasystems.com Precedence: bulk X-list: linux-mips Content-Length: 1368 Lines: 45 Jonathan Day wrote: > I've seen the case where the second CPU did not start > on a Broadcom 1250 running a 64-bit kernel, but I > don't know if anyone has a good solution. I just > rigged the values in the Linux kernel so that it knows > about the second CPU. Do you have a patch for that? > It's a godawful hack, but I > needed something quick at the time. I wrote another hack. I struggled with it for hours and then finally got it to work. Whoo! The idea is based on the hypothesis that the 64 bit kernel's environment somehow makes the CFE calls unreliable. Under this hack, the CPUs are started early through CFE, before most other initializations. They go into a holding function which is almost identical to the one inside CFE, except that it's running kernel code. Then later at the point where the CPU's are to be released into the kernel, it's purely an in-kernel operation, no longer involving any calls to CFE. Remarks: I have some CFE code which reads environment variables using CFE. Under 64 bit, there is a mysterious oops in it. The code looks good, and runs fine under 32. What could it be? Maybe CFE doesn't like being called from a task! Something about the 64 bit stack? Note that code which starts the other CPU's is called from a kernel thread which calls the init() function, not from the mainline. I will investigate further. From kevink@mips.com Mon Oct 9 11:37:35 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 11:37:39 +0100 (BST) Received: from mx.mips.com ([63.167.95.198]:31194 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S20037824AbWJIKhf (ORCPT ); Mon, 9 Oct 2006 11:37:35 +0100 Received: from mercury.mips.com (mercury [192.168.64.101]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id k99Ab2vn008798; Mon, 9 Oct 2006 03:37:02 -0700 (PDT) Received: from grendel (grendel [192.168.236.16]) by mercury.mips.com (8.13.5/8.13.5) with SMTP id k99AbNne004800; Mon, 9 Oct 2006 03:37:24 -0700 (PDT) Message-ID: <00f301c6eb8f$cd4b4270$10eca8c0@grendel> From: "Kevin D. Kissell" To: "Kevin D. Kissell" , , "Atsushi Nemoto" Cc: References: <20061009.012423.59032950.anemo@mba.ocn.ne.jp> <006501c6eb07$4fbf66c0$8003a8c0@Ulysses> Subject: Re: [PATCH] ret_from_irq adjustment Date: Mon, 9 Oct 2006 12:43:46 +0200 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_00F0_01C6EBA0.8FA9EA50" X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1807 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1807 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12842 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@mips.com Precedence: bulk X-list: linux-mips Content-Length: 4280 Lines: 125 This is a multi-part message in MIME format. ------=_NextPart_000_00F0_01C6EBA0.8FA9EA50 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit I attach a text file (inline cut-and-paste produces Windows whitespace which apparently is unacceptable) of a patch which (a) implements the ret_from_irq optimization that Atsushi wanted to do to the SMTC code, only without breaking it. I also reorganized and re-commented the code to be easier to maintain in the future, and in an unrelated matter (b) fixes a bug in arch/mips/kernel/smtc.c when there are 64 or more TLB entry pairs on a 34K core. This TLB patch has been in the internal MIPS repository forever, but for some reason has never made it out onto linux-mips.org. The resulting kernel boots and runs (with a 64-entry TLB). Note that these patches are relative to the 2.6.17 semi-stable tree, and not the latest hackfest, so the renaming of ret_from_irq to _ret_from_irq had not been done, and is not reflected in the patch. Regards, Kevin K. ----- Original Message ----- From: "Kevin D. Kissell" To: ; "Atsushi Nemoto" Cc: Sent: Sunday, October 08, 2006 8:26 PM Subject: Re: [PATCH] ret_from_irq adjustment > While setting up ra "by hand" and transferring control via the jr > is a reasonable optimization, you're otherwise breaking things for SMTC. > While the comments are misleading (they accurately described an earlier > version of the code), the function being called here is ipi_decode(), which > needs a pt_regs * in the first argument (hence the copy of the sp), and > the pointer to the IPI message descriptor in the second. > > Do you have access to a 34K to test changes to SMTC? I'd have > expected this one to have been pretty quickly fatal. > > Regards, > > Kevin K. > > > diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S > > index 76cb31d..1cb9441 100644 > > --- a/arch/mips/kernel/smtc-asm.S > > +++ b/arch/mips/kernel/smtc-asm.S > > @@ -97,15 +97,12 @@ FEXPORT(__smtc_ipi_vector) > > SAVE_ALL > > CLI > > TRACE_IRQS_OFF > > - move a0,sp > > /* Function to be invoked passed stack pad slot 5 */ > > lw t0,PT_PADSLOT5(sp) > > /* Argument from sender passed in stack pad slot 4 */ > > - lw a1,PT_PADSLOT4(sp) > > - jalr t0 > > - nop > > - j ret_from_irq > > - nop > > + lw a0,PT_PADSLOT4(sp) > > + PTR_LA ra, _ret_from_irq > > + jr t0 > > > > /* > > * Called from idle loop to provoke processing of queued IPIs > > > > > > ------=_NextPart_000_00F0_01C6EBA0.8FA9EA50 Content-Type: application/octet-stream; name="smtcpatch.gitdiff" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="smtcpatch.gitdiff" diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S=0A= index 72c6d98..a1709de 100644=0A= --- a/arch/mips/kernel/smtc-asm.S=0A= +++ b/arch/mips/kernel/smtc-asm.S=0A= @@ -96,15 +96,14 @@ FEXPORT(__smtc_ipi_vector)=0A= /* Save all will redundantly recompute the SP, but use it for now */=0A= SAVE_ALL=0A= CLI=0A= - move a0,sp=0A= /* Function to be invoked passed stack pad slot 5 */=0A= lw t0,PT_PADSLOT5(sp)=0A= - /* Argument from sender passed in stack pad slot 4 */=0A= + /* First argument is pointer to pt_regs on kernel stack */=0A= + move a0,sp=0A= + /* Additional argument from sender passed in stack pad slot 4 */=0A= lw a1,PT_PADSLOT4(sp)=0A= - jalr t0=0A= - nop=0A= - j ret_from_irq=0A= - nop=0A= + PTR_LA ra,ret_from_irq=0A= + jr t0=0A= =0A= /*=0A= * Called from idle loop to provoke processing of queued IPIs=0A= diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c=0A= index 2e8e52c..1657d15 100644=0A= --- a/arch/mips/kernel/smtc.c=0A= +++ b/arch/mips/kernel/smtc.c=0A= @@ -269,7 +269,8 @@ void smtc_configure_tlb(void)=0A= * of their initialization in smtc_cpu_setup().=0A= */=0A= =0A= - tlbsiz =3D tlbsiz & 0x3f; /* MIPS32 limits TLB indices to 64 */=0A= + /* MIPS32 limits TLB indices to 64 */=0A= + if (tlbsiz > 64) tlbsiz =3D 64;=0A= cpu_data[0].tlbsize =3D tlbsiz;=0A= smtc_status |=3D SMTC_TLB_SHARED;=0A= =0A= ------=_NextPart_000_00F0_01C6EBA0.8FA9EA50-- From vagabon.xyz@gmail.com Mon Oct 9 12:57:09 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 12:57:15 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.186]:63416 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20038469AbWJIL5J (ORCPT ); Mon, 9 Oct 2006 12:57:09 +0100 Received: by nf-out-0910.google.com with SMTP id n29so595220nfc for ; Mon, 09 Oct 2006 04:57:07 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:reply-to:user-agent:mime-version:to:cc:subject:references:in-reply-to:content-type:content-transfer-encoding:from; b=t2qhhnyRc58b5DFycBt177FscFy5/3Ud3B95koXVgCNVhAKE7Ubj+htFA9i322H4g6F+WIa7valWAu4YHhbVc1pR8uiTqxnIHeKanUju3P4i7cU6eQ+nIyJhQCH6QnWCDvNtWwV3fdbHwe6Onvjy4jZA2Ir59VyWVcLqoa3m4BA= Received: by 10.49.20.5 with SMTP id x5mr1843565nfi; Mon, 09 Oct 2006 04:57:06 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.google.com with ESMTP id k9sm419797nfc.2006.10.09.04.57.06; Mon, 09 Oct 2006 04:57:06 -0700 (PDT) Message-ID: <452A3953.4060802@innova-card.com> Date: Mon, 09 Oct 2006 13:58:11 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: Thiemo Seufer CC: Franck Bui-Huu , Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() References: <45265BF0.8080103@innova-card.com> <20061006172153.GB4456@networkno.de> In-Reply-To: <20061006172153.GB4456@networkno.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12843 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 503 Lines: 20 Thiemo Seufer wrote: > Franck Bui-Huu wrote: >> >> - if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { >> + if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) { > > ISTR this failed on O2, where kernel+initrd are loaded into KSEG0 but the > PAGE_OFFSET is for XKPHYS. > I guess that you were meaning somthing like: LOADADDR = 0xffffffff80004000 PAGE_OFFSET = 0xa800000000000000 is that correct ? If so could you explain the choice of these values because I fail to understand it. Thanks Franck From ths@networkno.de Mon Oct 9 14:21:32 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 14:21:38 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:10734 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20038606AbWJINVc (ORCPT ); Mon, 9 Oct 2006 14:21:32 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 300FF445CA; Mon, 9 Oct 2006 15:21:29 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GWv4W-0006v2-Bj; Mon, 09 Oct 2006 14:21:32 +0100 Date: Mon, 9 Oct 2006 14:21:32 +0100 From: Thiemo Seufer To: Franck Bui-Huu Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() Message-ID: <20061009132131.GA18308@networkno.de> References: <45265BF0.8080103@innova-card.com> <20061006172153.GB4456@networkno.de> <452A3953.4060802@innova-card.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <452A3953.4060802@innova-card.com> User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12844 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Content-Length: 759 Lines: 29 Franck Bui-Huu wrote: > Thiemo Seufer wrote: > > Franck Bui-Huu wrote: > >> > >> - if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { > >> + if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) { > > > > ISTR this failed on O2, where kernel+initrd are loaded into KSEG0 but the > > PAGE_OFFSET is for XKPHYS. > > > > I guess that you were meaning somthing like: > > LOADADDR = 0xffffffff80004000 > PAGE_OFFSET = 0xa800000000000000 > > is that correct ? Yes. > If so could you explain the choice of these values > because I fail to understand it. It allows to load a 64-bit kernel in KSEG0, and use short 2-instruction symbol references there. At the same time, it allows access to more address space for memory and I/O than would fit in KSEG0. Thiemo From ralf@linux-mips.org Mon Oct 9 14:25:36 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 14:25:38 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:15539 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20039425AbWJINZg (ORCPT ); Mon, 9 Oct 2006 14:25:36 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k99DPgJe013949; Mon, 9 Oct 2006 14:25:42 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k99DPfe3013948; Mon, 9 Oct 2006 14:25:41 +0100 Date: Mon, 9 Oct 2006 14:25:41 +0100 From: Ralf Baechle To: Jonathan Day Cc: girish , Kaz Kylheku , linux-mips@linux-mips.org Subject: Re: CFE problem: starting secondary CPU. Message-ID: <20061009132540.GA4372@linux-mips.org> References: <9D189830-9D85-4360-BEEE-72A3D5510D77@gmail.com> <20061008213538.84372.qmail@web31502.mail.mud.yahoo.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20061008213538.84372.qmail@web31502.mail.mud.yahoo.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12845 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1151 Lines: 27 On Sun, Oct 08, 2006 at 02:35:37PM -0700, Jonathan Day wrote: > > would it be reasonable to choose couple of > > bootmonitors and support > > them under MIPS/Linux umbrella. even bootable linux > > would be a good > > choice. > > I can't see why not. For that matter, I can't imagine > it would be too hard to write the necessary flash > support to get LinuxBIOS working. The average firmware implementation contains alot of dark magic about hardware initialization. Producing a decent replacement is not trivial. The current situation is that every vendor has a favorite firmware implementation or sometimes even several depending on vintage or endianess. Repeated problems over the years have taught me the only productive way to live with most firmware implementations is to touch them as little as possible since the rules for coexistence with the OS are usually very weakly worded, inconsistent across platforms and the governing features generally are bugs, incompatibilites and lack of features. End of rant :-) How x86 or Linux centric is LinuxBIOS? Makers of Linux devices want to support other operating systems as well. Ralf From ralf@linux-mips.org Mon Oct 9 14:53:28 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 14:53:29 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:36800 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20039425AbWJINx2 (ORCPT ); Mon, 9 Oct 2006 14:53:28 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k99DrYjA030702; Mon, 9 Oct 2006 14:53:35 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k99DrXWK030701; Mon, 9 Oct 2006 14:53:33 +0100 Date: Mon, 9 Oct 2006 14:53:33 +0100 From: Ralf Baechle To: "Kevin D. Kissell" Cc: linux-mips@linux-mips.org, Atsushi Nemoto Subject: Re: [PATCH] ret_from_irq adjustment Message-ID: <20061009135332.GA14048@linux-mips.org> References: <20061009.012423.59032950.anemo@mba.ocn.ne.jp> <006501c6eb07$4fbf66c0$8003a8c0@Ulysses> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <006501c6eb07$4fbf66c0$8003a8c0@Ulysses> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12846 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1745 Lines: 42 On Sun, Oct 08, 2006 at 08:26:44PM +0200, Kevin D. Kissell wrote: > While setting up ra "by hand" and transferring control via the jr > is a reasonable optimization, you're otherwise breaking things for SMTC. > While the comments are misleading (they accurately described an earlier > version of the code), the function being called here is ipi_decode(), which > needs a pt_regs * in the first argument (hence the copy of the sp), and > the pointer to the IPI message descriptor in the second. > > Do you have access to a 34K to test changes to SMTC? I'd have > expected this one to have been pretty quickly fatal. Second reply after a closer look at the patch. ipi_decode() has lost it's pt_regs argument like most of the interrupt related functions, so Atushi's patch was right. Any interrupt handler that wants to get a pointer to the register frame can do so by calling get_irq_regs(). The cleanup did actually work so well I'm tempted to use the same strategy also for the CU and RI exception handlers which would make the FPU exception handler look a whole lot more friendly. So with Atsushi's patch applied VSMP and SMTC with only two TCs activated are working again. It still crashes with 5 TCs enabled: Cpu 1 $ 0 : 00000000 18102000 00000000 8041ed44 $ 4 : 00000000 00000000 8041ec88 00000000 $ 8 : 00000000 18001c00 8010de78 80430000 $12 : 80420000 fffffffb ffffffff 0000000a $16 : 00000000 00000001 8041ec04 8041ec08 $20 : 803b0000 8041ed40 80380000 18102000 $24 : 00000000 810c3b11 $28 : 810c2000 810c3b58 00000100 80108bdc Hi : 00000009 Lo : fbe7d600 epc : 80132b74 profile_tick+0x20/0xb4 Not tainted ra : 80108bdc local_timer_interrupt+0x10/0x30 Status: 1100a603 KERNEL EXL IE Ralf From vagabon.xyz@gmail.com Mon Oct 9 15:24:36 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 15:24:41 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.191]:7250 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20037847AbWJIOYg (ORCPT ); Mon, 9 Oct 2006 15:24:36 +0100 Received: by nf-out-0910.google.com with SMTP id n29so632115nfc for ; Mon, 09 Oct 2006 07:24:35 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:reply-to:user-agent:mime-version:to:cc:subject:references:in-reply-to:content-type:content-transfer-encoding:from; b=mcXztVW623J6V+lYkQGCezMBBzNtJw0JvCiGJYZdfG/uXBstSkPzL9ZuEXP8Ir3Ou62sgzFt2XmdK+STgu7nCPqzIBhvqWSBzxEk1ga5tfDfWtWUjY+qFvDu5balRQHFvXe4AFNH92U5kc2fyy9XOHdEmV6IIl8yYAixkhlwsEs= Received: by 10.49.8.10 with SMTP id l10mr2108562nfi; Mon, 09 Oct 2006 07:24:35 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.google.com with ESMTP id l27sm7943594nfa.2006.10.09.07.24.34; Mon, 09 Oct 2006 07:24:35 -0700 (PDT) Message-ID: <452A5BEA.2060500@innova-card.com> Date: Mon, 09 Oct 2006 16:25:46 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: Thiemo Seufer CC: Franck Bui-Huu , Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() References: <45265BF0.8080103@innova-card.com> <20061006172153.GB4456@networkno.de> <452A3953.4060802@innova-card.com> <20061009132131.GA18308@networkno.de> In-Reply-To: <20061009132131.GA18308@networkno.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12847 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1275 Lines: 44 Thiemo Seufer wrote: > Franck Bui-Huu wrote: >> Thiemo Seufer wrote: >>> Franck Bui-Huu wrote: >>>> - if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { >>>> + if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) { >>> ISTR this failed on O2, where kernel+initrd are loaded into KSEG0 but the >>> PAGE_OFFSET is for XKPHYS. >>> >> I guess that you were meaning somthing like: >> >> LOADADDR = 0xffffffff80004000 >> PAGE_OFFSET = 0xa800000000000000 >> >> is that correct ? > > Yes. > >> If so could you explain the choice of these values >> because I fail to understand it. > > It allows to load a 64-bit kernel in KSEG0, sorry to be ignorant of 64 bit kernels, but what's the point to load them in KSEG0. > and use short 2-instruction symbol references there. do you mean "it allows to use only 2 'lui' instructions to load a symbol address into a register" ? Futhermore I don't see how some part of the kernel convert virtual address into a physical one with such values. For example in setup.c, the function resource_init() does: code_resource.start = virt_to_phys(&_text); code_resource.end = virt_to_phys(&_etext) - 1; data_resource.start = virt_to_phys(&_etext); data_resource.end = virt_to_phys(&_edata) - 1; How does it work in this case ? Thanks Franck From anemo@mba.ocn.ne.jp Mon Oct 9 15:38:12 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 15:38:17 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:23014 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20039672AbWJIOiM (ORCPT ); Mon, 9 Oct 2006 15:38:12 +0100 Received: from localhost (p4240-ipad02funabasi.chiba.ocn.ne.jp [61.207.151.240]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 8BF1CA68B; Mon, 9 Oct 2006 23:38:07 +0900 (JST) Date: Mon, 09 Oct 2006 23:40:22 +0900 (JST) Message-Id: <20061009.234022.07643427.anemo@mba.ocn.ne.jp> To: ralf@linux-mips.org Cc: KevinK@mips.com, linux-mips@linux-mips.org Subject: Re: [PATCH] ret_from_irq adjustment From: Atsushi Nemoto In-Reply-To: <20061009135332.GA14048@linux-mips.org> References: <20061009.012423.59032950.anemo@mba.ocn.ne.jp> <006501c6eb07$4fbf66c0$8003a8c0@Ulysses> <20061009135332.GA14048@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12848 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1578 Lines: 44 On Mon, 9 Oct 2006 14:53:33 +0100, Ralf Baechle wrote: > ipi_decode() has lost it's pt_regs argument like most of the interrupt > related functions, so Atushi's patch was right. Any interrupt handler > that wants to get a pointer to the register frame can do so by calling > get_irq_regs(). Yes, excuse me for a terse description. > So with Atsushi's patch applied VSMP and SMTC with only two TCs activated > are working again. It still crashes with 5 TCs enabled: > > Cpu 1 > $ 0 : 00000000 18102000 00000000 8041ed44 > $ 4 : 00000000 00000000 8041ec88 00000000 > $ 8 : 00000000 18001c00 8010de78 80430000 > $12 : 80420000 fffffffb ffffffff 0000000a > $16 : 00000000 00000001 8041ec04 8041ec08 > $20 : 803b0000 8041ed40 80380000 18102000 > $24 : 00000000 810c3b11 > $28 : 810c2000 810c3b58 00000100 80108bdc > Hi : 00000009 > Lo : fbe7d600 > epc : 80132b74 profile_tick+0x20/0xb4 Not tainted > ra : 80108bdc local_timer_interrupt+0x10/0x30 > Status: 1100a603 KERNEL EXL IE Hmm, this would be because local_timer_interrupt was called from ipi_decode(). Is this a proper fix? diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index 1cb9441..20938a4 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S @@ -101,7 +101,9 @@ FEXPORT(__smtc_ipi_vector) lw t0,PT_PADSLOT5(sp) /* Argument from sender passed in stack pad slot 4 */ lw a0,PT_PADSLOT4(sp) - PTR_LA ra, _ret_from_irq + LONG_L s0, TI_REGS($28) + LONG_S sp, TI_REGS($28) + PTR_LA ra, ret_from_irq jr t0 /* From ths@networkno.de Mon Oct 9 15:58:18 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 15:58:23 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:3497 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20039675AbWJIO6S (ORCPT ); Mon, 9 Oct 2006 15:58:18 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id DFDF1446E2; Mon, 9 Oct 2006 16:58:16 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GWwa9-0007Np-SY; Mon, 09 Oct 2006 15:58:17 +0100 Date: Mon, 9 Oct 2006 15:58:17 +0100 From: Thiemo Seufer To: Franck Bui-Huu Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() Message-ID: <20061009145817.GB18308@networkno.de> References: <45265BF0.8080103@innova-card.com> <20061006172153.GB4456@networkno.de> <452A3953.4060802@innova-card.com> <20061009132131.GA18308@networkno.de> <452A5BEA.2060500@innova-card.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <452A5BEA.2060500@innova-card.com> User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12849 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Content-Length: 1380 Lines: 41 Franck Bui-Huu wrote: [snip] > >> If so could you explain the choice of these values > >> because I fail to understand it. > > > > It allows to load a 64-bit kernel in KSEG0, > > sorry to be ignorant of 64 bit kernels, but what's the point > to load them in KSEG0. Smaller code with better performance. > > and use short 2-instruction symbol references there. > > do you mean "it allows to use only 2 'lui' instructions to load > a symbol address into a register" ? It allows a 2-instruction "lui ; addiu" sequence instead of a 6-instruction "lui ; lui ; addiu ; addiu ; dsll32 ; addu" sequence. > Futhermore I don't see how some part of the kernel convert virtual > address into a physical one with such values. For example in setup.c, > the function resource_init() does: > > code_resource.start = virt_to_phys(&_text); > code_resource.end = virt_to_phys(&_etext) - 1; > data_resource.start = virt_to_phys(&_etext); > data_resource.end = virt_to_phys(&_edata) - 1; > > How does it work in this case ? Those are addresses in 64-bit space, no special handling is needed there. The same doesn't hold for the initrd addresses supplied by the (32-bit) firmware. The firmware doesn't convert the kernel parameters to 64-bit values because the O2 kernel used to allow a pure 32-bit build, and the firmware can't find out what's actually inside the object file. Thiemo From vagabon.xyz@gmail.com Mon Oct 9 16:29:21 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 16:29:26 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.185]:42869 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20039676AbWJIP3V (ORCPT ); Mon, 9 Oct 2006 16:29:21 +0100 Received: by nf-out-0910.google.com with SMTP id n29so647944nfc for ; Mon, 09 Oct 2006 08:29:20 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:reply-to:user-agent:mime-version:to:cc:subject:references:in-reply-to:content-type:content-transfer-encoding:from; b=BqtHAU0VnAvgqE4WF7DxFVYbw+GkRBRkWa1RCkOdhBiY7lsnknZ0k0qaMEPVjkler0vqt3CZzKL571GMNV7DV/pb4pPsQJ2G61DZJ2vqm985OAoc+4oJBsjaphWcXXKWKP79xvSC/9Qj6HAzMyn6SrsLvinQealGAlqMm3fa0UU= Received: by 10.48.48.15 with SMTP id v15mr10393266nfv; Mon, 09 Oct 2006 08:29:20 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.google.com with ESMTP id k9sm825221nfc.2006.10.09.08.29.19; Mon, 09 Oct 2006 08:29:20 -0700 (PDT) Message-ID: <452A6B16.60507@innova-card.com> Date: Mon, 09 Oct 2006 17:30:30 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: Thiemo Seufer CC: Franck Bui-Huu , Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() References: <45265BF0.8080103@innova-card.com> <20061006172153.GB4456@networkno.de> <452A3953.4060802@innova-card.com> <20061009132131.GA18308@networkno.de> <452A5BEA.2060500@innova-card.com> <20061009145817.GB18308@networkno.de> In-Reply-To: <20061009145817.GB18308@networkno.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12850 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1897 Lines: 61 Thiemo Seufer wrote: > Franck Bui-Huu wrote: >> sorry to be ignorant of 64 bit kernels, but what's the point >> to load them in KSEG0. > > Smaller code with better performance. > you mean we get smaller code _only_ by using the short 2 instructions you described below ? >>> and use short 2-instruction symbol references there. >> do you mean "it allows to use only 2 'lui' instructions to load >> a symbol address into a register" ? > > It allows a 2-instruction "lui ; addiu" sequence instead of a > 6-instruction "lui ; lui ; addiu ; addiu ; dsll32 ; addu" sequence. > [snip] >> >> code_resource.start = virt_to_phys(&_text); >> code_resource.end = virt_to_phys(&_etext) - 1; >> data_resource.start = virt_to_phys(&_etext); >> data_resource.end = virt_to_phys(&_edata) - 1; >> >> How does it work in this case ? > > Those are addresses in 64-bit space, no special handling is needed > there. hm I'missing something there. Let's say that '&_text' is in KSEG0 and is equal to 0xffffffff80000000. In this case virt_to_phys() returns 0x57ffffff80000000 (with PAGE_OFFSET = 0xa800000000000000). Is this physical address correct ?? > > The same doesn't hold for the initrd addresses supplied by the (32-bit) > firmware. The firmware doesn't convert the kernel parameters to 64-bit > values because the O2 kernel used to allow a pure 32-bit build, and the > firmware can't find out what's actually inside the object file. > This should be already handled by this code taken from setup.c: static int __init rd_start_early(char *p) { unsigned long start = memparse(p, &p); #ifdef CONFIG_64BIT /* HACK: Guess if the sign extension was forgotten */ if (start > 0x0000000080000000 && start < 0x00000000ffffffff) start |= 0xffffffff00000000UL; #endif initrd_start = start; initrd_end += start; return 0; } Thanks Franck From anemo@mba.ocn.ne.jp Mon Oct 9 16:49:35 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 16:49:40 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:36329 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20039682AbWJIPtf (ORCPT ); Mon, 9 Oct 2006 16:49:35 +0100 Received: from localhost (p4240-ipad02funabasi.chiba.ocn.ne.jp [61.207.151.240]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 618C6AF92; Tue, 10 Oct 2006 00:49:27 +0900 (JST) Date: Tue, 10 Oct 2006 00:51:42 +0900 (JST) Message-Id: <20061010.005142.03977034.anemo@mba.ocn.ne.jp> To: ths@networkno.de Cc: vagabon.xyz@gmail.com, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() From: Atsushi Nemoto In-Reply-To: <20061009145817.GB18308@networkno.de> References: <20061009132131.GA18308@networkno.de> <452A5BEA.2060500@innova-card.com> <20061009145817.GB18308@networkno.de> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12851 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 476 Lines: 13 On Mon, 9 Oct 2006 15:58:17 +0100, Thiemo Seufer wrote: > > do you mean "it allows to use only 2 'lui' instructions to load > > a symbol address into a register" ? > > It allows a 2-instruction "lui ; addiu" sequence instead of a > 6-instruction "lui ; lui ; addiu ; addiu ; dsll32 ; addu" sequence. Just for clarification: IIRC this optimization needs somewhat up-to-date binutils/gcc and is not enabled on current lmo kernel, right? --- Atsushi Nemoto From ralf@linux-mips.org Mon Oct 9 17:02:14 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 17:02:15 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:10176 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20039692AbWJIQCO (ORCPT ); Mon, 9 Oct 2006 17:02:14 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k99G2Icj007876; Mon, 9 Oct 2006 17:02:21 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k99G2Gf1007875; Mon, 9 Oct 2006 17:02:16 +0100 Date: Mon, 9 Oct 2006 17:02:15 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, mlachwani@mvista.com Subject: Re: [PATCH] Make sure cpu_has_fpu is used only in atomic context Message-ID: <20061009160215.GA7642@linux-mips.org> References: <44F715F2.7050305@mvista.com> <20060901.122527.63741495.nemoto@toshiba-tops.co.jp> <20060901.170817.118968734.nemoto@toshiba-tops.co.jp> <20061009.001001.74753036.anemo@mba.ocn.ne.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20061009.001001.74753036.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12852 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 292 Lines: 9 On Mon, Oct 09, 2006 at 12:10:01AM +0900, Atsushi Nemoto wrote: > Make sure cpu_has_fpu (which uses smp_processor_id()) is used > only in atomic context. It's awfully ugly to have an increasing number of preemption kludgery around but it's not so trivial to avoid unfortunately ... Ralf From sshtylyov@ru.mvista.com Mon Oct 9 17:03:33 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 17:03:35 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:17446 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20039692AbWJIQDd (ORCPT ); Mon, 9 Oct 2006 17:03:33 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 1D0DA3ECC; Mon, 9 Oct 2006 09:03:03 -0700 (PDT) Message-ID: <452A72B9.80109@ru.mvista.com> Date: Mon, 09 Oct 2006 20:03:05 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Ralf Baechle , Linux-MIPS Subject: [PATCH] Alchemy: make OSS I2S driver build (resend) Content-Type: multipart/mixed; boundary="------------010205050805090509000102" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12853 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1313 Lines: 39 This is a multi-part message in MIME format. --------------010205050805090509000102 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Alchemy OSS I2S driver (sound/oss/au1550_i2s.c) doesn't build if I2C driver (drivers/i2c/busses/i2c_au1550.c) is not enabled because pb1550_wm_codec_write() is defined there (a dirty hack). So, mark that dependency in sound/oss/Kconfig... Signed-off-by: Sergei Shtylyov --------------010205050805090509000102 Content-Type: text/plain; name="Au1550-I2S-depends-on-I2C.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="Au1550-I2S-depends-on-I2C.patch" diff --git a/sound/oss/Kconfig b/sound/oss/Kconfig index b7bd8ab..07eb4a7 100644 Index: linux-mips/sound/oss/Kconfig =================================================================== --- linux-mips.orig/sound/oss/Kconfig +++ linux-mips/sound/oss/Kconfig @@ -121,6 +121,9 @@ config SOUND_AU1550_AC97 config SOUND_AU1550_I2S tristate "Au1550 I2S Sound" depends on SOUND_PRIME && SOC_AU1550 + # Weird I2S driver needs I2C driver to talk to the codec... + select I2C + select I2C_AU1550 config SOUND_TRIDENT tristate "Trident 4DWave DX/NX, SiS 7018 or ALi 5451 PCI Audio Core" --------------010205050805090509000102-- From igalch@gmail.com Mon Oct 9 17:21:19 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 17:21:21 +0100 (BST) Received: from wr-out-0506.google.com ([64.233.184.234]:17121 "EHLO wr-out-0506.google.com") by ftp.linux-mips.org with ESMTP id S20039694AbWJIQVT (ORCPT ); Mon, 9 Oct 2006 17:21:19 +0100 Received: by wr-out-0506.google.com with SMTP id 55so311087wri for ; Mon, 09 Oct 2006 09:21:18 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type; b=VSlQ4NPkQfCz81yqLkagikMkq2EPupd3TMkg/+Z7GDQ9mCro7/lGejhimQ5m29W7S9VJKx3/Hqft+NFJgqU4NkuMgRkcjBW9ltGUedwJaBJmueBBeq7m2UN50OdlYeR/QFJopDKAAHCRYHr2XK0WM4M/n9uNrtQ7+BabIgXWb2I= Received: by 10.90.104.14 with SMTP id b14mr2791707agc; Mon, 09 Oct 2006 09:21:18 -0700 (PDT) Received: by 10.90.66.14 with HTTP; Mon, 9 Oct 2006 09:21:18 -0700 (PDT) Message-ID: <103e245f0610090921g5348dbd3hd806129e75668763@mail.gmail.com> Date: Mon, 9 Oct 2006 18:21:18 +0200 From: "Igal Chernobelsky" To: linux-mips@linux-mips.org Subject: Math-emu issue MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_38565_29102388.1160410878107" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12854 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: igalch@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1077 Lines: 26 ------=_Part_38565_29102388.1160410878107 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline I started to use LinuxThread in Linux 2.4 (version 2.4.17_mvl21-malta-mips_fp_le) and sometimes encounter a problem of arithmetic exception while performing dividing of two variables of double type. Our MIPS core does not include FPU coprosessor so math-emu is used. Is there any known problems/patches for kernel math emulation when LinuxThreads is used? ------=_Part_38565_29102388.1160410878107 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline I started to use LinuxThread in Linux 2.4 (version 2.4.17_mvl21-malta-mips_fp_le) and sometimes encounter a problem of arithmetic exception while performing dividing of two variables of double type. Our MIPS core does not include FPU coprosessor so math-emu is used. Is there any known problems/patches for kernel math emulation when LinuxThreads is used?

------=_Part_38565_29102388.1160410878107-- From igalch@gmail.com Mon Oct 9 17:29:46 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 17:29:47 +0100 (BST) Received: from wx-out-0506.google.com ([66.249.82.236]:49733 "EHLO wx-out-0506.google.com") by ftp.linux-mips.org with ESMTP id S20039698AbWJIQ3q (ORCPT ); Mon, 9 Oct 2006 17:29:46 +0100 Received: by wx-out-0506.google.com with SMTP id h30so1732884wxd for ; Mon, 09 Oct 2006 09:29:44 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type; b=rvJO1sZvyksVtXlou4hArCmdR7M1x5M0z+8EB5URQVvwIjin550X5aWPagZsIpcYqiW8JZtJk59uLseEF8G+crYVUUsAmcTYXMbyR3kcAJWabvWxN79QlQFoYVpYRLz1QyL9TXxSVRKgfB48bySR4kONyqhweX7TudOfQXZI66Y= Received: by 10.90.79.6 with SMTP id c6mr2807661agb; Mon, 09 Oct 2006 09:29:44 -0700 (PDT) Received: by 10.90.66.14 with HTTP; Mon, 9 Oct 2006 09:29:44 -0700 (PDT) Message-ID: <103e245f0610090929i35c2033budaac2fae10ec7277@mail.gmail.com> Date: Mon, 9 Oct 2006 18:29:44 +0200 From: "Igal Chernobelsky" To: linux-mips@linux-mips.org Subject: Math-Emu Issue MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_38729_17194111.1160411384634" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12855 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: igalch@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1068 Lines: 25 ------=_Part_38729_17194111.1160411384634 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline I started to use LinuxThread in Linux 2.4 (version 2.4.17_mvl21-malta-mips_fp_le) and sometimes encounter a problem of arithmetic exception while performing dividing of two variables of double type. Our MIPS core does not include FPU coprocessor so math-emu is used. Is there any known problems/patches for kernel math emulation when LinuxThreads is used? ------=_Part_38729_17194111.1160411384634 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline I started to use LinuxThread in Linux 2.4 (version 2.4.17_mvl21-malta-mips_fp_le) and sometimes encounter a problem of arithmetic exception while performing dividing of two variables of double type. Our MIPS core does not include FPU coprocessor so math-emu is used. Is there any known problems/patches for kernel math emulation when LinuxThreads is used? ------=_Part_38729_17194111.1160411384634-- From ths@networkno.de Mon Oct 9 17:59:18 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 17:59:20 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:37090 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20039417AbWJIQ7S (ORCPT ); Mon, 9 Oct 2006 17:59:18 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id F3E0144641; Mon, 9 Oct 2006 18:59:16 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GWyTI-00086t-5s; Mon, 09 Oct 2006 17:59:20 +0100 Date: Mon, 9 Oct 2006 17:59:20 +0100 From: Thiemo Seufer To: Atsushi Nemoto Cc: vagabon.xyz@gmail.com, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() Message-ID: <20061009165920.GC18308@networkno.de> References: <20061009132131.GA18308@networkno.de> <452A5BEA.2060500@innova-card.com> <20061009145817.GB18308@networkno.de> <20061010.005142.03977034.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20061010.005142.03977034.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12856 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Content-Length: 634 Lines: 17 Atsushi Nemoto wrote: > On Mon, 9 Oct 2006 15:58:17 +0100, Thiemo Seufer wrote: > > > do you mean "it allows to use only 2 'lui' instructions to load > > > a symbol address into a register" ? > > > > It allows a 2-instruction "lui ; addiu" sequence instead of a > > 6-instruction "lui ; lui ; addiu ; addiu ; dsll32 ; addu" sequence. > > Just for clarification: IIRC this optimization needs somewhat > up-to-date binutils/gcc and is not enabled on current lmo kernel, > right? For old toolchains there used to be a gruesome hack (which AFAIR broke at some point), for modern toolchains there's -msym32. Thiemo From imipak@yahoo.com Mon Oct 9 20:12:59 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 20:13:01 +0100 (BST) Received: from web31506.mail.mud.yahoo.com ([68.142.198.135]:10098 "HELO web31506.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20039732AbWJITM7 (ORCPT ); Mon, 9 Oct 2006 20:12:59 +0100 Received: (qmail 13895 invoked by uid 60001); 9 Oct 2006 19:12:52 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:Cc:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=qJlMHlzL5eySTVMnY6tZANn2V5SSSAjyfPmPjyttluN41BzfQquaFkvsfBfQmUE+9VN3icQpKNpWSCdSMkn5YkRXjzBcC5kGphCeCy+qOaNZhkCQ7BmcEEDbIynDCeFA6ed9AUhLz96YIHYGM6SYchZRTdxvJ3TTkEftJ9wg/cc= ; Message-ID: <20061009191252.13893.qmail@web31506.mail.mud.yahoo.com> Received: from [70.103.67.194] by web31506.mail.mud.yahoo.com via HTTP; Mon, 09 Oct 2006 12:12:52 PDT Date: Mon, 9 Oct 2006 12:12:52 -0700 (PDT) From: Jonathan Day Subject: Re: CFE problem: starting secondary CPU. To: Ralf Baechle Cc: girish , Kaz Kylheku , linux-mips@linux-mips.org In-Reply-To: <20061009132540.GA4372@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12857 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips Content-Length: 1191 Lines: 35 --- Ralf Baechle wrote: > The average firmware implementation contains alot of > dark magic about > hardware initialization. Producing a decent > replacement is not trivial. Ok, does anyone here know if Voldemort is a good code hacker? :) (snip) > How x86 or Linux centric is LinuxBIOS? Makers of > Linux devices want to > support other operating systems as well. LinuxBIOS is listed as supporting Linux (!), Plan 9 and Windows 2000. They don't support any of the *BSDs, as there's apparently some BIOS calls in their bootloaders and LinuxBIOS doesn't do BIOS calls. The total intrusion into Linux is a 10-line hook and there obviously can't even be that for Windows, so I think most other OS' should be ok with it. The supported motherboards include your usual x86 stuff (including Opterons, which I'm taking as meaning it'll work on 64-bit systems) and PowerPC chips. The FAQ also mentions the Alpha processor, but I didn't see any examples amongst the listed vendors or supported motherboards. Jonathan __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From mark.e.mason@broadcom.com Mon Oct 9 20:42:39 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Oct 2006 20:42:43 +0100 (BST) Received: from mms2.broadcom.com ([216.31.210.18]:6160 "EHLO mms2.broadcom.com") by ftp.linux-mips.org with ESMTP id S20039691AbWJITmj convert rfc822-to-8bit (ORCPT ); Mon, 9 Oct 2006 20:42:39 +0100 Received: from 10.10.64.154 by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.2.2)); Mon, 09 Oct 2006 12:42:25 -0700 X-Server-Uuid: 79DB55DB-3CB4-423E-BEDB-D0F268247E63 Received: by mail-irva-10.broadcom.com (Postfix, from userid 47) id D50222AF; Mon, 9 Oct 2006 12:42:24 -0700 (PDT) Received: from mail-irva-8.broadcom.com (mail-irva-8 [10.10.64.221]) by mail-irva-10.broadcom.com (Postfix) with ESMTP id B08032AE; Mon, 9 Oct 2006 12:42:24 -0700 (PDT) Received: from mail-sj1-12.sj.broadcom.com (mail-sj1-12.sj.broadcom.com [10.16.128.215]) by mail-irva-8.broadcom.com (MOS 3.7.5a-GA) with ESMTP id EHC21974; Mon, 9 Oct 2006 12:42:24 -0700 (PDT) Received: from NT-SJCA-0750.brcm.ad.broadcom.com (nt-sjca-0750 [10.16.192.220]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 3A80C20501; Mon, 9 Oct 2006 12:42:24 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Subject: RE: CFE problem: starting secondary CPU. Date: Mon, 9 Oct 2006 12:42:23 -0700 Message-ID: <7E000E7F06B05C49BDBB769ADAF44D07011FE3A6@NT-SJCA-0750.brcm.ad.broadcom.com> In-Reply-To: <66910A579C9312469A7DF9ADB54A8B7D3E7324@exchange.ZeugmaSystems.local> Thread-Topic: CFE problem: starting secondary CPU. Thread-Index: Acbpo1bBhY91FwuRSxSoPT5JCpbUywCN3gGQ From: "Mark E Mason" To: "Kaz Kylheku" , linux-mips@linux-mips.org cc: mason@broadcom.com X-TMWD-Spam-Summary: TS=20061009194227; SEV=2.0.2; DFV=A2006100907; IFV=2.0.4,4.0-8; RPD=4.00.0004; ENG=IBF; RPDID=303030312E30413031303230322E34353241413542462E303035312D412D; CAT=NONE; CON=NONE X-MMS-Spam-Filter-ID: A2006100907_4.00.0004_4.0-8 X-WSS-ID: 693479AB2I02791255-01-01 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12858 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mark.e.mason@broadcom.com Precedence: bulk X-list: linux-mips Content-Length: 531 Lines: 19 Hello, > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Kaz Kylheku > Sent: Friday, October 06, 2006 4:59 PM > To: linux-mips@linux-mips.org > Subject: CFE problem: starting secondary CPU. > > Anyone seen a problem like this? cfe_cpu_start() works fine on a > 32 bit kernel, but not on 64. Which version of CFE are you using? We'd seen something like this with the 1480 eval boards, some specific versions of CFE, and 64-bit SMP Linux. Thx, Mark From ralf@linux-mips.org Tue Oct 10 00:24:54 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 00:24:55 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:64988 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20039764AbWJIXYy (ORCPT ); Tue, 10 Oct 2006 00:24:54 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k99NP101003191; Tue, 10 Oct 2006 00:25:01 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k99NOuB9003169; Tue, 10 Oct 2006 00:24:56 +0100 Date: Tue, 10 Oct 2006 00:24:56 +0100 From: Ralf Baechle To: Igal Chernobelsky Cc: linux-mips@linux-mips.org Subject: Re: Math-emu issue Message-ID: <20061009232455.GA26855@linux-mips.org> References: <103e245f0610090921g5348dbd3hd806129e75668763@mail.gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <103e245f0610090921g5348dbd3hd806129e75668763@mail.gmail.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12859 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 620 Lines: 14 On Mon, Oct 09, 2006 at 06:21:18PM +0200, Igal Chernobelsky wrote: > I started to use LinuxThread in Linux 2.4 (version > 2.4.17_mvl21-malta-mips_fp_le) and sometimes encounter a problem of > arithmetic exception while performing dividing of two variables of double > type. Our MIPS core does not include FPU coprosessor so math-emu is used. Is > there any known problems/patches for kernel math emulation when LinuxThreads > is used? This is an extremly old kernel; from my own experience I recall we hit heap and piles of bugs in that particular particular MV release so I can only recommend you to upgrade. Ralf From yoichi_yuasa@tripeaks.co.jp Tue Oct 10 08:56:15 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 08:56:17 +0100 (BST) Received: from mo30.po.2iij.net ([210.128.50.53]:36359 "EHLO mo30.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20038662AbWJJH4P (ORCPT ); Tue, 10 Oct 2006 08:56:15 +0100 Received: by mo.po.2iij.net (mo30) id k9A7uCn1096889; Tue, 10 Oct 2006 16:56:12 +0900 (JST) Received: from localhost.localdomain (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (mbox31) id k9A7uAqM051471 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 10 Oct 2006 16:56:11 +0900 (JST) Date: Tue, 10 Oct 2006 16:56:11 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH] fix timer setup for Jazz Message-Id: <20061010165611.2ee77306.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12860 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 705 Lines: 20 Hi Ralf, This patch has fixed timer setup function name for Jazz. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/jazz/setup.c mips/arch/mips/jazz/setup.c --- mips-orig/arch/mips/jazz/setup.c 2006-10-10 11:36:15.066873500 +0900 +++ mips/arch/mips/jazz/setup.c 2006-10-10 15:01:30.833109250 +0900 @@ -37,7 +37,7 @@ extern void jazz_machine_restart(char *c extern void jazz_machine_halt(void); extern void jazz_machine_power_off(void); -void __init plat_time_init(struct irqaction *irq) +void __init plat_timer_setup(struct irqaction *irq) { /* set the clock to 100 Hz */ r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9); From anemo@mba.ocn.ne.jp Tue Oct 10 09:49:07 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 09:49:10 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:38505 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20039798AbWJJItH (ORCPT ); Tue, 10 Oct 2006 09:49:07 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Tue, 10 Oct 2006 17:49:05 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id A87D84194C; Tue, 10 Oct 2006 17:49:02 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 9B134418D8; Tue, 10 Oct 2006 17:49:02 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k9A8n1W0025808; Tue, 10 Oct 2006 17:49:01 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Tue, 10 Oct 2006 17:49:01 +0900 (JST) Message-Id: <20061010.174901.25477190.nemoto@toshiba-tops.co.jp> To: ths@networkno.de Cc: vagabon.xyz@gmail.com, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() From: Atsushi Nemoto In-Reply-To: <20061009165920.GC18308@networkno.de> References: <20061009145817.GB18308@networkno.de> <20061010.005142.03977034.anemo@mba.ocn.ne.jp> <20061009165920.GC18308@networkno.de> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12861 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 640 Lines: 15 On Mon, 9 Oct 2006 17:59:20 +0100, Thiemo Seufer wrote: > > Just for clarification: IIRC this optimization needs somewhat > > up-to-date binutils/gcc and is not enabled on current lmo kernel, > > right? > > For old toolchains there used to be a gruesome hack (which AFAIR broke > at some point), for modern toolchains there's -msym32. Hmm, I found that the -msym32 is enabled if BUILD_ELF64 was not selected, since 2.6.17. But does CONFIG_BUILD_ELF64=n really work for modules? While MAP_BASE is 0xc000000000000000 for most 64-bit platforms, I suppose modules should not be compiled with -msym32. --- Atsushi Nemoto From anemo@mba.ocn.ne.jp Tue Oct 10 14:11:46 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 14:11:48 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:59859 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20039873AbWJJNLq (ORCPT ); Tue, 10 Oct 2006 14:11:46 +0100 Received: from localhost (p3213-ipad213funabasi.chiba.ocn.ne.jp [124.85.68.213]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 33AF9B718; Tue, 10 Oct 2006 22:11:40 +0900 (JST) Date: Tue, 10 Oct 2006 22:13:55 +0900 (JST) Message-Id: <20061010.221355.119270972.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Do not use -msym32 option for modules. From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12862 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 691 Lines: 21 On 64-bit kernel, modules are loaded into XKSEG for now. While XKSEG address is not a sign-extended 32-bit address, we can not use -msym32 option. Signed-off-by: Atsushi Nemoto diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 2124350..6691086 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -63,7 +63,9 @@ cflags-y += -mabi=64 ifdef CONFIG_BUILD_ELF64 cflags-y += $(call cc-option,-mno-explicit-relocs) else -cflags-y += $(call cc-option,-msym32) +# -msym32 can not be used for modules since they are loaded into XKSEG +CFLAGS_MODULE += $(call cc-option,-mno-explicit-relocs) +CFLAGS_KERNEL += $(call cc-option,-msym32) endif endif From anemo@mba.ocn.ne.jp Tue Oct 10 14:44:41 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 14:44:43 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:51710 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20039881AbWJJNol (ORCPT ); Tue, 10 Oct 2006 14:44:41 +0100 Received: from localhost (p3213-ipad213funabasi.chiba.ocn.ne.jp [124.85.68.213]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 2270E46BD; Tue, 10 Oct 2006 22:44:37 +0900 (JST) Date: Tue, 10 Oct 2006 22:46:52 +0900 (JST) Message-Id: <20061010.224652.53335173.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] optimize and cleanup get_saved_sp, set_saved_sp From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12863 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 2669 Lines: 105 If CONFIG_BUILD_ELF64 was not selected and gcc had -msym32 option (i.e. 4.0 or newer), there is no point to use %highest, %higher for kernel symbols. This patch also fixes 64-bit SMTC version of get_saved_sp() which is broken but harmless since there is no such CPUs for now. A bonus is set_saved_sp() and SMP version of get_saved_sp() are more readable now. Signed-off-by: Atsushi Nemoto diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 158a4cd..1fae5dc 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -59,69 +59,43 @@ #endif .endm #ifdef CONFIG_SMP - .macro get_saved_sp /* SMP variation */ -#ifdef CONFIG_32BIT #ifdef CONFIG_MIPS_MT_SMTC - .set mips32 - mfc0 k0, CP0_TCBIND; - .set mips0 - lui k1, %hi(kernelsp) - srl k0, k0, 19 - /* No need to shift down and up to clear bits 0-1 */ +#define PTEBASE_SHIFT 19 /* TCBIND */ #else - mfc0 k0, CP0_CONTEXT - lui k1, %hi(kernelsp) - srl k0, k0, 23 -#endif - addu k1, k0 - LONG_L k1, %lo(kernelsp)(k1) +#define PTEBASE_SHIFT 23 /* CONTEXT */ #endif -#ifdef CONFIG_64BIT + .macro get_saved_sp /* SMP variation */ #ifdef CONFIG_MIPS_MT_SMTC - .set mips64 - mfc0 k0, CP0_TCBIND; - .set mips0 - lui k0, %highest(kernelsp) - dsrl k1, 19 - /* No need to shift down and up to clear bits 0-2 */ + mfc0 k0, CP0_TCBIND #else - MFC0 k1, CP0_CONTEXT - lui k0, %highest(kernelsp) - dsrl k1, 23 - daddiu k0, %higher(kernelsp) - dsll k0, k0, 16 - daddiu k0, %hi(kernelsp) - dsll k0, k0, 16 -#endif /* CONFIG_MIPS_MT_SMTC */ - daddu k1, k1, k0 + MFC0 k0, CP0_CONTEXT +#endif +#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) + lui k1, %highest(kernelsp) + daddiu k1, %higher(kernelsp) + dsll k1, 16 + daddiu k1, %hi(kernelsp) + dsll k1, 16 +#else + lui k1, %hi(kernelsp) +#endif + LONG_SRL k0, PTEBASE_SHIFT + LONG_ADDU k1, k0 LONG_L k1, %lo(kernelsp)(k1) -#endif /* CONFIG_64BIT */ .endm .macro set_saved_sp stackp temp temp2 -#ifdef CONFIG_32BIT -#ifdef CONFIG_MIPS_MT_SMTC - mfc0 \temp, CP0_TCBIND - srl \temp, 19 -#else - mfc0 \temp, CP0_CONTEXT - srl \temp, 23 -#endif -#endif -#ifdef CONFIG_64BIT #ifdef CONFIG_MIPS_MT_SMTC mfc0 \temp, CP0_TCBIND - dsrl \temp, 19 #else MFC0 \temp, CP0_CONTEXT - dsrl \temp, 23 -#endif #endif + LONG_SRL \temp, PTEBASE_SHIFT LONG_S \stackp, kernelsp(\temp) .endm #else .macro get_saved_sp /* Uniprocessor variation */ -#ifdef CONFIG_64BIT +#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4) lui k1, %highest(kernelsp) daddiu k1, %higher(kernelsp) dsll k1, k1, 16 From vagabon.xyz@gmail.com Tue Oct 10 14:48:21 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 14:48:23 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.189]:11364 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20039871AbWJJNsV (ORCPT ); Tue, 10 Oct 2006 14:48:21 +0100 Received: by nf-out-0910.google.com with SMTP id n29so281833nfc for ; Tue, 10 Oct 2006 06:48:19 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:reply-to:user-agent:mime-version:to:cc:subject:references:in-reply-to:content-type:content-transfer-encoding:from; b=YjULFD4IURTJPzO3ieMUL/MS0Jpw7vzqfU7cEJQg/+4FD5PVkCi6Nw2J3uLZ58q5NTF5kxXqFHSmWEqM7DyTv3XLDILtVhrvmSvbinuq6usRxDwK/8Bo5QHVDqi+MBqj0DGP+h7gZ03C2FHjr7neX7vIjWJLZYVfZ9JnoY74gZ4= Received: by 10.49.20.5 with SMTP id x5mr1457638nfi; Tue, 10 Oct 2006 06:48:19 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.google.com with ESMTP id h1sm1957236nfe.2006.10.10.06.48.19; Tue, 10 Oct 2006 06:48:19 -0700 (PDT) Message-ID: <452BA4E7.30901@innova-card.com> Date: Tue, 10 Oct 2006 15:49:27 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: Atsushi Nemoto CC: ths@networkno.de, vagabon.xyz@gmail.com, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() References: <20061009145817.GB18308@networkno.de> <20061010.005142.03977034.anemo@mba.ocn.ne.jp> <20061009165920.GC18308@networkno.de> <20061010.174901.25477190.nemoto@toshiba-tops.co.jp> In-Reply-To: <20061010.174901.25477190.nemoto@toshiba-tops.co.jp> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12864 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1282 Lines: 32 Atsushi Nemoto wrote: > On Mon, 9 Oct 2006 17:59:20 +0100, Thiemo Seufer wrote: >>> Just for clarification: IIRC this optimization needs somewhat >>> up-to-date binutils/gcc and is not enabled on current lmo kernel, >>> right? >> For old toolchains there used to be a gruesome hack (which AFAIR broke >> at some point), for modern toolchains there's -msym32. > > Hmm, I found that the -msym32 is enabled if BUILD_ELF64 was not > selected, since 2.6.17. But does CONFIG_BUILD_ELF64=n really work for > modules? While MAP_BASE is 0xc000000000000000 for most 64-bit > platforms, I suppose modules should not be compiled with -msym32. > heh ? I'm wondering if anybody is using 'CONFIG_BUILD_ELF64=n' config at all... Atsushi, do you have any idea on how address are translated with 'CONFIG_BUILD_ELF64=n' config ? How such code is supposed to work ? code_resource.start = virt_to_phys(&_text); code_resource.end = virt_to_phys(&_etext) - 1; data_resource.start = virt_to_phys(&_etext); data_resource.end = virt_to_phys(&_edata) - 1; Let's say that '&_text' is in KSEG0 and is equal to 0xffffffff80000000. In this case virt_to_phys() returns 0x57ffffff80000000 (with PAGE_OFFSET = 0xa800000000000000). Is this physical address correct ? Thanks Franck From kevink@mips.com Tue Oct 10 14:49:46 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 14:49:50 +0100 (BST) Received: from mx.mips.com ([63.167.95.198]:49139 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S20039871AbWJJNtq (ORCPT ); Tue, 10 Oct 2006 14:49:46 +0100 Received: from mercury.mips.com (mercury [192.168.64.101]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id k9ADn9YG013160; Tue, 10 Oct 2006 06:49:13 -0700 (PDT) Received: from grendel (grendel [192.168.236.16]) by mercury.mips.com (8.13.5/8.13.5) with SMTP id k9ADnWug007750; Tue, 10 Oct 2006 06:49:33 -0700 (PDT) Message-ID: <003301c6ec73$cfe3ba00$10eca8c0@grendel> From: "Kevin D. Kissell" To: , "Atsushi Nemoto" Cc: References: <20061010.224652.53335173.anemo@mba.ocn.ne.jp> Subject: Re: [PATCH] optimize and cleanup get_saved_sp, set_saved_sp Date: Tue, 10 Oct 2006 15:55:56 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1807 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1807 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12865 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@mips.com Precedence: bulk X-list: linux-mips Content-Length: 236 Lines: 8 > This patch also fixes 64-bit SMTC version of get_saved_sp() which is > broken but harmless since there is no such CPUs for now. I appreciate and thank you for your prescience, though. ;o) Regards, Kevin K. From anemo@mba.ocn.ne.jp Tue Oct 10 15:17:34 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 15:17:37 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:51405 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20039800AbWJJORe (ORCPT ); Tue, 10 Oct 2006 15:17:34 +0100 Received: from localhost (p3213-ipad213funabasi.chiba.ocn.ne.jp [124.85.68.213]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id C960DAB3A; Tue, 10 Oct 2006 23:17:28 +0900 (JST) Date: Tue, 10 Oct 2006 23:19:44 +0900 (JST) Message-Id: <20061010.231944.42203018.anemo@mba.ocn.ne.jp> To: vagabon.xyz@gmail.com Cc: ths@networkno.de, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() From: Atsushi Nemoto In-Reply-To: <452BA4E7.30901@innova-card.com> References: <20061009165920.GC18308@networkno.de> <20061010.174901.25477190.nemoto@toshiba-tops.co.jp> <452BA4E7.30901@innova-card.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12866 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1444 Lines: 34 On Tue, 10 Oct 2006 15:49:27 +0200, Franck Bui-Huu wrote: > heh ? I'm wondering if anybody is using 'CONFIG_BUILD_ELF64=n' config at > all... arch/mips/configs/bigsur_defconfig:# CONFIG_BUILD_ELF64 is not set arch/mips/configs/ip27_defconfig:# CONFIG_BUILD_ELF64 is not set arch/mips/configs/ip32_defconfig:# CONFIG_BUILD_ELF64 is not set arch/mips/configs/ocelot_c_defconfig:# CONFIG_BUILD_ELF64 is not set arch/mips/configs/ocelot_g_defconfig:# CONFIG_BUILD_ELF64 is not set arch/mips/configs/sb1250-swarm_defconfig:# CONFIG_BUILD_ELF64 is not set According to arch/mips/configs, nobody is using CONFIG_BUILD_ELF64=y :-) Also one might use gcc 3.x which ignore -msym32 option ... > Atsushi, do you have any idea on how address are translated with > 'CONFIG_BUILD_ELF64=n' config ? How such code is supposed to work ? > > code_resource.start = virt_to_phys(&_text); > code_resource.end = virt_to_phys(&_etext) - 1; > data_resource.start = virt_to_phys(&_etext); > data_resource.end = virt_to_phys(&_edata) - 1; > > Let's say that '&_text' is in KSEG0 and is equal to 0xffffffff80000000. > In this case virt_to_phys() returns 0x57ffffff80000000 > (with PAGE_OFFSET = 0xa800000000000000). Is this physical address > correct ? I think this peice of code is just broken, as you said. This is bogus but harmless since we have not checked these resources are successfully registered or not. --- Atsushi Nemoto From yoichi_yuasa@tripeaks.co.jp Tue Oct 10 15:46:26 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 15:46:28 +0100 (BST) Received: from mo32.po.2iij.net ([210.128.50.17]:38424 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20039891AbWJJOq0 (ORCPT ); Tue, 10 Oct 2006 15:46:26 +0100 Received: by mo.po.2iij.net (mo32) id k9AEkMAn059739; Tue, 10 Oct 2006 23:46:22 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox32) id k9AEkJAM068784 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 10 Oct 2006 23:46:19 +0900 (JST) Date: Tue, 10 Oct 2006 23:46:18 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH] remove dead file arch/mips/arc/console.c Message-Id: <20061010234618.02af050b.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12867 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 1745 Lines: 76 Hi Ralf, This patch has removed arch/mips/arc/console.c . It seems to have been replaced by arch/mips/arc/promlib.c . Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/arc/console.c mips/arch/mips/arc/console.c --- mips-orig/arch/mips/arc/console.c 2006-07-26 10:34:31.756177500 +0900 +++ mips/arch/mips/arc/console.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,63 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996 David S. Miller (dm@sgi.com) - * Compability with board caches, Ulf Carlsson - */ -#include -#include -#include - -/* - * IP22 boardcache is not compatible with board caches. Thus we disable it - * during romvec action. Since r4xx0.c is always compiled and linked with your - * kernel, this shouldn't cause any harm regardless what MIPS processor you - * have. - * - * The ARC write and read functions seem to interfere with the serial lines - * in some way. You should be careful with them. - */ - -void prom_putchar(char c) -{ - ULONG cnt; - CHAR it = c; - - bc_disable(); - ArcWrite(1, &it, 1, &cnt); - bc_enable(); -} - -char prom_getchar(void) -{ - ULONG cnt; - CHAR c; - - bc_disable(); - ArcRead(0, &c, 1, &cnt); - bc_enable(); - - return c; -} - -void prom_printf(char *fmt, ...) -{ - va_list args; - char ppbuf[1024]; - char *bptr; - - va_start(args, fmt); - vsprintf(ppbuf, fmt, args); - - bptr = ppbuf; - - while (*bptr != 0) { - if (*bptr == '\n') - prom_putchar('\r'); - - prom_putchar(*bptr++); - } - va_end(args); -} From vagabon.xyz@gmail.com Tue Oct 10 16:00:49 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 16:00:51 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.187]:13236 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20039883AbWJJPAt (ORCPT ); Tue, 10 Oct 2006 16:00:49 +0100 Received: by nf-out-0910.google.com with SMTP id n29so299872nfc for ; Tue, 10 Oct 2006 08:00:45 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:reply-to:user-agent:mime-version:to:cc:subject:references:in-reply-to:content-type:content-transfer-encoding:from; b=h2COUBzSC6Zs6LJaOA/r4Q8i5++p752GwoNxSODUp4MekRFBQ+2+QHI4jpS+kNCU4z4SXltsl+LsQac0tuMqk/2VVum/UCI/Laj0M3XW3SPfnqUbb+rJYyX6ZnlvQ/WwFwqQIgaB1SpqJOb9gKX6eyQGKUMgpiAW8bwiGWUzUoI= Received: by 10.49.93.13 with SMTP id v13mr1561895nfl; Tue, 10 Oct 2006 08:00:45 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.google.com with ESMTP id x27sm2091322nfb.2006.10.10.08.00.44; Tue, 10 Oct 2006 08:00:44 -0700 (PDT) Message-ID: <452BB5E1.5090308@innova-card.com> Date: Tue, 10 Oct 2006 17:01:53 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: Atsushi Nemoto CC: vagabon.xyz@gmail.com, ths@networkno.de, ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] setup.c: introduce __pa_symbol() and get ride of CPHYSADDR() References: <20061009165920.GC18308@networkno.de> <20061010.174901.25477190.nemoto@toshiba-tops.co.jp> <452BA4E7.30901@innova-card.com> <20061010.231944.42203018.anemo@mba.ocn.ne.jp> In-Reply-To: <20061010.231944.42203018.anemo@mba.ocn.ne.jp> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12868 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1677 Lines: 42 Atsushi Nemoto wrote: > On Tue, 10 Oct 2006 15:49:27 +0200, Franck Bui-Huu wrote: >> heh ? I'm wondering if anybody is using 'CONFIG_BUILD_ELF64=n' config at >> all... > > arch/mips/configs/bigsur_defconfig:# CONFIG_BUILD_ELF64 is not set > arch/mips/configs/ip27_defconfig:# CONFIG_BUILD_ELF64 is not set > arch/mips/configs/ip32_defconfig:# CONFIG_BUILD_ELF64 is not set > arch/mips/configs/ocelot_c_defconfig:# CONFIG_BUILD_ELF64 is not set > arch/mips/configs/ocelot_g_defconfig:# CONFIG_BUILD_ELF64 is not set > arch/mips/configs/sb1250-swarm_defconfig:# CONFIG_BUILD_ELF64 is not set > > According to arch/mips/configs, nobody is using CONFIG_BUILD_ELF64=y :-) > > Also one might use gcc 3.x which ignore -msym32 option ... > yeah, that's probably the reason... >> Atsushi, do you have any idea on how address are translated with >> 'CONFIG_BUILD_ELF64=n' config ? How such code is supposed to work ? >> >> code_resource.start = virt_to_phys(&_text); >> code_resource.end = virt_to_phys(&_etext) - 1; >> data_resource.start = virt_to_phys(&_etext); >> data_resource.end = virt_to_phys(&_edata) - 1; >> >> Let's say that '&_text' is in KSEG0 and is equal to 0xffffffff80000000. >> In this case virt_to_phys() returns 0x57ffffff80000000 >> (with PAGE_OFFSET = 0xa800000000000000). Is this physical address >> correct ? > > I think this peice of code is just broken, as you said. This is bogus > but harmless since we have not checked these resources are > successfully registered or not. > what about all other uses of virt_to_phys(x) ? And what the point to set PAGE_OFFSET to 0xa800000000000000 ? I'm really confused... Franck From M.B.Lankhorst@gmail.com Tue Oct 10 16:17:21 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 16:17:23 +0100 (BST) Received: from mailserver.astro.rug.nl ([129.125.6.166]:15250 "EHLO mailserver.intra.astro.rug.nl") by ftp.linux-mips.org with ESMTP id S20039883AbWJJPRV (ORCPT ); Tue, 10 Oct 2006 16:17:21 +0100 Received: from [145.99.147.181] (guesswhos.boldlygoingnowhere.org [145.99.147.181]) (authenticated bits=0) by mailserver.intra.astro.rug.nl (8.12.11.20060308/8.12.11) with ESMTP id k9AFHFPf003433 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 10 Oct 2006 17:17:16 +0200 Message-ID: <452BB9C0.2080502@gmail.com> Date: Tue, 10 Oct 2006 17:18:24 +0200 From: Maarten Lankhorst User-Agent: Thunderbird 1.5.0.7 (Windows/20060909) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: [MIPS] Add bcm947xx support [3/5] Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12869 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: M.B.Lankhorst@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 98 Lines: 1 Add support for my specific flash chip, bit hard to get a valid mount to /dev/mtdblock otherwise. From 4c00e0a9a3cfca9dc77fd47004e467918575d3b9 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 10 Oct 2006 13:14:12 +0200 Subject: [PATCH] Detect-wrt54gl-flashchip Content-Length: 873 Lines: 24 --- drivers/mtd/chips/cfi_cmdset_0002.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c index 702ae4c..1a7a756 100644 --- a/drivers/mtd/chips/cfi_cmdset_0002.c +++ b/drivers/mtd/chips/cfi_cmdset_0002.c @@ -291,8 +291,10 @@ struct mtd_info *cfi_cmdset_0002(struct return NULL; } - if (extp->MajorVersion != '1' || - (extp->MinorVersion < '0' || extp->MinorVersion > '4')) { + /* Apparantly Major/Minor 3.3 is supported too */ + if (!(extp->MajorVersion == '3' && extp->MinorVersion == '3') && + (extp->MajorVersion != '1' || + (extp->MinorVersion < '0' || extp->MinorVersion > '4'))) { printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query " "version %c.%c.\n", extp->MajorVersion, extp->MinorVersion); -- 1.4.1 From M.B.Lankhorst@gmail.com Tue Oct 10 16:21:22 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 16:21:25 +0100 (BST) Received: from mailserver.astro.rug.nl ([129.125.6.166]:13459 "EHLO mailserver.intra.astro.rug.nl") by ftp.linux-mips.org with ESMTP id S20039883AbWJJPVW (ORCPT ); Tue, 10 Oct 2006 16:21:22 +0100 Received: from [145.99.147.181] (guesswhos.boldlygoingnowhere.org [145.99.147.181]) (authenticated bits=0) by mailserver.intra.astro.rug.nl (8.12.11.20060308/8.12.11) with ESMTP id k9AFLEiN003830 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 10 Oct 2006 17:21:14 +0200 Message-ID: <452BBAAF.3080406@gmail.com> Date: Tue, 10 Oct 2006 17:22:23 +0200 From: Maarten Lankhorst User-Agent: Thunderbird 1.5.0.7 (Windows/20060909) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: [MIPS] Add bcm947xx support [4/5] Content-Type: multipart/alternative; boundary="------------020609010802070204080008" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12870 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: M.B.Lankhorst@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 214 Lines: 6 This is a multi-part message in MIME format. --------------020609010802070204080008 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Add support for the ethernet device. From 4ce8bebff59c5cbce03b10278cc2fbc1fcc30c89 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 10 Oct 2006 13:15:40 +0200 Subject: [PATCH] b44 bcm47xx support Content-Length: 21843 Lines: 769 --- drivers/net/b44.c | 524 ++++++++++++++++++++++++++++++++++++++++++++++++----- drivers/net/b44.h | 8 + 2 files changed, 481 insertions(+), 51 deletions(-) diff --git a/drivers/net/b44.c b/drivers/net/b44.c index b124eee..a9717ba 100644 --- a/drivers/net/b44.c +++ b/drivers/net/b44.c @@ -1,8 +1,10 @@ -/* b44.c: Broadcom 4400 device driver. +/* b44.c: Broadcom 4400/47xx device driver. * * Copyright (C) 2002 David S. Miller (davem@redhat.com) - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi) + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi) + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org) * Copyright (C) 2006 Broadcom Corporation. + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org) * * Distribute under GPL. */ @@ -32,6 +34,28 @@ #define PFX DRV_MODULE_NAME ": " #define DRV_MODULE_VERSION "1.01" #define DRV_MODULE_RELDATE "Jun 16, 2006" +#ifdef CONFIG_BCM947XX +extern char *nvram_get(char *name); +static inline void e_aton(char *str, char *dest) +{ + int i = 0; + + if (str == NULL) { + memset(dest, 0, 6); + return; + } + + for (;;) { + dest[i++] = (char) simple_strtoul(str, NULL, 16); + str += 2; + if (!*str++ || i == 6) + break; + } +} + +static int b44_4713_instance; +#endif + #define B44_DEF_MSG_ENABLE \ (NETIF_MSG_DRV | \ NETIF_MSG_PROBE | \ @@ -87,8 +111,8 @@ #define B44_ETHIPV4UDP_HLEN 42 static char version[] __devinitdata = DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; -MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller"); -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver"); +MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller"); +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_MODULE_VERSION); @@ -103,6 +127,10 @@ static struct pci_device_id b44_pci_tbl[ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, +#ifdef CONFIG_BCM947XX + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, +#endif { } /* terminate list with empty entry */ }; @@ -141,17 +169,6 @@ static inline void b44_sync_dma_desc_for dma_desc_sync_size, dir); } -static inline unsigned long br32(const struct b44 *bp, unsigned long reg) -{ - return readl(bp->regs + reg); -} - -static inline void bw32(const struct b44 *bp, - unsigned long reg, unsigned long val) -{ - writel(val, bp->regs + reg); -} - static int b44_wait_bit(struct b44 *bp, unsigned long reg, u32 bit, unsigned long timeout, const int clear) { @@ -278,6 +295,10 @@ #if 0 break; }; #endif +#ifdef CONFIG_BCM947XX + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) + return b44_4713_instance++; +#endif return 0; } @@ -287,6 +308,30 @@ static int ssb_is_core_up(struct b44 *bp == SBTMSLOW_CLOCK); } +#ifdef CONFIG_BCM947XX +static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index) +{ + u32 val; + + bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ | + (index << CAM_CTRL_INDEX_SHIFT))); + + b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1); + + val = br32(bp, B44_CAM_DATA_LO); + + data[2] = (val >> 24) & 0xFF; + data[3] = (val >> 16) & 0xFF; + data[4] = (val >> 8) & 0xFF; + data[5] = (val >> 0) & 0xFF; + + val = br32(bp, B44_CAM_DATA_HI); + + data[0] = (val >> 8) & 0xFF; + data[1] = (val >> 0) & 0xFF; +} +#endif + static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index) { u32 val; @@ -323,14 +368,14 @@ static void b44_enable_ints(struct b44 * bw32(bp, B44_IMASK, bp->imask); } -static int b44_readphy(struct b44 *bp, int reg, u32 *val) +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val) { int err; bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII); bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START | (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) | - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) | + (phy_addr << MDIO_DATA_PMD_SHIFT) | (reg << MDIO_DATA_RA_SHIFT) | (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT))); err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0); @@ -339,18 +384,34 @@ static int b44_readphy(struct b44 *bp, i return err; } -static int b44_writephy(struct b44 *bp, int reg, u32 val) +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val) { bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII); bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START | (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) | - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) | + (phy_addr << MDIO_DATA_PMD_SHIFT) | (reg << MDIO_DATA_RA_SHIFT) | (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) | (val & MDIO_DATA_DATA))); return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0); } +static inline int b44_readphy(struct b44 *bp, int reg, u32 *val) +{ + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) + return 0; + + return __b44_readphy(bp, bp->phy_addr, reg, val); +} + +static inline int b44_writephy(struct b44 *bp, int reg, u32 val) +{ + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) + return 0; + + return __b44_writephy(bp, bp->phy_addr, reg, val); +} + /* miilib interface */ /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional * due to code existing before miilib use was added to this driver. @@ -379,6 +440,8 @@ static int b44_phy_reset(struct b44 *bp) u32 val; int err; + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) + return 0; err = b44_writephy(bp, MII_BMCR, BMCR_RESET); if (err) return err; @@ -442,6 +505,22 @@ static int b44_setup_phy(struct b44 *bp) u32 val; int err; +#ifdef CONFIG_BCM947XX + /* + * workaround for bad hardware design in Linksys WAP54G v1.0 + * see https://dev.openwrt.org/ticket/146 + * check and reset bit "isolate" + */ + if ((bp->pdev->device == PCI_DEVICE_ID_BCM4713) && + (atoi(nvram_get("boardnum")) == 2) && + (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) && + (val & BMCR_ISOLATE) && + (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) { + printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n"); + } +#endif + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) + return 0; if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0) goto out; if ((err = b44_writephy(bp, B44_MII_ALEDCTRL, @@ -537,6 +616,19 @@ static void b44_check_phy(struct b44 *bp { u32 bmsr, aux; + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) { + bp->flags |= B44_FLAG_100_BASE_T; + bp->flags |= B44_FLAG_FULL_DUPLEX; + if (!netif_carrier_ok(bp->dev)) { + u32 val = br32(bp, B44_TX_CTRL); + val |= TX_CTRL_DUPLEX; + bw32(bp, B44_TX_CTRL, val); + netif_carrier_on(bp->dev); + b44_link_report(bp); + } + return; + } + if (!b44_readphy(bp, MII_BMSR, &bmsr) && !b44_readphy(bp, B44_MII_AUXCTRL, &aux) && (bmsr != 0xffff)) { @@ -1291,9 +1383,10 @@ static void b44_chip_reset(struct b44 *b bw32(bp, B44_DMARX_CTRL, 0); bp->rx_prod = bp->rx_cons = 0; } else { - ssb_pci_setup(bp, (bp->core_unit == 0 ? - SBINTVEC_ENET0 : - SBINTVEC_ENET1)); + if (bp->pdev->device != PCI_DEVICE_ID_BCM4713) + ssb_pci_setup(bp, (bp->core_unit == 0 ? + SBINTVEC_ENET0 : + SBINTVEC_ENET1)); } ssb_core_reset(bp); @@ -1301,8 +1394,14 @@ static void b44_chip_reset(struct b44 *b b44_clear_stats(bp); /* Make PHY accessible. */ - bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE | + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE | + (((100000000 + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO) + & MDIO_CTRL_MAXF_MASK))); + else + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE | (0x0d & MDIO_CTRL_MAXF_MASK))); + br32(bp, B44_MDIO_CTRL); if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) { @@ -1345,6 +1444,7 @@ static int b44_set_mac_addr(struct net_d { struct b44 *bp = netdev_priv(dev); struct sockaddr *addr = p; + u32 val; if (netif_running(dev)) return -EBUSY; @@ -1355,7 +1455,11 @@ static int b44_set_mac_addr(struct net_d memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); spin_lock_irq(&bp->lock); - __b44_set_mac_addr(bp); + + val = br32(bp, B44_RXCONFIG); + if (!(val & RXCONFIG_CAM_ABSENT)) + __b44_set_mac_addr(bp); + spin_unlock_irq(&bp->lock); return 0; @@ -1697,7 +1801,7 @@ static void __b44_set_rx_mode(struct net val = br32(bp, B44_RXCONFIG); val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI); - if (dev->flags & IFF_PROMISC) { + if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) { val |= RXCONFIG_PROMISC; bw32(bp, B44_RXCONFIG, val); } else { @@ -2032,18 +2136,297 @@ static const struct ethtool_ops b44_etht .get_perm_addr = ethtool_op_get_perm_addr, }; +static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr) +{ + struct b44 *bp = dev->priv; + struct pci_dev *pci_dev = bp->pdev; + u32 ethcmd; + + if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd))) + return -EFAULT; + + switch (ethcmd) { + case ETHTOOL_GDRVINFO: { + struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO }; + strcpy (info.driver, DRV_MODULE_NAME); + strcpy (info.version, DRV_MODULE_VERSION); + memset(&info.fw_version, 0, sizeof(info.fw_version)); + strcpy (info.bus_info, pci_name(pci_dev)); + info.eedump_len = 0; + info.regdump_len = 0; + if (copy_to_user (useraddr, &info, sizeof (info))) + return -EFAULT; + return 0; + } + + case ETHTOOL_GSET: { + struct ethtool_cmd cmd = { ETHTOOL_GSET }; + + if (!(bp->flags & B44_FLAG_INIT_COMPLETE)) + return -EAGAIN; + cmd.supported = (SUPPORTED_Autoneg); + cmd.supported |= (SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_MII); + + cmd.advertising = 0; + if (bp->flags & B44_FLAG_ADV_10HALF) + cmd.advertising |= ADVERTISE_10HALF; + if (bp->flags & B44_FLAG_ADV_10FULL) + cmd.advertising |= ADVERTISE_10FULL; + if (bp->flags & B44_FLAG_ADV_100HALF) + cmd.advertising |= ADVERTISE_100HALF; + if (bp->flags & B44_FLAG_ADV_100FULL) + cmd.advertising |= ADVERTISE_100FULL; + cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; + cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ? + SPEED_100 : SPEED_10; + cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ? + DUPLEX_FULL : DUPLEX_HALF; + cmd.port = 0; + cmd.phy_address = bp->phy_addr; + cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ? + XCVR_INTERNAL : XCVR_EXTERNAL; + cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ? + AUTONEG_DISABLE : AUTONEG_ENABLE; + cmd.maxtxpkt = 0; + cmd.maxrxpkt = 0; + if (copy_to_user(useraddr, &cmd, sizeof(cmd))) + return -EFAULT; + return 0; + } + case ETHTOOL_SSET: { + struct ethtool_cmd cmd; + + if (!(bp->flags & B44_FLAG_INIT_COMPLETE)) + return -EAGAIN; + + if (copy_from_user(&cmd, useraddr, sizeof(cmd))) + return -EFAULT; + + /* We do not support gigabit. */ + if (cmd.autoneg == AUTONEG_ENABLE) { + if (cmd.advertising & + (ADVERTISED_1000baseT_Half | + ADVERTISED_1000baseT_Full)) + return -EINVAL; + } else if ((cmd.speed != SPEED_100 && + cmd.speed != SPEED_10) || + (cmd.duplex != DUPLEX_HALF && + cmd.duplex != DUPLEX_FULL)) { + return -EINVAL; + } + + spin_lock_irq(&bp->lock); + + if (cmd.autoneg == AUTONEG_ENABLE) { + bp->flags &= ~B44_FLAG_FORCE_LINK; + bp->flags &= ~(B44_FLAG_ADV_10HALF | + B44_FLAG_ADV_10FULL | + B44_FLAG_ADV_100HALF | + B44_FLAG_ADV_100FULL); + if (cmd.advertising & ADVERTISE_10HALF) + bp->flags |= B44_FLAG_ADV_10HALF; + if (cmd.advertising & ADVERTISE_10FULL) + bp->flags |= B44_FLAG_ADV_10FULL; + if (cmd.advertising & ADVERTISE_100HALF) + bp->flags |= B44_FLAG_ADV_100HALF; + if (cmd.advertising & ADVERTISE_100FULL) + bp->flags |= B44_FLAG_ADV_100FULL; + } else { + bp->flags |= B44_FLAG_FORCE_LINK; + if (cmd.speed == SPEED_100) + bp->flags |= B44_FLAG_100_BASE_T; + if (cmd.duplex == DUPLEX_FULL) + bp->flags |= B44_FLAG_FULL_DUPLEX; + } + + b44_setup_phy(bp); + + spin_unlock_irq(&bp->lock); + + return 0; + } + + case ETHTOOL_GMSGLVL: { + struct ethtool_value edata = { ETHTOOL_GMSGLVL }; + edata.data = bp->msg_enable; + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; + } + case ETHTOOL_SMSGLVL: { + struct ethtool_value edata; + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + bp->msg_enable = edata.data; + return 0; + } + case ETHTOOL_NWAY_RST: { + u32 bmcr; + int r; + + spin_lock_irq(&bp->lock); + b44_readphy(bp, MII_BMCR, &bmcr); + b44_readphy(bp, MII_BMCR, &bmcr); + r = -EINVAL; + if (bmcr & BMCR_ANENABLE) { + b44_writephy(bp, MII_BMCR, + bmcr | BMCR_ANRESTART); + r = 0; + } + spin_unlock_irq(&bp->lock); + + return r; + } + case ETHTOOL_GLINK: { + struct ethtool_value edata = { ETHTOOL_GLINK }; + edata.data = netif_carrier_ok(bp->dev) ? 1 : 0; + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; + } + case ETHTOOL_GRINGPARAM: { + struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM }; + + ering.rx_max_pending = B44_RX_RING_SIZE - 1; + ering.rx_pending = bp->rx_pending; + + /* XXX ethtool lacks a tx_max_pending, oops... */ + + if (copy_to_user(useraddr, &ering, sizeof(ering))) + return -EFAULT; + return 0; + } + case ETHTOOL_SRINGPARAM: { + struct ethtool_ringparam ering; + + if (copy_from_user(&ering, useraddr, sizeof(ering))) + return -EFAULT; + + if ((ering.rx_pending > B44_RX_RING_SIZE - 1) || + (ering.rx_mini_pending != 0) || + (ering.rx_jumbo_pending != 0) || + (ering.tx_pending > B44_TX_RING_SIZE - 1)) + return -EINVAL; + + spin_lock_irq(&bp->lock); + + bp->rx_pending = ering.rx_pending; + bp->tx_pending = ering.tx_pending; + + b44_halt(bp); + b44_init_rings(bp); + b44_init_hw(bp, 1); + netif_wake_queue(bp->dev); + spin_unlock_irq(&bp->lock); + + b44_enable_ints(bp); + + return 0; + } + case ETHTOOL_GPAUSEPARAM: { + struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM }; + + epause.autoneg = + (bp->flags & B44_FLAG_PAUSE_AUTO) != 0; + epause.rx_pause = + (bp->flags & B44_FLAG_RX_PAUSE) != 0; + epause.tx_pause = + (bp->flags & B44_FLAG_TX_PAUSE) != 0; + if (copy_to_user(useraddr, &epause, sizeof(epause))) + return -EFAULT; + return 0; + } + case ETHTOOL_SPAUSEPARAM: { + struct ethtool_pauseparam epause; + + if (copy_from_user(&epause, useraddr, sizeof(epause))) + return -EFAULT; + + spin_lock_irq(&bp->lock); + if (epause.autoneg) + bp->flags |= B44_FLAG_PAUSE_AUTO; + else + bp->flags &= ~B44_FLAG_PAUSE_AUTO; + if (epause.rx_pause) + bp->flags |= B44_FLAG_RX_PAUSE; + else + bp->flags &= ~B44_FLAG_RX_PAUSE; + if (epause.tx_pause) + bp->flags |= B44_FLAG_TX_PAUSE; + else + bp->flags &= ~B44_FLAG_TX_PAUSE; + if (bp->flags & B44_FLAG_PAUSE_AUTO) { + b44_halt(bp); + b44_init_rings(bp); + b44_init_hw(bp, 1); + } else { + __b44_set_flow_ctrl(bp, bp->flags); + } + spin_unlock_irq(&bp->lock); + + b44_enable_ints(bp); + + return 0; + } + }; + + return -EOPNOTSUPP; +} + static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { struct mii_ioctl_data *data = if_mii(ifr); struct b44 *bp = netdev_priv(dev); int err = -EINVAL; - if (!netif_running(dev)) + if (bp->pdev->device != PCI_DEVICE_ID_BCM4713) { + if (!netif_running(dev)) + goto out; + + spin_lock_irq(&bp->lock); + err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL); + spin_unlock_irq(&bp->lock); goto out; + } - spin_lock_irq(&bp->lock); - err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL); - spin_unlock_irq(&bp->lock); + switch (cmd) { + case SIOCETHTOOL: + return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data); + + case SIOCGMIIPHY: + data->phy_id = bp->phy_addr; + + /* fallthru */ + case SIOCGMIIREG: { + u32 mii_regval; + spin_lock_irq(&bp->lock); + err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval); + spin_unlock_irq(&bp->lock); + + data->val_out = mii_regval; + + return err; + } + + case SIOCSMIIREG: + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + + spin_lock_irq(&bp->lock); + err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); + spin_unlock_irq(&bp->lock); + + return err; + + default: + break; + }; + return -EOPNOTSUPP; + out: return err; } @@ -2063,27 +2446,65 @@ static int b44_read_eeprom(struct b44 *b static int __devinit b44_get_invariants(struct b44 *bp) { u8 eeprom[128]; - int err; + u8 buf[32]; + int err = 0; + unsigned long flags; + +#ifdef CONFIG_BCM947XX + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) { + /* + * BCM47xx boards don't have a EEPROM. The MAC is stored in + * a NVRAM area somewhere in the flash memory. + */ + sprintf(buf, "et%dmacaddr", b44_4713_instance); + if (nvram_get(buf)) { + e_aton(nvram_get(buf), bp->dev->dev_addr); + } else { + /* + * Getting the MAC out of NVRAM failed. To make it work + * here, we simply rely on the bootloader to write the + * MAC into the CAM. + */ + spin_lock_irqsave(&bp->lock, flags); + __b44_cam_read(bp, bp->dev->dev_addr, 0); + spin_unlock_irqrestore(&bp->lock, flags); + } - err = b44_read_eeprom(bp, &eeprom[0]); - if (err) - goto out; + if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){ + printk(KERN_ERR PFX "Invalid MAC address found in NVRAM\n"); + return -EINVAL; + } - bp->dev->dev_addr[0] = eeprom[79]; - bp->dev->dev_addr[1] = eeprom[78]; - bp->dev->dev_addr[2] = eeprom[81]; - bp->dev->dev_addr[3] = eeprom[80]; - bp->dev->dev_addr[4] = eeprom[83]; - bp->dev->dev_addr[5] = eeprom[82]; + /* + * BCM47xx boards don't have a PHY. Usually there is a switch + * chip with multiple PHYs connected to the PHY port. + */ + bp->phy_addr = B44_PHY_ADDR_NO_PHY; + bp->dma_offset = 0; + } else +#endif + { + err = b44_read_eeprom(bp, &eeprom[0]); + if (err) + goto out; - if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){ - printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n"); - return -EINVAL; - } + bp->dev->dev_addr[0] = eeprom[79]; + bp->dev->dev_addr[1] = eeprom[78]; + bp->dev->dev_addr[2] = eeprom[81]; + bp->dev->dev_addr[3] = eeprom[80]; + bp->dev->dev_addr[4] = eeprom[83]; + bp->dev->dev_addr[5] = eeprom[82]; + + if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){ + printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n"); + return -EINVAL; + } - memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len); + memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len); - bp->phy_addr = eeprom[90] & 0x1f; + bp->phy_addr = eeprom[90] & 0x1f; + bp->dma_offset = SB_PCI_DMA; + } /* With this, plus the rx_header prepended to the data by the * hardware, we'll land the ethernet header on a 2-byte boundary. @@ -2093,11 +2514,6 @@ static int __devinit b44_get_invariants( bp->imask = IMASK_DEF; bp->core_unit = ssb_core_unit(bp); - bp->dma_offset = SB_PCI_DMA; - - /* XXX - really required? - bp->flags |= B44_FLAG_BUGGY_TXPTR; - */ if (ssb_get_core_rev(bp) >= 7) bp->flags |= B44_FLAG_B0_ANDLATER; @@ -2244,11 +2660,17 @@ #endif */ b44_chip_reset(bp); - printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name); + printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name, + (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400"); for (i = 0; i < 6; i++) printk("%2.2x%c", dev->dev_addr[i], i == 5 ? '\n' : ':'); + /* Initialize phy */ + spin_lock_irq(&bp->lock); + b44_chip_reset(bp); + spin_unlock_irq(&bp->lock); + return 0; err_out_iounmap: diff --git a/drivers/net/b44.h b/drivers/net/b44.h index 4944507..1e6f2c5 100644 --- a/drivers/net/b44.h +++ b/drivers/net/b44.h @@ -129,6 +129,7 @@ #define RXCONFIG_LPBACK 0x00000010 /* L #define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */ #define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ #define RXCONFIG_RFILT 0x00000080 /* Reject Filter */ +#define RXCONFIG_CAM_ABSENT 0x00000100 /* CAM Absent */ #define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */ #define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */ #define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */ @@ -297,6 +298,10 @@ #define SSB_PCI_MASK0 0xfc000000 #define SSB_PCI_MASK1 0xfc000000 #define SSB_PCI_MASK2 0xc0000000 +#define br32(bp, REG) readl((void *)bp->regs + (REG)) +#define bw32(bp, REG,VAL) writel((VAL), (void *)bp->regs + (REG)) +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0) + /* 4400 PHY registers */ #define B44_MII_AUXCTRL 24 /* Auxiliary Control */ #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */ @@ -350,6 +355,8 @@ struct ring_info { }; #define B44_MCAST_TABLE_SIZE 32 +#define B44_PHY_ADDR_NO_PHY 30 +#define B44_MDC_RATIO 5000000 #define B44_STAT_REG_DECLARE \ _B44(tx_good_octets) \ @@ -428,6 +435,7 @@ struct b44 { #define B44_FLAG_B0_ANDLATER 0x00000001 #define B44_FLAG_BUGGY_TXPTR 0x00000002 #define B44_FLAG_REORDER_BUG 0x00000004 +#define B44_FLAG_INIT_COMPLETE 0x00000008 #define B44_FLAG_PAUSE_AUTO 0x00008000 #define B44_FLAG_FULL_DUPLEX 0x00010000 #define B44_FLAG_100_BASE_T 0x00020000 -- 1.4.1 --------------020609010802070204080008 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit 
Add support for the ethernet device.

From 4ce8bebff59c5cbce03b10278cc2fbc1fcc30c89 Mon Sep 17 00:00:00 2001
From: Maarten Lankhorst <M.B.Lankhorst@gmail.com>
Date: Tue, 10 Oct 2006 13:15:40 +0200
Subject: [PATCH] b44 bcm47xx support
Content-Length: 23055
Lines: 761

---
 drivers/net/b44.c |  524 ++++++++++++++++++++++++++++++++++++++++++++++++-----
 drivers/net/b44.h |    8 +
 2 files changed, 481 insertions(+), 51 deletions(-)

diff --git a/drivers/net/b44.c b/drivers/net/b44.c
index b124eee..a9717ba 100644
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -1,8 +1,10 @@
-/* b44.c: Broadcom 4400 device driver.
+/* b44.c: Broadcom 4400/47xx device driver.
  *
  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
- * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
+ * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
  * Copyright (C) 2006 Broadcom Corporation.
+ * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
  *
  * Distribute under GPL.
  */
@@ -32,6 +34,28 @@ #define PFX DRV_MODULE_NAME	": "
 #define DRV_MODULE_VERSION	"1.01"
 #define DRV_MODULE_RELDATE	"Jun 16, 2006"
 
+#ifdef CONFIG_BCM947XX
+extern char *nvram_get(char *name);
+static inline void e_aton(char *str, char *dest)
+{
+	int i = 0;
+
+	if (str == NULL) {
+		memset(dest, 0, 6);
+		return;
+	}
+	
+	for (;;) {
+		dest[i++] = (char) simple_strtoul(str, NULL, 16);
+		str += 2;
+		if (!*str++ || i == 6)
+			break;
+	}
+}
+
+static int b44_4713_instance;
+#endif
+
 #define B44_DEF_MSG_ENABLE	  \
 	(NETIF_MSG_DRV		| \
 	 NETIF_MSG_PROBE	| \
@@ -87,8 +111,8 @@ #define B44_ETHIPV4UDP_HLEN	42
 static char version[] __devinitdata =
 	DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 
-MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
-MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
+MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
+MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_MODULE_VERSION);
 
@@ -103,6 +127,10 @@ static struct pci_device_id b44_pci_tbl[
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+#ifdef CONFIG_BCM947XX
+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+#endif
 	{ }	/* terminate list with empty entry */
 };
 
@@ -141,17 +169,6 @@ static inline void b44_sync_dma_desc_for
 	                              dma_desc_sync_size, dir);
 }
 
-static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
-{
-	return readl(bp->regs + reg);
-}
-
-static inline void bw32(const struct b44 *bp,
-			unsigned long reg, unsigned long val)
-{
-	writel(val, bp->regs + reg);
-}
-
 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
 			u32 bit, unsigned long timeout, const int clear)
 {
@@ -278,6 +295,10 @@ #if 0
 		break;
 	};
 #endif
+#ifdef CONFIG_BCM947XX
+	if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
+		return b44_4713_instance++;
+#endif
 	return 0;
 }
 
@@ -287,6 +308,30 @@ static int ssb_is_core_up(struct b44 *bp
 		== SBTMSLOW_CLOCK);
 }
 
+#ifdef CONFIG_BCM947XX
+static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
+{
+	u32 val;
+
+	bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
+			    (index << CAM_CTRL_INDEX_SHIFT)));
+
+	b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
+
+	val = br32(bp, B44_CAM_DATA_LO);
+
+	data[2] = (val >> 24) & 0xFF;
+	data[3] = (val >> 16) & 0xFF;
+	data[4] = (val >> 8) & 0xFF;
+	data[5] = (val >> 0) & 0xFF;
+
+	val = br32(bp, B44_CAM_DATA_HI);
+
+	data[0] = (val >> 8) & 0xFF;
+	data[1] = (val >> 0) & 0xFF;
+}
+#endif
+
 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 {
 	u32 val;
@@ -323,14 +368,14 @@ static void b44_enable_ints(struct b44 *
 	bw32(bp, B44_IMASK, bp->imask);
 }
 
-static int b44_readphy(struct b44 *bp, int reg, u32 *val)
+static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
 {
 	int err;
 
 	bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 	bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 			     (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
-			     (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
+			     (phy_addr << MDIO_DATA_PMD_SHIFT) |
 			     (reg << MDIO_DATA_RA_SHIFT) |
 			     (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 	err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
@@ -339,18 +384,34 @@ static int b44_readphy(struct b44 *bp, i
 	return err;
 }
 
-static int b44_writephy(struct b44 *bp, int reg, u32 val)
+static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
 {
 	bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 	bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 			     (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
-			     (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
+			     (phy_addr << MDIO_DATA_PMD_SHIFT) |
 			     (reg << MDIO_DATA_RA_SHIFT) |
 			     (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 			     (val & MDIO_DATA_DATA)));
 	return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 }
 
+static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
+{
+	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
+		return 0;
+
+	return __b44_readphy(bp, bp->phy_addr, reg, val);
+}
+
+static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
+{
+	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
+		return 0;
+		
+	return __b44_writephy(bp, bp->phy_addr, reg, val);
+}
+
 /* miilib interface */
 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
  * due to code existing before miilib use was added to this driver.
@@ -379,6 +440,8 @@ static int b44_phy_reset(struct b44 *bp)
 	u32 val;
 	int err;
 
+	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
+		return 0;
 	err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 	if (err)
 		return err;
@@ -442,6 +505,22 @@ static int b44_setup_phy(struct b44 *bp)
 	u32 val;
 	int err;
 
+#ifdef CONFIG_BCM947XX
+	/*
+	 * workaround for bad hardware design in Linksys WAP54G v1.0
+	 * see https://dev.openwrt.org/ticket/146
+	 * check and reset bit "isolate"
+	 */
+	if ((bp->pdev->device == PCI_DEVICE_ID_BCM4713) &&
+			(atoi(nvram_get("boardnum")) == 2) &&
+			(__b44_readphy(bp, 0, MII_BMCR, &val) == 0) && 
+			(val & BMCR_ISOLATE) &&
+			(__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
+		printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
+	}
+#endif
+	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
+		return 0;
 	if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 		goto out;
 	if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
@@ -537,6 +616,19 @@ static void b44_check_phy(struct b44 *bp
 {
 	u32 bmsr, aux;
 
+	if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
+		bp->flags |= B44_FLAG_100_BASE_T;
+		bp->flags |= B44_FLAG_FULL_DUPLEX;
+		if (!netif_carrier_ok(bp->dev)) {
+			u32 val = br32(bp, B44_TX_CTRL);
+			val |= TX_CTRL_DUPLEX;
+			bw32(bp, B44_TX_CTRL, val);
+			netif_carrier_on(bp->dev);
+			b44_link_report(bp);
+		}
+		return;
+	}
+
 	if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 	    !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 	    (bmsr != 0xffff)) {
@@ -1291,9 +1383,10 @@ static void b44_chip_reset(struct b44 *b
 		bw32(bp, B44_DMARX_CTRL, 0);
 		bp->rx_prod = bp->rx_cons = 0;
 	} else {
-		ssb_pci_setup(bp, (bp->core_unit == 0 ?
-				   SBINTVEC_ENET0 :
-				   SBINTVEC_ENET1));
+		if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)
+			ssb_pci_setup(bp, (bp->core_unit == 0 ?
+					   SBINTVEC_ENET0 :
+					   SBINTVEC_ENET1));
 	}
 
 	ssb_core_reset(bp);
@@ -1301,8 +1394,14 @@ static void b44_chip_reset(struct b44 *b
 	b44_clear_stats(bp);
 
 	/* Make PHY accessible. */
-	bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
+	if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
+		bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
+			     (((100000000 + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
+			     & MDIO_CTRL_MAXF_MASK)));
+	else
+		bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
 			     (0x0d & MDIO_CTRL_MAXF_MASK)));
+
 	br32(bp, B44_MDIO_CTRL);
 
 	if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
@@ -1345,6 +1444,7 @@ static int b44_set_mac_addr(struct net_d
 {
 	struct b44 *bp = netdev_priv(dev);
 	struct sockaddr *addr = p;
+ 	u32 val;
 
 	if (netif_running(dev))
 		return -EBUSY;
@@ -1355,7 +1455,11 @@ static int b44_set_mac_addr(struct net_d
 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 
 	spin_lock_irq(&bp->lock);
-	__b44_set_mac_addr(bp);
+   
+   	val = br32(bp, B44_RXCONFIG);
+   	if (!(val & RXCONFIG_CAM_ABSENT))
+		__b44_set_mac_addr(bp);
+   
 	spin_unlock_irq(&bp->lock);
 
 	return 0;
@@ -1697,7 +1801,7 @@ static void __b44_set_rx_mode(struct net
 
 	val = br32(bp, B44_RXCONFIG);
 	val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
-	if (dev->flags & IFF_PROMISC) {
+	if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
 		val |= RXCONFIG_PROMISC;
 		bw32(bp, B44_RXCONFIG, val);
 	} else {
@@ -2032,18 +2136,297 @@ static const struct ethtool_ops b44_etht
 	.get_perm_addr		= ethtool_op_get_perm_addr,
 };
 
+static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
+{
+	struct b44 *bp = dev->priv;
+	struct pci_dev *pci_dev = bp->pdev;
+	u32 ethcmd;
+
+	if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
+		return -EFAULT;
+
+	switch (ethcmd) {
+	case ETHTOOL_GDRVINFO: {
+		struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
+		strcpy (info.driver, DRV_MODULE_NAME);
+		strcpy (info.version, DRV_MODULE_VERSION);
+		memset(&info.fw_version, 0, sizeof(info.fw_version));
+		strcpy (info.bus_info, pci_name(pci_dev));
+		info.eedump_len = 0;
+		info.regdump_len = 0;
+		if (copy_to_user (useraddr, &info, sizeof (info)))
+			return -EFAULT;
+		return 0;
+	}
+
+	case ETHTOOL_GSET: {
+		struct ethtool_cmd cmd = { ETHTOOL_GSET };
+
+		if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
+			return -EAGAIN;
+		cmd.supported = (SUPPORTED_Autoneg);
+		cmd.supported |= (SUPPORTED_100baseT_Half |
+				  SUPPORTED_100baseT_Full |
+				  SUPPORTED_10baseT_Half |
+				  SUPPORTED_10baseT_Full |
+				  SUPPORTED_MII);
+
+		cmd.advertising = 0;
+		if (bp->flags & B44_FLAG_ADV_10HALF)
+			cmd.advertising |= ADVERTISE_10HALF;
+		if (bp->flags & B44_FLAG_ADV_10FULL)
+			cmd.advertising |= ADVERTISE_10FULL;
+		if (bp->flags & B44_FLAG_ADV_100HALF)
+			cmd.advertising |= ADVERTISE_100HALF;
+		if (bp->flags & B44_FLAG_ADV_100FULL)
+			cmd.advertising |= ADVERTISE_100FULL;
+		cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
+		cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
+			SPEED_100 : SPEED_10;
+		cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
+			DUPLEX_FULL : DUPLEX_HALF;
+		cmd.port = 0;
+		cmd.phy_address = bp->phy_addr;
+		cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
+			XCVR_INTERNAL : XCVR_EXTERNAL;
+		cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
+			AUTONEG_DISABLE : AUTONEG_ENABLE;
+		cmd.maxtxpkt = 0;
+		cmd.maxrxpkt = 0;
+		if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_SSET: {
+		struct ethtool_cmd cmd;
+
+		if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
+			return -EAGAIN;
+
+		if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
+			return -EFAULT;
+
+		/* We do not support gigabit. */
+		if (cmd.autoneg == AUTONEG_ENABLE) {
+			if (cmd.advertising &
+			    (ADVERTISED_1000baseT_Half |
+			     ADVERTISED_1000baseT_Full))
+				return -EINVAL;
+		} else if ((cmd.speed != SPEED_100 &&
+			    cmd.speed != SPEED_10) ||
+			   (cmd.duplex != DUPLEX_HALF &&
+			    cmd.duplex != DUPLEX_FULL)) {
+				return -EINVAL;
+		}
+
+		spin_lock_irq(&bp->lock);
+
+		if (cmd.autoneg == AUTONEG_ENABLE) {
+			bp->flags &= ~B44_FLAG_FORCE_LINK;
+			bp->flags &= ~(B44_FLAG_ADV_10HALF |
+				       B44_FLAG_ADV_10FULL |
+				       B44_FLAG_ADV_100HALF |
+				       B44_FLAG_ADV_100FULL);
+			if (cmd.advertising & ADVERTISE_10HALF)
+				bp->flags |= B44_FLAG_ADV_10HALF;
+			if (cmd.advertising & ADVERTISE_10FULL)
+				bp->flags |= B44_FLAG_ADV_10FULL;
+			if (cmd.advertising & ADVERTISE_100HALF)
+				bp->flags |= B44_FLAG_ADV_100HALF;
+			if (cmd.advertising & ADVERTISE_100FULL)
+				bp->flags |= B44_FLAG_ADV_100FULL;
+		} else {
+			bp->flags |= B44_FLAG_FORCE_LINK;
+			if (cmd.speed == SPEED_100)
+				bp->flags |= B44_FLAG_100_BASE_T;
+			if (cmd.duplex == DUPLEX_FULL)
+				bp->flags |= B44_FLAG_FULL_DUPLEX;
+		}
+
+		b44_setup_phy(bp);
+
+		spin_unlock_irq(&bp->lock);
+
+		return 0;
+	}
+
+	case ETHTOOL_GMSGLVL: {
+		struct ethtool_value edata = { ETHTOOL_GMSGLVL };
+		edata.data = bp->msg_enable;
+		if (copy_to_user(useraddr, &edata, sizeof(edata)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_SMSGLVL: {
+		struct ethtool_value edata;
+		if (copy_from_user(&edata, useraddr, sizeof(edata)))
+			return -EFAULT;
+		bp->msg_enable = edata.data;
+		return 0;
+	}
+	case ETHTOOL_NWAY_RST: {
+		u32 bmcr;
+		int r;
+
+		spin_lock_irq(&bp->lock);
+		b44_readphy(bp, MII_BMCR, &bmcr);
+		b44_readphy(bp, MII_BMCR, &bmcr);
+		r = -EINVAL;
+		if (bmcr & BMCR_ANENABLE) {
+			b44_writephy(bp, MII_BMCR,
+				     bmcr | BMCR_ANRESTART);
+			r = 0;
+		}
+		spin_unlock_irq(&bp->lock);
+
+		return r;
+	}
+	case ETHTOOL_GLINK: {
+		struct ethtool_value edata = { ETHTOOL_GLINK };
+		edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
+		if (copy_to_user(useraddr, &edata, sizeof(edata)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_GRINGPARAM: {
+		struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
+
+		ering.rx_max_pending = B44_RX_RING_SIZE - 1;
+		ering.rx_pending = bp->rx_pending;
+
+		/* XXX ethtool lacks a tx_max_pending, oops... */
+
+		if (copy_to_user(useraddr, &ering, sizeof(ering)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_SRINGPARAM: {
+		struct ethtool_ringparam ering;
+
+		if (copy_from_user(&ering, useraddr, sizeof(ering)))
+			return -EFAULT;
+
+		if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
+		    (ering.rx_mini_pending != 0) ||
+		    (ering.rx_jumbo_pending != 0) ||
+		    (ering.tx_pending > B44_TX_RING_SIZE - 1))
+			return -EINVAL;
+
+		spin_lock_irq(&bp->lock);
+
+		bp->rx_pending = ering.rx_pending;
+		bp->tx_pending = ering.tx_pending;
+
+		b44_halt(bp);
+		b44_init_rings(bp);
+		b44_init_hw(bp, 1);
+		netif_wake_queue(bp->dev);
+		spin_unlock_irq(&bp->lock);
+
+		b44_enable_ints(bp);
+		
+		return 0;
+	}
+	case ETHTOOL_GPAUSEPARAM: {
+		struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
+
+		epause.autoneg =
+			(bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
+		epause.rx_pause =
+			(bp->flags & B44_FLAG_RX_PAUSE) != 0;
+		epause.tx_pause =
+			(bp->flags & B44_FLAG_TX_PAUSE) != 0;
+		if (copy_to_user(useraddr, &epause, sizeof(epause)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_SPAUSEPARAM: {
+		struct ethtool_pauseparam epause;
+
+		if (copy_from_user(&epause, useraddr, sizeof(epause)))
+			return -EFAULT;
+
+		spin_lock_irq(&bp->lock);
+		if (epause.autoneg)
+			bp->flags |= B44_FLAG_PAUSE_AUTO;
+		else
+			bp->flags &= ~B44_FLAG_PAUSE_AUTO;
+		if (epause.rx_pause)
+			bp->flags |= B44_FLAG_RX_PAUSE;
+		else
+			bp->flags &= ~B44_FLAG_RX_PAUSE;
+		if (epause.tx_pause)
+			bp->flags |= B44_FLAG_TX_PAUSE;
+		else
+			bp->flags &= ~B44_FLAG_TX_PAUSE;
+		if (bp->flags & B44_FLAG_PAUSE_AUTO) {
+			b44_halt(bp);
+			b44_init_rings(bp);
+			b44_init_hw(bp, 1);
+		} else {
+			__b44_set_flow_ctrl(bp, bp->flags);
+		}
+		spin_unlock_irq(&bp->lock);
+
+		b44_enable_ints(bp);
+		
+		return 0;
+	}
+	};
+
+	return -EOPNOTSUPP;
+}
+
 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 {
 	struct mii_ioctl_data *data = if_mii(ifr);
 	struct b44 *bp = netdev_priv(dev);
 	int err = -EINVAL;
 
-	if (!netif_running(dev))
+	if (bp->pdev->device != PCI_DEVICE_ID_BCM4713) {
+		if (!netif_running(dev))
+			goto out;
+
+		spin_lock_irq(&bp->lock);
+		err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
+		spin_unlock_irq(&bp->lock);
 		goto out;
+	}
 
-	spin_lock_irq(&bp->lock);
-	err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
-	spin_unlock_irq(&bp->lock);
+	switch (cmd) {
+	case SIOCETHTOOL:
+		return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
+
+	case SIOCGMIIPHY:
+		data->phy_id = bp->phy_addr;
+
+		/* fallthru */
+	case SIOCGMIIREG: {
+		u32 mii_regval;
+		spin_lock_irq(&bp->lock);
+		err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
+		spin_unlock_irq(&bp->lock);
+
+		data->val_out = mii_regval;
+
+		return err;
+	}
+
+	case SIOCSMIIREG:
+		if (!capable(CAP_NET_ADMIN))
+			return -EPERM;
+
+		spin_lock_irq(&bp->lock);
+		err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
+		spin_unlock_irq(&bp->lock);
+
+		return err;
+
+	default:
+		break;
+	};
+	return -EOPNOTSUPP;
+		
 out:
 	return err;
 }
@@ -2063,27 +2446,65 @@ static int b44_read_eeprom(struct b44 *b
 static int __devinit b44_get_invariants(struct b44 *bp)
 {
 	u8 eeprom[128];
-	int err;
+	u8 buf[32];
+	int err = 0;
+	unsigned long flags;
+
+#ifdef CONFIG_BCM947XX
+	if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
+		/*
+		 * BCM47xx boards don't have a EEPROM. The MAC is stored in
+		 * a NVRAM area somewhere in the flash memory.
+		 */
+		sprintf(buf, "et%dmacaddr", b44_4713_instance);
+		if (nvram_get(buf)) {
+			e_aton(nvram_get(buf), bp->dev->dev_addr);
+		} else {
+			/*
+			 * Getting the MAC out of NVRAM failed. To make it work
+			 * here, we simply rely on the bootloader to write the
+			 * MAC into the CAM.
+			 */
+			spin_lock_irqsave(&bp->lock, flags);
+			__b44_cam_read(bp, bp->dev->dev_addr, 0);
+			spin_unlock_irqrestore(&bp->lock, flags);
+		}
 
-	err = b44_read_eeprom(bp, &eeprom[0]);
-	if (err)
-		goto out;
+		if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
+			printk(KERN_ERR PFX "Invalid MAC address found in NVRAM\n");
+			return -EINVAL;
+		}
 
-	bp->dev->dev_addr[0] = eeprom[79];
-	bp->dev->dev_addr[1] = eeprom[78];
-	bp->dev->dev_addr[2] = eeprom[81];
-	bp->dev->dev_addr[3] = eeprom[80];
-	bp->dev->dev_addr[4] = eeprom[83];
-	bp->dev->dev_addr[5] = eeprom[82];
+		/*
+		 * BCM47xx boards don't have a PHY. Usually there is a switch
+		 * chip with multiple PHYs connected to the PHY port.
+		 */
+		bp->phy_addr = B44_PHY_ADDR_NO_PHY;
+		bp->dma_offset = 0;
+	} else
+#endif
+	{
+		err = b44_read_eeprom(bp, &eeprom[0]);
+		if (err)
+			goto out;
 
-	if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
-		printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
-		return -EINVAL;
-	}
+		bp->dev->dev_addr[0] = eeprom[79];
+		bp->dev->dev_addr[1] = eeprom[78];
+		bp->dev->dev_addr[2] = eeprom[81];
+		bp->dev->dev_addr[3] = eeprom[80];
+		bp->dev->dev_addr[4] = eeprom[83];
+		bp->dev->dev_addr[5] = eeprom[82];
+
+		if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
+			printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
+			return -EINVAL;
+		}
 
-	memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
+		memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
 
-	bp->phy_addr = eeprom[90] & 0x1f;
+		bp->phy_addr = eeprom[90] & 0x1f;
+		bp->dma_offset = SB_PCI_DMA;
+	}
 
 	/* With this, plus the rx_header prepended to the data by the
 	 * hardware, we'll land the ethernet header on a 2-byte boundary.
@@ -2093,11 +2514,6 @@ static int __devinit b44_get_invariants(
 	bp->imask = IMASK_DEF;
 
 	bp->core_unit = ssb_core_unit(bp);
-	bp->dma_offset = SB_PCI_DMA;
-
-	/* XXX - really required?
-	   bp->flags |= B44_FLAG_BUGGY_TXPTR;
-         */
 
  	if (ssb_get_core_rev(bp) >= 7)
  		bp->flags |= B44_FLAG_B0_ANDLATER;
@@ -2244,11 +2660,17 @@ #endif
 	 */
 	b44_chip_reset(bp);
 
-	printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
+	printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
+		(pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
 	for (i = 0; i < 6; i++)
 		printk("%2.2x%c", dev->dev_addr[i],
 		       i == 5 ? '\n' : ':');
 
+	/* Initialize phy */
+	spin_lock_irq(&bp->lock);
+	b44_chip_reset(bp);
+	spin_unlock_irq(&bp->lock);
+
 	return 0;
 
 err_out_iounmap:
diff --git a/drivers/net/b44.h b/drivers/net/b44.h
index 4944507..1e6f2c5 100644
--- a/drivers/net/b44.h
+++ b/drivers/net/b44.h
@@ -129,6 +129,7 @@ #define  RXCONFIG_LPBACK	0x00000010 /* L
 #define  RXCONFIG_FLOW		0x00000020 /* Flow Control Enable */
 #define  RXCONFIG_FLOW_ACCEPT	0x00000040 /* Accept Unicast Flow Control Frame */
 #define  RXCONFIG_RFILT		0x00000080 /* Reject Filter */
+#define  RXCONFIG_CAM_ABSENT	0x00000100 /* CAM Absent */
 #define B44_RXMAXLEN	0x0404UL /* EMAC RX Max Packet Length */
 #define B44_TXMAXLEN	0x0408UL /* EMAC TX Max Packet Length */
 #define B44_MDIO_CTRL	0x0410UL /* EMAC MDIO Control */
@@ -297,6 +298,10 @@ #define SSB_PCI_MASK0		0xfc000000
 #define SSB_PCI_MASK1		0xfc000000
 #define SSB_PCI_MASK2		0xc0000000
 
+#define br32(bp, REG)	readl((void *)bp->regs + (REG))
+#define bw32(bp, REG,VAL)	writel((VAL), (void *)bp->regs + (REG))
+#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
+
 /* 4400 PHY registers */
 #define B44_MII_AUXCTRL		24	/* Auxiliary Control */
 #define  MII_AUXCTRL_DUPLEX	0x0001  /* Full Duplex */
@@ -350,6 +355,8 @@ struct ring_info {
 };
 
 #define B44_MCAST_TABLE_SIZE	32
+#define B44_PHY_ADDR_NO_PHY	30
+#define B44_MDC_RATIO		5000000
 
 #define	B44_STAT_REG_DECLARE		\
 	_B44(tx_good_octets)		\
@@ -428,6 +435,7 @@ struct b44 {
 #define B44_FLAG_B0_ANDLATER	0x00000001
 #define B44_FLAG_BUGGY_TXPTR	0x00000002
 #define B44_FLAG_REORDER_BUG	0x00000004
+#define B44_FLAG_INIT_COMPLETE	0x00000008
 #define B44_FLAG_PAUSE_AUTO	0x00008000
 #define B44_FLAG_FULL_DUPLEX	0x00010000
 #define B44_FLAG_100_BASE_T	0x00020000
-- 
1.4.1
--------------020609010802070204080008-- From M.B.Lankhorst@gmail.com Tue Oct 10 16:22:45 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Oct 2006 16:22:49 +0100 (BST) Received: from mailserver.astro.rug.nl ([129.125.6.166]:31635 "EHLO mailserver.intra.astro.rug.nl") by ftp.linux-mips.org with ESMTP id S20039896AbWJJPWp (ORCPT ); Tue, 10 Oct 2006 16:22:45 +0100 Received: from [145.99.147.181] (guesswhos.boldlygoingnowhere.org [145.99.147.181]) (authenticated bits=0) by mailserver.intra.astro.rug.nl (8.12.11.20060308/8.12.11) with ESMTP id k9AFMccp003947 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 10 Oct 2006 17:22:38 +0200 Message-ID: <452BBB03.2080709@gmail.com> Date: Tue, 10 Oct 2006 17:23:47 +0200 From: Maarten Lankhorst User-Agent: Thunderbird 1.5.0.7 (Windows/20060909) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: [MIPS] Add bcm947xx support [5/5] Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12871 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: M.B.Lankhorst@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 85 Lines: 2 Add support for the leds in this device. (I know, I forgot 'depends on' in Kconfig) From 9489beb320fab8a2cf8ff135072ac6e1f0727622 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 10 Oct 2006 13:21:42 +0200 Subject: [PATCH] bcm947xx-led-support Content-Length: 8304 Lines: 338 --- drivers/net/Kconfig | 5 + drivers/net/Makefile | 1 drivers/net/diag/Makefile | 5 + drivers/net/diag/diag.c | 283 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 294 insertions(+), 0 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 414b949..b2e8775 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -60,6 +60,11 @@ config DUMMY Instead of 'dummy', the devices will then be called 'dummy0', 'dummy1' etc. +config DIAG_LED + tristate "Led driver for Broadcom BCM97xx" + ---help--- + Say 'Y' or 'M' if you like the leds to signal status of operation. + config BONDING tristate "Bonding driver support" depends on INET diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 0c08ede..9ab7bc9 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -1,6 +1,7 @@ # # Makefile for the Linux network (ethercard) device drivers. # +obj-$(CONFIG_DIAG_LED) += diag/ obj-$(CONFIG_E1000) += e1000/ obj-$(CONFIG_IBM_EMAC) += ibm_emac/ diff --git a/drivers/net/diag/Makefile b/drivers/net/diag/Makefile new file mode 100644 index 0000000..f87a62d --- /dev/null +++ b/drivers/net/diag/Makefile @@ -0,0 +1,5 @@ +#$Id$ + +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER + +obj-$(CONFIG_DIAG_LED) += diag.o diff --git a/drivers/net/diag/diag.c b/drivers/net/diag/diag.c new file mode 100644 index 0000000..09bb8a9 --- /dev/null +++ b/drivers/net/diag/diag.c @@ -0,0 +1,283 @@ +/* + * diag_led.c - replacement diag module + * + * Copyright (C) 2004 Mike Baker, + * Imre Kaloz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * $Id$ + */ + +/* + * ChangeLog: + * 2004/03/28 initial release + * 2004/08/26 asus & buffalo support added + * 2005/03/14 asus wl-500g deluxe and buffalo v2 support added + * 2005/04/13 added licensing informations + * 2005/04/18 base reset polarity off initial readings + * 2006/02/07 motorola wa840g/we800g support added + * 2006/08/18 asus power led support added + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern char * nvram_get(const char *name); +static void *sbh; + +// v2.x - - - - - +#define DIAG_GPIO (1<<1) +#define DMZ_GPIO (1<<7) + +static void set_gpio(uint32_t mask, uint32_t value) { + sb_gpiocontrol(sbh,mask, 0, GPIO_DRV_PRIORITY); + sb_gpioouten(sbh,mask,mask,GPIO_DRV_PRIORITY); + sb_gpioout(sbh,mask,value,GPIO_DRV_PRIORITY); +} + +static void v2_set_diag(u8 state) { + set_gpio(DIAG_GPIO,state); +} +static void v2_set_dmz(u8 state) { + set_gpio(DMZ_GPIO,state); +} + +// asus wl-500g (+deluxe) +#define ASUS_PWR_GPIO (1<<0) + +static void asus_set_pwr(u8 state) { + set_gpio(ASUS_PWR_GPIO,state); +} + +// v1.x - - - - - +#define LED_DIAG 0x13 +#define LED_DMZ 0x12 + +static void v1_set_diag(u8 state) { + if (!state) { + *(volatile u8*)(KSEG1ADDR(BCM4710_EUART)+LED_DIAG)=0xFF; + } else { + *(volatile u8*)(KSEG1ADDR(BCM4710_EUART)+LED_DIAG); + } +} +static void v1_set_dmz(u8 state) { + if (!state) { + *(volatile u8*)(KSEG1ADDR(BCM4710_EUART)+LED_DMZ)=0xFF; + } else { + *(volatile u8*)(KSEG1ADDR(BCM4710_EUART)+LED_DMZ); + } +} + +static void wap1_set_diag(u8 state) { + set_gpio(1<<3,state); +} +static void wap1_set_dmz(u8 state) { + set_gpio(1<<4,state); +} + +// - - - - - +static void ignore(u8 ignored) {}; + +// - - - - - +#define BIT_DMZ 0x01 +#define BIT_PWR 0x02 +#define BIT_DIAG 0x04 + +void (*set_diag)(u8 state); +void (*set_dmz)(u8 state); +void (*set_pwr)(u8 state); + +static unsigned int diag = 0x02; // default: diag off, pwr on, dmz off + +static void