From anemo@mba.ocn.ne.jp Fri Sep 1 04:35:25 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Sep 2006 04:35:27 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:44608 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20027677AbWIADfZ (ORCPT ); Fri, 1 Sep 2006 04:35:25 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Fri, 1 Sep 2006 12:35:23 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 243C7204AD; Fri, 1 Sep 2006 12:35:19 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 188BF1FF0A; Fri, 1 Sep 2006 12:35:19 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k813ZGW0053279; Fri, 1 Sep 2006 12:35:18 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Fri, 01 Sep 2006 12:35:16 +0900 (JST) Message-Id: <20060901.123516.21957726.nemoto@toshiba-tops.co.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, nigel@mips.com Subject: Re: [MIPS] Fix COW D-cache aliasing on fork From: Atsushi Nemoto In-Reply-To: References: X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12495 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Thu, 31 Aug 2006 21:32:39 +0100, linux-mips@linux-mips.org wrote: > Author: Atsushi Nemoto Thu Aug 24 00:31:30 2006 +0900 > Comitter: Ralf Baechle Thu Aug 31 19:50:02 2006 +0100 > Commit: b895b66990f22a8a030c41390c538660a02bb97f > Gitweb: http://www.linux-mips.org/g/linux/b895b669 > Branch: master Thanks!!! And please commit this fix too. The tlbidx variable should be signed int so that "tlbidx < 0" comparison works correctly. Nigel Stephens pointed this out. Signed-off-by: Atsushi Nemoto diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 2cfdc0b..bbc9458 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -136,7 +136,7 @@ static inline void *kmap_coherent(struct unsigned long vaddr, flags, entrylo; unsigned long old_ctx; pte_t pte; - unsigned int tlbidx; + int tlbidx; inc_preempt_count(); idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); From hemanth.venkatesh@wipro.com Fri Sep 1 07:29:09 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Sep 2006 07:29:13 +0100 (BST) Received: from wip-ec-wd.wipro.com ([203.91.193.32]:159 "EHLO wip-ec-wd.wipro.com") by ftp.linux-mips.org with ESMTP id S20037857AbWIAG3J (ORCPT ); Fri, 1 Sep 2006 07:29:09 +0100 Received: from wip-ec-wd.wipro.com (localhost.wipro.com [127.0.0.1]) by localhost (Postfix) with ESMTP id 3EAC32062C for ; Fri, 1 Sep 2006 11:55:03 +0530 (IST) Received: from blr-ec-bh02.wipro.com (blr-ec-bh02.wipro.com [10.201.50.92]) by wip-ec-wd.wipro.com (Postfix) with ESMTP id 270D320621 for ; Fri, 1 Sep 2006 11:55:03 +0530 (IST) Received: from blr-m2-msg.wipro.com ([10.116.50.99]) by blr-ec-bh02.wipro.com with Microsoft SMTPSVC(6.0.3790.1830); Fri, 1 Sep 2006 11:58:58 +0530 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C6CD8F.DF8228AA" Subject: AU1100 and AU1200 UDC Drivers Date: Fri, 1 Sep 2006 11:58:44 +0530 Message-ID: <2156B1E923F1A147AABDF4D9FDEAB4CB13829B@blr-m2-msg.wipro.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: AU1100 and AU1200 UDC Drivers Thread-Index: AcbNjwDH5nG/y0sBT0yxGvijxmAfqA== From: To: X-OriginalArrivalTime: 01 Sep 2006 06:28:58.0233 (UTC) FILETIME=[E7F63E90:01C6CD8F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12496 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hemanth.venkatesh@wipro.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. ------_=_NextPart_001_01C6CD8F.DF8228AA Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi All, =20 Does anyone have working peripheral controller drivers for AU1100 and AU1200 SOCs. I did see some patches in the mailing list, but doesn't seem to be part of the 2.6.17 linux-mips source. =20 Thanks Hemanth ------_=_NextPart_001_01C6CD8F.DF8228AA Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi All,

 

Does anyone have working peripheral controller = drivers for AU1100 and AU1200 SOCs. I did see some patches in the mailing list, but = doesn’t seem to be part of the 2.6.17 linux-mips = source.

 

Thanks

Hemanth

------_=_NextPart_001_01C6CD8F.DF8228AA-- From david.goodenough@linkchoose.co.uk Fri Sep 1 11:51:06 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Sep 2006 11:51:07 +0100 (BST) Received: from ip-217-204-115-127.easynet.co.uk ([217.204.115.127]:46864 "EHLO apollo.linkchoose.co.uk") by ftp.linux-mips.org with ESMTP id S20038427AbWIAKvG (ORCPT ); Fri, 1 Sep 2006 11:51:06 +0100 Received: from [10.98.1.127] (helo=galaxy.dga.co.uk) by apollo.linkchoose.co.uk with esmtp (Exim 4.60) (envelope-from ) id 1GJ6c9-0003Ns-An for linux-mips@linux-mips.org; Fri, 01 Sep 2006 11:51:09 +0100 Received: from [10.0.1.63] by galaxy.dga.co.uk with esmtp (Exim 4.62) (envelope-from ) id 1GJ6bs-0003LW-5t for linux-mips@linux-mips.org; Fri, 01 Sep 2006 11:50:53 +0100 From: David Goodenough Organization: Linkchoose Ltd To: linux-mips@linux-mips.org Subject: ADM5120 support Date: Fri, 1 Sep 2006 11:50:54 +0100 User-Agent: KMail/1.9.3 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200609011150.54312.david.goodenough@linkchoose.co.uk> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12497 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.goodenough@linkchoose.co.uk Precedence: bulk X-list: linux-mips I have found some patches for the ADM5120 on the web for 2.6.12, but nothing more recent. Anyone know of an updated patch (if updating is needed)? David From anemo@mba.ocn.ne.jp Fri Sep 1 16:41:24 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Sep 2006 16:41:27 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:15320 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20038478AbWIAPlY (ORCPT ); Fri, 1 Sep 2006 16:41:24 +0100 Received: from localhost (p2154-ipad201funabasi.chiba.ocn.ne.jp [222.146.65.154]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 231ABBBAB; Sat, 2 Sep 2006 00:41:15 +0900 (JST) Date: Sat, 02 Sep 2006 00:43:07 +0900 (JST) Message-Id: <20060902.004307.41010946.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] remove __flush_icache_page From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12498 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Now nobody use __flash_icache_page. We can remove them completely. Signed-off-by: Atsushi Nemoto diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index e1f35ef..d1af42c 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -268,26 +268,6 @@ static void r3k_flush_data_cache_page(un { } -static void r3k_flush_icache_page(struct vm_area_struct *vma, struct page *page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long physpage; - - if (cpu_context(smp_processor_id(), mm) == 0) - return; - - if (!(vma->vm_flags & VM_EXEC)) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", cpu_context(smp_processor_id(), mm), page); -#endif - - physpage = (unsigned long) page_address(page); - if (physpage) - r3k_flush_icache_range(physpage, physpage + PAGE_SIZE); -} - static void r3k_flush_cache_sigtramp(unsigned long addr) { unsigned long flags; @@ -335,7 +315,6 @@ void __init r3k_cache_init(void) flush_cache_mm = r3k_flush_cache_mm; flush_cache_range = r3k_flush_cache_range; flush_cache_page = r3k_flush_cache_page; - __flush_icache_page = r3k_flush_icache_page; flush_icache_range = r3k_flush_icache_range; flush_cache_sigtramp = r3k_flush_cache_sigtramp; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 2d729f6..6477e4a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -551,82 +551,6 @@ static void r4k_flush_icache_range(unsig instruction_hazard(); } -/* - * Ok, this seriously sucks. We use them to flush a user page but don't - * know the virtual address, so we have to blast away the whole icache - * which is significantly more expensive than the real thing. Otoh we at - * least know the kernel address of the page so we can flush it - * selectivly. - */ - -struct flush_icache_page_args { - struct vm_area_struct *vma; - struct page *page; -}; - -static inline void local_r4k_flush_icache_page(void *args) -{ - struct flush_icache_page_args *fip_args = args; - struct vm_area_struct *vma = fip_args->vma; - struct page *page = fip_args->page; - - /* - * Tricky ... Because we don't know the virtual address we've got the - * choice of either invalidating the entire primary and secondary - * caches or invalidating the secondary caches also. With the subset - * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the - * secondary cache will result in any entries in the primary caches - * also getting invalidated which hopefully is a bit more economical. - */ - if (cpu_has_inclusive_pcaches) { - unsigned long addr = (unsigned long) page_address(page); - - r4k_blast_scache_page(addr); - ClearPageDcacheDirty(page); - - return; - } - - if (!cpu_has_ic_fills_f_dc) { - unsigned long addr = (unsigned long) page_address(page); - r4k_blast_dcache_page(addr); - if (!cpu_icache_snoops_remote_store) - r4k_blast_scache_page(addr); - ClearPageDcacheDirty(page); - } - - /* - * We're not sure of the virtual address(es) involved here, so - * we have to flush the entire I-cache. - */ - if (cpu_has_vtag_icache && vma->vm_mm == current->active_mm) { - int cpu = smp_processor_id(); - - if (cpu_context(cpu, vma->vm_mm) != 0) - drop_mmu_context(vma->vm_mm, cpu); - } else - r4k_blast_icache(); -} - -static void r4k_flush_icache_page(struct vm_area_struct *vma, - struct page *page) -{ - struct flush_icache_page_args args; - - /* - * If there's no context yet, or the page isn't executable, no I-cache - * flush is needed. - */ - if (!(vma->vm_flags & VM_EXEC)) - return; - - args.vma = vma; - args.page = page; - - r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1); -} - - #ifdef CONFIG_DMA_NONCOHERENT static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) @@ -1291,7 +1215,6 @@ void __init r4k_cache_init(void) __flush_cache_all = r4k___flush_cache_all; flush_cache_mm = r4k_flush_cache_mm; flush_cache_page = r4k_flush_cache_page; - __flush_icache_page = r4k_flush_icache_page; flush_cache_range = r4k_flush_cache_range; flush_cache_sigtramp = r4k_flush_cache_sigtramp; diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c index 16bad7c..5537558 100644 --- a/arch/mips/mm/c-sb1.c +++ b/arch/mips/mm/c-sb1.c @@ -307,66 +307,6 @@ void sb1_flush_icache_range(unsigned lon #endif /* - * Flush the icache for a given physical page. Need to writeback the - * dcache first, then invalidate the icache. If the page isn't - * executable, nothing is required. - */ -static void local_sb1_flush_icache_page(struct vm_area_struct *vma, - struct page *page) -{ - unsigned long start; - int cpu = smp_processor_id(); - -#ifndef CONFIG_SMP - if (!(vma->vm_flags & VM_EXEC)) - return; -#endif - - /* Need to writeback any dirty data for that page, we have the PA */ - start = (unsigned long)(page-mem_map) << PAGE_SHIFT; - __sb1_writeback_inv_dcache_phys_range(start, start + PAGE_SIZE); - /* - * If there's a context, bump the ASID (cheaper than a flush, - * since we don't know VAs!) - */ - if (vma->vm_mm == current->active_mm) { - if (cpu_context(cpu, vma->vm_mm) != 0) - drop_mmu_context(vma->vm_mm, cpu); - } else - __sb1_flush_icache_range(start, start + PAGE_SIZE); - -} - -#ifdef CONFIG_SMP -struct flush_icache_page_args { - struct vm_area_struct *vma; - struct page *page; -}; - -static void sb1_flush_icache_page_ipi(void *info) -{ - struct flush_icache_page_args *args = info; - local_sb1_flush_icache_page(args->vma, args->page); -} - -/* Dirty dcache could be on another CPU, so do the IPIs */ -static void sb1_flush_icache_page(struct vm_area_struct *vma, - struct page *page) -{ - struct flush_icache_page_args args; - - if (!(vma->vm_flags & VM_EXEC)) - return; - args.vma = vma; - args.page = page; - on_each_cpu(sb1_flush_icache_page_ipi, (void *) &args, 1, 1); -} -#else -void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page) - __attribute__((alias("local_sb1_flush_icache_page"))); -#endif - -/* * A signal trampoline must fit into a single cacheline. */ static void local_sb1_flush_cache_sigtramp(unsigned long addr) @@ -526,7 +466,6 @@ #endif /* These routines are for Icache coherence with the Dcache */ flush_icache_range = sb1_flush_icache_range; - __flush_icache_page = sb1_flush_icache_page; flush_icache_all = __sb1_flush_icache_all; /* local only */ /* This implies an Icache flush too, so can't be nop'ed */ diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index 932a09d..f32ebde 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -248,33 +248,6 @@ static void tx39_flush_icache_range(unsi } } -/* - * Ok, this seriously sucks. We use them to flush a user page but don't - * know the virtual address, so we have to blast away the whole icache - * which is significantly more expensive than the real thing. Otoh we at - * least know the kernel address of the page so we can flush it - * selectivly. - */ -static void tx39_flush_icache_page(struct vm_area_struct *vma, struct page *page) -{ - unsigned long addr; - /* - * If there's no context yet, or the page isn't executable, no icache - * flush is needed. - */ - if (!(vma->vm_flags & VM_EXEC)) - return; - - addr = (unsigned long) page_address(page); - tx39_blast_dcache_page(addr); - - /* - * We're not sure of the virtual address(es) involved here, so - * we have to flush the entire I-cache. - */ - tx39_blast_icache(); -} - static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size) { unsigned long end; @@ -382,7 +355,6 @@ void __init tx39_cache_init(void) flush_cache_mm = (void *) tx39h_flush_icache_all; flush_cache_range = (void *) tx39h_flush_icache_all; flush_cache_page = (void *) tx39h_flush_icache_all; - __flush_icache_page = (void *) tx39h_flush_icache_all; flush_icache_range = (void *) tx39h_flush_icache_all; flush_cache_sigtramp = (void *) tx39h_flush_icache_all; @@ -408,7 +380,6 @@ void __init tx39_cache_init(void) flush_cache_mm = tx39_flush_cache_mm; flush_cache_range = tx39_flush_cache_range; flush_cache_page = tx39_flush_cache_page; - __flush_icache_page = tx39_flush_icache_page; flush_icache_range = tx39_flush_icache_range; flush_cache_sigtramp = tx39_flush_cache_sigtramp; diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 40c8b02..caf807d 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -25,7 +25,6 @@ void (*flush_cache_range)(struct vm_area void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); void (*flush_icache_range)(unsigned long start, unsigned long end); -void (*__flush_icache_page)(struct vm_area_struct *vma, struct page *page); /* MIPS specific cache operations */ void (*flush_cache_sigtramp)(unsigned long addr); diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h index d10517c..e3c9925 100644 --- a/include/asm-mips/cacheflush.h +++ b/include/asm-mips/cacheflush.h @@ -46,8 +46,6 @@ static inline void flush_dcache_page(str #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) -extern void (*__flush_icache_page)(struct vm_area_struct *vma, - struct page *page); static inline void flush_icache_page(struct vm_area_struct *vma, struct page *page) { From imipak@yahoo.com Fri Sep 1 17:40:11 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Sep 2006 17:40:13 +0100 (BST) Received: from web31504.mail.mud.yahoo.com ([68.142.198.133]:23992 "HELO web31504.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20038519AbWIAQkL (ORCPT ); Fri, 1 Sep 2006 17:40:11 +0100 Received: (qmail 49313 invoked by uid 60001); 1 Sep 2006 16:38:39 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=uN1DpCiNOo8KpBdfcXSN1O3uDVh4VXjs0rlvMIa8z1AmBI6lYEPMyeXLRb+jq9ChhrnAawSg/f4yc8aleo2pxCD8DNwzqfUVoO9yfVK+UkHRxbU0p7z3TByJod2A5mxI4I8GePPF+WTXBAJCiClrRodkiRMGuhEyOgi55WpPhlw= ; Message-ID: <20060901163839.49311.qmail@web31504.mail.mud.yahoo.com> Received: from [70.103.67.194] by web31504.mail.mud.yahoo.com via HTTP; Fri, 01 Sep 2006 09:38:39 PDT Date: Fri, 1 Sep 2006 09:38:39 -0700 (PDT) From: Jonathan Day Subject: Broadcom SB1 query To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12499 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips Hi, Can anyone verify that the current kernel in linux-mips git archive will work on a Broadcom 1250 (SB1), specifically the "Swarm" or the "Sentosa" flavours of the BCM91250. I have not been able to get anything more recent than a 2.6.17 kernel to compile and boot, the 2.6.18-rc kernels seem to randomly either lock up or reboot very early on in the kernel initialization. However, I am undecided whether it's a kernel issue, a hardware issue (we've had nothing but trouble from these boards) or a toolchain issue (versions: gcc 4.1.1, libc 2.4, binutils 2.17.50) as I've found a few large projects that should compile just fine are blowing the compiler up. If someone can post (or e-mail me direct) on what the latest combination of kernel and toolchain that works on the Swarm is, I would greatly appreciate it. This problem is driving me nuts. (Ok, more nuts than usual.) Jonathan __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From ths@networkno.de Fri Sep 1 18:39:02 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Sep 2006 18:39:04 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:30394 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20038524AbWIARjC (ORCPT ); Fri, 1 Sep 2006 18:39:02 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 0812C46590; Fri, 1 Sep 2006 19:39:21 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GJCxO-00067I-9x; Fri, 01 Sep 2006 18:37:30 +0100 Date: Fri, 1 Sep 2006 18:37:30 +0100 To: Jonathan Day Cc: linux-mips@linux-mips.org Subject: Re: Broadcom SB1 query Message-ID: <20060901173730.GC4893@networkno.de> References: <20060901163839.49311.qmail@web31504.mail.mud.yahoo.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060901163839.49311.qmail@web31504.mail.mud.yahoo.com> User-Agent: Mutt/1.5.13 (2006-08-11) From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12500 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Jonathan Day wrote: > Hi, > > Can anyone verify that the current kernel in > linux-mips git archive will work on a Broadcom 1250 > (SB1), specifically the "Swarm" or the "Sentosa" > flavours of the BCM91250. A 2.6.18-rc4 from a one week old git checkout works fine on a SWARM here, booted via tftp. The same kernel fails to boot on another SWARM board from the onboard IDE, I guess the swarm-ide is currently broken. > I have not been able to get anything more recent than > a 2.6.17 kernel to compile and boot, the 2.6.18-rc > kernels seem to randomly either lock up or reboot very > early on in the kernel initialization. However, I am > undecided whether it's a kernel issue, I presume you know that PCI devices and more than 1 GB of RAM don't work under Linux. > a hardware > issue (we've had nothing but trouble from these > boards) or a toolchain issue (versions: gcc 4.1.1, > libc 2.4, binutils 2.17.50) as I've found a few large > projects that should compile just fine are blowing the > compiler up. Hm, libc 2.4 means NPTL, that's not yet widely deployed and could well account for some exciting failures. > If someone can post (or e-mail me direct) on what the > latest combination of kernel and toolchain that works > on the Swarm is, I would greatly appreciate it. This > problem is driving me nuts. (Ok, more nuts than > usual.) Current Debian unstable works for me. Thiemo From imipak@yahoo.com Fri Sep 1 21:41:37 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Sep 2006 21:41:39 +0100 (BST) Received: from web31512.mail.mud.yahoo.com ([68.142.198.141]:40077 "HELO web31512.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20038553AbWIAUlh (ORCPT ); Fri, 1 Sep 2006 21:41:37 +0100 Received: (qmail 42146 invoked by uid 60001); 1 Sep 2006 20:41:31 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:Cc:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=3ZJGoq2bGO9gKnfSOAapEC+vuszhWZW2SjBbdin3X+LwIioS2B2xS6AUaZhMWS1Gq8i2kT4ShN/JgmsRAxtwySura3exGHQx8RD7+kNn37nFpN8aTSTBowlv1NWrNVTGWOtIo9VBcHlBNJn+XHOHvDmdrdFZi9OCy+kzB51mrOA= ; Message-ID: <20060901204131.42144.qmail@web31512.mail.mud.yahoo.com> Received: from [70.103.67.194] by web31512.mail.mud.yahoo.com via HTTP; Fri, 01 Sep 2006 13:41:31 PDT Date: Fri, 1 Sep 2006 13:41:31 -0700 (PDT) From: Jonathan Day Subject: Re: Broadcom SB1 query To: Thiemo Seufer Cc: linux-mips@linux-mips.org In-Reply-To: <20060901173730.GC4893@networkno.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12501 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips --- Thiemo Seufer wrote: > Jonathan Day wrote: > > Hi, > > > > Can anyone verify that the current kernel in > > linux-mips git archive will work on a Broadcom > 1250 > > (SB1), specifically the "Swarm" or the "Sentosa" > > flavours of the BCM91250. > > A 2.6.18-rc4 from a one week old git checkout works > fine on a SWARM > here, booted via tftp. The same kernel fails to boot > on another > SWARM board from the onboard IDE, I guess the > swarm-ide is currently > broken. That might explain it. I've included the output from the console at the end of this message, so you can take a squint at it and see if that confirms it. > > I have not been able to get anything more recent > than > > a 2.6.17 kernel to compile and boot, the 2.6.18-rc > > kernels seem to randomly either lock up or reboot > very > > early on in the kernel initialization. However, I > am > > undecided whether it's a kernel issue, > > I presume you know that PCI devices and more than 1 > GB of RAM don't > work under Linux. What a peculiar bug! (I don't think that's a limitation of PCI, but even if it were, Linux' VMM is more than sophisticated enough to map any assortment of pages that totalled a gigabyte or less into a blob such that buggy drivers or hardware only saw what memory they could handle, regardless of what physical memory has.) Regardless, the cards are all 1 Gb. > > a hardware > > issue (we've had nothing but trouble from these > > boards) or a toolchain issue (versions: gcc 4.1.1, > > libc 2.4, binutils 2.17.50) as I've found a few > large > > projects that should compile just fine are blowing > the > > compiler up. > > Hm, libc 2.4 means NPTL, that's not yet widely > deployed and could well > account for some exciting failures. Yeah. I've tried building from source as much as possible, but merely the lack of deployment opens up all kinds of possibilites of me hitting bugs others haven't seen, or don't see often enough to trace. I run some weird stuff on the Broadcom. > > If someone can post (or e-mail me direct) on what > the > > latest combination of kernel and toolchain that > works > > on the Swarm is, I would greatly appreciate it. > This > > problem is driving me nuts. (Ok, more nuts than > > usual.) > > Current Debian unstable works for me. > Well, my machine's already unstable, so I guess Debian can't hurt! :) I didn't know they had a big-endian 64-bit build, though. I'll have to look that up. Anyway, here is a logfile when trying to boot the swarm. As soon as it passes the high precision timer code, it jumps back into CFE. Starting program at 0x80633000 Broadcom SiByte BCM1250 B2 @ 800 MHz (SB1 rev 2) Board type: SiByte BCM91250A (SWARM) [17179569.184000] Linux version 2.6.18-rc5-swarm-lightfleet-0.4- gb895b669-dirty (root@10.1.3.202) (gcc version 4.1.1) #2 SMP PREEMPT Fri Sep 1 09:16:18 UTC 2006 [17179569.184000] CPU revision is: 01040102 [17179569.184000] FPU revision is: 000f0102 [17179569.184000] swarm setup: M41T81 RTC detected. [17179569.184000] This kernel optimized for board runs with CFE [17179569.184000] Determined physical RAM map: [17179569.184000] memory: 000000000fe99e00 @ 0000000000000000 (usable) [17179569.184000] memory: 000000001ffffe00 @ 0000000080000000 (usable) [17179569.184000] memory: 000000000ffffe00 @ 00000000c0000000 (usable) [17179569.184000] memory: 000000003ffffe00 @ 0000000100000000 (usable) [17179569.184000] Detected 1 available secondary CPU(s) [17179569.184000] Built 1 zonelists. Total pages: 1310719 [17179569.184000] Kernel command line: ip=any rw nfsroot=10.1.3.187:/home/developer root=/dev/nfs serial=1,115200n8 [17179569.184000] Primary instruction cache 32kB, 4-way, linesize 32 bytes. [17179569.184000] Primary data cache 32kB, 4-way, linesize 32 bytes. [17179569.184000] Synthesized TLB refill handler (39 instructions). [17179569.184000] Synthesized TLB load handler fastpath (53 instructions). [17179569.184000] Synthesized TLB store handler fastpath (48 instructions). [17179569.184000] Synthesized TLB modify handler fastpath (47 instructions). [17179569.184000] PID hash table entries: 4096 (order: 12, 32768 bytes) [17179569.184000] Using 512.000 MHz high precision timer. __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From ths@networkno.de Fri Sep 1 22:35:58 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Sep 2006 22:36:00 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:28330 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20038570AbWIAVf6 (ORCPT ); Fri, 1 Sep 2006 22:35:58 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 3EC6047443; Fri, 1 Sep 2006 23:34:24 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GJGch-0007XH-FI; Fri, 01 Sep 2006 22:32:23 +0100 Date: Fri, 1 Sep 2006 22:32:23 +0100 From: Thiemo Seufer To: Jonathan Day Cc: linux-mips@linux-mips.org Subject: Re: Broadcom SB1 query Message-ID: <20060901213223.GA24995@networkno.de> References: <20060901173730.GC4893@networkno.de> <20060901204131.42144.qmail@web31512.mail.mud.yahoo.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060901204131.42144.qmail@web31512.mail.mud.yahoo.com> User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12502 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Jonathan Day wrote: > --- Thiemo Seufer wrote: > > > Jonathan Day wrote: > > > Hi, > > > > > > Can anyone verify that the current kernel in > > > linux-mips git archive will work on a Broadcom > > 1250 > > > (SB1), specifically the "Swarm" or the "Sentosa" > > > flavours of the BCM91250. > > > > A 2.6.18-rc4 from a one week old git checkout works > > fine on a SWARM > > here, booted via tftp. The same kernel fails to boot > > on another > > SWARM board from the onboard IDE, I guess the > > swarm-ide is currently > > broken. > > That might explain it. I've included the output from > the console at the end of this message, so you can > take a squint at it and see if that confirms it. Hm, no. It hangs way too early for that. Looks like it dies on the first interrupts. [snip] > > Current Debian unstable works for me. > > > > Well, my machine's already unstable, so I guess Debian > can't hurt! :) I didn't know they had a big-endian > 64-bit build, though. I'll have to look that up. Only the kernel is 64 bit, userland is still 32 bit. This should at least help to verify the hardware. Thiemo From ashlesha@kenati.com Sat Sep 2 00:31:26 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Sep 2006 00:31:28 +0100 (BST) Received: from [69.90.147.196] ([69.90.147.196]:9094 "EHLO mail.kenati.com") by ftp.linux-mips.org with ESMTP id S20038655AbWIAXb0 (ORCPT ); Sat, 2 Sep 2006 00:31:26 +0100 Received: from [192.168.1.169] (adsl-71-130-109-177.dsl.snfc21.pacbell.net [71.130.109.177]) by mail.kenati.com (Postfix) with ESMTP id 136EDE404D for ; Fri, 1 Sep 2006 16:50:35 -0700 (PDT) Subject: early_initcall From: Ashlesha Shintre Reply-To: ashlesha@kenati.com To: linux-mips@linux-mips.org Content-Type: text/plain Date: Fri, 01 Sep 2006 16:38:40 -0700 Message-Id: <1157153920.8242.5.camel@sandbar.kenati.com> Mime-Version: 1.0 X-Mailer: Evolution 2.4.2.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12503 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ashlesha@kenati.com Precedence: bulk X-list: linux-mips Hi, I m using the 2.6.14.6 tree and trying to get the kernel running on the Encore M3 board. The kernel crashes during the boot process at the early_initcall. This function doesnt seem to be defined anywhere. Which is the last version of the 2.6 tree that still supports the early_initcall? Thanks, Ashlesha. From kaz@zeugmasystems.com Sat Sep 2 01:50:13 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Sep 2006 01:50:15 +0100 (BST) Received: from mail.zeugmasystems.com ([192.139.122.66]:57432 "EHLO zeugmasystems.com") by ftp.linux-mips.org with ESMTP id S20038659AbWIBAuN convert rfc822-to-8bit (ORCPT ); Sat, 2 Sep 2006 01:50:13 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: early_initcall Date: Fri, 1 Sep 2006 17:50:06 -0700 Message-ID: <66910A579C9312469A7DF9ADB54A8B7D366028@exchange.ZeugmaSystems.local> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: early_initcall Thread-Index: AcbOHtn4F6es/jjwRIGQDhE7P5JqjwACaz8g From: "Kaz Kylheku" To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12504 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kaz@zeugmasystems.com Precedence: bulk X-list: linux-mips > Ashlesha Shintre wrote: > > Hi, > > I m using the 2.6.14.6 tree and trying to get the kernel > running on the > Encore M3 board. > > The kernel crashes during the boot process at the > early_initcall. What is the exact output from the crash? > This function doesnt seem to be defined anywhere. It's not a function, but a macro. The macro is used to annotate a function as being among the list of functions that are called at startup by the "initcall" mechanism: a big loop that sweeps over a symbol table of registered initialization functions and calls them. E.g. #include /* ... */ int __init my_initialization_function(void) { printk(KERN_INFO "Hello, world\n"); } early_initcall(my_initialization_function); The __init tells the kernel build system that your function is not needed after initialization and its memory can be thrown away. The early_initcall arranges for the initialization call. Early means that it's in the first group of functions. If you suspect your kernel is dying during the calling of the initcall functions, you can turn on initcall debugging. Add these parameters to your kernel command line: debug debug_initcall Hope this helps. From sergio@amilda.org Sat Sep 2 04:30:05 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Sep 2006 04:30:07 +0100 (BST) Received: from [193.238.157.29] ([193.238.157.29]:24540 "EHLO MrWeb01.pc-net.at") by ftp.linux-mips.org with ESMTP id S20037503AbWIBDaF (ORCPT ); Sat, 2 Sep 2006 04:30:05 +0100 Received: from www.amilda.org (localhost [127.0.0.1]) by MrWeb01.pc-net.at (Postfix) with ESMTP id D394F216074 for ; Sat, 2 Sep 2006 05:29:56 +0200 (CEST) Received: from 201.230.45.190 (SquirrelMail authenticated user amilda0001) by www.amilda.org with HTTP; Fri, 1 Sep 2006 22:29:56 -0500 (PET) Message-ID: <58418.201.230.45.190.1157167796.squirrel@www.amilda.org> In-Reply-To: <200609011150.54312.david.goodenough@linkchoose.co.uk> References: <200609011150.54312.david.goodenough@linkchoose.co.uk> Date: Fri, 1 Sep 2006 22:29:56 -0500 (PET) Subject: Re: ADM5120 support From: "Sergio Aguayo" To: linux-mips@linux-mips.org User-Agent: SquirrelMail/1.4.6-rc1 MIME-Version: 1.0 Content-Type: text/plain;charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Priority: 3 (Normal) Importance: Normal Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12505 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sergio@amilda.org Precedence: bulk X-list: linux-mips Hello As far as i know there aren't any more recent patches for it, as far as the 2,6 branch is reffered. I have a patch for 2.4.32, other people too. You can find the patches at: http://www.amilda.org/ (my site, we have a little distribution for ADM5120-based routers) http://midgle.vlad.org.ua/ (another distribution, but with different goal) Hope this helps you. Sergio Aguayo > I have found some patches for the ADM5120 on the web for 2.6.12, but > nothing > more recent. Anyone know of an updated patch (if updating is needed)? > > David > > From nidajm@gmail.com Sat Sep 2 12:45:25 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Sep 2006 12:45:27 +0100 (BST) Received: from py-out-1112.google.com ([64.233.166.182]:50915 "EHLO py-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S20038684AbWIBLpZ (ORCPT ); Sat, 2 Sep 2006 12:45:25 +0100 Received: by py-out-1112.google.com with SMTP id i49so1314455pyi for ; Sat, 02 Sep 2006 04:45:23 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=BmPLIe/MVtSMBkBGPKWEMkNt/jK+Z+ctsrw9GeXC1tU+re4J06Y8zxyAqQfyNDX9rUog2r0olli+8VTnuZD/osaqOp89NbcwBq9ld2AYlP4K+uzevFJn5KizXNCMggIANeCz5r1Gx9wGKkKS4GVPp0z1edT4dousBi8GvDYCxfM= Received: by 10.65.237.1 with SMTP id o1mr1385433qbr; Sat, 02 Sep 2006 04:45:23 -0700 (PDT) Received: by 10.65.126.5 with HTTP; Sat, 2 Sep 2006 04:45:23 -0700 (PDT) Message-ID: Date: Sat, 2 Sep 2006 17:15:23 +0530 From: "Nida M" To: linux-mips@linux-mips.org Subject: single step in MIPS MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12506 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nidajm@gmail.com Precedence: bulk X-list: linux-mips Hi, I am woking for linux2.6.16 on MIPS platform. I am tring to implement single stepping on MIPS. But I found that there is no single step instruction in the MIPS. I need to implement single stepping for MIPS Can anybody help me in this..?? Is there any alternative to generate this exception..?? Thanks and Regards ~Nida From alan@lxorguk.ukuu.org.uk Sat Sep 2 16:45:33 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 Sep 2006 16:46:05 +0100 (BST) Received: from outpipe-village-512-1.bc.nu ([81.2.110.250]:59021 "EHLO lxorguk.ukuu.org.uk") by ftp.linux-mips.org with ESMTP id S20038716AbWIBPpd (ORCPT ); Sat, 2 Sep 2006 16:45:33 +0100 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by lxorguk.ukuu.org.uk (8.13.6/8.13.4) with ESMTP id k82G7uI4022291; Sat, 2 Sep 2006 17:07:56 +0100 Received: (from alan@localhost) by localhost.localdomain (8.13.6/8.13.6/Submit) id k82G7tsR022290; Sat, 2 Sep 2006 17:07:55 +0100 X-Authentication-Warning: localhost.localdomain: alan set sender to alan@lxorguk.ukuu.org.uk using -f Subject: Re: single step in MIPS From: Alan Cox To: Nida M Cc: linux-mips@linux-mips.org In-Reply-To: References: Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Sat, 02 Sep 2006 17:07:54 +0100 Message-Id: <1157213274.6271.382.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.6.2 (2.6.2-1.fc5.5) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12507 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alan@lxorguk.ukuu.org.uk Precedence: bulk X-list: linux-mips Ar Sad, 2006-09-02 am 17:15 +0530, ysgrifennodd Nida M: > I am woking for linux2.6.16 on MIPS platform. > I am tring to implement single stepping on MIPS. > But I found that there is no single step instruction in the MIPS. There is no single step instruction feature on most processors. Nor any need to "implement" single step I suspect man 2 ptrace man gdb The tools exist as standard. From sshtylyov@ru.mvista.com Sun Sep 3 19:16:27 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Sep 2006 19:16:32 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:57676 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20039007AbWICSQ1 (ORCPT ); Sun, 3 Sep 2006 19:16:27 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id CCD9B3ECE; Sun, 3 Sep 2006 11:16:04 -0700 (PDT) Message-ID: <44FB1C26.10402@ru.mvista.com> Date: Sun, 03 Sep 2006 22:17:10 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Linux-MIPS Cc: Manish Lachwani , Ralf Baechle Subject: [PATCH] Au1xx0 code sets incorrect mips_hpt_frequency References: <436FB625.2000302@ru.mvista.com> <4480AB90.8020203@ru.mvista.com> In-Reply-To: <4480AB90.8020203@ru.mvista.com> Content-Type: multipart/mixed; boundary="------------080102080909070809080704" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12508 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------080102080909070809080704 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Alchemy CPU counter ticks at the full CPU clock speed, not at the halved one -- this is not an issue with the current kernel since Alchemy uses its own timer handler here which pays no attention to mips_hpt_frequency. Signed-off-by: Sergei Shtylyov --- I joined this fix to the arch/mips/au1000/common/time.c cleanup patch previously but its earlier verison has been finally committed, so here's the recast which fixes the warning about the 'count' variable being unused... --------------080102080909070809080704 Content-Type: text/plain; name="Au1xx0-fix-counter-frequency.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="Au1xx0-fix-counter-frequency.patch" Index: linux-mips/arch/mips/au1000/common/time.c =================================================================== --- linux-mips.orig/arch/mips/au1000/common/time.c +++ linux-mips/arch/mips/au1000/common/time.c @@ -231,7 +231,6 @@ wakeup_counter0_set(int ticks) */ unsigned long cal_r4koff(void) { - unsigned long count; unsigned long cpu_speed; unsigned long flags; unsigned long counter; @@ -258,7 +257,7 @@ unsigned long cal_r4koff(void) #if defined(CONFIG_AU1000_USE32K) { - unsigned long start, end; + unsigned long start, end, count; start = au_readl(SYS_RTCREAD); start += 2; @@ -282,7 +281,6 @@ unsigned long cal_r4koff(void) #else cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; - count = cpu_speed / 2; #endif } else { @@ -291,10 +289,9 @@ unsigned long cal_r4koff(void) * NOTE: some old silicon doesn't allow reading the PLL. */ cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; - count = cpu_speed / 2; no_au1xxx_32khz = 1; } - mips_hpt_frequency = count; + mips_hpt_frequency = cpu_speed; // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); spin_unlock_irqrestore(&time_lock, flags); --------------080102080909070809080704-- From nidajm@gmail.com Mon Sep 4 05:57:13 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Sep 2006 05:57:45 +0100 (BST) Received: from py-out-1112.google.com ([64.233.166.178]:36248 "EHLO py-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S20037572AbWIDE5N (ORCPT ); Mon, 4 Sep 2006 05:57:13 +0100 Received: by py-out-1112.google.com with SMTP id i49so1910184pyi for ; Sun, 03 Sep 2006 21:57:12 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=s4zDVTjuyoiXzs2gRMvkom/LJEzVGC1CqE3xS22wXLDrr/7/ELnqHhsKAjHjqxoTF0AlZAiIcTJp5HsHXR1uOBmOtHGvfPZEGamM7akM+ToTdExRPJi1FZhxTvExxVe9dZhit0lD+DYjU1l3LjL1zkeAjK42o2/ZiPKJSeGMNS8= Received: by 10.65.116.7 with SMTP id t7mr2613811qbm; Sun, 03 Sep 2006 21:57:12 -0700 (PDT) Received: by 10.65.126.5 with HTTP; Sun, 3 Sep 2006 21:57:12 -0700 (PDT) Message-ID: Date: Mon, 4 Sep 2006 10:27:12 +0530 From: "Nida M" To: "Kevin D. Kissell" Subject: Re: single step in MIPS Cc: linux-mips@linux-mips.org In-Reply-To: <000b01c6cea8$7d480fa0$a803a8c0@Ulysses> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <000b01c6cea8$7d480fa0$a803a8c0@Ulysses> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12509 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nidajm@gmail.com Precedence: bulk X-list: linux-mips On 9/2/06, Kevin D. Kissell wrote: > As Alan indicted, mechanisms for emulating single step > behavior have long existed for MIPS and Linux. Newer > MIPS parts which implement the EJTAG debug system > do have a single-step mode, but they trap to Debug mode, > rather than to the kernel - this allows kernel code to be > single-stepped using an EJTAG probe. If the system > allows for it - one needs to have ROM at the right location > which transfers Debug mode control back to the kernel - it > is possible to exploit EJTAG debug features from an OS > kernel. We''ve prototyped this to prove that it works, but > never went so far as to wire up EJTAG signle-step mode > to a ptrace or other debug API. If for some strange reason > the standard emulation mechanism isn't adequate for you > (e.g. if your applicaiton is executing out of ROM), you > do have this as a potential alternative. But it would not > be a trivial hack. Well this is ok ..but I am trying to implement kenel debugger.. something like system tap. And I have started with kprobe.. where the kernel code execution will be stopped at user specified address using break, how do i single step that instruction to decode the instruction and print the registers value..? ~Nida From domen.puncer@telargo.com Mon Sep 4 07:11:51 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Sep 2006 07:11:55 +0100 (BST) Received: from out001.atlarge.net ([129.41.63.69]:136 "EHLO out001.atlarge.net") by ftp.linux-mips.org with ESMTP id S20037641AbWIDGLv (ORCPT ); Mon, 4 Sep 2006 07:11:51 +0100 Received: from hpmailfe-01.atlarge.net ([10.100.60.156]) by out001.atlarge.net with Microsoft SMTPSVC(6.0.3790.1830); Mon, 4 Sep 2006 01:10:22 -0500 Received: from localhost ([213.250.36.225]) by hpmailfe-01.atlarge.net with Microsoft SMTPSVC(6.0.3790.1830); Mon, 4 Sep 2006 01:10:20 -0500 Date: Mon, 4 Sep 2006 08:11:41 +0200 From: Domen Puncer To: David Goodenough Cc: linux-mips@linux-mips.org Subject: Re: ADM5120 support Message-ID: <20060904061141.GB5361@domen.puncer.telargo.com> References: <200609011150.54312.david.goodenough@linkchoose.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200609011150.54312.david.goodenough@linkchoose.co.uk> User-Agent: Mutt/1.5.12-2006-07-14 X-OriginalArrivalTime: 04 Sep 2006 06:10:21.0671 (UTC) FILETIME=[CDADA770:01C6CFE8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12510 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen.puncer@telargo.com Precedence: bulk X-list: linux-mips On 01/09/06 11:50 +0100, David Goodenough wrote: > I have found some patches for the ADM5120 on the web for 2.6.12, but nothing > more recent. Anyone know of an updated patch (if updating is needed)? Hi! I forward ported them to 2.6.15, but then lost interest. http://coderock.org/planet_xrt-401d/files/ Domen > > David From sshtylyov@ru.mvista.com Mon Sep 4 18:26:49 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Sep 2006 18:26:53 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:36969 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20039235AbWIDR0t (ORCPT ); Mon, 4 Sep 2006 18:26:49 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 58F773EBE; Mon, 4 Sep 2006 10:26:43 -0700 (PDT) Message-ID: <44FC625A.5050005@ru.mvista.com> Date: Mon, 04 Sep 2006 21:28:58 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Russell King Cc: Pantelis Antoniou , Linux-MIPS Subject: Re: [PATCH] AMD Alchemy: claim UART memory range References: <4432BF48.8030403@ru.mvista.com> <44F2E9F7.6030309@ru.mvista.com> <20060830080157.GA17632@flint.arm.linux.org.uk> In-Reply-To: <20060830080157.GA17632@flint.arm.linux.org.uk> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12511 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Russell King wrote: >>> BTW, can anybody enlighten me why 8250_au1x00.c came into being >>>at all? >>>Its only function seems to register the UART platform devices, the >>>thing >>>that is usually done in the board setup code, i. e. I'd rather have >>>it in arch/mips/au1000/common/platform.c (however, 8250.c should >>>have been able to filter out ports with UPIO_AU in case >>>CONFIG_SERIAL_8250_AU1X00 undefined)... >>Seemed like a good idea at the moment to follow the already existing >>convention. > Already existing convention is as per Sergei's mail actually - to have the > platform device registration in arch/*. The others which you thought were > convention there (accent, boca, fourport, hub6, mca) are all for add-in > cards and aren't architecture specific. > Hence, they can't live in arch/*. > So yes, 8250_au1x00.c breaks the established convention because it isn't > an add-in card. Thanks for clarification. Now another question to Pantelis: IIUC, the Alchemy UART platform devices have UPF_SKIP_TEST set because of the Alchemy docs claiming that UARTs other than UART3 don't have MCR/MSR and only UART3 does have the full set of the modem control/status lines? Were they indeed failing the loopback test for you? Asking because on DBAu1550 board all (enabled) UARTs do pass the loopback test if I get rid of this flag (however, Au1550 datasheet says MCR/MSR exists on all UARTs, just no modem pins exist on UART0, and only RTS-/CTS- pair on UART1 -- and the bits having no correspoding pins seem to be tied high internally). If I'm correct, the driver seems inconsistent in how it handles UART_BUG_NOMSR flag, only checking it when deciding whether to enable the modem status interrupts or not while actually it should have been checked in serial8250_set_mctrl() and check_modem_status() as well... It also looks like the driver doesn't use Alchemy UARTs to their full potential currently: UART3 has not only full set of modem lines, but also is capable of the auto flow control (UART1 on Au1550 also is). (Making use of these features howewer are complicated by the auto flow control being only available in the late steppings of Au1500 and UART3 modem pins being multiplexed with GPIO...) WBR, Sergei PS: CCing linux-mips to keep people here informed. :-) From pantelis@embeddedalley.com Mon Sep 4 18:39:15 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Sep 2006 18:39:17 +0100 (BST) Received: from smtp104.biz.mail.re2.yahoo.com ([206.190.52.173]:2966 "HELO smtp104.biz.mail.re2.yahoo.com") by ftp.linux-mips.org with SMTP id S20039235AbWIDRjP convert rfc822-to-8bit (ORCPT ); Mon, 4 Sep 2006 18:39:15 +0100 Received: (qmail 24362 invoked from network); 4 Sep 2006 17:39:05 -0000 Received: from unknown (HELO ?192.168.1.19?) (pantelis@embeddedalley.com@62.1.231.13 with plain) by smtp104.biz.mail.re2.yahoo.com with SMTP; 4 Sep 2006 17:39:04 -0000 In-Reply-To: <44FC625A.5050005@ru.mvista.com> References: <4432BF48.8030403@ru.mvista.com> <44F2E9F7.6030309@ru.mvista.com> <20060830080157.GA17632@flint.arm.linux.org.uk> <44FC625A.5050005@ru.mvista.com> Mime-Version: 1.0 (Apple Message framework v752.2) Content-Type: text/plain; charset=UTF-8; delsp=yes; format=flowed Message-Id: <4098748B-6105-4644-A86A-B776A23D0272@embeddedalley.com> Cc: Russell King , Linux-MIPS Content-Transfer-Encoding: 8BIT From: Pantelis Antoniou Subject: Re: [PATCH] AMD Alchemy: claim UART memory range Date: Mon, 4 Sep 2006 20:38:55 +0300 To: Sergei Shtylyov X-Mailer: Apple Mail (2.752.2) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12512 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pantelis@embeddedalley.com Precedence: bulk X-list: linux-mips On 04 Σεπ 2006, at 8:28 ΜΜ, Sergei Shtylyov wrote: > Hello. > > Russell King wrote: > >>>> BTW, can anybody enlighten me why 8250_au1x00.c came into >>>> being at all? >>>> Its only function seems to register the UART platform devices, >>>> the thing >>>> that is usually done in the board setup code, i. e. I'd rather >>>> have it in arch/mips/au1000/common/platform.c (however, 8250.c >>>> should have been able to filter out ports with UPIO_AU in case >>>> CONFIG_SERIAL_8250_AU1X00 undefined)... > >>> Seemed like a good idea at the moment to follow the already >>> existing convention. > >> Already existing convention is as per Sergei's mail actually - to >> have the >> platform device registration in arch/*. The others which you >> thought were >> convention there (accent, boca, fourport, hub6, mca) are all for >> add-in >> cards and aren't architecture specific. > >> Hence, they can't live in arch/*. > >> So yes, 8250_au1x00.c breaks the established convention because it >> isn't >> an add-in card. > > Thanks for clarification. > > Now another question to Pantelis: IIUC, the Alchemy UART > platform devices have UPF_SKIP_TEST set because of the Alchemy docs > claiming that UARTs other than UART3 don't have MCR/MSR and only > UART3 does have the full set of the modem control/status lines? > Were they indeed failing the loopback test for you? Asking because > on DBAu1550 board all (enabled) UARTs do pass the loopback test if > I get rid of this flag (however, Au1550 datasheet says MCR/MSR > exists on all UARTs, just no modem pins exist on UART0, and only > RTS-/CTS- pair on UART1 -- and the bits having no correspoding pins > seem to be tied high internally). > If I'm correct, the driver seems inconsistent in how it handles > UART_BUG_NOMSR flag, only checking it when deciding whether to > enable the modem status interrupts or not while actually it should > have been checked in serial8250_set_mctrl() and check_modem_status > () as well... > It also looks like the driver doesn't use Alchemy UARTs to their > full potential currently: UART3 has not only full set of modem > lines, but also is capable of the auto flow control (UART1 on > Au1550 also is). (Making use of these features howewer are > complicated by the auto flow control being only available in the > late steppings of Au1500 and UART3 modem pins being multiplexed > with GPIO...) > > WBR, Sergei > > PS: CCing linux-mips to keep people here informed. :-) Hi Sergei, Yes, 1550 has proper UARTs on all port, but not 1200 ;) Somehow I thought that hacking 8250 to support two different Au's (1550 & 1200) wouldn't go down well; so I chickened out & settled for a subset that would work on both. Feel free to fight your way through to support all the functionality you require. Pantelis From sshtylyov@ru.mvista.com Mon Sep 4 19:20:23 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Sep 2006 19:20:26 +0100 (BST) Received: from p549F5EA7.dip.t-dialin.net ([84.159.94.167]:49050 "EHLO p549F5EA7.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S20039253AbWIDSUX (ORCPT ); Mon, 4 Sep 2006 19:20:23 +0100 Received: from h155.mvista.com ([63.81.120.155]:10090 "EHLO imap.sh.mvista.com") by lappi.linux-mips.net with ESMTP id S1100038AbWIDSNt (ORCPT ); Mon, 4 Sep 2006 20:13:49 +0200 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id A21813EBE; Mon, 4 Sep 2006 11:13:01 -0700 (PDT) Message-ID: <44FC6D38.1000407@ru.mvista.com> Date: Mon, 04 Sep 2006 22:15:20 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Pantelis Antoniou Cc: Russell King , Linux-MIPS Subject: Re: [PATCH] AMD Alchemy: claim UART memory range References: <4432BF48.8030403@ru.mvista.com> <44F2E9F7.6030309@ru.mvista.com> <20060830080157.GA17632@flint.arm.linux.org.uk> <44FC625A.5050005@ru.mvista.com> <4098748B-6105-4644-A86A-B776A23D0272@embeddedalley.com> In-Reply-To: <4098748B-6105-4644-A86A-B776A23D0272@embeddedalley.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12513 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Pantelis Antoniou wrote: >>>>> BTW, can anybody enlighten me why 8250_au1x00.c came into being >>>>> at all? >>>>> Its only function seems to register the UART platform devices, >>>>> the thing >>>>> that is usually done in the board setup code, i. e. I'd rather >>>>> have it in arch/mips/au1000/common/platform.c (however, 8250.c >>>>> should have been able to filter out ports with UPIO_AU in case >>>>> CONFIG_SERIAL_8250_AU1X00 undefined)... >>>> Seemed like a good idea at the moment to follow the already >>>> existing convention. >>> Already existing convention is as per Sergei's mail actually - to >>> have the >>> platform device registration in arch/*. The others which you >>> thought were >>> convention there (accent, boca, fourport, hub6, mca) are all for add-in >>> cards and aren't architecture specific. >>> Hence, they can't live in arch/*. >>> So yes, 8250_au1x00.c breaks the established convention because it >>> isn't >>> an add-in card. >> Thanks for clarification. >> Now another question to Pantelis: IIUC, the Alchemy UART platform >> devices have UPF_SKIP_TEST set because of the Alchemy docs claiming >> that UARTs other than UART3 don't have MCR/MSR and only UART3 does >> have the full set of the modem control/status lines? Were they >> indeed failing the loopback test for you? Asking because on DBAu1550 >> board all (enabled) UARTs do pass the loopback test if I get rid of >> this flag (however, Au1550 datasheet says MCR/MSR exists on all >> UARTs, just no modem pins exist on UART0, and only RTS-/CTS- pair on >> UART1 -- and the bits having no correspoding pins seem to be tied >> high internally). >> If I'm correct, the driver seems inconsistent in how it handles >> UART_BUG_NOMSR flag, only checking it when deciding whether to enable >> the modem status interrupts or not while actually it should have been >> checked in serial8250_set_mctrl() and check_modem_status () as well... >> It also looks like the driver doesn't use Alchemy UARTs to their >> full potential currently: UART3 has not only full set of modem lines, >> but also is capable of the auto flow control (UART1 on Au1550 also >> is). (Making use of these features howewer are complicated by the >> auto flow control being only available in the late steppings of >> Au1500 and UART3 modem pins being multiplexed with GPIO...) >> PS: CCing linux-mips to keep people here informed. :-) > Yes, 1550 has proper UARTs on all port, but not 1200 ;) No, it doesn't have "proper" UARTs on all ports (like all the other Alchemies), it's just said it has MCR/MSR on UART0/1 as well as on UART3. Actually, Au1200 also does, according to its datasheet. > Somehow I thought that hacking 8250 to support two different Au's (1550 > & 1200) > wouldn't go down well; so I chickened out & settled for a subset that > would work on > both. Feel free to fight your way through to support all the > functionality you > require. Well, now I certainly have no time for enabling any features, even for fixing buglets. So, if anybody of the linux-mips readers cares enough, it's their call... :-) At least UART_BUG_NOMSR handling should be extended if MCR/MSR are indeed missing on some SOCs. And since 0 in the bit 7 (U3) bit of sys_pinfunc determines if UART3 modem control/status are used for GPIO, this is also worth checking somewhere (if one wants to support the full set of the modem lines)... > Pantelis WBR, Sergei From erik.niessen@gmail.com Tue Sep 5 07:55:51 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Sep 2006 07:55:58 +0100 (BST) Received: from wx-out-0506.google.com ([66.249.82.238]:17061 "EHLO wx-out-0506.google.com") by ftp.linux-mips.org with ESMTP id S20038727AbWIEGzv (ORCPT ); Tue, 5 Sep 2006 07:55:51 +0100 Received: by wx-out-0506.google.com with SMTP id h30so2540377wxd for ; Mon, 04 Sep 2006 23:55:49 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type; b=qIaGYaGjsH6ZJV8QbZt80md7yE8lUjJMAE1g7W+0eo7TqMD0CCbZnr/fLNbLfb5nQs6eU5jItxrPX40qapFnD34oIHrbfOv7ZTXlWx34O121YVfYVsufTYPyUqWHvxMmkXDoI4O3Q1HJZa8x6HzCIrEox48Y+HhCDwmES8s6u/w= Received: by 10.70.118.4 with SMTP id q4mr7061962wxc; Mon, 04 Sep 2006 23:55:18 -0700 (PDT) Received: by 10.70.25.11 with HTTP; Mon, 4 Sep 2006 23:55:18 -0700 (PDT) Message-ID: Date: Tue, 5 Sep 2006 08:55:18 +0200 From: "Erik Niessen" To: linux-mips@linux-mips.org Subject: Weird output from pmap MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_123085_32158524.1157439318223" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12514 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: erik.niessen@gmail.com Precedence: bulk X-list: linux-mips ------=_Part_123085_32158524.1157439318223 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi, I am using an embedded development board with a mips 4kEC on it. I use buildroot for building a rootfs and the toolchain. I cross compiled a helloword app. When I look at the output of pmap I see the following /helloworldmips(86) 00400000 (4 KB) r-xp (00:0a 33243002) linux/test/helloworldmips 10000000 (4 KB) rw-p (00:0a 33243002) linux/test/helloworldmips 10001000 (4 KB) rwxp (00:00 0) [heap] 2aaa8000 (20 KB) r-xp (00:07 1795853) /lib/ld-uClibc-0.9.27.so 2aaad000 (4 KB) rw-p (00:00 0) 2aaed000 (4 KB) rw-p (00:07 1795853) /lib/ld- uClibc-0.9.27.so 2aaee000 (48 KB) r-xp (00:07 1795861) /lib/libgcc_s.so.1 2aafa000 (252 KB) ---p (00:00 0) 2ab39000 (4 KB) rw-p (00:07 1795861) /lib/libgcc_s.so.1 2ab3a000 (368 KB) r-xp (00:07 1795855) /lib/libuClibc-0.9.27.so 2ab96000 (256 KB) ---p (00:00 0) 2abd6000 (8 KB) rw-p (00:07 1795855) /lib/libuClibc- 0.9.27.so 2abd8000 (16 KB) rw-p (00:00 0) 7fd49000 (84 KB) rwxp (00:00 0) [stack] mapped: 1076 KB writable/private: 128 KB shared: 0 KB It seems that the bss segments of the shared libs are protected and mapped to the zero page. I don't see this when I run this on a linux pc. I have the following questions: - Why is this segment protected? Accessing results in a seg fault. - Why is it so big (252k/256K)? - How much memory is physically allocated for this segment? Thanks for reading sofar Erik Niessen ------=_Part_123085_32158524.1157439318223 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi,

I am using an embedded development board with a mips 4kEC on it. I use buildroot for building a
rootfs and the toolchain.

I cross compiled a helloword app.
When I look at the output of pmap I see the following

/helloworldmips(86)
00400000 (4 KB)        r-xp (00:0a 33243002)   linux/test/helloworldmips
10000000 (4 KB)        rw-p (00:0a 33243002)   linux/test/helloworldmips
10001000 (4 KB)        rwxp (00:00 0)        [heap]
2aaa8000 (20 KB)       r-xp (00:07 1795853)  /lib/ld-uClibc-0.9.27.so
2aaad000 (4 KB)        rw-p (00:00 0)       
2aaed000 (4 KB)        rw-p (00:07 1795853)  /lib/ld- uClibc-0.9.27.so
2aaee000 (48 KB)       r-xp (00:07 1795861)  /lib/libgcc_s.so.1
2aafa000 (252 KB)      ---p (00:00 0)       
2ab39000 (4 KB)        rw-p (00:07 1795861)  /lib/libgcc_s.so.1
2ab3a000 (368 KB)      r-xp (00:07 1795855)  /lib/libuClibc-0.9.27.so
2ab96000 (256 KB)      ---p (00:00 0)       
2abd6000 (8 KB)        rw-p (00:07 1795855)  /lib/libuClibc- 0.9.27.so
2abd8000 (16 KB)       rw-p (00:00 0)       
7fd49000 (84 KB)       rwxp (00:00 0)        [stack]
mapped:   1076 KB writable/private: 128 KB shared: 0 KB

It seems that the bss segments of the shared libs are protected and mapped to the zero page. I don't see this
when I run this on a linux pc. I have the following questions:
- Why is this segment protected? Accessing results in a seg fault.
- Why is it so big (252k/256K)?
- How much memory is physically allocated for this segment?

Thanks for reading sofar

Erik Niessen
------=_Part_123085_32158524.1157439318223-- From mangoo@wpkg.org Tue Sep 5 13:26:31 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Sep 2006 13:26:34 +0100 (BST) Received: from mail.syneticon.net ([213.239.212.131]:15827 "EHLO mail2.syneticon.net") by ftp.linux-mips.org with ESMTP id S20027677AbWIEM0b (ORCPT ); Tue, 5 Sep 2006 13:26:31 +0100 Received: from localhost (localhost [127.0.0.1]) by mail2.syneticon.net (Postfix) with ESMTP id 77F5B4DCB6 for ; Tue, 5 Sep 2006 14:26:25 +0200 (CEST) Received: from mail2.syneticon.net ([127.0.0.1]) by localhost (linux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 06893-02 for ; Tue, 5 Sep 2006 14:26:18 +0200 (CEST) Received: from [192.168.10.145] (xdsl-81-173-239-45.netcologne.de [81.173.239.45]) by mail2.syneticon.net (Postfix) with ESMTP for ; Tue, 5 Sep 2006 14:26:18 +0200 (CEST) Message-ID: <44FD6CE4.6010001@wpkg.org> Date: Tue, 05 Sep 2006 14:26:12 +0200 From: Tomasz Chmielewski User-Agent: Thunderbird 1.5.0.5 (X11/20060814) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: no USB device other than storage detected Content-Type: text/plain; charset=ISO-8859-2; format=flowed Content-Transfer-Encoding: 7bit X-Virus-Scanned: amavisd-new at syneticon.de Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12515 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mangoo@wpkg.org Precedence: bulk X-list: linux-mips I have a tiny router (ASUS WL-500g deluxe, MIPS CPU, 32 MB RAM, 2x USB2), and would like to make it work with a USB DSL modem. Right now, it's running Debian and kernel 2.6.17, and boots off a USB-stick. My problem is, that it only sees USB storage devices (USB sticks etc.). When I connect other devices (USB modem, webcam, microphone, keyboard, printer etc.), they are not detected. By "not detected" I mean there are no "dmesg" entries with the device name, and no devices, other than "USB storage", listed with "lsusb". I even compiled "USB verbose logging" in, but it only gives me a couple of debug infos, no clue why the devices doesn't show up. This is an example when I plug the USB printer in (USB verbose logging): hub 1-0:1.0: state 7 ports 4 chg 0000 evt 0004 ehci_hcd 0000:01:02.2: GetStatus port 2 status 001803 POWER sig=j CSC CONNECT hub 1-0:1.0: port 2, status 0501, change 0001, 480 Mb/s hub 1-0:1.0: debounce: port 2: total 100ms stable 100ms status 0x501 ehci_hcd 0000:01:02.2: port 2 full speed --> companion ehci_hcd 0000:01:02.2: GetStatus port 2 status 003801 POWER OWNER sig=j CONNECT No new device appeared in /proc/bus/usb/devices. Of course, I have the appropriate device modules built (pwc for Philips webcam, usblp for a printer etc.), but inserting them doesn't change anything. Why it only detects USB storage devices, and no other devices? Did I forget to check some kernel option? For reference, I attach my .config file. Tomasz Chmielewski http://wpkg.org # # Automatically generated make config: don't edit # Linux kernel version: 2.6.17 # Mon Sep 4 21:32:01 2006 # CONFIG_MIPS=y # # Machine selection # # CONFIG_MIPS_MTX1 is not set # CONFIG_MIPS_BOSPORUS is not set # CONFIG_MIPS_PB1000 is not set # CONFIG_MIPS_PB1100 is not set # CONFIG_MIPS_PB1500 is not set # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_PB1200 is not set # CONFIG_MIPS_DB1000 is not set # CONFIG_MIPS_DB1100 is not set # CONFIG_MIPS_DB1500 is not set # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set # CONFIG_MIPS_ITE8172 is not set # CONFIG_MACH_JAZZ is not set CONFIG_BCM947XX=y # CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_MOMENCO_OCELOT_3 is not set # CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set # CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPSR1=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y # # Kernel type # CONFIG_32BIT=y # CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y # CONFIG_MIPS_MT is not set # CONFIG_64BIT_PHYS_ADDR is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # # Code maturity level options # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set # CONFIG_RELAY is not set CONFIG_INITRAMFS_SOURCE="" CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_EMBEDDED=y # CONFIG_KALLSYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y CONFIG_SHMEM=y CONFIG_SLAB=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 # CONFIG_SLOB is not set CONFIG_OBSOLETE_INTERMODULE=y # # Loadable module support # CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_KMOD is not set # # Block layer # # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y # CONFIG_IOSCHED_AS is not set CONFIG_IOSCHED_DEADLINE=y # CONFIG_IOSCHED_CFQ is not set # CONFIG_DEFAULT_AS is not set CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_MMU=y # # PCCARD (PCMCIA/CardBus) support # CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m # CONFIG_PCMCIA_LOAD_CIS is not set # CONFIG_PCMCIA_IOCTL is not set CONFIG_CARDBUS=y # # PC-card bridges # CONFIG_YENTA=m # CONFIG_YENTA_O2 is not set # CONFIG_YENTA_RICOH is not set # CONFIG_YENTA_TI is not set # CONFIG_YENTA_TOSHIBA is not set # CONFIG_PD6729 is not set # CONFIG_I82092 is not set CONFIG_PCCARD_NONSTATIC=m # # PCI Hotplug Support # # CONFIG_HOTPLUG_PCI is not set # # Executable file formats # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y # # Networking # CONFIG_NET=y # # Networking options # # CONFIG_NETDEBUG is not set CONFIG_PACKET=y CONFIG_PACKET_MMAP=y CONFIG_UNIX=y # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_ASK_IP_FIB_HASH=y # CONFIG_IP_FIB_TRIE is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_FWMARK=y CONFIG_IP_ROUTE_MULTIPATH=y # CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set # CONFIG_IP_ROUTE_VERBOSE is not set # CONFIG_IP_PNP is not set CONFIG_NET_IPIP=m # CONFIG_NET_IPGRE is not set # CONFIG_IPSEC_NAT_TRAVERSAL is not set # CONFIG_IP_MROUTE is not set # CONFIG_ARPD is not set # CONFIG_SYN_COOKIES is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set CONFIG_INET_TUNNEL=m CONFIG_INET_DIAG=m CONFIG_INET_TCP_DIAG=m CONFIG_TCP_CONG_ADVANCED=y # # TCP congestion control # CONFIG_TCP_CONG_BIC=m CONFIG_TCP_CONG_CUBIC=m CONFIG_TCP_CONG_WESTWOOD=m CONFIG_TCP_CONG_HTCP=m CONFIG_TCP_CONG_HSTCP=m CONFIG_TCP_CONG_HYBLA=m CONFIG_TCP_CONG_VEGAS=y CONFIG_TCP_CONG_SCALABLE=m # # IP: Virtual Server Configuration # # CONFIG_IP_VS is not set # CONFIG_IPV6 is not set # CONFIG_INET6_XFRM_TUNNEL is not set # CONFIG_INET6_TUNNEL is not set CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set # CONFIG_BRIDGE_NETFILTER is not set # # Core Netfilter Configuration # # CONFIG_NETFILTER_NETLINK is not set CONFIG_NETFILTER_XTABLES=y CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_MARK=m # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set # CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y # CONFIG_NETFILTER_XT_MATCH_DCCP is not set CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set # CONFIG_NETFILTER_XT_MATCH_REALM is not set # CONFIG_NETFILTER_XT_MATCH_SCTP is not set CONFIG_NETFILTER_XT_MATCH_STATE=y CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=y # # IP: Netfilter Configuration # CONFIG_IP_NF_CONNTRACK=y CONFIG_IP_NF_CT_ACCT=y CONFIG_IP_NF_CONNTRACK_MARK=y # CONFIG_IP_NF_CONNTRACK_EVENTS is not set # CONFIG_IP_NF_CT_PROTO_SCTP is not set CONFIG_IP_NF_FTP=y CONFIG_IP_NF_IRC=y # CONFIG_IP_NF_NETBIOS_NS is not set CONFIG_IP_NF_TFTP=m CONFIG_IP_NF_AMANDA=m CONFIG_IP_NF_PPTP=m CONFIG_IP_NF_H323=m CONFIG_IP_NF_SIP=m CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=y CONFIG_IP_NF_MATCH_IPRANGE=m CONFIG_IP_NF_MATCH_IPP2P=m CONFIG_IP_NF_MATCH_TOS=m CONFIG_IP_NF_MATCH_TIME=m CONFIG_IP_NF_MATCH_RECENT=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_DSCP=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_MATCH_OWNER=m # CONFIG_IP_NF_MATCH_ADDRTYPE is not set # CONFIG_IP_NF_MATCH_HASHLIMIT is not set CONFIG_IP_NF_MATCH_LAYER7=m # CONFIG_IP_NF_MATCH_LAYER7_DEBUG is not set CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y CONFIG_IP_NF_TARGET_IMQ=m # CONFIG_IP_NF_TARGET_LOG is not set CONFIG_IP_NF_TARGET_ULOG=m CONFIG_IP_NF_TARGET_TCPMSS=y CONFIG_IP_NF_NAT=y CONFIG_IP_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=y CONFIG_IP_NF_TARGET_REDIRECT=y # CONFIG_IP_NF_TARGET_ROUTE is not set # CONFIG_IP_NF_TARGET_NETMAP is not set # CONFIG_IP_NF_TARGET_SAME is not set # CONFIG_IP_NF_NAT_SNMP_BASIC is not set CONFIG_IP_NF_NAT_IRC=y CONFIG_IP_NF_NAT_FTP=y CONFIG_IP_NF_NAT_TFTP=m CONFIG_IP_NF_NAT_AMANDA=m CONFIG_IP_NF_NAT_PPTP=m CONFIG_IP_NF_NAT_H323=m CONFIG_IP_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=y CONFIG_IP_NF_TARGET_TOS=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_DSCP=m CONFIG_IP_NF_TARGET_TTL=m # CONFIG_IP_NF_TARGET_CLUSTERIP is not set CONFIG_IP_NF_RAW=m # CONFIG_IP_NF_ARPTABLES is not set CONFIG_IP_NF_SET=m CONFIG_IP_NF_SET_MAX=256 CONFIG_IP_NF_SET_HASHSIZE=1024 CONFIG_IP_NF_SET_IPMAP=m CONFIG_IP_NF_SET_MACIPMAP=m CONFIG_IP_NF_SET_PORTMAP=m CONFIG_IP_NF_SET_IPHASH=m CONFIG_IP_NF_SET_NETHASH=m CONFIG_IP_NF_SET_IPTREE=m CONFIG_IP_NF_MATCH_SET=m CONFIG_IP_NF_TARGET_SET=m # # Bridge: Netfilter Configuration # CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m CONFIG_BRIDGE_EBT_IP=m CONFIG_BRIDGE_EBT_LIMIT=m CONFIG_BRIDGE_EBT_MARK=m CONFIG_BRIDGE_EBT_PKTTYPE=m CONFIG_BRIDGE_EBT_STP=m CONFIG_BRIDGE_EBT_VLAN=m CONFIG_BRIDGE_EBT_ARPREPLY=m CONFIG_BRIDGE_EBT_DNAT=m CONFIG_BRIDGE_EBT_MARK_T=m CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m # # DCCP Configuration (EXPERIMENTAL) # # CONFIG_IP_DCCP is not set # # SCTP Configuration (EXPERIMENTAL) # # CONFIG_IP_SCTP is not set # # TIPC Configuration (EXPERIMENTAL) # # CONFIG_TIPC is not set CONFIG_ATM=m CONFIG_ATM_CLIP=m # CONFIG_ATM_CLIP_NO_ICMP is not set # CONFIG_ATM_LANE is not set CONFIG_ATM_BR2684=m # CONFIG_ATM_BR2684_IPFILTER is not set CONFIG_BRIDGE=y CONFIG_VLAN_8021Q=y # CONFIG_DECNET is not set CONFIG_LLC=y # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # # QoS and/or fair queueing # CONFIG_NET_SCHED=y CONFIG_NET_SCH_CLK_JIFFIES=y # CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set # CONFIG_NET_SCH_CLK_CPU is not set # # Queueing/Scheduling # CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m # CONFIG_NET_SCH_ATM is not set CONFIG_NET_SCH_PRIO=m CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_ESFQ=m CONFIG_NET_SCH_TEQL=m CONFIG_NET_SCH_TBF=m CONFIG_NET_SCH_GRED=m CONFIG_NET_SCH_DSMARK=m # CONFIG_NET_SCH_NETEM is not set CONFIG_NET_SCH_INGRESS=m # # Classification # CONFIG_NET_CLS=y CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_ROUTE=y CONFIG_NET_CLS_FW=m CONFIG_NET_CLS_U32=m # CONFIG_CLS_U32_PERF is not set # CONFIG_CLS_U32_MARK is not set CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m # CONFIG_NET_EMATCH is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_CLS_POLICE=y # CONFIG_NET_CLS_IND is not set CONFIG_NET_ESTIMATOR=y # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set CONFIG_IEEE80211=m # CONFIG_IEEE80211_DEBUG is not set CONFIG_IEEE80211_CRYPT_WEP=m # CONFIG_IEEE80211_CRYPT_CCMP is not set # CONFIG_IEEE80211_CRYPT_TKIP is not set CONFIG_IEEE80211_SOFTMAC=m CONFIG_IEEE80211_SOFTMAC_DEBUG=y CONFIG_WIRELESS_EXT=y # # Device Drivers # # # Generic Driver Options # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y # # Connector - unified userspace <-> kernelspace linker # # CONFIG_CONNECTOR is not set # # Memory Technology Devices (MTD) # CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set # # User Modules And Translation Layers # CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=y # CONFIG_MTD_JEDECPROBE is not set CONFIG_MTD_GEN_PROBE=y # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y # CONFIG_MTD_CFI_STAA is not set CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set # CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access # CONFIG_MTD_COMPLEX_MAPPINGS=y # CONFIG_MTD_PHYSMAP is not set CONFIG_MTD_BCM47XX=y # CONFIG_MTD_PCI is not set # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # # CONFIG_MTD_PMC551 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set # CONFIG_MTD_BLOCK2MTD is not set # # Disk-On-Chip Device Drivers # # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set # # NAND Flash Device Drivers # # CONFIG_MTD_NAND is not set # # OneNAND Flash Device Drivers # # CONFIG_MTD_ONENAND is not set # # Parallel port support # # CONFIG_PARPORT is not set # # Plug and Play support # # # Block devices # # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_INITRD=y # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # # ATA/ATAPI/MFM/RLL support # # CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # # SCSI Transport Attributes # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_ATTRS is not set # # SCSI low-level drivers # # CONFIG_ISCSI_TCP is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC7XXX_OLD is not set # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_SAS is not set # CONFIG_SCSI_SATA is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set # CONFIG_SCSI_QLOGIC_1280 is not set # CONFIG_SCSI_QLA_FC is not set # CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # # PCMCIA SCSI adapter support # # CONFIG_PCMCIA_AHA152X is not set # CONFIG_PCMCIA_FDOMAIN is not set # CONFIG_PCMCIA_NINJA_SCSI is not set # CONFIG_PCMCIA_QLOGIC is not set # CONFIG_PCMCIA_SYM53C500 is not set # # Multi-device support (RAID and LVM) # # CONFIG_MD is not set # # Fusion MPT device support # # CONFIG_FUSION is not set # CONFIG_FUSION_SPI is not set # CONFIG_FUSION_FC is not set # CONFIG_FUSION_SAS is not set # # IEEE 1394 (FireWire) support # # CONFIG_IEEE1394 is not set # # I2O device support # # CONFIG_I2O is not set # # Network device support # CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set CONFIG_IMQ=m # CONFIG_IMQ_BEHAVIOR_AA is not set # CONFIG_IMQ_BEHAVIOR_AB is not set CONFIG_IMQ_BEHAVIOR_BA=y # CONFIG_IMQ_BEHAVIOR_BB is not set CONFIG_IMQ_NUM_DEVS=2 CONFIG_TUN=m # # ARCnet devices # # CONFIG_ARCNET is not set # # PHY device support # # CONFIG_PHYLIB is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_DM9000 is not set # # Tulip family network device support # # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set # CONFIG_ADAPTEC_STARFIRE is not set CONFIG_B44=y # CONFIG_FORCEDETH is not set # CONFIG_DGRS is not set # CONFIG_EEPRO100 is not set # CONFIG_E100 is not set # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set # CONFIG_NE2K_PCI is not set # CONFIG_8139CP is not set # CONFIG_8139TOO is not set # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_LAN_SAA9730 is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set # # Ethernet (10000 Mbit) # # CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # # Token Ring devices # # CONFIG_TR is not set # # Wireless LAN (non-hamradio) # CONFIG_NET_RADIO=y # CONFIG_NET_WIRELESS_RTNETLINK is not set # # Obsolete Wireless cards support (pre-802.11) # # CONFIG_STRIP is not set # CONFIG_PCMCIA_WAVELAN is not set # CONFIG_PCMCIA_NETWAVE is not set # # Wireless 802.11 Frequency Hopping cards support # # CONFIG_PCMCIA_RAYCS is not set # # Wireless 802.11b ISA/PCI cards support # # CONFIG_IPW2100 is not set # CONFIG_IPW2200 is not set # CONFIG_HERMES is not set # CONFIG_ATMEL is not set # # Wireless 802.11b Pcmcia/Cardbus cards support # # CONFIG_AIRO_CS is not set # CONFIG_PCMCIA_WL3501 is not set # # Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support # # CONFIG_PRISM54 is not set # CONFIG_HOSTAP is not set CONFIG_BCM43XX=m CONFIG_BCM43XX_DEBUG=y CONFIG_BCM43XX_DMA=y CONFIG_BCM43XX_PIO=y CONFIG_BCM43XX_DMA_AND_PIO_MODE=y # CONFIG_BCM43XX_DMA_MODE is not set # CONFIG_BCM43XX_PIO_MODE is not set CONFIG_NET_WIRELESS=y # # PCMCIA network device support # # CONFIG_NET_PCMCIA is not set # # Wan interfaces # # CONFIG_WAN is not set # # ATM drivers # # CONFIG_ATM_DUMMY is not set # CONFIG_ATM_TCP is not set # CONFIG_ATM_LANAI is not set # CONFIG_ATM_ENI is not set # CONFIG_ATM_FIRESTREAM is not set # CONFIG_ATM_ZATM is not set # CONFIG_ATM_NICSTAR is not set # CONFIG_ATM_IDT77252 is not set # CONFIG_ATM_AMBASSADOR is not set # CONFIG_ATM_HORIZON is not set # CONFIG_ATM_IA is not set # CONFIG_ATM_FORE200E_MAYBE is not set # CONFIG_ATM_HE is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set CONFIG_PPP=y # CONFIG_PPP_MULTILINK is not set # CONFIG_PPP_FILTER is not set CONFIG_PPP_ASYNC=y # CONFIG_PPP_SYNC_TTY is not set CONFIG_PPP_DEFLATE=y CONFIG_PPP_BSDCOMP=y CONFIG_PPP_MPPE=y CONFIG_PPPOE=y CONFIG_PPPOATM=m # CONFIG_SLIP is not set # CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem # # CONFIG_ISDN is not set # # Telephony Support # # CONFIG_PHONE is not set # # Input device support # CONFIG_INPUT=y # # Userland interfaces # # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set # # Hardware I/O ports # # CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set # # Character devices # # CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set # # Serial drivers # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_SERIAL_8250_PCI is not set CONFIG_SERIAL_8250_CS=m CONFIG_SERIAL_8250_NR_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 # CONFIG_SERIAL_8250_EXTENDED is not set # # Non-8250 serial port support # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # # IPMI # # CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set # CONFIG_RTC is not set # CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # # Ftape, the floppy tape device driver # # CONFIG_DRM is not set # # PCMCIA character devices # # CONFIG_SYNCLINK_CS is not set # CONFIG_CARDMAN_4000 is not set # CONFIG_CARDMAN_4040 is not set # CONFIG_RAW_DRIVER is not set # # TPM devices # # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set # # I2C support # # CONFIG_I2C is not set # # SPI support # # CONFIG_SPI is not set # CONFIG_SPI_MASTER is not set # # Dallas's 1-wire bus # # CONFIG_W1 is not set # # Hardware Monitoring support # # CONFIG_HWMON is not set # CONFIG_HWMON_VID is not set # # Misc devices # # # Multimedia devices # CONFIG_VIDEO_DEV=m CONFIG_VIDEO_V4L1=y CONFIG_VIDEO_V4L1_COMPAT=y CONFIG_VIDEO_V4L2=y # # Video Capture Adapters # # # Video Capture Adapters # # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_VIVI is not set # CONFIG_VIDEO_CPIA is not set # CONFIG_VIDEO_CPIA2 is not set # CONFIG_VIDEO_STRADIS is not set # CONFIG_VIDEO_MXB is not set # CONFIG_VIDEO_DPC is not set # CONFIG_VIDEO_HEXIUM_ORION is not set # CONFIG_VIDEO_HEXIUM_GEMINI is not set # # Encoders and Decoders # # # V4L USB devices # # CONFIG_USB_DSBR is not set # CONFIG_USB_VICAM is not set # CONFIG_USB_IBMCAM is not set # CONFIG_USB_KONICAWC is not set # CONFIG_USB_ET61X251 is not set # CONFIG_USB_OV511 is not set # CONFIG_USB_SE401 is not set # CONFIG_USB_SN9C102 is not set # CONFIG_USB_STV680 is not set # CONFIG_USB_ZC0301 is not set CONFIG_USB_PWC=m # # Radio Adapters # # CONFIG_RADIO_GEMTEK_PCI is not set # CONFIG_RADIO_MAXIRADIO is not set # CONFIG_RADIO_MAESTRO is not set # # Digital Video Broadcasting Devices # # CONFIG_DVB is not set # CONFIG_USB_DABUSB is not set # # Graphics support # # CONFIG_FB is not set # # Sound # CONFIG_SOUND=m # # Advanced Linux Sound Architecture # CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m CONFIG_SND_HWDEP=m CONFIG_SND_RAWMIDI=m # CONFIG_SND_SEQUENCER is not set # CONFIG_SND_MIXER_OSS is not set # CONFIG_SND_PCM_OSS is not set # CONFIG_SND_DYNAMIC_MINORS is not set # CONFIG_SND_SUPPORT_OLD_API is not set CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set # # Generic devices # # CONFIG_SND_DUMMY is not set # CONFIG_SND_MTPAV is not set # CONFIG_SND_SERIAL_U16550 is not set # CONFIG_SND_MPU401 is not set # # PCI devices # # CONFIG_SND_AD1889 is not set # CONFIG_SND_ALS300 is not set # CONFIG_SND_ALI5451 is not set # CONFIG_SND_ATIIXP is not set # CONFIG_SND_ATIIXP_MODEM is not set # CONFIG_SND_AU8810 is not set # CONFIG_SND_AU8820 is not set # CONFIG_SND_AU8830 is not set # CONFIG_SND_AZT3328 is not set # CONFIG_SND_BT87X is not set # CONFIG_SND_CA0106 is not set # CONFIG_SND_CMIPCI is not set # CONFIG_SND_CS4281 is not set # CONFIG_SND_CS46XX is not set # CONFIG_SND_EMU10K1 is not set # CONFIG_SND_EMU10K1X is not set # CONFIG_SND_ENS1370 is not set # CONFIG_SND_ENS1371 is not set # CONFIG_SND_ES1938 is not set # CONFIG_SND_ES1968 is not set # CONFIG_SND_FM801 is not set # CONFIG_SND_HDA_INTEL is not set # CONFIG_SND_HDSP is not set # CONFIG_SND_HDSPM is not set # CONFIG_SND_ICE1712 is not set # CONFIG_SND_ICE1724 is not set # CONFIG_SND_INTEL8X0 is not set # CONFIG_SND_INTEL8X0M is not set # CONFIG_SND_KORG1212 is not set # CONFIG_SND_MAESTRO3 is not set # CONFIG_SND_MIXART is not set # CONFIG_SND_NM256 is not set # CONFIG_SND_PCXHR is not set # CONFIG_SND_RIPTIDE is not set # CONFIG_SND_RME32 is not set # CONFIG_SND_RME96 is not set # CONFIG_SND_RME9652 is not set # CONFIG_SND_SONICVIBES is not set # CONFIG_SND_TRIDENT is not set # CONFIG_SND_VIA82XX is not set # CONFIG_SND_VIA82XX_MODEM is not set # CONFIG_SND_VX222 is not set # CONFIG_SND_YMFPCI is not set # # ALSA MIPS devices # # # USB devices # CONFIG_SND_USB_AUDIO=m # # PCMCIA devices # # CONFIG_SND_VXPOCKET is not set # CONFIG_SND_PDAUDIOCF is not set # # Open Sound System # # CONFIG_SOUND_PRIME is not set # # USB support # CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=y CONFIG_USB_DEBUG=y # # Miscellaneous USB options # CONFIG_USB_DEVICEFS=y # CONFIG_USB_BANDWIDTH is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set # # USB Host Controller Drivers # CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_SPLIT_ISO is not set # CONFIG_USB_EHCI_ROOT_HUB_TT is not set CONFIG_USB_ISP116X_HCD=m CONFIG_USB_OHCI_HCD=m # CONFIG_USB_OHCI_BIG_ENDIAN is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # # USB Device Class drivers # CONFIG_USB_ACM=y CONFIG_USB_PRINTER=m # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # # may also be needed; see USB_STORAGE Help for more information # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_LIBUSUAL is not set # # USB Input Devices # CONFIG_USB_HID=y CONFIG_USB_HIDINPUT=y # CONFIG_USB_HIDINPUT_POWERBOOK is not set CONFIG_HID_FF=y CONFIG_HID_PID=y CONFIG_LOGITECH_FF=y CONFIG_THRUSTMASTER_FF=y CONFIG_USB_HIDDEV=y # CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set # CONFIG_USB_ACECAD is not set # CONFIG_USB_KBTAB is not set # CONFIG_USB_POWERMATE is not set # CONFIG_USB_TOUCHSCREEN is not set # CONFIG_USB_YEALINK is not set # CONFIG_USB_XPAD is not set # CONFIG_USB_ATI_REMOTE is not set # CONFIG_USB_ATI_REMOTE2 is not set # CONFIG_USB_KEYSPAN_REMOTE is not set # CONFIG_USB_APPLETOUCH is not set # # USB Imaging devices # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # # USB Network Adapters # # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set # CONFIG_USB_ZD1201 is not set CONFIG_USB_MON=y # # USB port drivers # # # USB Serial Converter support # # CONFIG_USB_SERIAL is not set # # USB Miscellaneous drivers # # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_AUERSWALD is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYTHERM is not set # CONFIG_USB_PHIDGETKIT is not set # CONFIG_USB_PHIDGETSERVO is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TEST is not set # # USB DSL modem support # CONFIG_USB_ATM=m # CONFIG_USB_SPEEDTOUCH is not set # CONFIG_USB_CXACRU is not set CONFIG_USB_UEAGLEATM=m # CONFIG_USB_XUSBATM is not set # # USB Gadget Support # # CONFIG_USB_GADGET is not set # # MMC/SD Card support # # CONFIG_MMC is not set # # LED devices # # CONFIG_NEW_LEDS is not set # # LED drivers # # # LED Triggers # # # InfiniBand support # # CONFIG_INFINIBAND is not set # # EDAC - error detection and reporting (RAS) (EXPERIMENTAL) # # # Real Time Clock # # CONFIG_RTC_CLASS is not set # # File systems # # CONFIG_EXT2_FS is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_INOTIFY=y # CONFIG_QUOTA is not set # CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # CONFIG_FAT_FS=m # CONFIG_MSDOS_FS is not set CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_NTFS_FS is not set # # Pseudo filesystems # CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set # CONFIG_DEVFS_FS is not set CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # # Miscellaneous filesystems # # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y # CONFIG_JFFS2_SUMMARY is not set CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set # CONFIG_JFFS2_CMODE_NONE is not set CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set # CONFIG_CRAMFS is not set CONFIG_SQUASHFS=y # CONFIG_SQUASHFS_EMBEDDED is not set CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_SQUASHFS_VMALLOC is not set # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # # Network File Systems # # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set # CONFIG_SMB_FS is not set CONFIG_CIFS=m # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_XATTR is not set # CONFIG_CIFS_EXPERIMENTAL is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set # CONFIG_9P_FS is not set # # Partition Types # CONFIG_PARTITION_ADVANCED=y # CONFIG_ACORN_PARTITION is not set # CONFIG_OSF_PARTITION is not set # CONFIG_AMIGA_PARTITION is not set # CONFIG_ATARI_PARTITION is not set # CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y # CONFIG_BSD_DISKLABEL is not set # CONFIG_MINIX_SUBPARTITION is not set # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set # CONFIG_SGI_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # # Native Language Support # CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set CONFIG_NLS_CODEPAGE_850=m # CONFIG_NLS_CODEPAGE_852 is not set # CONFIG_NLS_CODEPAGE_855 is not set # CONFIG_NLS_CODEPAGE_857 is not set # CONFIG_NLS_CODEPAGE_860 is not set # CONFIG_NLS_CODEPAGE_861 is not set # CONFIG_NLS_CODEPAGE_862 is not set # CONFIG_NLS_CODEPAGE_863 is not set # CONFIG_NLS_CODEPAGE_864 is not set # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set # CONFIG_NLS_CODEPAGE_869 is not set # CONFIG_NLS_CODEPAGE_936 is not set # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set # CONFIG_NLS_CODEPAGE_949 is not set # CONFIG_NLS_CODEPAGE_874 is not set # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_ASCII is not set CONFIG_NLS_ISO8859_1=m # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set # CONFIG_NLS_ISO8859_5 is not set # CONFIG_NLS_ISO8859_6 is not set # CONFIG_NLS_ISO8859_7 is not set # CONFIG_NLS_ISO8859_9 is not set # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set CONFIG_NLS_ISO8859_15=m # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set CONFIG_NLS_UTF8=m # # Profiling support # # CONFIG_PROFILING is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set # CONFIG_MAGIC_SYSRQ is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_DEBUG_FS is not set CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="root=/dev/sda1 rootdelay=10 console=ttyS0,115200" # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # # Cryptographic options # CONFIG_CRYPTO=y CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=m CONFIG_CRYPTO_SHA1=y # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_TGR192 is not set CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_TWOFISH is not set # CONFIG_CRYPTO_SERPENT is not set CONFIG_CRYPTO_AES=m # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set # CONFIG_CRYPTO_TEA is not set CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_ANUBIS is not set CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_MICHAEL_MIC=m # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_TEST is not set # # Hardware crypto devices # # # Library routines # CONFIG_CRC_CCITT=y CONFIG_CRC16=m CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m From david.goodenough@linkchoose.co.uk Tue Sep 5 16:11:48 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Sep 2006 16:11:49 +0100 (BST) Received: from ip-217-204-115-127.easynet.co.uk ([217.204.115.127]:21767 "EHLO apollo.linkchoose.co.uk") by ftp.linux-mips.org with ESMTP id S20037572AbWIEPLs (ORCPT ); Tue, 5 Sep 2006 16:11:48 +0100 Received: from [10.98.1.127] (helo=galaxy.dga.co.uk) by apollo.linkchoose.co.uk with esmtp (Exim 4.60) (envelope-from ) id 1GKcb7-0006q1-7M for linux-mips@linux-mips.org; Tue, 05 Sep 2006 16:12:21 +0100 Received: from [10.0.1.63] by galaxy.dga.co.uk with esmtp (Exim 4.62) (envelope-from ) id 1GKcaO-0002Kw-1l for linux-mips@linux-mips.org; Tue, 05 Sep 2006 16:11:36 +0100 From: David Goodenough Organization: Linkchoose Ltd To: linux-mips@linux-mips.org Subject: Re: ADM5120 support Date: Tue, 5 Sep 2006 16:11:33 +0100 User-Agent: KMail/1.9.3 References: <200609011150.54312.david.goodenough@linkchoose.co.uk> <20060904061141.GB5361@domen.puncer.telargo.com> In-Reply-To: <20060904061141.GB5361@domen.puncer.telargo.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200609051611.34286.david.goodenough@linkchoose.co.uk> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12516 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.goodenough@linkchoose.co.uk Precedence: bulk X-list: linux-mips On Monday 04 September 2006 07:11, Domen Puncer wrote: > On 01/09/06 11:50 +0100, David Goodenough wrote: > > I have found some patches for the ADM5120 on the web for 2.6.12, but > > nothing more recent. Anyone know of an updated patch (if updating is > > needed)? > > Hi! > > I forward ported them to 2.6.15, but then lost interest. > > http://coderock.org/planet_xrt-401d/files/ > > > Domen > > > David Thank you. I tried to use those but obviously I have something wrong in my config. The patches apply, but then when it tried to compile it complains on the first CC saying that THREAD_SIZE_ORDER is undefined. This looks as though I have the config wrong. Do you have a working config to go with your patches? Regards David From sshtylyov@ru.mvista.com Tue Sep 5 16:17:44 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Sep 2006 16:17:46 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:36992 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20037585AbWIEPRo (ORCPT ); Tue, 5 Sep 2006 16:17:44 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id CB26B3EBE; Tue, 5 Sep 2006 08:17:17 -0700 (PDT) Message-ID: <44FD9587.3030708@ru.mvista.com> Date: Tue, 05 Sep 2006 19:19:35 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Ralf Baechle Cc: Rodolfo Giometti , linux-mips@linux-mips.org, rmk+serial@arm.linux.org.uk Subject: Re: [PATCH] au1x00 serial real interrupt References: <20060522165244.GA16223@enneenne.com> In-Reply-To: <20060522165244.GA16223@enneenne.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12517 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Rodolfo Giometti wrote: > Here my patch to enable real interrupts management for the au1x00 > CPUs. > ------------------------------------------------------------------------ > > diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h > index 7b23664..0197062 100644 > --- a/include/asm-mips/serial.h > +++ b/include/asm-mips/serial.h > @@ -11,6 +11,14 @@ > > #include > > +#ifdef CONFIG_SOC_AU1X00 > +/* > + * We have to redefine "is_real_interrupt()" for Au1x00 CPUs... > + */ > +#undef is_real_interrupt > +#define is_real_interrupt(irq) ((irq) != ~0) > +#endif > + > /* > * This assumes you have a 1.8432 MHz clock for your UART. > * Ralf, how about this patch? Can it be applied, at least 3 months after posting? Alchemy UART0 uses IRQ0 and 0 is treated as "no IRQ" by drivers/serial/8250.c which says the macro should be redefined in if needed. WBR, Sergei From domen.puncer@telargo.com Wed Sep 6 07:21:37 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Sep 2006 07:21:41 +0100 (BST) Received: from out001.atlarge.net ([129.41.63.69]:43202 "EHLO out001.atlarge.net") by ftp.linux-mips.org with ESMTP id S20037854AbWIFGVh (ORCPT ); Wed, 6 Sep 2006 07:21:37 +0100 Received: from hpmailfe-01.atlarge.net ([10.100.60.156]) by out001.atlarge.net with Microsoft SMTPSVC(6.0.3790.1830); Wed, 6 Sep 2006 01:20:08 -0500 Received: from localhost ([213.250.36.225]) by hpmailfe-01.atlarge.net with Microsoft SMTPSVC(6.0.3790.1830); Wed, 6 Sep 2006 01:20:07 -0500 Date: Wed, 6 Sep 2006 08:21:28 +0200 From: Domen Puncer To: David Goodenough Cc: linux-mips@linux-mips.org Subject: Re: ADM5120 support Message-ID: <20060906062128.GE5361@domen.puncer.telargo.com> References: <200609011150.54312.david.goodenough@linkchoose.co.uk> <20060904061141.GB5361@domen.puncer.telargo.com> <200609051611.34286.david.goodenough@linkchoose.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200609051611.34286.david.goodenough@linkchoose.co.uk> User-Agent: Mutt/1.5.12-2006-07-14 X-OriginalArrivalTime: 06 Sep 2006 06:20:07.0798 (UTC) FILETIME=[7FDD0960:01C6D17C] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12518 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen.puncer@telargo.com Precedence: bulk X-list: linux-mips On 05/09/06 16:11 +0100, David Goodenough wrote: > On Monday 04 September 2006 07:11, Domen Puncer wrote: > > On 01/09/06 11:50 +0100, David Goodenough wrote: > > > I have found some patches for the ADM5120 on the web for 2.6.12, but > > > nothing more recent. Anyone know of an updated patch (if updating is > > > needed)? > > > > Hi! > > > > I forward ported them to 2.6.15, but then lost interest. > > > > http://coderock.org/planet_xrt-401d/files/ > > > > > > Domen > > > > > David > Thank you. I tried to use those but obviously I have something wrong in > my config. The patches apply, but then when it tried to compile it > complains on the first CC saying that THREAD_SIZE_ORDER is undefined. This > looks as though I have the config wrong. Do you have a working config to > go with your patches? http://coderock.org/planet_xrt-401d/files/config-adm should be the latest I tried. Domen > > Regards > > David From david.goodenough@linkchoose.co.uk Wed Sep 6 09:22:02 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Sep 2006 09:22:06 +0100 (BST) Received: from ip-217-204-115-127.easynet.co.uk ([217.204.115.127]:33554 "EHLO apollo.linkchoose.co.uk") by ftp.linux-mips.org with ESMTP id S20037874AbWIFIWC (ORCPT ); Wed, 6 Sep 2006 09:22:02 +0100 Received: from [10.98.1.127] (helo=galaxy.dga.co.uk) by apollo.linkchoose.co.uk with esmtp (Exim 4.60) (envelope-from ) id 1GKsgC-0007TG-Eq for linux-mips@linux-mips.org; Wed, 06 Sep 2006 09:22:40 +0100 Received: from [10.0.1.63] by galaxy.dga.co.uk with esmtp (Exim 4.62) (envelope-from ) id 1GKsfO-0003N1-G1 for linux-mips@linux-mips.org; Wed, 06 Sep 2006 09:21:50 +0100 From: David Goodenough Organization: Linkchoose Ltd To: linux-mips@linux-mips.org Subject: Re: ADM5120 support Date: Wed, 6 Sep 2006 09:21:52 +0100 User-Agent: KMail/1.9.3 References: <200609011150.54312.david.goodenough@linkchoose.co.uk> <200609051611.34286.david.goodenough@linkchoose.co.uk> <20060906062128.GE5361@domen.puncer.telargo.com> In-Reply-To: <20060906062128.GE5361@domen.puncer.telargo.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200609060921.52642.david.goodenough@linkchoose.co.uk> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12519 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.goodenough@linkchoose.co.uk Precedence: bulk X-list: linux-mips On Wednesday 06 September 2006 07:21, Domen Puncer wrote: > On 05/09/06 16:11 +0100, David Goodenough wrote: > > On Monday 04 September 2006 07:11, Domen Puncer wrote: > > > On 01/09/06 11:50 +0100, David Goodenough wrote: > > > > I have found some patches for the ADM5120 on the web for 2.6.12, but > > > > nothing more recent. Anyone know of an updated patch (if updating is > > > > needed)? > > > > > > Hi! > > > > > > I forward ported them to 2.6.15, but then lost interest. > > > > > > http://coderock.org/planet_xrt-401d/files/ > > > > > > > > > Domen > > > > > > > David > > > > Thank you. I tried to use those but obviously I have something wrong in > > my config. The patches apply, but then when it tried to compile it > > complains on the first CC saying that THREAD_SIZE_ORDER is undefined. > > This looks as though I have the config wrong. Do you have a working > > config to go with your patches? > > http://coderock.org/planet_xrt-401d/files/config-adm > should be the latest I tried. > Thank you David > > Domen > > > Regards > > > > David From anemo@mba.ocn.ne.jp Wed Sep 6 14:40:11 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Sep 2006 14:40:13 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:14066 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20037591AbWIFNkL (ORCPT ); Wed, 6 Sep 2006 14:40:11 +0100 Received: from localhost (p4200-ipad31funabasi.chiba.ocn.ne.jp [221.189.128.200]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 9FC05AB65; Wed, 6 Sep 2006 22:40:06 +0900 (JST) Date: Wed, 06 Sep 2006 22:42:02 +0900 (JST) Message-Id: <20060906.224202.25912085.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, drow@false.org, kaz@zeugmasystems.com Subject: [PATCH] Wire up set_robust_list(2) and get_robust_list(2) From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12520 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Signed-off-by: Atsushi Nemoto arch/mips/kernel/scall32-o32.S | 2 ++ arch/mips/kernel/scall64-64.S | 2 ++ arch/mips/kernel/scall64-n32.S | 4 +++- arch/mips/kernel/scall64-o32.S | 2 ++ include/asm-mips/unistd.h | 18 ++++++++++++------ 5 files changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index ba1bcd8..e717851 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -662,6 +662,8 @@ #endif /* CONFIG_MIPS_MT_FPAFF */ sys sys_tee 4 sys sys_vmsplice 4 sys sys_move_pages 6 + sys sys_set_robust_list 2 + sys sys_get_robust_list 3 .endm /* We pre-compute the number of _instruction_ bytes needed to diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 939e172..4c22d0b 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -466,3 +466,5 @@ sys_call_table: PTR sys_tee /* 5265 */ PTR sys_vmsplice PTR sys_move_pages + PTR sys_set_robust_list + PTR sys_get_robust_list diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 549b4bc..f25c2a2 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -390,5 +390,7 @@ EXPORT(sysn32_call_table) PTR sys_splice PTR sys_sync_file_range PTR sys_tee - PTR sys_vmsplice /* 6271 */ + PTR sys_vmsplice /* 6270 */ PTR sys_move_pages + PTR compat_sys_set_robust_list + PTR compat_sys_get_robust_list diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 505c9ee..2ac0141 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -514,4 +514,6 @@ sys_call_table: PTR sys_tee PTR sys_vmsplice PTR compat_sys_move_pages + PTR compat_sys_set_robust_list + PTR compat_sys_get_robust_list /* 4310 */ .size sys_call_table,.-sys_call_table diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index 610ccb8..558e3cb 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -329,16 +329,18 @@ #define __NR_sync_file_range (__NR_Linu #define __NR_tee (__NR_Linux + 306) #define __NR_vmsplice (__NR_Linux + 307) #define __NR_move_pages (__NR_Linux + 308) +#define __NR_set_robust_list (__NR_Linux + 309) +#define __NR_get_robust_list (__NR_Linux + 310) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 308 +#define __NR_Linux_syscalls 310 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 308 +#define __NR_O32_Linux_syscalls 310 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -614,16 +616,18 @@ #define __NR_sync_file_range (__NR_Linu #define __NR_tee (__NR_Linux + 265) #define __NR_vmsplice (__NR_Linux + 266) #define __NR_move_pages (__NR_Linux + 267) +#define __NR_set_robust_list (__NR_Linux + 268) +#define __NR_get_robust_list (__NR_Linux + 269) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 267 +#define __NR_Linux_syscalls 269 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 267 +#define __NR_64_Linux_syscalls 269 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -903,16 +907,18 @@ #define __NR_sync_file_range (__NR_Linu #define __NR_tee (__NR_Linux + 269) #define __NR_vmsplice (__NR_Linux + 270) #define __NR_move_pages (__NR_Linux + 271) +#define __NR_set_robust_list (__NR_Linux + 272) +#define __NR_get_robust_list (__NR_Linux + 273) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 271 +#define __NR_Linux_syscalls 273 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 271 +#define __NR_N32_Linux_syscalls 273 #ifdef __KERNEL__ From anemo@mba.ocn.ne.jp Wed Sep 6 16:58:33 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Sep 2006 16:58:35 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:448 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20037849AbWIFP6d (ORCPT ); Wed, 6 Sep 2006 16:58:33 +0100 Received: from localhost (p4200-ipad31funabasi.chiba.ocn.ne.jp [221.189.128.200]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 15843AAA0; Thu, 7 Sep 2006 00:58:27 +0900 (JST) Date: Thu, 07 Sep 2006 01:00:22 +0900 (JST) Message-Id: <20060907.010022.126141861.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] fix errors detected by "make headers_check" From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12521 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips * export asm/sgidefs.h * include asm/isadep.h only if in kernel * do not export contents of asm/timex.h and asm/user.h Signed-off-by: Atsushi Nemoto Kbuild | 2 ++ ptrace.h | 3 +-- timex.h | 4 ++++ user.h | 4 ++++ 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/include/asm-mips/Kbuild b/include/asm-mips/Kbuild index c68e168..01ea3e0 100644 --- a/include/asm-mips/Kbuild +++ b/include/asm-mips/Kbuild @@ -1 +1,3 @@ include include/asm-generic/Kbuild.asm + +header-y += sgidefs.h diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 4113316..4fb0fc4 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h @@ -10,8 +10,6 @@ #ifndef _ASM_PTRACE_H #define _ASM_PTRACE_H -#include - /* 0 - 31 are integer registers, 32 - 63 are fp registers. */ #define FPR_BASE 32 #define PC 64 @@ -73,6 +71,7 @@ #define PTRACE_GET_THREAD_AREA_3264 0xc4 #ifdef __KERNEL__ #include +#include /* * Does the process account for user or for system time? diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h index 98aa737..b80de8e 100644 --- a/include/asm-mips/timex.h +++ b/include/asm-mips/timex.h @@ -8,6 +8,8 @@ #ifndef _ASM_TIMEX_H #define _ASM_TIMEX_H +#ifdef __KERNEL__ + #include /* @@ -51,4 +53,6 @@ static inline cycles_t get_cycles (void) return read_c0_count(); } +#endif /* __KERNEL__ */ + #endif /* _ASM_TIMEX_H */ diff --git a/include/asm-mips/user.h b/include/asm-mips/user.h index 89bf8b4..61f2a09 100644 --- a/include/asm-mips/user.h +++ b/include/asm-mips/user.h @@ -8,6 +8,8 @@ #ifndef _ASM_USER_H #define _ASM_USER_H +#ifdef __KERNEL__ + #include #include @@ -55,4 +57,6 @@ #define HOST_TEXT_START_ADDR (u.start_co #define HOST_DATA_START_ADDR (u.start_data) #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) +#endif /* __KERNEL__ */ + #endif /* _ASM_USER_H */ From kaz@zeugmasystems.com Wed Sep 6 18:47:20 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Sep 2006 18:47:50 +0100 (BST) Received: from mail.zeugmasystems.com ([192.139.122.66]:39527 "EHLO zeugmasystems.com") by ftp.linux-mips.org with ESMTP id S20038428AbWIFRrU convert rfc822-to-8bit (ORCPT ); Wed, 6 Sep 2006 18:47:20 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH] Wire up set_robust_list(2) and get_robust_list(2) Date: Wed, 6 Sep 2006 10:47:16 -0700 Message-ID: <66910A579C9312469A7DF9ADB54A8B7D38FEF5@exchange.ZeugmaSystems.local> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH] Wire up set_robust_list(2) and get_robust_list(2) Thread-Index: AcbRufh0ljGa+eRQSYOoVReewsCxZwAFtHYw From: "Kaz Kylheku" To: "Atsushi Nemoto" , Cc: , , Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12522 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kaz@zeugmasystems.com Precedence: bulk X-list: linux-mips Arigato gozaimas, Nemoto-san! I have applied your patch (actually back-ported it to the 2.6.17.7 kernel I'm using). I built the kernel, and then recompiled glibc against the patched headers, and booted into the SB1-based board. The NPTL robust mutex test cases pass now, including the process-shared one. From ashlesha@kenati.com Wed Sep 6 19:03:16 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Sep 2006 19:03:18 +0100 (BST) Received: from [69.90.147.196] ([69.90.147.196]:44256 "EHLO mail.kenati.com") by ftp.linux-mips.org with ESMTP id S20038438AbWIFSDQ (ORCPT ); Wed, 6 Sep 2006 19:03:16 +0100 Received: from [192.168.1.169] (adsl-71-130-109-177.dsl.snfc21.pacbell.net [71.130.109.177]) by mail.kenati.com (Postfix) with ESMTP id 27059E404D for ; Wed, 6 Sep 2006 11:22:55 -0700 (PDT) Subject: RE: early_initcall From: Ashlesha Shintre Reply-To: ashlesha@kenati.com To: linux-mips@linux-mips.org In-Reply-To: <66910A579C9312469A7DF9ADB54A8B7D366028@exchange.ZeugmaSystems.local> References: <66910A579C9312469A7DF9ADB54A8B7D366028@exchange.ZeugmaSystems.local> Content-Type: multipart/mixed; boundary="=-WE85dbB5N2g9IOrFL7He" Date: Wed, 06 Sep 2006 11:10:47 -0700 Message-Id: <1157566247.6485.12.camel@sandbar.kenati.com> Mime-Version: 1.0 X-Mailer: Evolution 2.4.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12523 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ashlesha@kenati.com Precedence: bulk X-list: linux-mips --=-WE85dbB5N2g9IOrFL7He Content-Type: text/plain Content-Transfer-Encoding: 7bit I googled early_initcall and found a patch which basically adds this line to the /include/init.h file: #define early_initcall(fn) __define_initcall(".early1",fn) I built a kernel image with this new line included and now if I try executing it, the bootloader YAMON gives an exception error before it can even begin! Here is the dump: ************************* User Exception ********************************** Exception State 24 Machine check (((((((((((((((((((( CPU Registers ))))))))))))))))))))))))))))) zr: 00000000 at: 10007c00 v0: 00000003 v1: 00000004 a0: 14000017 a1: 14080017 a2: 50000000 a3: 00000000 t0: 40000000 t1: 01ffe000 t2: 80400000 t3: 80410000 t4: 80400000 t5: fffffffe t6: ffffffff t7: 00000010 s0: 10007c00 s1: 80380000 s2: 80400000 s3: 80401c5c s4: 80400000 s5: 803affc0 s6: 00000000 s7: 00000000 t8: 00000006 t9: 803afde6 k0: 00000000 k1: 00000000 gp: 803ae000 sp: 803aff10 s8: 800e8380 ra: 803f68c0 {{{{{{{{{{{{{{{{{{{{{ CP0 Registers }}}}}}}}}}}}}}}}}}}}}}}}}}}}} Index: 00000003 Random: 00000019 EntryLo0: 14000017 EntryLo1: 14080017 Context: 007ffff0 Page Mask: 00000000 Wired NO: 00000004 Reg 7: 00000000 Reg 8: fffffff4 Reg 9: 4d691cb7 Entry Hi: 50000000 Reg 11: 00000000 Reg 12: 10007c02 Reg 13: 00808060 Reg 14: 803f0484 Proc ID: 01030200 ERROREPC: 00000000 Config: 80008083 Config 1: 00000000 WatchLo: 00000000 WatchHi: 80000000 Debug: 00008000 DEPC: 00000000 STATUS: 10007c02 CAUSE: 00808060 EPC: 803f0484 BADVADDR: fffffff4 LO: 04000000 HI: 00000000 A machine check means that an exception is generated due to duplicate TLB entries. I dont understand why the kernel crashes so early. Also, what does the ".early1" mean? Is that a definition of a different segment in the init.h file? I checked output of the "readelf -a vmlinux" and found that the address for the early_initcall comes up about 5 times. I m not sure what each of the fields mean, so I have attached the above part of the readelf in a file called readelf. Thank you! Ashlesha. On Fri, 2006-09-01 at 17:50 -0700, Kaz Kylheku wrote: > > Ashlesha Shintre wrote: > > > > Hi, > > > > I m using the 2.6.14.6 tree and trying to get the kernel > > running on the > > Encore M3 board. > > > > The kernel crashes during the boot process at the > > early_initcall. > > What is the exact output from the crash? > > > This function doesnt seem to be defined anywhere. > > It's not a function, but a macro. The macro is used to annotate a > function as being among the list of functions that are called at startup > by the "initcall" mechanism: a big loop that sweeps over a symbol table > of registered initialization functions and calls them. E.g. > > #include > > /* ... */ > > int __init my_initialization_function(void) > { > printk(KERN_INFO "Hello, world\n"); > } > > early_initcall(my_initialization_function); > > The __init tells the kernel build system that your function is not > needed after initialization and its memory can be thrown away. The > early_initcall arranges for the initialization call. Early means that > it's in the first group of functions. > > If you suspect your kernel is dying during the calling of the initcall > functions, you can turn on initcall debugging. Add these parameters to > your kernel command line: > > debug debug_initcall > > Hope this helps. > > --=-WE85dbB5N2g9IOrFL7He Content-Disposition: attachment; filename=readelf.doc Content-Type: application/msword; name=readelf.doc Content-Transfer-Encoding: base64 0M8R4KGxGuEAAAAAAAAAAAAAAAAAAAAAOwADAP7/CQAGAAAAAAAAAAAAAAACAAAAhgAAAAAAAAAA EAAAAgAAAAEAAAD+////AAAAAAAAAACAAAAA//////////////////////////////////////// //////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////9 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From mangoo@wpkg.org Wed Sep 6 20:47:23 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Sep 2006 20:47:25 +0100 (BST) Received: from mail.syneticon.net ([213.239.212.131]:55262 "EHLO mail2.syneticon.net") by ftp.linux-mips.org with ESMTP id S20038457AbWIFTrX (ORCPT ); Wed, 6 Sep 2006 20:47:23 +0100 Received: from localhost (localhost [127.0.0.1]) by mail2.syneticon.net (Postfix) with ESMTP id A58A03C301 for ; Wed, 6 Sep 2006 21:47:16 +0200 (CEST) Received: from mail2.syneticon.net ([127.0.0.1]) by localhost (linux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 04700-05 for ; Wed, 6 Sep 2006 21:47:11 +0200 (CEST) Received: from [192.168.10.145] (xdsl-84-44-195-254.netcologne.de [84.44.195.254]) by mail2.syneticon.net (Postfix) with ESMTP for ; Wed, 6 Sep 2006 21:47:11 +0200 (CEST) Message-ID: <44FF25BE.5020901@wpkg.org> Date: Wed, 06 Sep 2006 21:47:10 +0200 From: Tomasz Chmielewski User-Agent: Thunderbird 1.5.0.5 (X11/20060814) MIME-Version: 1.0 Cc: linux-mips@linux-mips.org Subject: Re: no USB device other than storage detected References: <44FD6CE4.6010001@wpkg.org> In-Reply-To: <44FD6CE4.6010001@wpkg.org> Content-Type: text/plain; charset=ISO-8859-2; format=flowed Content-Transfer-Encoding: 7bit X-Virus-Scanned: amavisd-new at syneticon.de To: unlisted-recipients:; (no To-header on input) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12524 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mangoo@wpkg.org Precedence: bulk X-list: linux-mips Tomasz Chmielewski wrote: > I have a tiny router (ASUS WL-500g deluxe, MIPS CPU, 32 MB RAM, 2x > USB2), and would like to make it work with a USB DSL modem. > > Right now, it's running Debian and kernel 2.6.17, and boots off a > USB-stick. > > My problem is, that it only sees USB storage devices (USB sticks etc.). > > When I connect other devices (USB modem, webcam, microphone, keyboard, > printer etc.), they are not detected. > By "not detected" I mean there are no "dmesg" entries with the device > name, and no devices, other than "USB storage", listed with "lsusb". > > I even compiled "USB verbose logging" in, but it only gives me a couple > of debug infos, no clue why the devices doesn't show up. It looks that something's borked in 2.6.17 kernel. When I load ohci module, it complains a lot: USB Universal Host Controller Interface driver v3.0 PCI: Fixing up device 0000:01:02.0 uhci_hcd 0000:01:02.0: no i/o regions available uhci_hcd 0000:01:02.0: init 0000:01:02.0 fail, -16 uhci_hcd: probe of 0000:01:02.0 failed with error -16 PCI: Fixing up device 0000:01:02.1 uhci_hcd 0000:01:02.1: no i/o regions available uhci_hcd 0000:01:02.1: init 0000:01:02.1 fail, -16 uhci_hcd: probe of 0000:01:02.1 failed with error -16 With 2.4.30 kernel, ohci module loads fine, and I can use all USB devices: # lsusb Bus 002 Device 001: ID 0000:0000 Bus 001 Device 001: ID 0000:0000 Bus 001 Device 004: ID 03f0:3011 Hewlett-Packard Bus 001 Device 003: ID 0471:0310 Philips PCVC730K WebCam [pwc] Ideas what can be wrong? -- Tomasz Chmielewski http://wpkg.org From imipak@yahoo.com Wed Sep 6 22:41:43 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Sep 2006 22:41:44 +0100 (BST) Received: from web31504.mail.mud.yahoo.com ([68.142.198.133]:18613 "HELO web31504.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20038516AbWIFVln (ORCPT ); Wed, 6 Sep 2006 22:41:43 +0100 Received: (qmail 54754 invoked by uid 60001); 6 Sep 2006 21:41:36 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=4hWps08PpcZiUxBC8xmMCJ7tkf1LW39Ly1pAwSddZbB5apRZj9tzTjWjchF5iBnVoC6y4X3qf59ijHuaId4ayXGZy5gVUFOYUepB6jtv1iJcO89CgJcMfdqpMj5umoaTEJUm5NFuWhwXt3Wk4vv0MFLuWgr1O0UAHCSIq69b9v8= ; Message-ID: <20060906214136.54752.qmail@web31504.mail.mud.yahoo.com> Received: from [70.103.67.194] by web31504.mail.mud.yahoo.com via HTTP; Wed, 06 Sep 2006 14:41:36 PDT Date: Wed, 6 Sep 2006 14:41:36 -0700 (PDT) From: Jonathan Day Subject: Resetting a Broadcom in software To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="0-1897457798-1157578896=:54718" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12525 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips --0-1897457798-1157578896=:54718 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Content-Id: Content-Disposition: inline Hi, A co-worker wrote the following test of the Broadcom's maths abilities and discovered that it reboots some (but not all) MIPS processors it has been tested on. It'll reboot the Sentosa, for example, but NOT the Swarm. (Apologies for the ugly coding, btw.) You just make the first file, the ATL_ file gets included into it. The compiler flags I'm using are: -march=sb1 -mabi=64 -fomit-frame-pointer -O3 -mips64 -mfused-madd The program doesn't link to anything and no linker flags are needed. This begs three questions: 1) What is happening to cause the CPU to reset? (It's not a kernel bug, it's an actual CPU reset) 2) What is NOT happening on the Swarm, allowing it to work fine? 3) Is the problem in the category of "preventable in hardware", "preventable in the kernel", or "preventable by slowly roasting those coders who write like this"? __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! 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dl5rb.ham-radio-op.net (localhost [127.0.0.1]) by oss.sgi.com (8.12.10/8.12.10/SuSE Linux 0.7) with ESMTP id k86MWPDW023600 for ; Wed, 6 Sep 2006 15:32:26 -0700 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k86MWPpS013821; Thu, 7 Sep 2006 00:32:25 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k86MWOUo013820; Thu, 7 Sep 2006 00:32:24 +0200 Date: Thu, 7 Sep 2006 00:32:24 +0200 From: Ralf Baechle To: Jonathan Day Cc: linux-mips@linux-mips.org Subject: Re: Resetting a Broadcom in software Message-ID: <20060906223224.GA12175@linux-mips.org> References: <20060906214136.54752.qmail@web31504.mail.mud.yahoo.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060906214136.54752.qmail@web31504.mail.mud.yahoo.com> User-Agent: Mutt/1.4.2.1i X-Virus-Scanned: ClamAV 0.88.2/1594/Wed Jul 12 08:04:34 2006 on oss.sgi.com X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12526 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Sep 06, 2006 at 02:41:36PM -0700, Jonathan Day wrote: > Date: Wed, 6 Sep 2006 14:41:36 -0700 (PDT) > From: Jonathan Day > Subject: Resetting a Broadcom in software > To: linux-mips@linux-mips.org > Content-Type: multipart/mixed; boundary="0-1897457798-1157578896=:54718" > > Hi, > > A co-worker wrote the following test of the Broadcom's > maths abilities and discovered that it reboots some > (but not all) MIPS processors it has been tested on. > It'll reboot the Sentosa, for example, but NOT the > Swarm. > > (Apologies for the ugly coding, btw.) > > You just make the first file, the ATL_ file gets > included into it. The compiler flags I'm using are: > > -march=sb1 -mabi=64 -fomit-frame-pointer -O3 -mips64 > -mfused-madd > > The program doesn't link to anything and no linker > flags are needed. > > This begs three questions: > > 1) What is happening to cause the CPU to reset? (It's > not a kernel bug, it's an actual CPU reset) > > 2) What is NOT happening on the Swarm, allowing it to > work fine? > > 3) Is the problem in the category of "preventable in > hardware", "preventable in the kernel", or > "preventable by slowly roasting those coders who write > like this"? This is not a problem I know of but given your description it sounds very much like a hardware issue. Can you find about the exact versions of the 1250 on the various board? With the FPU being on chip I would expect some correlation between the chip revision and this issue. Ralf From imipak@yahoo.com Wed Sep 6 23:59:45 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Sep 2006 23:59:47 +0100 (BST) Received: from web31503.mail.mud.yahoo.com ([68.142.198.132]:41853 "HELO web31503.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20038532AbWIFW7p (ORCPT ); Wed, 6 Sep 2006 23:59:45 +0100 Received: (qmail 55261 invoked by uid 60001); 6 Sep 2006 22:59:39 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:Cc:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=x0qrWj72UTyWDjeMs9bawOVfV1pA8lTRcLYrkS7DnhoAPgJ+dUP8u/ys0yLp5ngYQ2uk+g4G7gQj1wSgy6nIKBpSQR77WyksZl61wpKq3FrFM7kPgF8gnzxWLHI0s8JrZTNp6Nq6ZxS6La74QLrZvuA9aB2VlH3kKeisX6eRqwY= ; Message-ID: <20060906225939.55259.qmail@web31503.mail.mud.yahoo.com> Received: from [70.103.67.194] by web31503.mail.mud.yahoo.com via HTTP; Wed, 06 Sep 2006 15:59:39 PDT Date: Wed, 6 Sep 2006 15:59:39 -0700 (PDT) From: Jonathan Day Subject: Re: Resetting a Broadcom in software To: Ralf Baechle Cc: linux-mips@linux-mips.org In-Reply-To: <20060906223224.GA12175@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12527 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips The Sentosa uses a dual-core Broadcom 1250 processor with an SB1 version 0.2 core. The board is BCM91250E Revision 1. The Swarm also uses a Broadcom 1250 with an SB1 version 0.2 core, but the board is a BCM91250A. Most of the difference seems to be in the motherboard, rather than the CPU, but I couldn't tell you what the difference is between an E and an A, and why the A seems better-behaved. --- Ralf Baechle wrote: > This is not a problem I know of but given your > description it sounds very > much like a hardware issue. Can you find about the > exact versions of the > 1250 on the various board? With the FPU being on > chip I would expect > some correlation between the chip revision and this > issue. __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From ralf@linux-mips.org Thu Sep 7 02:02:50 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Sep 2006 02:02:52 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:10911 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20037867AbWIGBCu (ORCPT ); Thu, 7 Sep 2006 02:02:50 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k8713OwS017635; Thu, 7 Sep 2006 03:03:24 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k8713OjX017634; Thu, 7 Sep 2006 03:03:24 +0200 Date: Thu, 7 Sep 2006 03:03:24 +0200 From: Ralf Baechle To: Jonathan Day Cc: linux-mips@linux-mips.org Subject: Re: Resetting a Broadcom in software Message-ID: <20060907010324.GA17536@linux-mips.org> References: <20060906223224.GA12175@linux-mips.org> <20060906225939.55259.qmail@web31503.mail.mud.yahoo.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060906225939.55259.qmail@web31503.mail.mud.yahoo.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12528 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Sep 06, 2006 at 03:59:39PM -0700, Jonathan Day wrote: > The Sentosa uses a dual-core Broadcom 1250 processor > with an SB1 version 0.2 core. The board is BCM91250E > Revision 1. > > The Swarm also uses a Broadcom 1250 with an SB1 > version 0.2 core, but the board is a BCM91250A. > > Most of the difference seems to be in the motherboard, > rather than the CPU, but I couldn't tell you what the > difference is between an E and an A, and why the A > seems better-behaved. There are sub-types to pass 2 but I don't know how to identify those. Probably by the content of the wafer id register or something like that. Ralf From ralf@linux-mips.org Thu Sep 7 04:30:18 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Sep 2006 04:30:20 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:39043 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20027695AbWIGDaS (ORCPT ); Thu, 7 Sep 2006 04:30:18 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k873UpGF025530; Thu, 7 Sep 2006 05:30:51 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k873UosZ025529; Thu, 7 Sep 2006 05:30:50 +0200 Date: Thu, 7 Sep 2006 05:30:50 +0200 From: Ralf Baechle To: Ashlesha Shintre Cc: linux-mips@linux-mips.org Subject: Re: early_initcall Message-ID: <20060907033050.GA17965@linux-mips.org> References: <66910A579C9312469A7DF9ADB54A8B7D366028@exchange.ZeugmaSystems.local> <1157566247.6485.12.camel@sandbar.kenati.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1157566247.6485.12.camel@sandbar.kenati.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12529 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Sep 06, 2006 at 11:10:47AM -0700, Ashlesha Shintre wrote: > I googled early_initcall and found a patch which basically adds this > line to the /include/init.h file: > > #define early_initcall(fn) __define_initcall(".early1",fn) There is more infrastructure needed to get this to work. And in fact why are you trying to get it to work at all - a direct call from setup_arch to your early init function is trivial to do. > I built a kernel image with this new line included and now if I try > executing it, the bootloader YAMON gives an exception error before it > can even begin! Here is the dump: Such a dump could be from YAMON or in the very early phase of the kernel initialization. > A machine check means that an exception is generated due to duplicate > TLB entries. I dont understand why the kernel crashes so early. There are also other implementation specified reasons that may result in a machine check exception as well. > Also, what does the ".early1" mean? Is that a definition of a different > segment in the init.h file? Section not segment. It's just a section name. > I checked output of the "readelf -a vmlinux" and found that the address > for the early_initcall comes up about 5 times. I m not sure what each > of the fields mean, so I have attached the above part of the readelf in > a file called readelf. And if you had not quoted 50 lines of the previous message in this thread but those lines from the readelf output we might actually tell you. Ralf From ralf@linux-mips.org Thu Sep 7 04:53:55 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Sep 2006 04:53:56 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:38845 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20027688AbWIGDxz (ORCPT ); Thu, 7 Sep 2006 04:53:55 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k873sRCx025973; Thu, 7 Sep 2006 05:54:27 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k873sObJ025972; Thu, 7 Sep 2006 05:54:24 +0200 Date: Thu, 7 Sep 2006 05:54:24 +0200 From: Ralf Baechle To: Nida M Cc: "Kevin D. Kissell" , linux-mips@linux-mips.org Subject: Re: single step in MIPS Message-ID: <20060907035424.GB17965@linux-mips.org> References: <000b01c6cea8$7d480fa0$a803a8c0@Ulysses> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12530 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Sep 04, 2006 at 10:27:12AM +0530, Nida M wrote: > Well this is ok ..but I am trying to implement kenel debugger.. > something like system tap. > And I have started with kprobe.. > where the kernel code execution will be stopped at user specified > address using break, how do i single step that instruction to decode > the instruction and print the registers value..? Insert a breakpoint instruction after the instruction you want to single step. Anything that triggers an exception but typicall a "break 0" would be used for debuggers. Branches need special care. Either they need to be executed in software or breakpoints at both the branch-taken and the not-taken address need to be inserted. Just to make this more entertaining, the kernel is a multithreaed piece of software, even if you only have a single processor and you do not necessarily want the singlestepping break point to be taken by each thread / process, so you want to implement some filtering in the exception handler. Executing the instruction that has been replaced with a breakpoint takes an interesting hack as well. Copy that instruction to the stackframe, perform the necessary cacheflushes so the CPU will actually fetch the right instruction. Then jump to that instruction. Obviously that needs to be followed by a jump to the logical next instruction. And with all those hints I leave the special case of instructions in branch delay slots to the you, I'm sure you'll find it trivial ;-) The FPU emulator in the kernel implements this btw. Not for single stepping but for entirely different reasons but you may want to look at it. Ralf From ralf@linux-mips.org Thu Sep 7 05:03:12 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Sep 2006 05:03:16 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:38602 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20037483AbWIGEDM (ORCPT ); Thu, 7 Sep 2006 05:03:12 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k8743jQL026224; Thu, 7 Sep 2006 06:03:45 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k8743j85026223; Thu, 7 Sep 2006 06:03:45 +0200 Date: Thu, 7 Sep 2006 06:03:44 +0200 From: Ralf Baechle To: Erik Niessen Cc: linux-mips@linux-mips.org Subject: Re: Weird output from pmap Message-ID: <20060907040344.GC17965@linux-mips.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12531 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Sep 05, 2006 at 08:55:18AM +0200, Erik Niessen wrote: > /helloworldmips(86) > 00400000 (4 KB) r-xp (00:0a 33243002) linux/test/helloworldmips > 10000000 (4 KB) rw-p (00:0a 33243002) linux/test/helloworldmips > 10001000 (4 KB) rwxp (00:00 0) [heap] > 2aaa8000 (20 KB) r-xp (00:07 1795853) > /lib/ld-uClibc-0.9.27.so > 2aaad000 (4 KB) rw-p (00:00 0) > 2aaed000 (4 KB) rw-p (00:07 1795853) /lib/ld- > uClibc-0.9.27.so > 2aaee000 (48 KB) r-xp (00:07 1795861) /lib/libgcc_s.so.1 > 2aafa000 (252 KB) ---p (00:00 0) > 2ab39000 (4 KB) rw-p (00:07 1795861) /lib/libgcc_s.so.1 > 2ab3a000 (368 KB) r-xp (00:07 1795855) /lib/libuClibc-0.9.27.so > 2ab96000 (256 KB) ---p (00:00 0) > 2abd6000 (8 KB) rw-p (00:07 1795855) /lib/libuClibc- 0.9.27.so > 2abd8000 (16 KB) rw-p (00:00 0) > 7fd49000 (84 KB) rwxp (00:00 0) [stack] > mapped: 1076 KB writable/private: 128 KB shared: 0 KB > > It seems that the bss segments of the shared libs are protected and mapped > to the zero page. I don't see this > when I run this on a linux pc. I have the following questions: > - Why is this segment protected? Accessing results in a seg fault. Protecting a bss segment doesn't make sense. The address and the "---p" flags make me suspect your executable might actually be wrong, so I suggest you check the binary with something like readelf -S. > - Why is it so big (252k/256K)? > - How much memory is physically allocated for this segment? None at this stage - the actuall allocation would happen lazily when a page is touched first which of course doesn't ever happen in your case. Ralf From domen.puncer@telargo.com Thu Sep 7 06:43:12 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Sep 2006 06:43:14 +0100 (BST) Received: from out001.atlarge.net ([129.41.63.69]:54547 "EHLO out001.atlarge.net") by ftp.linux-mips.org with ESMTP id S20037798AbWIGFnM (ORCPT ); Thu, 7 Sep 2006 06:43:12 +0100 Received: from hpmailfe-01.atlarge.net ([10.100.60.156]) by out001.atlarge.net with Microsoft SMTPSVC(6.0.3790.1830); Thu, 7 Sep 2006 00:41:43 -0500 Received: from localhost ([213.250.36.225]) by hpmailfe-01.atlarge.net with Microsoft SMTPSVC(6.0.3790.1830); Thu, 7 Sep 2006 00:41:41 -0500 Date: Thu, 7 Sep 2006 07:43:02 +0200 From: Domen Puncer To: Tomasz Chmielewski Cc: linux-mips@linux-mips.org Subject: Re: no USB device other than storage detected Message-ID: <20060907054302.GF5361@domen.puncer.telargo.com> References: <44FD6CE4.6010001@wpkg.org> <44FF25BE.5020901@wpkg.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <44FF25BE.5020901@wpkg.org> User-Agent: Mutt/1.5.12-2006-07-14 X-OriginalArrivalTime: 07 Sep 2006 05:41:42.0567 (UTC) FILETIME=[4C407370:01C6D240] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12532 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen.puncer@telargo.com Precedence: bulk X-list: linux-mips On 06/09/06 21:47 +0200, Tomasz Chmielewski wrote: > Tomasz Chmielewski wrote: > >I have a tiny router (ASUS WL-500g deluxe, MIPS CPU, 32 MB RAM, 2x > >USB2), and would like to make it work with a USB DSL modem. > > > >Right now, it's running Debian and kernel 2.6.17, and boots off a > >USB-stick. > > > >My problem is, that it only sees USB storage devices (USB sticks etc.). > > > >When I connect other devices (USB modem, webcam, microphone, keyboard, > >printer etc.), they are not detected. > >By "not detected" I mean there are no "dmesg" entries with the device > >name, and no devices, other than "USB storage", listed with "lsusb". > > > >I even compiled "USB verbose logging" in, but it only gives me a couple > >of debug infos, no clue why the devices doesn't show up. > > It looks that something's borked in 2.6.17 kernel. > > When I load ohci module, it complains a lot: You say Ohci, but output is from Uhci, and the output in the first e-mail is from Ehci. :-) Domen > > USB Universal Host Controller Interface driver v3.0 > PCI: Fixing up device 0000:01:02.0 > uhci_hcd 0000:01:02.0: no i/o regions available > uhci_hcd 0000:01:02.0: init 0000:01:02.0 fail, -16 > uhci_hcd: probe of 0000:01:02.0 failed with error -16 > PCI: Fixing up device 0000:01:02.1 > uhci_hcd 0000:01:02.1: no i/o regions available > uhci_hcd 0000:01:02.1: init 0000:01:02.1 fail, -16 > uhci_hcd: probe of 0000:01:02.1 failed with error -16 > > > With 2.4.30 kernel, ohci module loads fine, and I can use all USB devices: > > # lsusb > Bus 002 Device 001: ID 0000:0000 > Bus 001 Device 001: ID 0000:0000 > Bus 001 Device 004: ID 03f0:3011 Hewlett-Packard > Bus 001 Device 003: ID 0471:0310 Philips PCVC730K WebCam [pwc] > > > Ideas what can be wrong? > > > -- > Tomasz Chmielewski > http://wpkg.org From nidajm@gmail.com Thu Sep 7 07:22:16 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Sep 2006 07:22:17 +0100 (BST) Received: from nz-out-0102.google.com ([64.233.162.196]:44842 "EHLO nz-out-0102.google.com") by ftp.linux-mips.org with ESMTP id S20038430AbWIGGWQ (ORCPT ); Thu, 7 Sep 2006 07:22:16 +0100 Received: by nz-out-0102.google.com with SMTP id i1so38622nzh for ; Wed, 06 Sep 2006 23:22:14 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=XeEQlTW7AytXFlzxWHYoxiT1HHluIsR626yxRicuE6tfVT/RfsQ2KWHuwM4b6XrIQvshCYWG2wquTetvn5z++2awh67THvO1Xco/1eba48ez+SQvgp73u8yqPZvNAJnACoxF6mYpICvPWqkudztzE+oaofAf/hUJVpr96u9ZkOM= Received: by 10.65.151.6 with SMTP id d6mr163731qbo; Wed, 06 Sep 2006 23:22:14 -0700 (PDT) Received: by 10.65.126.5 with HTTP; Wed, 6 Sep 2006 23:22:14 -0700 (PDT) Message-ID: Date: Thu, 7 Sep 2006 11:52:14 +0530 From: "Nida M" To: "Ralf Baechle" Subject: Re: single step in MIPS Cc: "Kevin D. Kissell" , linux-mips@linux-mips.org In-Reply-To: <20060907035424.GB17965@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <000b01c6cea8$7d480fa0$a803a8c0@Ulysses> <20060907035424.GB17965@linux-mips.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12533 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nidajm@gmail.com Precedence: bulk X-list: linux-mips > Insert a breakpoint instruction after the instruction you want to single > step. Anything that triggers an exception but typicall a "break 0" would > be used for debuggers. Branches need special care. Either they need to > be executed in software or breakpoints at both the branch-taken and the > not-taken address need to be inserted. Instead of break 0, can I use Trap Exception 'Tr' with the special case for single step BRK_SSTEPBP (break 5) E.g : teq rs,rt,code which is nothing but : bne rs,rt,1f nop break code ....... ??? > And with all those hints I leave the special case of instructions in > branch delay slots to the you, I'm sure you'll find it trivial ;-) Thanks,I think i will do that ~Nida From mangoo@wpkg.org Thu Sep 7 07:53:18 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Sep 2006 07:53:23 +0100 (BST) Received: from mail.syneticon.net ([213.239.212.131]:23009 "EHLO mail2.syneticon.net") by ftp.linux-mips.org with ESMTP id S20038463AbWIGGxS (ORCPT ); Thu, 7 Sep 2006 07:53:18 +0100 Received: from localhost (localhost [127.0.0.1]) by mail2.syneticon.net (Postfix) with ESMTP id BB9294CE9A; Thu, 7 Sep 2006 08:53:12 +0200 (CEST) Received: from mail2.syneticon.net ([127.0.0.1]) by localhost (linux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 11857-03; Thu, 7 Sep 2006 08:53:10 +0200 (CEST) Received: from [192.168.10.145] (xdsl-84-44-195-254.netcologne.de [84.44.195.254]) by mail2.syneticon.net (Postfix) with ESMTP; Thu, 7 Sep 2006 08:53:10 +0200 (CEST) Message-ID: <44FFC1D5.4060604@wpkg.org> Date: Thu, 07 Sep 2006 08:53:09 +0200 From: Tomasz Chmielewski User-Agent: Thunderbird 1.5.0.5 (X11/20060814) MIME-Version: 1.0 To: Domen Puncer Cc: linux-mips@linux-mips.org Subject: Re: no USB device other than storage detected References: <44FD6CE4.6010001@wpkg.org> <44FF25BE.5020901@wpkg.org> <20060907054302.GF5361@domen.puncer.telargo.com> In-Reply-To: <20060907054302.GF5361@domen.puncer.telargo.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Virus-Scanned: amavisd-new at syneticon.de Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12534 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mangoo@wpkg.org Precedence: bulk X-list: linux-mips Domen Puncer wrote: > On 06/09/06 21:47 +0200, Tomasz Chmielewski wrote: >> Tomasz Chmielewski wrote: >>> I have a tiny router (ASUS WL-500g deluxe, MIPS CPU, 32 MB RAM, 2x >>> USB2), and would like to make it work with a USB DSL modem. >>> >>> Right now, it's running Debian and kernel 2.6.17, and boots off a >>> USB-stick. >>> >>> My problem is, that it only sees USB storage devices (USB sticks etc.). >>> >>> When I connect other devices (USB modem, webcam, microphone, keyboard, >>> printer etc.), they are not detected. >>> By "not detected" I mean there are no "dmesg" entries with the device >>> name, and no devices, other than "USB storage", listed with "lsusb". >>> >>> I even compiled "USB verbose logging" in, but it only gives me a couple >>> of debug infos, no clue why the devices doesn't show up. >> It looks that something's borked in 2.6.17 kernel. >> >> When I load ohci module, it complains a lot: > > You say Ohci, but output is from Uhci, and the output in the first > e-mail is from Ehci. :-) Yes, I meant uhci of course (as errors indicate, seen below). ehci works fine. >> USB Universal Host Controller Interface driver v3.0 >> PCI: Fixing up device 0000:01:02.0 >> uhci_hcd 0000:01:02.0: no i/o regions available >> uhci_hcd 0000:01:02.0: init 0000:01:02.0 fail, -16 >> uhci_hcd: probe of 0000:01:02.0 failed with error -16 >> PCI: Fixing up device 0000:01:02.1 >> uhci_hcd 0000:01:02.1: no i/o regions available >> uhci_hcd 0000:01:02.1: init 0000:01:02.1 fail, -16 >> uhci_hcd: probe of 0000:01:02.1 failed with error -16 >> >> >> With 2.4.30 kernel, ohci module loads fine, and I can use all USB devices: >> >> # lsusb >> Bus 002 Device 001: ID 0000:0000 >> Bus 001 Device 001: ID 0000:0000 >> Bus 001 Device 004: ID 03f0:3011 Hewlett-Packard >> Bus 001 Device 003: ID 0471:0310 Philips PCVC730K WebCam [pwc] >> >> >> Ideas what can be wrong? -- Tomasz Chmielewski http://wpkg.org From erik.niessen@gmail.com Thu Sep 7 08:58:21 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Sep 2006 08:58:27 +0100 (BST) Received: from wx-out-0506.google.com ([66.249.82.224]:20243 "EHLO wx-out-0506.google.com") by ftp.linux-mips.org with ESMTP id S20038487AbWIGH6V (ORCPT ); Thu, 7 Sep 2006 08:58:21 +0100 Received: by wx-out-0506.google.com with SMTP id h30so165383wxd for ; Thu, 07 Sep 2006 00:58:20 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:references; b=PYlk3os/spA+hMwT15FXu5npIaW8GxOa5mtHzA8/XAUqpfsXFEhq3pyf+1zfjz/HQND79SV/NUnQY9FCOuAkIYGjfzvCJW/hiptlWWlpe7ryiqCN7XthVAs/yG6ij1zDbmShwoBbRSqGWCcU+FlswXTvz53yFtFuw1N8tYyeAWM= Received: by 10.70.113.15 with SMTP id l15mr120753wxc; Thu, 07 Sep 2006 00:58:20 -0700 (PDT) Received: by 10.70.25.11 with HTTP; Thu, 7 Sep 2006 00:58:20 -0700 (PDT) Message-ID: Date: Thu, 7 Sep 2006 09:58:20 +0200 From: "Erik Niessen" To: "Ralf Baechle" Subject: Re: Weird output from pmap Cc: linux-mips@linux-mips.org In-Reply-To: <20060907040344.GC17965@linux-mips.org> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_167778_26410527.1157615900080" References: <20060907040344.GC17965@linux-mips.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12535 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: erik.niessen@gmail.com Precedence: bulk X-list: linux-mips ------=_Part_167778_26410527.1157615900080 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi Ralf, Thanks for your response. This is the output from readelf mipsel-linux-readelf -S helloworldmips There are 29 section headers, starting at offset 0x1290: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .interp PROGBITS 004000f4 0000f4 000014 00 A 0 0 1 [ 2] .reginfo MIPS_REGINFO 00400108 000108 000018 18 A 0 0 4 [ 3] .dynamic DYNAMIC 00400120 000120 0000f8 08 A 6 0 4 [ 4] .hash HASH 00400218 000218 0000b4 04 A 5 0 4 [ 5] .dynsym DYNSYM 004002cc 0002cc 0001a0 10 A 6 1 4 [ 6] .dynstr STRTAB 0040046c 00046c 00011b 00 A 0 0 1 [ 7] .gnu.version VERSYM 00400588 000588 000034 02 A 5 0 2 [ 8] .gnu.version_r VERNEED 004005bc 0005bc 000020 00 A 6 1 4 [ 9] .init PROGBITS 004005dc 0005dc 000088 00 AX 0 0 4 [10] .text PROGBITS 00400670 000670 0004c0 00 AX 0 0 16 [11] .MIPS.stubs PROGBITS 00400b30 000b30 000070 00 AX 0 0 4 [12] .fini PROGBITS 00400ba0 000ba0 000058 00 AX 0 0 4 [13] .rodata PROGBITS 00400c00 000c00 0000f0 00 A 0 0 16 [14] .eh_frame PROGBITS 00400cf0 000cf0 000004 00 A 0 0 4 [15] .ctors PROGBITS 10000000 001000 000008 00 WA 0 0 4 [16] .dtors PROGBITS 10000008 001008 000008 00 WA 0 0 4 [17] .jcr PROGBITS 10000010 001010 000004 00 WA 0 0 4 [18] .data PROGBITS 10000020 001020 000030 00 WA 0 0 16 [19] .rld_map PROGBITS 10000050 001050 000004 00 WA 0 0 4 [20] .got PROGBITS 10000060 001060 00004c 04 WAp 0 0 16 [21] .sbss NOBITS 100000ac 0010ac 000000 00 WAp 0 0 1 [22] .bss NOBITS 100000b0 0010ac 000020 00 WA 0 0 16 [23] .comment PROGBITS 00000000 0010ac 00005a 00 0 0 1 [24] .pdr PROGBITS 00000000 001108 0000a0 00 0 0 4 [25] .mdebug.abi32 PROGBITS 00000000 0011a8 000000 00 0 0 1 [26] .shstrtab STRTAB 00000000 0011a8 0000e5 00 0 0 1 [27] .symtab SYMTAB 00000000 001718 000500 10 28 51 4 [28] .strtab STRTAB 00000000 001c18 00023f 00 0 0 1 Key to Flags: W (write), A (alloc), X (execute), M (merge), S (strings) I (info), L (link order), G (group), x (unknown) O (extra OS processing required) o (OS specific), p (processor specific) This one tells me that the bss is writable?? Can you giev me a direction where the problem is?? Cheers, On 9/7/06, Ralf Baechle wrote: > > On Tue, Sep 05, 2006 at 08:55:18AM +0200, Erik Niessen wrote: > > > /helloworldmips(86) > > 00400000 (4 KB) r-xp (00:0a 33243002) linux/test/helloworldmips > > 10000000 (4 KB) rw-p (00:0a 33243002) linux/test/helloworldmips > > 10001000 (4 KB) rwxp (00:00 0) [heap] > > 2aaa8000 (20 KB) r-xp (00:07 1795853) > > /lib/ld-uClibc-0.9.27.so > > 2aaad000 (4 KB) rw-p (00:00 0) > > 2aaed000 (4 KB) rw-p (00:07 1795853) /lib/ld- > > uClibc-0.9.27.so > > 2aaee000 (48 KB) r-xp (00:07 1795861) /lib/libgcc_s.so.1 > > 2aafa000 (252 KB) ---p (00:00 0) > > 2ab39000 (4 KB) rw-p (00:07 1795861) /lib/libgcc_s.so.1 > > 2ab3a000 (368 KB) r-xp (00:07 1795855) /lib/libuClibc-0.9.27.so > > 2ab96000 (256 KB) ---p (00:00 0) > > 2abd6000 (8 KB) rw-p (00:07 1795855) /lib/libuClibc- 0.9.27.so > > 2abd8000 (16 KB) rw-p (00:00 0) > > 7fd49000 (84 KB) rwxp (00:00 0) [stack] > > mapped: 1076 KB writable/private: 128 KB shared: 0 KB > > > > It seems that the bss segments of the shared libs are protected and > mapped > > to the zero page. I don't see this > > when I run this on a linux pc. I have the following questions: > > - Why is this segment protected? Accessing results in a seg fault. > > Protecting a bss segment doesn't make sense. > > The address and the "---p" flags make me suspect your executable might > actually be wrong, so I suggest you check the binary with something like > readelf -S. > > > - Why is it so big (252k/256K)? > > - How much memory is physically allocated for this segment? > > None at this stage - the actuall allocation would happen lazily when > a page is touched first which of course doesn't ever happen in your > case. > > Ralf > ------=_Part_167778_26410527.1157615900080 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi Ralf,

Thanks for your response.
This is the output from readelf
 mipsel-linux-readelf -S helloworldmips
There are 29 section headers, starting at offset 0x1290:
 
Section Headers:
  [Nr] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
  [ 0]                   NULL            00000000 000000 000000 00      0   0  0
  [ 1] .interp           PROGBITS        004000f4 0000f4 000014 00   A  0   0  1
  [ 2] .reginfo          MIPS_REGINFO    00400108 000108 000018 18   A  0   0  4
  [ 3] .dynamic          DYNAMIC         00400120 000120 0000f8 08   A  6   0  4
  [ 4] .hash             HASH            00400218 000218 0000b4 04   A  5   0  4
  [ 5] .dynsym           DYNSYM          004002cc 0002cc 0001a0 10   A  6   1  4
  [ 6] .dynstr           STRTAB          0040046c 00046c 00011b 00   A  0   0  1
  [ 7] .gnu.version      VERSYM          00400588 000588 000034 02   A  5   0  2
  [ 8] .gnu.version_r    VERNEED         004005bc 0005bc 000020 00   A  6   1  4
  [ 9] .init             PROGBITS        004005dc 0005dc 000088 00  AX  0   0  4
  [10] .text             PROGBITS        00400670 000670 0004c0 00  AX  0   0 16
  [11] .MIPS.stubs       PROGBITS        00400b30 000b30 000070 00  AX  0   0  4
  [12] .fini             PROGBITS        00400ba0 000ba0 000058 00  AX  0   0  4
  [13] .rodata           PROGBITS        00400c00 000c00 0000f0 00   A  0   0 16
  [14] .eh_frame         PROGBITS        00400cf0 000cf0 000004 00   A  0   0  4
  [15] .ctors            PROGBITS        10000000 001000 000008 00  WA  0   0  4
  [16] .dtors            PROGBITS        10000008 001008 000008 00  WA  0   0  4
  [17] .jcr              PROGBITS        10000010 001010 000004 00  WA  0   0  4
  [18] .data             PROGBITS        10000020 001020 000030 00  WA  0   0 16
  [19] .rld_map          PROGBITS        10000050 001050 000004 00  WA  0   0  4
  [20] .got              PROGBITS        10000060 001060 00004c 04 WAp  0   0 16
  [21] .sbss             NOBITS          100000ac 0010ac 000000 00 WAp  0   0  1
  [22] .bss              NOBITS          100000b0 0010ac 000020 00  WA  0   0 16
  [23] .comment          PROGBITS        00000000 0010ac 00005a 00      0   0  1
  [24] .pdr              PROGBITS        00000000 001108 0000a0 00      0   0  4
  [25] .mdebug.abi32     PROGBITS        00000000 0011a8 000000 00      0   0  1
  [26] .shstrtab         STRTAB          00000000 0011a8 0000e5 00      0   0  1
  [27] .symtab           SYMTAB          00000000 001718 000500 10     28  51  4
  [28] .strtab           STRTAB          00000000 001c18 00023f 00      0   0  1
Key to Flags:
  W (write), A (alloc), X (execute), M (merge), S (strings)
  I (info), L (link order), G (group), x (unknown)
  O (extra OS processing required) o (OS specific), p (processor specific)

This one tells me that the bss is writable?? Can you giev me a direction where the problem is??

Cheers,


On 9/7/06, Ralf Baechle <ralf@linux-mips.org> wrote:
On Tue, Sep 05, 2006 at 08:55:18AM +0200, Erik Niessen wrote:

> /helloworldmips(86)
> 00400000 (4 KB)        r-xp (00:0a 33243002)   linux/test/helloworldmips
> 10000000 (4 KB)        rw-p (00:0a 33243002)   linux/test/helloworldmips
> 10001000 (4 KB)        rwxp (00:00 0)        [heap]
> 2aaa8000 (20 KB)       r-xp (00:07 1795853)
> /lib/ld-uClibc-0.9.27.so< http://uclibc-0.9.27.so/>
> 2aaad000 (4 KB)        rw-p (00:00 0)
> 2aaed000 (4 KB)        rw-p (00:07 1795853)  /lib/ld-
> uClibc-0.9.27.so< http://uclibc-0.9.27.so/>
> 2aaee000 (48 KB)       r-xp (00:07 1795861)  /lib/libgcc_s.so.1
> 2aafa000 (252 KB)      ---p (00:00 0)
> 2ab39000 (4 KB)        rw-p (00:07 1795861)  /lib/libgcc_s.so.1
> 2ab3a000 (368 KB)      r-xp (00:07 1795855)  /lib/libuClibc-0.9.27.so
> 2ab96000 (256 KB)      ---p (00:00 0)
> 2abd6000 (8 KB)        rw-p (00:07 1795855)  /lib/libuClibc- 0.9.27.so
> 2abd8000 (16 KB)       rw-p (00:00 0)
> 7fd49000 (84 KB)       rwxp (00:00 0)        [stack]
> mapped:   1076 KB writable/private: 128 KB shared: 0 KB
>
> It seems that the bss segments of the shared libs are protected and mapped
> to the zero page. I don't see this
> when I run this on a linux pc. I have the following questions:
> - Why is this segment protected? Accessing results in a seg fault.

Protecting a bss segment doesn't make sense.

The address and the "---p" flags make me suspect your executable might
actually be wrong, so I suggest you check the binary with something like
readelf -S.

> - Why is it so big (252k/256K)?
> - How much memory is physically allocated for this segment?

None at this stage - the actuall allocation would happen lazily when
a page is touched first which of course doesn't ever happen in your
case.

  Ralf

------=_Part_167778_26410527.1157615900080-- From langabe@gmail.com Thu Sep 7 12:54:29 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Sep 2006 12:54:31 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.184]:55341 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20038567AbWIGLy3 (ORCPT ); Thu, 7 Sep 2006 12:54:29 +0100 Received: by nf-out-0910.google.com with SMTP id l23so471438nfc for ; Thu, 07 Sep 2006 04:54:26 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=fF5Xv1k3voXa4NjnbHT/O9+qfanOMnW5YSvKoGo9CeztKvUgmi7iFJclF5WVEEVarJ4RMCrXbX3s+o9MFGrMFV4UqVagjn0NVMIG6FNUF2/FxVmcTEonkD8uCFq14ggm1yvTgVtFTVryxyUAZbvpEBD6e/Us8eeuXeIl16qwAlA= Received: by 10.48.220.15 with SMTP id s15mr2400831nfg; Thu, 07 Sep 2006 04:54:26 -0700 (PDT) Received: by 10.49.31.3 with HTTP; Thu, 7 Sep 2006 04:54:26 -0700 (PDT) Message-ID: Date: Thu, 7 Sep 2006 12:54:26 +0100 From: "Alex Gonzalez" To: linux-mips@linux-mips.org Subject: PMC RM9000x2 GL titan (yosemite) multicast address filtering MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12536 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: langabe@gmail.com Precedence: bulk X-list: linux-mips Hi, I am trying to configure the ethernet subsystem to filter out multicast streams selectively, and I am running into some problems. If anyone has done this before, could you try to answer the following questions? 1) For an incoming packet, the chip computes a non-inverted CRC32 calculation over the destination MAC address, and uses the top 6 bits (using the default values of MHASH_INDEX) to hash into the 64bin multicast hash table to decide whether to filter the packet out or not. As an example, if I set the multicast filter to accept packets from 225.10.10.0/255.255.255.252 ( MACs - 008a000a0a00 to 008a000a0a03 ). The port configuration is, AFAFIL1 0xffff0003 multicast 64bin hash filter 4000:0008:0100:0000 (high, mid-high , mid-low , low) With this configuration, the box sees streams like 225.10.10.11, but filters out 225.11.10.1. I would like to make sure that the CRC32 algorithm that the chip is using is the same I'm using. I have tried two different implementations that don't seem to work (in both cases they filter out some multicast streams but not the correct ones). My CRC32 implementation details are: CRC32(123456789) is 2dfd2d88, which is a bytes reversed, non-inverted result, seeded on 0x00000000 and with a polynomial base 0x04c11db7 implementation. CRC32(123456789) is cbf43926, which is a bytes reversed, result inverted, seeded on 0xffffffff and with a polynomial base 0x04c11db7 implementation. Has anybody tried this before? Could this be an endianness problem with my CRC32 calculations (even though they both give the correct checksum over the '123456789' pattern? 2) I will just mention my second problem just in case somebody else has seen it. I have three ethernet ports, eth0, eth1 and eth2, and I use the same code with the correct register offsets to write to the address filtering logic. I can't write any values to eth1, even though it works perfectly for eth0 and eth2. Thanks, Alex From imipak@yahoo.com Thu Sep 7 19:28:59 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Sep 2006 19:29:01 +0100 (BST) Received: from web31514.mail.mud.yahoo.com ([68.142.198.143]:28847 "HELO web31514.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20038620AbWIGS27 (ORCPT ); Thu, 7 Sep 2006 19:28:59 +0100 Received: (qmail 25364 invoked by uid 60001); 7 Sep 2006 18:28:53 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:Cc:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=sgAcF+3XQPGQZPRkzYRJ1QkEYjoDQRd9qJ1UE3/leF90qlex9B1kSHIdRji0IBM0HpIB3s2ozEo3xwd5y0Z5Wv1zcsiGMC3mXBjjlaVoDftrHcm/w9sgIetW2t2TO7dssPhjxtwJE1YFBK/fqX3x2aDpzXlDUiEbmPXbxpFCcYc= ; Message-ID: <20060907182853.25362.qmail@web31514.mail.mud.yahoo.com> Received: from [70.103.67.194] by web31514.mail.mud.yahoo.com via HTTP; Thu, 07 Sep 2006 11:28:53 PDT Date: Thu, 7 Sep 2006 11:28:53 -0700 (PDT) From: Jonathan Day Subject: Re: Resetting a Broadcom in software To: Ralf Baechle Cc: linux-mips@linux-mips.org In-Reply-To: <20060907010324.GA17536@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12537 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips Ok, I have the information... --- Ralf Baechle wrote: > There are sub-types to pass 2 but I don't know how > to identify those. > Probably by the content of the wafer id register or > something like that. Sentosa (which resets on running the program): Wafer ID: 92cee019 Lot 9395 Wafer 23 Mfg Test: Bin A CPU: 1040102 Linux' /proc/cpuinfo says a little more: cpu model : SiByte SB1 V0.2 (lots of uninteresting stuff) ASEs installed : mdmx Swarm (which does not reset on running the program): Wafer ID: 5838e019 Lot 5646 Wafer 7 Mfg Test: Bin A CPU: 1040102 Linux' /proc/cpuinfo: cpu model : SiByte SB1 V0.2 FPU 0.2 (more boring stuff) ASEs installed : mdmx mips3d On an aside, can anyone suggest some good values for Linux' "machine selection" kernel config menu? Well, I guess it's not really an aside as it's just occurred to me that the difference in wafer may require tweaking beyond just setting the system type. Also, if anyone knows of "must set" options elsewhere, I'd appreciate knowing. I know some: 1. Pages are 4K, unless the big page patch is appplied (try saying that three times quickly). 2. The Broadcom tech docs don't document the presence of multi-threading in the CPU, so I'm assuming that has to be off. 3. Most of the profiling options seem to barf in ways that can only be described as spectacular. 4. I don't know which debug options are needed or not needed, but certain apparently random permutations result in a working kernel, others will cause it to explode violently on bootup. Some third-party patches work... ...when the maintainer keeps them up-to-date. Mingo's -rt patches go in clean and seem to run fine, for example, but I'm cautious applying 2.6.17 patches to a 2.6.18-rc6 kernel (the current MIPSified Linux kernel in git). Unfortunately, a lot of the really really good 3rd party patches are for Intel processors only, and I'm reluctant to keep a port in sync, partly for reasons of time but also because I'm not convinced I understand the mechanisms used by the truly exceptional stuff well enough to implement on a platform I'm still figuring out some of the characteristics of. Jonathan __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From kaz@zeugmasystems.com Fri Sep 8 00:25:57 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Sep 2006 00:25:59 +0100 (BST) Received: from mail.zeugmasystems.com ([192.139.122.66]:43220 "EHLO zeugmasystems.com") by ftp.linux-mips.org with ESMTP id S20038667AbWIGXZ5 convert rfc822-to-8bit (ORCPT ); Fri, 8 Sep 2006 00:25:57 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: 64-bit 2.6.17.7 SMP hangs in __cpu_up(). Date: Thu, 7 Sep 2006 16:25:51 -0700 Message-ID: <66910A579C9312469A7DF9ADB54A8B7D390152@exchange.ZeugmaSystems.local> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: 64-bit 2.6.17.7 SMP hangs in __cpu_up(). Thread-Index: AcbS1PVG2vPyjOlUQySm6lGUUHn3SQ== From: "Kaz Kylheku" To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12538 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kaz@zeugmasystems.com Precedence: bulk X-list: linux-mips Anyone seen anything like this? Execution does not get past the loop: while (!cpu_isset(cpu, cpu_callin_map)) udelay(100); The other CPU is not coming up. 32 bit SMP works fine. The board is a relative of the Broadcom BigSur. The processor CPU is the 1280, dual core. From ralf@linux-mips.org Fri Sep 8 11:59:20 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Sep 2006 11:59:22 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:45448 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20037675AbWIHK7U (ORCPT ); Fri, 8 Sep 2006 11:59:20 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k88Axsm0021219; Fri, 8 Sep 2006 12:59:54 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k88Axrj7021218; Fri, 8 Sep 2006 12:59:53 +0200 Date: Fri, 8 Sep 2006 12:59:53 +0200 From: Ralf Baechle To: Kaz Kylheku Cc: linux-mips@linux-mips.org Subject: Re: 64-bit 2.6.17.7 SMP hangs in __cpu_up(). Message-ID: <20060908105953.GA1555@linux-mips.org> References: <66910A579C9312469A7DF9ADB54A8B7D390152@exchange.ZeugmaSystems.local> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <66910A579C9312469A7DF9ADB54A8B7D390152@exchange.ZeugmaSystems.local> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12539 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Sep 07, 2006 at 04:25:51PM -0700, Kaz Kylheku wrote: > Anyone seen anything like this? > > Execution does not get past the loop: > > while (!cpu_isset(cpu, cpu_callin_map)) > udelay(100); > > The other CPU is not coming up. > > 32 bit SMP works fine. Interesting because the 64-bit kernel is considered bettere tested on Sibyte chips than 32-bit these days. Not a problem I was aware of. Ralf From nigel@mips.com Fri Sep 8 18:39:42 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Sep 2006 18:39:44 +0100 (BST) Received: from dmz.mips-uk.com ([194.74.144.194]:29712 "EHLO dmz.mips-uk.com") by ftp.linux-mips.org with ESMTP id S20037816AbWIHRjm (ORCPT ); Fri, 8 Sep 2006 18:39:42 +0100 Received: from dmzgw.mips-uk.com ([194.74.144.193] helo=ukservices1.mips.com) by dmz.mips-uk.com with esmtp (Exim 3.35 #1 (Debian)) id 1GLkKF-0001L6-00; Fri, 08 Sep 2006 18:39:35 +0100 Received: from highbury.mips.com ([192.168.192.236]) by ukservices1.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1GLkJp-0007KS-00; Fri, 08 Sep 2006 18:39:09 +0100 Message-ID: <4501AABC.1050009@mips.com> Date: Fri, 08 Sep 2006 18:39:08 +0100 From: Nigel Stephens Organization: MIPS Technologies User-Agent: Thunderbird 1.5.0.2 (X11/20060501) MIME-Version: 1.0 To: Atsushi Nemoto , ralf@linux-mips.org CC: dan@debian.org, macro@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS References: <20060710.235553.48797818.anemo@mba.ocn.ne.jp> <20060711025342.GA6898@nevyn.them.org> <20060711.122014.52129937.nemoto@toshiba-tops.co.jp> In-Reply-To: <20060711.122014.52129937.nemoto@toshiba-tops.co.jp> X-Enigmail-Version: 0.94.0.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-MIPS-Technologies-UK-MailScanner: Found to be clean X-MIPS-Technologies-UK-MailScanner-From: nigel@mips.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12540 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nigel@mips.com Precedence: bulk X-list: linux-mips moto wrote: > >> BTW, if the fast emulation can't handle rdhwr in a delay slot, please >> report a bug on GCC asking it not to put rdhwr in delay slots by >> default. It's probably worthwhile. >> > > If rdhwr was on a delay slot, the slow emulation will be more slower. > So I think rdhwr should not be put on delay slot anyway regardless > fast emulation. > > I asked on GCC bugzilla a few days ago but can not got feedback yet. > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=28126 > In spite of the GCC issue, is this patch now at the point where it could be applied, or at least queued? Nigel From anemo@mba.ocn.ne.jp Sat Sep 9 14:54:51 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Sep 2006 14:54:53 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:60637 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20038415AbWIINyv (ORCPT ); Sat, 9 Sep 2006 14:54:51 +0100 Received: from localhost (p6097-ipad210funabasi.chiba.ocn.ne.jp [58.88.125.97]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 24B79A8E8; Sat, 9 Sep 2006 22:54:45 +0900 (JST) Date: Sat, 09 Sep 2006 22:56:41 +0900 (JST) Message-Id: <20060909.225641.41198763.anemo@mba.ocn.ne.jp> To: nigel@mips.com Cc: ralf@linux-mips.org, dan@debian.org, macro@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS From: Atsushi Nemoto In-Reply-To: <4501AABC.1050009@mips.com> References: <20060711025342.GA6898@nevyn.them.org> <20060711.122014.52129937.nemoto@toshiba-tops.co.jp> <4501AABC.1050009@mips.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12541 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Fri, 08 Sep 2006 18:39:08 +0100, Nigel Stephens wrote: > > I asked on GCC bugzilla a few days ago but can not got feedback yet. > > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=28126 > > > > In spite of the GCC issue, is this patch now at the point where it could > be applied, or at least queued? GCC 4.2 does not put RDHWR in delay slot now. Also, there is a "hackish fix" to prevent gcc move a RDHWR outside of a conditional (from Richard Sandiford). For kernel side, my patch can be still applied to current git tree as is. But I'm still looking for better solution (silver bullet?) for cpu_has_vtag_icache case. How about something like this (and do not touch tlbex.c)? LEAF(handle_ri_rdhwr_vivt) .set push .set noat .set noreorder /* check if TLB contains a entry for EPC */ MFC0 K1, CP0_ENTRYHI andi k1, ASID_MASK MFC0 k0, CP0_EPC andi k0, PAGE_MASK << 1 or k1, k0 MTC0 k1, CP0_ENTRYHI tlbp mfc0 k1, CP0_INDEX bltz k1, handle_ri /* slow path */ nop /* fall thru */ LEAF(handle_ri_rdhwr) I'm wondering if this could work on CONFIG_MIPS_MT_SMTC case... --- Atsushi Nemoto From anemo@mba.ocn.ne.jp Sat Sep 9 15:42:17 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Sep 2006 15:42:19 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:27597 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20038436AbWIIOmR (ORCPT ); Sat, 9 Sep 2006 15:42:17 +0100 Received: from localhost (p6097-ipad210funabasi.chiba.ocn.ne.jp [58.88.125.97]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id E630DB258; Sat, 9 Sep 2006 23:42:12 +0900 (JST) Date: Sat, 09 Sep 2006 23:44:10 +0900 (JST) Message-Id: <20060909.234410.08076589.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] fix errors detected by "make headers_check" From: Atsushi Nemoto In-Reply-To: <20060907.010022.126141861.anemo@mba.ocn.ne.jp> References: <20060907.010022.126141861.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12542 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Thu, 07 Sep 2006 01:00:22 +0900 (JST), Atsushi Nemoto wrote: > * export asm/sgidefs.h > * include asm/isadep.h only if in kernel > * do not export contents of asm/timex.h and asm/user.h > > Signed-off-by: Atsushi Nemoto > > Kbuild | 2 ++ > ptrace.h | 3 +-- > timex.h | 4 ++++ > user.h | 4 ++++ > 4 files changed, 11 insertions(+), 2 deletions(-) David Woodhouse posted a patch titled "[PATCH] [2/6] Remove from user export" to LKML today. If his patch was applied, the timex.h part of my patch can be reverted. --- Atsushi Nemoto From sshtylyov@ru.mvista.com Sat Sep 9 17:32:40 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Sep 2006 17:32:41 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:57593 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20038437AbWIIQck (ORCPT ); Sat, 9 Sep 2006 17:32:40 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 46C5D3F61; Sat, 9 Sep 2006 09:32:13 -0700 (PDT) Message-ID: <4502ED14.6080506@ru.mvista.com> Date: Sat, 09 Sep 2006 20:34:28 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Ralf Baechle Cc: Rodolfo Giometti , linux-mips@linux-mips.org, rmk@arm.linux.org.uk Subject: Re: [PATCH] au1x00 serial real interrupt References: <20060522165244.GA16223@enneenne.com> <44FD9587.3030708@ru.mvista.com> In-Reply-To: <44FD9587.3030708@ru.mvista.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12543 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Sergei Shtylyov wrote: >> ------------------------------------------------------------------------ >> >> diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h >> index 7b23664..0197062 100644 >> --- a/include/asm-mips/serial.h >> +++ b/include/asm-mips/serial.h >> @@ -11,6 +11,14 @@ >> >> #include >> >> +#ifdef CONFIG_SOC_AU1X00 >> +/* >> + * We have to redefine "is_real_interrupt()" for Au1x00 CPUs... >> + */ >> +#undef is_real_interrupt >> +#define is_real_interrupt(irq) ((irq) != ~0) >> +#endif >> + >> /* >> * This assumes you have a 1.8432 MHz clock for your UART. >> * > Ralf, how about this patch? Can it be applied, at least 3 months > after posting? Alchemy UART0 uses IRQ0 and 0 is treated as "no IRQ" by > drivers/serial/8250.c which says the macro should be redefined in > if needed. If the values other than 0 need to be filtered out, to be precise... Well, after looking at drivers/serial/8250.c a bit more, I think this may be even more simlified since that driver seems to treat the negative values as completely invalid anyway. IOW, we can just: #define is_real_interrupt(irq) 1 Russel, what do you think? WBR, Sergei From rmk+linux-mips=linux-mips.org@arm.linux.org.uk Sat Sep 9 17:39:21 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Sep 2006 17:39:24 +0100 (BST) Received: from caramon.arm.linux.org.uk ([217.147.92.249]:11533 "EHLO caramon.arm.linux.org.uk") by ftp.linux-mips.org with ESMTP id S20038481AbWIIQjV (ORCPT ); Sat, 9 Sep 2006 17:39:21 +0100 Received: from flint.arm.linux.org.uk ([2002:d993:5cf9:1:201:2ff:fe14:8fad]) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:DES-CBC3-SHA:168) (Exim 4.52) id 1GM5rK-0004Bi-3f; Sat, 09 Sep 2006 17:39:10 +0100 Received: from rmk by flint.arm.linux.org.uk with local (Exim 4.52) id 1GM5rI-0006l5-2f; Sat, 09 Sep 2006 17:39:08 +0100 Date: Sat, 9 Sep 2006 17:39:07 +0100 From: Russell King To: Sergei Shtylyov Cc: Ralf Baechle , Rodolfo Giometti , linux-mips@linux-mips.org Subject: Re: [PATCH] au1x00 serial real interrupt Message-ID: <20060909163907.GA24012@flint.arm.linux.org.uk> References: <20060522165244.GA16223@enneenne.com> <44FD9587.3030708@ru.mvista.com> <4502ED14.6080506@ru.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4502ED14.6080506@ru.mvista.com> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12544 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmk@arm.linux.org.uk Precedence: bulk X-list: linux-mips On Sat, Sep 09, 2006 at 08:34:28PM +0400, Sergei Shtylyov wrote: > Well, after looking at drivers/serial/8250.c a bit more, I think this > may be even more simlified since that driver seems to treat the negative > values as completely invalid anyway. IOW, we can just: > > #define is_real_interrupt(irq) 1 > > Russel, what do you think? That's Russell 8) Well, if you need IRQ0 to be real then redefining is_real_interrupt() is the correct way forward. However, Linus' policy is that IRQ0 shall be invalid at least on PCI systems, and architectures _should_ remap their real IRQ0 to some other number. Personally I don't like this. Hence why I prefer to give people the option. -- Russell King Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/ maintainer of: 2.6 Serial core From sshtylyov@ru.mvista.com Sat Sep 9 17:56:35 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Sep 2006 17:56:37 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:9466 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20038492AbWIIQ4f (ORCPT ); Sat, 9 Sep 2006 17:56:35 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 20DBF3F61; Sat, 9 Sep 2006 09:56:30 -0700 (PDT) Message-ID: <4502F2C8.9020107@ru.mvista.com> Date: Sat, 09 Sep 2006 20:58:48 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Russell King Cc: Sergei Shtylyov , Ralf Baechle , Rodolfo Giometti , linux-mips@linux-mips.org Subject: Re: [PATCH] au1x00 serial real interrupt References: <20060522165244.GA16223@enneenne.com> <44FD9587.3030708@ru.mvista.com> <4502ED14.6080506@ru.mvista.com> <20060909163907.GA24012@flint.arm.linux.org.uk> In-Reply-To: <20060909163907.GA24012@flint.arm.linux.org.uk> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12545 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Russell King wrote: >> Well, after looking at drivers/serial/8250.c a bit more, I think this >> may be even more simlified since that driver seems to treat the negative >>values as completely invalid anyway. IOW, we can just: >>#define is_real_interrupt(irq) 1 >> Russel, what do you think? > That's Russell 8) I'm sorry. :-) > Well, if you need IRQ0 to be real then redefining is_real_interrupt() > is the correct way forward. > However, Linus' policy is that IRQ0 shall be invalid at least on PCI > systems, and architectures _should_ remap their real IRQ0 to some other > number. Hm, given that NO_IRQ is #defined as -1 (when it's defined at all)... > Personally I don't like this. Hm, me neither but I can undestand the reasoning. 0 is the usual default value of the PCI interrupt line register, meaning interrupt is unassigned. > Hence why I prefer to give people the option. Thanks for the explanation. Would be better probably to have that #define in 8250.c going after #include but as this seems the first and only case of the override needed, it's good enough this way. :-) As for the PCI UARTs possibly plugged into Alchemy board, I really don't know... This macro has no provision to check for the UART type. So, skipping its invocation in 8250.c for UPIO_AU case might be a better (though not cleaner) solution... WBR, Sergei From sshtylyov@ru.mvista.com Sat Sep 9 18:17:23 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Sep 2006 18:17:25 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:35834 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20038495AbWIIRRX (ORCPT ); Sat, 9 Sep 2006 18:17:23 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id C17083F61; Sat, 9 Sep 2006 10:17:20 -0700 (PDT) Message-ID: <4502F7A9.3080301@ru.mvista.com> Date: Sat, 09 Sep 2006 21:19:37 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Thomas Koeller Cc: rmk@arm.linux.org.uk, linux-serial@vger.kernel.org, linux-mips@linux-mips.org, =?ISO-8859-1?Q?Thomas_K=F6ller?= Subject: Re: [PATCH] RM9000 serial driver References: <200608102318.52143.thomas.koeller@baslerweb.com> <200608260038.13662.thomas.koeller@baslerweb.com> <44F441F3.8050301@ru.mvista.com> <200608300100.32836.thomas.koeller@baslerweb.com> <44F5911D.8020807@ru.mvista.com> In-Reply-To: <44F5911D.8020807@ru.mvista.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12546 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello, I wrote: >>>> @@ -289,6 +296,36 @@ static inline int map_8250_out_reg(struc >>>> return au_io_out_map[offset]; >>>> } >>>> >>>> +#elif defined (CONFIG_SERIAL_8250_RM9K) >>>> + >>>> +static const u8 >>>> + regmap_in[8] = { >>>> + [UART_RX] = 0x00, >>>> + [UART_IER] = 0x0c, >>>> + [UART_IIR] = 0x14, >>>> + [UART_LCR] = 0x1c, >>>> + [UART_MCR] = 0x20, >>>> + [UART_LSR] = 0x24, >>>> + [UART_MSR] = 0x28, >>>> + [UART_SCR] = 0x2c >>>> + }, >>>> + regmap_out[8] = { >>>> + [UART_TX] = 0x04, >>>> + [UART_IER] = 0x0c, >>>> + [UART_FCR] = 0x18, >>>> + [UART_LCR] = 0x1c, >>>> + [UART_MCR] = 0x20, >>>> + [UART_LSR] = 0x24, >>>> + [UART_MSR] = 0x28, >>>> + [UART_SCR] = 0x2c >>>> + }; >>> I guess you're using regshift == 0? >> Yes. > Well, regshift of 2 seems more fitting for the 32-bit registers. This > is not principal but using 0 regshift don't actually buy anything -- the > shift will be perfomed anyway. Not only that -- look at serial8250_request_std_resources(). Withouth the proper regshift of 2 it won't be able to correctly calculate UART decoded memory range size. So, 0 simply doesn't fit. >> implementations, and hence every code to support a nonstandard device >> must define an >> iotype of its own, even though one of the existing iotypes would work >> just fine? In my > UPIO_MEM32 doesn't actually cover your case as it corresponds to the > UART with the > fully 8250-compatible register set, just having 32-bit registers instead > of the usual > 8-bit ones. RM9000 is clearly not fully compatible to 8250 in regard to > the register > addresses since it has RX/TX regs, FCR and the divisor latch mapped to > the separate > addresses, just like Alchemy UART. And I stressed that it's the main > issue with this > UART's compatibility to 8250 in my first followup. Further on, even if the regshift is correct it (being used as 8 << regshift) still won't give you the correct resource size since as I just said, the UART is not 8250-compatible and has more than 8 32-bit registers. So we end up with the need to modify serial8250_request_std_resources() and serial8250_release_std_resources(). >> Thomas WBR, Sergei From ralf@linux-mips.org Sun Sep 10 01:17:30 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Sep 2006 01:17:31 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:53456 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20037517AbWIJARa (ORCPT ); Sun, 10 Sep 2006 01:17:30 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k8A0I4Pe000899; Sun, 10 Sep 2006 02:18:04 +0200 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k8A0I31c000898; Sun, 10 Sep 2006 02:18:03 +0200 Date: Sun, 10 Sep 2006 02:18:03 +0200 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Subject: Re: cpu_idle and cpu_wait Message-ID: <20060910001803.GA826@linux-mips.org> References: <20051117.011906.25910026.anemo@mba.ocn.ne.jp> <20051116184201.GJ3229@linux-mips.org> <20051118.122242.07017522.nemoto@toshiba-tops.co.jp> <20060608.010901.108121387.anemo@mba.ocn.ne.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060608.010901.108121387.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12547 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jun 08, 2006 at 01:09:01AM +0900, Atsushi Nemoto wrote: > [MIPS] reduce race between cpu_wait() and need_resched() checking > > If a thread became runnable between need_resched() and the WAIT > instruction, switching to the thread will delay until a next interrupt. > Some CPUs can execute the WAIT instruction with interrupt disabled, so > we can get rid of this race on them (at least UP case). Applied but based on feedback from the 4K and 5K CPU designers I modified your patch to continue using the old code. Ralf From anemo@mba.ocn.ne.jp Sun Sep 10 13:50:58 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Sep 2006 13:51:02 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:52695 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20037888AbWIJMu6 (ORCPT ); Sun, 10 Sep 2006 13:50:58 +0100 Received: from localhost (p1239-ipad27funabasi.chiba.ocn.ne.jp [220.107.192.239]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 2ABDF94CA; Sun, 10 Sep 2006 21:50:54 +0900 (JST) Date: Sun, 10 Sep 2006 21:52:52 +0900 (JST) Message-Id: <20060910.215252.108307097.anemo@mba.ocn.ne.jp> To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: Re: cpu_idle and cpu_wait From: Atsushi Nemoto In-Reply-To: <20060910001803.GA826@linux-mips.org> References: <20051118.122242.07017522.nemoto@toshiba-tops.co.jp> <20060608.010901.108121387.anemo@mba.ocn.ne.jp> <20060910001803.GA826@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12548 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sun, 10 Sep 2006 02:18:03 +0200, Ralf Baechle wrote: > Applied but based on feedback from the 4K and 5K CPU designers I modified > your patch to continue using the old code. Thanks! IIRC MIPS4K? and MIPS5Kc datasheets state that any masked interrupts can break WAIT instruction, but I could not test by myself since I do not have any of them. I believe feedback from CPU designers of course :-) --- Atsushi Nemoto From nigel@mips.com Sun Sep 10 23:30:45 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Sep 2006 23:30:47 +0100 (BST) Received: from dmz.mips-uk.com ([194.74.144.194]:48392 "EHLO dmz.mips-uk.com") by ftp.linux-mips.org with ESMTP id S20037666AbWIJWap (ORCPT ); Sun, 10 Sep 2006 23:30:45 +0100 Received: from dmzgw.mips-uk.com ([194.74.144.193] helo=ukservices1.mips.com) by dmz.mips-uk.com with esmtp (Exim 3.35 #1 (Debian)) id 1GMXox-0000qP-00; Sun, 10 Sep 2006 23:30:35 +0100 Received: from bank.mips.com ([192.168.192.132] helo=[127.0.0.1]) by ukservices1.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1GMXob-0002Kw-00; Sun, 10 Sep 2006 23:30:13 +0100 Message-ID: <450491FA.3010600@mips.com> Date: Sun, 10 Sep 2006 23:30:18 +0100 From: Nigel Stephens Organization: MIPS Technologies Inc User-Agent: Thunderbird 1.5.0.5 (Windows/20060719) MIME-Version: 1.0 To: Atsushi Nemoto CC: ralf@linux-mips.org, dan@debian.org, macro@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS References: <20060711025342.GA6898@nevyn.them.org> <20060711.122014.52129937.nemoto@toshiba-tops.co.jp> <4501AABC.1050009@mips.com> <20060909.225641.41198763.anemo@mba.ocn.ne.jp> In-Reply-To: <20060909.225641.41198763.anemo@mba.ocn.ne.jp> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-MIPS-Technologies-UK-MailScanner: Found to be clean X-MIPS-Technologies-UK-MailScanner-From: nigel@mips.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12549 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nigel@mips.com Precedence: bulk X-list: linux-mips Atsushi Nemoto wrote: > On Fri, 08 Sep 2006 18:39:08 +0100, Nigel Stephens wrote: > >>> I asked on GCC bugzilla a few days ago but can not got feedback yet. >>> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=28126 >>> >>> >> In spite of the GCC issue, is this patch now at the point where it could >> be applied, or at least queued? >> > > GCC 4.2 does not put RDHWR in delay slot now. Also, there is a > "hackish fix" to prevent gcc move a RDHWR outside of a conditional > (from Richard Sandiford). > > For kernel side, my patch can be still applied to current git tree as > is. > > But I'm still looking for better solution (silver bullet?) for > cpu_has_vtag_icache case. > > How about something like this (and do not touch tlbex.c)? > > LEAF(handle_ri_rdhwr_vivt) > .set push > .set noat > .set noreorder > /* check if TLB contains a entry for EPC */ > MFC0 K1, CP0_ENTRYHI > andi k1, ASID_MASK > MFC0 k0, CP0_EPC > andi k0, PAGE_MASK << 1 > or k1, k0 > MTC0 k1, CP0_ENTRYHI > tlbp > mfc0 k1, CP0_INDEX > bltz k1, handle_ri /* slow path */ > nop > /* fall thru */ > LEAF(handle_ri_rdhwr) > > I'm wondering if this could work on CONFIG_MIPS_MT_SMTC case... > > No, that wouldn't be reliable for CONFIG_MIPS_MT_SMTC, but then again the only CPU which currently runs SMTC has VIPT caches Nigel From anemo@mba.ocn.ne.jp Mon Sep 11 06:04:14 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 06:04:17 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:19073 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20037821AbWIKFEO (ORCPT ); Mon, 11 Sep 2006 06:04:14 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Mon, 11 Sep 2006 14:04:13 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 0A09220598; Mon, 11 Sep 2006 14:04:04 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id EB12C20595; Mon, 11 Sep 2006 14:04:03 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k8B543W0097421; Mon, 11 Sep 2006 14:04:03 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Mon, 11 Sep 2006 14:04:03 +0900 (JST) Message-Id: <20060911.140403.126141483.nemoto@toshiba-tops.co.jp> To: nigel@mips.com Cc: ralf@linux-mips.org, dan@debian.org, macro@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS From: Atsushi Nemoto In-Reply-To: <450491FA.3010600@mips.com> References: <4501AABC.1050009@mips.com> <20060909.225641.41198763.anemo@mba.ocn.ne.jp> <450491FA.3010600@mips.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12550 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sun, 10 Sep 2006 23:30:18 +0100, Nigel Stephens wrote: > > LEAF(handle_ri_rdhwr_vivt) ... > > > > I'm wondering if this could work on CONFIG_MIPS_MT_SMTC case... > > No, that wouldn't be reliable for CONFIG_MIPS_MT_SMTC, but then again > the only CPU which currently runs SMTC has VIPT caches Then this woule be better then "take 2" patch? This add some overhead to fast RDHWR emulation path but no overhead to TLB refill path. The tlb_probe_hazard is not exist in main branch for now but already exist in queue branch. Take 3. Comments (especially from pipeline wizards) are welcome. Add special short path for emulationg RDHWR which is used to support TLS. Add an extra prologue for cpu_has_vtag_icache case. Signed-off-by: Atsushi Nemoto diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 37fda3d..55e090e 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -19,6 +19,7 @@ #include #include #include #include +#include #define PANIC_PIC(msg) \ .set push; \ @@ -375,6 +376,72 @@ #endif BUILD_HANDLER dsp dsp sti silent /* #26 */ BUILD_HANDLER reserved reserved sti verbose /* others */ + .align 5 + LEAF(handle_ri_rdhwr_vivt) +#ifdef CONFIG_MIPS_MT_SMTC + PANIC_PIC("handle_ri_rdhwr_vivt called") +#else + .set push + .set noat + .set noreorder + /* check if TLB contains a entry for EPC */ + MFC0 k1, CP0_ENTRYHI + andi k1, 0xff /* ASID_MASK */ + MFC0 k0, CP0_EPC + PTR_SRL k0, PAGE_SHIFT + 1 + PTR_SLL k0, PAGE_SHIFT + 1 + or k1, k0 + MTC0 k1, CP0_ENTRYHI + mtc0_tlbw_hazard + tlbp +#ifdef CONFIG_CPU_MIPSR2 + _ehb /* tlb_probe_hazard */ +#else + nop; nop; nop; nop; nop; nop /* tlb_probe_hazard */ +#endif + mfc0 k1, CP0_INDEX + .set pop + bltz k1, handle_ri /* slow path */ + /* fall thru */ +#endif + END(handle_ri_rdhwr_vivt) + + LEAF(handle_ri_rdhwr) + .set push + .set noat + .set noreorder + /* 0x7c03e83b: rdhwr v1,$29 */ + MFC0 k1, CP0_EPC + lui k0, 0x7c03 + lw k1, (k1) + ori k0, 0xe83b + .set reorder + bne k0, k1, handle_ri /* if not ours */ + /* The insn is rdhwr. No need to check CAUSE.BD here. */ + get_saved_sp /* k1 := current_thread_info */ + .set noreorder + MFC0 k0, CP0_EPC +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + ori k1, _THREAD_MASK + xori k1, _THREAD_MASK + LONG_L v1, TI_TP_VALUE(k1) + LONG_ADDIU k0, 4 + jr k0 + rfe +#else + LONG_ADDIU k0, 4 /* stall on $k0 */ + MTC0 k0, CP0_EPC + /* I hope three instructions between MTC0 and ERET are enough... */ + ori k1, _THREAD_MASK + xori k1, _THREAD_MASK + LONG_L v1, TI_TP_VALUE(k1) + .set mips3 + eret + .set mips0 +#endif + .set pop + END(handle_ri_rdhwr) + #ifdef CONFIG_64BIT /* A temporary overflow handler used by check_daddi(). */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e51d8fd..7ae454a 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -53,6 +53,8 @@ extern asmlinkage void handle_dbe(void); extern asmlinkage void handle_sys(void); extern asmlinkage void handle_bp(void); extern asmlinkage void handle_ri(void); +extern asmlinkage void handle_ri_rdhwr_vivt(void); +extern asmlinkage void handle_ri_rdhwr(void); extern asmlinkage void handle_cpu(void); extern asmlinkage void handle_ov(void); extern asmlinkage void handle_tr(void); @@ -1453,6 +1455,15 @@ #endif memcpy((void *)(uncached_ebase + offset), addr, size); } +int __initdata rdhwr_noopt; +static int __init set_rdhwr_noopt(char *str) +{ + rdhwr_noopt = 1; + return 1; +} + +__setup("rdhwr_noopt", set_rdhwr_noopt); + void __init trap_init(void) { extern char except_vec3_generic, except_vec3_r4000; @@ -1532,7 +1543,9 @@ void __init trap_init(void) set_except_vector(8, handle_sys); set_except_vector(9, handle_bp); - set_except_vector(10, handle_ri); + set_except_vector(10, rdhwr_noopt ? handle_ri : + (cpu_has_vtag_icache ? + handle_ri_rdhwr_vivt : handle_ri_rdhwr)); set_except_vector(11, handle_cpu); set_except_vector(12, handle_ov); set_except_vector(13, handle_tr); From anemo@mba.ocn.ne.jp Mon Sep 11 09:50:39 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 09:50:41 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:52988 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20037486AbWIKIuj (ORCPT ); Mon, 11 Sep 2006 09:50:39 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Mon, 11 Sep 2006 17:50:37 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 997A720510; Mon, 11 Sep 2006 17:50:32 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 843A12050F; Mon, 11 Sep 2006 17:50:32 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k8B8oTW0098198; Mon, 11 Sep 2006 17:50:29 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Mon, 11 Sep 2006 17:50:29 +0900 (JST) Message-Id: <20060911.175029.37531637.nemoto@toshiba-tops.co.jp> To: nigel@mips.com Cc: ralf@linux-mips.org, dan@debian.org, macro@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS From: Atsushi Nemoto In-Reply-To: <20060911.140403.126141483.nemoto@toshiba-tops.co.jp> References: <20060909.225641.41198763.anemo@mba.ocn.ne.jp> <450491FA.3010600@mips.com> <20060911.140403.126141483.nemoto@toshiba-tops.co.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12551 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Mon, 11 Sep 2006 14:04:03 +0900 (JST), Atsushi Nemoto wrote: > Then this woule be better then "take 2" patch? This add some overhead > to fast RDHWR emulation path but no overhead to TLB refill path. > > The tlb_probe_hazard is not exist in main branch for now but already > exist in queue branch. > > > Take 3. Comments (especially from pipeline wizards) are welcome. Oops, "rdhwr_noopt" should be static in this take. Revised. Take 3(revised). Add special short path for emulationg RDHWR which is used to support TLS. Add an extra prologue for cpu_has_vtag_icache case. Signed-off-by: Atsushi Nemoto diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 37fda3d..55e090e 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -19,6 +19,7 @@ #include #include #include #include +#include #define PANIC_PIC(msg) \ .set push; \ @@ -375,6 +376,72 @@ #endif BUILD_HANDLER dsp dsp sti silent /* #26 */ BUILD_HANDLER reserved reserved sti verbose /* others */ + .align 5 + LEAF(handle_ri_rdhwr_vivt) +#ifdef CONFIG_MIPS_MT_SMTC + PANIC_PIC("handle_ri_rdhwr_vivt called") +#else + .set push + .set noat + .set noreorder + /* check if TLB contains a entry for EPC */ + MFC0 k1, CP0_ENTRYHI + andi k1, 0xff /* ASID_MASK */ + MFC0 k0, CP0_EPC + PTR_SRL k0, PAGE_SHIFT + 1 + PTR_SLL k0, PAGE_SHIFT + 1 + or k1, k0 + MTC0 k1, CP0_ENTRYHI + mtc0_tlbw_hazard + tlbp +#ifdef CONFIG_CPU_MIPSR2 + _ehb /* tlb_probe_hazard */ +#else + nop; nop; nop; nop; nop; nop /* tlb_probe_hazard */ +#endif + mfc0 k1, CP0_INDEX + .set pop + bltz k1, handle_ri /* slow path */ + /* fall thru */ +#endif + END(handle_ri_rdhwr_vivt) + + LEAF(handle_ri_rdhwr) + .set push + .set noat + .set noreorder + /* 0x7c03e83b: rdhwr v1,$29 */ + MFC0 k1, CP0_EPC + lui k0, 0x7c03 + lw k1, (k1) + ori k0, 0xe83b + .set reorder + bne k0, k1, handle_ri /* if not ours */ + /* The insn is rdhwr. No need to check CAUSE.BD here. */ + get_saved_sp /* k1 := current_thread_info */ + .set noreorder + MFC0 k0, CP0_EPC +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + ori k1, _THREAD_MASK + xori k1, _THREAD_MASK + LONG_L v1, TI_TP_VALUE(k1) + LONG_ADDIU k0, 4 + jr k0 + rfe +#else + LONG_ADDIU k0, 4 /* stall on $k0 */ + MTC0 k0, CP0_EPC + /* I hope three instructions between MTC0 and ERET are enough... */ + ori k1, _THREAD_MASK + xori k1, _THREAD_MASK + LONG_L v1, TI_TP_VALUE(k1) + .set mips3 + eret + .set mips0 +#endif + .set pop + END(handle_ri_rdhwr) + #ifdef CONFIG_64BIT /* A temporary overflow handler used by check_daddi(). */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e51d8fd..e56b02f 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -53,6 +53,8 @@ extern asmlinkage void handle_dbe(void); extern asmlinkage void handle_sys(void); extern asmlinkage void handle_bp(void); extern asmlinkage void handle_ri(void); +extern asmlinkage void handle_ri_rdhwr_vivt(void); +extern asmlinkage void handle_ri_rdhwr(void); extern asmlinkage void handle_cpu(void); extern asmlinkage void handle_ov(void); extern asmlinkage void handle_tr(void); @@ -1453,6 +1455,15 @@ #endif memcpy((void *)(uncached_ebase + offset), addr, size); } +static int __initdata rdhwr_noopt; +static int __init set_rdhwr_noopt(char *str) +{ + rdhwr_noopt = 1; + return 1; +} + +__setup("rdhwr_noopt", set_rdhwr_noopt); + void __init trap_init(void) { extern char except_vec3_generic, except_vec3_r4000; @@ -1532,7 +1543,9 @@ void __init trap_init(void) set_except_vector(8, handle_sys); set_except_vector(9, handle_bp); - set_except_vector(10, handle_ri); + set_except_vector(10, rdhwr_noopt ? handle_ri : + (cpu_has_vtag_icache ? + handle_ri_rdhwr_vivt : handle_ri_rdhwr)); set_except_vector(11, handle_cpu); set_except_vector(12, handle_ov); set_except_vector(13, handle_tr); From ths@networkno.de Mon Sep 11 11:38:50 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 11:38:52 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:43163 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20037785AbWIKKiu (ORCPT ); Mon, 11 Sep 2006 11:38:50 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id AF43246407; Mon, 11 Sep 2006 12:38:38 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GMiPZ-0004jf-Un; Mon, 11 Sep 2006 10:49:05 +0100 Date: Mon, 11 Sep 2006 10:49:05 +0100 To: Atsushi Nemoto Cc: nigel@mips.com, ralf@linux-mips.org, dan@debian.org, macro@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS Message-ID: <20060911094905.GB13414@networkno.de> References: <20060909.225641.41198763.anemo@mba.ocn.ne.jp> <450491FA.3010600@mips.com> <20060911.140403.126141483.nemoto@toshiba-tops.co.jp> <20060911.175029.37531637.nemoto@toshiba-tops.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060911.175029.37531637.nemoto@toshiba-tops.co.jp> User-Agent: Mutt/1.5.13 (2006-08-11) From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12552 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Atsushi Nemoto wrote: [snip] > @@ -375,6 +376,72 @@ #endif > BUILD_HANDLER dsp dsp sti silent /* #26 */ > BUILD_HANDLER reserved reserved sti verbose /* others */ > > + .align 5 > + LEAF(handle_ri_rdhwr_vivt) > +#ifdef CONFIG_MIPS_MT_SMTC > + PANIC_PIC("handle_ri_rdhwr_vivt called") > +#else > + .set push > + .set noat > + .set noreorder > + /* check if TLB contains a entry for EPC */ > + MFC0 k1, CP0_ENTRYHI > + andi k1, 0xff /* ASID_MASK */ > + MFC0 k0, CP0_EPC > + PTR_SRL k0, PAGE_SHIFT + 1 > + PTR_SLL k0, PAGE_SHIFT + 1 > + or k1, k0 > + MTC0 k1, CP0_ENTRYHI > + mtc0_tlbw_hazard > + tlbp This needs a .set mips3/.set mips0 pair. > +#ifdef CONFIG_CPU_MIPSR2 > + _ehb /* tlb_probe_hazard */ > +#else > + nop; nop; nop; nop; nop; nop /* tlb_probe_hazard */ > +#endif What about a mtc0_tlbp_hazard macro here? Thiemo From macro@linux-mips.org Mon Sep 11 14:09:24 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 14:09:27 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:3846 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20038252AbWIKNJY (ORCPT ); Mon, 11 Sep 2006 14:09:24 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 11BECF81CF; Mon, 11 Sep 2006 15:09:20 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ipO-NVOsnkAJ; Mon, 11 Sep 2006 15:09:19 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id A858EF819B; Mon, 11 Sep 2006 15:09:19 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k8BD9OJe001822; Mon, 11 Sep 2006 15:09:25 +0200 Date: Mon, 11 Sep 2006 14:09:20 +0100 (BST) From: "Maciej W. Rozycki" To: Atsushi Nemoto cc: nigel@mips.com, ralf@linux-mips.org, dan@debian.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS In-Reply-To: <20060909.225641.41198763.anemo@mba.ocn.ne.jp> Message-ID: References: <20060711025342.GA6898@nevyn.them.org> <20060711.122014.52129937.nemoto@toshiba-tops.co.jp> <4501AABC.1050009@mips.com> <20060909.225641.41198763.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1850/Mon Sep 11 11:41:17 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12553 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, 9 Sep 2006, Atsushi Nemoto wrote: > But I'm still looking for better solution (silver bullet?) for > cpu_has_vtag_icache case. What's wrong with just letting a TLB fault happen? Maciej From carlos.mitidieri@sysgo.com Mon Sep 11 14:30:15 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 14:30:17 +0100 (BST) Received: from mail.sysgo.com ([62.8.134.5]:60684 "EHLO mail.sysgo.com") by ftp.linux-mips.org with ESMTP id S20037555AbWIKNaP (ORCPT ); Mon, 11 Sep 2006 14:30:15 +0100 Received: from localhost (localhost [127.0.0.1]) by mail.sysgo.com (Postfix) with ESMTP id C047FCC1BA for ; Mon, 11 Sep 2006 15:30:09 +0200 (CEST) Received: from mail.sysgo.com (localhost [127.0.0.1]) by localhost (AvMailGate-2.0.2-8) id 25047-0B643A2C; Mon, 11 Sep 2006 15:30:09 +0200 Received: from donald.sysgo.com (unknown [172.20.1.30]) by mail.sysgo.com (Postfix) with ESMTP id 6CEC2CC1B1 for ; Mon, 11 Sep 2006 15:30:09 +0200 (CEST) Received: by donald.sysgo.com (Postfix, from userid 65534) id B7BCC26A412; Mon, 11 Sep 2006 15:30:09 +0200 (CEST) Received: from cam (unknown [172.40.1.200]) by donald.sysgo.com (Postfix) with ESMTP id B76F126A406 for ; Mon, 11 Sep 2006 15:30:08 +0200 (CEST) From: Carlos Mitidieri To: linux-mips@linux-mips.org Date: Mon, 11 Sep 2006 15:30:13 +0200 User-Agent: KMail/1.8.2 MIME-Version: 1.0 Content-Disposition: inline Subject: "Uncompressing Linux at load address" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Message-Id: <200609111530.14447.carlos.mitidieri@sysgo.com> X-AntiVirus: checked by AntiVir MailGate (version: 2.0.2-8; AVE: 7.1.1.16; VDF: 6.35.1.212; host: mailgate.sysgo.com) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12554 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: carlos.mitidieri@sysgo.com Precedence: bulk X-list: linux-mips Hi, I am trying to boot a zImage from micromonitor on a csb655 board (Au1550 processor). For that matter, I patched my kernel 2.6.15 with the zImage_2_6_10.patch from Popov. In the arch/mips/boot/compressed/au1xxx/Makefile, I have set: 1) RAM_RUN_ADDR=0xa0300000, which is the value got from the umon's APPRAMBASE environment variable. 2) AVAIL_RAM_START=0x80500000 AVAIL_RAM_END=0x80900000 3) LOADADDR =0x80100000, which is the same value I have set in an entry for this board in arch/mips/Makefile. I can compile and link the zImage with home build gcc cross tools, based on gcc-3.4.4 and glibc-2.3.4 . When the (binary) zImage is decompressed on the target, I get these messages: zImage: size=680372 base=0xa0300000 loaded at: A0300000 A03A4000 zimage at: A0306180 A03A3EE1 Uncompressing Linux at load address 80100000 and then the target resets. This zImage is very small, so the decompressed image is not going beyond the AVAIL_RAM limits. Would you have any guess on what is going on? I have looked for this information the list through, but anyone seems to have had this problem before. Thanks for any comment. -- Carlos Mitidieri SYSGO AG - Office Ulm Lise-Meitner-Str. 15 D-89081 Ulm From hemanth.venkatesh@wipro.com Mon Sep 11 14:55:53 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 14:55:55 +0100 (BST) Received: from wip-ec-wd.wipro.com ([203.91.193.32]:64965 "EHLO wip-ec-wd.wipro.com") by ftp.linux-mips.org with ESMTP id S20038430AbWIKNzx convert rfc822-to-8bit (ORCPT ); Mon, 11 Sep 2006 14:55:53 +0100 Received: from wip-ec-wd.wipro.com (localhost.wipro.com [127.0.0.1]) by localhost (Postfix) with ESMTP id 4E892205F1 for ; Mon, 11 Sep 2006 19:21:33 +0530 (IST) Received: from blr-ec-bh01.wipro.com (blr-ec-bh01.wipro.com [10.201.50.91]) by wip-ec-wd.wipro.com (Postfix) with ESMTP id 3ACA0205DE for ; Mon, 11 Sep 2006 19:21:33 +0530 (IST) Received: from blr-m2-msg.wipro.com ([10.116.50.99]) by blr-ec-bh01.wipro.com with Microsoft SMTPSVC(6.0.3790.1830); Mon, 11 Sep 2006 19:25:42 +0530 x-mimeole: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: "Uncompressing Linux at load address" Date: Mon, 11 Sep 2006 19:25:41 +0530 Message-ID: <2156B1E923F1A147AABDF4D9FDEAB4CB1727D5@blr-m2-msg.wipro.com> In-Reply-To: <200609111530.14447.carlos.mitidieri@sysgo.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: "Uncompressing Linux at load address" Thread-Index: AcbVppWiQimmzwmrTrm1Ms/YaDSYuAAAf1IA From: To: , X-OriginalArrivalTime: 11 Sep 2006 13:55:42.0849 (UTC) FILETIME=[F8E38F10:01C6D5A9] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12555 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hemanth.venkatesh@wipro.com Precedence: bulk X-list: linux-mips I had faced similar issue with AU1100 based boards which also use the zImage patch. It turned out to be board initialization issue rather that a zImage problem, since after uncompressing the image control is transferred to kernel_entry. Thanks Hemanth -----Original Message----- From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Carlos Mitidieri Sent: Monday, September 11, 2006 7:00 PM To: linux-mips@linux-mips.org Subject: "Uncompressing Linux at load address" Hi, I am trying to boot a zImage from micromonitor on a csb655 board (Au1550 processor). For that matter, I patched my kernel 2.6.15 with the zImage_2_6_10.patch from Popov. In the arch/mips/boot/compressed/au1xxx/Makefile, I have set: 1) RAM_RUN_ADDR=0xa0300000, which is the value got from the umon's APPRAMBASE environment variable. 2) AVAIL_RAM_START=0x80500000 AVAIL_RAM_END=0x80900000 3) LOADADDR =0x80100000, which is the same value I have set in an entry for this board in arch/mips/Makefile. I can compile and link the zImage with home build gcc cross tools, based on gcc-3.4.4 and glibc-2.3.4 . When the (binary) zImage is decompressed on the target, I get these messages: zImage: size=680372 base=0xa0300000 loaded at: A0300000 A03A4000 zimage at: A0306180 A03A3EE1 Uncompressing Linux at load address 80100000 and then the target resets. This zImage is very small, so the decompressed image is not going beyond the AVAIL_RAM limits. Would you have any guess on what is going on? I have looked for this information the list through, but anyone seems to have had this problem before. Thanks for any comment. -- Carlos Mitidieri SYSGO AG - Office Ulm Lise-Meitner-Str. 15 D-89081 Ulm From anemo@mba.ocn.ne.jp Mon Sep 11 15:11:21 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 15:11:22 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:52167 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20037486AbWIKOLV (ORCPT ); Mon, 11 Sep 2006 15:11:21 +0100 Received: from localhost (p8244-ipad25funabasi.chiba.ocn.ne.jp [220.104.86.244]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 87116A685; Mon, 11 Sep 2006 23:11:15 +0900 (JST) Date: Mon, 11 Sep 2006 23:13:14 +0900 (JST) Message-Id: <20060911.231314.25910522.anemo@mba.ocn.ne.jp> To: ths@networkno.de Cc: nigel@mips.com, ralf@linux-mips.org, dan@debian.org, macro@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS From: Atsushi Nemoto In-Reply-To: <20060911094905.GB13414@networkno.de> References: <20060911.140403.126141483.nemoto@toshiba-tops.co.jp> <20060911.175029.37531637.nemoto@toshiba-tops.co.jp> <20060911094905.GB13414@networkno.de> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12556 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Mon, 11 Sep 2006 10:49:05 +0100, Thiemo Seufer wrote: > > + tlbp > > This needs a .set mips3/.set mips0 pair. The TLBP is belong to MIPS I ISA, isn't it? > > +#ifdef CONFIG_CPU_MIPSR2 > > + _ehb /* tlb_probe_hazard */ > > +#else > > + nop; nop; nop; nop; nop; nop /* tlb_probe_hazard */ > > +#endif > > What about a mtc0_tlbp_hazard macro here? You mean mtc0_tlbw_hazard? I took them from tlb_probe_hazard macro in queue branch. And it looks current mtc0_tlbw_hazard asm macro does not match with its C equivalent ... .macro mtc0_tlbw_hazard b . + 8 .endm #define mtc0_tlbw_hazard() \ __asm__ __volatile__( \ " .set noreorder \n" \ " nop \n" \ " nop \n" \ " nop \n" \ " nop \n" \ " nop \n" \ " nop \n" \ " .set reorder \n") --- Atsushi Nemoto From anemo@mba.ocn.ne.jp Mon Sep 11 15:28:52 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 15:28:53 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:45041 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20037486AbWIKO2w (ORCPT ); Mon, 11 Sep 2006 15:28:52 +0100 Received: from localhost (p8244-ipad25funabasi.chiba.ocn.ne.jp [220.104.86.244]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 6F5239CB5; Mon, 11 Sep 2006 23:28:47 +0900 (JST) Date: Mon, 11 Sep 2006 23:30:46 +0900 (JST) Message-Id: <20060911.233046.41631256.anemo@mba.ocn.ne.jp> To: macro@linux-mips.org Cc: nigel@mips.com, ralf@linux-mips.org, dan@debian.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS From: Atsushi Nemoto In-Reply-To: References: <4501AABC.1050009@mips.com> <20060909.225641.41198763.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12557 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Mon, 11 Sep 2006 14:09:20 +0100 (BST), "Maciej W. Rozycki" wrote: > > But I'm still looking for better solution (silver bullet?) for > > cpu_has_vtag_icache case. > > What's wrong with just letting a TLB fault happen? It might add a little overhead to usual TLB refill handling. The overhead might be neglectable, but I'm not sure. --- Atsushi Nemoto From ths@networkno.de Mon Sep 11 16:19:18 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 16:19:20 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:32930 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20038459AbWIKPTS (ORCPT ); Mon, 11 Sep 2006 16:19:18 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 0BDA6465DB; Mon, 11 Sep 2006 17:19:17 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GMnXT-0006oJ-0h; Mon, 11 Sep 2006 16:17:35 +0100 Date: Mon, 11 Sep 2006 16:17:34 +0100 From: Thiemo Seufer To: Atsushi Nemoto Cc: nigel@mips.com, ralf@linux-mips.org, dan@debian.org, macro@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS Message-ID: <20060911151734.GC13414@networkno.de> References: <20060911.140403.126141483.nemoto@toshiba-tops.co.jp> <20060911.175029.37531637.nemoto@toshiba-tops.co.jp> <20060911094905.GB13414@networkno.de> <20060911.231314.25910522.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060911.231314.25910522.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12558 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Atsushi Nemoto wrote: > On Mon, 11 Sep 2006 10:49:05 +0100, Thiemo Seufer wrote: > > > + tlbp > > > > This needs a .set mips3/.set mips0 pair. > > The TLBP is belong to MIPS I ISA, isn't it? Uh, right. I wasn't awake when I wrote that mail. :-) > > > +#ifdef CONFIG_CPU_MIPSR2 > > > + _ehb /* tlb_probe_hazard */ > > > +#else > > > + nop; nop; nop; nop; nop; nop /* tlb_probe_hazard */ > > > +#endif > > > > What about a mtc0_tlbp_hazard macro here? > > You mean mtc0_tlbw_hazard? I took them from tlb_probe_hazard macro in > queue branch. Actually, I meant an equivalent to the build_tlb_probe_entry in tlbex.c, plus a tlb_use_hazard. > And it looks current mtc0_tlbw_hazard asm macro does not match with > its C equivalent ... > > .macro mtc0_tlbw_hazard > b . + 8 > .endm > > #define mtc0_tlbw_hazard() \ > __asm__ __volatile__( \ > " .set noreorder \n" \ > " nop \n" \ > " nop \n" \ > " nop \n" \ > " nop \n" \ > " nop \n" \ > " nop \n" \ > " .set reorder \n") It also lacks a case for R2 CPUs, where IIRC _ehb is the the way approved by the spec. Thiemo From carlos.mitidieri@sysgo.com Mon Sep 11 16:25:14 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 16:25:15 +0100 (BST) Received: from mail.sysgo.com ([62.8.134.5]:5133 "EHLO mail.sysgo.com") by ftp.linux-mips.org with ESMTP id S20038456AbWIKPZN convert rfc822-to-8bit (ORCPT ); Mon, 11 Sep 2006 16:25:13 +0100 Received: from localhost (localhost [127.0.0.1]) by mail.sysgo.com (Postfix) with ESMTP id 5FB76CC1C0 for ; Mon, 11 Sep 2006 17:25:07 +0200 (CEST) Received: from mail.sysgo.com (localhost [127.0.0.1]) by localhost (AvMailGate-2.0.2-8) id 26031-392B27E7; Mon, 11 Sep 2006 17:25:07 +0200 Received: from donald.sysgo.com (unknown [172.20.1.30]) by mail.sysgo.com (Postfix) with ESMTP id 13A0ECC1BF for ; Mon, 11 Sep 2006 17:25:07 +0200 (CEST) Received: by donald.sysgo.com (Postfix, from userid 65534) id 7CC5826A66B; Mon, 11 Sep 2006 17:25:07 +0200 (CEST) Received: from cam (unknown [172.40.1.200]) by donald.sysgo.com (Postfix) with ESMTP id 714D126A669 for ; Mon, 11 Sep 2006 17:25:06 +0200 (CEST) From: Carlos Mitidieri To: linux-mips@linux-mips.org Subject: Re: "Uncompressing Linux at load address" Date: Mon, 11 Sep 2006 17:25:11 +0200 User-Agent: KMail/1.8.2 References: <2156B1E923F1A147AABDF4D9FDEAB4CB1727D5@blr-m2-msg.wipro.com> In-Reply-To: <2156B1E923F1A147AABDF4D9FDEAB4CB1727D5@blr-m2-msg.wipro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200609111725.12209.carlos.mitidieri@sysgo.com> X-AntiVirus: checked by AntiVir MailGate (version: 2.0.2-8; AVE: 7.1.1.16; VDF: 6.35.1.213; host: mailgate.sysgo.com) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12559 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: carlos.mitidieri@sysgo.com Precedence: bulk X-list: linux-mips thanks for commenting Since my APPRAMBASE in umon is 0xa0300000, I have changed my parametes in a way that the kernel would be loaded above that address: AVAIL_RAM_START=0xb0a00000 AVAIL_RAM_END=0xb0f00000 LOADADDR =0xb0000000 unfortunately, the problem persists, i.e., the systems hangs just after the messages: zImage: size=680372 base=0xa0300000 loaded at: A0300000 A03A4000 zimage at: A0306180 A03A3EE1 Uncompressing Linux at load address B0000000 I am pretty sure that the problem relates to where the things are loaded, but I don't realize exactly what. On Monday 11 September 2006 15:55, you wrote: > I had faced similar issue with AU1100 based boards which also use the > zImage patch. It turned out to be board initialization issue rather that > a zImage problem, since after uncompressing the image control is > transferred to kernel_entry. > > Thanks > Hemanth > > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Carlos Mitidieri > Sent: Monday, September 11, 2006 7:00 PM > To: linux-mips@linux-mips.org > Subject: "Uncompressing Linux at load address" > > Hi, > > I am trying to boot a zImage from micromonitor on a csb655 board > (Au1550 processor). > > For that matter, I patched my kernel 2.6.15 with the zImage_2_6_10.patch > from > Popov. > > In the arch/mips/boot/compressed/au1xxx/Makefile, I have set: > 1) RAM_RUN_ADDR=0xa0300000, which is the value got from the > umon's > APPRAMBASE environment variable. > 2) AVAIL_RAM_START=0x80500000 > AVAIL_RAM_END=0x80900000 > 3) LOADADDR =0x80100000, which is the same value I have set in > an > entry for this board in arch/mips/Makefile. > > I can compile and link the zImage with home build gcc cross tools, based > on > gcc-3.4.4 and glibc-2.3.4 . When the (binary) zImage is decompressed on > the > target, I get these messages: > > zImage: size=680372 base=0xa0300000 > loaded at: A0300000 A03A4000 > zimage at: A0306180 A03A3EE1 > Uncompressing Linux at load address 80100000 > > and then the target resets. > This zImage is very small, so the decompressed image is not going beyond > the > AVAIL_RAM limits. Would you have any guess on what is going on? > > I have looked for this information the list through, but anyone seems to > have > had this problem before. Thanks for any comment. -- Carlos Mitidieri SYSGO AG - Office Ulm Lise-Meitner-Str. 15 D-89081 Ulm Tel: +49 731 94683 16 Fax: +49 731 94683 10 Web: www.sysgo.com Meet us at our next event: RTS Embedded Systems 2006 April 4-6, 2006 Paris, La Défense http://www.birp.com/rts From dirk.behme@googlemail.com Mon Sep 11 17:07:00 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 17:07:02 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.187]:48745 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20037712AbWIKQHA (ORCPT ); Mon, 11 Sep 2006 17:07:00 +0100 Received: by nf-out-0910.google.com with SMTP id l23so1394619nfc for ; Mon, 11 Sep 2006 09:06:59 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=googlemail.com; h=received:message-id:date:user-agent:x-accept-language:mime-version:to:subject:content-type:content-transfer-encoding:from; b=ScE+XpczxooQutcmTSD/5hE5fneQI5MXj1kPI3l8iUqZw9HPfp/dUsBaFxTfVNf8BXIOlDdZDcqQ0vnjtFf9+uns8uWlilf6uCQD52IZvtEgD0djvBL1TLM3GaZTZREQwgt0+r9dYZEQOeYKbW2v2t3yfRFM5lyoitDl0vlVD5k= Received: by 10.48.242.19 with SMTP id p19mr8303147nfh; Mon, 11 Sep 2006 09:06:59 -0700 (PDT) Received: from ?192.168.178.25? ( [195.4.50.88]) by mx.gmail.com with ESMTP id 38sm4580123hua.2006.09.11.09.06.58; Mon, 11 Sep 2006 09:06:59 -0700 (PDT) Message-ID: <450589A6.5040808@gmail.com> Date: Mon, 11 Sep 2006 18:07:02 +0200 User-Agent: Mozilla Thunderbird 1.0.7 (X11/20050923) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: QEMU MIPS user space emulation issue Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit From: Dirk Behme Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12560 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dirk.behme@googlemail.com Precedence: bulk X-list: linux-mips Hi, we have an issue using QEMUs MIPS user space emulation running programs compiled with mipsel glibc based crosscompiler [1]. Because I'm not sure if it's a QEMU or toolchain (or anything else?) issue, I'd like to ask the experts here. Up to now, the conclusion from [1] is that QEMUs mipsel user space emulation fails executing a simple hello world program if compiled with glibc based mipsel toolchain build with crosstool and linked dynamically. Compiled with toolchain using uClib or same program linked statically (-static) is okay. For example, hello world compiled with mipsel toolchain build with crosstool-0.42 configuration cat mipsel.dat gcc-3.4.1-glibc-2.3.2.dat fails if dynamically linked. As mentioned above, using -static is okay. If failing, debug output shows that code ... 0x401fa00c: lw t9,-32600(gp) 0x401fa010: addiu a0,a0,30820 0x401fa014: addiu a1,a1,29452 0x401fa018: addiu a3,a3,25856 0x401fa01c: jalr t9 0x401fa020: li a2,161 ... fails because it seems that it gets a wrong jump address in t9: pc=0x00012a2c HI=0x00000000 LO=0x00000000 ds 0003 00000000 0 GPR00: r0 00000000 at 00000000 v0 401f60d4 v1 00000008 GPR04: a0 00017864 a1 0001730c a2 000000a1 a3 00016500 GPR08: t0 90000000 t1 401f6000 t2 40000000 t3 6fffffff GPR12: t4 70000053 t5 401f3c20 t6 401f3f20 t7 00000063 GPR16: s0 6fffff72 s1 00000000 s2 00000000 s3 00000000 GPR20: s4 00000000 s5 00000000 s6 00000000 s7 00000000 GPR24: t8 6ffffdff t9 00012a2c k0 00000000 k1 00000000 GPR28: gp 40257020 sp 401f3c08 s8 00000000 ra 401fa024 CP0 Status 0x30400014 Cause 0x00000000 EPC 0x00000000 Config0 0x80000082 Config1 0x1e190c8b LLAddr 0x00000000 CP1 FCR0 0x00000110 FCR31 0x00000000 SR.FR 0 ... cpu_mips_handle_mmu_fault pc 00012a2c ad 00012a2c rw 0 is_user 1 smmu 0 Any ideas or hints where to search? Many thanks Dirk [1] Thread "MIPS little endian user space emulation" on QEMU devel mailinglist http://lists.gnu.org/archive/html/qemu-devel/2006-09/msg00090.html From macro@linux-mips.org Mon Sep 11 18:53:34 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 18:53:39 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([153.19.208.7]:64521 "EHLO pollux.ds.pg.gda.pl") by ftp.linux-mips.org with ESMTP id S20037874AbWIKRxe (ORCPT ); Mon, 11 Sep 2006 18:53:34 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id A2C74F5C12; Mon, 11 Sep 2006 19:53:28 +0200 (CEST) X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux.ds.pg.gda.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vnMKIFrmQnZz; Mon, 11 Sep 2006 19:53:28 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id EACFCF5BC9; Mon, 11 Sep 2006 19:53:27 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.8/8.13.1) with ESMTP id k8BHrYKm008659; Mon, 11 Sep 2006 19:53:35 +0200 Date: Mon, 11 Sep 2006 18:53:29 +0100 (BST) From: "Maciej W. Rozycki" To: Atsushi Nemoto cc: nigel@mips.com, ralf@linux-mips.org, dan@debian.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS In-Reply-To: <20060911.233046.41631256.anemo@mba.ocn.ne.jp> Message-ID: References: <4501AABC.1050009@mips.com> <20060909.225641.41198763.anemo@mba.ocn.ne.jp> <20060911.233046.41631256.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.88.4/1856/Mon Sep 11 15:51:46 2006 on piorun.ds.pg.gda.pl X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12561 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 11 Sep 2006, Atsushi Nemoto wrote: > > What's wrong with just letting a TLB fault happen? > > It might add a little overhead to usual TLB refill handling. The > overhead might be neglectable, but I'm not sure. There is no need to change the refill handler -- only the general TLBL exception has to be modified. And this one may be not too critical -- the change required is in the path to mark pages accessed. Is the path frequent enough to seek a complex solution while a simple one would just work? Maciej From ths@networkno.de Mon Sep 11 22:32:04 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Sep 2006 22:32:06 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:57788 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20038533AbWIKVcE (ORCPT ); Mon, 11 Sep 2006 22:32:04 +0100 Received: from lagash (88-106-139-84.dynamic.dsl.as9105.com [88.106.139.84]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id BD75748A5C; Mon, 11 Sep 2006 23:32:03 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GMtM0-0008KG-8W; Mon, 11 Sep 2006 22:30:08 +0100 Date: Mon, 11 Sep 2006 22:30:08 +0100 To: Dirk Behme Cc: linux-mips@linux-mips.org Subject: Re: QEMU MIPS user space emulation issue Message-ID: <20060911213008.GD13414@networkno.de> References: <450589A6.5040808@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <450589A6.5040808@gmail.com> User-Agent: Mutt/1.5.13 (2006-08-11) From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12562 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Dirk Behme wrote: > Hi, > > we have an issue using QEMUs MIPS user space emulation > running programs compiled with mipsel glibc based > crosscompiler [1]. Because I'm not sure if it's a QEMU or > toolchain (or anything else?) issue, I'd like to ask the > experts here. > > Up to now, the conclusion from [1] is that QEMUs mipsel user > space emulation fails executing a simple hello world program > if compiled with glibc based mipsel toolchain build with > crosstool and linked dynamically. Compiled with toolchain > using uClib or same program linked statically (-static) is okay. So this is unlikely to be a kernel problem. > For example, hello world compiled with mipsel toolchain > build with crosstool-0.42 configuration > > cat mipsel.dat gcc-3.4.1-glibc-2.3.2.dat > > fails if dynamically linked. As mentioned above, using > -static is okay. Start from a known working mipsel userland, e.g. the one from Debian unstable, and use it to isolate the bug. > If failing, debug output shows that code > > ... > 0x401fa00c: lw t9,-32600(gp) > 0x401fa010: addiu a0,a0,30820 > 0x401fa014: addiu a1,a1,29452 > 0x401fa018: addiu a3,a3,25856 > 0x401fa01c: jalr t9 > 0x401fa020: li a2,161 > ... Sa a guess, it might be a dynamic symbol mis-resolved by the ld.so. Thiemo From anemo@mba.ocn.ne.jp Tue Sep 12 02:56:06 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Sep 2006 02:56:09 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:26845 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20038603AbWILB4G (ORCPT ); Tue, 12 Sep 2006 02:56:06 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Tue, 12 Sep 2006 10:56:04 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 102F820603; Tue, 12 Sep 2006 10:55:59 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 040FE205B1; Tue, 12 Sep 2006 10:55:59 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k8C1tuW0001517; Tue, 12 Sep 2006 10:55:57 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Tue, 12 Sep 2006 10:55:56 +0900 (JST) Message-Id: <20060912.105556.25910629.nemoto@toshiba-tops.co.jp> To: macro@linux-mips.org Cc: nigel@mips.com, ralf@linux-mips.org, dan@debian.org, linux-mips@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS From: Atsushi Nemoto In-Reply-To: References: <20060911.233046.41631256.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12563 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Mon, 11 Sep 2006 18:53:29 +0100 (BST), "Maciej W. Rozycki" wrote: > > It might add a little overhead to usual TLB refill handling. The > > overhead might be neglectable, but I'm not sure. > > There is no need to change the refill handler -- only the general TLBL > exception has to be modified. And this one may be not too critical -- the > change required is in the path to mark pages accessed. Is the path > frequent enough to seek a complex solution while a simple one would just > work? Yes, my description was wrong. general TLBL handling, not TLB refill handling. Hmm, it seems not so critical indeed. Then "take 2" patch would be exactly what you preferred. http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20060710.234010.07457279.anemo%40mba.ocn.ne.jp Any comments about that? --- Atsushi Nemoto From ydgoo9@gmail.com Tue Sep 12 12:40:44 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Sep 2006 12:40:46 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.186]:22381 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20037548AbWILLko (ORCPT ); Tue, 12 Sep 2006 12:40:44 +0100 Received: by nf-out-0910.google.com with SMTP id l23so1630313nfc for ; Tue, 12 Sep 2006 04:40:43 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=EBGSI+Wbd+wSQqR9RXqTq5ZHJPbZ+6UBGyrGjlRaERpGeo/ZZ1nDQGwW/HBPrb8VS+G21QZj5LaVl3Ztt3xA+V0DD7aWgPquaRPSPuuNZ/g5+xfbm5uYVOm/vwiwnOlnW7z56XWKMaermnN0YT89gR9+PfdPOfvXdeeN+hNSRMs= Received: by 10.49.90.4 with SMTP id s4mr9434688nfl; Tue, 12 Sep 2006 04:40:43 -0700 (PDT) Received: by 10.48.238.18 with HTTP; Tue, 12 Sep 2006 04:40:43 -0700 (PDT) Message-ID: <38dc7fce0609120440o11c6a11ejf7f0a3cb1371bb40@mail.gmail.com> Date: Tue, 12 Sep 2006 20:40:43 +0900 From: "Youngduk Goo" To: linux-mips@linux-mips.org Subject: NOR Flash memory write speed. MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12564 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ydgoo9@gmail.com Precedence: bulk X-list: linux-mips Hello, all I am developing the system using the NOR flash (32MB) and the core is about 300MHz mips. I wonder how long takes the whole erase and write time to flash memory. I tried it on the bootloader. Firstof all, bootloader(YAMON) load the image and erase the flash except bootloader region, write the image.. It took about 14-16minutes.I think it is too long. I would like to know, for you, normally how long it tasks ? Thanks, From 666f7374657262@gmail.com Tue Sep 12 13:55:33 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Sep 2006 13:55:34 +0100 (BST) Received: from wx-out-0506.google.com ([66.249.82.225]:36303 "EHLO wx-out-0506.google.com") by ftp.linux-mips.org with ESMTP id S20038701AbWILMzd (ORCPT ); Tue, 12 Sep 2006 13:55:33 +0100 Received: by wx-out-0506.google.com with SMTP id h30so2254453wxd for ; Tue, 12 Sep 2006 05:55:31 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:sender:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references:x-google-sender-auth; b=iKK1J5a8hUuU+GFtwXwS8Gpcmw/oEsPzZRN4yWWwvRwRQeLaznYy8y37W9c8uBAxxdjQLnB7KoI5jnAkiuOJcc0GCV1aCPwhw4cXQmTA2r0ZRtAJ9ElIjpZDUcMTlRrMMkmxtm+n1eJqKVYj4gbtRCCpjgQkoz43HLUBaj4GjBY= Received: by 10.90.100.2 with SMTP id x2mr2032162agb; Tue, 12 Sep 2006 05:55:31 -0700 (PDT) Received: by 10.90.86.20 with HTTP; Tue, 12 Sep 2006 05:55:31 -0700 (PDT) Message-ID: <474ab6f00609120555p33522851p151f7062e4379d17@mail.gmail.com> Date: Tue, 12 Sep 2006 08:55:31 -0400 From: "Brett Foster" To: "Youngduk Goo" Subject: Re: NOR Flash memory write speed. Cc: linux-mips@linux-mips.org In-Reply-To: <38dc7fce0609120440o11c6a11ejf7f0a3cb1371bb40@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <38dc7fce0609120440o11c6a11ejf7f0a3cb1371bb40@mail.gmail.com> X-Google-Sender-Auth: be1aed679b4d8efb Return-Path: <666f7374657262@gmail.com> X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12565 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fosterb@uoguelph.ca Precedence: bulk X-list: linux-mips On 9/12/06, Youngduk Goo wrote: > Hello, all > > I am developing the system using the NOR flash (32MB) and the core is > about 300MHz mips. > I wonder how long takes the whole erase and write time to flash memory. > I tried it on the bootloader. Firstof all, bootloader(YAMON) load the image > and erase the flash except bootloader region, write the image.. > It took about 14-16minutes.I think it is too long. Can't really say, but it seems ok to me. Each chip will have unique timing characteristics which are covered in the data sheet for the flash part with min, typical and max values. You can compute the upper and lower bounds of the operation using that information. > > I would like to know, for you, normally how long it tasks ? > > Thanks, > > From sshtylyov@ru.mvista.com Tue Sep 12 13:58:40 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Sep 2006 13:58:43 +0100 (BST) Received: from [63.81.120.155] ([63.81.120.155]:55126 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20038704AbWILM6k (ORCPT ); Tue, 12 Sep 2006 13:58:40 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id B8A4A3ED0; Tue, 12 Sep 2006 05:58:07 -0700 (PDT) Message-ID: <4506AF69.30905@ru.mvista.com> Date: Tue, 12 Sep 2006 17:00:25 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Suzuki Takashi Cc: linuxppc-embedded@ozlabs.org, Linux-MIPS Subject: Re: SM501 Kernel display driver for v2.6.17 References: In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12566 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Suzuki Takashi wrote: > I want to make Voyager GX PCI Demo Board Ver.A work on Yosemite board. > I know Silicon Motion have Linux Kernel_v2.6 Display driver: > http://www.siliconmotion.com.tw/en/en2/download2c.htm > But it's for v2.6.4 and it cannot be compiled with v2.6.17 working on > Yosemite board. > Does anybody have succeeded in making the board work with v2.6.17? > If there is a patch or source code available, let me know the location. I know that Linux/MIPS project maintains the framebuffer driver in drivers/video/smivgxfb.c. We used to backport it to 2.6.10 and it worked for us... Here's the link to the latest source: http://www.linux-mips.org/git?p=linux.git;a=blob;h=c521069c905b4252109b8144478b4381c0ccdb7f;hb=db092db967ec0824db433c4adf3b58202fe610e2;f=drivers/video/smivgxfb.c > Thanks in advance, > -- T.Suzuki WBR, Sergei From freddy@dusktilldawn.nl Tue Sep 12 16:47:10 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Sep 2006 16:47:14 +0100 (BST) Received: from tool.snarl.nl ([213.84.251.124]:27049 "EHLO tool.snarl.nl") by ftp.linux-mips.org with ESMTP id S20038596AbWILPrK (ORCPT ); Tue, 12 Sep 2006 16:47:10 +0100 Received: from localhost (tool.local.snarl.nl [127.0.0.1]) by tool.snarl.nl (Postfix) with ESMTP id 97E5A5E693; Tue, 12 Sep 2006 17:46:57 +0200 (CEST) Received: from tool.snarl.nl ([127.0.0.1]) by localhost (tool.local.snarl.nl [127.0.0.1]) (amavisd-new, port 10024) with LMTP id lvNvkVIrPEEo; Tue, 12 Sep 2006 17:46:57 +0200 (CEST) Received: by tool.snarl.nl (Postfix, from userid 1000) id 33E765E473; Tue, 12 Sep 2006 17:46:57 +0200 (CEST) Date: Tue, 12 Sep 2006 17:46:57 +0200 From: Freddy Spierenburg To: adaplas@pol.net Cc: linux-fbdev-devel@lists.sourceforge.net, linux-mips@linux-mips.org Subject: [PATCH] Fix to remove flickering. Message-ID: <20060912154656.GY10006@dusktilldawn.nl> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="i/VKSWANvDZSIhsB" Content-Disposition: inline X-User-Agent-Feature: All mail clients suck. This one just sucks less. X-GPG-Key: http://snarl.nl/~freddy/keys/freddyPublicKey.gpg User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12567 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: freddy@dusktilldawn.nl Precedence: bulk X-list: linux-mips --i/VKSWANvDZSIhsB Content-Type: multipart/mixed; boundary="yC91f7qSViS67v3c" Content-Disposition: inline --yC91f7qSViS67v3c Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Antonino, Currently a lot of flickering is seen on the VGA and LCD port when one starts a DBAu1100 board, with 'CONFIG_PRINTK=3Dy'. This patch removes the flickering and as a result all kernel messages come by in a nice steady fashion. Please apply. Signed-off-by: Freddy Spierenburg --=20 $ cat ~/.signature Freddy Spierenburg http://freddy.snarl.nl/ GnuPG: 0x7941D1E1=3DC948 5851 26D2 FA5C 39F1 E588 6F17 FD5D 7941 D1E1 $ # Please read http://www.ietf.org/rfc/rfc2015.txt before complain! --yC91f7qSViS67v3c Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="au1100fb.patch" diff -Naur linux-2.6.17.13-orig/drivers/video/au1100fb.h linux-2.6.17.13/drivers/video/au1100fb.h --- linux-2.6.17.13-orig/drivers/video/au1100fb.h 2006-09-09 03:23:25.000000000 +0000 +++ linux-2.6.17.13/drivers/video/au1100fb.h 2006-09-12 15:26:52.000000000 +0000 @@ -274,7 +274,7 @@ .bpp = 16, .control_base = 0x0004886A | LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF | - LCD_CONTROL_BPP_16, + LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4, .clkcontrol_base = 0x00020000, .horztiming = 0x005aff1f, .verttiming = 0x16000e57, --yC91f7qSViS67v3c-- --i/VKSWANvDZSIhsB Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5 (GNU/Linux) iD8DBQFFBtZwbxf9XXlB0eERAtcRAJ98NI4P0gat6ROB3UcIs37ebhNqbQCgibi+ sKl0Oq602P5FsbJhrqksMXA= =RJn2 -----END PGP SIGNATURE----- --i/VKSWANvDZSIhsB-- From ebs@ebshome.net Tue Sep 12 17:18:33 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Sep 2006 17:18:37 +0100 (BST) Received: from gate.ebshome.net ([208.106.21.240]:2784 "EHLO gate.ebshome.net") by ftp.linux-mips.org with ESMTP id S20038598AbWILQSd (ORCPT ); Tue, 12 Sep 2006 17:18:33 +0100 Received: (qmail 17615 invoked by uid 1000); 12 Sep 2006 09:18:25 -0700 Date: Tue, 12 Sep 2006 09:18:25 -0700 From: Eugene Surovegin To: Youngduk Goo Cc: linux-mips@linux-mips.org Subject: Re: NOR Flash memory write speed. Message-ID: <20060912161824.GA5987@gate.ebshome.net> Mail-Followup-To: Youngduk Goo , linux-mips@linux-mips.org References: <38dc7fce0609120440o11c6a11ejf7f0a3cb1371bb40@mail.gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <38dc7fce0609120440o11c6a11ejf7f0a3cb1371bb40@mail.gmail.com> X-ICQ-UIN: 1193073 X-Operating-System: Linux i686 X-PGP-Key: http://www.ebshome.net/pubkey.asc User-Agent: Mutt/1.5.8i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12568 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ebs@ebshome.net Precedence: bulk X-list: linux-mips On Tue, Sep 12, 2006 at 08:40:43PM +0900, Youngduk Goo wrote: > Hello, all > > I am developing the system using the NOR flash (32MB) and the core is > about 300MHz mips. > I wonder how long takes the whole erase and write time to flash memory. > I tried it on the bootloader. Firstof all, bootloader(YAMON) load the image > and erase the flash except bootloader region, write the image.. > It took about 14-16minutes.I think it is too long. > Yeah, this seems way too slow. Check if your chip supports "buffer write" mode and make sure software uses it. -- Eugene From thomas@koeller.dyndns.org Tue Sep 12 21:47:26 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Sep 2006 21:47:31 +0100 (BST) Received: from mail01.hansenet.de ([213.191.73.61]:6073 "EHLO webmail.hansenet.de") by ftp.linux-mips.org with ESMTP id S20038634AbWILUr0 (ORCPT ); Tue, 12 Sep 2006 21:47:26 +0100 Received: from [213.39.153.133] (213.39.153.133) by webmail.hansenet.de (7.2.074) (authenticated as mbx20228207@koeller-hh.org) id 45064C5C00030367; Tue, 12 Sep 2006 22:47:19 +0200 Received: from localhost.koeller.dyndns.org (localhost.koeller.dyndns.org [127.0.0.1]) by sarkovy.koeller.dyndns.org (Postfix) with ESMTP id 610472C408; Tue, 12 Sep 2006 22:47:19 +0200 (CEST) From: Thomas Koeller To: Ralf Baechle Subject: Patches Date: Tue, 12 Sep 2006 22:47:19 +0200 User-Agent: KMail/1.9.3 Cc: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200609122247.19091.thomas@koeller.dyndns.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12569 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas@koeller.dyndns.org Precedence: bulk X-list: linux-mips Hi Ralf, what about these patches: http://www.linux-mips.org/archives/linux-mips/2006-08/msg00271.html http://www.linux-mips.org/archives/linux-mips/2006-08/msg00270.html Are you going to apply them? Thomas -- Thomas Koeller thomas at koeller dot dyndns dot org From ralf@linux-mips.org Wed Sep 13 13:27:09 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Sep 2006 13:27:11 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:25760 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20037721AbWIMM1J (ORCPT ); Wed, 13 Sep 2006 13:27:09 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k8DCRkk6013286; Wed, 13 Sep 2006 13:27:46 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k8DCRklh013285; Wed, 13 Sep 2006 13:27:46 +0100 Date: Wed, 13 Sep 2006 13:27:46 +0100 From: Ralf Baechle To: Thomas Koeller Cc: linux-mips@linux-mips.org Subject: Re: Patches Message-ID: <20060913122746.GA10177@linux-mips.org> References: <200609122247.19091.thomas@koeller.dyndns.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200609122247.19091.thomas@koeller.dyndns.org> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12570 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Sep 12, 2006 at 10:47:19PM +0200, Thomas Koeller wrote: > what about these patches: > http://www.linux-mips.org/archives/linux-mips/2006-08/msg00271.html > http://www.linux-mips.org/archives/linux-mips/2006-08/msg00270.html > > Are you going to apply them? They've been applied to the queue branch weeks ago. Due to the still unmerged RM92xx seriver driver I didn't consider it 2.6.18 material. Ralf From vagabon.xyz@gmail.com Wed Sep 13 14:01:38 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Sep 2006 14:01:43 +0100 (BST) Received: from nf-out-0910.google.com ([64.233.182.188]:25965 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20037726AbWIMNBi (ORCPT ); Wed, 13 Sep 2006 14:01:38 +0100 Received: by nf-out-0910.google.com with SMTP id l23so1940263nfc for ; Wed, 13 Sep 2006 06:01:38 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:reply-to:user-agent:mime-version:to:cc:subject:references:in-reply-to:content-type:content-transfer-encoding:from; b=bPaiGoFAjrd1LD9xsbR78TRKbAbbfzNoW3edxnUuZUoLQOaLhPYRqPRYsG6RRyPWOz0el6saUJ9eikI2HrSXTiJgVrjgPgOU4mIqFXsp9Q1FcVPvbaENhFnuk73Z6Q+TJi4O9Bqb0vnVo+3RUZq3Ff6ubnY/B4kpkacqJnqIZhY= Received: by 10.49.21.8 with SMTP id y8mr10892818nfi; Wed, 13 Sep 2006 06:01:37 -0700 (PDT) Received: from ?192.168.0.24? ( [81.252.61.1]) by mx.gmail.com with ESMTP id c10sm17170788nfb.2006.09.13.06.01.36; Wed, 13 Sep 2006 06:01:37 -0700 (PDT) Message-ID: <45080148.3000104@innova-card.com> Date: Wed, 13 Sep 2006 15:02:00 +0200 Reply-To: Franck User-Agent: Thunderbird 1.5.0.4 (X11/20060614) MIME-Version: 1.0 To: Ralf Baechle CC: Atsushi Nemoto , linux-mips@linux-mips.org Subject: Re: Patches References: <200609122247.19091.thomas@koeller.dyndns.org> <20060913122746.GA10177@linux-mips.org> In-Reply-To: <20060913122746.GA10177@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit From: Franck Bui-Huu Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12571 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vagabon.xyz@gmail.com Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > On Tue, Sep 12, 2006 at 10:47:19PM +0200, Thomas Koeller wrote: > >> what about these patches: >> http://www.linux-mips.org/archives/linux-mips/2006-08/msg00271.html >> http://www.linux-mips.org/archives/linux-mips/2006-08/msg00270.html >> >> Are you going to apply them? > > They've been applied to the queue branch weeks ago. Due to the still > unmerged RM92xx seriver driver I didn't consider it 2.6.18 material. > and what about ? http://www.linux-mips.org/archives/linux-mips/2006-08/msg00112.html http://www.linux-mips.org/archives/linux-mips/2006-08/msg00113.html http://www.linux-mips.org/archives/linux-mips/2006-08/msg00114.html http://www.linux-mips.org/archives/linux-mips/2006-08/msg00115.html http://www.linux-mips.org/archives/linux-mips/2006-08/msg00117.html http://www.linux-mips.org/archives/linux-mips/2006-08/msg00118.html and these ones too ? http://www.linux-mips.org/archives/linux-mips/2006-08/msg00196.html http://www.linux-mips.org/archives/linux-mips/2006-08/msg00195.html http://www.linux-mips.org/archives/linux-mips/2006-08/msg00197.html BTW, mainline doesn't seem to merge MIPS repo anymore during election of release candidate. Do you know why ? Franck From treestem@gmail.com Thu Sep 14 16:51:44 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Sep 2006 16:51:46 +0100 (BST) Received: from wx-out-0506.google.com ([66.249.82.231]:36 "EHLO wx-out-0506.google.com") by ftp.linux-mips.org with ESMTP id S20038903AbWINPvo (ORCPT ); Thu, 14 Sep 2006 16:51:44 +0100 Received: by wx-out-0506.google.com with SMTP id h30so3155837wxd for ; Thu, 14 Sep 2006 08:51:41 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:user-agent:x-accept-language:mime-version:to:subject:content-type; b=X4b6bXtkqGqRy7yfs1qBTK7nD2nlxwMf2AkDfif54o61e0qm0j0KPNDEB3uio2H5jQbZlehWPFyAkIfH2ONrdcHDZCMN8H3Cv8/Kx2I6bwJuvV6x8I/9cjOL8O1stdw/KmFiF171tR4XrUhAPzd4b8/FqDl4Gdbfc1sWMryRurE= Received: by 10.70.29.7 with SMTP id c7mr12818166wxc; Thu, 14 Sep 2006 08:51:41 -0700 (PDT) Received: from ?10.0.1.104? ( [71.243.124.123]) by mx.gmail.com with ESMTP id i12sm1572680wxd.2006.09.14.08.51.40; Thu, 14 Sep 2006 08:51:40 -0700 (PDT) Message-ID: <45097A89.4060303@gmail.com> Date: Thu, 14 Sep 2006 11:51:37 -0400 From: Peter Watkins User-Agent: Mozilla Thunderbird 1.0.6 (X11/20050831) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org, Ralf Baechle Subject: [PATCH] Add cache info to /proc/cpuinfo Content-Type: multipart/mixed; boundary="------------080408080008000303090702" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12572 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: treestem@gmail.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------080408080008000303090702 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit This patch shows you more details about the cache using /proc/cpuinfo. It also shows the TLB page size. For example: system type : MIPS Malta processor : 0 cpu model : MIPS 20Kc V2.0 FPU V2.0 BogoMIPS : 478.20 wait instruction : no microsecond timers : yes tlb_entries : 48 64K pages icache size : 32K sets 256 ways 4 linesize 32 dcache size : 32K sets 256 ways 4 linesize 32 default cache policy : cached write-back extra interrupt vector : yes hardware watchpoint : yes ASEs implemented : mips3d VCED exceptions : not available VCEI exceptions : not available --------------080408080008000303090702 Content-Type: text/plain; name="0001-Add-cache-info-to-cpuinfo-display.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="0001-Add-cache-info-to-cpuinfo-display.txt" Date: Thu, 14 Sep 2006 11:24:51 -0400 Subject: [PATCH] Add cache info to cpuinfo display. --- arch/mips/kernel/proc.c | 34 +++++++++++++++++++++++++++++++++- 1 files changed, 33 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index d8beef1..54f4da3 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -92,6 +92,7 @@ static int show_cpuinfo(struct seq_file unsigned int version = current_cpu_data.processor_id; unsigned int fp_vers = current_cpu_data.fpu_id; unsigned long n = (unsigned long) v - 1; + unsigned long cache_size; char fmt [64]; #ifdef CONFIG_SMP @@ -118,7 +119,38 @@ #endif seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); seq_printf(m, "microsecond timers\t: %s\n", cpu_has_counter ? "yes" : "no"); - seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize); + seq_printf(m, "tlb_entries\t\t: %d %luK pages\n", current_cpu_data.tlbsize, + PAGE_SIZE/1024); + cache_size = current_cpu_data.icache.sets * + current_cpu_data.icache.ways * + current_cpu_data.icache.linesz; + if (cache_size) { + seq_printf(m, "icache size\t\t: %luK sets %d ways %d linesize %d\n", + cache_size/1024, current_cpu_data.icache.sets, + current_cpu_data.icache.ways, current_cpu_data.icache.linesz); + } + cache_size = current_cpu_data.dcache.sets * + current_cpu_data.dcache.ways * + current_cpu_data.dcache.linesz; + if (cache_size) { + seq_printf(m, "dcache size\t\t: %luK sets %d ways %d linesize %d\n", + cache_size/1024, current_cpu_data.dcache.sets, + current_cpu_data.dcache.ways, current_cpu_data.dcache.linesz); + } + cache_size = current_cpu_data.scache.sets * + current_cpu_data.scache.ways * + current_cpu_data.scache.linesz; + if (cache_size) { + seq_printf(m, "scache size\t\t: %luK sets %d ways %d linesize %d\n", + cache_size/1024, current_cpu_data.scache.sets, + current_cpu_data.scache.ways, current_cpu_data.scache.linesz); + } + /* In pgtable-bits.h we never use a write-through policy */ +#ifdef CONFIG_MIPS_UNCACHED + seq_printf(m, "default cache policy\t: uncached\n"); +#else + seq_printf(m, "default cache policy\t: cached write-back\n"); +#endif seq_printf(m, "extra interrupt vector\t: %s\n", cpu_has_divec ? "yes" : "no"); seq_printf(m, "hardware watchpoint\t: %s\n", -- 1.4.1 --------------080408080008000303090702-- From ralf@linux-mips.org Thu Sep 14 18:27:28 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Sep 2006 18:27:30 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:462 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20038903AbWINR12 (ORCPT ); Thu, 14 Sep 2006 18:27:28 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k8EHS6Aj002194; Thu, 14 Sep 2006 18:28:06 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k8EHS53t002193; Thu, 14 Sep 2006 18:28:05 +0100 Date: Thu, 14 Sep 2006 18:28:05 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, macro@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS Message-ID: <20060914172805.GA1756@linux-mips.org> References: <20060708.011245.82794581.anemo@mba.ocn.ne.jp> <20060709.011259.92587435.anemo@mba.ocn.ne.jp> <20060710.234010.07457279.anemo@mba.ocn.ne.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060710.234010.07457279.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12573 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jul 10, 2006 at 11:40:10PM +0900, Atsushi Nemoto wrote: > Add special short path for emulationg RDHWR which is used to support > TLS. The handle_tlbl synthesizer takes a care for > cpu_has_vtag_icache. I'm just wondering if we actually need such optimizations. Have you ran any application benchmarks? Ralf From ralf@linux-mips.org Thu Sep 14 19:10:01 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Sep 2006 19:10:03 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:40604 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20038922AbWINSKB (ORCPT ); Thu, 14 Sep 2006 19:10:01 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k8EIAcQe002889; Thu, 14 Sep 2006 19:10:38 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k8EIAbnB002888; Thu, 14 Sep 2006 19:10:37 +0100 Date: Thu, 14 Sep 2006 19:10:37 +0100 From: Ralf Baechle To: Russell King Cc: Sergei Shtylyov , Rodolfo Giometti , linux-mips@linux-mips.org Subject: Re: [PATCH] au1x00 serial real interrupt Message-ID: <20060914181037.GC2197@linux-mips.org> References: <20060522165244.GA16223@enneenne.com> <44FD9587.3030708@ru.mvista.com> <4502ED14.6080506@ru.mvista.com> <20060909163907.GA24012@flint.arm.linux.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060909163907.GA24012@flint.arm.linux.org.uk> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12574 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Sep 09, 2006 at 05:39:07PM +0100, Russell King wrote: > Well, if you need IRQ0 to be real then redefining is_real_interrupt() > is the correct way forward. > > However, Linus' policy is that IRQ0 shall be invalid at least on PCI > systems, and architectures _should_ remap their real IRQ0 to some other > number. Personally I don't like this. Hence why I prefer to give people > the option. I have no strong opinion either. In some cases not having interrupt 0 available sucks because Linux will have to use a different interrupt numbering than system documentation ... Ralf From ashlesha@kenati.com Thu Sep 14 22:57:06 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 14 Sep 2006 22:57:08 +0100 (BST) Received: from [69.90.147.196] ([69.90.147.196]:34460 "EHLO mail.kenati.com") by ftp.linux-mips.org with ESMTP id S20027711AbWINV5G (ORCPT ); Thu, 14 Sep 2006 22:57:06 +0100 Received: from [192.168.1.169] (adsl-71-130-109-177.dsl.snfc21.pacbell.net [71.130.109.177]) by mail.kenati.com (Postfix) with ESMTP id C30EBE404D; Thu, 14 Sep 2006 15:17:40 -0700 (PDT) Subject: Re: early_initcall From: Ashlesha Shintre Reply-To: ashlesha@kenati.com To: Ralf Baechle Cc: linux-mips@linux-mips.org In-Reply-To: <20060907033050.GA17965@linux-mips.org> References: <66910A579C9312469A7DF9ADB54A8B7D366028@exchange.ZeugmaSystems.local> <1157566247.6485.12.camel@sandbar.kenati.com> <20060907033050.GA17965@linux-mips.org> Content-Type: text/plain Date: Thu, 14 Sep 2006 15:05:05 -0700 Message-Id: <1158271505.7660.9.camel@sandbar.kenati.com> Mime-Version: 1.0 X-Mailer: Evolution 2.4.2.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12575 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ashlesha@kenati.com Precedence: bulk X-list: linux-mips Thank you for your email Ralf. The kernel now crashes inconsistently. Firstly when I load the image in YAMON and issue the go . command, it does not always give a machine exception. It seems to be stuck in the do_fast_cp0_gettimeoffset function, as the log buffer only contains this line recursively printed from the printk statement inserted in the function as below: static unsigned long cached_quotient=0; printk("INSIDE DO FAST CP0 GETTIMEOFFSET\n"); tmp = jiffies; When I step through the dissassembly code, do_fast_cp0_gettimeoffset function gets executed smoothly and the kernel crashed in the ways listed below: 1) After the 3rd iteration of the for (;;) loop in the parse_cmdline_early file, a machine exception was generated. -- If I step through the code in the for loop, all the 3 printk statments that I have put get executed sequentially. However if I only introduce one break point at the first printk statement and run through the loop, none of the statements are executed although control still comes back to the break point! Also, none of the if conditions in the for loop are ever satisfied. 2) In the same for loop -- between the 4th and 15th iteration the breakpoint at "c = *(from++);" is skipped and again the contents of the logbuf are bizzarely overwritten by the one printk("INSIDE DO FAST CP0 GETTIMEOFFSET\n"); statement! -- This happened 3 times. Any pointers? Thank you, Ashlesha. On Thu, 2006-09-07 at 05:30 +0200, Ralf Baechle wrote: > On Wed, Sep 06, 2006 at 11:10:47AM -0700, Ashlesha Shintre wrote: > > > I googled early_initcall and found a patch which basically adds this > > line to the /include/init.h file: > > > > #define early_initcall(fn) __define_initcall(".early1",fn) > > There is more infrastructure needed to get this to work. And in fact why > are you trying to get it to work at all - a direct call from setup_arch > to your early init function is trivial to do. > > > I built a kernel image with this new line included and now if I try > > executing it, the bootloader YAMON gives an exception error before it > > can even begin! Here is the dump: > > Such a dump could be from YAMON or in the very early phase of the kernel > initialization. > > A machine check means that an exception is generated due to duplicate > > TLB entries. I dont understand why the kernel crashes so early. > > There are also other implementation specified reasons that may result > in a machine check exception as well. > > > Also, what does the ".early1" mean? Is that a definition of a different > > segment in the init.h file? > > Section not segment. It's just a section name. > > > I checked output of the "readelf -a vmlinux" and found that the address > > for the early_initcall comes up about 5 times. I m not sure what each > > of the fields mean, so I have attached the above part of the readelf in > > a file called readelf. > > And if you had not quoted 50 lines of the previous message in this thread > but those lines from the readelf output we might actually tell you. > > Ralf From anemo@mba.ocn.ne.jp Fri Sep 15 04:09:16 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Sep 2006 04:09:20 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:38605 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20027576AbWIODJQ (ORCPT ); Fri, 15 Sep 2006 04:09:16 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Fri, 15 Sep 2006 12:09:15 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 762B52073D; Fri, 15 Sep 2006 12:09:08 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 6B5D5205D0; Fri, 15 Sep 2006 12:09:08 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k8F397W0015835; Fri, 15 Sep 2006 12:09:08 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Fri, 15 Sep 2006 12:09:07 +0900 (JST) Message-Id: <20060915.120907.96686013.nemoto@toshiba-tops.co.jp> To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, macro@linux-mips.org Subject: Re: [PATCH] fast path for rdhwr emulation for TLS From: Atsushi Nemoto In-Reply-To: <20060914172805.GA1756@linux-mips.org> References: <20060709.011259.92587435.anemo@mba.ocn.ne.jp> <20060710.234010.07457279.anemo@mba.ocn.ne.jp> <20060914172805.GA1756@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12576 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Thu, 14 Sep 2006 18:28:05 +0100, Ralf Baechle wrote: > > Add special short path for emulationg RDHWR which is used to support > > TLS. The handle_tlbl synthesizer takes a care for > > cpu_has_vtag_icache. > > I'm just wondering if we actually need such optimizations. Have you ran > any application benchmarks? I've measured time of NPTL pthread_mutex_lock/pthread_mutex_unlock loop. pthread_mutex_init(&m, NULL); gettimeofday(&start, NULL); for (i = 0; i < 1000000; i++) { pthread_mutex_lock(&m); pthread_mutex_unlock(&m); } gettimeofday(&end, NULL); Without optimization: 0.826407 sec / 1000000 loop With optimization: 0.415667 sec / 1000000 loop It would be worth to do. --- Atsushi Nemoto From carlos.mitidieri@sysgo.com Fri Sep 15 11:12:17 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Sep 2006 11:12:18 +0100 (BST) Received: from mail.sysgo.com ([62.8.134.5]:53769 "EHLO mail.sysgo.com") by ftp.linux-mips.org with ESMTP id S20037601AbWIOKMQ (ORCPT ); Fri, 15 Sep 2006 11:12:16 +0100 Received: from localhost (localhost [127.0.0.1]) by mail.sysgo.com (Postfix) with ESMTP id 6A92FCC19F for ; Fri, 15 Sep 2006 12:12:09 +0200 (CEST) Received: from mail.sysgo.com (localhost [127.0.0.1]) by localhost (AvMailGate-2.0.2-8) id 28706-19F1FBE3; Fri, 15 Sep 2006 12:12:09 +0200 Received: from donald.sysgo.com (unknown [172.20.1.30]) by mail.sysgo.com (Postfix) with ESMTP id E9FCFCC19E for ; Fri, 15 Sep 2006 12:12:08 +0200 (CEST) Received: by donald.sysgo.com (Postfix, from userid 65534) id ECF9526886D; Fri, 15 Sep 2006 12:12:08 +0200 (CEST) Received: from cam (unknown [172.40.1.200]) by donald.sysgo.com (Postfix) with ESMTP id A6035268701 for ; Fri, 15 Sep 2006 12:12:07 +0200 (CEST) From: Carlos Mitidieri To: linux-mips@linux-mips.org Subject: vmlinux and umon Date: Fri, 15 Sep 2006 12:12:16 +0200 User-Agent: KMail/1.8.2 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200609151212.16566.carlos.mitidieri@sysgo.com> X-AntiVirus: checked by AntiVir MailGate (version: 2.0.2-8; AVE: 7.2.0.16; VDF: 6.36.0.24; host: mailgate.sysgo.com) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12577 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: carlos.mitidieri@sysgo.com Precedence: bulk X-list: linux-mips Hi List, As I posted some days ago, I am porting the kernel 2.6.15 to a CSB655 board. I am trying to boot a vmlinux image from the umon that came with the board without sucess: The kernel crashes when setup_arch() is called in start_kernel() function (init/main.c), without any output to the console from the printk()'s that are just before setup_arch(). What I could devise until now is that there is a mismatch between the memory mappings of umon and linux. The umon sets RAMBASE to 0xa0000000, and loads applications to addresses above 0xa0300000, only. Linux-mips sets PAGE_OFFSET to 0x80000000 and assumes that the kernel is loaded in KSEG0 (correct me please if I am saying something that is not true). Now, if set LOADADD e.g. to 0xa0400000 in arch/mips/Makefile, the vmlinux booting fails for a more or less obvious reason (mismatch to PAGE_OFFSET). But if I adjust the PAGE_OFFSET to match the umon's mapping (i.e. to 0xa000 0000) the kernel booting. In both cases at the same point described above. What am I missing here? Thanks in advance and best regards. -- Carlos Mitidieri SYSGO AG - Office Ulm From anemo@mba.ocn.ne.jp Fri Sep 15 15:08:35 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Sep 2006 15:08:41 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:56831 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20037726AbWIOOIf (ORCPT ); Fri, 15 Sep 2006 15:08:35 +0100 Received: from localhost (p4242-ipad34funabasi.chiba.ocn.ne.jp [124.85.61.242]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id CD4FFB6AE; Fri, 15 Sep 2006 23:08:27 +0900 (JST) Date: Fri, 15 Sep 2006 23:10:29 +0900 (JST) Message-Id: <20060915.231029.74752822.anemo@mba.ocn.ne.jp> To: treestem@gmail.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] Add cache info to /proc/cpuinfo From: Atsushi Nemoto In-Reply-To: <45097A89.4060303@gmail.com> References: <45097A89.4060303@gmail.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12578 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Thu, 14 Sep 2006 11:51:37 -0400, Peter Watkins wrote: > This patch shows you more details about the cache using /proc/cpuinfo. > It also shows the TLB page size. Unfortunately this patch will not work for users of c-r3k.c and c-sb1.c. These does not fill correct values to cpu_data for now. Also, current_cpu_data should not be used in show_cpuinfo. You can use cpu_data[n] instead. # I know now show_cpuinfo _is_ using current_cpu_data in some place. # These should be fixed. A patch have been sent to Ralf already. --- Atsushi Nemoto From imipak@yahoo.com Fri Sep 15 21:39:38 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Sep 2006 21:39:43 +0100 (BST) Received: from web31506.mail.mud.yahoo.com ([68.142.198.135]:12696 "HELO web31506.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20037845AbWIOUji (ORCPT ); Fri, 15 Sep 2006 21:39:38 +0100 Received: (qmail 80611 invoked by uid 60001); 15 Sep 2006 20:39:31 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=OWj05PFDDQ6/9kHLDZ+cu9Pj9vr5XVLegPY854UKl5RW2c04xeymUhl+8CJLery9oSu54TYlTY74ZsFDTp6lVqCl5K27jMi0klCdikk6VSMrv16SXQsa+GFPLm6aLLp1T4GmVN6sh6c4aDtysOEaYSqprjN9DLUz0A8vf/cn/F8= ; Message-ID: <20060915203931.80609.qmail@web31506.mail.mud.yahoo.com> Received: from [70.103.67.194] by web31506.mail.mud.yahoo.com via HTTP; Fri, 15 Sep 2006 13:39:31 PDT Date: Fri, 15 Sep 2006 13:39:31 -0700 (PDT) From: Jonathan Day Subject: Kernel debugging question To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12579 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips Hi, So that I can stop pestering the list with kernel boot-time problems that (from the looks of it) aren't easily reproduced or tracked, I'd like a few suggestions on how to diagnose these sorts of problems myself. Specifically, there seem to be two areas that jam up most often - kernel initialization and between freeing up the memory & running the MIPS FPU emulator. Are there any specific debug flags I can set in the kernel that will dump to the console (which is on the serial port) more detailed information on what is going on at these times? Alternatively, I've had problems getting the kernel to link to a debugger live (eg: gdb), but presumably there are ways to do effective non-live debugging. What experience do people have with doing this? Jonathan Day __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From imipak@yahoo.com Fri Sep 15 23:11:47 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Sep 2006 23:11:51 +0100 (BST) Received: from web31504.mail.mud.yahoo.com ([68.142.198.133]:65426 "HELO web31504.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20037875AbWIOWLr (ORCPT ); Fri, 15 Sep 2006 23:11:47 +0100 Received: (qmail 69176 invoked by uid 60001); 15 Sep 2006 22:11:41 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=EL6EMe/0HiXDtiyEJhFWbKsro4MHywYRIHVWaLizVTBNc6hR40s9eHiMs9UkcHGNE92I2YY44AgunMqUyqqFezh5NfVNpogmYUBCtnsnmJfpb3zkgHTwqceIyfjejyW4bKerJBzQVQqrVzcYgeWbb9B47zZWrJxazH8Uc90a888= ; Message-ID: <20060915221141.69174.qmail@web31504.mail.mud.yahoo.com> Received: from [70.103.67.194] by web31504.mail.mud.yahoo.com via HTTP; Fri, 15 Sep 2006 15:11:40 PDT Date: Fri, 15 Sep 2006 15:11:40 -0700 (PDT) From: Jonathan Day Subject: Kernel debugging contd. To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12580 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips Ok, here's the console output with virtually every Linux debug option I could find enabled. It softlocks (no console activity, but kernel pings) after freeing memory. Any thoughts on using the magic key over minicom would also be welcome. The thing that stands out the most is line 864000, where we have an IRQ handler mismatch and a call trace. Suggestions, anyone? CFE version 1.2.5 for SENTOSA (64bit,MP,BE,MIPS) Build Date: Tue Feb 28 15:32:44 PST 2006 (elhoward@localhost.localdomain) Copyright (C) 2000,2001,2002,2003,2004,2005 Broadcom Corporation. Initializing Arena. Initializing PCI. [normal] HyperTransport: 400 MHz HyperTransport not initialized: InitDone not set SriCmd 5221 TXNum 0000ffff TxDen 10 RxNum 0000ffff RxDen 10 ErrCtl 00000000 LDTCmd 20010008 LDTCfg 000000c0 LDTFreq 00000211 Initializing Devices. SENTOSA board revision 2 sbeth: found phy 1, vendor 000818 part 0E sbeth: found phy 1, vendor 000818 part 0E PCIIDE: 0 controllers found Config switch: 2 CPU: BCM1250 B2 L2 Cache Status: OK Wafer ID: 0x92CEE019 [Lot 9395, Wafer 23] Manuf Test: Bin A [2CPU_FI_FD_F2 (OK)] SysCfg: 0000000024C20800 [PLL_DIV: 16, IOB0_DIV: CPUCLK/4, IOB1_DIV: CPUCLK/3] CPU type 0x1040102: 800MHz Total memory: 0x10000000 bytes (256MB) Total memory used by CFE: 0x8FEA8000 - 0x8FFFF080 (1405056) Initialized Data: 0x8FEF70B8 - 0x8FEFCA00 (22856) BSS Area: 0x8FEFCA00 - 0x8FEFD070 (1648) Local Heap: 0x8FEFD080 - 0x8FFFD080 (1048576) Stack Area: 0x8FFFD080 - 0x8FFFF080 (8192) Text (code) segment: 0x8FEA8000 - 0x8FEF68B1 (321713) Boot area (physical): 0x0FE67000 - 0x0FEA7000 Relocation Factor: I:F02A8000 - D:F02A8000 sbeth: found phy 1, vendor 000818 part 0E eth0: Link speed: 100BaseT FDX Device eth0: hwaddr 00-02-4C-FD-0D-3C, ipaddr 10.1.3.148, mask 255.255.255.0 gateway 10.1.3.1, nameserver 10.1.3.10, domain lightfleet Loader:elf Filesys:tftp Dev:eth0 File:10.1.3.187:vmlinux.sentosa Options:(null) eth0: Link speed: 100BaseT FDX 0xffffffff80680480/269184 Entry at 0x80640000 Closing network. Starting program at 0x80640000 Broadcom SiByte BCM1250 B2 @ 800 MHz (SB1 rev 2) Board type: SiByte BCM91250E (Sentosa) [17179569.184000] Linux version 2.6.18-rc7-lightfleet-0.3-g50125477 (root@10.1.3.148) (gcc version 4.1.1) #4 SMP Fri Sep 15 19:37:13 UTC 2006 [17179569.184000] CPU revision is: 01040102 [17179569.184000] FPU revision is: 000f0102 [17179569.184000] swarm setup: M41T81 RTC detected. [17179569.184000] This kernel optimized for board runs with CFE [17179569.184000] Determined physical RAM map: [17179569.184000] memory: 000000000fea7e00 @ 0000000000000000 (usable) [17179569.184000] Detected 1 available secondary CPU(s) [17179569.184000] Built 1 zonelists. Total pages: 65191 [17179569.184000] Kernel command line: ip=any rw nfsroot=10.1.3.187:/home/developer root=/dev/nfs serial=1,115200n8 [17179569.184000] Primary instruction cache 32kB, 4-way, linesize 32 bytes. [17179569.184000] Primary data cache 32kB, 4-way, linesize 32 bytes. [17179569.184000] Synthesized TLB refill handler (40 instructions). [17179569.184000] Synthesized TLB load handler fastpath (54 instructions). [17179569.184000] Synthesized TLB store handler fastpath (49 instructions). [17179569.184000] Synthesized TLB modify handler fastpath (48 instructions). [17179569.184000] PID hash table entries: 1024 (order: 10, 8192 bytes) [17179569.184000] Using 512.000 MHz high precision timer. [17179569.184000] start_kernel(): bug: interrupts were enabled early [17179569.188000] ------------------------ [17179569.192000] | Locking API testsuite: [17179569.192000] ---------------------------------------------------------------------------- [17179569.196000] | spin |wlock |rlock |mutex | wsem | rsem | [17179569.200000] -------------------------------------------------------------------------- [17179569.204000] A-A deadlock:failed|failed| ok |failed|failed|failed| [17179569.212000] A-B-B-A deadlock:failed|failed| ok |failed|failed|failed| [17179569.220000] A-B-B-C-C-A deadlock:failed|failed| ok |failed|failed|failed| [17179569.228000] A-B-C-A-B-C deadlock:failed|failed| ok |failed|failed|failed| [17179569.236000] A-B-B-C-C-D-D-A deadlock:failed|failed| ok |failed|failed|failed| [17179569.244000] A-B-C-D-B-D-D-A deadlock:failed|failed| ok |failed|failed|failed| [17179569.252000] A-B-C-D-B-C-D-A deadlock:failed|failed| ok |failed|failed|failed| [17179569.260000] double unlock: ok | ok |failed| ok |failed|failed| [17179569.268000] initialize held:failed|failed|failed|failed|failed|failed| [17179569.276000] bad unlock order: ok | ok | ok | ok | ok | ok | [17179569.284000] -------------------------------------------------------------------------- [17179569.288000] recursive read-lock: | ok | |failed| [17179569.296000] recursive read-lock #2: | ok | |failed| [17179569.300000] mixed read-write-lock: |failed| |failed| [17179569.308000] mixed write-read-lock: |failed| |failed| [17179569.316000] -------------------------------------------------------------------------- [17179569.320000] hard-irqs-on + irq-safe-A/12:failed|failed| ok | [17179569.324000] soft-irqs-on + irq-safe-A/12:failed|failed| ok | [17179569.332000] hard-irqs-on + irq-safe-A/21:failed|failed| ok | [17179569.340000] soft-irqs-on + irq-safe-A/21:failed|failed| ok | [17179569.344000] sirq-safe-A => hirqs-on/12:failed|failed| ok | [17179569.352000] sirq-safe-A => hirqs-on/21:failed|failed| ok | [17179569.356000] hard-safe-A + irqs-on/12:failed|failed| ok | [17179569.364000] soft-safe-A + irqs-on/12:failed|failed| ok | [17179569.372000] hard-safe-A + irqs-on/21:failed|failed| ok | [17179569.376000] soft-safe-A + irqs-on/21:failed|failed| ok | [17179569.384000] hard-safe-A + unsafe-B #1/123:failed|failed| ok | [17179569.388000] soft-safe-A + unsafe-B #1/123:failed|failed| ok | [17179569.392000] hard-safe-A + unsafe-B #1/132:failed|failed| ok | [17179569.400000] soft-safe-A + unsafe-B #1/132:failed|failed| ok | [17179569.404000] hard-safe-A + unsafe-B #1/213:failed|failed| ok | [17179569.412000] soft-safe-A + unsafe-B #1/213:failed|failed| ok | [17179569.416000] hard-safe-A + unsafe-B #1/231:failed|failed| ok | [17179569.420000] soft-safe-A + unsafe-B #1/231:failed|failed| ok | [17179569.428000] hard-safe-A + unsafe-B #1/312:failed|failed| ok | [17179569.432000] soft-safe-A + unsafe-B #1/312:failed|failed| ok | [17179569.440000] hard-safe-A + unsafe-B #1/321:failed|failed| ok | [17179569.448000] soft-safe-A + unsafe-B #1/321:failed|failed| ok | [17179569.452000] hard-safe-A + unsafe-B #2/123:failed|failed| ok | [17179569.460000] soft-safe-A + unsafe-B #2/123:failed|failed| ok | [17179569.464000] hard-safe-A + unsafe-B #2/132:failed|failed| ok | [17179569.472000] soft-safe-A + unsafe-B #2/132:failed|failed| ok | [17179569.480000] hard-safe-A + unsafe-B #2/213:failed|failed| ok | [17179569.484000] soft-safe-A + unsafe-B #2/213:failed|failed| ok | [17179569.492000] hard-safe-A + unsafe-B #2/231:failed|failed| ok | [17179569.496000] soft-safe-A + unsafe-B #2/231:failed|failed| ok | [17179569.500000] hard-safe-A + unsafe-B #2/312:failed|failed| ok | [17179569.508000] soft-safe-A + unsafe-B #2/312:failed|failed| ok | [17179569.512000] hard-safe-A + unsafe-B #2/321:failed|failed| ok | [17179569.520000] soft-safe-A + unsafe-B #2/321:failed|failed| ok | [17179569.524000] hard-irq lock-inversion/123:failed|failed| ok | [17179569.528000] soft-irq lock-inversion/123:failed|failed| ok | [17179569.536000] hard-irq lock-inversion/132:failed|failed| ok | [17179569.540000] soft-irq lock-inversion/132:failed|failed| ok | [17179569.548000] hard-irq lock-inversion/213:failed|failed| ok | [17179569.556000] soft-irq lock-inversion/213:failed|failed| ok | [17179569.560000] hard-irq lock-inversion/231:failed|failed| ok | [17179569.568000] soft-irq lock-inversion/231:failed|failed| ok | [17179569.572000] hard-irq lock-inversion/312:failed|failed| ok | [17179569.576000] soft-irq lock-inversion/312:failed|failed| ok | [17179569.584000] hard-irq lock-inversion/321:failed|failed| ok | [17179569.588000] soft-irq lock-inversion/321:failed|failed| ok | [17179569.596000] hard-irq read-recursion/123: ok | [17179569.600000] soft-irq read-recursion/123: ok | [17179569.604000] hard-irq read-recursion/132: ok | [17179569.608000] soft-irq read-recursion/132: ok | [17179569.612000] hard-irq read-recursion/213: ok | [17179569.616000] soft-irq read-recursion/213: ok | [17179569.620000] hard-irq read-recursion/231: ok | [17179569.624000] soft-irq read-recursion/231: ok | [17179569.628000] hard-irq read-recursion/312: ok | [17179569.636000] soft-irq read-recursion/312: ok | [17179569.640000] hard-irq read-recursion/321: ok | [17179569.644000] soft-irq read-recursion/321: ok | [17179569.652000] -------------------------------------------------------- [17179569.656000] 142 out of 218 testcases failed, as expected. | [17179569.660000] ---------------------------------------------------- [17179569.664000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes) [17179569.668000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes) [17179569.700000] Memory: 249464k/260764k available (4112k kernel code, 10976k reserved, 1260k data, 260k init, 0k highmem) [17179569.804000] Mount-cache hash table entries: 256 [17179569.808000] Checking for 'wait' instruction... unavailable. [17179569.816000] Checking for the multiply/shift bug... no. [17179569.820000] Checking for the daddi bug... no. [17179569.824000] Checking for the daddiu bug... no. [17179569.832000] CPU revision is: 03040102 [17179569.832000] FPU revision is: 000f0102 [17179569.832000] Primary instruction cache 32kB, 4-way, linesize 32 bytes. [17179569.832000] Primary data cache 32kB, 4-way, linesize 32 bytes. [17179569.832000] Synthesized TLB refill handler (40 instructions). [17179569.932000] Brought up 2 CPUs [17179570.248000] migration_cost=8000 [17179570.260000] NET: Registered protocol family 16 [17179570.272000] Generic PHY: Registered new driver [17179570.280000] SCSI subsystem initialized [17179570.284000] usbcore: registered new driver usbfs [17179570.292000] usbcore: registered new driver hub [17179570.304000] NET: Registered protocol family 2 [17179570.352000] IP route cache hash table entries: 2048 (order: 2, 16384 bytes) [17179570.360000] TCP established hash table entries: 8192 (order: 6, 262144 bytes) [17179570.368000] TCP bind hash table entries: 4096 (order: 5, 131072 bytes) [17179570.372000] TCP: Hash tables configured (established 8192 bind 4096) [17179570.376000] TCP reno registered [17179570.420000] Initializing RT-Tester: OK [17179570.428000] JFS: nTxBlock = 1951, nTxLock = 15611 [17179570.436000] Installing v9fs 9P2000 file system support [17179570.444000] Initializing Cryptographic API [17179570.448000] io scheduler noop registered [17179570.452000] io scheduler anticipatory registered [17179570.456000] io scheduler deadline registered (default) [17179570.460000] io scheduler cfq registered [17179570.840000] IRQ handler type mismatch for IRQ 8 [17179570.844000] Call Trace: [17179570.848000] [] dump_stack+0x18/0x58 [17179570.852000] [] setup_irq+0x1b0/0x2d8 [17179570.856000] [] request_irq+0x108/0x128 [17179570.864000] [] rtc_init+0xb4/0x5b8 [17179570.868000] [] init+0x29c/0x6c0 [17179570.872000] [] kernel_thread_helper+0x10/0x18 [17179570.880000] [17179570.880000] rtc: IRQ 8 is not free. [17179570.884000] RAMDISK driver initialized: 1 RAM disks of 4096K size 1024 blocksize [17179570.900000] loop: loaded (max 8 devices) [17179570.904000] nbd: registered device at major 43 [17179570.924000] Ethernet Channel Bonding Driver: v3.0.3 (March 23, 2006) [17179570.932000] bonding: Warning: either miimon or arp_interval and arp_ip_target module parameters must be specified, otherwise bonding will not detect li. [17179570.952000] eth0: enabling TCP rcv checksum [17179570.956000] eth0: SiByte Ethernet at 0x10064000, address: 00:02:4C:FD:0D:3C [17179570.964000] eth1: enabling TCP rcv checksum [17179570.968000] eth1: SiByte Ethernet at 0x10065000, address: 00:02:4C:FD:0D:3D [17179570.976000] Equalizer2002: Simon Janes (simon@ncm.com) and David S. Miller (davem@redhat.com) [17179570.988000] Initializing USB Mass Storage driver... [17179570.996000] usbcore: registered new driver usb-storage [17179571.000000] USB Mass Storage support registered. [17179571.004000] usbcore: registered new driver libusual [17179571.012000] usbcore: registered new driver usbhid [17179571.016000] drivers/usb/input/hid-core.c: v2.6:USB HID core driver [17179571.024000] mice: PS/2 mouse device common for all mice [17179571.032000] rtc-test rtc-test.0: rtc intf: sysfs [17179571.036000] rtc-test rtc-test.0: rtc intf: proc [17179571.040000] rtc-test rtc-test.0: rtc intf: dev (254:0) [17179571.048000] rtc-test rtc-test.0: rtc core: registered test as rtc0 [17179571.052000] rtc-test rtc-test.1: rtc intf: sysfs [17179571.060000] rtc-test rtc-test.1: rtc intf: dev (254:1) [17179571.064000] rtc-test rtc-test.1: rtc core: registered test as rtc1 [17179571.072000] i2c /dev entries driver [17179571.076000] i2c-swarm.o: i2c SMBus adapter module for SiByte board [17179571.092000] pktgen v2.67: Packet Generator for packet performance testing. [17179571.100000] netem: version 1.2 [17179571.104000] NET: Registered protocol family 1 [17179571.108000] NET: Registered protocol family 10 [17179571.116000] lo: Disabled Privacy Extensions [17179571.120000] IPv6 over IPv4 tunneling driver [17179571.124000] NET: Registered protocol family 17 [17179571.148000] CCID: Registered CCID 3 (ccid3) [17179571.152000] CCID: Registered CCID 2 (ccid2) [17179571.180000] SCTP: Hash tables configured (established 2048 bind 2048) [17179571.184000] TIPC: Activated (version 1.6.1 compiled Sep 15 2006 19:32:28) [17179571.196000] NET: Registered protocol family 30 [17179571.200000] TIPC: Started in single node mode [17179571.204000] rtc-test rtc-test.0: setting the system clock to 2006-09-15 19:53:10 (1158349990) [17179571.716000] ADDRCONF(NETDEV_UP): bond0: link is not ready [17179571.720000] eth0: found phy 1, vendor 000818 part 0e [17179571.728000] eth0: Link speed: 100BaseT FDX [17179571.732000] eth1: found phy 1, vendor 000818 part 0e [17179572.744000] Sending DHCP requests .,. OK [17179578.444000] IP-Config: Got DHCP answer from 0.0.0.0, my address is 10.1.3.148 [17179578.496000] IP-Config: Complete: [17179578.500000] device=eth0, addr=10.1.3.148, mask=255.255.255.0, gw=10.1.3.1, [17179578.508000] host=10.1.3.148, domain=lightfleet, nis-domain=(none), [17179578.512000] bootserver=0.0.0.0, rootserver=10.1.3.187, rootpath= [17179578.520000] Looking up port of RPC 100003/2 on 10.1.3.187 [17179578.532000] Looking up port of RPC 100005/1 on 10.1.3.187 [17179578.552000] VFS: Mounted root (nfs filesystem). [17179578.560000] Freeing unused kernel memory: 260k freed __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From mark.e.mason@broadcom.com Fri Sep 15 23:55:35 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 15 Sep 2006 23:55:37 +0100 (BST) Received: from mms2.broadcom.com ([216.31.210.18]:59402 "EHLO mms2.broadcom.com") by ftp.linux-mips.org with ESMTP id S20037883AbWIOWzf convert rfc822-to-8bit (ORCPT ); Fri, 15 Sep 2006 23:55:35 +0100 Received: from 10.10.64.154 by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.2.0)); Fri, 15 Sep 2006 15:55:13 -0700 X-Server-Uuid: D9EB6F12-1469-4C1C-87A2-5E4C0D6F9D06 Received: by mail-irva-10.broadcom.com (Postfix, from userid 47) id 6EC7A2B1; Fri, 15 Sep 2006 15:55:12 -0700 (PDT) Received: from mail-irva-8.broadcom.com (mail-irva-8 [10.10.64.221]) by mail-irva-10.broadcom.com (Postfix) with ESMTP id DFCE62B0; Fri, 15 Sep 2006 15:55:10 -0700 (PDT) Received: from mail-sj1-12.sj.broadcom.com (mail-sj1-12.sj.broadcom.com [10.16.128.215]) by mail-irva-8.broadcom.com (MOS 3.7.5a-GA) with ESMTP id EFE01288; Fri, 15 Sep 2006 15:54:10 -0700 (PDT) Received: from NT-SJCA-0750.brcm.ad.broadcom.com (nt-sjca-0750 [10.16.192.220]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 3D36720503; Fri, 15 Sep 2006 15:54:10 -0700 (PDT) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Subject: RE: Kernel debugging contd. Date: Fri, 15 Sep 2006 15:54:06 -0700 Message-ID: <7E000E7F06B05C49BDBB769ADAF44D070111E24B@NT-SJCA-0750.brcm.ad.broadcom.com> In-Reply-To: <20060915221141.69174.qmail@web31504.mail.mud.yahoo.com> Thread-Topic: Kernel debugging contd. Thread-Index: AcbZFAx6o7V2PcqYSEm0ARm+DYAUEQABaKhA From: "Mark E Mason" To: "Jonathan Day" , linux-mips@linux-mips.org X-TMWD-Spam-Summary: SEV=1.1; DFV=A2006091509; IFV=2.0.6,4.0-7; RPD=4.00.0004; RPDID=303030312E30413031303230322E34353042324439302E303030412D452D42494266314252712B51595268337955544B6A5A6E413D3D; ENG=IBF; TS=20060915225516; CAT=NONE; CON=NONE; X-MMS-Spam-Filter-ID: A2006091509_4.00.0004_2.0.6,4.0-7 X-WSS-ID: 6915F0DA3887106945-02-01 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12581 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mark.e.mason@broadcom.com Precedence: bulk X-list: linux-mips Hello, FWIW - this is the same place my boards are hanging (right after freeing kernel memory). I'd tracked it down to the commit that changed the cache/page handling for the sibyte parts from the sb1 specific to the generic codes -- but haven't found time to look into it further as yet. /Mark > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Jonathan Day > Sent: Friday, September 15, 2006 3:12 PM > To: linux-mips@linux-mips.org > Subject: Kernel debugging contd. > > Ok, here's the console output with virtually every > Linux debug option I could find enabled. It softlocks > (no console activity, but kernel pings) after freeing > memory. Any thoughts on using the magic key over > minicom would also be welcome. The thing that stands > out the most is line 864000, where we have an IRQ > handler mismatch and a call trace. > > Suggestions, anyone? > > CFE version 1.2.5 for SENTOSA (64bit,MP,BE,MIPS) > Build Date: Tue Feb 28 15:32:44 PST 2006 > (elhoward@localhost.localdomain) > Copyright (C) 2000,2001,2002,2003,2004,2005 Broadcom > Corporation. > > Initializing Arena. > Initializing PCI. [normal] > HyperTransport: 400 MHz > HyperTransport not initialized: InitDone not set > SriCmd 5221 > TXNum 0000ffff TxDen 10 RxNum 0000ffff RxDen 10 > ErrCtl 00000000 > LDTCmd 20010008 LDTCfg 000000c0 LDTFreq 00000211 > Initializing Devices. > SENTOSA board revision 2 > sbeth: found phy 1, vendor 000818 part 0E > sbeth: found phy 1, vendor 000818 part 0E > PCIIDE: 0 controllers found > Config switch: 2 > CPU: BCM1250 B2 > L2 Cache Status: OK > Wafer ID: 0x92CEE019 [Lot 9395, Wafer 23] > Manuf Test: Bin A [2CPU_FI_FD_F2 (OK)] > SysCfg: 0000000024C20800 [PLL_DIV: 16, IOB0_DIV: > CPUCLK/4, IOB1_DIV: CPUCLK/3] > CPU type 0x1040102: 800MHz > Total memory: 0x10000000 bytes (256MB) > > Total memory used by CFE: 0x8FEA8000 - 0x8FFFF080 > (1405056) > Initialized Data: 0x8FEF70B8 - 0x8FEFCA00 > (22856) > BSS Area: 0x8FEFCA00 - 0x8FEFD070 > (1648) > Local Heap: 0x8FEFD080 - 0x8FFFD080 > (1048576) > Stack Area: 0x8FFFD080 - 0x8FFFF080 > (8192) > Text (code) segment: 0x8FEA8000 - 0x8FEF68B1 > (321713) > Boot area (physical): 0x0FE67000 - 0x0FEA7000 > Relocation Factor: I:F02A8000 - D:F02A8000 > > sbeth: found phy 1, vendor 000818 part 0E > eth0: Link speed: 100BaseT FDX > Device eth0: hwaddr 00-02-4C-FD-0D-3C, ipaddr > 10.1.3.148, mask 255.255.255.0 > gateway 10.1.3.1, nameserver 10.1.3.10, domain > lightfleet > Loader:elf Filesys:tftp Dev:eth0 > File:10.1.3.187:vmlinux.sentosa Options:(null) > eth0: Link speed: 100BaseT FDX > 0xffffffff80680480/269184 Entry at 0x80640000 > Closing network. > Starting program at 0x80640000 > > Broadcom SiByte BCM1250 B2 @ 800 MHz (SB1 rev 2) > Board type: SiByte BCM91250E (Sentosa) > [17179569.184000] Linux version > 2.6.18-rc7-lightfleet-0.3-g50125477 (root@10.1.3.148) > (gcc version 4.1.1) #4 SMP Fri Sep 15 19:37:13 UTC > 2006 > [17179569.184000] CPU revision is: 01040102 > [17179569.184000] FPU revision is: 000f0102 > [17179569.184000] swarm setup: M41T81 RTC detected. > [17179569.184000] This kernel optimized for board runs > with CFE > [17179569.184000] Determined physical RAM map: > [17179569.184000] memory: 000000000fea7e00 @ > 0000000000000000 (usable) > [17179569.184000] Detected 1 available secondary > CPU(s) > [17179569.184000] Built 1 zonelists. Total pages: > 65191 > [17179569.184000] Kernel command line: ip=any rw > nfsroot=10.1.3.187:/home/developer root=/dev/nfs > serial=1,115200n8 > [17179569.184000] Primary instruction cache 32kB, > 4-way, linesize 32 bytes. > [17179569.184000] Primary data cache 32kB, 4-way, > linesize 32 bytes. > [17179569.184000] Synthesized TLB refill handler (40 > instructions). > [17179569.184000] Synthesized TLB load handler > fastpath (54 instructions). > [17179569.184000] Synthesized TLB store handler > fastpath (49 instructions). > [17179569.184000] Synthesized TLB modify handler > fastpath (48 instructions). > [17179569.184000] PID hash table entries: 1024 (order: > 10, 8192 bytes) > [17179569.184000] Using 512.000 MHz high precision > timer. > [17179569.184000] start_kernel(): bug: interrupts were > enabled early > [17179569.188000] ------------------------ > [17179569.192000] | Locking API testsuite: > [17179569.192000] > -------------------------------------------------------------- > -------------- > [17179569.196000] | > spin |wlock |rlock |mutex | wsem | rsem | > [17179569.200000] > -------------------------------------------------------------- > ------------ > [17179569.204000] A-A > deadlock:failed|failed| ok |failed|failed|failed| > [17179569.212000] A-B-B-A > deadlock:failed|failed| ok |failed|failed|failed| > [17179569.220000] A-B-B-C-C-A > deadlock:failed|failed| ok |failed|failed|failed| > [17179569.228000] A-B-C-A-B-C > deadlock:failed|failed| ok |failed|failed|failed| > [17179569.236000] A-B-B-C-C-D-D-A > deadlock:failed|failed| ok |failed|failed|failed| > [17179569.244000] A-B-C-D-B-D-D-A > deadlock:failed|failed| ok |failed|failed|failed| > [17179569.252000] A-B-C-D-B-C-D-A > deadlock:failed|failed| ok |failed|failed|failed| > [17179569.260000] double unlock: > ok | ok |failed| ok |failed|failed| > [17179569.268000] initialize > held:failed|failed|failed|failed|failed|failed| > [17179569.276000] bad unlock order: > ok | ok | ok | ok | ok | ok | > [17179569.284000] > -------------------------------------------------------------- > ------------ > [17179569.288000] recursive read-lock: > | ok | |failed| > [17179569.296000] recursive read-lock #2: > | ok | |failed| > [17179569.300000] mixed read-write-lock: > |failed| |failed| > [17179569.308000] mixed write-read-lock: > |failed| |failed| > [17179569.316000] > -------------------------------------------------------------- > ------------ > [17179569.320000] hard-irqs-on + > irq-safe-A/12:failed|failed| ok | > [17179569.324000] soft-irqs-on + > irq-safe-A/12:failed|failed| ok | > [17179569.332000] hard-irqs-on + > irq-safe-A/21:failed|failed| ok | > [17179569.340000] soft-irqs-on + > irq-safe-A/21:failed|failed| ok | > [17179569.344000] sirq-safe-A => > hirqs-on/12:failed|failed| ok | > [17179569.352000] sirq-safe-A => > hirqs-on/21:failed|failed| ok | > [17179569.356000] hard-safe-A + > irqs-on/12:failed|failed| ok | > [17179569.364000] soft-safe-A + > irqs-on/12:failed|failed| ok | > [17179569.372000] hard-safe-A + > irqs-on/21:failed|failed| ok | > [17179569.376000] soft-safe-A + > irqs-on/21:failed|failed| ok | > [17179569.384000] hard-safe-A + unsafe-B > #1/123:failed|failed| ok | > [17179569.388000] soft-safe-A + unsafe-B > #1/123:failed|failed| ok | > [17179569.392000] hard-safe-A + unsafe-B > #1/132:failed|failed| ok | > [17179569.400000] soft-safe-A + unsafe-B > #1/132:failed|failed| ok | > [17179569.404000] hard-safe-A + unsafe-B > #1/213:failed|failed| ok | > [17179569.412000] soft-safe-A + unsafe-B > #1/213:failed|failed| ok | > [17179569.416000] hard-safe-A + unsafe-B > #1/231:failed|failed| ok | > [17179569.420000] soft-safe-A + unsafe-B > #1/231:failed|failed| ok | > [17179569.428000] hard-safe-A + unsafe-B > #1/312:failed|failed| ok | > [17179569.432000] soft-safe-A + unsafe-B > #1/312:failed|failed| ok | > [17179569.440000] hard-safe-A + unsafe-B > #1/321:failed|failed| ok | > [17179569.448000] soft-safe-A + unsafe-B > #1/321:failed|failed| ok | > [17179569.452000] hard-safe-A + unsafe-B > #2/123:failed|failed| ok | > [17179569.460000] soft-safe-A + unsafe-B > #2/123:failed|failed| ok | > [17179569.464000] hard-safe-A + unsafe-B > #2/132:failed|failed| ok | > [17179569.472000] soft-safe-A + unsafe-B > #2/132:failed|failed| ok | > [17179569.480000] hard-safe-A + unsafe-B > #2/213:failed|failed| ok | > [17179569.484000] soft-safe-A + unsafe-B > #2/213:failed|failed| ok | > [17179569.492000] hard-safe-A + unsafe-B > #2/231:failed|failed| ok | > [17179569.496000] soft-safe-A + unsafe-B > #2/231:failed|failed| ok | > [17179569.500000] hard-safe-A + unsafe-B > #2/312:failed|failed| ok | > [17179569.508000] soft-safe-A + unsafe-B > #2/312:failed|failed| ok | > [17179569.512000] hard-safe-A + unsafe-B > #2/321:failed|failed| ok | > [17179569.520000] soft-safe-A + unsafe-B > #2/321:failed|failed| ok | > [17179569.524000] hard-irq > lock-inversion/123:failed|failed| ok | > [17179569.528000] soft-irq > lock-inversion/123:failed|failed| ok | > [17179569.536000] hard-irq > lock-inversion/132:failed|failed| ok | > [17179569.540000] soft-irq > lock-inversion/132:failed|failed| ok | > [17179569.548000] hard-irq > lock-inversion/213:failed|failed| ok | > [17179569.556000] soft-irq > lock-inversion/213:failed|failed| ok | > [17179569.560000] hard-irq > lock-inversion/231:failed|failed| ok | > [17179569.568000] soft-irq > lock-inversion/231:failed|failed| ok | > [17179569.572000] hard-irq > lock-inversion/312:failed|failed| ok | > [17179569.576000] soft-irq > lock-inversion/312:failed|failed| ok | > [17179569.584000] hard-irq > lock-inversion/321:failed|failed| ok | > [17179569.588000] soft-irq > lock-inversion/321:failed|failed| ok | > [17179569.596000] hard-irq read-recursion/123: > ok | > [17179569.600000] soft-irq read-recursion/123: > ok | > [17179569.604000] hard-irq read-recursion/132: > ok | > [17179569.608000] soft-irq read-recursion/132: > ok | > [17179569.612000] hard-irq read-recursion/213: > ok | > [17179569.616000] soft-irq read-recursion/213: > ok | > [17179569.620000] hard-irq read-recursion/231: > ok | > [17179569.624000] soft-irq read-recursion/231: > ok | > [17179569.628000] hard-irq read-recursion/312: > ok | > [17179569.636000] soft-irq read-recursion/312: > ok | > [17179569.640000] hard-irq read-recursion/321: > ok | > [17179569.644000] soft-irq read-recursion/321: > ok | > [17179569.652000] > -------------------------------------------------------- > [17179569.656000] 142 out of 218 testcases failed, as > expected. | > [17179569.660000] > ---------------------------------------------------- > [17179569.664000] Dentry cache hash table entries: > 32768 (order: 6, 262144 bytes) > [17179569.668000] Inode-cache hash table entries: > 16384 (order: 5, 131072 bytes) > [17179569.700000] Memory: 249464k/260764k available > (4112k kernel code, 10976k reserved, 1260k data, 260k > init, 0k highmem) > [17179569.804000] Mount-cache hash table entries: 256 > [17179569.808000] Checking for 'wait' instruction... > unavailable. > [17179569.816000] Checking for the multiply/shift > bug... no. > [17179569.820000] Checking for the daddi bug... no. > [17179569.824000] Checking for the daddiu bug... no. > [17179569.832000] CPU revision is: 03040102 > [17179569.832000] FPU revision is: 000f0102 > [17179569.832000] Primary instruction cache 32kB, > 4-way, linesize 32 bytes. > [17179569.832000] Primary data cache 32kB, 4-way, > linesize 32 bytes. > [17179569.832000] Synthesized TLB refill handler (40 > instructions). > [17179569.932000] Brought up 2 CPUs > [17179570.248000] migration_cost=8000 > [17179570.260000] NET: Registered protocol family 16 > [17179570.272000] Generic PHY: Registered new driver > [17179570.280000] SCSI subsystem initialized > [17179570.284000] usbcore: registered new driver usbfs > [17179570.292000] usbcore: registered new driver hub > [17179570.304000] NET: Registered protocol family 2 > [17179570.352000] IP route cache hash table entries: > 2048 (order: 2, 16384 bytes) > [17179570.360000] TCP established hash table entries: > 8192 (order: 6, 262144 bytes) > [17179570.368000] TCP bind hash table entries: 4096 > (order: 5, 131072 bytes) > [17179570.372000] TCP: Hash tables configured > (established 8192 bind 4096) > [17179570.376000] TCP reno registered > [17179570.420000] Initializing RT-Tester: OK > [17179570.428000] JFS: nTxBlock = 1951, nTxLock = > 15611 > [17179570.436000] Installing v9fs 9P2000 file system > support > [17179570.444000] Initializing Cryptographic API > [17179570.448000] io scheduler noop registered > [17179570.452000] io scheduler anticipatory registered > [17179570.456000] io scheduler deadline registered > (default) > [17179570.460000] io scheduler cfq registered > [17179570.840000] IRQ handler type mismatch for IRQ 8 > [17179570.844000] Call Trace: > [17179570.848000] [] > dump_stack+0x18/0x58 > [17179570.852000] [] > setup_irq+0x1b0/0x2d8 > [17179570.856000] [] > request_irq+0x108/0x128 > [17179570.864000] [] > rtc_init+0xb4/0x5b8 > [17179570.868000] [] > init+0x29c/0x6c0 > [17179570.872000] [] > kernel_thread_helper+0x10/0x18 > [17179570.880000] > [17179570.880000] rtc: IRQ 8 is not free. > [17179570.884000] RAMDISK driver initialized: 1 RAM > disks of 4096K size 1024 blocksize > [17179570.900000] loop: loaded (max 8 devices) > [17179570.904000] nbd: registered device at major 43 > [17179570.924000] Ethernet Channel Bonding Driver: > v3.0.3 (March 23, 2006) > [17179570.932000] bonding: Warning: either miimon or > arp_interval and arp_ip_target module parameters must > be specified, otherwise bonding will not detect li. > [17179570.952000] eth0: enabling TCP rcv checksum > [17179570.956000] eth0: SiByte Ethernet at 0x10064000, > address: 00:02:4C:FD:0D:3C > [17179570.964000] eth1: enabling TCP rcv checksum > [17179570.968000] eth1: SiByte Ethernet at 0x10065000, > address: 00:02:4C:FD:0D:3D > [17179570.976000] Equalizer2002: Simon Janes > (simon@ncm.com) and David S. Miller (davem@redhat.com) > [17179570.988000] Initializing USB Mass Storage > driver... > [17179570.996000] usbcore: registered new driver > usb-storage > [17179571.000000] USB Mass Storage support registered. > [17179571.004000] usbcore: registered new driver > libusual > [17179571.012000] usbcore: registered new driver > usbhid > [17179571.016000] drivers/usb/input/hid-core.c: > v2.6:USB HID core driver > [17179571.024000] mice: PS/2 mouse device common for > all mice > [17179571.032000] rtc-test rtc-test.0: rtc intf: sysfs > [17179571.036000] rtc-test rtc-test.0: rtc intf: proc > [17179571.040000] rtc-test rtc-test.0: rtc intf: dev > (254:0) > [17179571.048000] rtc-test rtc-test.0: rtc core: > registered test as rtc0 > [17179571.052000] rtc-test rtc-test.1: rtc intf: sysfs > [17179571.060000] rtc-test rtc-test.1: rtc intf: dev > (254:1) > [17179571.064000] rtc-test rtc-test.1: rtc core: > registered test as rtc1 > [17179571.072000] i2c /dev entries driver > [17179571.076000] i2c-swarm.o: i2c SMBus adapter > module for SiByte board > [17179571.092000] pktgen v2.67: Packet Generator for > packet performance testing. > [17179571.100000] netem: version 1.2 > [17179571.104000] NET: Registered protocol family 1 > [17179571.108000] NET: Registered protocol family 10 > [17179571.116000] lo: Disabled Privacy Extensions > [17179571.120000] IPv6 over IPv4 tunneling driver > [17179571.124000] NET: Registered protocol family 17 > [17179571.148000] CCID: Registered CCID 3 (ccid3) > [17179571.152000] CCID: Registered CCID 2 (ccid2) > [17179571.180000] SCTP: Hash tables configured > (established 2048 bind 2048) > [17179571.184000] TIPC: Activated (version 1.6.1 > compiled Sep 15 2006 19:32:28) > [17179571.196000] NET: Registered protocol family 30 > [17179571.200000] TIPC: Started in single node mode > [17179571.204000] rtc-test rtc-test.0: setting the > system clock to 2006-09-15 19:53:10 (1158349990) > [17179571.716000] ADDRCONF(NETDEV_UP): bond0: link is > not ready > [17179571.720000] eth0: found phy 1, vendor 000818 > part 0e > [17179571.728000] eth0: Link speed: 100BaseT FDX > [17179571.732000] eth1: found phy 1, vendor 000818 > part 0e > [17179572.744000] Sending DHCP requests .,. OK > [17179578.444000] IP-Config: Got DHCP answer from > 0.0.0.0, my address is 10.1.3.148 > [17179578.496000] IP-Config: Complete: > [17179578.500000] device=eth0, addr=10.1.3.148, > mask=255.255.255.0, gw=10.1.3.1, > [17179578.508000] host=10.1.3.148, > domain=lightfleet, nis-domain=(none), > [17179578.512000] bootserver=0.0.0.0, > rootserver=10.1.3.187, rootpath= > [17179578.520000] Looking up port of RPC 100003/2 on > 10.1.3.187 > [17179578.532000] Looking up port of RPC 100005/1 on > 10.1.3.187 > [17179578.552000] VFS: Mounted root (nfs filesystem). > [17179578.560000] Freeing unused kernel memory: 260k > freed > > > __________________________________________________ > Do You Yahoo!? > Tired of spam? Yahoo! Mail has the best spam protection around > http://mail.yahoo.com > > > From ralf@linux-mips.org Sun Sep 17 02:01:03 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 17 Sep 2006 02:01:05 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:41925 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20038562AbWIQBBD (ORCPT ); Sun, 17 Sep 2006 02:01:03 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k8H11gbN023726; Sun, 17 Sep 2006 02:01:42 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k8H11gWW023725; Sun, 17 Sep 2006 02:01:42 +0100 Date: Sun, 17 Sep 2006 02:01:42 +0100 From: Ralf Baechle To: Mark E Mason Cc: Jonathan Day , linux-mips@linux-mips.org Subject: Re: Kernel debugging contd. Message-ID: <20060917010142.GA23646@linux-mips.org> References: <20060915221141.69174.qmail@web31504.mail.mud.yahoo.com> <7E000E7F06B05C49BDBB769ADAF44D070111E24B@NT-SJCA-0750.brcm.ad.broadcom.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7E000E7F06B05C49BDBB769ADAF44D070111E24B@NT-SJCA-0750.brcm.ad.broadcom.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12582 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Sep 15, 2006 at 03:54:06PM -0700, Mark E Mason wrote: > FWIW - this is the same place my boards are hanging (right after freeing > kernel memory). I'd tracked it down to the commit that changed the > cache/page handling for the sibyte parts from the sb1 specific to the > generic codes -- but haven't found time to look into it further as yet. Got a commit ID? Ralf From anemo@mba.ocn.ne.jp Sun Sep 17 14:43:31 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 17 Sep 2006 14:43:33 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:46031 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20037619AbWIQNnb (ORCPT ); Sun, 17 Sep 2006 14:43:31 +0100 Received: from localhost (p8015-ipad204funabasi.chiba.ocn.ne.jp [222.146.95.15]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 5CD58A6B3; Sun, 17 Sep 2006 22:43:26 +0900 (JST) Date: Sun, 17 Sep 2006 22:45:28 +0900 (JST) Message-Id: <20060917.224528.93022156.anemo@mba.ocn.ne.jp> To: imipak@yahoo.com Cc: linux-mips@linux-mips.org Subject: Re: Kernel debugging contd. From: Atsushi Nemoto In-Reply-To: <20060915221141.69174.qmail@web31504.mail.mud.yahoo.com> References: <20060915221141.69174.qmail@web31504.mail.mud.yahoo.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12583 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Fri, 15 Sep 2006 15:11:40 -0700 (PDT), Jonathan Day wrote: > Ok, here's the console output with virtually every > Linux debug option I could find enabled. It softlocks > (no console activity, but kernel pings) after freeing > memory. Any thoughts on using the magic key over > minicom would also be welcome. The thing that stands > out the most is line 864000, where we have an IRQ > handler mismatch and a call trace. I suppose the "IRQ handler mismatch" happened just because you enabled wrong rtc driver(s). It would be irrelevant. In general, softlock just after "Freeing unused kernel memory" can happen because /sbin/init crashed for some reason (kernel keep sending signals to /sbin/init). 1. Enable second and third "#if 0" blocks in arch/mips/mm/fault.c 2. Add printk() before each force_sig() in arch/mips/kernel/traps.c, branch.c, unaligned.c might show you what's going on. Also, SYSRQ-p or SYSRQ-t (BRK + p or BRK + t for serial console) might be helpful, but it seems UART driver of your target board does not support the MAGIC_SYSRQ feature... --- Atsushi Nemoto From richard@codesourcery.com Sun Sep 17 20:30:54 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 17 Sep 2006 20:30:55 +0100 (BST) Received: from gateway.codesourcery.com ([65.74.133.9]:17067 "EHLO gateway.codesourcery.com") by ftp.linux-mips.org with ESMTP id S20027647AbWIQTay (ORCPT ); Sun, 17 Sep 2006 20:30:54 +0100 Received: (qmail 26659 invoked by uid 1010); 17 Sep 2006 19:30:46 -0000 From: Richard Sandiford To: linux-mips@linux-mips.org Mail-Followup-To: linux-mips@linux-mips.org, richard@codesourcery.com Subject: [PATCH] The o32 fstatat syscall behaves differently on 32 and 64 bit kernels Date: Sun, 17 Sep 2006 20:30:46 +0100 Message-ID: <87bqpexpcp.fsf@talisman.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/21.4 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12584 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: richard@codesourcery.com Precedence: bulk X-list: linux-mips While working on a glibc patch to support the fstatat() functions[1], I noticed that the o32 implementation behaves differently on 32-bit and 64-bit kernels; the former provides a stat64 while the latter provides a plain (o32) stat. I think the former is what's intended, as there is no separate fstatat64. It's also what x86 does. I think this is just a case of a compat too far. The o32 stat64 is the same as plain stat on n64, so 64-bit kernels can just use newfstatat. (n32 already does this, and works correctly as-is.) Tested with the glibc patch, where it fixes the test I'd written. Please install if OK. Richard [1] I've seen Khem's patch, but I don't think it's right. Signed-off-by: Richard Sandiford diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 2ac0141..288ee4a 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -498,7 +498,7 @@ sys_call_table: PTR sys_mknodat /* 4290 */ PTR sys_fchownat PTR compat_sys_futimesat - PTR compat_sys_newfstatat + PTR sys_newfstatat PTR sys_unlinkat PTR sys_renameat /* 4295 */ PTR sys_linkat From richard@codesourcery.com Sun Sep 17 20:38:46 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 17 Sep 2006 20:38:48 +0100 (BST) Received: from gateway.codesourcery.com ([65.74.133.9]:40639 "EHLO gateway.codesourcery.com") by ftp.linux-mips.org with ESMTP id S20027647AbWIQTiq (ORCPT ); Sun, 17 Sep 2006 20:38:46 +0100 Received: (qmail 26699 invoked by uid 1010); 17 Sep 2006 19:38:39 -0000 From: Richard Sandiford To: linux-mips@linux-mips.org Mail-Followup-To: linux-mips@linux-mips.org, richard@codesourcery.com Subject: [PATCH] fstatat syscall names Date: Sun, 17 Sep 2006 20:38:39 +0100 Message-ID: <877j02xozk.fsf@talisman.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/21.4 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12585 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: richard@codesourcery.com Precedence: bulk X-list: linux-mips MIPS is the only port to call its fstatat()-related syscalls "__NR_fstatat". Now I can see why that might be seen as every other port being wrong, but I think for o32, it is at best confusing. __NR_fstat provides a plain (32-bit) stat while __NR_fstatat provides a 64-bit stat. Changing the name to __NR_fstatat64 would make things more explicit, match x86, and make the glibc port slightly easier. The current name is more appropriate for n32 and n64, but it would be appropriate for other 64-bit targets too, and those targets have chosen to call it __NR_newfstatat instead. Using the same name for MIPS would again be more consistent and make the glibc port slightly easier. I'm not wedded to this idea if the current names are preferred, but FWIW... Richard Signed-off-by: Richard Sandiford diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index 558e3cb..c391429 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -313,7 +313,7 @@ #define __NR_mknodat (__NR_Linux + 290) #define __NR_fchownat (__NR_Linux + 291) #define __NR_futimesat (__NR_Linux + 292) -#define __NR_fstatat (__NR_Linux + 293) +#define __NR_fstatat64 (__NR_Linux + 293) #define __NR_unlinkat (__NR_Linux + 294) #define __NR_renameat (__NR_Linux + 295) #define __NR_linkat (__NR_Linux + 296) @@ -600,7 +600,7 @@ #define __NR_mknodat (__NR_Linux + 249) #define __NR_fchownat (__NR_Linux + 250) #define __NR_futimesat (__NR_Linux + 251) -#define __NR_fstatat (__NR_Linux + 252) +#define __NR_newfstatat (__NR_Linux + 252) #define __NR_unlinkat (__NR_Linux + 253) #define __NR_renameat (__NR_Linux + 254) #define __NR_linkat (__NR_Linux + 255) @@ -891,7 +891,7 @@ #define __NR_mknodat (__NR_Linux + 253) #define __NR_fchownat (__NR_Linux + 254) #define __NR_futimesat (__NR_Linux + 255) -#define __NR_fstatat (__NR_Linux + 256) +#define __NR_newfstatat (__NR_Linux + 256) #define __NR_unlinkat (__NR_Linux + 257) #define __NR_renameat (__NR_Linux + 258) #define __NR_linkat (__NR_Linux + 259) From richard@codesourcery.com Sun Sep 17 21:30:13 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 17 Sep 2006 21:30:15 +0100 (BST) Received: from gateway.codesourcery.com ([65.74.133.9]:20187 "EHLO gateway.codesourcery.com") by ftp.linux-mips.org with ESMTP id S20027658AbWIQUaN (ORCPT ); Sun, 17 Sep 2006 21:30:13 +0100 Received: (qmail 27447 invoked by uid 1010); 17 Sep 2006 20:03:25 -0000 From: Richard Sandiford To: linux-mips@linux-mips.org Mail-Followup-To: linux-mips@linux-mips.org, richard@codesourcery.com Subject: Re: [PATCH] The o32 fstatat syscall behaves differently on 32 and 64 bit kernels References: <87bqpexpcp.fsf@talisman.home> Date: Sun, 17 Sep 2006 21:03:24 +0100 In-Reply-To: <87bqpexpcp.fsf@talisman.home> (Richard Sandiford's message of "Sun, 17 Sep 2006 20:30:46 +0100") Message-ID: <873baqxnub.fsf@talisman.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/21.4 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12586 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: richard@codesourcery.com Precedence: bulk X-list: linux-mips Richard Sandiford writes: > I think this is just a case of a compat too far. The o32 stat64 is the > same as plain stat on n64, so 64-bit kernels can just use newfstatat. > (n32 already does this, and works correctly as-is.) Huh. The last sentence sounded like a really useful addition when I wrote it, but even so soon after the fact, I've no idea why. It sounds like I was implying that stat calls require conversion on n32, but that certainly wasn't my intention. Please ignore. ;) Richard From manoje@broadcom.com Sun Sep 17 21:34:24 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 17 Sep 2006 21:34:26 +0100 (BST) Received: from mms1.broadcom.com ([216.31.210.17]:24330 "EHLO mms1.broadcom.com") by ftp.linux-mips.org with ESMTP id S20027658AbWIQUeY convert rfc822-to-8bit (ORCPT ); Sun, 17 Sep 2006 21:34:24 +0100 Received: from 10.10.64.154 by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.2.0)); Sun, 17 Sep 2006 13:34:08 -0700 X-Server-Uuid: F962EFE0-448C-40EE-8100-87DF498ED0EA Received: by mail-irva-10.broadcom.com (Postfix, from userid 47) id A6D6B2AF; Sun, 17 Sep 2006 13:34:08 -0700 (PDT) Received: from mail-irva-8.broadcom.com (mail-irva-8 [10.10.64.221]) by mail-irva-10.broadcom.com (Postfix) with ESMTP id 80DF12AE; Sun, 17 Sep 2006 13:34:08 -0700 (PDT) Received: from mail-sj1-12.sj.broadcom.com (mail-sj1-12.sj.broadcom.com [10.16.128.215]) by mail-irva-8.broadcom.com (MOS 3.7.5a-GA) with ESMTP id EFG44303; Sun, 17 Sep 2006 13:34:08 -0700 (PDT) Received: from NT-SJCA-0750.brcm.ad.broadcom.com (nt-sjca-0750 [10.16.192.220]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 33F2720501; Sun, 17 Sep 2006 13:34:08 -0700 (PDT) Received: from NT-SJCA-0752.brcm.ad.broadcom.com ([10.16.192.222]) by NT-SJCA-0750.brcm.ad.broadcom.com with Microsoft SMTPSVC(6.0.3790.1830); Sun, 17 Sep 2006 13:34:08 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Subject: RE: Kernel debugging contd. Date: Sun, 17 Sep 2006 13:34:07 -0700 Message-ID: <710F16C36810444CA2F5821E5EAB7F2305D9C3@NT-SJCA-0752.brcm.ad.broadcom.com> In-Reply-To: <20060917010142.GA23646@linux-mips.org> Thread-Topic: Kernel debugging contd. Thread-Index: AcbZ9NV/zD7mfj6DSUGjMVfzufk6mgAokH0A From: "Manoj Ekbote" To: "Ralf Baechle" , "Mark E Mason" cc: "Jonathan Day" , linux-mips@linux-mips.org X-OriginalArrivalTime: 17 Sep 2006 20:34:08.0075 (UTC) FILETIME=[9FFE11B0:01C6DA98] X-TMWD-Spam-Summary: SEV=1.1; DFV=A2006091707; IFV=2.0.6,4.0-7; RPD=4.00.0004; RPDID=303030312E30413031303230322E34353044414637302E303030312D412D; ENG=IBF; TS=20060917203412; CAT=NONE; CON=NONE; X-MMS-Spam-Filter-ID: A2006091707_4.00.0004_2.0.6,4.0-7 X-WSS-ID: 69136ECA3CC7683758-01-01 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12587 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manoje@broadcom.com Precedence: bulk X-list: linux-mips If I may add, the changes made when the flush_icache_page call was retired seems to cause this problem. I reversed some of the changes and the kernel boots fine atleast on 1480. commit id : 4bbd62a93a1ab4b7d8a5b402b0c78ac265b35661 /manoj -----Original Message----- From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Ralf Baechle Sent: Saturday, September 16, 2006 6:02 PM To: Mark E Mason Cc: Jonathan Day; linux-mips@linux-mips.org Subject: Re: Kernel debugging contd. On Fri, Sep 15, 2006 at 03:54:06PM -0700, Mark E Mason wrote: > FWIW - this is the same place my boards are hanging (right after freeing > kernel memory). I'd tracked it down to the commit that changed the > cache/page handling for the sibyte parts from the sb1 specific to the > generic codes -- but haven't found time to look into it further as yet. Got a commit ID? Ralf From mucci@cs.utk.edu Sun Sep 17 22:09:18 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 17 Sep 2006 22:09:20 +0100 (BST) Received: from bes.cs.utk.edu ([160.36.56.220]:1447 "EHLO bes.cs.utk.edu") by ftp.linux-mips.org with ESMTP id S20027658AbWIQVJS (ORCPT ); Sun, 17 Sep 2006 22:09:18 +0100 Received: from localhost (localhost [127.0.0.1]) by bes.cs.utk.edu (Postfix) with ESMTP id 63988FD24; Sun, 17 Sep 2006 17:08:57 -0400 (EDT) X-Virus-Scanned: by amavisd-new with ClamAV and SpamAssasin at cs.utk.edu Received: from bes.cs.utk.edu ([127.0.0.1]) by localhost (bes.cs.utk.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nkHD6pz5qQ+P; Sun, 17 Sep 2006 17:08:51 -0400 (EDT) Received: from [192.168.1.3] (c83-248-50-12.bredband.comhem.se [83.248.50.12]) by bes.cs.utk.edu (Postfix) with ESMTP id 5FB1EFD28; Sun, 17 Sep 2006 17:08:38 -0400 (EDT) Subject: Re: Performance counters and profiling on MIPS From: Philip Mucci To: Jonathan Day Cc: Nigel Stephens , Prasad Boddupalli , linux-mips@linux-mips.org, Stephane Eranian In-Reply-To: <20060614181431.38314.qmail@web31506.mail.mud.yahoo.com> References: <20060614181431.38314.qmail@web31506.mail.mud.yahoo.com> Content-Type: text/plain Organization: Innovative Computing Laboratory Date: Sun, 17 Sep 2006 23:08:23 +0200 Message-Id: <1158527303.3722.77.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.6.3 (2.6.3-1.fc5.5) Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12588 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mucci@cs.utk.edu Precedence: bulk X-list: linux-mips Hi folks, I just got around to checking this thread...about 4 months late. Stefane will release another version of the perfmon2 kernel patch in a few days, he's been working with LKML on cleaning things up. The current patch should go reasonably cleanly into the latest tree. The problem is that he's maintaining the core patch against linux mainline, so there is a bit of skew...be prepared to fix up some sys call numbers and some includes, that's about it. There have been some issues with some versions of linux mips not registering a cpu in /sys/devices, but that may be fixed in the latest snapshots. A part of this patch is the libpfm support library, which helps in counter allocation amongst other things. It isn't necessary to use the interface. It can also support the scenario where The new release of PAPI will include support for this subsystem on Linux/MIPS, but only for some MIPS64 processors. To add a new MIPS processors should be fairly easy, as the performance hardware on these chips isn't so exciting. Regards, Philip On Wed, 2006-06-14 at 11:14 -0700, Jonathan Day wrote: > Ok, the kernel version number listed is current to > 2.6.17-rc6, and the MIPS patches -almost- go in > cleanly. > > In the syscalls in arch/mips/kernel, there is a new > syscall (sys_tee) that throws the patches off as it is > not in the context. This is very easy to massage. > > The same is true of include/asm-mips/unistd.h, except > there the count of syscalls is also off by one. Again, > a very easy fix. > > Other than that, it looks current and looks good. I'm > going to be doing some testing on it, to see whether > it works as well as it looks, or whether it causes the > CPU to leap three feet in the air, discharging the > magic blue smoke. > > If other people have had success with it, though, I > would definitely suggest considering it for inclusion > in the linux-mips GIT tree. Those who don't need > performance counters won't be adversely affected, and > those of us who do would likely benefit. > > If the linux-mips tree would not be appropriate, then > could someone take up hypnosis and get it included in > the main tree? > > Jonathan > > --- Nigel Stephens wrote: > > > Prasad Boddupalli wrote: > > > Perfctr > > (http://user.it.uu.se/~mikpe/linux/perfctr/) and > > PAPI > > > (http://icl.cs.utk.edu/papi/) are precisely such > > attempts. Except that > > > MIPS ports of them do not seem to be available. > > > > There's also perfmon2, for which a MIPS patch is > > available - though no > > idea how up-to-date it is. See > > http://www.linux-mips.org/wiki/Perfmon2 > > > > Nigel > > > > > __________________________________________________ > Do You Yahoo!? > Tired of spam? Yahoo! Mail has the best spam protection around > http://mail.yahoo.com > From kaz@zeugmasystems.com Mon Sep 18 17:30:14 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Sep 2006 17:30:18 +0100 (BST) Received: from mail.zeugmasystems.com ([192.139.122.66]:43179 "EHLO zeugmasystems.com") by ftp.linux-mips.org with ESMTP id S20037833AbWIRQaO convert rfc822-to-8bit (ORCPT ); Mon, 18 Sep 2006 17:30:14 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: Kernel debugging contd. Date: Mon, 18 Sep 2006 09:29:52 -0700 Message-ID: <66910A579C9312469A7DF9ADB54A8B7D390BF9@exchange.ZeugmaSystems.local> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Kernel debugging contd. Thread-Index: AcbZ9NV/zD7mfj6DSUGjMVfzufk6mgAokH0AACnvisA= From: "Kaz Kylheku" To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12589 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kaz@zeugmasystems.com Precedence: bulk X-list: linux-mips Manoj Ekbote wrote: > If I may add, the changes made when the flush_icache_page call was > retired seems to cause this problem. > I reversed some of the changes and the kernel boots fine atleast on > 1480. > > commit id : 4bbd62a93a1ab4b7d8a5b402b0c78ac265b35661 Speaking of the 1480, I'm still running a 2.6.17.7 kernel in which I patched back the old assembly-language IRQ handler. I can't boot our board with the IRQ handler rewritten in C. From ths@networkno.de Mon Sep 18 18:06:11 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Sep 2006 18:06:17 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:45486 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20037833AbWIRRGL (ORCPT ); Mon, 18 Sep 2006 18:06:11 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 3A52546E1C; Mon, 18 Sep 2006 19:06:04 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GPMZD-0005Wx-AG; Mon, 18 Sep 2006 18:05:59 +0100 Date: Mon, 18 Sep 2006 18:05:59 +0100 To: Kaz Kylheku Cc: linux-mips@linux-mips.org Subject: Re: Kernel debugging contd. Message-ID: <20060918170559.GD3924@networkno.de> References: <66910A579C9312469A7DF9ADB54A8B7D390BF9@exchange.ZeugmaSystems.local> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <66910A579C9312469A7DF9ADB54A8B7D390BF9@exchange.ZeugmaSystems.local> User-Agent: Mutt/1.5.13 (2006-08-11) From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12590 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Kaz Kylheku wrote: > Manoj Ekbote wrote: > > If I may add, the changes made when the flush_icache_page call was > > retired seems to cause this problem. > > I reversed some of the changes and the kernel boots fine atleast on > > 1480. > > > > commit id : 4bbd62a93a1ab4b7d8a5b402b0c78ac265b35661 > > Speaking of the 1480, I'm still running a 2.6.17.7 kernel in which I > patched back the old assembly-language IRQ handler. > > I can't boot our board with the IRQ handler rewritten in C. Can you try if http://people.debian.org/~ths/mips-kernels/vmlinux-bcm1480-6.32 works on your 1480? It works for me, but apparently fails on some other boards. Thiemo From imipak@yahoo.com Mon Sep 18 20:28:05 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Sep 2006 20:28:10 +0100 (BST) Received: from web31514.mail.mud.yahoo.com ([68.142.198.143]:20048 "HELO web31514.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20037850AbWIRT2F (ORCPT ); Mon, 18 Sep 2006 20:28:05 +0100 Received: (qmail 88938 invoked by uid 60001); 18 Sep 2006 19:27:56 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:Cc:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=ZYqE/2KuSL4ei8L20o6w1NF2/xtodZ0MCETlYpXyGb9Az5VhY4yDhSkGQXqkngg1Zwl1PC7LR4kIF9wR+ndROCu+HOhlBM7rKRM03qCe4CDL80rdzqT7IfhJ6+TJPSTgOVySCjnO7kzVFWnfwgzjE5CAxNXkvLYU/QpfT6kyMtg= ; Message-ID: <20060918192756.88936.qmail@web31514.mail.mud.yahoo.com> Received: from [70.103.67.194] by web31514.mail.mud.yahoo.com via HTTP; Mon, 18 Sep 2006 12:27:56 PDT Date: Mon, 18 Sep 2006 12:27:56 -0700 (PDT) From: Jonathan Day Subject: RE: Kernel debugging contd. To: Manoj Ekbote Cc: Jonathan Day , linux-mips@linux-mips.org In-Reply-To: <710F16C36810444CA2F5821E5EAB7F2305D9C3@NT-SJCA-0752.brcm.ad.broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12591 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips Hi, Any chance you could e-mail me a diff of the changes you made? I really need to get this Broadcom board back on its feet, preferably with the current kernel as there's a lot of stuff that I need in it. Thanks for any help you can give, Jonathan Day P.S. Oh, one other thing you might be able to help with. A lot of tools I have for modifying the speed or other parameters of ethernet chips are designed for 10/100 devices, but the 1250 works over a gigabit interface. You wouldn't happen to have any tools that would allow me to alter the state of the interface, would you? I'm getting some weird behaviour, with it switching to gigabit half-duplex, and would love to have some kind of disgnostic tool to see what's happening and modify the settings. Again, thanks for any help - there's a lot with this board that is simply stumping me. --- Manoj Ekbote wrote: > If I may add, the changes made when the > flush_icache_page call was > retired seems to cause this problem. > I reversed some of the changes and the kernel boots > fine atleast on > 1480. > > commit id : 4bbd62a93a1ab4b7d8a5b402b0c78ac265b35661 > > > /manoj > > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org] On Behalf > Of Ralf Baechle > Sent: Saturday, September 16, 2006 6:02 PM > To: Mark E Mason > Cc: Jonathan Day; linux-mips@linux-mips.org > Subject: Re: Kernel debugging contd. > > On Fri, Sep 15, 2006 at 03:54:06PM -0700, Mark E > Mason wrote: > > > FWIW - this is the same place my boards are > hanging (right after > freeing > > kernel memory). I'd tracked it down to the commit > that changed the > > cache/page handling for the sibyte parts from the > sb1 specific to the > > generic codes -- but haven't found time to look > into it further as > yet. > > Got a commit ID? > > Ralf > > > > __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From sshtylyov@ru.mvista.com Mon Sep 18 21:11:10 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 18 Sep 2006 21:11:13 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:43821 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20037885AbWIRULK (ORCPT ); Mon, 18 Sep 2006 21:11:10 +0100 Received: from [192.168.1.248] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 7207D3ECD; Mon, 18 Sep 2006 13:10:48 -0700 (PDT) Message-ID: <450EFDCF.2020400@ru.mvista.com> Date: Tue, 19 Sep 2006 00:13:03 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Rodolfo Giometti Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] au1x00 serial real interrupt References: <20060522165244.GA16223@enneenne.com> <44FD9587.3030708@ru.mvista.com> <4502ED14.6080506@ru.mvista.com> In-Reply-To: <4502ED14.6080506@ru.mvista.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12592 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Sergei Shtylyov wrote: >>> diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h >>> index 7b23664..0197062 100644 >>> --- a/include/asm-mips/serial.h >>> +++ b/include/asm-mips/serial.h >>> @@ -11,6 +11,14 @@ >>> >>> #include >>> >>> +#ifdef CONFIG_SOC_AU1X00 >>> +/* >>> + * We have to redefine "is_real_interrupt()" for Au1x00 CPUs... >>> + */ >>> +#undef is_real_interrupt >>> +#define is_real_interrupt(irq) ((irq) != ~0) >>> +#endif >>> + >>> /* >>> * This assumes you have a 1.8432 MHz clock for your UART. >>> * > Well, after looking at drivers/serial/8250.c a bit more, I think this > may be even more simlified since that driver seems to treat the negative > values as completely invalid anyway. IOW, we can just: > #define is_real_interrupt(irq) 1 Rodolfo, can you do this (possibly adding more elaborate comment about UART0 using IRQ0)? WBR, Sergei From edevolder@razamicroelectronics.com Tue Sep 19 16:39:39 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Sep 2006 16:39:40 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:22995 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S20038625AbWISPje (ORCPT ); Tue, 19 Sep 2006 16:39:34 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C6DC01.C95E134A" Subject: Differing results from cross and native compilers Date: Tue, 19 Sep 2006 08:39:25 -0700 Message-ID: <2E96546B3C2C8B4CA739323C6058204A0163548B@hq-ex-mb01.razamicroelectronics.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Differing results from cross and native compilers Thread-Index: AcbcAclb8MTuu14LT86YiDumaL+whA== From: "Eric DeVolder" To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12593 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: edevolder@razamicroelectronics.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. ------_=_NextPart_001_01C6DC01.C95E134A Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable =20 Hi, I have a MIPS native and cross compiler (gcc 3.4.4 and binutils = 2.15) both built using crosstool-0.42. I have an Alchemy system (MIPS32) for which I am building code. When I compile a simple example, I get different instructions from the cross and native compilers. =20 Specifically, the source file is: =20 #include int main (int argc, char **argv) { return -printf("Hello, world!\n"); } =20 To compile natively, I use: =20 % gcc -c hello.c -o obj1.o =20 To cross compile, I use: =20 % mipsel-unknown-linux-gnu-gcc -c hello.c -o obj2.o =20 If I use the -O0 or -O1 flags with each, I get identical output (for the .text), but when I compile in both environments with -O2; the compilers produce different results. =20 The native compiler on the Alchemy board results in the following: =20 obj1.o: file format elf32-tradlittlemips Disassembly of section .text: 00000000
: 0: 3c1c0000 lui gp,0x0 4: 279c0000 addiu gp,gp,0 8: 0399e021 addu gp,gp,t9 c: 27bdffe0 addiu sp,sp,-32 10: afbf0018 sw ra,24(sp) 14: afbc0010 sw gp,16(sp) 18: 8f840000 lw a0,0(gp) 1c: 00000000 nop 20: 24840000 addiu a0,a0,0 24: 8f990000 lw t9,0(gp) 28: 00000000 nop 2c: 0320f809 jalr t9 30: 00000000 nop 34: 8fbc0010 lw gp,16(sp) 38: 8fbf0018 lw ra,24(sp) 3c: 00021023 negu v0,v0 40: 03e00008 jr ra 44: 27bd0020 addiu sp,sp,32 =20 The cross compiler results in: =20 obj2.o: file format elf32-tradlittlemips Disassembly of section .text: 00000000
: 0: 3c1c0000 lui gp,0x0 4: 279c0000 addiu gp,gp,0 8: 0399e021 addu gp,gp,t9 c: 27bdffe0 addiu sp,sp,-32 10: afbf0018 sw ra,24(sp) 14: afbc0010 sw gp,16(sp) 18: 8f840000 lw a0,0(gp) 1c: 8f990000 lw t9,0(gp) 20: 00000000 nop 24: 0320f809 jalr t9 28: 24840000 addiu a0,a0,0 2c: 8fbc0010 lw gp,16(sp) 30: 8fbf0018 lw ra,24(sp) 34: 00021023 negu v0,v0 38: 03e00008 jr ra 3c: 27bd0020 addiu sp,sp,32 =20 I would have thought that for this simple example I'd get identical results. For reasons I have yet to figure out, the cross compiler is finding better optimizations than the native, though both are the same gcc version. I checked the specs files, and the two are identical other than the "cross_compile" setting. =20 I'd like to solve this little mystery to get to the bigger prize, and that is the ability to actually compile code (e.g. the entire system) for MIPS32. As is demonstrated above, the compilers are generating MIPS1 code (based on the NOPs between the load-to-use), but if I could get the compiler to honor -mips32 (this discovery I originally made while trying to get native -mips32 to work), I can get even tighter code... =20 I've done quite a bit of googling to no avail. I've also done some digging into gcc/binutils sources, and it appears that binutils has a "from-abi" option for choosing its architecture, which is o32 which probably means just MIPS1. I thought about trying to rebuild all the tools for mipsisa32-unknown-linux-gnu, but am concerned I'd still have the same problem of a particular compiler optimziation option not being honored by the compiler. =20 Any tips/advice much appreciated, thanks! Eric =20 ------_=_NextPart_001_01C6DC01.C95E134A Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable =0A=
 
=0A=
Hi, I have a MIPS = native and cross =0A= compiler (gcc 3.4.4 and binutils 2.15)
both built using = crosstool-0.42. I =0A= have an Alchemy system (MIPS32)
for which I am building code. When I = compile =0A= a simple example, I get
different instructions from the cross and = native =0A= compilers.
=0A=
 
=0A=
Specifically, the = source file =0A= is:
=0A=
 
=0A=
 #include =0A= <stdio.h>
 int
 main (int argc, char =0A= **argv)
 {
     return -printf("Hello, =0A= world!\n");
 }
=0A=
 
=0A=
To compile natively, I =0A= use:
=0A=
 
=0A=
 % gcc -c = hello.c -o =0A= obj1.o
=0A=
 
=0A=
To cross compile, I = use:
=0A=
 
=0A=
 % =0A= mipsel-unknown-linux-gnu-gcc -c hello.c -o obj2.o
=0A=
 
=0A=
If I use the -O0 or -O1 = flags with =0A= each, I get identical output
(for the .text), but when I compile in = both =0A= environments with -O2;
the compilers produce different = results.
=0A=
 
=0A=
The native compiler on = the Alchemy =0A= board results in the following:
=0A=
 
=0A=
obj1.o:     file format =0A= elf32-tradlittlemips
=0A=
Disassembly of = section =0A= .text:
=0A=
00000000 =0A= <main>:
   0:   =0A= 3c1c0000        = lui     =0A= gp,0x0
   4:   =0A= 279c0000        addiu   =0A= gp,gp,0
   8:   =0A= 0399e021        = addu    =0A= gp,gp,t9
   c:   =0A= 27bdffe0        addiu   =0A= sp,sp,-32
  10:   =0A= afbf0018        =0A= sw      ra,24(sp)
  14:   =0A= afbc0010        =0A= sw      gp,16(sp)
  18:   =0A= 8f840000        =0A= lw      a0,0(gp)
  1c:   =0A= 00000000        nop
  = 20:   =0A= 24840000        addiu   =0A= a0,a0,0
  24:   =0A= 8f990000        =0A= lw      t9,0(gp)
  28:   =0A= 00000000        nop
  = 2c:   =0A= 0320f809        = jalr    =0A= t9
  30:   = 00000000        =0A= nop
  34:   = 8fbc0010        =0A= lw      gp,16(sp)
  38:   =0A= 8fbf0018        =0A= lw      ra,24(sp)
  3c:   =0A= 00021023        = negu    =0A= v0,v0
  40:   =0A= 03e00008        =0A= jr      ra
  44:   =0A= 27bd0020        addiu   =0A= sp,sp,32
=0A=
 
=0A=
The cross compiler = results =0A= in:
=0A=
 
=0A=
obj2.o:     file format =0A= elf32-tradlittlemips
=0A=
Disassembly of = section =0A= .text:
=0A=
00000000 =0A= <main>:
   0:   =0A= 3c1c0000        = lui     =0A= gp,0x0
   4:   =0A= 279c0000        addiu   =0A= gp,gp,0
   8:   =0A= 0399e021        = addu    =0A= gp,gp,t9
   c:   =0A= 27bdffe0        addiu   =0A= sp,sp,-32
  10:   =0A= afbf0018        =0A= sw      ra,24(sp)
  14:   =0A= afbc0010        =0A= sw      gp,16(sp)
  18:   =0A= 8f840000        =0A= lw      a0,0(gp)
  1c:   =0A= 8f990000        =0A= lw      t9,0(gp)
  20:   =0A= 00000000        nop
  = 24:   =0A= 0320f809        = jalr    =0A= t9
  28:   = 24840000        =0A= addiu   a0,a0,0
  2c:   =0A= 8fbc0010        =0A= lw      gp,16(sp)
  30:   =0A= 8fbf0018        =0A= lw      ra,24(sp)
  34:   =0A= 00021023        = negu    =0A= v0,v0
  38:   =0A= 03e00008        =0A= jr      ra
  3c:   =0A= 27bd0020        addiu   =0A= sp,sp,32
=0A=
 
=0A=
I would have thought that for this = simple example =0A= I'd get identical
results. For reasons I have yet to figure out, the = cross =0A= compiler is
finding better optimizations than the native, though both = are =0A= the
same gcc version. I checked the specs files, and the two are =0A= identical
other than the "cross_compile" setting.
=0A=
 
=0A=
I'd like to solve this little mystery = to get to the =0A= bigger prize, and
that is the ability to actually compile code (e.g. = the =0A= entire system)
for MIPS32. As is demonstrated above, the compilers = are =0A= generating
MIPS1 code (based on the NOPs between the load-to-use), = but if =0A= I
could get the compiler to honor -mips32 (this discovery = I originally
=0A=
made while trying to get native -mips32 = to work), I =0A= can get even
=0A=
tighter code...
=0A=
 
=0A=
I've done quite a bit of googling to no = avail. I've =0A= also done some
digging into gcc/binutils sources, and it appears that =0A= binutils has a
"from-abi" option for choosing its architecture, which = is o32 =0A= which
probably means just MIPS1. I thought about trying to rebuild = all =0A= the
tools for mipsisa32-unknown-linux-gnu, but am concerned I'd = still
have =0A= the same problem of a particular compiler optimziation option
not = being =0A= honored by the compiler.
=0A=
 
=0A=
Any tips/advice much appreciated, =0A= thanks!
Eric
=0A=
 
------_=_NextPart_001_01C6DC01.C95E134A-- From ths@networkno.de Tue Sep 19 17:05:17 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Sep 2006 17:05:18 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:31690 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20038636AbWISQFR (ORCPT ); Tue, 19 Sep 2006 17:05:17 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 03A2447355; Tue, 19 Sep 2006 18:05:16 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GPi5x-0003o1-Qy; Tue, 19 Sep 2006 17:05:13 +0100 Date: Tue, 19 Sep 2006 17:05:13 +0100 To: Eric DeVolder Cc: linux-mips@linux-mips.org Subject: Re: Differing results from cross and native compilers Message-ID: <20060919160513.GD4553@networkno.de> References: <2E96546B3C2C8B4CA739323C6058204A0163548B@hq-ex-mb01.razamicroelectronics.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2E96546B3C2C8B4CA739323C6058204A0163548B@hq-ex-mb01.razamicroelectronics.com> User-Agent: Mutt/1.5.13 (2006-08-11) From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12594 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Eric DeVolder wrote: [snip] > I would have thought that for this simple example I'd get identical > results. For reasons I have yet to figure out, the cross compiler is > finding better optimizations than the native, though both are the > same gcc version. I checked the specs files, and the two are identical > other than the "cross_compile" setting. Have you checked (with -v) if the assembler gets the same optimisations in both cases, and/or (with -save-temps) where in the compile things start to diverge? Thiemo From edevolder@razamicroelectronics.com Tue Sep 19 17:58:01 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Sep 2006 17:58:03 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:39184 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S20038644AbWISQ6B (ORCPT ); Tue, 19 Sep 2006 17:58:01 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C6DC0C.BF680F2A" Subject: RE: Differing results from cross and native compilers Date: Tue, 19 Sep 2006 09:57:53 -0700 Message-ID: <2E96546B3C2C8B4CA739323C6058204A0163548C@hq-ex-mb01.razamicroelectronics.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Differing results from cross and native compilers Thread-Index: AcbcBWcGsplfevXUTWiUW0MsJ4LnHAABZ+IV From: "Eric DeVolder" To: "Thiemo Seufer" Cc: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12595 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: edevolder@razamicroelectronics.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. ------_=_NextPart_001_01C6DC0C.BF680F2A Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Yes, it appears to me that the compiler (cc1) and assembler (as) = invocations are the same. I've included the "-v" output of each below = for reference. Furthermore, the -save-temps output .i files are = effectively the same (differences due to cross vs. native paths, but = that is it). Nonetheless, the output assembly source still contains = differences! =20 I'm curious if anybody examined the output of a cross and native = toolchain of the same (recent) version? =20 Eric =20 =20 0:~$ diff -wbup cross.s native.s --- cross.s 2006-09-19 11:38:54.000000000 -0500 +++ native.s 2006-09-19 11:39:07.000000000 -0500 @@ -17,24 +17,20 @@ main: .fmask 0x00000000,0 .set noreorder .cpload $25 - .set nomacro - + .set reorder addiu $sp,$sp,-32 sw $31,24($sp) .cprestore 16 - lw $4,%got($LC0)($28) - lw $25,%call16(printf)($28) - nop - jalr $25 - addiu $4,$4,%lo($LC0) - - lw $28,16($sp) + la $4,$LC0 + jal printf lw $31,24($sp) subu $2,$0,$2 + .set noreorder + .set nomacro j $31 addiu $sp,$sp,32 - .set macro .set reorder + .end main .ident "GCC: (GNU) 3.4.4" For good measure, here's the assembly output from the cross compiler: =20 0:~$ more cross.s .file 1 "t.c" .section .mdebug.abi32 .previous .abicalls .section .rodata.str1.4,"aMS",@progbits,1 .align 2 $LC0: .ascii "Hello, World!\n\000" .text .align 2 .globl main .ent main .type main, @function main: .frame $sp,32,$31 # vars=3D 0, regs=3D 1/0, args=3D 16, gp=3D 8 .mask 0x80000000,-8 .fmask 0x00000000,0 .set noreorder .cpload $25 .set nomacro addiu $sp,$sp,-32 sw $31,24($sp) .cprestore 16 lw $4,%got($LC0)($28) lw $25,%call16(printf)($28) nop jalr $25 addiu $4,$4,%lo($LC0) lw $28,16($sp) lw $31,24($sp) subu $2,$0,$2 j $31 addiu $sp,$sp,32 .set macro .set reorder .end main .ident "GCC: (GNU) 3.4.4" And here is the cross and native screen capture due to -v: =20 =3D=3D=3D=3D cross =3D=3D=3D=3D 0:~$ mipsel-unknown-linux-gnu-gcc -v -save-temps -O2 -c = /opt/oe/target/root/t.c -o obj2.o Reading specs from = /opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/lib/gcc/mip= sel-unknown-linux-gnu/3.4.4/specs Configured with: = /home/edevolder/downloads/crosstool-0.42/build/mipsel-unknown-linux-gnu/g= cc-3.4.4-glibc-2.3.6/gcc-3.4.4/configure = --target=3Dmipsel-unknown-linux-gnu = --host=3Dx86_64-host_unknown-linux-gnu = --prefix=3D/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu = --with-sysroot=3D/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linu= x-gnu/mipsel-unknown-linux-gnu/sys-root = --with-local-prefix=3D/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown= -linux-gnu/mipsel-unknown-linux-gnu/sys-root --disable-nls = --enable-threads=3Dposix --enable-symvers=3Dgnu --enable-__cxa_atexit = --enable-languages=3Dc,c++ --enable-shared --enable-c99 = --enable-long-long Thread model: posix gcc version 3.4.4 = /opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/libexec/gcc= /mipsel-unknown-linux-gnu/3.4.4/cc1 -E -quiet -v /opt/oe/target/root/t.c = -O2 -o t.i ignoring nonexistent directory = "/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/mipsel-unk= nown-linux-gnu/sys-root/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknow= n-linux-gnu/mipsel-unknown-linux-gnu/sys-root/include" ignoring nonexistent directory = "/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/lib/gcc/mi= psel-unknown-linux-gnu/3.4.4/../../../../mipsel-unknown-linux-gnu/include= " #include "..." search starts here: #include <...> search starts here: = /opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/lib/gcc/mip= sel-unknown-linux-gnu/3.4.4/include = /opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/mipsel-unkn= own-linux-gnu/sys-root/usr/include End of search list. = /opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/libexec/gcc= /mipsel-unknown-linux-gnu/3.4.4/cc1 -fpreprocessed t.i -quiet -dumpbase = t.c -auxbase-strip obj2.o -O2 -version -o t.s GNU C version 3.4.4 (mipsel-unknown-linux-gnu) compiled by GNU C version 3.2.3 20030502 (Red Hat Linux = 3.2.3-54). GGC heuristics: --param ggc-min-expand=3D97 --param = ggc-min-heapsize=3D126001 = /opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/lib/gcc/mip= sel-unknown-linux-gnu/3.4.4/../../../../mipsel-unknown-linux-gnu/bin/as = -EL -O2 -no-mdebug -32 -v -KPIC -o obj2.o t.s GNU assembler version 2.15 (mipsel-unknown-linux-gnu) using BFD version = 2.15 =20 =3D=3D=3D native =3D=3D=3D root@db1200:~# gcc -v -save-temps -O2 -c t.c -o obj1.o Reading specs from /usr/lib/gcc/mipsel-unknown-linux-gnu/3.4.4/specs Configured with: = /home/edevolder/downloads/crosstool-0.42/build/mipsel-unknown-linux-gnu/g= cc-3.4.4-glibc-2.3.6/gcc-3.4.4/configure = --build=3Dx86_64-build_unknown-linux-gnu = --target=3Dmipsel-unknown-linux-gnu --host=3Dmipsel-unknown-linux-gnu = --prefix=3D/usr --disable-nls --enable-threads=3Dposix = --enable-symvers=3Dgnu --enable-__cxa_atexit --enable-languages=3Dc,c++ = --enable-shared --enable-c99 --enable-long-long Thread model: posix gcc version 3.4.4 /usr/libexec/gcc/mipsel-unknown-linux-gnu/3.4.4/cc1 -E -quiet -v t.c = -O2 -o t.iignoring nonexistent directory = "/usr/lib/gcc/mipsel-unknown-linux-gnu/3.4.4/../../../../mipsel-unknown-l= inux-gnu/include" #include "..." search starts here: #include <...> search starts here: /usr/local/include /usr/lib/gcc/mipsel-unknown-linux-gnu/3.4.4/include /usr/include End of search list. /usr/libexec/gcc/mipsel-unknown-linux-gnu/3.4.4/cc1 -fpreprocessed t.i = -quiet -dumpbase t.c -auxbase-strip obj1.o -O2 -version -o t.s GNU C version 3.4.4 (mipsel-unknown-linux-gnu) compiled by GNU C version 3.4.4. GGC heuristics: --param ggc-min-expand=3D47 --param = ggc-min-heapsize=3D31868 = /usr/lib/gcc/mipsel-unknown-linux-gnu/3.4.4/../../../../mipsel-unknown-li= nux-gnu/bin/as -EL -O2 -no-mdebug -32 -v -KPIC -o obj1.o t.s GNU assembler version 2.15 (mipsel-unknown-linux-gnu) using BFD version = 2.15 ________________________________ From: Thiemo Seufer [mailto:ths@networkno.de] Sent: Tue 9/19/2006 11:05 AM To: Eric DeVolder Cc: linux-mips@linux-mips.org Subject: Re: Differing results from cross and native compilers Eric DeVolder wrote: [snip] > I would have thought that for this simple example I'd get identical > results. For reasons I have yet to figure out, the cross compiler is > finding better optimizations than the native, though both are the > same gcc version. I checked the specs files, and the two are identical > other than the "cross_compile" setting. Have you checked (with -v) if the assembler gets the same optimisations in both cases, and/or (with -save-temps) where in the compile things start to diverge? Thiemo ------_=_NextPart_001_01C6DC0C.BF680F2A Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable =0A= =0A= =0A= =0A= =0A= =0A= Re: Differing results from cross and native compilers=0A= =0A= =0A=
=0A=
Yes, it = appears to me that =0A= the compiler (cc1) and assembler (as) invocations are the same. I've = included =0A= the "-v" output of each below for reference. Furthermore, the = -save-temps output =0A= .i files are effectively the same (differences due to cross vs. native = paths, =0A= but that is it). Nonetheless, the output assembly source still = contains =0A= differences!
=0A=
 
=0A=
I'm curious if anybody = examined the =0A= output of a cross and native toolchain of the same (recent) =0A= version?
=0A=
 
=0A=
Eric
=0A=
 
=0A=
 
=0A=
0:~$ diff -wbup cross.s = native.s
--- =0A= cross.s 2006-09-19 11:38:54.000000000 -0500
+++ =0A= native.s     2006-09-19 11:39:07.000000000 = -0500
@@ =0A= -17,24 +17,20 @@ main:
        =0A= .fmask  0x00000000,0
        =0A= .set    = noreorder
        =0A= .cpload $25
-       = .set    =0A= nomacro
-
+       = .set    =0A= reorder
        addiu   =0A= $sp,$sp,-32
        =0A= sw      =0A= $31,24($sp)
        =0A= .cprestore      =0A= 16
-       = lw      =0A= $4,%got($LC0)($28)
-       =0A= lw      =0A= $25,%call16(printf)($28)
-       =0A= nop
-       jalr    =0A= $25
-       addiu   =0A= $4,$4,%lo($LC0)
-
-       =0A= lw      =0A= $28,16($sp)
+       =0A= la      =0A= $4,$LC0
+       = jal     =0A= printf
        =0A= lw      =0A= $31,24($sp)
        = subu    =0A= $2,$0,$2
+       .set    =0A= noreorder
+       = .set    =0A= nomacro
        =0A= j       =0A= $31
        addiu   =0A= $sp,$sp,32
-
        =0A= .set    = macro
        =0A= .set    =0A= reorder
+
        =0A= .end    = main
        =0A= .ident  "GCC: (GNU) 3.4.4"
=0A=
For good measure, here's the assembly output from the = cross =0A= compiler:
=0A=
 
=0A=
0:~$ more cross.s
  = .file 1 =0A= "t.c"
  .section .mdebug.abi32
  .previous
  =0A= .abicalls
  .section  = .rodata.str1.4,"aMS",@progbits,1
  =0A= .align  2
$LC0:
  .ascii  "Hello, = World!\n\000"
  =0A= .text
  .align  2
  .globl  main
  = .ent  =0A= main
  .type main, @function
main:
  .frame  =0A= $sp,32,$31    # vars=3D 0, regs=3D 1/0, args=3D 16, gp=3D = 8
  =0A= .mask 0x80000000,-8
  .fmask  0x00000000,0
  = .set  =0A= noreorder
  .cpload $25
  .set  nomacro
=0A=
  addiu = $sp,$sp,-32
  =0A= sw  $31,24($sp)
  .cprestore  16
  lw  =0A= $4,%got($LC0)($28)
  lw  $25,%call16(printf)($28)
  =0A= nop
  jalr  $25
  addiu $4,$4,%lo($LC0)
=0A=
  lw  = $28,16($sp)
  =0A= lw  $31,24($sp)
  subu  $2,$0,$2
  j = $31
  =0A= addiu $sp,$sp,32
=0A=
  .set  = macro
  =0A= .set  reorder
  .end  main
  .ident  = "GCC: (GNU) =0A= 3.4.4"
=0A=
And here is the cross and native screen capture due to = -v:
=0A=
 
=0A=
=3D=3D=3D=3D cross =3D=3D=3D=3D
=0A=
0:~$ mipsel-unknown-linux-gnu-gcc -v -save-temps -O2 -c =0A= /opt/oe/target/root/t.c  -o obj2.o
Reading specs from =0A= /opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/lib/gcc/mip= sel-unknown-linux-gnu/3.4.4/specs
Configured =0A= with: =0A= /home/edevolder/downloads/crosstool-0.42/build/mipsel-unknown-linux-gnu/g= cc-3.4.4-glibc-2.3.6/gcc-3.4.4/configure =0A= --target=3Dmipsel-unknown-linux-gnu = --host=3Dx86_64-host_unknown-linux-gnu =0A= --prefix=3D/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu =0A= --with-sysroot=3D/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linu= x-gnu/mipsel-unknown-linux-gnu/sys-root =0A= --with-local-prefix=3D/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown= -linux-gnu/mipsel-unknown-linux-gnu/sys-root =0A= --disable-nls --enable-threads=3Dposix --enable-symvers=3Dgnu = --enable-__cxa_atexit =0A= --enable-languages=3Dc,c++ --enable-shared --enable-c99 =0A= --enable-long-long
Thread model: posix
gcc version =0A= 3.4.4
 /opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-= gnu/libexec/gcc/mipsel-unknown-linux-gnu/3.4.4/cc1 =0A= -E -quiet -v /opt/oe/target/root/t.c -O2 -o t.i
ignoring nonexistent =0A= directory =0A= "/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/mipsel-unk= nown-linux-gnu/sys-root/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknow= n-linux-gnu/mipsel-unknown-linux-gnu/sys-root/include"
ignoring =0A= nonexistent directory =0A= "/opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/lib/gcc/mi= psel-unknown-linux-gnu/3.4.4/../../../../mipsel-unknown-linux-gnu/include= "
#include =0A= "..." search starts here:
#include <...> search starts =0A= here:
 /opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-= gnu/lib/gcc/mipsel-unknown-linux-gnu/3.4.4/include
 /opt/crosstoo= l/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-gnu/mipsel-unknown-linux-gnu= /sys-root/usr/include
End =0A= of search =0A= list.
 /opt/crosstool/gcc-3.4.4-glibc-2.3.6/mipsel-unknown-linux-= gnu/libexec/gcc/mipsel-unknown-linux-gnu/3.4.4/cc1 =0A= -fpreprocessed t.i -quiet -dumpbase t.c -auxbase-strip obj2.o -O2 = -version -o =0A= t.s
GNU C version 3.4.4 =0A= (mipsel-unknown-linux-gnu)
        =0A= compiled by GNU C version 3.2.3 20030502 (Red Hat Linux = 3.2.3-54).
GGC =0A= heuristics: --param ggc-min-expand=3D97 --param =0A= ggc-min-heapsize=3D126001
 /opt/crosstool/gcc-3.4.4-glibc-2.3.6/m= ipsel-unknown-linux-gnu/lib/gcc/mipsel-unknown-linux-gnu/3.4.4/../../../.= ./mipsel-unknown-linux-gnu/bin/as =0A= -EL -O2 -no-mdebug -32 -v -KPIC -o obj2.o t.s
GNU assembler version = 2.15 =0A= (mipsel-unknown-linux-gnu) using BFD version 2.15
=0A=
 
=0A=
=3D=3D=3D native =3D=3D=3D
=0A=
root@db1200:~# gcc -v -save-temps -O2 -c t.c -o = obj1.o
Reading =0A= specs from = /usr/lib/gcc/mipsel-unknown-linux-gnu/3.4.4/specs
Configured with: =0A= /home/edevolder/downloads/crosstool-0.42/build/mipsel-unknown-linux-gnu/g= cc-3.4.4-glibc-2.3.6/gcc-3.4.4/configure =0A= --build=3Dx86_64-build_unknown-linux-gnu = --target=3Dmipsel-unknown-linux-gnu =0A= --host=3Dmipsel-unknown-linux-gnu --prefix=3D/usr --disable-nls =0A= --enable-threads=3Dposix --enable-symvers=3Dgnu --enable-__cxa_atexit =0A= --enable-languages=3Dc,c++ --enable-shared --enable-c99 =0A= --enable-long-long
Thread model: posix
gcc version =0A= 3.4.4
 /usr/libexec/gcc/mipsel-unknown-linux-gnu/3.4.4/cc1 -E = -quiet -v =0A= t.c -O2 -o t.iignoring nonexistent directory =0A= "/usr/lib/gcc/mipsel-unknown-linux-gnu/3.4.4/../../../../mipsel-unknown-l= inux-gnu/include"
#include =0A= "..." search starts here:
#include <...> search starts =0A= here:
 /usr/local/include
 /usr/lib/gcc/mipsel-unknown-li= nux-gnu/3.4.4/include
 /usr/include
End =0A= of search = list.
 /usr/libexec/gcc/mipsel-unknown-linux-gnu/3.4.4/cc1 =0A= -fpreprocessed t.i -quiet -dumpbase t.c -auxbase-strip obj1.o -O2 = -version -o =0A= t.s
GNU C version 3.4.4 =0A= (mipsel-unknown-linux-gnu)
        =0A= compiled by GNU C version 3.4.4.
GGC heuristics: --param = ggc-min-expand=3D47 =0A= --param =0A= ggc-min-heapsize=3D31868
 /usr/lib/gcc/mipsel-unknown-linux-gnu/3= .4.4/../../../../mipsel-unknown-linux-gnu/bin/as =0A= -EL -O2 -no-mdebug -32 -v -KPIC -o obj1.o t.s
GNU assembler version = 2.15 =0A= (mipsel-unknown-linux-gnu) using BFD version 2.15
=0A=

=0A=
=0A= From: Thiemo Seufer =0A= [mailto:ths@networkno.de]
Sent: Tue 9/19/2006 11:05 = AM
To: =0A= Eric DeVolder
Cc: linux-mips@linux-mips.org
Subject: = Re: =0A= Differing results from cross and native compilers

=0A=
=0A=

Eric DeVolder wrote:
[snip]
> I would have = thought that =0A= for this simple example I'd get identical
> results. For reasons I = have =0A= yet to figure out, the cross compiler is
> finding better = optimizations =0A= than the native, though both are the
> same gcc version. I checked = the =0A= specs files, and the two are identical
> other than the = "cross_compile" =0A= setting.

Have you checked (with -v) if the assembler gets the = same =0A= optimisations
in both cases, and/or (with -save-temps) where in the = compile =0A= things
start to diverge?


Thiemo

=0A= =0A= =0A= ------_=_NextPart_001_01C6DC0C.BF680F2A-- From ths@networkno.de Tue Sep 19 18:16:27 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Sep 2006 18:16:29 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:34539 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20038644AbWISRQ1 (ORCPT ); Tue, 19 Sep 2006 18:16:27 +0100 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id C041944A5F; Tue, 19 Sep 2006 19:16:26 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GPjCq-00063D-6n; Tue, 19 Sep 2006 18:16:24 +0100 Date: Tue, 19 Sep 2006 18:16:24 +0100 From: Thiemo Seufer To: Eric DeVolder Cc: linux-mips@linux-mips.org Subject: Re: Differing results from cross and native compilers Message-ID: <20060919171624.GA24864@networkno.de> References: <2E96546B3C2C8B4CA739323C6058204A0163548C@hq-ex-mb01.razamicroelectronics.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2E96546B3C2C8B4CA739323C6058204A0163548C@hq-ex-mb01.razamicroelectronics.com> User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12596 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Eric DeVolder wrote: > Yes, it appears to me that the compiler (cc1) and assembler (as) > invocations are the same. I've included the "-v" output of each > below for reference. Furthermore, the -save-temps output .i files > are effectively the same (differences due to cross vs. native paths, > but that is it). Nonetheless, the output assembly source still > contains differences! > > I'm curious if anybody examined the output of a cross and native > toolchain of the same (recent) version? I get the same (properly optimised) result from both compilers: gcc (GCC) 4.1.2 20060901 (prerelease) (Debian 4.1.1-13) mips-linux-gnu-gcc (GCC) 4.1.2 20060901 (prerelease) (Debian 4.1.1-13) I haven't tried a 3.4 crosscompiler, but the native one also behaves as expected: gcc-3.4 (GCC) 3.4.6 (Debian 3.4.6-4) Thiemo From ddaney@avtrex.com Tue Sep 19 18:18:56 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Sep 2006 18:18:58 +0100 (BST) Received: from smtp1.dnsmadeeasy.com ([205.234.170.134]:61324 "EHLO smtp1.dnsmadeeasy.com") by ftp.linux-mips.org with ESMTP id S20038626AbWISRS4 (ORCPT ); Tue, 19 Sep 2006 18:18:56 +0100 Received: from smtp1.dnsmadeeasy.com (localhost [127.0.0.1]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP id 340B2B8115; Tue, 19 Sep 2006 13:18:48 -0400 (EDT) X-Authenticated-Name: js.dnsmadeeasy X-Transit-System: In case of SPAM please contact abuse@dnsmadeeasy.com Received: from avtrex.com (unknown [67.116.42.147]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP; Tue, 19 Sep 2006 13:18:48 -0400 (EDT) Received: from [192.168.7.26] ([192.168.7.26]) by avtrex.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 19 Sep 2006 10:18:46 -0700 Message-ID: <45102676.6040800@avtrex.com> Date: Tue, 19 Sep 2006 10:18:46 -0700 From: David Daney User-Agent: Mozilla Thunderbird 1.0.7-1.1.fc3 (X11/20050929) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Eric DeVolder Cc: Thiemo Seufer , linux-mips@linux-mips.org Subject: Re: Differing results from cross and native compilers References: <2E96546B3C2C8B4CA739323C6058204A0163548C@hq-ex-mb01.razamicroelectronics.com> In-Reply-To: <2E96546B3C2C8B4CA739323C6058204A0163548C@hq-ex-mb01.razamicroelectronics.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 19 Sep 2006 17:18:46.0735 (UTC) FILETIME=[AA5B05F0:01C6DC0F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12597 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@avtrex.com Precedence: bulk X-list: linux-mips Eric DeVolder wrote: > Yes, it appears to me that the compiler (cc1) and assembler (as) invocations are the same. I've included the "-v" output of each below for reference. Furthermore, the -save-temps output .i files are effectively the same (differences due to cross vs. native paths, but that is it). Nonetheless, the output assembly source still contains differences! > > I'm curious if anybody examined the output of a cross and native toolchain of the same (recent) version? > Some of the code generation options of the compiler are set to default values which are controlled by options passed to the compiler's configure program. Unless identical configure options are used in the native and cross builds, you might different default code generation options. David Daney From edevolder@razamicroelectronics.com Tue Sep 19 18:57:23 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Sep 2006 18:57:25 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:27944 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S20038655AbWISR5X (ORCPT ); Tue, 19 Sep 2006 18:57:23 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C6DC15.09BBAAFA" Subject: RE: Differing results from cross and native compilers Date: Tue, 19 Sep 2006 10:56:09 -0700 Message-ID: <2E96546B3C2C8B4CA739323C6058204A0163548E@hq-ex-mb01.razamicroelectronics.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Differing results from cross and native compilers Thread-Index: AcbcD1jW+mUAhYzgTf6LbmJrWZigVwABYogm From: "Eric DeVolder" To: "Thiemo Seufer" Cc: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12598 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: edevolder@razamicroelectronics.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. ------_=_NextPart_001_01C6DC15.09BBAAFA Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Thiemo, could you share what the native 3.4 compiler reports as its = configuration? (e.g. the "Configured with: " statement)? =20 Thanks, Eric ________________________________ From: Thiemo Seufer [mailto:ths@networkno.de] Sent: Tue 9/19/2006 12:16 PM To: Eric DeVolder Cc: linux-mips@linux-mips.org Subject: Re: Differing results from cross and native compilers Eric DeVolder wrote: > Yes, it appears to me that the compiler (cc1) and assembler (as) > invocations are the same. I've included the "-v" output of each > below for reference. Furthermore, the -save-temps output .i files > are effectively the same (differences due to cross vs. native paths, > but that is it). Nonetheless, the output assembly source still > contains differences! >=20 > I'm curious if anybody examined the output of a cross and native > toolchain of the same (recent) version? I get the same (properly optimised) result from both compilers: gcc (GCC) 4.1.2 20060901 (prerelease) (Debian 4.1.1-13) mips-linux-gnu-gcc (GCC) 4.1.2 20060901 (prerelease) (Debian 4.1.1-13) I haven't tried a 3.4 crosscompiler, but the native one also behaves as expected: gcc-3.4 (GCC) 3.4.6 (Debian 3.4.6-4) Thiemo ------_=_NextPart_001_01C6DC15.09BBAAFA Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable =0A= =0A= =0A= =0A= =0A= =0A= Re: Differing results from cross and native compilers=0A= =0A= =0A=
=0A=
Thiemo, could = you share what =0A= the native 3.4 compiler reports as its configuration? (e.g. = the =0A= "Configured with: " statement)?
=0A=
 
=0A=
Thanks,
=0A=
Eric
=0A=

=0A=
=0A= From: Thiemo Seufer =0A= [mailto:ths@networkno.de]
Sent: Tue 9/19/2006 12:16 = PM
To: =0A= Eric DeVolder
Cc: linux-mips@linux-mips.org
Subject: = Re: =0A= Differing results from cross and native compilers

=0A=
=0A=

Eric DeVolder wrote:
> Yes, it appears to me = that the =0A= compiler (cc1) and assembler (as)
> invocations are the same. I've =0A= included the "-v" output of each
> below for reference. = Furthermore, the =0A= -save-temps output .i files
> are effectively the same = (differences due to =0A= cross vs. native paths,
> but that is it). Nonetheless, the output =0A= assembly source still
> contains = differences!
> 
> I'm =0A= curious if anybody examined the output of a cross and native
> = toolchain =0A= of the same (recent) version?

I get the same (properly optimised) = result =0A= from both compilers:

  gcc (GCC) 4.1.2 20060901 (prerelease) = (Debian =0A= 4.1.1-13)
  mips-linux-gnu-gcc (GCC) 4.1.2 20060901 (prerelease) = (Debian =0A= 4.1.1-13)


I haven't tried a 3.4 crosscompiler, but the native = one =0A= also behaves
as expected:

  gcc-3.4 (GCC) 3.4.6 (Debian =0A= 3.4.6-4)


Thiemo

=0A= =0A= =0A= ------_=_NextPart_001_01C6DC15.09BBAAFA-- From imipak@yahoo.com Tue Sep 19 19:06:52 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Sep 2006 19:06:54 +0100 (BST) Received: from web31501.mail.mud.yahoo.com ([68.142.198.130]:13156 "HELO web31501.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S20038661AbWISSGw (ORCPT ); Tue, 19 Sep 2006 19:06:52 +0100 Received: (qmail 8124 invoked by uid 60001); 19 Sep 2006 18:06:45 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:Received:Date:From:Subject:To:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=xcfkaUsYIKR7Z6UVAjPlrxV67sLnuQNOkq1CEWlMTb8KjJT2CnqQFBWPl3OtO0o8+pcTNTEiGCd943UNH/iJGvG7hJhyKTDY0X7oFxhcad163u6OOsqhBONQkrNEDInECJKlgXEVwrcvC0y0Mnnvw6l4gnT5b69aSD+l2lgfGvQ= ; Message-ID: <20060919180645.8122.qmail@web31501.mail.mud.yahoo.com> Received: from [70.103.67.194] by web31501.mail.mud.yahoo.com via HTTP; Tue, 19 Sep 2006 11:06:45 PDT Date: Tue, 19 Sep 2006 11:06:45 -0700 (PDT) From: Jonathan Day Subject: RE: Kernel debugging contd. To: Mark E Mason , linux-mips@linux-mips.org In-Reply-To: <7E000E7F06B05C49BDBB769ADAF44D070111E24B@NT-SJCA-0750.brcm.ad.broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12599 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: imipak@yahoo.com Precedence: bulk X-list: linux-mips I would guess I can fix the problem by simply cutting-and-pasting the SB1 codes back in and then changing the calls. (If there's a patch for this out there, that would be even easier...! :) Out of curiosity, any idea why the code was switched to a generic implementation? --- Mark E Mason wrote: > Hello, > > FWIW - this is the same place my boards are hanging > (right after freeing > kernel memory). I'd tracked it down to the commit > that changed the > cache/page handling for the sibyte parts from the > sb1 specific to the > generic codes -- but haven't found time to look into > it further as yet. > > /Mark __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com From ths@networkno.de Tue Sep 19 22:09:28 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Sep 2006 22:09:30 +0100 (BST) Received: from bender.bawue.de ([193.7.176.20]:16599 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S20038671AbWISVJ2 (ORCPT ); Tue, 19 Sep 2006 22:09:28 +0100 Received: from lagash (88-106-139-84.dynamic.dsl.as9105.com [88.106.139.84]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id D21D9447C8; Tue, 19 Sep 2006 23:09:22 +0200 (MEST) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GPmpk-0005OB-MK; Tue, 19 Sep 2006 22:08:48 +0100 Date: Tue, 19 Sep 2006 22:08:48 +0100 From: Thiemo Seufer To: Eric DeVolder Cc: linux-mips@linux-mips.org Subject: Re: Differing results from cross and native compilers Message-ID: <20060919210848.GC24864@networkno.de> References: <2E96546B3C2C8B4CA739323C6058204A0163548E@hq-ex-mb01.razamicroelectronics.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2E96546B3C2C8B4CA739323C6058204A0163548E@hq-ex-mb01.razamicroelectronics.com> User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12600 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Eric DeVolder wrote: > Thiemo, could you share what the native 3.4 compiler reports as > its configuration? (e.g. the "Configured with: " statement)? It was built by the Debian autobuilder, the buildlog at http://buildd.debian.org/fetch.php?&pkg=gcc-3.4&ver=3.4.6-4&arch=mips&stamp=1157712260&file=log&as=raw should show the configuration. Thiemo From ralf@linux-mips.org Tue Sep 19 23:44:00 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 19 Sep 2006 23:44:02 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:63406 "EHLO dl5rb.ham-radio-op.net") by ftp.linux-mips.org with ESMTP id S20038699AbWISWoA (ORCPT ); Tue, 19 Sep 2006 23:44:00 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by dl5rb.ham-radio-op.net (8.13.7/8.13.7) with ESMTP id k8JMigDj005785; Tue, 19 Sep 2006 23:44:42 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.13.7/8.13.7/Submit) id k8JMifX7005784; Tue, 19 Sep 2006 23:44:41 +0100 Date: Tue, 19 Sep 2006 23:44:41 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org, richard@codesourcery.com Subject: Re: [PATCH] fstatat syscall names Message-ID: <20060919224441.GA4031@linux-mips.org> References: <877j02xozk.fsf@talisman.home> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <877j02xozk.fsf@talisman.home> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12601 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Sep 17, 2006 at 08:38:39PM +0100, Richard Sandiford wrote: > MIPS is the only port to call its fstatat()-related syscalls > "__NR_fstatat". Now I can see why that might be seen as every > other port being wrong, but I think for o32, it is at best confusing. > __NR_fstat provides a plain (32-bit) stat while __NR_fstatat provides a > 64-bit stat. Changing the name to __NR_fstatat64 would make things more > explicit, match x86, and make the glibc port slightly easier. > > The current name is more appropriate for n32 and n64, but it would be > appropriate for other 64-bit targets too, and those targets have chosen > to call it __NR_newfstatat instead. Using the same name for MIPS would > again be more consistent and make the glibc port slightly easier. > > I'm not wedded to this idea if the current names are preferred, > but FWIW... I may have prefered the current naming at the time because they seemed to be more logical to me when I choose those names but I'm not married to them either. Ralf From wilson@specifix.com Wed Sep 20 00:27:04 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Sep 2006 00:27:06 +0100 (BST) Received: from w099.z064220152.sjc-ca.dsl.cnc.net ([64.220.152.99]:43680 "EHLO bluesmobile.corp.specifix.com") by ftp.linux-mips.org with ESMTP id S20038700AbWISX1E (ORCPT ); Wed, 20 Sep 2006 00:27:04 +0100 Received: from localhost.localdomain (bluesmobile.specifix.com [64.220.152.99]) by bluesmobile.corp.specifix.com (Postfix) with ESMTP id C2DB93B8A3; Tue, 19 Sep 2006 16:21:45 -0700 (PDT) Subject: RE: Differing results from cross and native compilers From: Jim Wilson To: Eric DeVolder Cc: Thiemo Seufer , linux-mips@linux-mips.org In-Reply-To: <2E96546B3C2C8B4CA739323C6058204A0163548C@hq-ex-mb01.razamicroelectronics.com> References: <2E96546B3C2C8B4CA739323C6058204A0163548C@hq-ex-mb01.razamicroelectronics.com> Content-Type: text/plain Date: Tue, 19 Sep 2006 16:22:59 -0700 Message-Id: <1158708179.22871.4.camel@dhcp-128-107-165-145.cisco.com> Mime-Version: 1.0 X-Mailer: Evolution 2.6.3 (2.6.3-1.fc5.5) Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12602 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilson@specifix.com Precedence: bulk X-list: linux-mips On Tue, 2006-09-19 at 09:57 -0700, Eric DeVolder wrote: > - lw $4,%got($LC0)($28) > + la $4,$LC0 The difference here is -mexplicit-relocs, which is the default for the first one (cross) but not the second one (native). The explicit-reloc support is enabled by a run-time configure test, which tries to run the assembler to see if you have a new enough version of GNU as that supports the necessary assembler reloc syntax. Apparently this is going wrong with the native build. Perhaps you have a different binutils version, or perhaps there is a problem with your PATH, or perhaps binutils and gcc weren't configured with the same prefix, etc. If you have the build trees, you can look at the gcc/config.h files and note that one has HAVE_AS_EXPLICIT_RELOCS defined and the other doesn't. -- Jim Wilson, GNU Tools Support, http://www.specifix.com From sathesh_edara2003@yahoo.co.in Wed Sep 20 10:16:38 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Sep 2006 10:16:40 +0100 (BST) Received: from web7908.mail.in.yahoo.com ([202.86.4.84]:51841 "HELO web7908.mail.in.yahoo.com") by ftp.linux-mips.org with SMTP id S20038430AbWITJQi (ORCPT ); Wed, 20 Sep 2006 10:16:38 +0100 Received: (qmail 49176 invoked by uid 60001); 20 Sep 2006 09:16:32 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.co.in; h=Message-ID:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=SFGASnnffp9Y06VmJD6eaCn81KXcMYmjgIGD/Kehz+buhiqy5GmG8kdpR7fc0yxx3qNqTQA1+03lSG+2FYdM6zNbIz1ZudnFJiQ97Oi3xGwXIFmarHpRzOF5S1owCRQUZUvQGtqQwXwIsywy9N8v6cf94ouo6pRW3UOisLO/KjQ= ; Message-ID: <20060920091632.49174.qmail@web7908.mail.in.yahoo.com> Received: from [61.246.223.98] by web7908.mail.in.yahoo.com via HTTP; Wed, 20 Sep 2006 10:16:32 BST Date: Wed, 20 Sep 2006 10:16:32 +0100 (BST) From: sathesh babu Subject: linux-libc-headers-2.6.17.0 To: linux-mips@linux-mips.org, linux-cvs-patches@linux-mips.org MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="0-1438772295-1158743792=:48413" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12603 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sathesh_edara2003@yahoo.co.in Precedence: bulk X-list: linux-mips --0-1438772295-1158743792=:48413 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi, I would like build toolchain to port Linux-2.6.17 kernel on MIPS processor. Can you please tell me where can i get linux-libc-headers-2.6.17.0 sources to build toolchain using buildroot. Has anybody built toolchain for Linux-2.6.17 kernel ver. Regards, Sathesh --------------------------------- Find out what India is talking about on - Yahoo! Answers India Send FREE SMS to your friend's mobile from Yahoo! Messenger Version 8. Get it NOW --0-1438772295-1158743792=:48413 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit
Hi,
   I would like build toolchain to port Linux-2.6.17 kernel on MIPS processor.
  Can you please tell me where can i get linux-libc-headers-2.6.17.0 sources to build toolchain using buildroot.
 
Has anybody built toolchain for Linux-2.6.17 kernel ver.
 
Regards,
Sathesh
 

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Send FREE SMS to your friend's mobile from Yahoo! Messenger Version 8. Get it NOW --0-1438772295-1158743792=:48413-- From sathesh_edara2003@yahoo.co.in Wed Sep 20 10:18:56 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Sep 2006 10:18:57 +0100 (BST) Received: from web7909.mail.in.yahoo.com ([202.86.4.85]:18358 "HELO web7909.mail.in.yahoo.com") by ftp.linux-mips.org with SMTP id S20038430AbWITJS4 (ORCPT ); Wed, 20 Sep 2006 10:18:56 +0100 Received: (qmail 29619 invoked by uid 60001); 20 Sep 2006 09:18:46 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.co.in; h=Message-ID:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=kk5/KflSobBvos6KdSLGTqRtQpLJ8U6S8PS3Uw1Dc2xgj7MnIR91bA/euTVSqN6TTrznhoM8FYvW2LTq+E6VrQ7cXQW/sxsCWDARua4RE9H3MlKA0KoJjcD1ExUKTh4QiJ6fjMrXxIi+ptXKFB44m2/nwrIHQEusw6G3gIugEKw= ; Message-ID: <20060920091846.29617.qmail@web7909.mail.in.yahoo.com> Received: from [61.246.223.98] by web7909.mail.in.yahoo.com via HTTP; Wed, 20 Sep 2006 10:18:46 BST Date: Wed, 20 Sep 2006 10:18:46 +0100 (BST) From: sathesh babu Subject: linux-libc-headers-2.6.17 To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="0-1148256633-1158743926=:28968" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12604 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sathesh_edara2003@yahoo.co.in Precedence: bulk X-list: linux-mips --0-1148256633-1158743926=:28968 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi, I would like build toolchain to port Linux-2.6.17 kernel on MIPS processor. Can you please tell me where can i get linux-libc-headers-2.6.17.0 sources to build toolchain using buildroot. Has anybody built toolchain for Linux-2.6.17 kernel ver. Regards, Sathesh --------------------------------- Find out what India is talking about on - Yahoo! Answers India Send FREE SMS to your friend's mobile from Yahoo! Messenger Version 8. Get it NOW --0-1148256633-1158743926=:28968 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi,
     I would like build toolchain to port Linux-2.6.17 kernel on MIPS
processor.
    Can you please tell me where can i get linux-libc-headers-2.6.17.0
sources to build toolchain using buildroot.
  
  Has anybody built toolchain for Linux-2.6.17 kernel ver.
  
  Regards,
  Sathesh
  

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Get it NOW --0-1148256633-1158743926=:28968-- From anemo@mba.ocn.ne.jp Wed Sep 20 17:35:03 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Sep 2006 17:35:06 +0100 (BST) Received: from mba.ocn.ne.jp ([210.190.142.172]:18634 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20038746AbWITQfD (ORCPT ); Wed, 20 Sep 2006 17:35:03 +0100 Received: from localhost (p5035-ipad201funabasi.chiba.ocn.ne.jp [222.146.68.35]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 7A950A590; Thu, 21 Sep 2006 01:34:57 +0900 (JST) Date: Thu, 21 Sep 2006 01:37:02 +0900 (JST) Message-Id: <20060921.013702.126573740.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] use proper hazard macro instead of BARRIER From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12605 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Signed-off-by: Atsushi Nemoto diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index a681f57..3bf5e8a 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -38,11 +38,6 @@ #include #include #include -/* CP0 hazard avoidance. */ -#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t") - /* Atomicity and interruptability */ #ifdef CONFIG_MIPS_MT_SMTC @@ -161,7 +156,7 @@ #ifdef CONFIG_MIPS_MT_SMTC /* preload TLB instead of local_flush_tlb_one() */ mtc0_tlbw_hazard(); tlb_probe(); - BARRIER; + tlb_probe_hazard(); tlbidx = read_c0_index(); mtc0_tlbw_hazard(); if (tlbidx < 0) From yoichi_yuasa@tripeaks.co.jp Wed Sep 20 18:08:07 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Sep 2006 18:08:08 +0100 (BST) Received: from mo31.po.2iij.net ([210.128.50.54]:48202 "EHLO mo31.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20027554AbWITRIH (ORCPT ); Wed, 20 Sep 2006 18:08:07 +0100 Received: by mo.po.2iij.net (mo31) id k8KH83Fx052680; Thu, 21 Sep 2006 02:08:03 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox33) id k8KH7sgh096138 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 21 Sep 2006 02:07:54 +0900 (JST) Date: Thu, 21 Sep 2006 01:56:38 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH 0/4] remove scheduled boards Message-Id: <20060921015638.480ea7b1.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12606 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ralf, These boards were scheduled to be removed after 2.6.18 released. [1/4] MIPS EV96100 evaluation board [2/4] Momentum / PMC-Sierra Jaguar ATX evaluation board [3/4] Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G [4/4] IT8172-based platforms, ITE 8172G and Globespan IVR also included in MIPS Technologies' Altas and SEAD evaluation board in the list. But, SEAD seems to be maintained by Maciej. Therefore, it is not included in. Please apply these patches. Thanks, Yoichi From yoichi_yuasa@tripeaks.co.jp Wed Sep 20 18:08:31 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Sep 2006 18:08:36 +0100 (BST) Received: from mo31.po.2iij.net ([210.128.50.54]:26670 "EHLO mo31.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20027543AbWITRIJ (ORCPT ); Wed, 20 Sep 2006 18:08:09 +0100 Received: by mo.po.2iij.net (mo31) id k8KH83jO052686; Thu, 21 Sep 2006 02:08:04 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox30) id k8KH7xb5028738 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 21 Sep 2006 02:07:59 +0900 (JST) Date: Thu, 21 Sep 2006 02:00:31 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH 2/4] removed Momentum / PMC-Sierra Jaguar ATX evaluation board support Message-Id: <20060921020031.0033e2d9.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20060921015758.639c4545.yoichi_yuasa@tripeaks.co.jp> References: <20060921015638.480ea7b1.yoichi_yuasa@tripeaks.co.jp> <20060921015758.639c4545.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12607 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips This patch has removed Momentum / PMC-Sierra Jaguar ATX evaluation board support. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/Documentation/feature-removal-schedule.txt mips/Documentation/feature-removal-schedule.txt --- mips-orig/Documentation/feature-removal-schedule.txt 2006-09-21 00:57:25.786852250 +0900 +++ mips/Documentation/feature-removal-schedule.txt 2006-09-21 00:57:52.720535500 +0900 @@ -202,16 +202,6 @@ Who: Nick Piggin --------------------------- -What: Support for the Momentum / PMC-Sierra Jaguar ATX evaluation board -When: September 2006 -Why: Does no longer build since quite some time, and was never popular, - due to the platform being replaced by successor models. Apparently - no user base left. It also is one of the last users of - WANT_PAGE_VIRTUAL. -Who: Ralf Baechle - ---------------------------- - What: Support for the Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G When: September 2006 Why: Some do no longer build and apparently there is no user base left diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Kconfig mips/arch/mips/Kconfig --- mips-orig/arch/mips/Kconfig 2006-09-21 00:57:25.790852500 +0900 +++ mips/arch/mips/Kconfig 2006-09-21 00:57:52.720535500 +0900 @@ -373,26 +373,6 @@ config MIPS_SIM This option enables support for MIPS Technologies MIPSsim software emulator. -config MOMENCO_JAGUAR_ATX - bool "Momentum Jaguar board" - select BOOT_ELF32 - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select IRQ_CPU_RM7K - select IRQ_MV64340 - select LIMITED_DMA - select PCI_MARVELL - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_RM9000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer . - config MOMENCO_OCELOT bool "Momentum Ocelot board" select DMA_NONCOHERENT @@ -802,7 +782,6 @@ source "arch/mips/gt64120/ev64120/Kconfi source "arch/mips/jazz/Kconfig" source "arch/mips/ite-boards/Kconfig" source "arch/mips/lasat/Kconfig" -source "arch/mips/momentum/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" @@ -875,11 +854,6 @@ config GENERIC_ISA_DMA config I8259 bool -config LIMITED_DMA - bool - select HIGHMEM - select SYS_SUPPORTS_HIGHMEM - config MIPS_BONITO64 bool diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Makefile mips/arch/mips/Makefile --- mips-orig/arch/mips/Makefile 2006-09-21 00:57:25.790852500 +0900 +++ mips/arch/mips/Makefile 2006-09-21 00:57:52.724535750 +0900 @@ -390,17 +390,6 @@ cflags-$(CONFIG_BASLER_EXCITE) += -Iincl load-$(CONFIG_BASLER_EXCITE) += 0x80100000 # -# Momentum Jaguar ATX -# -core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/ -cflags-$(CONFIG_MOMENCO_JAGUAR_ATX) += -Iinclude/asm-mips/mach-ja -#ifdef CONFIG_JAGUAR_DMALOW -#load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff88000000 -#else -load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff80100000 -#endif - -# # NEC DDB # core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/jaguar-atx_defconfig mips/arch/mips/configs/jaguar-atx_defconfig --- mips-orig/arch/mips/configs/jaguar-atx_defconfig 2006-09-21 00:46:00.164003500 +0900 +++ mips/arch/mips/configs/jaguar-atx_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,837 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:12 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_EV96100 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MOMENCO_JAGUAR_ATX=y -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_JAGUAR_DMALOW=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_LIMITED_DMA=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_CPU_RM7K=y -CONFIG_IRQ_MV64340=y -CONFIG_PCI_MARVELL=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_BOOT_ELF32=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -CONFIG_CPU_RM9000=y -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM9000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_HIGHMEM=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -# CONFIG_PACKET is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -CONFIG_IPV6=m -CONFIG_IPV6_PRIVACY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_IPV6_TUNNEL=m -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=m - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_LXT_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_SMSC_PHY=m - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -CONFIG_EEPRO100=y -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_MV643XX_ETH=y -CONFIG_MV643XX_ETH_0=y -CONFIG_MV643XX_ETH_1=y -CONFIG_MV643XX_ETH_2=y - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=m - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_HFSPLUS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=m -CONFIG_CRC32=m -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/mm/highmem.c mips/arch/mips/mm/highmem.c --- mips-orig/arch/mips/mm/highmem.c 2006-09-21 00:46:00.988055000 +0900 +++ mips/arch/mips/mm/highmem.c 2006-09-21 00:57:52.732536250 +0900 @@ -82,7 +82,6 @@ void __kunmap_atomic(void *kvaddr, enum preempt_check_resched(); } -#ifndef CONFIG_LIMITED_DMA /* * This is the same as kmap_atomic() but can map memory that doesn't * have a struct page associated with it. @@ -101,7 +100,6 @@ void *kmap_atomic_pfn(unsigned long pfn, return (void*) vaddr; } -#endif /* CONFIG_LIMITED_DMA */ struct page *__kmap_atomic_to_page(void *ptr) { diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/mm/init.c mips/arch/mips/mm/init.c --- mips-orig/arch/mips/mm/init.c 2006-09-21 00:46:00.988055000 +0900 +++ mips/arch/mips/mm/init.c 2006-09-21 00:57:52.736536500 +0900 @@ -453,9 +453,6 @@ void __init mem_init(void) continue; } ClearPageReserved(page); -#ifdef CONFIG_LIMITED_DMA - set_page_address(page, lowmem_page_address(page)); -#endif init_page_count(page); __free_page(page); totalhigh_pages++; diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/Kconfig mips/arch/mips/momentum/Kconfig --- mips-orig/arch/mips/momentum/Kconfig 2006-09-21 00:46:00.996055500 +0900 +++ mips/arch/mips/momentum/Kconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,6 +0,0 @@ -config JAGUAR_DMALOW - bool "Low DMA Mode" - depends on MOMENCO_JAGUAR_ATX - help - Select to Y if jump JP5 is set on your board, N otherwise. Normally - the jumper is set, so if you feel unsafe, just say Y. diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/Makefile mips/arch/mips/momentum/jaguar_atx/Makefile --- mips-orig/arch/mips/momentum/jaguar_atx/Makefile 2006-09-21 00:46:00.996055500 +0900 +++ mips/arch/mips/momentum/jaguar_atx/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,12 +0,0 @@ -# -# Makefile for Momentum Computer's Jaguar-ATX board. -# -# Note! Dependencies are done automagically by 'make dep', which also -# removes any old dependencies. DON'T put your own dependencies here -# unless it's something special (ie not a .c file). -# - -obj-y += irq.o prom.o reset.o setup.o - -obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o -obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/dbg_io.c mips/arch/mips/momentum/jaguar_atx/dbg_io.c --- mips-orig/arch/mips/momentum/jaguar_atx/dbg_io.c 2006-09-21 00:46:00.996055500 +0900 +++ mips/arch/mips/momentum/jaguar_atx/dbg_io.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,125 +0,0 @@ - -#if defined(CONFIG_REMOTE_DEBUG) - -#include /* For the serial port location and base baud */ - -/* --- CONFIG --- */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE OCELOT_SERIAL1_BASE -#define MAX_BAUD OCELOT_BASE_BAUD - -/* === END OF CONFIG === */ - -#define REG_OFFSET 4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/irq.c mips/arch/mips/momentum/jaguar_atx/irq.c --- mips-orig/arch/mips/momentum/jaguar_atx/irq.c 2006-09-21 00:46:00.996055500 +0900 +++ mips/arch/mips/momentum/jaguar_atx/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,94 +0,0 @@ -/* - * Copyright (C) 2002 Momentum Computer, Inc. - * Author: Matthew Dharm, mdharm@momenco.com - * - * Based on work by: - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP0) - do_IRQ(0, regs); - else if (pending & STATUSF_IP1) - do_IRQ(1, regs); - else if (pending & STATUSF_IP2) - do_IRQ(2, regs); - else if (pending & STATUSF_IP3) - do_IRQ(3, regs); - else if (pending & STATUSF_IP4) - do_IRQ(4, regs); - else if (pending & STATUSF_IP5) - do_IRQ(5, regs); - else if (pending & STATUSF_IP6) - do_IRQ(6, regs); - else if (pending & STATUSF_IP7) - ll_timer_interrupt(7, regs); - else { - /* - * Now look at the extended interrupts - */ - pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; - if (pending & STATUSF_IP8) - ll_mv64340_irq(regs); - } -} - -static struct irqaction cascade_mv64340 = { - no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL -}; - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM); - - mips_cpu_irq_init(0); - rm7k_cpu_irq_init(8); - - /* set up the cascading interrupts */ - setup_irq(8, &cascade_mv64340); - - mv64340_irq_init(16); - - set_c0_status(ST0_IM); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/ja-console.c mips/arch/mips/momentum/jaguar_atx/ja-console.c --- mips-orig/arch/mips/momentum/jaguar_atx/ja-console.c 2006-09-21 00:46:00.996055500 +0900 +++ mips/arch/mips/momentum/jaguar_atx/ja-console.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,106 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001, 2002, 2004 Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/* SUPERIO uart register map */ -struct ja_uartregs { - union { - volatile u8 pad0[3]; - volatile u8 rbr; /* read only, DLAB == 0 */ - volatile u8 pad1[3]; - volatile u8 thr; /* write only, DLAB == 0 */ - volatile u8 pad2[3]; - volatile u8 dll; /* DLAB == 1 */ - } u1; - union { - volatile u8 pad0[3]; - volatile u8 ier; /* DLAB == 0 */ - volatile u8 pad1[3]; - volatile u8 dlm; /* DLAB == 1 */ - } u2; - union { - volatile u8 pad0[3]; - volatile u8 iir; /* read only */ - volatile u8 pad1[3]; - volatile u8 fcr; /* write only */ - } u3; - volatile u8 pad0[3]; - volatile u8 iu_lcr; - volatile u8 pad1[3]; - volatile u8 iu_mcr; - volatile u8 pad2[3]; - volatile u8 iu_lsr; - volatile u8 pad3[3]; - volatile u8 iu_msr; - volatile u8 pad4[3]; - volatile u8 iu_scr; -} ja_uregs_t; - -#define iu_rbr u1.rbr -#define iu_thr u1.thr -#define iu_dll u1.dll -#define iu_ier u2.ier -#define iu_dlm u2.dlm -#define iu_iir u3.iir -#define iu_fcr u3.fcr - -extern unsigned long uart_base; - -static inline struct ja_uartregs *console_uart(void) -{ - return (struct ja_uartregs *) (uart_base + 0x23UL); -} - -void prom_putchar(char c) -{ - struct ja_uartregs *uart = console_uart(); - - while ((uart->iu_lsr & 0x20) == 0); - uart->iu_thr = c; -} - -char __init prom_getchar(void) -{ - return 0; -} - -static void inline ja_console_probe(void) -{ - struct uart_port up; - - /* - * Register to interrupt zero because we share the interrupt with - * the serial driver which we don't properly support yet. - */ - memset(&up, 0, sizeof(up)); - up.membase = (unsigned char *) uart_base + 0x23UL; - up.irq = JAGUAR_ATX_SERIAL1_IRQ; - up.uartclk = JAGUAR_ATX_UART_CLK; - up.regshift = 2; - up.iotype = UPIO_MEM; - up.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - up.line = 0; - - if (early_serial_setup(&up)) - printk(KERN_ERR "Early serial init of port 0 failed\n"); -} - -__init void ja_setup_console(void) -{ - ja_console_probe(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h mips/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h --- mips-orig/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h 2006-09-21 00:46:00.996055500 +0900 +++ mips/arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,52 +0,0 @@ -/* - * Jaguar-ATX Board Register Definitions - * - * (C) 2002 Momentum Computer Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __JAGUAR_ATX_FPGA_H__ -#define __JAGUAR_ATX_FPGA_H__ - -#define JAGUAR_ATX_REG_BOARDREV 0x0 -#define JAGUAR_ATX_REG_FPGA_REV 0x1 -#define JAGUAR_ATX_REG_FPGA_TYPE 0x2 -#define JAGUAR_ATX_REG_RESET_STATUS 0x3 -#define JAGUAR_ATX_REG_BOARD_STATUS 0x4 -#define JAGUAR_ATX_REG_RESERVED1 0x5 -#define JAGUAR_ATX_REG_SET 0x6 -#define JAGUAR_ATX_REG_CLR 0x7 -#define JAGUAR_ATX_REG_EEPROM_MODE 0x9 -#define JAGUAR_ATX_REG_RESERVED2 0xa -#define JAGUAR_ATX_REG_RESERVED3 0xb -#define JAGUAR_ATX_REG_RESERVED4 0xc -#define JAGUAR_ATX_REG_PHY_INTSTAT 0xd -#define JAGUAR_ATX_REG_RESERVED5 0xe -#define JAGUAR_ATX_REG_RESERVED6 0xf - -#define JAGUAR_ATX_CS0_ADDR 0xfc000000L - -extern unsigned long ja_fpga_base; - -#define JAGUAR_FPGA_WRITE(x,y) writeb(x, ja_fpga_base + JAGUAR_ATX_REG_##y) -#define JAGUAR_FPGA_READ(x) readb(ja_fpga_base + JAGUAR_ATX_REG_##x) - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/prom.c mips/arch/mips/momentum/jaguar_atx/prom.c --- mips-orig/arch/mips/momentum/jaguar_atx/prom.c 2006-09-21 00:46:00.996055500 +0900 +++ mips/arch/mips/momentum/jaguar_atx/prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,266 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Added changes for SMP - Manish Lachwani (lachwani@pmc-sierra.com) - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "jaguar_atx_fpga.h" - -extern void ja_setup_console(void); - -struct callvectors *debug_vectors; - -extern unsigned long cpu_clock; - -const char *get_system_type(void) -{ - return "Momentum Jaguar-ATX"; -} - -#ifdef CONFIG_MV643XX_ETH -extern unsigned char prom_mac_addr_base[6]; - -static void burn_clocks(void) -{ - int i; - - /* this loop should burn at least 1us -- this should be plenty */ - for (i = 0; i < 0x10000; i++) - ; -} - -static u8 exchange_bit(u8 val, u8 cs) -{ - /* place the data */ - JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE); - burn_clocks(); - - /* turn the clock on */ - JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE); - burn_clocks(); - - /* turn the clock off and read-strobe */ - JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - - /* return the data */ - return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); -} - -void get_mac(char dest[6]) -{ - u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int i,j; - - for (i = 0; i < 12; i++) - exchange_bit(read_opcode[i], 1); - - for (j = 0; j < 6; j++) { - dest[j] = 0; - for (i = 0; i < 8; i++) { - dest[j] <<= 1; - dest[j] |= exchange_bit(0, 1); - } - } - - /* turn off CS */ - exchange_bit(0,0); -} -#endif - -#ifdef CONFIG_64BIT - -unsigned long signext(unsigned long addr) -{ - addr &= 0xffffffff; - return (unsigned long)((int)addr); -} - -void *get_arg(unsigned long args, int arc) -{ - unsigned long ul; - unsigned char *puc, uc; - - args += (arc * 4); - ul = (unsigned long)signext(args); - puc = (unsigned char *)ul; - if (puc == 0) - return (void *)0; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - uc = *puc++; - l = (unsigned long)uc; - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 24); -#else - uc = *puc++; - ul = ((unsigned long)uc) << 24; - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= ((unsigned long)uc); -#endif - ul = signext(ul); - - return (void *)ul; -} - -char *arg64(unsigned long addrin, int arg_index) -{ - unsigned long args; - char *p; - - args = signext(addrin); - p = (char *)get_arg(args, arg_index); - - return p; -} -#endif /* CONFIG_64BIT */ - -/* PMON passes arguments in C main() style */ -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - int i; - -#ifdef CONFIG_SERIAL_8250_CONSOLE -// ja_setup_console(); /* The very first thing. */ -#endif - -#ifdef CONFIG_64BIT - char *ptr; - - printk("Mips64 Jaguar-ATX\n"); - /* save the PROM vectors for debugging use */ - debug_vectors = (struct callvectors *)signext((unsigned long)cv); - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - - for (i = 1; i < argc; i++) { - ptr = (char *)arg64((unsigned long)arg, i); - if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >= - sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ptr); - strcat(arcs_cmdline, " "); - } - - i = 0; - while (1) { - ptr = (char *)arg64((unsigned long)env, i); - if (! ptr) - break; - - if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(ptr + strlen("gtbase="), - NULL, 16); - - if ((marvell_base & 0xffffffff00000000) == 0) - marvell_base |= 0xffffffff00000000; - - printk("marvell_base set to 0x%016lx\n", marvell_base); - } - if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(ptr + strlen("cpuclock="), - NULL, 10); - printk("cpu_clock set to %d\n", cpu_clock); - } - i++; - } - printk("arcs_cmdline: %s\n", arcs_cmdline); - -#else /* CONFIG_64BIT */ - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - while (*env) { - if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - } - if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(*env + strlen("cpuclock="), - NULL, 10); - } - env++; - } -#endif /* CONFIG_64BIT */ - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_JAGUAR_ATX; - -#ifdef CONFIG_MV643XX_ETH - /* get the base MAC address for on-board ethernet ports */ - get_mac(prom_mac_addr_base); -#endif -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} - -void __init prom_fixup_mem_map(unsigned long start, unsigned long end) -{ -} - -int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp) -{ - /* Clear the semaphore */ - *(volatile uint32_t *)(0xbb000a68) = 0x80000000; - - return 1; -} - -void prom_init_secondary(void) -{ - clear_c0_config(CONF_CM_CMASK); - set_c0_config(0x2); - - clear_c0_status(ST0_IM); - set_c0_status(0x1ffff); -} - -void prom_smp_finish(void) -{ -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/reset.c mips/arch/mips/momentum/jaguar_atx/reset.c --- mips-orig/arch/mips/momentum/jaguar_atx/reset.c 2006-09-21 00:46:00.996055500 +0900 +++ mips/arch/mips/momentum/jaguar_atx/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,56 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - */ -#include -#include -#include -#include -#include -#include -#include -#include - -void momenco_jaguar_restart(char *command) -{ - /* base address of timekeeper portion of part */ -#ifdef CONFIG_64BIT - void *nvram = (void*) 0xfffffffffc807000; -#else - void *nvram = (void*) 0xfc807000; -#endif - /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ - writeb(0x84, nvram + 0xff7); - - /* wait for the watchdog to go off */ - mdelay(100+(1000/16)); - - /* if the watchdog fails for some reason, let people know */ - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_jaguar_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_jaguar_power_off(void) -{ - momenco_jaguar_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/jaguar_atx/setup.c mips/arch/mips/momentum/jaguar_atx/setup.c --- mips-orig/arch/mips/momentum/jaguar_atx/setup.c 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/jaguar_atx/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,476 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Momentum Computer Jaguar-ATX board dependent boot routines - * - * Copyright (C) 1996, 1997, 2001, 04, 06 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: Matthew Dharm, Momentum Computer - * mdharm@momenco.com - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "jaguar_atx_fpga.h" - -extern unsigned long mv64340_sram_base; -unsigned long cpu_clock; - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_jaguar_restart(char *command); -extern void momenco_jaguar_halt(void); -extern void momenco_jaguar_power_off(void); - -void momenco_time_init(void); - -static char reset_reason; - -static inline unsigned long ENTRYLO(unsigned long paddr) -{ - return ((paddr & PAGE_MASK) | - (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | - _CACHE_UNCACHED)) >> 6; -} - -void __init bus_error_init(void) { /* nothing */ } - -/* - * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going - * to be hit on every IRQ anyway - there's absolutely no point in letting it be - * a random TLB entry, as it'll just cause needless churning of the TLB. And we - * use the other half for the serial port, which is just a PITA otherwise :) - * - * Device Physical Virtual - * MV64340 Internal Regs 0xf4000000 0xf4000000 - * Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000 - * NVRAM (CS1) 0xfc800000 0xfc800000 - * UARTs (CS2) 0xfd000000 0xfd000000 - * Internal SRAM 0xfe000000 0xfe000000 - * M-Systems DOC (CS3) 0xff000000 0xff000000 - */ - -static __init void wire_stupidity_into_tlb(void) -{ -#ifdef CONFIG_32BIT - write_c0_wired(0); - local_flush_tlb_all(); - - /* marvell and extra space */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), - 0xf4000000UL, PM_64K); - /* fpga, rtc, and uart */ - add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), - 0xfc000000UL, PM_16M); -// /* m-sys and internal SRAM */ -// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), -// 0xfe000000UL, PM_16M); - - marvell_base = 0xf4000000; - //mv64340_sram_base = 0xfe000000; /* Currently unused */ -#endif -} - -unsigned long marvell_base = 0xf4000000L; -unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR; -unsigned long uart_base = 0xfd000000L; -static unsigned char *rtc_base = (unsigned char*) 0xfc800000L; - -EXPORT_SYMBOL(marvell_base); - -static __init int per_cpu_mappings(void) -{ - marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000); - ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000); - uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000); - rtc_base = ioremap(0xfc000000UL, 0x8000); - // ioremap(0xfe000000, 32 << 20); - write_c0_wired(0); - local_flush_tlb_all(); - ja_setup_console(); - - return 0; -} -arch_initcall(per_cpu_mappings); - -unsigned long m48t37y_get_time(void) -{ - unsigned int year, month, day, hour, min, sec; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - /* stop the update */ - rtc_base[0x7ff8] = 0x40; - - year = BCD2BIN(rtc_base[0x7fff]); - year += BCD2BIN(rtc_base[0x7ff1]) * 100; - - month = BCD2BIN(rtc_base[0x7ffe]); - - day = BCD2BIN(rtc_base[0x7ffd]); - - hour = BCD2BIN(rtc_base[0x7ffb]); - min = BCD2BIN(rtc_base[0x7ffa]); - sec = BCD2BIN(rtc_base[0x7ff9]); - - /* start the update */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return mktime(year, month, day, hour, min, sec); -} - -int m48t37y_set_time(unsigned long sec) -{ - struct rtc_time tm; - unsigned long flags; - - /* convert to a more useful format -- note months count from 0 */ - to_tm(sec, &tm); - tm.tm_mon += 1; - - spin_lock_irqsave(&rtc_lock, flags); - /* enable writing */ - rtc_base[0x7ff8] = 0x80; - - /* year */ - rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100); - rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100); - - /* month */ - rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon); - - /* day */ - rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday); - - /* hour/min/sec */ - rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour); - rtc_base[0x7ffa] = BIN2BCD(tm.tm_min); - rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec); - - /* day of week -- not really used, but let's keep it up-to-date */ - rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1); - - /* disable writing */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - -void __init plat_timer_setup(struct irqaction *irq) -{ - setup_irq(8, irq); -} - -/* - * Ugly but the least of all evils. TLB initialization did flush the TLB so - * We need to setup mappings again before we can touch the RTC. - */ -void momenco_time_init(void) -{ - wire_stupidity_into_tlb(); - - mips_hpt_frequency = cpu_clock / 2; - - rtc_mips_get_time = m48t37y_get_time; - rtc_mips_set_time = m48t37y_set_time; -} - -static struct resource mv_pci_io_mem0_resource = { - .name = "MV64340 PCI0 IO MEM", - .flags = IORESOURCE_IO -}; - -static struct resource mv_pci_mem0_resource = { - .name = "MV64340 PCI0 MEM", - .flags = IORESOURCE_MEM -}; - -static struct mv_pci_controller mv_bus0_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem0_resource, - .io_resource = &mv_pci_io_mem0_resource, - }, - .config_addr = MV64340_PCI_0_CONFIG_ADDR, - .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, -}; - -static uint32_t mv_io_base, mv_io_size; - -static void ja_pci0_init(void) -{ - uint32_t mem0_base, mem0_size; - uint32_t io_base, io_size; - - io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16; - io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16; - mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16; - mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16; - - mv_pci_io_mem0_resource.start = 0; - mv_pci_io_mem0_resource.end = io_size - 1; - mv_pci_mem0_resource.start = mem0_base; - mv_pci_mem0_resource.end = mem0_base + mem0_size - 1; - mv_bus0_controller.pcic.mem_offset = mem0_base; - mv_bus0_controller.pcic.io_offset = 0; - - ioport_resource.end = io_size - 1; - - register_pci_controller(&mv_bus0_controller.pcic); - - mv_io_base = io_base; - mv_io_size = io_size; -} - -static struct resource mv_pci_io_mem1_resource = { - .name = "MV64340 PCI1 IO MEM", - .flags = IORESOURCE_IO -}; - -static struct resource mv_pci_mem1_resource = { - .name = "MV64340 PCI1 MEM", - .flags = IORESOURCE_MEM -}; - -static struct mv_pci_controller mv_bus1_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem1_resource, - .io_resource = &mv_pci_io_mem1_resource, - }, - .config_addr = MV64340_PCI_1_CONFIG_ADDR, - .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, -}; - -static __init void ja_pci1_init(void) -{ - uint32_t mem0_base, mem0_size; - uint32_t io_base, io_size; - - io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16; - io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16; - mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16; - mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16; - - /* - * Here we assume the I/O window of second bus to be contiguous with - * the first. A gap is no problem but would waste address space for - * remapping the port space. - */ - mv_pci_io_mem1_resource.start = mv_io_size; - mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1; - mv_pci_mem1_resource.start = mem0_base; - mv_pci_mem1_resource.end = mem0_base + mem0_size - 1; - mv_bus1_controller.pcic.mem_offset = mem0_base; - mv_bus1_controller.pcic.io_offset = 0; - - ioport_resource.end = io_base + io_size -mv_io_base - 1; - - register_pci_controller(&mv_bus1_controller.pcic); - - mv_io_size = io_base + io_size - mv_io_base; -} - -static __init int __init ja_pci_init(void) -{ - unsigned long io_v_base; - uint32_t enable; - - enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE); - - /* - * We require at least one enabled I/O or PCI memory window or we - * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3. - */ - if (enable & (0x01 << 9) || enable & (0x01 << 10)) - ja_pci0_init(); - - if (enable & (0x01 << 14) || enable & (0x01 << 15)) - ja_pci1_init(); - - if (mv_io_size) { - io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size); - if (!io_v_base) - panic("Could not ioremap I/O port range"); - - set_io_port_base(io_v_base); - } - - return 0; -} - -arch_initcall(ja_pci_init); - -void __init plat_mem_setup(void) -{ - unsigned int tmpword; - - board_time_init = momenco_time_init; - - _machine_restart = momenco_jaguar_restart; - _machine_halt = momenco_jaguar_halt; - pm_power_off = momenco_jaguar_power_off; - - /* - * initrd_start = (unsigned long)jaguar_initrd_start; - * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size; - * initrd_below_start_ok = 1; - */ - - wire_stupidity_into_tlb(); - - /* - * shut down ethernet ports, just to be sure our memory doesn't get - * corrupted by random ethernet traffic. - */ - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8); - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff); - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1); - - /* Turn off the Bit-Error LED */ - JAGUAR_FPGA_WRITE(0x80, CLR); - - tmpword = JAGUAR_FPGA_READ(BOARDREV); - if (tmpword < 26) - printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n", - 'A'+tmpword); - else - printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n", - tmpword); - - tmpword = JAGUAR_FPGA_READ(FPGA_REV); - printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = JAGUAR_FPGA_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - switch (tmpword) { - case 0x1: - printk(" - Power-up reset\n"); - break; - case 0x2: - printk(" - Push-button reset\n"); - break; - case 0x8: - printk(" - Watchdog reset\n"); - break; - case 0x10: - printk(" - JTAG reset\n"); - break; - default: - printk(" - Unknown reset cause\n"); - } - reset_reason = tmpword; - JAGUAR_FPGA_WRITE(0xff, RESET_STATUS); - - tmpword = JAGUAR_FPGA_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - - /* 256MiB of RM9000x2 DDR */ -// add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM); - - /* 128MiB of MV-64340 DDR */ -// add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM); - - /* XXX Memory configuration should be picked up from PMON2k */ -#ifdef CONFIG_JAGUAR_DMALOW - printk("Jaguar ATX DMA-low mode set\n"); - add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM); - add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM); -#else - /* 128MiB of MV-64340 DDR RAM */ - printk("Jaguar ATX DMA-low mode is not set\n"); - add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM); -#endif - -#ifdef GEMDEBUG_TRACEBUFFER - { - unsigned int tbControl; - tbControl = - 0 << 26 | /* post trigger delay 0 */ - 0x2 << 16 | /* sequential trace mode */ - // 0x0 << 16 | /* non-sequential trace mode */ - // 0xf << 4 | /* watchpoints disabled */ - 2 << 2 | /* armed */ - 2 ; /* interrupt disabled */ - printk ("setting tbControl = %08lx\n", tbControl); - write_32bit_cp0_set1_register($22, tbControl); - __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t"); - - } -#endif -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/Makefile mips/arch/mips/pci/Makefile --- mips-orig/arch/mips/pci/Makefile 2006-09-21 00:57:25.810853750 +0900 +++ mips/arch/mips/pci/Makefile 2006-09-21 00:57:52.744537000 +0900 @@ -34,7 +34,6 @@ obj-$(CONFIG_SOC_AU1500) += fixup-au1000 obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o -obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-jaguar.c mips/arch/mips/pci/fixup-jaguar.c --- mips-orig/arch/mips/pci/fixup-jaguar.c 2006-09-21 00:46:01.016056750 +0900 +++ mips/arch/mips/pci/fixup-jaguar.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,43 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Marvell MV64340 interrupt fixup code. - * - * Marvell wants an NDA for their docs so this was written without - * documentation. You've been warned. - * - * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) - */ -#include -#include -#include - -#include - -/* - * WARNING: Example of how _NOT_ to do it. - */ -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) - return 3; /* PCI-X A */ - if (bus == 0 && slot == 2) - return 4; /* PCI-X B */ - if (bus == 1 && slot == 1) - return 5; /* PCI A */ - if (bus == 1 && slot == 2) - return 6; /* PCI B */ - -return 0; - panic("Whooops in pcibios_map_irq"); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/net/Kconfig mips/drivers/net/Kconfig --- mips-orig/drivers/net/Kconfig 2006-09-21 00:57:25.814854000 +0900 +++ mips/drivers/net/Kconfig 2006-09-21 00:59:23.530210750 +0900 @@ -2252,7 +2252,7 @@ config UGETH_HAS_GIGA config MV643XX_ETH tristate "MV-643XX Ethernet support" - depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MOMENCO_OCELOT_3 || PPC_MULTIPLATFORM + depends on MOMENCO_OCELOT_C || MV64360 || MOMENCO_OCELOT_3 || PPC_MULTIPLATFORM select MII help This driver supports the gigabit Ethernet on the Marvell MV643XX diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/bootinfo.h mips/include/asm-mips/bootinfo.h --- mips-orig/include/asm-mips/bootinfo.h 2006-09-21 00:57:25.830855000 +0900 +++ mips/include/asm-mips/bootinfo.h 2006-09-21 00:57:52.748537250 +0900 @@ -121,7 +121,6 @@ #define MACH_MOMENCO_OCELOT 0 #define MACH_MOMENCO_OCELOT_G 1 #define MACH_MOMENCO_OCELOT_C 2 -#define MACH_MOMENCO_JAGUAR_ATX 3 #define MACH_MOMENCO_OCELOT_3 4 /* diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/highmem.h mips/include/asm-mips/highmem.h --- mips-orig/include/asm-mips/highmem.h 2006-09-21 00:46:17.493086500 +0900 +++ mips/include/asm-mips/highmem.h 2006-09-21 00:57:52.748537250 +0900 @@ -47,41 +47,6 @@ extern pte_t *pkmap_page_table; extern void * kmap_high(struct page *page); extern void kunmap_high(struct page *page); -/* - * CONFIG_LIMITED_DMA is for systems with DMA limitations such as Momentum's - * Jaguar ATX. This option exploits the highmem code in the kernel so is - * always enabled together with CONFIG_HIGHMEM but at this time doesn't - * actually add highmem functionality. - */ - -#ifdef CONFIG_LIMITED_DMA - -/* - * These are the default functions for the no-highmem case from - * - */ -static inline void *kmap(struct page *page) -{ - might_sleep(); - return page_address(page); -} - -#define kunmap(page) do { (void) (page); } while (0) - -static inline void *kmap_atomic(struct page *page, enum km_type type) -{ - return page_address(page); -} - -static inline void kunmap_atomic(void *kvaddr, enum km_type type) { } -#define kmap_atomic_pfn(pfn, idx) page_address(pfn_to_page(pfn)) - -#define kmap_atomic_to_page(ptr) virt_to_page(ptr) - -#define flush_cache_kmaps() do { } while (0) - -#else /* LIMITED_DMA */ - extern void *__kmap(struct page *page); extern void __kunmap(struct page *page); extern void *__kmap_atomic(struct page *page, enum km_type type); @@ -97,8 +62,6 @@ extern struct page *__kmap_atomic_to_pag #define flush_cache_kmaps() flush_cache_all() -#endif /* LIMITED_DMA */ - #endif /* __KERNEL__ */ #endif /* _ASM_HIGHMEM_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/mach-ja/cpu-feature-overrides.h mips/include/asm-mips/mach-ja/cpu-feature-overrides.h --- mips-orig/include/asm-mips/mach-ja/cpu-feature-overrides.h 2006-09-21 00:46:18.013119000 +0900 +++ mips/include/asm-mips/mach-ja/cpu-feature-overrides.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,45 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Ralf Baechle - */ -#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H - -/* - * Momentum Jaguar ATX always has the RM9000 processor. - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_icache_snoops_remote_store 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 32 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/mach-ja/spaces.h mips/include/asm-mips/mach-ja/spaces.h --- mips-orig/include/asm-mips/mach-ja/spaces.h 2006-09-21 00:46:18.013119000 +0900 +++ mips/include/asm-mips/mach-ja/spaces.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,20 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef __ASM_MACH_JA_SPACES_H -#define __ASM_MACH_JA_SPACES_H - -/* - * Memory above this physical address will be considered highmem. - */ -#define HIGHMEM_START 0x08000000UL - -#include_next - -#endif /* __ASM_MACH_JA_SPACES_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/page.h mips/include/asm-mips/page.h --- mips-orig/include/asm-mips/page.h 2006-09-21 00:46:18.601155750 +0900 +++ mips/include/asm-mips/page.h 2006-09-21 00:57:52.760538000 +0900 @@ -164,10 +164,6 @@ typedef struct { unsigned long pgprot; } #define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) #define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) -#ifdef CONFIG_LIMITED_DMA -#define WANT_PAGE_VIRTUAL -#endif - #include #include diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/serial.h mips/include/asm-mips/serial.h --- mips-orig/include/asm-mips/serial.h 2006-09-21 00:57:25.842855750 +0900 +++ mips/include/asm-mips/serial.h 2006-09-21 00:57:52.760538000 +0900 @@ -112,25 +112,6 @@ #define STD_SERIAL_PORT_DEFNS #endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ -#ifdef CONFIG_MOMENCO_JAGUAR_ATX -/* Ordinary NS16552 duart with a 20MHz crystal. */ -#define JAGUAR_ATX_UART_CLK 20000000 -#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16) - -#define JAGUAR_ATX_SERIAL1_IRQ 6 -#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L - -#define _JAGUAR_ATX_SERIAL_INIT(int, base) \ - { .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \ - .flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ - .iomem_base = (u8 *) base, iomem_reg_shift: 2, \ - io_type: SERIAL_IO_MEM } -#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \ - _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE) -#else -#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS -#endif - #ifdef CONFIG_MOMENCO_OCELOT_3 #define OCELOT_3_BASE_BAUD ( 20000000 / 16 ) #define OCELOT_3_SERIAL_IRQ 6 diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/war.h mips/include/asm-mips/war.h --- mips-orig/include/asm-mips/war.h 2006-09-21 00:46:19.445208500 +0900 +++ mips/include/asm-mips/war.h 2006-09-21 00:57:52.760538000 +0900 @@ -171,8 +171,7 @@ * On the RM9000 there is a problem which makes the CreateDirtyExclusive * cache operation unusable on SMP systems. */ -#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \ - defined(CONFIG_BASLER_EXCITE) +#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) #define RM9000_CDEX_SMP_WAR 1 #endif @@ -181,8 +180,8 @@ * where invalid instructions in the same I-cache line worth of instructions * being fetched may case spurious exceptions. */ -#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ - defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) +#if defined(CONFIG_MOMENCO_OCELOT_3) || defined(CONFIG_PMC_YOSEMITE) || \ + defined(CONFIG_BASLER_EXCITE) #define ICACHE_REFILLS_WORKAROUND_WAR 1 #endif From yoichi_yuasa@tripeaks.co.jp Wed Sep 20 18:08:59 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Sep 2006 18:09:04 +0100 (BST) Received: from mo32.po.2iij.net ([210.128.50.17]:56329 "EHLO mo32.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20027607AbWITRIK (ORCPT ); Wed, 20 Sep 2006 18:08:10 +0100 Received: by mo.po.2iij.net (mo32) id k8KH83w0007074; Thu, 21 Sep 2006 02:08:03 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox33) id k8KH7tCK096142 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 21 Sep 2006 02:07:56 +0900 (JST) Date: Thu, 21 Sep 2006 01:57:58 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH 1/4] removed MIPS EV96100 evaluation board support Message-Id: <20060921015758.639c4545.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20060921015638.480ea7b1.yoichi_yuasa@tripeaks.co.jp> References: <20060921015638.480ea7b1.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12608 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips This patch has removed MIPS EV96100 evaluation board support. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/Documentation/feature-removal-schedule.txt mips/Documentation/feature-removal-schedule.txt --- mips-orig/Documentation/feature-removal-schedule.txt 2006-09-21 00:45:57.327826250 +0900 +++ mips/Documentation/feature-removal-schedule.txt 2006-09-21 00:46:07.336451750 +0900 @@ -202,14 +202,6 @@ Who: Nick Piggin --------------------------- -What: Support for the MIPS EV96100 evaluation board -When: September 2006 -Why: Does no longer build since at least November 15, 2003, apparently - no userbase left. -Who: Ralf Baechle - ---------------------------- - What: Support for the Momentum / PMC-Sierra Jaguar ATX evaluation board When: September 2006 Why: Does no longer build since quite some time, and was never popular, diff -pruN -X mips/Documentation/dontdiff mips-orig/Documentation/kernel-parameters.txt mips/Documentation/kernel-parameters.txt --- mips-orig/Documentation/kernel-parameters.txt 2006-09-21 00:45:57.443833500 +0900 +++ mips/Documentation/kernel-parameters.txt 2006-09-21 00:53:06.886672000 +0900 @@ -573,8 +573,6 @@ running once the system is up. gscd= [HW,CD] Format: - gt96100eth= [NET] MIPS GT96100 Advanced Communication Controller - gus= [HW,OSS] Format: ,,, diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Kconfig mips/arch/mips/Kconfig --- mips-orig/arch/mips/Kconfig 2006-09-21 00:46:00.103999750 +0900 +++ mips/arch/mips/Kconfig 2006-09-21 00:46:07.440458250 +0900 @@ -202,26 +202,6 @@ config MIPS_EV64120 . Say Y here if you wish to build a kernel for this platform. -config MIPS_EV96100 - bool "Galileo EV96100 Evaluation board (EXPERIMENTAL)" - depends on EXPERIMENTAL - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select MIPS_GT96100 - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_R5000 - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_BIG_ENDIAN - help - This is an evaluation board based on the Galileo GT-96100 LAN/WAN - communications controllers containing a MIPS R5000 compatible core - running at 83MHz. Their website is . Say Y - here if you wish to build a kernel for this platform. - config MIPS_IVR bool "Globespan IVR board" select DMA_NONCOHERENT @@ -1051,10 +1031,6 @@ config AU1X00_USB_DEVICE depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 default n -config MIPS_GT96100 - bool - select MIPS_GT64120 - config IT8172_CIR bool depends on MIPS_ITE8172 || MIPS_IVR diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Makefile mips/arch/mips/Makefile --- mips-orig/arch/mips/Makefile 2006-09-21 00:46:00.103999750 +0900 +++ mips/arch/mips/Makefile 2006-09-21 00:46:07.452459000 +0900 @@ -280,13 +280,6 @@ cflags-$(CONFIG_MIPS_EV64120) += -Iinclu load-$(CONFIG_MIPS_EV64120) += 0xffffffff80100000 # -# Galileo EV96100 Board -# -core-$(CONFIG_MIPS_EV96100) += arch/mips/galileo-boards/ev96100/ -cflags-$(CONFIG_MIPS_EV96100) += -Iinclude/asm-mips/mach-ev96100 -load-$(CONFIG_MIPS_EV96100) += 0xffffffff80100000 - -# # Wind River PPMC Board (4KC + GT64120) # core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/ev96100_defconfig mips/arch/mips/configs/ev96100_defconfig --- mips-orig/arch/mips/configs/ev96100_defconfig 2006-09-21 00:46:00.156003000 +0900 +++ mips/arch/mips/configs/ev96100_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,850 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:05 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -CONFIG_MIPS_EV96100=y -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_MIPS_GT64120=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_MIPS_GT96100=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -CONFIG_CPU_RM7000=y -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_R5000=y -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_HOTPLUG is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_KMOD is not set - -# -# Block layer -# -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -# CONFIG_PCI is not set -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -# CONFIG_PACKET is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# PHY device support -# -CONFIG_PHYLIB=m - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_LXT_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_SMSC_PHY=m - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -CONFIG_MIPS_GT96100ETH=y -# CONFIG_DM9000 is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=m - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=m -CONFIG_CRC32=m -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/galileo-boards/ev96100/Makefile mips/arch/mips/galileo-boards/ev96100/Makefile --- mips-orig/arch/mips/galileo-boards/ev96100/Makefile 2006-09-21 00:46:00.208006250 +0900 +++ mips/arch/mips/galileo-boards/ev96100/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,9 +0,0 @@ -# -# Copyright 2000 MontaVista Software Inc. -# Author: MontaVista Software, Inc. -# ppopov@mvista.com or source@mvista.com -# -# Makefile for the Galileo EV96100 board. -# - -obj-y += init.o irq.o puts.o reset.o time.o setup.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/galileo-boards/ev96100/init.c mips/arch/mips/galileo-boards/ev96100/init.c --- mips-orig/arch/mips/galileo-boards/ev96100/init.c 2006-09-21 00:46:00.208006250 +0900 +++ mips/arch/mips/galileo-boards/ev96100/init.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,173 +0,0 @@ -/* - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/generic/generic.c - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include - - -/* Environment variable */ - -typedef struct { - char *name; - char *val; -} t_env_var; - -int prom_argc; -char **prom_argv, **prom_envp; - -int init_debug = 0; - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; -} - -char *prom_getenv(char *envname) -{ - /* - * Return a pointer to the given environment variable. - */ - - t_env_var *env = (t_env_var *) prom_envp; - int i; - - i = strlen(envname); - - while (env->name) { - if (strncmp(envname, env->name, i) == 0) { - return (env->val); - } - env++; - } - return (NULL); -} - -static inline unsigned char str2hexnum(unsigned char c) -{ - if (c >= '0' && c <= '9') - return c - '0'; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return 0; /* foo */ -} - -static inline void str2eaddr(unsigned char *ea, unsigned char *str) -{ - int i; - - for (i = 0; i < 6; i++) { - unsigned char num; - - if ((*str == '.') || (*str == ':')) - str++; - num = str2hexnum(*str++) << 4; - num |= (str2hexnum(*str++)); - ea[i] = num; - } -} - -int get_ethernet_addr(char *ethernet_addr) -{ - char *ethaddr_str; - - ethaddr_str = prom_getenv("ethaddr"); - if (!ethaddr_str) { - printk("ethaddr not set in boot prom\n"); - return -1; - } - str2eaddr(ethernet_addr, ethaddr_str); - - if (init_debug > 1) { - int i; - printk("get_ethernet_addr: "); - for (i = 0; i < 5; i++) - printk("%02x:", - (unsigned char) *(ethernet_addr + i)); - printk("%02x\n", *(ethernet_addr + i)); - } - - return 0; -} - -const char *get_system_type(void) -{ - return "Galileo EV96100"; -} - -void __init prom_init(void) -{ - volatile unsigned char *uart; - char ppbuf[8]; - - prom_argc = fw_arg0; - prom_argv = (char **) fw_arg1; - prom_envp = (char **) fw_arg2; - - mips_machgroup = MACH_GROUP_GALILEO; - mips_machtype = MACH_EV96100; - - prom_init_cmdline(); - - /* 32 MB upgradable */ - add_memory_region(0, 32 << 20, BOOT_MEM_RAM); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/galileo-boards/ev96100/irq.c mips/arch/mips/galileo-boards/ev96100/irq.c --- mips-orig/arch/mips/galileo-boards/ev96100/irq.c 2006-09-21 00:46:00.208006250 +0900 +++ mips/arch/mips/galileo-boards/ev96100/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,77 +0,0 @@ -/* - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/atlas/atlas_int.c. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static inline unsigned int ffz8(unsigned int word) -{ - unsigned long k; - - k = 7; - if (word & 0x0fUL) { k -= 4; word <<= 4; } - if (word & 0x30UL) { k -= 2; word <<= 2; } - if (word & 0x40UL) { k -= 1; } - - return k; -} - -extern void mips_timer_interrupt(struct pt_regs *regs); - -asmlinkage void ev96100_cpu_irq(unsigned int pending, struct pt_regs *regs) -{ - do_IRQ(ffz8(pending >> 8), regs); -} - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - - if (pending & CAUSEF_IP7) - mips_timer_interrupt(regs); - else if (pending) - ev96100_cpu_irq(pending, regs); - else - spurious_interrupt(regs); -} - -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(0); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/galileo-boards/ev96100/puts.c mips/arch/mips/galileo-boards/ev96100/puts.c --- mips-orig/arch/mips/galileo-boards/ev96100/puts.c 2006-09-21 00:46:00.208006250 +0900 +++ mips/arch/mips/galileo-boards/ev96100/puts.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,138 +0,0 @@ - -/* - * Debug routines which directly access the uart. - */ - -#include -#include - - -//#define SERIAL_BASE EV96100_UART0_REGS_BASE -#define SERIAL_BASE 0xBD000020 -#define NS16550_BASE SERIAL_BASE - -#define SERA_CMD 0x0D -#define SERA_DATA 0x08 -//#define SERB_CMD 0x05 -#define SERB_CMD 20 -#define SERB_DATA 0x00 -#define TX_BUSY 0x20 - -#define TIMEOUT 0xffff -#undef SLOW_DOWN - -static const char digits[16] = "0123456789abcdef"; -static volatile unsigned char *const com1 = (unsigned char *) SERIAL_BASE; - - -#ifdef SLOW_DOWN -static inline void slow_down() -{ - int k; - for (k = 0; k < 10000; k++); -} -#else -#define slow_down() -#endif - -void putch(const unsigned char c) -{ - unsigned char ch; - int i = 0; - - do { - ch = com1[SERB_CMD]; - slow_down(); - i++; - if (i > TIMEOUT) { - break; - } - } while (0 == (ch & TX_BUSY)); - com1[SERB_DATA] = c; -} - -void putchar(const unsigned char c) -{ - unsigned char ch; - int i = 0; - - do { - ch = com1[SERB_CMD]; - slow_down(); - i++; - if (i > TIMEOUT) { - break; - } - } while (0 == (ch & TX_BUSY)); - com1[SERB_DATA] = c; -} - -void puts(unsigned char *cp) -{ - unsigned char ch; - int i = 0; - - while (*cp) { - do { - ch = com1[SERB_CMD]; - slow_down(); - i++; - if (i > TIMEOUT) { - break; - } - } while (0 == (ch & TX_BUSY)); - com1[SERB_DATA] = *cp++; - } - putch('\r'); - putch('\n'); -} - -void fputs(unsigned char *cp) -{ - unsigned char ch; - int i = 0; - - while (*cp) { - - do { - ch = com1[SERB_CMD]; - slow_down(); - i++; - if (i > TIMEOUT) { - break; - } - } while (0 == (ch & TX_BUSY)); - com1[SERB_DATA] = *cp++; - } -} - - -void put64(uint64_t ul) -{ - int cnt; - unsigned ch; - - cnt = 16; /* 16 nibbles in a 64 bit long */ - putch('0'); - putch('x'); - do { - cnt--; - ch = (unsigned char) (ul >> cnt * 4) & 0x0F; - putch(digits[ch]); - } while (cnt > 0); -} - -void put32(unsigned u) -{ - int cnt; - unsigned ch; - - cnt = 8; /* 8 nibbles in a 32 bit long */ - putch('0'); - putch('x'); - do { - cnt--; - ch = (unsigned char) (u >> cnt * 4) & 0x0F; - putch(digits[ch]); - } while (cnt > 0); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/galileo-boards/ev96100/reset.c mips/arch/mips/galileo-boards/ev96100/reset.c --- mips-orig/arch/mips/galileo-boards/ev96100/reset.c 2006-09-21 00:46:00.208006250 +0900 +++ mips/arch/mips/galileo-boards/ev96100/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,70 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Galileo EV96100 reset routines. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/generic/reset.c - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -static void mips_machine_restart(char *command); -static void mips_machine_halt(void); - -static void mips_machine_restart(char *command) -{ - set_c0_status(ST0_BEV | ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); - while (1); -} - -static void mips_machine_halt(void) -{ - printk(KERN_NOTICE "You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void mips_reboot_setup(void) -{ - _machine_restart = mips_machine_restart; - _machine_halt = mips_machine_halt; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/galileo-boards/ev96100/setup.c mips/arch/mips/galileo-boards/ev96100/setup.c --- mips-orig/arch/mips/galileo-boards/ev96100/setup.c 2006-09-21 00:46:00.208006250 +0900 +++ mips/arch/mips/galileo-boards/ev96100/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,159 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Galileo EV96100 setup. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/atlas/atlas_setup.c. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - - -extern char *__init prom_getcmdline(void); - -extern void mips_reboot_setup(void); - -unsigned char mac_0_1[12]; - -void __init plat_mem_setup(void) -{ - unsigned int config = read_c0_config(); - unsigned int status = read_c0_status(); - unsigned int info = read_c0_info(); - u32 tmp; - - char *argptr; - - clear_c0_status(ST0_FR); - - if (config & 0x8) - printk("Secondary cache is enabled\n"); - else - printk("Secondary cache is disabled\n"); - - if (status & (1 << 27)) - printk("User-mode cache ops enabled\n"); - else - printk("User-mode cache ops disabled\n"); - - printk("CP0 info reg: %x\n", (unsigned) info); - if (info & (1 << 28)) - printk("burst mode Scache RAMS\n"); - else - printk("pipelined Scache RAMS\n"); - - if (info & 0x1) - printk("Atomic Enable is set\n"); - - argptr = prom_getcmdline(); -#ifdef CONFIG_SERIAL_CONSOLE - if (strstr(argptr, "console=") == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS0,115200"); - } -#endif - - mips_reboot_setup(); - - set_io_port_base(KSEG1); - ioport_resource.start = GT_PCI_IO_BASE; - ioport_resource.end = GT_PCI_IO_BASE + 0x01ffffff; - -#ifdef CONFIG_BLK_DEV_INITRD - ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); -#endif - - - /* - * Setup GT controller master bit so we can do config cycles - */ - - /* Clear cause register bits */ - GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT)); - /* Setup address */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | - (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | - ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | - GT_PCI0_CFGADDR_CONFIGEN_BIT); - - udelay(2); - tmp = GT_READ(GT_PCI0_CFGDATA_OFS); - - tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SERR); - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | - (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | - ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | - GT_PCI0_CFGADDR_CONFIGEN_BIT); - udelay(2); - GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp); - - /* Setup address */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | - (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | - ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | - GT_PCI0_CFGADDR_CONFIGEN_BIT); - - udelay(2); - tmp = GT_READ(GT_PCI0_CFGDATA_OFS); -} - -unsigned short get_gt_devid(void) -{ - u32 gt_devid; - - /* Figure out if this is a gt96100 or gt96100A */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | - (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | - ((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | - GT_PCI0_CFGADDR_CONFIGEN_BIT); - - udelay(4); - gt_devid = GT_READ(GT_PCI0_CFGDATA_OFS); - - return gt_devid >> 16; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/galileo-boards/ev96100/time.c mips/arch/mips/galileo-boards/ev96100/time.c --- mips-orig/arch/mips/galileo-boards/ev96100/time.c 2006-09-21 00:46:00.208006250 +0900 +++ mips/arch/mips/galileo-boards/ev96100/time.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,88 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Galileo EV96100 rtc routines. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/atlas/atlas_rtc.c. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include - - -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) - -extern volatile unsigned long wall_jiffies; -unsigned long missed_heart_beats = 0; - -static unsigned long r4k_offset; /* Amount to increment compare reg each time */ -static unsigned long r4k_cur; /* What counter should be at next timer irq */ - -static inline void ack_r4ktimer(unsigned long newval) -{ - write_c0_compare(newval); -} - -/* - * There are a lot of conceptually broken versions of the MIPS timer interrupt - * handler floating around. This one is rather different, but the algorithm - * is probably more robust. - */ -void mips_timer_interrupt(struct pt_regs *regs) -{ - int irq = 7; /* FIX ME */ - - if (r4k_offset == 0) { - goto null; - } - - do { - kstat_this_cpu.irqs[irq]++; - do_timer(regs); -#ifndef CONFIG_SMP - update_process_times(user_mode(regs)); -#endif - r4k_cur += r4k_offset; - ack_r4ktimer(r4k_cur); - - } while (((unsigned long)read_c0_count() - - r4k_cur) < 0x7fffffff); - return; - -null: - ack_r4ktimer(0); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/Makefile mips/arch/mips/pci/Makefile --- mips-orig/arch/mips/pci/Makefile 2006-09-21 00:46:01.012056500 +0900 +++ mips/arch/mips/pci/Makefile 2006-09-21 00:46:07.464459750 +0900 @@ -11,7 +11,6 @@ obj-$(CONFIG_ITE_BOARD_GEN) += ops-it817 obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o -obj-$(CONFIG_MIPS_GT96100) += ops-gt96100.o obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o obj-$(CONFIG_MIPS_MSC) += ops-msc.o obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o @@ -29,7 +28,6 @@ obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_MIPS_EV64120) += fixup-ev64120.o -obj-$(CONFIG_MIPS_EV96100) += fixup-ev96100.o pci-ev96100.o obj-$(CONFIG_MIPS_ITE8172) += fixup-ite8172g.o obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ev96100.c mips/arch/mips/pci/fixup-ev96100.c --- mips-orig/arch/mips/pci/fixup-ev96100.c 2006-09-21 00:46:01.016056750 +0900 +++ mips/arch/mips/pci/fixup-ev96100.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,48 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * EV96100 Board specific pci fixups. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include - -static char irq_tab_ev96100[][5] __initdata = { - [8] = { 0, 5, 5, 5, 5 }, - [9] = { 0, 2, 2, 2, 2 } -}; - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_tab_ev96100[slot][pin]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/ops-gt96100.c mips/arch/mips/pci/ops-gt96100.c --- mips-orig/arch/mips/pci/ops-gt96100.c 2006-09-21 00:46:01.024057250 +0900 +++ mips/arch/mips/pci/ops-gt96100.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,169 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Galileo EV96100 board specific pci support. - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/generic/pci.c - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -#include -#include -#include - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -static int static gt96100_config_access(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, int where, u32 * data) -{ - unsigned char bus = bus->number; - u32 intr; - - /* - * Because of a bug in the galileo (for slot 31). - */ - if (bus == 0 && devfn >= PCI_DEVFN(31, 0)) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* Clear cause register bits */ - GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT)); - - /* Setup address */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) | - (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | - ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | - GT_PCI0_CFGADDR_CONFIGEN_BIT); - udelay(2); - - - if (access_type == PCI_ACCESS_WRITE) { - if (devfn != 0) - *data = le32_to_cpu(*data); - GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); - } else { - *data = GT_READ(GT_PCI0_CFGDATA_OFS); - if (devfn != 0) - *data = le32_to_cpu(*data); - } - - udelay(2); - - /* Check for master or target abort */ - intr = GT_READ(GT_INTRCAUSE_OFS); - - if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { - /* Error occured */ - - /* Clear bits */ - GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT)); - return -1; - } - return 0; -} - -/* - * We can't address 8 and 16 bit words directly. Instead we have to - * read/write a 32bit word and mask/modify the data we actually want. - */ -static int gt96100_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - u32 data = 0; - - if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - switch (size) { - case 1: - *val = (data >> ((where & 3) << 3)) & 0xff; - break; - - case 2: - *val = (data >> ((where & 3) << 3)) & 0xffff; - break; - - case 4: - *val = data; - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static int gt96100_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data = 0; - - switch (size) { - case 1: - if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (gt96100_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; - - case 2: - if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data)) - return -1; - - - return PCIBIOS_SUCCESSFUL; - - case 4: - if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &val)) - return -1; - - return PCIBIOS_SUCCESSFUL; - } -} - -struct pci_ops gt96100_pci_ops = { - .read = gt96100_pcibios_read, - .write = gt96100_pcibios_write -}; diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/pci-ev96100.c mips/arch/mips/pci/pci-ev96100.c --- mips-orig/arch/mips/pci/pci-ev96100.c 2006-09-21 00:46:01.032057750 +0900 +++ mips/arch/mips/pci/pci-ev96100.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,63 +0,0 @@ -/* - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -static struct resource pci_io_resource = { - .name = "io pci IO space", - .start = 0x10000000, - .end = 0x11ffffff, - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource = { - .name = "ext pci memory space", - .start = 0x12000000, - .end = 0x13ffffff, - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops gt96100_pci_ops; - -struct pci_controller ev96100_controller = { - .pci_ops = >96100_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, -}; - -static void ev96100_pci_init(void) -{ - register_pci_controller(&ev96100_controller); -} - -arch_initcall(ev96100_pci_init); diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/net/Kconfig mips/drivers/net/Kconfig --- mips-orig/drivers/net/Kconfig 2006-09-21 00:46:08.100499500 +0900 +++ mips/drivers/net/Kconfig 2006-09-21 00:51:48.629781250 +0900 @@ -446,12 +446,6 @@ config GALILEO_64240_ETH This is the driver for the ethernet interfaces integrated into the Galileo (now Marvell) GT64240 chipset. -config MIPS_GT96100ETH - bool "MIPS GT96100 Ethernet support" - depends on NET_ETHERNET && MIPS_GT96100 - help - Say Y here to support the Ethernet subsystem on your GT96100 card. - config MIPS_AU1X00_ENET bool "MIPS AU1000 Ethernet support" depends on NET_ETHERNET && SOC_AU1X00 diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/net/Makefile mips/drivers/net/Makefile --- mips-orig/drivers/net/Makefile 2006-09-21 00:46:08.100499500 +0900 +++ mips/drivers/net/Makefile 2006-09-21 00:52:01.742600750 +0900 @@ -179,7 +179,6 @@ obj-$(CONFIG_HPLANCE) += hplance.o 7990. obj-$(CONFIG_MVME147_NET) += mvme147.o 7990.o obj-$(CONFIG_EQUALIZER) += eql.o obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o -obj-$(CONFIG_MIPS_GT96100ETH) += gt96100eth.o obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/net/gt96100eth.c mips/drivers/net/gt96100eth.c --- mips-orig/drivers/net/gt96100eth.c 2006-09-21 00:46:08.328513750 +0900 +++ mips/drivers/net/gt96100eth.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,1566 +0,0 @@ -/* - * Copyright 2000, 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * stevel@mvista.com or source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Ethernet driver for the MIPS GT96100 Advanced Communication Controller. - * - * Revision history - * - * 11.11.2001 Moved to 2.4.14, ppopov@mvista.com. Modified driver to add - * proper gt96100A support. - * 12.05.2001 Moved eth port 0 to irq 3 (mapped to GT_SERINT0 on EV96100A) - * in order for both ports to work. Also cleaned up boot - * option support (mac address string parsing), fleshed out - * gt96100_cleanup_module(), and other general code cleanups - * . - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define DESC_BE 1 -#define DESC_DATA_BE 1 - -#define GT96100_DEBUG 2 - -#include "gt96100eth.h" - -// prototypes -static void* dmaalloc(size_t size, dma_addr_t *dma_handle); -static void dmafree(size_t size, void *vaddr); -static void gt96100_delay(int msec); -static int gt96100_add_hash_entry(struct net_device *dev, - unsigned char* addr); -static void read_mib_counters(struct gt96100_private *gp); -static int read_MII(int phy_addr, u32 reg); -static int write_MII(int phy_addr, u32 reg, u16 data); -static int gt96100_init_module(void); -static void gt96100_cleanup_module(void); -static void dump_MII(int dbg_lvl, struct net_device *dev); -static void dump_tx_desc(int dbg_lvl, struct net_device *dev, int i); -static void dump_rx_desc(int dbg_lvl, struct net_device *dev, int i); -static void dump_skb(int dbg_lvl, struct net_device *dev, - struct sk_buff *skb); -static void update_stats(struct gt96100_private *gp); -static void abort(struct net_device *dev, u32 abort_bits); -static void hard_stop(struct net_device *dev); -static void enable_ether_irq(struct net_device *dev); -static void disable_ether_irq(struct net_device *dev); -static int gt96100_probe1(struct pci_dev *pci, int port_num); -static void reset_tx(struct net_device *dev); -static void reset_rx(struct net_device *dev); -static int gt96100_check_tx_consistent(struct gt96100_private *gp); -static int gt96100_init(struct net_device *dev); -static int gt96100_open(struct net_device *dev); -static int gt96100_close(struct net_device *dev); -static int gt96100_tx(struct sk_buff *skb, struct net_device *dev); -static int gt96100_rx(struct net_device *dev, u32 status); -static irqreturn_t gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs); -static void gt96100_tx_timeout(struct net_device *dev); -static void gt96100_set_rx_mode(struct net_device *dev); -static struct net_device_stats* gt96100_get_stats(struct net_device *dev); - -extern char * __init prom_getcmdline(void); - -static int max_interrupt_work = 32; - -#define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0)) - -#define RUN_AT(x) (jiffies + (x)) - -// For reading/writing 32-bit words and half-words from/to DMA memory -#ifdef DESC_BE -#define cpu_to_dma32 cpu_to_be32 -#define dma32_to_cpu be32_to_cpu -#define cpu_to_dma16 cpu_to_be16 -#define dma16_to_cpu be16_to_cpu -#else -#define cpu_to_dma32 cpu_to_le32 -#define dma32_to_cpu le32_to_cpu -#define cpu_to_dma16 cpu_to_le16 -#define dma16_to_cpu le16_to_cpu -#endif - -static char mac0[18] = "00.02.03.04.05.06"; -static char mac1[18] = "00.01.02.03.04.05"; -module_param_string(mac0, mac0, 18, 0); -module_param_string(mac1, mac0, 18, 0); -MODULE_PARM_DESC(mac0, "MAC address for GT96100 ethernet port 0"); -MODULE_PARM_DESC(mac1, "MAC address for GT96100 ethernet port 1"); - -/* - * Info for the GT96100 ethernet controller's ports. - */ -static struct gt96100_if_t { - struct net_device *dev; - unsigned int iobase; // IO Base address of this port - int irq; // IRQ number of this port - char *mac_str; -} gt96100_iflist[NUM_INTERFACES] = { - { - NULL, - GT96100_ETH0_BASE, GT96100_ETHER0_IRQ, - mac0 - }, - { - NULL, - GT96100_ETH1_BASE, GT96100_ETHER1_IRQ, - mac1 - } -}; - -static inline const char* -chip_name(int chip_rev) -{ - switch (chip_rev) { - case REV_GT96100: - return "GT96100"; - case REV_GT96100A_1: - case REV_GT96100A: - return "GT96100A"; - default: - return "Unknown GT96100"; - } -} - -/* - DMA memory allocation, derived from pci_alloc_consistent. -*/ -static void * dmaalloc(size_t size, dma_addr_t *dma_handle) -{ - void *ret; - - ret = (void *)__get_free_pages(GFP_ATOMIC | GFP_DMA, get_order(size)); - - if (ret != NULL) { - dma_cache_inv((unsigned long)ret, size); - if (dma_handle != NULL) - *dma_handle = virt_to_phys(ret); - - /* bump virtual address up to non-cached area */ - ret = (void*)KSEG1ADDR(ret); - } - - return ret; -} - -static void dmafree(size_t size, void *vaddr) -{ - vaddr = (void*)KSEG0ADDR(vaddr); - free_pages((unsigned long)vaddr, get_order(size)); -} - -static void gt96100_delay(int ms) -{ - if (in_interrupt()) - return; - else - msleep_interruptible(ms); -} - -static int -parse_mac_addr(struct net_device *dev, char* macstr) -{ - int i, j; - unsigned char result, value; - - for (i=0; i<6; i++) { - result = 0; - if (i != 5 && *(macstr+2) != '.') { - err(__FILE__ "invalid mac address format: %d %c\n", - i, *(macstr+2)); - return -EINVAL; - } - - for (j=0; j<2; j++) { - if (isxdigit(*macstr) && - (value = isdigit(*macstr) ? *macstr-'0' : - toupper(*macstr)-'A'+10) < 16) { - result = result*16 + value; - macstr++; - } else { - err(__FILE__ "invalid mac address " - "character: %c\n", *macstr); - return -EINVAL; - } - } - - macstr++; // step over '.' - dev->dev_addr[i] = result; - } - - return 0; -} - - -static int -read_MII(int phy_addr, u32 reg) -{ - int timedout = 20; - u32 smir = smirOpCode | (phy_addr << smirPhyAdBit) | - (reg << smirRegAdBit); - - // wait for last operation to complete - while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) { - // snooze for 1 msec and check again - gt96100_delay(1); - - if (--timedout == 0) { - printk(KERN_ERR "%s: busy timeout!!\n", __FUNCTION__); - return -ENODEV; - } - } - - GT96100_WRITE(GT96100_ETH_SMI_REG, smir); - - timedout = 20; - // wait for read to complete - while (!((smir = GT96100_READ(GT96100_ETH_SMI_REG)) & smirReadValid)) { - // snooze for 1 msec and check again - gt96100_delay(1); - - if (--timedout == 0) { - printk(KERN_ERR "%s: timeout!!\n", __FUNCTION__); - return -ENODEV; - } - } - - return (int)(smir & smirDataMask); -} - -static void -dump_tx_desc(int dbg_lvl, struct net_device *dev, int i) -{ - struct gt96100_private *gp = netdev_priv(dev); - gt96100_td_t *td = &gp->tx_ring[i]; - - dbg(dbg_lvl, "Tx descriptor at 0x%08lx:\n", virt_to_phys(td)); - dbg(dbg_lvl, - " cmdstat=%04x, byte_cnt=%04x, buff_ptr=%04x, next=%04x\n", - dma32_to_cpu(td->cmdstat), - dma16_to_cpu(td->byte_cnt), - dma32_to_cpu(td->buff_ptr), - dma32_to_cpu(td->next)); -} - -static void -dump_rx_desc(int dbg_lvl, struct net_device *dev, int i) -{ - struct gt96100_private *gp = netdev_priv(dev); - gt96100_rd_t *rd = &gp->rx_ring[i]; - - dbg(dbg_lvl, "Rx descriptor at 0x%08lx:\n", virt_to_phys(rd)); - dbg(dbg_lvl, " cmdstat=%04x, buff_sz=%04x, byte_cnt=%04x, " - "buff_ptr=%04x, next=%04x\n", - dma32_to_cpu(rd->cmdstat), - dma16_to_cpu(rd->buff_sz), - dma16_to_cpu(rd->byte_cnt), - dma32_to_cpu(rd->buff_ptr), - dma32_to_cpu(rd->next)); -} - -static int -write_MII(int phy_addr, u32 reg, u16 data) -{ - int timedout = 20; - u32 smir = (phy_addr << smirPhyAdBit) | - (reg << smirRegAdBit) | data; - - // wait for last operation to complete - while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) { - // snooze for 1 msec and check again - gt96100_delay(1); - - if (--timedout == 0) { - printk(KERN_ERR "%s: busy timeout!!\n", __FUNCTION__); - return -1; - } - } - - GT96100_WRITE(GT96100_ETH_SMI_REG, smir); - return 0; -} - -static void -dump_MII(int dbg_lvl, struct net_device *dev) -{ - int i, val; - struct gt96100_private *gp = netdev_priv(dev); - - if (dbg_lvl <= GT96100_DEBUG) { - for (i=0; i<7; i++) { - if ((val = read_MII(gp->phy_addr, i)) >= 0) - printk("MII Reg %d=%x\n", i, val); - } - for (i=16; i<21; i++) { - if ((val = read_MII(gp->phy_addr, i)) >= 0) - printk("MII Reg %d=%x\n", i, val); - } - } -} - -static void -dump_hw_addr(int dbg_lvl, struct net_device *dev, const char* pfx, - const char* func, unsigned char* addr_str) -{ - int i; - char buf[100], octet[5]; - - if (dbg_lvl <= GT96100_DEBUG) { - sprintf(buf, pfx, func); - for (i = 0; i < 6; i++) { - sprintf(octet, "%2.2x%s", - addr_str[i], i<5 ? ":" : "\n"); - strcat(buf, octet); - } - info("%s", buf); - } -} - - -static void -dump_skb(int dbg_lvl, struct net_device *dev, struct sk_buff *skb) -{ - int i; - unsigned char* skbdata; - - if (dbg_lvl <= GT96100_DEBUG) { - dbg(dbg_lvl, "%s: skb=%p, skb->data=%p, skb->len=%d\n", - __FUNCTION__, skb, skb->data, skb->len); - - skbdata = (unsigned char*)KSEG1ADDR(skb->data); - - for (i=0; ilen; i++) { - if (!(i % 16)) - printk(KERN_DEBUG "\n %3.3x: %2.2x,", - i, skbdata[i]); - else - printk(KERN_DEBUG "%2.2x,", skbdata[i]); - } - printk(KERN_DEBUG "\n"); - } -} - - -static int -gt96100_add_hash_entry(struct net_device *dev, unsigned char* addr) -{ - struct gt96100_private *gp = netdev_priv(dev); - //u16 hashResult, stmp; - //unsigned char ctmp, hash_ea[6]; - u32 tblEntry1, tblEntry0, *tblEntryAddr; - int i; - - tblEntry1 = hteValid | hteRD; - tblEntry1 |= (u32)addr[5] << 3; - tblEntry1 |= (u32)addr[4] << 11; - tblEntry1 |= (u32)addr[3] << 19; - tblEntry1 |= ((u32)addr[2] & 0x1f) << 27; - dbg(3, "%s: tblEntry1=%x\n", __FUNCTION__, tblEntry1); - tblEntry0 = ((u32)addr[2] >> 5) & 0x07; - tblEntry0 |= (u32)addr[1] << 3; - tblEntry0 |= (u32)addr[0] << 11; - dbg(3, "%s: tblEntry0=%x\n", __FUNCTION__, tblEntry0); - -#if 0 - - for (i=0; i<6; i++) { - // nibble swap - ctmp = nibswap(addr[i]); - // invert every nibble - hash_ea[i] = ((ctmp&1)<<3) | ((ctmp&8)>>3) | - ((ctmp&2)<<1) | ((ctmp&4)>>1); - hash_ea[i] |= ((ctmp&0x10)<<3) | ((ctmp&0x80)>>3) | - ((ctmp&0x20)<<1) | ((ctmp&0x40)>>1); - } - - dump_hw_addr(3, dev, "%s: nib swap/invt addr=", __FUNCTION__, hash_ea); - - if (gp->hash_mode == 0) { - hashResult = ((u16)hash_ea[0] & 0xfc) << 7; - stmp = ((u16)hash_ea[0] & 0x03) | - (((u16)hash_ea[1] & 0x7f) << 2); - stmp ^= (((u16)hash_ea[1] >> 7) & 0x01) | - ((u16)hash_ea[2] << 1); - stmp ^= (u16)hash_ea[3] | (((u16)hash_ea[4] & 1) << 8); - hashResult |= stmp; - } else { - return -1; // don't support hash mode 1 - } - - dbg(3, "%s: hashResult=%x\n", __FUNCTION__, hashResult); - - tblEntryAddr = - (u32 *)(&gp->hash_table[((u32)hashResult & 0x7ff) << 3]); - - dbg(3, "%s: tblEntryAddr=%p\n", tblEntryAddr, __FUNCTION__); - - for (i=0; i= HASH_HOP_NUMBER) { - err("%s: expired!\n", __FUNCTION__); - return -1; // Couldn't find an unused entry - } - -#else - - tblEntryAddr = (u32 *)gp->hash_table; - for (i=0; imib; - int i; - - for (i=0; imib; - struct net_device_stats *stats = &gp->stats; - - read_mib_counters(gp); - - stats->rx_packets = mib->totalFramesReceived; - stats->tx_packets = mib->framesSent; - stats->rx_bytes = mib->totalByteReceived; - stats->tx_bytes = mib->byteSent; - stats->rx_errors = mib->totalFramesReceived - mib->framesReceived; - //the tx error counters are incremented by the ISR - //rx_dropped incremented by gt96100_rx - //tx_dropped incremented by gt96100_tx - stats->multicast = mib->multicastFramesReceived; - // collisions incremented by gt96100_tx_complete - stats->rx_length_errors = mib->oversizeFrames + mib->fragments; - // The RxError condition means the Rx DMA encountered a - // CPU owned descriptor, which, if things are working as - // they should, means the Rx ring has overflowed. - stats->rx_over_errors = mib->macRxError; - stats->rx_crc_errors = mib->cRCError; -} - -static void -abort(struct net_device *dev, u32 abort_bits) -{ - struct gt96100_private *gp = netdev_priv(dev); - int timedout = 100; // wait up to 100 msec for hard stop to complete - - dbg(3, "%s\n", __FUNCTION__); - - // Return if neither Rx or Tx abort bits are set - if (!(abort_bits & (sdcmrAR | sdcmrAT))) - return; - - // make sure only the Rx/Tx abort bits are set - abort_bits &= (sdcmrAR | sdcmrAT); - - spin_lock(&gp->lock); - - // abort any Rx/Tx DMA immediately - GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, abort_bits); - - dbg(3, "%s: SDMA comm = %x\n", __FUNCTION__, - GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM)); - - // wait for abort to complete - while (GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM) & abort_bits) { - // snooze for 1 msec and check again - gt96100_delay(1); - - if (--timedout == 0) { - err("%s: timeout!!\n", __FUNCTION__); - break; - } - } - - spin_unlock(&gp->lock); -} - - -static void -hard_stop(struct net_device *dev) -{ - struct gt96100_private *gp = netdev_priv(dev); - - dbg(3, "%s\n", __FUNCTION__); - - disable_ether_irq(dev); - - abort(dev, sdcmrAR | sdcmrAT); - - // disable port - GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, 0); -} - - -static void -enable_ether_irq(struct net_device *dev) -{ - struct gt96100_private *gp = netdev_priv(dev); - u32 intMask; - /* - * route ethernet interrupt to GT_SERINT0 for port 0, - * GT_INT0 for port 1. - */ - int intr_mask_reg = (gp->port_num == 0) ? - GT96100_SERINT0_MASK : GT96100_INT0_HIGH_MASK; - - if (gp->chip_rev >= REV_GT96100A_1) { - intMask = icrTxBufferLow | icrTxEndLow | - icrTxErrorLow | icrRxOVR | icrTxUdr | - icrRxBufferQ0 | icrRxErrorQ0 | - icrMIIPhySTC | icrEtherIntSum; - } - else { - intMask = icrTxBufferLow | icrTxEndLow | - icrTxErrorLow | icrRxOVR | icrTxUdr | - icrRxBuffer | icrRxError | - icrMIIPhySTC | icrEtherIntSum; - } - - // unmask interrupts - GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, intMask); - - intMask = GT96100_READ(intr_mask_reg); - intMask |= 1<port_num; - GT96100_WRITE(intr_mask_reg, intMask); -} - -static void -disable_ether_irq(struct net_device *dev) -{ - struct gt96100_private *gp = netdev_priv(dev); - u32 intMask; - int intr_mask_reg = (gp->port_num == 0) ? - GT96100_SERINT0_MASK : GT96100_INT0_HIGH_MASK; - - intMask = GT96100_READ(intr_mask_reg); - intMask &= ~(1<port_num); - GT96100_WRITE(intr_mask_reg, intMask); - - GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, 0); -} - - -/* - * Init GT96100 ethernet controller driver - */ -static int gt96100_init_module(void) -{ - struct pci_dev *pci; - int i, retval=0; - u32 cpuConfig; - - /* - * Stupid probe because this really isn't a PCI device - */ - if (!(pci = pci_find_device(PCI_VENDOR_ID_MARVELL, - PCI_DEVICE_ID_MARVELL_GT96100, NULL)) && - !(pci = pci_find_device(PCI_VENDOR_ID_MARVELL, - PCI_DEVICE_ID_MARVELL_GT96100A, NULL))) { - printk(KERN_ERR __FILE__ ": GT96100 not found!\n"); - return -ENODEV; - } - - cpuConfig = GT96100_READ(GT96100_CPU_INTERF_CONFIG); - if (cpuConfig & (1<<12)) { - printk(KERN_ERR __FILE__ - ": must be in Big Endian mode!\n"); - return -ENODEV; - } - - for (i=0; i < NUM_INTERFACES; i++) - retval |= gt96100_probe1(pci, i); - - return retval; -} - -static int __init gt96100_probe1(struct pci_dev *pci, int port_num) -{ - struct gt96100_private *gp = NULL; - struct gt96100_if_t *gtif = >96100_iflist[port_num]; - int phy_addr, phy_id1, phy_id2; - u32 phyAD; - int retval; - unsigned char chip_rev; - struct net_device *dev = NULL; - - if (gtif->irq < 0) { - printk(KERN_ERR "%s: irq unknown - probing not supported\n", - __FUNCTION__); - return -ENODEV; - } - - pci_read_config_byte(pci, PCI_REVISION_ID, &chip_rev); - - if (chip_rev >= REV_GT96100A_1) { - phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG); - phy_addr = (phyAD >> (5*port_num)) & 0x1f; - } else { - /* - * not sure what's this about -- probably a gt bug - */ - phy_addr = port_num; - phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG); - phyAD &= ~(0x1f << (port_num*5)); - phyAD |= phy_addr << (port_num*5); - GT96100_WRITE(GT96100_ETH_PHY_ADDR_REG, phyAD); - } - - // probe for the external PHY - if ((phy_id1 = read_MII(phy_addr, 2)) <= 0 || - (phy_id2 = read_MII(phy_addr, 3)) <= 0) { - printk(KERN_ERR "%s: no PHY found on MII%d\n", __FUNCTION__, port_num); - return -ENODEV; - } - - if (!request_region(gtif->iobase, GT96100_ETH_IO_SIZE, "GT96100ETH")) { - printk(KERN_ERR "%s: request_region failed\n", __FUNCTION__); - return -EBUSY; - } - - dev = alloc_etherdev(sizeof(struct gt96100_private)); - if (!dev) - goto out; - gtif->dev = dev; - - /* private struct aligned and zeroed by alloc_etherdev */ - /* Fill in the 'dev' fields. */ - dev->base_addr = gtif->iobase; - dev->irq = gtif->irq; - - if ((retval = parse_mac_addr(dev, gtif->mac_str))) { - err("%s: MAC address parse failed\n", __FUNCTION__); - retval = -EINVAL; - goto out1; - } - - gp = netdev_priv(dev); - - memset(gp, 0, sizeof(*gp)); // clear it - - gp->port_num = port_num; - gp->port_offset = port_num * GT96100_ETH_IO_SIZE; - gp->phy_addr = phy_addr; - gp->chip_rev = chip_rev; - - info("%s found at 0x%x, irq %d\n", - chip_name(gp->chip_rev), gtif->iobase, gtif->irq); - dump_hw_addr(0, dev, "%s: HW Address ", __FUNCTION__, dev->dev_addr); - info("%s chip revision=%d\n", chip_name(gp->chip_rev), gp->chip_rev); - info("%s ethernet port %d\n", chip_name(gp->chip_rev), gp->port_num); - info("external PHY ID1=0x%04x, ID2=0x%04x\n", phy_id1, phy_id2); - - // Allocate Rx and Tx descriptor rings - if (gp->rx_ring == NULL) { - // All descriptors in ring must be 16-byte aligned - gp->rx_ring = dmaalloc(sizeof(gt96100_rd_t) * RX_RING_SIZE - + sizeof(gt96100_td_t) * TX_RING_SIZE, - &gp->rx_ring_dma); - if (gp->rx_ring == NULL) { - retval = -ENOMEM; - goto out1; - } - - gp->tx_ring = (gt96100_td_t *)(gp->rx_ring + RX_RING_SIZE); - gp->tx_ring_dma = - gp->rx_ring_dma + sizeof(gt96100_rd_t) * RX_RING_SIZE; - } - - // Allocate the Rx Data Buffers - if (gp->rx_buff == NULL) { - gp->rx_buff = dmaalloc(PKT_BUF_SZ*RX_RING_SIZE, - &gp->rx_buff_dma); - if (gp->rx_buff == NULL) { - retval = -ENOMEM; - goto out2; - } - } - - dbg(3, "%s: rx_ring=%p, tx_ring=%p\n", __FUNCTION__, - gp->rx_ring, gp->tx_ring); - - // Allocate Rx Hash Table - if (gp->hash_table == NULL) { - gp->hash_table = (char*)dmaalloc(RX_HASH_TABLE_SIZE, - &gp->hash_table_dma); - if (gp->hash_table == NULL) { - retval = -ENOMEM; - goto out3; - } - } - - dbg(3, "%s: hash=%p\n", __FUNCTION__, gp->hash_table); - - spin_lock_init(&gp->lock); - - dev->open = gt96100_open; - dev->hard_start_xmit = gt96100_tx; - dev->stop = gt96100_close; - dev->get_stats = gt96100_get_stats; - //dev->do_ioctl = gt96100_ioctl; - dev->set_multicast_list = gt96100_set_rx_mode; - dev->tx_timeout = gt96100_tx_timeout; - dev->watchdog_timeo = GT96100ETH_TX_TIMEOUT; - - retval = register_netdev(dev); - if (retval) - goto out4; - return 0; - -out4: - dmafree(RX_HASH_TABLE_SIZE, gp->hash_table_dma); -out3: - dmafree(PKT_BUF_SZ*RX_RING_SIZE, gp->rx_buff); -out2: - dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE - + sizeof(gt96100_td_t) * TX_RING_SIZE, - gp->rx_ring); -out1: - free_netdev (dev); -out: - release_region(gtif->iobase, GT96100_ETH_IO_SIZE); - - err("%s failed. Returns %d\n", __FUNCTION__, retval); - return retval; -} - - -static void -reset_tx(struct net_device *dev) -{ - struct gt96100_private *gp = netdev_priv(dev); - int i; - - abort(dev, sdcmrAT); - - for (i=0; itx_skbuff[i]) { - if (in_interrupt()) - dev_kfree_skb_irq(gp->tx_skbuff[i]); - else - dev_kfree_skb(gp->tx_skbuff[i]); - gp->tx_skbuff[i] = NULL; - } - - gp->tx_ring[i].cmdstat = 0; // CPU owns - gp->tx_ring[i].byte_cnt = 0; - gp->tx_ring[i].buff_ptr = 0; - gp->tx_ring[i].next = - cpu_to_dma32(gp->tx_ring_dma + - sizeof(gt96100_td_t) * (i+1)); - dump_tx_desc(4, dev, i); - } - /* Wrap the ring. */ - gp->tx_ring[i-1].next = cpu_to_dma32(gp->tx_ring_dma); - - // setup only the lowest priority TxCDP reg - GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR0, gp->tx_ring_dma); - GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR1, 0); - - // init Tx indeces and pkt counter - gp->tx_next_in = gp->tx_next_out = 0; - gp->tx_count = 0; - -} - -static void -reset_rx(struct net_device *dev) -{ - struct gt96100_private *gp = netdev_priv(dev); - int i; - - abort(dev, sdcmrAR); - - for (i=0; irx_ring[i].next = - cpu_to_dma32(gp->rx_ring_dma + - sizeof(gt96100_rd_t) * (i+1)); - gp->rx_ring[i].buff_ptr = - cpu_to_dma32(gp->rx_buff_dma + i*PKT_BUF_SZ); - gp->rx_ring[i].buff_sz = cpu_to_dma16(PKT_BUF_SZ); - // Give ownership to device, set first and last, enable intr - gp->rx_ring[i].cmdstat = - cpu_to_dma32((u32)(rxFirst | rxLast | rxOwn | rxEI)); - dump_rx_desc(4, dev, i); - } - /* Wrap the ring. */ - gp->rx_ring[i-1].next = cpu_to_dma32(gp->rx_ring_dma); - - // Setup only the lowest priority RxFDP and RxCDP regs - for (i=0; i<4; i++) { - if (i == 0) { - GT96100ETH_WRITE(gp, GT96100_ETH_1ST_RX_DESC_PTR0, - gp->rx_ring_dma); - GT96100ETH_WRITE(gp, GT96100_ETH_CURR_RX_DESC_PTR0, - gp->rx_ring_dma); - } else { - GT96100ETH_WRITE(gp, - GT96100_ETH_1ST_RX_DESC_PTR0 + i*4, - 0); - GT96100ETH_WRITE(gp, - GT96100_ETH_CURR_RX_DESC_PTR0 + i*4, - 0); - } - } - - // init Rx NextOut index - gp->rx_next_out = 0; -} - - -// Returns 1 if the Tx counter and indeces don't gel -static int -gt96100_check_tx_consistent(struct gt96100_private *gp) -{ - int diff = gp->tx_next_in - gp->tx_next_out; - - diff = diff<0 ? TX_RING_SIZE + diff : diff; - diff = gp->tx_count == TX_RING_SIZE ? diff + TX_RING_SIZE : diff; - - return (diff != gp->tx_count); -} - -static int -gt96100_init(struct net_device *dev) -{ - struct gt96100_private *gp = netdev_priv(dev); - u32 tmp; - u16 mii_reg; - - dbg(3, "%s: dev=%p\n", __FUNCTION__, dev); - dbg(3, "%s: scs10_lo=%4x, scs10_hi=%4x\n", __FUNCTION__, - GT96100_READ(0x8), GT96100_READ(0x10)); - dbg(3, "%s: scs32_lo=%4x, scs32_hi=%4x\n", __FUNCTION__, - GT96100_READ(0x18), GT96100_READ(0x20)); - - // Stop and disable Port - hard_stop(dev); - - // Setup CIU Arbiter - tmp = GT96100_READ(GT96100_CIU_ARBITER_CONFIG); - tmp |= (0x0c << (gp->port_num*2)); // set Ether DMA req priority to hi -#ifndef DESC_BE - tmp &= ~(1<<31); // set desc endianess to little -#else - tmp |= (1<<31); -#endif - GT96100_WRITE(GT96100_CIU_ARBITER_CONFIG, tmp); - dbg(3, "%s: CIU Config=%x/%x\n", __FUNCTION__, - tmp, GT96100_READ(GT96100_CIU_ARBITER_CONFIG)); - - // Set routing. - tmp = GT96100_READ(GT96100_ROUTE_MAIN) & (0x3f << 18); - tmp |= (0x07 << (18 + gp->port_num*3)); - GT96100_WRITE(GT96100_ROUTE_MAIN, tmp); - - /* set MII as peripheral func */ - tmp = GT96100_READ(GT96100_GPP_CONFIG2); - tmp |= 0x7fff << (gp->port_num*16); - GT96100_WRITE(GT96100_GPP_CONFIG2, tmp); - - /* Set up MII port pin directions */ - tmp = GT96100_READ(GT96100_GPP_IO2); - tmp |= 0x003d << (gp->port_num*16); - GT96100_WRITE(GT96100_GPP_IO2, tmp); - - // Set-up hash table - memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it - gp->hash_mode = 0; - // Add a single entry to hash table - our ethernet address - gt96100_add_hash_entry(dev, dev->dev_addr); - // Set-up DMA ptr to hash table - GT96100ETH_WRITE(gp, GT96100_ETH_HASH_TBL_PTR, gp->hash_table_dma); - dbg(3, "%s: Hash Tbl Ptr=%x\n", __FUNCTION__, - GT96100ETH_READ(gp, GT96100_ETH_HASH_TBL_PTR)); - - // Setup Tx - reset_tx(dev); - - dbg(3, "%s: Curr Tx Desc Ptr0=%x\n", __FUNCTION__, - GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0)); - - // Setup Rx - reset_rx(dev); - - dbg(3, "%s: 1st/Curr Rx Desc Ptr0=%x/%x\n", __FUNCTION__, - GT96100ETH_READ(gp, GT96100_ETH_1ST_RX_DESC_PTR0), - GT96100ETH_READ(gp, GT96100_ETH_CURR_RX_DESC_PTR0)); - - // eth port config register - GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT, - pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrDPLXen); - - mii_reg = read_MII(gp->phy_addr, 0x11); /* int enable register */ - mii_reg |= 2; /* enable mii interrupt */ - write_MII(gp->phy_addr, 0x11, mii_reg); - - dbg(3, "%s: PhyAD=%x\n", __FUNCTION__, - GT96100_READ(GT96100_ETH_PHY_ADDR_REG)); - - // setup DMA - - // We want the Rx/Tx DMA to write/read data to/from memory in - // Big Endian mode. Also set DMA Burst Size to 8 64Bit words. -#ifdef DESC_DATA_BE - GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG, - (0xf<irq, dev); - return retval; - } - - if ((retval = request_irq(dev->irq, >96100_interrupt, - IRQF_SHARED, dev->name, dev))) { - err("unable to get IRQ %d\n", dev->irq); - return retval; - } - - dbg(2, "%s: Initialization done.\n", __FUNCTION__); - - return 0; -} - -static int -gt96100_close(struct net_device *dev) -{ - dbg(3, "%s: dev=%p\n", __FUNCTION__, dev); - - // stop the device - if (netif_device_present(dev)) { - netif_stop_queue(dev); - hard_stop(dev); - } - - free_irq(dev->irq, dev); - - return 0; -} - - -static int -gt96100_tx(struct sk_buff *skb, struct net_device *dev) -{ - struct gt96100_private *gp = netdev_priv(dev); - unsigned long flags; - int nextIn; - - spin_lock_irqsave(&gp->lock, flags); - - nextIn = gp->tx_next_in; - - dbg(3, "%s: nextIn=%d\n", __FUNCTION__, nextIn); - - if (gp->tx_count >= TX_RING_SIZE) { - warn("Tx Ring full, pkt dropped.\n"); - gp->stats.tx_dropped++; - spin_unlock_irqrestore(&gp->lock, flags); - return 1; - } - - if (!(gp->last_psr & psrLink)) { - err("%s: Link down, pkt dropped.\n", __FUNCTION__); - gp->stats.tx_dropped++; - spin_unlock_irqrestore(&gp->lock, flags); - return 1; - } - - if (dma32_to_cpu(gp->tx_ring[nextIn].cmdstat) & txOwn) { - err("%s: device owns descriptor, pkt dropped.\n", __FUNCTION__); - gp->stats.tx_dropped++; - // stop the queue, so Tx timeout can fix it - netif_stop_queue(dev); - spin_unlock_irqrestore(&gp->lock, flags); - return 1; - } - - // Prepare the Descriptor at tx_next_in - gp->tx_skbuff[nextIn] = skb; - gp->tx_ring[nextIn].byte_cnt = cpu_to_dma16(skb->len); - gp->tx_ring[nextIn].buff_ptr = cpu_to_dma32(virt_to_phys(skb->data)); - // make sure packet gets written back to memory - dma_cache_wback_inv((unsigned long)(skb->data), skb->len); - // Give ownership to device, set first and last desc, enable interrupt - // Setting of ownership bit must be *last*! - gp->tx_ring[nextIn].cmdstat = - cpu_to_dma32((u32)(txOwn | txGenCRC | txEI | - txPad | txFirst | txLast)); - - dump_tx_desc(4, dev, nextIn); - dump_skb(4, dev, skb); - - // increment tx_next_in with wrap - gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE; - // If DMA is stopped, restart - if (!(GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS) & psrTxLow)) - GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, - sdcmrERD | sdcmrTXDL); - - // increment count and stop queue if full - if (++gp->tx_count == TX_RING_SIZE) { - gp->tx_full = 1; - netif_stop_queue(dev); - dbg(2, "Tx Ring now full, queue stopped.\n"); - } - - dev->trans_start = jiffies; - spin_unlock_irqrestore(&gp->lock, flags); - - return 0; -} - - -static int -gt96100_rx(struct net_device *dev, u32 status) -{ - struct gt96100_private *gp = netdev_priv(dev); - struct sk_buff *skb; - int pkt_len, nextOut, cdp; - gt96100_rd_t *rd; - u32 cmdstat; - - dbg(3, "%s: dev=%p, status=%x\n", __FUNCTION__, dev, status); - - cdp = (GT96100ETH_READ(gp, GT96100_ETH_1ST_RX_DESC_PTR0) - - gp->rx_ring_dma) / sizeof(gt96100_rd_t); - - // Continue until we reach 1st descriptor pointer - for (nextOut = gp->rx_next_out; nextOut != cdp; - nextOut = (nextOut + 1) % RX_RING_SIZE) { - - if (--gp->intr_work_done == 0) - break; - - rd = &gp->rx_ring[nextOut]; - cmdstat = dma32_to_cpu(rd->cmdstat); - - dbg(4, "%s: Rx desc cmdstat=%x, nextOut=%d\n", __FUNCTION__, - cmdstat, nextOut); - - if (cmdstat & (u32)rxOwn) { - //err("%s: device owns descriptor!\n", __FUNCTION__); - // DMA is not finished updating descriptor??? - // Leave and come back later to pick-up where - // we left off. - break; - } - - // Drop this received pkt if there were any errors - if (((cmdstat & (u32)(rxErrorSummary)) && - (cmdstat & (u32)(rxFirst))) || (status & icrRxError)) { - // update the detailed rx error counters that - // are not covered by the MIB counters. - if (cmdstat & (u32)rxOverrun) - gp->stats.rx_fifo_errors++; - cmdstat |= (u32)rxOwn; - rd->cmdstat = cpu_to_dma32(cmdstat); - continue; - } - - /* - * Must be first and last (ie only) descriptor of packet. We - * ignore (drop) any packets that do not fit in one descriptor. - * Every descriptor's receive buffer is large enough to hold - * the maximum 802.3 frame size, so a multi-descriptor packet - * indicates an error. Most if not all corrupted packets will - * have already been dropped by the above check for the - * rxErrorSummary status bit. - */ - if (!(cmdstat & (u32)rxFirst) || !(cmdstat & (u32)rxLast)) { - if (cmdstat & (u32)rxFirst) { - /* - * This is the first descriptor of a - * multi-descriptor packet. It isn't corrupted - * because the above check for rxErrorSummary - * would have dropped it already, so what's - * the deal with this packet? Good question, - * let's dump it out. - */ - err("%s: desc not first and last!\n", __FUNCTION__); - dump_rx_desc(0, dev, nextOut); - } - cmdstat |= (u32)rxOwn; - rd->cmdstat = cpu_to_dma32(cmdstat); - // continue to drop every descriptor of this packet - continue; - } - - pkt_len = dma16_to_cpu(rd->byte_cnt); - - /* Create new skb. */ - skb = dev_alloc_skb(pkt_len+2); - if (skb == NULL) { - err("%s: Memory squeeze, dropping packet.\n", __FUNCTION__); - gp->stats.rx_dropped++; - cmdstat |= (u32)rxOwn; - rd->cmdstat = cpu_to_dma32(cmdstat); - continue; - } - skb->dev = dev; - skb_reserve(skb, 2); /* 16 byte IP header align */ - memcpy(skb_put(skb, pkt_len), - &gp->rx_buff[nextOut*PKT_BUF_SZ], pkt_len); - skb->protocol = eth_type_trans(skb, dev); - dump_skb(4, dev, skb); - - netif_rx(skb); /* pass the packet to upper layers */ - dev->last_rx = jiffies; - - // now we can release ownership of this desc back to device - cmdstat |= (u32)rxOwn; - rd->cmdstat = cpu_to_dma32(cmdstat); - } - - if (nextOut == gp->rx_next_out) - dbg(3, "%s: RxCDP did not increment?\n", __FUNCTION__); - - gp->rx_next_out = nextOut; - return 0; -} - - -static void -gt96100_tx_complete(struct net_device *dev, u32 status) -{ - struct gt96100_private *gp = netdev_priv(dev); - int nextOut, cdp; - gt96100_td_t *td; - u32 cmdstat; - - cdp = (GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0) - - gp->tx_ring_dma) / sizeof(gt96100_td_t); - - // Continue until we reach the current descriptor pointer - for (nextOut = gp->tx_next_out; nextOut != cdp; - nextOut = (nextOut + 1) % TX_RING_SIZE) { - - if (--gp->intr_work_done == 0) - break; - - td = &gp->tx_ring[nextOut]; - cmdstat = dma32_to_cpu(td->cmdstat); - - dbg(3, "%s: Tx desc cmdstat=%x, nextOut=%d\n", __FUNCTION__, - cmdstat, nextOut); - - if (cmdstat & (u32)txOwn) { - /* - * DMA is not finished writing descriptor??? - * Leave and come back later to pick-up where - * we left off. - */ - break; - } - - // increment Tx error stats - if (cmdstat & (u32)txErrorSummary) { - dbg(2, "%s: Tx error, cmdstat = %x\n", __FUNCTION__, - cmdstat); - gp->stats.tx_errors++; - if (cmdstat & (u32)txReTxLimit) - gp->stats.tx_aborted_errors++; - if (cmdstat & (u32)txUnderrun) - gp->stats.tx_fifo_errors++; - if (cmdstat & (u32)txLateCollision) - gp->stats.tx_window_errors++; - } - - if (cmdstat & (u32)txCollision) - gp->stats.collisions += - (u32)((cmdstat & txReTxCntMask) >> - txReTxCntBit); - - // Wake the queue if the ring was full - if (gp->tx_full) { - gp->tx_full = 0; - if (gp->last_psr & psrLink) { - netif_wake_queue(dev); - dbg(2, "%s: Tx Ring was full, queue waked\n", - __FUNCTION__); - } - } - - // decrement tx ring buffer count - if (gp->tx_count) gp->tx_count--; - - // free the skb - if (gp->tx_skbuff[nextOut]) { - dbg(3, "%s: good Tx, skb=%p\n", __FUNCTION__, - gp->tx_skbuff[nextOut]); - dev_kfree_skb_irq(gp->tx_skbuff[nextOut]); - gp->tx_skbuff[nextOut] = NULL; - } else { - err("%s: no skb!\n", __FUNCTION__); - } - } - - gp->tx_next_out = nextOut; - - if (gt96100_check_tx_consistent(gp)) { - err("%s: Tx queue inconsistent!\n", __FUNCTION__); - } - - if ((status & icrTxEndLow) && gp->tx_count != 0) { - // we must restart the DMA - dbg(3, "%s: Restarting Tx DMA\n", __FUNCTION__); - GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, - sdcmrERD | sdcmrTXDL); - } -} - - -static irqreturn_t -gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct gt96100_private *gp = netdev_priv(dev); - u32 status; - int handled = 0; - - if (dev == NULL) { - err("%s: null dev ptr\n", __FUNCTION__); - return IRQ_NONE; - } - - dbg(3, "%s: entry, icr=%x\n", __FUNCTION__, - GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE)); - - spin_lock(&gp->lock); - - gp->intr_work_done = max_interrupt_work; - - while (gp->intr_work_done > 0) { - - status = GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE); - // ACK interrupts - GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, ~status); - - if ((status & icrEtherIntSum) == 0 && - !(status & (icrTxBufferLow|icrTxBufferHigh|icrRxBuffer))) - break; - - handled = 1; - - if (status & icrMIIPhySTC) { - u32 psr = GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS); - if (gp->last_psr != psr) { - dbg(0, "port status:\n"); - dbg(0, " %s MBit/s, %s-duplex, " - "flow-control %s, link is %s,\n", - psr & psrSpeed ? "100":"10", - psr & psrDuplex ? "full":"half", - psr & psrFctl ? "disabled":"enabled", - psr & psrLink ? "up":"down"); - dbg(0, " TxLowQ is %s, TxHighQ is %s, " - "Transmitter is %s\n", - psr & psrTxLow ? "running":"stopped", - psr & psrTxHigh ? "running":"stopped", - psr & psrTxInProg ? "on":"off"); - - if ((psr & psrLink) && !gp->tx_full && - netif_queue_stopped(dev)) { - dbg(0, "%s: Link up, waking queue.\n", - __FUNCTION__); - netif_wake_queue(dev); - } else if (!(psr & psrLink) && - !netif_queue_stopped(dev)) { - dbg(0, "%s: Link down, stopping queue.\n", - __FUNCTION__); - netif_stop_queue(dev); - } - - gp->last_psr = psr; - } - - if (--gp->intr_work_done == 0) - break; - } - - if (status & (icrTxBufferLow | icrTxEndLow)) - gt96100_tx_complete(dev, status); - - if (status & (icrRxBuffer | icrRxError)) { - gt96100_rx(dev, status); - } - - // Now check TX errors (RX errors were handled in gt96100_rx) - if (status & icrTxErrorLow) { - err("%s: Tx resource error\n", __FUNCTION__); - if (--gp->intr_work_done == 0) - break; - } - - if (status & icrTxUdr) { - err("%s: Tx underrun error\n", __FUNCTION__); - if (--gp->intr_work_done == 0) - break; - } - } - - if (gp->intr_work_done == 0) { - // ACK any remaining pending interrupts - GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, 0); - dbg(3, "%s: hit max work\n", __FUNCTION__); - } - - dbg(3, "%s: exit, icr=%x\n", __FUNCTION__, - GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE)); - - spin_unlock(&gp->lock); - return IRQ_RETVAL(handled); -} - - -static void -gt96100_tx_timeout(struct net_device *dev) -{ - struct gt96100_private *gp = netdev_priv(dev); - unsigned long flags; - - spin_lock_irqsave(&gp->lock, flags); - - if (!(gp->last_psr & psrLink)) { - err("tx_timeout: link down.\n"); - spin_unlock_irqrestore(&gp->lock, flags); - } else { - if (gt96100_check_tx_consistent(gp)) - err("tx_timeout: Tx ring error.\n"); - - disable_ether_irq(dev); - spin_unlock_irqrestore(&gp->lock, flags); - reset_tx(dev); - enable_ether_irq(dev); - - netif_wake_queue(dev); - } -} - - -static void -gt96100_set_rx_mode(struct net_device *dev) -{ - struct gt96100_private *gp = netdev_priv(dev); - unsigned long flags; - //struct dev_mc_list *mcptr; - - dbg(3, "%s: dev=%p, flags=%x\n", __FUNCTION__, dev, dev->flags); - - // stop the Receiver DMA - abort(dev, sdcmrAR); - - spin_lock_irqsave(&gp->lock, flags); - - if (dev->flags & IFF_PROMISC) { - GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, - pcrEN | pcrHS | pcrPM); - } - -#if 0 - /* - FIXME: currently multicast doesn't work - need to get hash table - working first. - */ - if (dev->mc_count) { - // clear hash table - memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); - // Add our ethernet address - gt96100_add_hash_entry(dev, dev->dev_addr); - - for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) { - dump_hw_addr(2, dev, "%s: addr=", __FUNCTION__, - mcptr->dmi_addr); - gt96100_add_hash_entry(dev, mcptr->dmi_addr); - } - } -#endif - - // restart Rx DMA - GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD); - - spin_unlock_irqrestore(&gp->lock, flags); -} - -static struct net_device_stats * -gt96100_get_stats(struct net_device *dev) -{ - struct gt96100_private *gp = netdev_priv(dev); - unsigned long flags; - - dbg(3, "%s: dev=%p\n", __FUNCTION__, dev); - - if (netif_device_present(dev)) { - spin_lock_irqsave (&gp->lock, flags); - update_stats(gp); - spin_unlock_irqrestore (&gp->lock, flags); - } - - return &gp->stats; -} - -static void gt96100_cleanup_module(void) -{ - int i; - for (i=0; idev != NULL) { - struct gt96100_private *gp = (struct gt96100_private *) - netdev_priv(gtif->dev); - unregister_netdev(gtif->dev); - dmafree(RX_HASH_TABLE_SIZE, gp->hash_table_dma); - dmafree(PKT_BUF_SZ*RX_RING_SIZE, gp->rx_buff); - dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE - + sizeof(gt96100_td_t) * TX_RING_SIZE, - gp->rx_ring); - free_netdev(gtif->dev); - release_region(gtif->iobase, GT96100_ETH_IO_SIZE); - } - } -} - -static int __init gt96100_setup(char *options) -{ - char *this_opt; - - if (!options || !*options) - return 0; - - while ((this_opt = strsep (&options, ",")) != NULL) { - if (!*this_opt) - continue; - if (!strncmp(this_opt, "mac0:", 5)) { - memcpy(mac0, this_opt+5, 17); - mac0[17]= '\0'; - } else if (!strncmp(this_opt, "mac1:", 5)) { - memcpy(mac1, this_opt+5, 17); - mac1[17]= '\0'; - } - } - - return 1; -} - -__setup("gt96100eth=", gt96100_setup); - -module_init(gt96100_init_module); -module_exit(gt96100_cleanup_module); - -MODULE_AUTHOR("Steve Longerbeam "); -MODULE_DESCRIPTION("GT96100 Ethernet driver"); diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/net/gt96100eth.h mips/drivers/net/gt96100eth.h --- mips-orig/drivers/net/gt96100eth.h 2006-09-21 00:46:08.328513750 +0900 +++ mips/drivers/net/gt96100eth.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,346 +0,0 @@ -/* - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * stevel@mvista.com or source@mvista.com - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Ethernet driver definitions for the MIPS GT96100 Advanced - * Communication Controller. - * - */ -#ifndef _GT96100ETH_H -#define _GT96100ETH_H - -#include - -#define dbg(lvl, format, arg...) \ - if (lvl <= GT96100_DEBUG) \ - printk(KERN_DEBUG "%s: " format, dev->name , ## arg) -#define err(format, arg...) \ - printk(KERN_ERR "%s: " format, dev->name , ## arg) -#define info(format, arg...) \ - printk(KERN_INFO "%s: " format, dev->name , ## arg) -#define warn(format, arg...) \ - printk(KERN_WARNING "%s: " format, dev->name , ## arg) - -/* Keep the ring sizes a power of two for efficiency. */ -#define TX_RING_SIZE 16 -#define RX_RING_SIZE 32 -#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ - -#define RX_HASH_TABLE_SIZE 16384 -#define HASH_HOP_NUMBER 12 - -#define NUM_INTERFACES 2 - -#define GT96100ETH_TX_TIMEOUT HZ/4 - -#define GT96100_ETH0_BASE (MIPS_GT96100_BASE + GT96100_ETH_PORT_CONFIG) -#define GT96100_ETH1_BASE (GT96100_ETH0_BASE + GT96100_ETH_IO_SIZE) - -#ifdef CONFIG_MIPS_EV96100 -#define GT96100_ETHER0_IRQ 3 -#define GT96100_ETHER1_IRQ 4 -#else -#define GT96100_ETHER0_IRQ -1 -#define GT96100_ETHER1_IRQ -1 -#endif - -#define REV_GT96100 1 -#define REV_GT96100A_1 2 -#define REV_GT96100A 3 - -#define GT96100ETH_READ(gp, offset) \ - GT96100_READ((gp->port_offset + offset)) - -#define GT96100ETH_WRITE(gp, offset, data) \ - GT96100_WRITE((gp->port_offset + offset), data) - -#define GT96100ETH_SETBIT(gp, offset, bits) {\ - u32 val = GT96100ETH_READ(gp, offset); val |= (u32)(bits); \ - GT96100ETH_WRITE(gp, offset, val); } - -#define GT96100ETH_CLRBIT(gp, offset, bits) {\ - u32 val = GT96100ETH_READ(gp, offset); val &= (u32)(~(bits)); \ - GT96100ETH_WRITE(gp, offset, val); } - - -/* Bit definitions of the SMI Reg */ -enum { - smirDataMask = 0xffff, - smirPhyAdMask = 0x1f<<16, - smirPhyAdBit = 16, - smirRegAdMask = 0x1f<<21, - smirRegAdBit = 21, - smirOpCode = 1<<26, - smirReadValid = 1<<27, - smirBusy = 1<<28 -}; - -/* Bit definitions of the Port Config Reg */ -enum pcr_bits { - pcrPM = 1, - pcrRBM = 2, - pcrPBF = 4, - pcrEN = 1<<7, - pcrLPBKMask = 0x3<<8, - pcrLPBKBit = 8, - pcrFC = 1<<10, - pcrHS = 1<<12, - pcrHM = 1<<13, - pcrHDM = 1<<14, - pcrHD = 1<<15, - pcrISLMask = 0x7<<28, - pcrISLBit = 28, - pcrACCS = 1<<31 -}; - -/* Bit definitions of the Port Config Extend Reg */ -enum pcxr_bits { - pcxrIGMP = 1, - pcxrSPAN = 2, - pcxrPAR = 4, - pcxrPRIOtxMask = 0x7<<3, - pcxrPRIOtxBit = 3, - pcxrPRIOrxMask = 0x3<<6, - pcxrPRIOrxBit = 6, - pcxrPRIOrxOverride = 1<<8, - pcxrDPLXen = 1<<9, - pcxrFCTLen = 1<<10, - pcxrFLP = 1<<11, - pcxrFCTL = 1<<12, - pcxrMFLMask = 0x3<<14, - pcxrMFLBit = 14, - pcxrMIBclrMode = 1<<16, - pcxrSpeed = 1<<18, - pcxrSpeeden = 1<<19, - pcxrRMIIen = 1<<20, - pcxrDSCPen = 1<<21 -}; - -/* Bit definitions of the Port Command Reg */ -enum pcmr_bits { - pcmrFJ = 1<<15 -}; - - -/* Bit definitions of the Port Status Reg */ -enum psr_bits { - psrSpeed = 1, - psrDuplex = 2, - psrFctl = 4, - psrLink = 8, - psrPause = 1<<4, - psrTxLow = 1<<5, - psrTxHigh = 1<<6, - psrTxInProg = 1<<7 -}; - -/* Bit definitions of the SDMA Config Reg */ -enum sdcr_bits { - sdcrRCMask = 0xf<<2, - sdcrRCBit = 2, - sdcrBLMR = 1<<6, - sdcrBLMT = 1<<7, - sdcrPOVR = 1<<8, - sdcrRIFB = 1<<9, - sdcrBSZMask = 0x3<<12, - sdcrBSZBit = 12 -}; - -/* Bit definitions of the SDMA Command Reg */ -enum sdcmr_bits { - sdcmrERD = 1<<7, - sdcmrAR = 1<<15, - sdcmrSTDH = 1<<16, - sdcmrSTDL = 1<<17, - sdcmrTXDH = 1<<23, - sdcmrTXDL = 1<<24, - sdcmrAT = 1<<31 -}; - -/* Bit definitions of the Interrupt Cause Reg */ -enum icr_bits { - icrRxBuffer = 1, - icrTxBufferHigh = 1<<2, - icrTxBufferLow = 1<<3, - icrTxEndHigh = 1<<6, - icrTxEndLow = 1<<7, - icrRxError = 1<<8, - icrTxErrorHigh = 1<<10, - icrTxErrorLow = 1<<11, - icrRxOVR = 1<<12, - icrTxUdr = 1<<13, - icrRxBufferQ0 = 1<<16, - icrRxBufferQ1 = 1<<17, - icrRxBufferQ2 = 1<<18, - icrRxBufferQ3 = 1<<19, - icrRxErrorQ0 = 1<<20, - icrRxErrorQ1 = 1<<21, - icrRxErrorQ2 = 1<<22, - icrRxErrorQ3 = 1<<23, - icrMIIPhySTC = 1<<28, - icrSMIdone = 1<<29, - icrEtherIntSum = 1<<31 -}; - - -/* The Rx and Tx descriptor lists. */ -typedef struct { -#ifdef DESC_BE - u16 byte_cnt; - u16 reserved; -#else - u16 reserved; - u16 byte_cnt; -#endif - u32 cmdstat; - u32 next; - u32 buff_ptr; -} __attribute__ ((packed)) gt96100_td_t; - -typedef struct { -#ifdef DESC_BE - u16 buff_sz; - u16 byte_cnt; -#else - u16 byte_cnt; - u16 buff_sz; -#endif - u32 cmdstat; - u32 next; - u32 buff_ptr; -} __attribute__ ((packed)) gt96100_rd_t; - - -/* Values for the Tx command-status descriptor entry. */ -enum td_cmdstat { - txOwn = 1<<31, - txAutoMode = 1<<30, - txEI = 1<<23, - txGenCRC = 1<<22, - txPad = 1<<18, - txFirst = 1<<17, - txLast = 1<<16, - txErrorSummary = 1<<15, - txReTxCntMask = 0x0f<<10, - txReTxCntBit = 10, - txCollision = 1<<9, - txReTxLimit = 1<<8, - txUnderrun = 1<<6, - txLateCollision = 1<<5 -}; - - -/* Values for the Rx command-status descriptor entry. */ -enum rd_cmdstat { - rxOwn = 1<<31, - rxAutoMode = 1<<30, - rxEI = 1<<23, - rxFirst = 1<<17, - rxLast = 1<<16, - rxErrorSummary = 1<<15, - rxIGMP = 1<<14, - rxHashExpired = 1<<13, - rxMissedFrame = 1<<12, - rxFrameType = 1<<11, - rxShortFrame = 1<<8, - rxMaxFrameLen = 1<<7, - rxOverrun = 1<<6, - rxCollision = 1<<4, - rxCRCError = 1 -}; - -/* Bit fields of a Hash Table Entry */ -enum hash_table_entry { - hteValid = 1, - hteSkip = 2, - hteRD = 4 -}; - -// The MIB counters -typedef struct { - u32 byteReceived; - u32 byteSent; - u32 framesReceived; - u32 framesSent; - u32 totalByteReceived; - u32 totalFramesReceived; - u32 broadcastFramesReceived; - u32 multicastFramesReceived; - u32 cRCError; - u32 oversizeFrames; - u32 fragments; - u32 jabber; - u32 collision; - u32 lateCollision; - u32 frames64; - u32 frames65_127; - u32 frames128_255; - u32 frames256_511; - u32 frames512_1023; - u32 frames1024_MaxSize; - u32 macRxError; - u32 droppedFrames; - u32 outMulticastFrames; - u32 outBroadcastFrames; - u32 undersizeFrames; -} mib_counters_t; - - -struct gt96100_private { - gt96100_rd_t* rx_ring; - gt96100_td_t* tx_ring; - // The Rx and Tx rings must be 16-byte aligned - dma_addr_t rx_ring_dma; - dma_addr_t tx_ring_dma; - char* hash_table; - // The Hash Table must be 8-byte aligned - dma_addr_t hash_table_dma; - int hash_mode; - - // The Rx buffers must be 8-byte aligned - char* rx_buff; - dma_addr_t rx_buff_dma; - // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes - // of payload must be 8-byte aligned - struct sk_buff* tx_skbuff[TX_RING_SIZE]; - int rx_next_out; /* The next free ring entry to receive */ - int tx_next_in; /* The next free ring entry to send */ - int tx_next_out; /* The last ring entry the ISR processed */ - int tx_count; /* current # of pkts waiting to be sent in Tx ring */ - int intr_work_done; /* number of Rx and Tx pkts processed in the isr */ - int tx_full; /* Tx ring is full */ - - mib_counters_t mib; - struct net_device_stats stats; - - int port_num; // 0 or 1 - int chip_rev; - u32 port_offset; - - int phy_addr; // PHY address - u32 last_psr; // last value of the port status register - - int options; /* User-settable misc. driver options. */ - struct timer_list timer; - spinlock_t lock; /* Serialise access to device */ -}; - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/bootinfo.h mips/include/asm-mips/bootinfo.h --- mips-orig/include/asm-mips/bootinfo.h 2006-09-21 00:46:16.777041750 +0900 +++ mips/include/asm-mips/bootinfo.h 2006-09-21 00:46:07.468460000 +0900 @@ -112,7 +112,6 @@ * Valid machtype for group GALILEO */ #define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */ -#define MACH_EV96100 0 /* EV96100 */ #define MACH_EV64120A 1 /* EV64120A */ /* diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/galileo-boards/ev96100.h mips/include/asm-mips/galileo-boards/ev96100.h --- mips-orig/include/asm-mips/galileo-boards/ev96100.h 2006-09-21 00:46:17.489086250 +0900 +++ mips/include/asm-mips/galileo-boards/ev96100.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,55 +0,0 @@ -/* - * - */ -#ifndef _MIPS_EV96100_H -#define _MIPS_EV96100_H - -#include - -/* - * GT64120 config space base address - */ -#define GT64120_BASE (KSEG1ADDR(0x14000000)) -#define MIPS_GT_BASE GT64120_BASE - -/* - * PCI Bus allocation - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - -/* - * Duart I/O ports. - */ -#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20) -#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00) - - -/* - * EV96100 interrupt controller register base. - */ -#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) - -/* - * EV96100 UART register base. - */ -#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR -#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR -#define EV96100_BASE_BAUD ( 3686400 / 16 ) - - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. - */ -#define __GT_READ(ofs) \ - (*(volatile u32 *)(GT64120_BASE+(ofs))) -#define __GT_WRITE(ofs, data) \ - do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) -#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) -#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) - -#endif /* !(_MIPS_EV96100_H) */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/galileo-boards/ev96100int.h mips/include/asm-mips/galileo-boards/ev96100int.h --- mips-orig/include/asm-mips/galileo-boards/ev96100int.h 2006-09-21 00:46:17.489086250 +0900 +++ mips/include/asm-mips/galileo-boards/ev96100int.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,12 +0,0 @@ -/* - * - */ -#ifndef _MIPS_EV96100INT_H -#define _MIPS_EV96100INT_H - -#define EV96100INT_UART_0 6 /* IP 6 */ -#define EV96100INT_TIMER 7 /* IP 7 */ - -extern void ev96100int_init(void); - -#endif /* !(_MIPS_EV96100_H) */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/galileo-boards/gt96100.h mips/include/asm-mips/galileo-boards/gt96100.h --- mips-orig/include/asm-mips/galileo-boards/gt96100.h 2006-09-21 00:46:17.489086250 +0900 +++ mips/include/asm-mips/galileo-boards/gt96100.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,427 +0,0 @@ -/* - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * stevel@mvista.com or source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Register offsets of the MIPS GT96100 Advanced Communication Controller. - */ -#ifndef _GT96100_H -#define _GT96100_H - -/* - * Galileo GT96100 internal register base. - */ -#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000)) - -#define GT96100_WRITE(ofs, data) \ - *(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data) -#define GT96100_READ(ofs) \ - le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs)) - -#define GT96100_ETH_IO_SIZE 0x4000 - -/************************************************************************ - * Register offset addresses follow - ************************************************************************/ - -/* CPU Interface Control Registers */ -#define GT96100_CPU_INTERF_CONFIG 0x000000 - -/* Ethernet Ports */ -#define GT96100_ETH_PHY_ADDR_REG 0x080800 -#define GT96100_ETH_SMI_REG 0x080810 -/* - These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to - get offsets to port 1 registers. -*/ -#define GT96100_ETH_PORT_CONFIG 0x084800 -#define GT96100_ETH_PORT_CONFIG_EXT 0x084808 -#define GT96100_ETH_PORT_COMM 0x084810 -#define GT96100_ETH_PORT_STATUS 0x084818 -#define GT96100_ETH_SER_PARAM 0x084820 -#define GT96100_ETH_HASH_TBL_PTR 0x084828 -#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L 0x084830 -#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H 0x084838 -#define GT96100_ETH_SDMA_CONFIG 0x084840 -#define GT96100_ETH_SDMA_COMM 0x084848 -#define GT96100_ETH_INT_CAUSE 0x084850 -#define GT96100_ETH_INT_MASK 0x084858 -#define GT96100_ETH_1ST_RX_DESC_PTR0 0x084880 -#define GT96100_ETH_1ST_RX_DESC_PTR1 0x084884 -#define GT96100_ETH_1ST_RX_DESC_PTR2 0x084888 -#define GT96100_ETH_1ST_RX_DESC_PTR3 0x08488C -#define GT96100_ETH_CURR_RX_DESC_PTR0 0x0848A0 -#define GT96100_ETH_CURR_RX_DESC_PTR1 0x0848A4 -#define GT96100_ETH_CURR_RX_DESC_PTR2 0x0848A8 -#define GT96100_ETH_CURR_RX_DESC_PTR3 0x0848AC -#define GT96100_ETH_CURR_TX_DESC_PTR0 0x0848E0 -#define GT96100_ETH_CURR_TX_DESC_PTR1 0x0848E4 -#define GT96100_ETH_MIB_COUNT_BASE 0x085800 - -/* SDMAs */ -#define GT96100_SDMA_GROUP_CONFIG 0x101AF0 -/* SDMA Group 0 */ -#define GT96100_SDMA_G0_CHAN0_CONFIG 0x000900 -#define GT96100_SDMA_G0_CHAN0_COMM 0x000908 -#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE 0x008900 -#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR 0x008910 -#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE 0x00C900 -#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR 0x00C910 -#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR 0x00C914 -#define GT96100_SDMA_G0_CHAN1_CONFIG 0x010900 -#define GT96100_SDMA_G0_CHAN1_COMM 0x010908 -#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE 0x018900 -#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR 0x018910 -#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE 0x01C900 -#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR 0x01C910 -#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR 0x01C914 -#define GT96100_SDMA_G0_CHAN2_CONFIG 0x020900 -#define GT96100_SDMA_G0_CHAN2_COMM 0x020908 -#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE 0x028900 -#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR 0x028910 -#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE 0x02C900 -#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR 0x02C910 -#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR 0x02C914 -#define GT96100_SDMA_G0_CHAN3_CONFIG 0x030900 -#define GT96100_SDMA_G0_CHAN3_COMM 0x030908 -#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE 0x038900 -#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR 0x038910 -#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE 0x03C900 -#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR 0x03C910 -#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR 0x03C914 -#define GT96100_SDMA_G0_CHAN4_CONFIG 0x040900 -#define GT96100_SDMA_G0_CHAN4_COMM 0x040908 -#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE 0x048900 -#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR 0x048910 -#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE 0x04C900 -#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR 0x04C910 -#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR 0x04C914 -#define GT96100_SDMA_G0_CHAN5_CONFIG 0x050900 -#define GT96100_SDMA_G0_CHAN5_COMM 0x050908 -#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE 0x058900 -#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR 0x058910 -#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE 0x05C900 -#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR 0x05C910 -#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR 0x05C914 -#define GT96100_SDMA_G0_CHAN6_CONFIG 0x060900 -#define GT96100_SDMA_G0_CHAN6_COMM 0x060908 -#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE 0x068900 -#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR 0x068910 -#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE 0x06C900 -#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR 0x06C910 -#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR 0x06C914 -#define GT96100_SDMA_G0_CHAN7_CONFIG 0x070900 -#define GT96100_SDMA_G0_CHAN7_COMM 0x070908 -#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE 0x078900 -#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR 0x078910 -#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE 0x07C900 -#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR 0x07C910 -#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR 0x07C914 -/* SDMA Group 1 */ -#define GT96100_SDMA_G1_CHAN0_CONFIG 0x100900 -#define GT96100_SDMA_G1_CHAN0_COMM 0x100908 -#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE 0x108900 -#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR 0x108910 -#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE 0x10C900 -#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR 0x10C910 -#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR 0x10C914 -#define GT96100_SDMA_G1_CHAN1_CONFIG 0x110900 -#define GT96100_SDMA_G1_CHAN1_COMM 0x110908 -#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE 0x118900 -#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR 0x118910 -#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE 0x11C900 -#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR 0x11C910 -#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR 0x11C914 -#define GT96100_SDMA_G1_CHAN2_CONFIG 0x120900 -#define GT96100_SDMA_G1_CHAN2_COMM 0x120908 -#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE 0x128900 -#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR 0x128910 -#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE 0x12C900 -#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR 0x12C910 -#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR 0x12C914 -#define GT96100_SDMA_G1_CHAN3_CONFIG 0x130900 -#define GT96100_SDMA_G1_CHAN3_COMM 0x130908 -#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE 0x138900 -#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR 0x138910 -#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE 0x13C900 -#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR 0x13C910 -#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR 0x13C914 -#define GT96100_SDMA_G1_CHAN4_CONFIG 0x140900 -#define GT96100_SDMA_G1_CHAN4_COMM 0x140908 -#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE 0x148900 -#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR 0x148910 -#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE 0x14C900 -#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR 0x14C910 -#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR 0x14C914 -#define GT96100_SDMA_G1_CHAN5_CONFIG 0x150900 -#define GT96100_SDMA_G1_CHAN5_COMM 0x150908 -#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE 0x158900 -#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR 0x158910 -#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE 0x15C900 -#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR 0x15C910 -#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR 0x15C914 -#define GT96100_SDMA_G1_CHAN6_CONFIG 0x160900 -#define GT96100_SDMA_G1_CHAN6_COMM 0x160908 -#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE 0x168900 -#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR 0x168910 -#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE 0x16C900 -#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR 0x16C910 -#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR 0x16C914 -#define GT96100_SDMA_G1_CHAN7_CONFIG 0x170900 -#define GT96100_SDMA_G1_CHAN7_COMM 0x170908 -#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE 0x178900 -#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR 0x178910 -#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE 0x17C900 -#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR 0x17C910 -#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR 0x17C914 -/* MPSCs */ -#define GT96100_MPSC0_MAIN_CONFIG_LOW 0x000A00 -#define GT96100_MPSC0_MAIN_CONFIG_HIGH 0x000A04 -#define GT96100_MPSC0_PROTOCOL_CONFIG 0x000A08 -#define GT96100_MPSC_CHAN0_REG1 0x000A0C -#define GT96100_MPSC_CHAN0_REG2 0x000A10 -#define GT96100_MPSC_CHAN0_REG3 0x000A14 -#define GT96100_MPSC_CHAN0_REG4 0x000A18 -#define GT96100_MPSC_CHAN0_REG5 0x000A1C -#define GT96100_MPSC_CHAN0_REG6 0x000A20 -#define GT96100_MPSC_CHAN0_REG7 0x000A24 -#define GT96100_MPSC_CHAN0_REG8 0x000A28 -#define GT96100_MPSC_CHAN0_REG9 0x000A2C -#define GT96100_MPSC_CHAN0_REG10 0x000A30 -#define GT96100_MPSC_CHAN0_REG11 0x000A34 -#define GT96100_MPSC1_MAIN_CONFIG_LOW 0x008A00 -#define GT96100_MPSC1_MAIN_CONFIG_HIGH 0x008A04 -#define GT96100_MPSC1_PROTOCOL_CONFIG 0x008A08 -#define GT96100_MPSC_CHAN1_REG1 0x008A0C -#define GT96100_MPSC_CHAN1_REG2 0x008A10 -#define GT96100_MPSC_CHAN1_REG3 0x008A14 -#define GT96100_MPSC_CHAN1_REG4 0x008A18 -#define GT96100_MPSC_CHAN1_REG5 0x008A1C -#define GT96100_MPSC_CHAN1_REG6 0x008A20 -#define GT96100_MPSC_CHAN1_REG7 0x008A24 -#define GT96100_MPSC_CHAN1_REG8 0x008A28 -#define GT96100_MPSC_CHAN1_REG9 0x008A2C -#define GT96100_MPSC_CHAN1_REG10 0x008A30 -#define GT96100_MPSC_CHAN1_REG11 0x008A34 -#define GT96100_MPSC2_MAIN_CONFIG_LOW 0x010A00 -#define GT96100_MPSC2_MAIN_CONFIG_HIGH 0x010A04 -#define GT96100_MPSC2_PROTOCOL_CONFIG 0x010A08 -#define GT96100_MPSC_CHAN2_REG1 0x010A0C -#define GT96100_MPSC_CHAN2_REG2 0x010A10 -#define GT96100_MPSC_CHAN2_REG3 0x010A14 -#define GT96100_MPSC_CHAN2_REG4 0x010A18 -#define GT96100_MPSC_CHAN2_REG5 0x010A1C -#define GT96100_MPSC_CHAN2_REG6 0x010A20 -#define GT96100_MPSC_CHAN2_REG7 0x010A24 -#define GT96100_MPSC_CHAN2_REG8 0x010A28 -#define GT96100_MPSC_CHAN2_REG9 0x010A2C -#define GT96100_MPSC_CHAN2_REG10 0x010A30 -#define GT96100_MPSC_CHAN2_REG11 0x010A34 -#define GT96100_MPSC3_MAIN_CONFIG_LOW 0x018A00 -#define GT96100_MPSC3_MAIN_CONFIG_HIGH 0x018A04 -#define GT96100_MPSC3_PROTOCOL_CONFIG 0x018A08 -#define GT96100_MPSC_CHAN3_REG1 0x018A0C -#define GT96100_MPSC_CHAN3_REG2 0x018A10 -#define GT96100_MPSC_CHAN3_REG3 0x018A14 -#define GT96100_MPSC_CHAN3_REG4 0x018A18 -#define GT96100_MPSC_CHAN3_REG5 0x018A1C -#define GT96100_MPSC_CHAN3_REG6 0x018A20 -#define GT96100_MPSC_CHAN3_REG7 0x018A24 -#define GT96100_MPSC_CHAN3_REG8 0x018A28 -#define GT96100_MPSC_CHAN3_REG9 0x018A2C -#define GT96100_MPSC_CHAN3_REG10 0x018A30 -#define GT96100_MPSC_CHAN3_REG11 0x018A34 -#define GT96100_MPSC4_MAIN_CONFIG_LOW 0x020A00 -#define GT96100_MPSC4_MAIN_CONFIG_HIGH 0x020A04 -#define GT96100_MPSC4_PROTOCOL_CONFIG 0x020A08 -#define GT96100_MPSC_CHAN4_REG1 0x020A0C -#define GT96100_MPSC_CHAN4_REG2 0x020A10 -#define GT96100_MPSC_CHAN4_REG3 0x020A14 -#define GT96100_MPSC_CHAN4_REG4 0x020A18 -#define GT96100_MPSC_CHAN4_REG5 0x020A1C -#define GT96100_MPSC_CHAN4_REG6 0x020A20 -#define GT96100_MPSC_CHAN4_REG7 0x020A24 -#define GT96100_MPSC_CHAN4_REG8 0x020A28 -#define GT96100_MPSC_CHAN4_REG9 0x020A2C -#define GT96100_MPSC_CHAN4_REG10 0x020A30 -#define GT96100_MPSC_CHAN4_REG11 0x020A34 -#define GT96100_MPSC5_MAIN_CONFIG_LOW 0x028A00 -#define GT96100_MPSC5_MAIN_CONFIG_HIGH 0x028A04 -#define GT96100_MPSC5_PROTOCOL_CONFIG 0x028A08 -#define GT96100_MPSC_CHAN5_REG1 0x028A0C -#define GT96100_MPSC_CHAN5_REG2 0x028A10 -#define GT96100_MPSC_CHAN5_REG3 0x028A14 -#define GT96100_MPSC_CHAN5_REG4 0x028A18 -#define GT96100_MPSC_CHAN5_REG5 0x028A1C -#define GT96100_MPSC_CHAN5_REG6 0x028A20 -#define GT96100_MPSC_CHAN5_REG7 0x028A24 -#define GT96100_MPSC_CHAN5_REG8 0x028A28 -#define GT96100_MPSC_CHAN5_REG9 0x028A2C -#define GT96100_MPSC_CHAN5_REG10 0x028A30 -#define GT96100_MPSC_CHAN5_REG11 0x028A34 -#define GT96100_MPSC6_MAIN_CONFIG_LOW 0x030A00 -#define GT96100_MPSC6_MAIN_CONFIG_HIGH 0x030A04 -#define GT96100_MPSC6_PROTOCOL_CONFIG 0x030A08 -#define GT96100_MPSC_CHAN6_REG1 0x030A0C -#define GT96100_MPSC_CHAN6_REG2 0x030A10 -#define GT96100_MPSC_CHAN6_REG3 0x030A14 -#define GT96100_MPSC_CHAN6_REG4 0x030A18 -#define GT96100_MPSC_CHAN6_REG5 0x030A1C -#define GT96100_MPSC_CHAN6_REG6 0x030A20 -#define GT96100_MPSC_CHAN6_REG7 0x030A24 -#define GT96100_MPSC_CHAN6_REG8 0x030A28 -#define GT96100_MPSC_CHAN6_REG9 0x030A2C -#define GT96100_MPSC_CHAN6_REG10 0x030A30 -#define GT96100_MPSC_CHAN6_REG11 0x030A34 -#define GT96100_MPSC7_MAIN_CONFIG_LOW 0x038A00 -#define GT96100_MPSC7_MAIN_CONFIG_HIGH 0x038A04 -#define GT96100_MPSC7_PROTOCOL_CONFIG 0x038A08 -#define GT96100_MPSC_CHAN7_REG1 0x038A0C -#define GT96100_MPSC_CHAN7_REG2 0x038A10 -#define GT96100_MPSC_CHAN7_REG3 0x038A14 -#define GT96100_MPSC_CHAN7_REG4 0x038A18 -#define GT96100_MPSC_CHAN7_REG5 0x038A1C -#define GT96100_MPSC_CHAN7_REG6 0x038A20 -#define GT96100_MPSC_CHAN7_REG7 0x038A24 -#define GT96100_MPSC_CHAN7_REG8 0x038A28 -#define GT96100_MPSC_CHAN7_REG9 0x038A2C -#define GT96100_MPSC_CHAN7_REG10 0x038A30 -#define GT96100_MPSC_CHAN7_REG11 0x038A34 -/* FlexTDMs */ -/* TDPR0 - Transmit Dual Port RAM. block size 0xff */ -#define GT96100_FXTDM0_TDPR0_BLK0_BASE 0x000B00 -#define GT96100_FXTDM0_TDPR0_BLK1_BASE 0x001B00 -#define GT96100_FXTDM0_TDPR0_BLK2_BASE 0x002B00 -#define GT96100_FXTDM0_TDPR0_BLK3_BASE 0x003B00 -/* RDPR0 - Receive Dual Port RAM. block size 0xff */ -#define GT96100_FXTDM0_RDPR0_BLK0_BASE 0x004B00 -#define GT96100_FXTDM0_RDPR0_BLK1_BASE 0x005B00 -#define GT96100_FXTDM0_RDPR0_BLK2_BASE 0x006B00 -#define GT96100_FXTDM0_RDPR0_BLK3_BASE 0x007B00 -#define GT96100_FXTDM0_TX_READ_PTR 0x008B00 -#define GT96100_FXTDM0_RX_READ_PTR 0x008B04 -#define GT96100_FXTDM0_CONFIG 0x008B08 -#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C -#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10 -#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14 -#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18 -#define GT96100_FXTDM1_TDPR1_BLK0_BASE 0x010B00 -#define GT96100_FXTDM1_TDPR1_BLK1_BASE 0x011B00 -#define GT96100_FXTDM1_TDPR1_BLK2_BASE 0x012B00 -#define GT96100_FXTDM1_TDPR1_BLK3_BASE 0x013B00 -#define GT96100_FXTDM1_RDPR1_BLK0_BASE 0x014B00 -#define GT96100_FXTDM1_RDPR1_BLK1_BASE 0x015B00 -#define GT96100_FXTDM1_RDPR1_BLK2_BASE 0x016B00 -#define GT96100_FXTDM1_RDPR1_BLK3_BASE 0x017B00 -#define GT96100_FXTDM1_TX_READ_PTR 0x018B00 -#define GT96100_FXTDM1_RX_READ_PTR 0x018B04 -#define GT96100_FXTDM1_CONFIG 0x018B08 -#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C -#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10 -#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14 -#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18 -#define GT96100_FLTDM2_TDPR2_BLK0_BASE 0x020B00 -#define GT96100_FLTDM2_TDPR2_BLK1_BASE 0x021B00 -#define GT96100_FLTDM2_TDPR2_BLK2_BASE 0x022B00 -#define GT96100_FLTDM2_TDPR2_BLK3_BASE 0x023B00 -#define GT96100_FLTDM2_RDPR2_BLK0_BASE 0x024B00 -#define GT96100_FLTDM2_RDPR2_BLK1_BASE 0x025B00 -#define GT96100_FLTDM2_RDPR2_BLK2_BASE 0x026B00 -#define GT96100_FLTDM2_RDPR2_BLK3_BASE 0x027B00 -#define GT96100_FLTDM2_TX_READ_PTR 0x028B00 -#define GT96100_FLTDM2_RX_READ_PTR 0x028B04 -#define GT96100_FLTDM2_CONFIG 0x028B08 -#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C -#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10 -#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14 -#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18 -#define GT96100_FLTDM3_TDPR3_BLK0_BASE 0x030B00 -#define GT96100_FLTDM3_TDPR3_BLK1_BASE 0x031B00 -#define GT96100_FLTDM3_TDPR3_BLK2_BASE 0x032B00 -#define GT96100_FLTDM3_TDPR3_BLK3_BASE 0x033B00 -#define GT96100_FXTDM3_RDPR3_BLK0_BASE 0x034B00 -#define GT96100_FXTDM3_RDPR3_BLK1_BASE 0x035B00 -#define GT96100_FXTDM3_RDPR3_BLK2_BASE 0x036B00 -#define GT96100_FXTDM3_RDPR3_BLK3_BASE 0x037B00 -#define GT96100_FXTDM3_TX_READ_PTR 0x038B00 -#define GT96100_FXTDM3_RX_READ_PTR 0x038B04 -#define GT96100_FXTDM3_CONFIG 0x038B08 -#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C -#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10 -#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14 -#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18 -/* Baud Rate Generators */ -#define GT96100_BRG0_CONFIG 0x102A00 -#define GT96100_BRG0_BAUD_TUNE 0x102A04 -#define GT96100_BRG1_CONFIG 0x102A08 -#define GT96100_BRG1_BAUD_TUNE 0x102A0C -#define GT96100_BRG2_CONFIG 0x102A10 -#define GT96100_BRG2_BAUD_TUNE 0x102A14 -#define GT96100_BRG3_CONFIG 0x102A18 -#define GT96100_BRG3_BAUD_TUNE 0x102A1C -#define GT96100_BRG4_CONFIG 0x102A20 -#define GT96100_BRG4_BAUD_TUNE 0x102A24 -#define GT96100_BRG5_CONFIG 0x102A28 -#define GT96100_BRG5_BAUD_TUNE 0x102A2C -#define GT96100_BRG6_CONFIG 0x102A30 -#define GT96100_BRG6_BAUD_TUNE 0x102A34 -#define GT96100_BRG7_CONFIG 0x102A38 -#define GT96100_BRG7_BAUD_TUNE 0x102A3C -/* Routing Registers */ -#define GT96100_ROUTE_MAIN 0x101A00 -#define GT96100_ROUTE_RX_CLOCK 0x101A10 -#define GT96100_ROUTE_TX_CLOCK 0x101A20 -/* General Purpose Ports */ -#define GT96100_GPP_CONFIG0 0x100A00 -#define GT96100_GPP_CONFIG1 0x100A04 -#define GT96100_GPP_CONFIG2 0x100A08 -#define GT96100_GPP_CONFIG3 0x100A0C -#define GT96100_GPP_IO0 0x100A20 -#define GT96100_GPP_IO1 0x100A24 -#define GT96100_GPP_IO2 0x100A28 -#define GT96100_GPP_IO3 0x100A2C -#define GT96100_GPP_DATA0 0x100A40 -#define GT96100_GPP_DATA1 0x100A44 -#define GT96100_GPP_DATA2 0x100A48 -#define GT96100_GPP_DATA3 0x100A4C -#define GT96100_GPP_LEVEL0 0x100A60 -#define GT96100_GPP_LEVEL1 0x100A64 -#define GT96100_GPP_LEVEL2 0x100A68 -#define GT96100_GPP_LEVEL3 0x100A6C -/* Watchdog */ -#define GT96100_WD_CONFIG 0x101A80 -#define GT96100_WD_VALUE 0x101A84 -/* Communication Unit Arbiter */ -#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0 -/* PCI Arbiters */ -#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0 -#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4 -/* CIU Arbiter */ -#define GT96100_CIU_ARBITER_CONFIG 0x101AC0 -/* Interrupt Controller */ -#define GT96100_MAIN_CAUSE 0x000C18 -#define GT96100_INT0_MAIN_MASK 0x000C1C -#define GT96100_INT1_MAIN_MASK 0x000C24 -#define GT96100_HIGH_CAUSE 0x000C98 -#define GT96100_INT0_HIGH_MASK 0x000C9C -#define GT96100_INT1_HIGH_MASK 0x000CA4 -#define GT96100_INT0_SELECT 0x000C70 -#define GT96100_INT1_SELECT 0x000C74 -#define GT96100_SERIAL_CAUSE 0x103A00 -#define GT96100_SERINT0_MASK 0x103A80 -#define GT96100_SERINT1_MASK 0x103A88 - -#endif /* _GT96100_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/mach-ev96100/mach-gt64120.h mips/include/asm-mips/mach-ev96100/mach-gt64120.h --- mips-orig/include/asm-mips/mach-ev96100/mach-gt64120.h 2006-09-21 00:46:17.877110500 +0900 +++ mips/include/asm-mips/mach-ev96100/mach-gt64120.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,46 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef _ASM_GT64120_EV96100_GT64120_DEP_H -#define _ASM_GT64120_EV96100_GT64120_DEP_H - -/* - * GT96100 config space base address - */ -#define GT64120_BASE (KSEG1ADDR(0x14000000)) - -/* - * PCI Bus allocation - * - * (Guessing ...) - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - -/* - * Duart I/O ports. - */ -#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20) -#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00) - - -/* - * EV96100 interrupt controller register base. - */ -#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) - -/* - * EV96100 UART register base. - */ -#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR -#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR -#define EV96100_BASE_BAUD ( 3686400 / 16 ) - -#endif /* _ASM_GT64120_EV96100_GT64120_DEP_H */ diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/serial.h mips/include/asm-mips/serial.h --- mips-orig/include/asm-mips/serial.h 2006-09-21 00:46:18.805168500 +0900 +++ mips/include/asm-mips/serial.h 2006-09-21 00:46:07.476460500 +0900 @@ -54,20 +54,18 @@ /* * Both Galileo boards have the same UART mappings. */ -#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120) -#include -#include -#define EV96100_SERIAL_PORT_DEFNS \ - { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \ +#ifdef CONFIG_MIPS_EV64120 +#define EV64120_SERIAL_PORT_DEFNS \ + { .baud_base = 3686400 / 16, .irq = 6, \ .flags = STD_COM_FLAGS, \ - .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \ + .iomem_base = 0xBD000020, .iomem_reg_shift = 2, \ .io_type = SERIAL_IO_MEM }, \ - { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \ + { .baud_base = 3686400 / 16, .irq = 6, \ .flags = STD_COM_FLAGS, \ - .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \ + .iomem_base = 0xBD000000, .iomem_reg_shift = 2, \ .io_type = SERIAL_IO_MEM }, #else -#define EV96100_SERIAL_PORT_DEFNS +#define EV64120_SERIAL_PORT_DEFNS #endif #ifdef CONFIG_MIPS_ITE8172 @@ -239,7 +237,7 @@ #define SERIAL_PORT_DFNS \ DDB5477_SERIAL_PORT_DEFNS \ - EV96100_SERIAL_PORT_DEFNS \ + EV64120_SERIAL_PORT_DEFNS \ IP32_SERIAL_PORT_DEFNS \ ITE_SERIAL_PORT_DEFNS \ IVR_SERIAL_PORT_DEFNS \ From yoichi_yuasa@tripeaks.co.jp Wed Sep 20 18:09:28 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 20 Sep 2006 18:09:39 +0100 (BST) Received: from mo30.po.2iij.net ([210.128.50.53]:37641 "EHLO mo30.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20027627AbWITRIO (ORCPT ); Wed, 20 Sep 2006 18:08:14 +0100 Received: by mo.po.2iij.net (mo30) id k8KH88xN006026; Thu, 21 Sep 2006 02:08:08 +0900 (JST) Received: from localhost.localdomain (34.26.30.125.dy.iij4u.or.jp [125.30.26.34]) by mbox.po.2iij.net (mbox30) id k8KH81rW028746 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 21 Sep 2006 02:08:01 +0900 (JST) Date: Thu, 21 Sep 2006 02:02:21 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH 3/4] removed Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G support Message-Id: <20060921020221.00287460.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20060921020031.0033e2d9.yoichi_yuasa@tripeaks.co.jp> References: <20060921015638.480ea7b1.yoichi_yuasa@tripeaks.co.jp> <20060921015758.639c4545.yoichi_yuasa@tripeaks.co.jp> <20060921020031.0033e2d9.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 1.0.6 (GTK+ 1.2.10; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 12609 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips This patch has removed Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G support. Yoichi Signed-off-by: Yoichi Yuasa diff -pruN -X mips/Documentation/dontdiff mips-orig/Documentation/feature-removal-schedule.txt mips/Documentation/feature-removal-schedule.txt --- mips-orig/Documentation/feature-removal-schedule.txt 2006-09-21 01:00:57.740734250 +0900 +++ mips/Documentation/feature-removal-schedule.txt 2006-09-21 01:01:14.757286250 +0900 @@ -202,14 +202,6 @@ Who: Nick Piggin --------------------------- -What: Support for the Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G -When: September 2006 -Why: Some do no longer build and apparently there is no user base left - for these platforms. -Who: Ralf Baechle - ---------------------------- - What: Support for MIPS Technologies' Altas and SEAD evaluation board When: September 2006 Why: Some do no longer build and apparently there is no user base left diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Kconfig mips/arch/mips/Kconfig --- mips-orig/arch/mips/Kconfig 2006-09-21 01:00:57.744732500 +0900 +++ mips/arch/mips/Kconfig 2006-09-21 01:01:14.757286250 +0900 @@ -373,76 +373,6 @@ config MIPS_SIM This option enables support for MIPS Technologies MIPSsim software emulator. -config MOMENCO_OCELOT - bool "Momentum Ocelot board" - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select IRQ_CPU_RM7K - select MIPS_GT64120 - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - The Ocelot is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer . - -config MOMENCO_OCELOT_3 - bool "Momentum Ocelot-3 board" - select BOOT_ELF32 - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select IRQ_CPU_RM7K - select IRQ_MV64340 - select PCI_MARVELL - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_RM9000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - The Ocelot-3 is based off Discovery III System Controller and - PMC-Sierra Rm79000 core. - -config MOMENCO_OCELOT_C - bool "Momentum Ocelot-C board" - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select IRQ_MV64340 - select PCI_MARVELL - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - The Ocelot is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer . - -config MOMENCO_OCELOT_G - bool "Momentum Ocelot-G board" - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select IRQ_CPU_RM7K - select PCI_MARVELL - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - The Ocelot is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer . - config MIPS_XXS1500 bool "MyCable XXS1500 board" select DMA_NONCOHERENT @@ -906,9 +836,6 @@ config IRQ_CPU_RM7K config IRQ_CPU_RM9K bool -config IRQ_MV64340 - bool - config DDB5XXX_COMMON bool @@ -982,9 +909,8 @@ config EMMA2RH choice prompt "Galileo Chip Clock" #default SYSCLK_83 if MIPS_EV64120 - depends on MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G + depends on MIPS_EV64120 default SYSCLK_83 if MIPS_EV64120 - default SYSCLK_100 if MOMENCO_OCELOT || MOMENCO_OCELOT_G config SYSCLK_75 bool "75" if MIPS_EV64120 @@ -993,7 +919,7 @@ config SYSCLK_83 bool "83.3" if MIPS_EV64120 config SYSCLK_100 - bool "100" if MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G + bool "100" if MIPS_EV64120 endchoice diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/Makefile mips/arch/mips/Makefile --- mips-orig/arch/mips/Makefile 2006-09-21 01:00:57.744732500 +0900 +++ mips/arch/mips/Makefile 2006-09-21 01:01:14.761284500 +0900 @@ -334,34 +334,6 @@ cflags-$(CONFIG_MIPS_SIM) += -Iinclude/a load-$(CONFIG_MIPS_SIM) += 0x80100000 # -# Momentum Ocelot board -# -# The Ocelot setup.o must be linked early - it does the ioremap() for the -# mips_io_port_base. -# -core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \ - arch/mips/gt64120/momenco_ocelot/ -cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot -load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000 - -# -# Momentum Ocelot-G board -# -# The Ocelot-G setup.o must be linked early - it does the ioremap() for the -# mips_io_port_base. -# -core-$(CONFIG_MOMENCO_OCELOT_G) += arch/mips/momentum/ocelot_g/ -load-$(CONFIG_MOMENCO_OCELOT_G) += 0xffffffff80100000 - -# -# Momentum Ocelot-C and -CS boards -# -# The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the -# mips_io_port_base. -core-$(CONFIG_MOMENCO_OCELOT_C) += arch/mips/momentum/ocelot_c/ -load-$(CONFIG_MOMENCO_OCELOT_C) += 0xffffffff80100000 - -# # PMC-Sierra Yosemite # core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ @@ -376,13 +348,6 @@ cflags-$(CONFIG_QEMU) += -Iinclude/asm- load-$(CONFIG_QEMU) += 0xffffffff80010000 # -# Momentum Ocelot-3 -# -core-$(CONFIG_MOMENCO_OCELOT_3) += arch/mips/momentum/ocelot_3/ -cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3 -load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000 - -# # Basler eXcite # core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/ocelot_3_defconfig mips/arch/mips/configs/ocelot_3_defconfig --- mips-orig/arch/mips/configs/ocelot_3_defconfig 2006-09-21 00:46:00.168003750 +0900 +++ mips/arch/mips/configs/ocelot_3_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,1156 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:15 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_EV96100 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -CONFIG_MOMENCO_OCELOT_3=y -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_CPU_RM7K=y -CONFIG_IRQ_MV64340=y -CONFIG_PCI_MARVELL=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_BOOT_ELF32=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -CONFIG_CPU_RM9000=y -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM9000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# Block layer -# -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -# CONFIG_IPV6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -# CONFIG_NF_CONNTRACK is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set - -# -# IPv6: Netfilter Configuration (EXPERIMENTAL) -# -# CONFIG_IP6_NF_QUEUE is not set -# CONFIG_IP6_NF_IPTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_CDROM_PKTCDVD is not set -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=m -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -# CONFIG_BLK_DEV_SD is not set -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI Transport Attributes -# -# CONFIG_SCSI_SPI_ATTRS is not set -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_ISCSI_ATTRS=m -CONFIG_SCSI_SAS_ATTRS=m - -# -# SCSI low-level drivers -# -CONFIG_ISCSI_TCP=m -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_SATA is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -CONFIG_TUN=m - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=m - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_LXT_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_SMSC_PHY=m - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -CONFIG_E100=y -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_LAN_SAA9730 is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_MV643XX_ETH=y -CONFIG_MV643XX_ETH_0=y -CONFIG_MV643XX_ETH_1=y -CONFIG_MV643XX_ETH_2=y - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PPP=m -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -# CONFIG_PPP_BSDCOMP is not set -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -CONFIG_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FB=y -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_TILEBLITTING is not set -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_SMIVGX is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_VIRTUAL is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y - -# -# Logo configuration -# -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=m -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -CONFIG_JBD=m -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set -# CONFIG_REISERFS_FS_XATTR is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -CONFIG_XFS_FS=m -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_SECURITY is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=m - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_EFS_FS=y -CONFIG_CRAMFS=y -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -# CONFIG_NFSD_V3_ACL is not set -# CONFIG_NFSD_V4 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=m -# CONFIG_SMB_NLS_DEFAULT is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=m -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="ip=any root=nfs" - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -CONFIG_CRC_CCITT=m -CONFIG_CRC16=m -CONFIG_CRC32=y -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=m -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/ocelot_c_defconfig mips/arch/mips/configs/ocelot_c_defconfig --- mips-orig/arch/mips/configs/ocelot_c_defconfig 2006-09-21 00:46:00.168003750 +0900 +++ mips/arch/mips/configs/ocelot_c_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,901 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:16 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_EV96100 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -CONFIG_MOMENCO_OCELOT_C=y -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_MV64340=y -CONFIG_PCI_MARVELL=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -CONFIG_CPU_RM7000=y -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -# CONFIG_32BIT is not set -CONFIG_64BIT=y -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_RESOURCES_64BIT=y -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# -# CONFIG_BLK_DEV_IO_TRACE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_BUILD_ELF64 is not set -CONFIG_MIPS32_COMPAT=y -CONFIG_COMPAT=y -CONFIG_MIPS32_O32=y -CONFIG_MIPS32_N32=y -CONFIG_BINFMT_ELF32=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -# CONFIG_PACKET is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_SOFTMAC=y -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=y - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=y -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -# CONFIG_MV643XX_ETH is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -# CONFIG_UNWIND_INFO is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -CONFIG_CRC32=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/ocelot_defconfig mips/arch/mips/configs/ocelot_defconfig --- mips-orig/arch/mips/configs/ocelot_defconfig 2006-09-21 00:46:00.168003750 +0900 +++ mips/arch/mips/configs/ocelot_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,850 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:16 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_EV96100 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -CONFIG_MOMENCO_OCELOT=y -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_CPU_RM7K=y -CONFIG_MIPS_GT64120=y -CONFIG_SWAP_IO_SPACE=y -# CONFIG_SYSCLK_75 is not set -# CONFIG_SYSCLK_83 is not set -CONFIG_SYSCLK_100=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -CONFIG_CPU_RM7000=y -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_HOTPLUG is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -# CONFIG_PCI is not set -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -# CONFIG_PACKET is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_SOFTMAC=y -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=y - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=y -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# PHY device support -# -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_DM9000 is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -# CONFIG_UNWIND_INFO is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -CONFIG_CRC32=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/configs/ocelot_g_defconfig mips/arch/mips/configs/ocelot_g_defconfig --- mips-orig/arch/mips/configs/ocelot_g_defconfig 2006-09-21 00:46:00.172004000 +0900 +++ mips/arch/mips/configs/ocelot_g_defconfig 1970-01-01 09:00:00.000000000 +0900 @@ -1,904 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.18-rc1 -# Thu Jul 6 10:04:16 2006 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_EV96100 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -CONFIG_MOMENCO_OCELOT_G=y -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_V2PCI is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5477 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_QEMU is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_CPU_RM7K=y -CONFIG_PCI_MARVELL=y -CONFIG_SWAP_IO_SPACE=y -# CONFIG_SYSCLK_75 is not set -# CONFIG_SYSCLK_83 is not set -CONFIG_SYSCLK_100=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -CONFIG_CPU_RM7000=y -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -# CONFIG_32BIT is not set -CONFIG_64BIT=y -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_RESOURCES_64BIT=y -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_RT_MUTEXES=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# -# CONFIG_BLK_DEV_IO_TRACE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_BUILD_ELF64 is not set -CONFIG_MIPS32_COMPAT=y -CONFIG_COMPAT=y -CONFIG_MIPS32_O32=y -CONFIG_MIPS32_N32=y -CONFIG_BINFMT_ELF32=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -# CONFIG_PACKET is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_SOFTMAC=y -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=y - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=y -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_GALILEO_64240_ETH=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -# CONFIG_UNWIND_INFO is not set -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -CONFIG_CRC32=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_PLIST=y diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/Makefile mips/arch/mips/gt64120/momenco_ocelot/Makefile --- mips-orig/arch/mips/gt64120/momenco_ocelot/Makefile 2006-09-21 00:46:00.212006500 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,9 +0,0 @@ -# -# Makefile for Momentum's Ocelot board. -# - -obj-y += irq.o prom.o reset.o setup.o - -obj-$(CONFIG_KGDB) += dbg_io.o - -EXTRA_AFLAGS := $(CFLAGS) diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/dbg_io.c mips/arch/mips/gt64120/momenco_ocelot/dbg_io.c --- mips-orig/arch/mips/gt64120/momenco_ocelot/dbg_io.c 2006-09-21 00:46:00.212006500 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/dbg_io.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,125 +0,0 @@ - -#ifdef CONFIG_KGDB - -#include /* For the serial port location and base baud */ - -/* --- CONFIG --- */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE OCELOT_SERIAL1_BASE -#define MAX_BAUD OCELOT_BASE_BAUD - -/* === END OF CONFIG === */ - -#define REG_OFFSET 4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/irq.c mips/arch/mips/gt64120/momenco_ocelot/irq.c --- mips-orig/arch/mips/gt64120/momenco_ocelot/irq.c 2006-09-21 00:46:00.216006750 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,95 +0,0 @@ -/* - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_status() & read_c0_cause(); - - if (pending & STATUSF_IP2) /* int0 hardware line */ - do_IRQ(2, regs); - else if (pending & STATUSF_IP3) /* int1 hardware line */ - do_IRQ(3, regs); - else if (pending & STATUSF_IP4) /* int2 hardware line */ - do_IRQ(4, regs); - else if (pending & STATUSF_IP5) /* int3 hardware line */ - do_IRQ(5, regs); - else if (pending & STATUSF_IP6) /* int4 hardware line */ - do_IRQ(6, regs); - else if (pending & STATUSF_IP7) /* cpu timer */ - do_IRQ(7, regs); - else { - /* - * Now look at the extended interrupts - */ - pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; - - if (pending & STATUSF_IP8) /* int6 hardware line */ - do_IRQ(8, regs); - else if (pending & STATUSF_IP9) /* int7 hardware line */ - do_IRQ(9, regs); - else if (pending & STATUSF_IP10) /* int8 hardware line */ - do_IRQ(10, regs); - else if (pending & STATUSF_IP11) /* int9 hardware line */ - do_IRQ(11, regs); - } -} - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM); - local_irq_disable(); - - mips_cpu_irq_init(0); - rm7k_cpu_irq_init(8); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h mips/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h --- mips-orig/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h 2006-09-21 00:46:00.216006750 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,30 +0,0 @@ -/* - * Ocelot Board Register Definitions - * - * (C) 2001 Red Hat, Inc. - * - * GPL'd - */ -#ifndef __MOMENCO_OCELOT_PLD_H__ -#define __MOMENCO_OCELOT_PLD_H__ - -#define OCELOT_CS0_ADDR (0xe0020000) - -#define OCELOT_REG_BOARDREV (0) -#define OCELOT_REG_PLD1_ID (1) -#define OCELOT_REG_PLD2_ID (2) -#define OCELOT_REG_RESET_STATUS (3) -#define OCELOT_REG_BOARD_STATUS (4) -#define OCELOT_REG_CPCI_ID (5) -#define OCELOT_REG_I2C_CTRL (8) -#define OCELOT_REG_EEPROM_MODE (9) -#define OCELOT_REG_INTMASK (10) -#define OCELOT_REG_INTSTATUS (11) -#define OCELOT_REG_INTSET (12) -#define OCELOT_REG_INTCLR (13) - -#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y) -#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x) - - -#endif /* __MOMENCO_OCELOT_PLD_H__ */ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/prom.c mips/arch/mips/gt64120/momenco_ocelot/prom.c --- mips-orig/arch/mips/gt64120/momenco_ocelot/prom.c 2006-09-21 00:46:00.216006750 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,73 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include - -#include -#include -#include - -struct callvectors* debug_vectors; - -extern unsigned long gt64120_base; - -const char *get_system_type(void) -{ - return "Momentum Ocelot"; -} - -/* [jsun@junsun.net] PMON passes arguments in C main() style */ -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - uint32_t tmp; - int i; - - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_OCELOT; - - while (*env) { - if (strncmp("gtbase", *env, 6) == 0) { - gt64120_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - break; - } - *env++; - } - - debug_vectors->printf("Booting Linux kernel...\n"); - - /* All the boards have at least 64MiB. If there's more, we - detect and register it later */ - add_memory_region(0, 64 << 20, BOOT_MEM_RAM); -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/reset.c mips/arch/mips/gt64120/momenco_ocelot/reset.c --- mips-orig/arch/mips/gt64120/momenco_ocelot/reset.c 2006-09-21 00:46:00.216006750 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,47 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - */ -#include -#include -#include -#include -#include -#include -#include -#include - -void momenco_ocelot_restart(char *command) -{ - void *nvram = ioremap_nocache(0x2c807000, 0x1000); - - if (!nvram) { - printk(KERN_NOTICE "ioremap of reset register failed\n"); - return; - } - writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to - assert reset in 1/16 second */ - mdelay(10+(1000/16)); - iounmap(nvram); - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_ocelot_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_ocelot_power_off(void) -{ - momenco_ocelot_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/gt64120/momenco_ocelot/setup.c mips/arch/mips/gt64120/momenco_ocelot/setup.c --- mips-orig/arch/mips/gt64120/momenco_ocelot/setup.c 2006-09-21 00:46:00.216006750 +0900 +++ mips/arch/mips/gt64120/momenco_ocelot/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,369 +0,0 @@ -/* - * setup.c - * - * BRIEF MODULE DESCRIPTION - * Momentum Computer Ocelot (CP7000) - board dependent boot routines - * - * Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ocelot_pld.h" - -unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE); - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_ocelot_restart(char *command); -extern void momenco_ocelot_halt(void); -extern void momenco_ocelot_power_off(void); - -extern void gt64120_time_init(void); -extern void momenco_ocelot_irq_setup(void); - -static char reset_reason; - -#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1) - -static void __init setup_l3cache(unsigned long size); - -/* setup code for a handoff from a version 1 PMON 2000 PROM */ -void PMON_v1_setup() -{ - /* A wired TLB entry for the GT64120A and the serial port. The - GT64120A is going to be hit on every IRQ anyway - there's - absolutely no point in letting it be a random TLB entry, as - it'll just cause needless churning of the TLB. And we use - the other half for the serial port, which is just a PITA - otherwise :) - - Device Physical Virtual - GT64120 Internal Regs 0x24000000 0xe0000000 - UARTs (CS2) 0x2d000000 0xe0001000 - */ - add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K); - - /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM - in the CS[012] region. We can't use ioremap() yet. The NVRAM - is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. - - Ocelot PLD (CS0) 0x2c000000 0xe0020000 - NVRAM 0x2c800000 0xe0030000 - */ - - add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K); - - /* Relocate the CS3/BootCS region */ - GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21); - - /* Relocate CS[012] */ - GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21); - - /* Relocate the GT64120A itself... */ - GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21); - mb(); - gt64120_base = 0xe0000000; - - /* ...and the PCI0 view of it. */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000); - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001); -} - -/* setup code for a handoff from a version 2 PMON 2000 PROM */ -void PMON_v2_setup() -{ - /* A wired TLB entry for the GT64120A and the serial port. The - GT64120A is going to be hit on every IRQ anyway - there's - absolutely no point in letting it be a random TLB entry, as - it'll just cause needless churning of the TLB. And we use - the other half for the serial port, which is just a PITA - otherwise :) - - Device Physical Virtual - GT64120 Internal Regs 0xf4000000 0xe0000000 - UARTs (CS2) 0xfd000000 0xe0001000 - */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K); - - /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM - in the CS[012] region. We can't use ioremap() yet. The NVRAM - is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. - - Ocelot PLD (CS0) 0xfc000000 0xe0020000 - NVRAM 0xfc800000 0xe0030000 - */ - add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K); - - gt64120_base = 0xe0000000; -} - -void __init plat_mem_setup(void) -{ - void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); - unsigned int tmpword; - - board_time_init = gt64120_time_init; - - _machine_restart = momenco_ocelot_restart; - _machine_halt = momenco_ocelot_halt; - pm_power_off = momenco_ocelot_power_off; - - /* - * initrd_start = (unsigned long)ocelot_initrd_start; - * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; - * initrd_below_start_ok = 1; - */ - - /* do handoff reconfiguration */ - if (gt64120_base == KSEG1ADDR(GT_DEF_BASE)) - PMON_v1_setup(); - else - PMON_v2_setup(); - - /* Turn off the Bit-Error LED */ - OCELOT_PLD_WRITE(0x80, INTCLR); - - /* Relocate all the PCI1 stuff, not that we use it */ - GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21); - GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21); - GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21); - - /* Relocate PCI0 I/O and Mem0 */ - GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21); - GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21); - - /* Relocate PCI0 Mem1 */ - GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21); - - /* For the initial programming, we assume 512MB configuration */ - /* Relocate the CPU's view of the RAM... */ - GT_WRITE(GT_SCS10LD_OFS, 0); - GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21); - - GT_WRITE(GT_SCS1LD_OFS, 0xff); - GT_WRITE(GT_SCS1HD_OFS, 0x00); - GT_WRITE(GT_SCS0LD_OFS, 0); - GT_WRITE(GT_SCS0HD_OFS, 0xff); - GT_WRITE(GT_SCS3LD_OFS, 0xff); - GT_WRITE(GT_SCS3HD_OFS, 0x00); - GT_WRITE(GT_SCS2LD_OFS, 0); - GT_WRITE(GT_SCS2HD_OFS, 0xff); - - /* ...and the PCI0 view of it. */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000); - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000); - - tmpword = OCELOT_PLD_READ(BOARDREV); - if (tmpword < 26) - printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword); - else - printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword); - - tmpword = OCELOT_PLD_READ(PLD1_ID); - printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_PLD_READ(PLD2_ID); - printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_PLD_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - reset_reason = tmpword; - OCELOT_PLD_WRITE(0xff, RESET_STATUS); - - tmpword = OCELOT_PLD_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not"); - printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); - printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); - - if (tmpword&12) - l3func((1<<(((tmpword&12) >> 2)+20))); - - switch(tmpword &3) { - case 3: - /* 512MiB */ - /* Decoders are allready set -- just add the - * appropriate region */ - add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM); - add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM); - break; - case 2: - /* 256MiB -- two banks of 128MiB */ - GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21); - - GT_WRITE(GT_SCS0HD_OFS, 0x7f); - GT_WRITE(GT_SCS2LD_OFS, 0x80); - GT_WRITE(GT_SCS2HD_OFS, 0xff); - - /* reconfigure the PCI0 interface view of memory */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000); - - add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); - add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM); - break; - case 1: - /* 128MiB -- 64MiB per bank */ - GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21); - - GT_WRITE(GT_SCS0HD_OFS, 0x3f); - GT_WRITE(GT_SCS2LD_OFS, 0x40); - GT_WRITE(GT_SCS2HD_OFS, 0x7f); - - /* reconfigure the PCI0 interface view of memory */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000); - - /* add the appropriate region */ - add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); - break; - case 0: - /* 64MiB */ - GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21); - GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21); - GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21); - - GT_WRITE(GT_SCS0HD_OFS, 0x1f); - GT_WRITE(GT_SCS2LD_OFS, 0x20); - GT_WRITE(GT_SCS2HD_OFS, 0x3f); - - /* reconfigure the PCI0 interface view of memory */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); - GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000); - GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000); - GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000); - - break; - } - - /* Fix up the DiskOnChip mapping */ - GT_WRITE(GT_DEV_B3_OFS, 0xfef73); -} - -extern int rm7k_tcache_enabled; -/* - * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() - */ -#define Page_Invalidate_T 0x16 -static void __init setup_l3cache(unsigned long size) -{ - int register i; - unsigned long tmp; - - printk("Enabling L3 cache..."); - - /* Enable the L3 cache in the GT64120A's CPU Configuration register */ - tmp = GT_READ(GT_CPU_OFS); - GT_WRITE(GT_CPU_OFS, tmp | (1<<14)); - - /* Enable the L3 cache in the CPU */ - set_c0_config(1<<12 /* CONF_TE */); - - /* Clear the cache */ - write_c0_taglo(0); - write_c0_taghi(0); - - for (i=0; i < size; i+= 4096) { - __asm__ __volatile__ ( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (KSEG0ADDR(i)), - "i" (Page_Invalidate_T)); - } - - /* Let the RM7000 MM code know that the tertiary cache is enabled */ - rm7k_tcache_enabled = 1; - - printk("Done\n"); -} - - -/* This needs to be one of the first initcalls, because no I/O port access - can work before this */ - -static int io_base_ioremap(void) -{ - void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE); - - if (!io_remap_range) { - panic("Could not ioremap I/O port range"); - } - set_io_port_base(io_remap_range - GT_PCI_IO_BASE); - - return 0; -} - -module_init(io_base_ioremap); diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/kernel/Makefile mips/arch/mips/kernel/Makefile --- mips-orig/arch/mips/kernel/Makefile 2006-09-21 00:46:00.256009250 +0900 +++ mips/arch/mips/kernel/Makefile 2006-09-21 01:01:14.781275750 +0900 @@ -49,7 +49,6 @@ obj-$(CONFIG_I8259) += i8259.o obj-$(CONFIG_IRQ_CPU) += irq_cpu.o obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o -obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o obj-$(CONFIG_32BIT) += scall32-o32.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/kernel/irq-mv6434x.c mips/arch/mips/kernel/irq-mv6434x.c --- mips-orig/arch/mips/kernel/irq-mv6434x.c 2006-09-21 00:46:00.268010000 +0900 +++ mips/arch/mips/kernel/irq-mv6434x.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,162 +0,0 @@ -/* - * Copyright 2002 Momentum Computer - * Author: mdharm@momenco.com - * Copyright (C) 2004 Ralf Baechle - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -static unsigned int irq_base; - -static inline int ls1bit32(unsigned int x) -{ - int b = 31, s; - - s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; - s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; - s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; - s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; - s = 1; if (x << 1 == 0) s = 0; b -= s; - - return b; -} - -/* mask off an interrupt -- 1 is enable, 0 is disable */ -static inline void mask_mv64340_irq(unsigned int irq) -{ - uint32_t value; - - if (irq < (irq_base + 32)) { - value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); - value &= ~(1 << (irq - irq_base)); - MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value); - } else { - value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); - value &= ~(1 << (irq - irq_base - 32)); - MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value); - } -} - -/* unmask an interrupt -- 1 is enable, 0 is disable */ -static inline void unmask_mv64340_irq(unsigned int irq) -{ - uint32_t value; - - if (irq < (irq_base + 32)) { - value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); - value |= 1 << (irq - irq_base); - MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value); - } else { - value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); - value |= 1 << (irq - irq_base - 32); - MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value); - } -} - -/* - * Enables the IRQ on Marvell Chip - */ -static void enable_mv64340_irq(unsigned int irq) -{ - unmask_mv64340_irq(irq); -} - -/* - * Initialize the IRQ on Marvell Chip - */ -static unsigned int startup_mv64340_irq(unsigned int irq) -{ - unmask_mv64340_irq(irq); - return 0; -} - -/* - * Disables the IRQ on Marvell Chip - */ -static void disable_mv64340_irq(unsigned int irq) -{ - mask_mv64340_irq(irq); -} - -/* - * Masks and ACKs an IRQ - */ -static void mask_and_ack_mv64340_irq(unsigned int irq) -{ - mask_mv64340_irq(irq); -} - -/* - * End IRQ processing - */ -static void end_mv64340_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - unmask_mv64340_irq(irq); -} - -/* - * Interrupt handler for interrupts coming from the Marvell chip. - * It could be built in ethernet ports etc... - */ -void ll_mv64340_irq(struct pt_regs *regs) -{ - unsigned int irq_src_low, irq_src_high; - unsigned int irq_mask_low, irq_mask_high; - - /* read the interrupt status registers */ - irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); - irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); - irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW); - irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH); - - /* mask for just the interrupts we want */ - irq_src_low &= irq_mask_low; - irq_src_high &= irq_mask_high; - - if (irq_src_low) - do_IRQ(ls1bit32(irq_src_low) + irq_base, regs); - else - do_IRQ(ls1bit32(irq_src_high) + irq_base + 32, regs); -} - -#define shutdown_mv64340_irq disable_mv64340_irq - -struct irq_chip mv64340_irq_type = { - .typename = "MV-64340", - .startup = startup_mv64340_irq, - .shutdown = shutdown_mv64340_irq, - .enable = enable_mv64340_irq, - .disable = disable_mv64340_irq, - .ack = mask_and_ack_mv64340_irq, - .end = end_mv64340_irq, -}; - -void __init mv64340_irq_init(unsigned int base) -{ - int i; - - /* Reset irq handlers pointers to NULL */ - for (i = base; i < base + 64; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 2; - irq_desc[i].chip = &mv64340_irq_type; - } - - irq_base = base; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/Makefile mips/arch/mips/momentum/ocelot_3/Makefile --- mips-orig/arch/mips/momentum/ocelot_3/Makefile 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/ocelot_3/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,8 +0,0 @@ -# -# Makefile for Momentum Computer's Ocelot-3 board. -# -# Note! Dependencies are done automagically by 'make dep', which also -# removes any old dependencies. DON'T put your own dependencies here -# unless it's something special (ie not a .c file). -# -obj-y += irq.o prom.o reset.o setup.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/irq.c mips/arch/mips/momentum/ocelot_3/irq.c --- mips-orig/arch/mips/momentum/ocelot_3/irq.c 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/ocelot_3/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,109 +0,0 @@ -/* - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) - * - * Copyright 2004 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct irqaction cascade_mv64340 = { - no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL -}; - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM | ST0_BEV); - - rm7k_cpu_irq_init(8); - - /* set up the cascading interrupts */ - setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */ - mv64340_irq_init(16); - - set_c0_status(ST0_IM); /* IE in the status register */ - -} - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP0) - do_IRQ(0, regs); - else if (pending & STATUSF_IP1) - do_IRQ(1, regs); - else if (pending & STATUSF_IP2) - do_IRQ(2, regs); - else if (pending & STATUSF_IP3) - do_IRQ(3, regs); - else if (pending & STATUSF_IP4) - do_IRQ(4, regs); - else if (pending & STATUSF_IP5) - do_IRQ(5, regs); - else if (pending & STATUSF_IP6) - do_IRQ(6, regs); - else if (pending & STATUSF_IP7) - do_IRQ(7, regs); - else { - /* - * Now look at the extended interrupts - */ - pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; - - if (pending & STATUSF_IP8) - ll_mv64340_irq(regs); - else - spurious_interrupt(regs); - } -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h mips/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h --- mips-orig/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,57 +0,0 @@ -/* - * Ocelot-3 Board Register Definitions - * - * (C) 2002 Momentum Computer Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - */ - -#ifndef __OCELOT_3_FPGA_H__ -#define __OCELOT_3_FPGA_H__ - -#define OCELOT_3_REG_BOARDREV 0x0 -#define OCELOT_3_REG_FPGA_REV 0x1 -#define OCELOT_3_REG_FPGA_TYPE 0x2 -#define OCELOT_3_REG_RESET_STATUS 0x3 -#define OCELOT_3_REG_BOARD_STATUS 0x4 -#define OCELOT_3_REG_CPCI_ID 0x5 -#define OCELOT_3_REG_SET 0x6 -#define OCELOT_3_REG_CLR 0x7 -#define OCELOT_3_REG_EEPROM_MODE 0x9 -#define OCELOT_3_REG_INTMASK 0xa -#define OCELOT_3_REG_INTSTAT 0xb -#define OCELOT_3_REG_UART_INTMASK 0xc -#define OCELOT_3_REG_UART_INTSTAT 0xd -#define OCELOT_3_REG_INTSET 0xe -#define OCELOT_3_REG_INTCLR 0xf - -extern unsigned long ocelot_fpga_base; - -#define OCELOT_FPGA_WRITE(x, y) writeb(x, ocelot_fpga_base + OCELOT_3_REG_##y) -#define OCELOT_FPGA_READ(x) readb(ocelot_fpga_base + OCELOT_3_REG_##x) - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/prom.c mips/arch/mips/momentum/ocelot_3/prom.c --- mips-orig/arch/mips/momentum/ocelot_3/prom.c 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/ocelot_3/prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,248 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Copyright 2004 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - */ -#include -#include -#include - -#include -#include -#include -#include "ocelot_3_fpga.h" - -struct callvectors* debug_vectors; -extern unsigned long marvell_base; -extern unsigned long cpu_clock; - -#ifdef CONFIG_MV643XX_ETH -extern unsigned char prom_mac_addr_base[6]; -#endif - -const char *get_system_type(void) -{ - return "Momentum Ocelot-3"; -} - -#ifdef CONFIG_MV643XX_ETH -void burn_clocks(void) -{ - int i; - - /* this loop should burn at least 1us -- this should be plenty */ - for (i = 0; i < 0x10000; i++) - ; -} - -u8 exchange_bit(u8 val, u8 cs) -{ - /* place the data */ - OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE); - burn_clocks(); - - /* turn the clock on */ - OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE); - burn_clocks(); - - /* turn the clock off and read-strobe */ - OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - - /* return the data */ - return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); -} - -void get_mac(char dest[6]) -{ - u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int i,j; - - for (i = 0; i < 12; i++) - exchange_bit(read_opcode[i], 1); - - for (j = 0; j < 6; j++) { - dest[j] = 0; - for (i = 0; i < 8; i++) { - dest[j] <<= 1; - dest[j] |= exchange_bit(0, 1); - } - } - - /* turn off CS */ - exchange_bit(0,0); -} -#endif - - -#ifdef CONFIG_64BIT - -unsigned long signext(unsigned long addr) -{ - addr &= 0xffffffff; - return (unsigned long)((int)addr); -} - -void *get_arg(unsigned long args, int arc) -{ - unsigned long ul; - unsigned char *puc, uc; - - args += (arc * 4); - ul = (unsigned long)signext(args); - puc = (unsigned char *)ul; - if (puc == 0) - return (void *)0; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - uc = *puc++; - ul = (unsigned long)uc; - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 24); -#else /* CONFIG_CPU_LITTLE_ENDIAN */ - uc = *puc++; - ul = ((unsigned long)uc) << 24; - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= ((unsigned long)uc); -#endif /* CONFIG_CPU_LITTLE_ENDIAN */ - ul = signext(ul); - return (void *)ul; -} - -char *arg64(unsigned long addrin, int arg_index) -{ - unsigned long args; - char *p; - - args = signext(addrin); - p = (char *)get_arg(args, arg_index); - - return p; -} -#endif /* CONFIG_64BIT */ - -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - int i; - -#ifdef CONFIG_64BIT - char *ptr; - printk("prom_init - MIPS64\n"); - - /* save the PROM vectors for debugging use */ - debug_vectors = (struct callvectors *)signext((unsigned long)cv); - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - - for (i = 1; i < argc; i++) { - ptr = (char *)arg64((unsigned long)arg, i); - if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >= - sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ptr); - strcat(arcs_cmdline, " "); - } - i = 0; - - while (1) { - ptr = (char *)arg64((unsigned long)env, i); - if (! ptr) - break; - - if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(ptr + strlen("gtbase="), - NULL, 16); - - if ((marvell_base & 0xffffffff00000000) == 0) - marvell_base |= 0xffffffff00000000; - - printk("marvell_base set to 0x%016lx\n", marvell_base); - } - if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(ptr + strlen("cpuclock="), - NULL, 10); - printk("cpu_clock set to %d\n", cpu_clock); - } - i++; - } - printk("arcs_cmdline: %s\n", arcs_cmdline); - -#else /* CONFIG_64BIT */ - - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - while (*env) { - if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - } - if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(*env + strlen("cpuclock="), - NULL, 10); - } - env++; - } -#endif /* CONFIG_64BIT */ - - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_OCELOT_3; - -#ifdef CONFIG_MV643XX_ETH - /* get the base MAC address for on-board ethernet ports */ - get_mac(prom_mac_addr_base); -#endif - -#ifndef CONFIG_64BIT - debug_vectors->printf("Booting Linux kernel...\n"); -#endif -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} - -void __init prom_fixup_mem_map(unsigned long start, unsigned long end) -{ -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/reset.c mips/arch/mips/momentum/ocelot_3/reset.c --- mips-orig/arch/mips/momentum/ocelot_3/reset.c 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/ocelot_3/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,59 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 01, 05 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Copyright 2004 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - */ -#include -#include -#include -#include -#include -#include -#include -#include - -void momenco_ocelot_restart(char *command) -{ - /* base address of timekeeper portion of part */ - void *nvram = (void *) 0xfc807000L; - - /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ - writeb(0x84, nvram + 0xff7); - - /* wait for the watchdog to go off */ - mdelay(100+(1000/16)); - - /* if the watchdog fails for some reason, let people know */ - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_ocelot_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_ocelot_power_off(void) -{ - momenco_ocelot_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_3/setup.c mips/arch/mips/momentum/ocelot_3/setup.c --- mips-orig/arch/mips/momentum/ocelot_3/setup.c 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/ocelot_3/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,399 +0,0 @@ -/* - * setup.c - * - * BRIEF MODULE DESCRIPTION - * Momentum Computer Ocelot-3 board dependent boot routines - * - * Copyright (C) 1996, 1997, 01, 05 Ralf Baechle - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: Matthew Dharm, Momentum Computer - * mdharm@momenco.com - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2004 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ocelot_3_fpga.h" - -/* Marvell Discovery Register Base */ -unsigned long marvell_base = (signed)0xf4000000; - -/* CPU clock */ -unsigned long cpu_clock; - -/* RTC/NVRAM */ -unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000; - -/* FPGA Base */ -unsigned long ocelot_fpga_base = (signed)0xfc000000; - -/* Serial base */ -unsigned long uart_base = (signed)0xfd000000; - -/* - * Marvell Discovery SRAM. This is one place where Ethernet - * Tx and Rx descriptors can be placed to improve performance - */ -extern unsigned long mv64340_sram_base; - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_ocelot_restart(char *command); -extern void momenco_ocelot_halt(void); -extern void momenco_ocelot_power_off(void); - -void momenco_time_init(void); -static char reset_reason; - -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask); - -static inline unsigned long ENTRYLO(unsigned long paddr) -{ - return ((paddr & PAGE_MASK) | - (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | - _CACHE_UNCACHED)) >> 6; -} - -void __init bus_error_init(void) -{ - /* nothing */ -} - -/* - * setup code for a handoff from a version 2 PMON 2000 PROM - */ -void setup_wired_tlb_entries(void) -{ - write_c0_wired(0); - local_flush_tlb_all(); - - /* marvell and extra space */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K); - - /* fpga, rtc, and uart */ - add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M); -} - -unsigned long m48t37y_get_time(void) -{ - unsigned int year, month, day, hour, min, sec; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - /* stop the update */ - rtc_base[0x7ff8] = 0x40; - - year = BCD2BIN(rtc_base[0x7fff]); - year += BCD2BIN(rtc_base[0x7ff1]) * 100; - - month = BCD2BIN(rtc_base[0x7ffe]); - - day = BCD2BIN(rtc_base[0x7ffd]); - - hour = BCD2BIN(rtc_base[0x7ffb]); - min = BCD2BIN(rtc_base[0x7ffa]); - sec = BCD2BIN(rtc_base[0x7ff9]); - - /* start the update */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return mktime(year, month, day, hour, min, sec); -} - -int m48t37y_set_time(unsigned long sec) -{ - struct rtc_time tm; - unsigned long flags; - - /* convert to a more useful format -- note months count from 0 */ - to_tm(sec, &tm); - tm.tm_mon += 1; - - spin_lock_irqsave(&rtc_lock, flags); - /* enable writing */ - rtc_base[0x7ff8] = 0x80; - - /* year */ - rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100); - rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100); - - /* month */ - rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon); - - /* day */ - rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday); - - /* hour/min/sec */ - rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour); - rtc_base[0x7ffa] = BIN2BCD(tm.tm_min); - rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec); - - /* day of week -- not really used, but let's keep it up-to-date */ - rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1); - - /* disable writing */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - -void __init plat_timer_setup(struct irqaction *irq) -{ - setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */ -} - -void momenco_time_init(void) -{ - setup_wired_tlb_entries(); - - /* - * Ocelot-3 board has been built with both - * the Rm7900 and the Rm7065C - */ - mips_hpt_frequency = cpu_clock / 2; - - rtc_mips_get_time = m48t37y_get_time; - rtc_mips_set_time = m48t37y_set_time; -} - -/* - * PCI Support for Ocelot-3 - */ - -/* Bus #0 IO and MEM space */ -#define OCELOT_3_PCI_IO_0_START 0xe0000000 -#define OCELOT_3_PCI_IO_0_SIZE 0x08000000 -#define OCELOT_3_PCI_MEM_0_START 0xc0000000 -#define OCELOT_3_PCI_MEM_0_SIZE 0x10000000 - -/* Bus #1 IO and MEM space */ -#define OCELOT_3_PCI_IO_1_START 0xe8000000 -#define OCELOT_3_PCI_IO_1_SIZE 0x08000000 -#define OCELOT_3_PCI_MEM_1_START 0xd0000000 -#define OCELOT_3_PCI_MEM_1_SIZE 0x10000000 - -static struct resource mv_pci_io_mem0_resource = { - .name = "MV64340 PCI0 IO MEM", - .start = OCELOT_3_PCI_IO_0_START, - .end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE - 1, - .flags = IORESOURCE_IO, -}; - -static struct resource mv_pci_io_mem1_resource = { - .name = "MV64340 PCI1 IO MEM", - .start = OCELOT_3_PCI_IO_1_START, - .end = OCELOT_3_PCI_IO_1_START + OCELOT_3_PCI_IO_1_SIZE - 1, - .flags = IORESOURCE_IO, -}; - -static struct resource mv_pci_mem0_resource = { - .name = "MV64340 PCI0 MEM", - .start = OCELOT_3_PCI_MEM_0_START, - .end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct resource mv_pci_mem1_resource = { - .name = "MV64340 PCI1 MEM", - .start = OCELOT_3_PCI_MEM_1_START, - .end = OCELOT_3_PCI_MEM_1_START + OCELOT_3_PCI_MEM_1_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct mv_pci_controller mv_bus0_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem0_resource, - .io_resource = &mv_pci_io_mem0_resource, - }, - .config_addr = MV64340_PCI_0_CONFIG_ADDR, - .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, -}; - -static struct mv_pci_controller mv_bus1_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem1_resource, - .io_resource = &mv_pci_io_mem1_resource, - }, - .config_addr = MV64340_PCI_1_CONFIG_ADDR, - .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, -}; - -static __init int __init ja_pci_init(void) -{ - uint32_t enable; - extern int pci_probe_only; - - /* PMON will assign PCI resources */ - pci_probe_only = 1; - - enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE); - /* - * We require at least one enabled I/O or PCI memory window or we - * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3. - */ - if (enable & (0x01 << 9) || enable & (0x01 << 10)) - register_pci_controller(&mv_bus0_controller.pcic); - - if (enable & (0x01 << 14) || enable & (0x01 << 15)) - register_pci_controller(&mv_bus1_controller.pcic); - - ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE + - OCELOT_3_PCI_IO_1_SIZE - 1; - - iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE + - OCELOT_3_PCI_MEM_1_SIZE - 1; - - set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */ - - return 0; -} - -arch_initcall(ja_pci_init); - -void __init plat_mem_setup(void) -{ - unsigned int tmpword; - - board_time_init = momenco_time_init; - - _machine_restart = momenco_ocelot_restart; - _machine_halt = momenco_ocelot_halt; - pm_power_off = momenco_ocelot_power_off; - - /* Wired TLB entries */ - setup_wired_tlb_entries(); - - /* shut down ethernet ports, just to be sure our memory doesn't get - * corrupted by random ethernet traffic. - */ - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); - do {} - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); - - /* Turn off the Bit-Error LED */ - OCELOT_FPGA_WRITE(0x80, CLR); - - tmpword = OCELOT_FPGA_READ(BOARDREV); - if (tmpword < 26) - printk("Momenco Ocelot-3: Board Assembly Rev. %c\n", - 'A'+tmpword); - else - printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n", - tmpword); - - tmpword = OCELOT_FPGA_READ(FPGA_REV); - printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_FPGA_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - switch (tmpword) { - case 0x1: - printk(" - Power-up reset\n"); - break; - case 0x2: - printk(" - Push-button reset\n"); - break; - case 0x4: - printk(" - cPCI bus reset\n"); - break; - case 0x8: - printk(" - Watchdog reset\n"); - break; - case 0x10: - printk(" - Software reset\n"); - break; - default: - printk(" - Unknown reset cause\n"); - } - reset_reason = tmpword; - OCELOT_FPGA_WRITE(0xff, RESET_STATUS); - - tmpword = OCELOT_FPGA_READ(CPCI_ID); - printk("cPCI ID register: 0x%02x\n", tmpword); - printk(" - Slot number: %d\n", tmpword & 0x1f); - printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); - printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); - - tmpword = OCELOT_FPGA_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1); - - /* Support for 128 MB memory */ - add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/Makefile mips/arch/mips/momentum/ocelot_c/Makefile --- mips-orig/arch/mips/momentum/ocelot_c/Makefile 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/ocelot_c/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,8 +0,0 @@ -# -# Makefile for Momentum Computer's Ocelot-C and -CS boards. -# - -obj-y += cpci-irq.o irq.o prom.o reset.o \ - setup.o uart-irq.o - -obj-$(CONFIG_KGDB) += dbg_io.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/cpci-irq.c mips/arch/mips/momentum/ocelot_c/cpci-irq.c --- mips-orig/arch/mips/momentum/ocelot_c/cpci-irq.c 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/ocelot_c/cpci-irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,152 +0,0 @@ -/* - * Copyright 2002 Momentum Computer - * Author: mdharm@momenco.com - * - * arch/mips/momentum/ocelot_c/cpci-irq.c - * Interrupt routines for cpci. Interrupt numbers are assigned from - * CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources). - * - * Note that the high-level software will need to be careful about using - * these interrupts. If this board is asserting a cPCI interrupt, it will - * also see the asserted interrupt. Care must be taken to avoid an - * interrupt flood. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "ocelot_c_fpga.h" - -#define CPCI_IRQ_BASE 8 - -static inline int ls1bit8(unsigned int x) -{ - int b = 7, s; - - s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s; - s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s; - s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s; - - return b; -} - -/* mask off an interrupt -- 0 is enable, 1 is disable */ -static inline void mask_cpci_irq(unsigned int irq) -{ - uint32_t value; - - value = OCELOT_FPGA_READ(INTMASK); - value |= 1 << (irq - CPCI_IRQ_BASE); - OCELOT_FPGA_WRITE(value, INTMASK); - - /* read the value back to assure that it's really been written */ - value = OCELOT_FPGA_READ(INTMASK); -} - -/* unmask an interrupt -- 0 is enable, 1 is disable */ -static inline void unmask_cpci_irq(unsigned int irq) -{ - uint32_t value; - - value = OCELOT_FPGA_READ(INTMASK); - value &= ~(1 << (irq - CPCI_IRQ_BASE)); - OCELOT_FPGA_WRITE(value, INTMASK); - - /* read the value back to assure that it's really been written */ - value = OCELOT_FPGA_READ(INTMASK); -} - -/* - * Enables the IRQ in the FPGA - */ -static void enable_cpci_irq(unsigned int irq) -{ - unmask_cpci_irq(irq); -} - -/* - * Initialize the IRQ in the FPGA - */ -static unsigned int startup_cpci_irq(unsigned int irq) -{ - unmask_cpci_irq(irq); - return 0; -} - -/* - * Disables the IRQ in the FPGA - */ -static void disable_cpci_irq(unsigned int irq) -{ - mask_cpci_irq(irq); -} - -/* - * Masks and ACKs an IRQ - */ -static void mask_and_ack_cpci_irq(unsigned int irq) -{ - mask_cpci_irq(irq); -} - -/* - * End IRQ processing - */ -static void end_cpci_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - unmask_cpci_irq(irq); -} - -/* - * Interrupt handler for interrupts coming from the FPGA chip. - * It could be built in ethernet ports etc... - */ -void ll_cpci_irq(struct pt_regs *regs) -{ - unsigned int irq_src, irq_mask; - - /* read the interrupt status registers */ - irq_src = OCELOT_FPGA_READ(INTSTAT); - irq_mask = OCELOT_FPGA_READ(INTMASK); - - /* mask for just the interrupts we want */ - irq_src &= ~irq_mask; - - do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs); -} - -#define shutdown_cpci_irq disable_cpci_irq - -struct irq_chip cpci_irq_type = { - .typename = "CPCI/FPGA", - .startup = startup_cpci_irq, - .shutdown = shutdown_cpci_irq, - .enable = enable_cpci_irq, - .disable = disable_cpci_irq, - .ack = mask_and_ack_cpci_irq, - .end = end_cpci_irq, -}; - -void cpci_irq_init(void) -{ - int i; - - /* Reset irq handlers pointers to NULL */ - for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 2; - irq_desc[i].chip = &cpci_irq_type; - } -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/dbg_io.c mips/arch/mips/momentum/ocelot_c/dbg_io.c --- mips-orig/arch/mips/momentum/ocelot_c/dbg_io.c 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/ocelot_c/dbg_io.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,125 +0,0 @@ - -#ifdef CONFIG_KGDB - -#include /* For the serial port location and base baud */ - -/* --- CONFIG --- */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE OCELOT_SERIAL1_BASE -#define MAX_BAUD OCELOT_BASE_BAUD - -/* === END OF CONFIG === */ - -#define REG_OFFSET 4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/irq.c mips/arch/mips/momentum/ocelot_c/irq.c --- mips-orig/arch/mips/momentum/ocelot_c/irq.c 2006-09-21 00:46:01.000055750 +0900 +++ mips/arch/mips/momentum/ocelot_c/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,107 +0,0 @@ -/* - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void uart_irq_init(void); -extern void cpci_irq_init(void); - -static struct irqaction cascade_fpga = { - no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL -}; - -static struct irqaction cascade_mv64340 = { - no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL -}; - -extern void ll_uart_irq(struct pt_regs *regs); -extern void ll_cpci_irq(struct pt_regs *regs); - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP0) - do_IRQ(0, regs); - else if (pending & STATUSF_IP1) - do_IRQ(1, regs); - else if (pending & STATUSF_IP2) - do_IRQ(2, regs); - else if (pending & STATUSF_IP3) - ll_uart_irq(regs); - else if (pending & STATUSF_IP4) - do_IRQ(4, regs); - else if (pending & STATUSF_IP5) - ll_cpci_irq(regs); - else if (pending & STATUSF_IP6) - ll_mv64340_irq(regs); - else if (pending & STATUSF_IP7) - do_IRQ(7, regs); - else - spurious_interrupt(regs); -} - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM); - - mips_cpu_irq_init(0); - - /* set up the cascading interrupts */ - setup_irq(3, &cascade_fpga); - setup_irq(5, &cascade_fpga); - setup_irq(6, &cascade_mv64340); - - mv64340_irq_init(16); - uart_irq_init(); - cpci_irq_init(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h mips/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h --- mips-orig/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,59 +0,0 @@ -/* - * Ocelot-C Board Register Definitions - * - * (C) 2002 Momentum Computer Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - */ - -#ifndef __OCELOT_C_FPGA_H__ -#define __OCELOT_C_FPGA_H__ - - -#ifdef CONFIG_64BIT -#define OCELOT_C_CS0_ADDR (0xfffffffffc000000) -#else -#define OCELOT_C_CS0_ADDR (0xfc000000) -#endif - -#define OCELOT_C_REG_BOARDREV 0x0 -#define OCELOT_C_REG_FPGA_REV 0x1 -#define OCELOT_C_REG_FPGA_TYPE 0x2 -#define OCELOT_C_REG_RESET_STATUS 0x3 -#define OCELOT_C_REG_BOARD_STATUS 0x4 -#define OCELOT_C_REG_CPCI_ID 0x5 -#define OCELOT_C_REG_SET 0x6 -#define OCELOT_C_REG_CLR 0x7 -#define OCELOT_C_REG_EEPROM_MODE 0x9 -#define OCELOT_C_REG_INTMASK 0xa -#define OCELOT_C_REG_INTSTAT 0xb -#define OCELOT_C_REG_UART_INTMASK 0xc -#define OCELOT_C_REG_UART_INTSTAT 0xd -#define OCELOT_C_REG_INTSET 0xe -#define OCELOT_C_REG_INTCLR 0xf - -#define OCELOT_FPGA_WRITE(x, y) writeb(x, OCELOT_C_CS0_ADDR + OCELOT_C_REG_##y) -#define OCELOT_FPGA_READ(x) readb(OCELOT_C_CS0_ADDR + OCELOT_C_REG_##x) - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/prom.c mips/arch/mips/momentum/ocelot_c/prom.c --- mips-orig/arch/mips/momentum/ocelot_c/prom.c 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_c/prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,242 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "ocelot_c_fpga.h" - -struct callvectors* debug_vectors; - -extern unsigned long marvell_base; -extern unsigned long cpu_clock; - -#ifdef CONFIG_MV643XX_ETH -extern unsigned char prom_mac_addr_base[6]; -#endif - -const char *get_system_type(void) -{ -#ifdef CONFIG_CPU_SR71000 - return "Momentum Ocelot-CS"; -#else - return "Momentum Ocelot-C"; -#endif -} - -#ifdef CONFIG_MV643XX_ETH -static void burn_clocks(void) -{ - int i; - - /* this loop should burn at least 1us -- this should be plenty */ - for (i = 0; i < 0x10000; i++) - ; -} - -static u8 exchange_bit(u8 val, u8 cs) -{ - /* place the data */ - OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE); - burn_clocks(); - - /* turn the clock on */ - OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE); - burn_clocks(); - - /* turn the clock off and read-strobe */ - OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - - /* return the data */ - return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); -} - -void get_mac(char dest[6]) -{ - u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int i,j; - - for (i = 0; i < 12; i++) - exchange_bit(read_opcode[i], 1); - - for (j = 0; j < 6; j++) { - dest[j] = 0; - for (i = 0; i < 8; i++) { - dest[j] <<= 1; - dest[j] |= exchange_bit(0, 1); - } - } - - /* turn off CS */ - exchange_bit(0,0); -} -#endif - - -#ifdef CONFIG_64BIT - -unsigned long signext(unsigned long addr) -{ - addr &= 0xffffffff; - return (unsigned long)((int)addr); -} - -void *get_arg(unsigned long args, int arc) -{ - unsigned long ul; - unsigned char *puc, uc; - - args += (arc * 4); - ul = (unsigned long)signext(args); - puc = (unsigned char *)ul; - if (puc == 0) - return (void *)0; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - uc = *puc++; - ul = (unsigned long)uc; - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 24); -#else /* CONFIG_CPU_LITTLE_ENDIAN */ - uc = *puc++; - ul = ((unsigned long)uc) << 24; - uc = *puc++; - ul |= (((unsigned long)uc) << 16); - uc = *puc++; - ul |= (((unsigned long)uc) << 8); - uc = *puc++; - ul |= ((unsigned long)uc); -#endif /* CONFIG_CPU_LITTLE_ENDIAN */ - ul = signext(ul); - return (void *)ul; -} - -char *arg64(unsigned long addrin, int arg_index) -{ - unsigned long args; - char *p; - args = signext(addrin); - p = (char *)get_arg(args, arg_index); - return p; -} -#endif /* CONFIG_64BIT */ - - -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - int i; - -#ifdef CONFIG_64BIT - char *ptr; - - printk("prom_init - MIPS64\n"); - /* save the PROM vectors for debugging use */ - debug_vectors = (struct callvectors *)signext((unsigned long)cv); - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - - for (i = 1; i < argc; i++) { - ptr = (char *)arg64((unsigned long)arg, i); - if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >= - sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ptr); - strcat(arcs_cmdline, " "); - } - i = 0; - while (1) { - ptr = (char *)arg64((unsigned long)env, i); - if (! ptr) - break; - - if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(ptr + strlen("gtbase="), - NULL, 16); - - if ((marvell_base & 0xffffffff00000000) == 0) - marvell_base |= 0xffffffff00000000; - - printk("marvell_base set to 0x%016lx\n", marvell_base); - } - if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(ptr + strlen("cpuclock="), - NULL, 10); - printk("cpu_clock set to %d\n", cpu_clock); - } - i++; - } - printk("arcs_cmdline: %s\n", arcs_cmdline); - -#else /* CONFIG_64BIT */ - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - while (*env) { - if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - } - if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) { - cpu_clock = simple_strtol(*env + strlen("cpuclock="), - NULL, 10); - } - env++; - } -#endif /* CONFIG_64BIT */ - - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_OCELOT_C; - -#ifdef CONFIG_MV643XX_ETH - /* get the base MAC address for on-board ethernet ports */ - get_mac(prom_mac_addr_base); -#endif - -#ifndef CONFIG_64BIT - debug_vectors->printf("Booting Linux kernel...\n"); -#endif -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/reset.c mips/arch/mips/momentum/ocelot_c/reset.c --- mips-orig/arch/mips/momentum/ocelot_c/reset.c 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_c/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,58 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - */ -#include -#include -#include -#include -#include -#include -#include -#include - -void momenco_ocelot_restart(char *command) -{ - /* base address of timekeeper portion of part */ - void *nvram = (void *) -#ifdef CONFIG_64BIT - 0xfffffffffc807000; -#else - 0xfc807000; -#endif - - /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ - writeb(0x84, nvram + 0xff7); - - /* wait for the watchdog to go off */ - mdelay(100+(1000/16)); - - /* if the watchdog fails for some reason, let people know */ - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_ocelot_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_ocelot_power_off(void) -{ - momenco_ocelot_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/setup.c mips/arch/mips/momentum/ocelot_c/setup.c --- mips-orig/arch/mips/momentum/ocelot_c/setup.c 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_c/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,368 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Momentum Computer Ocelot-C and -CS board dependent boot routines - * - * Copyright (C) 1996, 1997, 2001 Ralf Baechle - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: Matthew Dharm, Momentum Computer - * mdharm@momenco.com - * - * Louis Hamilton, Red Hat, Inc. - * hamilton@redhat.com [MIPS64 modifications] - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ocelot_c_fpga.h" - -unsigned long marvell_base; -extern unsigned long mv64340_sram_base; -unsigned long cpu_clock; - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_ocelot_restart(char *command); -extern void momenco_ocelot_halt(void); -extern void momenco_ocelot_power_off(void); - -void momenco_time_init(void); - -static char reset_reason; - -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask); - -static unsigned long ENTRYLO(unsigned long paddr) -{ - return ((paddr & PAGE_MASK) | - (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | - _CACHE_UNCACHED)) >> 6; -} - -/* setup code for a handoff from a version 2 PMON 2000 PROM */ -void PMON_v2_setup(void) -{ - /* Some wired TLB entries for the MV64340 and perhiperals. The - MV64340 is going to be hit on every IRQ anyway - there's - absolutely no point in letting it be a random TLB entry, as - it'll just cause needless churning of the TLB. And we use - the other half for the serial port, which is just a PITA - otherwise :) - - Device Physical Virtual - MV64340 Internal Regs 0xf4000000 0xf4000000 - Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000 - NVRAM (CS1) 0xfc800000 0xfc800000 - UARTs (CS2) 0xfd000000 0xfd000000 - Internal SRAM 0xfe000000 0xfe000000 - M-Systems DOC (CS3) 0xff000000 0xff000000 - */ - printk("PMON_v2_setup\n"); - -#ifdef CONFIG_64BIT - /* marvell and extra space */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K); - /* fpga, rtc, and uart */ - add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M); - /* m-sys and internal SRAM */ - add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M); - - marvell_base = 0xfffffffff4000000; - mv64340_sram_base = 0xfffffffffe000000; -#else - /* marvell and extra space */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K); - /* fpga, rtc, and uart */ - add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M); - /* m-sys and internal SRAM */ - add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M); - - marvell_base = 0xf4000000; - mv64340_sram_base = 0xfe000000; -#endif -} - -unsigned long m48t37y_get_time(void) -{ -#ifdef CONFIG_64BIT - unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000; -#else - unsigned char* rtc_base = (unsigned char*)0xfc800000; -#endif - unsigned int year, month, day, hour, min, sec; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - /* stop the update */ - rtc_base[0x7ff8] = 0x40; - - year = BCD2BIN(rtc_base[0x7fff]); - year += BCD2BIN(rtc_base[0x7ff1]) * 100; - - month = BCD2BIN(rtc_base[0x7ffe]); - - day = BCD2BIN(rtc_base[0x7ffd]); - - hour = BCD2BIN(rtc_base[0x7ffb]); - min = BCD2BIN(rtc_base[0x7ffa]); - sec = BCD2BIN(rtc_base[0x7ff9]); - - /* start the update */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return mktime(year, month, day, hour, min, sec); -} - -int m48t37y_set_time(unsigned long sec) -{ -#ifdef CONFIG_64BIT - unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000; -#else - unsigned char* rtc_base = (unsigned char*)0xfc800000; -#endif - struct rtc_time tm; - unsigned long flags; - - /* convert to a more useful format -- note months count from 0 */ - to_tm(sec, &tm); - tm.tm_mon += 1; - - spin_lock_irqsave(&rtc_lock, flags); - /* enable writing */ - rtc_base[0x7ff8] = 0x80; - - /* year */ - rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100); - rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100); - - /* month */ - rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon); - - /* day */ - rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday); - - /* hour/min/sec */ - rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour); - rtc_base[0x7ffa] = BIN2BCD(tm.tm_min); - rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec); - - /* day of week -- not really used, but let's keep it up-to-date */ - rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1); - - /* disable writing */ - rtc_base[0x7ff8] = 0x00; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - -void __init plat_timer_setup(struct irqaction *irq) -{ - setup_irq(7, irq); -} - -void momenco_time_init(void) -{ -#ifdef CONFIG_CPU_SR71000 - mips_hpt_frequency = cpu_clock; -#elif defined(CONFIG_CPU_RM7000) - mips_hpt_frequency = cpu_clock / 2; -#else -#error Unknown CPU for this board -#endif - printk("momenco_time_init cpu_clock=%d\n", cpu_clock); - - rtc_mips_get_time = m48t37y_get_time; - rtc_mips_set_time = m48t37y_set_time; -} - -void __init plat_mem_setup(void) -{ - unsigned int tmpword; - - board_time_init = momenco_time_init; - - _machine_restart = momenco_ocelot_restart; - _machine_halt = momenco_ocelot_halt; - pm_power_off = momenco_ocelot_power_off; - - /* - * initrd_start = (unsigned long)ocelot_initrd_start; - * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; - * initrd_below_start_ok = 1; - */ - - /* do handoff reconfiguration */ - PMON_v2_setup(); - - /* shut down ethernet ports, just to be sure our memory doesn't get - * corrupted by random ethernet traffic. - */ - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); - MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); - do {} - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); - do {} - while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); - MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1), - MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); - - /* Turn off the Bit-Error LED */ - OCELOT_FPGA_WRITE(0x80, CLR); - - tmpword = OCELOT_FPGA_READ(BOARDREV); -#ifdef CONFIG_CPU_SR71000 - if (tmpword < 26) - printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n", - 'A'+tmpword); - else - printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n", - tmpword); -#else - if (tmpword < 26) - printk("Momenco Ocelot-C: Board Assembly Rev. %c\n", - 'A'+tmpword); - else - printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n", - tmpword); -#endif - - tmpword = OCELOT_FPGA_READ(FPGA_REV); - printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_FPGA_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - switch (tmpword) { - case 0x1: - printk(" - Power-up reset\n"); - break; - case 0x2: - printk(" - Push-button reset\n"); - break; - case 0x4: - printk(" - cPCI bus reset\n"); - break; - case 0x8: - printk(" - Watchdog reset\n"); - break; - case 0x10: - printk(" - Software reset\n"); - break; - default: - printk(" - Unknown reset cause\n"); - } - reset_reason = tmpword; - OCELOT_FPGA_WRITE(0xff, RESET_STATUS); - - tmpword = OCELOT_FPGA_READ(CPCI_ID); - printk("cPCI ID register: 0x%02x\n", tmpword); - printk(" - Slot number: %d\n", tmpword & 0x1f); - printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); - printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); - - tmpword = OCELOT_FPGA_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); - printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); - - switch(tmpword &3) { - case 3: - /* 512MiB */ - add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM); - break; - case 2: - /* 256MiB */ - add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM); - break; - case 1: - /* 128MiB */ - add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM); - break; - case 0: - /* 1GiB -- needs CONFIG_HIGHMEM */ - add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM); - break; - } -} - -#ifndef CONFIG_64BIT -/* This needs to be one of the first initcalls, because no I/O port access - can work before this */ -static int io_base_ioremap(void) -{ - /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */ - void *io_remap_range = ioremap(0xc0000000, 0x30000000); - - if (!io_remap_range) { - panic("Could not ioremap I/O port range"); - } - printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range); - set_io_port_base(io_remap_range - 0xc0000000); - - return 0; -} - -module_init(io_base_ioremap); -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_c/uart-irq.c mips/arch/mips/momentum/ocelot_c/uart-irq.c --- mips-orig/arch/mips/momentum/ocelot_c/uart-irq.c 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_c/uart-irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,146 +0,0 @@ -/* - * Copyright 2002 Momentum Computer - * Author: mdharm@momenco.com - * - * arch/mips/momentum/ocelot_c/uart-irq.c - * Interrupt routines for UARTs. Interrupt numbers are assigned from - * 80 to 81 (2 interrupt sources). - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ocelot_c_fpga.h" - -static inline int ls1bit8(unsigned int x) -{ - int b = 7, s; - - s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s; - s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s; - s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s; - - return b; -} - -/* mask off an interrupt -- 0 is enable, 1 is disable */ -static inline void mask_uart_irq(unsigned int irq) -{ - uint8_t value; - - value = OCELOT_FPGA_READ(UART_INTMASK); - value |= 1 << (irq - 74); - OCELOT_FPGA_WRITE(value, UART_INTMASK); - - /* read the value back to assure that it's really been written */ - value = OCELOT_FPGA_READ(UART_INTMASK); -} - -/* unmask an interrupt -- 0 is enable, 1 is disable */ -static inline void unmask_uart_irq(unsigned int irq) -{ - uint8_t value; - - value = OCELOT_FPGA_READ(UART_INTMASK); - value &= ~(1 << (irq - 74)); - OCELOT_FPGA_WRITE(value, UART_INTMASK); - - /* read the value back to assure that it's really been written */ - value = OCELOT_FPGA_READ(UART_INTMASK); -} - -/* - * Enables the IRQ in the FPGA - */ -static void enable_uart_irq(unsigned int irq) -{ - unmask_uart_irq(irq); -} - -/* - * Initialize the IRQ in the FPGA - */ -static unsigned int startup_uart_irq(unsigned int irq) -{ - unmask_uart_irq(irq); - return 0; -} - -/* - * Disables the IRQ in the FPGA - */ -static void disable_uart_irq(unsigned int irq) -{ - mask_uart_irq(irq); -} - -/* - * Masks and ACKs an IRQ - */ -static void mask_and_ack_uart_irq(unsigned int irq) -{ - mask_uart_irq(irq); -} - -/* - * End IRQ processing - */ -static void end_uart_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - unmask_uart_irq(irq); -} - -/* - * Interrupt handler for interrupts coming from the FPGA chip. - */ -void ll_uart_irq(struct pt_regs *regs) -{ - unsigned int irq_src, irq_mask; - - /* read the interrupt status registers */ - irq_src = OCELOT_FPGA_READ(UART_INTSTAT); - irq_mask = OCELOT_FPGA_READ(UART_INTMASK); - - /* mask for just the interrupts we want */ - irq_src &= ~irq_mask; - - do_IRQ(ls1bit8(irq_src) + 74, regs); -} - -#define shutdown_uart_irq disable_uart_irq - -struct irq_chip uart_irq_type = { - .typename = "UART/FPGA", - .startup = startup_uart_irq, - .shutdown = shutdown_uart_irq, - .enable = enable_uart_irq, - .disable = disable_uart_irq, - .ack = mask_and_ack_uart_irq, - .end = end_uart_irq, -}; - -void uart_irq_init(void) -{ - /* Reset irq handlers pointers to NULL */ - irq_desc[80].status = IRQ_DISABLED; - irq_desc[80].action = 0; - irq_desc[80].depth = 2; - irq_desc[80].chip = &uart_irq_type; - - irq_desc[81].status = IRQ_DISABLED; - irq_desc[81].action = 0; - irq_desc[81].depth = 2; - irq_desc[81].chip = &uart_irq_type; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/Makefile mips/arch/mips/momentum/ocelot_g/Makefile --- mips-orig/arch/mips/momentum/ocelot_g/Makefile 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_g/Makefile 1970-01-01 09:00:00.000000000 +0900 @@ -1,8 +0,0 @@ -# -# Makefile for Momentum Computer's Ocelot-G board. -# - -obj-y += irq.o gt-irq.o prom.o reset.o setup.o -obj-$(CONFIG_KGDB) += dbg_io.o - -EXTRA_AFLAGS := $(CFLAGS) diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/dbg_io.c mips/arch/mips/momentum/ocelot_g/dbg_io.c --- mips-orig/arch/mips/momentum/ocelot_g/dbg_io.c 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_g/dbg_io.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,125 +0,0 @@ - -#ifdef CONFIG_KGDB - -#include /* For the serial port location and base baud */ - -/* --- CONFIG --- */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE OCELOT_SERIAL1_BASE -#define MAX_BAUD OCELOT_BASE_BAUD - -/* === END OF CONFIG === */ - -#define REG_OFFSET 4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -#endif diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/gt-irq.c mips/arch/mips/momentum/ocelot_g/gt-irq.c --- mips-orig/arch/mips/momentum/ocelot_g/gt-irq.c 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_g/gt-irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,213 +0,0 @@ -/* - * - * Copyright 2002 Momentum Computer - * Author: mdharm@momenco.com - * - * arch/mips/momentum/ocelot_g/gt_irq.c - * Interrupt routines for gt64240. Currently it only handles timer irq. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -unsigned long bus_clock; - -/* - * These are interrupt handlers for the GT on-chip interrupts. They - * all come in to the MIPS on a single interrupt line, and have to - * be handled and ack'ed differently than other MIPS interrupts. - */ - -#if CURRENTLY_UNUSED - -struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH]; -void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr); - -/* - * Hooks IRQ handler to the system. When the system is interrupted - * the interrupt service routine is called. - * - * Inputs : - * int_cause - The interrupt cause number. In EVB64120 two parameters - * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. - * bit_num - Indicates which bit number in the cause register - * isr_ptr - Pointer to the interrupt service routine - */ -void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr) -{ - irq_handlers[int_cause][bit_num].routine = isr_ptr; -} - - -/* - * Enables the IRQ on Galileo Chip - * - * Inputs : - * int_cause - The interrupt cause number. In EVB64120 two parameters - * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. - * bit_num - Indicates which bit number in the cause register - * - * Outputs : - * 1 if successful, 0 if failure - */ -int enable_galileo_irq(int int_cause, int bit_num) -{ - if (int_cause == INT_CAUSE_MAIN) - SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num)); - else if (int_cause == INT_CAUSE_HIGH) - SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER, - (1 << bit_num)); - else - return 0; - - return 1; -} - -/* - * Disables the IRQ on Galileo Chip - * - * Inputs : - * int_cause - The interrupt cause number. In EVB64120 two parameters - * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. - * bit_num - Indicates which bit number in the cause register - * - * Outputs : - * 1 if successful, 0 if failure - */ -int disable_galileo_irq(int int_cause, int bit_num) -{ - if (int_cause == INT_CAUSE_MAIN) - RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, - (1 << bit_num)); - else if (int_cause == INT_CAUSE_HIGH) - RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER, - (1 << bit_num)); - else - return 0; - return 1; -} -#endif /* UNUSED */ - -/* - * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#. - * - * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this - * routine can handle, for now. - * - * In the future, we'll route more interrupts to this pin, and that's why - * we keep this particular structure in the function. - */ - -static irqreturn_t gt64240_p0int_irq(int irq, void *dev, struct pt_regs *regs) -{ - uint32_t irq_src, irq_src_mask; - int handled; - - /* get the low interrupt cause register */ - irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER); - - /* get the mask register for this pin */ - irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW); - - /* mask off only the interrupts we're interested in */ - irq_src = irq_src & irq_src_mask; - - handled = IRQ_NONE; - - /* Check for timer interrupt */ - if (irq_src & 0x00000100) { - handled = IRQ_HANDLED; - irq_src &= ~0x00000100; - - /* Clear any pending cause bits */ - MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); - - /* handle the timer call */ - do_timer(regs); -#ifndef CONFIG_SMP - update_process_times(user_mode(regs)); -#endif - } - - if (irq_src) { - printk(KERN_INFO - "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n", - irq_src); - } - - return handled; -} - -/* - * Initializes timer using galileo's built in timer. - */ - -/* - * This will ignore the standard MIPS timer interrupt handler - * that is passed in as *irq (=irq0 in ../kernel/time.c). - * We will do our own timer interrupt handling. - */ -void gt64240_time_init(void) -{ - static struct irqaction timer; - - /* Stop the timer -- we'll use timer #0 */ - MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0); - - /* Load timer value for 100 Hz */ - MV_WRITE(TIMER_COUNTER0, bus_clock / 100); - - /* - * Create the IRQ structure entry for the timer. Since we're too early - * in the boot process to use the "request_irq()" call, we'll hard-code - * the values to the correct interrupt line. - */ - timer.handler = >64240_p0int_irq; - timer.flags = IRQF_SHARED | IRQF_DISABLED; - timer.name = "timer"; - timer.dev_id = NULL; - timer.next = NULL; - timer.mask = CPU_MASK_NONE; - irq_desc[6].action = &timer; - - enable_irq(6); - - /* Clear any pending cause bits */ - MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); - - /* Enable the interrupt for timer 0 */ - MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1); - - /* Enable the timer interrupt for GT-64240 pin P0_INT# */ - MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100); - - /* Configure and start the timer */ - MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3); -} - -void gt64240_irq_init(void) -{ -#if CURRENTLY_UNUSED - int i, j; - - /* Reset irq handlers pointers to NULL */ - for (i = 0; i < MAX_CAUSE_REGS; i++) { - for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) { - irq_handlers[i][j].next = NULL; - irq_handlers[i][j].sync = 0; - irq_handlers[i][j].routine = NULL; - irq_handlers[i][j].data = NULL; - } - } -#endif -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/irq.c mips/arch/mips/momentum/ocelot_g/irq.c --- mips-orig/arch/mips/momentum/ocelot_g/irq.c 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_g/irq.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP2) - do_IRQ(2, regs); - else if (pending & STATUSF_IP3) - do_IRQ(3, regs); - else if (pending & STATUSF_IP4) - do_IRQ(4, regs); - else if (pending & STATUSF_IP5) - do_IRQ(5, regs); - else if (pending & STATUSF_IP6) - do_IRQ(6, regs); - else if (pending & STATUSF_IP7) - do_IRQ(7, regs); - else { - /* - * Now look at the extended interrupts - */ - pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; - - if (pending & STATUSF_IP8) - do_IRQ(8, regs); - else if (pending & STATUSF_IP9) - do_IRQ(9, regs); - else if (pending & STATUSF_IP10) - do_IRQ(10, regs); - else if (pending & STATUSF_IP11) - do_IRQ(11, regs); - else - spurious_interrupt(regs); - } -} - -extern void gt64240_irq_init(void); - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM); - local_irq_disable(); - - mips_cpu_irq_init(0); - rm7k_cpu_irq_init(8); - - gt64240_irq_init(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/ocelot_pld.h mips/arch/mips/momentum/ocelot_g/ocelot_pld.h --- mips-orig/arch/mips/momentum/ocelot_g/ocelot_pld.h 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_g/ocelot_pld.h 1970-01-01 09:00:00.000000000 +0900 @@ -1,30 +0,0 @@ -/* - * Ocelot Board Register Definitions - * - * (C) 2001 Red Hat, Inc. - * - * GPL'd - */ -#ifndef __MOMENCO_OCELOT_PLD_H__ -#define __MOMENCO_OCELOT_PLD_H__ - -#define OCELOT_CS0_ADDR (0xfc000000) - -#define OCELOT_REG_BOARDREV (0) -#define OCELOT_REG_PLD1_ID (1) -#define OCELOT_REG_PLD2_ID (2) -#define OCELOT_REG_RESET_STATUS (3) -#define OCELOT_REG_BOARD_STATUS (4) -#define OCELOT_REG_CPCI_ID (5) -#define OCELOT_REG_I2C_CTRL (8) -#define OCELOT_REG_EEPROM_MODE (9) -#define OCELOT_REG_INTMASK (10) -#define OCELOT_REG_INTSTATUS (11) -#define OCELOT_REG_INTSET (12) -#define OCELOT_REG_INTCLR (13) - -#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y) -#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x) - - -#endif /* __MOMENCO_OCELOT_PLD_H__ */ diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/prom.c mips/arch/mips/momentum/ocelot_g/prom.c --- mips-orig/arch/mips/momentum/ocelot_g/prom.c 2006-09-21 00:46:01.004056000 +0900 +++ mips/arch/mips/momentum/ocelot_g/prom.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,85 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "ocelot_pld.h" - -struct callvectors* debug_vectors; - -extern unsigned long marvell_base; -extern unsigned long bus_clock; - -#ifdef CONFIG_GALILLEO_GT64240_ETH -extern unsigned char prom_mac_addr_base[6]; -#endif - -const char *get_system_type(void) -{ - return "Momentum Ocelot"; -} - -void __init prom_init(void) -{ - int argc = fw_arg0; - char **arg = (char **) fw_arg1; - char **env = (char **) fw_arg2; - struct callvectors *cv = (struct callvectors *) fw_arg3; - int i; - - /* save the PROM vectors for debugging use */ - debug_vectors = cv; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - mips_machgroup = MACH_GROUP_MOMENCO; - mips_machtype = MACH_MOMENCO_OCELOT_G; - -#ifdef CONFIG_GALILLEO_GT64240_ETH - /* get the base MAC address for on-board ethernet ports */ - memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6); -#endif - - while (*env) { - if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { - marvell_base = simple_strtol(*env + strlen("gtbase="), - NULL, 16); - } - if (strncmp("busclock", *env, strlen("busclock")) == 0) { - bus_clock = simple_strtol(*env + strlen("busclock="), - NULL, 10); - } - env++; - } -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/reset.c mips/arch/mips/momentum/ocelot_g/reset.c --- mips-orig/arch/mips/momentum/ocelot_g/reset.c 2006-09-21 00:46:01.008056250 +0900 +++ mips/arch/mips/momentum/ocelot_g/reset.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,47 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - */ -#include -#include -#include -#include -#include -#include -#include -#include - -void momenco_ocelot_restart(char *command) -{ - void *nvram = ioremap_nocache(0x2c807000, 0x1000); - - if (!nvram) { - printk(KERN_NOTICE "ioremap of reset register failed\n"); - return; - } - writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to - assert reset in 1/16 second */ - mdelay(10+(1000/16)); - iounmap(nvram); - printk(KERN_NOTICE "Watchdog reset failed\n"); -} - -void momenco_ocelot_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void momenco_ocelot_power_off(void) -{ - momenco_ocelot_halt(); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/momentum/ocelot_g/setup.c mips/arch/mips/momentum/ocelot_g/setup.c --- mips-orig/arch/mips/momentum/ocelot_g/setup.c 2006-09-21 00:46:01.008056250 +0900 +++ mips/arch/mips/momentum/ocelot_g/setup.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,263 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines - * - * Copyright (C) 1996, 1997, 2001 Ralf Baechle - * Copyright (C) 2000 RidgeRun, Inc. - * Copyright (C) 2001 Red Hat, Inc. - * Copyright (C) 2002 Momentum Computer - * - * Author: Matthew Dharm, Momentum Computer - * mdharm@momenco.com - * - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ocelot_pld.h" - -#ifdef CONFIG_GALILLEO_GT64240_ETH -extern unsigned char prom_mac_addr_base[6]; -#endif - -unsigned long marvell_base; - -/* These functions are used for rebooting or halting the machine*/ -extern void momenco_ocelot_restart(char *command); -extern void momenco_ocelot_halt(void); -extern void momenco_ocelot_power_off(void); - -extern void gt64240_time_init(void); -extern void momenco_ocelot_irq_setup(void); - -static char reset_reason; - -static unsigned long ENTRYLO(unsigned long paddr) -{ - return ((paddr & PAGE_MASK) | - (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | - _CACHE_UNCACHED)) >> 6; -} - -/* setup code for a handoff from a version 2 PMON 2000 PROM */ -void PMON_v2_setup(void) -{ - /* A wired TLB entry for the GT64240 and the serial port. The - GT64240 is going to be hit on every IRQ anyway - there's - absolutely no point in letting it be a random TLB entry, as - it'll just cause needless churning of the TLB. And we use - the other half for the serial port, which is just a PITA - otherwise :) - - Device Physical Virtual - GT64240 Internal Regs 0xf4000000 0xe0000000 - UARTs (CS2) 0xfd000000 0xe0001000 - */ - add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), - 0xf4000000, PM_64K); - add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000), - 0xfd000000, PM_4K); - - /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM - in the CS[012] region. We can't use ioremap() yet. The NVRAM - is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. - - Ocelot PLD (CS0) 0xfc000000 0xe0020000 - NVRAM (CS1) 0xfc800000 0xe0030000 - */ - add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000), - 0xfc000000, PM_64K); - add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000), - 0xfc800000, PM_64K); - - marvell_base = 0xf4000000; -} - -extern int rm7k_tcache_enabled; - -/* - * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() - */ -#define Page_Invalidate_T 0x16 -static void __init setup_l3cache(unsigned long size) -{ - int register i; - - printk("Enabling L3 cache..."); - - /* Enable the L3 cache in the GT64120A's CPU Configuration register */ - MV_WRITE(0, MV_READ(0) | (1<<14)); - - /* Enable the L3 cache in the CPU */ - set_c0_config(1<<12 /* CONF_TE */); - - /* Clear the cache */ - write_c0_taglo(0); - write_c0_taghi(0); - - for (i=0; i < size; i+= 4096) { - __asm__ __volatile__ ( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (KSEG0ADDR(i)), - "i" (Page_Invalidate_T)); - } - - /* Let the RM7000 MM code know that the tertiary cache is enabled */ - rm7k_tcache_enabled = 1; - - printk("Done\n"); -} - -void __init plat_mem_setup(void) -{ - void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache); - unsigned int tmpword; - - board_time_init = gt64240_time_init; - - _machine_restart = momenco_ocelot_restart; - _machine_halt = momenco_ocelot_halt; - pm_power_off = momenco_ocelot_power_off; - - /* - * initrd_start = (unsigned long)ocelot_initrd_start; - * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; - * initrd_below_start_ok = 1; - */ - - /* do handoff reconfiguration */ - PMON_v2_setup(); - -#ifdef CONFIG_GALILLEO_GT64240_ETH - /* get the mac addr */ - memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6); -#endif - - /* Turn off the Bit-Error LED */ - OCELOT_PLD_WRITE(0x80, INTCLR); - - tmpword = OCELOT_PLD_READ(BOARDREV); - if (tmpword < 26) - printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword); - else - printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword); - - tmpword = OCELOT_PLD_READ(PLD1_ID); - printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_PLD_READ(PLD2_ID); - printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15); - tmpword = OCELOT_PLD_READ(RESET_STATUS); - printk("Reset reason: 0x%x\n", tmpword); - reset_reason = tmpword; - OCELOT_PLD_WRITE(0xff, RESET_STATUS); - - tmpword = OCELOT_PLD_READ(BOARD_STATUS); - printk("Board Status register: 0x%02x\n", tmpword); - printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); - printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); - printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not"); - printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); - printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); - - if (tmpword&12) - l3func((1<<(((tmpword&12) >> 2)+20))); - - switch(tmpword &3) { - case 3: - /* 512MiB -- two banks of 256MiB */ - add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM); -/* - add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM); -*/ - break; - case 2: - /* 256MiB -- two banks of 128MiB */ - add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM); - add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM); - break; - case 1: - /* 128MiB -- 64MiB per bank */ - add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM); - add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); - break; - case 0: - /* 64MiB */ - add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM); - break; - } - - /* FIXME: Fix up the DiskOnChip mapping */ - MV_WRITE(0x468, 0xfef73); -} - -/* This needs to be one of the first initcalls, because no I/O port access - can work before this */ - -static int io_base_ioremap(void) -{ - /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */ - unsigned long io_remap_range; - - io_remap_range = (unsigned long) ioremap(0xc0000000, 0x30000000); - if (!io_remap_range) - panic("Could not ioremap I/O port range"); - - set_io_port_base(io_remap_range - 0xc0000000); - - return 0; -} - -module_init(io_base_ioremap); diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/Makefile mips/arch/mips/pci/Makefile --- mips-orig/arch/mips/pci/Makefile 2006-09-21 01:00:57.764723750 +0900 +++ mips/arch/mips/pci/Makefile 2006-09-21 01:01:14.805265250 +0900 @@ -11,7 +11,6 @@ obj-$(CONFIG_ITE_BOARD_GEN) += ops-it817 obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o -obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o obj-$(CONFIG_MIPS_MSC) += ops-msc.o obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o @@ -34,10 +33,6 @@ obj-$(CONFIG_SOC_AU1500) += fixup-au1000 obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o -obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o -obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o -obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o -obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ pci-yosemite.o obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ocelot-c.c mips/arch/mips/pci/fixup-ocelot-c.c --- mips-orig/arch/mips/pci/fixup-ocelot-c.c 2006-09-21 00:46:01.016056750 +0900 +++ mips/arch/mips/pci/fixup-ocelot-c.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,41 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * Based on work for the Linux port to the Ocelot board, which is - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/momentum/ocelot_g/pci.c - * Board-specific PCI routines for mv64340 controller. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) - return 2; /* PCI-X A */ - if (bus == 1 && slot == 1) - return 12; /* PCI-X B */ - if (bus == 1 && slot == 2) - return 4; /* PCI B */ - -return 0; - panic("Whooops in pcibios_map_irq"); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ocelot-g.c mips/arch/mips/pci/fixup-ocelot-g.c --- mips-orig/arch/mips/pci/fixup-ocelot-g.c 2006-09-21 00:46:01.016056750 +0900 +++ mips/arch/mips/pci/fixup-ocelot-g.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,37 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) - */ -#include -#include -#include -#include - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) /* Intel 82543 Gigabit MAC */ - return 2; /* irq_nr is 2 for INT0 */ - - if (bus == 0 && slot == 2) /* Intel 82543 Gigabit MAC */ - return 3; /* irq_nr is 3 for INT1 */ - - if (bus == 1 && slot == 3) /* Intel 21555 bridge */ - return 5; /* irq_nr is 8 for INT6 */ - - if (bus == 1 && slot == 4) /* PMC Slot */ - return 9; /* irq_nr is 9 for INT7 */ - - return -1; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ocelot.c mips/arch/mips/pci/fixup-ocelot.c --- mips-orig/arch/mips/pci/fixup-ocelot.c 2006-09-21 00:46:01.020057000 +0900 +++ mips/arch/mips/pci/fixup-ocelot.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,75 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/gt64120/momenco_ocelot/pci.c - * Board-specific PCI routines for gt64120 controller. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include - - -void __devinit pcibios_fixup_bus(struct pci_bus *bus) -{ - struct pci_bus *current_bus = bus; - struct pci_dev *devices; - struct list_head *devices_link; - u16 cmd; - - list_for_each(devices_link, &(current_bus->devices)) { - - devices = pci_dev_b(devices_link); - if (devices == NULL) - continue; - - if (PCI_SLOT(devices->devfn) == 1) { - /* - * Slot 1 is primary ether port, i82559 - * we double-check against that assumption - */ - if ((devices->vendor != 0x8086) || - (devices->device != 0x1209)) { - panic("pcibios_fixup_bus: found " - "unexpected PCI device in slot 1."); - } - devices->irq = 2; /* irq_nr is 2 for INT0 */ - } else if (PCI_SLOT(devices->devfn) == 2) { - /* - * Slot 2 is secondary ether port, i21143 - * we double-check against that assumption - */ - if ((devices->vendor != 0x1011) || - (devices->device != 0x19)) { - panic("galileo_pcibios_fixup_bus: " - "found unexpected PCI device in slot 2."); - } - devices->irq = 3; /* irq_nr is 3 for INT1 */ - } else if (PCI_SLOT(devices->devfn) == 4) { - /* PMC Slot 1 */ - devices->irq = 8; /* irq_nr is 8 for INT6 */ - } else if (PCI_SLOT(devices->devfn) == 5) { - /* PMC Slot 1 */ - devices->irq = 9; /* irq_nr is 9 for INT7 */ - } else { - /* We don't have assign interrupts for other devices. */ - devices->irq = 0xff; - } - - /* Assign an interrupt number for the device */ - bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, - devices->irq); - - /* enable master */ - bus->ops->read_word(devices, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_MASTER; - bus->ops->write_word(devices, PCI_COMMAND, cmd); - } -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/fixup-ocelot3.c mips/arch/mips/pci/fixup-ocelot3.c --- mips-orig/arch/mips/pci/fixup-ocelot3.c 2006-09-21 00:46:01.020057000 +0900 +++ mips/arch/mips/pci/fixup-ocelot3.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,41 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 Montavista Software Inc. - * Author: Manish Lachwani (mlachwani@mvista.com) - * - * Looking at the schematics for the Ocelot-3 board, there are - * two PCI busses and each bus has two PCI slots. - */ -#include -#include -#include -#include - -/* - * Do platform specific device initialization at - * pci_enable_device() time - */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) - return 2; /* PCI-X A */ - if (bus == 0 && slot == 2) - return 3; /* PCI-X B */ - if (bus == 1 && slot == 1) - return 4; /* PCI A */ - if (bus == 1 && slot == 2) - return 5; /* PCI B */ - -return 0; - panic("Whooops in pcibios_map_irq"); -} diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/ops-marvell.c mips/arch/mips/pci/ops-marvell.c --- mips-orig/arch/mips/pci/ops-marvell.c 2006-09-21 00:46:01.028057500 +0900 +++ mips/arch/mips/pci/ops-marvell.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,93 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) - */ -#include -#include -#include - -#include - -static int mv_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - struct mv_pci_controller *mvbc = bus->sysdata; - unsigned long address_reg, data_reg; - u32 address; - - address_reg = mvbc->config_addr; - data_reg = mvbc->config_vreg; - - /* Accessing device 31 crashes those Marvells. Since years. - Will they ever make sane controllers ... */ - if (PCI_SLOT(devfn) == 31) - return PCIBIOS_DEVICE_NOT_FOUND; - - address = (bus->number << 16) | (devfn << 8) | - (where & 0xfc) | 0x80000000; - - /* start the configuration cycle */ - MV_WRITE(address_reg, address); - - switch (size) { - case 1: - *val = MV_READ_8(data_reg + (where & 0x3)); - break; - - case 2: - *val = MV_READ_16(data_reg + (where & 0x3)); - break; - - case 4: - *val = MV_READ(data_reg); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int mv_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - struct mv_pci_controller *mvbc = bus->sysdata; - unsigned long address_reg, data_reg; - u32 address; - - address_reg = mvbc->config_addr; - data_reg = mvbc->config_vreg; - - /* Accessing device 31 crashes those Marvells. Since years. - Will they ever make sane controllers ... */ - if (PCI_SLOT(devfn) == 31) - return PCIBIOS_DEVICE_NOT_FOUND; - - address = (bus->number << 16) | (devfn << 8) | - (where & 0xfc) | 0x80000000; - - /* start the configuration cycle */ - MV_WRITE(address_reg, address); - - switch (size) { - case 1: - MV_WRITE_8(data_reg + (where & 0x3), val); - break; - - case 2: - MV_WRITE_16(data_reg + (where & 0x3), val); - break; - - case 4: - MV_WRITE(data_reg, val); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops mv_pci_ops = { - .read = mv_read_config, - .write = mv_write_config -}; diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/pci-ocelot-c.c mips/arch/mips/pci/pci-ocelot-c.c --- mips-orig/arch/mips/pci/pci-ocelot-c.c 2006-09-21 00:46:01.036058000 +0900 +++ mips/arch/mips/pci/pci-ocelot-c.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,145 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004, 06 by Ralf Baechle (ralf@linux-mips.org) - */ - -#include -#include -#include - -#include - -#include - -/* - * We assume the address ranges have already been setup appropriately by - * the firmware. PMON in case of the Ocelot C does that. - */ -static struct resource mv_pci_io_mem0_resource = { - .name = "MV64340 PCI0 IO MEM", - .flags = IORESOURCE_IO -}; - -static struct resource mv_pci_mem0_resource = { - .name = "MV64340 PCI0 MEM", - .flags = IORESOURCE_MEM -}; - -static struct mv_pci_controller mv_bus0_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem0_resource, - .io_resource = &mv_pci_io_mem0_resource, - }, - .config_addr = MV64340_PCI_0_CONFIG_ADDR, - .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, -}; - -static uint32_t mv_io_base, mv_io_size; - -static void mv64340_pci0_init(void) -{ - uint32_t mem0_base, mem0_size; - uint32_t io_base, io_size; - - io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16; - io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16; - mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16; - mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16; - - mv_pci_io_mem0_resource.start = 0; - mv_pci_io_mem0_resource.end = io_size - 1; - mv_pci_mem0_resource.start = mem0_base; - mv_pci_mem0_resource.end = mem0_base + mem0_size - 1; - mv_bus0_controller.pcic.mem_offset = mem0_base; - mv_bus0_controller.pcic.io_offset = 0; - - ioport_resource.end = io_size - 1; - - register_pci_controller(&mv_bus0_controller.pcic); - - mv_io_base = io_base; - mv_io_size = io_size; -} - -static struct resource mv_pci_io_mem1_resource = { - .name = "MV64340 PCI1 IO MEM", - .flags = IORESOURCE_IO -}; - -static struct resource mv_pci_mem1_resource = { - .name = "MV64340 PCI1 MEM", - .flags = IORESOURCE_MEM -}; - -static struct mv_pci_controller mv_bus1_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem1_resource, - .io_resource = &mv_pci_io_mem1_resource, - }, - .config_addr = MV64340_PCI_1_CONFIG_ADDR, - .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, -}; - -static __init void mv64340_pci1_init(void) -{ - uint32_t mem0_base, mem0_size; - uint32_t io_base, io_size; - - io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16; - io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16; - mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16; - mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16; - - /* - * Here we assume the I/O window of second bus to be contiguous with - * the first. A gap is no problem but would waste address space for - * remapping the port space. - */ - mv_pci_io_mem1_resource.start = mv_io_size; - mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1; - mv_pci_mem1_resource.start = mem0_base; - mv_pci_mem1_resource.end = mem0_base + mem0_size - 1; - mv_bus1_controller.pcic.mem_offset = mem0_base; - mv_bus1_controller.pcic.io_offset = 0; - - ioport_resource.end = io_base + io_size -mv_io_base - 1; - - register_pci_controller(&mv_bus1_controller.pcic); - - mv_io_size = io_base + io_size - mv_io_base; -} - -static __init int __init ocelot_c_pci_init(void) -{ - unsigned long io_v_base; - uint32_t enable; - - enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE); - - /* - * We require at least one enabled I/O or PCI memory window or we - * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3. - */ - if (enable & (0x01 << 9) || enable & (0x01 << 10)) - mv64340_pci0_init(); - - if (enable & (0x01 << 14) || enable & (0x01 << 15)) - mv64340_pci1_init(); - - if (mv_io_size) { - io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size); - if (!io_v_base) - panic("Could not ioremap I/O port range"); - - set_io_port_base(io_v_base); - } - - return 0; -} - -arch_initcall(ocelot_c_pci_init); diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/pci-ocelot-g.c mips/arch/mips/pci/pci-ocelot-g.c --- mips-orig/arch/mips/pci/pci-ocelot-g.c 2006-09-21 00:46:01.036058000 +0900 +++ mips/arch/mips/pci/pci-ocelot-g.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,97 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This doesn't really fly - but I don't have a GT64240 system for testing. - */ -#include -#include -#include -#include -#include - -/* - * We assume these address ranges have been programmed into the GT-64240 by - * the firmware. PMON in case of the Ocelot G does that. Note the size of - * the I/O range is completly stupid; I/O mappings are limited to at most - * 256 bytes by the PCI spec and deprecated; and just to make things worse - * apparently many devices don't decode more than 64k of I/O space. - */ - -#define gt_io_size 0x20000000UL -#define gt_io_base 0xe0000000UL - -static struct resource gt_pci_mem0_resource = { - .name = "MV64240 PCI0 MEM", - .start = 0xc0000000UL, - .end = 0xcfffffffUL, - .flags = IORESOURCE_MEM -}; - -static struct resource gt_pci_io_mem0_resource = { - .name = "MV64240 PCI0 IO MEM", - .start = 0xe0000000UL, - .end = 0xefffffffUL, - .flags = IORESOURCE_IO -}; - -static struct mv_pci_controller gt_bus0_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = >_pci_mem0_resource, - .mem_offset = 0xc0000000UL, - .io_resource = >_pci_io_mem0_resource, - .io_offset = 0x00000000UL - }, - .config_addr = PCI_0CONFIGURATION_ADDRESS, - .config_vreg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, -}; - -static struct resource gt_pci_mem1_resource = { - .name = "MV64240 PCI1 MEM", - .start = 0xd0000000UL, - .end = 0xdfffffffUL, - .flags = IORESOURCE_MEM -}; - -static struct resource gt_pci_io_mem1_resource = { - .name = "MV64240 PCI1 IO MEM", - .start = 0xf0000000UL, - .end = 0xffffffffUL, - .flags = IORESOURCE_IO -}; - -static struct mv_pci_controller gt_bus1_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = >_pci_mem1_resource, - .mem_offset = 0xd0000000UL, - .io_resource = >_pci_io_mem1_resource, - .io_offset = 0x10000000UL - }, - .config_addr = PCI_1CONFIGURATION_ADDRESS, - .config_vreg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, -}; - -static __init int __init ocelot_g_pci_init(void) -{ - unsigned long io_v_base; - - if (gt_io_size) { - io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size); - if (!io_v_base) - panic("Could not ioremap I/O port range"); - - set_io_port_base(io_v_base); - } - - register_pci_controller(>_bus0_controller.pcic); - register_pci_controller(>_bus1_controller.pcic); - - return 0; -} - -arch_initcall(ocelot_g_pci_init); diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/pci-ocelot.c mips/arch/mips/pci/pci-ocelot.c --- mips-orig/arch/mips/pci/pci-ocelot.c 2006-09-21 00:46:01.036058000 +0900 +++ mips/arch/mips/pci/pci-ocelot.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,107 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Galileo Evaluation Boards PCI support. - * - * The general-purpose functions to read/write and configure the GT64120A's - * PCI registers (function names start with pci0 or pci1) are either direct - * copies of functions written by Galileo Technology, or are modifications - * of their functions to work with Linux 2.4 vs Linux 2.2. These functions - * are Copyright - Galileo Technology. - * - * Other functions are derived from other MIPS PCI implementations, or were - * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static inline unsigned int pci0ReadConfigReg(unsigned int offset) -{ - unsigned int DataForRegCf8; - unsigned int data; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - GT_READ(GT_PCI0_CFGDATA_OFS, &data); - - return data; -} - -static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data) -{ - unsigned int DataForRegCf8; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - GT_WRITE(GT_PCI0_CFGDATA_OFS, data); -} - -static struct resource ocelot_mem_resource = { - start = GT_PCI_MEM_BASE; - end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1; -}; - -static struct resource ocelot_io_resource = { - start = GT_PCI_IO_BASE; - end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; -}; - -static struct pci_controller ocelot_pci_controller = { - .pci_ops = gt64120_pci_ops; - .mem_resource = &ocelot_mem_resource; - .io_resource = &ocelot_io_resource; -}; - -static int __init ocelot_pcibios_init(void) -{ - u32 tmp; - - GT_READ(GT_PCI0_CMD_OFS, &tmp); - GT_READ(GT_PCI0_BARE_OFS, &tmp); - - /* - * You have to enable bus mastering to configure any other - * card on the bus. - */ - tmp = pci0ReadConfigReg(PCI_COMMAND); - tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - pci0WriteConfigReg(PCI_COMMAND, tmp); - - register_pci_controller(&ocelot_pci_controller); -} - -arch_initcall(ocelot_pcibios_init); diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/mtd/devices/docprobe.c mips/drivers/mtd/devices/docprobe.c --- mips-orig/drivers/mtd/devices/docprobe.c 2006-09-21 00:46:08.044496000 +0900 +++ mips/drivers/mtd/devices/docprobe.c 2006-09-21 01:02:49.999599500 +0900 @@ -81,11 +81,6 @@ static unsigned long __initdata doc_loca #endif /* CONFIG_MTD_DOCPROBE_HIGH */ #elif defined(__PPC__) 0xe4000000, -#elif defined(CONFIG_MOMENCO_OCELOT) - 0x2f000000, - 0xff000000, -#elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C) - 0xff000000, #else #warning Unknown architecture for DiskOnChip. No default probe locations defined #endif diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/mtd/maps/Kconfig mips/drivers/mtd/maps/Kconfig --- mips-orig/drivers/mtd/maps/Kconfig 2006-09-21 00:46:08.052496500 +0900 +++ mips/drivers/mtd/maps/Kconfig 2006-09-21 01:03:16.052196500 +0900 @@ -411,14 +411,6 @@ config MTD_CSTM_MIPS_IXX_BUSWIDTH This is the total bus width of the mapping of the flash chips on your particular board. -config MTD_OCELOT - tristate "Momenco Ocelot boot flash device" - depends on MIPS && MOMENCO_OCELOT - help - This enables access routines for the boot flash device and for the - NVRAM on the Momenco Ocelot board. If you have one of these boards - and would like access to either of these, say 'Y'. - config MTD_SOLUTIONENGINE tristate "CFI Flash device mapped on Hitachi SolutionEngine" depends on SUPERH && MTD_CFI && MTD_REDBOOT_PARTS diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/mtd/maps/Makefile mips/drivers/mtd/maps/Makefile --- mips-orig/drivers/mtd/maps/Makefile 2006-09-21 00:46:08.052496500 +0900 +++ mips/drivers/mtd/maps/Makefile 2006-09-21 01:03:27.871023500 +0900 @@ -40,7 +40,6 @@ obj-$(CONFIG_MTD_SUN_UFLASH) += sun_ufla obj-$(CONFIG_MTD_VMAX) += vmax301.o obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx200_docflash.o obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o -obj-$(CONFIG_MTD_OCELOT) += ocelot.o obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o obj-$(CONFIG_MTD_PCI) += pci.o obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/mtd/maps/ocelot.c mips/drivers/mtd/maps/ocelot.c --- mips-orig/drivers/mtd/maps/ocelot.c 2006-09-21 00:46:08.060497000 +0900 +++ mips/drivers/mtd/maps/ocelot.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,175 +0,0 @@ -/* - * $Id: ocelot.c,v 1.17 2005/11/07 11:14:27 gleixner Exp $ - * - * Flash on Momenco Ocelot - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define OCELOT_PLD 0x2c000000 -#define FLASH_WINDOW_ADDR 0x2fc00000 -#define FLASH_WINDOW_SIZE 0x00080000 -#define FLASH_BUSWIDTH 1 -#define NVRAM_WINDOW_ADDR 0x2c800000 -#define NVRAM_WINDOW_SIZE 0x00007FF0 -#define NVRAM_BUSWIDTH 1 - -static unsigned int cacheflush = 0; - -static struct mtd_info *flash_mtd; -static struct mtd_info *nvram_mtd; - -static void ocelot_ram_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) -{ - struct map_info *map = mtd->priv; - size_t done = 0; - - /* If we use memcpy, it does word-wide writes. Even though we told the - GT64120A that it's an 8-bit wide region, word-wide writes don't work. - We end up just writing the first byte of the four to all four bytes. - So we have this loop instead */ - *retlen = len; - while(len) { - __raw_writeb(*(unsigned char *) from, map->virt + to); - from++; - to++; - len--; - } -} - -static struct mtd_partition *parsed_parts; - -struct map_info ocelot_flash_map = { - .name = "Ocelot boot flash", - .size = FLASH_WINDOW_SIZE, - .bankwidth = FLASH_BUSWIDTH, - .phys = FLASH_WINDOW_ADDR, -}; - -struct map_info ocelot_nvram_map = { - .name = "Ocelot NVRAM", - .size = NVRAM_WINDOW_SIZE, - .bankwidth = NVRAM_BUSWIDTH, - .phys = NVRAM_WINDOW_ADDR, -}; - -static const char *probes[] = { "RedBoot", NULL }; - -static int __init init_ocelot_maps(void) -{ - void *pld; - int nr_parts; - unsigned char brd_status; - - printk(KERN_INFO "Momenco Ocelot MTD mappings: Flash 0x%x at 0x%x, NVRAM 0x%x at 0x%x\n", - FLASH_WINDOW_SIZE, FLASH_WINDOW_ADDR, NVRAM_WINDOW_SIZE, NVRAM_WINDOW_ADDR); - - /* First check whether the flash jumper is present */ - pld = ioremap(OCELOT_PLD, 0x10); - if (!pld) { - printk(KERN_NOTICE "Failed to ioremap Ocelot PLD\n"); - return -EIO; - } - brd_status = readb(pld+4); - iounmap(pld); - - /* Now ioremap the NVRAM space */ - ocelot_nvram_map.virt = ioremap_nocache(NVRAM_WINDOW_ADDR, NVRAM_WINDOW_SIZE); - if (!ocelot_nvram_map.virt) { - printk(KERN_NOTICE "Failed to ioremap Ocelot NVRAM space\n"); - return -EIO; - } - - simple_map_init(&ocelot_nvram_map); - - /* And do the RAM probe on it to get an MTD device */ - nvram_mtd = do_map_probe("map_ram", &ocelot_nvram_map); - if (!nvram_mtd) { - printk("NVRAM probe failed\n"); - goto fail_1; - } - nvram_mtd->owner = THIS_MODULE; - nvram_mtd->erasesize = 16; - /* Override the write() method */ - nvram_mtd->write = ocelot_ram_write; - - /* Now map the flash space */ - ocelot_flash_map.virt = ioremap_nocache(FLASH_WINDOW_ADDR, FLASH_WINDOW_SIZE); - if (!ocelot_flash_map.virt) { - printk(KERN_NOTICE "Failed to ioremap Ocelot flash space\n"); - goto fail_2; - } - /* Now the cached version */ - ocelot_flash_map.cached = (unsigned long)__ioremap(FLASH_WINDOW_ADDR, FLASH_WINDOW_SIZE, 0); - - simple_map_init(&ocelot_flash_map); - - /* Only probe for flash if the write jumper is present */ - if (brd_status & 0x40) { - flash_mtd = do_map_probe("jedec", &ocelot_flash_map); - } else { - printk(KERN_NOTICE "Ocelot flash write jumper not present. Treating as ROM\n"); - } - /* If that failed or the jumper's absent, pretend it's ROM */ - if (!flash_mtd) { - flash_mtd = do_map_probe("map_rom", &ocelot_flash_map); - /* If we're treating it as ROM, set the erase size */ - if (flash_mtd) - flash_mtd->erasesize = 0x10000; - } - if (!flash_mtd) - goto fail3; - - add_mtd_device(nvram_mtd); - - flash_mtd->owner = THIS_MODULE; - nr_parts = parse_mtd_partitions(flash_mtd, probes, &parsed_parts, 0); - - if (nr_parts > 0) - add_mtd_partitions(flash_mtd, parsed_parts, nr_parts); - else - add_mtd_device(flash_mtd); - - return 0; - - fail3: - iounmap((void *)ocelot_flash_map.virt); - if (ocelot_flash_map.cached) - iounmap((void *)ocelot_flash_map.cached); - fail_2: - map_destroy(nvram_mtd); - fail_1: - iounmap((void *)ocelot_nvram_map.virt); - - return -ENXIO; -} - -static void __exit cleanup_ocelot_maps(void) -{ - del_mtd_device(nvram_mtd); - map_destroy(nvram_mtd); - iounmap((void *)ocelot_nvram_map.virt); - - if (parsed_parts) - del_mtd_partitions(flash_mtd); - else - del_mtd_device(flash_mtd); - map_destroy(flash_mtd); - iounmap((void *)ocelot_flash_map.virt); - if (ocelot_flash_map.cached) - iounmap((void *)ocelot_flash_map.cached); -} - -module_init(init_ocelot_maps); -module_exit(cleanup_ocelot_maps); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Red Hat, Inc. - David Woodhouse "); -MODULE_DESCRIPTION("MTD map driver for Momenco Ocelot board"); diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/mtd/nand/diskonchip.c mips/drivers/mtd/nand/diskonchip.c --- mips-orig/drivers/mtd/nand/diskonchip.c 2006-09-21 00:46:08.072497750 +0900 +++ mips/drivers/mtd/nand/diskonchip.c 2006-09-21 01:03:57.162203000 +0900 @@ -56,11 +56,6 @@ static unsigned long __initdata doc_loca #endif /* CONFIG_MTD_DOCPROBE_HIGH */ #elif defined(__PPC__) 0xe4000000, -#elif defined(CONFIG_MOMENCO_OCELOT) - 0x2f000000, - 0xff000000, -#elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C) - 0xff000000, #else #warning Unknown architecture for DiskOnChip. No default probe locations defined #endif diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/net/Kconfig mips/drivers/net/Kconfig --- mips-orig/drivers/net/Kconfig 2006-09-21 01:00:57.768722000 +0900 +++ mips/drivers/net/Kconfig 2006-09-21 01:05:11.097842000 +0900 @@ -438,14 +438,6 @@ config MIPS_JAZZ_SONIC This is the driver for the onboard card of MIPS Magnum 4000, Acer PICA, Olivetti M700-10 and a few other identical OEM systems. -config GALILEO_64240_ETH - tristate "Galileo GT64240 Ethernet support" - depends on NET_ETHERNET && MOMENCO_OCELOT_G - select MII - help - This is the driver for the ethernet interfaces integrated into - the Galileo (now Marvell) GT64240 chipset. - config MIPS_AU1X00_ENET bool "MIPS AU1000 Ethernet support" depends on NET_ETHERNET && SOC_AU1X00 @@ -2252,7 +2244,7 @@ config UGETH_HAS_GIGA config MV643XX_ETH tristate "MV-643XX Ethernet support" - depends on MOMENCO_OCELOT_C || MV64360 || MOMENCO_OCELOT_3 || PPC_MULTIPLATFORM + depends on MV64360 || PPC_MULTIPLATFORM select MII help This driver supports the gigabit Ethernet on the Marvell MV643XX diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/net/Makefile mips/drivers/net/Makefile --- mips-orig/drivers/net/Makefile 2006-09-21 00:57:25.818854250 +0900 +++ mips/drivers/net/Makefile 2006-09-21 01:05:26.866940000 +0900 @@ -114,7 +114,6 @@ obj-$(CONFIG_NE_H8300) += ne-h8300.o 839 obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o -obj-$(CONFIG_GALILEO_64240_ETH) += gt64240eth.o obj-$(CONFIG_MV64340_ETH) += mv64340_eth.o obj-$(CONFIG_BIG_SUR_FE) += big_sur_ge.o obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o diff -pruN -X mips/Documentation/dontdiff mips-orig/drivers/net/gt64240eth.c mips/drivers/net/gt64240eth.c --- mips-orig/drivers/net/gt64240eth.c 2006-09-21 00:46:08.328513750 +0900 +++ mips/drivers/net/gt64240eth.c 1970-01-01 09:00:00.000000000 +0900 @@ -1,1672 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001 Patton Electronics Company - * Copyright (C) 2002 Momentum Computer - * - * Copyright 2000 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * stevel@mvista.com or support@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Ethernet driver for the MIPS GT96100 Advanced Communication Controller. - * - * Modified for the Gallileo/Marvell GT-64240 Communication Controller. - * - * Support for Rx NAPI, Rx checksum offload, IOCTL and ETHTOOL added - * Manish Lachwani (lachwani@pmc-sierra.com) - 09/16/2003 - * - * Modified for later version of Linux 2.4 kernel - * Manish Lachwani (lachwani@pmc-sierra.com) - 04/29/2004 - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define DESC_DATA_BE 1 - -#include "gt64240eth.h" - -// enable this port (set hash size to 1/2K) -//- #define PORT_CONFIG pcrHS -#define PORT_CONFIG (pcrHS | pcrHD) -//- #define PORT_CONFIG pcrHS |pcrPM |pcrPBF|pcrHDM -//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS); -//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM); -//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM | 1< 2 some warnings such as queue full, ..... - * > 3 lots of change-of-state messages. - * > 4 EXTENSIVE data/descriptor dumps. - */ - -#ifdef GT64240_DEBUG -static int gt64240_debug = GT64240_DEBUG; -#else -static int gt64240_debug = 0; -#endif - -static int debug = -1; - -#define GT64240_MSG_ENABLE (NETIF_MSG_DRV | \ - NETIF_MSG_PROBE | \ - NETIF_MSG_LINK) - - -/********************************************************/ - -// prototypes -static void gt64240_delay(int msec); -static int gt64240_add_hash_entry(struct net_device *dev, - unsigned char *addr); -static void read_mib_counters(struct gt64240_private *gp); -static void dump_MII(struct net_device *dev); -static void dump_tx_desc(struct net_device *dev, int i); -static void dump_rx_desc(struct net_device *dev, int i); -static void dump_hw_addr(unsigned char *addr_str); -static void update_stats(struct gt64240_private *gp); -static void abort(struct net_device *dev, u32 abort_bits); -static void hard_stop(struct net_device *dev); -static void enable_ether_irq(struct net_device *dev); -static void disable_ether_irq(struct net_device *dev); -static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num); -static void reset_tx(struct net_device *dev); -static void reset_rx(struct net_device *dev); -static int gt64240_init(struct net_device *dev); -static int gt64240_open(struct net_device *dev); -static int gt64240_close(struct net_device *dev); -static int gt64240_tx(struct sk_buff *skb, struct net_device *dev); -#ifdef GT64240_NAPI -static int gt64240_poll(struct net_device *dev, int *budget); -static int gt64240_rx(struct net_device *dev, u32 status, int budget); -#else -static int gt64240_rx(struct net_device *dev, u32 status); -#endif -static void gt64240_tx_timeout(struct net_device *dev); -static void gt64240_set_rx_mode(struct net_device *dev); -static struct net_device_stats *gt64240_get_stats(struct net_device *dev); - -extern char *__init prom_getcmdline(void); -extern int prom_get_mac_addrs(unsigned char - station_addr[NUM_INTERFACES][6]); - -static char version[] __devinitdata = - "gt64240eth.o: version 0.1, \n"; - -// PHY device addresses -static u32 gt64240_phy_addr[NUM_INTERFACES] __devinitdata = { 0x8, 0x1, 0xa }; - -// Need real Ethernet addresses -- in parse_mac_addr_options(), -// these will be replaced by prom_get_mac_addrs() and/or prom_getcmdline(). -static unsigned char gt64240_station_addr[NUM_INTERFACES][6] = { - {0x00, 0x01, 0x02, 0x03, 0x04, 0x05}, - {0x01, 0x02, 0x03, 0x04, 0x05, 0x06}, - {0x02, 0x03, 0x04, 0x05, 0x06, 0x07} -}; - -static int max_interrupt_work = 32; - -/* - * Base address and interupt of the GT64240 ethernet controllers - */ -static struct { - unsigned int port; - int irq; -} gt64240_iflist[NUM_INTERFACES] = { - { - GT64240_ETH0_BASE, 8}, { - GT64240_ETH1_BASE, 8}, { - GT64240_ETH2_BASE, 8} -}; - -static void gt64240_delay(int ms) -{ - if (in_interrupt()) - return; - else { - current->state = TASK_INTERRUPTIBLE; - schedule_timeout(ms * HZ / 1000); - } -} - -unsigned char prom_mac_addr_base[6]; - -int prom_get_mac_addrs(unsigned char station_addr[NUM_INTERFACES][6]) -{ - memcpy(station_addr[0], prom_mac_addr_base, 6); - memcpy(station_addr[1], prom_mac_addr_base, 6); - memcpy(station_addr[2], prom_mac_addr_base, 6); - - station_addr[1][5] += 1; - station_addr[2][5] += 2; - - return 0; -} - -void parse_mac_addr_options(void) -{ - prom_get_mac_addrs(gt64240_station_addr); -} - -static int read_MII(struct net_device *dev, int phy, int reg) -{ - int timedout = 20; - u32 smir = smirOpCode | (phy << smirPhyAdBit) | - (reg << smirRegAdBit); - - // wait for last operation to complete - while ((GT64240_READ(GT64240_ETH_SMI_REG)) & smirBusy) { - // snooze for 1 msec and check again - gt64240_delay(1); - - if (--timedout == 0) { - printk("%s: read_MII busy timeout!!\n", dev->name); - return -1; - } - } - - GT64240_WRITE(GT64240_ETH_SMI_REG, smir); - - timedout = 20; - // wait for read to complete - while (! -