From tbm@cyrius.com Wed Mar 1 01:39:49 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 01:40:07 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:15878 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133654AbWCABjt (ORCPT ); Wed, 1 Mar 2006 01:39:49 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 7309D64D3D; Wed, 1 Mar 2006 01:47:31 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id F26EB81F5; Wed, 1 Mar 2006 02:47:23 +0100 (CET) Date: Wed, 1 Mar 2006 01:47:23 +0000 From: Martin Michlmayr To: Mark E Mason Cc: linux-mips@linux-mips.org Subject: [PATCH] Offer Sibyte IDE driver only on platforms that have IDE Message-ID: <20060301014723.GA16315@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10688 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Mark, can you ack this patch? [PATCH] Offer Sibyte IDE driver only on platforms that have IDE Currently Kconfig allows you to select the Sibyte IDE driver on any SB1 based SOC platform. However, not all of them actually have IDE. Nor do they import the correct files needed to compile the Sibyte (SWARM) IDE driver, leading to the compilation failure below on a SB1A 1480 board. The situation can be improved by adding a SIBYTE_HAS_IDE Kconfig variable and change the dependency of the Sibyte IDE driver accordingly. CC drivers/ide/mips/swarm.o drivers/ide/mips/swarm.c: In function ‘swarm_ide_probe’: drivers/ide/mips/swarm.c:95: error: ‘A_PHYS_GENBUS’ undeclared (first use in this function) drivers/ide/mips/swarm.c:95: error: (Each undeclared identifier is reported only once drivers/ide/mips/swarm.c:95: error: for each function it appears in.) drivers/ide/mips/swarm.c:95: error: ‘A_PHYS_GENBUS_END’ undeclared (first use in this function) drivers/ide/mips/swarm.c:125: error: ‘K_INT_GPIO_0’ undeclared (first use in this function) Signed-off-by: Martin Michlmayr --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -619,6 +619,8 @@ config SIBYTE_SWARM select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN + select SIBYTE_HAS_IDE + select SIBYTE_HAS_PCMCIA config SIBYTE_SENTOSA bool "Support for Sibyte BCM91250E-Sentosa" @@ -664,6 +666,8 @@ config SIBYTE_PTSWARM select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN + select SIBYTE_HAS_IDE + select SIBYTE_HAS_PCMCIA config SIBYTE_LITTLESUR bool "Support for Sibyte BCM91250C2-LittleSur" @@ -676,6 +680,7 @@ config SIBYTE_LITTLESUR select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN + select SIBYTE_HAS_IDE config SIBYTE_CRHINE bool "Support for Sibyte BCM91120C-CRhine" diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index 816aee7..12712ef 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -95,6 +95,14 @@ config SIBYTE_HAS_LDT depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H) default y +config SIBYTE_HAS_IDE + bool + default n + +config SIBYTE_HAS_PCMCIA + bool + default n + config SIMULATION bool "Running under simulation" depends on SIBYTE_SB1xxx_SOC diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig index d633081..91514c5 100644 --- a/drivers/ide/Kconfig +++ b/drivers/ide/Kconfig @@ -782,7 +782,7 @@ config BLK_DEV_IDE_PMAC_BLINK config BLK_DEV_IDE_SWARM tristate "IDE for Sibyte evaluation boards" - depends on SIBYTE_SB1xxx_SOC + depends on SIBYTE_HAS_IDE config BLK_DEV_IDE_AU1XXX bool "IDE for AMD Alchemy Au1200" diff --git a/drivers/ide/mips/swarm.c b/drivers/ide/mips/swarm.c index 66f6064..55f77fc 100644 --- a/drivers/ide/mips/swarm.c +++ b/drivers/ide/mips/swarm.c @@ -33,8 +33,7 @@ * other PCI devices, for example, will require swapping). Any * SiByte-targetted kernel including IDE support will include this * file. Probing of a Generic Bus for an IDE device is controlled by - * the definition of "SIBYTE_HAVE_IDE", which is provided by - * for Broadcom boards. + * the definition of "SIBYTE_HAS_IDE". */ #include @@ -71,9 +70,6 @@ static int __devinit swarm_ide_probe(str phys_t offset, size; int i; - if (!SIBYTE_HAVE_IDE) - return -ENODEV; - /* Find an empty slot. */ for (i = 0; i < MAX_HWIFS; i++) if (!ide_hwifs[i].io_ports[IDE_DATA_OFFSET]) diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h index 06e1d52..a560c4c 100644 --- a/include/asm-mips/sibyte/swarm.h +++ b/include/asm-mips/sibyte/swarm.h @@ -24,44 +24,34 @@ #ifdef CONFIG_SIBYTE_SWARM #define SIBYTE_BOARD_NAME "BCM91250A (SWARM)" -#define SIBYTE_HAVE_PCMCIA 1 -#define SIBYTE_HAVE_IDE 1 #endif #ifdef CONFIG_SIBYTE_PTSWARM #define SIBYTE_BOARD_NAME "PTSWARM" -#define SIBYTE_HAVE_PCMCIA 1 -#define SIBYTE_HAVE_IDE 1 #define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200" #endif #ifdef CONFIG_SIBYTE_LITTLESUR #define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)" -#define SIBYTE_HAVE_PCMCIA 0 -#define SIBYTE_HAVE_IDE 1 #define SIBYTE_DEFAULT_CONSOLE "cfe0" #endif #ifdef CONFIG_SIBYTE_CRHONE #define SIBYTE_BOARD_NAME "BCM91125C (CRhone)" -#define SIBYTE_HAVE_PCMCIA 0 -#define SIBYTE_HAVE_IDE 0 #endif #ifdef CONFIG_SIBYTE_CRHINE #define SIBYTE_BOARD_NAME "BCM91120C (CRhine)" -#define SIBYTE_HAVE_PCMCIA 0 -#define SIBYTE_HAVE_IDE 0 #endif /* Generic bus chip selects */ #define LEDS_CS 3 #define LEDS_PHYS 0x100a0000 -#ifdef SIBYTE_HAVE_IDE +#ifdef CONFIG_SIBYTE_HAS_IDE #define IDE_CS 4 #define IDE_PHYS 0x100b0000 #define K_GPIO_GB_IDE 4 #define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) #endif -#ifdef SIBYTE_HAVE_PCMCIA +#ifdef CONFIG_SIBYTE_HAS_PCMCIA #define PCMCIA_CS 6 #define PCMCIA_PHYS 0x11000000 #define K_GPIO_PC_READY 9 -- Martin Michlmayr http://www.cyrius.com/ From tbm@cyrius.com Wed Mar 1 01:47:28 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 01:47:36 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:18182 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133654AbWCABr2 (ORCPT ); Wed, 1 Mar 2006 01:47:28 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 19BB964D3D; Wed, 1 Mar 2006 01:55:14 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 1B7AE81F5; Wed, 1 Mar 2006 02:55:06 +0100 (CET) Date: Wed, 1 Mar 2006 01:55:05 +0000 From: Martin Michlmayr To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: [PATCH] Mention Broadcom part number for BigSur board Message-ID: <20060301015505.GA16567@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10689 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips [PATCH] Mention Broadcom part number for BigSur board Mention the Broadcom part number for the BigSur board (BCM91480B) in Kconfig, just like it's done for other Broadcom boards. Signed-off-by: Martin Michlmayr --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -599,7 +599,7 @@ config SGI_IP32 If you want this kernel to run on SGI O2 workstation, say Y here. config SIBYTE_BIGSUR - bool "Support for Sibyte BigSur" + bool "Support for Sibyte BCM91480B-BigSur" select BOOT_ELF32 select DMA_COHERENT select PCI_DOMAINS -- Martin Michlmayr http://www.cyrius.com/ From tbm@cyrius.com Wed Mar 1 01:57:24 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 01:57:35 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:28422 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133658AbWCAB5Y (ORCPT ); Wed, 1 Mar 2006 01:57:24 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 5C09F64D3D; Wed, 1 Mar 2006 02:05:09 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 153A381F5; Wed, 1 Mar 2006 03:04:38 +0100 (CET) Date: Wed, 1 Mar 2006 02:04:38 +0000 From: Martin Michlmayr To: linux-mips@linux-mips.org Subject: Re: Non-fatal oops on SGI IP22 when doing: md5sum /dev/mem Message-ID: <20060301020438.GA22131@deprecation.cyrius.com> References: <20060228114137.GA3087@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060228114137.GA3087@deprecation.cyrius.com> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10690 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips * Martin Michlmayr [2006-02-28 11:41]: > I get the following non-fatal oops on SGI IP22 (2.6.16-rc5) when > running "md5sum /dev/mem". I know it's not very smart to run this > command but nevertheless we shouldn't oops. FWIW, i386 reports > "md5sum: /dev/mem: Bad address". Right, so we had a fun discussion about this on IRC today... The bottom line is that the kernel cannot to anything about it and root should know what they're doing. 12:39 < ladis> tbm: you cannot read from /dev/mem randomly ;-) 12:46 < tbm> ladis: yeah, but my point is that it shouldn't oops/segfault 12:48 < ladis> tbm: Well, you acessed GIO space and MC asserted BERR interrupt. That's pretty valid behaviour. 12:50 < tbm> ladis: a oops and segfault doesn't seem like valid behaviour from the perspective of an end user. Why cannot it catch such an access and return "Bad address" like i386 does 12:51 < p2-mate> tbm: if you do hw access in userland, you're on your own :) 12:53 < tbm> p2-mate: I still maintain that an oops is not an acceptable behaviour from a user POV 12:56 < Bacchus> tbm: I'm missing some context here - what is oopsing? 12:57 < p2-mate> tbm: rm /dev/mem 12:57 < p2-mate> tbm: problem solved :) 12:57 < tbm> p2-mate: so why does /dev/mem exist in the first place... 12:57 < tbm> Bacchus: print a traceback 12:57 < p2-mate> tbm: otherwise the X server does not work 12:58 < Bacchus> tbm: Doesn't work very well but I've never seen a traceback oopsing. 12:59 < tbm> well, isn't this thing called an oops? Or what's the right terminiology? 12:59 < tbm> Data bus error, epc == ffffffff881b0cf0, ra == ffffffff881c9ab4 12:59 < tbm> Oops[#8]: 12:59 < tbm> Cpu 0 12:59 < tbm> $ 0 : 0000000000000000 0000000000000004 ffffffff80090000 0000000000000000 12:59 < tbm> $ 4 : 00000000100023a8 ffffffff80090000 0000000000001000 ffffffff8a6dfe88 12:59 < tbm> .. 12:59 < tbm> Call Trace: 12:59 < tbm> [] vfs_read+0xfc/0x1b8 12:59 < tbm> .. 12:59 < ladis> p2-mate: That's problem of bloody crappy random number generator in xdm 12:59 < ladis> tbm: Right, it is Data bus error and I implemented it ;-) 12:59 < tbm> p2-mate: right, but my point is that the file is there and so it can be expected that some users try to read it 13:00 < Bacchus> Okay - and a DBE when doing what? 13:00 < tbm> so either we shouldn't ship the file, or we should handle reading from it gracefully 13:00 < p2-mate> tbm: well, perhapd it should not be there ? 13:00 < ladis> tbm: There was long debate about acesing /dev/mem on debian-mips archive few years ago 13:00 < tbm> Bacchus: doing "md5sum /dev/mem" 13:00 < ladis> tbm: search for xdm 13:00 < p2-mate> BERR is imprecise ? 13:00 < Bacchus> tbm: You're kidding? 13:00 < tbm> Bacchus: which may be a stupid thing, but still shouldn't oops and segfault 13:00 < ladis> tbm: It *will* always segfault on certain machines 13:01 < tbm> so why does i386 manage to produce a nice "Bad address" error? 13:01 < tbm> why is that not possible on mips? 13:01 < Bacchus> tbm: FOr this operation even formatting your hard disk would be ok. 13:01 < geoman> heh, I can confirm the oops on 2.6.16-rc4 13:01 < ladis> aiiie ;-) 13:01 < tbm> Bacchus: well, that's what i disagree with. If /dev/mem is so dangerous, it shouldn't exist. 13:02 < Bacchus> Welcome to UNIX :) 13:02 < ladis> tbm: No. It is very powerfull. And only root can cope with that... 13:02 < ladis> tbm: Remember userspace drivers 13:03 < geoman> hmm, speaking of display managers and oopses 13:03 < Bacchus> tbm: /dev/mem gives free access to any and all devices in the system just like the kernel. No safety net. 13:03 < ladis> tbm: And even removing /dev/mem doesn't prevent you from writing program that does mmap 13:03 < geoman> I seem to recall that wdm causes a non-fatal oops on ip22 13:04 < geoman> perhaps it is related 13:04 < ladis> geoman: sure it is 13:05 < ladis> display managers authors are insane i386 centric idiots thinking that reading enough /dev/mem gives you enough randomness for security purposes 13:05 < ladis> I never got this point... 13:05 < Bacchus> tbm: And yes, there are many that argue that /dev/mem should be deprecated. 13:11 < geoman> yep, wdm causes an identical oops 13:12 < tbm> ok, at least my O2 boots again 13:13 < tbm> anyway, I do agree with you that /dev/mem is dangerous and that root should know what they're doing 13:13 < tbm> however, the tiny bit I don't understand is that if the kernel manages to recognize this wrong access and issue a BERR, why cannot it simply return an error to the userland program 13:13 < tbm> but anyway, I guess there are more important things to worry about 13:14 < geoman> well, my understanding is that the kernel should never oops 13:15 < Bacchus> tbm: By the time we receive a bus error we're dead in the water. Game over. Tilt. Insert coin to continue ;-) 13:18 < geoman> heh, doing "md5sum /dev/mem" on my O2 doesn't return any error at all 13:18 < geoman> I think it is really trying to take the md5sum of all that random crud ;) 13:19 < Bacchus> A bus error just doesn't have enough knowledge about what went wrong, aside of a few carefully controlled scenarios like hw probing. ... 13:37 < Bacchus> geoman: So how does wdm trigger it? 13:38 < ladis> Bacchus: Read above 13:38 < ladis> Bacchus: display managers authors are insane i386 centric idiots thinking that reading enough /dev/mem gives you enough randomness for security purposes 13:39 < Bacchus> ladis: Eh... You meant you were serious?!? 13:39 < ladis> Bacchus: They are indeed doing that. 13:39 < ths> Bacchus: Sure. Wdm dies on my Indy. 13:39 < geoman> Bacchus: by simply tring to start it 13:39 < ladis> ...and the reason is above.. 13:48 * Bacchus googles for wdm ... 13:50 < Bacchus> Btw, wtf does wdm work for non-root then? 13:50 < geoman> nope 13:51 < geoman> if you try to run it non-root, it returns a message that "Only root wants to run wdm" 13:55 < ladis> Bacchus: http://lists.debian.org/debian-mips/2002/08/msg00060.html 13:55 < ladis> Bacchus: That's start of pretty nice discussion. Read on your own risc ;-) -- Martin Michlmayr http://www.cyrius.com/ From anemo@mba.ocn.ne.jp Wed Mar 1 05:37:00 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 05:37:09 +0000 (GMT) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:34642 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S8133385AbWCAFhA (ORCPT ); Wed, 1 Mar 2006 05:37:00 +0000 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Wed, 1 Mar 2006 14:44:47 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id CE3E8204EB; Wed, 1 Mar 2006 14:44:43 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id C1E68203B7; Wed, 1 Mar 2006 14:44:43 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k215ig4D052035; Wed, 1 Mar 2006 14:44:42 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Wed, 01 Mar 2006 14:44:42 +0900 (JST) Message-Id: <20060301.144442.118975101.nemoto@toshiba-tops.co.jp> To: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Subject: jiffies_64 vs. jiffies From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10691 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Hi. I noticed that the 'jiffies' variable has 'wall_jiffies + 1' value in most of time. I'm using MIPS platform but I think this is same for other platforms. I suppose this is due to gcc does not know that jiffies_64 and jiffies share same place. In kernel/timer.c: static inline void update_times(void) { unsigned long ticks; ticks = jiffies - wall_jiffies; if (ticks) { wall_jiffies += ticks; update_wall_time(ticks); } calc_load(ticks); } void do_timer(struct pt_regs *regs) { jiffies_64++; update_times(); softlockup_tick(regs); } This is compiled MIPS code (gcc 3.4.5): 80056db4 : ... 80056de0: lui a3,0x8033 80056de4: lw v0,21400(a3) # load jiffies_64(lo) 80056de8: lui a1,0x8033 80056dec: lui t1,0x8033 80056df0: lw a2,21400(a1) # load jiffies 80056df4: lw v1,21404(a3) # load jiffies_64(hi) 80056df8: addiu v0,v0,1 # inc jiffies_64(lo) 80056dfc: lw t0,21360(t1) # load wall_jiffies 80056e00: sltiu a1,v0,1 # calc carry 80056e04: addu v1,v1,a1 # add carry to jiffies_64(hi) 80056e08: subu s4,a2,t0 # calc ticks (jiffies - wall_jiffies) 80056e0c: sw v0,21400(a3) # store jiffies_64(lo) 80056e10: sw v1,21404(a3) # store jiffies_64(hi) 80056e14: beqz s4,80057060 80056e18: move s8,a0 The 'tick' variable is calculated using 'jiffies' value before incrementing 'jiffies_64'. As a result, wall_jiffies will always one smaller then jiffies on elsewhere. I also checked x86 code (3.4.4). c012696a : ... c012696e: mov 0xc0482400,%eax # load jiffies c0126973: addl $0x1,0xc0482400 # inc jiffies_64(lo) c012697a: mov 0xc041a230,%edx # load wall_jiffies c0126980: mov %eax,%ebx c0126982: adcl $0x0,0xc0482404 # add carry to jiffies_64(hi) c0126989: sub %edx,%ebx # calc ticks (jiffies - wall_jiffies) c012698b: jne c01269a0 Though I'm not familiar with x86, it looks same. Is this really expected code? If no, how it can be fixed? Insert "barrier()" right after "jiffies_64++" ? --- Atsushi Nemoto From anemo@mba.ocn.ne.jp Wed Mar 1 06:08:43 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 06:08:53 +0000 (GMT) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:170 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S8133385AbWCAGIm (ORCPT ); Wed, 1 Mar 2006 06:08:42 +0000 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Wed, 1 Mar 2006 15:16:30 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 9A5E620535; Wed, 1 Mar 2006 15:16:28 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 85F7220268; Wed, 1 Mar 2006 15:16:28 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k216GQ4D052138; Wed, 1 Mar 2006 15:16:27 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Wed, 01 Mar 2006 15:16:26 +0900 (JST) Message-Id: <20060301.151626.48531391.nemoto@toshiba-tops.co.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, geert@linux-m68k.org, takata@linux-m32r.org, davem@davemloft.net Subject: [PATCH] [MIPS] use USECS_PER_SEC / HZ instead of tick_usec in do_gettimeofday From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10692 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips The 'tick_usec' is USER_HZ period in usec. do_gettimeofday() should use kernel HZ value. Here is a patch for MIPS. It seems m32r, m68k and sparc have same problem though their HZ and USER_HZ are same for now. Signed-off-by: Atsushi Nemoto diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 7050b4f..42c94c7 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -163,7 +163,7 @@ void do_gettimeofday(struct timeval *tv) unsigned long seq; unsigned long lost; unsigned long usec, sec; - unsigned long max_ntp_tick = tick_usec - tickadj; + unsigned long max_ntp_tick; do { seq = read_seqbegin(&xtime_lock); @@ -178,12 +178,13 @@ void do_gettimeofday(struct timeval *tv) * Better to lose some accuracy than have time go backwards.. */ if (unlikely(time_adjust < 0)) { + max_ntp_tick = (USEC_PER_SEC / HZ) - tickadj; usec = min(usec, max_ntp_tick); if (lost) usec += lost * max_ntp_tick; } else if (unlikely(lost)) - usec += lost * tick_usec; + usec += lost * (USEC_PER_SEC / HZ); sec = xtime.tv_sec; usec += (xtime.tv_nsec / 1000); From mic@daemon.nethack.at Wed Mar 1 10:00:30 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 10:00:38 +0000 (GMT) Received: from daemon.nethack.at ([213.235.236.206]:41092 "EHLO daemon.nethack.at") by ftp.linux-mips.org with ESMTP id S8133385AbWCAKAa (ORCPT ); Wed, 1 Mar 2006 10:00:30 +0000 Received: (qmail 30636 invoked by uid 1000); 1 Mar 2006 11:08:18 +0100 Date: Wed, 1 Mar 2006 11:08:18 +0100 From: Michael Dosser To: Martin Michlmayr Cc: linux-mips@linux-mips.org Subject: Re: MIPS kernel status as of 2.6.16-rc5 Message-ID: <20060301100817.GB928@nethack.at> References: <20060228214144.GA6615@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060228214144.GA6615@deprecation.cyrius.com> Organization: Nethack.at X-Operating-System: Debian GNU/Linux mips X-PGP-Key: http://mic.priv.at/mic.asc X-PGP-Public-Key: 1024D/5D872C06 X-PGP-Fingerprint: 2A21 7A7D BB77 8A41 B645 88BC 941A 80E8 5D87 2C06 X-RIPE-Handle: MD254-RIPE X-sig-random-gen: http://cfml.sourceforge.net/perl/chsig.tar.gz User-Agent: mutt-ng/devel-r655 (Debian) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10694 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mic@nethack.at Precedence: bulk X-list: linux-mips Content-Length: 500 Lines: 17 Hi, * On 2006-02-28 22:41 wrote: > - IP22: Indigo2 with > 256 MB fails to boot (regression from 2.4; > while 2.4 would only see 256 MB, it would at least boot) Is there a chance, that even if it would boot with > 256 MB linux could actually use all 384 MB of RAM? If not, does anybody know why and can explain it (I am no kernel developer and know only very little about the I2 hardware)? Thanks, bye mic -- Postmodernism is german romanticism with better special effects. From ralf@linux-mips.org Wed Mar 1 11:52:38 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 11:53:01 +0000 (GMT) Received: from mipsfw.mips-uk.com ([194.74.144.146]:27154 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133385AbWCALwi (ORCPT ); Wed, 1 Mar 2006 11:52:38 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k21BxLmd004628; Wed, 1 Mar 2006 11:59:21 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k21BxLZe004627; Wed, 1 Mar 2006 11:59:21 GMT Date: Wed, 1 Mar 2006 11:59:21 +0000 From: Ralf Baechle To: Martin Michlmayr Cc: Mark E Mason , linux-mips@linux-mips.org Subject: Re: [PATCH] Offer Sibyte IDE driver only on platforms that have IDE Message-ID: <20060301115921.GB3779@linux-mips.org> References: <20060301014723.GA16315@deprecation.cyrius.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060301014723.GA16315@deprecation.cyrius.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10695 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 680 Lines: 18 On Wed, Mar 01, 2006 at 01:47:23AM +0000, Martin Michlmayr wrote: > [PATCH] Offer Sibyte IDE driver only on platforms that have IDE > > Currently Kconfig allows you to select the Sibyte IDE driver on > any SB1 based SOC platform. However, not all of them actually > have IDE. Nor do they import the correct files needed to compile > the Sibyte (SWARM) IDE driver, leading to the compilation failure > below on a SB1A 1480 board. > > The situation can be improved by adding a SIBYTE_HAS_IDE Kconfig > variable and change the dependency of the Sibyte IDE driver > accordingly. I would really prefer to see runtime probing etc. as step towards a generic Sibyte kernel. Ralf From anemo@mba.ocn.ne.jp Wed Mar 1 11:59:44 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 12:00:12 +0000 (GMT) Received: from p549F6BF0.dip.t-dialin.net ([84.159.107.240]:62851 "EHLO p549F6BF0.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S8133138AbWCAL7o (ORCPT ); Wed, 1 Mar 2006 11:59:44 +0000 Received: from [IPv6:::ffff:202.230.225.126] ([IPv6:::ffff:202.230.225.126]:50519 "EHLO topsns2.toshiba-tops.co.jp") by linux-mips.net with ESMTP id ; Wed, 1 Mar 2006 13:06:56 +0100 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for p549F6BF0.dip.t-dialin.net [84.159.107.240]) with ESMTP; Wed, 1 Mar 2006 21:06:46 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 067E020404; Wed, 1 Mar 2006 21:05:42 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id E6C7820341; Wed, 1 Mar 2006 21:05:41 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k21C5f4D053710; Wed, 1 Mar 2006 21:05:41 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Wed, 01 Mar 2006 21:05:41 +0900 (JST) Message-Id: <20060301.210541.30439818.nemoto@toshiba-tops.co.jp> To: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Subject: Re: jiffies_64 vs. jiffies From: Atsushi Nemoto In-Reply-To: <20060301.144442.118975101.nemoto@toshiba-tops.co.jp> References: <20060301.144442.118975101.nemoto@toshiba-tops.co.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10696 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1472 Lines: 50 >>>>> On Wed, 01 Mar 2006 14:44:42 +0900 (JST), Atsushi Nemoto said: anemo> Hi. I noticed that the 'jiffies' variable has 'wall_jiffies + anemo> 1' value in most of time. I'm using MIPS platform but I think anemo> this is same for other platforms. anemo> I suppose this is due to gcc does not know that jiffies_64 and anemo> jiffies share same place. ... anemo> Is this really expected code? If no, how it can be fixed? anemo> Insert "barrier()" right after "jiffies_64++" ? I suppose passing updated jiffies to update_times() would be more efficient than barrier(). Here is a patch. Pass updated jiffies to update_times() to avoid jiffies/jiffies_64 aliasing. Signed-off-by: Atsushi Nemoto diff --git a/kernel/timer.c b/kernel/timer.c index fe3a9a9..7734788 100644 --- a/kernel/timer.c +++ b/kernel/timer.c @@ -904,11 +904,11 @@ void run_local_timers(void) * Called by the timer interrupt. xtime_lock must already be taken * by the timer IRQ! */ -static inline void update_times(void) +static inline void update_times(unsigned long jif) { unsigned long ticks; - ticks = jiffies - wall_jiffies; + ticks = jif - wall_jiffies; if (ticks) { wall_jiffies += ticks; update_wall_time(ticks); @@ -924,8 +924,7 @@ static inline void update_times(void) void do_timer(struct pt_regs *regs) { - jiffies_64++; - update_times(); + update_times(++jiffies_64); softlockup_tick(regs); } --- Atsushi Nemoto From zzh.hust@gmail.com Wed Mar 1 12:12:04 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 12:12:28 +0000 (GMT) Received: from nproxy.gmail.com ([64.233.182.199]:31301 "EHLO nproxy.gmail.com") by ftp.linux-mips.org with ESMTP id S8133572AbWCAMME convert rfc822-to-8bit (ORCPT ); Wed, 1 Mar 2006 12:12:04 +0000 Received: by nproxy.gmail.com with SMTP id c2so76465nfe for ; Wed, 01 Mar 2006 04:18:50 -0800 (PST) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=sGVbt1EL9dwx7YNJd7w0c1Ugr0iCy5eJEUCn6PCrcnBELUc5zK2APd6iqHDvTcYBaCSvbqZZqPCZ2fMD7IaKySnSxgQrL8C2yInZMNoGMZgAFl/R9BHb42rvJYJUccWNjmyiQaf004wIdpDGnGNnWiFNPf9xMEZHD6ZJoVm52Wo= Received: by 10.49.87.6 with SMTP id p6mr60999nfl; Wed, 01 Mar 2006 04:18:50 -0800 (PST) Received: by 10.48.249.14 with HTTP; Wed, 1 Mar 2006 04:18:50 -0800 (PST) Message-ID: <50c9a2250603010418s6f778c25s799d79cee2b79333@mail.gmail.com> Date: Wed, 1 Mar 2006 20:18:50 +0800 From: zhuzhenhua To: linux-mips Subject: how to select a rootfs for embedded linux based hardisk? MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10697 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zzh.hust@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 330 Lines: 12 dear all i want to port the linux to our board based hardisk with mips arch. i do not find too much file sytem for rootfs on hardisk besides ext2/ext3. but it seems ext2/ext3 is not suitable for embedded system. does someone have idea or experience with these products? thanks for any hints. Best regards zhuzhenhua From tbm@cyrius.com Wed Mar 1 12:36:06 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 12:36:23 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:41737 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133138AbWCAMgG (ORCPT ); Wed, 1 Mar 2006 12:36:06 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 61EB064D3D; Wed, 1 Mar 2006 12:43:50 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 06CDF9028; Wed, 1 Mar 2006 13:43:41 +0100 (CET) Date: Wed, 1 Mar 2006 12:43:41 +0000 From: Martin Michlmayr To: zhuzhenhua Cc: linux-mips Subject: Re: how to select a rootfs for embedded linux based hardisk? Message-ID: <20060301124341.GM24493@deprecation.cyrius.com> References: <50c9a2250603010418s6f778c25s799d79cee2b79333@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50c9a2250603010418s6f778c25s799d79cee2b79333@mail.gmail.com> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10698 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 737 Lines: 16 * zhuzhenhua [2006-03-01 20:18]: > i want to port the linux to our board based hardisk with > mips arch. i do not find too much file sytem for rootfs on hardisk > besides ext2/ext3. > but it seems ext2/ext3 is not suitable for embedded system. > does someone have idea or experience with these products? How large is your hard drive exactly and is it a real IDE hard drive or some kind of flash? If the disk/flash is very small, ext3 may be a bad choice since it's a journalling file system which means that a) it'll take up quite a significant portion of space on a small drive and b) it'll write to the same sectors all the time, which will kill the flash in no time. -- Martin Michlmayr http://www.cyrius.com/ From tbm@cyrius.com Wed Mar 1 12:38:11 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 12:38:19 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:43529 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133138AbWCAMiL (ORCPT ); Wed, 1 Mar 2006 12:38:11 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id EC92A64D3D; Wed, 1 Mar 2006 12:45:59 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id AE55A9028; Wed, 1 Mar 2006 13:45:52 +0100 (CET) Date: Wed, 1 Mar 2006 12:45:52 +0000 From: Martin Michlmayr To: Dave Johnson Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] fix lost ticks on SB1250 Message-ID: <20060301124552.GA5831@deprecation.cyrius.com> References: <17118.25343.948383.547250@cortez.sw.starentnetworks.com> <20060116160031.GA28383@deprecation.cyrius.com> <17355.52046.456176.406834@cortez.sw.starentnetworks.com> <17355.59571.567485.592914@cortez.sw.starentnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <17355.59571.567485.592914@cortez.sw.starentnetworks.com> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10699 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 331 Lines: 10 * Dave Johnson [2006-01-16 13:40]: > Patch is against 2.6.12 with some other patches unfortunatly (only > the gettimeofday one should matter as far as merging) Do you think you can update the patch for 2.6.16 and clean it up for submission? -- Martin Michlmayr http://www.cyrius.com/ From nickpiggin@yahoo.com.au Wed Mar 1 12:45:03 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 12:45:16 +0000 (GMT) Received: from smtp101.mail.mud.yahoo.com ([209.191.85.211]:30080 "HELO smtp101.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S8133138AbWCAMpD (ORCPT ); Wed, 1 Mar 2006 12:45:03 +0000 Received: (qmail 70651 invoked from network); 1 Mar 2006 12:52:46 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com.au; h=Received:Message-ID:Date:From:User-Agent:X-Accept-Language:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding; b=Vck0wRFnynPksIlhpHe0MFKs/xq7qDi0cE9Km5oWL70gXP7FHZBc4mK9G0N34I3olj9P2qljwgDS3GTqayRbt8zwE7vLySqPA6uBAyE7PXiX3+rZZw7EYwei+GA+zItMkVp+iOmYE2Q4blfipvCQwsWlIoow0ADLdkM/wcOEHtg= ; Received: from unknown (HELO ?192.168.0.1?) (nickpiggin@203.173.4.201 with plain) by smtp101.mail.mud.yahoo.com with SMTP; 1 Mar 2006 12:52:46 -0000 Message-ID: <44059915.3010800@yahoo.com.au> Date: Wed, 01 Mar 2006 23:52:37 +1100 From: Nick Piggin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.7.12) Gecko/20051007 Debian/1.7.12-1 X-Accept-Language: en MIME-Version: 1.0 To: Atsushi Nemoto CC: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: jiffies_64 vs. jiffies References: <20060301.144442.118975101.nemoto@toshiba-tops.co.jp> <20060301.210541.30439818.nemoto@toshiba-tops.co.jp> In-Reply-To: <20060301.210541.30439818.nemoto@toshiba-tops.co.jp> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10700 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nickpiggin@yahoo.com.au Precedence: bulk X-list: linux-mips Content-Length: 403 Lines: 18 Atsushi Nemoto wrote: > @@ -924,8 +924,7 @@ static inline void update_times(void) > > void do_timer(struct pt_regs *regs) > { > - jiffies_64++; > - update_times(); > + update_times(++jiffies_64); > softlockup_tick(regs); > } > jiffies_64 is not volatile so you should not have to obfuscate the code like this. -- Send instant messages to your online friends http://au.messenger.yahoo.com From sbharathi@MidasComm.Com Wed Mar 1 14:22:39 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 14:22:48 +0000 (GMT) Received: from midas-91-171-chn.midascomm.com ([203.196.171.91]:62125 "EHLO info.midascomm.com") by ftp.linux-mips.org with ESMTP id S8133138AbWCAOWj (ORCPT ); Wed, 1 Mar 2006 14:22:39 +0000 Received: from bharathi.midascomm.com ([192.168.13.175]) by info.midascomm.com (8.12.10/8.12.10) with ESMTP id k21ETvLG024237; Wed, 1 Mar 2006 20:00:01 +0530 Date: Wed, 1 Mar 2006 20:11:52 +0530 (IST) From: Bharathi Subramanian To: "Nori, Soma Sekhar" cc: Linux MIPS Subject: RE: CPU Frequency change using PLL In-Reply-To: Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-midascomm.com-MailScanner-Information: Please contact the ISP for more information X-midascomm.com-MailScanner: Found to be clean X-midascomm.com-MailScanner-From: sbharathi@midascomm.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10701 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sbharathi@MidasComm.Com Precedence: bulk X-list: linux-mips Content-Length: 1000 Lines: 28 On Tue, 28 Feb 2006, Nori, Soma Sekhar wrote: > > During my try, after changing the PLL Freq, the board is stops > > running. I feel, it is due to change in SDRAM Refresh rate. Is it > > right ?? Any body tried this, Kindly share exprience with me. Like > > how to reprogram the peripherals with-out affecting the operation > > etc.. > > Changing the PLL feeding only to the MIPS should not freeze the > board. You are likely messing with PLL which feeds the peripherals > as well. No. PLL-A (Low Freq) is feeding to peripherals and PLL-B(High Feeq) is feeding the MIPS. To save power, I switch from PLL-B to PLL-A during run-time. After wirte in to PLL-Reg the MIPS Hangs. No reboot. > Changing the PLL which feeds the SDRAM will also likely cause memory > corruption. Try putting the SDRAM in self-refresh for the duration > of PLL stablization and then re-program the SDRAM refresh rate. I didn't tried this Self-Refresh trick, Let me try ... Kindly CC to me. Thanks :) -- Bharathi S From anemo@mba.ocn.ne.jp Wed Mar 1 14:50:09 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 14:50:18 +0000 (GMT) Received: from mba.ocn.ne.jp ([210.190.142.172]:49346 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S8133138AbWCAOuJ (ORCPT ); Wed, 1 Mar 2006 14:50:09 +0000 Received: from localhost (p7129-ipad01funabasi.chiba.ocn.ne.jp [61.207.81.129]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id C0C4DA522; Wed, 1 Mar 2006 23:57:55 +0900 (JST) Date: Wed, 01 Mar 2006 23:57:50 +0900 (JST) Message-Id: <20060301.235750.25910018.anemo@mba.ocn.ne.jp> To: nickpiggin@yahoo.com.au Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: jiffies_64 vs. jiffies From: Atsushi Nemoto In-Reply-To: <44059915.3010800@yahoo.com.au> References: <20060301.144442.118975101.nemoto@toshiba-tops.co.jp> <20060301.210541.30439818.nemoto@toshiba-tops.co.jp> <44059915.3010800@yahoo.com.au> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10702 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 466 Lines: 21 >>>>> On Wed, 01 Mar 2006 23:52:37 +1100, Nick Piggin said: >> void do_timer(struct pt_regs *regs) >> { >> - jiffies_64++; >> - update_times(); >> + update_times(++jiffies_64); >> softlockup_tick(regs); >> } nick> jiffies_64 is not volatile so you should not have to obfuscate nick> the code like this. Well, do you mean it should be like this ? jiffies_64++; update_times(jiffies_64); Thanks for your comments. --- Atsushi Nemoto From nickpiggin@yahoo.com.au Wed Mar 1 14:52:35 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 14:52:46 +0000 (GMT) Received: from smtp109.mail.mud.yahoo.com ([209.191.85.219]:53344 "HELO smtp109.mail.mud.yahoo.com") by ftp.linux-mips.org with SMTP id S8133138AbWCAOwf (ORCPT ); Wed, 1 Mar 2006 14:52:35 +0000 Received: (qmail 70826 invoked from network); 1 Mar 2006 15:00:19 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com.au; h=Received:Message-ID:Date:From:User-Agent:X-Accept-Language:MIME-Version:To:CC:Subject:References:In-Reply-To:Content-Type:Content-Transfer-Encoding; b=uk+6687T9kQY+egMbUwOkw9k9w97Jg5Zop6QAOpQ5AgN3eKbh2LK9xiHi+Z7xZpxkg+wuVu+2Ojsec6a9mxtidSXX52wqJ/MdzMvtmdG2NUtcJNf2FrpkPM7CpOQT61rXFR7ZNYaCQPMt+t3CCVRGQoohTY4mTmpMuBIsYs2BLQ= ; Received: from unknown (HELO ?192.168.0.1?) (nickpiggin@203.173.4.201 with plain) by smtp109.mail.mud.yahoo.com with SMTP; 1 Mar 2006 15:00:19 -0000 Message-ID: <4405B700.1080607@yahoo.com.au> Date: Thu, 02 Mar 2006 02:00:16 +1100 From: Nick Piggin User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.7.12) Gecko/20051007 Debian/1.7.12-1 X-Accept-Language: en MIME-Version: 1.0 To: Atsushi Nemoto CC: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: jiffies_64 vs. jiffies References: <20060301.144442.118975101.nemoto@toshiba-tops.co.jp> <20060301.210541.30439818.nemoto@toshiba-tops.co.jp> <44059915.3010800@yahoo.com.au> <20060301.235750.25910018.anemo@mba.ocn.ne.jp> In-Reply-To: <20060301.235750.25910018.anemo@mba.ocn.ne.jp> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10703 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nickpiggin@yahoo.com.au Precedence: bulk X-list: linux-mips Content-Length: 679 Lines: 31 Atsushi Nemoto wrote: >>>>>>On Wed, 01 Mar 2006 23:52:37 +1100, Nick Piggin said: > > >>>void do_timer(struct pt_regs *regs) >>>{ >>>- jiffies_64++; >>>- update_times(); >>>+ update_times(++jiffies_64); >>> softlockup_tick(regs); >>>} > > > nick> jiffies_64 is not volatile so you should not have to obfuscate > nick> the code like this. > > Well, do you mean it should be like this ? > > jiffies_64++; > update_times(jiffies_64); > Yeah. It makes your patch a line smaller too! > Thanks for your comments. Oh it was nothing really ;) -- SUSE Labs, Novell Inc. Send instant messages to your online friends http://au.messenger.yahoo.com From anemo@mba.ocn.ne.jp Wed Mar 1 16:05:23 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 16:05:32 +0000 (GMT) Received: from mba.ocn.ne.jp ([210.190.142.172]:19183 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S8133572AbWCAQFX (ORCPT ); Wed, 1 Mar 2006 16:05:23 +0000 Received: from localhost (p7129-ipad01funabasi.chiba.ocn.ne.jp [61.207.81.129]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 07D31B4D9; Thu, 2 Mar 2006 01:13:08 +0900 (JST) Date: Thu, 02 Mar 2006 01:13:04 +0900 (JST) Message-Id: <20060302.011304.75185944.anemo@mba.ocn.ne.jp> To: nickpiggin@yahoo.com.au Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: jiffies_64 vs. jiffies From: Atsushi Nemoto In-Reply-To: <4405B700.1080607@yahoo.com.au> References: <44059915.3010800@yahoo.com.au> <20060301.235750.25910018.anemo@mba.ocn.ne.jp> <4405B700.1080607@yahoo.com.au> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10704 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 943 Lines: 41 >>>>> On Thu, 02 Mar 2006 02:00:16 +1100, Nick Piggin said: >> Well, do you mean it should be like this ? >> >> jiffies_64++; >> update_times(jiffies_64); nick> Yeah. It makes your patch a line smaller too! Another solution might be simplifying update_times() like this. It looks there is no point to calculate ticks in update_times(). diff --git a/kernel/timer.c b/kernel/timer.c index fe3a9a9..6188c99 100644 --- a/kernel/timer.c +++ b/kernel/timer.c @@ -906,14 +906,9 @@ void run_local_timers(void) */ static inline void update_times(void) { - unsigned long ticks; - - ticks = jiffies - wall_jiffies; - if (ticks) { - wall_jiffies += ticks; - update_wall_time(ticks); - } - calc_load(ticks); + wall_jiffies++; + update_wall_time(1); + calc_load(1); } /* As for long term solution, using an union for jiffies and jiffies_64 would be robust. But it affects so many codes ... --- Atsushi Nemoto From geoffrey.levand@am.sony.com Wed Mar 1 16:42:47 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 16:42:57 +0000 (GMT) Received: from mail8.fw-bc.sony.com ([160.33.98.75]:7325 "EHLO mail8.fw-bc.sony.com") by ftp.linux-mips.org with ESMTP id S8133594AbWCAQmr (ORCPT ); Wed, 1 Mar 2006 16:42:47 +0000 Received: from mail3.sjc.in.sel.sony.com (mail3.sjc.in.sel.sony.com [43.134.1.211]) by mail8.fw-bc.sony.com (8.12.11/8.12.11) with ESMTP id k21GoWN2001781 for ; Wed, 1 Mar 2006 16:50:33 GMT Received: from [192.168.1.10] ([43.134.85.105]) by mail3.sjc.in.sel.sony.com (8.12.11/8.12.11) with ESMTP id k21GoWh8010152; Wed, 1 Mar 2006 16:50:32 GMT Message-ID: <4405D0D8.7030704@am.sony.com> Date: Wed, 01 Mar 2006 08:50:32 -0800 From: Geoff Levand User-Agent: Mozilla Thunderbird 1.0.7-1.1.fc4 (X11/20050929) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: git trouble Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10705 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geoffrey.levand@am.sony.com Precedence: bulk X-list: linux-mips Content-Length: 381 Lines: 8 I'm having this problem lately... Any help? $ cg-clone http://www.linux-mips.org/pub/scm/linux.git linux-mips.git defaulting to local storage area 08:45:45 URL:http://www.linux-mips.org/pub/scm/linux.git/HEAD [23/23] -> "refs/heads/.origin-fetching" [1] error: Could not interpret ref: refs/heads/master as something to pull cg-fetch: objects fetch failed cg-clone: fetch failed From ralf@linux-mips.org Wed Mar 1 16:57:29 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 16:57:39 +0000 (GMT) Received: from mipsfw.mips-uk.com ([194.74.144.146]:32526 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133604AbWCAQ53 (ORCPT ); Wed, 1 Mar 2006 16:57:29 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k21H4Jg3024777; Wed, 1 Mar 2006 17:04:19 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k21H4J4F024776; Wed, 1 Mar 2006 17:04:19 GMT Date: Wed, 1 Mar 2006 17:04:18 +0000 From: Ralf Baechle To: Geoff Levand Cc: linux-mips@linux-mips.org Subject: Re: git trouble Message-ID: <20060301170418.GA22739@linux-mips.org> References: <4405D0D8.7030704@am.sony.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4405D0D8.7030704@am.sony.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10706 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 695 Lines: 17 On Wed, Mar 01, 2006 at 08:50:32AM -0800, Geoff Levand wrote: > I'm having this problem lately... Any help? > > $ cg-clone http://www.linux-mips.org/pub/scm/linux.git linux-mips.git > defaulting to local storage area > 08:45:45 URL:http://www.linux-mips.org/pub/scm/linux.git/HEAD [23/23] -> "refs/heads/.origin-fetching" [1] > error: Could not interpret ref: refs/heads/master as something to pull > cg-fetch: objects fetch failed > cg-clone: fetch failed HEAD used to be a symlink; more recent versions of git which try to support operating systems without symlinks put something like "ref: refs/heads/master" into that file. I suspect your cogito is simply too old to grok that. Ralf From ralf@linux-mips.org Wed Mar 1 17:16:22 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 17:16:34 +0000 (GMT) Received: from mipsfw.mips-uk.com ([194.74.144.146]:14611 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133604AbWCARQW (ORCPT ); Wed, 1 Mar 2006 17:16:22 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k21HO9xh026059 for ; Wed, 1 Mar 2006 17:24:09 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k21HO99k026058 for linux-mips@linux-mips.org; Wed, 1 Mar 2006 17:24:09 GMT Date: Wed, 1 Mar 2006 17:24:09 +0000 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: CVS cronjobs Message-ID: <20060301172409.GA25995@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10707 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 240 Lines: 6 I'd like to remind the remain users running a regular CVS update on the linux-mips.org CVS kernel repository that CVS is dead and frozen, there will be no more updates to the CVS kernel repository, so please disable those cronjobs. Ralf From jcrouse@cosmic.amd.com Wed Mar 1 18:24:39 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 18:24:53 +0000 (GMT) Received: from amdext3.amd.com ([139.95.251.6]:41633 "EHLO amdext3.amd.com") by ftp.linux-mips.org with ESMTP id S8133618AbWCASYj (ORCPT ); Wed, 1 Mar 2006 18:24:39 +0000 Received: from SSVLGW01.amd.com (ssvlgw01.amd.com [139.95.250.169]) by amdext3.amd.com (8.12.11/8.12.11/AMD) with ESMTP id k21IS8Vk022206; Wed, 1 Mar 2006 10:32:25 -0800 Received: from 139.95.53.182 by SSVLGW02.amd.com with ESMTP (AMD SMTP Relay (Email Firewall v6.1.0)); Wed, 01 Mar 2006 10:20:48 -0800 X-Server-Uuid: 519AC16A-9632-469E-B354-112C592D09E8 Received: from ldcmail.amd.com ([147.5.200.40]) by SSVLEXBH1.amd.com with Microsoft SMTPSVC(6.0.3790.0); Wed, 1 Mar 2006 10:20:48 -0800 Received: from cosmic.amd.com (cosmic.amd.com [147.5.201.206]) by ldcmail.amd.com (Postfix) with ESMTP id BD5142028; Wed, 1 Mar 2006 11:20:47 -0700 (MST) Received: from cosmic.amd.com (localhost [127.0.0.1]) by cosmic.amd.com (8.13.4/8.13.4) with ESMTP id k21IUQXI020952; Wed, 1 Mar 2006 11:30:26 -0700 Received: (from jcrouse@localhost) by cosmic.amd.com ( 8.13.4/8.13.4/Submit) id k21IUQ1n020951; Wed, 1 Mar 2006 11:30:26 -0700 Date: Wed, 1 Mar 2006 11:30:26 -0700 From: "Jordan Crouse" To: linux-usb-devel@lists.sourceforge.net cc: linux-mips@linux-mips.org, gregkh@suse.de, tbm@cyrius.com Subject: [PATCH] Buglet in Alchemy OHCI driver Message-ID: <20060301183026.GL31957@cosmic.amd.com> MIME-Version: 1.0 User-Agent: Mutt/1.5.11 X-OriginalArrivalTime: 01 Mar 2006 18:20:48.0528 (UTC) FILETIME=[DD461100:01C63D5C] X-WSS-ID: 681B398A1V04264282-01-01 Content-Type: multipart/mixed; boundary=5vNYLRcllDrimb99 Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10708 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jordan.crouse@amd.com Precedence: bulk X-list: linux-mips Content-Length: 1322 Lines: 54 --5vNYLRcllDrimb99 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit Martin Michlmayr spotted this potentially serious bug. Please apply. Jordan -- Jordan Crouse Senior Linux Engineer AMD - Personal Connectivity Solutions Group --5vNYLRcllDrimb99 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename=ohci-fix.patch Content-Transfer-Encoding: 7bit [PATCH] Buglet in Alchemy OCHI From: Jordan Crouse Failure to get the right resources should immediately return. Current code has the possiblity of running off into the weeds. Spotted by Martin Michlmayr. Signed-off-by: Jordan Crouse --- drivers/usb/host/ohci-au1xxx.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index aa4d0cd..d8fb1bb 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -94,7 +94,7 @@ int usb_hcd_au1xxx_probe (const struct h if (dev->resource[1].flags != IORESOURCE_IRQ) { pr_debug ("resource[1] is not IORESOURCE_IRQ"); - retval = -ENOMEM; + return -ENOMEM; } hcd = usb_create_hcd(driver, &dev->dev, "Au1xxx"); --5vNYLRcllDrimb99-- From tbm@cyrius.com Wed Mar 1 18:29:57 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 18:30:08 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:27148 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133619AbWCAS35 (ORCPT ); Wed, 1 Mar 2006 18:29:57 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 4C9F464D3D; Wed, 1 Mar 2006 18:37:45 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 775D89025; Wed, 1 Mar 2006 19:37:35 +0100 (CET) Date: Wed, 1 Mar 2006 18:37:35 +0000 From: Martin Michlmayr To: Jordan Crouse Cc: linux-usb-devel@lists.sourceforge.net, linux-mips@linux-mips.org, gregkh@suse.de Subject: Re: [PATCH] Buglet in Alchemy OHCI driver Message-ID: <20060301183735.GA28491@deprecation.cyrius.com> References: <20060301183026.GL31957@cosmic.amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060301183026.GL31957@cosmic.amd.com> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10709 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 1186 Lines: 40 * Jordan Crouse [2006-03-01 11:30]: > Martin Michlmayr spotted this potentially serious bug. Please apply. Please don't send patches as MIME attachments. Here it is again (with a better summary too): [PATCH] Alchemy OCHI: return if right resources cannot be obtained From: Jordan Crouse Failure to get the right resources should immediately return. Current code has the possiblity of running off into the weeds. Spotted by Martin Michlmayr. Signed-off-by: Jordan Crouse Signed-off-by: Martin Michlmayr --- drivers/usb/host/ohci-au1xxx.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index aa4d0cd..d8fb1bb 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -94,7 +94,7 @@ int usb_hcd_au1xxx_probe (const struct h if (dev->resource[1].flags != IORESOURCE_IRQ) { pr_debug ("resource[1] is not IORESOURCE_IRQ"); - retval = -ENOMEM; + return -ENOMEM; } hcd = usb_create_hcd(driver, &dev->dev, "Au1xxx"); -- Martin Michlmayr http://www.cyrius.com/ From ralf@linux-mips.org Wed Mar 1 19:19:22 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 19:19:31 +0000 (GMT) Received: from mipsfw.mips-uk.com ([194.74.144.146]:25101 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133619AbWCATTW (ORCPT ); Wed, 1 Mar 2006 19:19:22 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k21JQvkn030912; Wed, 1 Mar 2006 19:26:57 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k21JQv2O030910; Wed, 1 Mar 2006 19:26:57 GMT Date: Wed, 1 Mar 2006 19:26:57 +0000 From: Ralf Baechle To: Dominique Quatravaux Cc: linux-mips@linux-mips.org Subject: Re: Error trying to update www.linux-mips.org/wiki Message-ID: <20060301192657.GA28396@linux-mips.org> References: <440384D2.5040109@kilimandjaro.dyndns.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <440384D2.5040109@kilimandjaro.dyndns.org> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10710 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 722 Lines: 22 On Tue, Feb 28, 2006 at 12:01:38AM +0100, Dominique Quatravaux wrote: > Hi, while trying to reorganize information a bit in the Linux-Mips wiki, > I came across the following error when I try to save my changes. This > apparently happens on all pages. > > Best regards, Dom > > == 8< == 8< == > > A database query syntax error has occurred. This may indicate a bug in > the software. The last attempted database query was: > > (SQL query hidden) > > from within function "SearchUpdate::doUpdate". MySQL returned error > "1016: Can't open file: 'searchindex.MYI' (errno: 145) (localhost)". MySQL for unknown reasons seems to love marking it's tables as crashed every once in a while. I just fixed that. Ralf From tbm@cyrius.com Wed Mar 1 23:06:17 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 23:06:26 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:35086 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133711AbWCAXGQ (ORCPT ); Wed, 1 Mar 2006 23:06:16 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 39A5A64D3D; Wed, 1 Mar 2006 23:14:06 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id D07F986BB; Thu, 2 Mar 2006 00:13:58 +0100 (CET) Resent-From: tbm@cyrius.com Resent-Date: Wed, 1 Mar 2006 23:13:58 +0000 Resent-Message-ID: <20060301231358.GR26088@deprecation.cyrius.com> Resent-To: linux-mips@linux-mips.org X-Original-To: tbm@cyrius.com Received: by deprecation.cyrius.com (Postfix, from userid 10) id 887B191C2; Thu, 2 Mar 2006 00:12:06 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by sorrow.cyrius.com (Postfix) with ESMTP id D501D64D3E for ; Wed, 1 Mar 2006 22:40:13 +0000 (UTC) Received: from nephila.localnet (i-83-67-53-76.freedom2surf.net [83.67.53.76]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by sorrow.cyrius.com (Postfix) with ESMTP id E11F764D3D for ; Wed, 1 Mar 2006 22:40:04 +0000 (UTC) Received: from pdh by nephila.localnet with local (Exim 4.50) id 1FEZzF-0000Dj-Dx for tbm@cyrius.com; Wed, 01 Mar 2006 22:40:01 +0000 Date: Wed, 1 Mar 2006 22:40:01 +0000 To: Martin Michlmayr Subject: Re: Crash on Cobalt with CONFIG_SERIO=y Message-ID: <20060301224001.GA719@colonel-panic.org> References: <20060120004208.GA18327@deprecation.cyrius.com> <20060120144710.GA30415@linux-mips.org> <20060121010455.GC3514@colonel-panic.org> <20060228165404.GA8442@deprecation.cyrius.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060228165404.GA8442@deprecation.cyrius.com> User-Agent: Mutt/1.5.9i From: Peter Horton X-Virus-Scanned: by amavisd-new-20030616-p10 (Debian) at cyrius.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10711 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 1734 Lines: 44 On Tue, Feb 28, 2006 at 04:54:05PM +0000, Martin Michlmayr wrote: > * Peter Horton [2006-01-21 01:04]: > > > > Real Time Clock Driver v1.12a > > > > Cobalt LCD Driver v2.10 > > > > i8042.c: i8042 controller self test timeout. > > > > Unhandled kernel unaligned access[#1]: > > > > > > The i8042 error message is a little surprising. The Cobalt boards afair > > No SuperIO, but there is a bog standard VIA PCI-ISA bridge which > > contains a bog standard PS/2 keyboard controller, which you would have > > thought should just work ... > > That's really interesting. I tried latest git (2.6.16-rc5) to see if > this is still there. First of all, 32-bit is fine, both regarding > i8042 as well as ALSA with a PCI audio card. With a 64-bit kernel, > i8042 appears to be okay now. I get: > > Cobalt LCD Driver v2.10 > i8042.c: i8042 controller self test timeout. > Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled > > and the kernel boots fine. > > I then built ALSA support into the kernel to see whether > http://www.linux-mips.org/archives/linux-mips/2006-01/msg00325.html > disappeared too. I got almost the same oops as the one I got before > because of i8042. > > Peter, does that make any sense to you? I assume your recent PCI fix > may be related. > Those addresses that begin 9b640000 (including the fault address) look very strange. The low 32-bits look like a valid physical address in the PCI space but the top bits definitely don't look right (unless the kernel's playing tricks with unused address bits; I'll have to check the RM523x data sheet to see if they have any effect). Have any of the MIPs experts commented ? > > BadVA : 9b64000001014c87 > P. From tbm@cyrius.com Wed Mar 1 23:06:52 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 23:07:09 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:35598 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133712AbWCAXGf (ORCPT ); Wed, 1 Mar 2006 23:06:35 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 36B1764D3D; Wed, 1 Mar 2006 23:14:27 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id D28CA86BB; Thu, 2 Mar 2006 00:14:19 +0100 (CET) Date: Wed, 1 Mar 2006 23:14:19 +0000 From: Martin Michlmayr To: Peter Horton Cc: linux-mips@linux-mips.org Subject: Re: Crash on Cobalt with CONFIG_SERIO=y Message-ID: <20060301231419.GS26088@deprecation.cyrius.com> References: <20060120004208.GA18327@deprecation.cyrius.com> <20060120144710.GA30415@linux-mips.org> <20060121010455.GC3514@colonel-panic.org> <20060228165404.GA8442@deprecation.cyrius.com> <20060301224001.GA719@colonel-panic.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060301224001.GA719@colonel-panic.org> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10712 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 503 Lines: 12 * Peter Horton [2006-03-01 22:40]: > Those addresses that begin 9b640000 (including the fault address) look > very strange. The low 32-bits look like a valid physical address in the > PCI space but the top bits definitely don't look right (unless the > kernel's playing tricks with unused address bits; I'll have to check the > RM523x data sheet to see if they have any effect). Have any of the MIPs > experts commented ? Raaalf? ;-) -- Martin Michlmayr http://www.cyrius.com/ From greg@kroah.org Wed Mar 1 23:14:30 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Mar 2006 23:14:38 +0000 (GMT) Received: from dsl093-040-174.pdx1.dsl.speakeasy.net ([66.93.40.174]:44768 "EHLO aria.kroah.org") by ftp.linux-mips.org with ESMTP id S8133711AbWCAXOa (ORCPT ); Wed, 1 Mar 2006 23:14:30 +0000 Received: from press.kroah.org ([192.168.0.25] helo=localhost) by aria.kroah.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.54) id 1FEadZ-00058S-7x; Wed, 01 Mar 2006 15:21:41 -0800 Date: Wed, 1 Mar 2006 15:21:54 -0800 From: Greg KH To: Martin Michlmayr Cc: Jordan Crouse , linux-usb-devel@lists.sourceforge.net, linux-mips@linux-mips.org, gregkh@suse.de Subject: Re: [PATCH] Buglet in Alchemy OHCI driver Message-ID: <20060301232154.GA13698@kroah.com> References: <20060301183026.GL31957@cosmic.amd.com> <20060301183735.GA28491@deprecation.cyrius.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060301183735.GA28491@deprecation.cyrius.com> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10713 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: greg@kroah.com Precedence: bulk X-list: linux-mips Content-Length: 835 Lines: 25 On Wed, Mar 01, 2006 at 06:37:35PM +0000, Martin Michlmayr wrote: > * Jordan Crouse [2006-03-01 11:30]: > > Martin Michlmayr spotted this potentially serious bug. Please apply. > > Please don't send patches as MIME attachments. Here it is again (with > a better summary too): > > > [PATCH] Alchemy OCHI: return if right resources cannot be obtained > > From: Jordan Crouse > > Failure to get the right resources should immediately return. Current > code has the possiblity of running off into the weeds. Spotted by > Martin Michlmayr. > > Signed-off-by: Jordan Crouse > Signed-off-by: Martin Michlmayr This patch is already in my tree, in the other patch from Jordan, so it will make it in after 2.6.16-final is out. thanks, greg k-h From tbm@cyrius.com Thu Mar 2 00:44:12 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 00:44:24 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:49679 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133714AbWCBAoM (ORCPT ); Thu, 2 Mar 2006 00:44:12 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id E341064D3D; Thu, 2 Mar 2006 00:52:02 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id DF0E38545; Thu, 2 Mar 2006 01:51:52 +0100 (CET) Resent-From: tbm@cyrius.com Resent-Date: Thu, 2 Mar 2006 00:51:52 +0000 Resent-Message-ID: <20060302005152.GB4118@deprecation.cyrius.com> Resent-To: linux-mips@linux-mips.org X-Original-To: tbm@cyrius.com Received: by deprecation.cyrius.com (Postfix, from userid 10) id 808B39122; Wed, 1 Mar 2006 23:04:23 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by sorrow.cyrius.com (Postfix) with ESMTP id 0933364D3D for ; Wed, 1 Mar 2006 21:53:15 +0000 (UTC) Received: from nephila.localnet (i-83-67-53-76.freedom2surf.net [83.67.53.76]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by sorrow.cyrius.com (Postfix) with ESMTP id C2A8864D3E for ; Wed, 1 Mar 2006 21:53:12 +0000 (UTC) Received: from pdh by nephila.localnet with local (Exim 4.50) id 1FEZFu-0000n5-Vx for tbm@cyrius.com; Wed, 01 Mar 2006 21:53:10 +0000 Date: Wed, 1 Mar 2006 21:53:10 +0000 To: Martin Michlmayr Subject: Re: Diff between Linus' and linux-mips git: tulip Message-ID: <20060301215310.GB2993@colonel-panic.org> References: <20060219234318.GA16311@deprecation.cyrius.com> <20060220000141.GX10266@deprecation.cyrius.com> <20060220001907.GC17967@deprecation.cyrius.com> <20060220230349.GB1122@colonel-panic.org> <20060224011324.GN9704@deprecation.cyrius.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060224011324.GN9704@deprecation.cyrius.com> User-Agent: Mutt/1.5.9i From: Peter Horton X-Virus-Scanned: by amavisd-new-20030616-p10 (Debian) at cyrius.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10714 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 1266 Lines: 27 On Fri, Feb 24, 2006 at 01:13:27AM +0000, Martin Michlmayr wrote: > * Peter Horton [2006-02-20 23:03]: > > > - /* No media table either */ > > > - tp->flags &= ~HAS_MEDIA_TABLE; > > > + /* Ensure our media table fixup get's applied */ > > > + memcpy(ee_data + 16, ee_data, 8); > > > #endif > > > #ifdef CONFIG_MIPS_COBALT > > Didn't the memcpy() used to be inside the CONFIG_MIPS_COBALT section ? > > Looking at tulip/eeprom.c I can't work out why it was ever there though > > Yeah, and it's still there in the Cobalt section. But now (in the > mips tree) it's _also_ there for CONFIG_DDB5477. So I have several > questions: > - can we just get rid of the code between CONFIG_MIPS_COBALT? > - should the CONFIG_DDB5477 change be reverted (probably), and do we > need these special cases for CONFIG_DDB* anyway or can they be > solved in a better way (e.g. by putting something in eeprom.c). > > It seems mips is the only arch that mucks around with "#ifdef CONFIG_" > in this file... Looks like both the "sa_offset = 0" and "memcpy(...)" are required to ensure our fixup from tulip/eeprom.c gets applied. I don't know why it only seems to be us that needs it :-( P. From zzh.hust@gmail.com Thu Mar 2 00:47:59 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 00:48:09 +0000 (GMT) Received: from nproxy.gmail.com ([64.233.182.196]:39920 "EHLO nproxy.gmail.com") by ftp.linux-mips.org with ESMTP id S8133716AbWCBAr7 convert rfc822-to-8bit (ORCPT ); Thu, 2 Mar 2006 00:47:59 +0000 Received: by nproxy.gmail.com with SMTP id h2so194092nfe for ; Wed, 01 Mar 2006 16:55:51 -0800 (PST) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=rbtMfOZ1oSj2htWvqVMHULkbkY4FntqXj2aFvvCHpChamKGZnCbom6RxFi3xauScFux7+zct+yBRpiH4F4eMBqhsWPMQjqAiOmS2wq/DG1LGV6V/EpYIdbFbjm2Kteht6Y+O7FfxUs1ncgK3eTdxJjzj2Iv7vaPZsvzDqp6XnGw= Received: by 10.48.238.3 with SMTP id l3mr388395nfh; Wed, 01 Mar 2006 16:55:51 -0800 (PST) Received: by 10.48.249.14 with HTTP; Wed, 1 Mar 2006 16:55:51 -0800 (PST) Message-ID: <50c9a2250603011655m4a61c262v41898d496056d3a7@mail.gmail.com> Date: Thu, 2 Mar 2006 08:55:51 +0800 From: zhuzhenhua To: "Martin Michlmayr" Subject: Re: how to select a rootfs for embedded linux based hardisk? Cc: linux-mips In-Reply-To: <20060301124341.GM24493@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Content-Disposition: inline References: <50c9a2250603010418s6f778c25s799d79cee2b79333@mail.gmail.com> <20060301124341.GM24493@deprecation.cyrius.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10715 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zzh.hust@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1029 Lines: 26 On 3/1/06, Martin Michlmayr wrote: > * zhuzhenhua [2006-03-01 20:18]: > > i want to port the linux to our board based hardisk with > > mips arch. i do not find too much file sytem for rootfs on hardisk > > besides ext2/ext3. > > but it seems ext2/ext3 is not suitable for embedded system. > > does someone have idea or experience with these products? > > How large is your hard drive exactly and is it a real IDE hard drive > or some kind of flash? If the disk/flash is very small, ext3 may be a > bad choice since it's a journalling file system which means that a) > it'll take up quite a significant portion of space on a small drive > and b) it'll write to the same sectors all the time, which will kill > the flash in no time. > -- > Martin Michlmayr > http://www.cyrius.com/ > i mean the real IDE hard, and it will at least > 2GB,and for these ide hard,someone said the ext2 or ext3 not suitable for embedded.but i still find no other file system available. Best Regards Zhuzhenhua From tbm@cyrius.com Thu Mar 2 00:51:16 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 00:51:24 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:61199 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133716AbWCBAvQ (ORCPT ); Thu, 2 Mar 2006 00:51:16 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 9C08E64D3D; Thu, 2 Mar 2006 00:59:07 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 2DD138545; Thu, 2 Mar 2006 01:59:00 +0100 (CET) Date: Thu, 2 Mar 2006 00:59:00 +0000 From: Martin Michlmayr To: zhuzhenhua Cc: linux-mips Subject: Re: how to select a rootfs for embedded linux based hardisk? Message-ID: <20060302005900.GE4118@deprecation.cyrius.com> References: <50c9a2250603010418s6f778c25s799d79cee2b79333@mail.gmail.com> <20060301124341.GM24493@deprecation.cyrius.com> <50c9a2250603011655m4a61c262v41898d496056d3a7@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50c9a2250603011655m4a61c262v41898d496056d3a7@mail.gmail.com> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10716 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 245 Lines: 8 * zhuzhenhua [2006-03-02 08:55]: > i mean the real IDE hard, and it will at least > 2GB,and for these ide > hard,someone said the ext2 or ext3 not suitable for embedded. Why not? -- Martin Michlmayr http://www.cyrius.com/ From cklai@itri.org.tw Thu Mar 2 02:44:14 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 02:44:33 +0000 (GMT) Received: from maillog.itri.org.tw ([61.61.254.20]:44971 "EHLO maillog.itri.org.tw") by ftp.linux-mips.org with ESMTP id S8133727AbWCBCoO (ORCPT ); Thu, 2 Mar 2006 02:44:14 +0000 Received: from mail.itri.org.tw (mail [140.96.157.2]) by maillog.itri.org.tw (8.11.6+Sun/8.11.6) with ESMTP id k222kpg16124 for ; Thu, 2 Mar 2006 10:46:56 +0800 (CST) Received: from mail.itri.org.tw (localhost [127.0.0.1]) by mail.itri.org.tw (8.13.4/8.13.4) with ESMTP id k222u05P020946 for ; Thu, 2 Mar 2006 10:56:10 +0800 (CST) Received: from ms4.itri.org.tw ([140.96.151.44]) by mail.itri.org.tw (8.13.4/8.13.4) with ESMTP id k222taHn020771 for ; Thu, 2 Mar 2006 10:56:00 +0800 (CST) Received: from 11088002601 ([140.96.151.160]) by ms4.itri.org.tw (Lotus Domino Release 5.0.13a) with ESMTP id 2006030210511299:40494 ; Thu, 2 Mar 2006 10:51:12 +0800 Message-ID: <03a101c63da4$2b119020$8873608c@11088002601> Reply-To: "Charles C.K.Lai" From: "Charles C.K.Lai" To: Subject: Initramfs on AMD DB1550 Board Date: Thu, 2 Mar 2006 10:51:02 +0800 Organization: N300 ICL/ITRI MIME-Version: 1.0 X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2900.2527 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2527 X-MIMETrack: Itemize by SMTP Server on MS4/ITRI(Release 5.0.13a |April 8, 2004) at 2006-03-02 10:51:13 AM, Serialize by Router on MS4/ITRI(Release 5.0.13a |April 8, 2004) at 2006-03-02 10:51:38 AM, Serialize complete at 2006-03-02 10:51:38 AM Content-Type: multipart/alternative; boundary="----=_NextPart_000_0399_01C63DE7.329F2CB0" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10717 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cklai@itri.org.tw Precedence: bulk X-list: linux-mips Content-Length: 7450 Lines: 177 This is a multi-part message in MIME format. ------=_NextPart_000_0399_01C63DE7.329F2CB0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="big5" I downloaded kernel 2.6.14 from Linux-MIPS, and compiled with gcc-3.4.4 and mipssde-6.02.03 toolchain. I put the target directory at /init, run gen_initramfs_list.sh with /init to a text file, and assigned this text file to the initrd for cpio. After compiled, loaded, and ran, I got the message below, Would someone tell me how to set the root parameter? Thanks a lot! ========================================================================================================= Linux version 2.6.14 (gcc version 3.4.4 mipssde-6.02.03-20050626CPU revision is: 03030200 AMD Alchemy Au1550/Db1550 Board (PRId 03030200) @ 396MHZ BCLK switching enabled! Determined physical RAM map: memory: 0c000000 @ 00000000 (usable) Built 1 zonelists Kernel command line: ln -s /linuxrc /init console=ttyS0,115200 Primary instruction cache 16kB, physically tagged, 4-way, linesize 32 bytes. Primary data cache 16kB, 4-way, linesize 32 bytes. Synthesized TLB refill handler (17 instructions). Synthesized TLB load handler fastpath (34 instructions). Synthesized TLB store handler fastpath (34 instructions). Synthesized TLB modify handler fastpath (33 instructions). PID hash table entries: 1024 (order: 10, 16384 bytes) calculating r4koff... 00060ae0(396000) CPU frequency 396.00 MHz Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) Memory: 187268k/196608k available (1952k kernel code, 9056k reserved, 323k data)Mount-cache hash table entries: 512 Checking for 'wait' instruction... unavailable. NET: Registered protocol family 16 Serial: Au1x00 driver ttyS0 at I/O 0xb1100000 (irq = 0) is a AU1X00_UART ttyS1 at I/O 0xb1200000 (irq = 8) is a AU1X00_UART ttyS2 at I/O 0xb1400000 (irq = 9) is a AU1X00_UART io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize loop: loaded (max 8 devices) au1000eth version 1.5 Pete Popov eth0: Au1x Ethernet found at 0xb0500000, irq 27 eth0: AMD 79C874 10/100 BaseT PHY at phy address 31 eth0: Using AMD 79C874 10/100 BaseT PHY as default eth1: Au1x Ethernet found at 0xb0510000, irq 28 eth1: AMD 79C874 10/100 BaseT PHY at phy address 31 eth1: Using AMD 79C874 10/100 BaseT PHY as default mice: PS/2 mouse device common for all mice NET: Registered protocol family 2 IP route cache hash table entries: 2048 (order: 1, 8192 bytes) TCP established hash table entries: 8192 (order: 3, 32768 bytes) TCP bind hash table entries: 8192 (order: 3, 32768 bytes) TCP: Hash tables configured (established 8192 bind 8192) TCP reno registered TCP bic registered NET: Registered protocol family 1 NET: Registered protocol family 17 NET: Registered protocol family 15 VFS: Cannot open root device "" or unknown-block(1,0) Please append a correct "root=" boot option Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(1,0) ------=_NextPart_000_0399_01C63DE7.329F2CB0 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset="big5"
I downloaded kernel 2.6.14 from Linux-MIPS,
and compiled with gcc-3.4.4 and mipssde-6.02.03 = toolchain.
 
I put the target directory at /init,
run gen_initramfs_list.sh with /init to a text file,
and assigned this text file to the initrd for cpio.
 
After compiled, loaded, and ran,
I got the message below,
Would someone tell me how to set the root parameter?
Thanks a lot!
 
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D
 
Linux version 2.6.14 (gcc version 3.4.4 mipssde-6.02.03-20050626CPU = revision is: 03030200
AMD Alchemy Au1550/Db1550 Board
(PRId = 03030200) @=20 396MHZ
BCLK switching enabled!
Determined physical RAM=20 map:
 memory: 0c000000 @ 00000000 (usable)
Built 1=20 zonelists
Kernel command line: ln -s /linuxrc /init=20 console=3DttyS0,115200
Primary instruction cache 16kB, physically = tagged,=20 4-way, linesize 32 bytes.
Primary data cache 16kB, 4-way, linesize 32 = bytes.
Synthesized TLB refill handler (17 = instructions).
Synthesized TLB=20 load handler fastpath (34 instructions).
Synthesized TLB store = handler=20 fastpath (34 instructions).
Synthesized TLB modify handler fastpath = (33=20 instructions).
PID hash table entries: 1024 (order: 10, 16384=20 bytes)
calculating r4koff... 00060ae0(396000)
CPU frequency 396.00 = MHz
Dentry cache hash table entries: 32768 (order: 5, 131072=20 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536=20 bytes)
Memory: 187268k/196608k available (1952k kernel code, 9056k = reserved,=20 323k data)Mount-cache hash table entries: 512
Checking for 'wait'=20 instruction...  unavailable.
NET: Registered protocol family=20 16
Serial: Au1x00 driver
ttyS0 at I/O 0xb1100000 (irq =3D 0) is a=20 AU1X00_UART
ttyS1 at I/O 0xb1200000 (irq =3D 8) is a = AU1X00_UART
ttyS2 at=20 I/O 0xb1400000 (irq =3D 9) is a AU1X00_UART
io scheduler noop = registered
io=20 scheduler anticipatory registered
io scheduler deadline = registered
io=20 scheduler cfq registered
RAMDISK driver initialized: 16 RAM disks of = 8192K=20 size 1024 blocksize
loop: loaded (max 8 devices)
au1000eth version = 1.5=20 Pete Popov <ppopov@embeddedalley.com>=
eth0:=20 Au1x Ethernet found at 0xb0500000, irq 27
eth0: AMD 79C874 10/100 = BaseT PHY=20 at phy address 31
eth0: Using AMD 79C874 10/100 BaseT PHY as = default
eth1:=20 Au1x Ethernet found at 0xb0510000, irq 28
eth1: AMD 79C874 10/100 = BaseT PHY=20 at phy address 31
eth1: Using AMD 79C874 10/100 BaseT PHY as = default
mice:=20 PS/2 mouse device common for all mice
NET: Registered protocol family = 2
IP=20 route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP = established=20 hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table = entries:=20 8192 (order: 3, 32768 bytes)
TCP: Hash tables configured (established = 8192=20 bind 8192)
TCP reno registered
TCP bic registered
NET: = Registered=20 protocol family 1
NET: Registered protocol family 17
NET: = Registered=20 protocol family 15
VFS: Cannot open root device "<NULL>" or=20 unknown-block(1,0)
Please append a correct "root=3D" boot = option
Kernel=20 panic - not syncing: VFS: Unable to mount root fs on=20 unknown-block(1,0)
------=_NextPart_000_0399_01C63DE7.329F2CB0-- From jonah@omegav.ntnu.no Thu Mar 2 11:52:39 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 11:52:48 +0000 (GMT) Received: from fri.itea.ntnu.no ([129.241.7.60]:8386 "EHLO fri.itea.ntnu.no") by ftp.linux-mips.org with ESMTP id S8133394AbWCBLwj (ORCPT ); Thu, 2 Mar 2006 11:52:39 +0000 Received: from localhost (localhost [127.0.0.1]) by fri.itea.ntnu.no (Postfix) with ESMTP id EECEC8330; Thu, 2 Mar 2006 13:00:29 +0100 (CET) Received: from invalid.ed.ntnu.no (invalid.ed.ntnu.no [129.241.205.150]) by fri.itea.ntnu.no (Postfix) with ESMTP; Thu, 2 Mar 2006 13:00:28 +0100 (CET) Received: from invalid.ed.ntnu.no (jonah@localhost.ed.ntnu.no [127.0.0.1]) by invalid.ed.ntnu.no (8.13.3/8.13.3) with ESMTP id k22C0SM2081339 (version=TLSv1/SSLv3 cipher=DHE-DSS-AES256-SHA bits=256 verify=NO); Thu, 2 Mar 2006 13:00:28 +0100 (CET) (envelope-from jonah@omegav.ntnu.no) Received: from localhost (jonah@localhost) by invalid.ed.ntnu.no (8.13.3/8.13.3/Submit) with ESMTP id k22C0RpS081336; Thu, 2 Mar 2006 13:00:28 +0100 (CET) (envelope-from jonah@omegav.ntnu.no) X-Authentication-Warning: invalid.ed.ntnu.no: jonah owned process doing -bs Date: Thu, 2 Mar 2006 13:00:27 +0100 (CET) From: Jon Anders Haugum X-X-Sender: jonah@invalid.ed.ntnu.no To: Jordan Crouse Cc: linux-serial@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] Fix compile error in 8250_au1x00.c In-Reply-To: <20060207211500.GC5227@cosmic.amd.com> Message-ID: <20060302124634.T81066@invalid.ed.ntnu.no> References: <20060207211500.GC5227@cosmic.amd.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed X-Content-Scanned: with sophos and spamassassin at mailgw.ntnu.no. Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10718 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonah@omegav.ntnu.no Precedence: bulk X-list: linux-mips Content-Length: 911 Lines: 25 On Tue, 7 Feb 2006, Jordan Crouse wrote: > There are additional rumors of strangeness on the DB1550, but those > are unsubstantiated at this point. At least with this patch, it will > compile. I can confirm strangeness on Au1550, and I've pinned it down to wrong way of setting the divisor register. The alchemy uart have got a spearate register for divisor, while the driver tries to set the divisor latch just like on any 16550 uart. How would be a good way of solving this? I can imagine a couple of ways: 1. Make divisor latch read/write a bit more abstract, so that a alternative function can be used for alchemy. 2. Add divisor latch to the alchemy uart register map. But since the divisor register is located in a single 32-bit register and the driver will try to access it one byte at a time; byte access would be needed. And this would add some endian handling... -- Jon Anders Haugum From ralf@linux-mips.org Thu Mar 2 15:31:08 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 15:31:17 +0000 (GMT) Received: from mipsfw.mips-uk.com ([194.74.144.146]:21785 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133787AbWCBPbI (ORCPT ); Thu, 2 Mar 2006 15:31:08 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k22FXjRw010734; Thu, 2 Mar 2006 15:33:45 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k22FXils010733; Thu, 2 Mar 2006 15:33:44 GMT Date: Thu, 2 Mar 2006 15:33:44 +0000 From: Ralf Baechle To: Jordan Crouse Cc: linux-usb-devel@lists.sourceforge.net, linux-mips@linux-mips.org, gregkh@suse.de, tbm@cyrius.com Subject: Re: [PATCH] Buglet in Alchemy OHCI driver Message-ID: <20060302153344.GA8487@linux-mips.org> References: <20060301183026.GL31957@cosmic.amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060301183026.GL31957@cosmic.amd.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10719 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 543 Lines: 15 On Wed, Mar 01, 2006 at 11:30:26AM -0700, Jordan Crouse wrote: > Date: Wed, 1 Mar 2006 11:30:26 -0700 > From: "Jordan Crouse" > To: linux-usb-devel@lists.sourceforge.net > cc: linux-mips@linux-mips.org, gregkh@suse.de, tbm@cyrius.com > Subject: [PATCH] Buglet in Alchemy OHCI driver > Content-Type: multipart/mixed; > boundary=5vNYLRcllDrimb99 > > Martin Michlmayr spotted this potentially serious bug. Please apply. Ehh... This problem doesn't exist on kernel.org. Greg, can you ignore this one, please? Ralf From ralf@linux-mips.org Thu Mar 2 16:03:44 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 16:03:53 +0000 (GMT) Received: from mipsfw.mips-uk.com ([194.74.144.146]:39172 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133791AbWCBQDo (ORCPT ); Thu, 2 Mar 2006 16:03:44 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k22GBabQ012532 for ; Thu, 2 Mar 2006 16:11:36 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k22GBaeh012531 for linux-mips@linux-mips.org; Thu, 2 Mar 2006 16:11:36 GMT Date: Thu, 2 Mar 2006 16:11:36 +0000 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: DDB5074 and DDB5476 eval boards Message-ID: <20060302161136.GA12460@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10720 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 259 Lines: 6 Both boards don't compile anymore since include/linux/kbd_ll.h was removed and nobody did complain making them perfect candidates for somebody who either wants to take over maintenance or alternatively, removal of the code. Anybody still interested? Ralf From geert@linux-m68k.org Thu Mar 2 16:11:03 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 16:11:14 +0000 (GMT) Received: from witte.sonytel.be ([80.88.33.193]:3766 "EHLO witte.sonytel.be") by ftp.linux-mips.org with ESMTP id S8133791AbWCBQLD (ORCPT ); Thu, 2 Mar 2006 16:11:03 +0000 Received: from pademelon.sonytel.be (mail.sonytel.be [43.221.60.197]) by witte.sonytel.be (8.12.10/8.12.10) with ESMTP id k22GIxlR008322; Thu, 2 Mar 2006 17:18:59 +0100 (MET) Date: Thu, 2 Mar 2006 17:18:59 +0100 (CET) From: Geert Uytterhoeven To: Ralf Baechle cc: Linux/MIPS Development Subject: Re: DDB5074 and DDB5476 eval boards In-Reply-To: <20060302161136.GA12460@linux-mips.org> Message-ID: References: <20060302161136.GA12460@linux-mips.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10721 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Content-Length: 736 Lines: 19 On Thu, 2 Mar 2006, Ralf Baechle wrote: > Both boards don't compile anymore since include/linux/kbd_ll.h was removed > and nobody did complain making them perfect candidates for somebody who > either wants to take over maintenance or alternatively, removal of the > code. Anybody still interested? Since I finally moved last week, I hope to have more spare time in the future and revive my DDB5074. So please don't remove it yet. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From greg@kroah.org Thu Mar 2 16:21:42 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 16:21:52 +0000 (GMT) Received: from dsl093-040-174.pdx1.dsl.speakeasy.net ([66.93.40.174]:7897 "EHLO aria.kroah.org") by ftp.linux-mips.org with ESMTP id S8133795AbWCBQVm (ORCPT ); Thu, 2 Mar 2006 16:21:42 +0000 Received: from press.kroah.org ([192.168.0.25] helo=localhost) by aria.kroah.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.54) id 1FEqff-0007m0-HV; Thu, 02 Mar 2006 08:28:55 -0800 Date: Thu, 2 Mar 2006 08:28:51 -0800 From: Greg KH To: Ralf Baechle Cc: Jordan Crouse , linux-usb-devel@lists.sourceforge.net, linux-mips@linux-mips.org, tbm@cyrius.com Subject: Re: [PATCH] Buglet in Alchemy OHCI driver Message-ID: <20060302162851.GA30455@suse.de> References: <20060301183026.GL31957@cosmic.amd.com> <20060302153344.GA8487@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060302153344.GA8487@linux-mips.org> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10722 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Content-Length: 666 Lines: 20 On Thu, Mar 02, 2006 at 03:33:44PM +0000, Ralf Baechle wrote: > On Wed, Mar 01, 2006 at 11:30:26AM -0700, Jordan Crouse wrote: > > Date: Wed, 1 Mar 2006 11:30:26 -0700 > > From: "Jordan Crouse" > > To: linux-usb-devel@lists.sourceforge.net > > cc: linux-mips@linux-mips.org, gregkh@suse.de, tbm@cyrius.com > > Subject: [PATCH] Buglet in Alchemy OHCI driver > > Content-Type: multipart/mixed; > > boundary=5vNYLRcllDrimb99 > > > > Martin Michlmayr spotted this potentially serious bug. Please apply. > > Ehh... This problem doesn't exist on kernel.org. Greg, can you ignore > this one, please? Consider it ignored :) thanks, greg k-h From ralf@linux-mips.org Thu Mar 2 16:22:21 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 16:22:35 +0000 (GMT) Received: from mipsfw.mips-uk.com ([194.74.144.146]:263 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133801AbWCBQWQ (ORCPT ); Thu, 2 Mar 2006 16:22:16 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k22GTgWb013062; Thu, 2 Mar 2006 16:29:42 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k22GTgA8013061; Thu, 2 Mar 2006 16:29:42 GMT Date: Thu, 2 Mar 2006 16:29:42 +0000 From: Ralf Baechle To: Geert Uytterhoeven Cc: Linux/MIPS Development Subject: Re: DDB5074 and DDB5476 eval boards Message-ID: <20060302162942.GB8487@linux-mips.org> References: <20060302161136.GA12460@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10723 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 788 Lines: 19 On Thu, Mar 02, 2006 at 05:18:59PM +0100, Geert Uytterhoeven wrote: > On Thu, 2 Mar 2006, Ralf Baechle wrote: > > Both boards don't compile anymore since include/linux/kbd_ll.h was removed > > and nobody did complain making them perfect candidates for somebody who > > either wants to take over maintenance or alternatively, removal of the > > code. Anybody still interested? > > Since I finally moved last week, I hope to have more spare time in the future > and revive my DDB5074. So please don't remove it yet. If anything I'd be planning to remove the code after 2.6.17 has been released which would leave several months. But of course until then you and Peter De Schrijver who also raised his hand for the DDB5074 will have fixed things ;-) Any takers for the DDB5476? Ralf From geoffrey.levand@am.sony.com Thu Mar 2 17:02:30 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 17:02:44 +0000 (GMT) Received: from mail8.fw-bc.sony.com ([160.33.98.75]:47869 "EHLO mail8.fw-bc.sony.com") by ftp.linux-mips.org with ESMTP id S8133799AbWCBRCa (ORCPT ); Thu, 2 Mar 2006 17:02:30 +0000 Received: from mail3.sjc.in.sel.sony.com (mail3.sjc.in.sel.sony.com [43.134.1.211]) by mail8.fw-bc.sony.com (8.12.11/8.12.11) with ESMTP id k22HAHBF009283; Thu, 2 Mar 2006 17:10:18 GMT Received: from [192.168.1.10] ([43.134.85.105]) by mail3.sjc.in.sel.sony.com (8.12.11/8.12.11) with ESMTP id k22HAHMr018391; Thu, 2 Mar 2006 17:10:17 GMT Message-ID: <440726F9.7090000@am.sony.com> Date: Thu, 02 Mar 2006 09:10:17 -0800 From: Geoff Levand User-Agent: Mozilla Thunderbird 1.0.7-1.1.fc4 (X11/20050929) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Ralf Baechle CC: Geert Uytterhoeven , Linux/MIPS Development Subject: Re: DDB5074 and DDB5476 eval boards References: <20060302161136.GA12460@linux-mips.org> <20060302162942.GB8487@linux-mips.org> In-Reply-To: <20060302162942.GB8487@linux-mips.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10724 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geoffrey.levand@am.sony.com Precedence: bulk X-list: linux-mips Content-Length: 996 Lines: 25 Ralf Baechle wrote: > On Thu, Mar 02, 2006 at 05:18:59PM +0100, Geert Uytterhoeven wrote: > >> On Thu, 2 Mar 2006, Ralf Baechle wrote: >> > Both boards don't compile anymore since include/linux/kbd_ll.h was removed >> > and nobody did complain making them perfect candidates for somebody who >> > either wants to take over maintenance or alternatively, removal of the >> > code. Anybody still interested? >> >> Since I finally moved last week, I hope to have more spare time in the future >> and revive my DDB5074. So please don't remove it yet. > > If anything I'd be planning to remove the code after 2.6.17 has been > released which would leave several months. But of course until then > you and Peter De Schrijver who also raised his hand for the DDB5074 > will have fixed things ;-) > > Any takers for the DDB5476? > I have a DDB5476, and if someone wants to maintain the code, can help with testing, etc. I was just thinking of throwing it in the trash a week or so ago... -Geoff From jb@jblache.org Thu Mar 2 21:15:59 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 21:16:12 +0000 (GMT) Received: from sardaukar.technologeek.org ([213.41.134.240]:17024 "EHLO frigate.technologeek.org") by ftp.linux-mips.org with ESMTP id S8133815AbWCBVP5 (ORCPT ); Thu, 2 Mar 2006 21:15:57 +0000 Received: by frigate.technologeek.org (Postfix, from userid 1000) id 86B011474E17; Thu, 2 Mar 2006 22:23:39 +0100 (CET) From: Julien BLACHE To: Michael Dosser Cc: linux-mips@linux-mips.org Subject: Re: MIPS kernel status as of 2.6.16-rc5 References: <20060228214144.GA6615@deprecation.cyrius.com> <20060301100817.GB928@nethack.at> Date: Thu, 02 Mar 2006 22:23:39 +0100 In-Reply-To: <20060301100817.GB928@nethack.at> (Michael Dosser's message of "Wed, 1 Mar 2006 11:08:18 +0100") Message-ID: <87d5h4wnfo.fsf@frigate.technologeek.org> User-Agent: Gnus/5.110004 (No Gnus v0.4) XEmacs/21.4.17 (linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10725 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jb@jblache.org Precedence: bulk X-list: linux-mips Content-Length: 878 Lines: 24 Michael Dosser wrote: Hi, >> - IP22: Indigo2 with > 256 MB fails to boot (regression from 2.4; >> while 2.4 would only see 256 MB, it would at least boot) > > Is there a chance, that even if it would boot with > 256 MB linux could > actually use all 384 MB of RAM? If not, does anybody know why and can > explain it (I am no kernel developer and know only very little about the > I2 hardware)? IIRC, a discontig memory implementation is needed for the I2 to use more than 256 MB, due to the memory layout on this machine (with aliased memory etc -- see the R3000 MC spec). I kind of lost track of this issue recently, so I may have forgotten some details and got part of the above totally wrong :) JB. -- Julien BLACHE GPG KeyID 0xF5D65169 From tbm@cyrius.com Thu Mar 2 22:20:27 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 22:20:36 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:45320 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133813AbWCBWU1 (ORCPT ); Thu, 2 Mar 2006 22:20:27 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id EFD1A64D3E; Thu, 2 Mar 2006 22:28:21 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 7981292E8; Thu, 2 Mar 2006 23:27:52 +0100 (CET) Date: Thu, 2 Mar 2006 22:27:52 +0000 From: Martin Michlmayr To: linux-mips@linux-mips.org Cc: mark.e.mason@broadcom.com Subject: 1480: duart0: 1 input overrun(s) Message-ID: <20060302222752.GA27348@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10726 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 255 Lines: 10 I get errors such as the following when copy&pasting something into my screen session which is connected at 115200 to the serial console of my 1480 board: duart0: 1 input overrun(s) duart0: 4 input overrun(s) -- Martin Michlmayr http://www.cyrius.com/ From dan.mcgee@ntsoc.com Thu Mar 2 23:37:28 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Mar 2006 23:37:37 +0000 (GMT) Received: from xrelay03.mail2web.com ([168.144.1.54]:42963 "EHLO xrelay03.mail2web.com") by ftp.linux-mips.org with ESMTP id S8133813AbWCBXh2 convert rfc822-to-8bit (ORCPT ); Thu, 2 Mar 2006 23:37:28 +0000 Received: from [168.144.251.152] (helo=M2W046.mail2web.com) by xrelay03.mail2web.com with smtp (Exim 4.50) id 1FExTz-0005Pu-Ih for linux-mips@linux-mips.org; Thu, 02 Mar 2006 18:45:20 -0500 Message-ID: <380-22006342234519512@M2W046.mail2web.com> X-Priority: 3 Reply-To: dan.mcgee@ntsoc.com X-Originating-IP: 64.241.199.88 X-URL: http://mail2web.com/ From: "dan.mcgee@ntsoc.com" To: linux-mips@linux-mips.org Date: Thu, 2 Mar 2006 18:45:19 -0500 MIME-Version: 1.0 Content-type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Subject: nfs network timeout on bcm1480 BigSur Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10727 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan.mcgee@ntsoc.com Precedence: bulk X-list: linux-mips Content-Length: 883 Lines: 22 With kernel 2.6.15 from linux-mips respository. I'm seeing a nfs server timeout error, during heavy network traffic. Example make -j 5 will lock the system up anywhere from 3 to 15 minutes after start the make process. I built the kernel with the default arch/mips/configs/bigsur_defconfig. I have tried to increase the RPC timeout, which didn't help. The following is the output from the console before the network locks up. 172.22.250.195 login: [4295020.091000] nfs: server 172.22.250.78 not respondingg[4295021.251000] nfs: server 172.22.250.78 not responding, still trying [4295038.852000] nfs: server 172.22.250.78 not responding, still trying [4295056.452000] nfs: server 172.22.250.78 not responding, still trying Thanks Dan McGee. -------------------------------------------------------------------- mail2web - Check your email from the web at http://mail2web.com/ . From paulus@ozlabs.org Fri Mar 3 03:58:45 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Mar 2006 03:58:53 +0000 (GMT) Received: from ozlabs.org ([203.10.76.45]:58794 "EHLO ozlabs.org") by ftp.linux-mips.org with ESMTP id S8133825AbWCCD6p (ORCPT ); Fri, 3 Mar 2006 03:58:45 +0000 Received: by ozlabs.org (Postfix, from userid 1003) id E8B4467A04; Fri, 3 Mar 2006 15:06:40 +1100 (EST) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <17415.49336.31224.641069@cargo.ozlabs.ibm.com> Date: Fri, 3 Mar 2006 15:06:16 +1100 From: Paul Mackerras To: Atsushi Nemoto Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, akpm@osdl.org Subject: Re: jiffies_64 vs. jiffies In-Reply-To: <20060301.144442.118975101.nemoto@toshiba-tops.co.jp> References: <20060301.144442.118975101.nemoto@toshiba-tops.co.jp> X-Mailer: VM 7.19 under Emacs 21.4.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10728 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paulus@samba.org Precedence: bulk X-list: linux-mips Content-Length: 626 Lines: 18 Atsushi Nemoto writes: > Hi. I noticed that the 'jiffies' variable has 'wall_jiffies + 1' > value in most of time. I'm using MIPS platform but I think this is > same for other platforms. > > I suppose this is due to gcc does not know that jiffies_64 and jiffies > share same place. I can confirm that the same thing happens on powerpc, both 32-bit and 64-bit. The compiler loads up jiffies, jiffies_64 and wall_jiffies into registers before storing back the incremented value into jiffies_64 and then updating wall_jiffies. Thanks for finding that, it explains some other strange things that I have seen happen. Paul. From jonah@omegav.ntnu.no Fri Mar 3 13:48:42 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Mar 2006 13:48:51 +0000 (GMT) Received: from merke.itea.ntnu.no ([129.241.7.61]:64709 "EHLO merke.itea.ntnu.no") by ftp.linux-mips.org with ESMTP id S8133432AbWCCNsm (ORCPT ); Fri, 3 Mar 2006 13:48:42 +0000 Received: from localhost (localhost [127.0.0.1]) by merke.itea.ntnu.no (Postfix) with ESMTP id 91DD313C667; Fri, 3 Mar 2006 14:56:42 +0100 (CET) Received: from invalid.ed.ntnu.no (invalid.ed.ntnu.no [129.241.205.150]) by merke.itea.ntnu.no (Postfix) with ESMTP; Fri, 3 Mar 2006 14:56:42 +0100 (CET) Received: from invalid.ed.ntnu.no (jonah@localhost.ed.ntnu.no [127.0.0.1]) by invalid.ed.ntnu.no (8.13.3/8.13.3) with ESMTP id k23DugO1096506 (version=TLSv1/SSLv3 cipher=DHE-DSS-AES256-SHA bits=256 verify=NO); Fri, 3 Mar 2006 14:56:42 +0100 (CET) (envelope-from jonah@omegav.ntnu.no) Received: from localhost (jonah@localhost) by invalid.ed.ntnu.no (8.13.3/8.13.3/Submit) with ESMTP id k23DuctF096503; Fri, 3 Mar 2006 14:56:41 +0100 (CET) (envelope-from jonah@omegav.ntnu.no) X-Authentication-Warning: invalid.ed.ntnu.no: jonah owned process doing -bs Date: Fri, 3 Mar 2006 14:56:38 +0100 (CET) From: Jon Anders Haugum X-X-Sender: jonah@invalid.ed.ntnu.no To: rmk+serial@arm.linux.org.uk Cc: linux-serial@vger.kernel.org, linux-mips@linux-mips.org Subject: [PATCH] serial8250: set divisor register correctly for AMD Alchemy SoC uart Message-ID: <20060303140428.T96056@invalid.ed.ntnu.no> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed X-Content-Scanned: with sophos and spamassassin at mailgw.ntnu.no. Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10729 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jonah@omegav.ntnu.no Precedence: bulk X-list: linux-mips Content-Length: 4527 Lines: 145 Alchemy SoC uart have got a non-standard divisor register that needs some special handling. This patch adds divisor read/write functions with test and special handling for Alchemy internal uart. Signed-off-by: Jon Anders Haugum --- --- linux-2.6.16-rc5/drivers/serial/8250.c.orig 2006-03-03 02:12:10.000000000 +0100 +++ linux-2.6.16-rc5/drivers/serial/8250.c 2006-03-03 02:16:19.000000000 +0100 @@ -362,6 +362,40 @@ serial_out(struct uart_8250_port *up, in #define serial_inp(up, offset) serial_in(up, offset) #define serial_outp(up, offset, value) serial_out(up, offset, value) +/* Uart divisor latch read */ +static inline int _serial_dl_read(struct uart_8250_port *up) +{ + return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8; +} + +/* Uart divisor latch write */ +static inline void _serial_dl_write(struct uart_8250_port *up, int value) +{ + serial_outp(up, UART_DLL, value & 0xff); + serial_outp(up, UART_DLM, value >> 8 & 0xff); +} + +#ifdef CONFIG_SERIAL_8250_AU1X00 +/* Au1x00 haven't got a standard divisor latch */ +static int serial_dl_read(struct uart_8250_port *up) +{ + if (up->port.iotype == UPIO_AU) + return __raw_readl(up->port.membase + 0x28); + else + return _serial_dl_read(up); +} + +static void serial_dl_write(struct uart_8250_port *up, int value) +{ + if (up->port.iotype == UPIO_AU) + __raw_writel(value, up->port.membase + 0x28); + else + _serial_dl_write(up, value); +} +#else +#define serial_dl_read(up) _serial_dl_read(up) +#define serial_dl_write(up, value) _serial_dl_write(up, value) +#endif /* * For the 16C950 @@ -494,7 +528,8 @@ static void disable_rsa(struct uart_8250 */ static int size_fifo(struct uart_8250_port *up) { - unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr; + unsigned char old_fcr, old_mcr, old_lcr; + unsigned short old_dl; int count; old_lcr = serial_inp(up, UART_LCR); @@ -505,10 +540,8 @@ static int size_fifo(struct uart_8250_po UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); serial_outp(up, UART_MCR, UART_MCR_LOOP); serial_outp(up, UART_LCR, UART_LCR_DLAB); - old_dll = serial_inp(up, UART_DLL); - old_dlm = serial_inp(up, UART_DLM); - serial_outp(up, UART_DLL, 0x01); - serial_outp(up, UART_DLM, 0x00); + old_dl = serial_dl_read(up); + serial_dl_write(up, 0x0001); serial_outp(up, UART_LCR, 0x03); for (count = 0; count < 256; count++) serial_outp(up, UART_TX, count); @@ -519,8 +552,7 @@ static int size_fifo(struct uart_8250_po serial_outp(up, UART_FCR, old_fcr); serial_outp(up, UART_MCR, old_mcr); serial_outp(up, UART_LCR, UART_LCR_DLAB); - serial_outp(up, UART_DLL, old_dll); - serial_outp(up, UART_DLM, old_dlm); + serial_dl_write(up, old_dl); serial_outp(up, UART_LCR, old_lcr); return count; @@ -533,22 +565,20 @@ static int size_fifo(struct uart_8250_po */ static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) { - unsigned char old_dll, old_dlm, old_lcr; + unsigned char old_lcr; unsigned int id; + unsigned short old_dl; old_lcr = serial_inp(p, UART_LCR); serial_outp(p, UART_LCR, UART_LCR_DLAB); - old_dll = serial_inp(p, UART_DLL); - old_dlm = serial_inp(p, UART_DLM); + old_dl = serial_dl_read(p); - serial_outp(p, UART_DLL, 0); - serial_outp(p, UART_DLM, 0); + serial_dl_write(p, 0); - id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8; + id = serial_dl_read(p); - serial_outp(p, UART_DLL, old_dll); - serial_outp(p, UART_DLM, old_dlm); + serial_dl_write(p, old_dl); serial_outp(p, UART_LCR, old_lcr); return id; @@ -750,8 +780,7 @@ static void autoconfig_16550a(struct uar serial_outp(up, UART_LCR, 0xE0); - quot = serial_inp(up, UART_DLM) << 8; - quot += serial_inp(up, UART_DLL); + quot = serial_dl_read(up); quot <<= 3; status1 = serial_in(up, 0x04); /* EXCR1 */ @@ -759,8 +788,7 @@ static void autoconfig_16550a(struct uar status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ serial_outp(up, 0x04, status1); - serial_outp(up, UART_DLL, quot & 0xff); - serial_outp(up, UART_DLM, quot >> 8); + serial_dl_write(up, quot); serial_outp(up, UART_LCR, 0); @@ -1862,8 +1890,7 @@ serial8250_set_termios(struct uart_port serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ } - serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */ - serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */ + serial_dl_write(up, quot); /* * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR From zzh.hust@gmail.com Sun Mar 5 06:09:45 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Mar 2006 06:09:53 +0000 (GMT) Received: from nproxy.gmail.com ([64.233.182.201]:52727 "EHLO nproxy.gmail.com") by ftp.linux-mips.org with ESMTP id S8133462AbWCEGJp convert rfc822-to-8bit (ORCPT ); Sun, 5 Mar 2006 06:09:45 +0000 Received: by nproxy.gmail.com with SMTP id g2so659247nfe for ; Sat, 04 Mar 2006 22:17:56 -0800 (PST) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=p15KiSRI2McidAoPyVVkPETKZ/Oxw1BKQ7rbilAJZIawHJUmplIQrxYdcMMHIbq8mZwNn+e+EifWQ+QJ7ODwxCq1a327qT+4yLxHWOFr8kxbdjRzAkcfJiQjVxu9om57aKTYEHI+ee46VlmGQ8NZVvJ8nxTt9z6fyxNBJnGkQ8s= Received: by 10.48.225.15 with SMTP id x15mr1820036nfg; Sat, 04 Mar 2006 22:17:56 -0800 (PST) Received: by 10.48.249.14 with HTTP; Sat, 4 Mar 2006 22:17:56 -0800 (PST) Message-ID: <50c9a2250603042217l475e84pc9ab7ce87c40eb76@mail.gmail.com> Date: Sun, 5 Mar 2006 14:17:56 +0800 From: zhuzhenhua To: linux-mips Subject: does the linux support rootfs on vfat? MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10730 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zzh.hust@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 210 Lines: 8 if in my product based ide disk, i want to it to support the u-disk(with vfat fs), and can i set the root fs as vfat too? if use vfat as rootfs, what's disadvantage of the selection? Best Regards Zhuzhenhua From jbglaw@lug-owl.de Sun Mar 5 08:01:49 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Mar 2006 08:01:59 +0000 (GMT) Received: from lug-owl.de ([195.71.106.12]:17352 "EHLO lug-owl.de") by ftp.linux-mips.org with ESMTP id S8133469AbWCEIBt (ORCPT ); Sun, 5 Mar 2006 08:01:49 +0000 Received: by lug-owl.de (Postfix, from userid 1001) id 7E082F0040; Sun, 5 Mar 2006 09:09:58 +0100 (CET) Date: Sun, 5 Mar 2006 09:09:58 +0100 From: Jan-Benedict Glaw To: zhuzhenhua Cc: linux-mips Subject: Re: does the linux support rootfs on vfat? Message-ID: <20060305080958.GX19232@lug-owl.de> Mail-Followup-To: zhuzhenhua , linux-mips References: <50c9a2250603042217l475e84pc9ab7ce87c40eb76@mail.gmail.com> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="o7OlDVNVrpEggBeY" Content-Disposition: inline In-Reply-To: <50c9a2250603042217l475e84pc9ab7ce87c40eb76@mail.gmail.com> X-Operating-System: Linux mail 2.6.12.3lug-owl X-gpg-fingerprint: 250D 3BCF 7127 0D8C A444 A961 1DBD 5E75 8399 E1BB X-gpg-key: wwwkeys.de.pgp.net X-Echelon-Enable: howto poison arsenous mail psychological biological nuclear warfare test the bombastical terror of flooding the spy listeners explosion sex drugs and rock'n'roll X-TKUeV: howto poison arsenous mail psychological biological nuclear warfare test the bombastical terror of flooding the spy listeners explosion sex drugs and rock'n'roll User-Agent: Mutt/1.5.9i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10731 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jbglaw@lug-owl.de Precedence: bulk X-list: linux-mips Content-Length: 1277 Lines: 41 --o7OlDVNVrpEggBeY Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, 2006-03-05 14:17:56 +0800, zhuzhenhua wrote: > if in my product based ide disk, i want to it to support the > u-disk(with vfat fs), and can i set the root fs as vfat too? > if use vfat as rootfs, what's disadvantage of the selection? Well, most notably you won't have device nodes. Maybe a ram-backed filesystem mounted to /dev/ could solve that, but you'd probably need an initrd for that to do. MfG, JBG --=20 Jan-Benedict Glaw jbglaw@lug-owl.de . +49-172-7608481 = _ O _ "Eine Freie Meinung in einem Freien Kopf | Gegen Zensur | Gegen Krieg = _ _ O f=C3=BCr einen Freien Staat voll Freier B=C3=BCrger" | im Internet! | i= m Irak! O O O ret =3D do_actions((curr | FREE_SPEECH) & ~(NEW_COPYRIGHT_LAW | DRM | TCPA)= ); --o7OlDVNVrpEggBeY Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (GNU/Linux) iD8DBQFECpzWHb1edYOZ4bsRApTNAJ9nnHoDz7FlJRw/K4FZyI/yGATfsACcCWm4 Ld71XhQiljmHv++Nwzn/MPI= =YP6z -----END PGP SIGNATURE----- --o7OlDVNVrpEggBeY-- From ralf@linux-mips.org Sun Mar 5 11:14:51 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Mar 2006 11:14:59 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:57810 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133518AbWCELOv (ORCPT ); Sun, 5 Mar 2006 11:14:51 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k25BN08m004871; Sun, 5 Mar 2006 11:23:00 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k25BMll2004869; Sun, 5 Mar 2006 11:22:47 GMT Date: Sun, 5 Mar 2006 11:22:47 +0000 From: Ralf Baechle To: zhuzhenhua , linux-mips Subject: Re: does the linux support rootfs on vfat? Message-ID: <20060305112247.GA4243@linux-mips.org> References: <50c9a2250603042217l475e84pc9ab7ce87c40eb76@mail.gmail.com> <20060305080958.GX19232@lug-owl.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060305080958.GX19232@lug-owl.de> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10732 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 893 Lines: 18 On Sun, Mar 05, 2006 at 09:09:58AM +0100, Jan-Benedict Glaw wrote: > On Sun, 2006-03-05 14:17:56 +0800, zhuzhenhua wrote: > > if in my product based ide disk, i want to it to support the > > u-disk(with vfat fs), and can i set the root fs as vfat too? > > if use vfat as rootfs, what's disadvantage of the selection? > > Well, most notably you won't have device nodes. Maybe a ram-backed > filesystem mounted to /dev/ could solve that, but you'd probably need > an initrd for that to do. It's anso case-insensitive which may cause some further troubles. It's doesn't have proper inodes, no UNIX file modes, no UID / GID support (These two can be kludges in awfully insufficient way through mount options), not only lacks device special files but also no FIFO, no UNIX domain sockets, no hard or soft links. It's simply a sorry excuse for a useful filesystem. Ralf From anemo@mba.ocn.ne.jp Mon Mar 6 11:24:14 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Mar 2006 11:24:27 +0000 (GMT) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:11207 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S8133371AbWCFLYN (ORCPT ); Mon, 6 Mar 2006 11:24:13 +0000 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Mon, 6 Mar 2006 20:32:28 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 12BE1204EF; Mon, 6 Mar 2006 20:32:19 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 0529C20006; Mon, 6 Mar 2006 20:32:19 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k26BWI4D077675; Mon, 6 Mar 2006 20:32:18 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Mon, 06 Mar 2006 20:32:18 +0900 (JST) Message-Id: <20060306.203218.69025300.nemoto@toshiba-tops.co.jp> To: ralf@linux-mips.org Cc: akpm@osdl.org, linux-mips@linux-mips.org Subject: Re: [PATCH] 64bit unaligned access on 32bit kernel From: Atsushi Nemoto In-Reply-To: <20050830104056.GA4710@linux-mips.org> References: <20050830104056.GA4710@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10733 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1537 Lines: 48 >>>>> On Tue, 30 Aug 2005 11:40:56 +0100, Ralf Baechle said: > I've rewriten Atushi's fix for the 64-bit put_unaligned on 32-bit > systems bug to generate more efficient code. > This case has buzilla URL http://bugzilla.kernel.org/show_bug.cgi?id=5138. > Signed-off-by: Ralf Baechle ... > #define __get_unaligned(ptr, size) ({ \ > const void *__gu_p = ptr; \ > - unsigned long val; \ > + __typeof__(*(ptr)) val; \ > switch (size) { \ > case 1: \ > val = *(const __u8 *)__gu_p; \ It looks gcc 4.x strike back. If the 'ptr' is a const, this code cause "assignment of read-only variable" error on gcc 4.x. Let's step a back, or do you have any other good idea? Use __u64 instead of __typeof__(*(ptr)) for temporary variable to get rid of errors on gcc 4.x. Signed-off-by: Atsushi Nemoto diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h index 4dc8ddb..09ec447 100644 --- a/include/asm-generic/unaligned.h +++ b/include/asm-generic/unaligned.h @@ -78,7 +78,7 @@ static inline void __ustw(__u16 val, __u #define __get_unaligned(ptr, size) ({ \ const void *__gu_p = ptr; \ - __typeof__(*(ptr)) val; \ + __u64 val; \ switch (size) { \ case 1: \ val = *(const __u8 *)__gu_p; \ @@ -95,7 +95,7 @@ static inline void __ustw(__u16 val, __u default: \ bad_unaligned_access_length(); \ }; \ - val; \ + (__typeof__(*(ptr)))val; \ }) #define __put_unaligned(val, ptr, size) \ From redhatter@gentoo.org Mon Mar 6 12:24:05 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Mar 2006 12:24:25 +0000 (GMT) Received: from 202-47-55-78.adsl.gil.com.au ([202.47.55.78]:37859 "EHLO longlandclan.hopto.org") by ftp.linux-mips.org with ESMTP id S8133371AbWCFMYD (ORCPT ); Mon, 6 Mar 2006 12:24:03 +0000 Received: (qmail 7240 invoked from network); 6 Mar 2006 22:32:13 +1000 Received: from beast.redhatters.home (HELO ?10.0.0.251?) (10.0.0.251) by 192.168.5.1 with SMTP; 6 Mar 2006 22:32:13 +1000 Message-ID: <440C2CE8.9090204@gentoo.org> Date: Mon, 06 Mar 2006 22:36:56 +1000 From: Stuart Longland Organization: Gentoo Foundation User-Agent: Mozilla Thunderbird 1.0.7 (X11/20051029) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: does the linux support rootfs on vfat? References: <50c9a2250603042217l475e84pc9ab7ce87c40eb76@mail.gmail.com> In-Reply-To: <50c9a2250603042217l475e84pc9ab7ce87c40eb76@mail.gmail.com> X-Enigmail-Version: 0.93.0.0 OpenPGP: id=63264AB9; url=http://dev.gentoo.org/~redhatter/gpgkey.asc Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enigCC11A17E0815C80708E22A58" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10734 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: redhatter@gentoo.org Precedence: bulk X-list: linux-mips Content-Length: 2033 Lines: 53 This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enigCC11A17E0815C80708E22A58 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit (Gah... I meant this to be sent publically, not just privately ;-) zhuzhenhua wrote: > if in my product based ide disk, i want to it to support the > u-disk(with vfat fs), and can i set the root fs as vfat too? > if use vfat as rootfs, what's disadvantage of the selection? In theory, you could... BUT... FAT32 (and every other FAT variant) lacks: - Ownership metadata (uid/gid fields) - Permissions (mode: read/write/execute/sticky/suid/sgid) - Links (both hard-links and symbolic links) ... probably character devices, block devices, pipes and other numerous devices that 99.999999% of distributions rely on. Now, there is UMSDOS, which uses additional special files to emulate these on top of a standard MS-DOS filesystem ... mind you, it predates VFAT by many years, and so I'm not sure what it's support is like for long filenames. I also haven't seen it in the kernel File System menu for some time now. I'd recommend using an external initrd... or an initramfs-based kernel. That way it's just one or two files, not one or two hundred. ;-) -- Stuart Longland (aka Redhatter) .'''. Gentoo Linux/MIPS Cobalt and Docs Developer '.'` : . . . . . . . . . . . . . . . . . . . . . . .'.' http://dev.gentoo.org/~redhatter :.' International Asperger's Year (1906 ~ 2006) http://dev.gentoo.org/~redhatter/iay --------------enigCC11A17E0815C80708E22A58 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.2 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org iD8DBQFEDCzruarJ1mMmSrkRAvY1AJ4jJDt6iJ0uaZPT+zqhHrYSdZIZJACfb5YK o29h1orWv/OFvji4gCJ/f+M= =Hw/J -----END PGP SIGNATURE----- --------------enigCC11A17E0815C80708E22A58-- From colin@realtek.com.tw Mon Mar 6 12:42:53 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Mar 2006 12:43:03 +0000 (GMT) Received: from mf2.realtek.com.tw ([60.248.182.46]:15625 "EHLO mf2.realtek.com.tw") by ftp.linux-mips.org with ESMTP id S8133371AbWCFMmx (ORCPT ); Mon, 6 Mar 2006 12:42:53 +0000 Received: from msx.realtek.com.tw (unverified [172.21.1.77]) by mf2.realtek.com.tw (Clearswift SMTPRS 5.1.7) with ESMTP id for ; Mon, 6 Mar 2006 20:53:46 +0800 Received: from rtpdii3098 ([172.21.98.16]) by msx.realtek.com.tw (Lotus Domino Release 6.5.3) with ESMTP id 2006030620510325-303468 ; Mon, 6 Mar 2006 20:51:03 +0800 Message-ID: <002201c6411c$a06dadb0$106215ac@realtek.com.tw> From: "colin" To: Subject: To stick the kernel start address to 0x80100000 Date: Mon, 6 Mar 2006 20:51:02 +0800 MIME-Version: 1.0 X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1506 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1506 X-MIMETrack: Itemize by SMTP Server on msx/Realtek(Release 6.5.3|September 14, 2004) at 2006/03/06 =?Bog5?B?pFWkyCAwODo1MTowMw==?=, Serialize by Router on msx/Realtek(Release 6.5.3|September 14, 2004) at 2006/03/06 =?Bog5?B?pFWkyCAwODo1MTowNQ==?=, Serialize complete at 2006/03/06 =?Bog5?B?pFWkyCAwODo1MTowNQ==?= Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="big5" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10735 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: colin@realtek.com.tw Precedence: bulk X-list: linux-mips Content-Length: 364 Lines: 19 Hi all, I tried to stick the kernel start address to 0x80100000 and modified vmlinux.ld.S like this: .text : { arch/mips/kernel/head.o(.init.text) *(.text) SCHED_TEXT LOCK_TEXT *(.fixup) *(.gnu.warning) } =0 After some tests, it seems to work well. Is this a good way to stick the kernel start address to 0x80100000? Regards, Colin From geoffrey.levand@am.sony.com Mon Mar 6 16:33:15 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Mar 2006 16:33:26 +0000 (GMT) Received: from mail8.fw-bc.sony.com ([160.33.98.75]:52944 "EHLO mail8.fw-bc.sony.com") by ftp.linux-mips.org with ESMTP id S8133494AbWCFQdP (ORCPT ); Mon, 6 Mar 2006 16:33:15 +0000 Received: from mail3.sjc.in.sel.sony.com (mail3.sjc.in.sel.sony.com [43.134.1.211]) by mail8.fw-bc.sony.com (8.12.11/8.12.11) with ESMTP id k26GfTHO009198; Mon, 6 Mar 2006 16:41:29 GMT Received: from [192.168.1.10] ([43.134.85.105]) by mail3.sjc.in.sel.sony.com (8.12.11/8.12.11) with ESMTP id k26GfS5M024093; Mon, 6 Mar 2006 16:41:28 GMT Message-ID: <440C6638.7000909@am.sony.com> Date: Mon, 06 Mar 2006 08:41:28 -0800 From: Geoff Levand User-Agent: Mozilla Thunderbird 1.0.7-1.1.fc4 (X11/20050929) X-Accept-Language: en-us, en MIME-Version: 1.0 To: zhuzhenhua CC: linux-mips , Hiroyuki Machida Subject: Re: does the linux support rootfs on vfat? References: <50c9a2250603042217l475e84pc9ab7ce87c40eb76@mail.gmail.com> In-Reply-To: <50c9a2250603042217l475e84pc9ab7ce87c40eb76@mail.gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10736 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geoffrey.levand@am.sony.com Precedence: bulk X-list: linux-mips Content-Length: 393 Lines: 13 zhuzhenhua wrote: > if in my product based ide disk, i want to it to support the > u-disk(with vfat fs), and can i set the root fs as vfat too? > if use vfat as rootfs, what's disadvantage of the selection? > See these threads, 'Posix file attribute support on VFAT', which disscusses using VFAT for a root fs: http://lkml.org/lkml/2005/8/8/76 http://lkml.org/lkml/2005/8/8/326 -Geoff From geoffrey.levand@am.sony.com Mon Mar 6 16:41:06 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Mar 2006 16:41:20 +0000 (GMT) Received: from mail8.fw-bc.sony.com ([160.33.98.75]:1238 "EHLO mail8.fw-bc.sony.com") by ftp.linux-mips.org with ESMTP id S8133566AbWCFQlF (ORCPT ); Mon, 6 Mar 2006 16:41:05 +0000 Received: from mail3.sjc.in.sel.sony.com (mail3.sjc.in.sel.sony.com [43.134.1.211]) by mail8.fw-bc.sony.com (8.12.11/8.12.11) with ESMTP id k26GnO96010558; Mon, 6 Mar 2006 16:49:25 GMT Received: from [192.168.1.10] ([43.134.85.105]) by mail3.sjc.in.sel.sony.com (8.12.11/8.12.11) with ESMTP id k26GnO59025633; Mon, 6 Mar 2006 16:49:24 GMT Message-ID: <440C6814.4020204@am.sony.com> Date: Mon, 06 Mar 2006 08:49:24 -0800 From: Geoff Levand User-Agent: Mozilla Thunderbird 1.0.7-1.1.fc4 (X11/20050929) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Ralf Baechle CC: zhuzhenhua , linux-mips Subject: Re: does the linux support rootfs on vfat? References: <50c9a2250603042217l475e84pc9ab7ce87c40eb76@mail.gmail.com> <20060305080958.GX19232@lug-owl.de> <20060305112247.GA4243@linux-mips.org> In-Reply-To: <20060305112247.GA4243@linux-mips.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10737 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geoffrey.levand@am.sony.com Precedence: bulk X-list: linux-mips Content-Length: 1225 Lines: 25 Ralf Baechle wrote: > On Sun, Mar 05, 2006 at 09:09:58AM +0100, Jan-Benedict Glaw wrote: > >> On Sun, 2006-03-05 14:17:56 +0800, zhuzhenhua wrote: >> > if in my product based ide disk, i want to it to support the >> > u-disk(with vfat fs), and can i set the root fs as vfat too? >> > if use vfat as rootfs, what's disadvantage of the selection? >> >> Well, most notably you won't have device nodes. Maybe a ram-backed >> filesystem mounted to /dev/ could solve that, but you'd probably need >> an initrd for that to do. > > It's anso case-insensitive which may cause some further troubles. It's > doesn't have proper inodes, no UNIX file modes, no UID / GID support (These > two can be kludges in awfully insufficient way through mount options), not > only lacks device special files but also no FIFO, no UNIX domain sockets, > no hard or soft links. It's simply a sorry excuse for a useful filesystem. It's attractive for a limited resource device that needs to have FAT support for a removable flash memory card (for Windows PC interoperability). If you can use FAT for the root fs, that reduces the system resource needs. It doesn't make sense if his ide disk is non-removable though. -Geoff From p_christ@hol.gr Mon Mar 6 17:01:34 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Mar 2006 17:01:44 +0000 (GMT) Received: from [62.38.112.228] ([62.38.112.228]:35718 "EHLO pfn3.pefnos") by ftp.linux-mips.org with ESMTP id S8133992AbWCFRBe (ORCPT ); Mon, 6 Mar 2006 17:01:34 +0000 Received: from xorhgos2.pefnos (xorhgos2.pefnos [192.168.0.3]) by pfn3.pefnos (Postfix) with ESMTP id 6E0B932F69; Mon, 6 Mar 2006 19:09:21 +0200 (EET) From: "P. Christeas" To: Geoff Levand Subject: Re: does the linux support rootfs on vfat? Date: Mon, 6 Mar 2006 19:08:54 +0200 User-Agent: KMail/1.9 References: <50c9a2250603042217l475e84pc9ab7ce87c40eb76@mail.gmail.com> <20060305112247.GA4243@linux-mips.org> <440C6814.4020204@am.sony.com> In-Reply-To: <440C6814.4020204@am.sony.com> Cc: linux-mips MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200603061908.58658.p_christ@hol.gr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10738 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: p_christ@hol.gr Precedence: bulk X-list: linux-mips Content-Length: 944 Lines: 19 On Monday 06 March 2006 6:49 pm, you wrote: > It's attractive for a limited resource device that needs to have FAT > support for a removable flash memory card (for Windows PC > interoperability). If you can use FAT for the root fs, that reduces the > system resource needs. > > It doesn't make sense if his ide disk is non-removable though. > IMHO it is a bad idea alltogether. You are asking for trouble. The system resource needs are rather increased [1] than decreased. On the other hand, you would you need to trade files between the *root* fs of the linux and Windoze? Usually we want to trade some user files (like photos, music etc.), but not the system files. Would you trust Windoze ever not to destroy something in those root files? Why don't you create a second, VFAT partition and mount it somewhere? [1] ext2 or whatever is optimized. FAT isn't so and you really want to run Linux trivial files from an optimized system. From ralf@linux-mips.org Mon Mar 6 17:49:12 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Mar 2006 17:49:33 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:44425 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133742AbWCFRtM (ORCPT ); Mon, 6 Mar 2006 17:49:12 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k26HvWGq018660; Mon, 6 Mar 2006 17:57:32 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k26HvWR2018659; Mon, 6 Mar 2006 17:57:32 GMT Date: Mon, 6 Mar 2006 17:57:32 +0000 From: Ralf Baechle To: linux-cvs@linux-mips.org, linux-cvs-patches@linux-mips.org, linux-mips@linux-mips.org Subject: CVS commit notification list and the git conversion Message-ID: <20060306175732.GA18027@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10739 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1227 Lines: 24 As you may have noticed, the good old linux-cvs and linux-cvs-patches mailing lists haven't received any postings since I converted the MIPS kernel repository to git. I now have the necessary bits and pieces in places to resume the same kind of notifications with git. I'm therefore going to rename the two lists to linux-git rsp. linux-git-patches and will have the notification catch up on postings that were not sent out due since the conversion. If you were subscribed to linux-cvs or linux-cvs-patches you will be subscribed to the new list; there is nothing you will have to do. As candy for procmail users the list has headers that looks like: X-Git-Branch: master, X-Git-Branch: linux-2.4 etc. which can be used to sort email. As an implmentation choice I decieded to aggregate all commits merge from kernel.org into a single mail rather than a large number of individual mails, so it's going to be easier to follow what's really going on on linux-mips.org. In case you care about all the details of the changesets from kernel.org as well I suggest you subscribe via majordomo to either git-commits-head@vger.kernel.org to follow 2.6 development or git-commits-24@vger.kernel.org for the 2.4 development. Ralf From tbm@cyrius.com Tue Mar 7 03:40:40 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Mar 2006 03:40:49 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:12548 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133566AbWCGDkk (ORCPT ); Tue, 7 Mar 2006 03:40:40 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 626AD64D3D; Tue, 7 Mar 2006 03:49:01 +0000 (UTC) Received: by unjust.cyrius.com (Postfix, from userid 1000) id 9C2C83EB2A; Tue, 7 Mar 2006 03:48:51 +0000 (GMT) Resent-From: tbm@cyrius.com Resent-Date: Tue, 7 Mar 2006 03:48:51 +0000 Resent-Message-ID: <20060307034851.GB29936@unjust.cyrius.com> Resent-To: linux-mips@linux-mips.org Date: Mon, 6 Mar 2006 22:51:31 +0000 From: Martin Michlmayr To: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH, RESEND] Add MWI workaround for Tulip DC21143 Message-ID: <20060306225131.GA23327@unjust.cyrius.com> References: <20060129230816.GD4094@colonel-panic.org> <20060218220851.GA1601@colonel-panic.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060218220851.GA1601@colonel-panic.org> User-Agent: Mutt/1.5.9i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10740 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 668 Lines: 16 * Peter Horton [2006-02-18 22:08]: > This patch works around the MWI bug on the DC21143 rev 65 Tulip by > ensuring that the receive buffers don't end on a cache line boundary (as > documented in the errata). > > This patch is required for the MIPs based Cobalt Qube/RaQ as supporting > the extra PCI commands seems to reduce the chance of a hard lockup > between the Tulip and the PCI bridge. Does anyone have comments regarding this patch? I received confirmation from a number of Debian users that this patch significantly improves the lockup situation on Cobalt, so it would be nice if it could go in. -- Martin Michlmayr tbm@cyrius.com From tbm@cyrius.com Tue Mar 7 03:42:42 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Mar 2006 03:42:54 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:14596 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133566AbWCGDmm (ORCPT ); Tue, 7 Mar 2006 03:42:42 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 6FA5464D3D; Tue, 7 Mar 2006 03:51:02 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 9BDEE66D0E; Tue, 7 Mar 2006 03:50:48 +0000 (GMT) Resent-From: tbm@cyrius.com Resent-Date: Tue, 7 Mar 2006 03:50:48 +0000 Resent-Message-ID: <20060307035048.GA22201@deprecation.cyrius.com> Resent-To: linux-mips@linux-mips.org X-Original-To: tbm@cyrius.com Received: by deprecation.cyrius.com (Postfix, from userid 10) id 02AB366EBE; Mon, 6 Mar 2006 23:19:10 +0000 (GMT) Received: from localhost (localhost [127.0.0.1]) by sorrow.cyrius.com (Postfix) with ESMTP id 7E21F64D3F for ; Mon, 6 Mar 2006 23:15:59 +0000 (UTC) Received: from fr.zoreil.com (electric-eye.fr.zoreil.com [213.41.134.224]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by sorrow.cyrius.com (Postfix) with ESMTP id 33F5064D3D for ; Mon, 6 Mar 2006 23:15:54 +0000 (UTC) Received: from electric-eye.fr.zoreil.com (localhost.localdomain [127.0.0.1]) by fr.zoreil.com (8.13.4/8.12.1) with ESMTP id k26NFUkL021899; Tue, 7 Mar 2006 00:15:30 +0100 Received: (from romieu@localhost) by electric-eye.fr.zoreil.com (8.13.4/8.12.1) id k26NFUYZ021898; Tue, 7 Mar 2006 00:15:30 +0100 Date: Tue, 7 Mar 2006 00:15:30 +0100 From: Francois Romieu To: Martin Michlmayr Cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH, RESEND] Add MWI workaround for Tulip DC21143 Message-ID: <20060306231530.GB16082@electric-eye.fr.zoreil.com> References: <20060129230816.GD4094@colonel-panic.org> <20060218220851.GA1601@colonel-panic.org> <20060306225131.GA23327@unjust.cyrius.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060306225131.GA23327@unjust.cyrius.com> User-Agent: Mutt/1.4.2.1i X-Organisation: Land of Sunshine Inc. X-Virus-Scanned: by amavisd-new-20030616-p10 (Debian) at cyrius.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10741 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 348 Lines: 12 Martin Michlmayr : [...] > Does anyone have comments regarding this patch? I received > confirmation from a number of Debian users that this patch > significantly improves the lockup situation on Cobalt, so > it would be nice if it could go in. I'll queue it with the pending de2104x fix(es ?) during my next upkeep. -- Ueimor From ralf@linux-mips.org Tue Mar 7 03:50:08 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Mar 2006 03:50:16 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:4833 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133606AbWCGDuI (ORCPT ); Tue, 7 Mar 2006 03:50:08 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k273wRa8026956; Tue, 7 Mar 2006 03:58:27 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k273wOlc026954; Tue, 7 Mar 2006 03:58:24 GMT Date: Tue, 7 Mar 2006 03:58:24 +0000 From: Ralf Baechle To: Francois Romieu Cc: Martin Michlmayr , netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH, RESEND] Add MWI workaround for Tulip DC21143 Message-ID: <20060307035824.GA24018@linux-mips.org> References: <20060129230816.GD4094@colonel-panic.org> <20060218220851.GA1601@colonel-panic.org> <20060306225131.GA23327@unjust.cyrius.com> <20060306231530.GB16082@electric-eye.fr.zoreil.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060306231530.GB16082@electric-eye.fr.zoreil.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10742 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 565 Lines: 16 On Tue, Mar 07, 2006 at 12:15:30AM +0100, Francois Romieu wrote: > [...] > > Does anyone have comments regarding this patch? I received > > confirmation from a number of Debian users that this patch > > significantly improves the lockup situation on Cobalt, so > > it would be nice if it could go in. > > I'll queue it with the pending de2104x fix(es ?) during my next > upkeep. I'm just not convinced of having such a workaround as a build option. The average person building a a kernel will probably not know if the option needs to be enabled or not. Ralf From anemo@mba.ocn.ne.jp Tue Mar 7 05:54:36 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Mar 2006 05:54:49 +0000 (GMT) Received: from smtp-out-0101.amazon.com ([207.171.180.182]:15069 "EHLO smtp-out-0101.amazon.com") by ftp.linux-mips.org with ESMTP id S8127233AbWCGFyf (ORCPT ); Tue, 7 Mar 2006 05:54:35 +0000 X-Amazon-Corporate-Relay: smtp-out-0101.sea3.amazon.com X-AMAZON-TRACK: ralf@linux-mips.org Received: from smtp-in-2001.iad2.amazon.com by smtp-out-0101.amazon.com with ESMTP (peer crosscheck: smtp-in-2001.iad2.amazon.com) Received: from ex-gate-01.ant.amazon.com (ex-gate-01.ant.amazon.com [172.20.21.33]) by smtp-in-2001.iad2.amazon.com (8.12.10/8.12.10) with ESMTP id k275xnRn025797; Tue, 7 Mar 2006 06:02:55 GMT Received: from mail pickup service by ex-gate-01.ant.amazon.com with Microsoft SMTPSVC; Mon, 6 Mar 2006 22:02:21 -0800 Received: from smtp-in-1001.vdc.amazon.com ([10.130.7.44]) by ex-gate-01.ant.amazon.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.1830); Mon, 6 Mar 2006 18:05:51 -0800 Received: from smtp-border-fw-1101.amazon.com (smtp-border-fw-1101.vdc.amazon.com [10.30.167.40]) by smtp-in-1001.vdc.amazon.com (8.12.10/8.12.10) with ESMTP id k2724ch2017391 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=FAIL) for ; Tue, 7 Mar 2006 02:05:47 GMT Received: from vger.kernel.org ([209.132.176.167]) by smtp-border-fw-1101.amazon.com with ESMTP; 07 Mar 2006 02:05:36 +0000 X-Amazon-External-Envelope-Sender: linux-kernel-owner+psubash=40amazon.com-S1752474AbWCGCDS@vger.kernel.org X-Amazon-External-Envelope-Recipient: psubash@amazon.com X-Amazon-External-Source: yes X-Amazon-Approved-Domain: no X-BrightmailFiltered: true X-Brightmail-Tracker: AAAAAA== X-IronPort-AV: i="4.02,169,1139184000"; d="scan'208"; a="179720437:sNHT27854144" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752474AbWCGCDS (ORCPT ); Mon, 6 Mar 2006 21:03:18 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752477AbWCGCDS (ORCPT ); Mon, 6 Mar 2006 21:03:18 -0500 Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:64767 "EHLO topsns2.toshiba-tops.co.jp") by vger.kernel.org with ESMTP id S1752474AbWCGCDR (ORCPT ); Mon, 6 Mar 2006 21:03:17 -0500 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for vger.kernel.org [209.132.176.167]) with ESMTP; Tue, 7 Mar 2006 11:03:16 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id F25C820686; Tue, 7 Mar 2006 11:03:14 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id E7C8E20040; Tue, 7 Mar 2006 11:03:14 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k2723E4D080974; Tue, 7 Mar 2006 11:03:14 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Tue, 07 Mar 2006 11:03:14 +0900 (JST) Message-Id: <20060307.110314.00927749.nemoto@toshiba-tops.co.jp> To: akpm@osdl.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] 64bit unaligned access on 32bit kernel From: Atsushi Nemoto In-Reply-To: <20060306170552.0aab29c5.akpm@osdl.org> References: <20050830104056.GA4710@linux-mips.org> <20060306.203218.69025300.nemoto@toshiba-tops.co.jp> <20060306170552.0aab29c5.akpm@osdl.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org X-OriginalArrivalTime: 07 Mar 2006 02:05:51.0394 (UTC) FILETIME=[A8BE4820:01C6418B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10743 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 721 Lines: 19 >>>>> On Mon, 6 Mar 2006 17:05:52 -0800, Andrew Morton said: >> Use __u64 instead of __typeof__(*(ptr)) for temporary variable to >> get rid of errors on gcc 4.x. akpm> I worry about what impact that change might have on code akpm> generation. Hopefully none, if gcc is good enough. akpm> But I cannot think of a better fix. As I tested on MIPS gcc 3.x, the impact is not none, but not so huge. And it becomes much smaller with gcc 4.x. --- Atsushi Nemoto - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ From geert@linux-m68k.org Tue Mar 7 09:23:57 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Mar 2006 09:24:05 +0000 (GMT) Received: from witte.sonytel.be ([80.88.33.193]:61898 "EHLO witte.sonytel.be") by ftp.linux-mips.org with ESMTP id S8133353AbWCGJX5 (ORCPT ); Tue, 7 Mar 2006 09:23:57 +0000 Received: from pademelon.sonytel.be (mail.sonytel.be [43.221.60.197]) by witte.sonytel.be (8.12.10/8.12.10) with ESMTP id k279WDlR002769; Tue, 7 Mar 2006 10:32:13 +0100 (MET) Date: Tue, 7 Mar 2006 10:32:13 +0100 (CET) From: Geert Uytterhoeven To: Ralf Baechle cc: Francois Romieu , Martin Michlmayr , netdev@vger.kernel.org, Linux/MIPS Development Subject: Re: [PATCH, RESEND] Add MWI workaround for Tulip DC21143 In-Reply-To: <20060307035824.GA24018@linux-mips.org> Message-ID: References: <20060129230816.GD4094@colonel-panic.org> <20060218220851.GA1601@colonel-panic.org> <20060306225131.GA23327@unjust.cyrius.com> <20060306231530.GB16082@electric-eye.fr.zoreil.com> <20060307035824.GA24018@linux-mips.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10744 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Content-Length: 1018 Lines: 29 On Tue, 7 Mar 2006, Ralf Baechle wrote: > On Tue, Mar 07, 2006 at 12:15:30AM +0100, Francois Romieu wrote: > > > [...] > > > Does anyone have comments regarding this patch? I received > > > confirmation from a number of Debian users that this patch > > > significantly improves the lockup situation on Cobalt, so > > > it would be nice if it could go in. > > > > I'll queue it with the pending de2104x fix(es ?) during my next > > upkeep. > > I'm just not convinced of having such a workaround as a build option. > The average person building a a kernel will probably not know if the > option needs to be enabled or not. Indeed, if it's mentioned in the errata of the chip, the driver should take care of it. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From Ian.Hamilton@xerox.com Tue Mar 7 12:10:53 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Mar 2006 12:11:03 +0000 (GMT) Received: from wbmler1.mail.xerox.com ([13.13.138.216]:50627 "EHLO wbmler1.mail.xerox.com") by ftp.linux-mips.org with ESMTP id S8133391AbWCGMKx convert rfc822-to-8bit (ORCPT ); Tue, 7 Mar 2006 12:10:53 +0000 Received: from wbmlir3.mail.xerox.com (wbmlir3.mail.xerox.com [13.131.8.223]) by wbmler1.mail.xerox.com (8.13.4/8.13.1) with ESMTP id k27CJ2Mo011893; Tue, 7 Mar 2006 07:19:10 -0500 Received: from wbmlir3.mail.xerox.com (localhost [127.0.0.1]) by wbmlir3.mail.xerox.com (8.13.4/8.13.1) with ESMTP id k27CIriL032333; Tue, 7 Mar 2006 07:18:53 -0500 Received: from usa7061gw02.na.xerox.net (usa7061gw02.na.xerox.net [13.151.32.4]) by wbmlir3.mail.xerox.com (8.13.4/8.13.1) with ESMTP id k27CIaeA032197; Tue, 7 Mar 2006 07:18:52 -0500 Received: from usa7061bh01.na.xerox.net ([13.151.33.5]) by usa7061gw02.na.xerox.net with Microsoft SMTPSVC(6.0.3790.211); Tue, 7 Mar 2006 04:18:36 -0800 Received: from gbrmiteubh01.eu.xerox.net ([13.223.7.13]) by usa7061bh01.na.xerox.net with Microsoft SMTPSVC(6.0.3790.211); Tue, 7 Mar 2006 04:18:33 -0800 Received: from gbrwgceumf02.eu.xerox.net ([13.200.0.54]) by gbrmiteubh01.eu.xerox.net with Microsoft SMTPSVC(6.0.3790.211); Tue, 7 Mar 2006 12:18:02 +0000 X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH] Buglet in Alchemy OHCI driver Date: Tue, 7 Mar 2006 12:17:21 -0000 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH] Buglet in Alchemy OHCI driver Thread-Index: AcY9h5dEM4/7bNVSTsOAI1TsrD7H5gEWJ4Sw From: "Hamilton, Ian" To: "Greg KH" , "Martin Michlmayr" Cc: "Jordan Crouse" , , , X-OriginalArrivalTime: 07 Mar 2006 12:18:02.0275 (UTC) FILETIME=[2E0DEF30:01C641E1] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10745 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Ian.Hamilton@xerox.com Precedence: bulk X-list: linux-mips Content-Length: 1992 Lines: 69 Hi Greg, I spotted this in the current latest version of ohci-au1xxx.c (accessed via git web interface): 94 95 if (dev->resource[1].flags != IORESOURCE_IRQ) { 96 pr_debug ("resource[1] is not IORESOURCE_IRQ"); 97 retval -ENOMEM; 98 } 99 instead this from Martin's patch: diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index aa4d0cd..d8fb1bb 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -94,7 +94,7 @@ int usb_hcd_au1xxx_probe (const struct h if (dev->resource[1].flags != IORESOURCE_IRQ) { pr_debug ("resource[1] is not IORESOURCE_IRQ"); - retval = -ENOMEM; + return -ENOMEM; } Line 97 produces a warning, but doesn't stop the build, so may have been missed. Cheers, Ian Hamilton. -----Original Message----- From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Greg KH Sent: 01 March 2006 23:22 To: Martin Michlmayr Cc: Jordan Crouse; linux-usb-devel@lists.sourceforge.net; linux-mips@linux-mips.org; gregkh@suse.de Subject: Re: [PATCH] Buglet in Alchemy OHCI driver On Wed, Mar 01, 2006 at 06:37:35PM +0000, Martin Michlmayr wrote: > * Jordan Crouse [2006-03-01 11:30]: > > Martin Michlmayr spotted this potentially serious bug. Please apply. > > Please don't send patches as MIME attachments. Here it is again (with > a better summary too): > > > [PATCH] Alchemy OCHI: return if right resources cannot be obtained > > From: Jordan Crouse > > Failure to get the right resources should immediately return. Current > code has the possiblity of running off into the weeds. Spotted by > Martin Michlmayr. > > Signed-off-by: Jordan Crouse > Signed-off-by: Martin Michlmayr This patch is already in my tree, in the other patch from Jordan, so it will make it in after 2.6.16-final is out. thanks, greg k-h From greg@kroah.org Tue Mar 7 16:46:38 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Mar 2006 16:46:51 +0000 (GMT) Received: from dsl093-040-174.pdx1.dsl.speakeasy.net ([66.93.40.174]:22689 "EHLO aria.kroah.org") by ftp.linux-mips.org with ESMTP id S8133621AbWCGQqh (ORCPT ); Tue, 7 Mar 2006 16:46:37 +0000 Received: from press.kroah.org ([192.168.0.25] helo=localhost) by aria.kroah.org with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.54) id 1FGfSS-0008KA-E2; Tue, 07 Mar 2006 08:54:48 -0800 Date: Tue, 7 Mar 2006 08:54:45 -0800 From: Greg KH To: "Hamilton, Ian" Cc: Greg KH , Martin Michlmayr , Jordan Crouse , linux-usb-devel@lists.sourceforge.net, linux-mips@linux-mips.org Subject: Re: [PATCH] Buglet in Alchemy OHCI driver Message-ID: <20060307165445.GA6623@suse.de> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10746 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Content-Length: 1132 Lines: 39 On Tue, Mar 07, 2006 at 12:17:21PM -0000, Hamilton, Ian wrote: > Hi Greg, > > I spotted this in the current latest version of ohci-au1xxx.c (accessed > via git web interface): > > 94 > 95 if (dev->resource[1].flags != IORESOURCE_IRQ) { > 96 pr_debug ("resource[1] is not IORESOURCE_IRQ"); > 97 retval -ENOMEM; > 98 } > 99 > > instead this from Martin's patch: > > diff --git a/drivers/usb/host/ohci-au1xxx.c > b/drivers/usb/host/ohci-au1xxx.c > index aa4d0cd..d8fb1bb 100644 > --- a/drivers/usb/host/ohci-au1xxx.c > +++ b/drivers/usb/host/ohci-au1xxx.c > @@ -94,7 +94,7 @@ int usb_hcd_au1xxx_probe (const struct h > > if (dev->resource[1].flags != IORESOURCE_IRQ) { > pr_debug ("resource[1] is not IORESOURCE_IRQ"); > - retval = -ENOMEM; > + return -ENOMEM; > } > > Line 97 produces a warning, but doesn't stop the build, so may have been > missed. Can you check the -mm tree to see if it is fixed there or not? That has the patches that are pending from my usb tree in it. And if not, can you send me a patch against the latest -mm? thanks, greg k-h From ralf@linux-mips.org Tue Mar 7 18:00:42 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Mar 2006 18:00:51 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:50382 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133625AbWCGSAm (ORCPT ); Tue, 7 Mar 2006 18:00:42 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k27I988H016405; Tue, 7 Mar 2006 18:09:08 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k27I97vs016404; Tue, 7 Mar 2006 18:09:07 GMT Date: Tue, 7 Mar 2006 18:09:07 +0000 From: Ralf Baechle To: Andrew Morton Cc: Atsushi Nemoto , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] 64bit unaligned access on 32bit kernel Message-ID: <20060307180907.GA13577@linux-mips.org> References: <20050830104056.GA4710@linux-mips.org> <20060306.203218.69025300.nemoto@toshiba-tops.co.jp> <20060306170552.0aab29c5.akpm@osdl.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060306170552.0aab29c5.akpm@osdl.org> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10747 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 2878 Lines: 102 On Mon, Mar 06, 2006 at 05:05:52PM -0800, Andrew Morton wrote: > I worry about what impact that change might have on code generation. > Hopefully none, if gcc is good enough. > > But I cannot think of a better fix. Below's fix results in exactly the same code size on all compilers and configurations I've tested it. I also have another more elegant fix which as a side effect makes get_unaligned work for arbitrary data types but it that one results in a slight code bloat: gcc 4.1.0 ip22 64-bit text data bss dec hex filename 2717213 337920 167968 3223101 312e3d vmlinux 2717277 337920 167968 3223165 312e7d vmlinux unaligned-4.patch Ralf Signed-off-by: Ralf Baechle diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h index 4dc8ddb..9a63564 100644 --- a/include/asm-generic/unaligned.h +++ b/include/asm-generic/unaligned.h @@ -26,35 +26,13 @@ * the linker will alert us to the problem via an unresolved reference * error. */ -extern void bad_unaligned_access_length(void) __attribute__((noreturn)); +extern int bad_unaligned_access_length(void) __attribute__((noreturn)); struct __una_u64 { __u64 x __attribute__((packed)); }; struct __una_u32 { __u32 x __attribute__((packed)); }; struct __una_u16 { __u16 x __attribute__((packed)); }; /* - * Elemental unaligned loads - */ - -static inline __u64 __uldq(const __u64 *addr) -{ - const struct __una_u64 *ptr = (const struct __una_u64 *) addr; - return ptr->x; -} - -static inline __u32 __uldl(const __u32 *addr) -{ - const struct __una_u32 *ptr = (const struct __una_u32 *) addr; - return ptr->x; -} - -static inline __u16 __uldw(const __u16 *addr) -{ - const struct __una_u16 *ptr = (const struct __una_u16 *) addr; - return ptr->x; -} - -/* * Elemental unaligned stores */ @@ -76,26 +54,16 @@ static inline void __ustw(__u16 val, __u ptr->x = val; } -#define __get_unaligned(ptr, size) ({ \ - const void *__gu_p = ptr; \ - __typeof__(*(ptr)) val; \ - switch (size) { \ - case 1: \ - val = *(const __u8 *)__gu_p; \ - break; \ - case 2: \ - val = __uldw(__gu_p); \ - break; \ - case 4: \ - val = __uldl(__gu_p); \ - break; \ - case 8: \ - val = __uldq(__gu_p); \ - break; \ - default: \ - bad_unaligned_access_length(); \ - }; \ - val; \ +#define __get_unaligned(ptr, size) \ +({ \ + const void *__gu_p = ptr; \ + int __sz = size; \ + \ + ((__sz == 1) ? (__typeof__(*(ptr)))*(const __u8 *)__gu_p \ + : ((__sz == 2) ? (__typeof__(*(ptr)))((struct __una_u16 *)__gu_p)->x \ + : ((__sz == 4) ? (__typeof__(*(ptr)))((struct __una_u32 *)__gu_p)->x \ + : ((__sz == 8) ? (__typeof__(*(ptr)))((struct __una_u64 *)__gu_p)->x \ + : bad_unaligned_access_length())))); \ }) #define __put_unaligned(val, ptr, size) \ From ralf@linux-mips.org Tue Mar 7 18:20:29 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Mar 2006 18:20:37 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:9168 "EHLO bacchus.dhis.org") by ftp.linux-mips.org with ESMTP id S8133712AbWCGSU3 (ORCPT ); Tue, 7 Mar 2006 18:20:29 +0000 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by bacchus.dhis.org (8.13.4/8.13.4) with ESMTP id k27ISsOK016998; Tue, 7 Mar 2006 18:28:54 GMT Received: (from ralf@localhost) by denk.linux-mips.net (8.13.4/8.13.4/Submit) id k27ISjJt016997; Tue, 7 Mar 2006 18:28:45 GMT Date: Tue, 7 Mar 2006 18:28:45 +0000 From: Ralf Baechle To: Greg KH Cc: "Hamilton, Ian" , Greg KH , Martin Michlmayr , Jordan Crouse , linux-usb-devel@lists.sourceforge.net, linux-mips@linux-mips.org Subject: Re: [PATCH] Buglet in Alchemy OHCI driver Message-ID: <20060307182845.GA16685@linux-mips.org> References: <20060307165445.GA6623@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060307165445.GA6623@suse.de> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10748 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 191 Lines: 6 On Tue, Mar 07, 2006 at 08:54:45AM -0800, Greg KH wrote: Again that's been a bug report against the wrong tree - it was broken in the MIPS tree only and is fixed since this morning. Ralf From anemo@mba.ocn.ne.jp Wed Mar 8 04:50:17 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 04:50:27 +0000 (GMT) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:32060 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S8127208AbWCHEuR (ORCPT ); Wed, 8 Mar 2006 04:50:17 +0000 Received: from topsms.toshiba-tops.co.jp by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [194.74.144.162]) with ESMTP; Wed, 8 Mar 2006 13:58:44 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 34F5520141; Wed, 8 Mar 2006 13:58:42 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 1FB8D20057; Wed, 8 Mar 2006 13:58:42 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id k284we4D086741; Wed, 8 Mar 2006 13:58:41 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Wed, 08 Mar 2006 13:58:40 +0900 (JST) Message-Id: <20060308.135840.69058042.nemoto@toshiba-tops.co.jp> To: ralf@linux-mips.org Cc: akpm@osdl.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] 64bit unaligned access on 32bit kernel From: Atsushi Nemoto In-Reply-To: <20060307180907.GA13577@linux-mips.org> References: <20060306.203218.69025300.nemoto@toshiba-tops.co.jp> <20060306170552.0aab29c5.akpm@osdl.org> <20060307180907.GA13577@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10749 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 614 Lines: 16 >>>>> On Tue, 7 Mar 2006 18:09:07 +0000, Ralf Baechle said: ralf> Below's fix results in exactly the same code size on all ralf> compilers and configurations I've tested it. ralf> I also have another more elegant fix which as a side effect ralf> makes get_unaligned work for arbitrary data types but it that ralf> one results in a slight code bloat: I tested the patch attached on several MIPS kernel (big/little, 32bit/64bit) with gcc 3.4.5. In most (but not all) case, Ralf's fix resulted better than the previous fix. Acked-by: Atsushi Nemoto --- Atsushi Nemoto From akpm@osdl.org Wed Mar 8 05:06:03 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 05:06:12 +0000 (GMT) Received: from smtp.osdl.org ([65.172.181.4]:28891 "EHLO smtp.osdl.org") by ftp.linux-mips.org with ESMTP id S8133373AbWCHFGD (ORCPT ); Wed, 8 Mar 2006 05:06:03 +0000 Received: from shell0.pdx.osdl.net (fw.osdl.org [65.172.181.6]) by smtp.osdl.org (8.12.8/8.12.8) with ESMTP id k285EUDZ010463 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Tue, 7 Mar 2006 21:14:30 -0800 Received: from bix (shell0.pdx.osdl.net [10.9.0.31]) by shell0.pdx.osdl.net (8.13.1/8.11.6) with SMTP id k285ESTm028187; Tue, 7 Mar 2006 21:14:29 -0800 Date: Tue, 7 Mar 2006 21:12:40 -0800 From: Andrew Morton To: Atsushi Nemoto Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] 64bit unaligned access on 32bit kernel Message-Id: <20060307211240.4b1bb373.akpm@osdl.org> In-Reply-To: <20060308.135840.69058042.nemoto@toshiba-tops.co.jp> References: <20060306.203218.69025300.nemoto@toshiba-tops.co.jp> <20060306170552.0aab29c5.akpm@osdl.org> <20060307180907.GA13577@linux-mips.org> <20060308.135840.69058042.nemoto@toshiba-tops.co.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: osdl$Revision: 1.129 $ X-Scanned-By: MIMEDefang 2.36 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10750 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@osdl.org Precedence: bulk X-list: linux-mips Content-Length: 873 Lines: 20 Atsushi Nemoto wrote: > > >>>>> On Tue, 7 Mar 2006 18:09:07 +0000, Ralf Baechle said: > ralf> Below's fix results in exactly the same code size on all > ralf> compilers and configurations I've tested it. > > ralf> I also have another more elegant fix which as a side effect > ralf> makes get_unaligned work for arbitrary data types but it that > ralf> one results in a slight code bloat: > > I tested the patch attached on several MIPS kernel (big/little, > 32bit/64bit) with gcc 3.4.5. In most (but not all) case, Ralf's fix > resulted better than the previous fix. > hmm, well, your earlier patch has had more testing on various platforms, for what that's worth. I think for 2.6.16 we should run with that. If you want to prepare a patch which implements Ralf's version for post-2.6.16 then that would be good, thanks. From jbglaw@lug-owl.de Wed Mar 8 17:29:56 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 17:30:14 +0000 (GMT) Received: from lug-owl.de ([195.71.106.12]:51910 "EHLO lug-owl.de") by ftp.linux-mips.org with ESMTP id S8133835AbWCHR34 (ORCPT ); Wed, 8 Mar 2006 17:29:56 +0000 Received: by lug-owl.de (Postfix, from userid 1001) id 8B8DDF0034; Wed, 8 Mar 2006 18:38:25 +0100 (CET) Date: Wed, 8 Mar 2006 18:38:25 +0100 From: Jan-Benedict Glaw To: linux-mips@linux-mips.org Subject: Re: [MIPS] Always pass -msoft-float. Message-ID: <20060308173825.GJ12575@lug-owl.de> Mail-Followup-To: linux-mips@linux-mips.org References: Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="SLfjTIIQuAzj8yil" Content-Disposition: inline In-Reply-To: X-Operating-System: Linux mail 2.6.12.3lug-owl X-gpg-fingerprint: 250D 3BCF 7127 0D8C A444 A961 1DBD 5E75 8399 E1BB X-gpg-key: wwwkeys.de.pgp.net X-Echelon-Enable: howto poison arsenous mail psychological biological nuclear warfare test the bombastical terror of flooding the spy listeners explosion sex drugs and rock'n'roll X-TKUeV: howto poison arsenous mail psychological biological nuclear warfare test the bombastical terror of flooding the spy listeners explosion sex drugs and rock'n'roll User-Agent: Mutt/1.5.9i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10751 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jbglaw@lug-owl.de Precedence: bulk X-list: linux-mips Content-Length: 1373 Lines: 47 --SLfjTIIQuAzj8yil Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, 2006-03-08 17:06:32 +0000, linux-mips@linux-mips.org wrote: > Author: Ralf Baechle Wed Mar 8 17:14:49 2006 +0000 > Commit: 36981cd8fd95a584ca93364b55a3916f9ee7ba13 > Branch: master >=20 > Some people still haven't heared that fp in the kernel is forbidden. >=20 > Signed-off-by: Ralf Baechle Hi Ralf! Is there any chance that you'd also include the diff in these emails? Maybe that's not a good idea for merges from Linus' repo, though:-) MfG, JBG --=20 Jan-Benedict Glaw jbglaw@lug-owl.de . +49-172-7608481 = _ O _ "Eine Freie Meinung in einem Freien Kopf | Gegen Zensur | Gegen Krieg = _ _ O f=C3=BCr einen Freien Staat voll Freier B=C3=BCrger" | im Internet! | i= m Irak! O O O ret =3D do_actions((curr | FREE_SPEECH) & ~(NEW_COPYRIGHT_LAW | DRM | TCPA)= ); --SLfjTIIQuAzj8yil Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (GNU/Linux) iD8DBQFEDxaRHb1edYOZ4bsRArQPAJ9dHEivLGDDafFyf1TJR7kaBk54pgCfQjlk n5yU70t7wYhl0lNHD7cLAgU= =ibTw -----END PGP SIGNATURE----- --SLfjTIIQuAzj8yil-- From tbm@cyrius.com Wed Mar 8 17:35:22 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 17:35:34 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:12805 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133870AbWCHRfW (ORCPT ); Wed, 8 Mar 2006 17:35:22 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id EDFEB64D3D; Wed, 8 Mar 2006 17:43:48 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 3331566EA5; Wed, 8 Mar 2006 17:43:33 +0000 (GMT) Date: Wed, 8 Mar 2006 17:43:33 +0000 From: Martin Michlmayr To: linux-mips@linux-mips.org Subject: Re: [MIPS] Always pass -msoft-float. Message-ID: <20060308174333.GQ8094@deprecation.cyrius.com> References: <20060308173825.GJ12575@lug-owl.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060308173825.GJ12575@lug-owl.de> User-Agent: Mutt/1.5.11+cvs20060126 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10752 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 304 Lines: 8 * Jan-Benedict Glaw [2006-03-08 18:38]: > Is there any chance that you'd also include the diff in these emails? > Maybe that's not a good idea for merges from Linus' repo, though:-) Mine come with patches... you're on git-commits@, right? -- Martin Michlmayr http://www.cyrius.com/ From ths@networkno.de Wed Mar 8 17:38:37 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 17:38:46 +0000 (GMT) Received: from bender.bawue.de ([193.7.176.20]:17307 "EHLO bender.bawue.de") by ftp.linux-mips.org with ESMTP id S8133835AbWCHRih (ORCPT ); Wed, 8 Mar 2006 17:38:37 +0000 Received: from lagash (unknown [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 30612443E1 for ; Wed, 8 Mar 2006 18:45:43 +0100 (MET) Received: from ths by lagash with local (Exim 4.60) (envelope-from ) id 1FH2jh-0004un-Ct for linux-mips@linux-mips.org; Wed, 08 Mar 2006 17:46:09 +0000 Date: Wed, 8 Mar 2006 17:46:09 +0000 To: linux-mips@linux-mips.org Subject: Re: [MIPS] Always pass -msoft-float. Message-ID: <20060308174609.GF8033@networkno.de> References: <20060308173825.GJ12575@lug-owl.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060308173825.GJ12575@lug-owl.de> User-Agent: Mutt/1.5.11+cvs20060126 From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10753 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Content-Length: 633 Lines: 19 On Wed, Mar 08, 2006 at 06:38:25PM +0100, Jan-Benedict Glaw wrote: > On Wed, 2006-03-08 17:06:32 +0000, linux-mips@linux-mips.org wrote: > > Author: Ralf Baechle Wed Mar 8 17:14:49 2006 +0000 > > Commit: 36981cd8fd95a584ca93364b55a3916f9ee7ba13 > > Branch: master > > > > Some people still haven't heared that fp in the kernel is forbidden. > > > > Signed-off-by: Ralf Baechle > > Hi Ralf! > > Is there any chance that you'd also include the diff in these emails? > Maybe that's not a good idea for merges from Linus' repo, though:-) RTFWiki. :-) Thiemo From jbglaw@lug-owl.de Wed Mar 8 17:39:11 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 17:39:32 +0000 (GMT) Received: from lug-owl.de ([195.71.106.12]:31203 "EHLO lug-owl.de") by ftp.linux-mips.org with ESMTP id S8133873AbWCHRjK (ORCPT ); Wed, 8 Mar 2006 17:39:10 +0000 Received: by lug-owl.de (Postfix, from userid 1001) id 6F540F0034; Wed, 8 Mar 2006 18:47:39 +0100 (CET) Date: Wed, 8 Mar 2006 18:47:39 +0100 From: Jan-Benedict Glaw To: linux-mips@linux-mips.org Subject: Re: [MIPS] Always pass -msoft-float. Message-ID: <20060308174739.GK12575@lug-owl.de> Mail-Followup-To: linux-mips@linux-mips.org References: <20060308173825.GJ12575@lug-owl.de> <20060308174333.GQ8094@deprecation.cyrius.com> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="hl1kWnBARzJiTscN" Content-Disposition: inline In-Reply-To: <20060308174333.GQ8094@deprecation.cyrius.com> X-Operating-System: Linux mail 2.6.12.3lug-owl X-gpg-fingerprint: 250D 3BCF 7127 0D8C A444 A961 1DBD 5E75 8399 E1BB X-gpg-key: wwwkeys.de.pgp.net X-Echelon-Enable: howto poison arsenous mail psychological biological nuclear warfare test the bombastical terror of flooding the spy listeners explosion sex drugs and rock'n'roll X-TKUeV: howto poison arsenous mail psychological biological nuclear warfare test the bombastical terror of flooding the spy listeners explosion sex drugs and rock'n'roll User-Agent: Mutt/1.5.9i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10754 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jbglaw@lug-owl.de Precedence: bulk X-list: linux-mips Content-Length: 1253 Lines: 41 --hl1kWnBARzJiTscN Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, 2006-03-08 17:43:33 +0000, Martin Michlmayr wrote: > * Jan-Benedict Glaw [2006-03-08 18:38]: > > Is there any chance that you'd also include the diff in these emails? > > Maybe that's not a good idea for merges from Linus' repo, though:-) >=20 > Mine come with patches... you're on git-commits@, right? Right, I'm on that list. Where are you subscribed to? MfG, JBG --=20 Jan-Benedict Glaw jbglaw@lug-owl.de . +49-172-7608481 = _ O _ "Eine Freie Meinung in einem Freien Kopf | Gegen Zensur | Gegen Krieg = _ _ O f=C3=BCr einen Freien Staat voll Freier B=C3=BCrger" | im Internet! | i= m Irak! O O O ret =3D do_actions((curr | FREE_SPEECH) & ~(NEW_COPYRIGHT_LAW | DRM | TCPA)= ); --hl1kWnBARzJiTscN Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (GNU/Linux) iD8DBQFEDxi7Hb1edYOZ4bsRAg+HAJ9RL2Ih1Mwh7pObjdlT6qitSo2azwCfQos7 sZwJ6bX8cLt7rAf0wHAgg6c= =7sl4 -----END PGP SIGNATURE----- --hl1kWnBARzJiTscN-- From jbglaw@lug-owl.de Wed Mar 8 17:50:31 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 17:50:39 +0000 (GMT) Received: from lug-owl.de ([195.71.106.12]:18669 "EHLO lug-owl.de") by ftp.linux-mips.org with ESMTP id S8133866AbWCHRub (ORCPT ); Wed, 8 Mar 2006 17:50:31 +0000 Received: by lug-owl.de (Postfix, from userid 1001) id B0C46F003B; Wed, 8 Mar 2006 18:59:00 +0100 (CET) Date: Wed, 8 Mar 2006 18:59:00 +0100 From: Jan-Benedict Glaw To: linux-mips@linux-mips.org Subject: Re: [MIPS] Always pass -msoft-float. Message-ID: <20060308175900.GM12575@lug-owl.de> Mail-Followup-To: linux-mips@linux-mips.org References: <20060308173825.GJ12575@lug-owl.de> <20060308174609.GF8033@networkno.de> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="OGLMwEELQbPC02lM" Content-Disposition: inline In-Reply-To: <20060308174609.GF8033@networkno.de> X-Operating-System: Linux mail 2.6.12.3lug-owl X-gpg-fingerprint: 250D 3BCF 7127 0D8C A444 A961 1DBD 5E75 8399 E1BB X-gpg-key: wwwkeys.de.pgp.net X-Echelon-Enable: howto poison arsenous mail psychological biological nuclear warfare test the bombastical terror of flooding the spy listeners explosion sex drugs and rock'n'roll X-TKUeV: howto poison arsenous mail psychological biological nuclear warfare test the bombastical terror of flooding the spy listeners explosion sex drugs and rock'n'roll User-Agent: Mutt/1.5.9i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10755 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jbglaw@lug-owl.de Precedence: bulk X-list: linux-mips Content-Length: 1214 Lines: 41 --OGLMwEELQbPC02lM Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, 2006-03-08 17:46:09 +0000, Thiemo Seufer wrote: > On Wed, Mar 08, 2006 at 06:38:25PM +0100, Jan-Benedict Glaw wrote: > > Is there any chance that you'd also include the diff in these emails? > > Maybe that's not a good idea for merges from Linus' repo, though:-) >=20 > RTFWiki. :-) Thanks, I'm taking the well-known brown paper bag... MfG, JBG --=20 Jan-Benedict Glaw jbglaw@lug-owl.de . +49-172-7608481 = _ O _ "Eine Freie Meinung in einem Freien Kopf | Gegen Zensur | Gegen Krieg = _ _ O f=C3=BCr einen Freien Staat voll Freier B=C3=BCrger" | im Internet! | i= m Irak! O O O ret =3D do_actions((curr | FREE_SPEECH) & ~(NEW_COPYRIGHT_LAW | DRM | TCPA)= ); --OGLMwEELQbPC02lM Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (GNU/Linux) iD8DBQFEDxtkHb1edYOZ4bsRAlPQAJ0QAlgk65mQJ4H8Lt+0eMWFXtqshQCeIhRi +a/UJGzhHJKFGiquQGEFdZ0= =nNdO -----END PGP SIGNATURE----- --OGLMwEELQbPC02lM-- From frederic.temporelli@tele2.fr Wed Mar 8 18:04:46 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 18:04:58 +0000 (GMT) Received: from mailfe05.tele2.fr ([212.247.154.140]:59059 "EHLO swip.net") by ftp.linux-mips.org with ESMTP id S8133888AbWCHSEq (ORCPT ); Wed, 8 Mar 2006 18:04:46 +0000 X-T2-Posting-ID: g63wq726D5fsXb2UbU6LU0KOXzHnTHjCzHZ35sC2MDs= X-Cloudmark-Score: 0.000000 [] Received: from [83.179.129.29] (HELO [192.168.0.32]) by mailfe05.swip.net (CommuniGate Pro SMTP 5.0.8) with ESMTP id 46425844; Wed, 08 Mar 2006 19:13:08 +0100 Received: from 127.0.0.1 (AVG SMTP 7.1.375 [268.2.1/277]); Wed, 08 Mar 2006 19:13:08 +0100 Message-ID: <440F1EB2.8050605@tele2.fr> Date: Wed, 08 Mar 2006 19:13:06 +0100 From: Frederic Temporelli User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.7.12) Gecko/20050915 X-Accept-Language: fr, en To: iet-dev , linux-mips Subject: mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - ioctl unknown command Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=ISO-8859-1; format=flowed Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10756 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: frederic.temporelli@tele2.fr Precedence: bulk X-list: linux-mips Content-Length: 1069 Lines: 33 Hello, I would like to report an ioctl issue using IET 0.4.13 (iSCSI target) and kernel 2.6.16-rc1, running on mips / SGI O2 The driver seems to load nicely, but there was no way to do ioctl on the userspace device /dev/ietctl. I got such messages in syslog: Mar 4 16:47:16 o2 kernel: [4303606.514000] ioctl32(ietd:3448): Unknown cmd fd(4) cmd(81046900){01} arg(7f942ab0) on /dev/ietctl => I've been able to resolve the issue by adding a by-pass (goto do_ioctl) in kernel compat_sys_ioctl function (fs/compat.c) and all is working fine now. I don't know if such issue is related to mips only or is due to changes 2.6.16 kernel I've also did some tries on x86 with linux 2.6.15.5, all was working fine without needing to change anything in the kernel. Did somebody report such issue with IET and recent kernel ? May some people from linux-mips tell if such issue is mips specific ? Best regards. -- Fred -- No virus found in this outgoing message. Checked by AVG Free Edition. Version: 7.1.375 / Virus Database: 268.2.1/277 - Release Date: 08/03/2006 From skiranp@cisco.com Wed Mar 8 18:10:35 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 18:10:45 +0000 (GMT) Received: from sj-iport-2-in.cisco.com ([171.71.176.71]:59581 "EHLO sj-iport-2.cisco.com") by ftp.linux-mips.org with ESMTP id S8133835AbWCHSKf convert rfc822-to-8bit (ORCPT ); Wed, 8 Mar 2006 18:10:35 +0000 Received: from sj-core-1.cisco.com ([171.71.177.237]) by sj-iport-2.cisco.com with ESMTP; 08 Mar 2006 10:19:01 -0800 X-IronPort-AV: i="4.02,176,1139212800"; d="scan'208"; a="312671743:sNHT31492536" Received: from xbh-sjc-221.amer.cisco.com (xbh-sjc-221.cisco.com [128.107.191.63]) by sj-core-1.cisco.com (8.12.10/8.12.6) with ESMTP id k28IITwP000803; Wed, 8 Mar 2006 10:19:00 -0800 (PST) Received: from xmb-sjc-215.amer.cisco.com ([171.70.151.169]) by xbh-sjc-221.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.211); Wed, 8 Mar 2006 10:18:59 -0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - ioctl unknown command Date: Wed, 8 Mar 2006 10:18:57 -0800 Message-ID: <5547014632ED654F971D7E1E0C2E0C3E016546DF@xmb-sjc-215.amer.cisco.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - ioctl unknown command Thread-Index: AcZC3Be9zDsVQbxHQv2UPWDtxWtjMwAAF3YQ From: "Shanthi Kiran Pendyala \(skiranp\)" To: "Frederic Temporelli" , "iet-dev" , "linux-mips" X-OriginalArrivalTime: 08 Mar 2006 18:18:59.0828 (UTC) FILETIME=[C5600340:01C642DC] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10757 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skiranp@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 1664 Lines: 54 I have seen such error messages when userspace app is built in 32bit mode And kernel is built in 64 bit mode. Does this apply to your setup ? The way to fix this is to register a ioctl32 conversion routine in The driver. Google is your friend.. Thx Kiran >-----Original Message----- >From: linux-mips-bounce@linux-mips.org >[mailto:linux-mips-bounce@linux-mips.org] On Behalf Of >Frederic Temporelli >Sent: Wednesday, March 08, 2006 10:13 AM >To: iet-dev; linux-mips >Subject: mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - >ioctl unknown command > >Hello, > >I would like to report an ioctl issue using IET 0.4.13 (iSCSI >target) and kernel 2.6.16-rc1, running on mips / SGI O2 > >The driver seems to load nicely, but there was no way to do >ioctl on the userspace device /dev/ietctl. >I got such messages in syslog: >Mar 4 16:47:16 o2 kernel: [4303606.514000] >ioctl32(ietd:3448): Unknown cmd fd(4) cmd(81046900){01} >arg(7f942ab0) on /dev/ietctl > >=> I've been able to resolve the issue by adding a by-pass (goto >do_ioctl) in kernel compat_sys_ioctl function (fs/compat.c) >and all is working fine now. > >I don't know if such issue is related to mips only or is due to changes >2.6.16 kernel >I've also did some tries on x86 with linux 2.6.15.5, all was >working fine without needing to change anything in the kernel. > >Did somebody report such issue with IET and recent kernel ? >May some people from linux-mips tell if such issue is mips specific ? > >Best regards. >-- >Fred > > >-- >No virus found in this outgoing message. >Checked by AVG Free Edition. >Version: 7.1.375 / Virus Database: 268.2.1/277 - Release Date: >08/03/2006 > From mingz@ele.uri.edu Wed Mar 8 18:16:27 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 18:16:36 +0000 (GMT) Received: from orca.ele.uri.edu ([131.128.51.63]:10430 "EHLO orca.ele.uri.edu") by ftp.linux-mips.org with ESMTP id S8133835AbWCHSQ1 (ORCPT ); Wed, 8 Mar 2006 18:16:27 +0000 Received: from [192.168.1.4] (c-71-192-62-254.hsd1.ma.comcast.net [71.192.62.254]) (authenticated bits=0) by orca.ele.uri.edu (8.13.4/8.13.4) with ESMTP id k28IOndI000501 (version=TLSv1/SSLv3 cipher=RC4-MD5 bits=128 verify=NO); Wed, 8 Mar 2006 13:24:50 -0500 Subject: Re: [Iscsitarget-devel] mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - ioctl unknown command From: Ming Zhang Reply-To: mingz@ele.uri.edu To: Frederic Temporelli Cc: iet-dev , linux-mips In-Reply-To: <440F1EB2.8050605@tele2.fr> References: <440F1EB2.8050605@tele2.fr> Content-Type: text/plain Date: Wed, 08 Mar 2006 13:24:44 -0500 Message-Id: <1141842284.11406.69.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.4.1 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.52 on 131.128.51.63 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10758 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingz@ele.uri.edu Precedence: bulk X-list: linux-mips Content-Length: 1118 Lines: 38 thanks for the catch. could u show us how u did that bypass? thanks. ming On Wed, 2006-03-08 at 19:13 +0100, Frederic Temporelli wrote: > Hello, > > I would like to report an ioctl issue using IET 0.4.13 (iSCSI target) > and kernel 2.6.16-rc1, running on mips / SGI O2 > > The driver seems to load nicely, but there was no way to do ioctl on the > userspace device /dev/ietctl. > I got such messages in syslog: > Mar 4 16:47:16 o2 kernel: [4303606.514000] ioctl32(ietd:3448): Unknown > cmd fd(4) cmd(81046900){01} arg(7f942ab0) on /dev/ietctl > > => I've been able to resolve the issue by adding a by-pass (goto > do_ioctl) in kernel compat_sys_ioctl function (fs/compat.c) and all is > working fine now. > > I don't know if such issue is related to mips only or is due to changes > 2.6.16 kernel > I've also did some tries on x86 with linux 2.6.15.5, all was working > fine without needing to change anything in the kernel. > > Did somebody report such issue with IET and recent kernel ? > May some people from linux-mips tell if such issue is mips specific ? > > Best regards. > -- > Fred > > From frederic.temporelli@tele2.fr Wed Mar 8 19:33:27 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 19:33:40 +0000 (GMT) Received: from mailfe01.tele2.fr ([212.247.154.12]:31117 "EHLO swip.net") by ftp.linux-mips.org with ESMTP id S8133879AbWCHTd1 (ORCPT ); Wed, 8 Mar 2006 19:33:27 +0000 X-T2-Posting-ID: g63wq726D5fsXb2UbU6LU0KOXzHnTHjCzHZ35sC2MDs= X-Cloudmark-Score: 0.000000 [] Received: from [83.179.129.29] (HELO [192.168.0.32]) by mailfe01.swip.net (CommuniGate Pro SMTP 5.0.8) with ESMTP id 126917820; Wed, 08 Mar 2006 20:41:51 +0100 Received: from 127.0.0.1 (AVG SMTP 7.1.375 [268.2.1/277]); Wed, 08 Mar 2006 20:41:50 +0100 Message-ID: <440F337E.3080506@tele2.fr> Date: Wed, 08 Mar 2006 20:41:50 +0100 From: Frederic Temporelli User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.7.12) Gecko/20050915 X-Accept-Language: fr, en To: mingz@ele.uri.edu CC: iet-dev , linux-mips , skiranp@cisco.com Subject: Re: [Iscsitarget-devel] mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - ioctl unknown command References: <440F1EB2.8050605@tele2.fr> <1141842284.11406.69.camel@localhost.localdomain> In-Reply-To: <1141842284.11406.69.camel@localhost.localdomain> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=ISO-8859-1; format=flowed Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10759 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: frederic.temporelli@tele2.fr Precedence: bulk X-list: linux-mips Content-Length: 2538 Lines: 91 Hi, Here's the bypass (really ugly, just skip the following cmd test and directly go to the vfs_ioctl call later in the func). And yes, I'm using a 64bits kernel and app is 32 bits... = 8< ========================== --- compat.c.git 2006-03-08 20:31:27.000000000 +0100 +++ compat.c 2006-03-08 20:30:10.000000000 +0100 @@ -400,6 +400,7 @@ asmlinkage long compat_sys_ioctl(unsigne } else { static int count; + goto do_ioctl; if (++count <= 50) compat_ioctl_error(filp, fd, cmd, arg); error = -EINVAL; = 8< ========================== Regards -- Fred Ming Zhang a écrit : >thanks for the catch. > >could u show us how u did that bypass? thanks. > >ming > > > >On Wed, 2006-03-08 at 19:13 +0100, Frederic Temporelli wrote: > > >>Hello, >> >>I would like to report an ioctl issue using IET 0.4.13 (iSCSI target) >>and kernel 2.6.16-rc1, running on mips / SGI O2 >> >>The driver seems to load nicely, but there was no way to do ioctl on the >>userspace device /dev/ietctl. >>I got such messages in syslog: >>Mar 4 16:47:16 o2 kernel: [4303606.514000] ioctl32(ietd:3448): Unknown >>cmd fd(4) cmd(81046900){01} arg(7f942ab0) on /dev/ietctl >> >>=> I've been able to resolve the issue by adding a by-pass (goto >>do_ioctl) in kernel compat_sys_ioctl function (fs/compat.c) and all is >>working fine now. >> >>I don't know if such issue is related to mips only or is due to changes >>2.6.16 kernel >>I've also did some tries on x86 with linux 2.6.15.5, all was working >>fine without needing to change anything in the kernel. >> >>Did somebody report such issue with IET and recent kernel ? >>May some people from linux-mips tell if such issue is mips specific ? >> >>Best regards. >>-- >>Fred >> >> >> >> > > > >------------------------------------------------------- >This SF.Net email is sponsored by xPML, a groundbreaking scripting language >that extends applications into web and mobile media. Attend the live webcast >and join the prime developer group breaking into this new coding territory! >http://sel.as-us.falkag.net/sel?cmd=lnk&kid=110944&bid=241720&dat=121642 >_______________________________________________ >Iscsitarget-devel mailing list >Iscsitarget-devel@lists.sourceforge.net >https://lists.sourceforge.net/lists/listinfo/iscsitarget-devel > > > -- No virus found in this outgoing message. Checked by AVG Free Edition. Version: 7.1.375 / Virus Database: 268.2.1/277 - Release Date: 08/03/2006 From skiranp@cisco.com Wed Mar 8 19:43:37 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 19:43:49 +0000 (GMT) Received: from sj-iport-3-in.cisco.com ([171.71.176.72]:37404 "EHLO sj-iport-3.cisco.com") by ftp.linux-mips.org with ESMTP id S8133867AbWCHTnh convert rfc822-to-8bit (ORCPT ); Wed, 8 Mar 2006 19:43:37 +0000 Received: from sj-core-1.cisco.com ([171.71.177.237]) by sj-iport-3.cisco.com with ESMTP; 08 Mar 2006 11:52:03 -0800 X-IronPort-AV: i="4.02,176,1139212800"; d="scan'208"; a="413640878:sNHT32995212" Received: from xbh-sjc-211.amer.cisco.com (xbh-sjc-211.cisco.com [171.70.151.144]) by sj-core-1.cisco.com (8.12.10/8.12.6) with ESMTP id k28Jq0w3002637; Wed, 8 Mar 2006 11:52:02 -0800 (PST) Received: from xmb-sjc-215.amer.cisco.com ([171.70.151.169]) by xbh-sjc-211.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.211); Wed, 8 Mar 2006 11:52:01 -0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: RE: [Iscsitarget-devel] mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - ioctl unknown command Date: Wed, 8 Mar 2006 11:52:01 -0800 Message-ID: <5547014632ED654F971D7E1E0C2E0C3E01654777@xmb-sjc-215.amer.cisco.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [Iscsitarget-devel] mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - ioctl unknown command Thread-Index: AcZC6GDxfUYbB21ZRIS2AVseFJWRmwAAQq6g From: "Shanthi Kiran Pendyala \(skiranp\)" To: "Frederic Temporelli" , Cc: "iet-dev" , "linux-mips" X-OriginalArrivalTime: 08 Mar 2006 19:52:01.0914 (UTC) FILETIME=[C48EBDA0:01C642E9] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10760 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skiranp@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 3299 Lines: 117 If kernel is 64bit and app is 32bit the size of ioctl structures exchanged Between userspace and kernel space will be different if you use data types Like pointer, long, size_t etc., Here is LWN article which explains the register_ioctl32_conversion routine That you need to use. http://lwn.net/Articles/115651/ Thx Kiran >-----Original Message----- >From: Frederic Temporelli [mailto:frederic.temporelli@tele2.fr] >Sent: Wednesday, March 08, 2006 11:42 AM >To: mingz@ele.uri.edu >Cc: iet-dev; linux-mips; Shanthi Kiran Pendyala (skiranp) >Subject: Re: [Iscsitarget-devel] mips kernel 2.6.16rc1 + IET >0.4.13 - /dev/ietctl - ioctl unknown command > >Hi, > > >Here's the bypass (really ugly, just skip the following cmd >test and directly go to the vfs_ioctl call later in the func). >And yes, I'm using a 64bits kernel and app is 32 bits... > >= 8< ========================== >--- compat.c.git 2006-03-08 20:31:27.000000000 +0100 >+++ compat.c 2006-03-08 20:30:10.000000000 +0100 >@@ -400,6 +400,7 @@ asmlinkage long compat_sys_ioctl(unsigne > } else { > static int count; > >+ goto do_ioctl; > if (++count <= 50) > compat_ioctl_error(filp, fd, cmd, arg); > error = -EINVAL; >= 8< ========================== > >Regards >-- >Fred > > >Ming Zhang a écrit : > >>thanks for the catch. >> >>could u show us how u did that bypass? thanks. >> >>ming >> >> >> >>On Wed, 2006-03-08 at 19:13 +0100, Frederic Temporelli wrote: >> >> >>>Hello, >>> >>>I would like to report an ioctl issue using IET 0.4.13 >(iSCSI target) >>>and kernel 2.6.16-rc1, running on mips / SGI O2 >>> >>>The driver seems to load nicely, but there was no way to do ioctl on >>>the userspace device /dev/ietctl. >>>I got such messages in syslog: >>>Mar 4 16:47:16 o2 kernel: [4303606.514000] ioctl32(ietd:3448): >>>Unknown cmd fd(4) cmd(81046900){01} arg(7f942ab0) on /dev/ietctl >>> >>>=> I've been able to resolve the issue by adding a by-pass (goto >>>do_ioctl) in kernel compat_sys_ioctl function (fs/compat.c) and all >>>is working fine now. >>> >>>I don't know if such issue is related to mips only or is due to >>>changes >>>2.6.16 kernel >>>I've also did some tries on x86 with linux 2.6.15.5, all was working >>>fine without needing to change anything in the kernel. >>> >>>Did somebody report such issue with IET and recent kernel ? >>>May some people from linux-mips tell if such issue is mips specific ? >>> >>>Best regards. >>>-- >>>Fred >>> >>> >>> >>> >> >> >> >>------------------------------------------------------- >>This SF.Net email is sponsored by xPML, a groundbreaking scripting >>language that extends applications into web and mobile media. Attend >>the live webcast and join the prime developer group breaking >into this new coding territory! >>http://sel.as-us.falkag.net/sel?cmd=lnk&kid=110944&bid=241720& >dat=12164 >>2 _______________________________________________ >>Iscsitarget-devel mailing list >>Iscsitarget-devel@lists.sourceforge.net >>https://lists.sourceforge.net/lists/listinfo/iscsitarget-devel >> >> >> > > > >-- >No virus found in this outgoing message. >Checked by AVG Free Edition. >Version: 7.1.375 / Virus Database: 268.2.1/277 - Release Date: >08/03/2006 > From mingz@ele.uri.edu Wed Mar 8 19:44:15 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 19:44:36 +0000 (GMT) Received: from orca.ele.uri.edu ([131.128.51.63]:5836 "EHLO orca.ele.uri.edu") by ftp.linux-mips.org with ESMTP id S8133884AbWCHTn5 (ORCPT ); Wed, 8 Mar 2006 19:43:57 +0000 Received: from [192.168.1.4] (c-71-192-62-254.hsd1.ma.comcast.net [71.192.62.254]) (authenticated bits=0) by orca.ele.uri.edu (8.13.4/8.13.4) with ESMTP id k28JqK3u029168 (version=TLSv1/SSLv3 cipher=RC4-MD5 bits=128 verify=NO); Wed, 8 Mar 2006 14:52:21 -0500 Subject: Re: [Iscsitarget-devel] mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - ioctl unknown command From: Ming Zhang Reply-To: mingz@ele.uri.edu To: Frederic Temporelli Cc: iet-dev , linux-mips , skiranp@cisco.com In-Reply-To: <440F337E.3080506@tele2.fr> References: <440F1EB2.8050605@tele2.fr> <1141842284.11406.69.camel@localhost.localdomain> <440F337E.3080506@tele2.fr> Content-Type: text/plain; charset=utf-8 Date: Wed, 08 Mar 2006 14:52:14 -0500 Message-Id: <1141847534.11406.85.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.4.1 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.52 on 131.128.51.63 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10761 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingz@ele.uri.edu Precedence: bulk X-list: linux-mips Content-Length: 2818 Lines: 98 just tested, iet works on Linux dopteron.localdomain 2.6.16-rc5 #1 SMP PREEMPT Wed Mar 8 14:11:41 EST 2006 i686 athlon i386 GNU/Linux so i would think this is a mips specific issue. ming On Wed, 2006-03-08 at 20:41 +0100, Frederic Temporelli wrote: > Hi, > > > Here's the bypass (really ugly, just skip the following cmd test and > directly go to the vfs_ioctl call later in the func). > And yes, I'm using a 64bits kernel and app is 32 bits... > > = 8< ========================== > --- compat.c.git 2006-03-08 20:31:27.000000000 +0100 > +++ compat.c 2006-03-08 20:30:10.000000000 +0100 > @@ -400,6 +400,7 @@ asmlinkage long compat_sys_ioctl(unsigne > } else { > static int count; > > + goto do_ioctl; > if (++count <= 50) > compat_ioctl_error(filp, fd, cmd, arg); > error = -EINVAL; > = 8< ========================== > > Regards > -- > Fred > > > Ming Zhang a écrit : > > >thanks for the catch. > > > >could u show us how u did that bypass? thanks. > > > >ming > > > > > > > >On Wed, 2006-03-08 at 19:13 +0100, Frederic Temporelli wrote: > > > > > >>Hello, > >> > >>I would like to report an ioctl issue using IET 0.4.13 (iSCSI target) > >>and kernel 2.6.16-rc1, running on mips / SGI O2 > >> > >>The driver seems to load nicely, but there was no way to do ioctl on the > >>userspace device /dev/ietctl. > >>I got such messages in syslog: > >>Mar 4 16:47:16 o2 kernel: [4303606.514000] ioctl32(ietd:3448): Unknown > >>cmd fd(4) cmd(81046900){01} arg(7f942ab0) on /dev/ietctl > >> > >>=> I've been able to resolve the issue by adding a by-pass (goto > >>do_ioctl) in kernel compat_sys_ioctl function (fs/compat.c) and all is > >>working fine now. > >> > >>I don't know if such issue is related to mips only or is due to changes > >>2.6.16 kernel > >>I've also did some tries on x86 with linux 2.6.15.5, all was working > >>fine without needing to change anything in the kernel. > >> > >>Did somebody report such issue with IET and recent kernel ? > >>May some people from linux-mips tell if such issue is mips specific ? > >> > >>Best regards. > >>-- > >>Fred > >> > >> > >> > >> > > > > > > > >------------------------------------------------------- > >This SF.Net email is sponsored by xPML, a groundbreaking scripting language > >that extends applications into web and mobile media. Attend the live webcast > >and join the prime developer group breaking into this new coding territory! > >http://sel.as-us.falkag.net/sel?cmd=lnk&kid=110944&bid=241720&dat=121642 > >_______________________________________________ > >Iscsitarget-devel mailing list > >Iscsitarget-devel@lists.sourceforge.net > >https://lists.sourceforge.net/lists/listinfo/iscsitarget-devel > > > > > > > > > From mingz@ele.uri.edu Wed Mar 8 19:54:36 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 19:54:47 +0000 (GMT) Received: from orca.ele.uri.edu ([131.128.51.63]:36301 "EHLO orca.ele.uri.edu") by ftp.linux-mips.org with ESMTP id S8133867AbWCHTyg (ORCPT ); Wed, 8 Mar 2006 19:54:36 +0000 Received: from [192.168.1.4] (c-71-192-62-254.hsd1.ma.comcast.net [71.192.62.254]) (authenticated bits=0) by orca.ele.uri.edu (8.13.4/8.13.4) with ESMTP id k28K2xgq032119 (version=TLSv1/SSLv3 cipher=RC4-MD5 bits=128 verify=NO); Wed, 8 Mar 2006 15:03:00 -0500 Subject: RE: [Iscsitarget-devel] mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - ioctl unknown command From: Ming Zhang Reply-To: mingz@ele.uri.edu To: "Shanthi Kiran Pendyala (skiranp)" Cc: Frederic Temporelli , iet-dev , linux-mips In-Reply-To: <5547014632ED654F971D7E1E0C2E0C3E01654777@xmb-sjc-215.amer.cisco.com> References: <5547014632ED654F971D7E1E0C2E0C3E01654777@xmb-sjc-215.amer.cisco.com> Content-Type: text/plain; charset=utf-8 Date: Wed, 08 Mar 2006 15:02:54 -0500 Message-Id: <1141848174.11406.88.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.4.1 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.52 on 131.128.51.63 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10762 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingz@ele.uri.edu Precedence: bulk X-list: linux-mips Content-Length: 3810 Lines: 131 we use unlock_ioctl and we only have u32 u64 like data in the structures. anyway i dig out this email http://sourceforge.net/mailarchive/message.php?msg_id=13230597 u might meet same issue. Ming On Wed, 2006-03-08 at 11:52 -0800, Shanthi Kiran Pendyala (skiranp) wrote: > If kernel is 64bit and app is 32bit the size of ioctl structures exchanged > Between userspace and kernel space will be different if you use data types > Like pointer, long, size_t etc., > > Here is LWN article which explains the register_ioctl32_conversion routine > That you need to use. > > http://lwn.net/Articles/115651/ > > Thx > Kiran > > > >-----Original Message----- > >From: Frederic Temporelli [mailto:frederic.temporelli@tele2.fr] > >Sent: Wednesday, March 08, 2006 11:42 AM > >To: mingz@ele.uri.edu > >Cc: iet-dev; linux-mips; Shanthi Kiran Pendyala (skiranp) > >Subject: Re: [Iscsitarget-devel] mips kernel 2.6.16rc1 + IET > >0.4.13 - /dev/ietctl - ioctl unknown command > > > >Hi, > > > > > >Here's the bypass (really ugly, just skip the following cmd > >test and directly go to the vfs_ioctl call later in the func). > >And yes, I'm using a 64bits kernel and app is 32 bits... > > > >= 8< ========================== > >--- compat.c.git 2006-03-08 20:31:27.000000000 +0100 > >+++ compat.c 2006-03-08 20:30:10.000000000 +0100 > >@@ -400,6 +400,7 @@ asmlinkage long compat_sys_ioctl(unsigne > > } else { > > static int count; > > > >+ goto do_ioctl; > > if (++count <= 50) > > compat_ioctl_error(filp, fd, cmd, arg); > > error = -EINVAL; > >= 8< ========================== > > > >Regards > >-- > >Fred > > > > > >Ming Zhang a écrit : > > > >>thanks for the catch. > >> > >>could u show us how u did that bypass? thanks. > >> > >>ming > >> > >> > >> > >>On Wed, 2006-03-08 at 19:13 +0100, Frederic Temporelli wrote: > >> > >> > >>>Hello, > >>> > >>>I would like to report an ioctl issue using IET 0.4.13 > >(iSCSI target) > >>>and kernel 2.6.16-rc1, running on mips / SGI O2 > >>> > >>>The driver seems to load nicely, but there was no way to do ioctl on > >>>the userspace device /dev/ietctl. > >>>I got such messages in syslog: > >>>Mar 4 16:47:16 o2 kernel: [4303606.514000] ioctl32(ietd:3448): > >>>Unknown cmd fd(4) cmd(81046900){01} arg(7f942ab0) on /dev/ietctl > >>> > >>>=> I've been able to resolve the issue by adding a by-pass (goto > >>>do_ioctl) in kernel compat_sys_ioctl function (fs/compat.c) and all > >>>is working fine now. > >>> > >>>I don't know if such issue is related to mips only or is due to > >>>changes > >>>2.6.16 kernel > >>>I've also did some tries on x86 with linux 2.6.15.5, all was working > >>>fine without needing to change anything in the kernel. > >>> > >>>Did somebody report such issue with IET and recent kernel ? > >>>May some people from linux-mips tell if such issue is mips specific ? > >>> > >>>Best regards. > >>>-- > >>>Fred > >>> > >>> > >>> > >>> > >> > >> > >> > >>------------------------------------------------------- > >>This SF.Net email is sponsored by xPML, a groundbreaking scripting > >>language that extends applications into web and mobile media. Attend > >>the live webcast and join the prime developer group breaking > >into this new coding territory! > >>http://sel.as-us.falkag.net/sel?cmd=lnk&kid=110944&bid=241720& > >dat=12164 > >>2 _______________________________________________ > >>Iscsitarget-devel mailing list > >>Iscsitarget-devel@lists.sourceforge.net > >>https://lists.sourceforge.net/lists/listinfo/iscsitarget-devel > >> > >> > >> > > > > > > > >-- > >No virus found in this outgoing message. > >Checked by AVG Free Edition. > >Version: 7.1.375 / Virus Database: 268.2.1/277 - Release Date: > >08/03/2006 > > From romieu@fr.zoreil.com Wed Mar 8 22:35:36 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Mar 2006 22:35:46 +0000 (GMT) Received: from electric-eye.fr.zoreil.com ([213.41.134.224]:48041 "EHLO fr.zoreil.com") by ftp.linux-mips.org with ESMTP id S8133889AbWCHWfg (ORCPT ); Wed, 8 Mar 2006 22:35:36 +0000 Received: from electric-eye.fr.zoreil.com (localhost.localdomain [127.0.0.1]) by fr.zoreil.com (8.13.4/8.12.1) with ESMTP id k28Mfgl3014256; Wed, 8 Mar 2006 23:41:42 +0100 Received: (from romieu@localhost) by electric-eye.fr.zoreil.com (8.13.4/8.12.1) id k28Mfd78014255; Wed, 8 Mar 2006 23:41:39 +0100 Date: Wed, 8 Mar 2006 23:41:39 +0100 From: Francois Romieu To: Geert Uytterhoeven Cc: Ralf Baechle , Martin Michlmayr , netdev@vger.kernel.org, Linux/MIPS Development , "P. Horton" Subject: Re: [PATCH, RESEND] Add MWI workaround for Tulip DC21143 Message-ID: <20060308224139.GA7536@electric-eye.fr.zoreil.com> References: <20060129230816.GD4094@colonel-panic.org> <20060218220851.GA1601@colonel-panic.org> <20060306225131.GA23327@unjust.cyrius.com> <20060306231530.GB16082@electric-eye.fr.zoreil.com> <20060307035824.GA24018@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.1i X-Organisation: Land of Sunshine Inc. Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10763 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: romieu@fr.zoreil.com Precedence: bulk X-list: linux-mips Content-Length: 2210 Lines: 64 Geert Uytterhoeven : > On Tue, 7 Mar 2006, Ralf Baechle wrote: [...] > > I'm just not convinced of having such a workaround as a build option. > > The average person building a a kernel will probably not know if the > > option needs to be enabled or not. > > Indeed, if it's mentioned in the errata of the chip, the driver should take > care of it. Something like the patch below (+Mr Horton Signed-off-by: and description): diff --git a/drivers/net/tulip/tulip.h b/drivers/net/tulip/tulip.h index 05d2d96..d109540 100644 --- a/drivers/net/tulip/tulip.h +++ b/drivers/net/tulip/tulip.h @@ -262,7 +262,14 @@ enum t21143_csr6_bits { #define RX_RING_SIZE 128 #define MEDIA_MASK 31 +/* MWI can fail on 21143 rev 65 if the receive buffer ends + on a cache line boundary. Ensure it doesn't ... */ + +#ifdef CONFIG_MIPS_COBALT +#define PKT_BUF_SZ (1536 + 4) +#else #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ +#endif #define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */ diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c index c67c912..ca6eeda 100644 --- a/drivers/net/tulip/tulip_core.c +++ b/drivers/net/tulip/tulip_core.c @@ -294,6 +294,8 @@ static void tulip_up(struct net_device * if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii)) iowrite32(0x00040000, ioaddr + CSR6); + printk(KERN_DEBUG "%s: CSR0 %08x\n", dev->name, tp->csr0); + /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ iowrite32(0x00000001, ioaddr + CSR0); udelay(100); @@ -1155,8 +1157,10 @@ static void __devinit tulip_mwi_config ( /* if we have any cache line size at all, we can do MRM */ csr0 |= MRM; +#ifndef CONFIG_MIPS_COBALT /* ...and barring hardware bugs, MWI */ if (!(tp->chip_id == DC21143 && tp->revision == 65)) +#endif csr0 |= MWI; /* set or disable MWI in the standard PCI command bit. @@ -1182,7 +1186,7 @@ static void __devinit tulip_mwi_config ( */ switch (cache) { case 8: - csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift); + csr0 |= MRL | (1 << CALShift) | (8 << BurstLenShift); break; case 16: csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift); From zzh.hust@gmail.com Thu Mar 9 01:39:49 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Mar 2006 01:39:57 +0000 (GMT) Received: from nproxy.gmail.com ([64.233.182.207]:31414 "EHLO nproxy.gmail.com") by ftp.linux-mips.org with ESMTP id S8133906AbWCIBjt convert rfc822-to-8bit (ORCPT ); Thu, 9 Mar 2006 01:39:49 +0000 Received: by nproxy.gmail.com with SMTP id p77so252585nfc for ; Wed, 08 Mar 2006 17:48:22 -0800 (PST) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=IeKwPMxhGzaHH7mLvVF9CTO/8Y3yrqqMrYqGtgpz5DVz+qnLH39xqXOoAr9hNQn/S/9qLthU67ABf4fu2AZlo65YKbvg+g+4Q5ozqPh8qN2O6krongCCE6bF+6NmLxFqmwJzsmNQE++Ue62ZShVye/bVrWCXqXwRiRw9lnKwlBI= Received: by 10.49.95.20 with SMTP id x20mr677867nfl; Wed, 08 Mar 2006 17:48:21 -0800 (PST) Received: by 10.48.144.19 with HTTP; Wed, 8 Mar 2006 17:48:21 -0800 (PST) Message-ID: <50c9a2250603081748u639d35c0n272d53e24acc9f02@mail.gmail.com> Date: Thu, 9 Mar 2006 09:48:21 +0800 From: zhuzhenhua To: linux-mips Subject: how to select the filesystem for nand flash? MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10764 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zzh.hust@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 294 Lines: 8 In the linux, I find there are two solutions for nand flash: one is YAFFS2/JFFS2 + MTD, other is EXT2/EXT3+FTL. Because we have to implement vfat based FTL for our u-disk,so i wonder if the ext2/ext3 + FTL is stable enough to be root filesystem? thanks for any hints. Best Regards Zhuzhenhua From zhaoyw@langchao.com Thu Mar 9 02:46:32 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Mar 2006 02:46:40 +0000 (GMT) Received: from [218.57.135.52] ([218.57.135.52]:14090 "EHLO mail.langchao.com") by ftp.linux-mips.org with ESMTP id S8133924AbWCICqc (ORCPT ); Thu, 9 Mar 2006 02:46:32 +0000 Received: from [10.30.11.17] ([192.168.1.1]) by mail.langchao.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 9 Mar 2006 10:53:29 +0800 Message-ID: <440F999F.4040703@langchao.com> Date: Thu, 09 Mar 2006 10:57:35 +0800 From: zhaoyw User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.7.7) Gecko/20050422 Red Hat/1.7.7-1.4.2 X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: help Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 09 Mar 2006 02:53:29.0609 (UTC) FILETIME=[A532C790:01C64324] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10765 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhaoyw@langchao.com Precedence: bulk X-list: linux-mips Content-Length: 265 Lines: 6 I seem to get cross-compile using Buildroot . And tinyx included . But when I nfs program to my target board. It can not run. Prompt is : /usr/X11R6/bin/Xfbdev:1: syntax error : " ( " unexpected. PS: my target board is mips arch. Any suggestion. Thanks in advance. From tbm@cyrius.com Thu Mar 9 05:57:49 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Mar 2006 05:58:01 +0000 (GMT) Received: from sorrow.cyrius.com ([65.19.161.204]:778 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S8133408AbWCIF5s (ORCPT ); Thu, 9 Mar 2006 05:57:48 +0000 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 9EC6F64D3D; Thu, 9 Mar 2006 06:06:21 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id DE41266EA8; Thu, 9 Mar 2006 06:06:06 +0000 (GMT) Date: Thu, 9 Mar 2006 06:06:06 +0000 From: Martin Michlmayr To: linux-mips@linux-mips.org Subject: 1480: ethernet stops working, box okay Message-ID: <20060309060606.GA16963@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.11+cvs20060126 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10766 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 390 Lines: 10 I just thought that my 1480 box had crashed, but as it turns out I could still issue commands on the serial console - however, the network wasn't working anymore. There was nothing in dmesg and bringing the interface down and up again didn't help. I've seen this twice now while compiling lots of stuff in parallel. Has anyone else seen this? -- Martin Michlmayr http://www.cyrius.com/ From geert@linux-m68k.org Thu Mar 9 09:29:30 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Mar 2006 09:29:40 +0000 (GMT) Received: from witte.sonytel.be ([80.88.33.193]:8631 "EHLO witte.sonytel.be") by ftp.linux-mips.org with ESMTP id S8133439AbWCIJ3a (ORCPT ); Thu, 9 Mar 2006 09:29:30 +0000 Received: from pademelon.sonytel.be (mail.sonytel.be [43.221.60.197]) by witte.sonytel.be (8.12.10/8.12.10) with ESMTP id k299bplR009623; Thu, 9 Mar 2006 10:37:51 +0100 (MET) Date: Thu, 9 Mar 2006 10:37:50 +0100 (CET) From: Geert Uytterhoeven To: Francois Romieu cc: Ralf Baechle , Martin Michlmayr , netdev@vger.kernel.org, Linux/MIPS Development , "P. Horton" Subject: Re: [PATCH, RESEND] Add MWI workaround for Tulip DC21143 In-Reply-To: <20060308224139.GA7536@electric-eye.fr.zoreil.com> Message-ID: References: <20060129230816.GD4094@colonel-panic.org> <20060218220851.GA1601@colonel-panic.org> <20060306225131.GA23327@unjust.cyrius.com> <20060306231530.GB16082@electric-eye.fr.zoreil.com> <20060307035824.GA24018@linux-mips.org> <20060308224139.GA7536@electric-eye.fr.zoreil.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10767 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Content-Length: 2891 Lines: 82 On Wed, 8 Mar 2006, Francois Romieu wrote: > Geert Uytterhoeven : > > On Tue, 7 Mar 2006, Ralf Baechle wrote: > [...] > > > I'm just not convinced of having such a workaround as a build option. > > > The average person building a a kernel will probably not know if the > > > option needs to be enabled or not. > > > > Indeed, if it's mentioned in the errata of the chip, the driver should take > > care of it. > > Something like the patch below (+Mr Horton Signed-off-by: and description): > > diff --git a/drivers/net/tulip/tulip.h b/drivers/net/tulip/tulip.h > index 05d2d96..d109540 100644 > --- a/drivers/net/tulip/tulip.h > +++ b/drivers/net/tulip/tulip.h > @@ -262,7 +262,14 @@ enum t21143_csr6_bits { > #define RX_RING_SIZE 128 > #define MEDIA_MASK 31 > > +/* MWI can fail on 21143 rev 65 if the receive buffer ends > + on a cache line boundary. Ensure it doesn't ... */ > + > +#ifdef CONFIG_MIPS_COBALT > +#define PKT_BUF_SZ (1536 + 4) > +#else > #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ > +#endif > > #define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */ > > diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c > index c67c912..ca6eeda 100644 > --- a/drivers/net/tulip/tulip_core.c > +++ b/drivers/net/tulip/tulip_core.c > @@ -294,6 +294,8 @@ static void tulip_up(struct net_device * > if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii)) > iowrite32(0x00040000, ioaddr + CSR6); > > + printk(KERN_DEBUG "%s: CSR0 %08x\n", dev->name, tp->csr0); > + > /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ > iowrite32(0x00000001, ioaddr + CSR0); > udelay(100); > @@ -1155,8 +1157,10 @@ static void __devinit tulip_mwi_config ( > /* if we have any cache line size at all, we can do MRM */ > csr0 |= MRM; > > +#ifndef CONFIG_MIPS_COBALT > /* ...and barring hardware bugs, MWI */ > if (!(tp->chip_id == DC21143 && tp->revision == 65)) > +#endif > csr0 |= MWI; So when compiling for Cobalt, we work around the hardware bug, while for other platforms, we just disable MWI? Wouldn't it be possible to always (I mean, when a rev 65 chip is detected) work around the bug? > /* set or disable MWI in the standard PCI command bit. > @@ -1182,7 +1186,7 @@ static void __devinit tulip_mwi_config ( > */ > switch (cache) { > case 8: > - csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift); > + csr0 |= MRL | (1 << CALShift) | (8 << BurstLenShift); > break; > case 16: > csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift); Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From matej.kupljen@ultra.si Thu Mar 9 09:43:29 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Mar 2006 09:43:37 +0000 (GMT) Received: from deliver-1.mx.triera.net ([213.161.0.31]:50314 "HELO deliver-1.mx.triera.net") by ftp.linux-mips.org with SMTP id S8133398AbWCIJn3 (ORCPT ); Thu, 9 Mar 2006 09:43:29 +0000 Received: from localhost (in-2.mx.triera.net [213.161.0.26]) by deliver-1.mx.triera.net (Postfix) with ESMTP id EBCAEC01B; Thu, 9 Mar 2006 10:51:59 +0100 (CET) Received: from smtp.triera.net (smtp.triera.net [213.161.0.30]) by in-2.mx.triera.net (Postfix) with SMTP id 746851BC089; Thu, 9 Mar 2006 10:52:02 +0100 (CET) Received: from kupljenlap (unknown [213.161.20.162]) by smtp.triera.net (Postfix) with ESMTP id DA3C11A18B2; Thu, 9 Mar 2006 10:52:01 +0100 (CET) Subject: Re: help From: Matej Kupljen To: zhaoyw Cc: linux-mips@linux-mips.org In-Reply-To: <440F999F.4040703@langchao.com> References: <440F999F.4040703@langchao.com> Content-Type: text/plain Date: Thu, 09 Mar 2006 10:51:59 +0100 Message-Id: <1141897920.7135.1.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.4.2.1 Content-Transfer-Encoding: 7bit X-Virus-Scanned: Triera AV Service Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10768 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: matej.kupljen@ultra.si Precedence: bulk X-list: linux-mips Content-Length: 338 Lines: 13 Hi > I seem to get cross-compile using Buildroot . And tinyx included . > But when I nfs program to my target board. It can not run. > Prompt is : /usr/X11R6/bin/Xfbdev:1: syntax error : " ( " unexpected. Are you sure, this is a cross compiled binary? Check it with the file command on the host machine, like: # file Xfbdev BR, Matej From trix@specifix.com Thu Mar 9 09:53:48 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Mar 2006 09:53:57 +0000 (GMT) Received: from w099.z064220152.sjc-ca.dsl.cnc.net ([64.220.152.99]:19592 "EHLO duck.specifix.com") by ftp.linux-mips.org with ESMTP id S8133426AbWCIJxs (ORCPT ); Thu, 9 Mar 2006 09:53:48 +0000 Received: from localhost.localdomain (duck.corp.specifix.com [192.168.1.1]) by duck.specifix.com (Postfix) with ESMTP id D5B56FC4F; Thu, 9 Mar 2006 02:02:21 -0800 (PST) Date: Thu, 09 Mar 2006 04:05:15 -0600 To: "Martin Michlmayr" , linux-mips@linux-mips.org Subject: Re: 1480: ethernet stops working, box okay References: <20060309060606.GA16963@deprecation.cyrius.com> From: "Tom Rix" Organization: specifix Content-Type: text/plain; format=flowed; delsp=yes; charset=utf-8 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Message-ID: In-Reply-To: <20060309060606.GA16963@deprecation.cyrius.com> User-Agent: Opera M2/8.51 (Linux, build 1462) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10769 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: trix@specifix.com Precedence: bulk X-list: linux-mips Content-Length: 648 Lines: 21 I have seen something similar on my 1250. I have a patch that should help. I am cleaning it up and will post it shortly. Tom On Thu, 09 Mar 2006 00:06:06 -0600, Martin Michlmayr wrote: > I just thought that my 1480 box had crashed, but as it turns out I > could still issue commands on the serial console - however, the > network wasn't working anymore. There was nothing in dmesg and > bringing the interface down and up again didn't help. I've seen this > twice now while compiling lots of stuff in parallel. > > Has anyone else seen this? -- Using Opera's revolutionary e-mail client: http://www.opera.com/mail/ From mingz@ele.uri.edu Thu Mar 9 14:10:58 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Mar 2006 14:11:08 +0000 (GMT) Received: from orca.ele.uri.edu ([131.128.51.63]:26591 "EHLO orca.ele.uri.edu") by ftp.linux-mips.org with ESMTP id S8133603AbWCIOK6 (ORCPT ); Thu, 9 Mar 2006 14:10:58 +0000 Received: from [192.168.1.4] (c-71-192-62-254.hsd1.ma.comcast.net [71.192.62.254]) (authenticated bits=0) by orca.ele.uri.edu (8.13.4/8.13.4) with ESMTP id k29EJQiB030734 (version=TLSv1/SSLv3 cipher=RC4-MD5 bits=128 verify=NO); Thu, 9 Mar 2006 09:19:26 -0500 Subject: Re: [Iscsitarget-devel] RE: mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - ioctl unknown command From: Ming Zhang Reply-To: mingz@ele.uri.edu To: "Shanthi Kiran Pendyala (skiranp)" Cc: Frederic Temporelli , iet-dev , linux-mips In-Reply-To: <5547014632ED654F971D7E1E0C2E0C3E016546DF@xmb-sjc-215.amer.cisco.com> References: <5547014632ED654F971D7E1E0C2E0C3E016546DF@xmb-sjc-215.amer.cisco.com> Content-Type: text/plain Date: Thu, 09 Mar 2006 09:19:21 -0500 Message-Id: <1141913962.7361.39.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.4.1 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.52 on 131.128.51.63 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10771 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingz@ele.uri.edu Precedence: bulk X-list: linux-mips Content-Length: 2550 Lines: 75 thanks. i guess this is the reason. @Frederic, could you confirm this? also if you compile u user space as 64bit, it should be ok then. ming On Wed, 2006-03-08 at 10:18 -0800, Shanthi Kiran Pendyala (skiranp) wrote: > I have seen such error messages when userspace app is built in 32bit > mode > And kernel is built in 64 bit mode. Does this apply to your setup ? > > The way to fix this is to register a ioctl32 conversion routine in > The driver. Google is your friend.. > > Thx > Kiran > > >-----Original Message----- > >From: linux-mips-bounce@linux-mips.org > >[mailto:linux-mips-bounce@linux-mips.org] On Behalf Of > >Frederic Temporelli > >Sent: Wednesday, March 08, 2006 10:13 AM > >To: iet-dev; linux-mips > >Subject: mips kernel 2.6.16rc1 + IET 0.4.13 - /dev/ietctl - > >ioctl unknown command > > > >Hello, > > > >I would like to report an ioctl issue using IET 0.4.13 (iSCSI > >target) and kernel 2.6.16-rc1, running on mips / SGI O2 > > > >The driver seems to load nicely, but there was no way to do > >ioctl on the userspace device /dev/ietctl. > >I got such messages in syslog: > >Mar 4 16:47:16 o2 kernel: [4303606.514000] > >ioctl32(ietd:3448): Unknown cmd fd(4) cmd(81046900){01} > >arg(7f942ab0) on /dev/ietctl > > > >=> I've been able to resolve the issue by adding a by-pass (goto > >do_ioctl) in kernel compat_sys_ioctl function (fs/compat.c) > >and all is working fine now. > > > >I don't know if such issue is related to mips only or is due to changes > >2.6.16 kernel > >I've also did some tries on x86 with linux 2.6.15.5, all was > >working fine without needing to change anything in the kernel. > > > >Did somebody report such issue with IET and recent kernel ? > >May some people from linux-mips tell if such issue is mips specific ? > > > >Best regards. > >-- > >Fred > > > > > >-- > >No virus found in this outgoing message. > >Checked by AVG Free Edition. > >Version: 7.1.375 / Virus Database: 268.2.1/277 - Release Date: > >08/03/2006 > > > > > ------------------------------------------------------- > This SF.Net email is sponsored by xPML, a groundbreaking scripting language > that extends applications into web and mobile media. Attend the live webcast > and join the prime developer group breaking into this new coding territory! > http://sel.as-us.falkag.net/sel?cmd=lnk&kid0944&bid$1720&dat1642 > _______________________________________________ > Iscsitarget-devel mailing list > Iscsitarget-devel@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/iscsitarget-devel From romieu@fr.zoreil.com Thu Mar 9 22:39:32 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Mar 2006 22:39:42 +0000 (GMT) Received: from electric-eye.fr.zoreil.com ([213.41.134.224]:57065 "EHLO fr.zoreil.com") by ftp.linux-mips.org with ESMTP id S8133941AbWCIWjc (ORCPT ); Thu, 9 Mar 2006 22:39:32 +0000 Received: from electric-eye.fr.zoreil.com (localhost.localdomain [127.0.0.1]) by fr.zoreil.com (8.13.4/8.12.1) with ESMTP id k29MivC4014174; Thu, 9 Mar 2006 23:44:57 +0100 Received: (from romieu@localhost) by electric-eye.fr.zoreil.com (8.13.4/8.12.1) id k29MiuEk014173; Thu, 9 Mar 2006 23:44:56 +0100 Date: Thu, 9 Mar 2006 23:44:56 +0100 From: Francois Romieu To: Geert Uytterhoeven Cc: Ralf Baechle , Martin Michlmayr , netdev@vger.kernel.org, Linux/MIPS Development , "P. Horton" Subject: Re: [PATCH, RESEND] Add MWI workaround for Tulip DC21143 Message-ID: <20060309224456.GB9103@electric-eye.fr.zoreil.com> References: <20060129230816.GD4094@colonel-panic.org> <20060218220851.GA1601@colonel-panic.org> <20060306225131.GA23327@unjust.cyrius.com> <20060306231530.GB16082@electric-eye.fr.zoreil.com> <20060307035824.GA24018@linux-mips.org> <20060308224139.GA7536@electric-eye.fr.zoreil.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.1i X-Organisation: Land of Sunshine Inc. Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10772 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: romieu@fr.zoreil.com Precedence: bulk X-list: linux-mips Content-Length: 477 Lines: 17 Geert Uytterhoeven : [...] > So when compiling for Cobalt, we work around the hardware bug, while for other > platforms, we just disable MWI? > > Wouldn't it be possible to always (I mean, when a rev 65 chip is detected) > work around the bug? Of course it is possible but it is not the same semantic as the initial patch (not that I know if it is right or not). So: - does the issue exist beyond Cobalt hosts ? - is the fix Cobalt-only ? -- Ueimor From zzh.hust@gmail.com Fri Mar 10 00:43:00 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Mar 2006 00:43:08 +0000 (GMT) Received: from nproxy.gmail.com ([64.233.182.194]:7645 "EHLO nproxy.gmail.com") by ftp.linux-mips.org with ESMTP id S8133953AbWCJAnA convert rfc822-to-8bit (ORCPT ); Fri, 10 Mar 2006 00:43:00 +0000 Received: by nproxy.gmail.com with SMTP id m19so436107nfc for ; Thu, 09 Mar 2006 16:51:39 -0800 (PST) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=bQjx4+k5Wt7yQ6KyaSJ4aiV0e2vKhdRfGJBxDjU5QTj9BGx6GyglnLtV9w741FnW7WkSV3SjcSSwDqLaeg0lXap6I7gi3QXEWu2FB76hKmWEmkX7KSAGPi7e6IUskKzjsVvjhTfiGnz75e0fSQbkTHUdebvvLthGTPUlvzoo5BM= Received: by 10.49.39.4 with SMTP id r4mr83968nfj; Thu, 09 Mar 2006 16:51:39 -0800 (PST) Received: by 10.48.144.19 with HTTP; Thu, 9 Mar 2006 16:51:39 -0800 (PST) Message-ID: <50c9a2250603091651k15088a83l85767ba8d919b6d2@mail.gmail.com> Date: Fri, 10 Mar 2006 08:51:39 +0800 From: zhuzhenhua To: "David Daney" Subject: Re: how to select the filesystem for nand flash? Cc: linux-mips In-Reply-To: <44105361.9000909@avtrex.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Content-Disposition: inline References: <50c9a2250603081748u639d35c0n272d53e24acc9f02@mail.gmail.com> <44105361.9000909@avtrex.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10773 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zzh.hust@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 947 Lines: 22 On 3/10/06, David Daney wrote: > zhuzhenhua wrote: > > In the linux, I find there are two solutions for nand flash: one is > > YAFFS2/JFFS2 + MTD, other is EXT2/EXT3+FTL. Because we have to > > implement vfat based FTL for our u-disk,so i wonder if the ext2/ext3 > > + FTL is stable enough to be root filesystem? > > thanks for any hints. > > If you are going to be writing to the rootfs then you will want either > yaffs or jffs2 as they distribute the wear across the entire device > instead of concentrating it on a few blocks. > > Most implementations I have seen (and what I do myself) is to have a > read-only rootfs on cramfs of squashfs, and then have a seperate > writable partition with either yaffs or jffs2. > > David Daney. > thanks for your advice. if i don't want u-disk function, i will select your solution. but i don't know how to use yaffs or jffs2 to implement a u-disk it seems that i have to use fat+FTL From Rakesh.Tiwari@idt.com Fri Mar 10 01:01:43 2006 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Mar 2006 01:02:04 +0000 (GMT) Received: from mxout.mainstreet.net ([199.245.73.25]:36849 "EHLO mxout.mainstreet.net") by ftp.linux-mips.org with ESMTP id S8133953AbWCJBBn (ORCPT ); Fri, 10 Mar 2006 01:01:43 +0000 Received: from mail.idt.com (mail.idt.com [157.165.5.20]) by mxout.mainstreet.net (8.13.4/8.13.4) with ESMTP id k2A19d1g027500; Thu, 9 Mar 2006 17:09:42 -0800 (PST) Received: from corpml1.corp.idt.com (corpml1.corp.idt.com [157.165.140.20]) by mail.idt.com (8.13.4/8.13.4) with ESMTP id k2A19CM2023759; Thu, 9 Mar 2006 17:09:12 -0800 (PST) Received: from CORPBRIDGE.corp.idt.com (localhost [127.0.0.1]) by corpml1.corp.idt.com (8.11.7p1+Sun/8.11.7) with ESMTP id k2A190l21351; Thu, 9 Mar 2006 17:09:00 -0800 (PST) Received: by corpbridge.corp.idt.com with Internet Mail Service (5.5.2658.3) id <1X0B0LXS>; Thu, 9 Mar 2006 17:08:59 -0800 Message-ID: <73943A6B3BEAA1468EE1A4A090129F4316B15A73@corpbridge.corp.idt.com> From: "Tiwari, Rakesh" To: "'Ralf Baechle'" Cc: linux-mips@linux-mips.org Subject: [PATCH] IDT Interprise Processor Support for Linux 2.6.x Date: Thu, 9 Mar 2006 17:08:49 -0800 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2658.3) Content-Type: multipart/mixed; boundary="----_=_NextPart_000_01C643DF.3058CF34" X-Scanned-By: MIMEDefang 2.43 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 10774 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Rakesh.Tiwari@idt.com Precedence: bulk X-list: linux-mips Content-Length: 1638696 Lines: 53691 This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. ------_=_NextPart_000_01C643DF.3058CF34 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C643DF.3058CF34" ------_=_NextPart_001_01C643DF.3058CF34 Content-Type: text/plain Hi Ralf, The attached patch adds support for the IDT Interprise series of processor based on the MIPS 4KC and Cronus (RC32300) core. The patch is against the latest MIPS kernel linux-2.6.16-rc5. Look forward for your feedback/comments. Regards Rakesh PS: Additional information regarding IDT's processor can be found at http://www.idt.com/?catID=58532 ------_=_NextPart_001_01C643DF.3058CF34 Content-Type: text/html [PATCH] IDT Interprise Processor Support for Linux 2.6.x

Hi Ralf,

The attached patch adds support for the IDT Interprise series of processor
based on the MIPS 4KC and Cronus (RC32300) core.

The patch is against the latest MIPS kernel linux-2.6.16-rc5.

Look forward for your feedback/comments.

Regards
Rakesh

PS: Additional information regarding IDT's processor can be found at
http://www.idt.com/?catID=58532


  ------_=_NextPart_001_01C643DF.3058CF34-- ------_=_NextPart_000_01C643DF.3058CF34 Content-Type: application/octet-stream; name="idt_processor.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="idt_processor.patch" diff -uNr linux-2.6.16-rc5/arch/mips/configs/rc32334_defconfig = idtlinux/arch/mips/configs/rc32334_defconfig=0A= --- linux-2.6.16-rc5/arch/mips/configs/rc32334_defconfig 1969-12-31 = 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/configs/rc32334_defconfig 2006-03-09 = 16:25:45.000000000 -0800=0A= @@ -0,0 +1,969 @@=0A= +#=0A= +# Automatically generated make config: don't edit=0A= +# Linux kernel version: 2.6.16-rc5=0A= +# Thu Mar 9 15:47:19 2006=0A= +#=0A= +CONFIG_MIPS=3Dy=0A= +=0A= +#=0A= +# Machine selection=0A= +#=0A= +# CONFIG_MIPS_MTX1 is not set=0A= +# CONFIG_MIPS_BOSPORUS is not set=0A= +# CONFIG_MIPS_PB1000 is not set=0A= +# CONFIG_MIPS_PB1100 is not set=0A= +# CONFIG_MIPS_PB1500 is not set=0A= +# CONFIG_MIPS_PB1550 is not set=0A= +# CONFIG_MIPS_PB1200 is not set=0A= +# CONFIG_MIPS_DB1000 is not set=0A= +# CONFIG_MIPS_DB1100 is not set=0A= +# CONFIG_MIPS_DB1500 is not set=0A= +# CONFIG_MIPS_DB1550 is not set=0A= +# CONFIG_MIPS_DB1200 is not set=0A= +# CONFIG_MIPS_MIRAGE is not set=0A= +# CONFIG_MIPS_COBALT is not set=0A= +# CONFIG_MACH_DECSTATION is not set=0A= +# CONFIG_MIPS_EV64120 is not set=0A= +# CONFIG_MIPS_EV96100 is not set=0A= +# CONFIG_MIPS_IVR is not set=0A= +CONFIG_IDT_BOARDS=3Dy=0A= +# CONFIG_MIPS_ITE8172 is not set=0A= +# CONFIG_MACH_JAZZ is not set=0A= +# CONFIG_LASAT is not set=0A= +# CONFIG_MIPS_ATLAS is not set=0A= +# CONFIG_MIPS_MALTA is not set=0A= +# CONFIG_MIPS_SEAD is not set=0A= +# CONFIG_MIPS_SIM is not set=0A= +# CONFIG_MOMENCO_JAGUAR_ATX is not set=0A= +# CONFIG_MOMENCO_OCELOT is not set=0A= +# CONFIG_MOMENCO_OCELOT_3 is not set=0A= +# CONFIG_MOMENCO_OCELOT_C is not set=0A= +# CONFIG_MOMENCO_OCELOT_G is not set=0A= +# CONFIG_MIPS_XXS1500 is not set=0A= +# CONFIG_PNX8550_V2PCI is not set=0A= +# CONFIG_PNX8550_JBS is not set=0A= +# CONFIG_DDB5074 is not set=0A= +# CONFIG_DDB5476 is not set=0A= +# CONFIG_DDB5477 is not set=0A= +# CONFIG_MACH_VR41XX is not set=0A= +# CONFIG_PMC_YOSEMITE is not set=0A= +# CONFIG_QEMU is not set=0A= +# CONFIG_SGI_IP22 is not set=0A= +# CONFIG_SGI_IP27 is not set=0A= +# CONFIG_SGI_IP32 is not set=0A= +# CONFIG_SIBYTE_BIGSUR is not set=0A= +# CONFIG_SIBYTE_SWARM is not set=0A= +# CONFIG_SIBYTE_SENTOSA is not set=0A= +# CONFIG_SIBYTE_RHONE is not set=0A= +# CONFIG_SIBYTE_CARMEL is not set=0A= +# CONFIG_SIBYTE_PTSWARM is not set=0A= +# CONFIG_SIBYTE_LITTLESUR is not set=0A= +# CONFIG_SIBYTE_CRHINE is not set=0A= +# CONFIG_SIBYTE_CRHONE is not set=0A= +# CONFIG_SNI_RM200_PCI is not set=0A= +# CONFIG_TOSHIBA_JMR3927 is not set=0A= +# CONFIG_TOSHIBA_RBTX4927 is not set=0A= +# CONFIG_TOSHIBA_RBTX4938 is not set=0A= +# CONFIG_IDT_EB438 is not set=0A= +# CONFIG_IDT_EB434 is not set=0A= +# CONFIG_IDT_EB365 is not set=0A= +# CONFIG_IDT_EB355 is not set=0A= +CONFIG_IDT_S334=3Dy=0A= +CONFIG_IDT_BOARD_FREQ=3D75000000=0A= +CONFIG_IDT_ZIMAGE_ADDR=3D0x80800000=0A= +CONFIG_IDT_BOOT_NVRAM=3Dy=0A= +CONFIG_RWSEM_GENERIC_SPINLOCK=3Dy=0A= +CONFIG_GENERIC_CALIBRATE_DELAY=3Dy=0A= +CONFIG_DMA_NONCOHERENT=3Dy=0A= +CONFIG_DMA_NEED_PCI_MAP_STATE=3Dy=0A= +# CONFIG_CPU_BIG_ENDIAN is not set=0A= +CONFIG_CPU_LITTLE_ENDIAN=3Dy=0A= +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=3Dy=0A= +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=3Dy=0A= +CONFIG_IRQ_CPU=3Dy=0A= +CONFIG_SWAP_IO_SPACE=3Dy=0A= +CONFIG_BOOT_ELF32=3Dy=0A= +CONFIG_MIPS_L1_CACHE_SHIFT=3D5=0A= +=0A= +#=0A= +# CPU selection=0A= +#=0A= +# CONFIG_CPU_MIPS32_R1 is not set=0A= +# CONFIG_CPU_MIPS32_R2 is not set=0A= +# CONFIG_CPU_MIPS64_R1 is not set=0A= +# CONFIG_CPU_MIPS64_R2 is not set=0A= +# CONFIG_CPU_R3000 is not set=0A= +CONFIG_CPU_RC32300=3Dy=0A= +# CONFIG_CPU_TX39XX is not set=0A= +# CONFIG_CPU_VR41XX is not set=0A= +# CONFIG_CPU_R4300 is not set=0A= +# CONFIG_CPU_R4X00 is not set=0A= +# CONFIG_CPU_TX49XX is not set=0A= +# CONFIG_CPU_R5000 is not set=0A= +# CONFIG_CPU_R5432 is not set=0A= +# CONFIG_CPU_R6000 is not set=0A= +# CONFIG_CPU_NEVADA is not set=0A= +# CONFIG_CPU_R8000 is not set=0A= +# CONFIG_CPU_R10000 is not set=0A= +# CONFIG_CPU_RM7000 is not set=0A= +# CONFIG_CPU_RM9000 is not set=0A= +# CONFIG_CPU_SB1 is not set=0A= +CONFIG_SYS_HAS_CPU_MIPS32_R1=3Dy=0A= +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=3Dy=0A= +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=3Dy=0A= +=0A= +#=0A= +# Kernel type=0A= +#=0A= +CONFIG_32BIT=3Dy=0A= +# CONFIG_64BIT is not set=0A= +CONFIG_PAGE_SIZE_4KB=3Dy=0A= +# CONFIG_PAGE_SIZE_8KB is not set=0A= +# CONFIG_PAGE_SIZE_16KB is not set=0A= +# CONFIG_PAGE_SIZE_64KB is not set=0A= +CONFIG_CPU_HAS_PREFETCH=3Dy=0A= +# CONFIG_MIPS_MT is not set=0A= +CONFIG_CPU_ADVANCED=3Dy=0A= +CONFIG_CPU_HAS_LLSC=3Dy=0A= +# CONFIG_CPU_HAS_WB is not set=0A= +CONFIG_CPU_HAS_SYNC=3Dy=0A= +CONFIG_GENERIC_HARDIRQS=3Dy=0A= +CONFIG_GENERIC_IRQ_PROBE=3Dy=0A= +CONFIG_ARCH_FLATMEM_ENABLE=3Dy=0A= +CONFIG_SELECT_MEMORY_MODEL=3Dy=0A= +CONFIG_FLATMEM_MANUAL=3Dy=0A= +# CONFIG_DISCONTIGMEM_MANUAL is not set=0A= +# CONFIG_SPARSEMEM_MANUAL is not set=0A= +CONFIG_FLATMEM=3Dy=0A= +CONFIG_FLAT_NODE_MEM_MAP=3Dy=0A= +# CONFIG_SPARSEMEM_STATIC is not set=0A= +CONFIG_SPLIT_PTLOCK_CPUS=3D4=0A= +CONFIG_PREEMPT_NONE=3Dy=0A= +# CONFIG_PREEMPT_VOLUNTARY is not set=0A= +# CONFIG_PREEMPT is not set=0A= +=0A= +#=0A= +# Code maturity level options=0A= +#=0A= +CONFIG_EXPERIMENTAL=3Dy=0A= +CONFIG_BROKEN_ON_SMP=3Dy=0A= +CONFIG_INIT_ENV_ARG_LIMIT=3D32=0A= +=0A= +#=0A= +# General setup=0A= +#=0A= +CONFIG_LOCALVERSION=3D""=0A= +CONFIG_LOCALVERSION_AUTO=3Dy=0A= +# CONFIG_SWAP is not set=0A= +CONFIG_SYSVIPC=3Dy=0A= +# CONFIG_POSIX_MQUEUE is not set=0A= +# CONFIG_BSD_PROCESS_ACCT is not set=0A= +CONFIG_SYSCTL=3Dy=0A= +# CONFIG_AUDIT is not set=0A= +CONFIG_IKCONFIG=3Dy=0A= +# CONFIG_IKCONFIG_PROC is not set=0A= +CONFIG_INITRAMFS_SOURCE=3D""=0A= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set=0A= +CONFIG_EMBEDDED=3Dy=0A= +# CONFIG_KALLSYMS is not set=0A= +# CONFIG_HOTPLUG is not set=0A= +CONFIG_PRINTK=3Dy=0A= +CONFIG_BUG=3Dy=0A= +CONFIG_ELF_CORE=3Dy=0A= +# CONFIG_BASE_FULL is not set=0A= +# CONFIG_FUTEX is not set=0A= +# CONFIG_EPOLL is not set=0A= +CONFIG_SHMEM=3Dy=0A= +CONFIG_CC_ALIGN_FUNCTIONS=3D0=0A= +CONFIG_CC_ALIGN_LABELS=3D0=0A= +CONFIG_CC_ALIGN_LOOPS=3D0=0A= +CONFIG_CC_ALIGN_JUMPS=3D0=0A= +# CONFIG_SLAB is not set=0A= +# CONFIG_TINY_SHMEM is not set=0A= +CONFIG_BASE_SMALL=3D1=0A= +CONFIG_SLOB=3Dy=0A= +=0A= +#=0A= +# Loadable module support=0A= +#=0A= +CONFIG_MODULES=3Dy=0A= +CONFIG_MODULE_UNLOAD=3Dy=0A= +# CONFIG_MODULE_FORCE_UNLOAD is not set=0A= +CONFIG_OBSOLETE_MODPARM=3Dy=0A= +# CONFIG_MODVERSIONS is not set=0A= +# CONFIG_MODULE_SRCVERSION_ALL is not set=0A= +# CONFIG_KMOD is not set=0A= +=0A= +#=0A= +# Block layer=0A= +#=0A= +# CONFIG_LBD is not set=0A= +=0A= +#=0A= +# IO Schedulers=0A= +#=0A= +CONFIG_IOSCHED_NOOP=3Dy=0A= +CONFIG_IOSCHED_AS=3Dy=0A= +CONFIG_IOSCHED_DEADLINE=3Dy=0A= +CONFIG_IOSCHED_CFQ=3Dy=0A= +CONFIG_DEFAULT_AS=3Dy=0A= +# CONFIG_DEFAULT_DEADLINE is not set=0A= +# CONFIG_DEFAULT_CFQ is not set=0A= +# CONFIG_DEFAULT_NOOP is not set=0A= +CONFIG_DEFAULT_IOSCHED=3D"anticipatory"=0A= +=0A= +#=0A= +# Bus options (PCI, PCMCIA, EISA, ISA, TC)=0A= +#=0A= +CONFIG_HW_HAS_PCI=3Dy=0A= +CONFIG_PCI=3Dy=0A= +CONFIG_PCI_LEGACY_PROC=3Dy=0A= +CONFIG_MMU=3Dy=0A= +=0A= +#=0A= +# PCCARD (PCMCIA/CardBus) support=0A= +#=0A= +# CONFIG_PCCARD is not set=0A= +=0A= +#=0A= +# PCI Hotplug Support=0A= +#=0A= +# CONFIG_HOTPLUG_PCI is not set=0A= +=0A= +#=0A= +# Executable file formats=0A= +#=0A= +CONFIG_BINFMT_ELF=3Dy=0A= +# CONFIG_BINFMT_MISC is not set=0A= +CONFIG_TRAD_SIGNALS=3Dy=0A= +=0A= +#=0A= +# Networking=0A= +#=0A= +CONFIG_NET=3Dy=0A= +=0A= +#=0A= +# Networking options=0A= +#=0A= +# CONFIG_NETDEBUG is not set=0A= +CONFIG_PACKET=3Dy=0A= +CONFIG_PACKET_MMAP=3Dy=0A= +CONFIG_UNIX=3Dy=0A= +CONFIG_XFRM=3Dy=0A= +# CONFIG_XFRM_USER is not set=0A= +CONFIG_NET_KEY=3Dy=0A= +CONFIG_INET=3Dy=0A= +CONFIG_IP_MULTICAST=3Dy=0A= +# CONFIG_IP_ADVANCED_ROUTER is not set=0A= +CONFIG_IP_FIB_HASH=3Dy=0A= +CONFIG_IP_PNP=3Dy=0A= +# CONFIG_IP_PNP_DHCP is not set=0A= +# CONFIG_IP_PNP_BOOTP is not set=0A= +# CONFIG_IP_PNP_RARP is not set=0A= +# CONFIG_NET_IPIP is not set=0A= +# CONFIG_NET_IPGRE is not set=0A= +# CONFIG_IP_MROUTE is not set=0A= +# CONFIG_ARPD is not set=0A= +# CONFIG_SYN_COOKIES is not set=0A= +# CONFIG_INET_AH is not set=0A= +# CONFIG_INET_ESP is not set=0A= +# CONFIG_INET_IPCOMP is not set=0A= +# CONFIG_INET_TUNNEL is not set=0A= +# CONFIG_INET_DIAG is not set=0A= +# CONFIG_TCP_CONG_ADVANCED is not set=0A= +CONFIG_TCP_CONG_BIC=3Dy=0A= +=0A= +#=0A= +# IP: Virtual Server Configuration=0A= +#=0A= +CONFIG_IP_VS=3Dm=0A= +# CONFIG_IP_VS_DEBUG is not set=0A= +CONFIG_IP_VS_TAB_BITS=3D12=0A= +=0A= +#=0A= +# IPVS transport protocol load balancing support=0A= +#=0A= +CONFIG_IP_VS_PROTO_TCP=3Dy=0A= +CONFIG_IP_VS_PROTO_UDP=3Dy=0A= +CONFIG_IP_VS_PROTO_ESP=3Dy=0A= +CONFIG_IP_VS_PROTO_AH=3Dy=0A= +=0A= +#=0A= +# IPVS scheduler=0A= +#=0A= +CONFIG_IP_VS_RR=3Dm=0A= +CONFIG_IP_VS_WRR=3Dm=0A= +CONFIG_IP_VS_LC=3Dm=0A= +CONFIG_IP_VS_WLC=3Dm=0A= +CONFIG_IP_VS_LBLC=3Dm=0A= +CONFIG_IP_VS_LBLCR=3Dm=0A= +CONFIG_IP_VS_DH=3Dm=0A= +CONFIG_IP_VS_SH=3Dm=0A= +CONFIG_IP_VS_SED=3Dm=0A= +CONFIG_IP_VS_NQ=3Dm=0A= +=0A= +#=0A= +# IPVS application helper=0A= +#=0A= +CONFIG_IP_VS_FTP=3Dm=0A= +# CONFIG_IPV6 is not set=0A= +CONFIG_NETFILTER=3Dy=0A= +# CONFIG_NETFILTER_DEBUG is not set=0A= +=0A= +#=0A= +# Core Netfilter Configuration=0A= +#=0A= +CONFIG_NETFILTER_NETLINK=3Dm=0A= +CONFIG_NETFILTER_NETLINK_QUEUE=3Dm=0A= +CONFIG_NETFILTER_NETLINK_LOG=3Dm=0A= +CONFIG_NETFILTER_XTABLES=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_CONNMARK=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_MARK=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_NOTRACK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_COMMENT=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNMARK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_DCCP=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_HELPER=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_LENGTH=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_LIMIT=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_MAC=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_MARK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_REALM=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_SCTP=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_STATE=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_STRING=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_TCPMSS=3Dm=0A= +=0A= +#=0A= +# IP: Netfilter Configuration=0A= +#=0A= +CONFIG_IP_NF_CONNTRACK=3Dm=0A= +CONFIG_IP_NF_CT_ACCT=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_MARK=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_EVENTS=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_NETLINK=3Dm=0A= +# CONFIG_IP_NF_CT_PROTO_SCTP is not set=0A= +CONFIG_IP_NF_FTP=3Dm=0A= +CONFIG_IP_NF_IRC=3Dm=0A= +# CONFIG_IP_NF_NETBIOS_NS is not set=0A= +CONFIG_IP_NF_TFTP=3Dm=0A= +CONFIG_IP_NF_AMANDA=3Dm=0A= +CONFIG_IP_NF_PPTP=3Dm=0A= +CONFIG_IP_NF_QUEUE=3Dm=0A= +CONFIG_IP_NF_IPTABLES=3Dm=0A= +CONFIG_IP_NF_MATCH_IPRANGE=3Dm=0A= +CONFIG_IP_NF_MATCH_MULTIPORT=3Dm=0A= +CONFIG_IP_NF_MATCH_TOS=3Dm=0A= +CONFIG_IP_NF_MATCH_RECENT=3Dm=0A= +CONFIG_IP_NF_MATCH_ECN=3Dm=0A= +CONFIG_IP_NF_MATCH_DSCP=3Dm=0A= +CONFIG_IP_NF_MATCH_AH_ESP=3Dm=0A= +CONFIG_IP_NF_MATCH_TTL=3Dm=0A= +CONFIG_IP_NF_MATCH_OWNER=3Dm=0A= +CONFIG_IP_NF_MATCH_ADDRTYPE=3Dm=0A= +CONFIG_IP_NF_MATCH_HASHLIMIT=3Dm=0A= +CONFIG_IP_NF_MATCH_POLICY=3Dm=0A= +CONFIG_IP_NF_FILTER=3Dm=0A= +CONFIG_IP_NF_TARGET_REJECT=3Dm=0A= +CONFIG_IP_NF_TARGET_LOG=3Dm=0A= +CONFIG_IP_NF_TARGET_ULOG=3Dm=0A= +CONFIG_IP_NF_TARGET_TCPMSS=3Dm=0A= +CONFIG_IP_NF_NAT=3Dm=0A= +CONFIG_IP_NF_NAT_NEEDED=3Dy=0A= +CONFIG_IP_NF_TARGET_MASQUERADE=3Dm=0A= +CONFIG_IP_NF_TARGET_REDIRECT=3Dm=0A= +CONFIG_IP_NF_TARGET_NETMAP=3Dm=0A= +CONFIG_IP_NF_TARGET_SAME=3Dm=0A= +CONFIG_IP_NF_NAT_SNMP_BASIC=3Dm=0A= +CONFIG_IP_NF_NAT_IRC=3Dm=0A= +CONFIG_IP_NF_NAT_FTP=3Dm=0A= +CONFIG_IP_NF_NAT_TFTP=3Dm=0A= +CONFIG_IP_NF_NAT_AMANDA=3Dm=0A= +CONFIG_IP_NF_NAT_PPTP=3Dm=0A= +CONFIG_IP_NF_MANGLE=3Dm=0A= +CONFIG_IP_NF_TARGET_TOS=3Dm=0A= +CONFIG_IP_NF_TARGET_ECN=3Dm=0A= +CONFIG_IP_NF_TARGET_DSCP=3Dm=0A= +CONFIG_IP_NF_TARGET_TTL=3Dm=0A= +CONFIG_IP_NF_TARGET_CLUSTERIP=3Dm=0A= +CONFIG_IP_NF_RAW=3Dm=0A= +CONFIG_IP_NF_ARPTABLES=3Dm=0A= +CONFIG_IP_NF_ARPFILTER=3Dm=0A= +CONFIG_IP_NF_ARP_MANGLE=3Dm=0A= +=0A= +#=0A= +# DCCP Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_IP_DCCP is not set=0A= +=0A= +#=0A= +# SCTP Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_IP_SCTP is not set=0A= +=0A= +#=0A= +# TIPC Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_TIPC is not set=0A= +# CONFIG_ATM is not set=0A= +# CONFIG_BRIDGE is not set=0A= +# CONFIG_VLAN_8021Q is not set=0A= +# CONFIG_DECNET is not set=0A= +# CONFIG_LLC2 is not set=0A= +# CONFIG_IPX is not set=0A= +# CONFIG_ATALK is not set=0A= +# CONFIG_X25 is not set=0A= +# CONFIG_LAPB is not set=0A= +# CONFIG_NET_DIVERT is not set=0A= +# CONFIG_ECONET is not set=0A= +# CONFIG_WAN_ROUTER is not set=0A= +=0A= +#=0A= +# QoS and/or fair queueing=0A= +#=0A= +CONFIG_NET_SCHED=3Dy=0A= +# CONFIG_NET_SCH_CLK_JIFFIES is not set=0A= +CONFIG_NET_SCH_CLK_GETTIMEOFDAY=3Dy=0A= +# CONFIG_NET_SCH_CLK_CPU is not set=0A= +=0A= +#=0A= +# Queueing/Scheduling=0A= +#=0A= +CONFIG_NET_SCH_CBQ=3Dm=0A= +CONFIG_NET_SCH_HTB=3Dm=0A= +CONFIG_NET_SCH_HFSC=3Dm=0A= +CONFIG_NET_SCH_PRIO=3Dm=0A= +CONFIG_NET_SCH_RED=3Dm=0A= +CONFIG_NET_SCH_SFQ=3Dm=0A= +CONFIG_NET_SCH_TEQL=3Dm=0A= +CONFIG_NET_SCH_TBF=3Dm=0A= +CONFIG_NET_SCH_GRED=3Dm=0A= +CONFIG_NET_SCH_DSMARK=3Dm=0A= +CONFIG_NET_SCH_NETEM=3Dm=0A= +CONFIG_NET_SCH_INGRESS=3Dm=0A= +=0A= +#=0A= +# Classification=0A= +#=0A= +CONFIG_NET_CLS=3Dy=0A= +CONFIG_NET_CLS_BASIC=3Dm=0A= +CONFIG_NET_CLS_TCINDEX=3Dm=0A= +CONFIG_NET_CLS_ROUTE4=3Dm=0A= +CONFIG_NET_CLS_ROUTE=3Dy=0A= +CONFIG_NET_CLS_FW=3Dm=0A= +CONFIG_NET_CLS_U32=3Dm=0A= +# CONFIG_CLS_U32_PERF is not set=0A= +# CONFIG_CLS_U32_MARK is not set=0A= +CONFIG_NET_CLS_RSVP=3Dm=0A= +CONFIG_NET_CLS_RSVP6=3Dm=0A= +# CONFIG_NET_EMATCH is not set=0A= +# CONFIG_NET_CLS_ACT is not set=0A= +CONFIG_NET_CLS_POLICE=3Dy=0A= +# CONFIG_NET_CLS_IND is not set=0A= +CONFIG_NET_ESTIMATOR=3Dy=0A= +=0A= +#=0A= +# Network testing=0A= +#=0A= +# CONFIG_NET_PKTGEN is not set=0A= +# CONFIG_HAMRADIO is not set=0A= +# CONFIG_IRDA is not set=0A= +# CONFIG_BT is not set=0A= +# CONFIG_IEEE80211 is not set=0A= +=0A= +#=0A= +# Device Drivers=0A= +#=0A= +=0A= +#=0A= +# Generic Driver Options=0A= +#=0A= +CONFIG_STANDALONE=3Dy=0A= +CONFIG_PREVENT_FIRMWARE_BUILD=3Dy=0A= +# CONFIG_FW_LOADER is not set=0A= +=0A= +#=0A= +# Connector - unified userspace <-> kernelspace linker=0A= +#=0A= +# CONFIG_CONNECTOR is not set=0A= +=0A= +#=0A= +# Memory Technology Devices (MTD)=0A= +#=0A= +# CONFIG_MTD is not set=0A= +=0A= +#=0A= +# Parallel port support=0A= +#=0A= +# CONFIG_PARPORT is not set=0A= +=0A= +#=0A= +# Plug and Play support=0A= +#=0A= +=0A= +#=0A= +# Block devices=0A= +#=0A= +# CONFIG_BLK_CPQ_DA is not set=0A= +# CONFIG_BLK_CPQ_CISS_DA is not set=0A= +# CONFIG_BLK_DEV_DAC960 is not set=0A= +# CONFIG_BLK_DEV_UMEM is not set=0A= +# CONFIG_BLK_DEV_COW_COMMON is not set=0A= +# CONFIG_BLK_DEV_LOOP is not set=0A= +# CONFIG_BLK_DEV_NBD is not set=0A= +# CONFIG_BLK_DEV_SX8 is not set=0A= +# CONFIG_BLK_DEV_RAM is not set=0A= +CONFIG_BLK_DEV_RAM_COUNT=3D16=0A= +# CONFIG_CDROM_PKTCDVD is not set=0A= +# CONFIG_ATA_OVER_ETH is not set=0A= +=0A= +#=0A= +# ATA/ATAPI/MFM/RLL support=0A= +#=0A= +# CONFIG_IDE is not set=0A= +=0A= +#=0A= +# SCSI device support=0A= +#=0A= +# CONFIG_RAID_ATTRS is not set=0A= +# CONFIG_SCSI is not set=0A= +=0A= +#=0A= +# Multi-device support (RAID and LVM)=0A= +#=0A= +# CONFIG_MD is not set=0A= +=0A= +#=0A= +# Fusion MPT device support=0A= +#=0A= +# CONFIG_FUSION is not set=0A= +=0A= +#=0A= +# IEEE 1394 (FireWire) support=0A= +#=0A= +# CONFIG_IEEE1394 is not set=0A= +=0A= +#=0A= +# I2O device support=0A= +#=0A= +# CONFIG_I2O is not set=0A= +=0A= +#=0A= +# Network device support=0A= +#=0A= +CONFIG_NETDEVICES=3Dy=0A= +# CONFIG_DUMMY is not set=0A= +# CONFIG_BONDING is not set=0A= +# CONFIG_EQUALIZER is not set=0A= +# CONFIG_TUN is not set=0A= +=0A= +#=0A= +# ARCnet devices=0A= +#=0A= +# CONFIG_ARCNET is not set=0A= +=0A= +#=0A= +# PHY device support=0A= +#=0A= +# CONFIG_PHYLIB is not set=0A= +=0A= +#=0A= +# Ethernet (10 or 100Mbit)=0A= +#=0A= +CONFIG_NET_ETHERNET=3Dy=0A= +CONFIG_MII=3Dy=0A= +# CONFIG_HAPPYMEAL is not set=0A= +# CONFIG_SUNGEM is not set=0A= +# CONFIG_CASSINI is not set=0A= +# CONFIG_NET_VENDOR_3COM is not set=0A= +# CONFIG_DM9000 is not set=0A= +=0A= +#=0A= +# Tulip family network device support=0A= +#=0A= +# CONFIG_NET_TULIP is not set=0A= +# CONFIG_HP100 is not set=0A= +CONFIG_NET_PCI=3Dy=0A= +# CONFIG_PCNET32 is not set=0A= +# CONFIG_AMD8111_ETH is not set=0A= +# CONFIG_ADAPTEC_STARFIRE is not set=0A= +# CONFIG_B44 is not set=0A= +# CONFIG_FORCEDETH is not set=0A= +# CONFIG_DGRS is not set=0A= +# CONFIG_EEPRO100 is not set=0A= +CONFIG_E100=3Dy=0A= +# CONFIG_FEALNX is not set=0A= +# CONFIG_NATSEMI is not set=0A= +# CONFIG_NE2K_PCI is not set=0A= +# CONFIG_8139CP is not set=0A= +# CONFIG_8139TOO is not set=0A= +# CONFIG_SIS900 is not set=0A= +# CONFIG_EPIC100 is not set=0A= +# CONFIG_SUNDANCE is not set=0A= +# CONFIG_TLAN is not set=0A= +# CONFIG_VIA_RHINE is not set=0A= +# CONFIG_LAN_SAA9730 is not set=0A= +=0A= +#=0A= +# Ethernet (1000 Mbit)=0A= +#=0A= +# CONFIG_ACENIC is not set=0A= +# CONFIG_DL2K is not set=0A= +# CONFIG_E1000 is not set=0A= +# CONFIG_NS83820 is not set=0A= +# CONFIG_HAMACHI is not set=0A= +# CONFIG_YELLOWFIN is not set=0A= +# CONFIG_R8169 is not set=0A= +# CONFIG_SIS190 is not set=0A= +# CONFIG_SKGE is not set=0A= +# CONFIG_SKY2 is not set=0A= +# CONFIG_SK98LIN is not set=0A= +# CONFIG_VIA_VELOCITY is not set=0A= +# CONFIG_TIGON3 is not set=0A= +# CONFIG_BNX2 is not set=0A= +=0A= +#=0A= +# Ethernet (10000 Mbit)=0A= +#=0A= +# CONFIG_CHELSIO_T1 is not set=0A= +# CONFIG_IXGB is not set=0A= +# CONFIG_S2IO is not set=0A= +=0A= +#=0A= +# Token Ring devices=0A= +#=0A= +# CONFIG_TR is not set=0A= +=0A= +#=0A= +# Wireless LAN (non-hamradio)=0A= +#=0A= +# CONFIG_NET_RADIO is not set=0A= +=0A= +#=0A= +# Wan interfaces=0A= +#=0A= +# CONFIG_WAN is not set=0A= +# CONFIG_FDDI is not set=0A= +# CONFIG_HIPPI is not set=0A= +# CONFIG_PPP is not set=0A= +# CONFIG_SLIP is not set=0A= +# CONFIG_SHAPER is not set=0A= +# CONFIG_NETCONSOLE is not set=0A= +# CONFIG_NETPOLL is not set=0A= +# CONFIG_NET_POLL_CONTROLLER is not set=0A= +=0A= +#=0A= +# ISDN subsystem=0A= +#=0A= +# CONFIG_ISDN is not set=0A= +=0A= +#=0A= +# Telephony Support=0A= +#=0A= +# CONFIG_PHONE is not set=0A= +=0A= +#=0A= +# Input device support=0A= +#=0A= +CONFIG_INPUT=3Dy=0A= +=0A= +#=0A= +# Userland interfaces=0A= +#=0A= +# CONFIG_INPUT_MOUSEDEV is not set=0A= +# CONFIG_INPUT_JOYDEV is not set=0A= +# CONFIG_INPUT_TSDEV is not set=0A= +# CONFIG_INPUT_EVDEV is not set=0A= +# CONFIG_INPUT_EVBUG is not set=0A= +=0A= +#=0A= +# Input Device Drivers=0A= +#=0A= +# CONFIG_INPUT_KEYBOARD is not set=0A= +# CONFIG_INPUT_MOUSE is not set=0A= +# CONFIG_INPUT_JOYSTICK is not set=0A= +# CONFIG_INPUT_TOUCHSCREEN is not set=0A= +# CONFIG_INPUT_MISC is not set=0A= +=0A= +#=0A= +# Hardware I/O ports=0A= +#=0A= +# CONFIG_SERIO is not set=0A= +# CONFIG_GAMEPORT is not set=0A= +=0A= +#=0A= +# Character devices=0A= +#=0A= +CONFIG_VT=3Dy=0A= +CONFIG_VT_CONSOLE=3Dy=0A= +CONFIG_HW_CONSOLE=3Dy=0A= +# CONFIG_SERIAL_NONSTANDARD is not set=0A= +=0A= +#=0A= +# Serial drivers=0A= +#=0A= +CONFIG_SERIAL_8250=3Dy=0A= +CONFIG_SERIAL_8250_CONSOLE=3Dy=0A= +CONFIG_SERIAL_8250_NR_UARTS=3D4=0A= +CONFIG_SERIAL_8250_RUNTIME_UARTS=3D4=0A= +# CONFIG_SERIAL_8250_EXTENDED is not set=0A= +=0A= +#=0A= +# Non-8250 serial port support=0A= +#=0A= +CONFIG_SERIAL_CORE=3Dy=0A= +CONFIG_SERIAL_CORE_CONSOLE=3Dy=0A= +# CONFIG_SERIAL_JSM is not set=0A= +CONFIG_UNIX98_PTYS=3Dy=0A= +CONFIG_LEGACY_PTYS=3Dy=0A= +CONFIG_LEGACY_PTY_COUNT=3D256=0A= +=0A= +#=0A= +# IPMI=0A= +#=0A= +# CONFIG_IPMI_HANDLER is not set=0A= +=0A= +#=0A= +# Watchdog Cards=0A= +#=0A= +# CONFIG_WATCHDOG is not set=0A= +# CONFIG_RTC is not set=0A= +# CONFIG_GEN_RTC is not set=0A= +# CONFIG_DTLK is not set=0A= +# CONFIG_R3964 is not set=0A= +# CONFIG_APPLICOM is not set=0A= +=0A= +#=0A= +# Ftape, the floppy tape device driver=0A= +#=0A= +# CONFIG_DRM is not set=0A= +# CONFIG_RAW_DRIVER is not set=0A= +=0A= +#=0A= +# TPM devices=0A= +#=0A= +# CONFIG_TCG_TPM is not set=0A= +# CONFIG_TELCLOCK is not set=0A= +=0A= +#=0A= +# I2C support=0A= +#=0A= +# CONFIG_I2C is not set=0A= +=0A= +#=0A= +# SPI support=0A= +#=0A= +# CONFIG_SPI is not set=0A= +# CONFIG_SPI_MASTER is not set=0A= +=0A= +#=0A= +# Dallas's 1-wire bus=0A= +#=0A= +# CONFIG_W1 is not set=0A= +=0A= +#=0A= +# Hardware Monitoring support=0A= +#=0A= +# CONFIG_HWMON is not set=0A= +# CONFIG_HWMON_VID is not set=0A= +=0A= +#=0A= +# Misc devices=0A= +#=0A= +=0A= +#=0A= +# Multimedia Capabilities Port drivers=0A= +#=0A= +=0A= +#=0A= +# Multimedia devices=0A= +#=0A= +# CONFIG_VIDEO_DEV is not set=0A= +=0A= +#=0A= +# Digital Video Broadcasting Devices=0A= +#=0A= +# CONFIG_DVB is not set=0A= +=0A= +#=0A= +# Graphics support=0A= +#=0A= +# CONFIG_FB is not set=0A= +=0A= +#=0A= +# Console display driver support=0A= +#=0A= +# CONFIG_VGA_CONSOLE is not set=0A= +CONFIG_DUMMY_CONSOLE=3Dy=0A= +=0A= +#=0A= +# Sound=0A= +#=0A= +# CONFIG_SOUND is not set=0A= +=0A= +#=0A= +# USB support=0A= +#=0A= +CONFIG_USB_ARCH_HAS_HCD=3Dy=0A= +CONFIG_USB_ARCH_HAS_OHCI=3Dy=0A= +# CONFIG_USB is not set=0A= +=0A= +#=0A= +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'=0A= +#=0A= +=0A= +#=0A= +# USB Gadget Support=0A= +#=0A= +# CONFIG_USB_GADGET is not set=0A= +=0A= +#=0A= +# MMC/SD Card support=0A= +#=0A= +# CONFIG_MMC is not set=0A= +=0A= +#=0A= +# InfiniBand support=0A= +#=0A= +# CONFIG_INFINIBAND is not set=0A= +=0A= +#=0A= +# SN Devices=0A= +#=0A= +=0A= +#=0A= +# EDAC - error detection and reporting (RAS)=0A= +#=0A= +=0A= +#=0A= +# File systems=0A= +#=0A= +CONFIG_EXT2_FS=3Dy=0A= +# CONFIG_EXT2_FS_XATTR is not set=0A= +# CONFIG_EXT2_FS_XIP is not set=0A= +# CONFIG_EXT3_FS is not set=0A= +# CONFIG_REISERFS_FS is not set=0A= +# CONFIG_JFS_FS is not set=0A= +# CONFIG_FS_POSIX_ACL is not set=0A= +# CONFIG_XFS_FS is not set=0A= +# CONFIG_OCFS2_FS is not set=0A= +# CONFIG_MINIX_FS is not set=0A= +# CONFIG_ROMFS_FS is not set=0A= +# CONFIG_INOTIFY is not set=0A= +# CONFIG_QUOTA is not set=0A= +# CONFIG_DNOTIFY is not set=0A= +# CONFIG_AUTOFS_FS is not set=0A= +# CONFIG_AUTOFS4_FS is not set=0A= +# CONFIG_FUSE_FS is not set=0A= +=0A= +#=0A= +# CD-ROM/DVD Filesystems=0A= +#=0A= +# CONFIG_ISO9660_FS is not set=0A= +# CONFIG_UDF_FS is not set=0A= +=0A= +#=0A= +# DOS/FAT/NT Filesystems=0A= +#=0A= +# CONFIG_MSDOS_FS is not set=0A= +# CONFIG_VFAT_FS is not set=0A= +# CONFIG_NTFS_FS is not set=0A= +=0A= +#=0A= +# Pseudo filesystems=0A= +#=0A= +CONFIG_PROC_FS=3Dy=0A= +CONFIG_PROC_KCORE=3Dy=0A= +CONFIG_SYSFS=3Dy=0A= +# CONFIG_TMPFS is not set=0A= +# CONFIG_HUGETLB_PAGE is not set=0A= +CONFIG_RAMFS=3Dy=0A= +# CONFIG_RELAYFS_FS is not set=0A= +# CONFIG_CONFIGFS_FS is not set=0A= +=0A= +#=0A= +# Miscellaneous filesystems=0A= +#=0A= +# CONFIG_ADFS_FS is not set=0A= +# CONFIG_AFFS_FS is not set=0A= +# CONFIG_HFS_FS is not set=0A= +# CONFIG_HFSPLUS_FS is not set=0A= +# CONFIG_BEFS_FS is not set=0A= +# CONFIG_BFS_FS is not set=0A= +# CONFIG_EFS_FS is not set=0A= +# CONFIG_CRAMFS is not set=0A= +# CONFIG_VXFS_FS is not set=0A= +# CONFIG_HPFS_FS is not set=0A= +# CONFIG_QNX4FS_FS is not set=0A= +# CONFIG_SYSV_FS is not set=0A= +# CONFIG_UFS_FS is not set=0A= +=0A= +#=0A= +# Network File Systems=0A= +#=0A= +# CONFIG_NFS_FS is not set=0A= +# CONFIG_NFSD is not set=0A= +# CONFIG_SMB_FS is not set=0A= +# CONFIG_CIFS is not set=0A= +# CONFIG_NCP_FS is not set=0A= +# CONFIG_CODA_FS is not set=0A= +# CONFIG_AFS_FS is not set=0A= +# CONFIG_9P_FS is not set=0A= +=0A= +#=0A= +# Partition Types=0A= +#=0A= +# CONFIG_PARTITION_ADVANCED is not set=0A= +CONFIG_MSDOS_PARTITION=3Dy=0A= +=0A= +#=0A= +# Native Language Support=0A= +#=0A= +# CONFIG_NLS is not set=0A= +=0A= +#=0A= +# Profiling support=0A= +#=0A= +# CONFIG_PROFILING is not set=0A= +=0A= +#=0A= +# Kernel hacking=0A= +#=0A= +# CONFIG_PRINTK_TIME is not set=0A= +# CONFIG_MAGIC_SYSRQ is not set=0A= +# CONFIG_DEBUG_KERNEL is not set=0A= +CONFIG_LOG_BUF_SHIFT=3D14=0A= +CONFIG_CROSSCOMPILE=3Dy=0A= +CONFIG_CMDLINE=3D""=0A= +=0A= +#=0A= +# Security options=0A= +#=0A= +# CONFIG_KEYS is not set=0A= +# CONFIG_SECURITY is not set=0A= +=0A= +#=0A= +# Cryptographic options=0A= +#=0A= +# CONFIG_CRYPTO is not set=0A= +=0A= +#=0A= +# Hardware crypto devices=0A= +#=0A= +=0A= +#=0A= +# Library routines=0A= +#=0A= +# CONFIG_CRC_CCITT is not set=0A= +CONFIG_CRC16=3Dy=0A= +CONFIG_CRC32=3Dy=0A= +CONFIG_LIBCRC32C=3Dy=0A= +CONFIG_TEXTSEARCH=3Dy=0A= +CONFIG_TEXTSEARCH_KMP=3Dm=0A= +CONFIG_TEXTSEARCH_BM=3Dm=0A= +CONFIG_TEXTSEARCH_FSM=3Dm=0A= diff -uNr linux-2.6.16-rc5/arch/mips/configs/rc32355_defconfig = idtlinux/arch/mips/configs/rc32355_defconfig=0A= --- linux-2.6.16-rc5/arch/mips/configs/rc32355_defconfig 1969-12-31 = 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/configs/rc32355_defconfig 2006-03-09 = 16:25:45.000000000 -0800=0A= @@ -0,0 +1,940 @@=0A= +#=0A= +# Automatically generated make config: don't edit=0A= +# Linux kernel version: 2.6.16-rc5=0A= +# Thu Mar 9 16:01:25 2006=0A= +#=0A= +CONFIG_MIPS=3Dy=0A= +=0A= +#=0A= +# Machine selection=0A= +#=0A= +# CONFIG_MIPS_MTX1 is not set=0A= +# CONFIG_MIPS_BOSPORUS is not set=0A= +# CONFIG_MIPS_PB1000 is not set=0A= +# CONFIG_MIPS_PB1100 is not set=0A= +# CONFIG_MIPS_PB1500 is not set=0A= +# CONFIG_MIPS_PB1550 is not set=0A= +# CONFIG_MIPS_PB1200 is not set=0A= +# CONFIG_MIPS_DB1000 is not set=0A= +# CONFIG_MIPS_DB1100 is not set=0A= +# CONFIG_MIPS_DB1500 is not set=0A= +# CONFIG_MIPS_DB1550 is not set=0A= +# CONFIG_MIPS_DB1200 is not set=0A= +# CONFIG_MIPS_MIRAGE is not set=0A= +# CONFIG_MIPS_COBALT is not set=0A= +# CONFIG_MACH_DECSTATION is not set=0A= +# CONFIG_MIPS_EV64120 is not set=0A= +# CONFIG_MIPS_EV96100 is not set=0A= +# CONFIG_MIPS_IVR is not set=0A= +CONFIG_IDT_BOARDS=3Dy=0A= +# CONFIG_MIPS_ITE8172 is not set=0A= +# CONFIG_MACH_JAZZ is not set=0A= +# CONFIG_LASAT is not set=0A= +# CONFIG_MIPS_ATLAS is not set=0A= +# CONFIG_MIPS_MALTA is not set=0A= +# CONFIG_MIPS_SEAD is not set=0A= +# CONFIG_MIPS_SIM is not set=0A= +# CONFIG_MOMENCO_JAGUAR_ATX is not set=0A= +# CONFIG_MOMENCO_OCELOT is not set=0A= +# CONFIG_MOMENCO_OCELOT_3 is not set=0A= +# CONFIG_MOMENCO_OCELOT_C is not set=0A= +# CONFIG_MOMENCO_OCELOT_G is not set=0A= +# CONFIG_MIPS_XXS1500 is not set=0A= +# CONFIG_PNX8550_V2PCI is not set=0A= +# CONFIG_PNX8550_JBS is not set=0A= +# CONFIG_DDB5074 is not set=0A= +# CONFIG_DDB5476 is not set=0A= +# CONFIG_DDB5477 is not set=0A= +# CONFIG_MACH_VR41XX is not set=0A= +# CONFIG_PMC_YOSEMITE is not set=0A= +# CONFIG_QEMU is not set=0A= +# CONFIG_SGI_IP22 is not set=0A= +# CONFIG_SGI_IP27 is not set=0A= +# CONFIG_SGI_IP32 is not set=0A= +# CONFIG_SIBYTE_BIGSUR is not set=0A= +# CONFIG_SIBYTE_SWARM is not set=0A= +# CONFIG_SIBYTE_SENTOSA is not set=0A= +# CONFIG_SIBYTE_RHONE is not set=0A= +# CONFIG_SIBYTE_CARMEL is not set=0A= +# CONFIG_SIBYTE_PTSWARM is not set=0A= +# CONFIG_SIBYTE_LITTLESUR is not set=0A= +# CONFIG_SIBYTE_CRHINE is not set=0A= +# CONFIG_SIBYTE_CRHONE is not set=0A= +# CONFIG_SNI_RM200_PCI is not set=0A= +# CONFIG_TOSHIBA_JMR3927 is not set=0A= +# CONFIG_TOSHIBA_RBTX4927 is not set=0A= +# CONFIG_TOSHIBA_RBTX4938 is not set=0A= +# CONFIG_IDT_EB438 is not set=0A= +# CONFIG_IDT_EB434 is not set=0A= +# CONFIG_IDT_EB365 is not set=0A= +CONFIG_IDT_EB355=3Dy=0A= +# CONFIG_IDT_S334 is not set=0A= +CONFIG_IDT_BOARD_FREQ=3D75000000=0A= +CONFIG_IDT_ZIMAGE_ADDR=3D0x8c000000=0A= +# CONFIG_IDT_BOOT_NVRAM is not set=0A= +CONFIG_RWSEM_GENERIC_SPINLOCK=3Dy=0A= +CONFIG_GENERIC_CALIBRATE_DELAY=3Dy=0A= +CONFIG_DMA_NONCOHERENT=3Dy=0A= +CONFIG_DMA_NEED_PCI_MAP_STATE=3Dy=0A= +# CONFIG_CPU_BIG_ENDIAN is not set=0A= +CONFIG_CPU_LITTLE_ENDIAN=3Dy=0A= +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=3Dy=0A= +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=3Dy=0A= +CONFIG_IRQ_CPU=3Dy=0A= +CONFIG_SWAP_IO_SPACE=3Dy=0A= +CONFIG_BOOT_ELF32=3Dy=0A= +CONFIG_MIPS_L1_CACHE_SHIFT=3D5=0A= +=0A= +#=0A= +# CPU selection=0A= +#=0A= +# CONFIG_CPU_MIPS32_R1 is not set=0A= +# CONFIG_CPU_MIPS32_R2 is not set=0A= +# CONFIG_CPU_MIPS64_R1 is not set=0A= +# CONFIG_CPU_MIPS64_R2 is not set=0A= +# CONFIG_CPU_R3000 is not set=0A= +CONFIG_CPU_RC32300=3Dy=0A= +# CONFIG_CPU_TX39XX is not set=0A= +# CONFIG_CPU_VR41XX is not set=0A= +# CONFIG_CPU_R4300 is not set=0A= +# CONFIG_CPU_R4X00 is not set=0A= +# CONFIG_CPU_TX49XX is not set=0A= +# CONFIG_CPU_R5000 is not set=0A= +# CONFIG_CPU_R5432 is not set=0A= +# CONFIG_CPU_R6000 is not set=0A= +# CONFIG_CPU_NEVADA is not set=0A= +# CONFIG_CPU_R8000 is not set=0A= +# CONFIG_CPU_R10000 is not set=0A= +# CONFIG_CPU_RM7000 is not set=0A= +# CONFIG_CPU_RM9000 is not set=0A= +# CONFIG_CPU_SB1 is not set=0A= +CONFIG_SYS_HAS_CPU_MIPS32_R1=3Dy=0A= +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=3Dy=0A= +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=3Dy=0A= +=0A= +#=0A= +# Kernel type=0A= +#=0A= +CONFIG_32BIT=3Dy=0A= +# CONFIG_64BIT is not set=0A= +CONFIG_PAGE_SIZE_4KB=3Dy=0A= +# CONFIG_PAGE_SIZE_8KB is not set=0A= +# CONFIG_PAGE_SIZE_16KB is not set=0A= +# CONFIG_PAGE_SIZE_64KB is not set=0A= +CONFIG_CPU_HAS_PREFETCH=3Dy=0A= +# CONFIG_MIPS_MT is not set=0A= +# CONFIG_CPU_ADVANCED is not set=0A= +CONFIG_CPU_HAS_LLSC=3Dy=0A= +CONFIG_CPU_HAS_SYNC=3Dy=0A= +CONFIG_GENERIC_HARDIRQS=3Dy=0A= +CONFIG_GENERIC_IRQ_PROBE=3Dy=0A= +CONFIG_ARCH_FLATMEM_ENABLE=3Dy=0A= +CONFIG_SELECT_MEMORY_MODEL=3Dy=0A= +CONFIG_FLATMEM_MANUAL=3Dy=0A= +# CONFIG_DISCONTIGMEM_MANUAL is not set=0A= +# CONFIG_SPARSEMEM_MANUAL is not set=0A= +CONFIG_FLATMEM=3Dy=0A= +CONFIG_FLAT_NODE_MEM_MAP=3Dy=0A= +# CONFIG_SPARSEMEM_STATIC is not set=0A= +CONFIG_SPLIT_PTLOCK_CPUS=3D4=0A= +CONFIG_PREEMPT_NONE=3Dy=0A= +# CONFIG_PREEMPT_VOLUNTARY is not set=0A= +# CONFIG_PREEMPT is not set=0A= +=0A= +#=0A= +# Code maturity level options=0A= +#=0A= +CONFIG_EXPERIMENTAL=3Dy=0A= +CONFIG_BROKEN_ON_SMP=3Dy=0A= +CONFIG_INIT_ENV_ARG_LIMIT=3D32=0A= +=0A= +#=0A= +# General setup=0A= +#=0A= +CONFIG_LOCALVERSION=3D""=0A= +CONFIG_LOCALVERSION_AUTO=3Dy=0A= +# CONFIG_SWAP is not set=0A= +CONFIG_SYSVIPC=3Dy=0A= +# CONFIG_POSIX_MQUEUE is not set=0A= +# CONFIG_BSD_PROCESS_ACCT is not set=0A= +CONFIG_SYSCTL=3Dy=0A= +# CONFIG_AUDIT is not set=0A= +CONFIG_IKCONFIG=3Dy=0A= +# CONFIG_IKCONFIG_PROC is not set=0A= +CONFIG_INITRAMFS_SOURCE=3D""=0A= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set=0A= +CONFIG_EMBEDDED=3Dy=0A= +# CONFIG_KALLSYMS is not set=0A= +# CONFIG_HOTPLUG is not set=0A= +CONFIG_PRINTK=3Dy=0A= +CONFIG_BUG=3Dy=0A= +CONFIG_ELF_CORE=3Dy=0A= +# CONFIG_BASE_FULL is not set=0A= +# CONFIG_FUTEX is not set=0A= +# CONFIG_EPOLL is not set=0A= +CONFIG_SHMEM=3Dy=0A= +CONFIG_CC_ALIGN_FUNCTIONS=3D0=0A= +CONFIG_CC_ALIGN_LABELS=3D0=0A= +CONFIG_CC_ALIGN_LOOPS=3D0=0A= +CONFIG_CC_ALIGN_JUMPS=3D0=0A= +# CONFIG_SLAB is not set=0A= +# CONFIG_TINY_SHMEM is not set=0A= +CONFIG_BASE_SMALL=3D1=0A= +CONFIG_SLOB=3Dy=0A= +=0A= +#=0A= +# Loadable module support=0A= +#=0A= +CONFIG_MODULES=3Dy=0A= +CONFIG_MODULE_UNLOAD=3Dy=0A= +# CONFIG_MODULE_FORCE_UNLOAD is not set=0A= +CONFIG_OBSOLETE_MODPARM=3Dy=0A= +# CONFIG_MODVERSIONS is not set=0A= +# CONFIG_MODULE_SRCVERSION_ALL is not set=0A= +# CONFIG_KMOD is not set=0A= +=0A= +#=0A= +# Block layer=0A= +#=0A= +# CONFIG_LBD is not set=0A= +=0A= +#=0A= +# IO Schedulers=0A= +#=0A= +CONFIG_IOSCHED_NOOP=3Dy=0A= +CONFIG_IOSCHED_AS=3Dy=0A= +CONFIG_IOSCHED_DEADLINE=3Dy=0A= +CONFIG_IOSCHED_CFQ=3Dy=0A= +CONFIG_DEFAULT_AS=3Dy=0A= +# CONFIG_DEFAULT_DEADLINE is not set=0A= +# CONFIG_DEFAULT_CFQ is not set=0A= +# CONFIG_DEFAULT_NOOP is not set=0A= +CONFIG_DEFAULT_IOSCHED=3D"anticipatory"=0A= +=0A= +#=0A= +# Bus options (PCI, PCMCIA, EISA, ISA, TC)=0A= +#=0A= +CONFIG_MMU=3Dy=0A= +=0A= +#=0A= +# PCCARD (PCMCIA/CardBus) support=0A= +#=0A= +# CONFIG_PCCARD is not set=0A= +=0A= +#=0A= +# PCI Hotplug Support=0A= +#=0A= +=0A= +#=0A= +# Executable file formats=0A= +#=0A= +CONFIG_BINFMT_ELF=3Dy=0A= +# CONFIG_BINFMT_MISC is not set=0A= +CONFIG_TRAD_SIGNALS=3Dy=0A= +=0A= +#=0A= +# Networking=0A= +#=0A= +CONFIG_NET=3Dy=0A= +=0A= +#=0A= +# Networking options=0A= +#=0A= +# CONFIG_NETDEBUG is not set=0A= +CONFIG_PACKET=3Dy=0A= +CONFIG_PACKET_MMAP=3Dy=0A= +CONFIG_UNIX=3Dy=0A= +CONFIG_XFRM=3Dy=0A= +# CONFIG_XFRM_USER is not set=0A= +CONFIG_NET_KEY=3Dy=0A= +CONFIG_INET=3Dy=0A= +CONFIG_IP_MULTICAST=3Dy=0A= +# CONFIG_IP_ADVANCED_ROUTER is not set=0A= +CONFIG_IP_FIB_HASH=3Dy=0A= +CONFIG_IP_PNP=3Dy=0A= +# CONFIG_IP_PNP_DHCP is not set=0A= +# CONFIG_IP_PNP_BOOTP is not set=0A= +# CONFIG_IP_PNP_RARP is not set=0A= +# CONFIG_NET_IPIP is not set=0A= +# CONFIG_NET_IPGRE is not set=0A= +# CONFIG_IP_MROUTE is not set=0A= +# CONFIG_ARPD is not set=0A= +# CONFIG_SYN_COOKIES is not set=0A= +# CONFIG_INET_AH is not set=0A= +# CONFIG_INET_ESP is not set=0A= +# CONFIG_INET_IPCOMP is not set=0A= +# CONFIG_INET_TUNNEL is not set=0A= +# CONFIG_INET_DIAG is not set=0A= +# CONFIG_TCP_CONG_ADVANCED is not set=0A= +CONFIG_TCP_CONG_BIC=3Dy=0A= +=0A= +#=0A= +# IP: Virtual Server Configuration=0A= +#=0A= +CONFIG_IP_VS=3Dm=0A= +# CONFIG_IP_VS_DEBUG is not set=0A= +CONFIG_IP_VS_TAB_BITS=3D12=0A= +=0A= +#=0A= +# IPVS transport protocol load balancing support=0A= +#=0A= +CONFIG_IP_VS_PROTO_TCP=3Dy=0A= +CONFIG_IP_VS_PROTO_UDP=3Dy=0A= +CONFIG_IP_VS_PROTO_ESP=3Dy=0A= +CONFIG_IP_VS_PROTO_AH=3Dy=0A= +=0A= +#=0A= +# IPVS scheduler=0A= +#=0A= +CONFIG_IP_VS_RR=3Dm=0A= +CONFIG_IP_VS_WRR=3Dm=0A= +CONFIG_IP_VS_LC=3Dm=0A= +CONFIG_IP_VS_WLC=3Dm=0A= +CONFIG_IP_VS_LBLC=3Dm=0A= +CONFIG_IP_VS_LBLCR=3Dm=0A= +CONFIG_IP_VS_DH=3Dm=0A= +CONFIG_IP_VS_SH=3Dm=0A= +CONFIG_IP_VS_SED=3Dm=0A= +CONFIG_IP_VS_NQ=3Dm=0A= +=0A= +#=0A= +# IPVS application helper=0A= +#=0A= +CONFIG_IP_VS_FTP=3Dm=0A= +# CONFIG_IPV6 is not set=0A= +CONFIG_NETFILTER=3Dy=0A= +# CONFIG_NETFILTER_DEBUG is not set=0A= +=0A= +#=0A= +# Core Netfilter Configuration=0A= +#=0A= +CONFIG_NETFILTER_NETLINK=3Dm=0A= +CONFIG_NETFILTER_NETLINK_QUEUE=3Dm=0A= +CONFIG_NETFILTER_NETLINK_LOG=3Dm=0A= +CONFIG_NETFILTER_XTABLES=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_CONNMARK=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_MARK=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_NOTRACK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_COMMENT=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNMARK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_DCCP=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_HELPER=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_LENGTH=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_LIMIT=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_MAC=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_MARK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_REALM=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_SCTP=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_STATE=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_STRING=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_TCPMSS=3Dm=0A= +=0A= +#=0A= +# IP: Netfilter Configuration=0A= +#=0A= +CONFIG_IP_NF_CONNTRACK=3Dm=0A= +CONFIG_IP_NF_CT_ACCT=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_MARK=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_EVENTS=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_NETLINK=3Dm=0A= +# CONFIG_IP_NF_CT_PROTO_SCTP is not set=0A= +CONFIG_IP_NF_FTP=3Dm=0A= +CONFIG_IP_NF_IRC=3Dm=0A= +# CONFIG_IP_NF_NETBIOS_NS is not set=0A= +CONFIG_IP_NF_TFTP=3Dm=0A= +CONFIG_IP_NF_AMANDA=3Dm=0A= +CONFIG_IP_NF_PPTP=3Dm=0A= +CONFIG_IP_NF_QUEUE=3Dm=0A= +CONFIG_IP_NF_IPTABLES=3Dm=0A= +CONFIG_IP_NF_MATCH_IPRANGE=3Dm=0A= +CONFIG_IP_NF_MATCH_MULTIPORT=3Dm=0A= +CONFIG_IP_NF_MATCH_TOS=3Dm=0A= +CONFIG_IP_NF_MATCH_RECENT=3Dm=0A= +CONFIG_IP_NF_MATCH_ECN=3Dm=0A= +CONFIG_IP_NF_MATCH_DSCP=3Dm=0A= +CONFIG_IP_NF_MATCH_AH_ESP=3Dm=0A= +CONFIG_IP_NF_MATCH_TTL=3Dm=0A= +CONFIG_IP_NF_MATCH_OWNER=3Dm=0A= +CONFIG_IP_NF_MATCH_ADDRTYPE=3Dm=0A= +CONFIG_IP_NF_MATCH_HASHLIMIT=3Dm=0A= +CONFIG_IP_NF_MATCH_POLICY=3Dm=0A= +CONFIG_IP_NF_FILTER=3Dm=0A= +CONFIG_IP_NF_TARGET_REJECT=3Dm=0A= +CONFIG_IP_NF_TARGET_LOG=3Dm=0A= +CONFIG_IP_NF_TARGET_ULOG=3Dm=0A= +CONFIG_IP_NF_TARGET_TCPMSS=3Dm=0A= +CONFIG_IP_NF_NAT=3Dm=0A= +CONFIG_IP_NF_NAT_NEEDED=3Dy=0A= +CONFIG_IP_NF_TARGET_MASQUERADE=3Dm=0A= +CONFIG_IP_NF_TARGET_REDIRECT=3Dm=0A= +CONFIG_IP_NF_TARGET_NETMAP=3Dm=0A= +CONFIG_IP_NF_TARGET_SAME=3Dm=0A= +CONFIG_IP_NF_NAT_SNMP_BASIC=3Dm=0A= +CONFIG_IP_NF_NAT_IRC=3Dm=0A= +CONFIG_IP_NF_NAT_FTP=3Dm=0A= +CONFIG_IP_NF_NAT_TFTP=3Dm=0A= +CONFIG_IP_NF_NAT_AMANDA=3Dm=0A= +CONFIG_IP_NF_NAT_PPTP=3Dm=0A= +CONFIG_IP_NF_MANGLE=3Dm=0A= +CONFIG_IP_NF_TARGET_TOS=3Dm=0A= +CONFIG_IP_NF_TARGET_ECN=3Dm=0A= +CONFIG_IP_NF_TARGET_DSCP=3Dm=0A= +CONFIG_IP_NF_TARGET_TTL=3Dm=0A= +CONFIG_IP_NF_TARGET_CLUSTERIP=3Dm=0A= +CONFIG_IP_NF_RAW=3Dm=0A= +CONFIG_IP_NF_ARPTABLES=3Dm=0A= +CONFIG_IP_NF_ARPFILTER=3Dm=0A= +CONFIG_IP_NF_ARP_MANGLE=3Dm=0A= +=0A= +#=0A= +# DCCP Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_IP_DCCP is not set=0A= +=0A= +#=0A= +# SCTP Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_IP_SCTP is not set=0A= +=0A= +#=0A= +# TIPC Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_TIPC is not set=0A= +# CONFIG_ATM is not set=0A= +# CONFIG_BRIDGE is not set=0A= +# CONFIG_VLAN_8021Q is not set=0A= +# CONFIG_DECNET is not set=0A= +# CONFIG_LLC2 is not set=0A= +# CONFIG_IPX is not set=0A= +# CONFIG_ATALK is not set=0A= +# CONFIG_X25 is not set=0A= +# CONFIG_LAPB is not set=0A= +# CONFIG_NET_DIVERT is not set=0A= +# CONFIG_ECONET is not set=0A= +# CONFIG_WAN_ROUTER is not set=0A= +=0A= +#=0A= +# QoS and/or fair queueing=0A= +#=0A= +CONFIG_NET_SCHED=3Dy=0A= +# CONFIG_NET_SCH_CLK_JIFFIES is not set=0A= +CONFIG_NET_SCH_CLK_GETTIMEOFDAY=3Dy=0A= +# CONFIG_NET_SCH_CLK_CPU is not set=0A= +=0A= +#=0A= +# Queueing/Scheduling=0A= +#=0A= +CONFIG_NET_SCH_CBQ=3Dm=0A= +CONFIG_NET_SCH_HTB=3Dm=0A= +CONFIG_NET_SCH_HFSC=3Dm=0A= +CONFIG_NET_SCH_PRIO=3Dm=0A= +CONFIG_NET_SCH_RED=3Dm=0A= +CONFIG_NET_SCH_SFQ=3Dm=0A= +CONFIG_NET_SCH_TEQL=3Dm=0A= +CONFIG_NET_SCH_TBF=3Dm=0A= +CONFIG_NET_SCH_GRED=3Dm=0A= +CONFIG_NET_SCH_DSMARK=3Dm=0A= +CONFIG_NET_SCH_NETEM=3Dm=0A= +CONFIG_NET_SCH_INGRESS=3Dm=0A= +=0A= +#=0A= +# Classification=0A= +#=0A= +CONFIG_NET_CLS=3Dy=0A= +CONFIG_NET_CLS_BASIC=3Dm=0A= +CONFIG_NET_CLS_TCINDEX=3Dm=0A= +CONFIG_NET_CLS_ROUTE4=3Dm=0A= +CONFIG_NET_CLS_ROUTE=3Dy=0A= +CONFIG_NET_CLS_FW=3Dm=0A= +CONFIG_NET_CLS_U32=3Dm=0A= +# CONFIG_CLS_U32_PERF is not set=0A= +# CONFIG_CLS_U32_MARK is not set=0A= +CONFIG_NET_CLS_RSVP=3Dm=0A= +CONFIG_NET_CLS_RSVP6=3Dm=0A= +# CONFIG_NET_EMATCH is not set=0A= +# CONFIG_NET_CLS_ACT is not set=0A= +CONFIG_NET_CLS_POLICE=3Dy=0A= +# CONFIG_NET_CLS_IND is not set=0A= +CONFIG_NET_ESTIMATOR=3Dy=0A= +=0A= +#=0A= +# Network testing=0A= +#=0A= +# CONFIG_NET_PKTGEN is not set=0A= +# CONFIG_HAMRADIO is not set=0A= +# CONFIG_IRDA is not set=0A= +# CONFIG_BT is not set=0A= +# CONFIG_IEEE80211 is not set=0A= +=0A= +#=0A= +# Device Drivers=0A= +#=0A= +=0A= +#=0A= +# Generic Driver Options=0A= +#=0A= +CONFIG_STANDALONE=3Dy=0A= +CONFIG_PREVENT_FIRMWARE_BUILD=3Dy=0A= +# CONFIG_FW_LOADER is not set=0A= +=0A= +#=0A= +# Connector - unified userspace <-> kernelspace linker=0A= +#=0A= +# CONFIG_CONNECTOR is not set=0A= +=0A= +#=0A= +# Memory Technology Devices (MTD)=0A= +#=0A= +# CONFIG_MTD is not set=0A= +=0A= +#=0A= +# Parallel port support=0A= +#=0A= +# CONFIG_PARPORT is not set=0A= +=0A= +#=0A= +# Plug and Play support=0A= +#=0A= +=0A= +#=0A= +# Block devices=0A= +#=0A= +# CONFIG_BLK_DEV_COW_COMMON is not set=0A= +# CONFIG_BLK_DEV_LOOP is not set=0A= +# CONFIG_BLK_DEV_NBD is not set=0A= +# CONFIG_BLK_DEV_RAM is not set=0A= +CONFIG_BLK_DEV_RAM_COUNT=3D16=0A= +# CONFIG_CDROM_PKTCDVD is not set=0A= +# CONFIG_ATA_OVER_ETH is not set=0A= +=0A= +#=0A= +# ATA/ATAPI/MFM/RLL support=0A= +#=0A= +# CONFIG_IDE is not set=0A= +=0A= +#=0A= +# SCSI device support=0A= +#=0A= +# CONFIG_RAID_ATTRS is not set=0A= +# CONFIG_SCSI is not set=0A= +=0A= +#=0A= +# Multi-device support (RAID and LVM)=0A= +#=0A= +# CONFIG_MD is not set=0A= +=0A= +#=0A= +# Fusion MPT device support=0A= +#=0A= +# CONFIG_FUSION is not set=0A= +=0A= +#=0A= +# IEEE 1394 (FireWire) support=0A= +#=0A= +=0A= +#=0A= +# I2O device support=0A= +#=0A= +=0A= +#=0A= +# Network device support=0A= +#=0A= +CONFIG_NETDEVICES=3Dy=0A= +# CONFIG_DUMMY is not set=0A= +# CONFIG_BONDING is not set=0A= +# CONFIG_EQUALIZER is not set=0A= +# CONFIG_TUN is not set=0A= +=0A= +#=0A= +# PHY device support=0A= +#=0A= +CONFIG_PHYLIB=3Dm=0A= +=0A= +#=0A= +# MII PHY device drivers=0A= +#=0A= +CONFIG_MARVELL_PHY=3Dm=0A= +CONFIG_DAVICOM_PHY=3Dm=0A= +CONFIG_QSEMI_PHY=3Dm=0A= +CONFIG_LXT_PHY=3Dm=0A= +CONFIG_CICADA_PHY=3Dm=0A= +=0A= +#=0A= +# Ethernet (10 or 100Mbit)=0A= +#=0A= +CONFIG_NET_ETHERNET=3Dy=0A= +CONFIG_MII=3Dy=0A= +CONFIG_IDT_RC32355_ETH=3Dy=0A= +# CONFIG_DM9000 is not set=0A= +=0A= +#=0A= +# Ethernet (1000 Mbit)=0A= +#=0A= +=0A= +#=0A= +# Ethernet (10000 Mbit)=0A= +#=0A= +=0A= +#=0A= +# Token Ring devices=0A= +#=0A= +=0A= +#=0A= +# Wireless LAN (non-hamradio)=0A= +#=0A= +# CONFIG_NET_RADIO is not set=0A= +=0A= +#=0A= +# Wan interfaces=0A= +#=0A= +# CONFIG_WAN is not set=0A= +# CONFIG_PPP is not set=0A= +# CONFIG_SLIP is not set=0A= +# CONFIG_SHAPER is not set=0A= +# CONFIG_NETCONSOLE is not set=0A= +# CONFIG_NETPOLL is not set=0A= +# CONFIG_NET_POLL_CONTROLLER is not set=0A= +=0A= +#=0A= +# ISDN subsystem=0A= +#=0A= +# CONFIG_ISDN is not set=0A= +=0A= +#=0A= +# Telephony Support=0A= +#=0A= +# CONFIG_PHONE is not set=0A= +=0A= +#=0A= +# Input device support=0A= +#=0A= +CONFIG_INPUT=3Dy=0A= +=0A= +#=0A= +# Userland interfaces=0A= +#=0A= +# CONFIG_INPUT_MOUSEDEV is not set=0A= +# CONFIG_INPUT_JOYDEV is not set=0A= +# CONFIG_INPUT_TSDEV is not set=0A= +# CONFIG_INPUT_EVDEV is not set=0A= +# CONFIG_INPUT_EVBUG is not set=0A= +=0A= +#=0A= +# Input Device Drivers=0A= +#=0A= +# CONFIG_INPUT_KEYBOARD is not set=0A= +# CONFIG_INPUT_MOUSE is not set=0A= +# CONFIG_INPUT_JOYSTICK is not set=0A= +# CONFIG_INPUT_TOUCHSCREEN is not set=0A= +# CONFIG_INPUT_MISC is not set=0A= +=0A= +#=0A= +# Hardware I/O ports=0A= +#=0A= +# CONFIG_SERIO is not set=0A= +# CONFIG_GAMEPORT is not set=0A= +=0A= +#=0A= +# Character devices=0A= +#=0A= +CONFIG_VT=3Dy=0A= +CONFIG_VT_CONSOLE=3Dy=0A= +CONFIG_HW_CONSOLE=3Dy=0A= +# CONFIG_SERIAL_NONSTANDARD is not set=0A= +=0A= +#=0A= +# Serial drivers=0A= +#=0A= +CONFIG_SERIAL_8250=3Dy=0A= +CONFIG_SERIAL_8250_CONSOLE=3Dy=0A= +CONFIG_SERIAL_8250_NR_UARTS=3D4=0A= +CONFIG_SERIAL_8250_RUNTIME_UARTS=3D4=0A= +# CONFIG_SERIAL_8250_EXTENDED is not set=0A= +=0A= +#=0A= +# Non-8250 serial port support=0A= +#=0A= +CONFIG_SERIAL_CORE=3Dy=0A= +CONFIG_SERIAL_CORE_CONSOLE=3Dy=0A= +CONFIG_UNIX98_PTYS=3Dy=0A= +CONFIG_LEGACY_PTYS=3Dy=0A= +CONFIG_LEGACY_PTY_COUNT=3D256=0A= +=0A= +#=0A= +# IPMI=0A= +#=0A= +# CONFIG_IPMI_HANDLER is not set=0A= +=0A= +#=0A= +# Watchdog Cards=0A= +#=0A= +# CONFIG_WATCHDOG is not set=0A= +# CONFIG_RTC is not set=0A= +# CONFIG_GEN_RTC is not set=0A= +# CONFIG_DTLK is not set=0A= +# CONFIG_R3964 is not set=0A= +=0A= +#=0A= +# Ftape, the floppy tape device driver=0A= +#=0A= +# CONFIG_RAW_DRIVER is not set=0A= +=0A= +#=0A= +# TPM devices=0A= +#=0A= +# CONFIG_TCG_TPM is not set=0A= +# CONFIG_TELCLOCK is not set=0A= +=0A= +#=0A= +# I2C support=0A= +#=0A= +CONFIG_I2C=3Dy=0A= +CONFIG_I2C_CHARDEV=3Dy=0A= +=0A= +#=0A= +# I2C Algorithms=0A= +#=0A= +# CONFIG_I2C_ALGOBIT is not set=0A= +# CONFIG_I2C_ALGOPCF is not set=0A= +# CONFIG_I2C_ALGOPCA is not set=0A= +=0A= +#=0A= +# I2C Hardware Bus support=0A= +#=0A= +# CONFIG_I2C_PARPORT_LIGHT is not set=0A= +# CONFIG_I2C_STUB is not set=0A= +# CONFIG_I2C_PCA_ISA is not set=0A= +CONFIG_I2C_RC32355=3Dy=0A= +=0A= +#=0A= +# Miscellaneous I2C Chip support=0A= +#=0A= +# CONFIG_SENSORS_DS1337 is not set=0A= +# CONFIG_SENSORS_DS1374 is not set=0A= +# CONFIG_SENSORS_EEPROM is not set=0A= +# CONFIG_SENSORS_PCF8574 is not set=0A= +# CONFIG_SENSORS_PCA9539 is not set=0A= +# CONFIG_SENSORS_PCF8591 is not set=0A= +# CONFIG_SENSORS_RTC8564 is not set=0A= +# CONFIG_SENSORS_MAX6875 is not set=0A= +# CONFIG_RTC_X1205_I2C is not set=0A= +# CONFIG_I2C_DEBUG_CORE is not set=0A= +# CONFIG_I2C_DEBUG_ALGO is not set=0A= +# CONFIG_I2C_DEBUG_BUS is not set=0A= +# CONFIG_I2C_DEBUG_CHIP is not set=0A= +=0A= +#=0A= +# SPI support=0A= +#=0A= +# CONFIG_SPI is not set=0A= +# CONFIG_SPI_MASTER is not set=0A= +=0A= +#=0A= +# Dallas's 1-wire bus=0A= +#=0A= +# CONFIG_W1 is not set=0A= +=0A= +#=0A= +# Hardware Monitoring support=0A= +#=0A= +# CONFIG_HWMON is not set=0A= +# CONFIG_HWMON_VID is not set=0A= +=0A= +#=0A= +# Misc devices=0A= +#=0A= +=0A= +#=0A= +# Multimedia Capabilities Port drivers=0A= +#=0A= +=0A= +#=0A= +# Multimedia devices=0A= +#=0A= +# CONFIG_VIDEO_DEV is not set=0A= +=0A= +#=0A= +# Digital Video Broadcasting Devices=0A= +#=0A= +# CONFIG_DVB is not set=0A= +=0A= +#=0A= +# Graphics support=0A= +#=0A= +# CONFIG_FB is not set=0A= +=0A= +#=0A= +# Console display driver support=0A= +#=0A= +# CONFIG_VGA_CONSOLE is not set=0A= +CONFIG_DUMMY_CONSOLE=3Dy=0A= +=0A= +#=0A= +# Sound=0A= +#=0A= +# CONFIG_SOUND is not set=0A= +=0A= +#=0A= +# USB support=0A= +#=0A= +# CONFIG_USB_ARCH_HAS_HCD is not set=0A= +# CONFIG_USB_ARCH_HAS_OHCI is not set=0A= +=0A= +#=0A= +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'=0A= +#=0A= +=0A= +#=0A= +# USB Gadget Support=0A= +#=0A= +# CONFIG_USB_GADGET is not set=0A= +=0A= +#=0A= +# MMC/SD Card support=0A= +#=0A= +# CONFIG_MMC is not set=0A= +=0A= +#=0A= +# InfiniBand support=0A= +#=0A= +=0A= +#=0A= +# SN Devices=0A= +#=0A= +=0A= +#=0A= +# EDAC - error detection and reporting (RAS)=0A= +#=0A= +=0A= +#=0A= +# File systems=0A= +#=0A= +CONFIG_EXT2_FS=3Dy=0A= +# CONFIG_EXT2_FS_XATTR is not set=0A= +# CONFIG_EXT2_FS_XIP is not set=0A= +# CONFIG_EXT3_FS is not set=0A= +# CONFIG_REISERFS_FS is not set=0A= +# CONFIG_JFS_FS is not set=0A= +# CONFIG_FS_POSIX_ACL is not set=0A= +# CONFIG_XFS_FS is not set=0A= +# CONFIG_OCFS2_FS is not set=0A= +# CONFIG_MINIX_FS is not set=0A= +# CONFIG_ROMFS_FS is not set=0A= +# CONFIG_INOTIFY is not set=0A= +# CONFIG_QUOTA is not set=0A= +# CONFIG_DNOTIFY is not set=0A= +# CONFIG_AUTOFS_FS is not set=0A= +# CONFIG_AUTOFS4_FS is not set=0A= +# CONFIG_FUSE_FS is not set=0A= +=0A= +#=0A= +# CD-ROM/DVD Filesystems=0A= +#=0A= +# CONFIG_ISO9660_FS is not set=0A= +# CONFIG_UDF_FS is not set=0A= +=0A= +#=0A= +# DOS/FAT/NT Filesystems=0A= +#=0A= +# CONFIG_MSDOS_FS is not set=0A= +# CONFIG_VFAT_FS is not set=0A= +# CONFIG_NTFS_FS is not set=0A= +=0A= +#=0A= +# Pseudo filesystems=0A= +#=0A= +CONFIG_PROC_FS=3Dy=0A= +CONFIG_PROC_KCORE=3Dy=0A= +CONFIG_SYSFS=3Dy=0A= +# CONFIG_TMPFS is not set=0A= +# CONFIG_HUGETLB_PAGE is not set=0A= +CONFIG_RAMFS=3Dy=0A= +# CONFIG_RELAYFS_FS is not set=0A= +# CONFIG_CONFIGFS_FS is not set=0A= +=0A= +#=0A= +# Miscellaneous filesystems=0A= +#=0A= +# CONFIG_ADFS_FS is not set=0A= +# CONFIG_AFFS_FS is not set=0A= +# CONFIG_HFS_FS is not set=0A= +# CONFIG_HFSPLUS_FS is not set=0A= +# CONFIG_BEFS_FS is not set=0A= +# CONFIG_BFS_FS is not set=0A= +# CONFIG_EFS_FS is not set=0A= +# CONFIG_CRAMFS is not set=0A= +# CONFIG_VXFS_FS is not set=0A= +# CONFIG_HPFS_FS is not set=0A= +# CONFIG_QNX4FS_FS is not set=0A= +# CONFIG_SYSV_FS is not set=0A= +# CONFIG_UFS_FS is not set=0A= +=0A= +#=0A= +# Network File Systems=0A= +#=0A= +# CONFIG_NFS_FS is not set=0A= +# CONFIG_NFSD is not set=0A= +# CONFIG_SMB_FS is not set=0A= +# CONFIG_CIFS is not set=0A= +# CONFIG_NCP_FS is not set=0A= +# CONFIG_CODA_FS is not set=0A= +# CONFIG_AFS_FS is not set=0A= +# CONFIG_9P_FS is not set=0A= +=0A= +#=0A= +# Partition Types=0A= +#=0A= +# CONFIG_PARTITION_ADVANCED is not set=0A= +CONFIG_MSDOS_PARTITION=3Dy=0A= +=0A= +#=0A= +# Native Language Support=0A= +#=0A= +# CONFIG_NLS is not set=0A= +=0A= +#=0A= +# Profiling support=0A= +#=0A= +# CONFIG_PROFILING is not set=0A= +=0A= +#=0A= +# Kernel hacking=0A= +#=0A= +# CONFIG_PRINTK_TIME is not set=0A= +# CONFIG_MAGIC_SYSRQ is not set=0A= +# CONFIG_DEBUG_KERNEL is not set=0A= +CONFIG_LOG_BUF_SHIFT=3D14=0A= +CONFIG_CROSSCOMPILE=3Dy=0A= +CONFIG_CMDLINE=3D""=0A= +=0A= +#=0A= +# Security options=0A= +#=0A= +# CONFIG_KEYS is not set=0A= +# CONFIG_SECURITY is not set=0A= +=0A= +#=0A= +# Cryptographic options=0A= +#=0A= +# CONFIG_CRYPTO is not set=0A= +=0A= +#=0A= +# Hardware crypto devices=0A= +#=0A= +=0A= +#=0A= +# Library routines=0A= +#=0A= +CONFIG_CRC_CCITT=3Dy=0A= +CONFIG_CRC16=3Dm=0A= +CONFIG_CRC32=3Dy=0A= +# CONFIG_LIBCRC32C is not set=0A= +CONFIG_TEXTSEARCH=3Dy=0A= +CONFIG_TEXTSEARCH_KMP=3Dm=0A= +CONFIG_TEXTSEARCH_BM=3Dm=0A= +CONFIG_TEXTSEARCH_FSM=3Dm=0A= diff -uNr linux-2.6.16-rc5/arch/mips/configs/rc32365_defconfig = idtlinux/arch/mips/configs/rc32365_defconfig=0A= --- linux-2.6.16-rc5/arch/mips/configs/rc32365_defconfig 1969-12-31 = 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/configs/rc32365_defconfig 2006-03-09 = 16:25:45.000000000 -0800=0A= @@ -0,0 +1,1029 @@=0A= +#=0A= +# Automatically generated make config: don't edit=0A= +# Linux kernel version: 2.6.16-rc5=0A= +# Thu Mar 9 16:13:13 2006=0A= +#=0A= +CONFIG_MIPS=3Dy=0A= +=0A= +#=0A= +# Machine selection=0A= +#=0A= +# CONFIG_MIPS_MTX1 is not set=0A= +# CONFIG_MIPS_BOSPORUS is not set=0A= +# CONFIG_MIPS_PB1000 is not set=0A= +# CONFIG_MIPS_PB1100 is not set=0A= +# CONFIG_MIPS_PB1500 is not set=0A= +# CONFIG_MIPS_PB1550 is not set=0A= +# CONFIG_MIPS_PB1200 is not set=0A= +# CONFIG_MIPS_DB1000 is not set=0A= +# CONFIG_MIPS_DB1100 is not set=0A= +# CONFIG_MIPS_DB1500 is not set=0A= +# CONFIG_MIPS_DB1550 is not set=0A= +# CONFIG_MIPS_DB1200 is not set=0A= +# CONFIG_MIPS_MIRAGE is not set=0A= +# CONFIG_MIPS_COBALT is not set=0A= +# CONFIG_MACH_DECSTATION is not set=0A= +# CONFIG_MIPS_EV64120 is not set=0A= +# CONFIG_MIPS_EV96100 is not set=0A= +# CONFIG_MIPS_IVR is not set=0A= +CONFIG_IDT_BOARDS=3Dy=0A= +# CONFIG_MIPS_ITE8172 is not set=0A= +# CONFIG_MACH_JAZZ is not set=0A= +# CONFIG_LASAT is not set=0A= +# CONFIG_MIPS_ATLAS is not set=0A= +# CONFIG_MIPS_MALTA is not set=0A= +# CONFIG_MIPS_SEAD is not set=0A= +# CONFIG_MIPS_SIM is not set=0A= +# CONFIG_MOMENCO_JAGUAR_ATX is not set=0A= +# CONFIG_MOMENCO_OCELOT is not set=0A= +# CONFIG_MOMENCO_OCELOT_3 is not set=0A= +# CONFIG_MOMENCO_OCELOT_C is not set=0A= +# CONFIG_MOMENCO_OCELOT_G is not set=0A= +# CONFIG_MIPS_XXS1500 is not set=0A= +# CONFIG_PNX8550_V2PCI is not set=0A= +# CONFIG_PNX8550_JBS is not set=0A= +# CONFIG_DDB5074 is not set=0A= +# CONFIG_DDB5476 is not set=0A= +# CONFIG_DDB5477 is not set=0A= +# CONFIG_MACH_VR41XX is not set=0A= +# CONFIG_PMC_YOSEMITE is not set=0A= +# CONFIG_QEMU is not set=0A= +# CONFIG_SGI_IP22 is not set=0A= +# CONFIG_SGI_IP27 is not set=0A= +# CONFIG_SGI_IP32 is not set=0A= +# CONFIG_SIBYTE_BIGSUR is not set=0A= +# CONFIG_SIBYTE_SWARM is not set=0A= +# CONFIG_SIBYTE_SENTOSA is not set=0A= +# CONFIG_SIBYTE_RHONE is not set=0A= +# CONFIG_SIBYTE_CARMEL is not set=0A= +# CONFIG_SIBYTE_PTSWARM is not set=0A= +# CONFIG_SIBYTE_LITTLESUR is not set=0A= +# CONFIG_SIBYTE_CRHINE is not set=0A= +# CONFIG_SIBYTE_CRHONE is not set=0A= +# CONFIG_SNI_RM200_PCI is not set=0A= +# CONFIG_TOSHIBA_JMR3927 is not set=0A= +# CONFIG_TOSHIBA_RBTX4927 is not set=0A= +# CONFIG_TOSHIBA_RBTX4938 is not set=0A= +# CONFIG_IDT_EB438 is not set=0A= +# CONFIG_IDT_EB434 is not set=0A= +CONFIG_IDT_EB365=3Dy=0A= +# CONFIG_IDT_EB355 is not set=0A= +# CONFIG_IDT_S334 is not set=0A= +CONFIG_IDT_BOARD_FREQ=3D90000000=0A= +CONFIG_IDT_ZIMAGE_ADDR=3D0x88000000=0A= +# CONFIG_IDT_BOOT_NVRAM is not set=0A= +CONFIG_RWSEM_GENERIC_SPINLOCK=3Dy=0A= +CONFIG_GENERIC_CALIBRATE_DELAY=3Dy=0A= +CONFIG_DMA_NONCOHERENT=3Dy=0A= +CONFIG_DMA_NEED_PCI_MAP_STATE=3Dy=0A= +# CONFIG_CPU_BIG_ENDIAN is not set=0A= +CONFIG_CPU_LITTLE_ENDIAN=3Dy=0A= +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=3Dy=0A= +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=3Dy=0A= +CONFIG_IRQ_CPU=3Dy=0A= +CONFIG_SWAP_IO_SPACE=3Dy=0A= +CONFIG_BOOT_ELF32=3Dy=0A= +CONFIG_MIPS_L1_CACHE_SHIFT=3D5=0A= +=0A= +#=0A= +# CPU selection=0A= +#=0A= +# CONFIG_CPU_MIPS32_R1 is not set=0A= +# CONFIG_CPU_MIPS32_R2 is not set=0A= +# CONFIG_CPU_MIPS64_R1 is not set=0A= +# CONFIG_CPU_MIPS64_R2 is not set=0A= +# CONFIG_CPU_R3000 is not set=0A= +CONFIG_CPU_RC32300=3Dy=0A= +# CONFIG_CPU_TX39XX is not set=0A= +# CONFIG_CPU_VR41XX is not set=0A= +# CONFIG_CPU_R4300 is not set=0A= +# CONFIG_CPU_R4X00 is not set=0A= +# CONFIG_CPU_TX49XX is not set=0A= +# CONFIG_CPU_R5000 is not set=0A= +# CONFIG_CPU_R5432 is not set=0A= +# CONFIG_CPU_R6000 is not set=0A= +# CONFIG_CPU_NEVADA is not set=0A= +# CONFIG_CPU_R8000 is not set=0A= +# CONFIG_CPU_R10000 is not set=0A= +# CONFIG_CPU_RM7000 is not set=0A= +# CONFIG_CPU_RM9000 is not set=0A= +# CONFIG_CPU_SB1 is not set=0A= +CONFIG_SYS_HAS_CPU_MIPS32_R1=3Dy=0A= +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=3Dy=0A= +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=3Dy=0A= +=0A= +#=0A= +# Kernel type=0A= +#=0A= +CONFIG_32BIT=3Dy=0A= +# CONFIG_64BIT is not set=0A= +CONFIG_PAGE_SIZE_4KB=3Dy=0A= +# CONFIG_PAGE_SIZE_8KB is not set=0A= +# CONFIG_PAGE_SIZE_16KB is not set=0A= +# CONFIG_PAGE_SIZE_64KB is not set=0A= +CONFIG_CPU_HAS_PREFETCH=3Dy=0A= +# CONFIG_MIPS_MT is not set=0A= +CONFIG_CPU_ADVANCED=3Dy=0A= +CONFIG_CPU_HAS_LLSC=3Dy=0A= +# CONFIG_CPU_HAS_WB is not set=0A= +CONFIG_CPU_HAS_SYNC=3Dy=0A= +CONFIG_GENERIC_HARDIRQS=3Dy=0A= +CONFIG_GENERIC_IRQ_PROBE=3Dy=0A= +CONFIG_ARCH_FLATMEM_ENABLE=3Dy=0A= +CONFIG_SELECT_MEMORY_MODEL=3Dy=0A= +CONFIG_FLATMEM_MANUAL=3Dy=0A= +# CONFIG_DISCONTIGMEM_MANUAL is not set=0A= +# CONFIG_SPARSEMEM_MANUAL is not set=0A= +CONFIG_FLATMEM=3Dy=0A= +CONFIG_FLAT_NODE_MEM_MAP=3Dy=0A= +# CONFIG_SPARSEMEM_STATIC is not set=0A= +CONFIG_SPLIT_PTLOCK_CPUS=3D4=0A= +CONFIG_PREEMPT_NONE=3Dy=0A= +# CONFIG_PREEMPT_VOLUNTARY is not set=0A= +# CONFIG_PREEMPT is not set=0A= +=0A= +#=0A= +# Code maturity level options=0A= +#=0A= +CONFIG_EXPERIMENTAL=3Dy=0A= +CONFIG_BROKEN_ON_SMP=3Dy=0A= +CONFIG_INIT_ENV_ARG_LIMIT=3D32=0A= +=0A= +#=0A= +# General setup=0A= +#=0A= +CONFIG_LOCALVERSION=3D""=0A= +CONFIG_LOCALVERSION_AUTO=3Dy=0A= +# CONFIG_SWAP is not set=0A= +CONFIG_SYSVIPC=3Dy=0A= +# CONFIG_POSIX_MQUEUE is not set=0A= +# CONFIG_BSD_PROCESS_ACCT is not set=0A= +CONFIG_SYSCTL=3Dy=0A= +# CONFIG_AUDIT is not set=0A= +CONFIG_IKCONFIG=3Dy=0A= +# CONFIG_IKCONFIG_PROC is not set=0A= +CONFIG_INITRAMFS_SOURCE=3D""=0A= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set=0A= +CONFIG_EMBEDDED=3Dy=0A= +# CONFIG_KALLSYMS is not set=0A= +# CONFIG_HOTPLUG is not set=0A= +CONFIG_PRINTK=3Dy=0A= +CONFIG_BUG=3Dy=0A= +CONFIG_ELF_CORE=3Dy=0A= +# CONFIG_BASE_FULL is not set=0A= +# CONFIG_FUTEX is not set=0A= +# CONFIG_EPOLL is not set=0A= +CONFIG_SHMEM=3Dy=0A= +CONFIG_CC_ALIGN_FUNCTIONS=3D0=0A= +CONFIG_CC_ALIGN_LABELS=3D0=0A= +CONFIG_CC_ALIGN_LOOPS=3D0=0A= +CONFIG_CC_ALIGN_JUMPS=3D0=0A= +# CONFIG_SLAB is not set=0A= +# CONFIG_TINY_SHMEM is not set=0A= +CONFIG_BASE_SMALL=3D1=0A= +CONFIG_SLOB=3Dy=0A= +=0A= +#=0A= +# Loadable module support=0A= +#=0A= +CONFIG_MODULES=3Dy=0A= +CONFIG_MODULE_UNLOAD=3Dy=0A= +# CONFIG_MODULE_FORCE_UNLOAD is not set=0A= +CONFIG_OBSOLETE_MODPARM=3Dy=0A= +# CONFIG_MODVERSIONS is not set=0A= +# CONFIG_MODULE_SRCVERSION_ALL is not set=0A= +# CONFIG_KMOD is not set=0A= +=0A= +#=0A= +# Block layer=0A= +#=0A= +# CONFIG_LBD is not set=0A= +=0A= +#=0A= +# IO Schedulers=0A= +#=0A= +CONFIG_IOSCHED_NOOP=3Dy=0A= +CONFIG_IOSCHED_AS=3Dy=0A= +CONFIG_IOSCHED_DEADLINE=3Dy=0A= +CONFIG_IOSCHED_CFQ=3Dy=0A= +CONFIG_DEFAULT_AS=3Dy=0A= +# CONFIG_DEFAULT_DEADLINE is not set=0A= +# CONFIG_DEFAULT_CFQ is not set=0A= +# CONFIG_DEFAULT_NOOP is not set=0A= +CONFIG_DEFAULT_IOSCHED=3D"anticipatory"=0A= +=0A= +#=0A= +# Bus options (PCI, PCMCIA, EISA, ISA, TC)=0A= +#=0A= +CONFIG_HW_HAS_PCI=3Dy=0A= +CONFIG_PCI=3Dy=0A= +CONFIG_PCI_LEGACY_PROC=3Dy=0A= +CONFIG_MMU=3Dy=0A= +=0A= +#=0A= +# PCCARD (PCMCIA/CardBus) support=0A= +#=0A= +# CONFIG_PCCARD is not set=0A= +=0A= +#=0A= +# PCI Hotplug Support=0A= +#=0A= +# CONFIG_HOTPLUG_PCI is not set=0A= +=0A= +#=0A= +# Executable file formats=0A= +#=0A= +CONFIG_BINFMT_ELF=3Dy=0A= +# CONFIG_BINFMT_MISC is not set=0A= +CONFIG_TRAD_SIGNALS=3Dy=0A= +=0A= +#=0A= +# Networking=0A= +#=0A= +CONFIG_NET=3Dy=0A= +=0A= +#=0A= +# Networking options=0A= +#=0A= +# CONFIG_NETDEBUG is not set=0A= +CONFIG_PACKET=3Dy=0A= +CONFIG_PACKET_MMAP=3Dy=0A= +CONFIG_UNIX=3Dy=0A= +CONFIG_XFRM=3Dy=0A= +# CONFIG_XFRM_USER is not set=0A= +CONFIG_NET_KEY=3Dy=0A= +CONFIG_INET=3Dy=0A= +CONFIG_IP_MULTICAST=3Dy=0A= +# CONFIG_IP_ADVANCED_ROUTER is not set=0A= +CONFIG_IP_FIB_HASH=3Dy=0A= +CONFIG_IP_PNP=3Dy=0A= +# CONFIG_IP_PNP_DHCP is not set=0A= +# CONFIG_IP_PNP_BOOTP is not set=0A= +# CONFIG_IP_PNP_RARP is not set=0A= +# CONFIG_NET_IPIP is not set=0A= +# CONFIG_NET_IPGRE is not set=0A= +# CONFIG_IP_MROUTE is not set=0A= +# CONFIG_ARPD is not set=0A= +# CONFIG_SYN_COOKIES is not set=0A= +# CONFIG_INET_AH is not set=0A= +# CONFIG_INET_ESP is not set=0A= +# CONFIG_INET_IPCOMP is not set=0A= +# CONFIG_INET_TUNNEL is not set=0A= +# CONFIG_INET_DIAG is not set=0A= +# CONFIG_TCP_CONG_ADVANCED is not set=0A= +CONFIG_TCP_CONG_BIC=3Dy=0A= +=0A= +#=0A= +# IP: Virtual Server Configuration=0A= +#=0A= +CONFIG_IP_VS=3Dm=0A= +# CONFIG_IP_VS_DEBUG is not set=0A= +CONFIG_IP_VS_TAB_BITS=3D12=0A= +=0A= +#=0A= +# IPVS transport protocol load balancing support=0A= +#=0A= +CONFIG_IP_VS_PROTO_TCP=3Dy=0A= +CONFIG_IP_VS_PROTO_UDP=3Dy=0A= +CONFIG_IP_VS_PROTO_ESP=3Dy=0A= +CONFIG_IP_VS_PROTO_AH=3Dy=0A= +=0A= +#=0A= +# IPVS scheduler=0A= +#=0A= +CONFIG_IP_VS_RR=3Dm=0A= +CONFIG_IP_VS_WRR=3Dm=0A= +CONFIG_IP_VS_LC=3Dm=0A= +CONFIG_IP_VS_WLC=3Dm=0A= +CONFIG_IP_VS_LBLC=3Dm=0A= +CONFIG_IP_VS_LBLCR=3Dm=0A= +CONFIG_IP_VS_DH=3Dm=0A= +CONFIG_IP_VS_SH=3Dm=0A= +CONFIG_IP_VS_SED=3Dm=0A= +CONFIG_IP_VS_NQ=3Dm=0A= +=0A= +#=0A= +# IPVS application helper=0A= +#=0A= +CONFIG_IP_VS_FTP=3Dm=0A= +# CONFIG_IPV6 is not set=0A= +CONFIG_NETFILTER=3Dy=0A= +# CONFIG_NETFILTER_DEBUG is not set=0A= +=0A= +#=0A= +# Core Netfilter Configuration=0A= +#=0A= +CONFIG_NETFILTER_NETLINK=3Dm=0A= +CONFIG_NETFILTER_NETLINK_QUEUE=3Dm=0A= +CONFIG_NETFILTER_NETLINK_LOG=3Dm=0A= +CONFIG_NETFILTER_XTABLES=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_CONNMARK=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_MARK=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_NOTRACK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_COMMENT=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNMARK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_DCCP=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_HELPER=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_LENGTH=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_LIMIT=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_MAC=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_MARK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_REALM=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_SCTP=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_STATE=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_STRING=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_TCPMSS=3Dm=0A= +=0A= +#=0A= +# IP: Netfilter Configuration=0A= +#=0A= +CONFIG_IP_NF_CONNTRACK=3Dm=0A= +CONFIG_IP_NF_CT_ACCT=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_MARK=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_EVENTS=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_NETLINK=3Dm=0A= +# CONFIG_IP_NF_CT_PROTO_SCTP is not set=0A= +CONFIG_IP_NF_FTP=3Dm=0A= +CONFIG_IP_NF_IRC=3Dm=0A= +# CONFIG_IP_NF_NETBIOS_NS is not set=0A= +CONFIG_IP_NF_TFTP=3Dm=0A= +CONFIG_IP_NF_AMANDA=3Dm=0A= +CONFIG_IP_NF_PPTP=3Dm=0A= +CONFIG_IP_NF_QUEUE=3Dm=0A= +CONFIG_IP_NF_IPTABLES=3Dm=0A= +CONFIG_IP_NF_MATCH_IPRANGE=3Dm=0A= +CONFIG_IP_NF_MATCH_MULTIPORT=3Dm=0A= +CONFIG_IP_NF_MATCH_TOS=3Dm=0A= +CONFIG_IP_NF_MATCH_RECENT=3Dm=0A= +CONFIG_IP_NF_MATCH_ECN=3Dm=0A= +CONFIG_IP_NF_MATCH_DSCP=3Dm=0A= +CONFIG_IP_NF_MATCH_AH_ESP=3Dm=0A= +CONFIG_IP_NF_MATCH_TTL=3Dm=0A= +CONFIG_IP_NF_MATCH_OWNER=3Dm=0A= +CONFIG_IP_NF_MATCH_ADDRTYPE=3Dm=0A= +CONFIG_IP_NF_MATCH_HASHLIMIT=3Dm=0A= +CONFIG_IP_NF_MATCH_POLICY=3Dm=0A= +CONFIG_IP_NF_FILTER=3Dm=0A= +CONFIG_IP_NF_TARGET_REJECT=3Dm=0A= +CONFIG_IP_NF_TARGET_LOG=3Dm=0A= +CONFIG_IP_NF_TARGET_ULOG=3Dm=0A= +CONFIG_IP_NF_TARGET_TCPMSS=3Dm=0A= +CONFIG_IP_NF_NAT=3Dm=0A= +CONFIG_IP_NF_NAT_NEEDED=3Dy=0A= +CONFIG_IP_NF_TARGET_MASQUERADE=3Dm=0A= +CONFIG_IP_NF_TARGET_REDIRECT=3Dm=0A= +CONFIG_IP_NF_TARGET_NETMAP=3Dm=0A= +CONFIG_IP_NF_TARGET_SAME=3Dm=0A= +CONFIG_IP_NF_NAT_SNMP_BASIC=3Dm=0A= +CONFIG_IP_NF_NAT_IRC=3Dm=0A= +CONFIG_IP_NF_NAT_FTP=3Dm=0A= +CONFIG_IP_NF_NAT_TFTP=3Dm=0A= +CONFIG_IP_NF_NAT_AMANDA=3Dm=0A= +CONFIG_IP_NF_NAT_PPTP=3Dm=0A= +CONFIG_IP_NF_MANGLE=3Dm=0A= +CONFIG_IP_NF_TARGET_TOS=3Dm=0A= +CONFIG_IP_NF_TARGET_ECN=3Dm=0A= +CONFIG_IP_NF_TARGET_DSCP=3Dm=0A= +CONFIG_IP_NF_TARGET_TTL=3Dm=0A= +CONFIG_IP_NF_TARGET_CLUSTERIP=3Dm=0A= +CONFIG_IP_NF_RAW=3Dm=0A= +CONFIG_IP_NF_ARPTABLES=3Dm=0A= +CONFIG_IP_NF_ARPFILTER=3Dm=0A= +CONFIG_IP_NF_ARP_MANGLE=3Dm=0A= +=0A= +#=0A= +# DCCP Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_IP_DCCP is not set=0A= +=0A= +#=0A= +# SCTP Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_IP_SCTP is not set=0A= +=0A= +#=0A= +# TIPC Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_TIPC is not set=0A= +# CONFIG_ATM is not set=0A= +# CONFIG_BRIDGE is not set=0A= +# CONFIG_VLAN_8021Q is not set=0A= +# CONFIG_DECNET is not set=0A= +# CONFIG_LLC2 is not set=0A= +# CONFIG_IPX is not set=0A= +# CONFIG_ATALK is not set=0A= +# CONFIG_X25 is not set=0A= +# CONFIG_LAPB is not set=0A= +# CONFIG_NET_DIVERT is not set=0A= +# CONFIG_ECONET is not set=0A= +# CONFIG_WAN_ROUTER is not set=0A= +=0A= +#=0A= +# QoS and/or fair queueing=0A= +#=0A= +CONFIG_NET_SCHED=3Dy=0A= +# CONFIG_NET_SCH_CLK_JIFFIES is not set=0A= +CONFIG_NET_SCH_CLK_GETTIMEOFDAY=3Dy=0A= +# CONFIG_NET_SCH_CLK_CPU is not set=0A= +=0A= +#=0A= +# Queueing/Scheduling=0A= +#=0A= +CONFIG_NET_SCH_CBQ=3Dm=0A= +CONFIG_NET_SCH_HTB=3Dm=0A= +CONFIG_NET_SCH_HFSC=3Dm=0A= +CONFIG_NET_SCH_PRIO=3Dm=0A= +CONFIG_NET_SCH_RED=3Dm=0A= +CONFIG_NET_SCH_SFQ=3Dm=0A= +CONFIG_NET_SCH_TEQL=3Dm=0A= +CONFIG_NET_SCH_TBF=3Dm=0A= +CONFIG_NET_SCH_GRED=3Dm=0A= +CONFIG_NET_SCH_DSMARK=3Dm=0A= +CONFIG_NET_SCH_NETEM=3Dm=0A= +CONFIG_NET_SCH_INGRESS=3Dm=0A= +=0A= +#=0A= +# Classification=0A= +#=0A= +CONFIG_NET_CLS=3Dy=0A= +CONFIG_NET_CLS_BASIC=3Dm=0A= +CONFIG_NET_CLS_TCINDEX=3Dm=0A= +CONFIG_NET_CLS_ROUTE4=3Dm=0A= +CONFIG_NET_CLS_ROUTE=3Dy=0A= +CONFIG_NET_CLS_FW=3Dm=0A= +CONFIG_NET_CLS_U32=3Dm=0A= +# CONFIG_CLS_U32_PERF is not set=0A= +# CONFIG_CLS_U32_MARK is not set=0A= +CONFIG_NET_CLS_RSVP=3Dm=0A= +CONFIG_NET_CLS_RSVP6=3Dm=0A= +# CONFIG_NET_EMATCH is not set=0A= +# CONFIG_NET_CLS_ACT is not set=0A= +CONFIG_NET_CLS_POLICE=3Dy=0A= +# CONFIG_NET_CLS_IND is not set=0A= +CONFIG_NET_ESTIMATOR=3Dy=0A= +=0A= +#=0A= +# Network testing=0A= +#=0A= +# CONFIG_NET_PKTGEN is not set=0A= +# CONFIG_HAMRADIO is not set=0A= +# CONFIG_IRDA is not set=0A= +# CONFIG_BT is not set=0A= +# CONFIG_IEEE80211 is not set=0A= +=0A= +#=0A= +# Device Drivers=0A= +#=0A= +=0A= +#=0A= +# Generic Driver Options=0A= +#=0A= +CONFIG_STANDALONE=3Dy=0A= +CONFIG_PREVENT_FIRMWARE_BUILD=3Dy=0A= +# CONFIG_FW_LOADER is not set=0A= +=0A= +#=0A= +# Connector - unified userspace <-> kernelspace linker=0A= +#=0A= +# CONFIG_CONNECTOR is not set=0A= +=0A= +#=0A= +# Memory Technology Devices (MTD)=0A= +#=0A= +# CONFIG_MTD is not set=0A= +=0A= +#=0A= +# Parallel port support=0A= +#=0A= +# CONFIG_PARPORT is not set=0A= +=0A= +#=0A= +# Plug and Play support=0A= +#=0A= +=0A= +#=0A= +# Block devices=0A= +#=0A= +# CONFIG_BLK_CPQ_DA is not set=0A= +# CONFIG_BLK_CPQ_CISS_DA is not set=0A= +# CONFIG_BLK_DEV_DAC960 is not set=0A= +# CONFIG_BLK_DEV_UMEM is not set=0A= +# CONFIG_BLK_DEV_COW_COMMON is not set=0A= +# CONFIG_BLK_DEV_LOOP is not set=0A= +# CONFIG_BLK_DEV_NBD is not set=0A= +# CONFIG_BLK_DEV_SX8 is not set=0A= +# CONFIG_BLK_DEV_RAM is not set=0A= +CONFIG_BLK_DEV_RAM_COUNT=3D16=0A= +# CONFIG_CDROM_PKTCDVD is not set=0A= +# CONFIG_ATA_OVER_ETH is not set=0A= +=0A= +#=0A= +# ATA/ATAPI/MFM/RLL support=0A= +#=0A= +# CONFIG_IDE is not set=0A= +=0A= +#=0A= +# SCSI device support=0A= +#=0A= +# CONFIG_RAID_ATTRS is not set=0A= +# CONFIG_SCSI is not set=0A= +=0A= +#=0A= +# Multi-device support (RAID and LVM)=0A= +#=0A= +# CONFIG_MD is not set=0A= +=0A= +#=0A= +# Fusion MPT device support=0A= +#=0A= +# CONFIG_FUSION is not set=0A= +=0A= +#=0A= +# IEEE 1394 (FireWire) support=0A= +#=0A= +# CONFIG_IEEE1394 is not set=0A= +=0A= +#=0A= +# I2O device support=0A= +#=0A= +# CONFIG_I2O is not set=0A= +=0A= +#=0A= +# Network device support=0A= +#=0A= +CONFIG_NETDEVICES=3Dy=0A= +# CONFIG_DUMMY is not set=0A= +# CONFIG_BONDING is not set=0A= +# CONFIG_EQUALIZER is not set=0A= +# CONFIG_TUN is not set=0A= +=0A= +#=0A= +# ARCnet devices=0A= +#=0A= +# CONFIG_ARCNET is not set=0A= +=0A= +#=0A= +# PHY device support=0A= +#=0A= +CONFIG_PHYLIB=3Dm=0A= +=0A= +#=0A= +# MII PHY device drivers=0A= +#=0A= +CONFIG_MARVELL_PHY=3Dm=0A= +CONFIG_DAVICOM_PHY=3Dm=0A= +CONFIG_QSEMI_PHY=3Dm=0A= +CONFIG_LXT_PHY=3Dm=0A= +CONFIG_CICADA_PHY=3Dm=0A= +=0A= +#=0A= +# Ethernet (10 or 100Mbit)=0A= +#=0A= +CONFIG_NET_ETHERNET=3Dy=0A= +CONFIG_MII=3Dy=0A= +CONFIG_IDT_RC32365_ETH=3Dy=0A= +# CONFIG_HAPPYMEAL is not set=0A= +# CONFIG_SUNGEM is not set=0A= +# CONFIG_CASSINI is not set=0A= +# CONFIG_NET_VENDOR_3COM is not set=0A= +# CONFIG_DM9000 is not set=0A= +=0A= +#=0A= +# Tulip family network device support=0A= +#=0A= +# CONFIG_NET_TULIP is not set=0A= +# CONFIG_HP100 is not set=0A= +CONFIG_NET_PCI=3Dy=0A= +# CONFIG_PCNET32 is not set=0A= +# CONFIG_AMD8111_ETH is not set=0A= +# CONFIG_ADAPTEC_STARFIRE is not set=0A= +# CONFIG_B44 is not set=0A= +# CONFIG_FORCEDETH is not set=0A= +# CONFIG_DGRS is not set=0A= +# CONFIG_EEPRO100 is not set=0A= +CONFIG_E100=3Dy=0A= +# CONFIG_FEALNX is not set=0A= +# CONFIG_NATSEMI is not set=0A= +# CONFIG_NE2K_PCI is not set=0A= +# CONFIG_8139CP is not set=0A= +# CONFIG_8139TOO is not set=0A= +# CONFIG_SIS900 is not set=0A= +# CONFIG_EPIC100 is not set=0A= +# CONFIG_SUNDANCE is not set=0A= +# CONFIG_TLAN is not set=0A= +# CONFIG_VIA_RHINE is not set=0A= +# CONFIG_LAN_SAA9730 is not set=0A= +=0A= +#=0A= +# Ethernet (1000 Mbit)=0A= +#=0A= +# CONFIG_ACENIC is not set=0A= +# CONFIG_DL2K is not set=0A= +# CONFIG_E1000 is not set=0A= +# CONFIG_NS83820 is not set=0A= +# CONFIG_HAMACHI is not set=0A= +# CONFIG_YELLOWFIN is not set=0A= +# CONFIG_R8169 is not set=0A= +# CONFIG_SIS190 is not set=0A= +# CONFIG_SKGE is not set=0A= +# CONFIG_SKY2 is not set=0A= +# CONFIG_SK98LIN is not set=0A= +# CONFIG_VIA_VELOCITY is not set=0A= +# CONFIG_TIGON3 is not set=0A= +# CONFIG_BNX2 is not set=0A= +=0A= +#=0A= +# Ethernet (10000 Mbit)=0A= +#=0A= +# CONFIG_CHELSIO_T1 is not set=0A= +# CONFIG_IXGB is not set=0A= +# CONFIG_S2IO is not set=0A= +=0A= +#=0A= +# Token Ring devices=0A= +#=0A= +# CONFIG_TR is not set=0A= +=0A= +#=0A= +# Wireless LAN (non-hamradio)=0A= +#=0A= +# CONFIG_NET_RADIO is not set=0A= +=0A= +#=0A= +# Wan interfaces=0A= +#=0A= +# CONFIG_WAN is not set=0A= +# CONFIG_FDDI is not set=0A= +# CONFIG_HIPPI is not set=0A= +# CONFIG_PPP is not set=0A= +# CONFIG_SLIP is not set=0A= +# CONFIG_SHAPER is not set=0A= +# CONFIG_NETCONSOLE is not set=0A= +# CONFIG_NETPOLL is not set=0A= +# CONFIG_NET_POLL_CONTROLLER is not set=0A= +=0A= +#=0A= +# ISDN subsystem=0A= +#=0A= +# CONFIG_ISDN is not set=0A= +=0A= +#=0A= +# Telephony Support=0A= +#=0A= +# CONFIG_PHONE is not set=0A= +=0A= +#=0A= +# Input device support=0A= +#=0A= +CONFIG_INPUT=3Dy=0A= +=0A= +#=0A= +# Userland interfaces=0A= +#=0A= +# CONFIG_INPUT_MOUSEDEV is not set=0A= +# CONFIG_INPUT_JOYDEV is not set=0A= +# CONFIG_INPUT_TSDEV is not set=0A= +# CONFIG_INPUT_EVDEV is not set=0A= +# CONFIG_INPUT_EVBUG is not set=0A= +=0A= +#=0A= +# Input Device Drivers=0A= +#=0A= +# CONFIG_INPUT_KEYBOARD is not set=0A= +# CONFIG_INPUT_MOUSE is not set=0A= +# CONFIG_INPUT_JOYSTICK is not set=0A= +# CONFIG_INPUT_TOUCHSCREEN is not set=0A= +# CONFIG_INPUT_MISC is not set=0A= +=0A= +#=0A= +# Hardware I/O ports=0A= +#=0A= +# CONFIG_SERIO is not set=0A= +# CONFIG_GAMEPORT is not set=0A= +=0A= +#=0A= +# Character devices=0A= +#=0A= +CONFIG_VT=3Dy=0A= +CONFIG_VT_CONSOLE=3Dy=0A= +CONFIG_HW_CONSOLE=3Dy=0A= +# CONFIG_SERIAL_NONSTANDARD is not set=0A= +=0A= +#=0A= +# Serial drivers=0A= +#=0A= +CONFIG_SERIAL_8250=3Dy=0A= +CONFIG_SERIAL_8250_CONSOLE=3Dy=0A= +CONFIG_SERIAL_8250_NR_UARTS=3D4=0A= +CONFIG_SERIAL_8250_RUNTIME_UARTS=3D4=0A= +# CONFIG_SERIAL_8250_EXTENDED is not set=0A= +=0A= +#=0A= +# Non-8250 serial port support=0A= +#=0A= +CONFIG_SERIAL_CORE=3Dy=0A= +CONFIG_SERIAL_CORE_CONSOLE=3Dy=0A= +# CONFIG_SERIAL_JSM is not set=0A= +CONFIG_UNIX98_PTYS=3Dy=0A= +CONFIG_LEGACY_PTYS=3Dy=0A= +CONFIG_LEGACY_PTY_COUNT=3D256=0A= +=0A= +#=0A= +# IPMI=0A= +#=0A= +# CONFIG_IPMI_HANDLER is not set=0A= +=0A= +#=0A= +# Watchdog Cards=0A= +#=0A= +# CONFIG_WATCHDOG is not set=0A= +# CONFIG_RTC is not set=0A= +# CONFIG_GEN_RTC is not set=0A= +# CONFIG_DTLK is not set=0A= +# CONFIG_R3964 is not set=0A= +# CONFIG_APPLICOM is not set=0A= +=0A= +#=0A= +# Ftape, the floppy tape device driver=0A= +#=0A= +# CONFIG_DRM is not set=0A= +# CONFIG_RAW_DRIVER is not set=0A= +=0A= +#=0A= +# TPM devices=0A= +#=0A= +# CONFIG_TCG_TPM is not set=0A= +# CONFIG_TELCLOCK is not set=0A= +=0A= +#=0A= +# I2C support=0A= +#=0A= +CONFIG_I2C=3Dy=0A= +CONFIG_I2C_CHARDEV=3Dy=0A= +=0A= +#=0A= +# I2C Algorithms=0A= +#=0A= +# CONFIG_I2C_ALGOBIT is not set=0A= +# CONFIG_I2C_ALGOPCF is not set=0A= +# CONFIG_I2C_ALGOPCA is not set=0A= +=0A= +#=0A= +# I2C Hardware Bus support=0A= +#=0A= +# CONFIG_I2C_ALI1535 is not set=0A= +# CONFIG_I2C_ALI1563 is not set=0A= +# CONFIG_I2C_ALI15X3 is not set=0A= +# CONFIG_I2C_AMD756 is not set=0A= +# CONFIG_I2C_AMD8111 is not set=0A= +# CONFIG_I2C_I801 is not set=0A= +# CONFIG_I2C_I810 is not set=0A= +# CONFIG_I2C_PIIX4 is not set=0A= +# CONFIG_I2C_NFORCE2 is not set=0A= +# CONFIG_I2C_PARPORT_LIGHT is not set=0A= +# CONFIG_I2C_PROSAVAGE is not set=0A= +# CONFIG_I2C_SAVAGE4 is not set=0A= +# CONFIG_SCx200_ACB is not set=0A= +# CONFIG_I2C_SIS5595 is not set=0A= +# CONFIG_I2C_SIS630 is not set=0A= +# CONFIG_I2C_SIS96X is not set=0A= +# CONFIG_I2C_STUB is not set=0A= +# CONFIG_I2C_VIA is not set=0A= +# CONFIG_I2C_VIAPRO is not set=0A= +# CONFIG_I2C_VOODOO3 is not set=0A= +# CONFIG_I2C_PCA_ISA is not set=0A= +=0A= +#=0A= +# Miscellaneous I2C Chip support=0A= +#=0A= +# CONFIG_SENSORS_DS1337 is not set=0A= +# CONFIG_SENSORS_DS1374 is not set=0A= +# CONFIG_SENSORS_EEPROM is not set=0A= +# CONFIG_SENSORS_PCF8574 is not set=0A= +# CONFIG_SENSORS_PCA9539 is not set=0A= +# CONFIG_SENSORS_PCF8591 is not set=0A= +# CONFIG_SENSORS_RTC8564 is not set=0A= +# CONFIG_SENSORS_MAX6875 is not set=0A= +# CONFIG_RTC_X1205_I2C is not set=0A= +# CONFIG_I2C_DEBUG_CORE is not set=0A= +# CONFIG_I2C_DEBUG_ALGO is not set=0A= +# CONFIG_I2C_DEBUG_BUS is not set=0A= +# CONFIG_I2C_DEBUG_CHIP is not set=0A= +=0A= +#=0A= +# SPI support=0A= +#=0A= +# CONFIG_SPI is not set=0A= +# CONFIG_SPI_MASTER is not set=0A= +=0A= +#=0A= +# Dallas's 1-wire bus=0A= +#=0A= +# CONFIG_W1 is not set=0A= +=0A= +#=0A= +# Hardware Monitoring support=0A= +#=0A= +# CONFIG_HWMON is not set=0A= +# CONFIG_HWMON_VID is not set=0A= +=0A= +#=0A= +# Misc devices=0A= +#=0A= +=0A= +#=0A= +# Multimedia Capabilities Port drivers=0A= +#=0A= +=0A= +#=0A= +# Multimedia devices=0A= +#=0A= +# CONFIG_VIDEO_DEV is not set=0A= +=0A= +#=0A= +# Digital Video Broadcasting Devices=0A= +#=0A= +# CONFIG_DVB is not set=0A= +=0A= +#=0A= +# Graphics support=0A= +#=0A= +# CONFIG_FB is not set=0A= +=0A= +#=0A= +# Console display driver support=0A= +#=0A= +# CONFIG_VGA_CONSOLE is not set=0A= +CONFIG_DUMMY_CONSOLE=3Dy=0A= +=0A= +#=0A= +# Sound=0A= +#=0A= +# CONFIG_SOUND is not set=0A= +=0A= +#=0A= +# USB support=0A= +#=0A= +CONFIG_USB_ARCH_HAS_HCD=3Dy=0A= +CONFIG_USB_ARCH_HAS_OHCI=3Dy=0A= +# CONFIG_USB is not set=0A= +=0A= +#=0A= +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'=0A= +#=0A= +=0A= +#=0A= +# USB Gadget Support=0A= +#=0A= +# CONFIG_USB_GADGET is not set=0A= +=0A= +#=0A= +# MMC/SD Card support=0A= +#=0A= +# CONFIG_MMC is not set=0A= +=0A= +#=0A= +# InfiniBand support=0A= +#=0A= +# CONFIG_INFINIBAND is not set=0A= +=0A= +#=0A= +# SN Devices=0A= +#=0A= +=0A= +#=0A= +# EDAC - error detection and reporting (RAS)=0A= +#=0A= +=0A= +#=0A= +# File systems=0A= +#=0A= +CONFIG_EXT2_FS=3Dy=0A= +# CONFIG_EXT2_FS_XATTR is not set=0A= +# CONFIG_EXT2_FS_XIP is not set=0A= +# CONFIG_EXT3_FS is not set=0A= +# CONFIG_REISERFS_FS is not set=0A= +# CONFIG_JFS_FS is not set=0A= +# CONFIG_FS_POSIX_ACL is not set=0A= +# CONFIG_XFS_FS is not set=0A= +# CONFIG_OCFS2_FS is not set=0A= +# CONFIG_MINIX_FS is not set=0A= +# CONFIG_ROMFS_FS is not set=0A= +# CONFIG_INOTIFY is not set=0A= +# CONFIG_QUOTA is not set=0A= +# CONFIG_DNOTIFY is not set=0A= +# CONFIG_AUTOFS_FS is not set=0A= +# CONFIG_AUTOFS4_FS is not set=0A= +# CONFIG_FUSE_FS is not set=0A= +=0A= +#=0A= +# CD-ROM/DVD Filesystems=0A= +#=0A= +# CONFIG_ISO9660_FS is not set=0A= +# CONFIG_UDF_FS is not set=0A= +=0A= +#=0A= +# DOS/FAT/NT Filesystems=0A= +#=0A= +# CONFIG_MSDOS_FS is not set=0A= +# CONFIG_VFAT_FS is not set=0A= +# CONFIG_NTFS_FS is not set=0A= +=0A= +#=0A= +# Pseudo filesystems=0A= +#=0A= +CONFIG_PROC_FS=3Dy=0A= +CONFIG_PROC_KCORE=3Dy=0A= +CONFIG_SYSFS=3Dy=0A= +# CONFIG_TMPFS is not set=0A= +# CONFIG_HUGETLB_PAGE is not set=0A= +CONFIG_RAMFS=3Dy=0A= +# CONFIG_RELAYFS_FS is not set=0A= +# CONFIG_CONFIGFS_FS is not set=0A= +=0A= +#=0A= +# Miscellaneous filesystems=0A= +#=0A= +# CONFIG_ADFS_FS is not set=0A= +# CONFIG_AFFS_FS is not set=0A= +# CONFIG_HFS_FS is not set=0A= +# CONFIG_HFSPLUS_FS is not set=0A= +# CONFIG_BEFS_FS is not set=0A= +# CONFIG_BFS_FS is not set=0A= +# CONFIG_EFS_FS is not set=0A= +# CONFIG_CRAMFS is not set=0A= +# CONFIG_VXFS_FS is not set=0A= +# CONFIG_HPFS_FS is not set=0A= +# CONFIG_QNX4FS_FS is not set=0A= +# CONFIG_SYSV_FS is not set=0A= +# CONFIG_UFS_FS is not set=0A= +=0A= +#=0A= +# Network File Systems=0A= +#=0A= +# CONFIG_NFS_FS is not set=0A= +# CONFIG_NFSD is not set=0A= +# CONFIG_SMB_FS is not set=0A= +# CONFIG_CIFS is not set=0A= +# CONFIG_NCP_FS is not set=0A= +# CONFIG_CODA_FS is not set=0A= +# CONFIG_AFS_FS is not set=0A= +# CONFIG_9P_FS is not set=0A= +=0A= +#=0A= +# Partition Types=0A= +#=0A= +# CONFIG_PARTITION_ADVANCED is not set=0A= +CONFIG_MSDOS_PARTITION=3Dy=0A= +=0A= +#=0A= +# Native Language Support=0A= +#=0A= +# CONFIG_NLS is not set=0A= +=0A= +#=0A= +# Profiling support=0A= +#=0A= +# CONFIG_PROFILING is not set=0A= +=0A= +#=0A= +# Kernel hacking=0A= +#=0A= +# CONFIG_PRINTK_TIME is not set=0A= +# CONFIG_MAGIC_SYSRQ is not set=0A= +# CONFIG_DEBUG_KERNEL is not set=0A= +CONFIG_LOG_BUF_SHIFT=3D14=0A= +CONFIG_CROSSCOMPILE=3Dy=0A= +CONFIG_CMDLINE=3D""=0A= +=0A= +#=0A= +# Security options=0A= +#=0A= +# CONFIG_KEYS is not set=0A= +# CONFIG_SECURITY is not set=0A= +=0A= +#=0A= +# Cryptographic options=0A= +#=0A= +# CONFIG_CRYPTO is not set=0A= +=0A= +#=0A= +# Hardware crypto devices=0A= +#=0A= +=0A= +#=0A= +# Library routines=0A= +#=0A= +CONFIG_CRC_CCITT=3Dy=0A= +CONFIG_CRC16=3Dm=0A= +CONFIG_CRC32=3Dy=0A= +# CONFIG_LIBCRC32C is not set=0A= +CONFIG_TEXTSEARCH=3Dy=0A= +CONFIG_TEXTSEARCH_KMP=3Dm=0A= +CONFIG_TEXTSEARCH_BM=3Dm=0A= +CONFIG_TEXTSEARCH_FSM=3Dm=0A= diff -uNr linux-2.6.16-rc5/arch/mips/configs/rc32434_defconfig = idtlinux/arch/mips/configs/rc32434_defconfig=0A= --- linux-2.6.16-rc5/arch/mips/configs/rc32434_defconfig 1969-12-31 = 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/configs/rc32434_defconfig 2006-03-09 = 16:25:45.000000000 -0800=0A= @@ -0,0 +1,1032 @@=0A= +#=0A= +# Automatically generated make config: don't edit=0A= +# Linux kernel version: 2.6.16-rc5=0A= +# Thu Mar 9 11:35:54 2006=0A= +#=0A= +CONFIG_MIPS=3Dy=0A= +=0A= +#=0A= +# Machine selection=0A= +#=0A= +# CONFIG_MIPS_MTX1 is not set=0A= +# CONFIG_MIPS_BOSPORUS is not set=0A= +# CONFIG_MIPS_PB1000 is not set=0A= +# CONFIG_MIPS_PB1100 is not set=0A= +# CONFIG_MIPS_PB1500 is not set=0A= +# CONFIG_MIPS_PB1550 is not set=0A= +# CONFIG_MIPS_PB1200 is not set=0A= +# CONFIG_MIPS_DB1000 is not set=0A= +# CONFIG_MIPS_DB1100 is not set=0A= +# CONFIG_MIPS_DB1500 is not set=0A= +# CONFIG_MIPS_DB1550 is not set=0A= +# CONFIG_MIPS_DB1200 is not set=0A= +# CONFIG_MIPS_MIRAGE is not set=0A= +# CONFIG_MIPS_COBALT is not set=0A= +# CONFIG_MACH_DECSTATION is not set=0A= +# CONFIG_MIPS_EV64120 is not set=0A= +# CONFIG_MIPS_EV96100 is not set=0A= +# CONFIG_MIPS_IVR is not set=0A= +CONFIG_IDT_BOARDS=3Dy=0A= +# CONFIG_MIPS_ITE8172 is not set=0A= +# CONFIG_MACH_JAZZ is not set=0A= +# CONFIG_LASAT is not set=0A= +# CONFIG_MIPS_ATLAS is not set=0A= +# CONFIG_MIPS_MALTA is not set=0A= +# CONFIG_MIPS_SEAD is not set=0A= +# CONFIG_MIPS_SIM is not set=0A= +# CONFIG_MOMENCO_JAGUAR_ATX is not set=0A= +# CONFIG_MOMENCO_OCELOT is not set=0A= +# CONFIG_MOMENCO_OCELOT_3 is not set=0A= +# CONFIG_MOMENCO_OCELOT_C is not set=0A= +# CONFIG_MOMENCO_OCELOT_G is not set=0A= +# CONFIG_MIPS_XXS1500 is not set=0A= +# CONFIG_PNX8550_V2PCI is not set=0A= +# CONFIG_PNX8550_JBS is not set=0A= +# CONFIG_DDB5074 is not set=0A= +# CONFIG_DDB5476 is not set=0A= +# CONFIG_DDB5477 is not set=0A= +# CONFIG_MACH_VR41XX is not set=0A= +# CONFIG_PMC_YOSEMITE is not set=0A= +# CONFIG_QEMU is not set=0A= +# CONFIG_SGI_IP22 is not set=0A= +# CONFIG_SGI_IP27 is not set=0A= +# CONFIG_SGI_IP32 is not set=0A= +# CONFIG_SIBYTE_BIGSUR is not set=0A= +# CONFIG_SIBYTE_SWARM is not set=0A= +# CONFIG_SIBYTE_SENTOSA is not set=0A= +# CONFIG_SIBYTE_RHONE is not set=0A= +# CONFIG_SIBYTE_CARMEL is not set=0A= +# CONFIG_SIBYTE_PTSWARM is not set=0A= +# CONFIG_SIBYTE_LITTLESUR is not set=0A= +# CONFIG_SIBYTE_CRHINE is not set=0A= +# CONFIG_SIBYTE_CRHONE is not set=0A= +# CONFIG_SNI_RM200_PCI is not set=0A= +# CONFIG_TOSHIBA_JMR3927 is not set=0A= +# CONFIG_TOSHIBA_RBTX4927 is not set=0A= +# CONFIG_TOSHIBA_RBTX4938 is not set=0A= +# CONFIG_IDT_EB438 is not set=0A= +CONFIG_IDT_EB434=3Dy=0A= +# CONFIG_IDT_EB365 is not set=0A= +# CONFIG_IDT_EB355 is not set=0A= +# CONFIG_IDT_S334 is not set=0A= +CONFIG_IDT_BOARD_FREQ=3D200000000=0A= +CONFIG_IDT_ZIMAGE_ADDR=3D0x9b000000=0A= +# CONFIG_IDT_BOOT_NVRAM is not set=0A= +CONFIG_RWSEM_GENERIC_SPINLOCK=3Dy=0A= +CONFIG_GENERIC_CALIBRATE_DELAY=3Dy=0A= +CONFIG_DMA_NONCOHERENT=3Dy=0A= +CONFIG_DMA_NEED_PCI_MAP_STATE=3Dy=0A= +# CONFIG_CPU_BIG_ENDIAN is not set=0A= +CONFIG_CPU_LITTLE_ENDIAN=3Dy=0A= +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=3Dy=0A= +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=3Dy=0A= +CONFIG_IRQ_CPU=3Dy=0A= +CONFIG_SWAP_IO_SPACE=3Dy=0A= +CONFIG_BOOT_ELF32=3Dy=0A= +CONFIG_MIPS_L1_CACHE_SHIFT=3D5=0A= +=0A= +#=0A= +# CPU selection=0A= +#=0A= +CONFIG_CPU_MIPS32_R1=3Dy=0A= +# CONFIG_CPU_MIPS32_R2 is not set=0A= +# CONFIG_CPU_MIPS64_R1 is not set=0A= +# CONFIG_CPU_MIPS64_R2 is not set=0A= +# CONFIG_CPU_R3000 is not set=0A= +# CONFIG_CPU_TX39XX is not set=0A= +# CONFIG_CPU_VR41XX is not set=0A= +# CONFIG_CPU_R4300 is not set=0A= +# CONFIG_CPU_R4X00 is not set=0A= +# CONFIG_CPU_TX49XX is not set=0A= +# CONFIG_CPU_R5000 is not set=0A= +# CONFIG_CPU_R5432 is not set=0A= +# CONFIG_CPU_R6000 is not set=0A= +# CONFIG_CPU_NEVADA is not set=0A= +# CONFIG_CPU_R8000 is not set=0A= +# CONFIG_CPU_R10000 is not set=0A= +# CONFIG_CPU_RM7000 is not set=0A= +# CONFIG_CPU_RM9000 is not set=0A= +# CONFIG_CPU_SB1 is not set=0A= +CONFIG_SYS_HAS_CPU_MIPS32_R1=3Dy=0A= +CONFIG_CPU_MIPS32=3Dy=0A= +CONFIG_CPU_MIPSR1=3Dy=0A= +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=3Dy=0A= +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=3Dy=0A= +=0A= +#=0A= +# Kernel type=0A= +#=0A= +CONFIG_32BIT=3Dy=0A= +# CONFIG_64BIT is not set=0A= +CONFIG_PAGE_SIZE_4KB=3Dy=0A= +# CONFIG_PAGE_SIZE_8KB is not set=0A= +# CONFIG_PAGE_SIZE_16KB is not set=0A= +# CONFIG_PAGE_SIZE_64KB is not set=0A= +CONFIG_CPU_HAS_PREFETCH=3Dy=0A= +# CONFIG_MIPS_MT is not set=0A= +# CONFIG_64BIT_PHYS_ADDR is not set=0A= +CONFIG_CPU_ADVANCED=3Dy=0A= +CONFIG_CPU_HAS_LLSC=3Dy=0A= +# CONFIG_CPU_HAS_WB is not set=0A= +CONFIG_CPU_HAS_SYNC=3Dy=0A= +CONFIG_GENERIC_HARDIRQS=3Dy=0A= +CONFIG_GENERIC_IRQ_PROBE=3Dy=0A= +CONFIG_ARCH_FLATMEM_ENABLE=3Dy=0A= +CONFIG_SELECT_MEMORY_MODEL=3Dy=0A= +CONFIG_FLATMEM_MANUAL=3Dy=0A= +# CONFIG_DISCONTIGMEM_MANUAL is not set=0A= +# CONFIG_SPARSEMEM_MANUAL is not set=0A= +CONFIG_FLATMEM=3Dy=0A= +CONFIG_FLAT_NODE_MEM_MAP=3Dy=0A= +# CONFIG_SPARSEMEM_STATIC is not set=0A= +CONFIG_SPLIT_PTLOCK_CPUS=3D4=0A= +CONFIG_PREEMPT_NONE=3Dy=0A= +# CONFIG_PREEMPT_VOLUNTARY is not set=0A= +# CONFIG_PREEMPT is not set=0A= +=0A= +#=0A= +# Code maturity level options=0A= +#=0A= +CONFIG_EXPERIMENTAL=3Dy=0A= +CONFIG_BROKEN_ON_SMP=3Dy=0A= +CONFIG_INIT_ENV_ARG_LIMIT=3D32=0A= +=0A= +#=0A= +# General setup=0A= +#=0A= +CONFIG_LOCALVERSION=3D""=0A= +CONFIG_LOCALVERSION_AUTO=3Dy=0A= +# CONFIG_SWAP is not set=0A= +CONFIG_SYSVIPC=3Dy=0A= +# CONFIG_POSIX_MQUEUE is not set=0A= +# CONFIG_BSD_PROCESS_ACCT is not set=0A= +CONFIG_SYSCTL=3Dy=0A= +# CONFIG_AUDIT is not set=0A= +CONFIG_IKCONFIG=3Dy=0A= +# CONFIG_IKCONFIG_PROC is not set=0A= +CONFIG_INITRAMFS_SOURCE=3D""=0A= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set=0A= +CONFIG_EMBEDDED=3Dy=0A= +# CONFIG_KALLSYMS is not set=0A= +# CONFIG_HOTPLUG is not set=0A= +CONFIG_PRINTK=3Dy=0A= +CONFIG_BUG=3Dy=0A= +CONFIG_ELF_CORE=3Dy=0A= +# CONFIG_BASE_FULL is not set=0A= +# CONFIG_FUTEX is not set=0A= +# CONFIG_EPOLL is not set=0A= +CONFIG_SHMEM=3Dy=0A= +CONFIG_CC_ALIGN_FUNCTIONS=3D0=0A= +CONFIG_CC_ALIGN_LABELS=3D0=0A= +CONFIG_CC_ALIGN_LOOPS=3D0=0A= +CONFIG_CC_ALIGN_JUMPS=3D0=0A= +# CONFIG_SLAB is not set=0A= +# CONFIG_TINY_SHMEM is not set=0A= +CONFIG_BASE_SMALL=3D1=0A= +CONFIG_SLOB=3Dy=0A= +=0A= +#=0A= +# Loadable module support=0A= +#=0A= +CONFIG_MODULES=3Dy=0A= +CONFIG_MODULE_UNLOAD=3Dy=0A= +# CONFIG_MODULE_FORCE_UNLOAD is not set=0A= +CONFIG_OBSOLETE_MODPARM=3Dy=0A= +# CONFIG_MODVERSIONS is not set=0A= +# CONFIG_MODULE_SRCVERSION_ALL is not set=0A= +# CONFIG_KMOD is not set=0A= +=0A= +#=0A= +# Block layer=0A= +#=0A= +# CONFIG_LBD is not set=0A= +=0A= +#=0A= +# IO Schedulers=0A= +#=0A= +CONFIG_IOSCHED_NOOP=3Dy=0A= +CONFIG_IOSCHED_AS=3Dy=0A= +CONFIG_IOSCHED_DEADLINE=3Dy=0A= +CONFIG_IOSCHED_CFQ=3Dy=0A= +CONFIG_DEFAULT_AS=3Dy=0A= +# CONFIG_DEFAULT_DEADLINE is not set=0A= +# CONFIG_DEFAULT_CFQ is not set=0A= +# CONFIG_DEFAULT_NOOP is not set=0A= +CONFIG_DEFAULT_IOSCHED=3D"anticipatory"=0A= +=0A= +#=0A= +# Bus options (PCI, PCMCIA, EISA, ISA, TC)=0A= +#=0A= +CONFIG_HW_HAS_PCI=3Dy=0A= +CONFIG_PCI=3Dy=0A= +CONFIG_PCI_LEGACY_PROC=3Dy=0A= +CONFIG_MMU=3Dy=0A= +=0A= +#=0A= +# PCCARD (PCMCIA/CardBus) support=0A= +#=0A= +# CONFIG_PCCARD is not set=0A= +=0A= +#=0A= +# PCI Hotplug Support=0A= +#=0A= +# CONFIG_HOTPLUG_PCI is not set=0A= +=0A= +#=0A= +# Executable file formats=0A= +#=0A= +CONFIG_BINFMT_ELF=3Dy=0A= +# CONFIG_BINFMT_MISC is not set=0A= +CONFIG_TRAD_SIGNALS=3Dy=0A= +=0A= +#=0A= +# Networking=0A= +#=0A= +CONFIG_NET=3Dy=0A= +=0A= +#=0A= +# Networking options=0A= +#=0A= +# CONFIG_NETDEBUG is not set=0A= +CONFIG_PACKET=3Dy=0A= +CONFIG_PACKET_MMAP=3Dy=0A= +CONFIG_UNIX=3Dy=0A= +CONFIG_XFRM=3Dy=0A= +# CONFIG_XFRM_USER is not set=0A= +CONFIG_NET_KEY=3Dy=0A= +CONFIG_INET=3Dy=0A= +CONFIG_IP_MULTICAST=3Dy=0A= +# CONFIG_IP_ADVANCED_ROUTER is not set=0A= +CONFIG_IP_FIB_HASH=3Dy=0A= +CONFIG_IP_PNP=3Dy=0A= +# CONFIG_IP_PNP_DHCP is not set=0A= +# CONFIG_IP_PNP_BOOTP is not set=0A= +# CONFIG_IP_PNP_RARP is not set=0A= +# CONFIG_NET_IPIP is not set=0A= +# CONFIG_NET_IPGRE is not set=0A= +# CONFIG_IP_MROUTE is not set=0A= +# CONFIG_ARPD is not set=0A= +# CONFIG_SYN_COOKIES is not set=0A= +# CONFIG_INET_AH is not set=0A= +# CONFIG_INET_ESP is not set=0A= +# CONFIG_INET_IPCOMP is not set=0A= +# CONFIG_INET_TUNNEL is not set=0A= +# CONFIG_INET_DIAG is not set=0A= +# CONFIG_TCP_CONG_ADVANCED is not set=0A= +CONFIG_TCP_CONG_BIC=3Dy=0A= +=0A= +#=0A= +# IP: Virtual Server Configuration=0A= +#=0A= +CONFIG_IP_VS=3Dm=0A= +# CONFIG_IP_VS_DEBUG is not set=0A= +CONFIG_IP_VS_TAB_BITS=3D12=0A= +=0A= +#=0A= +# IPVS transport protocol load balancing support=0A= +#=0A= +CONFIG_IP_VS_PROTO_TCP=3Dy=0A= +CONFIG_IP_VS_PROTO_UDP=3Dy=0A= +CONFIG_IP_VS_PROTO_ESP=3Dy=0A= +CONFIG_IP_VS_PROTO_AH=3Dy=0A= +=0A= +#=0A= +# IPVS scheduler=0A= +#=0A= +CONFIG_IP_VS_RR=3Dm=0A= +CONFIG_IP_VS_WRR=3Dm=0A= +CONFIG_IP_VS_LC=3Dm=0A= +CONFIG_IP_VS_WLC=3Dm=0A= +CONFIG_IP_VS_LBLC=3Dm=0A= +CONFIG_IP_VS_LBLCR=3Dm=0A= +CONFIG_IP_VS_DH=3Dm=0A= +CONFIG_IP_VS_SH=3Dm=0A= +CONFIG_IP_VS_SED=3Dm=0A= +CONFIG_IP_VS_NQ=3Dm=0A= +=0A= +#=0A= +# IPVS application helper=0A= +#=0A= +CONFIG_IP_VS_FTP=3Dm=0A= +# CONFIG_IPV6 is not set=0A= +CONFIG_NETFILTER=3Dy=0A= +# CONFIG_NETFILTER_DEBUG is not set=0A= +=0A= +#=0A= +# Core Netfilter Configuration=0A= +#=0A= +CONFIG_NETFILTER_NETLINK=3Dm=0A= +CONFIG_NETFILTER_NETLINK_QUEUE=3Dm=0A= +CONFIG_NETFILTER_NETLINK_LOG=3Dm=0A= +CONFIG_NETFILTER_XTABLES=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_CONNMARK=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_MARK=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_NOTRACK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_COMMENT=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNMARK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_DCCP=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_HELPER=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_LENGTH=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_LIMIT=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_MAC=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_MARK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_REALM=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_SCTP=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_STATE=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_STRING=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_TCPMSS=3Dm=0A= +=0A= +#=0A= +# IP: Netfilter Configuration=0A= +#=0A= +CONFIG_IP_NF_CONNTRACK=3Dm=0A= +CONFIG_IP_NF_CT_ACCT=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_MARK=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_EVENTS=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_NETLINK=3Dm=0A= +# CONFIG_IP_NF_CT_PROTO_SCTP is not set=0A= +CONFIG_IP_NF_FTP=3Dm=0A= +CONFIG_IP_NF_IRC=3Dm=0A= +# CONFIG_IP_NF_NETBIOS_NS is not set=0A= +CONFIG_IP_NF_TFTP=3Dm=0A= +CONFIG_IP_NF_AMANDA=3Dm=0A= +CONFIG_IP_NF_PPTP=3Dm=0A= +CONFIG_IP_NF_QUEUE=3Dm=0A= +CONFIG_IP_NF_IPTABLES=3Dm=0A= +CONFIG_IP_NF_MATCH_IPRANGE=3Dm=0A= +CONFIG_IP_NF_MATCH_MULTIPORT=3Dm=0A= +CONFIG_IP_NF_MATCH_TOS=3Dm=0A= +CONFIG_IP_NF_MATCH_RECENT=3Dm=0A= +CONFIG_IP_NF_MATCH_ECN=3Dm=0A= +CONFIG_IP_NF_MATCH_DSCP=3Dm=0A= +CONFIG_IP_NF_MATCH_AH_ESP=3Dm=0A= +CONFIG_IP_NF_MATCH_TTL=3Dm=0A= +CONFIG_IP_NF_MATCH_OWNER=3Dm=0A= +CONFIG_IP_NF_MATCH_ADDRTYPE=3Dm=0A= +CONFIG_IP_NF_MATCH_HASHLIMIT=3Dm=0A= +CONFIG_IP_NF_MATCH_POLICY=3Dm=0A= +CONFIG_IP_NF_FILTER=3Dm=0A= +CONFIG_IP_NF_TARGET_REJECT=3Dm=0A= +CONFIG_IP_NF_TARGET_LOG=3Dm=0A= +CONFIG_IP_NF_TARGET_ULOG=3Dm=0A= +CONFIG_IP_NF_TARGET_TCPMSS=3Dm=0A= +CONFIG_IP_NF_NAT=3Dm=0A= +CONFIG_IP_NF_NAT_NEEDED=3Dy=0A= +CONFIG_IP_NF_TARGET_MASQUERADE=3Dm=0A= +CONFIG_IP_NF_TARGET_REDIRECT=3Dm=0A= +CONFIG_IP_NF_TARGET_NETMAP=3Dm=0A= +CONFIG_IP_NF_TARGET_SAME=3Dm=0A= +CONFIG_IP_NF_NAT_SNMP_BASIC=3Dm=0A= +CONFIG_IP_NF_NAT_IRC=3Dm=0A= +CONFIG_IP_NF_NAT_FTP=3Dm=0A= +CONFIG_IP_NF_NAT_TFTP=3Dm=0A= +CONFIG_IP_NF_NAT_AMANDA=3Dm=0A= +CONFIG_IP_NF_NAT_PPTP=3Dm=0A= +CONFIG_IP_NF_MANGLE=3Dm=0A= +CONFIG_IP_NF_TARGET_TOS=3Dm=0A= +CONFIG_IP_NF_TARGET_ECN=3Dm=0A= +CONFIG_IP_NF_TARGET_DSCP=3Dm=0A= +CONFIG_IP_NF_TARGET_TTL=3Dm=0A= +CONFIG_IP_NF_TARGET_CLUSTERIP=3Dm=0A= +CONFIG_IP_NF_RAW=3Dm=0A= +CONFIG_IP_NF_ARPTABLES=3Dm=0A= +CONFIG_IP_NF_ARPFILTER=3Dm=0A= +CONFIG_IP_NF_ARP_MANGLE=3Dm=0A= +=0A= +#=0A= +# DCCP Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_IP_DCCP is not set=0A= +=0A= +#=0A= +# SCTP Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_IP_SCTP is not set=0A= +=0A= +#=0A= +# TIPC Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_TIPC is not set=0A= +# CONFIG_ATM is not set=0A= +# CONFIG_BRIDGE is not set=0A= +# CONFIG_VLAN_8021Q is not set=0A= +# CONFIG_DECNET is not set=0A= +# CONFIG_LLC2 is not set=0A= +# CONFIG_IPX is not set=0A= +# CONFIG_ATALK is not set=0A= +# CONFIG_X25 is not set=0A= +# CONFIG_LAPB is not set=0A= +# CONFIG_NET_DIVERT is not set=0A= +# CONFIG_ECONET is not set=0A= +# CONFIG_WAN_ROUTER is not set=0A= +=0A= +#=0A= +# QoS and/or fair queueing=0A= +#=0A= +CONFIG_NET_SCHED=3Dy=0A= +# CONFIG_NET_SCH_CLK_JIFFIES is not set=0A= +CONFIG_NET_SCH_CLK_GETTIMEOFDAY=3Dy=0A= +# CONFIG_NET_SCH_CLK_CPU is not set=0A= +=0A= +#=0A= +# Queueing/Scheduling=0A= +#=0A= +CONFIG_NET_SCH_CBQ=3Dm=0A= +CONFIG_NET_SCH_HTB=3Dm=0A= +CONFIG_NET_SCH_HFSC=3Dm=0A= +CONFIG_NET_SCH_PRIO=3Dm=0A= +CONFIG_NET_SCH_RED=3Dm=0A= +CONFIG_NET_SCH_SFQ=3Dm=0A= +CONFIG_NET_SCH_TEQL=3Dm=0A= +CONFIG_NET_SCH_TBF=3Dm=0A= +CONFIG_NET_SCH_GRED=3Dm=0A= +CONFIG_NET_SCH_DSMARK=3Dm=0A= +CONFIG_NET_SCH_NETEM=3Dm=0A= +CONFIG_NET_SCH_INGRESS=3Dm=0A= +=0A= +#=0A= +# Classification=0A= +#=0A= +CONFIG_NET_CLS=3Dy=0A= +CONFIG_NET_CLS_BASIC=3Dm=0A= +CONFIG_NET_CLS_TCINDEX=3Dm=0A= +CONFIG_NET_CLS_ROUTE4=3Dm=0A= +CONFIG_NET_CLS_ROUTE=3Dy=0A= +CONFIG_NET_CLS_FW=3Dm=0A= +CONFIG_NET_CLS_U32=3Dm=0A= +# CONFIG_CLS_U32_PERF is not set=0A= +# CONFIG_CLS_U32_MARK is not set=0A= +CONFIG_NET_CLS_RSVP=3Dm=0A= +CONFIG_NET_CLS_RSVP6=3Dm=0A= +# CONFIG_NET_EMATCH is not set=0A= +# CONFIG_NET_CLS_ACT is not set=0A= +CONFIG_NET_CLS_POLICE=3Dy=0A= +# CONFIG_NET_CLS_IND is not set=0A= +CONFIG_NET_ESTIMATOR=3Dy=0A= +=0A= +#=0A= +# Network testing=0A= +#=0A= +# CONFIG_NET_PKTGEN is not set=0A= +# CONFIG_HAMRADIO is not set=0A= +# CONFIG_IRDA is not set=0A= +# CONFIG_BT is not set=0A= +# CONFIG_IEEE80211 is not set=0A= +=0A= +#=0A= +# Device Drivers=0A= +#=0A= +=0A= +#=0A= +# Generic Driver Options=0A= +#=0A= +CONFIG_STANDALONE=3Dy=0A= +CONFIG_PREVENT_FIRMWARE_BUILD=3Dy=0A= +# CONFIG_FW_LOADER is not set=0A= +=0A= +#=0A= +# Connector - unified userspace <-> kernelspace linker=0A= +#=0A= +# CONFIG_CONNECTOR is not set=0A= +=0A= +#=0A= +# Memory Technology Devices (MTD)=0A= +#=0A= +# CONFIG_MTD is not set=0A= +=0A= +#=0A= +# Parallel port support=0A= +#=0A= +# CONFIG_PARPORT is not set=0A= +=0A= +#=0A= +# Plug and Play support=0A= +#=0A= +=0A= +#=0A= +# Block devices=0A= +#=0A= +# CONFIG_BLK_CPQ_DA is not set=0A= +# CONFIG_BLK_CPQ_CISS_DA is not set=0A= +# CONFIG_BLK_DEV_DAC960 is not set=0A= +# CONFIG_BLK_DEV_UMEM is not set=0A= +# CONFIG_BLK_DEV_COW_COMMON is not set=0A= +# CONFIG_BLK_DEV_LOOP is not set=0A= +# CONFIG_BLK_DEV_NBD is not set=0A= +# CONFIG_BLK_DEV_SX8 is not set=0A= +# CONFIG_BLK_DEV_RAM is not set=0A= +CONFIG_BLK_DEV_RAM_COUNT=3D16=0A= +# CONFIG_CDROM_PKTCDVD is not set=0A= +# CONFIG_ATA_OVER_ETH is not set=0A= +=0A= +#=0A= +# ATA/ATAPI/MFM/RLL support=0A= +#=0A= +# CONFIG_IDE is not set=0A= +=0A= +#=0A= +# SCSI device support=0A= +#=0A= +# CONFIG_RAID_ATTRS is not set=0A= +# CONFIG_SCSI is not set=0A= +=0A= +#=0A= +# Multi-device support (RAID and LVM)=0A= +#=0A= +# CONFIG_MD is not set=0A= +=0A= +#=0A= +# Fusion MPT device support=0A= +#=0A= +# CONFIG_FUSION is not set=0A= +=0A= +#=0A= +# IEEE 1394 (FireWire) support=0A= +#=0A= +# CONFIG_IEEE1394 is not set=0A= +=0A= +#=0A= +# I2O device support=0A= +#=0A= +# CONFIG_I2O is not set=0A= +=0A= +#=0A= +# Network device support=0A= +#=0A= +CONFIG_NETDEVICES=3Dy=0A= +# CONFIG_DUMMY is not set=0A= +# CONFIG_BONDING is not set=0A= +# CONFIG_EQUALIZER is not set=0A= +# CONFIG_TUN is not set=0A= +=0A= +#=0A= +# ARCnet devices=0A= +#=0A= +# CONFIG_ARCNET is not set=0A= +=0A= +#=0A= +# PHY device support=0A= +#=0A= +CONFIG_PHYLIB=3Dm=0A= +=0A= +#=0A= +# MII PHY device drivers=0A= +#=0A= +CONFIG_MARVELL_PHY=3Dm=0A= +CONFIG_DAVICOM_PHY=3Dm=0A= +CONFIG_QSEMI_PHY=3Dm=0A= +CONFIG_LXT_PHY=3Dm=0A= +CONFIG_CICADA_PHY=3Dm=0A= +=0A= +#=0A= +# Ethernet (10 or 100Mbit)=0A= +#=0A= +CONFIG_NET_ETHERNET=3Dy=0A= +CONFIG_MII=3Dy=0A= +CONFIG_IDT_RC32434_ETH=3Dy=0A= +# CONFIG_HAPPYMEAL is not set=0A= +# CONFIG_SUNGEM is not set=0A= +# CONFIG_CASSINI is not set=0A= +# CONFIG_NET_VENDOR_3COM is not set=0A= +# CONFIG_DM9000 is not set=0A= +=0A= +#=0A= +# Tulip family network device support=0A= +#=0A= +# CONFIG_NET_TULIP is not set=0A= +# CONFIG_HP100 is not set=0A= +CONFIG_NET_PCI=3Dy=0A= +# CONFIG_PCNET32 is not set=0A= +# CONFIG_AMD8111_ETH is not set=0A= +# CONFIG_ADAPTEC_STARFIRE is not set=0A= +# CONFIG_B44 is not set=0A= +# CONFIG_FORCEDETH is not set=0A= +# CONFIG_DGRS is not set=0A= +# CONFIG_EEPRO100 is not set=0A= +CONFIG_E100=3Dy=0A= +# CONFIG_FEALNX is not set=0A= +# CONFIG_NATSEMI is not set=0A= +# CONFIG_NE2K_PCI is not set=0A= +# CONFIG_8139CP is not set=0A= +# CONFIG_8139TOO is not set=0A= +# CONFIG_SIS900 is not set=0A= +# CONFIG_EPIC100 is not set=0A= +# CONFIG_SUNDANCE is not set=0A= +# CONFIG_TLAN is not set=0A= +# CONFIG_VIA_RHINE is not set=0A= +# CONFIG_LAN_SAA9730 is not set=0A= +=0A= +#=0A= +# Ethernet (1000 Mbit)=0A= +#=0A= +# CONFIG_ACENIC is not set=0A= +# CONFIG_DL2K is not set=0A= +# CONFIG_E1000 is not set=0A= +# CONFIG_NS83820 is not set=0A= +# CONFIG_HAMACHI is not set=0A= +# CONFIG_YELLOWFIN is not set=0A= +# CONFIG_R8169 is not set=0A= +# CONFIG_SIS190 is not set=0A= +# CONFIG_SKGE is not set=0A= +# CONFIG_SKY2 is not set=0A= +# CONFIG_SK98LIN is not set=0A= +# CONFIG_VIA_VELOCITY is not set=0A= +# CONFIG_TIGON3 is not set=0A= +# CONFIG_BNX2 is not set=0A= +=0A= +#=0A= +# Ethernet (10000 Mbit)=0A= +#=0A= +# CONFIG_CHELSIO_T1 is not set=0A= +# CONFIG_IXGB is not set=0A= +# CONFIG_S2IO is not set=0A= +=0A= +#=0A= +# Token Ring devices=0A= +#=0A= +# CONFIG_TR is not set=0A= +=0A= +#=0A= +# Wireless LAN (non-hamradio)=0A= +#=0A= +# CONFIG_NET_RADIO is not set=0A= +=0A= +#=0A= +# Wan interfaces=0A= +#=0A= +# CONFIG_WAN is not set=0A= +# CONFIG_FDDI is not set=0A= +# CONFIG_HIPPI is not set=0A= +# CONFIG_PPP is not set=0A= +# CONFIG_SLIP is not set=0A= +# CONFIG_SHAPER is not set=0A= +# CONFIG_NETCONSOLE is not set=0A= +# CONFIG_NETPOLL is not set=0A= +# CONFIG_NET_POLL_CONTROLLER is not set=0A= +=0A= +#=0A= +# ISDN subsystem=0A= +#=0A= +# CONFIG_ISDN is not set=0A= +=0A= +#=0A= +# Telephony Support=0A= +#=0A= +# CONFIG_PHONE is not set=0A= +=0A= +#=0A= +# Input device support=0A= +#=0A= +CONFIG_INPUT=3Dy=0A= +=0A= +#=0A= +# Userland interfaces=0A= +#=0A= +# CONFIG_INPUT_MOUSEDEV is not set=0A= +# CONFIG_INPUT_JOYDEV is not set=0A= +# CONFIG_INPUT_TSDEV is not set=0A= +# CONFIG_INPUT_EVDEV is not set=0A= +# CONFIG_INPUT_EVBUG is not set=0A= +=0A= +#=0A= +# Input Device Drivers=0A= +#=0A= +# CONFIG_INPUT_KEYBOARD is not set=0A= +# CONFIG_INPUT_MOUSE is not set=0A= +# CONFIG_INPUT_JOYSTICK is not set=0A= +# CONFIG_INPUT_TOUCHSCREEN is not set=0A= +# CONFIG_INPUT_MISC is not set=0A= +=0A= +#=0A= +# Hardware I/O ports=0A= +#=0A= +# CONFIG_SERIO is not set=0A= +# CONFIG_GAMEPORT is not set=0A= +=0A= +#=0A= +# Character devices=0A= +#=0A= +CONFIG_VT=3Dy=0A= +CONFIG_VT_CONSOLE=3Dy=0A= +CONFIG_HW_CONSOLE=3Dy=0A= +# CONFIG_SERIAL_NONSTANDARD is not set=0A= +=0A= +#=0A= +# Serial drivers=0A= +#=0A= +CONFIG_SERIAL_8250=3Dy=0A= +CONFIG_SERIAL_8250_CONSOLE=3Dy=0A= +CONFIG_SERIAL_8250_NR_UARTS=3D4=0A= +CONFIG_SERIAL_8250_RUNTIME_UARTS=3D4=0A= +# CONFIG_SERIAL_8250_EXTENDED is not set=0A= +=0A= +#=0A= +# Non-8250 serial port support=0A= +#=0A= +CONFIG_SERIAL_CORE=3Dy=0A= +CONFIG_SERIAL_CORE_CONSOLE=3Dy=0A= +# CONFIG_SERIAL_JSM is not set=0A= +CONFIG_UNIX98_PTYS=3Dy=0A= +CONFIG_LEGACY_PTYS=3Dy=0A= +CONFIG_LEGACY_PTY_COUNT=3D256=0A= +=0A= +#=0A= +# IPMI=0A= +#=0A= +# CONFIG_IPMI_HANDLER is not set=0A= +=0A= +#=0A= +# Watchdog Cards=0A= +#=0A= +# CONFIG_WATCHDOG is not set=0A= +# CONFIG_RTC is not set=0A= +# CONFIG_GEN_RTC is not set=0A= +# CONFIG_DTLK is not set=0A= +# CONFIG_R3964 is not set=0A= +# CONFIG_APPLICOM is not set=0A= +=0A= +#=0A= +# Ftape, the floppy tape device driver=0A= +#=0A= +# CONFIG_DRM is not set=0A= +# CONFIG_RAW_DRIVER is not set=0A= +=0A= +#=0A= +# TPM devices=0A= +#=0A= +# CONFIG_TCG_TPM is not set=0A= +# CONFIG_TELCLOCK is not set=0A= +=0A= +#=0A= +# I2C support=0A= +#=0A= +CONFIG_I2C=3Dy=0A= +CONFIG_I2C_CHARDEV=3Dy=0A= +=0A= +#=0A= +# I2C Algorithms=0A= +#=0A= +# CONFIG_I2C_ALGOBIT is not set=0A= +# CONFIG_I2C_ALGOPCF is not set=0A= +# CONFIG_I2C_ALGOPCA is not set=0A= +=0A= +#=0A= +# I2C Hardware Bus support=0A= +#=0A= +# CONFIG_I2C_ALI1535 is not set=0A= +# CONFIG_I2C_ALI1563 is not set=0A= +# CONFIG_I2C_ALI15X3 is not set=0A= +# CONFIG_I2C_AMD756 is not set=0A= +# CONFIG_I2C_AMD8111 is not set=0A= +# CONFIG_I2C_I801 is not set=0A= +# CONFIG_I2C_I810 is not set=0A= +# CONFIG_I2C_PIIX4 is not set=0A= +# CONFIG_I2C_NFORCE2 is not set=0A= +# CONFIG_I2C_PARPORT_LIGHT is not set=0A= +# CONFIG_I2C_PROSAVAGE is not set=0A= +# CONFIG_I2C_SAVAGE4 is not set=0A= +# CONFIG_SCx200_ACB is not set=0A= +# CONFIG_I2C_SIS5595 is not set=0A= +# CONFIG_I2C_SIS630 is not set=0A= +# CONFIG_I2C_SIS96X is not set=0A= +# CONFIG_I2C_STUB is not set=0A= +# CONFIG_I2C_VIA is not set=0A= +# CONFIG_I2C_VIAPRO is not set=0A= +# CONFIG_I2C_VOODOO3 is not set=0A= +# CONFIG_I2C_PCA_ISA is not set=0A= +CONFIG_I2C_RC32434=3Dy=0A= +=0A= +#=0A= +# Miscellaneous I2C Chip support=0A= +#=0A= +# CONFIG_SENSORS_DS1337 is not set=0A= +# CONFIG_SENSORS_DS1374 is not set=0A= +# CONFIG_SENSORS_EEPROM is not set=0A= +# CONFIG_SENSORS_PCF8574 is not set=0A= +# CONFIG_SENSORS_PCA9539 is not set=0A= +# CONFIG_SENSORS_PCF8591 is not set=0A= +# CONFIG_SENSORS_RTC8564 is not set=0A= +# CONFIG_SENSORS_MAX6875 is not set=0A= +# CONFIG_RTC_X1205_I2C is not set=0A= +# CONFIG_I2C_DEBUG_CORE is not set=0A= +# CONFIG_I2C_DEBUG_ALGO is not set=0A= +# CONFIG_I2C_DEBUG_BUS is not set=0A= +# CONFIG_I2C_DEBUG_CHIP is not set=0A= +=0A= +#=0A= +# SPI support=0A= +#=0A= +# CONFIG_SPI is not set=0A= +# CONFIG_SPI_MASTER is not set=0A= +=0A= +#=0A= +# Dallas's 1-wire bus=0A= +#=0A= +# CONFIG_W1 is not set=0A= +=0A= +#=0A= +# Hardware Monitoring support=0A= +#=0A= +# CONFIG_HWMON is not set=0A= +# CONFIG_HWMON_VID is not set=0A= +=0A= +#=0A= +# Misc devices=0A= +#=0A= +=0A= +#=0A= +# Multimedia Capabilities Port drivers=0A= +#=0A= +=0A= +#=0A= +# Multimedia devices=0A= +#=0A= +# CONFIG_VIDEO_DEV is not set=0A= +=0A= +#=0A= +# Digital Video Broadcasting Devices=0A= +#=0A= +# CONFIG_DVB is not set=0A= +=0A= +#=0A= +# Graphics support=0A= +#=0A= +# CONFIG_FB is not set=0A= +=0A= +#=0A= +# Console display driver support=0A= +#=0A= +# CONFIG_VGA_CONSOLE is not set=0A= +CONFIG_DUMMY_CONSOLE=3Dy=0A= +=0A= +#=0A= +# Sound=0A= +#=0A= +# CONFIG_SOUND is not set=0A= +=0A= +#=0A= +# USB support=0A= +#=0A= +CONFIG_USB_ARCH_HAS_HCD=3Dy=0A= +CONFIG_USB_ARCH_HAS_OHCI=3Dy=0A= +# CONFIG_USB is not set=0A= +=0A= +#=0A= +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'=0A= +#=0A= +=0A= +#=0A= +# USB Gadget Support=0A= +#=0A= +# CONFIG_USB_GADGET is not set=0A= +=0A= +#=0A= +# MMC/SD Card support=0A= +#=0A= +# CONFIG_MMC is not set=0A= +=0A= +#=0A= +# InfiniBand support=0A= +#=0A= +# CONFIG_INFINIBAND is not set=0A= +=0A= +#=0A= +# SN Devices=0A= +#=0A= +=0A= +#=0A= +# EDAC - error detection and reporting (RAS)=0A= +#=0A= +=0A= +#=0A= +# File systems=0A= +#=0A= +CONFIG_EXT2_FS=3Dy=0A= +# CONFIG_EXT2_FS_XATTR is not set=0A= +# CONFIG_EXT2_FS_XIP is not set=0A= +# CONFIG_EXT3_FS is not set=0A= +# CONFIG_REISERFS_FS is not set=0A= +# CONFIG_JFS_FS is not set=0A= +# CONFIG_FS_POSIX_ACL is not set=0A= +# CONFIG_XFS_FS is not set=0A= +# CONFIG_OCFS2_FS is not set=0A= +# CONFIG_MINIX_FS is not set=0A= +# CONFIG_ROMFS_FS is not set=0A= +# CONFIG_INOTIFY is not set=0A= +# CONFIG_QUOTA is not set=0A= +# CONFIG_DNOTIFY is not set=0A= +# CONFIG_AUTOFS_FS is not set=0A= +# CONFIG_AUTOFS4_FS is not set=0A= +# CONFIG_FUSE_FS is not set=0A= +=0A= +#=0A= +# CD-ROM/DVD Filesystems=0A= +#=0A= +# CONFIG_ISO9660_FS is not set=0A= +# CONFIG_UDF_FS is not set=0A= +=0A= +#=0A= +# DOS/FAT/NT Filesystems=0A= +#=0A= +# CONFIG_MSDOS_FS is not set=0A= +# CONFIG_VFAT_FS is not set=0A= +# CONFIG_NTFS_FS is not set=0A= +=0A= +#=0A= +# Pseudo filesystems=0A= +#=0A= +CONFIG_PROC_FS=3Dy=0A= +CONFIG_PROC_KCORE=3Dy=0A= +CONFIG_SYSFS=3Dy=0A= +# CONFIG_TMPFS is not set=0A= +# CONFIG_HUGETLB_PAGE is not set=0A= +CONFIG_RAMFS=3Dy=0A= +# CONFIG_RELAYFS_FS is not set=0A= +# CONFIG_CONFIGFS_FS is not set=0A= +=0A= +#=0A= +# Miscellaneous filesystems=0A= +#=0A= +# CONFIG_ADFS_FS is not set=0A= +# CONFIG_AFFS_FS is not set=0A= +# CONFIG_HFS_FS is not set=0A= +# CONFIG_HFSPLUS_FS is not set=0A= +# CONFIG_BEFS_FS is not set=0A= +# CONFIG_BFS_FS is not set=0A= +# CONFIG_EFS_FS is not set=0A= +# CONFIG_CRAMFS is not set=0A= +# CONFIG_VXFS_FS is not set=0A= +# CONFIG_HPFS_FS is not set=0A= +# CONFIG_QNX4FS_FS is not set=0A= +# CONFIG_SYSV_FS is not set=0A= +# CONFIG_UFS_FS is not set=0A= +=0A= +#=0A= +# Network File Systems=0A= +#=0A= +# CONFIG_NFS_FS is not set=0A= +# CONFIG_NFSD is not set=0A= +# CONFIG_SMB_FS is not set=0A= +# CONFIG_CIFS is not set=0A= +# CONFIG_NCP_FS is not set=0A= +# CONFIG_CODA_FS is not set=0A= +# CONFIG_AFS_FS is not set=0A= +# CONFIG_9P_FS is not set=0A= +=0A= +#=0A= +# Partition Types=0A= +#=0A= +# CONFIG_PARTITION_ADVANCED is not set=0A= +CONFIG_MSDOS_PARTITION=3Dy=0A= +=0A= +#=0A= +# Native Language Support=0A= +#=0A= +# CONFIG_NLS is not set=0A= +=0A= +#=0A= +# Profiling support=0A= +#=0A= +# CONFIG_PROFILING is not set=0A= +=0A= +#=0A= +# Kernel hacking=0A= +#=0A= +# CONFIG_PRINTK_TIME is not set=0A= +# CONFIG_MAGIC_SYSRQ is not set=0A= +# CONFIG_DEBUG_KERNEL is not set=0A= +CONFIG_LOG_BUF_SHIFT=3D14=0A= +CONFIG_CROSSCOMPILE=3Dy=0A= +CONFIG_CMDLINE=3D""=0A= +=0A= +#=0A= +# Security options=0A= +#=0A= +# CONFIG_KEYS is not set=0A= +# CONFIG_SECURITY is not set=0A= +=0A= +#=0A= +# Cryptographic options=0A= +#=0A= +# CONFIG_CRYPTO is not set=0A= +=0A= +#=0A= +# Hardware crypto devices=0A= +#=0A= +=0A= +#=0A= +# Library routines=0A= +#=0A= +CONFIG_CRC_CCITT=3Dy=0A= +CONFIG_CRC16=3Dm=0A= +CONFIG_CRC32=3Dy=0A= +# CONFIG_LIBCRC32C is not set=0A= +CONFIG_TEXTSEARCH=3Dy=0A= +CONFIG_TEXTSEARCH_KMP=3Dm=0A= +CONFIG_TEXTSEARCH_BM=3Dm=0A= +CONFIG_TEXTSEARCH_FSM=3Dm=0A= diff -uNr linux-2.6.16-rc5/arch/mips/configs/rc32438_defconfig = idtlinux/arch/mips/configs/rc32438_defconfig=0A= --- linux-2.6.16-rc5/arch/mips/configs/rc32438_defconfig 1969-12-31 = 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/configs/rc32438_defconfig 2006-03-09 = 16:25:45.000000000 -0800=0A= @@ -0,0 +1,982 @@=0A= +#=0A= +# Automatically generated make config: don't edit=0A= +# Linux kernel version: 2.6.16-rc5=0A= +# Thu Mar 9 10:57:39 2006=0A= +#=0A= +CONFIG_MIPS=3Dy=0A= +=0A= +#=0A= +# Machine selection=0A= +#=0A= +# CONFIG_MIPS_MTX1 is not set=0A= +# CONFIG_MIPS_BOSPORUS is not set=0A= +# CONFIG_MIPS_PB1000 is not set=0A= +# CONFIG_MIPS_PB1100 is not set=0A= +# CONFIG_MIPS_PB1500 is not set=0A= +# CONFIG_MIPS_PB1550 is not set=0A= +# CONFIG_MIPS_PB1200 is not set=0A= +# CONFIG_MIPS_DB1000 is not set=0A= +# CONFIG_MIPS_DB1100 is not set=0A= +# CONFIG_MIPS_DB1500 is not set=0A= +# CONFIG_MIPS_DB1550 is not set=0A= +# CONFIG_MIPS_DB1200 is not set=0A= +# CONFIG_MIPS_MIRAGE is not set=0A= +# CONFIG_MIPS_COBALT is not set=0A= +# CONFIG_MACH_DECSTATION is not set=0A= +# CONFIG_MIPS_EV64120 is not set=0A= +# CONFIG_MIPS_EV96100 is not set=0A= +# CONFIG_MIPS_IVR is not set=0A= +CONFIG_IDT_BOARDS=3Dy=0A= +# CONFIG_MIPS_ITE8172 is not set=0A= +# CONFIG_MACH_JAZZ is not set=0A= +# CONFIG_LASAT is not set=0A= +# CONFIG_MIPS_ATLAS is not set=0A= +# CONFIG_MIPS_MALTA is not set=0A= +# CONFIG_MIPS_SEAD is not set=0A= +# CONFIG_MIPS_SIM is not set=0A= +# CONFIG_MOMENCO_JAGUAR_ATX is not set=0A= +# CONFIG_MOMENCO_OCELOT is not set=0A= +# CONFIG_MOMENCO_OCELOT_3 is not set=0A= +# CONFIG_MOMENCO_OCELOT_C is not set=0A= +# CONFIG_MOMENCO_OCELOT_G is not set=0A= +# CONFIG_MIPS_XXS1500 is not set=0A= +# CONFIG_PNX8550_V2PCI is not set=0A= +# CONFIG_PNX8550_JBS is not set=0A= +# CONFIG_DDB5074 is not set=0A= +# CONFIG_DDB5476 is not set=0A= +# CONFIG_DDB5477 is not set=0A= +# CONFIG_MACH_VR41XX is not set=0A= +# CONFIG_PMC_YOSEMITE is not set=0A= +# CONFIG_QEMU is not set=0A= +# CONFIG_SGI_IP22 is not set=0A= +# CONFIG_SGI_IP27 is not set=0A= +# CONFIG_SGI_IP32 is not set=0A= +# CONFIG_SIBYTE_BIGSUR is not set=0A= +# CONFIG_SIBYTE_SWARM is not set=0A= +# CONFIG_SIBYTE_SENTOSA is not set=0A= +# CONFIG_SIBYTE_RHONE is not set=0A= +# CONFIG_SIBYTE_CARMEL is not set=0A= +# CONFIG_SIBYTE_PTSWARM is not set=0A= +# CONFIG_SIBYTE_LITTLESUR is not set=0A= +# CONFIG_SIBYTE_CRHINE is not set=0A= +# CONFIG_SIBYTE_CRHONE is not set=0A= +# CONFIG_SNI_RM200_PCI is not set=0A= +# CONFIG_TOSHIBA_JMR3927 is not set=0A= +# CONFIG_TOSHIBA_RBTX4927 is not set=0A= +# CONFIG_TOSHIBA_RBTX4938 is not set=0A= +CONFIG_IDT_EB438=3Dy=0A= +# CONFIG_RC32438_REVISION_ZA is not set=0A= +# CONFIG_IDT_EB434 is not set=0A= +# CONFIG_IDT_EB365 is not set=0A= +# CONFIG_IDT_EB355 is not set=0A= +# CONFIG_IDT_S334 is not set=0A= +CONFIG_IDT_BOARD_FREQ=3D150000000=0A= +CONFIG_IDT_ZIMAGE_ADDR=3D0x91000000=0A= +# CONFIG_IDT_BOOT_NVRAM is not set=0A= +CONFIG_RWSEM_GENERIC_SPINLOCK=3Dy=0A= +CONFIG_GENERIC_CALIBRATE_DELAY=3Dy=0A= +CONFIG_DMA_NONCOHERENT=3Dy=0A= +CONFIG_DMA_NEED_PCI_MAP_STATE=3Dy=0A= +# CONFIG_CPU_BIG_ENDIAN is not set=0A= +CONFIG_CPU_LITTLE_ENDIAN=3Dy=0A= +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=3Dy=0A= +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=3Dy=0A= +CONFIG_IRQ_CPU=3Dy=0A= +CONFIG_SWAP_IO_SPACE=3Dy=0A= +CONFIG_BOOT_ELF32=3Dy=0A= +CONFIG_MIPS_L1_CACHE_SHIFT=3D5=0A= +=0A= +#=0A= +# CPU selection=0A= +#=0A= +CONFIG_CPU_MIPS32_R1=3Dy=0A= +# CONFIG_CPU_MIPS32_R2 is not set=0A= +# CONFIG_CPU_MIPS64_R1 is not set=0A= +# CONFIG_CPU_MIPS64_R2 is not set=0A= +# CONFIG_CPU_R3000 is not set=0A= +# CONFIG_CPU_TX39XX is not set=0A= +# CONFIG_CPU_VR41XX is not set=0A= +# CONFIG_CPU_R4300 is not set=0A= +# CONFIG_CPU_R4X00 is not set=0A= +# CONFIG_CPU_TX49XX is not set=0A= +# CONFIG_CPU_R5000 is not set=0A= +# CONFIG_CPU_R5432 is not set=0A= +# CONFIG_CPU_R6000 is not set=0A= +# CONFIG_CPU_NEVADA is not set=0A= +# CONFIG_CPU_R8000 is not set=0A= +# CONFIG_CPU_R10000 is not set=0A= +# CONFIG_CPU_RM7000 is not set=0A= +# CONFIG_CPU_RM9000 is not set=0A= +# CONFIG_CPU_SB1 is not set=0A= +CONFIG_SYS_HAS_CPU_MIPS32_R1=3Dy=0A= +CONFIG_CPU_MIPS32=3Dy=0A= +CONFIG_CPU_MIPSR1=3Dy=0A= +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=3Dy=0A= +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=3Dy=0A= +=0A= +#=0A= +# Kernel type=0A= +#=0A= +CONFIG_32BIT=3Dy=0A= +# CONFIG_64BIT is not set=0A= +CONFIG_PAGE_SIZE_4KB=3Dy=0A= +# CONFIG_PAGE_SIZE_8KB is not set=0A= +# CONFIG_PAGE_SIZE_16KB is not set=0A= +# CONFIG_PAGE_SIZE_64KB is not set=0A= +CONFIG_CPU_HAS_PREFETCH=3Dy=0A= +# CONFIG_MIPS_MT is not set=0A= +# CONFIG_64BIT_PHYS_ADDR is not set=0A= +CONFIG_CPU_ADVANCED=3Dy=0A= +CONFIG_CPU_HAS_LLSC=3Dy=0A= +# CONFIG_CPU_HAS_WB is not set=0A= +CONFIG_CPU_HAS_SYNC=3Dy=0A= +CONFIG_GENERIC_HARDIRQS=3Dy=0A= +CONFIG_GENERIC_IRQ_PROBE=3Dy=0A= +CONFIG_ARCH_FLATMEM_ENABLE=3Dy=0A= +CONFIG_SELECT_MEMORY_MODEL=3Dy=0A= +CONFIG_FLATMEM_MANUAL=3Dy=0A= +# CONFIG_DISCONTIGMEM_MANUAL is not set=0A= +# CONFIG_SPARSEMEM_MANUAL is not set=0A= +CONFIG_FLATMEM=3Dy=0A= +CONFIG_FLAT_NODE_MEM_MAP=3Dy=0A= +# CONFIG_SPARSEMEM_STATIC is not set=0A= +CONFIG_SPLIT_PTLOCK_CPUS=3D4=0A= +CONFIG_PREEMPT_NONE=3Dy=0A= +# CONFIG_PREEMPT_VOLUNTARY is not set=0A= +# CONFIG_PREEMPT is not set=0A= +=0A= +#=0A= +# Code maturity level options=0A= +#=0A= +CONFIG_EXPERIMENTAL=3Dy=0A= +CONFIG_BROKEN_ON_SMP=3Dy=0A= +CONFIG_INIT_ENV_ARG_LIMIT=3D32=0A= +=0A= +#=0A= +# General setup=0A= +#=0A= +CONFIG_LOCALVERSION=3D""=0A= +CONFIG_LOCALVERSION_AUTO=3Dy=0A= +# CONFIG_SWAP is not set=0A= +CONFIG_SYSVIPC=3Dy=0A= +# CONFIG_POSIX_MQUEUE is not set=0A= +# CONFIG_BSD_PROCESS_ACCT is not set=0A= +CONFIG_SYSCTL=3Dy=0A= +# CONFIG_AUDIT is not set=0A= +CONFIG_IKCONFIG=3Dy=0A= +# CONFIG_IKCONFIG_PROC is not set=0A= +CONFIG_INITRAMFS_SOURCE=3D""=0A= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set=0A= +CONFIG_EMBEDDED=3Dy=0A= +# CONFIG_KALLSYMS is not set=0A= +# CONFIG_HOTPLUG is not set=0A= +CONFIG_PRINTK=3Dy=0A= +CONFIG_BUG=3Dy=0A= +CONFIG_ELF_CORE=3Dy=0A= +# CONFIG_BASE_FULL is not set=0A= +# CONFIG_FUTEX is not set=0A= +# CONFIG_EPOLL is not set=0A= +CONFIG_SHMEM=3Dy=0A= +CONFIG_CC_ALIGN_FUNCTIONS=3D0=0A= +CONFIG_CC_ALIGN_LABELS=3D0=0A= +CONFIG_CC_ALIGN_LOOPS=3D0=0A= +CONFIG_CC_ALIGN_JUMPS=3D0=0A= +# CONFIG_SLAB is not set=0A= +# CONFIG_TINY_SHMEM is not set=0A= +CONFIG_BASE_SMALL=3D1=0A= +CONFIG_SLOB=3Dy=0A= +=0A= +#=0A= +# Loadable module support=0A= +#=0A= +CONFIG_MODULES=3Dy=0A= +CONFIG_MODULE_UNLOAD=3Dy=0A= +# CONFIG_MODULE_FORCE_UNLOAD is not set=0A= +CONFIG_OBSOLETE_MODPARM=3Dy=0A= +# CONFIG_MODVERSIONS is not set=0A= +# CONFIG_MODULE_SRCVERSION_ALL is not set=0A= +# CONFIG_KMOD is not set=0A= +=0A= +#=0A= +# Block layer=0A= +#=0A= +# CONFIG_LBD is not set=0A= +=0A= +#=0A= +# IO Schedulers=0A= +#=0A= +CONFIG_IOSCHED_NOOP=3Dy=0A= +CONFIG_IOSCHED_AS=3Dy=0A= +CONFIG_IOSCHED_DEADLINE=3Dy=0A= +CONFIG_IOSCHED_CFQ=3Dy=0A= +CONFIG_DEFAULT_AS=3Dy=0A= +# CONFIG_DEFAULT_DEADLINE is not set=0A= +# CONFIG_DEFAULT_CFQ is not set=0A= +# CONFIG_DEFAULT_NOOP is not set=0A= +CONFIG_DEFAULT_IOSCHED=3D"anticipatory"=0A= +=0A= +#=0A= +# Bus options (PCI, PCMCIA, EISA, ISA, TC)=0A= +#=0A= +CONFIG_HW_HAS_PCI=3Dy=0A= +CONFIG_PCI=3Dy=0A= +CONFIG_PCI_LEGACY_PROC=3Dy=0A= +CONFIG_MMU=3Dy=0A= +=0A= +#=0A= +# PCCARD (PCMCIA/CardBus) support=0A= +#=0A= +# CONFIG_PCCARD is not set=0A= +=0A= +#=0A= +# PCI Hotplug Support=0A= +#=0A= +# CONFIG_HOTPLUG_PCI is not set=0A= +=0A= +#=0A= +# Executable file formats=0A= +#=0A= +CONFIG_BINFMT_ELF=3Dy=0A= +# CONFIG_BINFMT_MISC is not set=0A= +CONFIG_TRAD_SIGNALS=3Dy=0A= +=0A= +#=0A= +# Networking=0A= +#=0A= +CONFIG_NET=3Dy=0A= +=0A= +#=0A= +# Networking options=0A= +#=0A= +# CONFIG_NETDEBUG is not set=0A= +CONFIG_PACKET=3Dy=0A= +CONFIG_PACKET_MMAP=3Dy=0A= +CONFIG_UNIX=3Dy=0A= +CONFIG_XFRM=3Dy=0A= +# CONFIG_XFRM_USER is not set=0A= +CONFIG_NET_KEY=3Dy=0A= +CONFIG_INET=3Dy=0A= +CONFIG_IP_MULTICAST=3Dy=0A= +# CONFIG_IP_ADVANCED_ROUTER is not set=0A= +CONFIG_IP_FIB_HASH=3Dy=0A= +CONFIG_IP_PNP=3Dy=0A= +# CONFIG_IP_PNP_DHCP is not set=0A= +# CONFIG_IP_PNP_BOOTP is not set=0A= +# CONFIG_IP_PNP_RARP is not set=0A= +# CONFIG_NET_IPIP is not set=0A= +# CONFIG_NET_IPGRE is not set=0A= +# CONFIG_IP_MROUTE is not set=0A= +# CONFIG_ARPD is not set=0A= +# CONFIG_SYN_COOKIES is not set=0A= +# CONFIG_INET_AH is not set=0A= +# CONFIG_INET_ESP is not set=0A= +# CONFIG_INET_IPCOMP is not set=0A= +# CONFIG_INET_TUNNEL is not set=0A= +# CONFIG_INET_DIAG is not set=0A= +# CONFIG_TCP_CONG_ADVANCED is not set=0A= +CONFIG_TCP_CONG_BIC=3Dy=0A= +=0A= +#=0A= +# IP: Virtual Server Configuration=0A= +#=0A= +CONFIG_IP_VS=3Dm=0A= +# CONFIG_IP_VS_DEBUG is not set=0A= +CONFIG_IP_VS_TAB_BITS=3D12=0A= +=0A= +#=0A= +# IPVS transport protocol load balancing support=0A= +#=0A= +CONFIG_IP_VS_PROTO_TCP=3Dy=0A= +CONFIG_IP_VS_PROTO_UDP=3Dy=0A= +CONFIG_IP_VS_PROTO_ESP=3Dy=0A= +CONFIG_IP_VS_PROTO_AH=3Dy=0A= +=0A= +#=0A= +# IPVS scheduler=0A= +#=0A= +CONFIG_IP_VS_RR=3Dm=0A= +CONFIG_IP_VS_WRR=3Dm=0A= +CONFIG_IP_VS_LC=3Dm=0A= +CONFIG_IP_VS_WLC=3Dm=0A= +CONFIG_IP_VS_LBLC=3Dm=0A= +CONFIG_IP_VS_LBLCR=3Dm=0A= +CONFIG_IP_VS_DH=3Dm=0A= +CONFIG_IP_VS_SH=3Dm=0A= +CONFIG_IP_VS_SED=3Dm=0A= +CONFIG_IP_VS_NQ=3Dm=0A= +=0A= +#=0A= +# IPVS application helper=0A= +#=0A= +CONFIG_IP_VS_FTP=3Dm=0A= +# CONFIG_IPV6 is not set=0A= +CONFIG_NETFILTER=3Dy=0A= +# CONFIG_NETFILTER_DEBUG is not set=0A= +=0A= +#=0A= +# Core Netfilter Configuration=0A= +#=0A= +CONFIG_NETFILTER_NETLINK=3Dm=0A= +CONFIG_NETFILTER_NETLINK_QUEUE=3Dm=0A= +CONFIG_NETFILTER_NETLINK_LOG=3Dm=0A= +CONFIG_NETFILTER_XTABLES=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_CONNMARK=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_MARK=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=3Dm=0A= +CONFIG_NETFILTER_XT_TARGET_NOTRACK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_COMMENT=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNMARK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_DCCP=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_HELPER=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_LENGTH=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_LIMIT=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_MAC=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_MARK=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_REALM=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_SCTP=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_STATE=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_STRING=3Dm=0A= +CONFIG_NETFILTER_XT_MATCH_TCPMSS=3Dm=0A= +=0A= +#=0A= +# IP: Netfilter Configuration=0A= +#=0A= +CONFIG_IP_NF_CONNTRACK=3Dm=0A= +CONFIG_IP_NF_CT_ACCT=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_MARK=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_EVENTS=3Dy=0A= +CONFIG_IP_NF_CONNTRACK_NETLINK=3Dm=0A= +# CONFIG_IP_NF_CT_PROTO_SCTP is not set=0A= +CONFIG_IP_NF_FTP=3Dm=0A= +CONFIG_IP_NF_IRC=3Dm=0A= +# CONFIG_IP_NF_NETBIOS_NS is not set=0A= +CONFIG_IP_NF_TFTP=3Dm=0A= +CONFIG_IP_NF_AMANDA=3Dm=0A= +CONFIG_IP_NF_PPTP=3Dm=0A= +CONFIG_IP_NF_QUEUE=3Dm=0A= +CONFIG_IP_NF_IPTABLES=3Dm=0A= +CONFIG_IP_NF_MATCH_IPRANGE=3Dm=0A= +CONFIG_IP_NF_MATCH_MULTIPORT=3Dm=0A= +CONFIG_IP_NF_MATCH_TOS=3Dm=0A= +CONFIG_IP_NF_MATCH_RECENT=3Dm=0A= +CONFIG_IP_NF_MATCH_ECN=3Dm=0A= +CONFIG_IP_NF_MATCH_DSCP=3Dm=0A= +CONFIG_IP_NF_MATCH_AH_ESP=3Dm=0A= +CONFIG_IP_NF_MATCH_TTL=3Dm=0A= +CONFIG_IP_NF_MATCH_OWNER=3Dm=0A= +CONFIG_IP_NF_MATCH_ADDRTYPE=3Dm=0A= +CONFIG_IP_NF_MATCH_HASHLIMIT=3Dm=0A= +CONFIG_IP_NF_MATCH_POLICY=3Dm=0A= +CONFIG_IP_NF_FILTER=3Dm=0A= +CONFIG_IP_NF_TARGET_REJECT=3Dm=0A= +CONFIG_IP_NF_TARGET_LOG=3Dm=0A= +CONFIG_IP_NF_TARGET_ULOG=3Dm=0A= +CONFIG_IP_NF_TARGET_TCPMSS=3Dm=0A= +CONFIG_IP_NF_NAT=3Dm=0A= +CONFIG_IP_NF_NAT_NEEDED=3Dy=0A= +CONFIG_IP_NF_TARGET_MASQUERADE=3Dm=0A= +CONFIG_IP_NF_TARGET_REDIRECT=3Dm=0A= +CONFIG_IP_NF_TARGET_NETMAP=3Dm=0A= +CONFIG_IP_NF_TARGET_SAME=3Dm=0A= +CONFIG_IP_NF_NAT_SNMP_BASIC=3Dm=0A= +CONFIG_IP_NF_NAT_IRC=3Dm=0A= +CONFIG_IP_NF_NAT_FTP=3Dm=0A= +CONFIG_IP_NF_NAT_TFTP=3Dm=0A= +CONFIG_IP_NF_NAT_AMANDA=3Dm=0A= +CONFIG_IP_NF_NAT_PPTP=3Dm=0A= +CONFIG_IP_NF_MANGLE=3Dm=0A= +CONFIG_IP_NF_TARGET_TOS=3Dm=0A= +CONFIG_IP_NF_TARGET_ECN=3Dm=0A= +CONFIG_IP_NF_TARGET_DSCP=3Dm=0A= +CONFIG_IP_NF_TARGET_TTL=3Dm=0A= +CONFIG_IP_NF_TARGET_CLUSTERIP=3Dm=0A= +CONFIG_IP_NF_RAW=3Dm=0A= +CONFIG_IP_NF_ARPTABLES=3Dm=0A= +CONFIG_IP_NF_ARPFILTER=3Dm=0A= +CONFIG_IP_NF_ARP_MANGLE=3Dm=0A= +=0A= +#=0A= +# DCCP Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_IP_DCCP is not set=0A= +=0A= +#=0A= +# SCTP Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_IP_SCTP is not set=0A= +=0A= +#=0A= +# TIPC Configuration (EXPERIMENTAL)=0A= +#=0A= +# CONFIG_TIPC is not set=0A= +# CONFIG_ATM is not set=0A= +# CONFIG_BRIDGE is not set=0A= +# CONFIG_VLAN_8021Q is not set=0A= +# CONFIG_DECNET is not set=0A= +# CONFIG_LLC2 is not set=0A= +# CONFIG_IPX is not set=0A= +# CONFIG_ATALK is not set=0A= +# CONFIG_X25 is not set=0A= +# CONFIG_LAPB is not set=0A= +# CONFIG_NET_DIVERT is not set=0A= +# CONFIG_ECONET is not set=0A= +# CONFIG_WAN_ROUTER is not set=0A= +=0A= +#=0A= +# QoS and/or fair queueing=0A= +#=0A= +CONFIG_NET_SCHED=3Dy=0A= +# CONFIG_NET_SCH_CLK_JIFFIES is not set=0A= +CONFIG_NET_SCH_CLK_GETTIMEOFDAY=3Dy=0A= +# CONFIG_NET_SCH_CLK_CPU is not set=0A= +=0A= +#=0A= +# Queueing/Scheduling=0A= +#=0A= +CONFIG_NET_SCH_CBQ=3Dm=0A= +CONFIG_NET_SCH_HTB=3Dm=0A= +CONFIG_NET_SCH_HFSC=3Dm=0A= +CONFIG_NET_SCH_PRIO=3Dm=0A= +CONFIG_NET_SCH_RED=3Dm=0A= +CONFIG_NET_SCH_SFQ=3Dm=0A= +CONFIG_NET_SCH_TEQL=3Dm=0A= +CONFIG_NET_SCH_TBF=3Dm=0A= +CONFIG_NET_SCH_GRED=3Dm=0A= +CONFIG_NET_SCH_DSMARK=3Dm=0A= +CONFIG_NET_SCH_NETEM=3Dm=0A= +CONFIG_NET_SCH_INGRESS=3Dm=0A= +=0A= +#=0A= +# Classification=0A= +#=0A= +CONFIG_NET_CLS=3Dy=0A= +CONFIG_NET_CLS_BASIC=3Dm=0A= +CONFIG_NET_CLS_TCINDEX=3Dm=0A= +CONFIG_NET_CLS_ROUTE4=3Dm=0A= +CONFIG_NET_CLS_ROUTE=3Dy=0A= +CONFIG_NET_CLS_FW=3Dm=0A= +CONFIG_NET_CLS_U32=3Dm=0A= +# CONFIG_CLS_U32_PERF is not set=0A= +# CONFIG_CLS_U32_MARK is not set=0A= +CONFIG_NET_CLS_RSVP=3Dm=0A= +CONFIG_NET_CLS_RSVP6=3Dm=0A= +# CONFIG_NET_EMATCH is not set=0A= +# CONFIG_NET_CLS_ACT is not set=0A= +CONFIG_NET_CLS_POLICE=3Dy=0A= +# CONFIG_NET_CLS_IND is not set=0A= +CONFIG_NET_ESTIMATOR=3Dy=0A= +=0A= +#=0A= +# Network testing=0A= +#=0A= +# CONFIG_NET_PKTGEN is not set=0A= +# CONFIG_HAMRADIO is not set=0A= +# CONFIG_IRDA is not set=0A= +# CONFIG_BT is not set=0A= +# CONFIG_IEEE80211 is not set=0A= +=0A= +#=0A= +# Device Drivers=0A= +#=0A= +=0A= +#=0A= +# Generic Driver Options=0A= +#=0A= +CONFIG_STANDALONE=3Dy=0A= +CONFIG_PREVENT_FIRMWARE_BUILD=3Dy=0A= +# CONFIG_FW_LOADER is not set=0A= +=0A= +#=0A= +# Connector - unified userspace <-> kernelspace linker=0A= +#=0A= +# CONFIG_CONNECTOR is not set=0A= +=0A= +#=0A= +# Memory Technology Devices (MTD)=0A= +#=0A= +# CONFIG_MTD is not set=0A= +=0A= +#=0A= +# Parallel port support=0A= +#=0A= +# CONFIG_PARPORT is not set=0A= +=0A= +#=0A= +# Plug and Play support=0A= +#=0A= +=0A= +#=0A= +# Block devices=0A= +#=0A= +# CONFIG_BLK_CPQ_DA is not set=0A= +# CONFIG_BLK_CPQ_CISS_DA is not set=0A= +# CONFIG_BLK_DEV_DAC960 is not set=0A= +# CONFIG_BLK_DEV_UMEM is not set=0A= +# CONFIG_BLK_DEV_COW_COMMON is not set=0A= +# CONFIG_BLK_DEV_LOOP is not set=0A= +# CONFIG_BLK_DEV_NBD is not set=0A= +# CONFIG_BLK_DEV_SX8 is not set=0A= +# CONFIG_BLK_DEV_RAM is not set=0A= +CONFIG_BLK_DEV_RAM_COUNT=3D16=0A= +# CONFIG_CDROM_PKTCDVD is not set=0A= +# CONFIG_ATA_OVER_ETH is not set=0A= +=0A= +#=0A= +# ATA/ATAPI/MFM/RLL support=0A= +#=0A= +# CONFIG_IDE is not set=0A= +=0A= +#=0A= +# SCSI device support=0A= +#=0A= +# CONFIG_RAID_ATTRS is not set=0A= +# CONFIG_SCSI is not set=0A= +=0A= +#=0A= +# Multi-device support (RAID and LVM)=0A= +#=0A= +# CONFIG_MD is not set=0A= +=0A= +#=0A= +# Fusion MPT device support=0A= +#=0A= +# CONFIG_FUSION is not set=0A= +=0A= +#=0A= +# IEEE 1394 (FireWire) support=0A= +#=0A= +# CONFIG_IEEE1394 is not set=0A= +=0A= +#=0A= +# I2O device support=0A= +#=0A= +# CONFIG_I2O is not set=0A= +=0A= +#=0A= +# Network device support=0A= +#=0A= +CONFIG_NETDEVICES=3Dy=0A= +# CONFIG_DUMMY is not set=0A= +# CONFIG_BONDING is not set=0A= +# CONFIG_EQUALIZER is not set=0A= +# CONFIG_TUN is not set=0A= +=0A= +#=0A= +# ARCnet devices=0A= +#=0A= +# CONFIG_ARCNET is not set=0A= +=0A= +#=0A= +# PHY device support=0A= +#=0A= +CONFIG_PHYLIB=3Dm=0A= +=0A= +#=0A= +# MII PHY device drivers=0A= +#=0A= +CONFIG_MARVELL_PHY=3Dm=0A= +CONFIG_DAVICOM_PHY=3Dm=0A= +CONFIG_QSEMI_PHY=3Dm=0A= +CONFIG_LXT_PHY=3Dm=0A= +CONFIG_CICADA_PHY=3Dm=0A= +=0A= +#=0A= +# Ethernet (10 or 100Mbit)=0A= +#=0A= +CONFIG_NET_ETHERNET=3Dy=0A= +CONFIG_MII=3Dy=0A= +CONFIG_IDT_RC32438_ETH=3Dy=0A= +# CONFIG_HAPPYMEAL is not set=0A= +# CONFIG_SUNGEM is not set=0A= +# CONFIG_CASSINI is not set=0A= +# CONFIG_NET_VENDOR_3COM is not set=0A= +# CONFIG_DM9000 is not set=0A= +=0A= +#=0A= +# Tulip family network device support=0A= +#=0A= +# CONFIG_NET_TULIP is not set=0A= +# CONFIG_HP100 is not set=0A= +CONFIG_NET_PCI=3Dy=0A= +# CONFIG_PCNET32 is not set=0A= +# CONFIG_AMD8111_ETH is not set=0A= +# CONFIG_ADAPTEC_STARFIRE is not set=0A= +# CONFIG_B44 is not set=0A= +# CONFIG_FORCEDETH is not set=0A= +# CONFIG_DGRS is not set=0A= +# CONFIG_EEPRO100 is not set=0A= +CONFIG_E100=3Dy=0A= +# CONFIG_FEALNX is not set=0A= +# CONFIG_NATSEMI is not set=0A= +# CONFIG_NE2K_PCI is not set=0A= +# CONFIG_8139CP is not set=0A= +# CONFIG_8139TOO is not set=0A= +# CONFIG_SIS900 is not set=0A= +# CONFIG_EPIC100 is not set=0A= +# CONFIG_SUNDANCE is not set=0A= +# CONFIG_TLAN is not set=0A= +# CONFIG_VIA_RHINE is not set=0A= +# CONFIG_LAN_SAA9730 is not set=0A= +=0A= +#=0A= +# Ethernet (1000 Mbit)=0A= +#=0A= +# CONFIG_ACENIC is not set=0A= +# CONFIG_DL2K is not set=0A= +# CONFIG_E1000 is not set=0A= +# CONFIG_NS83820 is not set=0A= +# CONFIG_HAMACHI is not set=0A= +# CONFIG_YELLOWFIN is not set=0A= +# CONFIG_R8169 is not set=0A= +# CONFIG_SIS190 is not set=0A= +# CONFIG_SKGE is not set=0A= +# CONFIG_SKY2 is not set=0A= +# CONFIG_SK98LIN is not set=0A= +# CONFIG_VIA_VELOCITY is not set=0A= +# CONFIG_TIGON3 is not set=0A= +# CONFIG_BNX2 is not set=0A= +=0A= +#=0A= +# Ethernet (10000 Mbit)=0A= +#=0A= +# CONFIG_CHELSIO_T1 is not set=0A= +# CONFIG_IXGB is not set=0A= +# CONFIG_S2IO is not set=0A= +=0A= +#=0A= +# Token Ring devices=0A= +#=0A= +# CONFIG_TR is not set=0A= +=0A= +#=0A= +# Wireless LAN (non-hamradio)=0A= +#=0A= +# CONFIG_NET_RADIO is not set=0A= +=0A= +#=0A= +# Wan interfaces=0A= +#=0A= +# CONFIG_WAN is not set=0A= +# CONFIG_FDDI is not set=0A= +# CONFIG_HIPPI is not set=0A= +# CONFIG_PPP is not set=0A= +# CONFIG_SLIP is not set=0A= +# CONFIG_SHAPER is not set=0A= +# CONFIG_NETCONSOLE is not set=0A= +# CONFIG_NETPOLL is not set=0A= +# CONFIG_NET_POLL_CONTROLLER is not set=0A= +=0A= +#=0A= +# ISDN subsystem=0A= +#=0A= +# CONFIG_ISDN is not set=0A= +=0A= +#=0A= +# Telephony Support=0A= +#=0A= +# CONFIG_PHONE is not set=0A= +=0A= +#=0A= +# Input device support=0A= +#=0A= +CONFIG_INPUT=3Dy=0A= +=0A= +#=0A= +# Userland interfaces=0A= +#=0A= +# CONFIG_INPUT_MOUSEDEV is not set=0A= +# CONFIG_INPUT_JOYDEV is not set=0A= +# CONFIG_INPUT_TSDEV is not set=0A= +# CONFIG_INPUT_EVDEV is not set=0A= +# CONFIG_INPUT_EVBUG is not set=0A= +=0A= +#=0A= +# Input Device Drivers=0A= +#=0A= +# CONFIG_INPUT_KEYBOARD is not set=0A= +# CONFIG_INPUT_MOUSE is not set=0A= +# CONFIG_INPUT_JOYSTICK is not set=0A= +# CONFIG_INPUT_TOUCHSCREEN is not set=0A= +# CONFIG_INPUT_MISC is not set=0A= +=0A= +#=0A= +# Hardware I/O ports=0A= +#=0A= +# CONFIG_SERIO is not set=0A= +# CONFIG_GAMEPORT is not set=0A= +=0A= +#=0A= +# Character devices=0A= +#=0A= +CONFIG_VT=3Dy=0A= +CONFIG_VT_CONSOLE=3Dy=0A= +CONFIG_HW_CONSOLE=3Dy=0A= +# CONFIG_SERIAL_NONSTANDARD is not set=0A= +=0A= +#=0A= +# Serial drivers=0A= +#=0A= +CONFIG_SERIAL_8250=3Dy=0A= +CONFIG_SERIAL_8250_CONSOLE=3Dy=0A= +CONFIG_SERIAL_8250_NR_UARTS=3D4=0A= +CONFIG_SERIAL_8250_RUNTIME_UARTS=3D4=0A= +# CONFIG_SERIAL_8250_EXTENDED is not set=0A= +=0A= +#=0A= +# Non-8250 serial port support=0A= +#=0A= +CONFIG_SERIAL_CORE=3Dy=0A= +CONFIG_SERIAL_CORE_CONSOLE=3Dy=0A= +# CONFIG_SERIAL_JSM is not set=0A= +CONFIG_UNIX98_PTYS=3Dy=0A= +CONFIG_LEGACY_PTYS=3Dy=0A= +CONFIG_LEGACY_PTY_COUNT=3D256=0A= +=0A= +#=0A= +# IPMI=0A= +#=0A= +# CONFIG_IPMI_HANDLER is not set=0A= +=0A= +#=0A= +# Watchdog Cards=0A= +#=0A= +# CONFIG_WATCHDOG is not set=0A= +# CONFIG_RTC is not set=0A= +# CONFIG_GEN_RTC is not set=0A= +# CONFIG_DTLK is not set=0A= +# CONFIG_R3964 is not set=0A= +# CONFIG_APPLICOM is not set=0A= +=0A= +#=0A= +# Ftape, the floppy tape device driver=0A= +#=0A= +# CONFIG_DRM is not set=0A= +# CONFIG_RAW_DRIVER is not set=0A= +=0A= +#=0A= +# TPM devices=0A= +#=0A= +# CONFIG_TCG_TPM is not set=0A= +# CONFIG_TELCLOCK is not set=0A= +=0A= +#=0A= +# I2C support=0A= +#=0A= +# CONFIG_I2C is not set=0A= +=0A= +#=0A= +# SPI support=0A= +#=0A= +# CONFIG_SPI is not set=0A= +# CONFIG_SPI_MASTER is not set=0A= +=0A= +#=0A= +# Dallas's 1-wire bus=0A= +#=0A= +# CONFIG_W1 is not set=0A= +=0A= +#=0A= +# Hardware Monitoring support=0A= +#=0A= +# CONFIG_HWMON is not set=0A= +# CONFIG_HWMON_VID is not set=0A= +=0A= +#=0A= +# Misc devices=0A= +#=0A= +=0A= +#=0A= +# Multimedia Capabilities Port drivers=0A= +#=0A= +=0A= +#=0A= +# Multimedia devices=0A= +#=0A= +# CONFIG_VIDEO_DEV is not set=0A= +=0A= +#=0A= +# Digital Video Broadcasting Devices=0A= +#=0A= +# CONFIG_DVB is not set=0A= +=0A= +#=0A= +# Graphics support=0A= +#=0A= +# CONFIG_FB is not set=0A= +=0A= +#=0A= +# Console display driver support=0A= +#=0A= +# CONFIG_VGA_CONSOLE is not set=0A= +CONFIG_DUMMY_CONSOLE=3Dy=0A= +=0A= +#=0A= +# Sound=0A= +#=0A= +# CONFIG_SOUND is not set=0A= +=0A= +#=0A= +# USB support=0A= +#=0A= +CONFIG_USB_ARCH_HAS_HCD=3Dy=0A= +CONFIG_USB_ARCH_HAS_OHCI=3Dy=0A= +# CONFIG_USB is not set=0A= +=0A= +#=0A= +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'=0A= +#=0A= +=0A= +#=0A= +# USB Gadget Support=0A= +#=0A= +# CONFIG_USB_GADGET is not set=0A= +=0A= +#=0A= +# MMC/SD Card support=0A= +#=0A= +# CONFIG_MMC is not set=0A= +=0A= +#=0A= +# InfiniBand support=0A= +#=0A= +# CONFIG_INFINIBAND is not set=0A= +=0A= +#=0A= +# SN Devices=0A= +#=0A= +=0A= +#=0A= +# EDAC - error detection and reporting (RAS)=0A= +#=0A= +=0A= +#=0A= +# File systems=0A= +#=0A= +CONFIG_EXT2_FS=3Dy=0A= +# CONFIG_EXT2_FS_XATTR is not set=0A= +# CONFIG_EXT2_FS_XIP is not set=0A= +# CONFIG_EXT3_FS is not set=0A= +# CONFIG_REISERFS_FS is not set=0A= +# CONFIG_JFS_FS is not set=0A= +# CONFIG_FS_POSIX_ACL is not set=0A= +# CONFIG_XFS_FS is not set=0A= +# CONFIG_OCFS2_FS is not set=0A= +# CONFIG_MINIX_FS is not set=0A= +# CONFIG_ROMFS_FS is not set=0A= +# CONFIG_INOTIFY is not set=0A= +# CONFIG_QUOTA is not set=0A= +# CONFIG_DNOTIFY is not set=0A= +# CONFIG_AUTOFS_FS is not set=0A= +# CONFIG_AUTOFS4_FS is not set=0A= +# CONFIG_FUSE_FS is not set=0A= +=0A= +#=0A= +# CD-ROM/DVD Filesystems=0A= +#=0A= +# CONFIG_ISO9660_FS is not set=0A= +# CONFIG_UDF_FS is not set=0A= +=0A= +#=0A= +# DOS/FAT/NT Filesystems=0A= +#=0A= +# CONFIG_MSDOS_FS is not set=0A= +# CONFIG_VFAT_FS is not set=0A= +# CONFIG_NTFS_FS is not set=0A= +=0A= +#=0A= +# Pseudo filesystems=0A= +#=0A= +CONFIG_PROC_FS=3Dy=0A= +CONFIG_PROC_KCORE=3Dy=0A= +CONFIG_SYSFS=3Dy=0A= +# CONFIG_TMPFS is not set=0A= +# CONFIG_HUGETLB_PAGE is not set=0A= +CONFIG_RAMFS=3Dy=0A= +# CONFIG_RELAYFS_FS is not set=0A= +# CONFIG_CONFIGFS_FS is not set=0A= +=0A= +#=0A= +# Miscellaneous filesystems=0A= +#=0A= +# CONFIG_ADFS_FS is not set=0A= +# CONFIG_AFFS_FS is not set=0A= +# CONFIG_HFS_FS is not set=0A= +# CONFIG_HFSPLUS_FS is not set=0A= +# CONFIG_BEFS_FS is not set=0A= +# CONFIG_BFS_FS is not set=0A= +# CONFIG_EFS_FS is not set=0A= +# CONFIG_CRAMFS is not set=0A= +# CONFIG_VXFS_FS is not set=0A= +# CONFIG_HPFS_FS is not set=0A= +# CONFIG_QNX4FS_FS is not set=0A= +# CONFIG_SYSV_FS is not set=0A= +# CONFIG_UFS_FS is not set=0A= +=0A= +#=0A= +# Network File Systems=0A= +#=0A= +# CONFIG_NFS_FS is not set=0A= +# CONFIG_NFSD is not set=0A= +# CONFIG_SMB_FS is not set=0A= +# CONFIG_CIFS is not set=0A= +# CONFIG_NCP_FS is not set=0A= +# CONFIG_CODA_FS is not set=0A= +# CONFIG_AFS_FS is not set=0A= +# CONFIG_9P_FS is not set=0A= +=0A= +#=0A= +# Partition Types=0A= +#=0A= +# CONFIG_PARTITION_ADVANCED is not set=0A= +CONFIG_MSDOS_PARTITION=3Dy=0A= +=0A= +#=0A= +# Native Language Support=0A= +#=0A= +# CONFIG_NLS is not set=0A= +=0A= +#=0A= +# Profiling support=0A= +#=0A= +# CONFIG_PROFILING is not set=0A= +=0A= +#=0A= +# Kernel hacking=0A= +#=0A= +# CONFIG_PRINTK_TIME is not set=0A= +# CONFIG_MAGIC_SYSRQ is not set=0A= +# CONFIG_DEBUG_KERNEL is not set=0A= +CONFIG_LOG_BUF_SHIFT=3D14=0A= +CONFIG_CROSSCOMPILE=3Dy=0A= +CONFIG_CMDLINE=3D""=0A= +=0A= +#=0A= +# Security options=0A= +#=0A= +# CONFIG_KEYS is not set=0A= +# CONFIG_SECURITY is not set=0A= +=0A= +#=0A= +# Cryptographic options=0A= +#=0A= +# CONFIG_CRYPTO is not set=0A= +=0A= +#=0A= +# Hardware crypto devices=0A= +#=0A= +=0A= +#=0A= +# Library routines=0A= +#=0A= +CONFIG_CRC_CCITT=3Dy=0A= +CONFIG_CRC16=3Dm=0A= +CONFIG_CRC32=3Dy=0A= +# CONFIG_LIBCRC32C is not set=0A= +CONFIG_TEXTSEARCH=3Dy=0A= +CONFIG_TEXTSEARCH_KMP=3Dm=0A= +CONFIG_TEXTSEARCH_BM=3Dm=0A= +CONFIG_TEXTSEARCH_FSM=3Dm=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/Kconfig = idtlinux/arch/mips/idt-boards/Kconfig=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/Kconfig 1969-12-31 = 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/Kconfig 2006-03-09 16:25:51.000000000 = -0800=0A= @@ -0,0 +1,107 @@=0A= +config IDT_EB438=0A= + bool " Support for the IDT 79EB438 evaluation board"=0A= + depends on IDT_BOARDS=0A= + select DMA_NONCOHERENT=0A= + select IRQ_CPU=0A= + select HW_HAS_PCI=0A= + select SWAP_IO_SPACE=0A= + select SYS_HAS_CPU_MIPS32_R1=0A= + select SYS_SUPPORTS_LITTLE_ENDIAN=0A= + select BOOT_ELF32=0A= + select SYS_SUPPORTS_32BIT_KERNEL=0A= + select SYS_SUPPORTS_BIG_ENDIAN=0A= + help=0A= + IDT evaluation board based on RC32438 Interprise Processor=0A= +=0A= +config RC32438_REVISION_ZA=0A= + bool " Support for ZA version"=0A= + depends on IDT_EB438=0A= + help=0A= + Enable this option for enabling the workaround for the bugs=0A= + in the ZA part.=0A= +=0A= +config IDT_EB434=0A= + bool " Support for the IDT 79EB434/435 evaluation board"=0A= + depends on IDT_BOARDS=0A= + select DMA_NONCOHERENT=0A= + select IRQ_CPU=0A= + select HW_HAS_PCI=0A= + select SWAP_IO_SPACE=0A= + select SYS_HAS_CPU_MIPS32_R1=0A= + select SYS_SUPPORTS_LITTLE_ENDIAN=0A= + select BOOT_ELF32=0A= + select SYS_SUPPORTS_32BIT_KERNEL=0A= + select SYS_SUPPORTS_BIG_ENDIAN=0A= + help=0A= + IDT evaluation board based on RC32434/435 Interprise = Processor=0A= +=0A= +config IDT_EB365=0A= + bool " Support for the IDT 79EB365/336 based evaluation = boards"=0A= + depends on IDT_BOARDS=0A= + select DMA_NONCOHERENT=0A= + select IRQ_CPU=0A= + select HW_HAS_PCI=0A= + select SYS_HAS_CPU_MIPS32_R1=0A= + select SYS_SUPPORTS_LITTLE_ENDIAN=0A= + select BOOT_ELF32=0A= + select SYS_SUPPORTS_32BIT_KERNEL=0A= + select SYS_SUPPORTS_BIG_ENDIAN=0A= + select SWAP_IO_SPACE=0A= + help=0A= + IDT evaluation boards based RC32300 core.=0A= +=0A= +config IDT_EB355=0A= + bool " Support for the IDT 79EB355 based evaluation boards"=0A= + depends on IDT_BOARDS=0A= + select DMA_NONCOHERENT=0A= + select IRQ_CPU=0A= + select SYS_HAS_CPU_MIPS32_R1=0A= + select SYS_SUPPORTS_LITTLE_ENDIAN=0A= + select BOOT_ELF32=0A= + select SYS_SUPPORTS_32BIT_KERNEL=0A= + select SYS_SUPPORTS_BIG_ENDIAN=0A= + select SWAP_IO_SPACE=0A= + help=0A= + IDT evaluation boards based RC32300 core.=0A= +=0A= +config IDT_S334=0A= + bool " Support for the IDT 79EB334 based evaluation boards"=0A= + depends on IDT_BOARDS=0A= + select DMA_NONCOHERENT=0A= + select IRQ_CPU=0A= + select HW_HAS_PCI=0A= + select SYS_SUPPORTS_LITTLE_ENDIAN=0A= + select SYS_HAS_CPU_MIPS32_R1=0A= + select BOOT_ELF32=0A= + select SYS_SUPPORTS_32BIT_KERNEL=0A= + select SYS_SUPPORTS_BIG_ENDIAN=0A= + select SWAP_IO_SPACE=0A= + help=0A= + IDT evaluation boards based RC32300 core.=0A= +=0A= +=0A= +config IDT_BOARD_FREQ=0A= + int " Board Frequency (HZ)"=0A= + depends on IDT_EB438 || IDT_EB365 || IDT_EB434 || IDT_S334 || = IDT_EB355=0A= + default 100000000 if IDT_EB434 || IDT_EB438=0A= + default 75000000 if IDT_EB355 || IDT_S334=0A= + default 90000000 if IDT_EB365=0A= + help=0A= + Specify the board frequency in Hz.=0A= +=0A= +config IDT_ZIMAGE_ADDR=0A= + hex " zImage Address"=0A= + depends on IDT_EB438 || IDT_EB355 || IDT_EB365 || IDT_EB434 || = IDT_S334=0A= + default "0x88000000" if IDT_EB365 || IDT_EB438=0A= + default "0x9b000000" if IDT_EB434=0A= + default "0x8c000000" if IDT_EB355=0A= + default "0x80800000" if IDT_S334=0A= + help=0A= + You may create a compressed image by running 'make zImage' = that can=0A= + either be loaded using the bootloader, or can be burned into = the flash.=0A= + Specify the address where zImage will be loaded. The default = address=0A= + is that of flash.=0A= +=0A= +config IDT_BOOT_NVRAM=0A= + depends on IDT_EB438 || IDT_EB365 || IDT_EB434 || IDT_S334 || = IDT_EB355=0A= + bool " Enable reading environment variables from NVRAM"=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/csu_idt.S = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/csu_idt.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/csu_idt.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/csu_idt.S = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,285 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Board initialization code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= + =0A= +=0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include "iregdef.h"=0A= +#include "idtcpu.h"=0A= +#include "idthdr.h"=0A= + =0A= +#define MHZ CONFIG_IDT_BOARD_FREQ=0A= +=0A= +#include "s364.h" =0A= +#include "s355ram.h"=0A= +=0A= +#define IndexInvalidate_I 0x00=0A= + =0A= +/*--------------------------------------------------------------=0A= +* prom entry point table=0A= +*-------------------------------------------------------------*/=0A= +=0A= +FRAME(start,sp,0,ra)=0A= +=0A= + j idtstart /* begin monitor from start |00| */=0A= + =0A= +idtstart:=0A= +=0A= + .set noreorder=0A= + =0A= + mtc0 zero, C0_CAUSE=0A= + li v0, 0x0=0A= + or v0, (SR_CU0 | SR_BEV | SR_DE)=0A= + mtc0 v0, C0_SR=0A= +=0A= + mfc0 v1, C0_CONFIG=0A= + li v0, CFG_C_NCHRNT_WB /* CFG_C_NCHRNT_WB CFG_C_NCHRNT_WT_NWA = CFG_C_UNCACHED */=0A= + and v1, ~(0x7)=0A= + or v1, v1, v0=0A= + mtc0 v1, C0_CONFIG=0A= + nop=0A= + nop=0A= + li t0, ERR_CNTL_STATUS=0A= + lw t1, 0(t0) =0A= + li t2, ERR_CNTL_VALUE=0A= + and t1, t2 =0A= + sw t1, 0(t0) =0A= +=0A= +/* ------------------- Setup Device Controller = -------------------------------*/=0A= + li t0, DEV_CTL_BASE /* load 2 base address registers' base = */=0A= +=0A= + lw t2, 0x8(t0)=0A= + andi t2, t2, 0x3=0A= + li t1, MCR_CS0_BS /* device0 control parameter */=0A= + or t1, t1, t2=0A= + sw t1, 0x8(t0) /* set the control register for CS 1 - SRAM = */=0A= + li t1, MCR_CS0_TC /* device0 timing config. parameter */=0A= + sw t1, 0xC(t0)=0A= +=0A= + li t1, 0x0=0A= + sw t1, 0x14(t0)=0A= + sw t1, 0x24(t0)=0A= + sw t1, 0x34(t0)=0A= + sw t1, 0x44(t0)=0A= + sw t1, 0x54(t0)=0A= +=0A= + li t1, MBA_REG1=0A= + sw t1, 0x10(t0)=0A= + li t1, MCR_CS1_BS=0A= + sw t1, 0x18(t0)=0A= + li t1, MCR_CS1_TC=0A= + sw t1, 0x1C(t0)=0A= + li t1, MBM_REG1=0A= + sw t1, 0x14(t0)=0A= +=0A= + li t1, MBA_REG2=0A= + sw t1, 0x20(t0)=0A= + li t1, MCR_CS2_BS=0A= + sw t1, 0x28(t0)=0A= + li t1, MCR_CS2_TC=0A= + sw t1, 0x2C(t0)=0A= + li t1, MBM_REG2=0A= + sw t1, 0x24(t0)=0A= +=0A= + li t1, MBA_REG3=0A= + sw t1, 0x30(t0)=0A= + li t1, MCR_CS3_BS=0A= + sw t1, 0x38(t0)=0A= + li t1, MCR_CS3_TC=0A= + sw t1, 0x3C(t0)=0A= + li t1, MBM_REG3=0A= + sw t1, 0x34(t0)=0A= +=0A= + li t1, MBA_REG4=0A= + sw t1, 0x40(t0)=0A= + li t1, MCR_CS4_BS=0A= + sw t1, 0x48(t0)=0A= + li t1, MCR_CS4_TC=0A= + sw t1, 0x4C(t0)=0A= + li t1, MBM_REG4=0A= + sw t1, 0x44(t0)=0A= +=0A= + li t1, MBA_REG5=0A= + sw t1, 0x50(t0)=0A= + li t1, MCR_CS5_BS=0A= + sw t1, 0x58(t0)=0A= + li t1, MCR_CS5_TC=0A= + sw t1, 0x5C(t0)=0A= + li t1, MBM_REG5=0A= + sw t1, 0x54(t0)=0A= +=0A= +/* USB fix for RP355 - set GPIO_26 as GPIO output low */=0A= + li t0, GPIO_BASE=0A= + li t1, 0xf9ffffff /* All alternate functions for GPIO pins = except GPIO_26*/=0A= + sw t1, 0x0(t0)=0A= +=0A= + lw t1, 0x8(t0) /* Reset GPIOD bit */=0A= + and t1, ~0x04000000=0A= + sw t1, 0x8(t0)=0A= +=0A= + lw t2, 0x4(t0) /* Set as output */=0A= + or t2, 0x04000000=0A= + sw t2, 0x4(t0)=0A= +=0A= + sw t1, 0x8(t0) /* Once again reset output */=0A= +=0A= +/*------------ load all R32355 internal registers' base address = ----------*/=0A= + li t0, TIMER_BASE =0A= +=0A= +/* ------------------- Disable WatchDog Timer = --------------------------------- */=0A= + li t1, DISABLE_TIMER=0A= + sw t1, 0x40(t0)=0A= +=0A= +/* ------------------- Reduce Bus Timeout Count = -----------------------------*/=0A= + li t1, TIMEOUT_COUNT=0A= + sw t1, 0x34(t0)=0A= +=0A= +/*-------------- Initialize SDRAM Base and Mask Registers = ----------*/=0A= +=0A= + li t0, SDRAM_CTL_BASE=0A= + li t1, SDRAM_CR_BS=0A= + li t2, 0x7FFFFFFF=0A= + and t1, t1, t2=0A= + sw t1, 0x10(t0) /* disable SDRAM refresh */=0A= +=0A= + li t1, 0x0 /* Disable Bank0 */=0A= + sw t1, 0x4(t0)=0A= + li t1, 0x0 /* Disable Bank1 */=0A= + sw t1, 0xC(t0) /* set DRAM bank 1 mask */=0A= +=0A= + li t1, DRAM_BNK0_BASE /* load DRAM bank 0 physical address in t1 = */=0A= + sw t1, 0x0(t0) /* set DRAM bank 0 base */=0A= + li t1, DRAM_BNK0_MASK /* load DRAM bank 0 size in t1 */=0A= + sw t1, 0x4(t0) /* set DRAM bank 0 mask */=0A= +=0A= +/*-------------- Enable SDRAM Controller = ---------------------------*/=0A= + li t0, SDRAM_CTL_BASE=0A= +=0A= +/*-------------- Setup Precharge Command = ---------------------------*/=0A= + li t2, 2=0A= + li t3, 0=0A= +1: =0A= + li t1, SDRAM_PC_VAL=0A= + sw t1, 0x10(t0)=0A= + nop=0A= + nop=0A= + lw t7, 0x10(t0)=0A= + nop=0A= + li t4, APATTERN=0A= + li t5, 0xA0000000 | DRAM_BNK0_BASE=0A= + sw t4, 0x0(t5)=0A= + addu t3, 1=0A= + bne t3, t2, 1b=0A= + nop=0A= +/*--------------- Setup Refresh Command = ----------------------------*/=0A= + li t2, 8=0A= + li t3, 0=0A= +1: =0A= + li t1, SDRAM_RFRSH_CMD=0A= + sw t1, 0x10(t0)=0A= + sw t4, 0x0(t5)=0A= + addu t3, 1=0A= + bne t3, t2, 1b=0A= + nop=0A= +/*-------------- Setup up to write to Mode Register = ----------------*/=0A= + li t1, SDRAM_MODE_REG=0A= + sw t1, 0x10(t0)=0A= + addu t5, 0x80 /* Kasi addu t5,0xC0 (CL=3D3)*/=0A= + sw t4, 0x0(t5) /* note: same old t5 */=0A= +=0A= +/*-------------- Setup and Enable Refresh Timer = --------------------*/=0A= +=0A= + li t0, TIMER_BASE /* load timer register set base */=0A= +=0A= + li t1, DISABLE_TIMER /* load diable timer bit settings into t1 = */=0A= + sw t1, 0x2c(t0) /* disable timer */=0A= +=0A= + li t1, 0 /* load DRAM refresh timer count register = bit settings in t1 */=0A= + sw t1, 0x24(t0) /* set DRAM refresh timer count register = bit settings */=0A= + li t1, DRAM_RF_CMPR_SE_BS /* load refresh timer compare value for = slower expiration */=0A= + sw t1, 0x28(t0) /* set compare register again */=0A= +=0A= + li t1, ENABLE_TIMER /* load timer enable bit */=0A= + sw t1, 0x2c(t0) /* enable refresh timer */=0A= +=0A= + li t0, SDRAM_CTL_BASE=0A= + li t1, SDRAM_CR_BS=0A= + sw t1, 0x10(t0)=0A= +/* the memory system may need up to 120us to start up... */=0A= + li v0, 128 /* ~256us */=0A= +1: =0A= + bne v0, zero, 1b=0A= + subu v0, 1 /* BDSLOT */=0A= + nop=0A= + nop=0A= +=0A= +/**********************************************************************= **=0A= +** before doing anything=0A= +** initialize the section of memory used by cache initialization=0A= +** whenever you boot out of ROM or reset-vector=0A= +** This assumed to be 1MB.=0A= +** --Sugan (11-22-96)=0A= +***********************************************************************= */=0A= + =0A= + li t0, 0xa0000000=0A= + li t1, 0xa0100000=0A= +1:=0A= + sw zero, 0x00(t0)=0A= + sw zero, 0x04(t0)=0A= + sw zero, 0x08(t0)=0A= + sw zero, 0x0c(t0)=0A= + addiu t0, 16=0A= + nop=0A= + blt t0, t1, 1b=0A= + nop=0A= + nop=0A= + nop=0A= +3:=0A= + mfc0 t0, C0_SR=0A= + nop=0A= + nop=0A= + and t0, ~SR_BEV=0A= + mtc0 t0, C0_SR=0A= + nop=0A= + nop=0A= +=0A= + la k0, zstartup=0A= + j k0=0A= + nop=0A= + nop=0A= + =0A= +ENDFRAME(start)=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/head.S = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/head.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/head.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/head.S 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,138 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Board initialisation code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= + =0A= +=0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#define IndexInvalidate_I 0x00=0A= +=0A= + .set noreorder=0A= + .cprestore=0A= + LEAF(zstartup)=0A= +zstartup:=0A= +=0A= + la sp, .stack=0A= + move s0, a0=0A= + move s1, a1=0A= + move s2, a2=0A= + move s3, a3=0A= +=0A= + /* Clear BSS */=0A= + /* Note: when zImage is in ROM, _edata and _bss point to=0A= + * ROM space even when using -Tbss on the linker command line;=0A= + * maybe ld.script needs to be corrected.=0A= + */=0A= + la a0, .stack=0A= + la a2, _end=0A= +1: sw zero, 0(a0)=0A= + bne a2, a0, 1b=0A= + addu a0, 4=0A= +=0A= +#if 1=0A= + /* flush the I-Cache */=0A= + li k0, 0x80000000 # start address=0A= + li k1, 0x80002000 # end address (8KB I-Cache)=0A= + subu k1, 128=0A= +2:=0A= + .set mips3=0A= + cache IndexInvalidate_I, 0(k0)=0A= + cache IndexInvalidate_I, 16(k0)=0A= + cache IndexInvalidate_I, 32(k0)=0A= + cache IndexInvalidate_I, 48(k0)=0A= + cache IndexInvalidate_I, 64(k0)=0A= + cache IndexInvalidate_I, 80(k0)=0A= + cache IndexInvalidate_I, 96(k0)=0A= + cache IndexInvalidate_I, 112(k0)=0A= + .set mips0=0A= +=0A= + bne k0, k1, 2b=0A= + addu k0, k0, 128=0A= + /* done */=0A= +#endif=0A= +#if 1=0A= + /* flush the D-Cache */=0A= + li k0, 0x80000000 # start address=0A= + li k1, 0x80000400 # end address (2KB I-Cache)=0A= + subu k1, 128=0A= +3: =0A= + .set mips3=0A= + /* First way */=0A= + cache Index_Writeback_Inv_D, 0(k0)=0A= + cache Index_Writeback_Inv_D, 16(k0)=0A= + cache Index_Writeback_Inv_D, 32(k0)=0A= + cache Index_Writeback_Inv_D, 48(k0)=0A= + cache Index_Writeback_Inv_D, 64(k0)=0A= + cache Index_Writeback_Inv_D, 80(k0)=0A= + cache Index_Writeback_Inv_D, 96(k0)=0A= + cache Index_Writeback_Inv_D, 112(k0)=0A= + /* Second way */=0A= + cache Index_Writeback_Inv_D, 1024(k0)=0A= + cache Index_Writeback_Inv_D, 1040(k0)=0A= + cache Index_Writeback_Inv_D, 1056(k0)=0A= + cache Index_Writeback_Inv_D, 1072(k0)=0A= + cache Index_Writeback_Inv_D, 1088(k0)=0A= + cache Index_Writeback_Inv_D, 1104(k0)=0A= + cache Index_Writeback_Inv_D, 1120(k0)=0A= + cache Index_Writeback_Inv_D, 1136(k0)=0A= + .set mips0=0A= +=0A= + bne k0, k1, 3b=0A= + addu k0, k0, 128=0A= + /* done */=0A= +#endif=0A= +=0A= + la ra, 3f=0A= + la k0, decompress_kernel=0A= + jr k0=0A= + nop=0A= +3:=0A= +=0A= + move a0, s0=0A= + move a1, s1=0A= + move a2, s2=0A= + move a3, s3=0A= + li k0, KERNEL_ENTRY=0A= + jr k0=0A= + nop=0A= +4:=0A= + b 4b=0A= + END(zstartup)=0A= +=0A= + .bss=0A= + .fill 0x2000=0A= + EXPORT(.stack)=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/idtcpu.h = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/idtcpu.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/idtcpu.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/idtcpu.h = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,614 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT CPU register definitions. Though the registers are already = defined=0A= + * under asm directory, they are once again declared here for the = ease of=0A= + * syncing up with IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#if defined(__IDTCPU_H__)=0A= +#else=0A= +#define __IDTCPU_H__=0A= +=0A= +=0A= +/*=0A= +** memory configuration and mapping=0A= +*/=0A= +#define K0BASE 0x80000000=0A= +#define K0SIZE 0x20000000=0A= +#define K1BASE 0xa0000000=0A= +#define K1SIZE 0x20000000=0A= +#define K2BASE 0xc0000000=0A= +#if defined(S364)=0A= +#define K2SIZE 0x3e000000=0A= +#define ICEBASE 0xff000000=0A= +#define ICESIZE 0x01000000=0A= +#else=0A= +#define K2SIZE 0x20000000=0A= +#endif=0A= +#if defined(CPU_R4000)=0A= +#define KSBASE 0xe0000000=0A= +#define KSSIZE 0x20000000=0A= +#endif=0A= +=0A= +#define KUBASE 0=0A= +#define KUSIZE 0x80000000=0A= +=0A= +/*=0A= +** Exception Vectors=0A= +*/=0A= +#if defined(CPU_R3000)=0A= +#define UT_VEC K0BASE /* utlbmiss vector */=0A= +#define E_VEC (K0BASE+0x80) /* exception vevtor */=0A= +#endif=0A= +#if defined(CPU_R4000) || defined S364 /*(CPU_R32364) */=0A= +#define T_VEC (K0BASE+0x000) /* tlbmiss vector */=0A= +#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */=0A= +#define C_VEC (K1BASE+0x100) /* cache error vector */=0A= +#define E_VEC (K0BASE+0x180) /* exception vector */=0A= +#define I_VEC (K0BASE+0X200) /* interrupt vector */=0A= +#endif=0A= +#define R_VEC (K1BASE+0x1fc00000) /* reset vector */=0A= +=0A= +/*=0A= +** Address conversion macros=0A= +*/=0A= +#ifdef CLANGUAGE=0A= +#define CAST(as) (as)=0A= +#else=0A= +#define CAST(as)=0A= +#endif=0A= +#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 = */=0A= +#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 = */=0A= +#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to = physical */=0A= +#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to = physical */=0A= +#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to = kseg0 */=0A= +#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to = kseg1 */=0A= +=0A= +/*=0A= +** Cache size constants=0A= +*/=0A= +/* Sugan changed so that MINCACHE is 0x200 instead of 0x800 */=0A= +#define MINCACHE 0x200 /* 512 bytes */=0A= +#define MAXCACHE 0x40000 /* 256*1024 256k */ =0A= +=0A= +#if defined CPU_R32364 /* Includes RC32364, RC32332, = RC32334 */=0A= +#define CFG_ICE 0x80000000 /* ICE detect */=0A= +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */=0A= +#define CFG_ECBY2 0x00000000 /* divide by 2 */=0A= +#define CFG_ECBY3 0x10000000 /* divide by 3 */=0A= +#define CFG_ECBY4 0x20000000 /* divide by 4 */=0A= +#define CFG_NBL 0x00800000 /* Non-Blocking load pending */=0A= +#define CFG_BE 0x00008000 /* Big Endian */=0A= +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */=0A= +#define CFG_ICSHIFT 9=0A= +#define CFG_DCMASK 0x000001c0 /* Data cache size */=0A= +#define CFG_DCSHIFT 6=0A= +#define CFG_IB 0x00000020 /* Instruction cache line size */=0A= +#define CFG_DB 0x00000010 /* Data cache line size */=0A= +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */=0A= +=0A= +/*=0A= + * R32364 primary cache mode=0A= + */=0A= +#define CFG_C_NCHRNT_WT_NWA 0=0A= +#define CFG_C_NCHRNT_WT 1=0A= +#define CFG_C_UNCACHED 2=0A= +#define CFG_C_NCHRNT_WB 3=0A= +=0A= +/* Cache Operations */=0A= +#define Index_Invalidate_I 0x0 /* 0 0 = */=0A= +#define Index_Writeback_Inv_D 0x1 /* 0 1 = */=0A= +#define Index_Invalidate_SI 0x2 /* 0 2 = */=0A= +#define Index_Writeback_Inv_SD 0x3 /* 0 3 = */=0A= +#define Index_Load_Tag_I 0x4 /* 1 0 = */=0A= +#define Index_Load_Tag_D 0x5 /* 1 1 = */=0A= +#define Index_Load_Tag_SI 0x6 /* 1 2 = */=0A= +#define Index_Load_Tag_SD 0x7 /* 1 3 = */=0A= +#define Index_Store_Tag_I 0x8 /* 2 0 = */=0A= +#define Index_Store_Tag_D 0x9 /* 2 1 = */=0A= +#define Index_Store_Tag_SI 0xA /* 2 2 = */=0A= +#define Index_Store_Tag_SD 0xB /* 2 3 = */=0A= +#define Create_Dirty_Exc_D 0xD /* 3 1 = */=0A= +#define Create_Dirty_Exc_SD 0xF /* 3 3 = */=0A= +#define Hit_Invalidate_I 0x10 /* 4 0 = */=0A= +#define Hit_Invalidate_D 0x11 /* 4 1 = */=0A= +#define Hit_Invalidate_SI 0x12 /* 4 2 = */=0A= +#define Hit_Invalidate_SD 0x13 /* 4 3 = */=0A= +#define Hit_Writeback_Inv_D 0x15 /* 5 1 = */=0A= +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 = */=0A= +#define Fill_I 0x14 /* 5 0 = */=0A= +#define Hit_Writeback_D 0x19 /* 6 1 = */=0A= +#define Hit_Writeback_SD 0x1B /* 6 3 = */=0A= +#define Hit_Writeback_I 0x18 /* 6 0 = */=0A= +#define Hit_Set_Virtual_SI 0x1E /* 7 2 = */=0A= +#define Hit_Set_Virtual_SD 0x1F /* 7 3 = */=0A= +#define CFG_EW32 0x00040000 /* 32 bit */=0A= +#endif /* CPU_R32364 */=0A= +=0A= +#if defined(CPU_R4000)=0A= +/* R4000 configuration register definitions */=0A= +#define CFG_CM 0x80000000 /* Master-Checker mode */=0A= +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */=0A= +#define CFG_ECBY2 0x00000000 /* divide by 2 */=0A= +#define CFG_ECBY3 0x10000000 /* divide by 3 */=0A= +#define CFG_ECBY4 0x20000000 /* divide by 4 */=0A= +#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */=0A= +#define CFG_EPD 0x00000000 /* D */=0A= +#define CFG_EPDDX 0x01000000 /* DDX */=0A= +#define CFG_EPDDXX 0x02000000 /* DDXX */=0A= +#define CFG_EPDXDX 0x03000000 /* DXDX */=0A= +#define CFG_EPDDXXX 0x04000000 /* DDXXX */=0A= +#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */=0A= +#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */=0A= +#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */=0A= +#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */=0A= +#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */=0A= +#define CFG_SBSHIFT 22=0A= +#define CFG_SB4 0x00000000 /* 4 words */=0A= +#define CFG_SB8 0x00400000 /* 8 words */=0A= +#define CFG_SB16 0x00800000 /* 16 words */=0A= +#define CFG_SB32 0x00c00000 /* 32 words */=0A= +#define CFG_SS 0x00200000 /* Split secondary cache */=0A= +#define CFG_SW 0x00100000 /* Secondary cache port width */=0A= +#define CFG_EWMASK 0x000c0000 /* System port width */=0A= +#define CFG_EWSHIFT 18=0A= +#define CFG_EW64 0x00000000 /* 64 bit */=0A= +#define CFG_EW32 0x00040000 /* 32 bit */=0A= +/* #if defined(CPU_R5000) */=0A= +/* Sugan added for R5000 L2 cache 07-17-96 */=0A= +#define L2_PAGESIZE 0x1000=0A= +#define SIZE256K 0x00040000 /* 256KB in Hex */=0A= +#define CFG_HARDL2 0x00020000 /* Hardware bit that enables/disables=0A= + L2 cache */=0A= +#define CFG_SE 0x1000=0A= +#define CFG_SIZE512K 0x00000000 /* size of Scache is 512k */=0A= +#define CFG_SIZE1MB 0x00100000 /* size of Scache is 1MB */=0A= +#define CFG_SIZE2MB 0x00200000 /* size of Scache is 2MB */=0A= +#define CFG_SIZEMASK 0x00300000 /* size mask */=0A= +/* #endif */=0A= +#define CFG_SC 0x00020000 /* Secondary cache absent */=0A= +#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */=0A= +#define CFG_BE 0x00008000 /* Big Endian */=0A= +#define CFG_EM 0x00004000 /* ECC mode enable */=0A= +#define CFG_EB 0x00002000 /* Block ordering */=0A= +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */=0A= +#define CFG_ICSHIFT 9=0A= +#define CFG_DCMASK 0x000001c0 /* Data cache size */=0A= +#define CFG_DCSHIFT 6=0A= +#define CFG_IB 0x00000020 /* Instruction cache block size */=0A= +#define CFG_DB 0x00000010 /* Data cache block size */=0A= +#define CFG_CU 0x00000008 /* Update on Store Conditional */=0A= +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */=0A= +=0A= +/*=0A= + * R4000 primary cache mode=0A= + */=0A= +#define CFG_C_WRITETHROUGH_CACHE 0=0A= +#define CFG_C_UNCACHED 2=0A= +#define CFG_C_NONCOHERENT 3=0A= +#define CFG_C_COHERENTXCL 4=0A= +#define CFG_C_COHERENTXCLW 5=0A= +#define CFG_C_COHERENTUPD 6=0A= +=0A= +/*=0A= + * R4000 cache operations (should be in assembler...?)=0A= + */=0A= +#if defined(CPU_R5000)=0A= +#define InvAllScache 0x03 /* 0 3 */=0A= +#define IndexLoadTagScache 0x07 /* 1 3 */=0A= +#define IndexStoreTagScache 0x0b /* 2 3 */=0A= +#define PageInvScache 0x17 /* 5 3 */=0A= +#endif=0A= +#define Index_Invalidate_I 0x0 /* 0 0 = */=0A= +#define Index_Writeback_Inv_D 0x1 /* 0 1 = */=0A= +#define Index_Invalidate_SI 0x2 /* 0 2 = */=0A= +#define Index_Writeback_Inv_SD 0x3 /* 0 3 = */=0A= +#define Index_Load_Tag_I 0x4 /* 1 0 = */=0A= +#define Index_Load_Tag_D 0x5 /* 1 1 = */=0A= +#define Index_Load_Tag_SI 0x6 /* 1 2 = */=0A= +#define Index_Load_Tag_SD 0x7 /* 1 3 = */=0A= +#define Index_Store_Tag_I 0x8 /* 2 0 = */=0A= +#define Index_Store_Tag_D 0x9 /* 2 1 = */=0A= +#define Index_Store_Tag_SI 0xA /* 2 2 = */=0A= +#define Index_Store_Tag_SD 0xB /* 2 3 = */=0A= +#define Create_Dirty_Exc_D 0xD /* 3 1 = */=0A= +#define Create_Dirty_Exc_SD 0xF /* 3 3 = */=0A= +#define Hit_Invalidate_I 0x10 /* 4 0 = */=0A= +#define Hit_Invalidate_D 0x11 /* 4 1 = */=0A= +#define Hit_Invalidate_SI 0x12 /* 4 2 = */=0A= +#define Hit_Invalidate_SD 0x13 /* 4 3 = */=0A= +#define Hit_Writeback_Inv_D 0x15 /* 5 1 = */=0A= +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 = */=0A= +#define Fill_I 0x14 /* 5 0 = */=0A= +#define Hit_Writeback_D 0x19 /* 6 1 = */=0A= +#define Hit_Writeback_SD 0x1B /* 6 3 = */=0A= +#define Hit_Writeback_I 0x18 /* 6 0 = */=0A= +#define Hit_Set_Virtual_SI 0x1E /* 7 2 = */=0A= +#define Hit_Set_Virtual_SD 0x1F /* 7 3 = */=0A= +=0A= +#endif=0A= +=0A= +/*=0A= +** TLB resource defines=0A= +*/=0A= +=0A= +#if defined(CPU_R32364) =0A= +#define N_TLB_ENTRIES 16=0A= +#endif =0A= +=0A= +#if defined(CPU_R4000)=0A= +#define N_TLB_ENTRIES 48=0A= +#endif=0A= +=0A= +#if defined (CPU_R32364)=0A= +#define TLBHI_VPN2MASK 0xffffe000=0A= +#define TLBHI_PIDMASK 0x000000ff=0A= +#define TLBHI_NPID 256=0A= +=0A= +#define TLBLO_PFNMASK 0x03ffffc0=0A= +#define TLBLO_PFNSHIFT 6=0A= +#define TLBLO_D 0x00000004 /* writeable */=0A= +#define TLBLO_V 0x00000002 /* valid bit */=0A= +#define TLBLO_G 0x00000001 /* global access bit */=0A= +#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */=0A= +#define TLBLO_CSHIFT 3=0A= +=0A= +#define TLBLO_UNCACHED (CFG_C_UNCACHED< k, 1 =3D> u = */=0A= +#define SR_IEO 0x00000010 /* old interrupt enable, 1 =3D> enable = */=0A= +#define SR_KUP 0x00000008 /* prev kernel/user, 0 =3D> k, 1 =3D> u = */=0A= +#define SR_IEP 0x00000004 /* prev interrupt enable, 1 =3D> enable = */=0A= +#define SR_KUC 0x00000002 /* cur kernel/user, 0 =3D> k, 1 =3D> u = */=0A= +#define SR_IEC 0x00000001 /* cur interrupt enable, 1 =3D> enable = */=0A= +#endif=0A= +=0A= +#if defined S364 /* (CPU_R32364) */=0A= +#define SR_CUMASK 0xf0000000 /* coproc usable bits */=0A= +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */=0A= +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */=0A= +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */=0A= +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */=0A= +=0A= +/* defines for R32364 processor */=0A= +#define SR_NBL 0x08000000 /* Non Blocking Load */=0A= +#define SR_RE 0X02000000 /* Reverse Endianness */=0A= +#define SR_DL 0x01000000 /* Data Cache Locking */=0A= +#define SR_IL 0x00800000 /* Instruction Cache Locking */=0A= +=0A= +#define SR_BEV 0x00400000 /* Use boot exception vectors */=0A= +#define SR_SR 0x00100000 /* Soft reset */=0A= +#define SR_CH 0x00040000 /* Cache hit */=0A= +#define SR_CE 0x00020000 /* Use cache ECC */=0A= +#define SR_DE 0x00010000 /* Disable cache exceptions */=0A= +=0A= +/*=0A= +** status register interrupt masks and bits=0A= +*/=0A= +=0A= +#define SR_IMASK 0x0000ff00 /* Interrupt mask */=0A= +#define SR_IMASK8 0x00000000 /* mask level 8 */=0A= +#define SR_IMASK7 0x00008000 /* mask level 7 */=0A= +#define SR_IMASK6 0x0000c000 /* mask level 6 */=0A= +#define SR_IMASK5 0x0000e000 /* mask level 5 */=0A= +#define SR_IMASK4 0x0000f000 /* mask level 4 */=0A= +#define SR_IMASK3 0x0000f800 /* mask level 3 */=0A= +#define SR_IMASK2 0x0000fc00 /* mask level 2 */=0A= +#define SR_IMASK1 0x0000fe00 /* mask level 1 */=0A= +#define SR_IMASK0 0x0000ff00 /* mask level 0 */=0A= +=0A= +#define SR_IMASKSHIFT 8=0A= +=0A= +#define SR_IBIT8 0x00008000 /* bit level 8 */=0A= +#define SR_IBIT7 0x00004000 /* bit level 7 */=0A= +#define SR_IBIT6 0x00002000 /* bit level 6 */=0A= +#define SR_IBIT5 0x00001000 /* bit level 5 */=0A= +#define SR_IBIT4 0x00000800 /* bit level 4 */=0A= +#define SR_IBIT3 0x00000400 /* bit level 3 */=0A= +#define SR_IBIT2 0x00000200 /* bit level 2 */=0A= +#define SR_IBIT1 0x00000100 /* bit level 1 */=0A= +=0A= +#define SR_KSMASK 0x00000016 /* Kernel mode mask */=0A= +#define SR_KSUSER 0x00000000 /* User Mode */=0A= +#define SR_KSKERNEL 0x00000016 /* Kernel Mode */=0A= +=0A= +#define SR_ERL 0x00000004 /* Error level */=0A= +#define SR_EXL 0x00000002 /* Exception level */=0A= +#define SR_IE 0x00000001 /* Interrupts enabled */=0A= +#define NOT_SR_IEC 0xfffffffe /* assembler problem with = li=0A= +~SR_IEC */=0A= +=0A= +/* R32364 Cache locking bits */=0A= +#define SR_ICACHELOCK 0x00800000=0A= +#define SR_DCACHELOCK 0x01000000=0A= +=0A= +#endif /* CPU_R32364 */=0A= +=0A= +#if defined(CPU_R4000)=0A= +#define SR_CUMASK 0xf0000000 /* coproc usable bits */=0A= +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */=0A= +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */=0A= +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */=0A= +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */=0A= +=0A= +#define SR_RP 0x08000000 /* Reduced power operation */=0A= +#define SR_FR 0x04000000 /* Additional floating pt registers */=0A= +#define SR_RE 0x02000000 /* Reverse endian in user mode */=0A= +=0A= +#define SR_BEV 0x00400000 /* Use boot exception vectors */=0A= +#define SR_TS 0x00200000 /* TLB shutdown */=0A= +#define SR_SR 0x00100000 /* Soft reset */=0A= +#define SR_CH 0x00040000 /* Cache hit */=0A= +#define SR_CE 0x00020000 /* Use cache ECC */=0A= +#define SR_DE 0x00010000 /* Disable cache exceptions */=0A= +=0A= +/*=0A= +** status register interrupt masks and bits=0A= +*/=0A= +=0A= +#define SR_IMASK 0x0000ff00 /* Interrupt mask */=0A= +#define SR_IMASK8 0x00000000 /* mask level 8 */=0A= +#define SR_IMASK7 0x00008000 /* mask level 7 */=0A= +#define SR_IMASK6 0x0000c000 /* mask level 6 */=0A= +#define SR_IMASK5 0x0000e000 /* mask level 5 */=0A= +#define SR_IMASK4 0x0000f000 /* mask level 4 */=0A= +#define SR_IMASK3 0x0000f800 /* mask level 3 */=0A= +#define SR_IMASK2 0x0000fc00 /* mask level 2 */=0A= +#define SR_IMASK1 0x0000fe00 /* mask level 1 */=0A= +#define SR_IMASK0 0x0000ff00 /* mask level 0 */=0A= +=0A= +#define SR_IMASKSHIFT 8=0A= +=0A= +#define SR_IBIT8 0x00008000 /* bit level 8 */=0A= +#define SR_IBIT7 0x00004000 /* bit level 7 */=0A= +#define SR_IBIT6 0x00002000 /* bit level 6 */=0A= +#define SR_IBIT5 0x00001000 /* bit level 5 */=0A= +#define SR_IBIT4 0x00000800 /* bit level 4 */=0A= +#define SR_IBIT3 0x00000400 /* bit level 3 */=0A= +#define SR_IBIT2 0x00000200 /* bit level 2 */=0A= +#define SR_IBIT1 0x00000100 /* bit level 1 */=0A= +=0A= +#define SR_KSMASK 0x00000018 /* Kernel mode mask */=0A= +#define SR_KSUSER 0x00000010 /* User mode */=0A= +#define SR_KSSUPER 0x00000008 /* Supervisor mode */=0A= +#define SR_KSKERNEL 0x00000000 /* Kernel mode */=0A= +#define SR_ERL 0x00000004 /* Error level */=0A= +#define SR_EXL 0x00000002 /* Exception level */=0A= +#define SR_IE 0x00000001 /* Interrupts enabled */=0A= +=0A= +/* R4650 Cache locking bits */=0A= +#define SR_ICACHELOCK 0x00800000=0A= +#define SR_DCACHELOCK 0x01000000=0A= +=0A= +=0A= +#endif=0A= +#if defined(CPU_R3000)=0A= +#define SR_FR 0x04000000 /* Additional floating point registers */=0A= +#endif=0A= +=0A= +=0A= +=0A= +/*=0A= + * Cause Register=0A= + */=0A= +#define CAUSE_BD 0x80000000 /* Branch delay slot */=0A= +#define CAUSE_CEMASK 0x30000000 /* coprocessor error */=0A= +#define CAUSE_CESHIFT 28=0A= +#define CAUSE_IW 0x01000000 /* Instruction watch */=0A= +#define CAUSE_DW 0x02000000 /* Data watch */=0A= +#define CAUSE_IPE 0x04000000 /* Imprecise exception */=0A= +=0A= +=0A= +#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */=0A= +#define CAUSE_IPSHIFT 8=0A= +=0A= +/* Notice: Watch Exception if Exc. Code is 23 is not included in the = mask=0A= + * for R32364.=0A= + */=0A= +#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */=0A= +#define CAUSE_EXCSHIFT 2=0A= +=0A= +#ifndef XDS=0A= +/*=0A= +** Coprocessor 0 registers=0A= +*/=0A= +=0A= +/* Evelyn, 12/12/94, for P3 */=0A= +#define C0_IBASE $0 /* I base */=0A= +#define C0_IBOUND $1 /* I bound */=0A= +=0A= +#define C0_INX $0 /* tlb index */=0A= +#define C0_RAND $1 /* tlb random */=0A= +#if defined(CPU_R3000)=0A= +#define C0_TLBLO $2 /* tlb entry low */=0A= +#define C0_BUSCTRL $2 /* bus control R3041 specific */=0A= +#define C0_CONFIG $3 /* cache config */=0A= +#define C0_CTXT $4 /* tlb context */=0A= +#define C0_BADVADDR $8 /* bad virtual address */=0A= +#define C0_COUNT $9 /* count R3041 specific */=0A= +#define C0_PORTSIZE $10 /* port size R3041 specific */=0A= +#define C0_TLBHI $10 /* tlb entry hi */=0A= +#define C0_COMPARE $11 /* compare R3041 specific */=0A= +#define C0_SR $12 /* status register */=0A= +#define C0_CAUSE $13 /* exception cause */=0A= +#define C0_EPC $14 /* exception pc */=0A= +#define C0_PRID $15 /* revision identifier */=0A= +#endif=0A= +=0A= +#if defined(S364) /*(CPU_R32364) */=0A= +#define C0_RANDOM $1=0A= +#define C0_TLBLO0 $2 /* tlb entry low 0 */=0A= +#define C0_TLBLO1 $3 /* tlb entry low 1 */=0A= +#define C0_CTXT $4 /* tlb context */=0A= +#define C0_PAGEMASK $5 /* tlb page mask */=0A= +#define C0_WIRED $6 /* number of wired tlb entries */=0A= +=0A= +#define C0_INX $0 /* tlb index */=0A= +#define C0_BADVADDR $8 /* bad virtual address */=0A= +#define C0_COUNT $9 /* timer count */=0A= +#define C0_TLBHI $10 /* tlb entry hi */=0A= +#define C0_COMPARE $11 /* timer comparator */=0A= +#define C0_SR $12 /* status register */=0A= +#define C0_CAUSE $13 /* exception cause */=0A= +#define C0_EPC $14 /* exception pc */=0A= +#define C0_PRID $15 /* revision identifier */=0A= +#define C0_CONFIG $16 /* configuration register */=0A= +=0A= +#define C0_IWATCH $18 /* Instr brk pt Virtual add. */=0A= +#define C0_DWATCH $19 /* Data brk pt Virtual add. */=0A= +=0A= +#define C0_IEPC $22 /* Imprecise Exception pc */=0A= +#define C0_DEPC $23 /* Debug Exception pc */=0A= +#define C0_DEBUG $24 /* Debug control/status reg */=0A= +=0A= +#define C0_ECC $26 /* primary cache Parity control */=0A= +#define C0_CACHEERR $27 /* cache error status */=0A= +#define C0_TAGLO $28 /* cache tag lo */=0A= +#define C0_TAGHI $29=0A= +#define C0_ERRPC $30 /* cache error pc */=0A= +#endif /* CPU_R32364 */=0A= +=0A= +#if defined(CPU_R4000)=0A= +=0A= +/* Evelyn, 12/12/94, for P3 */=0A= +#define C0_DBASE $2 /* D base */=0A= +#define C0_DBOUND $3 /* D bound */=0A= +=0A= +#define C0_TLBLO0 $2 /* tlb entry low 0 */=0A= +#define C0_TLBLO1 $3 /* tlb entry low 1 */=0A= +#define C0_CTXT $4 /* tlb context */=0A= +#define C0_PAGEMASK $5 /* tlb page mask */=0A= +#define C0_WIRED $6 /* number of wired tlb entries */=0A= +=0A= +#define C0_BADVADDR $8 /* bad virtual address */=0A= +#define C0_COUNT $9 /* cycle count */=0A= +#define C0_TLBHI $10 /* tlb entry hi */=0A= +#define C0_COMPARE $11 /* cyccle count comparator */=0A= +#define C0_SR $12 /* status register */=0A= +#define C0_CAUSE $13 /* exception cause */=0A= +#define C0_EPC $14 /* exception pc */=0A= +#define C0_PRID $15 /* revision identifier */=0A= +#define C0_CONFIG $16 /* configuration register */=0A= +=0A= +/* Evelyn, 12/12/94, for P3 */=0A= +#define C0_CALG $17 /* Calg rigister */=0A= +#define C0_IWATCH $18 /* IWatch register */=0A= +#define C0_DWATCH $19 /* DWatch register */=0A= +=0A= +#define C0_LLADDR $17 /* linked load address */=0A= +#define C0_WATCHLO $18 /* watchpoint trap register */=0A= +#define C0_WATCHHI $19 /* watchpoint trap register */=0A= +#define C0_XCTXT $20 /* extended tlb context */=0A= +#define C0_ECC $26 /* secondary cache ECC control */=0A= +#define C0_CACHEERR $27 /* cache error status */=0A= +#define C0_TAGLO $28 /* cache tag lo */=0A= +#define C0_TAGHI $29 /* cache tag hi */=0A= +#define C0_ERRPC $30 /* cache error pc */=0A= +#endif=0A= +#endif =0A= +#endif /* defined(__IDTCPU_H__) */=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/idthdr.h = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/idthdr.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/idthdr.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/idthdr.h = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,53 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Some macros. Though they are already defined else where in the = linux=0A= + * tree, they are once again declared here for the ease of syncing = up with=0A= + * IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef XDS=0A= +=0A= +#define FRAME(name,frm_reg,offset,ret_reg) \=0A= + .globl name; \=0A= + .ent name; \=0A= +name:; \=0A= + .frame frm_reg,offset,ret_reg=0A= +=0A= +#define ENDFRAME(name) .end name=0A= +=0A= +#else=0A= +=0A= +#define FRAME(name,frm_reg,offset,ret_reg) \=0A= +name:=0A= +=0A= +#define ENDFRAME(name)=0A= +=0A= +#endif=0A= +=0A= +=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/image.lds.in = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/image.lds.in=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/image.lds.in = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/image.lds.in = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D IMSTART;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32300/EB355/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D BSS_START;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/iregdef.h = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/iregdef.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/iregdef.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/iregdef.h = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,284 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT CPU register definitions. Though the registers are already = defined=0A= + * under asm directory, they are once again declared here for the = ease of=0A= + * syncing up with IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#define r0 $0=0A= +#define r1 $1 /*at assembler temp */=0A= +#define r2 $2 /*v0 return value */=0A= +#define r3 $3 /*v1 return value */=0A= +#define r4 $4 /*a0 argument 0 */=0A= +#define r5 $5 /*a1 argument 1 */=0A= +#define r6 $6=0A= +#define r7 $7=0A= +#define r8 $8=0A= +#define r9 $9=0A= +#define r10 $10=0A= +#define r11 $11=0A= +#define r12 $12=0A= +#define r13 $13=0A= +=0A= +#define r14 $14=0A= +#define r15 $15=0A= +#define r16 $16 /*s0 called saved */=0A= +#define r17 $17=0A= +#define r18 $18=0A= +#define r19 $19=0A= +#define r20 $20=0A= +#define r21 $21=0A= +#define r22 $22=0A= +#define r23 $23 /*s7 called saved */=0A= +#define r24 $24=0A= +#define r25 $25=0A= +#define r26 $26 /*k0 kernel temp. */=0A= +#define r27 $27 /*k1 "" "" */=0A= +#define r28 $28 /*gp global pointer */=0A= +#define r29 $29 /*sp stack pointer */=0A= +#define r30 $30 /*fp frame pointer */=0A= +#define r31 $31 /*ra return address */=0A= +=0A= +#define fp0 $f0=0A= +#define fp1 $f1=0A= +#define fp2 $f2=0A= +#define fp3 $f3=0A= +#define fp4 $f4=0A= +#define fp5 $f5=0A= +#define fp6 $f6=0A= +#define fp7 $f7=0A= +#define fp8 $f8=0A= +#define fp9 $f9=0A= +#define fp10 $f10=0A= +#define fp11 $f11=0A= +#define fp12 $f12=0A= +#define fp13 $f13=0A= +#define fp14 $f14=0A= +#define fp15 $f15=0A= +#define fp16 $f16=0A= +#define fp17 $f17=0A= +#define fp18 $f18=0A= +#define fp19 $f19=0A= +#define fp20 $f20=0A= +#define fp21 $f21=0A= +#define fp22 $f22=0A= +#define fp23 $f23=0A= +#define fp24 $f24=0A= +#define fp25 $f25=0A= +#define fp26 $f26=0A= +#define fp27 $f27=0A= +#define fp28 $f28=0A= +#define fp29 $f29=0A= +#define fp30 $f30=0A= +#define fp31 $f31=0A= +=0A= +#define fcr0 $0=0A= +#define fcr30 $30=0A= +#define fcr31 $31=0A= +=0A= +#define zero $0 /* wired zero */=0A= +#define AT $at /* assembler temp */=0A= +#define v0 $2 /* return value */=0A= +#define v1 $3=0A= +#define a0 $4 /* argument registers */=0A= +#define a1 $5=0A= +#define a2 $6=0A= +#define a3 $7=0A= +#define t0 $8 /* caller saved */=0A= +#define t1 $9=0A= +#define t2 $10=0A= +#define t3 $11=0A= +#define t4 $12=0A= +#define t5 $13=0A= +#define t6 $14=0A= +#define t7 $15=0A= +#define s0 $16 /* callee saved */=0A= +#define s1 $17=0A= +#define s2 $18=0A= +#define s3 $19=0A= +#define s4 $20=0A= +#define s5 $21=0A= +#define s6 $22=0A= +#define s7 $23=0A= +#define t8 $24 /* code generator */=0A= +#define t9 $25=0A= +#define k0 $26 /* kernel temporary */=0A= +#define k1 $27=0A= +#define gp $28 /* global pointer */=0A= +#define sp $29 /* stack pointer */=0A= +#define s8 $30 /* yet another saved reg for the callee */=0A= +#define fp $30 /* frame pointer - this is being phased out by MIPS = */=0A= +#define ra $31 /* return address */=0A= +=0A= +=0A= +/*=0A= + * register names=0A= + */=0A= +#define R_R0 0=0A= +#define R_R1 1=0A= +#define R_R2 2=0A= +#define R_R3 3=0A= +#define R_R4 4=0A= +#define R_R5 5=0A= +#define R_R6 6=0A= +#define R_R7 7=0A= +#define R_R8 8=0A= +#define R_R9 9=0A= +#define R_R10 10=0A= +#define R_R11 11=0A= +#define R_R12 12=0A= +#define R_R13 13=0A= +#define R_R14 14=0A= +#define R_R15 15=0A= +#define R_R16 16=0A= +#define R_R17 17=0A= +#define R_R18 18=0A= +#define R_R19 19=0A= +#define R_R20 20=0A= +#define R_R21 21=0A= +#define R_R22 22=0A= +#define R_R23 23=0A= +#define R_R24 24=0A= +#define R_R25 25=0A= +#define R_R26 26=0A= +#define R_R27 27=0A= +#define R_R28 28=0A= +#define R_R29 29=0A= +#define R_R30 30=0A= +#define R_R31 31=0A= +#define R_F0 32=0A= +#define R_F1 33=0A= +#define R_F2 34=0A= +#define R_F3 35=0A= +#define R_F4 36=0A= +#define R_F5 37=0A= +#define R_F6 38=0A= +#define R_F7 39=0A= +#define R_F8 40=0A= +#define R_F9 41=0A= +#define R_F10 42=0A= +#define R_F11 43=0A= +#define R_F12 44=0A= +#define R_F13 45=0A= +#define R_F14 46=0A= +#define R_F15 47=0A= +#define R_F16 48=0A= +#define R_F17 49=0A= +#define R_F18 50=0A= +#define R_F19 51=0A= +#define R_F20 52=0A= +#define R_F21 53=0A= +#define R_F22 54=0A= +#define R_F23 55=0A= +#define R_F24 56=0A= +#define R_F25 57=0A= +#define R_F26 58=0A= +#define R_F27 59=0A= +#define R_F28 60=0A= +#define R_F29 61=0A= +#define R_F30 62=0A= +#define R_F31 63=0A= +#define NCLIENTREGS 64=0A= +#define R_EPC 64=0A= +#define R_MDHI 65=0A= +#define R_MDLO 66=0A= +#define R_SR 67=0A= +#define R_CAUSE 68=0A= +#define R_TLBHI 69=0A= +#ifdef CPU_R4000=0A= +#define R_TLBLO0 70=0A= +#else=0A= +#define R_TLBLO 70=0A= +#endif=0A= +#define R_BADVADDR 71=0A= +#define R_INX 72=0A= +#define R_RAND 73=0A= +#define R_CTXT 74=0A= +#define R_EXCTYPE 75=0A= +#define R_MODE 76=0A= +#define R_PRID 77=0A= +#define R_FCSR 78=0A= +#define R_FEIR 79=0A= +#ifdef CPU_R4000=0A= +#define R_TLBLO1 80=0A= +#define R_PAGEMASK 81=0A= +#define R_WIRED 82=0A= +#define R_COUNT 83=0A= +#define R_COMPARE 84=0A= +#define R_CONFIG 85=0A= +#define R_LLADDR 86=0A= +#define R_WATCHLO 87=0A= +#define R_WATCHHI 88=0A= +#define R_ECC 89=0A= +#define R_CACHEERR 90=0A= +#define R_TAGLO 91=0A= +#define R_TAGHI 92=0A= +#define R_ERRPC 93=0A= +#endif=0A= +=0A= +#ifdef CPU_R4000=0A= +#define NREGS 94=0A= +#else=0A= +#define NREGS 80=0A= +#endif=0A= +=0A= +/*=0A= + * compiler defined bindings=0A= + */=0A= +#define R_ZERO R_R0=0A= +#define R_AT R_R1=0A= +#define R_V0 R_R2=0A= +#define R_V1 R_R3=0A= +#define R_A0 R_R4=0A= +#define R_A1 R_R5=0A= +#define R_A2 R_R6=0A= +#define R_A3 R_R7=0A= +#define R_T0 R_R8=0A= +#define R_T1 R_R9=0A= +#define R_T2 R_R10=0A= +#define R_T3 R_R11=0A= +#define R_T4 R_R12=0A= +#define R_T5 R_R13=0A= +#define R_T6 R_R14=0A= +#define R_T7 R_R15=0A= +#define R_S0 R_R16=0A= +#define R_S1 R_R17=0A= +#define R_S2 R_R18=0A= +#define R_S3 R_R19=0A= +#define R_S4 R_R20=0A= +#define R_S5 R_R21=0A= +#define R_S6 R_R22=0A= +#define R_S7 R_R23=0A= +#define R_T8 R_R24=0A= +#define R_T9 R_R25=0A= +#define R_K0 R_R26=0A= +#define R_K1 R_R27=0A= +#define R_GP R_R28=0A= +#define R_SP R_R29=0A= +#define R_FP R_R30=0A= +#define R_RA R_R31=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/Makefile = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/Makefile = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,134 @@=0A= +#######################################################################= ########=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile create a compressed zImage or Rommable rImage=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +#=0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +# =0A= +# =0A= +#######################################################################= ########=0A= +=0A= +#######################################################################= ########=0A= +# The following is taken from IDT/Sim Makefile=0A= +#######################################################################= ######=0A= +TARGET=3D355=0A= +=0A= +# following refers to size of the DRAM space.=0A= +# These are values for the switch DRAMSZ.=0A= +SRAM_ONLY=3D1=0A= +SDRAM_ONLY=3D2=0A= +SRAM_N_SDRAM=3D3=0A= +SDRAM_N_SRAM=3D4=0A= +=0A= +MB16=3D1=0A= +MB32=3D2=0A= +MB64=3D3=0A= +MB128=3D4=0A= +MB32SO=3D5=0A= +=0A= +FLASH_2M=3D0=0A= +FLASH_4M=3D1=0A= +FLASH_8M=3D2=0A= +=0A= +MACH=3D -DS$(TARGET) -DEB355 -DS364 -DCPU_R32364 = -DMEMCFG=3D$(SDRAM_ONLY) -DDRAMSZ=3D$(MB32SO) = -DFLASHSZ=3D$(FLASH_8M)=0A= +COMMSWITCHES =3D $(INCDIRS) $(MACH)=0A= +#***************** END IDT/Sim Makefile = #####################################=0A= +ZDEBUG=3D0=0A= +export ZDEBUG=0A= +=0A= +# working space for gunzip:=0A= +FREE_RAM :=3D 0x80C00000=0A= +END_RAM :=3D 0x80E00000=0A= +=0A= +KERNELCONFIG :=3D $(TOPDIR)/.config=0A= +include $(KERNELCONFIG)=0A= +=0A= +SIZE =3D $(CROSS_COMPILE)size=0A= +=0A= +O_FORMAT =3D $(shell $(OBJDUMP) -i | head -2 | grep elf32)=0A= +=0A= +SYSTEM :=3D $(TOPDIR)/vmlinux=0A= +ZBSS :=3D 0x800A0000=0A= +=0A= +ZIMSTART :=3D $(CONFIG_IDT_ZIMAGE_ADDR)=0A= +RIMSTART :=3D 0x9FC00000=0A= +=0A= +LOADADDR :=3D 0x$(shell $(NM) $(SYSTEM) | grep "A _text" |cut -f1 = -d' ')=0A= +KERNEL_ENTRY :=3D $(shell $(OBJDUMP) -f $(SYSTEM) | sed -n -e = 's/^start address //p')=0A= +=0A= +#######################################################################= #############=0A= +ZIMFLAGS =3D s/IMSTART/$(ZIMSTART)/;s/BSS_START/$(ZBSS)/=0A= +RIMFLAGS =3D s/IMSTART/$(RIMSTART)/;s/BSS_START/$(ZBSS)/=0A= +CFLAGS :=3D -fno-pic -nostdinc -G 0 -mno-abicalls -fno-pic -pipe = -I$(TOPDIR)/include=0A= +AFLAGS :=3D -D__ASSEMBLY__ $(CFLAGS)=0A= +=0A= +#######################################################################= #############=0A= +OBJECTS=3D $(obj)/piggy.o $(obj)/head.o $(obj)/misc.o=0A= +ifneq ($(ZDEBUG),0)=0A= +OBJECTS +=3D $(obj)/uart16550.o=0A= +endif=0A= +=0A= +$(obj)/zImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)=0A= + @sed "$(ZIMFLAGS)" < $< > $@=0A= +=0A= +$(obj)/rImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)=0A= + @sed "$(RIMFLAGS)" < $< > $@=0A= +=0A= +$(obj)/piggy.o: $(SYSTEM) $(obj)/Makefile=0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(SYSTEM) = $(SYSTEM).bin=0A= + gzip -f -9 < $(SYSTEM).bin > $(SYSTEM).gz=0A= + echo "O_FORMAT: " $(O_FORMAT); =0A= + $(LD) -r -b binary --oformat $(O_FORMAT) -o $(obj)/piggy.o = $(SYSTEM).gz=0A= + rm -f $(SYSTEM).bin $(SYSTEM).gz=0A= +=0A= +$(obj)/head.o: $(obj)/head.S $(SYSTEM) $(obj)/Makefile=0A= + $(CC) $(AFLAGS) -DKERNEL_ENTRY=3D$(KERNEL_ENTRY) -c $(obj)/head.S -o = $(obj)/head.o=0A= +=0A= +$(obj)/misc.o: $(obj)/misc.c $(obj)/Makefile=0A= + $(CC) $(CFLAGS) -DLOADADDR=3D$(LOADADDR) -DFREE_RAM=3D$(FREE_RAM) = -DEND_RAM=3D$(END_RAM) \=0A= + -c $< -DZDEBUG=3D$(ZDEBUG) -o $(obj)/misc.o=0A= +=0A= +$(obj)/uart16550.o: $(obj)/uart16550.c $(KERNELCONFIG)=0A= + $(CC) $(CFLAGS) -c $< -o $(obj)/uart16550.o=0A= +=0A= +$(obj)/csu_idt.o: $(obj)/csu_idt.S Makefile $(SYSTEM)=0A= + $(CC) $(AFLAGS) $(COMMSWITCHES) -c $< -o $(obj)/csu_idt.o=0A= +=0A= +zImage: $(obj)/zImage.lds $(SYSTEM) $(OBJECTS)=0A= + $(LD) -T$(obj)/zImage.lds -o $(TOPDIR)/zImage $(OBJECTS)=0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/zImage = $(TOPDIR)/zImage.bin=0A= + $(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 \=0A= + $(TOPDIR)/zImage.bin $(TOPDIR)/zImage.prm=0A= + $(SIZE) $(TOPDIR)/zImage |awk -F" " '{ print $$4 "\t" $$5 }' > = $(TOPDIR)/zImage.size=0A= + rm -f *.o=0A= +=0A= +rImage: $(obj)/rImage.lds $(OBJECTS) $(obj)/csu_idt.o $(SYSTEM)=0A= + @rm -f $(TOPDIR)/*.prm=0A= + $(LD) -T$(obj)/rImage.lds -o $(TOPDIR)/rImage $(obj)/csu_idt.o = $(OBJECTS) =0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/rImage = $(TOPDIR)/rImage.bin=0A= + $(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 \=0A= + $(TOPDIR)/rImage.bin $(TOPDIR)/rImage.prm=0A= + $(SIZE) $(TOPDIR)/rImage |awk -F" " '{ print $$4 "\t" $$5 }' > = $(TOPDIR)/rImage.size=0A= + rm -f *.o=0A= +clean:=0A= + rm -f *.o $(TOPDIR)/zImage $(TOPDIR)/rImage $(TOPDIR)/*.prm = $(TOPDIR)/rImage.size $(TOPDIR)/zImage.size=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/misc.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/misc.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/misc.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/misc.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,341 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Code to un-compress linux image=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +=0A= +/*=0A= + * gzip declarations=0A= + */=0A= +#define OF(args) args=0A= +#define STATIC static=0A= +#define memzero(s, n) memset ((s), 0, (n))=0A= +typedef unsigned char uch;=0A= +typedef unsigned short ush;=0A= +typedef unsigned long ulg;=0A= +#define WSIZE 0x8000 /* Window size must be at least 32k, */=0A= + /* and a power of two */=0A= +static uch *inbuf; /* input buffer */=0A= +static uch window[WSIZE]; /* Sliding window buffer */=0A= +=0A= +/* gzip flag byte */=0A= +#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */=0A= +#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part = gzip file */=0A= +#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */=0A= +#define ORIG_NAME 0x08 /* bit 3 set: original file name present = */=0A= +#define COMMENT 0x10 /* bit 4 set: file comment present */=0A= +#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */=0A= +#define RESERVED 0xC0 /* bit 6,7: reserved */=0A= +=0A= +=0A= +static unsigned insize; /* valid bytes in inbuf */=0A= +static unsigned inptr; /* index of next byte to be processed in inbuf = */=0A= +static unsigned outcnt; /* bytes in output buffer */=0A= +=0A= +void variable_init(void);=0A= +#if ZDEBUG > 0=0A= +static void puts(const char *);=0A= +extern void putc_init(void);=0A= +extern void putc(unsigned char c);=0A= +#endif=0A= +static int fill_inbuf(void);=0A= +static void flush_window(void);=0A= +static void error(char *m);=0A= +static void gzip_mark(void **);=0A= +static void gzip_release(void **);=0A= +=0A= +extern char input_data[];=0A= +//extern int input_len;=0A= +extern char input_data_end[];=0A= +=0A= +=0A= +#if ZDEBUG > 0=0A= +void int2hex(unsigned long val)=0A= +{=0A= + unsigned char buf[10];=0A= + int i;=0A= + for (i =3D 7; i >=3D 0; i--)=0A= + {=0A= + buf[i] =3D "0123456789ABCDEF"[val & 0x0F];=0A= + val >>=3D 4;=0A= + }=0A= + buf[8] =3D '\0';=0A= + puts(buf);=0A= +}=0A= +#endif=0A= +=0A= +static unsigned long byte_count;=0A= +=0A= +int get_byte(void)=0A= +{=0A= +#if ZDEBUG > 1=0A= + static int printCnt;=0A= +#endif=0A= + unsigned char c =3D (inptr < insize ? inbuf[inptr++] : = fill_inbuf());=0A= + byte_count++;=0A= +=0A= +#if ZDEBUG > 1=0A= + if (printCnt++ < 32)=0A= + {=0A= + puts("byte count =3D ");=0A= + int2hex(byte_count);=0A= + puts(" byte val =3D ");=0A= + int2hex(c);=0A= + puts("\n");=0A= + }=0A= +#endif=0A= + return c;=0A= +}=0A= +=0A= +/* Diagnostic functions */=0A= +#ifdef DEBUG=0A= +# define Assert(cond,msg) {if(!(cond)) error(msg);}=0A= +# define Trace(x) fprintf x=0A= +# define Tracev(x) {if (verbose) fprintf x ;}=0A= +# define Tracevv(x) {if (verbose>1) fprintf x ;}=0A= +# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}=0A= +# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}=0A= +#else=0A= +# define Assert(cond,msg)=0A= +# define Trace(x)=0A= +# define Tracev(x)=0A= +# define Tracevv(x)=0A= +# define Tracec(c,x)=0A= +# define Tracecv(c,x)=0A= +#endif=0A= +=0A= +/*=0A= + * This is set up by the setup-routine at boot-time=0A= + */=0A= +=0A= +static long bytes_out;=0A= +static uch *output_data;=0A= +static unsigned long output_ptr;=0A= +=0A= +=0A= +static void *malloc(int size);=0A= +static void free(void *where);=0A= +static void error(char *m);=0A= +static void gzip_mark(void **);=0A= +static void gzip_release(void **);=0A= +=0A= +static unsigned long free_mem_ptr;=0A= +static unsigned long free_mem_end_ptr;=0A= +=0A= +#include "../../../../../../lib/inflate.c"=0A= +=0A= +static void *malloc(int size)=0A= +{=0A= + void *p;=0A= +=0A= + if (size < 0)=0A= + error("Malloc error\n");=0A= + if (free_mem_ptr <=3D 0) error("Memory error\n");=0A= +=0A= + free_mem_ptr =3D (free_mem_ptr + 3) & ~3; /* Align */=0A= +=0A= + p =3D (void *) free_mem_ptr;=0A= + free_mem_ptr +=3D size;=0A= +=0A= + if (free_mem_ptr >=3D free_mem_end_ptr)=0A= + error("\nOut of memory\n");=0A= +=0A= + return p;=0A= +}=0A= +=0A= +static void free(void *where)=0A= +{ /* Don't care */=0A= +}=0A= +=0A= +static void gzip_mark(void **ptr)=0A= +{=0A= + *ptr =3D (void *) free_mem_ptr;=0A= +}=0A= +=0A= +static void gzip_release(void **ptr)=0A= +{=0A= + free_mem_ptr =3D (long) *ptr;=0A= +}=0A= +#if ZDEBUG > 0=0A= +static void puts(const char *s)=0A= +{=0A= + while (*s) {=0A= + if (*s =3D=3D 10)=0A= + putc(13);=0A= + putc(*s++);=0A= + }=0A= +}=0A= +#endif=0A= +void *memset(void *s, int c, size_t n)=0A= +{=0A= + int i;=0A= + char *ss =3D (char *) s;=0A= +=0A= + for (i =3D 0; i < n; i++)=0A= + ss[i] =3D c;=0A= + return s;=0A= +}=0A= +=0A= +void *memcpy(void *__dest, __const void *__src, size_t __n)=0A= +{=0A= + int i;=0A= + char *d =3D (char *) __dest, *s =3D (char *) __src;=0A= +=0A= + for (i =3D 0; i < __n; i++)=0A= + d[i] =3D s[i];=0A= + return __dest;=0A= +}=0A= +=0A= +/* = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=0A= + * Fill the input buffer. This is called only when the buffer is = empty=0A= + * and at least one byte is really needed.=0A= + */=0A= +static int fill_inbuf(void)=0A= +{=0A= + if (insize !=3D 0) {=0A= + error("ran out of input data\n");=0A= + }=0A= +=0A= + inbuf =3D input_data;=0A= + // insize =3D input_len;=0A= + insize =3D &input_data_end[0] - &input_data[0]; =0A= + inptr =3D 1;=0A= + return inbuf[0];=0A= +}=0A= +=0A= +/* = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=0A= + * Write the output window window[0..outcnt-1] and update crc and = bytes_out.=0A= + * (Used for the decompressed data only.)=0A= + */=0A= +static void flush_window(void)=0A= +{=0A= + ulg c =3D crc; /* temporary variable */=0A= + unsigned n;=0A= + uch *in, *out, ch;=0A= +=0A= + in =3D window;=0A= + out =3D &output_data[output_ptr];=0A= + for (n =3D 0; n < outcnt; n++) {=0A= + ch =3D *out++ =3D *in++;=0A= + c =3D crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8);=0A= + }=0A= + crc =3D c;=0A= + bytes_out +=3D (ulg) outcnt;=0A= + output_ptr +=3D (ulg) outcnt;=0A= + outcnt =3D 0;=0A= +}=0A= +=0A= +#if ZDEBUG > 0=0A= +void check_mem(void)=0A= +{=0A= + int i;=0A= +=0A= + puts("\ncplens =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(cplens[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\ncplext =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(cplext[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\nborder =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(border[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\n");=0A= +}=0A= +#endif=0A= +static void error(char *x)=0A= +{=0A= +#if ZDEBUG > 1=0A= + check_mem();=0A= + puts("\n\n");=0A= + puts(x);=0A= + puts("byte_count =3D ");=0A= + int2hex(byte_count);=0A= + puts("\n");=0A= + puts("\n\n -- Error. System halted");=0A= +#endif=0A= + while (1); /* Halt */=0A= +}=0A= +=0A= +void variable_init(void)=0A= +{=0A= + byte_count =3D 0;=0A= + // output_data =3D (char *) LOADADDR;=0A= + free_mem_ptr =3D FREE_RAM;=0A= + free_mem_end_ptr =3D END_RAM;=0A= +#if ZDEBUG > 1=0A= + puts("output_data 0x");=0A= + int2hex((unsigned long)output_data); puts("\n");=0A= + puts("free_mem_ptr 0x");=0A= + int2hex(free_mem_ptr); puts("\n");=0A= + puts("free_mem_end_ptr 0x");=0A= + int2hex(free_mem_end_ptr); puts("\n");=0A= + puts("input_data 0x");=0A= + int2hex((unsigned long)input_data); puts("\n");=0A= +#endif=0A= +}=0A= +=0A= +int decompress_kernel(void)=0A= +{=0A= +#if ZDEBUG > 0=0A= + putc_init();=0A= +#if ZDEBUG > 2=0A= + check_mem();=0A= +#endif=0A= +#endif=0A= +=0A= + variable_init();=0A= +=0A= + makecrc();=0A= +#if ZDEBUG > 0=0A= + puts("\n");=0A= + puts("Uncompressing Linux... \n");=0A= +#endif=0A= + gunzip(); // ...see inflate.c=0A= +#if ZDEBUG > 0=0A= + puts("Ok, booting the kernel.\n");=0A= +#endif=0A= +=0A= +#if ZDEBUG > 1=0A= + {=0A= + unsigned long *p =3D (unsigned long *)LOADADDR;=0A= + int2hex(p[0]); puts("\n");=0A= + int2hex(p[1]); puts("\n");=0A= + int2hex(p[2]); puts("\n");=0A= + int2hex(p[3]); puts("\n");=0A= + }=0A= +#endif=0A= +=0A= + return 0;=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/rImage.lds = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/rImage.lds=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/rImage.lds = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/rImage.lds = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D 0x9FC00000;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32300/EB355/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D 0x800A0000;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/s355ram.h = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/s355ram.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/s355ram.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/s355ram.h = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,613 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT EB355 SDRAM setup values.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +=0A= +#ifndef __S355RAM__=0A= +#define __S355RAM__=0A= +=0A= +#define SRAM_ONLY 1=0A= +#define SDRAM_ONLY 2=0A= +#define SRAM_N_SDRAM 3=0A= +#define SDRAM_N_SRAM 4=0A= + =0A= +#define MB16 1=0A= +#define MB32 2=0A= +#define MB64 3=0A= +#define MB128 4=0A= +#define MB32SO 5=0A= +=0A= +=0A= +#define EXTU 1=0A= +#define INTU 2=0A= +=0A= +#define RST_CTL_BASE PHYS_TO_K1(0x18008000) /* base address of = reset controller register */=0A= +#define DEV_CTL_BASE PHYS_TO_K1(0x18010000) /* base address of = device controller Registers */=0A= +#define SDRAM_CTL_BASE PHYS_TO_K1(0x18018000) /* base address of = SDRAM controller Registers */=0A= +#define BANYAN_IREG_BASE PHYS_TO_K1(0x18000000) /* all Banyan = internal registers' base address */=0A= +#define GPIO_BASE PHYS_TO_K1(0x18040000)=0A= +#define ERR_CNTL_STATUS 0xb8028030=0A= +#define ERR_CNTL_VALUE 0x000000bf=0A= +=0A= +/*=0A= +** b14:13=3D>01=3DPROM;b12=3D>1=3D do not assert CS during writes; = b11:10=3D>00=3D8 bit port=0A= +** b09:05=3D>0A=3D10 wait states; b04:00=3D>0A=3D 10 wait states=0A= +*/=0A= +=0A= +=0A= +/******** Chip Select 0 Control Register settings ***********/=0A= +#if defined(EB355)=0A= +#define MCR_CS0_BS 0x028A2204=0A= +#define MCR_CS0_TC 0x00000A44=0A= +#else=0A= +#define MCR_CS0_BS 0x01CA333C=0A= +#define MCR_CS0_TC 0x00001FFF=0A= +#endif=0A= +=0A= +/*=0A= +** b14:13=3D>00=3DSRAM;b12=3D>0=3D assert CS during writes; = b11:10=3D>10=3D32 bit port=0A= +** b09:05=3D>FF=3D31 wait states; b04:00=3D>FF=3D 31 wait states.=0A= +** NOTE: wait states should be tuned.=0A= +*/=0A= +=0A= +=0A= +/*#define MCR_CS1_BS 0x28e728e7*/=0A= +#if defined(EB355)=0A= +#define MCR_CS1_BS 0x01C73336=0A= +#define MCR_CS1_TC 0x00000A44=0A= +#else=0A= +#define MCR_CS1_BS 0x01C73336=0A= +#define MCR_CS1_TC 0x00001fff=0A= +#endif=0A= +=0A= +/*=0A= +** b14:13=3D>01=3DI Type;b12=3D>0=3D assert CS during writes; = b11:10=3D>00=3D8 bit port=0A= +** b09:05=3D>FF=3D31 wait states; b04:00=3D>FF=3D 31 wait states=0A= +*/=0A= +#if defined(EB355)=0A= +#define MCR_CS2_BS 0x028A2204=0A= +#ifdef FLASHSZ=0A= +#define MCR_CS2_TC (0x00000A44 | FLASHSZ)=0A= +#else=0A= +#define MCR_CS2_TC 0x00000A46=0A= +#endif=0A= +#else=0A= +#define MCR_CS2_BS 0x0ffffff4=0A= +#define MCR_CS2_TC 0x00001fff=0A= +#endif=0A= +=0A= +#if defined(EB355)=0A= +#define MCR_CS3_BS 0x0ffffff4=0A= +#define MCR_CS3_TC 0x00001fff=0A= +#endif=0A= +=0A= +#define MCR_CS4_BS 0x0ffffff4=0A= +#define MCR_CS4_TC 0x00001fff=0A= +=0A= +#define MCR_CS5_BS 0x0ffffff4=0A= +#define MCR_CS5_TC 0x00001fff=0A= +=0A= +/*=0A= +** physical memory base address register value for Chip Select 0 - = EPROM=0A= +** NOTE: for starters see if you can just set the default value: = 0x1FC00000 Banyan=0A= +*/=0A= +#define MBA_REG0 0x1FC00000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 0 - EPROM - 4MB = Banyan=0A= +*/=0A= +#define MBM_REG0 0xFFC00000=0A= +=0A= +#ifdef EB355=0A= +#define MBA_REG2 0x0C000000=0A= +#ifdef FLASHSZ=0A= +#define MBM_REG2 (~(0x200000 * FLASHSZ - 1))=0A= +#else=0A= +#define MBM_REG2 0xFFC00000=0A= +#endif=0A= +#else=0A= +#define MBA_REG2 0x0C000000=0A= +#define MBM_REG2 0xFC000000=0A= +#endif=0A= +=0A= +#ifdef EB355=0A= +#define MBA_REG3 0x1A000000=0A= +#define MBM_REG3 0xFFFF0000=0A= +#endif=0A= +=0A= +#define MBA_REG4 0x14000000=0A= +#define MBM_REG4 0xFC000000=0A= +=0A= +#define MBA_REG5 0x00000000=0A= +#ifdef EB355=0A= +#define MBM_REG5 0x00000000=0A= +#else=0A= +#define MBM_REG5 0xFC000000=0A= +#endif=0A= +=0A= +#define CPU_BERR_BS 0xFF=0A= +#define IP_BERR_BS 0xFF=0A= +=0A= +=0A= +=0A= +#if MEMCFG =3D=3D SRAM_ONLY=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +*/=0A= +#define MBA_REG1 0x00000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +#elif MEMCFG =3D=3D SDRAM_ONLY || MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/*=0A= +*************************************=0A= +** SDRAM_ONLY or SDRAM_N_SRAM section=0A= +*************************************=0A= +*/=0A= +=0A= +#define APATTERN 0xa5a5a5a5=0A= +=0A= +#if DRAMSZ =3D=3D MB64=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 128MB section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 0MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x00000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 64MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x04000000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFFF00000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +#define SDRAM_CR_BS 0xb95500FF /* old: 0x9EFBOOFF */=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +#define SDRAM_DS_BS 0x2AF800FF=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +#define SDRAM_PC_VAL 0xb95501a0=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +#define SDRAM_RFRSH_CMD 0xb9550090=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +#define SDRAM_MODE_REG 0xAAF80080=0A= +=0A= +#if MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +** at 128MB:=0A= +*/=0A= +#define MBA_REG1 0x08000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +#endif /* #if MEMCFG =3D=3D SDRAM_N_SRAM */=0A= +=0A= +#elif DRAMSZ =3D=3D MB32=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 32MB section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 0MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x00000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 8MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x00800000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFF800000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +#define SDRAM_CR_BS 0xB95500FF /* 11:18:99 0xBAF800FF */=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +#define SDRAM_DS_BS 0x395500FF /* 11:18:99 0x3AF800FF */=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +#define SDRAM_PC_VAL 0xB95501A0 /* 11:18:99 0xBAF801A0 */=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +#define SDRAM_RFRSH_CMD 0xB9550090 /* 11:18:99 0xBAF80090 */=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +#define SDRAM_MODE_REG 0xB9550080 /* 11:18:99 0xBAF80080 */=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x000002A0=0A= +=0A= +#if MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +** at 32MB:=0A= +*/=0A= +#define MBA_REG1 0x04000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +#endif /* MEMCFG =3D=3D SDRAM_N_SRAM */=0A= +#elif DRAMSZ =3D=3D MB32SO=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 32MB SODIMM section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 0MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x00000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 8MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x02000000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFE000000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK 0xFE000000=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +/* for other boards such as S355, EB355=0A= +*/=0A= +#define SDRAM_CR_BS 0x9a281080=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +#define SDRAM_DS_BS 0x1a681080=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +#define SDRAM_PC_VAL 0x1a6810c3=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +=0A= +#define SDRAM_RFRSH_CMD 0x1a681093=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +#define SDRAM_MODE_REG 0x1a681083=0A= +=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x00000271=0A= +=0A= +//#if MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +** at 32MB:=0A= +*/=0A= +#define MBA_REG1 0x02000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +#endif /* MEMCFG =3D=3D SDRAM_N_SRAM */=0A= +=0A= +//#endif /* DRAMSZ =3D=3D MB32SO */=0A= +=0A= +#elif MEMCFG =3D=3D SRAM_N_SDRAM=0A= +=0A= +#define APATTERN 0xa5a5a5a5=0A= +=0A= +/*=0A= +*******************************=0A= +** SRAM and SDRAM section=0A= +*******************************=0A= +*/=0A= +#if DRAMSZ =3D=3D MB128=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 128MB section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +*/=0A= +#define MBA_REG1 0x00000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 32MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x02000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 64MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x04000000=0A= +/*=0A= +** DRAM BANK2 BASE. 3rd bank at 96MB:=0A= +*/=0A= +#define DRAM_BNK2_BASE 0x06000000=0A= +/*=0A= +** DRAM BANK3 BASE. 4th bank at 128MB:=0A= +*/=0A= +#define DRAM_BNK3_BASE 0x08000000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFE000000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 2 Mask=0A= +*/=0A= +#define DRAM_BNK2_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 3 Mask=0A= +*/=0A= +#define DRAM_BNK3_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +#define SDRAM_CR_BS 0xAAF800FF /* old: 0x9EFBOOFF */=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +#define SDRAM_DS_BS 0x2AF800FF=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +#define SDRAM_PC_VAL 0xAAF801A0=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +#define SDRAM_RFRSH_CMD 0xAAF80090=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +#define SDRAM_MODE_REG 0xAAF80080=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x000000A0=0A= +=0A= +#elif DRAMSZ =3D=3D MB32=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 32MB section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +*/=0A= +#define MBA_REG1 0x00000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 8MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x00800000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 16MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x01000000=0A= +=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFF800000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +#define SDRAM_CR_BS 0xB95500FF /* 11:18:99 0xBAF800FF */=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +#define SDRAM_DS_BS 0x395500FF /* 11:18:99 0x3AF800FF */=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +#define SDRAM_PC_VAL 0xB95501A0 /* 11:18:99 0xBAF801A0 */=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +#define SDRAM_RFRSH_CMD 0xB9550090 /* 11:18:99 0xBAF80090 */=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +#define SDRAM_MODE_REG 0xB9550080 /* 11:18:99 0xBAF80080 */=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x000002A0 /* 11:18:99 0x000000A0 */=0A= +=0A= +#elif DRAMSZ =3D=3D MB32SO=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 32MB section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +*/=0A= +#define MBA_REG1 0x00000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 32MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x02000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 16MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x02100000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFE000000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK 0xFE000000=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +#define SDRAM_CR_BS 0x9a281080=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +#define SDRAM_DS_BS 0x1a681080=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +#define SDRAM_PC_VAL 0x1a6810c3=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +=0A= +#define SDRAM_RFRSH_CMD 0x1a681093=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +=0A= +#define SDRAM_MODE_REG 0x1a681083=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x00000271 /* 11:18:99 0x000000A0 */=0A= +=0A= +=0A= +#else=0A= +#error "unrecognized dram size"=0A= +#endif /* DRAMSZ */=0A= +=0A= +#else=0A= +#error "unrecogized memory configuration parameter"=0A= +#endif /* error */=0A= +=0A= +#endif /* __S355RAM__ */=0A= +=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/s364.h = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/s364.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/s364.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/s364.h 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,156 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * LCD Display routines=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef __S364134__=0A= +#define __S364134__=0A= +/******************************** D E F I N E S = *******************************/=0A= +#ifndef GPIO_BASE=0A= +#ifdef S355=0A= +#define GPIO_BASE PHYS_TO_K1(0x18040000)=0A= +#else=0A= +#define GPIO_BASE PHYS_TO_K1(0x18000600)=0A= +#endif=0A= +#endif=0A= +/*=0A= +** following defines simple and uniform to save and restore context=0A= +** when enrtering and leaving as assemblu language program when = memory=0A= +** and registers are both premiunm.=0A= +*/=0A= +#define SAVE_CNTXT \=0A= + subu sp,64; \=0A= + sw t0,60(sp); \=0A= + sw t1,56(sp); \=0A= + sw t2,52(sp); \=0A= + sw t3,48(sp); \=0A= + sw t4,44(sp); \=0A= + sw t5,40(sp); \=0A= + sw t6,36(sp); \=0A= + sw t7,32(sp); \=0A= + sw t8,28(sp); \=0A= + sw t9,24(sp); \=0A= + sw a0,20(sp); \=0A= + sw a1,16(sp); \=0A= + sw a2,12(sp); \=0A= + sw a3,8(sp); \=0A= + sw ra,4(sp)=0A= +=0A= +#define RSTR_CNTXT \=0A= + lw t0,60(sp); \=0A= + lw t1,56(sp); \=0A= + lw t2,52(sp); \=0A= + lw t3,48(sp); \=0A= + lw t4,44(sp); \=0A= + lw t5,40(sp); \=0A= + lw t6,36(sp); \=0A= + lw t7,32(sp); \=0A= + lw t8,28(sp); \=0A= + lw t9,24(sp); \=0A= + lw a0,20(sp); \=0A= + lw a1,16(sp); \=0A= + lw a2,12(sp); \=0A= + lw a3,8(sp); \=0A= + lw ra,4(sp); \=0A= + add sp,64=0A= +=0A= +/*=0A= +** Following define is to specify a maximum value for a software=0A= +** busy wait counter.=0A= +*/=0A= +=0A= +#define LP_CNT_100NS 1000 /* set this based on processor speed = */=0A= +#define LP_CNT_3S 1000000 /* set this based on processor speed = */=0A= +=0A= +/*=0A= +** Following are other common timer definitions.=0A= +*/=0A= +#ifdef S355=0A= +#define TIMER_BASE PHYS_TO_K1(0x18028000) =0A= +#define TIMEOUT_COUNT 0x00000FFF=0A= +#else=0A= +#define TIMER_BASE PHYS_TO_K1(0x18000700) =0A= +#endif=0A= +#define ENABLE_TIMER 0x1=0A= +#define DISABLE_TIMER 0x0=0A= +#define BIG_VALUE 0xFFFFFFFF=0A= +=0A= +#ifdef S355=0A= +/* There is no DISPLAY on 355 boards*/=0A= +#elif defined(S334)=0A= +/*=0A= +** following few lines define a macro DISPLAY=0A= +** which is used to write a set of 4 characters=0A= +** onto the S334 LED.=0A= +*/=0A= +=0A= +#if defined(EB332)=0A= +#define LED_BASE PHYS_TO_K1(0x10000000)=0A= +#define LED_DIGIT0 0xc=0A= +#define LED_DIGIT1 0x8=0A= +#define LED_DIGIT2 0x4=0A= +#define LED_DIGIT3 0x0=0A= +=0A= +#define LED_CLEAR 0x400=0A= +=0A= +#else=0A= +#define LED_BASE PHYS_TO_K1(0x14000000)=0A= +#define LED_DIGIT0 0xf=0A= +#define LED_DIGIT1 0xb=0A= +#define LED_DIGIT2 0x7=0A= +#define LED_DIGIT3 0x3=0A= +=0A= +#define LED_CLEAR 0x400=0A= +=0A= +#endif=0A= +=0A= +#define DISPLAY(d0, d1, d2, d3) \=0A= + li t6, LED_BASE ;\=0A= + lb t7, LED_CLEAR(t6) ;\=0A= + nop ;\=0A= + li t7, (d0) & 0xff ;\=0A= + sb t7, LED_DIGIT0(t6) ;\=0A= + li t7, (d1) & 0xff ;\=0A= + sb t7, LED_DIGIT1(t6) ;\=0A= + li t7, (d2) & 0xff ;\=0A= + sb t7, LED_DIGIT2(t6) ;\=0A= + li t7, (d3) & 0xff ;\=0A= + sb t7, LED_DIGIT3(t6)=0A= +=0A= +#define LEDCLEAR() \=0A= + li t6, LED_BASE ;\=0A= + lb t7, LED_CLEAR(t6) ;\=0A= + nop=0A= +=0A= +#endif=0A= +=0A= +#define DESTRUCTIVE 1=0A= +#define NONDESTRUCTIVE 0=0A= +=0A= +#endif=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/uart16550.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/uart16550.c=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/uart16550.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/uart16550.c = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,180 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * UART code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +=0A= +#define RC32355_REG_BASE 0xb8000000=0A= +#ifdef __MIPSEB__=0A= +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)=0A= +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)=0A= +#else=0A= +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)=0A= +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)=0A= +#endif=0A= +=0A= +#define BASE RC32300_UART0_BASE=0A= +=0A= +#define MAX_BAUD (CONFIG_IDT_BOARD_FREQ / 16)=0A= +#define REG_OFFSET 0x4=0A= +=0A= +/* =3D=3D=3D CONFIG =3D=3D=3D */=0A= +=0A= +/*=0A= + * #define BASE 0xb2001000=0A= + * #define MAX_BAUD 1152000=0A= + * #define REG_OFFSET 0x10=0A= + */=0A= +#if (!defined(BASE) || !defined(MAX_BAUD) || !defined(REG_OFFSET))=0A= +#error You must define BASE, MAX_BAUD and REG_OFFSET in the = Makefile.=0A= +#endif=0A= +=0A= +#ifndef INIT_SERIAL_PORT=0A= +#define INIT_SERIAL_PORT 1=0A= +#endif=0A= +=0A= +#ifndef DEFAULT_BAUD=0A= +//#define DEFAULT_BAUD UART16550_BAUD_115200=0A= +#define DEFAULT_BAUD UART16550_BAUD_9600=0A= +#endif=0A= +#ifndef DEFAULT_PARITY=0A= +#define DEFAULT_PARITY UART16550_PARITY_NONE=0A= +#endif=0A= +#ifndef DEFAULT_DATA=0A= +#define DEFAULT_DATA UART16550_DATA_8BIT=0A= +#endif=0A= +#ifndef DEFAULT_STOP=0A= +#define DEFAULT_STOP UART16550_STOP_1BIT=0A= +#endif=0A= +=0A= +/* =3D=3D=3D END OF CONFIG =3D=3D=3D */=0A= +=0A= +typedef unsigned char uint8;=0A= +typedef unsigned int uint32;=0A= +=0A= +#define UART16550_BAUD_2400 2400=0A= +#define UART16550_BAUD_4800 4800=0A= +#define UART16550_BAUD_9600 9600=0A= +#define UART16550_BAUD_19200 19200=0A= +#define UART16550_BAUD_38400 38400=0A= +#define UART16550_BAUD_57600 57600=0A= +#define UART16550_BAUD_115200 115200=0A= +=0A= +#define UART16550_PARITY_NONE 0=0A= +#define UART16550_PARITY_ODD 0x08=0A= +#define UART16550_PARITY_EVEN 0x18=0A= +#define UART16550_PARITY_MARK 0x28=0A= +#define UART16550_PARITY_SPACE 0x38=0A= +=0A= +#define UART16550_DATA_5BIT 0x0=0A= +#define UART16550_DATA_6BIT 0x1=0A= +#define UART16550_DATA_7BIT 0x2=0A= +#define UART16550_DATA_8BIT 0x3=0A= +=0A= +#define UART16550_STOP_1BIT 0x0=0A= +#define UART16550_STOP_2BIT 0x4=0A= +=0A= +/* register offset */=0A= +#define OFS_RCV_BUFFER (0*REG_OFFSET)=0A= +#define OFS_TRANS_HOLD (0*REG_OFFSET)=0A= +#define OFS_SEND_BUFFER (0*REG_OFFSET)=0A= +#define OFS_INTR_ENABLE (1*REG_OFFSET)=0A= +#define OFS_INTR_ID (2*REG_OFFSET)=0A= +#define OFS_DATA_FORMAT (3*REG_OFFSET)=0A= +#define OFS_LINE_CONTROL (3*REG_OFFSET)=0A= +#define OFS_MODEM_CONTROL (4*REG_OFFSET)=0A= +#define OFS_RS232_OUTPUT (4*REG_OFFSET)=0A= +#define OFS_LINE_STATUS (5*REG_OFFSET)=0A= +#define OFS_MODEM_STATUS (6*REG_OFFSET)=0A= +#define OFS_RS232_INPUT (6*REG_OFFSET)=0A= +#define OFS_SCRATCH_PAD (7*REG_OFFSET)=0A= +=0A= +#define OFS_DIVISOR_LSB (0*REG_OFFSET)=0A= +#define OFS_DIVISOR_MSB (1*REG_OFFSET)=0A= +=0A= +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))=0A= +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) =3D = z)=0A= +=0A= +static void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 = stop)=0A= +{=0A= + /* disable interrupts */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x0);=0A= + UART16550_WRITE(OFS_INTR_ENABLE, 0);=0A= +=0A= + /* set up baud rate */=0A= + {=0A= + uint32 divisor;=0A= +=0A= + /* set DIAB bit */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x80);=0A= +=0A= + /* set divisor */=0A= + divisor =3D MAX_BAUD / baud;=0A= + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);=0A= + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);=0A= +=0A= + /* clear DIAB bit */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x0);=0A= + }=0A= +=0A= + /* set data format */=0A= + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);=0A= +}=0A= +=0A= +=0A= +void=0A= +putc_init(void)=0A= +{=0A= +#if INIT_SERIAL_PORT=0A= + Uart16550Init(DEFAULT_BAUD, DEFAULT_DATA, DEFAULT_PARITY, = DEFAULT_STOP);=0A= +#endif=0A= +}=0A= +=0A= +void=0A= +putc(unsigned char c)=0A= +{=0A= + while ((UART16550_READ(OFS_LINE_STATUS) &0x20) =3D=3D 0);=0A= + UART16550_WRITE(OFS_SEND_BUFFER, c);=0A= +}=0A= +=0A= +#if 0=0A= +unsigned char=0A= +getc(void)=0A= +{=0A= + while((UART16550_READ(OFS_LINE_STATUS) & 0x1) =3D=3D 0);=0A= + return UART16550_READ(OFS_RCV_BUFFER);=0A= +}=0A= +=0A= +int=0A= +tstc(void)=0A= +{=0A= + return((UART16550_READ(OFS_LINE_STATUS) & 0x01) !=3D 0);=0A= +}=0A= +#endif=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/zImage.lds = idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/zImage.lds=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/boot/zImage.lds = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/boot/zImage.lds = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D 0x8c000000;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32300/EB355/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D 0x800A0000;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/idtIRQ.S = idtlinux/arch/mips/idt-boards/rc32300/EB355/idtIRQ.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/idtIRQ.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/idtIRQ.S 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,75 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Interrupt dispatcher for IDT EB355 boards=0A= + *=0A= + * Copyright 2006 IDT Inc.=0A= + * Author: Integrated Device Technology Inc. rischelp@idt.com=0A= + *=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= + =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= + .text=0A= + .set noreorder=0A= + .set noat=0A= + .align 5=0A= + NESTED(rc32300_IRQ, PT_SIZE, sp)=0A= + SAVE_ALL=0A= + CLI=0A= +=0A= + .set at=0A= + .set noreorder=0A= +=0A= + /* Get the pending interrupts */=0A= + mfc0 t0, CP0_CAUSE=0A= + nop=0A= + =0A= + /* Isolate the allowed ones by anding the irq mask */=0A= + mfc0 t2, CP0_STATUS =0A= + move a1, sp /* need a nop here, hence we anticipate */=0A= + andi t0, CAUSEF_IP =0A= + and t0, t2=0A= + =0A= + /* check for r4k counter/timer IRQ. */=0A= + =0A= + andi t1, t0, CAUSEF_IP7=0A= + beqz t1, 1f=0A= + nop=0A= +=0A= + jal idt_timer_interrupt /* bypass rc32300_irqdispatch */=0A= + li a0, 7=0A= + j ret_from_irq=0A= + nop=0A= +1:=0A= + jal rc32300_irqdispatch=0A= + move a0, t0=0A= + j ret_from_irq=0A= + nop=0A= +=0A= + END(rc32300_IRQ)=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/irq.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/irq.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/irq.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/irq.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,287 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * RC32355 interrupt routines.=0A= + *=0A= + * Copyright 2006 IDT Inc.=0A= + * Author: Integrated Device Technology Inc. rischelp@idt.com=0A= + *=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#undef DEBUG_IRQ=0A= +#ifdef DEBUG_IRQ=0A= +/* note: prints function name for you */=0A= +#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## = args)=0A= +#else=0A= +#define DPRINTK(fmt, args...)=0A= +#endif=0A= +=0A= +extern asmlinkage void rc32300_IRQ(void);=0A= +extern irq_cpustat_t irq_stat [NR_CPUS];=0A= +unsigned int local_bh_count[NR_CPUS];=0A= +unsigned int local_irq_count[NR_CPUS];=0A= +=0A= +static unsigned int startup_irq(unsigned int irq);=0A= +static void end_irq(unsigned int irq_nr);=0A= +static void mask_and_ack_irq(unsigned int irq_nr);=0A= +static void rc32355_enable_irq(unsigned int irq_nr);=0A= +static void rc32355_disable_irq(unsigned int irq_nr);=0A= +=0A= +extern void __init init_generic_irq(void);=0A= +=0A= +#ifdef CONFIG_PM=0A= +extern void counter0_irq(int irq, void *dev_id, struct pt_regs = *regs);=0A= +#endif=0A= +=0A= +typedef struct {=0A= + u32 mask; /* mask of valid bits in pending/mask registers */=0A= + volatile u32 *base_addr;=0A= +} intr_group_t;=0A= +=0A= +static const intr_group_t intr_group[NUM_INTR_GROUPS] =3D {=0A= + { 0x0000003f, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) = },=0A= + { 0x0000ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) = },=0A= + { 0x000003ff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) = },=0A= + { 0x00ffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) = },=0A= + { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) = }=0A= +};=0A= +=0A= +#define READ_PEND(base) (*(base))=0A= +#define READ_MASK(base) (*(base + 1))=0A= +#define WRITE_MASK(base, val) (*(base + 1) =3D (val))=0A= +=0A= +static inline int irq_to_group(unsigned int irq_nr)=0A= +{=0A= + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);=0A= +}=0A= +=0A= +static inline int group_to_ip(unsigned int group)=0A= +{=0A= + return group + 2;=0A= +}=0A= +=0A= +static inline void enable_local_irq(unsigned int ip)=0A= +{=0A= + int ipnum =3D 0x100 << ip;=0A= + clear_c0_cause(ipnum);=0A= + set_c0_status(ipnum);=0A= +}=0A= +=0A= +static inline void disable_local_irq(unsigned int ip)=0A= +{=0A= + int ipnum =3D 0x100 << ip;=0A= + clear_c0_status(ipnum);=0A= +}=0A= +=0A= +static inline void ack_local_irq(unsigned int ip)=0A= +{=0A= + int ipnum =3D 0x100 << ip;=0A= + clear_c0_cause(ipnum);=0A= +}=0A= +=0A= +static void rc32355_enable_irq(unsigned int irq_nr)=0A= +{=0A= + unsigned long flags;=0A= + int ip =3D irq_nr - GROUP0_IRQ_BASE;=0A= + unsigned int group, intr_bit;=0A= + volatile unsigned int *addr;=0A= + =0A= + local_irq_save(flags);=0A= + if (ip < 0)=0A= + enable_local_irq(irq_nr);=0A= + else {=0A= + // calculate group=0A= + group =3D ip >> 5;=0A= + =0A= + // calc interrupt bit within group=0A= + ip -=3D (group << 5);=0A= + intr_bit =3D 1 << ip;=0A= + =0A= + // first enable the IP mapped to this IRQ=0A= + enable_local_irq(group_to_ip(group));=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + // unmask intr within group=0A= + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);=0A= + }=0A= + =0A= + local_irq_restore(flags);=0A= +}=0A= +=0A= +static void rc32355_disable_irq(unsigned int irq_nr)=0A= +{=0A= + unsigned long flags;=0A= + int ip =3D irq_nr - GROUP0_IRQ_BASE;=0A= + unsigned int group, intr_bit, mask;=0A= + volatile unsigned int *addr;=0A= + =0A= + local_irq_save(flags);=0A= + if (ip < 0)=0A= + disable_local_irq(irq_nr);=0A= + else {=0A= + // calculate group=0A= + group =3D ip >> 5;=0A= + =0A= + // calc interrupt bit within group=0A= + ip -=3D group << 5;=0A= + intr_bit =3D 1 << ip;=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + // mask intr within group=0A= + mask =3D READ_MASK(addr);=0A= + mask |=3D intr_bit;=0A= + WRITE_MASK(addr, mask);=0A= + =0A= + /*=0A= + if there are no more interrupts enabled in this=0A= + group, disable corresponding IP=0A= + */=0A= + if (mask =3D=3D intr_group[group].mask)=0A= + disable_local_irq(group_to_ip(group));=0A= + }=0A= + =0A= + local_irq_restore(flags);=0A= +}=0A= +=0A= +static unsigned int startup_irq(unsigned int irq_nr)=0A= +{=0A= + rc32355_enable_irq(irq_nr);=0A= + return 0; =0A= +}=0A= +=0A= +static void shutdown_irq(unsigned int irq_nr)=0A= +{=0A= + rc32355_disable_irq(irq_nr);=0A= + return;=0A= +}=0A= +=0A= +static void mask_and_ack_irq(unsigned int irq_nr)=0A= +{=0A= + rc32355_disable_irq(irq_nr);=0A= + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));=0A= +}=0A= +=0A= +static void end_irq(unsigned int irq_nr)=0A= +{=0A= + int ip =3D irq_nr - GROUP0_IRQ_BASE;=0A= + unsigned int intr_bit, group;=0A= + volatile unsigned int *addr;=0A= + =0A= + if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) = {=0A= + if (ip < 0)=0A= + enable_local_irq(irq_nr);=0A= + else {=0A= + =0A= + group =3D ip >> 5;=0A= + =0A= + // calc interrupt bit within group=0A= + ip -=3D (group << 5);=0A= + intr_bit =3D 1 << ip;=0A= + =0A= + // first enable the IP mapped to this IRQ=0A= + enable_local_irq(group_to_ip(group));=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + // unmask intr within group=0A= + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);=0A= + }=0A= + } =0A= + else {=0A= + printk("warning: end_irq %d did not enable (%x)\n", =0A= + irq_nr, irq_desc[irq_nr].status);=0A= + }=0A= +}=0A= +=0A= +static struct hw_interrupt_type rc32355_irq_type =3D {=0A= + "RC32355",=0A= + startup_irq,=0A= + shutdown_irq,=0A= + rc32355_enable_irq,=0A= + rc32355_disable_irq,=0A= + mask_and_ack_irq,=0A= + end_irq,=0A= + NULL=0A= +};=0A= +=0A= +=0A= +void __init arch_init_irq(void)=0A= +{=0A= + int i;=0A= + =0A= + printk("Initializing IRQ's: %d\n", RC32355_NR_IRQS);=0A= + memset(irq_desc, 0, sizeof(irq_desc));=0A= + set_except_vector(0, rc32300_IRQ);=0A= + =0A= + for (i =3D 0; i < RC32355_NR_IRQS; i++) {=0A= + irq_desc[i].status =3D IRQ_DISABLED;=0A= + irq_desc[i].action =3D NULL;=0A= + irq_desc[i].depth =3D 1;=0A= + irq_desc[i].handler =3D &rc32355_irq_type;=0A= + spin_lock_init(&irq_desc[i].lock);=0A= + }=0A= +}=0A= +=0A= +/* Main Interrupt dispatcher */=0A= +void rc32300_irqdispatch(unsigned long cp0_cause, struct pt_regs = *regs)=0A= +{=0A= + unsigned int ip, pend, group;=0A= + volatile unsigned int *addr;=0A= + =0A= + if ((ip =3D (cp0_cause & 0x7c00))) {=0A= + group =3D 21 - rc32300_clz(ip);=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + =0A= + pend =3D READ_PEND(addr);=0A= + pend &=3D ~READ_MASK(addr); // only unmasked interrupts=0A= + pend =3D 39 - rc32300_clz(pend);=0A= + do_IRQ((group << 5) + pend, regs);=0A= + return;=0A= + } =0A= + else =0A= + return; //spurious interrupt, do nothing....=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/lcd.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/lcd.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/lcd.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/lcd.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,144 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT 79EB355 lcd support.=0A= + *=0A= + * Copyright 2006 IDT Inc.=0A= + * Author: Integrated Device Technology Inc. rischelp@idt.com=0A= + *=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#define LCD_FUNC_SET 0x38=0A= +#define LCD_ENT_MODE 0x06=0A= +#define LCD_DISP_ON_CURS_OFF 0x0C =0A= +#define LCD_DISP_ON_CURS_ON 0x0E =0A= +#define LCD_DISP_CLEAR 0x01=0A= +#define LCD_DDRAM_ADR_SET_0 0x80=0A= +#define LCD_DDRAM_ADR_SET_1 0xC0=0A= +=0A= +#define LCD_MAX_CHAR_PER_LINE 16=0A= +#define LCD_MAX_LINES 2=0A= +=0A= +=0A= +static void delay_lcd_long(void)=0A= +{=0A= + int ii ;=0A= + for (ii =3D 0 ; ii < 0x5FFFF ; ii++)=0A= + ;=0A= +}=0A= +=0A= +=0A= +static void delay_lcd_short(void)=0A= +{=0A= + int ii ;=0A= + for (ii =3D 0 ; ii < 0x1FFFF ; ii++)=0A= + ;=0A= +}=0A= +=0A= +=0A= +int init_lcd(void)=0A= +{=0A= + u8* chLcdBase =3D (u8*)KSEG1ADDR(LCD_BASE);=0A= + =0A= + /*-------------- Reset LCD ---------------------------*/=0A= + =0A= + delay_lcd_long() ;=0A= + =0A= + /* send function select 4 times */=0A= + rc32300_writeb(LCD_FUNC_SET, (unsigned long)chLcdBase);=0A= + delay_lcd_long() ;=0A= + rc32300_writeb(LCD_FUNC_SET, (unsigned long)chLcdBase);=0A= + delay_lcd_long() ;=0A= + rc32300_writeb(LCD_FUNC_SET, (unsigned long)chLcdBase);=0A= + delay_lcd_long() ;=0A= + rc32300_writeb(LCD_FUNC_SET, (unsigned long)chLcdBase);=0A= + delay_lcd_long() ; =0A= + =0A= + =0A= + rc32300_writeb(LCD_ENT_MODE, (unsigned long)chLcdBase);=0A= + delay_lcd_long() ;=0A= +=0A= + rc32300_writeb(LCD_DISP_ON_CURS_OFF, (unsigned long)chLcdBase);=0A= + delay_lcd_long() ;=0A= + =0A= + rc32300_writeb(LCD_DISP_CLEAR, (unsigned long)chLcdBase);=0A= + delay_lcd_long() ;=0A= + =0A= + /* set it to row-0, column-0 */=0A= + rc32300_writeb(LCD_DDRAM_ADR_SET_0, (unsigned long)chLcdBase);=0A= + delay_lcd_long() ;=0A= + =0A= + return 0;=0A= +}=0A= +=0A= +=0A= +int idtprintf(const char *fmt, ...)=0A= +{=0A= + va_list args;=0A= + u8* chLcdData =3D (u8*)KSEG1ADDR((LCD_BASE+1));=0A= + u8* chLcdBase =3D (u8*)KSEG1ADDR(LCD_BASE);=0A= + char str[LCD_MAX_CHAR_PER_LINE * LCD_MAX_LINES];=0A= + int iNumChars, iCharsSent;=0A= + =0A= + va_start(args, fmt);=0A= + vsprintf(str, fmt, args);=0A= + va_end(args);=0A= + =0A= + iNumChars =3D strlen(str);=0A= + =0A= + /* Can't have more characters than what will fit on the display */=0A= + if (iNumChars > (LCD_MAX_CHAR_PER_LINE * LCD_MAX_LINES))=0A= + iNumChars =3D (LCD_MAX_CHAR_PER_LINE * LCD_MAX_LINES) ;=0A= + =0A= + /* first blank out the whole display */=0A= + rc32300_writeb(LCD_DISP_CLEAR, (unsigned long)chLcdBase);=0A= + delay_lcd_long() ;=0A= + =0A= + /* set it to row-0, column-0 */=0A= + rc32300_writeb(LCD_DDRAM_ADR_SET_0, (unsigned long)chLcdBase);=0A= + delay_lcd_long() ;=0A= + =0A= + /* Now display characters one by one*/=0A= + for(iCharsSent =3D 0 ; iCharsSent < iNumChars ; iCharsSent++) {=0A= + if (iCharsSent =3D=3D LCD_MAX_CHAR_PER_LINE ) {=0A= + /* move over to the next line */=0A= + rc32300_writeb(LCD_DDRAM_ADR_SET_1, (unsigned long)chLcdBase); =0A= + delay_lcd_long() ;=0A= + }=0A= + rc32300_writeb(str[iCharsSent], (unsigned long)chLcdData);=0A= + delay_lcd_short() ;=0A= + }=0A= +=0A= + return iNumChars;=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/Makefile = idtlinux/arch/mips/idt-boards/rc32300/EB355/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/Makefile 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,41 @@=0A= +#**********************************************************************= ****=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile for EB355 BSP=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +# =0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR = TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +#=0A= +#**********************************************************************= ****=0A= +#=0A= +=0A= +.S.s:=0A= + $(CPP) $(CFLAGS) $< -o $*.s=0A= +.S.o:=0A= + $(CC) $(CFLAGS) -c $< -o $*.o=0A= +=0A= +obj-y :=3D irq.o lcd.o setup.o idtIRQ.o reset.o prom.o time.o=0A= +obj-$(CONFIG_KGDB) +=3D serial_gdb.o=0A= +obj-$(CONFIG_SERIAL_8250) +=3D serial.o=0A= +subdir-$(CONFIG_IDT_BOOT_NVRAM) +=3D nvram=0A= +obj-$(CONFIG_IDT_BOOT_NVRAM) +=3D nvram/built-in.o=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/Makefile = idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/Makefile = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,40 @@=0A= +#**********************************************************************= ****=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile for nvram driver=0A= +#=0A= +# Copyright 2006 IDT Inc.=0A= +# Author: Integrated Device Technology Inc. rischelp@idt.com=0A= +#=0A= +# =0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR = TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +#=0A= +#=0A= +#**********************************************************************= ***=0A= +#/=0A= +=0A= +.S.s: =0A= + $(CPP) $(CFLAGS) $< -o $*.s=0A= +.S.o: =0A= + $(CC) $(CFLAGS) -c $< -o $*.o=0A= +=0A= +=0A= +obj-y :=3D nvram355.o=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.c=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.c = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,423 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * nvram API=0A= + *=0A= + * Copyright 2006 IDT Inc.=0A= + * Author: Integrated Device Technology Inc. rischelp@idt.com=0A= + *=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include "nvram355.h"=0A= +=0A= +void setenv (char *e, char *v, int rewrite);=0A= +char *getenv (char *e);=0A= +void unsetenv (char *e);=0A= +void mapenv (int (*func)(char *, char *));=0A= +void purgeenv(void);=0A= +extern char *getenv (char *s);=0A= +unsigned int is_valid =3D 0;=0A= +static void nvram_initenv(void);=0A= +=0A= +/*=0A= + * The *env routines provide wrappers to the nvram_*env=0A= + * routines to allow any special processing of the environment=0A= + * to be carried out=0A= + * Yes this is a bit naff=0A= + */=0A= +#define WAIT(x) { int i=3D0; while (++i < (x)) ; }=0A= +=0A= +static unsigned char=0A= +nvram_getbyte(int offs)=0A= +{=0A= + int i =3D 0;=0A= +=0A= + unsigned char* nvramAddrPointer =3D (unsigned char*)(NVRAM_BASE + = 0x10);=0A= + unsigned char* nvramDataPointer =3D (unsigned char*)(NVRAM_BASE + = 0x13);=0A= + =0A= + *nvramAddrPointer =3D (unsigned char) offs;=0A= + =0A= + while (++i < 0x100);=0A= + =0A= + return ((unsigned int)(*nvramDataPointer));=0A= +}=0A= +=0A= +static void=0A= +nvram_setbyte(int offs, unsigned char val)=0A= +{=0A= + int i =3D 0;=0A= + unsigned char* nvramAddrPointer=3D(unsigned char*)(NVRAM_BASE + = 0x10);=0A= + unsigned char* nvramDataPointer=3D(unsigned char*)(NVRAM_BASE + = 0x13);=0A= + =0A= + *nvramAddrPointer=3D(unsigned char)offs;=0A= + =0A= + while(++i < 0x100);=0A= + =0A= + *nvramDataPointer =3D val;=0A= + =0A= + i =3D 0;=0A= + while(++i < 0x100);=0A= +}=0A= +=0A= +/*=0A= + * BigEndian!=0A= + */=0A= +static unsigned short=0A= +nvram_getshort(int offs)=0A= +{=0A= + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));=0A= +}=0A= +=0A= +static void=0A= +nvram_setshort(int offs, unsigned short val)=0A= +{=0A= + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));=0A= + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));=0A= +}=0A= +=0A= +#if 0=0A= +static unsigned int=0A= +nvram_getint(int offs)=0A= +{=0A= + unsigned int val;=0A= + val =3D nvram_getbyte(offs) << 24;=0A= + val |=3D nvram_getbyte(offs + 1) << 16;=0A= + val |=3D nvram_getbyte(offs + 2) << 8;=0A= + val |=3D nvram_getbyte(offs + 3);=0A= + return(val);=0A= +}=0A= +=0A= +static void=0A= +nvram_setint(int offs, unsigned int val)=0A= +{=0A= + nvram_setbyte(offs, val >> 24);=0A= + nvram_setbyte(offs + 1, val >> 16);=0A= + nvram_setbyte(offs + 2, val >> 8);=0A= + nvram_setbyte(offs + 3, val);=0A= +}=0A= +#endif=0A= +/*=0A= + * calculate NVRAM checksum=0A= + */=0A= +static unsigned short=0A= +nvram_calcsum(void)=0A= +{=0A= + unsigned short sum =3D NV_MAGIC;=0A= + int i;=0A= + =0A= + for (i =3D ENV_BASE; i < ENV_TOP; i +=3D 2)=0A= + sum +=3D nvram_getshort(i);=0A= + return(sum);=0A= +}=0A= +=0A= +/*=0A= + * update the nvram checksum=0A= + */=0A= +static void=0A= +nvram_updatesum(void)=0A= +{=0A= + nvram_setshort(NVOFF_CSUM, nvram_calcsum());=0A= +}=0A= +=0A= +/*=0A= + * test validity of nvram by checksumming it=0A= + */=0A= +static int=0A= +nvram_isvalid(void)=0A= +{=0A= +#if defined(PRETEND_NVRAM) || defined(NO_NVRAM)=0A= + is_valid =3D 1;=0A= + return(1);=0A= +#else=0A= + =0A= + if (is_valid)=0A= + return(1);=0A= + =0A= + if (nvram_getshort(NVOFF_MAGIC) !=3D NV_MAGIC) {=0A= + nvram_initenv();=0A= + return(0);=0A= + }=0A= + =0A= + is_valid =3D 1;=0A= + return(1);=0A= +#endif=0A= +}=0A= +=0A= +/* return nvram address of environment string */=0A= +static int=0A= +nvram_matchenv(char *s)=0A= +{=0A= + int envsize, envp, n, i, varsize;=0A= + char *var;=0A= + =0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + if (envsize > ENV_AVAIL)=0A= + return(0); /* sanity */=0A= + envp =3D ENV_BASE;=0A= + =0A= + if ((n =3D strlen (s)) > 255)=0A= + return(0);=0A= + =0A= + while (envsize > 0) {=0A= + varsize =3D nvram_getbyte(envp);=0A= + if (varsize =3D=3D 0 || (envp + varsize) > ENV_TOP)=0A= + return(0); /* sanity */=0A= + for (i =3D envp + 1, var =3D s; i <=3D envp + n; i++, var++) {=0A= + char c1 =3D nvram_getbyte(i);=0A= + char c2 =3D *var;=0A= + if (islower(c1))=0A= + c1 =3D toupper(c1);=0A= + if (islower(c2))=0A= + c2 =3D toupper(c2);=0A= + if (c1 !=3D c2)=0A= + break;=0A= + }=0A= + if (i > envp + n) { /* match so far */=0A= + if (n =3D=3D varsize - 1) /* match on boolean */=0A= + return(envp);=0A= + if (nvram_getbyte(i) =3D=3D '=3D') /* exact match on variable = */=0A= + return(envp);=0A= + }=0A= + envsize -=3D varsize;=0A= + envp +=3D varsize;=0A= + }=0A= + return(0);=0A= +}=0A= +=0A= +static void nvram_initenv(void)=0A= +{=0A= + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);=0A= + nvram_setshort(NVOFF_ENVSIZE, 0);=0A= + nvram_updatesum();=0A= +}=0A= +=0A= +static void=0A= +nvram_delenv(char *s)=0A= +{=0A= + int nenvp, envp, envsize, nbytes;=0A= + =0A= + envp =3D nvram_matchenv(s);=0A= + if (envp =3D=3D 0)=0A= + return;=0A= + =0A= + nenvp =3D envp + nvram_getbyte(envp);=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + nbytes =3D envsize - (nenvp - ENV_BASE);=0A= + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));=0A= + while (nbytes--) {=0A= + nvram_setbyte(envp, nvram_getbyte(nenvp));=0A= + envp++;=0A= + nenvp++;=0A= + }=0A= + nvram_updatesum();=0A= +}=0A= +=0A= +static int=0A= +nvram_setenv(char *s, char *v)=0A= +{=0A= + int ns, nv, total;=0A= + int envp;=0A= + =0A= + if (!nvram_isvalid())=0A= + return(-1);=0A= + =0A= + nvram_delenv(s);=0A= + ns =3D strlen(s);=0A= + if (ns =3D=3D 0)=0A= + return (-1);=0A= + if (v && *v) {=0A= + nv =3D strlen(v);=0A= + total =3D ns + nv + 2;=0A= + }=0A= + else {=0A= + nv =3D 0;=0A= + total =3D ns + 1;=0A= + }=0A= + if (total > 255 || total > ENV_AVAIL - = nvram_getshort(NVOFF_ENVSIZE))=0A= + return(-1);=0A= + =0A= + envp =3D ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);=0A= + =0A= + nvram_setbyte(envp, (unsigned char)total);=0A= + envp++;=0A= + =0A= + while (ns--) {=0A= + nvram_setbyte(envp, *s);=0A= + envp++;=0A= + s++;=0A= + }=0A= + =0A= + if (nv) {=0A= + nvram_setbyte(envp, '=3D');=0A= + envp++;=0A= + while (nv--) {=0A= + nvram_setbyte(envp, *v);=0A= + envp++;=0A= + v++;=0A= + }=0A= + }=0A= + nvram_setshort(NVOFF_ENVSIZE, envp - ENV_BASE);=0A= + nvram_updatesum();=0A= + return(0);=0A= +}=0A= +=0A= +static char *=0A= +nvram_getenv(char *s)=0A= +{=0A= + static char buf[256];=0A= + int envp, ns, nbytes, i;=0A= + =0A= + if (!nvram_isvalid())=0A= + return((char *)0);=0A= + =0A= + envp =3D nvram_matchenv(s);=0A= + if (envp =3D=3D 0)=0A= + return((char *)0);=0A= + ns =3D strlen(s);=0A= + if (nvram_getbyte(envp) =3D=3D ns + 1) /* boolean */=0A= + buf[0] =3D '\0';=0A= + else {=0A= + nbytes =3D nvram_getbyte(envp) - (ns + 2);=0A= + envp +=3D ns + 2;=0A= + for (i =3D 0; i < nbytes; i++)=0A= + buf[i] =3D nvram_getbyte(envp++);=0A= + buf[i] =3D '\0';=0A= + }=0A= + return(buf);=0A= +}=0A= +=0A= +static void=0A= +nvram_unsetenv(char *s)=0A= +{=0A= + if (!nvram_isvalid())=0A= + return;=0A= + =0A= + nvram_delenv(s);=0A= +}=0A= +=0A= +void=0A= +purgeenv()=0A= +{=0A= + int i;=0A= + unsigned char temp;=0A= + =0A= + unsigned char* nvramAddrPointer =3D (unsigned char*)(NVRAM_BASE + = 0x10);=0A= + unsigned char* nvramDataPointer =3D (unsigned char*)(NVRAM_BASE + = 0x13);=0A= + =0A= + /* enable burst mode for DS1511*/=0A= + unsigned char* controlB =3D (unsigned char*)(NVRAM_BASE + 0x0F);=0A= + temp =3D *controlB;=0A= + *controlB =3D temp | 0x20;=0A= + *nvramAddrPointer =3D (unsigned char)ENV_BASE;=0A= + for (i =3D ENV_BASE; i < ENV_TOP; i++)=0A= + *nvramDataPointer=3D 0;=0A= + *controlB =3D temp;=0A= + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);=0A= + nvram_setshort(NVOFF_ENVSIZE, 0);=0A= + nvram_setshort(NVOFF_CSUM, NV_MAGIC);=0A= +}=0A= +=0A= +/*=0A= + * apply func to each string in environment=0A= + */=0A= +static void=0A= +nvram_mapenv(int (*func)(char *, char *))=0A= +{=0A= + int envsize, envp, n, i, seeneql;=0A= + char name[256], value[256];=0A= + char c, *s;=0A= + =0A= + if (!nvram_isvalid())=0A= + return;=0A= + =0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + envp =3D ENV_BASE;=0A= + =0A= + while (envsize > 0) {=0A= + value[0] =3D '\0';=0A= + seeneql =3D 0;=0A= + s =3D name;=0A= + n =3D nvram_getbyte(envp);=0A= + for (i =3D envp + 1; i < envp + n; i++) {=0A= + c =3D nvram_getbyte(i);=0A= + if ((c =3D=3D '=3D') && !seeneql) {=0A= + *s =3D '\0';=0A= + s =3D value;=0A= + seeneql =3D 1;=0A= + continue;=0A= + }=0A= + *s++ =3D c;=0A= + }=0A= + *s =3D '\0';=0A= + (*func)(name, value);=0A= + envsize -=3D n;=0A= + envp +=3D n;=0A= + }=0A= +}=0A= +#if 0=0A= +static unsigned int=0A= +digit(char c)=0A= +{=0A= + if ('0' <=3D c && c <=3D '9')=0A= + return(c - '0');=0A= + if ('A' <=3D c && c <=3D 'Z')=0A= + return(10 + c - 'A');=0A= + if ('a' <=3D c && c <=3D 'z')=0A= + return(10 + c - 'a');=0A= + return(~0);=0A= +}=0A= +#endif=0A= +=0A= +/*=0A= + * Wrappers to allow 'special' environment variables to get = processed=0A= + */=0A= +void=0A= +setenv(char *e, char *v, int rewrite)=0A= +{=0A= + if (nvram_getenv(e) && !rewrite)=0A= + return;=0A= + nvram_setenv(e, v);=0A= +}=0A= +=0A= +char *=0A= +getenv(char *e)=0A= +{=0A= + return(nvram_getenv(e));=0A= +}=0A= +=0A= +void=0A= +unsetenv(char *e)=0A= +{=0A= + nvram_unsetenv(e);=0A= +}=0A= +=0A= +void=0A= +mapenv(int (*func)(char *, char *))=0A= +{=0A= + nvram_mapenv(func);=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.h = idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.h=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvram355.h = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,72 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * nvram.h: NVRAM layout definitions=0A= + *=0A= + * Copyright 2006 IDT Inc.=0A= + * Author: Integrated Device Technology Inc. rischelp@idt.com=0A= + *=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +=0A= +#ifndef _NVRAM_=0A= +#define _NVRAM_=0A= +/*=0A= + * defining ALGCOMPAT provides backward compatibility=0A= + * with Algorithmics derived PROM monitors=0A= + */=0A= +#define ALGCOMPAT=0A= +#ifdef ALGCOMPAT=0A= +#define NVOFFSET 0 /* use all of NVRAM */=0A= +#else=0A= +#define NVOFFSET 128 /* first 1Kb reserved for DECelx */=0A= +#endif=0A= +=0A= +/* Offsets to reserved locations */=0A= +/* size description */=0A= +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */=0A= +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum = */=0A= +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */=0A= +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */=0A= +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address = */=0A= +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */=0A= +=0A= +#define NV_MAGIC 0xdeaf /* nvram magic number */=0A= +#define NV_RESERVED 32 /* number of reserved bytes = */=0A= +=0A= +#ifdef ALGCOMPAT=0A= +/* ho hum... */=0A= +#undef NVOFF_ETHADDR=0A= +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)=0A= +#endif=0A= +=0A= +/* number of bytes available for environment */=0A= +#define ENV_BASE (NVOFFSET + NV_RESERVED)=0A= +#define ENV_TOP TD_NVRAM_SIZE=0A= +#define ENV_AVAIL (ENV_TOP - ENV_BASE)=0A= +#endif /* _NVRAM_ */=0A= +=0A= +#define NVRAM_BASE 0xba004000=0A= +#define TD_NVRAM_SIZE 0x100=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvramproc.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvramproc.c=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/nvram/nvramproc.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/nvram/nvramproc.c = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,219 @@=0A= +/**********************************************************************= ********=0A= + We provide a /proc interface to the nvram. We make an entry=0A= + for 'nvram' and under which 'boot'. 'boot' is a deivce that=0A= + is read/write. Together with nvram365.c, we provide an interface = for=0A= + the user to set and modify the environment variables stored in = NVRAM.=0A= + = ************************************************************************= *******=0A= + Examples=0A= + =0A= + #cat /proc/nvram/boot=0A= + will display the boot environment variables, like = netaddr0,bootaddr etc.=0A= + #echo "netaddr0 192.168.1.3" >/proc/nvram/boot=0A= + will modify the boot environment variable netaddr0.=0A= + #echo "netaddr0" >/proc/nvram/boot=0A= + will erase the "netaddr0" environment variable=0A= + #echo >/proc/nvram/boot=0A= + will erase all environment variables stored in nvram=0A= +=0A= +***********************************************************************= *******/=0A= + =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +//#define DEBUG 1=0A= +#define MODULE_VERSION "1.0"=0A= +#define MODULE_NAME "nvram"=0A= +#define BOOT_MAJOR 240=0A= +#define BUF_LEN 8192=0A= +=0A= +extern void setenv (char *e, char *v, int rewrite);=0A= +extern char *getenv (char *e);=0A= +extern void unsetenv (char *e);=0A= +extern void mapenv (int (*func)(char *, char *));=0A= +extern void purgeenv(void);=0A= +extern char *getenv (char *s);=0A= +=0A= +static struct proc_dir_entry *nvram, *boot;=0A= +=0A= +static int boot_open(struct inode *, struct file *);=0A= +static int boot_release(struct inode *, struct file *);=0A= +static ssize_t boot_read(struct file *, char *, size_t, loff_t *);=0A= +static ssize_t boot_write(struct file *, const char *, size_t, loff_t = *);=0A= +=0A= +static struct file_operations boot_fops =3D {=0A= + .read =3D boot_read, =0A= + .write =3D boot_write,=0A= + .open =3D boot_open,=0A= + .release =3D boot_release=0A= +};=0A= +=0A= +static char msg[BUF_LEN];=0A= +static char *msg_Ptr;=0A= +const char delimiters[] =3D " \n";=0A= +=0A= +static int printVal(char *name,char *val)=0A= +{=0A= + strcat(msg,name);=0A= + strcat(msg," ");=0A= + strcat(msg,val);=0A= + strcat(msg,"\n");=0A= + return 0;=0A= +}=0A= +=0A= +static int boot_open(struct inode *inode, struct file *file)=0A= +{=0A= + MOD_INC_USE_COUNT;=0A= + memset(msg,0,BUF_LEN);=0A= + msg_Ptr =3D msg;=0A= + return 0;=0A= +}=0A= +static int boot_release(struct inode *inode, struct file *file)=0A= +{=0A= + MOD_DEC_USE_COUNT;=0A= + return 0;=0A= +}=0A= +=0A= +static ssize_t boot_read(struct file *filp,=0A= + char *buffer, /* The buffer to fill with data */=0A= + size_t length, /* The length of the buffer */=0A= + off_t *offset) /* Our offset in the file */=0A= +{=0A= + int bytes_read =3D 0;=0A= + if(msg_Ptr =3D=3D msg)=0A= + {=0A= + mapenv(&printVal);=0A= + }=0A= + if (*msg_Ptr =3D=3D 0){=0A= + msg_Ptr =3D msg;=0A= + return 0;=0A= + }=0A= + while (length && *msg_Ptr)=0A= + {=0A= + put_user(*(msg_Ptr++), buffer++);=0A= + length--;=0A= + bytes_read++;=0A= + }=0A= + return bytes_read;=0A= +}=0A= +=0A= +static ssize_t boot_write(struct file *filp,=0A= + const char *buffer,=0A= + size_t length,=0A= + loff_t *offset)=0A= +{=0A= + int bytes_written =3D 0;=0A= + char *token1,*token2;=0A= + =0A= + memset(msg,0,BUF_LEN);=0A= + =0A= + while(length && *buffer)=0A= + {=0A= + get_user(msg[bytes_written],buffer++);=0A= + length--;=0A= + bytes_written++;=0A= + }=0A= + =0A= + token1 =3D strsep(&msg_Ptr,delimiters);=0A= + token2 =3D strsep(&msg_Ptr,delimiters);=0A= + =0A= + if((*token1 !=3D'\0') && (*token2 !=3D '\0'))=0A= + {=0A= +#ifdef DEBUG=0A= + printk(__FILE__": setting environment %s to %s\n",token1,token2);=0A= +#endif=0A= + setenv(token1,token2,1);=0A= + }=0A= + else if(*token1 !=3D '\0')=0A= + {=0A= +#ifdef DEBUG=0A= + printk(__FILE__": pugring environment variable %s\n",token1);=0A= +#endif=0A= + unsetenv(token1);=0A= + }=0A= + else=0A= + {=0A= +#ifdef DEBUG=0A= + printk(__FILE__": purging all environment variables\n");=0A= +#endif=0A= + purgeenv();=0A= + }=0A= + =0A= + return bytes_written;=0A= +}=0A= +=0A= +=0A= +static int __init init_procfs_nvram(void)=0A= +{=0A= + int rv =3D 0;=0A= + =0A= + /* create directory */=0A= + nvram =3D proc_mkdir(MODULE_NAME, NULL);=0A= + if(nvram =3D=3D NULL) {=0A= +#ifdef DEBUG=0A= + printk(__FILE__": Cannot make proc entry for 'nvram'\n");=0A= +#endif=0A= + rv =3D -ENOMEM;=0A= + goto out1;=0A= + }=0A= +#ifdef DEBUG=0A= + printk(__FILE__": module %s %s initialised\n", MODULE_NAME, = MODULE_VERSION);=0A= +#endif=0A= + if (register_chrdev(BOOT_MAJOR,"boot", &boot_fops) <0)=0A= + {=0A= +#ifdef DEBUG =0A= + printk(__FILE__": Cannot register 'boot' device.\n");=0A= +#endif=0A= + rv =3D -EINVAL;=0A= + goto out2;=0A= + }=0A= + =0A= +#ifdef DEBUG =0A= + printk(__FILE__": device 'boot' (major %d) = registered\n",BOOT_MAJOR);=0A= +#endif=0A= + =0A= + boot =3D proc_mknod("boot", S_IFCHR | 0644, nvram, MKDEV(BOOT_MAJOR, = 0));=0A= + if(boot =3D=3D NULL) {=0A= +#ifdef DEBUG=0A= + printk(__FILE__": Cannot make proc entry for boot.\n");=0A= +#endif=0A= + rv =3D -ENOMEM;=0A= + goto out3;=0A= + }=0A= + =0A= + boot->owner =3D THIS_MODULE;=0A= + =0A= + return 0;=0A= + =0A= + out3:=0A= + unregister_chrdev(BOOT_MAJOR,"boot");=0A= + out2:=0A= + remove_proc_entry(MODULE_NAME, NULL);=0A= + out1:=0A= + return rv;=0A= +}=0A= +=0A= +=0A= +static void __exit cleanup_procfs_nvram(void)=0A= +{=0A= + remove_proc_entry("boot", nvram);=0A= + unregister_chrdev(BOOT_MAJOR,"boot");=0A= + remove_proc_entry(MODULE_NAME, NULL);=0A= +#ifdef DEBUG=0A= + printk("%s %s removed\n", MODULE_NAME, MODULE_VERSION);=0A= +#endif=0A= +}=0A= +=0A= +=0A= +module_init(init_procfs_nvram);=0A= +module_exit(cleanup_procfs_nvram);=0A= +=0A= +MODULE_AUTHOR("idt");=0A= +MODULE_DESCRIPTION("proc interface for nvram");=0A= +MODULE_LICENSE("GPL");=0A= +=0A= +EXPORT_NO_SYMBOLS;=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/prom.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/prom.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/prom.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/prom.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,141 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT EB32355 kernel boot-parameters setup=0A= + *=0A= + * Copyright 2006 IDT Inc.=0A= + * Author: Integrated Device Technology Inc. rischelp@idt.com=0A= + *=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +=0A= +unsigned int idt_cpu_freq =3D CONFIG_IDT_BOARD_FREQ;=0A= +EXPORT_SYMBOL(idt_cpu_freq);=0A= +extern void setup_serial_port(int);=0A= +=0A= +=0A= +#ifdef CONFIG_IDT_BOOT_NVRAM=0A= +extern void mapenv(int (*func)(char *, char *));=0A= +static int make_bootparm(char *name,char *val)=0A= +{ =0A= + if (strncmp(name, "bootparm", 8) =3D=3D 0) {=0A= + strcat(arcs_cmdline,val);=0A= + strcat(arcs_cmdline," ");=0A= + }=0A= + else if(strncmp(name, "HZ", 2) =3D=3D 0) {=0A= + idt_cpu_freq =3D simple_strtoul(val, 0, 10);=0A= + printk("CPU Clock at %d Hz (from HZ environment variable)\n",=0A= + idt_cpu_freq);=0A= + }=0A= + return 0;=0A= +}=0A= +=0A= +=0A= +/*=0A= + * Parses environment variable strings in NVRAM, copying strings=0A= + * beginning with "bootparm?=3D" to arcs_cmdline[]. For example,=0A= + *=0A= + * netaddr=3D10.0.1.95=0A= + * bootaddr=3D10.0.0.139=0A= + * bootfile=3Dvmlinus=0A= + * bootparm1=3Droot=3D/dev/nfs=0A= + * bootparm2=3Dip=3D10.0.1.95=0A= + *=0A= + * is parsed to:=0A= + *=0A= + * root=3D/dev/nfs ip=3D10.0.1.95=0A= + *=0A= + * in arcs_cmdline[].=0A= + */=0A= +static void prom_init_cmdline(void)=0A= +{ =0A= + memset(arcs_cmdline,0,sizeof(arcs_cmdline));=0A= + mapenv(&make_bootparm);=0A= +}=0A= +#else=0A= +/* Kernel Boot parameters */=0A= +static unsigned char bootparm[]=3D"console=3DttyS0,9600";=0A= +#endif=0A= +extern unsigned long mips_machgroup;=0A= +extern unsigned long mips_machtype;=0A= +=0A= +const char *get_system_type(void)=0A= +{=0A= + return "IDT 79EB355";=0A= +}=0A= +=0A= +struct resource rc32300_res_ram =3D {=0A= + "RAM",=0A= + 0,=0A= + RAM_SIZE,=0A= + IORESOURCE_MEM=0A= +};=0A= +=0A= +char * __init prom_getcmdline(void)=0A= +{=0A= + return &(arcs_cmdline[0]);=0A= +}=0A= +=0A= +void __init prom_init(void)=0A= +{=0A= +#ifdef CONFIG_IDT_BOOT_NVRAM=0A= + /* set up command line */=0A= + prom_init_cmdline();=0A= +#else=0A= + sprintf(arcs_cmdline,"%s",bootparm);=0A= +#endif=0A= + =0A= + setup_serial_port(0); // UART0=0A= + setup_serial_port(1); // UART1=0A= + =0A= + /* set our arch type */=0A= + mips_machgroup =3D MACH_GROUP_IDT;=0A= + mips_machtype =3D MACH_IDT_EB355;=0A= + add_memory_region(0,=0A= + rc32300_res_ram.end - rc32300_res_ram.start,=0A= + BOOT_MEM_RAM);=0A= + =0A= +}=0A= +=0A= +void prom_free_prom_memory(void)=0A= +{=0A= +}=0A= +=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/reset.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/reset.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/reset.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/reset.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,70 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT EB32355 reset/power-off routines=0A= + *=0A= + * Copyright 2006 IDT Inc.=0A= + * Author: Integrated Device Technology Inc. rischelp@idt.com=0A= + *=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +=0A= +void rc32300_restart(char *command)=0A= +{=0A= + set_c0_status((ST0_BEV | ST0_ERL));=0A= + set_c0_config(CONF_CM_UNCACHED);=0A= + flush_cache_all();=0A= + write_c0_wired(0);=0A= + =0A= + rc32300_writel(0x80000001, RESET_CNTL);=0A= +}=0A= +=0A= +void rc32300_halt(void)=0A= +{=0A= + printk(KERN_NOTICE "\n** You can safely turn off the power\n");=0A= + while (1)=0A= + __asm__(".set\tmips3\n\t"=0A= + "wait\n\t"=0A= + ".set\tmips0");=0A= +}=0A= +=0A= +void rc32300_power_off(void)=0A= +{=0A= + rc32300_halt();=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/serial.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/serial.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/serial.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/serial.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,82 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Serial Port Setup (2 UART)=0A= + *=0A= + * Copyright 2006 IDT Inc.=0A= + * Author: Integrated Device Technology Inc. rischelp@idt.com=0A= + *=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +=0A= +extern int __init early_serial_setup(struct uart_port *port);=0A= +extern unsigned int idt_cpu_freq;=0A= +=0A= +=0A= +extern int __init setup_serial_port(int port)=0A= +{ =0A= + static struct uart_port serial_req[2];=0A= + memset(serial_req, 0, sizeof(serial_req));=0A= + if(port =3D=3D 0){=0A= + serial_req[0].type =3D PORT_16550A;=0A= + serial_req[0].line =3D 0;=0A= + serial_req[0].irq =3D RC32300_UART0_IRQ;=0A= + serial_req[0].flags =3D STD_COM_FLAGS;=0A= + serial_req[0].uartclk =3D idt_cpu_freq;=0A= + serial_req[0].iotype =3D SERIAL_IO_MEM;=0A= + serial_req[0].membase =3D (char *) = KSEG1ADDR(RC32300_UART0_BASE);=0A= + serial_req[0].mapbase =3D KSEG1ADDR(RC32300_UART0_BASE);=0A= + serial_req[0].regshift =3D 2;=0A= + early_serial_setup(&serial_req[0]);=0A= + }=0A= + else if (port =3D=3D 1){=0A= + serial_req[1].type =3D PORT_16550A;=0A= + serial_req[1].line =3D 1;=0A= + serial_req[1].irq =3D RC32300_UART1_IRQ;=0A= + serial_req[1].flags =3D STD_COM_FLAGS;=0A= + serial_req[1].uartclk =3D idt_cpu_freq;=0A= + serial_req[1].iotype =3D SERIAL_IO_MEM;=0A= + serial_req[1].membase =3D (char *) = KSEG1ADDR(RC32300_UART1_BASE);=0A= + serial_req[1].mapbase =3D KSEG1ADDR(RC32300_UART1_BASE);=0A= + serial_req[1].regshift =3D 2;=0A= + early_serial_setup(&serial_req[1]);=0A= + }=0A= + return(0);=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/serial_gdb.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/serial_gdb.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/serial_gdb.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/serial_gdb.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,273 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * EB355 specific polling driver for 16550 UART.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +=0A= +/* set remote gdb baud rate at 115200 */=0A= +=0A= +#define GDB_BAUD 115200=0A= +#define CONS_BAUD 9600=0A= +=0A= +extern unsigned int idt_cpu_freq;=0A= +=0A= +=0A= +/* turn this on to watch the debug protocol echoed on the console port = */=0A= +#undef DEBUG_REMOTE_DEBUG=0A= +=0A= +#ifdef __MIPSEB__=0A= +#define CONS_PORT 0xb8050003u=0A= +#define GDB_PORT 0xb8050023u=0A= +#else=0A= +#define CONS_PORT 0xb8050000u=0A= +#define GDB_PORT 0xb8050020u=0A= +#endif=0A= + =0A= +volatile unsigned char *ports[2] =3D {=0A= + (volatile unsigned char *)CONS_PORT,=0A= + (volatile unsigned char *)GDB_PORT=0A= +};=0A= +=0A= +=0A= +void reset_gdb_port(void);=0A= +void cons_putc(char c);=0A= +int port_getc(int port);=0A= +void port_putc(int port, char c);=0A= +=0A= +int cons_getc(void)=0A= +{=0A= + return port_getc(0);=0A= +}=0A= +=0A= +void cons_putc(char c)=0A= +{=0A= + port_putc(0, c);=0A= +}=0A= +=0A= +void cons_puts(char *s)=0A= +{=0A= + while(*s) {=0A= + if(*s =3D=3D '\n') cons_putc('\r');=0A= + cons_putc(*s);=0A= + s++;=0A= + }=0A= +}=0A= +=0A= +void cons_do_putn(int n)=0A= +{=0A= + if(n) {=0A= + cons_do_putn(n / 10);=0A= + cons_putc(n % 10 + '0');=0A= + }=0A= +}=0A= +=0A= +void cons_putn(int n)=0A= +{=0A= + if(n < 0) {=0A= + cons_putc('-');=0A= + n =3D -n;=0A= + }=0A= +=0A= + if (n =3D=3D 0) {=0A= + cons_putc('0');=0A= + } else {=0A= + cons_do_putn(n);=0A= + }=0A= +}=0A= +=0A= +#ifdef DEBUG_REMOTE_DEBUG=0A= +static enum {HUH, SENDING, GETTING} state;=0A= +=0A= +static void sent(int c)=0A= +{=0A= + switch(state) {=0A= + case HUH:=0A= + case GETTING:=0A= + cons_puts("\nSNT ");=0A= + state =3D SENDING;=0A= + /* fall through */=0A= + case SENDING:=0A= + cons_putc(c);=0A= + break;=0A= + } =0A= +}=0A= +=0A= +static void got(int c)=0A= +{=0A= + switch(state) {=0A= + case HUH:=0A= + case SENDING:=0A= + cons_puts("\nGOT ");=0A= + state =3D GETTING;=0A= + /* fall through */=0A= + case GETTING:=0A= + cons_putc(c);=0A= + break;=0A= + } =0A= +}=0A= +#endif /* DEBUG_REMOTE_DEBUG */=0A= +=0A= +static int first =3D 1;=0A= +=0A= +int getDebugChar(void)=0A= +{=0A= + int c;=0A= +=0A= + if(first) reset_gdb_port();=0A= +=0A= + c =3D port_getc(1);=0A= +=0A= +#ifdef DEBUG_REMOTE_DEBUG=0A= + got(c);=0A= +#endif=0A= +=0A= + return c;=0A= +}=0A= +=0A= +int port_getc(int p)=0A= +{=0A= + volatile unsigned char *port =3D ports[p];=0A= + int c;=0A= +=0A= + while((*(port + UART_LSR * 4) & UART_LSR_DR) =3D=3D 0) {=0A= + continue;=0A= + } =0A= +=0A= + c =3D *(port + UART_RX * 4);=0A= +=0A= + return c;=0A= +}=0A= +=0A= +int port_getc_ready(int p)=0A= +{=0A= + volatile unsigned char *port =3D ports[p];=0A= +=0A= + return *(port + UART_LSR * 4) & UART_LSR_DR;=0A= +}=0A= +=0A= +int isDebugReady(void)=0A= +{=0A= + return port_getc_ready(1);=0A= +}=0A= +=0A= +void putDebugChar(char c)=0A= +{=0A= + if(first) reset_gdb_port();=0A= +=0A= +#ifdef DEBUG_REMOTE_DEBUG=0A= + sent(c);=0A= +#endif=0A= +=0A= + port_putc(1, c);=0A= +}=0A= +=0A= +#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)=0A= +=0A= +void port_putc(int p, char c)=0A= +{=0A= + volatile unsigned char *port =3D ports[p];=0A= + volatile unsigned char *lsr =3D port + UART_LSR * 4;=0A= +=0A= + while((*lsr & OK_TO_XMT) !=3D OK_TO_XMT) {=0A= + continue;=0A= + }=0A= +=0A= + *(port + UART_TX * 4) =3D c;=0A= +}=0A= +=0A= +void reset_gdb_port(void)=0A= +{=0A= + volatile unsigned char *port =3D ports[1];=0A= + unsigned int DIVISOR =3D (idt_cpu_freq / 16 / GDB_BAUD);=0A= +=0A= + first =3D 0;=0A= +=0A= +#ifdef DEBUG_REMOTE_DEBUG=0A= + cons_puts("reset_gdb_port: initializing remote debug serial port = (internal UART 1, ");=0A= + cons_putn(GDB_BAUD);=0A= + cons_puts("baud, MHz=3D");=0A= + cons_putn(idt_cpu_freq);=0A= + cons_puts(", divisor=3D");=0A= + cons_putn(DIVISOR);=0A= + cons_puts(")\n");=0A= +#endif=0A= +=0A= + /* reset the port */=0A= + *(port + UART_CSR * 4) =3D 0;=0A= +=0A= + /* clear and enable the FIFOs */=0A= + *(port + UART_FCR * 4) =3D UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR = | =0A= + UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;=0A= +=0A= + /* set the baud rate */=0A= + *(port + UART_LCR * 4) =3D UART_LCR_DLAB; /* enable DLL, DLM = registers */=0A= + *(port + UART_DLL * 4) =3D DIVISOR;=0A= + *(port + UART_DLM * 4) =3D DIVISOR >> 8;=0A= +=0A= + /* set the line control stuff and disable DLL, DLM regs */=0A= +=0A= + *(port + UART_LCR * 4) =3D UART_LCR_STOP | /* 2 stop bits */=0A= + UART_LCR_WLEN8; /* 8 bit word length */=0A= + =0A= + /* leave interrupts off */=0A= + *(port + UART_IER * 4) =3D 0;=0A= +=0A= + /* the modem controls don't leave the chip on this port, so leave = them alone */=0A= + *(port + UART_MCR * 4) =3D 0;=0A= +}=0A= +=0A= +void reset_cons_port(void)=0A= +{=0A= + volatile unsigned char *port =3D ports[0];=0A= + unsigned int DIVISOR =3D (idt_cpu_freq / 16 / CONS_BAUD);=0A= +=0A= + /* reset the port */=0A= + *(port + UART_CSR * 4) =3D 0;=0A= +=0A= + /* clear and enable the FIFOs */=0A= + *(port + UART_FCR * 4) =3D UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR = | =0A= + UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;=0A= +=0A= + /* set the baud rate */=0A= + *(port + UART_LCR * 4) =3D UART_LCR_DLAB; /* enable DLL, DLM = registers */=0A= +=0A= + *(port + UART_DLL * 4) =3D DIVISOR;=0A= + *(port + UART_DLM * 4) =3D DIVISOR >> 8;=0A= + /* set the line control stuff and disable DLL, DLM regs */=0A= +=0A= + *(port + UART_LCR * 4) =3D UART_LCR_STOP | /* 2 stop bits */=0A= + UART_LCR_WLEN8; /* 8 bit word length */=0A= + =0A= + /* leave interrupts off */=0A= + *(port + UART_IER * 4) =3D 0;=0A= +=0A= + /* the modem controls don't leave the chip on this port, so leave = them alone */=0A= + *(port + UART_MCR * 4) =3D 0;=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/setup.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/setup.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/setup.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/setup.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,138 @@=0A= +/**********************************************************************= ****=0A= +*=0A= +* BRIEF MODULE DESCRIPTION=0A= +* IDT EB32355 board setup=0A= +*=0A= +* Copyright 2006 IDT Inc.=0A= +* Author: Integrated Device Technology Inc. rischelp@idt.com=0A= +*=0A= +* =0A= +* This program is free software; you can redistribute it and/or = modify it=0A= +* under the terms of the GNU General Public License as published = by the=0A= +* Free Software Foundation; either version 2 of the License, or (at = your=0A= +* option) any later version.=0A= +*=0A= +* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR = TORT=0A= +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +*=0A= +* You should have received a copy of the GNU General Public License = along=0A= +* with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +* 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +*=0A= +***********************************************************************= ***=0A= +*/=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +=0A= +extern void (*board_time_init)(void);=0A= +extern void (*board_timer_setup)(struct irqaction *irq);=0A= +extern void rc32300_time_init(void);=0A= +extern void rc32300_timer_setup(struct irqaction *irq);=0A= +extern char * __init prom_getcmdline(void);=0A= +extern void rc32300_restart(char *);=0A= +extern void rc32300_halt(void);=0A= +extern void rc32300_power_off(void);=0A= +extern int init_lcd(void);=0A= +extern int idtprintf(const char *fmt, ...);=0A= +=0A= +static int __init idt_setup(void)=0A= +{=0A= + char* argptr;=0A= + argptr =3D prom_getcmdline();=0A= + =0A= +#ifdef CONFIG_SERIAL_8250_CONSOLE=0A= + if ((argptr =3D strstr(argptr, "console=3D")) =3D=3D NULL) {=0A= + argptr =3D prom_getcmdline();=0A= + strcat(argptr, " console=3DttyS0,9600");=0A= + }=0A= +#endif=0A= + =0A= + board_time_init =3D rc32300_time_init;=0A= + board_timer_setup =3D rc32300_timer_setup;=0A= + =0A= + _machine_restart =3D rc32300_restart;=0A= + _machine_halt =3D rc32300_halt;=0A= + pm_power_off =3D rc32300_power_off;=0A= + =0A= + set_io_port_base(KSEG1);=0A= + =0A= + // clear out any wired entries=0A= + write_c0_wired(0);=0A= + =0A= + /*=0A= + * Setup Device 3. The EPLD (U13) splits device 3 chip-select=0A= + * into seperate chip selects for the TDM, LCD, and RTC=0A= + * devices. Timings are from IDT-SIM source.=0A= + */=0A= + rc32300_writel(0x00000000, DEV0_MASK + 3*DEV_REG_OFFSET);=0A= + rc32300_writel(TDM_BASE, DEV0_BASE + 3*DEV_REG_OFFSET);=0A= + rc32300_writel(0x0FFFFF84, DEV0_CNTL + 3*DEV_REG_OFFSET);=0A= + rc32300_writel(0x00001FFF, DEV0_TIMING + 3*DEV_REG_OFFSET);=0A= + rc32300_writel(0xFFFF0000, DEV0_MASK + 3*DEV_REG_OFFSET);=0A= + =0A= + init_lcd();=0A= + idtprintf("IDT-Linux 2.6");=0A= + =0A= + =0A= +#ifdef CONFIG_MTD=0A= + /*=0A= + * Setup device 2 for flash devices. Set for=0A= + * 32-bit databus size, write-enable.=0A= + */=0A= + rc32300_writel(0x00000000, DEV0_MASK + 2*DEV_REG_OFFSET);=0A= + rc32300_writel(FLASH_BASE, DEV0_BASE + 2*DEV_REG_OFFSET);=0A= + /* timings are from IDT/sim source */=0A= + rc32300_writel(0x03CF3316, DEV0_CNTL + 2*DEV_REG_OFFSET);=0A= + rc32300_writel(0x00001133, DEV0_TIMING + 2*DEV_REG_OFFSET);=0A= + rc32300_writel(0xFF800000, DEV0_MASK + 2*DEV_REG_OFFSET);=0A= +#endif=0A= + =0A= + =0A= + /* Disable Watchdog timer */=0A= + rc32300_writel(0, 0xb8028040);=0A= + =0A= + return 0;=0A= +}=0A= +=0A= +//early_initcall(idt_setup);=0A= +=0A= +void __init plat_setup(void){=0A= + idt_setup();=0A= +}=0A= +=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/time.c = idtlinux/arch/mips/idt-boards/rc32300/EB355/time.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB355/time.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB355/time.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,133 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT EB32355 timer routines=0A= + *=0A= + * Copyright 2006 IDT Inc.=0A= + * Author: Integrated Device Technology Inc. rischelp@idt.com=0A= + *=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + * =0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +static unsigned long r4k_offset; /* Amount to incr compare reg each = time */=0A= +static unsigned long r4k_cur; /* What counter should be at next = timer irq */=0A= +=0A= +extern unsigned int idt_cpu_freq;=0A= +#if defined(CONFIG_IDT_79EB355) && defined(CONFIG_MIPS_RTC)=0A= +extern void rtc_ds1501_init(void);=0A= +#endif=0A= +=0A= +=0A= +/* =0A= + * Figure out the r4k offset, the amount to increment the compare=0A= + * register for each time tick. There is no RTC available.=0A= + *=0A= + * The RC32300 counts at half the CPU *core* speed.=0A= + */=0A= +=0A= +static unsigned long __init cal_r4koff(void)=0A= +{=0A= + mips_hpt_frequency =3D idt_cpu_freq * IDT_CLOCK_MULT / 2;=0A= + return (mips_hpt_frequency / HZ);=0A= +}=0A= +=0A= +=0A= +void __init rc32300_time_init(void)=0A= +{=0A= + unsigned int est_freq, flags;=0A= + =0A= + local_irq_save(flags);=0A= + =0A= + printk("calculating r4koff... ");=0A= + r4k_offset =3D cal_r4koff();=0A= + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);=0A= + =0A= + est_freq =3D 2*r4k_offset*HZ; =0A= + est_freq +=3D 5000; /* round */=0A= + est_freq -=3D est_freq%10000;=0A= + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, =0A= + (est_freq%1000000)*100/1000000);=0A= + local_irq_restore(flags);=0A= + =0A= +#if defined(CONFIG_IDT_79EB355) && defined(CONFIG_MIPS_RTC)=0A= + rtc_ds1501_init();=0A= +#endif=0A= + =0A= +}=0A= +=0A= +=0A= +void __init rc32300_timer_setup(struct irqaction *irq)=0A= +{=0A= + /* we are using the cpu counter for timer interrupts */=0A= + setup_irq(MIPS_CPU_TIMER_IRQ, irq);=0A= + =0A= + /* to generate the first timer interrupt */=0A= + r4k_cur =3D (read_c0_count() + r4k_offset);=0A= + write_c0_compare(r4k_cur);=0A= +}=0A= +=0A= +static inline void ack_r4ktimer(unsigned long newval)=0A= +{=0A= + write_c0_compare(newval);=0A= +}=0A= +=0A= +=0A= +asmlinkage void idt_timer_interrupt(int irq,struct pt_regs *regs)=0A= +{ =0A= +#ifdef CONFIG_KGDB=0A= + void kgdb_check(void);=0A= +#endif=0A= +=0A= + irq_enter();=0A= + kstat_this_cpu.irqs[irq]++;=0A= + timer_interrupt(irq, NULL, regs);=0A= + irq_exit();=0A= +=0A= +#ifdef CONFIG_KGDB=0A= + kgdb_check();=0A= +#endif=0A= +}=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/csu_idt.S = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/csu_idt.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/csu_idt.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/csu_idt.S = 2006-03-09 16:25:47.000000000 -0800=0A= @@ -0,0 +1,320 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Board initialization code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include "iregdef.h"=0A= +#include "idtcpu.h"=0A= +#include "idthdr.h"=0A= + =0A= +#define MHZ (CONFIG_IDT_BOARD_FREQ/(1000*1000))=0A= + =0A= +#include "s365led.h" =0A= +#include "s365ram.h"=0A= +=0A= + =0A= +/*--------------------------------------------------------------=0A= +* prom entry point table=0A= +*-------------------------------------------------------------*/=0A= +=0A= +FRAME(start,sp,0,ra)=0A= +=0A= + j idtstart /* begin monitor from start |00| */=0A= + =0A= +idtstart:=0A= +=0A= + .set noreorder=0A= + =0A= + mtc0 zero, C0_CAUSE=0A= + li v0, 0x0=0A= + or v0, (SR_CU0 | SR_BEV | SR_DE)=0A= + mtc0 v0, C0_SR=0A= +=0A= + mfc0 v1, C0_CONFIG=0A= + li v0, CFG_C_NCHRNT_WB /* CFG_C_NCHRNT_WB CFG_C_NCHRNT_WT_NWA = CFG_C_UNCACHED */=0A= + and v1, ~(0x7)=0A= + or v1, v1, v0=0A= + mtc0 v1, C0_CONFIG=0A= + nop=0A= + nop=0A= + li t0, ERR_CNTL_STATUS =0A= + sw zero, 0(t0)=0A= +=0A= +/* ------------------- Setup Device Controller = ---------------------------- */=0A= + li t0, DEV_CTL_BASE /* load 2 base address registers' base = */=0A= +=0A= + lui t2, 0xB800=0A= + lw t1, 0x8004(t2) /* get BCV = */=0A= + li t2, 0x60 /* check width of boot device 16/32 bit = */=0A= + and t1, t1, t2=0A= + li t2, 0x20=0A= + bne t1, t2, 1f=0A= + nop=0A= +/* 16 bit device - boot from PROM - CS1 is FLASH = */=0A= + li t1, DEV_PROM_CTRL /* device0 control parameter = */=0A= + sw t1, 0x8(t0) /* set the control register CS0 = */=0A= + li t1, DEV_PROM_TC /* device0 timing config parameter = */=0A= + sw t1, 0xC(t0)=0A= +=0A= + li t1, DEV1_BASE /* set the device base register for CS1 = */=0A= + sw t1, 0x10(t0)=0A= + li t1, DEV_FLASH_MASK /* set the device mask register for CS1 = */=0A= + sw t1, 0x14(t0) =0A= + li t1, DEV_FLASH_CTRL /* set the device control register for = CS1*/=0A= + sw t1, 0x18(t0)=0A= + li t1, DEV_FLASH_TC /* set the device timing register for CS1 = */=0A= + sw t1, 0x1C(t0) =0A= + b 2f =0A= + nop=0A= +1:=0A= +/* 32 bit device - boot from FLASH - CS1 is PROM = */=0A= + li t1, DEV_FLASH_CTRL /* device0 control parameter = */=0A= + sw t1, 0x8(t0) /* set the control register CS0 = */=0A= + li t1, DEV_FLASH_TC /* device0 timing config parameter = */=0A= + sw t1, 0xC(t0)=0A= + li t1, DEV1_BASE /* set the device base register for CS1 */=0A= + sw t1, 0x10(t0)=0A= + li t1, DEV_PROM_MASK /* set the device mask register for CS1 = */=0A= + sw t1, 0x14(t0) =0A= + li t1, DEV_PROM_CTRL /* set the device control register for = CS1*/=0A= + sw t1, 0x18(t0)=0A= + li t1, DEV_PROM_TC /* set the device timing register for CS1 = */=0A= + sw t1, 0x1C(t0) =0A= +2:=0A= + li t1, DEV2_BASE /* set the device base register for CS2 = */=0A= + sw t1, 0x20(t0)=0A= + li t1, DEV2_MASK /* set the device mask register for CS2 = */=0A= + sw t1, 0x24(t0) =0A= + li t1, DEV2_CTRL /* set the device control register for = CS2*/=0A= + sw t1, 0x28(t0) =0A= + li t1, DEV2_TC /* set the device timing register for CS2 = */=0A= + sw t1, 0x2C(t0) =0A= +=0A= + li t1, DEV3_BASE /* set the device base register for CS3 = */=0A= + sw t1, 0x30(t0)=0A= + li t1, DEV3_MASK /* set the device mask register for CS3 = */=0A= + sw t1, 0x34(t0) =0A= + li t1, DEV3_CTRL /* set the device control register for = CS3*/=0A= + sw t1, 0x38(t0)=0A= + li t1, DEV3_TC /* set the device timing register for CS3 = */=0A= + sw t1, 0x3C(t0) =0A= +=0A= + li t1, DEV4_BASE /* set the device base register for CS4 = */=0A= + sw t1, 0x40(t0)=0A= + li t1, DEV4_MASK /* set the device mask register for CS4 = */=0A= + sw t1, 0x44(t0) =0A= + li t1, DEV4_CTRL /* set the device control register for = CS4*/=0A= + sw t1, 0x48(t0)=0A= + li t1, DEV4_TC /* set the device timing register for CS4 = */=0A= + sw t1, 0x4C(t0) =0A= +=0A= + li t1, DEV5_BASE /* set the device base register for CS5 = */=0A= + sw t1, 0x50(t0)=0A= + li t1, DEV5_MASK /* set the device mask register for CS5 = */=0A= + sw t1, 0x54(t0) =0A= + li t1, DEV5_CTRL /* set the device control register for = CS5*/=0A= + sw t1, 0x58(t0)=0A= + li t1, DEV5_TC /* set the device timing register for CS5 */=0A= + sw t1, 0x5C(t0)=0A= +=0A= +/* ------------------ Initialize GPIO = ------------------------------------- */=0A= + li t0, GPIO_BASE=0A= + li t1, GPIO_FUNC=0A= + sw t1, 0x0(t0)=0A= + li t1, GPIO_CFG=0A= + sw t1, 0x4(t0)=0A= + li t1, GPIO_OUT=0A= + sw t1, 0x8(t0)=0A= +=0A= +/* ------------- Clear PCI Local Base Control registers = ------------------- */=0A= + li t0, 0xb8068000=0A= + sw zero, 0x18(t0)=0A= + sw zero, 0x24(t0)=0A= + sw zero, 0x30(t0)=0A= + sw zero, 0x3c(t0)=0A= +/* ------------------- Assert PCI reset = ----------------------------------- */=0A= + lw t1, (t0)=0A= + andi t2, t1, 0x1=0A= + beqz t2, 2f=0A= + nop=0A= + andi t2, t1, 0x3fe=0A= + sw t2, (t0)=0A= + li t2, 0x1000=0A= +1:=0A= + addi t2, -1=0A= + bnez t2, 1b=0A= + nop=0A= +2:=0A= + ori t2, t1, 0x1=0A= + sw t2, (t0)=0A= + lui t2, 0x2=0A= +rip:=0A= + lw t1, 4(t0)=0A= + and t1, t1, t2=0A= + bnez t1, rip=0A= + nop=0A= +=0A= + DISPLAY('I','S','D','R')=0A= +=0A= + li t0, SDRAM_BASE /* load t0 with internal registers' base address = */=0A= +=0A= +/*-------------- Initialize SDRAM Base and Mask Registers = ----------*/=0A= +=0A= + li t1, SDRAM_BNK0_BASE /* load SDRAM bank 0 physical address in t1 = */=0A= + sw t1, 0x0(t0) /* set SDRAM bank 0 base */=0A= + li t1, SDRAM_BNK1_BASE /* load SDRAM bank 1 physical address in t1 = */=0A= + sw t1, 0x8(t0) /* set SDRAM bank 1 base */=0A= + li t1, SDRAM_BNK0_ABASE /* load Alternate SDRAM bank 0 physical = address in t1 */=0A= + sw t1, 0x20(t0) /* set Alternate SDRAM bank 0 base */=0A= +=0A= + li t1, SDRAM_BNK0_MASK /* load SDRAM bank 0 size in t1 */=0A= + sw t1, 0x4(t0) /* set SDRAM bank 0 mask */=0A= + li t1, SDRAM_BNK1_MASK /* load SDRAM bank 1 size in t1 */=0A= + sw t1, 0xC(t0) /* set SDRAM bank 1 mask */=0A= + li t1, SDRAM_BNK0_AMASK /* load Alternate SDRAM bank 0 size in t1 = */=0A= + sw t1, 0x24(t0) /* set Alternate SDRAM bank 0 mask */=0A= +=0A= +/*-------------- Setup and Enable Refresh Timer = --------------------*/=0A= + li t1, DISABLE_TIMER /* load diable timer bit settings into t1 */=0A= + sw t1, 0x1C(t0) /* disable timer */=0A= + nop=0A= +=0A= +/*-------------- Enable SDRAM Controller = ---------------------------*/=0A= + li t1, SDRAM_CR_BS=0A= + sw t1, 0x10(t0)=0A= + nop=0A= + =0A= +/*-------------- Delay Loop = ----------------------------------------*/=0A= + li v0, 10000 /* 8x256us */=0A= +1: =0A= + bne v0, zero,1b=0A= + subu v0, 1 /* BDSLOT */=0A= + nop=0A= + nop=0A= +/*-------------- Setup Precharge Command = ---------------------------*/=0A= + li t2, 2=0A= + li t3, 0=0A= +1: =0A= + li t1, SDRAM_PC_VAL=0A= + sw t1, 0x10(t0)=0A= + nop=0A= + nop=0A= + lw t7, 0x10(t0)=0A= + nop=0A= + li t4, DATA_PATTERN=0A= + li t5, 0xA0000000 | SDRAM_BNK0_BASE=0A= + sw t4, 0x0(t5)=0A= + addu t3, 1=0A= + bne t3, t2, 1b=0A= + nop=0A= +/*-------------- Setup Refresh Command = -----------------------------*/=0A= + li t2, 8=0A= + li t3, 0=0A= +1: =0A= + li t1, SDRAM_RFRSH_CMD=0A= + sw t1, 0x10(t0)=0A= + sw t4, 0x0(t5) /* note: t5 not disturbed */=0A= + addu t3, 1=0A= + bne t3, t2, 1b=0A= + nop=0A= +/*-------------- Setup up to write to Mode Register = ----------------*/=0A= + li t1, SDRAM_MODE_REG=0A= + sw t1, 0x10(t0)=0A= + addu t5, 0x80=0A= + sw t4, 0x0(t5)=0A= +=0A= +/*-------------- Setup and Enable Refresh Timer = --------------------*/=0A= +=0A= + li t1, DISABLE_TIMER /* load diable timer bit settings into t1 = */=0A= + sw t1, 0x1c(t0) /* disable timer */=0A= + sw zero, 0x14(t0) /* set SDRAM refresh timer count register bit = settings */=0A= +=0A= + li t1, SDRAM_RF_CMPR_SE_BS /* load SDRAM refresh timer compare = register bit settings in t1 */=0A= + sw t1, 0x18(t0) /* set SDRAM refresh timer compare register bit = settings */=0A= +=0A= + li t1, ENABLE_TIMER /* load timer enable bit */=0A= + sw t1, 0x1c(t0) /* enable refresh timer */=0A= +=0A= + li t1, SDRAM_CR_BS=0A= + sw t1, 0x10(t0)=0A= +=0A= + /* the memory system may need some time to start up... */=0A= + li v0, 10000 /* 8x256us */=0A= +1: =0A= + bne v0, zero, 1b=0A= + subu v0, 1=0A= + nop=0A= + nop=0A= +=0A= +/**********************************************************************= **=0A= +** before doing anything=0A= +** initialize the section of memory used by cache initialization=0A= +** whenever you boot out of ROM or reset-vector=0A= +** This assumed to be 1MB.=0A= +** --Sugan (11-22-96)=0A= +***********************************************************************= */=0A= + =0A= + li t0, 0xa0000000=0A= + li t1, 0xa0100000=0A= +1:=0A= + sw zero, 0x00(t0)=0A= + sw zero, 0x04(t0)=0A= + sw zero, 0x08(t0)=0A= + sw zero, 0x0c(t0)=0A= + addiu t0, 16=0A= + nop=0A= + blt t0, t1, 1b=0A= + nop=0A= + nop=0A= + nop=0A= +3:=0A= + mfc0 t0, C0_SR=0A= + nop=0A= + nop=0A= + and t0, ~SR_BEV=0A= + mtc0 t0, C0_SR=0A= + nop=0A= + nop=0A= +=0A= + DISPLAY('U','N','Z','P')=0A= +=0A= +/* Jump to zImage start */=0A= + =0A= + la k0, zstartup=0A= + j k0=0A= + nop=0A= + nop=0A= + =0A= +ENDFRAME(start)=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/head.S = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/head.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/head.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/head.S 2006-03-09 = 16:25:47.000000000 -0800=0A= @@ -0,0 +1,134 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Board initialisation code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +=0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#define IndexInvalidate_I 0x00=0A= +=0A= + .set noreorder=0A= + .cprestore=0A= + LEAF(zstartup)=0A= +zstartup:=0A= +=0A= + la sp, .stack=0A= + move s0, a0=0A= + move s1, a1=0A= + move s2, a2=0A= + move s3, a3=0A= +=0A= + /* Clear BSS */=0A= + la a0, .stack=0A= + la a2, _end=0A= +1: sw zero, 0(a0)=0A= + bne a2, a0, 1b=0A= + addu a0, 4=0A= +#if 1=0A= + /* flush the I-Cache */=0A= + li k0, 0x80000000 # start address=0A= + li k1, 0x80002000 # end address (8KB I-Cache)=0A= + subu k1, 128=0A= +2:=0A= + .set mips3=0A= + cache IndexInvalidate_I, 0(k0)=0A= + cache IndexInvalidate_I, 16(k0)=0A= + cache IndexInvalidate_I, 32(k0)=0A= + cache IndexInvalidate_I, 48(k0)=0A= + cache IndexInvalidate_I, 64(k0)=0A= + cache IndexInvalidate_I, 80(k0)=0A= + cache IndexInvalidate_I, 96(k0)=0A= + cache IndexInvalidate_I, 112(k0)=0A= + .set mips0=0A= +=0A= + bne k0, k1, 2b=0A= + addu k0, k0, 128=0A= + /* done */=0A= +#endif=0A= +#if 1=0A= + /* flush the D-Cache */=0A= + li k0, 0x80000000 # start address=0A= + li k1, 0x80000400 # end address (2KB I-Cache)=0A= + subu k1, 128=0A= +3: =0A= + .set mips3=0A= + /* First way */=0A= + cache Index_Writeback_Inv_D, 0(k0)=0A= + cache Index_Writeback_Inv_D, 16(k0)=0A= + cache Index_Writeback_Inv_D, 32(k0)=0A= + cache Index_Writeback_Inv_D, 48(k0)=0A= + cache Index_Writeback_Inv_D, 64(k0)=0A= + cache Index_Writeback_Inv_D, 80(k0)=0A= + cache Index_Writeback_Inv_D, 96(k0)=0A= + cache Index_Writeback_Inv_D, 112(k0)=0A= + /* Second way */=0A= + cache Index_Writeback_Inv_D, 1024(k0)=0A= + cache Index_Writeback_Inv_D, 1040(k0)=0A= + cache Index_Writeback_Inv_D, 1056(k0)=0A= + cache Index_Writeback_Inv_D, 1072(k0)=0A= + cache Index_Writeback_Inv_D, 1088(k0)=0A= + cache Index_Writeback_Inv_D, 1104(k0)=0A= + cache Index_Writeback_Inv_D, 1120(k0)=0A= + cache Index_Writeback_Inv_D, 1136(k0)=0A= + .set mips0=0A= +=0A= + bne k0, k1, 3b=0A= + addu k0, k0, 128=0A= + /* done */=0A= +#endif=0A= + =0A= +=0A= + la ra, 4f=0A= + la k0, decompress_kernel=0A= + jr k0=0A= + nop=0A= +4:=0A= +=0A= + move a0, s0=0A= + move a1, s1=0A= + move a2, s2=0A= + move a3, s3=0A= + li k0, KERNEL_ENTRY=0A= + jr k0=0A= + nop=0A= +5:=0A= + b 5b=0A= + END(zstartup)=0A= +=0A= + .bss=0A= + .fill 0x2000=0A= + EXPORT(.stack)=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/idtcpu.h = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/idtcpu.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/idtcpu.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/idtcpu.h = 2006-03-09 16:25:47.000000000 -0800=0A= @@ -0,0 +1,614 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT CPU register definitions. Though the registers are already = defined=0A= + * under asm directory, they are once again declared here for the = ease of=0A= + * syncing up with IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#if defined(__IDTCPU_H__)=0A= +#else=0A= +#define __IDTCPU_H__=0A= +=0A= +=0A= +/*=0A= +** memory configuration and mapping=0A= +*/=0A= +#define K0BASE 0x80000000=0A= +#define K0SIZE 0x20000000=0A= +#define K1BASE 0xa0000000=0A= +#define K1SIZE 0x20000000=0A= +#define K2BASE 0xc0000000=0A= +#if defined(S364)=0A= +#define K2SIZE 0x3e000000=0A= +#define ICEBASE 0xff000000=0A= +#define ICESIZE 0x01000000=0A= +#else=0A= +#define K2SIZE 0x20000000=0A= +#endif=0A= +#if defined(CPU_R4000)=0A= +#define KSBASE 0xe0000000=0A= +#define KSSIZE 0x20000000=0A= +#endif=0A= +=0A= +#define KUBASE 0=0A= +#define KUSIZE 0x80000000=0A= +=0A= +/*=0A= +** Exception Vectors=0A= +*/=0A= +#if defined(CPU_R3000)=0A= +#define UT_VEC K0BASE /* utlbmiss vector */=0A= +#define E_VEC (K0BASE+0x80) /* exception vevtor */=0A= +#endif=0A= +#if defined(CPU_R4000) || defined S364 /*(CPU_R32364) */=0A= +#define T_VEC (K0BASE+0x000) /* tlbmiss vector */=0A= +#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */=0A= +#define C_VEC (K1BASE+0x100) /* cache error vector */=0A= +#define E_VEC (K0BASE+0x180) /* exception vector */=0A= +#define I_VEC (K0BASE+0X200) /* interrupt vector */=0A= +#endif=0A= +#define R_VEC (K1BASE+0x1fc00000) /* reset vector */=0A= +=0A= +/*=0A= +** Address conversion macros=0A= +*/=0A= +#ifdef CLANGUAGE=0A= +#define CAST(as) (as)=0A= +#else=0A= +#define CAST(as)=0A= +#endif=0A= +#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 = */=0A= +#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 = */=0A= +#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to = physical */=0A= +#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to = physical */=0A= +#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to = kseg0 */=0A= +#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to = kseg1 */=0A= +=0A= +/*=0A= +** Cache size constants=0A= +*/=0A= +/* Sugan changed so that MINCACHE is 0x200 instead of 0x800 */=0A= +#define MINCACHE 0x200 /* 512 bytes */=0A= +#define MAXCACHE 0x40000 /* 256*1024 256k */ =0A= +=0A= +#if defined CPU_R32364 /* Includes RC32364, RC32332, = RC32334 */=0A= +#define CFG_ICE 0x80000000 /* ICE detect */=0A= +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */=0A= +#define CFG_ECBY2 0x00000000 /* divide by 2 */=0A= +#define CFG_ECBY3 0x10000000 /* divide by 3 */=0A= +#define CFG_ECBY4 0x20000000 /* divide by 4 */=0A= +#define CFG_NBL 0x00800000 /* Non-Blocking load pending */=0A= +#define CFG_BE 0x00008000 /* Big Endian */=0A= +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */=0A= +#define CFG_ICSHIFT 9=0A= +#define CFG_DCMASK 0x000001c0 /* Data cache size */=0A= +#define CFG_DCSHIFT 6=0A= +#define CFG_IB 0x00000020 /* Instruction cache line size */=0A= +#define CFG_DB 0x00000010 /* Data cache line size */=0A= +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */=0A= +=0A= +/*=0A= + * R32364 primary cache mode=0A= + */=0A= +#define CFG_C_NCHRNT_WT_NWA 0=0A= +#define CFG_C_NCHRNT_WT 1=0A= +#define CFG_C_UNCACHED 2=0A= +#define CFG_C_NCHRNT_WB 3=0A= +=0A= +/* Cache Operations */=0A= +#define Index_Invalidate_I 0x0 /* 0 0 = */=0A= +#define Index_Writeback_Inv_D 0x1 /* 0 1 = */=0A= +#define Index_Invalidate_SI 0x2 /* 0 2 = */=0A= +#define Index_Writeback_Inv_SD 0x3 /* 0 3 = */=0A= +#define Index_Load_Tag_I 0x4 /* 1 0 = */=0A= +#define Index_Load_Tag_D 0x5 /* 1 1 = */=0A= +#define Index_Load_Tag_SI 0x6 /* 1 2 = */=0A= +#define Index_Load_Tag_SD 0x7 /* 1 3 = */=0A= +#define Index_Store_Tag_I 0x8 /* 2 0 = */=0A= +#define Index_Store_Tag_D 0x9 /* 2 1 = */=0A= +#define Index_Store_Tag_SI 0xA /* 2 2 = */=0A= +#define Index_Store_Tag_SD 0xB /* 2 3 = */=0A= +#define Create_Dirty_Exc_D 0xD /* 3 1 = */=0A= +#define Create_Dirty_Exc_SD 0xF /* 3 3 = */=0A= +#define Hit_Invalidate_I 0x10 /* 4 0 = */=0A= +#define Hit_Invalidate_D 0x11 /* 4 1 = */=0A= +#define Hit_Invalidate_SI 0x12 /* 4 2 = */=0A= +#define Hit_Invalidate_SD 0x13 /* 4 3 = */=0A= +#define Hit_Writeback_Inv_D 0x15 /* 5 1 = */=0A= +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 = */=0A= +#define Fill_I 0x14 /* 5 0 = */=0A= +#define Hit_Writeback_D 0x19 /* 6 1 = */=0A= +#define Hit_Writeback_SD 0x1B /* 6 3 = */=0A= +#define Hit_Writeback_I 0x18 /* 6 0 = */=0A= +#define Hit_Set_Virtual_SI 0x1E /* 7 2 = */=0A= +#define Hit_Set_Virtual_SD 0x1F /* 7 3 = */=0A= +#define CFG_EW32 0x00040000 /* 32 bit */=0A= +#endif /* CPU_R32364 */=0A= +=0A= +#if defined(CPU_R4000)=0A= +/* R4000 configuration register definitions */=0A= +#define CFG_CM 0x80000000 /* Master-Checker mode */=0A= +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */=0A= +#define CFG_ECBY2 0x00000000 /* divide by 2 */=0A= +#define CFG_ECBY3 0x10000000 /* divide by 3 */=0A= +#define CFG_ECBY4 0x20000000 /* divide by 4 */=0A= +#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */=0A= +#define CFG_EPD 0x00000000 /* D */=0A= +#define CFG_EPDDX 0x01000000 /* DDX */=0A= +#define CFG_EPDDXX 0x02000000 /* DDXX */=0A= +#define CFG_EPDXDX 0x03000000 /* DXDX */=0A= +#define CFG_EPDDXXX 0x04000000 /* DDXXX */=0A= +#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */=0A= +#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */=0A= +#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */=0A= +#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */=0A= +#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */=0A= +#define CFG_SBSHIFT 22=0A= +#define CFG_SB4 0x00000000 /* 4 words */=0A= +#define CFG_SB8 0x00400000 /* 8 words */=0A= +#define CFG_SB16 0x00800000 /* 16 words */=0A= +#define CFG_SB32 0x00c00000 /* 32 words */=0A= +#define CFG_SS 0x00200000 /* Split secondary cache */=0A= +#define CFG_SW 0x00100000 /* Secondary cache port width */=0A= +#define CFG_EWMASK 0x000c0000 /* System port width */=0A= +#define CFG_EWSHIFT 18=0A= +#define CFG_EW64 0x00000000 /* 64 bit */=0A= +#define CFG_EW32 0x00040000 /* 32 bit */=0A= +/* #if defined(CPU_R5000) */=0A= +/* Sugan added for R5000 L2 cache 07-17-96 */=0A= +#define L2_PAGESIZE 0x1000=0A= +#define SIZE256K 0x00040000 /* 256KB in Hex */=0A= +#define CFG_HARDL2 0x00020000 /* Hardware bit that enables/disables=0A= + L2 cache */=0A= +#define CFG_SE 0x1000=0A= +#define CFG_SIZE512K 0x00000000 /* size of Scache is 512k */=0A= +#define CFG_SIZE1MB 0x00100000 /* size of Scache is 1MB */=0A= +#define CFG_SIZE2MB 0x00200000 /* size of Scache is 2MB */=0A= +#define CFG_SIZEMASK 0x00300000 /* size mask */=0A= +/* #endif */=0A= +#define CFG_SC 0x00020000 /* Secondary cache absent */=0A= +#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */=0A= +#define CFG_BE 0x00008000 /* Big Endian */=0A= +#define CFG_EM 0x00004000 /* ECC mode enable */=0A= +#define CFG_EB 0x00002000 /* Block ordering */=0A= +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */=0A= +#define CFG_ICSHIFT 9=0A= +#define CFG_DCMASK 0x000001c0 /* Data cache size */=0A= +#define CFG_DCSHIFT 6=0A= +#define CFG_IB 0x00000020 /* Instruction cache block size */=0A= +#define CFG_DB 0x00000010 /* Data cache block size */=0A= +#define CFG_CU 0x00000008 /* Update on Store Conditional */=0A= +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */=0A= +=0A= +/*=0A= + * R4000 primary cache mode=0A= + */=0A= +#define CFG_C_WRITETHROUGH_CACHE 0=0A= +#define CFG_C_UNCACHED 2=0A= +#define CFG_C_NONCOHERENT 3=0A= +#define CFG_C_COHERENTXCL 4=0A= +#define CFG_C_COHERENTXCLW 5=0A= +#define CFG_C_COHERENTUPD 6=0A= +=0A= +/*=0A= + * R4000 cache operations (should be in assembler...?)=0A= + */=0A= +#if defined(CPU_R5000)=0A= +#define InvAllScache 0x03 /* 0 3 */=0A= +#define IndexLoadTagScache 0x07 /* 1 3 */=0A= +#define IndexStoreTagScache 0x0b /* 2 3 */=0A= +#define PageInvScache 0x17 /* 5 3 */=0A= +#endif=0A= +#define Index_Invalidate_I 0x0 /* 0 0 = */=0A= +#define Index_Writeback_Inv_D 0x1 /* 0 1 = */=0A= +#define Index_Invalidate_SI 0x2 /* 0 2 = */=0A= +#define Index_Writeback_Inv_SD 0x3 /* 0 3 = */=0A= +#define Index_Load_Tag_I 0x4 /* 1 0 = */=0A= +#define Index_Load_Tag_D 0x5 /* 1 1 = */=0A= +#define Index_Load_Tag_SI 0x6 /* 1 2 = */=0A= +#define Index_Load_Tag_SD 0x7 /* 1 3 = */=0A= +#define Index_Store_Tag_I 0x8 /* 2 0 = */=0A= +#define Index_Store_Tag_D 0x9 /* 2 1 = */=0A= +#define Index_Store_Tag_SI 0xA /* 2 2 = */=0A= +#define Index_Store_Tag_SD 0xB /* 2 3 = */=0A= +#define Create_Dirty_Exc_D 0xD /* 3 1 = */=0A= +#define Create_Dirty_Exc_SD 0xF /* 3 3 = */=0A= +#define Hit_Invalidate_I 0x10 /* 4 0 = */=0A= +#define Hit_Invalidate_D 0x11 /* 4 1 = */=0A= +#define Hit_Invalidate_SI 0x12 /* 4 2 = */=0A= +#define Hit_Invalidate_SD 0x13 /* 4 3 = */=0A= +#define Hit_Writeback_Inv_D 0x15 /* 5 1 = */=0A= +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 = */=0A= +#define Fill_I 0x14 /* 5 0 = */=0A= +#define Hit_Writeback_D 0x19 /* 6 1 = */=0A= +#define Hit_Writeback_SD 0x1B /* 6 3 = */=0A= +#define Hit_Writeback_I 0x18 /* 6 0 = */=0A= +#define Hit_Set_Virtual_SI 0x1E /* 7 2 = */=0A= +#define Hit_Set_Virtual_SD 0x1F /* 7 3 = */=0A= +=0A= +#endif=0A= +=0A= +/*=0A= +** TLB resource defines=0A= +*/=0A= +=0A= +#if defined(CPU_R32364) =0A= +#define N_TLB_ENTRIES 16=0A= +#endif =0A= +=0A= +#if defined(CPU_R4000)=0A= +#define N_TLB_ENTRIES 48=0A= +#endif=0A= +=0A= +#if defined (CPU_R32364)=0A= +#define TLBHI_VPN2MASK 0xffffe000=0A= +#define TLBHI_PIDMASK 0x000000ff=0A= +#define TLBHI_NPID 256=0A= +=0A= +#define TLBLO_PFNMASK 0x03ffffc0=0A= +#define TLBLO_PFNSHIFT 6=0A= +#define TLBLO_D 0x00000004 /* writeable */=0A= +#define TLBLO_V 0x00000002 /* valid bit */=0A= +#define TLBLO_G 0x00000001 /* global access bit */=0A= +#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */=0A= +#define TLBLO_CSHIFT 3=0A= +=0A= +#define TLBLO_UNCACHED (CFG_C_UNCACHED< k, 1 =3D> u = */=0A= +#define SR_IEO 0x00000010 /* old interrupt enable, 1 =3D> enable = */=0A= +#define SR_KUP 0x00000008 /* prev kernel/user, 0 =3D> k, 1 =3D> u = */=0A= +#define SR_IEP 0x00000004 /* prev interrupt enable, 1 =3D> enable = */=0A= +#define SR_KUC 0x00000002 /* cur kernel/user, 0 =3D> k, 1 =3D> u = */=0A= +#define SR_IEC 0x00000001 /* cur interrupt enable, 1 =3D> enable = */=0A= +#endif=0A= +=0A= +#if defined S364 /* (CPU_R32364) */=0A= +#define SR_CUMASK 0xf0000000 /* coproc usable bits */=0A= +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */=0A= +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */=0A= +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */=0A= +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */=0A= +=0A= +/* defines for R32364 processor */=0A= +#define SR_NBL 0x08000000 /* Non Blocking Load */=0A= +#define SR_RE 0X02000000 /* Reverse Endianness */=0A= +#define SR_DL 0x01000000 /* Data Cache Locking */=0A= +#define SR_IL 0x00800000 /* Instruction Cache Locking */=0A= +=0A= +#define SR_BEV 0x00400000 /* Use boot exception vectors */=0A= +#define SR_SR 0x00100000 /* Soft reset */=0A= +#define SR_CH 0x00040000 /* Cache hit */=0A= +#define SR_CE 0x00020000 /* Use cache ECC */=0A= +#define SR_DE 0x00010000 /* Disable cache exceptions */=0A= +=0A= +/*=0A= +** status register interrupt masks and bits=0A= +*/=0A= +=0A= +#define SR_IMASK 0x0000ff00 /* Interrupt mask */=0A= +#define SR_IMASK8 0x00000000 /* mask level 8 */=0A= +#define SR_IMASK7 0x00008000 /* mask level 7 */=0A= +#define SR_IMASK6 0x0000c000 /* mask level 6 */=0A= +#define SR_IMASK5 0x0000e000 /* mask level 5 */=0A= +#define SR_IMASK4 0x0000f000 /* mask level 4 */=0A= +#define SR_IMASK3 0x0000f800 /* mask level 3 */=0A= +#define SR_IMASK2 0x0000fc00 /* mask level 2 */=0A= +#define SR_IMASK1 0x0000fe00 /* mask level 1 */=0A= +#define SR_IMASK0 0x0000ff00 /* mask level 0 */=0A= +=0A= +#define SR_IMASKSHIFT 8=0A= +=0A= +#define SR_IBIT8 0x00008000 /* bit level 8 */=0A= +#define SR_IBIT7 0x00004000 /* bit level 7 */=0A= +#define SR_IBIT6 0x00002000 /* bit level 6 */=0A= +#define SR_IBIT5 0x00001000 /* bit level 5 */=0A= +#define SR_IBIT4 0x00000800 /* bit level 4 */=0A= +#define SR_IBIT3 0x00000400 /* bit level 3 */=0A= +#define SR_IBIT2 0x00000200 /* bit level 2 */=0A= +#define SR_IBIT1 0x00000100 /* bit level 1 */=0A= +=0A= +#define SR_KSMASK 0x00000016 /* Kernel mode mask */=0A= +#define SR_KSUSER 0x00000000 /* User Mode */=0A= +#define SR_KSKERNEL 0x00000016 /* Kernel Mode */=0A= +=0A= +#define SR_ERL 0x00000004 /* Error level */=0A= +#define SR_EXL 0x00000002 /* Exception level */=0A= +#define SR_IE 0x00000001 /* Interrupts enabled */=0A= +#define NOT_SR_IEC 0xfffffffe /* assembler problem with = li=0A= +~SR_IEC */=0A= +=0A= +/* R32364 Cache locking bits */=0A= +#define SR_ICACHELOCK 0x00800000=0A= +#define SR_DCACHELOCK 0x01000000=0A= +=0A= +#endif /* CPU_R32364 */=0A= +=0A= +#if defined(CPU_R4000)=0A= +#define SR_CUMASK 0xf0000000 /* coproc usable bits */=0A= +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */=0A= +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */=0A= +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */=0A= +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */=0A= +=0A= +#define SR_RP 0x08000000 /* Reduced power operation */=0A= +#define SR_FR 0x04000000 /* Additional floating pt registers */=0A= +#define SR_RE 0x02000000 /* Reverse endian in user mode */=0A= +=0A= +#define SR_BEV 0x00400000 /* Use boot exception vectors */=0A= +#define SR_TS 0x00200000 /* TLB shutdown */=0A= +#define SR_SR 0x00100000 /* Soft reset */=0A= +#define SR_CH 0x00040000 /* Cache hit */=0A= +#define SR_CE 0x00020000 /* Use cache ECC */=0A= +#define SR_DE 0x00010000 /* Disable cache exceptions */=0A= +=0A= +/*=0A= +** status register interrupt masks and bits=0A= +*/=0A= +=0A= +#define SR_IMASK 0x0000ff00 /* Interrupt mask */=0A= +#define SR_IMASK8 0x00000000 /* mask level 8 */=0A= +#define SR_IMASK7 0x00008000 /* mask level 7 */=0A= +#define SR_IMASK6 0x0000c000 /* mask level 6 */=0A= +#define SR_IMASK5 0x0000e000 /* mask level 5 */=0A= +#define SR_IMASK4 0x0000f000 /* mask level 4 */=0A= +#define SR_IMASK3 0x0000f800 /* mask level 3 */=0A= +#define SR_IMASK2 0x0000fc00 /* mask level 2 */=0A= +#define SR_IMASK1 0x0000fe00 /* mask level 1 */=0A= +#define SR_IMASK0 0x0000ff00 /* mask level 0 */=0A= +=0A= +#define SR_IMASKSHIFT 8=0A= +=0A= +#define SR_IBIT8 0x00008000 /* bit level 8 */=0A= +#define SR_IBIT7 0x00004000 /* bit level 7 */=0A= +#define SR_IBIT6 0x00002000 /* bit level 6 */=0A= +#define SR_IBIT5 0x00001000 /* bit level 5 */=0A= +#define SR_IBIT4 0x00000800 /* bit level 4 */=0A= +#define SR_IBIT3 0x00000400 /* bit level 3 */=0A= +#define SR_IBIT2 0x00000200 /* bit level 2 */=0A= +#define SR_IBIT1 0x00000100 /* bit level 1 */=0A= +=0A= +#define SR_KSMASK 0x00000018 /* Kernel mode mask */=0A= +#define SR_KSUSER 0x00000010 /* User mode */=0A= +#define SR_KSSUPER 0x00000008 /* Supervisor mode */=0A= +#define SR_KSKERNEL 0x00000000 /* Kernel mode */=0A= +#define SR_ERL 0x00000004 /* Error level */=0A= +#define SR_EXL 0x00000002 /* Exception level */=0A= +#define SR_IE 0x00000001 /* Interrupts enabled */=0A= +=0A= +/* R4650 Cache locking bits */=0A= +#define SR_ICACHELOCK 0x00800000=0A= +#define SR_DCACHELOCK 0x01000000=0A= +=0A= +=0A= +#endif=0A= +#if defined(CPU_R3000)=0A= +#define SR_FR 0x04000000 /* Additional floating point registers */=0A= +#endif=0A= +=0A= +=0A= +=0A= +/*=0A= + * Cause Register=0A= + */=0A= +#define CAUSE_BD 0x80000000 /* Branch delay slot */=0A= +#define CAUSE_CEMASK 0x30000000 /* coprocessor error */=0A= +#define CAUSE_CESHIFT 28=0A= +#define CAUSE_IW 0x01000000 /* Instruction watch */=0A= +#define CAUSE_DW 0x02000000 /* Data watch */=0A= +#define CAUSE_IPE 0x04000000 /* Imprecise exception */=0A= +=0A= +=0A= +#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */=0A= +#define CAUSE_IPSHIFT 8=0A= +=0A= +/* Notice: Watch Exception if Exc. Code is 23 is not included in the = mask=0A= + * for R32364.=0A= + */=0A= +#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */=0A= +#define CAUSE_EXCSHIFT 2=0A= +=0A= +#ifndef XDS=0A= +/*=0A= +** Coprocessor 0 registers=0A= +*/=0A= +=0A= +/* Evelyn, 12/12/94, for P3 */=0A= +#define C0_IBASE $0 /* I base */=0A= +#define C0_IBOUND $1 /* I bound */=0A= +=0A= +#define C0_INX $0 /* tlb index */=0A= +#define C0_RAND $1 /* tlb random */=0A= +#if defined(CPU_R3000)=0A= +#define C0_TLBLO $2 /* tlb entry low */=0A= +#define C0_BUSCTRL $2 /* bus control R3041 specific */=0A= +#define C0_CONFIG $3 /* cache config */=0A= +#define C0_CTXT $4 /* tlb context */=0A= +#define C0_BADVADDR $8 /* bad virtual address */=0A= +#define C0_COUNT $9 /* count R3041 specific */=0A= +#define C0_PORTSIZE $10 /* port size R3041 specific */=0A= +#define C0_TLBHI $10 /* tlb entry hi */=0A= +#define C0_COMPARE $11 /* compare R3041 specific */=0A= +#define C0_SR $12 /* status register */=0A= +#define C0_CAUSE $13 /* exception cause */=0A= +#define C0_EPC $14 /* exception pc */=0A= +#define C0_PRID $15 /* revision identifier */=0A= +#endif=0A= +=0A= +#if defined(S364) /*(CPU_R32364) */=0A= +#define C0_RANDOM $1=0A= +#define C0_TLBLO0 $2 /* tlb entry low 0 */=0A= +#define C0_TLBLO1 $3 /* tlb entry low 1 */=0A= +#define C0_CTXT $4 /* tlb context */=0A= +#define C0_PAGEMASK $5 /* tlb page mask */=0A= +#define C0_WIRED $6 /* number of wired tlb entries */=0A= +=0A= +#define C0_INX $0 /* tlb index */=0A= +#define C0_BADVADDR $8 /* bad virtual address */=0A= +#define C0_COUNT $9 /* timer count */=0A= +#define C0_TLBHI $10 /* tlb entry hi */=0A= +#define C0_COMPARE $11 /* timer comparator */=0A= +#define C0_SR $12 /* status register */=0A= +#define C0_CAUSE $13 /* exception cause */=0A= +#define C0_EPC $14 /* exception pc */=0A= +#define C0_PRID $15 /* revision identifier */=0A= +#define C0_CONFIG $16 /* configuration register */=0A= +=0A= +#define C0_IWATCH $18 /* Instr brk pt Virtual add. */=0A= +#define C0_DWATCH $19 /* Data brk pt Virtual add. */=0A= +=0A= +#define C0_IEPC $22 /* Imprecise Exception pc */=0A= +#define C0_DEPC $23 /* Debug Exception pc */=0A= +#define C0_DEBUG $24 /* Debug control/status reg */=0A= +=0A= +#define C0_ECC $26 /* primary cache Parity control */=0A= +#define C0_CACHEERR $27 /* cache error status */=0A= +#define C0_TAGLO $28 /* cache tag lo */=0A= +#define C0_TAGHI $29=0A= +#define C0_ERRPC $30 /* cache error pc */=0A= +#endif /* CPU_R32364 */=0A= +=0A= +#if defined(CPU_R4000)=0A= +=0A= +/* Evelyn, 12/12/94, for P3 */=0A= +#define C0_DBASE $2 /* D base */=0A= +#define C0_DBOUND $3 /* D bound */=0A= +=0A= +#define C0_TLBLO0 $2 /* tlb entry low 0 */=0A= +#define C0_TLBLO1 $3 /* tlb entry low 1 */=0A= +#define C0_CTXT $4 /* tlb context */=0A= +#define C0_PAGEMASK $5 /* tlb page mask */=0A= +#define C0_WIRED $6 /* number of wired tlb entries */=0A= +=0A= +#define C0_BADVADDR $8 /* bad virtual address */=0A= +#define C0_COUNT $9 /* cycle count */=0A= +#define C0_TLBHI $10 /* tlb entry hi */=0A= +#define C0_COMPARE $11 /* cyccle count comparator */=0A= +#define C0_SR $12 /* status register */=0A= +#define C0_CAUSE $13 /* exception cause */=0A= +#define C0_EPC $14 /* exception pc */=0A= +#define C0_PRID $15 /* revision identifier */=0A= +#define C0_CONFIG $16 /* configuration register */=0A= +=0A= +/* Evelyn, 12/12/94, for P3 */=0A= +#define C0_CALG $17 /* Calg rigister */=0A= +#define C0_IWATCH $18 /* IWatch register */=0A= +#define C0_DWATCH $19 /* DWatch register */=0A= +=0A= +#define C0_LLADDR $17 /* linked load address */=0A= +#define C0_WATCHLO $18 /* watchpoint trap register */=0A= +#define C0_WATCHHI $19 /* watchpoint trap register */=0A= +#define C0_XCTXT $20 /* extended tlb context */=0A= +#define C0_ECC $26 /* secondary cache ECC control */=0A= +#define C0_CACHEERR $27 /* cache error status */=0A= +#define C0_TAGLO $28 /* cache tag lo */=0A= +#define C0_TAGHI $29 /* cache tag hi */=0A= +#define C0_ERRPC $30 /* cache error pc */=0A= +#endif=0A= +#endif =0A= +#endif /* defined(__IDTCPU_H__) */=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/idthdr.h = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/idthdr.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/idthdr.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/idthdr.h = 2006-03-09 16:25:47.000000000 -0800=0A= @@ -0,0 +1,54 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Some macros. Though they are already defined else where in the = linux=0A= + * tree, they are once again declared here for the ease of syncing = up with=0A= + * IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef XDS=0A= +=0A= +#define FRAME(name,frm_reg,offset,ret_reg) \=0A= + .globl name; \=0A= + .ent name; \=0A= +name:; \=0A= + .frame frm_reg,offset,ret_reg=0A= +=0A= +#define ENDFRAME(name) .end name=0A= +=0A= +#else=0A= +=0A= +#define FRAME(name,frm_reg,offset,ret_reg) \=0A= +name:=0A= +=0A= +#define ENDFRAME(name)=0A= +=0A= +#endif=0A= +=0A= +=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/image.lds.in = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/image.lds.in=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/image.lds.in = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/image.lds.in = 2006-03-09 16:25:47.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D IMSTART;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32300/EB365/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D BSS_START;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/iregdef.h = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/iregdef.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/iregdef.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/iregdef.h = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,285 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT CPU register definitions. Though the registers are already = defined=0A= + * under asm directory, they are once again declared here for the = ease of=0A= + * syncing up with IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#define r0 $0=0A= +#define r1 $1 /*at assembler temp */=0A= +#define r2 $2 /*v0 return value */=0A= +#define r3 $3 /*v1 return value */=0A= +#define r4 $4 /*a0 argument 0 */=0A= +#define r5 $5 /*a1 argument 1 */=0A= +#define r6 $6=0A= +#define r7 $7=0A= +#define r8 $8=0A= +#define r9 $9=0A= +#define r10 $10=0A= +#define r11 $11=0A= +#define r12 $12=0A= +#define r13 $13=0A= +=0A= +#define r14 $14=0A= +#define r15 $15=0A= +#define r16 $16 /*s0 called saved */=0A= +#define r17 $17=0A= +#define r18 $18=0A= +#define r19 $19=0A= +#define r20 $20=0A= +#define r21 $21=0A= +#define r22 $22=0A= +#define r23 $23 /*s7 called saved */=0A= +#define r24 $24=0A= +#define r25 $25=0A= +#define r26 $26 /*k0 kernel temp. */=0A= +#define r27 $27 /*k1 "" "" */=0A= +#define r28 $28 /*gp global pointer */=0A= +#define r29 $29 /*sp stack pointer */=0A= +#define r30 $30 /*fp frame pointer */=0A= +#define r31 $31 /*ra return address */=0A= +=0A= +#define fp0 $f0=0A= +#define fp1 $f1=0A= +#define fp2 $f2=0A= +#define fp3 $f3=0A= +#define fp4 $f4=0A= +#define fp5 $f5=0A= +#define fp6 $f6=0A= +#define fp7 $f7=0A= +#define fp8 $f8=0A= +#define fp9 $f9=0A= +#define fp10 $f10=0A= +#define fp11 $f11=0A= +#define fp12 $f12=0A= +#define fp13 $f13=0A= +#define fp14 $f14=0A= +#define fp15 $f15=0A= +#define fp16 $f16=0A= +#define fp17 $f17=0A= +#define fp18 $f18=0A= +#define fp19 $f19=0A= +#define fp20 $f20=0A= +#define fp21 $f21=0A= +#define fp22 $f22=0A= +#define fp23 $f23=0A= +#define fp24 $f24=0A= +#define fp25 $f25=0A= +#define fp26 $f26=0A= +#define fp27 $f27=0A= +#define fp28 $f28=0A= +#define fp29 $f29=0A= +#define fp30 $f30=0A= +#define fp31 $f31=0A= +=0A= +#define fcr0 $0=0A= +#define fcr30 $30=0A= +#define fcr31 $31=0A= +=0A= +#define zero $0 /* wired zero */=0A= +#define AT $at /* assembler temp */=0A= +#define v0 $2 /* return value */=0A= +#define v1 $3=0A= +#define a0 $4 /* argument registers */=0A= +#define a1 $5=0A= +#define a2 $6=0A= +#define a3 $7=0A= +#define t0 $8 /* caller saved */=0A= +#define t1 $9=0A= +#define t2 $10=0A= +#define t3 $11=0A= +#define t4 $12=0A= +#define t5 $13=0A= +#define t6 $14=0A= +#define t7 $15=0A= +#define s0 $16 /* callee saved */=0A= +#define s1 $17=0A= +#define s2 $18=0A= +#define s3 $19=0A= +#define s4 $20=0A= +#define s5 $21=0A= +#define s6 $22=0A= +#define s7 $23=0A= +#define t8 $24 /* code generator */=0A= +#define t9 $25=0A= +#define k0 $26 /* kernel temporary */=0A= +#define k1 $27=0A= +#define gp $28 /* global pointer */=0A= +#define sp $29 /* stack pointer */=0A= +#define s8 $30 /* yet another saved reg for the callee */=0A= +#define fp $30 /* frame pointer - this is being phased out by MIPS = */=0A= +#define ra $31 /* return address */=0A= +=0A= +=0A= +/*=0A= + * register names=0A= + */=0A= +#define R_R0 0=0A= +#define R_R1 1=0A= +#define R_R2 2=0A= +#define R_R3 3=0A= +#define R_R4 4=0A= +#define R_R5 5=0A= +#define R_R6 6=0A= +#define R_R7 7=0A= +#define R_R8 8=0A= +#define R_R9 9=0A= +#define R_R10 10=0A= +#define R_R11 11=0A= +#define R_R12 12=0A= +#define R_R13 13=0A= +#define R_R14 14=0A= +#define R_R15 15=0A= +#define R_R16 16=0A= +#define R_R17 17=0A= +#define R_R18 18=0A= +#define R_R19 19=0A= +#define R_R20 20=0A= +#define R_R21 21=0A= +#define R_R22 22=0A= +#define R_R23 23=0A= +#define R_R24 24=0A= +#define R_R25 25=0A= +#define R_R26 26=0A= +#define R_R27 27=0A= +#define R_R28 28=0A= +#define R_R29 29=0A= +#define R_R30 30=0A= +#define R_R31 31=0A= +#define R_F0 32=0A= +#define R_F1 33=0A= +#define R_F2 34=0A= +#define R_F3 35=0A= +#define R_F4 36=0A= +#define R_F5 37=0A= +#define R_F6 38=0A= +#define R_F7 39=0A= +#define R_F8 40=0A= +#define R_F9 41=0A= +#define R_F10 42=0A= +#define R_F11 43=0A= +#define R_F12 44=0A= +#define R_F13 45=0A= +#define R_F14 46=0A= +#define R_F15 47=0A= +#define R_F16 48=0A= +#define R_F17 49=0A= +#define R_F18 50=0A= +#define R_F19 51=0A= +#define R_F20 52=0A= +#define R_F21 53=0A= +#define R_F22 54=0A= +#define R_F23 55=0A= +#define R_F24 56=0A= +#define R_F25 57=0A= +#define R_F26 58=0A= +#define R_F27 59=0A= +#define R_F28 60=0A= +#define R_F29 61=0A= +#define R_F30 62=0A= +#define R_F31 63=0A= +#define NCLIENTREGS 64=0A= +#define R_EPC 64=0A= +#define R_MDHI 65=0A= +#define R_MDLO 66=0A= +#define R_SR 67=0A= +#define R_CAUSE 68=0A= +#define R_TLBHI 69=0A= +#ifdef CPU_R4000=0A= +#define R_TLBLO0 70=0A= +#else=0A= +#define R_TLBLO 70=0A= +#endif=0A= +#define R_BADVADDR 71=0A= +#define R_INX 72=0A= +#define R_RAND 73=0A= +#define R_CTXT 74=0A= +#define R_EXCTYPE 75=0A= +#define R_MODE 76=0A= +#define R_PRID 77=0A= +#define R_FCSR 78=0A= +#define R_FEIR 79=0A= +#ifdef CPU_R4000=0A= +#define R_TLBLO1 80=0A= +#define R_PAGEMASK 81=0A= +#define R_WIRED 82=0A= +#define R_COUNT 83=0A= +#define R_COMPARE 84=0A= +#define R_CONFIG 85=0A= +#define R_LLADDR 86=0A= +#define R_WATCHLO 87=0A= +#define R_WATCHHI 88=0A= +#define R_ECC 89=0A= +#define R_CACHEERR 90=0A= +#define R_TAGLO 91=0A= +#define R_TAGHI 92=0A= +#define R_ERRPC 93=0A= +#endif=0A= +=0A= +#ifdef CPU_R4000=0A= +#define NREGS 94=0A= +#else=0A= +#define NREGS 80=0A= +#endif=0A= +=0A= +/*=0A= + * compiler defined bindings=0A= + */=0A= +#define R_ZERO R_R0=0A= +#define R_AT R_R1=0A= +#define R_V0 R_R2=0A= +#define R_V1 R_R3=0A= +#define R_A0 R_R4=0A= +#define R_A1 R_R5=0A= +#define R_A2 R_R6=0A= +#define R_A3 R_R7=0A= +#define R_T0 R_R8=0A= +#define R_T1 R_R9=0A= +#define R_T2 R_R10=0A= +#define R_T3 R_R11=0A= +#define R_T4 R_R12=0A= +#define R_T5 R_R13=0A= +#define R_T6 R_R14=0A= +#define R_T7 R_R15=0A= +#define R_S0 R_R16=0A= +#define R_S1 R_R17=0A= +#define R_S2 R_R18=0A= +#define R_S3 R_R19=0A= +#define R_S4 R_R20=0A= +#define R_S5 R_R21=0A= +#define R_S6 R_R22=0A= +#define R_S7 R_R23=0A= +#define R_T8 R_R24=0A= +#define R_T9 R_R25=0A= +#define R_K0 R_R26=0A= +#define R_K1 R_R27=0A= +#define R_GP R_R28=0A= +#define R_SP R_R29=0A= +#define R_FP R_R30=0A= +#define R_RA R_R31=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/Makefile = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/Makefile = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,126 @@=0A= +#######################################################################= ########=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile create a compressed zImage or Rommable rImage=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +#=0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +# =0A= +# =0A= +#######################################################################= ########=0A= +=0A= +#######################################################################= ########=0A= +# The following is taken from IDT/Sim Makefile=0A= +#######################################################################= ######=0A= +TARGET=3D365=0A= +=0A= +# following refers to size of the DRAM space.=0A= +# These are values for the switch DRAMSZ.=0A= +=0A= +MB16=3D1=0A= +MB32=3D2=0A= +MB64=3D3=0A= +MB128=3D4=0A= +MB32SO=3D5=0A= +=0A= +MACH=3D -DS$(TARGET) -DEB365 -DS364 -DCPU_R32364 = -DDRAMSZ=3D$(MB32SO)=0A= +COMMSWITCHES =3D $(INCDIRS) $(MACH)=0A= +#***************** END IDT/Sim Makefile = #####################################=0A= +ZDEBUG=3D1=0A= +export ZDEBUG=0A= +=0A= +# working space for gunzip:=0A= +FREE_RAM :=3D 0x80C00000=0A= +END_RAM :=3D 0x80E00000=0A= +=0A= +KERNELCONFIG :=3D $(TOPDIR)/.config=0A= +include $(KERNELCONFIG)=0A= +=0A= +SIZE =3D $(CROSS_COMPILE)size=0A= +=0A= +O_FORMAT =3D $(shell $(OBJDUMP) -i | head -2 | grep elf32)=0A= +=0A= +SYSTEM :=3D $(TOPDIR)/vmlinux=0A= +ZBSS :=3D 0x800A0000=0A= +=0A= +ZIMSTART :=3D $(CONFIG_IDT_ZIMAGE_ADDR)=0A= +RIMSTART :=3D 0x9FC00000=0A= +=0A= +LOADADDR :=3D 0x$(shell $(NM) $(SYSTEM) | grep "A _text" |cut -f1 = -d' ')=0A= +KERNEL_ENTRY :=3D $(shell $(OBJDUMP) -f $(SYSTEM) | sed -n -e = 's/^start address //p')=0A= +=0A= +#######################################################################= #############=0A= +ZIMFLAGS =3D s/IMSTART/$(ZIMSTART)/;s/BSS_START/$(ZBSS)/=0A= +RIMFLAGS =3D s/IMSTART/$(RIMSTART)/;s/BSS_START/$(ZBSS)/=0A= +CFLAGS :=3D -fno-pic -nostdinc -G 0 -mno-abicalls -fno-pic -pipe = -I$(TOPDIR)/include=0A= +AFLAGS :=3D -D__ASSEMBLY__ $(CFLAGS)=0A= +=0A= +#######################################################################= #############=0A= +OBJECTS=3D $(obj)/piggy.o $(obj)/head.o $(obj)/misc.o=0A= +ifneq ($(ZDEBUG),0)=0A= +OBJECTS +=3D $(obj)/uart16550.o=0A= +endif=0A= +=0A= +$(obj)/zImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)=0A= + @sed "$(ZIMFLAGS)" < $< > $@=0A= +=0A= +$(obj)/rImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)=0A= + @sed "$(RIMFLAGS)" < $< > $@=0A= +=0A= +$(obj)/piggy.o: $(SYSTEM) $(obj)/Makefile=0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(SYSTEM) = $(SYSTEM).bin=0A= + gzip -f -9 < $(SYSTEM).bin > $(SYSTEM).gz=0A= + echo "O_FORMAT: " $(O_FORMAT); =0A= + $(LD) -r -b binary --oformat $(O_FORMAT) -o $(obj)/piggy.o = $(SYSTEM).gz=0A= + rm -f $(SYSTEM).bin $(SYSTEM).gz=0A= +=0A= +$(obj)/head.o: $(obj)/head.S $(SYSTEM) $(obj)/Makefile=0A= + $(CC) $(AFLAGS) -DKERNEL_ENTRY=3D$(KERNEL_ENTRY) -c $(obj)/head.S -o = $(obj)/head.o=0A= +=0A= +$(obj)/misc.o: $(obj)/misc.c $(obj)/Makefile=0A= + $(CC) $(CFLAGS) -DLOADADDR=3D$(LOADADDR) -DFREE_RAM=3D$(FREE_RAM) = -DEND_RAM=3D$(END_RAM) \=0A= + -c $< -DZDEBUG=3D$(ZDEBUG) -o $(obj)/misc.o=0A= +=0A= +$(obj)/uart16550.o: $(obj)/uart16550.c $(KERNELCONFIG)=0A= + $(CC) $(CFLAGS) -c $< -o $(obj)/uart16550.o=0A= +=0A= +$(obj)/csu_idt.o: $(obj)/csu_idt.S Makefile $(SYSTEM)=0A= + $(CC) $(AFLAGS) $(COMMSWITCHES) -c $< -o $(obj)/csu_idt.o=0A= +=0A= +zImage: $(obj)/zImage.lds $(SYSTEM) $(OBJECTS)=0A= + $(LD) -T$(obj)/zImage.lds -o $(TOPDIR)/zImage $(OBJECTS)=0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/zImage = $(TOPDIR)/zImage.bin=0A= + $(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 \=0A= + $(TOPDIR)/zImage.bin $(TOPDIR)/zImage.prm=0A= + $(SIZE) $(TOPDIR)/zImage |awk -F" " '{ print $$4 "\t" $$5 }' > = $(TOPDIR)/zImage.size=0A= + rm -f *.o=0A= +=0A= +rImage: $(obj)/rImage.lds $(OBJECTS) $(obj)/csu_idt.o $(SYSTEM)=0A= + @rm -f $(TOPDIR)/*.prm=0A= + $(LD) -T$(obj)/rImage.lds -o $(TOPDIR)/rImage $(obj)/csu_idt.o = $(OBJECTS) =0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/rImage = $(TOPDIR)/rImage.bin=0A= + $(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 \=0A= + $(TOPDIR)/rImage.bin $(TOPDIR)/rImage.prm=0A= + $(SIZE) $(TOPDIR)/rImage |awk -F" " '{ print $$4 "\t" $$5 }' > = $(TOPDIR)/rImage.size=0A= + rm -f *.o=0A= +clean:=0A= + rm -f *.o $(TOPDIR)/zImage $(TOPDIR)/rImage $(TOPDIR)/*.prm = $(TOPDIR)/rImage.size $(TOPDIR)/zImage.size=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/misc.c idtlinux= /arch/mips/idt-boards/rc32300/EB365/boot/misc.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/misc.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/misc.c 2006-03-09 = 16:25:47.000000000 -0800=0A= @@ -0,0 +1,340 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Code to un-compress linux image=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +=0A= +/*=0A= + * gzip declarations=0A= + */=0A= +#define OF(args) args=0A= +#define STATIC static=0A= +#define memzero(s, n) memset ((s), 0, (n))=0A= +typedef unsigned char uch;=0A= +typedef unsigned short ush;=0A= +typedef unsigned long ulg;=0A= +#define WSIZE 0x8000 /* Window size must be at least 32k, */=0A= + /* and a power of two */=0A= +static uch *inbuf; /* input buffer */=0A= +static uch window[WSIZE]; /* Sliding window buffer */=0A= +=0A= +/* gzip flag byte */=0A= +#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */=0A= +#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part = gzip file */=0A= +#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */=0A= +#define ORIG_NAME 0x08 /* bit 3 set: original file name present = */=0A= +#define COMMENT 0x10 /* bit 4 set: file comment present */=0A= +#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */=0A= +#define RESERVED 0xC0 /* bit 6,7: reserved */=0A= +=0A= +=0A= +static unsigned insize; /* valid bytes in inbuf */=0A= +static unsigned inptr; /* index of next byte to be processed in inbuf = */=0A= +static unsigned outcnt; /* bytes in output buffer */=0A= +=0A= +void variable_init(void);=0A= +#if ZDEBUG > 0=0A= +static void puts(const char *);=0A= +extern void putc_init(void);=0A= +extern void putc(unsigned char c);=0A= +#endif=0A= +static int fill_inbuf(void);=0A= +static void flush_window(void);=0A= +static void error(char *m);=0A= +static void gzip_mark(void **);=0A= +static void gzip_release(void **);=0A= +=0A= +extern char input_data[];=0A= +=0A= +extern char input_data_end[];=0A= +=0A= +#if ZDEBUG > 0=0A= +void int2hex(unsigned long val)=0A= +{=0A= + unsigned char buf[10];=0A= + int i;=0A= + for (i =3D 7; i >=3D 0; i--)=0A= + {=0A= + buf[i] =3D "0123456789ABCDEF"[val & 0x0F];=0A= + val >>=3D 4;=0A= + }=0A= + buf[8] =3D '\0';=0A= + puts(buf);=0A= +}=0A= +#endif=0A= +=0A= +static unsigned long byte_count;=0A= +=0A= +int get_byte(void)=0A= +{=0A= +#if ZDEBUG > 1=0A= + static int printCnt;=0A= +#endif=0A= + unsigned char c =3D (inptr < insize ? inbuf[inptr++] : = fill_inbuf());=0A= + byte_count++;=0A= +=0A= +#if ZDEBUG > 1=0A= + if (printCnt++ < 32)=0A= + {=0A= + puts("byte count =3D ");=0A= + int2hex(byte_count);=0A= + puts(" byte val =3D ");=0A= + int2hex(c);=0A= + puts("\n");=0A= + }=0A= +#endif=0A= + return c;=0A= +}=0A= +=0A= +/* Diagnostic functions */=0A= +#ifdef DEBUG=0A= +# define Assert(cond,msg) {if(!(cond)) error(msg);}=0A= +# define Trace(x) fprintf x=0A= +# define Tracev(x) {if (verbose) fprintf x ;}=0A= +# define Tracevv(x) {if (verbose>1) fprintf x ;}=0A= +# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}=0A= +# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}=0A= +#else=0A= +# define Assert(cond,msg)=0A= +# define Trace(x)=0A= +# define Tracev(x)=0A= +# define Tracevv(x)=0A= +# define Tracec(c,x)=0A= +# define Tracecv(c,x)=0A= +#endif=0A= +=0A= +/*=0A= + * This is set up by the setup-routine at boot-time=0A= + */=0A= +=0A= +static long bytes_out;=0A= +static uch *output_data;=0A= +static unsigned long output_ptr;=0A= +=0A= +=0A= +static void *malloc(int size);=0A= +static void free(void *where);=0A= +static void error(char *m);=0A= +static void gzip_mark(void **);=0A= +static void gzip_release(void **);=0A= +=0A= +static unsigned long free_mem_ptr;=0A= +static unsigned long free_mem_end_ptr;=0A= +=0A= +#include "../../../../../../lib/inflate.c"=0A= +=0A= +static void *malloc(int size)=0A= +{=0A= + void *p;=0A= +=0A= + if (size < 0)=0A= + error("Malloc error\n");=0A= + if (free_mem_ptr <=3D 0) error("Memory error\n");=0A= +=0A= + free_mem_ptr =3D (free_mem_ptr + 3) & ~3; /* Align */=0A= +=0A= + p =3D (void *) free_mem_ptr;=0A= + free_mem_ptr +=3D size;=0A= +=0A= + if (free_mem_ptr >=3D free_mem_end_ptr)=0A= + error("\nOut of memory\n");=0A= +=0A= + return p;=0A= +}=0A= +=0A= +static void free(void *where)=0A= +{ /* Don't care */=0A= +}=0A= +=0A= +static void gzip_mark(void **ptr)=0A= +{=0A= + *ptr =3D (void *) free_mem_ptr;=0A= +}=0A= +=0A= +static void gzip_release(void **ptr)=0A= +{=0A= + free_mem_ptr =3D (long) *ptr;=0A= +}=0A= +#if ZDEBUG > 0=0A= +static void puts(const char *s)=0A= +{=0A= + while (*s) {=0A= + if (*s =3D=3D 10)=0A= + putc(13);=0A= + putc(*s++);=0A= + }=0A= +}=0A= +#endif=0A= +void *memset(void *s, int c, size_t n)=0A= +{=0A= + int i;=0A= + char *ss =3D (char *) s;=0A= +=0A= + for (i =3D 0; i < n; i++)=0A= + ss[i] =3D c;=0A= + return s;=0A= +}=0A= +=0A= +void *memcpy(void *__dest, __const void *__src, size_t __n)=0A= +{=0A= + int i;=0A= + char *d =3D (char *) __dest, *s =3D (char *) __src;=0A= +=0A= + for (i =3D 0; i < __n; i++)=0A= + d[i] =3D s[i];=0A= + return __dest;=0A= +}=0A= +=0A= +/* = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=0A= + * Fill the input buffer. This is called only when the buffer is = empty=0A= + * and at least one byte is really needed.=0A= + */=0A= +static int fill_inbuf(void)=0A= +{=0A= + if (insize !=3D 0) {=0A= + error("ran out of input data\n");=0A= + }=0A= +=0A= + inbuf =3D input_data;=0A= + insize =3D &input_data_end[0] - &input_data[0];=0A= + inptr =3D 1;=0A= + return inbuf[0];=0A= +}=0A= +=0A= +/* = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=0A= + * Write the output window window[0..outcnt-1] and update crc and = bytes_out.=0A= + * (Used for the decompressed data only.)=0A= + */=0A= +static void flush_window(void)=0A= +{=0A= + ulg c =3D crc; /* temporary variable */=0A= + unsigned n;=0A= + uch *in, *out, ch;=0A= +=0A= + in =3D window;=0A= + out =3D &output_data[output_ptr];=0A= + for (n =3D 0; n < outcnt; n++) {=0A= + ch =3D *out++ =3D *in++;=0A= + c =3D crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8);=0A= + }=0A= + crc =3D c;=0A= + bytes_out +=3D (ulg) outcnt;=0A= + output_ptr +=3D (ulg) outcnt;=0A= + outcnt =3D 0;=0A= +}=0A= +=0A= +#if ZDEBUG > 0=0A= +void check_mem(void)=0A= +{=0A= + int i;=0A= +=0A= + puts("\ncplens =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(cplens[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\ncplext =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(cplext[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\nborder =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(border[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\n");=0A= +}=0A= +#endif=0A= +static void error(char *x)=0A= +{=0A= +#if ZDEBUG > 1=0A= + check_mem();=0A= + puts("\n\n");=0A= + puts(x);=0A= + puts("byte_count =3D ");=0A= + int2hex(byte_count);=0A= + puts("\n");=0A= + puts("\n\n -- Error. System halted");=0A= +#endif=0A= + while (1); /* Halt */=0A= +}=0A= +=0A= +void variable_init(void)=0A= +{=0A= + byte_count =3D 0;=0A= + output_data =3D (char *) LOADADDR;=0A= + free_mem_ptr =3D FREE_RAM;=0A= + free_mem_end_ptr =3D END_RAM;=0A= +#if ZDEBUG > 1=0A= + puts("output_data 0x");=0A= + int2hex((unsigned long)output_data); puts("\n");=0A= + puts("free_mem_ptr 0x");=0A= + int2hex(free_mem_ptr); puts("\n");=0A= + puts("free_mem_end_ptr 0x");=0A= + int2hex(free_mem_end_ptr); puts("\n");=0A= + puts("input_data 0x");=0A= + int2hex((unsigned long)input_data); puts("\n");=0A= +#endif=0A= +}=0A= +=0A= +int decompress_kernel(void)=0A= +{=0A= +#if ZDEBUG > 0=0A= + putc_init();=0A= +#if ZDEBUG > 2=0A= + check_mem();=0A= +#endif=0A= +#endif=0A= +=0A= + variable_init();=0A= +=0A= + makecrc();=0A= +#if ZDEBUG > 0=0A= + puts("\n");=0A= + puts("Uncompressing Linux... \n");=0A= +#endif=0A= + gunzip(); // ...see inflate.c=0A= +#if ZDEBUG > 0=0A= + puts("Ok, booting the kernel.\n");=0A= +#endif=0A= +=0A= +#if ZDEBUG > 1=0A= + {=0A= + unsigned long *p =3D (unsigned long *)LOADADDR;=0A= + int2hex(p[0]); puts("\n");=0A= + int2hex(p[1]); puts("\n");=0A= + int2hex(p[2]); puts("\n");=0A= + int2hex(p[3]); puts("\n");=0A= + }=0A= +#endif=0A= +=0A= + return 0;=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/rImage.lds = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/rImage.lds=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/rImage.lds = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/rImage.lds = 2006-03-09 16:25:47.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D 0x9FC00000;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32300/EB365/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D 0x800A0000;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/s365led.h = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/s365led.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/s365led.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/s365led.h = 2006-03-09 16:25:47.000000000 -0800=0A= @@ -0,0 +1,62 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT CPU LED address definitions. Though the registers are already = defined=0A= + * else where under linux tree, they are once again declared here = for the=0A= + * ease of syncing up with IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef __S365LED__=0A= +#define __S365LED__=0A= +=0A= +/*=0A= +** following few lines define a macro DISPLAY=0A= +** which is used to write a set of 4 characters=0A= +** onto the EB365 LED.=0A= +*/=0A= +=0A= +#define GPIO_BASE PHYS_TO_K1(0x18048000)=0A= +=0A= +#define LED_BASE PHYS_TO_K1(0x0C000000)=0A= +#define LED_DIGIT0 0x3=0A= +#define LED_DIGIT1 0x2=0A= +#define LED_DIGIT2 0x1=0A= +#define LED_DIGIT3 0x0=0A= +=0A= +#define DISPLAY(d0, d1, d2, d3) \=0A= + li t6, LED_BASE ;\=0A= + li t7, (d0) & 0xff ;\=0A= + sb t7, LED_DIGIT0(t6) ;\=0A= + li t7, (d1) & 0xff ;\=0A= + sb t7, LED_DIGIT1(t6) ;\=0A= + li t7, (d2) & 0xff ;\=0A= + sb t7, LED_DIGIT2(t6) ;\=0A= + li t7, (d3) & 0xff ;\=0A= + sb t7, LED_DIGIT3(t6)=0A= +=0A= +#endif=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/s365ram.h = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/s365ram.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/s365ram.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/s365ram.h = 2006-03-09 16:25:47.000000000 -0800=0A= @@ -0,0 +1,144 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT EB365 SDRAM setup values.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef __S365RAM__=0A= +#define __S365RAM__=0A= +/******************************** D E F I N E S = *******************************/=0A= +=0A= +#define MB16 1=0A= +#define MB32 2=0A= +#define MB64 3=0A= +#define MB128 4=0A= +#define MB32SO 5=0A= +=0A= +#define DEV_CTL_BASE PHYS_TO_K1(0x18010000) /* device = controller regs */=0A= +#define SDRAM_BASE PHYS_TO_K1(0x18018000) /* SDRAM = controller regs */=0A= +#define GPIO_FUNC 0x0000609f /* SDRAM CLK; MEM[25:22]; = UART */=0A= +#define GPIO_CFG 0x00000020 /* GPIO5 ouput for SPI CS */=0A= +#define GPIO_OUT 0x00000020 /* GPIO5 ouput 1 */=0A= +#define ERR_CNTL_STATUS PHYS_TO_K1(0x18028030)=0A= +=0A= +#define DEV1_BASE 0x08000000=0A= +#define DEV_PROM_MASK 0xFFE00000=0A= +#define DEV_PROM_CTRL 0x028A2205=0A= +#define DEV_PROM_TC 0x00000A44=0A= +#define DEV_FLASH_MASK 0xFF800000=0A= +#define DEV_FLASH_CTRL 0x028A2206=0A= +#define DEV_FLASH_TC 0x00000A44=0A= +=0A= +#define DEV2_BASE 0x0C000000=0A= +#define DEV2_MASK 0xFF000000=0A= +#define DEV2_CTRL 0x04108324 /* 8-bit devices = */=0A= +#define DEV2_TC 0x00000A44=0A= +=0A= +#define DEV3_BASE 0x00000000=0A= +#define DEV3_MASK 0x00000000=0A= +#define DEV3_CTRL 0x0FFFFFF4 /* ?-bit devices = */=0A= +#define DEV3_TC 0x00001FFF=0A= +=0A= +#define DEV4_BASE 0x00000000=0A= +#define DEV4_MASK 0x00000000=0A= +#define DEV4_CTRL 0x0FFFFFF4 /* ?-bit devices = */=0A= +#define DEV4_TC 0x00001FFF=0A= +=0A= +#define DEV5_BASE 0x00000000=0A= +#define DEV5_MASK 0x00000000=0A= +#define DEV5_CTRL 0x0FFFFFF4 /* ?-bit devices = */=0A= +#define DEV5_TC 0x00001FFF=0A= +=0A= +#define DATA_PATTERN 0xA5A5A5A5=0A= +=0A= +#if DRAMSZ =3D=3D MB32SO=0A= +=0A= +/* Address space allocations */=0A= +#define SDRAM_BNK0_BASE 0x00000000 /* 0 MB */=0A= +#define SDRAM_BNK0_MASK 0xFE000000=0A= +#define SDRAM_BNK1_BASE 0x02000000 /* 32 MB */=0A= +#define SDRAM_BNK1_MASK 0x00000000=0A= +#define SDRAM_BNK0_ABASE 0x00000000 /* 0 MB */=0A= +#define SDRAM_BNK0_AMASK 0x00000000=0A= +=0A= +/* SDRAM Chip specific setup */=0A= +#if MHZ =3D=3D 90=0A= +#define SDRAM_CR_BS 0x994330F0 /* SDRAM enable */=0A= +#define SDRAM_DS_BS 0x19433080 /* SDRAM disable */=0A= +#define SDRAM_PC_VAL 0x194330c3 /* Precharge val */=0A= +#define SDRAM_RFRSH_CMD 0x19433093 /* refresh cmd */=0A= +#define SDRAM_MODE_REG 0x19433083 /* mode register */=0A= +#else=0A= +#define SDRAM_CR_BS 0x984330F0 /* SDRAM enable */=0A= +#define SDRAM_DS_BS 0x18433080 /* SDRAM disable */=0A= +#define SDRAM_PC_VAL 0x184330c3 /* Precharge val */=0A= +#define SDRAM_RFRSH_CMD 0x18433093 /* refresh cmd */=0A= +#define SDRAM_MODE_REG 0x18433083 /* mode register */=0A= +#endif=0A= +=0A= +#else=0A= +=0A= +/* Address space allocations */=0A= +#define SDRAM_BNK0_BASE 0x00000000 /* 0 MB */=0A= +#define SDRAM_BNK0_MASK 0xFF000000=0A= +#define SDRAM_BNK1_BASE 0x01000000 /* 16 MB */=0A= +#define SDRAM_BNK1_MASK 0x00000000=0A= +#define SDRAM_BNK0_ABASE 0x00000000 /* 0 MB */=0A= +#define SDRAM_BNK0_AMASK 0x00000000=0A= +=0A= +/* SDRAM Chip specific setup */=0A= +#if MHZ =3D=3D 90=0A= +#define SDRAM_CR_BS 0x894370F0 /* SDRAM enable */=0A= +#define SDRAM_DS_BS 0x09437080 /* SDRAM disable */=0A= +#define SDRAM_PC_VAL 0x094370c3 /* Precharge val */=0A= +#define SDRAM_RFRSH_CMD 0x09437093 /* refresh cmd */=0A= +#define SDRAM_MODE_REG 0x09437083 /* mode register */=0A= +#else=0A= +#define SDRAM_CR_BS 0x884370F0 /* SDRAM enable */=0A= +#define SDRAM_DS_BS 0x08437080 /* SDRAM disable */=0A= +#define SDRAM_PC_VAL 0x084370c3 /* Precharge val */=0A= +#define SDRAM_RFRSH_CMD 0x08437093 /* refresh cmd */=0A= +#define SDRAM_MODE_REG 0x08437083 /* mode register */=0A= +#endif=0A= +=0A= +#endif=0A= +=0A= +/* Refresh timer */=0A= +#define SDRAM_RF_CNT_BS 0x00000000 /* refresh count reg */=0A= +#define SDRAM_RF_CMPR_BS 0x00000040 /* refresh comp reg */=0A= +#if MHZ =3D=3D 90=0A= +#define SDRAM_RF_CMPR_SE_BS 0x000002EE /* slow expiration */=0A= +#else=0A= +#define SDRAM_RF_CMPR_SE_BS 0x00000271 /* slow expiration */=0A= +#endif=0A= +=0A= +#define DELAY_200USEC 30000 /* not exactly */=0A= +#define DISABLE_TIMER 0=0A= +#define ENABLE_TIMER 1=0A= +=0A= +#endif=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/uart16550.c = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/uart16550.c=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/uart16550.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/uart16550.c = 2006-03-09 16:25:47.000000000 -0800=0A= @@ -0,0 +1,178 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * UART code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + **********************************************************************= ****=0A= + */=0A= +=0A= +#include =0A= +=0A= +#define RC32365_REG_BASE 0xb8000000=0A= +#ifdef __MIPSEB__=0A= +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)=0A= +#else=0A= +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)=0A= +#endif=0A= +=0A= +#define BASE RC32300_UART0_BASE=0A= +=0A= +#define MAX_BAUD (CONFIG_IDT_BOARD_FREQ / 16)=0A= +#define REG_OFFSET 0x4=0A= +=0A= +/* =3D=3D=3D CONFIG =3D=3D=3D */=0A= +=0A= +/*=0A= + * #define BASE 0xb2001000=0A= + * #define MAX_BAUD 1152000=0A= + * #define REG_OFFSET 0x10=0A= + */=0A= +#if (!defined(BASE) || !defined(MAX_BAUD) || !defined(REG_OFFSET))=0A= +#error You must define BASE, MAX_BAUD and REG_OFFSET in the = Makefile.=0A= +#endif=0A= +=0A= +#ifndef INIT_SERIAL_PORT=0A= +#define INIT_SERIAL_PORT 1=0A= +#endif=0A= +=0A= +#ifndef DEFAULT_BAUD=0A= +//#define DEFAULT_BAUD UART16550_BAUD_115200=0A= +#define DEFAULT_BAUD UART16550_BAUD_9600=0A= +#endif=0A= +#ifndef DEFAULT_PARITY=0A= +#define DEFAULT_PARITY UART16550_PARITY_NONE=0A= +#endif=0A= +#ifndef DEFAULT_DATA=0A= +#define DEFAULT_DATA UART16550_DATA_8BIT=0A= +#endif=0A= +#ifndef DEFAULT_STOP=0A= +#define DEFAULT_STOP UART16550_STOP_1BIT=0A= +#endif=0A= +=0A= +/* =3D=3D=3D END OF CONFIG =3D=3D=3D */=0A= +=0A= +typedef unsigned char uint8;=0A= +typedef unsigned int uint32;=0A= +=0A= +#define UART16550_BAUD_2400 2400=0A= +#define UART16550_BAUD_4800 4800=0A= +#define UART16550_BAUD_9600 9600=0A= +#define UART16550_BAUD_19200 19200=0A= +#define UART16550_BAUD_38400 38400=0A= +#define UART16550_BAUD_57600 57600=0A= +#define UART16550_BAUD_115200 115200=0A= +=0A= +#define UART16550_PARITY_NONE 0=0A= +#define UART16550_PARITY_ODD 0x08=0A= +#define UART16550_PARITY_EVEN 0x18=0A= +#define UART16550_PARITY_MARK 0x28=0A= +#define UART16550_PARITY_SPACE 0x38=0A= +=0A= +#define UART16550_DATA_5BIT 0x0=0A= +#define UART16550_DATA_6BIT 0x1=0A= +#define UART16550_DATA_7BIT 0x2=0A= +#define UART16550_DATA_8BIT 0x3=0A= +=0A= +#define UART16550_STOP_1BIT 0x0=0A= +#define UART16550_STOP_2BIT 0x4=0A= +=0A= +/* register offset */=0A= +#define OFS_RCV_BUFFER (0*REG_OFFSET)=0A= +#define OFS_TRANS_HOLD (0*REG_OFFSET)=0A= +#define OFS_SEND_BUFFER (0*REG_OFFSET)=0A= +#define OFS_INTR_ENABLE (1*REG_OFFSET)=0A= +#define OFS_INTR_ID (2*REG_OFFSET)=0A= +#define OFS_DATA_FORMAT (3*REG_OFFSET)=0A= +#define OFS_LINE_CONTROL (3*REG_OFFSET)=0A= +#define OFS_MODEM_CONTROL (4*REG_OFFSET)=0A= +#define OFS_RS232_OUTPUT (4*REG_OFFSET)=0A= +#define OFS_LINE_STATUS (5*REG_OFFSET)=0A= +#define OFS_MODEM_STATUS (6*REG_OFFSET)=0A= +#define OFS_RS232_INPUT (6*REG_OFFSET)=0A= +#define OFS_SCRATCH_PAD (7*REG_OFFSET)=0A= +=0A= +#define OFS_DIVISOR_LSB (0*REG_OFFSET)=0A= +#define OFS_DIVISOR_MSB (1*REG_OFFSET)=0A= +=0A= +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))=0A= +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) =3D = z)=0A= +=0A= +static void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 = stop)=0A= +{=0A= + /* disable interrupts */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x0);=0A= + UART16550_WRITE(OFS_INTR_ENABLE, 0);=0A= +=0A= + /* set up baud rate */=0A= + {=0A= + uint32 divisor;=0A= +=0A= + /* set DIAB bit */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x80);=0A= +=0A= + /* set divisor */=0A= + divisor =3D MAX_BAUD / baud;=0A= + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);=0A= + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);=0A= +=0A= + /* clear DIAB bit */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x0);=0A= + }=0A= +=0A= + /* set data format */=0A= + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);=0A= +}=0A= +=0A= +=0A= +void=0A= +putc_init(void)=0A= +{=0A= +#if INIT_SERIAL_PORT=0A= + Uart16550Init(DEFAULT_BAUD, DEFAULT_DATA, DEFAULT_PARITY, = DEFAULT_STOP);=0A= +#endif=0A= +}=0A= +=0A= +void=0A= +putc(unsigned char c)=0A= +{=0A= + while ((UART16550_READ(OFS_LINE_STATUS) &0x20) =3D=3D 0);=0A= + UART16550_WRITE(OFS_SEND_BUFFER, c);=0A= +}=0A= +=0A= +#if 0=0A= +unsigned char=0A= +getc(void)=0A= +{=0A= + while((UART16550_READ(OFS_LINE_STATUS) & 0x1) =3D=3D 0);=0A= + return UART16550_READ(OFS_RCV_BUFFER);=0A= +}=0A= +=0A= +int=0A= +tstc(void)=0A= +{=0A= + return((UART16550_READ(OFS_LINE_STATUS) & 0x01) !=3D 0);=0A= +}=0A= +#endif=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/zImage.lds = idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/zImage.lds=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/boot/zImage.lds = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/boot/zImage.lds = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D 0x88000000;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32300/EB365/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D 0x800A0000;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/idtIRQ.S = idtlinux/arch/mips/idt-boards/rc32300/EB365/idtIRQ.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/idtIRQ.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/idtIRQ.S 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,66 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Intterrupt dispatcher code for IDT boards=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= + =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= + .text=0A= + .set noreorder=0A= + .set noat=0A= + .align 5=0A= + NESTED(rc32300_IRQ, PT_SIZE, sp)=0A= + SAVE_ALL=0A= + CLI=0A= +=0A= + .set at=0A= + .set noreorder=0A= +=0A= + mfc0 t0, CP0_CAUSE=0A= + move a1, sp=0A= + =0A= + /* check for r4k counter/timer IRQ. */=0A= + =0A= + andi t1, t0, CAUSEF_IP7=0A= + beqz t1, 1f=0A= + nop=0A= +=0A= + jal idt_timer_interrupt=0A= + li a0, 7=0A= + j ret_from_irq=0A= + nop=0A= +1:=0A= + jal rc32300_irqdispatch=0A= + move a0, t0=0A= + j ret_from_irq=0A= + nop=0A= +=0A= + END(rc32300_IRQ)=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/irq.c = idtlinux/arch/mips/idt-boards/rc32300/EB365/irq.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/irq.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/irq.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,284 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Interrupt routines for IDT EB365 boards=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +=0A= +#undef DEBUG_IRQ=0A= +#ifdef DEBUG_IRQ=0A= +/* note: prints function name for you */=0A= +#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## = args)=0A= +#else=0A= +#define DPRINTK(fmt, args...)=0A= +#endif=0A= +=0A= +extern asmlinkage void rc32300_IRQ(void);=0A= +=0A= +static unsigned int startup_irq(unsigned int irq);=0A= +static void end_irq(unsigned int irq_nr);=0A= +static void mask_and_ack_irq(unsigned int irq_nr);=0A= +static void rc32365_enable_irq(unsigned int irq_nr);=0A= +static void rc32365_disable_irq(unsigned int irq_nr);=0A= +=0A= +extern void __init init_generic_irq(void);=0A= +=0A= +typedef struct {=0A= + u32 mask; =0A= + volatile u32 *base_addr;=0A= +} intr_group_t;=0A= +=0A= +static const intr_group_t intr_group[NUM_INTR_GROUPS] =3D {=0A= + { 0x00000fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) = },=0A= + { 0x000001ff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) = },=0A= + { 0x00000003, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) = },=0A= + { 0x00000fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) = },=0A= + { 0x0000ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) = }=0A= +};=0A= +=0A= +#define READ_PEND(base) (*(base))=0A= +#define READ_MASK(base) (*(base + 2))=0A= +#define WRITE_MASK(base, val) (*(base + 2) =3D (val))=0A= +=0A= +static inline int irq_to_group(unsigned int irq_nr)=0A= +{=0A= + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);=0A= +}=0A= +=0A= +static inline int group_to_ip(unsigned int group)=0A= +{=0A= + return group + 2;=0A= +}=0A= +=0A= +static inline void enable_local_irq(unsigned int ip)=0A= +{=0A= + int ipnum =3D 0x100 << ip;=0A= + clear_c0_cause(ipnum);=0A= + set_c0_status(ipnum);=0A= +}=0A= +=0A= +static inline void disable_local_irq(unsigned int ip)=0A= +{=0A= + int ipnum =3D 0x100 << ip;=0A= + clear_c0_status(ipnum);=0A= +}=0A= +=0A= +static inline void ack_local_irq(unsigned int ip)=0A= +{=0A= + int ipnum =3D 0x100 << ip;=0A= + unsigned long flags;=0A= + =0A= + local_irq_save(flags);=0A= + =0A= + clear_c0_cause(ipnum);=0A= + =0A= + local_irq_restore(flags);=0A= +}=0A= +static void rc32365_enable_irq(unsigned int irq_nr)=0A= +{=0A= + unsigned long flags;=0A= + int ip =3D irq_nr - GROUP0_IRQ_BASE;=0A= + unsigned int group, intr_bit;=0A= + volatile unsigned int *addr;=0A= + =0A= + local_irq_save(flags);=0A= + =0A= + if (ip < 0)=0A= + enable_local_irq(irq_nr);=0A= + else {=0A= + group =3D ip >> 5;=0A= + =0A= + ip -=3D (group << 5);=0A= + intr_bit =3D 1 << ip;=0A= + =0A= + enable_local_irq(group_to_ip(group));=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);=0A= + }=0A= +=0A= + local_irq_restore(flags);=0A= +}=0A= +=0A= +static void rc32365_disable_irq(unsigned int irq_nr)=0A= +{=0A= + unsigned long flags;=0A= + int ip =3D irq_nr - GROUP0_IRQ_BASE;=0A= + unsigned int group, intr_bit, mask;=0A= + volatile unsigned int *addr;=0A= +=0A= + local_irq_save(flags);=0A= + =0A= + if (ip < 0)=0A= + disable_local_irq(irq_nr);=0A= + else {=0A= + group =3D ip >> 5;=0A= +=0A= + ip -=3D group << 5;=0A= + intr_bit =3D 1 << ip;=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + =0A= + mask =3D READ_MASK(addr);=0A= + mask |=3D intr_bit;=0A= + WRITE_MASK(addr, mask);=0A= + =0A= + if (mask =3D=3D intr_group[group].mask)=0A= + disable_local_irq(group_to_ip(group));=0A= + }=0A= + =0A= + local_irq_restore(flags);=0A= +}=0A= +=0A= +static unsigned int startup_irq(unsigned int irq_nr)=0A= +{=0A= + rc32365_enable_irq(irq_nr);=0A= + return 0; =0A= +}=0A= +=0A= +static void shutdown_irq(unsigned int irq_nr)=0A= +{=0A= + rc32365_disable_irq(irq_nr);=0A= + return;=0A= +}=0A= +=0A= +static void mask_and_ack_irq(unsigned int irq_nr)=0A= +{=0A= + rc32365_disable_irq(irq_nr);=0A= + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));=0A= +}=0A= +=0A= +static void end_irq(unsigned int irq_nr)=0A= +{=0A= + int ip =3D irq_nr - GROUP0_IRQ_BASE;=0A= + unsigned int intr_bit, group;=0A= + volatile unsigned int *addr;=0A= +=0A= + unsigned long flags;=0A= +=0A= + local_irq_save(flags);=0A= +=0A= + if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) = {=0A= + if (ip < 0)=0A= + enable_local_irq(irq_nr);=0A= + else {=0A= + if (irq_nr >=3D RC32365_PCI_INTA_IRQ && irq_nr <=3D = RC32365_PCI_INTD_IRQ)=0A= + gpio->gpioistat =3D 0x0000f0ff;=0A= + =0A= + group =3D ip >> 5;=0A= +=0A= + ip -=3D (group << 5);=0A= + intr_bit =3D 1 << ip;=0A= +=0A= + =0A= + enable_local_irq(group_to_ip(group));=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);=0A= + }=0A= + } =0A= + else {=0A= + printk("warning: end_irq %d did not enable (%x)\n", =0A= + irq_nr, irq_desc[irq_nr].status);=0A= + }=0A= +=0A= + local_irq_restore(flags);=0A= +}=0A= +=0A= +static struct hw_interrupt_type rc32365_irq_type =3D {=0A= + "RC32365",=0A= + startup_irq,=0A= + shutdown_irq,=0A= + rc32365_enable_irq,=0A= + rc32365_disable_irq,=0A= + mask_and_ack_irq,=0A= + end_irq,=0A= + NULL=0A= +};=0A= +=0A= +=0A= +void __init arch_init_irq(void)=0A= +{=0A= + int i;=0A= +=0A= + printk("Initializing IRQ's: %d of %d\n", RC32365_NR_IRQS,NR_IRQS); = =0A= + memset(irq_desc, 0, sizeof(irq_desc));=0A= + set_except_vector(0, rc32300_IRQ);=0A= + =0A= + for (i =3D 0; i < RC32365_NR_IRQS; i++) {=0A= + irq_desc[i].status =3D IRQ_DISABLED;=0A= + irq_desc[i].action =3D NULL;=0A= + irq_desc[i].depth =3D 1;=0A= + irq_desc[i].handler =3D &rc32365_irq_type;=0A= + spin_lock_init(&irq_desc[i].lock);=0A= + }=0A= +}=0A= +=0A= +/* Main Interrupt dispatcher */=0A= +void rc32300_irqdispatch(unsigned long cp0_cause, struct pt_regs = *regs)=0A= +{=0A= + unsigned int ip, pend, group;=0A= + volatile unsigned int *addr;=0A= +=0A= + if ((ip =3D (cp0_cause & 0x7c00))) {=0A= + group =3D 21 - rc32300_clz(ip);=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= +=0A= + pend =3D READ_PEND(addr);=0A= + pend &=3D ~READ_MASK(addr); =0A= + pend =3D 39 - rc32300_clz(pend);=0A= + do_IRQ((group << 5) + pend, regs);=0A= + return;=0A= + } =0A= + else=0A= + return;=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/Makefile = idtlinux/arch/mips/idt-boards/rc32300/EB365/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/Makefile 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,42 @@=0A= +#######################################################################= ########=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile for IDT EB365 board BSP=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +#=0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +# =0A= +# =0A= +# =0A= +#######################################################################= ########=0A= +=0A= +.S.s:=0A= + $(CPP) $(CFLAGS) $< -o $*.s=0A= +.S.o:=0A= + $(CC) $(CFLAGS) -c $< -o $*.o=0A= +=0A= +obj-y :=3D irq.o setup.o idtIRQ.o reset.o prom.o time.o=0A= +obj-$(CONFIG_KGDB) +=3D serial_gdb.o=0A= +obj-$(CONFIG_SERIAL_8250) +=3D serial.o=0A= +subdir-$(CONFIG_IDT_BOOT_NVRAM) +=3D nvram=0A= +obj-$(CONFIG_IDT_BOOT_NVRAM) +=3D nvram/built-in.o=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/Makefile = idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/Makefile = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,44 @@=0A= +#######################################################################= ########=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile for IDT EB365 nvram access routines=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +#=0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +# =0A= +# =0A= +# =0A= +#######################################################################= ########=0A= +=0A= +.S.s: =0A= + $(CPP) $(CFLAGS) $< -o $*.s=0A= +.S.o: =0A= + $(CC) $(CFLAGS) -c $< -o $*.o=0A= +=0A= +obj-y :=3D nvram365.o =0A= +=0A= +=0A= +=0A= +=0A= +=0A= +=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.c = idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.c=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.c = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,342 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * nvram interface routines.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include "nvram365.h"=0A= +=0A= +void setenv (char *e, char *v, int rewrite);=0A= +char *getenv (char *e);=0A= +void unsetenv (char *e);=0A= +void purgeenv(void);=0A= +char *getenv (char *s);=0A= +void mapenv (int (*func)(char *, char *));=0A= +=0A= +static void nvram_initenv(void);=0A= +=0A= +static unsigned char=0A= +nvram_getbyte(int offs)=0A= +{=0A= + return(*((unsigned char*)(NVRAM_BASE + offs)));=0A= +}=0A= +=0A= +static void=0A= +nvram_setbyte(int offs, unsigned char val)=0A= +{=0A= + unsigned char* nvramDataPointer =3D (unsigned char*)(NVRAM_BASE + = offs);=0A= +=0A= + *nvramDataPointer =3D val;=0A= +}=0A= +=0A= +static unsigned short=0A= +nvram_getshort(int offs)=0A= +{=0A= + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));=0A= +}=0A= +=0A= +static void=0A= +nvram_setshort(int offs, unsigned short val)=0A= +{=0A= + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));=0A= + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));=0A= +}=0A= +/*=0A= + * calculate NVRAM checksum=0A= + */=0A= +static unsigned short=0A= +nvram_calcsum(void)=0A= +{=0A= + unsigned short sum =3D NV_MAGIC;=0A= + int i;=0A= +=0A= + for (i =3D ENV_BASE; i < ENV_TOP; i +=3D 2)=0A= + sum +=3D nvram_getshort(i);=0A= + return(sum);=0A= +}=0A= +=0A= +/*=0A= + * update the nvram checksum=0A= + */=0A= +static void=0A= +nvram_updatesum (void)=0A= +{=0A= + nvram_setshort(NVOFF_CSUM, nvram_calcsum());=0A= +}=0A= +=0A= +/*=0A= + * test validity of nvram by checksumming it=0A= + */=0A= +static int=0A= +nvram_isvalid(void)=0A= +{=0A= + static unsigned int is_valid;=0A= +=0A= + if (is_valid)=0A= + return(1);=0A= +=0A= + if (nvram_getshort(NVOFF_MAGIC) !=3D NV_MAGIC)=0A= + nvram_initenv();=0A= + is_valid =3D 1;=0A= + return(1);=0A= +}=0A= +=0A= +/* return nvram address of environment string */=0A= +static int=0A= +nvram_matchenv(char *s)=0A= +{=0A= + int envsize, envp, n, i, varsize;=0A= + char *var;=0A= +=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + if (envsize > ENV_AVAIL)=0A= + return(0); /* sanity */=0A= + =0A= + envp =3D ENV_BASE;=0A= +=0A= + if ((n =3D strlen (s)) > 255)=0A= + return(0);=0A= + =0A= + while (envsize > 0) {=0A= + varsize =3D nvram_getbyte(envp);=0A= + if (varsize =3D=3D 0 || (envp + varsize) > ENV_TOP)=0A= + return(0); /* sanity */=0A= + for (i =3D envp + 1, var =3D s; i <=3D envp + n; i++, var++) {=0A= + char c1 =3D nvram_getbyte(i);=0A= + char c2 =3D *var;=0A= + if (islower(c1))=0A= + c1 =3D toupper(c1);=0A= + if (islower(c2))=0A= + c2 =3D toupper(c2);=0A= + if (c1 !=3D c2)=0A= + break;=0A= + }=0A= + if (i > envp + n) { /* match so far */=0A= + if (n =3D=3D varsize - 1) /* match on boolean */=0A= + return(envp);=0A= + if (nvram_getbyte(i) =3D=3D '=3D') /* exact match on variable = */=0A= + return(envp);=0A= + }=0A= + envsize -=3D varsize;=0A= + envp +=3D varsize;=0A= + }=0A= + return(0);=0A= +}=0A= +=0A= +static void nvram_initenv(void)=0A= +{=0A= + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);=0A= + nvram_setshort(NVOFF_ENVSIZE, 0);=0A= +=0A= + nvram_updatesum();=0A= +}=0A= +=0A= +static void=0A= +nvram_delenv(char *s)=0A= +{=0A= + int nenvp, envp, envsize, nbytes;=0A= +=0A= + envp =3D nvram_matchenv(s);=0A= + if (envp =3D=3D 0)=0A= + return;=0A= +=0A= + nenvp =3D envp + nvram_getbyte(envp);=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + nbytes =3D envsize - (nenvp - ENV_BASE);=0A= + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));=0A= + while (nbytes--) {=0A= + nvram_setbyte(envp, nvram_getbyte(nenvp));=0A= + envp++;=0A= + nenvp++;=0A= + }=0A= + nvram_updatesum();=0A= +}=0A= +=0A= +static int=0A= +nvram_setenv(char *s, char *v)=0A= +{=0A= + int ns, nv, total;=0A= + int envp;=0A= +=0A= + if (!nvram_isvalid())=0A= + return(-1);=0A= +=0A= + nvram_delenv(s);=0A= + ns =3D strlen(s);=0A= + if (ns =3D=3D 0)=0A= + return(0);=0A= + if (v && *v) {=0A= + nv =3D strlen(v);=0A= + total =3D ns + nv + 2;=0A= + }=0A= + else {=0A= + nv =3D 0;=0A= + total =3D ns + 1;=0A= + }=0A= + if (total > 255 || total > ENV_AVAIL - = nvram_getshort(NVOFF_ENVSIZE))=0A= + return(0);=0A= +=0A= + envp =3D ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);=0A= +=0A= + nvram_setbyte(envp, (unsigned char) total); =0A= + envp++;=0A= +=0A= + while (ns--) {=0A= + nvram_setbyte(envp, *s); =0A= + envp++; =0A= + s++;=0A= + }=0A= +=0A= + if (nv) {=0A= + nvram_setbyte(envp, '=3D'); =0A= + envp++;=0A= + while (nv--) {=0A= + nvram_setbyte(envp, *v); =0A= + envp++; =0A= + v++;=0A= + }=0A= + }=0A= + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);=0A= + nvram_updatesum();=0A= + return(0);=0A= +}=0A= +=0A= +static char *=0A= +nvram_getenv(char *s)=0A= +{=0A= + static char buf[256]; /* FIXME: this cannot be static */=0A= + int envp, ns, nbytes, i;=0A= +=0A= + if (!nvram_isvalid())=0A= + return((char *)0);=0A= +=0A= + envp =3D nvram_matchenv(s);=0A= + if (envp =3D=3D 0)=0A= + return((char *)0);=0A= + ns =3D strlen(s);=0A= + if (nvram_getbyte(envp) =3D=3D ns + 1) /* boolean */=0A= + buf[0] =3D '\0';=0A= + else {=0A= + nbytes =3D nvram_getbyte(envp) - (ns + 2);=0A= + envp +=3D ns + 2;=0A= + for (i =3D 0; i < nbytes; i++)=0A= + buf[i] =3D nvram_getbyte(envp++);=0A= + buf[i] =3D '\0';=0A= + }=0A= + return(buf);=0A= +}=0A= +=0A= +static void=0A= +nvram_unsetenv(char *s)=0A= +{=0A= + if (!nvram_isvalid())=0A= + return;=0A= +=0A= + nvram_delenv(s);=0A= +}=0A= +/*=0A= + * apply func to each string in environment=0A= + */=0A= +static void=0A= +nvram_mapenv(int (*func)(char *, char *))=0A= +{=0A= + int envsize, envp, n, i, seeneql;=0A= + char name[256], value[256];=0A= + char c, *s;=0A= +=0A= + if (!nvram_isvalid())=0A= + return;=0A= +=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + envp =3D ENV_BASE;=0A= +=0A= + while (envsize > 0) {=0A= + value[0] =3D '\0';=0A= + seeneql =3D 0;=0A= + s =3D name;=0A= + n =3D nvram_getbyte(envp);=0A= + for (i =3D envp + 1; i < envp + n; i++) {=0A= + c =3D nvram_getbyte(i);=0A= + if ((c =3D=3D '=3D') && !seeneql) {=0A= + *s =3D '\0';=0A= + s =3D value;=0A= + seeneql =3D 1;=0A= + continue;=0A= + }=0A= + *s++ =3D c;=0A= + }=0A= + *s =3D '\0';=0A= + (*func)(name, value);=0A= + envsize -=3D n;=0A= + envp +=3D n;=0A= + }=0A= +}=0A= +/*=0A= + * Wrappers to allow 'special' environment variables to get = processed=0A= + */=0A= +void=0A= +setenv(char *e, char *v, int rewrite)=0A= +{=0A= + if (nvram_getenv(e) && !rewrite)=0A= + return;=0A= + =0A= + nvram_setenv(e, v);=0A= +}=0A= +=0A= +char *=0A= +getenv(char *e)=0A= +{=0A= + return(nvram_getenv(e));=0A= +}=0A= +=0A= +void=0A= +unsetenv(char *e)=0A= +{=0A= + nvram_unsetenv(e);=0A= +}=0A= +=0A= +void=0A= +purgeenv(void)=0A= +{=0A= + int i;=0A= + unsigned char* nvramDataPointer =3D (unsigned char*)(NVRAM_BASE);=0A= + =0A= + for (i =3D ENV_BASE; i < ENV_TOP; i++)=0A= + *nvramDataPointer++ =3D 0;=0A= + =0A= + nvram_initenv();=0A= +}=0A= +=0A= +void=0A= +mapenv(int (*func)(char *, char *))=0A= +{=0A= + nvram_mapenv(func);=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.h = idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.h=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/nvram/nvram365.h = 2006-03-09 16:25:48.000000000 -0800=0A= @@ -0,0 +1,60 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * nvram layout definitions=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#define NVRAM_BASE 0xAC800000=0A= +#define TD_NVRAM_SIZE 0x2000=0A= +=0A= +/*=0A= + * defining ALGCOMPAT provides backward compatibility=0A= + * with Algorithmics derived PROM monitors=0A= + */=0A= +#define NVOFFSET 0 /* use all of NVRAM */=0A= +=0A= +/* Offsets to reserved locations */=0A= + /* size description */=0A= +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */=0A= +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment = checksum */=0A= +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' = */=0A= +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte = */=0A= +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address = */=0A= +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table = */=0A= +=0A= +#define NV_MAGIC 0xdeaf /* nvram magic number */=0A= +#define NV_RESERVED 32 /* number of reserved bytes = */=0A= +=0A= +#undef NVOFF_ETHADDR=0A= +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)=0A= +=0A= +/* number of bytes available for environment */=0A= +#define ENV_BASE (NVOFFSET + NV_RESERVED)=0A= +#define ENV_TOP TD_NVRAM_SIZE=0A= +#define ENV_AVAIL (ENV_TOP - ENV_BASE)=0A= +=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/prom.c = idtlinux/arch/mips/idt-boards/rc32300/EB365/prom.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/prom.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/prom.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,117 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * prom interface routines=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +=0A= +extern void setup_serial_port(void);=0A= +unsigned int idt_cpu_freq =3D CONFIG_IDT_BOARD_FREQ;=0A= +=0A= +EXPORT_SYMBOL(idt_cpu_freq);=0A= +=0A= +#ifdef CONFIG_IDT_BOOT_NVRAM=0A= +extern void mapenv(int (*func)(char *, char *));=0A= +static int make_bootparm(char *name,char *val)=0A= +{ =0A= + if (strncmp(name, "bootparm", 8) =3D=3D 0) {=0A= + strcat(arcs_cmdline," ");=0A= + strcat(arcs_cmdline,val);=0A= + }=0A= + else if(strncmp(name, "HZ", 2) =3D=3D 0) {=0A= + idt_cpu_freq =3D simple_strtoul(val, 0, 10);=0A= + printk("CPU Clock at %d Hz (from HZ environment variable)\n",=0A= + idt_cpu_freq);=0A= + }=0A= + return 0;=0A= +}=0A= +=0A= +static void prom_init_cmdline(void)=0A= +{ =0A= + mapenv(&make_bootparm);=0A= +}=0A= +=0A= +#else=0A= +/* Kernel Boot parameters */=0A= +//static unsigned char = bootparm[]=3D"ip=3D157.165.29.36:157.165.29.18::255.255.0.0::eth0";=0A= +static unsigned char bootparm[]=3D"console=3DttyS0,9600";=0A= +#endif=0A= +=0A= +extern unsigned long mips_machgroup;=0A= +extern unsigned long mips_machtype;=0A= +=0A= +const char *get_system_type(void)=0A= +{=0A= + return "IDT 79EB365";=0A= +}=0A= +=0A= +struct resource rc32300_res_ram =3D {=0A= + "RAM",=0A= + 0,=0A= + RAM_SIZE,=0A= + IORESOURCE_MEM=0A= +};=0A= +=0A= +char * __init prom_getcmdline(void)=0A= +{=0A= + return &(arcs_cmdline[0]);=0A= +}=0A= +=0A= +void __init prom_init(void)=0A= +{=0A= +#ifdef CONFIG_IDT_BOOT_NVRAM=0A= + prom_init_cmdline();=0A= +#endif=0A= +=0A= + setup_serial_port();=0A= + mips_machgroup =3D MACH_GROUP_IDT;=0A= + mips_machtype =3D MACH_IDT_EB365;=0A= + add_memory_region(0,rc32300_res_ram.end - = rc32300_res_ram.start,BOOT_MEM_RAM);=0A= + =0A= +}=0A= +=0A= +unsigned long __init prom_free_prom_memory(void)=0A= +{=0A= + return 0;=0A= +}=0A= +=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/reset.c = idtlinux/arch/mips/idt-boards/rc32300/EB365/reset.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/reset.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/reset.c 2006-03-09 = 16:25:47.000000000 -0800=0A= @@ -0,0 +1,67 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Reset EB365 board.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +extern void (*flush_cache_all)(void);=0A= +=0A= +void rc32300_restart(char *command)=0A= +{=0A= + set_c0_status((ST0_BEV | ST0_ERL));=0A= + set_c0_config(CONF_CM_UNCACHED);=0A= + flush_cache_all();=0A= + write_c0_wired(0);=0A= +=0A= + rc32300_writel(0x80000001, RESET_CNTL);=0A= +}=0A= +=0A= +void rc32300_halt(void)=0A= +{=0A= + printk(KERN_NOTICE "\n** You can safely turn off the power\n");=0A= + while (1)=0A= + __asm__(".set\tmips3\n\t"=0A= + "wait\n\t"=0A= + ".set\tmips0");=0A= +}=0A= +=0A= +void rc32300_power_off(void)=0A= +{=0A= + rc32300_halt();=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/serial.c = idtlinux/arch/mips/idt-boards/rc32300/EB365/serial.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/serial.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/serial.c 2006-03-09 = 16:25:47.000000000 -0800=0A= @@ -0,0 +1,74 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Serial port initialisation.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +=0A= +#include =0A= +=0A= +extern int __init early_serial_setup(struct uart_port *port);=0A= +=0A= +extern unsigned int idt_cpu_freq;=0A= +=0A= +extern int __init setup_serial_port(void)=0A= +{ =0A= + static struct uart_port serial_req[2];=0A= +=0A= + memset(serial_req, 0, sizeof(serial_req));=0A= + serial_req[0].type =3D PORT_16550A;=0A= + serial_req[0].line =3D 0;=0A= + serial_req[0].irq =3D RC32300_UART0_IRQ;=0A= + serial_req[0].flags =3D STD_COM_FLAGS;=0A= + serial_req[0].uartclk =3D idt_cpu_freq;=0A= + serial_req[0].iotype =3D SERIAL_IO_MEM;=0A= + serial_req[0].membase =3D (char *) = KSEG1ADDR(RC32300_UART0_BASE);=0A= + serial_req[0].mapbase =3D KSEG1ADDR(RC32300_UART0_BASE);=0A= + serial_req[0].regshift =3D 2;=0A= + =0A= + early_serial_setup(&serial_req[0]);=0A= + =0A= + return 0;=0A= +}=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/serial_gdb.c = idtlinux/arch/mips/idt-boards/rc32300/EB365/serial_gdb.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/serial_gdb.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/serial_gdb.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,236 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * EB365 specific polling driver for 16550 UART.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +=0A= +/* set remote gdb baud rate at 115200 */=0A= +=0A= +#define GDB_BAUD 115200=0A= +#define CONS_BAUD 9600=0A= +=0A= +extern unsigned int idt_cpu_freq;=0A= +=0A= +=0A= +/* turn this on to watch the debug protocol echoed on the console port = */=0A= +#define DEBUG_REMOTE_DEBUG=0A= +=0A= +#ifdef __MIPSEB__=0A= +#define CONS_PORT 0xb8050003u=0A= +#define GDB_PORT 0xb8050003u=0A= +#else=0A= +#define CONS_PORT 0xb8050000u=0A= +#define GDB_PORT 0xb8050000u=0A= +#endif=0A= + =0A= +volatile unsigned char *ports[2] =3D {=0A= + (volatile unsigned char *)CONS_PORT,=0A= + (volatile unsigned char *)GDB_PORT=0A= +};=0A= +=0A= +=0A= +void reset_gdb_port(void);=0A= +void cons_putc(char c);=0A= +int port_getc(int port);=0A= +void port_putc(int port, char c);=0A= +=0A= +int cons_getc(void)=0A= +{=0A= + return port_getc(0);=0A= +}=0A= +=0A= +void cons_putc(char c)=0A= +{=0A= + port_putc(0, c);=0A= +}=0A= +=0A= +void cons_puts(char *s)=0A= +{=0A= + while(*s) {=0A= + if(*s =3D=3D '\n') cons_putc('\r');=0A= + cons_putc(*s);=0A= + s++;=0A= + }=0A= +}=0A= +=0A= +void cons_do_putn(int n)=0A= +{=0A= + if(n) {=0A= + cons_do_putn(n / 10);=0A= + cons_putc(n % 10 + '0');=0A= + }=0A= +}=0A= +=0A= +void cons_putn(int n)=0A= +{=0A= + if(n < 0) {=0A= + cons_putc('-');=0A= + n =3D -n;=0A= + }=0A= +=0A= + if (n =3D=3D 0) {=0A= + cons_putc('0');=0A= + } else {=0A= + cons_do_putn(n);=0A= + }=0A= +}=0A= +=0A= +static int first =3D 1;=0A= +=0A= +int getDebugChar(void)=0A= +{=0A= + int c;=0A= +=0A= + if(first) reset_gdb_port();=0A= +=0A= + c =3D port_getc(1);=0A= +=0A= + return c;=0A= +}=0A= +=0A= +int port_getc(int p)=0A= +{=0A= + volatile unsigned char *port =3D ports[p];=0A= + int c;=0A= +=0A= + while((*(port + UART_LSR * 4) & UART_LSR_DR) =3D=3D 0) {=0A= + continue;=0A= + } =0A= +=0A= + c =3D *(port + UART_RX * 4);=0A= +=0A= + return c;=0A= +}=0A= +=0A= +int port_getc_ready(int p)=0A= +{=0A= + volatile unsigned char *port =3D ports[p];=0A= +=0A= + return *(port + UART_LSR * 4) & UART_LSR_DR;=0A= +}=0A= +=0A= +int isDebugReady(void)=0A= +{=0A= + return port_getc_ready(1);=0A= +}=0A= +=0A= +void putDebugChar(char c)=0A= +{=0A= + if(first) reset_gdb_port();=0A= +=0A= + port_putc(1, c);=0A= +}=0A= +=0A= +#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)=0A= +=0A= +void port_putc(int p, char c)=0A= +{=0A= + volatile unsigned char *port =3D ports[p];=0A= + volatile unsigned char *lsr =3D port + UART_LSR * 4;=0A= +=0A= + while((*lsr & OK_TO_XMT) !=3D OK_TO_XMT) {=0A= + continue;=0A= + }=0A= +=0A= + *(port + UART_TX * 4) =3D c;=0A= +}=0A= +=0A= +void reset_gdb_port(void)=0A= +{=0A= + volatile unsigned char *port =3D ports[1];=0A= + unsigned int DIVISOR =3D (idt_cpu_freq / 16 / GDB_BAUD);=0A= +=0A= + first =3D 0;=0A= +=0A= +#ifdef DEBUG_REMOTE_DEBUG=0A= + cons_puts("\n");=0A= + cons_puts("reset_gdb_port: initializing remote debug serial port = (internal UART 0, baud=3D");=0A= + cons_putn(GDB_BAUD);=0A= + cons_puts(", MHz=3D");=0A= + cons_putn(idt_cpu_freq);=0A= + cons_puts(", divisor=3D");=0A= + cons_putn(DIVISOR);=0A= + cons_puts(")\n");=0A= +#endif=0A= +=0A= + /* wait for pending transfer to finish */=0A= + while((*(port + UART_LSR * 4) & OK_TO_XMT) !=3D OK_TO_XMT);=0A= +=0A= + /* reset the port */=0A= + *(port + UART_CSR * 4) =3D 0;=0A= +=0A= + /* clear and enable the FIFOs */=0A= + *(port + UART_FCR * 4) =3D UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR = | =0A= + UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;=0A= +=0A= + /* set the baud rate */=0A= + *(port + UART_LCR * 4) =3D UART_LCR_DLAB; /* enable DLL, DLM = registers */=0A= + *(port + UART_DLL * 4) =3D DIVISOR;=0A= + *(port + UART_DLM * 4) =3D DIVISOR >> 8;=0A= +=0A= + /* set the line control stuff and disable DLL, DLM regs */=0A= +=0A= + *(port + UART_LCR * 4) =3D UART_LCR_STOP | /* 2 stop bits */=0A= + UART_LCR_WLEN8; /* 8 bit word length */=0A= + =0A= + /* leave interrupts off */=0A= + *(port + UART_IER * 4) =3D 0;=0A= +=0A= + /* the modem controls don't leave the chip on this port, so leave = them alone */=0A= + *(port + UART_MCR * 4) =3D 0;=0A= +}=0A= +=0A= +void reset_cons_port(void)=0A= +{=0A= + volatile unsigned char *port =3D ports[0];=0A= + unsigned int DIVISOR =3D (idt_cpu_freq / 16 / CONS_BAUD);=0A= +=0A= + /* reset the port */=0A= + *(port + UART_CSR * 4) =3D 0;=0A= +=0A= + /* clear and enable the FIFOs */=0A= + *(port + UART_FCR * 4) =3D UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR = | =0A= + UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;=0A= +=0A= + /* set the baud rate */=0A= + *(port + UART_LCR * 4) =3D UART_LCR_DLAB; /* enable DLL, DLM = registers */=0A= +=0A= + *(port + UART_DLL * 4) =3D DIVISOR;=0A= + *(port + UART_DLM * 4) =3D DIVISOR >> 8;=0A= + /* set the line control stuff and disable DLL, DLM regs */=0A= +=0A= + *(port + UART_LCR * 4) =3D UART_LCR_STOP | /* 2 stop bits */=0A= + UART_LCR_WLEN8; /* 8 bit word length */=0A= + =0A= + /* leave interrupts off */=0A= + *(port + UART_IER * 4) =3D 0;=0A= +=0A= + /* the modem controls don't leave the chip on this port, so leave = them alone */=0A= + *(port + UART_MCR * 4) =3D 0;=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/setup.c = idtlinux/arch/mips/idt-boards/rc32300/EB365/setup.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/setup.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/setup.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,157 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * setup routines for IDT EB365 boards=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +=0A= +#include =0A= +=0A= +extern void (*board_time_init)(void);=0A= +extern void (*board_timer_setup)(struct irqaction *irq);=0A= +extern void rc32300_time_init(void);=0A= +extern void rc32300_timer_setup(struct irqaction *irq);=0A= +extern char * __init prom_getcmdline(void);=0A= +=0A= +extern void rc32300_restart(char *);=0A= +extern void rc32300_halt(void);=0A= +extern void rc32300_power_off(void);=0A= +=0A= +unsigned int cedar_za;=0A= +=0A= +#define DIG0 ((volatile unsigned char *)0xAC000003)=0A= +#define DIG1 ((volatile unsigned char *)0xAC000002)=0A= +#define DIG2 ((volatile unsigned char *)0xAC000001)=0A= +#define DIG3 ((volatile unsigned char *)0xAC000000)=0A= +=0A= +void idt_disp_char(int i, char c)=0A= +{=0A= + switch (i) {=0A= + case 0: *DIG0 =3D c; break;=0A= + case 1: *DIG1 =3D c; break;=0A= + case 2: *DIG2 =3D c; break;=0A= + case 3: *DIG3 =3D c; break;=0A= + default: *DIG0 =3D '?'; break;=0A= + }=0A= +}=0A= +=0A= +void idt_disp_str(char *s)=0A= +{=0A= + int i;=0A= + =0A= + if (s =3D=3D 0) {=0A= + idt_disp_char(0, 0x20);=0A= + idt_disp_char(1, 0x20);=0A= + idt_disp_char(2, 0x20);=0A= + idt_disp_char(3, 0x20);=0A= + } =0A= + else {=0A= + for (i =3D 0; i < 4; i++) {=0A= + if (s[i]) =0A= + idt_disp_char(i, s[i]);=0A= + }=0A= + }=0A= +}=0A= +=0A= +static int __init idt_setup(void)=0A= +{=0A= + char* argptr;=0A= + idt_disp_str("Unix");=0A= + =0A= + argptr =3D prom_getcmdline();=0A= +=0A= +#ifdef CONFIG_SERIAL_8250_CONSOLE=0A= + if ((argptr =3D strstr(argptr, "console=3D")) =3D=3D NULL) {=0A= + argptr =3D prom_getcmdline();=0A= + strcat(argptr, " console=3DttyS0,9600");=0A= + }=0A= +#endif=0A= +=0A= + board_time_init =3D rc32300_time_init;=0A= + board_timer_setup =3D rc32300_timer_setup;=0A= +=0A= + _machine_restart =3D rc32300_restart;=0A= + _machine_halt =3D rc32300_halt;=0A= + pm_power_off =3D rc32300_power_off;=0A= +=0A= + set_io_port_base(KSEG1);=0A= +=0A= + write_c0_wired(0);=0A= +=0A= + /* Disable Watchdog timer */=0A= + rc32300_writel(0, 0xb802803c);=0A= +=0A= + /* Revision ZA? */=0A= + cedar_za =3D (rc32300_readl(0xb8000018) & 0xff) ? 0 : 1;=0A= +=0A= + if (cedar_za)=0A= + idt_disp_str("ZA ");=0A= + else=0A= + idt_disp_str(" ZB");=0A= +=0A= + =0A= + return 0;=0A= +}=0A= +=0A= +//early_initcall(idt_setup);=0A= +void __init plat_setup(void){=0A= + idt_setup();=0A= +}=0A= +=0A= +int page_is_ram(unsigned long pagenr)=0A= +{=0A= + return 1;=0A= +}=0A= +=0A= +=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/time.c = idtlinux/arch/mips/idt-boards/rc32300/EB365/time.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/EB365/time.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/EB365/time.c 2006-03-09 = 16:25:48.000000000 -0800=0A= @@ -0,0 +1,140 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * timer routines for IDT EB365 boards=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + * =0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +=0A= +static unsigned long r4k_offset; /* Amount to incr compare reg each = time */=0A= +static unsigned long r4k_cur; /* What counter should be at next = timer irq */=0A= +=0A= +extern unsigned int idt_cpu_freq;=0A= +#if defined(CONFIG_MIPS_RTC)=0A= +extern void rtc_ds1553_init(void);=0A= +#endif=0A= +=0A= +/* =0A= + * Figure out the r4k offset, the amount to increment the compare=0A= + * register for each time tick. There is no RTC available.=0A= + *=0A= + * The RC32300 counts at half the CPU *core* speed.=0A= + */=0A= +static unsigned long __init cal_r4koff(void)=0A= +{=0A= + mips_hpt_frequency =3D idt_cpu_freq * IDT_CLOCK_MULT / 2;=0A= + return (mips_hpt_frequency / HZ);=0A= +}=0A= +=0A= +=0A= +void __init rc32300_time_init(void)=0A= +{=0A= + unsigned int est_freq, flags;=0A= + =0A= + local_irq_save(flags);=0A= + =0A= + printk("calculating r4koff... ");=0A= + r4k_offset =3D cal_r4koff();=0A= + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);=0A= + =0A= + est_freq =3D 2*r4k_offset*HZ; =0A= + est_freq +=3D 5000; /* round */=0A= + est_freq -=3D est_freq%10000;=0A= + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, =0A= + (est_freq%1000000)*100/1000000);=0A= + local_irq_restore(flags);=0A= + =0A= +#if defined(CONFIG_MIPS_RTC)=0A= + rtc_ds1553_init();=0A= +#endif=0A= +=0A= +}=0A= +=0A= +=0A= +void __init rc32300_timer_setup(struct irqaction *irq)=0A= +{=0A= + setup_irq(MIPS_CPU_TIMER_IRQ, irq);=0A= + =0A= + /* to generate the first timer interrupt */=0A= + r4k_cur =3D (read_c0_count() + r4k_offset);=0A= + write_c0_compare(r4k_cur);=0A= +}=0A= +=0A= +static inline void ack_r4ktimer(unsigned long newval)=0A= +{=0A= + write_c0_compare(newval);=0A= +}=0A= +=0A= +extern void idt_disp_char(int i,char c);=0A= +=0A= +asmlinkage void idt_timer_interrupt(int irq,struct pt_regs *regs)=0A= +{ =0A= +#ifdef CONFIG_KGDB=0A= + void kgdb_check(void);=0A= +#endif=0A= +=0A= + static unsigned int timerCount =3D 0;=0A= + static int toggle =3D 0;=0A= + =0A= + irq_enter();=0A= + kstat_this_cpu.irqs[irq]++;=0A= + =0A= + if( (timerCount++ % HZ) =3D=3D 0)=0A= + { =0A= + toggle ^=3D 1;=0A= + idt_disp_char(0,toggle ? 'u' :'U');=0A= + }=0A= + =0A= + timer_interrupt(irq, NULL, regs);=0A= + irq_exit();=0A= +=0A= +#ifdef CONFIG_KGDB=0A= + kgdb_check();=0A= +#endif=0A= +}=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/csu_idt.S = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/csu_idt.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/csu_idt.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/csu_idt.S = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,412 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Board initialization code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include "iregdef.h"=0A= +#include "idtcpu.h"=0A= +#include "idthdr.h"=0A= +=0A= +#define MHZ CONFIG_IDT_BOARD_FREQ=0A= +=0A= +#include "s364.h"=0A= +=0A= +#if defined (S334A)=0A= +#include "s334aram.h"=0A= +#elif defined (S334)=0A= +#include "s334ram.h"=0A= +#endif =0A= +=0A= +#define IndexInvalidate_I 0x00=0A= +=0A= +/*--------------------------------------------------------------=0A= +** prom entry point table=0A= +*-------------------------------------------------------------*/=0A= +FRAME(start,sp,0,ra)=0A= + j idtstart=0A= +=0A= +idtstart:=0A= + .set noreorder=0A= +=0A= +#if defined(CPU_R32364)=0A= + li t0,PORT_WIDTH_CONTROL=0A= + li t1,PORT_SETUP=0A= + sw t1,0x0(t0)=0A= + li t0,BTA_CONTROL=0A= + li t1,BTA_SETUP=0A= + sw t1,0x0(t0)=0A= + li t0,SYS_BTA_CTRL=0A= + sw t1,0x0(t0)=0A= +#if MHZ > 50000000=0A= + li t0,SYS_ALT_CTRL=0A= + li t1,SYS_ALT_SETUP=0A= + sw t1,0x0(t0)=0A= +#endif=0A= + li v0,0x00=0A= + or v0,(SR_CU0|SR_BEV|SR_DE)=0A= +#endif=0A= + mtc0 v0,C0_SR # state unknown on reset=0A= + mtc0 zero,C0_CAUSE # clear software interrupts=0A= +=0A= +#ifdef S334=0A= + /* initialize the PIO Direction for UART RC32334/2*/=0A= +#define PIO_BASE_ADDR 0xb8000600=0A= +#define PIO_DC_SET 0x00500050=0A= +#define PIO_DC_MASK 0xff0fff0f=0A= +=0A= + li t0,PIO_BASE_ADDR=0A= + lw t1,0x4(t0)=0A= + nop=0A= + li t2,PIO_DC_MASK #mask the UART bits=0A= + and t1,t1,t2=0A= + nop=0A= + li t2,PIO_DC_SET #rx0=3Drx1=3Dinput, = tx0=3Dtx1=3Doutput=0A= + or t1,t1,t2=0A= + nop=0A= + sw t1,0x4(t0)=0A= +=0A= + /* disable the PCI bus error */=0A= + lui t1,0xb800=0A= + ori t1,t1,0x10=0A= + nop=0A= + lw t0,0x0(t1)=0A= + nop=0A= + nop=0A= + ori t0,t0,0x80=0A= + nop=0A= + sw t0,0x0(t1)=0A= + nop=0A= + nop=0A= + nop=0A= +#endif=0A= +=0A= +#if defined(CPU_R4000) || defined(CPU_R32364)=0A= + mfc0 v1,C0_CONFIG=0A= + /* Set cache mode: write-back */=0A= + li v0, CFG_C_NCHRNT_WB /* CFG_C_NCHRNT_WB CFG_C_NCHRNT_WT_NWA = CFG_C_UNCACHED */=0A= + and v1,~(0x7)=0A= + or v1,v1,v0=0A= + mtc0 v1,C0_CONFIG=0A= + nop=0A= + nop=0A= + li t0,MEM_BASE_BASE /* load 2 base address registers' base */=0A= +=0A= + li t1,MBA_REG0 /* load into memory base address register 0 */=0A= + sw t1,0x0(t0) /* set the memory base address register for Chip = Select 0 - EPROM */=0A= +=0A= + li t1,MBM_REG0 /* load into memory base mask register 0 */=0A= + sw t1,0x4(t0) /* set the memory base mask register for Chip Select 0 = - EPROM */=0A= +=0A= +=0A= + li t0,MEM_CTL_BASE /* load all control registers' base address */=0A= +=0A= + li t1,MCR_CS0_BS /* load memory control register chip = select 0 bit settings */=0A= + sw t1,0x0(t0) /* set the control register for Chip Select 0 - EPROM = */=0A= +=0A= + nop=0A= +=0A= + li t1,MCR_CS1_BS /* load into upper half memory control register = chip select 1 bit settings */=0A= + sw t1,0x4(t0) /* set the control register for Chip Select 1 - SRAM = */=0A= + nop=0A= +#ifdef S334=0A= + li t1,MCR_CS2_BS /* initialize CHIP-SELECT2 */=0A= + sw t1,0x08(t0)=0A= + nop=0A= +=0A= + li t1,MCR_CS3_BS /* initialize CHIP-SELECT3 */=0A= + sw t1,0x0C(t0)=0A= + nop=0A= +=0A= + li t1,MCR_CS4_BS /* initialize CHIP-SELECT4 for LED = */=0A= + sw t1,0x10(t0)=0A= + nop=0A= +=0A= +#endif=0A= + li t1,MCR_CS5_BS /* load into upper half memory control register = chip select 5 bit settings */=0A= + sw t1,0x14(t0) /* set the control register for Chip Select 5 - = External UART */=0A= + nop=0A= +=0A= +/*------------ load all R32 internal registers' base address = ----------*/=0A= + li t0,R32134_IREG_BASE /* load t0 with all R32134 internal registers' = base address */=0A= +=0A= +/* ------------------- Disable WatchDog Timer = --------------------------------- */=0A= + li t1,DISABLE_TIMER=0A= + sw t1,0x730(t0)=0A= +=0A= +#if MEMCFG =3D=3D SDRAM_ONLY || MEMCFG =3D=3D SRAM_N_SDRAM || MEMCFG = =3D=3D SDRAM_N_SRAM=0A= +/*--------------- disable EDO Controller = ---------------------------*/=0A= + li t1,0 /* EDO_CR_BS load EDO control register bit settings in t1 = */=0A= + sw t1,0x310(t0) /* Disable EDO control register */=0A= +=0A= +#elif MEMCFG =3D=3D EDO_ONLY || MEMCFG =3D=3D SRAM_N_EDO || MEMCFG = =3D=3D EDO_N_SRAM=0A= +/*------------------------- disable SDRAM Controller = --------------------------*/=0A= + li t1,0=0A= + sw t1,0x300(t0)=0A= +#endif /* MEMCFG =3D=3D EDO_ONLY || MEMCFG =3D=3D SRAM_N_EDO || MEMCFG = =3D=3D EDO_N_SRAM */=0A= +=0A= +#if MEMCFG !=3D SRAM_ONLY=0A= +/*-------------- Initialize SDRAM or EDO Base and Mask Registers = ----------*/=0A= +=0A= + li t1,DRAM_BNK0_BASE /* load DRAM bank 0 physical address in t1 */=0A= + sw t1,0xC0(t0) /* set DRAM bank 0 base */=0A= + li t1,DRAM_BNK1_BASE /* load DRAM bank 1 physical address in t1 */=0A= + sw t1,0xC8(t0) /* set DRAM bank 1 base */=0A= + li t1,DRAM_BNK2_BASE /* load DRAM bank 2 physical address in t1 */=0A= + sw t1,0xD0(t0) /* set DRAM bank 2 base */=0A= + li t1,DRAM_BNK3_BASE /* load DRAM bank 3 physical address in t1 */=0A= + sw t1,0xD8(t0) /* set DRAM bank 3 base */=0A= +=0A= + li t1,DRAM_BNK0_MASK /* load DRAM bank 0 size in t1 */=0A= + sw t1,0xC4(t0) /* set DRAM bank 0 mask */=0A= + li t1,DRAM_BNK1_MASK /* load DRAM bank 1 size in t1 */=0A= + sw t1,0xCC(t0) /* set DRAM bank 1 mask */=0A= + li t1,DRAM_BNK2_MASK /* load DRAM bank 2 size in t1 */=0A= + sw t1,0xD4(t0) /* set DRAM bank 2 mask */=0A= + li t1,DRAM_BNK3_MASK /* load DRAM bank 3 size in t1 */=0A= + sw t1,0xDC(t0) /* set DRAM bank 3 mask */=0A= +=0A= +#if MEMCFG =3D=3D SRAM_N_SDRAM || MEMCFG =3D=3D SRAM_N_EDO || MEMCFG = =3D=3D SDRAM_N_SRAM || MEMCFG =3D=3D EDO_N_SRAM=0A= +/* ------------------------------- Setup SRAM if in place = -----------------------------------------*/=0A= + li t0,MEM_BASE_BASE /* load 2 base address registers' base */=0A= + li t1,MBA_REG1 /* load into memory base address register 1 */=0A= + sw t1,0x8(t0) /* set the memory base address register for Chip = Select 1 - SRAM */=0A= +=0A= + li t1,MBM_REG1 /* load into memory base mask register 1 */=0A= + sw t1,0xC(t0) /* set the memory base mask register for Chip Select 1 = - SRAM */=0A= +#endif /* MEMCFG =3D=3D SRAM_N_SDRAM || MEMCFG =3D=3D SRAM_N_EDO || = MEMCFG =3D=3D SDRAM_N_SRAM || MEMCFG =3D=3D EDO_N_SRAM*/=0A= +=0A= +#if MEMCFG =3D=3D EDO_ONLY || MEMCFG =3D=3D SRAM_N_EDO || MEMCFG = =3D=3D EDO_N_SRAM=0A= +/*-------------- Set EDO control register = --------------------------*/=0A= + li t1,EDO_CR_BS /* load EDO control register bit settings in t1 = */=0A= + sw t1,0x310(t0) /* set EDO control register */=0A= +#endif /* MEMCFG =3D=3D EDO_ONLY || MEMCFG =3D=3D SRAM_N_EDO || MEMCFG = =3D=3D EDO_N_SRAM */=0A= +=0A= +/*-------------- Setup and Enable Refresh Timer = --------------------*/=0A= + li t0,TIMER_BASE /* load timer register set base */=0A= +=0A= + li t1,DISABLE_TIMER /* load diable timer bit settings into t1 */=0A= + sw t1,0x60(t0) /* disable timer */=0A= + nop=0A= +=0A= +#if MEMCFG =3D=3D SDRAM_ONLY || MEMCFG =3D=3D SRAM_N_SDRAM || MEMCFG = =3D=3D SDRAM_N_SRAM=0A= +/*-------------- Enable SDRAM Controller = ---------------------------*/=0A= + li t0,R32134_IREG_BASE=0A= + li t1,SDRAM_CR_BS=0A= + sw t1,0x300(t0)=0A= + nop=0A= +/*-------------- Delay Loop = ----------------------------------------*/=0A= + li v0,10000 /* 8x256us */=0A= +1: bne v0,zero,1b=0A= + subu v0,1 /* BDSLOT */=0A= + nop=0A= + nop=0A= +/*-------------- Setup Precharge Command = ---------------------------*/=0A= + li t2,2=0A= + li t3,0=0A= +1: li t1,SDRAM_PC_VAL=0A= + sw t1,0x300(t0)=0A= + nop=0A= + nop=0A= + lw t7,0x300(t0)=0A= + nop=0A= + li t4,APATTERN=0A= +#ifdef S334=0A= +#if DRAMSZ !=3D MB32SO=0A= + li t5,0xA0000000 | DRAM_BNK0_BASE=0A= +#else=0A= +#ifdef S334A=0A= + li t5,0xA0000000 | DRAM_BNK0_BASE=0A= +#else=0A= + li t5,0xA0000000 | DRAM_BNK3_BASE=0A= +#endif=0A= +#endif=0A= +#else=0A= + li t5,0xA0000000 | DRAM_BNK0_BASE=0A= +#endif=0A= + sw t4,0x0(t5)=0A= + addu t3,1=0A= + bne t3,t2,1b=0A= + nop=0A= +#ifdef S334=0A= +/*-------------- Setup Refresh Command = -----------------------------*/=0A= + li t2,8=0A= + li t3,0=0A= +1: li t1,SDRAM_RFRSH_CMD=0A= + sw t1,0x300(t0)=0A= + sw t4,0x0(t5) /* note: t5 not disturbed */=0A= + addu t3,1=0A= + bne t3,t2,1b=0A= + nop=0A= +#endif=0A= +/*-------------- Setup up to write to Mode Register = ----------------*/=0A= + li t1,SDRAM_MODE_REG=0A= + sw t1,0x300(t0)=0A= +#ifdef S1254=0A= + addu t5,0xC0 /* CAS Latency of 3 */=0A= +#else=0A= + addu t5,0x80=0A= +#endif=0A= + sw t4,0x0(t5)=0A= +#ifdef S334=0A= + ori t1,t1,0xff=0A= + sw t1,0x300(t0)=0A= +=0A= +/* Set Secondary SDRAM Control register based on revision */=0A= + lw t1,0x18(t0) /* get SysID */=0A= + andi t1,0xf0 /* BD slot */=0A= + beqz t1,2f /* skip if Z part */=0A= + li t3,0x10=0A= + beq t1,t3,1f /* Y part? */=0A= + li t2,0x2 /* BD slot */=0A= + ori t2,0x200 /* Add tWR for X part */=0A= +1:=0A= + sw t2, 0x304(t0) /* set secondary SDRAM control register = */=0A= + nop=0A= +2:=0A= +#endif=0A= +#endif /* MEMCFG =3D=3D SDRAM_ONLY || MEMCFG =3D=3D SRAM_N_SDRAM || = MEMCFG =3D=3D SDRAM_N_SRAM */=0A= +=0A= +/*-------------- Setup and Enable Refresh Timer --------------------*/=0A= +=0A= + li t0,TIMER_BASE /* load timer register set base */=0A= +=0A= + li t1,0 /* load DRAM refresh timer count register bit settings in = t1 */=0A= + sw t1,0x64(t0) /* set DRAM refresh timer count register bit settings = */=0A= +=0A= + li t1,DRAM_RF_CMPR_BS /* load DRAM refresh timer compare register bit = settings in t1 */=0A= + sw t1,0x68(t0) /* set DRAM refresh timer compare register bit = settings */=0A= +=0A= + li t1,CPU_BERR_BS=0A= + sw t1,0x48(t0)=0A= + li t1,IP_BERR_BS=0A= + sw t1,0x58(t0)=0A= +=0A= + li t1,ENABLE_TIMER /* load timer enable bit */=0A= + sw t1,0x60(t0) /* enable refresh timer */=0A= +#ifdef S334=0A= + /* the memory system may need some time to start up... */=0A= + li v0,10000 /* 8x256us */=0A= +1: bne v0,zero,1b=0A= + subu v0,1 /* BDSLOT */=0A= + nop=0A= + nop=0A= +=0A= + li t1,DRAM_RF_CMPR_SE_BS /* load refresh timer compare value for = slower expiration */=0A= + sw t1,0x68(t0) /* set compare register again */=0A= +#else=0A= +#if MEMCFG =3D=3D EDO_ONLY || MEMCFG =3D=3D EDO_N_SRAM || MEMCFG = =3D=3D SRAM_N_EDO=0A= + /* the memory system may need up to 120us to start up... */=0A= + li v0,128 /* ~256us */=0A= +1: bne v0,zero,1b=0A= + subu v0,1 /* BDSLOT */=0A= + nop=0A= + nop=0A= +=0A= + li t1,DRAM_RF_CMPR_SE_BS /* load refresh timer compare value for = slower expiration */=0A= + sw t1,0x68(t0) /* set compare register again */=0A= +#endif /* MEMCFG =3D=3D EDO_ONLY || MEMCFG =3D=3D EDO_N_SRAM || MEMCFG = =3D=3D SRAM_N_EDO */=0A= +#endif=0A= +=0A= +#endif /* MEMCFG !=3D SRAM_ONLY */=0A= +#if MEMCFG =3D=3D SRAM_ONLY=0A= +/* ------------------------------- Setup SRAM if in place = -----------------------------------------*/=0A= +=0A= +/*=0A= +** write some thing else in DRAM BANK 0 BASE address first since it = has 0 by default.=0A= +*/=0A= + li t1,0x01000000 /* load DRAM bank 0 physical address in t1 */=0A= + sw t1,0xC0(t0) /* set DRAM bank 0 base */=0A= +=0A= + li t0,MEM_BASE_BASE /* load 2 base address registers' base */=0A= + li t1,MBA_REG1 /* load into memory base address register 1 */=0A= + sw t1,0x8(t0) /* set the memory base address register for Chip = Select 1 - SRAM */=0A= +=0A= + li t1,MBM_REG1 /* load into memory base mask register 1 */=0A= + sw t1,0xC(t0) /* set the memory base mask register for Chip Select 1 = - SRAM */=0A= +#endif /* MEMCFG =3D=3D SRAM_ONLY */=0A= +=0A= +=0A= +#endif /* (CPU_R4000) || defined(CPU_R32364) */=0A= +=0A= +#if defined(S364)=0A= +=0A= +/*=0A= +** before doing anything=0A= +** initialize the section of memory used by cache initialization=0A= +** whenever you boot out of ROM or reset-vector=0A= +** This assumed to be 1MB.=0A= +** --Sugan (11-22-96)=0A= +*/=0A= + li t0, 0xa0000000=0A= + li t1, 0xa0100000=0A= +1:=0A= + sw zero,0x00(t0)=0A= + sw zero,0x04(t0)=0A= + sw zero,0x08(t0)=0A= + sw zero,0x0c(t0)=0A= + addiu t0,16 # DO NOT put this instruction in the=0A= + # delay slot of "blt t0,t1,1b" since = it=0A= + # will run over the 1M boundary for 16 = byte=0A= + # more which would cause problem if we = have=0A= + # exactly 1M memory available on board.=0A= + nop=0A= + blt t0,t1,1b=0A= + nop=0A= + nop=0A= + nop=0A= +3:=0A= + mfc0 t0,C0_SR=0A= + nop=0A= + nop=0A= + and t0,~SR_BEV=0A= + mtc0 t0,C0_SR=0A= + nop=0A= + nop=0A= +4:=0A= +#endif=0A= +=0A= + li v0,100000 /* large delay */=0A= +1: subu v0,1 /* BDSLOT */=0A= + bne v0,zero,1b=0A= + nop=0A= + nop=0A= +=0A= + la k0, zstartup=0A= + j k0=0A= + nop=0A= + nop=0A= +=0A= +ENDFRAME(start)=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/head.S = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/head.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/head.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/head.S 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,134 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Board initialisation code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#define IndexInvalidate_I 0x00=0A= +=0A= + .set noreorder=0A= + .cprestore=0A= + LEAF(zstartup)=0A= +zstartup:=0A= +=0A= + la sp, .stack=0A= + move s0, a0=0A= + move s1, a1=0A= + move s2, a2=0A= + move s3, a3=0A= +=0A= + /* Clear BSS */=0A= + la a0, .stack=0A= + la a2, _end=0A= +1: sw zero, 0(a0)=0A= + bne a2, a0, 1b=0A= + addu a0, 4=0A= +#if 1=0A= + /* flush the I-Cache */=0A= + li k0, 0x80000000 # start address=0A= + li k1, 0x80002000 # end address (8KB I-Cache)=0A= + subu k1, 128=0A= +2:=0A= + .set mips3=0A= + cache IndexInvalidate_I, 0(k0)=0A= + cache IndexInvalidate_I, 16(k0)=0A= + cache IndexInvalidate_I, 32(k0)=0A= + cache IndexInvalidate_I, 48(k0)=0A= + cache IndexInvalidate_I, 64(k0)=0A= + cache IndexInvalidate_I, 80(k0)=0A= + cache IndexInvalidate_I, 96(k0)=0A= + cache IndexInvalidate_I, 112(k0)=0A= + .set mips0=0A= +=0A= + bne k0, k1, 2b=0A= + addu k0, k0, 128=0A= + /* done */=0A= +#endif=0A= +#if 1=0A= + /* flush the D-Cache */=0A= + li k0, 0x80000000 # start address=0A= + li k1, 0x80000400 # end address (2KB I-Cache)=0A= + subu k1, 128=0A= +3: =0A= + .set mips3=0A= + /* First way */=0A= + cache Index_Writeback_Inv_D, 0(k0)=0A= + cache Index_Writeback_Inv_D, 16(k0)=0A= + cache Index_Writeback_Inv_D, 32(k0)=0A= + cache Index_Writeback_Inv_D, 48(k0)=0A= + cache Index_Writeback_Inv_D, 64(k0)=0A= + cache Index_Writeback_Inv_D, 80(k0)=0A= + cache Index_Writeback_Inv_D, 96(k0)=0A= + cache Index_Writeback_Inv_D, 112(k0)=0A= + /* Second way */=0A= + cache Index_Writeback_Inv_D, 1024(k0)=0A= + cache Index_Writeback_Inv_D, 1040(k0)=0A= + cache Index_Writeback_Inv_D, 1056(k0)=0A= + cache Index_Writeback_Inv_D, 1072(k0)=0A= + cache Index_Writeback_Inv_D, 1088(k0)=0A= + cache Index_Writeback_Inv_D, 1104(k0)=0A= + cache Index_Writeback_Inv_D, 1120(k0)=0A= + cache Index_Writeback_Inv_D, 1136(k0)=0A= + .set mips0=0A= +=0A= + bne k0, k1, 3b=0A= + addu k0, k0, 128=0A= + /* done */=0A= +#endif=0A= + =0A= +=0A= + la ra, 4f=0A= + la k0, decompress_kernel=0A= + jr k0=0A= + nop=0A= +4:=0A= +=0A= + move a0, s0=0A= + move a1, s1=0A= + move a2, s2=0A= + move a3, s3=0A= + li k0, KERNEL_ENTRY=0A= + jr k0=0A= + nop=0A= +5:=0A= + b 5b=0A= + END(zstartup)=0A= +=0A= + .bss=0A= + .fill 0x2000=0A= + EXPORT(.stack)=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/idtcpu.h = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/idtcpu.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/idtcpu.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/idtcpu.h 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,614 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT CPU register definitions. Though the registers are already = defined=0A= + * under asm directory, they are once again declared here for the = ease of=0A= + * syncing up with IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#if defined(__IDTCPU_H__)=0A= +#else=0A= +#define __IDTCPU_H__=0A= +=0A= +=0A= +/*=0A= +** memory configuration and mapping=0A= +*/=0A= +#define K0BASE 0x80000000=0A= +#define K0SIZE 0x20000000=0A= +#define K1BASE 0xa0000000=0A= +#define K1SIZE 0x20000000=0A= +#define K2BASE 0xc0000000=0A= +#if defined(S364)=0A= +#define K2SIZE 0x3e000000=0A= +#define ICEBASE 0xff000000=0A= +#define ICESIZE 0x01000000=0A= +#else=0A= +#define K2SIZE 0x20000000=0A= +#endif=0A= +#if defined(CPU_R4000)=0A= +#define KSBASE 0xe0000000=0A= +#define KSSIZE 0x20000000=0A= +#endif=0A= +=0A= +#define KUBASE 0=0A= +#define KUSIZE 0x80000000=0A= +=0A= +/*=0A= +** Exception Vectors=0A= +*/=0A= +#if defined(CPU_R3000)=0A= +#define UT_VEC K0BASE /* utlbmiss vector */=0A= +#define E_VEC (K0BASE+0x80) /* exception vevtor */=0A= +#endif=0A= +#if defined(CPU_R4000) || defined S364 /*(CPU_R32364) */=0A= +#define T_VEC (K0BASE+0x000) /* tlbmiss vector */=0A= +#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */=0A= +#define C_VEC (K1BASE+0x100) /* cache error vector */=0A= +#define E_VEC (K0BASE+0x180) /* exception vector */=0A= +#define I_VEC (K0BASE+0X200) /* interrupt vector */=0A= +#endif=0A= +#define R_VEC (K1BASE+0x1fc00000) /* reset vector */=0A= +=0A= +/*=0A= +** Address conversion macros=0A= +*/=0A= +#ifdef CLANGUAGE=0A= +#define CAST(as) (as)=0A= +#else=0A= +#define CAST(as)=0A= +#endif=0A= +#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 = */=0A= +#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 = */=0A= +#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to = physical */=0A= +#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to = physical */=0A= +#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to = kseg0 */=0A= +#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to = kseg1 */=0A= +=0A= +/*=0A= +** Cache size constants=0A= +*/=0A= +/* Sugan changed so that MINCACHE is 0x200 instead of 0x800 */=0A= +#define MINCACHE 0x200 /* 512 bytes */=0A= +#define MAXCACHE 0x40000 /* 256*1024 256k */ =0A= +=0A= +#if defined CPU_R32364 /* Includes RC32364, RC32332, = RC32334 */=0A= +#define CFG_ICE 0x80000000 /* ICE detect */=0A= +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */=0A= +#define CFG_ECBY2 0x00000000 /* divide by 2 */=0A= +#define CFG_ECBY3 0x10000000 /* divide by 3 */=0A= +#define CFG_ECBY4 0x20000000 /* divide by 4 */=0A= +#define CFG_NBL 0x00800000 /* Non-Blocking load pending */=0A= +#define CFG_BE 0x00008000 /* Big Endian */=0A= +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */=0A= +#define CFG_ICSHIFT 9=0A= +#define CFG_DCMASK 0x000001c0 /* Data cache size */=0A= +#define CFG_DCSHIFT 6=0A= +#define CFG_IB 0x00000020 /* Instruction cache line size */=0A= +#define CFG_DB 0x00000010 /* Data cache line size */=0A= +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */=0A= +=0A= +/*=0A= + * R32364 primary cache mode=0A= + */=0A= +#define CFG_C_NCHRNT_WT_NWA 0=0A= +#define CFG_C_NCHRNT_WT 1=0A= +#define CFG_C_UNCACHED 2=0A= +#define CFG_C_NCHRNT_WB 3=0A= +=0A= +/* Cache Operations */=0A= +#define Index_Invalidate_I 0x0 /* 0 0 = */=0A= +#define Index_Writeback_Inv_D 0x1 /* 0 1 = */=0A= +#define Index_Invalidate_SI 0x2 /* 0 2 = */=0A= +#define Index_Writeback_Inv_SD 0x3 /* 0 3 = */=0A= +#define Index_Load_Tag_I 0x4 /* 1 0 = */=0A= +#define Index_Load_Tag_D 0x5 /* 1 1 = */=0A= +#define Index_Load_Tag_SI 0x6 /* 1 2 = */=0A= +#define Index_Load_Tag_SD 0x7 /* 1 3 = */=0A= +#define Index_Store_Tag_I 0x8 /* 2 0 = */=0A= +#define Index_Store_Tag_D 0x9 /* 2 1 = */=0A= +#define Index_Store_Tag_SI 0xA /* 2 2 = */=0A= +#define Index_Store_Tag_SD 0xB /* 2 3 = */=0A= +#define Create_Dirty_Exc_D 0xD /* 3 1 = */=0A= +#define Create_Dirty_Exc_SD 0xF /* 3 3 = */=0A= +#define Hit_Invalidate_I 0x10 /* 4 0 = */=0A= +#define Hit_Invalidate_D 0x11 /* 4 1 = */=0A= +#define Hit_Invalidate_SI 0x12 /* 4 2 = */=0A= +#define Hit_Invalidate_SD 0x13 /* 4 3 = */=0A= +#define Hit_Writeback_Inv_D 0x15 /* 5 1 = */=0A= +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 = */=0A= +#define Fill_I 0x14 /* 5 0 = */=0A= +#define Hit_Writeback_D 0x19 /* 6 1 = */=0A= +#define Hit_Writeback_SD 0x1B /* 6 3 = */=0A= +#define Hit_Writeback_I 0x18 /* 6 0 = */=0A= +#define Hit_Set_Virtual_SI 0x1E /* 7 2 = */=0A= +#define Hit_Set_Virtual_SD 0x1F /* 7 3 = */=0A= +#define CFG_EW32 0x00040000 /* 32 bit */=0A= +#endif /* CPU_R32364 */=0A= +=0A= +#if defined(CPU_R4000)=0A= +/* R4000 configuration register definitions */=0A= +#define CFG_CM 0x80000000 /* Master-Checker mode */=0A= +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */=0A= +#define CFG_ECBY2 0x00000000 /* divide by 2 */=0A= +#define CFG_ECBY3 0x10000000 /* divide by 3 */=0A= +#define CFG_ECBY4 0x20000000 /* divide by 4 */=0A= +#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */=0A= +#define CFG_EPD 0x00000000 /* D */=0A= +#define CFG_EPDDX 0x01000000 /* DDX */=0A= +#define CFG_EPDDXX 0x02000000 /* DDXX */=0A= +#define CFG_EPDXDX 0x03000000 /* DXDX */=0A= +#define CFG_EPDDXXX 0x04000000 /* DDXXX */=0A= +#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */=0A= +#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */=0A= +#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */=0A= +#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */=0A= +#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */=0A= +#define CFG_SBSHIFT 22=0A= +#define CFG_SB4 0x00000000 /* 4 words */=0A= +#define CFG_SB8 0x00400000 /* 8 words */=0A= +#define CFG_SB16 0x00800000 /* 16 words */=0A= +#define CFG_SB32 0x00c00000 /* 32 words */=0A= +#define CFG_SS 0x00200000 /* Split secondary cache */=0A= +#define CFG_SW 0x00100000 /* Secondary cache port width */=0A= +#define CFG_EWMASK 0x000c0000 /* System port width */=0A= +#define CFG_EWSHIFT 18=0A= +#define CFG_EW64 0x00000000 /* 64 bit */=0A= +#define CFG_EW32 0x00040000 /* 32 bit */=0A= +/* #if defined(CPU_R5000) */=0A= +/* Sugan added for R5000 L2 cache 07-17-96 */=0A= +#define L2_PAGESIZE 0x1000=0A= +#define SIZE256K 0x00040000 /* 256KB in Hex */=0A= +#define CFG_HARDL2 0x00020000 /* Hardware bit that enables/disables=0A= + L2 cache */=0A= +#define CFG_SE 0x1000=0A= +#define CFG_SIZE512K 0x00000000 /* size of Scache is 512k */=0A= +#define CFG_SIZE1MB 0x00100000 /* size of Scache is 1MB */=0A= +#define CFG_SIZE2MB 0x00200000 /* size of Scache is 2MB */=0A= +#define CFG_SIZEMASK 0x00300000 /* size mask */=0A= +/* #endif */=0A= +#define CFG_SC 0x00020000 /* Secondary cache absent */=0A= +#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */=0A= +#define CFG_BE 0x00008000 /* Big Endian */=0A= +#define CFG_EM 0x00004000 /* ECC mode enable */=0A= +#define CFG_EB 0x00002000 /* Block ordering */=0A= +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */=0A= +#define CFG_ICSHIFT 9=0A= +#define CFG_DCMASK 0x000001c0 /* Data cache size */=0A= +#define CFG_DCSHIFT 6=0A= +#define CFG_IB 0x00000020 /* Instruction cache block size */=0A= +#define CFG_DB 0x00000010 /* Data cache block size */=0A= +#define CFG_CU 0x00000008 /* Update on Store Conditional */=0A= +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */=0A= +=0A= +/*=0A= + * R4000 primary cache mode=0A= + */=0A= +#define CFG_C_WRITETHROUGH_CACHE 0=0A= +#define CFG_C_UNCACHED 2=0A= +#define CFG_C_NONCOHERENT 3=0A= +#define CFG_C_COHERENTXCL 4=0A= +#define CFG_C_COHERENTXCLW 5=0A= +#define CFG_C_COHERENTUPD 6=0A= +=0A= +/*=0A= + * R4000 cache operations (should be in assembler...?)=0A= + */=0A= +#if defined(CPU_R5000)=0A= +#define InvAllScache 0x03 /* 0 3 */=0A= +#define IndexLoadTagScache 0x07 /* 1 3 */=0A= +#define IndexStoreTagScache 0x0b /* 2 3 */=0A= +#define PageInvScache 0x17 /* 5 3 */=0A= +#endif=0A= +#define Index_Invalidate_I 0x0 /* 0 0 = */=0A= +#define Index_Writeback_Inv_D 0x1 /* 0 1 = */=0A= +#define Index_Invalidate_SI 0x2 /* 0 2 = */=0A= +#define Index_Writeback_Inv_SD 0x3 /* 0 3 = */=0A= +#define Index_Load_Tag_I 0x4 /* 1 0 = */=0A= +#define Index_Load_Tag_D 0x5 /* 1 1 = */=0A= +#define Index_Load_Tag_SI 0x6 /* 1 2 = */=0A= +#define Index_Load_Tag_SD 0x7 /* 1 3 = */=0A= +#define Index_Store_Tag_I 0x8 /* 2 0 = */=0A= +#define Index_Store_Tag_D 0x9 /* 2 1 = */=0A= +#define Index_Store_Tag_SI 0xA /* 2 2 = */=0A= +#define Index_Store_Tag_SD 0xB /* 2 3 = */=0A= +#define Create_Dirty_Exc_D 0xD /* 3 1 = */=0A= +#define Create_Dirty_Exc_SD 0xF /* 3 3 = */=0A= +#define Hit_Invalidate_I 0x10 /* 4 0 = */=0A= +#define Hit_Invalidate_D 0x11 /* 4 1 = */=0A= +#define Hit_Invalidate_SI 0x12 /* 4 2 = */=0A= +#define Hit_Invalidate_SD 0x13 /* 4 3 = */=0A= +#define Hit_Writeback_Inv_D 0x15 /* 5 1 = */=0A= +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 = */=0A= +#define Fill_I 0x14 /* 5 0 = */=0A= +#define Hit_Writeback_D 0x19 /* 6 1 = */=0A= +#define Hit_Writeback_SD 0x1B /* 6 3 = */=0A= +#define Hit_Writeback_I 0x18 /* 6 0 = */=0A= +#define Hit_Set_Virtual_SI 0x1E /* 7 2 = */=0A= +#define Hit_Set_Virtual_SD 0x1F /* 7 3 = */=0A= +=0A= +#endif=0A= +=0A= +/*=0A= +** TLB resource defines=0A= +*/=0A= +=0A= +#if defined(CPU_R32364) =0A= +#define N_TLB_ENTRIES 16=0A= +#endif =0A= +=0A= +#if defined(CPU_R4000)=0A= +#define N_TLB_ENTRIES 48=0A= +#endif=0A= +=0A= +#if defined (CPU_R32364)=0A= +#define TLBHI_VPN2MASK 0xffffe000=0A= +#define TLBHI_PIDMASK 0x000000ff=0A= +#define TLBHI_NPID 256=0A= +=0A= +#define TLBLO_PFNMASK 0x03ffffc0=0A= +#define TLBLO_PFNSHIFT 6=0A= +#define TLBLO_D 0x00000004 /* writeable */=0A= +#define TLBLO_V 0x00000002 /* valid bit */=0A= +#define TLBLO_G 0x00000001 /* global access bit */=0A= +#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */=0A= +#define TLBLO_CSHIFT 3=0A= +=0A= +#define TLBLO_UNCACHED (CFG_C_UNCACHED< k, 1 =3D> u = */=0A= +#define SR_IEO 0x00000010 /* old interrupt enable, 1 =3D> enable = */=0A= +#define SR_KUP 0x00000008 /* prev kernel/user, 0 =3D> k, 1 =3D> u = */=0A= +#define SR_IEP 0x00000004 /* prev interrupt enable, 1 =3D> enable = */=0A= +#define SR_KUC 0x00000002 /* cur kernel/user, 0 =3D> k, 1 =3D> u = */=0A= +#define SR_IEC 0x00000001 /* cur interrupt enable, 1 =3D> enable = */=0A= +#endif=0A= +=0A= +#if defined S364 /* (CPU_R32364) */=0A= +#define SR_CUMASK 0xf0000000 /* coproc usable bits */=0A= +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */=0A= +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */=0A= +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */=0A= +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */=0A= +=0A= +/* defines for R32364 processor */=0A= +#define SR_NBL 0x08000000 /* Non Blocking Load */=0A= +#define SR_RE 0X02000000 /* Reverse Endianness */=0A= +#define SR_DL 0x01000000 /* Data Cache Locking */=0A= +#define SR_IL 0x00800000 /* Instruction Cache Locking */=0A= +=0A= +#define SR_BEV 0x00400000 /* Use boot exception vectors */=0A= +#define SR_SR 0x00100000 /* Soft reset */=0A= +#define SR_CH 0x00040000 /* Cache hit */=0A= +#define SR_CE 0x00020000 /* Use cache ECC */=0A= +#define SR_DE 0x00010000 /* Disable cache exceptions */=0A= +=0A= +/*=0A= +** status register interrupt masks and bits=0A= +*/=0A= +=0A= +#define SR_IMASK 0x0000ff00 /* Interrupt mask */=0A= +#define SR_IMASK8 0x00000000 /* mask level 8 */=0A= +#define SR_IMASK7 0x00008000 /* mask level 7 */=0A= +#define SR_IMASK6 0x0000c000 /* mask level 6 */=0A= +#define SR_IMASK5 0x0000e000 /* mask level 5 */=0A= +#define SR_IMASK4 0x0000f000 /* mask level 4 */=0A= +#define SR_IMASK3 0x0000f800 /* mask level 3 */=0A= +#define SR_IMASK2 0x0000fc00 /* mask level 2 */=0A= +#define SR_IMASK1 0x0000fe00 /* mask level 1 */=0A= +#define SR_IMASK0 0x0000ff00 /* mask level 0 */=0A= +=0A= +#define SR_IMASKSHIFT 8=0A= +=0A= +#define SR_IBIT8 0x00008000 /* bit level 8 */=0A= +#define SR_IBIT7 0x00004000 /* bit level 7 */=0A= +#define SR_IBIT6 0x00002000 /* bit level 6 */=0A= +#define SR_IBIT5 0x00001000 /* bit level 5 */=0A= +#define SR_IBIT4 0x00000800 /* bit level 4 */=0A= +#define SR_IBIT3 0x00000400 /* bit level 3 */=0A= +#define SR_IBIT2 0x00000200 /* bit level 2 */=0A= +#define SR_IBIT1 0x00000100 /* bit level 1 */=0A= +=0A= +#define SR_KSMASK 0x00000016 /* Kernel mode mask */=0A= +#define SR_KSUSER 0x00000000 /* User Mode */=0A= +#define SR_KSKERNEL 0x00000016 /* Kernel Mode */=0A= +=0A= +#define SR_ERL 0x00000004 /* Error level */=0A= +#define SR_EXL 0x00000002 /* Exception level */=0A= +#define SR_IE 0x00000001 /* Interrupts enabled */=0A= +#define NOT_SR_IEC 0xfffffffe /* assembler problem with = li=0A= +~SR_IEC */=0A= +=0A= +/* R32364 Cache locking bits */=0A= +#define SR_ICACHELOCK 0x00800000=0A= +#define SR_DCACHELOCK 0x01000000=0A= +=0A= +#endif /* CPU_R32364 */=0A= +=0A= +#if defined(CPU_R4000)=0A= +#define SR_CUMASK 0xf0000000 /* coproc usable bits */=0A= +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */=0A= +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */=0A= +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */=0A= +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */=0A= +=0A= +#define SR_RP 0x08000000 /* Reduced power operation */=0A= +#define SR_FR 0x04000000 /* Additional floating pt registers */=0A= +#define SR_RE 0x02000000 /* Reverse endian in user mode */=0A= +=0A= +#define SR_BEV 0x00400000 /* Use boot exception vectors */=0A= +#define SR_TS 0x00200000 /* TLB shutdown */=0A= +#define SR_SR 0x00100000 /* Soft reset */=0A= +#define SR_CH 0x00040000 /* Cache hit */=0A= +#define SR_CE 0x00020000 /* Use cache ECC */=0A= +#define SR_DE 0x00010000 /* Disable cache exceptions */=0A= +=0A= +/*=0A= +** status register interrupt masks and bits=0A= +*/=0A= +=0A= +#define SR_IMASK 0x0000ff00 /* Interrupt mask */=0A= +#define SR_IMASK8 0x00000000 /* mask level 8 */=0A= +#define SR_IMASK7 0x00008000 /* mask level 7 */=0A= +#define SR_IMASK6 0x0000c000 /* mask level 6 */=0A= +#define SR_IMASK5 0x0000e000 /* mask level 5 */=0A= +#define SR_IMASK4 0x0000f000 /* mask level 4 */=0A= +#define SR_IMASK3 0x0000f800 /* mask level 3 */=0A= +#define SR_IMASK2 0x0000fc00 /* mask level 2 */=0A= +#define SR_IMASK1 0x0000fe00 /* mask level 1 */=0A= +#define SR_IMASK0 0x0000ff00 /* mask level 0 */=0A= +=0A= +#define SR_IMASKSHIFT 8=0A= +=0A= +#define SR_IBIT8 0x00008000 /* bit level 8 */=0A= +#define SR_IBIT7 0x00004000 /* bit level 7 */=0A= +#define SR_IBIT6 0x00002000 /* bit level 6 */=0A= +#define SR_IBIT5 0x00001000 /* bit level 5 */=0A= +#define SR_IBIT4 0x00000800 /* bit level 4 */=0A= +#define SR_IBIT3 0x00000400 /* bit level 3 */=0A= +#define SR_IBIT2 0x00000200 /* bit level 2 */=0A= +#define SR_IBIT1 0x00000100 /* bit level 1 */=0A= +=0A= +#define SR_KSMASK 0x00000018 /* Kernel mode mask */=0A= +#define SR_KSUSER 0x00000010 /* User mode */=0A= +#define SR_KSSUPER 0x00000008 /* Supervisor mode */=0A= +#define SR_KSKERNEL 0x00000000 /* Kernel mode */=0A= +#define SR_ERL 0x00000004 /* Error level */=0A= +#define SR_EXL 0x00000002 /* Exception level */=0A= +#define SR_IE 0x00000001 /* Interrupts enabled */=0A= +=0A= +/* R4650 Cache locking bits */=0A= +#define SR_ICACHELOCK 0x00800000=0A= +#define SR_DCACHELOCK 0x01000000=0A= +=0A= +=0A= +#endif=0A= +#if defined(CPU_R3000)=0A= +#define SR_FR 0x04000000 /* Additional floating point registers */=0A= +#endif=0A= +=0A= +=0A= +=0A= +/*=0A= + * Cause Register=0A= + */=0A= +#define CAUSE_BD 0x80000000 /* Branch delay slot */=0A= +#define CAUSE_CEMASK 0x30000000 /* coprocessor error */=0A= +#define CAUSE_CESHIFT 28=0A= +#define CAUSE_IW 0x01000000 /* Instruction watch */=0A= +#define CAUSE_DW 0x02000000 /* Data watch */=0A= +#define CAUSE_IPE 0x04000000 /* Imprecise exception */=0A= +=0A= +=0A= +#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */=0A= +#define CAUSE_IPSHIFT 8=0A= +=0A= +/* Notice: Watch Exception if Exc. Code is 23 is not included in the = mask=0A= + * for R32364.=0A= + */=0A= +#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */=0A= +#define CAUSE_EXCSHIFT 2=0A= +=0A= +#ifndef XDS=0A= +/*=0A= +** Coprocessor 0 registers=0A= +*/=0A= +=0A= +/* Evelyn, 12/12/94, for P3 */=0A= +#define C0_IBASE $0 /* I base */=0A= +#define C0_IBOUND $1 /* I bound */=0A= +=0A= +#define C0_INX $0 /* tlb index */=0A= +#define C0_RAND $1 /* tlb random */=0A= +#if defined(CPU_R3000)=0A= +#define C0_TLBLO $2 /* tlb entry low */=0A= +#define C0_BUSCTRL $2 /* bus control R3041 specific */=0A= +#define C0_CONFIG $3 /* cache config */=0A= +#define C0_CTXT $4 /* tlb context */=0A= +#define C0_BADVADDR $8 /* bad virtual address */=0A= +#define C0_COUNT $9 /* count R3041 specific */=0A= +#define C0_PORTSIZE $10 /* port size R3041 specific */=0A= +#define C0_TLBHI $10 /* tlb entry hi */=0A= +#define C0_COMPARE $11 /* compare R3041 specific */=0A= +#define C0_SR $12 /* status register */=0A= +#define C0_CAUSE $13 /* exception cause */=0A= +#define C0_EPC $14 /* exception pc */=0A= +#define C0_PRID $15 /* revision identifier */=0A= +#endif=0A= +=0A= +#if defined(S364) /*(CPU_R32364) */=0A= +#define C0_RANDOM $1=0A= +#define C0_TLBLO0 $2 /* tlb entry low 0 */=0A= +#define C0_TLBLO1 $3 /* tlb entry low 1 */=0A= +#define C0_CTXT $4 /* tlb context */=0A= +#define C0_PAGEMASK $5 /* tlb page mask */=0A= +#define C0_WIRED $6 /* number of wired tlb entries */=0A= +=0A= +#define C0_INX $0 /* tlb index */=0A= +#define C0_BADVADDR $8 /* bad virtual address */=0A= +#define C0_COUNT $9 /* timer count */=0A= +#define C0_TLBHI $10 /* tlb entry hi */=0A= +#define C0_COMPARE $11 /* timer comparator */=0A= +#define C0_SR $12 /* status register */=0A= +#define C0_CAUSE $13 /* exception cause */=0A= +#define C0_EPC $14 /* exception pc */=0A= +#define C0_PRID $15 /* revision identifier */=0A= +#define C0_CONFIG $16 /* configuration register */=0A= +=0A= +#define C0_IWATCH $18 /* Instr brk pt Virtual add. */=0A= +#define C0_DWATCH $19 /* Data brk pt Virtual add. */=0A= +=0A= +#define C0_IEPC $22 /* Imprecise Exception pc */=0A= +#define C0_DEPC $23 /* Debug Exception pc */=0A= +#define C0_DEBUG $24 /* Debug control/status reg */=0A= +=0A= +#define C0_ECC $26 /* primary cache Parity control */=0A= +#define C0_CACHEERR $27 /* cache error status */=0A= +#define C0_TAGLO $28 /* cache tag lo */=0A= +#define C0_TAGHI $29=0A= +#define C0_ERRPC $30 /* cache error pc */=0A= +#endif /* CPU_R32364 */=0A= +=0A= +#if defined(CPU_R4000)=0A= +=0A= +/* Evelyn, 12/12/94, for P3 */=0A= +#define C0_DBASE $2 /* D base */=0A= +#define C0_DBOUND $3 /* D bound */=0A= +=0A= +#define C0_TLBLO0 $2 /* tlb entry low 0 */=0A= +#define C0_TLBLO1 $3 /* tlb entry low 1 */=0A= +#define C0_CTXT $4 /* tlb context */=0A= +#define C0_PAGEMASK $5 /* tlb page mask */=0A= +#define C0_WIRED $6 /* number of wired tlb entries */=0A= +=0A= +#define C0_BADVADDR $8 /* bad virtual address */=0A= +#define C0_COUNT $9 /* cycle count */=0A= +#define C0_TLBHI $10 /* tlb entry hi */=0A= +#define C0_COMPARE $11 /* cyccle count comparator */=0A= +#define C0_SR $12 /* status register */=0A= +#define C0_CAUSE $13 /* exception cause */=0A= +#define C0_EPC $14 /* exception pc */=0A= +#define C0_PRID $15 /* revision identifier */=0A= +#define C0_CONFIG $16 /* configuration register */=0A= +=0A= +/* Evelyn, 12/12/94, for P3 */=0A= +#define C0_CALG $17 /* Calg rigister */=0A= +#define C0_IWATCH $18 /* IWatch register */=0A= +#define C0_DWATCH $19 /* DWatch register */=0A= +=0A= +#define C0_LLADDR $17 /* linked load address */=0A= +#define C0_WATCHLO $18 /* watchpoint trap register */=0A= +#define C0_WATCHHI $19 /* watchpoint trap register */=0A= +#define C0_XCTXT $20 /* extended tlb context */=0A= +#define C0_ECC $26 /* secondary cache ECC control */=0A= +#define C0_CACHEERR $27 /* cache error status */=0A= +#define C0_TAGLO $28 /* cache tag lo */=0A= +#define C0_TAGHI $29 /* cache tag hi */=0A= +#define C0_ERRPC $30 /* cache error pc */=0A= +#endif=0A= +#endif =0A= +#endif /* defined(__IDTCPU_H__) */=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/idthdr.h = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/idthdr.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/idthdr.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/idthdr.h 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,54 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Some macros. Though they are already defined else where in the = linux=0A= + * tree, they are once again declared here for the ease of syncing = up with=0A= + * IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef XDS=0A= +=0A= +#define FRAME(name,frm_reg,offset,ret_reg) \=0A= + .globl name; \=0A= + .ent name; \=0A= +name:; \=0A= + .frame frm_reg,offset,ret_reg=0A= +=0A= +#define ENDFRAME(name) .end name=0A= +=0A= +#else=0A= +=0A= +#define FRAME(name,frm_reg,offset,ret_reg) \=0A= +name:=0A= +=0A= +#define ENDFRAME(name)=0A= +=0A= +#endif=0A= +=0A= +=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/image.lds.in = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/image.lds.in=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/image.lds.in = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/image.lds.in = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D IMSTART;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32300/S334/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D BSS_START;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/iregdef.h = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/iregdef.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/iregdef.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/iregdef.h = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,284 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT CPU register definitions. Though the registers are already = defined=0A= + * under asm directory, they are once again declared here for the = ease of=0A= + * syncing up with IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#define r0 $0=0A= +#define r1 $1 /*at assembler temp */=0A= +#define r2 $2 /*v0 return value */=0A= +#define r3 $3 /*v1 return value */=0A= +#define r4 $4 /*a0 argument 0 */=0A= +#define r5 $5 /*a1 argument 1 */=0A= +#define r6 $6=0A= +#define r7 $7=0A= +#define r8 $8=0A= +#define r9 $9=0A= +#define r10 $10=0A= +#define r11 $11=0A= +#define r12 $12=0A= +#define r13 $13=0A= +=0A= +#define r14 $14=0A= +#define r15 $15=0A= +#define r16 $16 /*s0 called saved */=0A= +#define r17 $17=0A= +#define r18 $18=0A= +#define r19 $19=0A= +#define r20 $20=0A= +#define r21 $21=0A= +#define r22 $22=0A= +#define r23 $23 /*s7 called saved */=0A= +#define r24 $24=0A= +#define r25 $25=0A= +#define r26 $26 /*k0 kernel temp. */=0A= +#define r27 $27 /*k1 "" "" */=0A= +#define r28 $28 /*gp global pointer */=0A= +#define r29 $29 /*sp stack pointer */=0A= +#define r30 $30 /*fp frame pointer */=0A= +#define r31 $31 /*ra return address */=0A= +=0A= +#define fp0 $f0=0A= +#define fp1 $f1=0A= +#define fp2 $f2=0A= +#define fp3 $f3=0A= +#define fp4 $f4=0A= +#define fp5 $f5=0A= +#define fp6 $f6=0A= +#define fp7 $f7=0A= +#define fp8 $f8=0A= +#define fp9 $f9=0A= +#define fp10 $f10=0A= +#define fp11 $f11=0A= +#define fp12 $f12=0A= +#define fp13 $f13=0A= +#define fp14 $f14=0A= +#define fp15 $f15=0A= +#define fp16 $f16=0A= +#define fp17 $f17=0A= +#define fp18 $f18=0A= +#define fp19 $f19=0A= +#define fp20 $f20=0A= +#define fp21 $f21=0A= +#define fp22 $f22=0A= +#define fp23 $f23=0A= +#define fp24 $f24=0A= +#define fp25 $f25=0A= +#define fp26 $f26=0A= +#define fp27 $f27=0A= +#define fp28 $f28=0A= +#define fp29 $f29=0A= +#define fp30 $f30=0A= +#define fp31 $f31=0A= +=0A= +#define fcr0 $0=0A= +#define fcr30 $30=0A= +#define fcr31 $31=0A= +=0A= +#define zero $0 /* wired zero */=0A= +#define AT $at /* assembler temp */=0A= +#define v0 $2 /* return value */=0A= +#define v1 $3=0A= +#define a0 $4 /* argument registers */=0A= +#define a1 $5=0A= +#define a2 $6=0A= +#define a3 $7=0A= +#define t0 $8 /* caller saved */=0A= +#define t1 $9=0A= +#define t2 $10=0A= +#define t3 $11=0A= +#define t4 $12=0A= +#define t5 $13=0A= +#define t6 $14=0A= +#define t7 $15=0A= +#define s0 $16 /* callee saved */=0A= +#define s1 $17=0A= +#define s2 $18=0A= +#define s3 $19=0A= +#define s4 $20=0A= +#define s5 $21=0A= +#define s6 $22=0A= +#define s7 $23=0A= +#define t8 $24 /* code generator */=0A= +#define t9 $25=0A= +#define k0 $26 /* kernel temporary */=0A= +#define k1 $27=0A= +#define gp $28 /* global pointer */=0A= +#define sp $29 /* stack pointer */=0A= +#define s8 $30 /* yet another saved reg for the callee */=0A= +#define fp $30 /* frame pointer - this is being phased out by MIPS = */=0A= +#define ra $31 /* return address */=0A= +=0A= +=0A= +/*=0A= + * register names=0A= + */=0A= +#define R_R0 0=0A= +#define R_R1 1=0A= +#define R_R2 2=0A= +#define R_R3 3=0A= +#define R_R4 4=0A= +#define R_R5 5=0A= +#define R_R6 6=0A= +#define R_R7 7=0A= +#define R_R8 8=0A= +#define R_R9 9=0A= +#define R_R10 10=0A= +#define R_R11 11=0A= +#define R_R12 12=0A= +#define R_R13 13=0A= +#define R_R14 14=0A= +#define R_R15 15=0A= +#define R_R16 16=0A= +#define R_R17 17=0A= +#define R_R18 18=0A= +#define R_R19 19=0A= +#define R_R20 20=0A= +#define R_R21 21=0A= +#define R_R22 22=0A= +#define R_R23 23=0A= +#define R_R24 24=0A= +#define R_R25 25=0A= +#define R_R26 26=0A= +#define R_R27 27=0A= +#define R_R28 28=0A= +#define R_R29 29=0A= +#define R_R30 30=0A= +#define R_R31 31=0A= +#define R_F0 32=0A= +#define R_F1 33=0A= +#define R_F2 34=0A= +#define R_F3 35=0A= +#define R_F4 36=0A= +#define R_F5 37=0A= +#define R_F6 38=0A= +#define R_F7 39=0A= +#define R_F8 40=0A= +#define R_F9 41=0A= +#define R_F10 42=0A= +#define R_F11 43=0A= +#define R_F12 44=0A= +#define R_F13 45=0A= +#define R_F14 46=0A= +#define R_F15 47=0A= +#define R_F16 48=0A= +#define R_F17 49=0A= +#define R_F18 50=0A= +#define R_F19 51=0A= +#define R_F20 52=0A= +#define R_F21 53=0A= +#define R_F22 54=0A= +#define R_F23 55=0A= +#define R_F24 56=0A= +#define R_F25 57=0A= +#define R_F26 58=0A= +#define R_F27 59=0A= +#define R_F28 60=0A= +#define R_F29 61=0A= +#define R_F30 62=0A= +#define R_F31 63=0A= +#define NCLIENTREGS 64=0A= +#define R_EPC 64=0A= +#define R_MDHI 65=0A= +#define R_MDLO 66=0A= +#define R_SR 67=0A= +#define R_CAUSE 68=0A= +#define R_TLBHI 69=0A= +#ifdef CPU_R4000=0A= +#define R_TLBLO0 70=0A= +#else=0A= +#define R_TLBLO 70=0A= +#endif=0A= +#define R_BADVADDR 71=0A= +#define R_INX 72=0A= +#define R_RAND 73=0A= +#define R_CTXT 74=0A= +#define R_EXCTYPE 75=0A= +#define R_MODE 76=0A= +#define R_PRID 77=0A= +#define R_FCSR 78=0A= +#define R_FEIR 79=0A= +#ifdef CPU_R4000=0A= +#define R_TLBLO1 80=0A= +#define R_PAGEMASK 81=0A= +#define R_WIRED 82=0A= +#define R_COUNT 83=0A= +#define R_COMPARE 84=0A= +#define R_CONFIG 85=0A= +#define R_LLADDR 86=0A= +#define R_WATCHLO 87=0A= +#define R_WATCHHI 88=0A= +#define R_ECC 89=0A= +#define R_CACHEERR 90=0A= +#define R_TAGLO 91=0A= +#define R_TAGHI 92=0A= +#define R_ERRPC 93=0A= +#endif=0A= +=0A= +#ifdef CPU_R4000=0A= +#define NREGS 94=0A= +#else=0A= +#define NREGS 80=0A= +#endif=0A= +=0A= +/*=0A= + * compiler defined bindings=0A= + */=0A= +#define R_ZERO R_R0=0A= +#define R_AT R_R1=0A= +#define R_V0 R_R2=0A= +#define R_V1 R_R3=0A= +#define R_A0 R_R4=0A= +#define R_A1 R_R5=0A= +#define R_A2 R_R6=0A= +#define R_A3 R_R7=0A= +#define R_T0 R_R8=0A= +#define R_T1 R_R9=0A= +#define R_T2 R_R10=0A= +#define R_T3 R_R11=0A= +#define R_T4 R_R12=0A= +#define R_T5 R_R13=0A= +#define R_T6 R_R14=0A= +#define R_T7 R_R15=0A= +#define R_S0 R_R16=0A= +#define R_S1 R_R17=0A= +#define R_S2 R_R18=0A= +#define R_S3 R_R19=0A= +#define R_S4 R_R20=0A= +#define R_S5 R_R21=0A= +#define R_S6 R_R22=0A= +#define R_S7 R_R23=0A= +#define R_T8 R_R24=0A= +#define R_T9 R_R25=0A= +#define R_K0 R_R26=0A= +#define R_K1 R_R27=0A= +#define R_GP R_R28=0A= +#define R_SP R_R29=0A= +#define R_FP R_R30=0A= +#define R_RA R_R31=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/Makefile = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/Makefile 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,151 @@=0A= +#######################################################################= ########=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile create a compressed zImage or Rommable rImage=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +#=0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +# =0A= +# =0A= +#######################################################################= ########=0A= +=0A= +#######################################################################= ########=0A= +# The following is taken from IDT/Sim Makefile=0A= +#######################################################################= ########=0A= +TARGET=3D134=0A= +TARGETDIR=3DS134_334=0A= +# Even though this makefile is for S334A board, we continue to use = files=0A= +# from the S134 & S334 board based source. A -DS334A in the = sources=0A= +# will distinguish code that is unique to S334A boards.=0A= +=0A= +#=0A= +# following refers to memory type in use in eval board and if more = than one=0A= +# then the order is implied. These are values for the switch = MEMCFG.=0A= +#=0A= +SRAM_ONLY=3D1=0A= +SDRAM_ONLY=3D2=0A= +EDO_ONLY=3D3=0A= +SRAM_N_SDRAM=3D4=0A= +SRAM_N_EDO=3D5=0A= +SDRAM_N_SRAM=3D6=0A= +EDO_N_SRAM=3D7=0A= +=0A= +# following refers to size of the DRAM space.=0A= +# These are values for the switch DRAMSZ.=0A= +=0A= +MB32=3D1=0A= +MB64=3D2=0A= +MB128=3D3=0A= +MB32SO=3D4=0A= +=0A= +# following refers to the size of the boot EPROM space port width.=0A= +# These values are for the switch EPRMPRTWD.=0A= +=0A= +EP8=3D1=0A= +EP32=3D2=0A= +=0A= +MACH=3D -DS$(TARGET) -DS334A -DS334 -DS364 -DCPU_R32364 = -DMEMCFG=3D$(SDRAM_ONLY) -DDRAMSZ=3D$(MB32SO) -DEPRMPRTWD=3D$(EP32)=0A= +COMMSWITCHES=3D $(INCDIRS) $(MACH)=0A= +#***************** END IDT/Sim Makefile = #####################################=0A= +ZDEBUG=3D0=0A= +export ZDEBUG=0A= +=0A= +# working space for gunzip:=0A= +FREE_RAM :=3D 0x80C00000=0A= +END_RAM :=3D 0x80E00000=0A= +=0A= +KERNELCONFIG :=3D $(TOPDIR)/.config=0A= +include $(KERNELCONFIG)=0A= +=0A= +SIZE =3D $(CROSS_COMPILE)size=0A= +=0A= +O_FORMAT =3D $(shell $(OBJDUMP) -i | head -2 | grep elf32)=0A= +=0A= +SYSTEM :=3D $(TOPDIR)/vmlinux=0A= +ZBSS :=3D 0x800A0000=0A= +=0A= +ZIMSTART :=3D $(CONFIG_IDT_ZIMAGE_ADDR)=0A= +RIMSTART :=3D 0x9FC00000=0A= +=0A= +LOADADDR :=3D 0x$(shell $(NM) $(SYSTEM) | grep "A _text" |cut -f1 = -d' ')=0A= +KERNEL_ENTRY :=3D $(shell $(OBJDUMP) -f $(SYSTEM) | sed -n -e = 's/^start address //p')=0A= +=0A= +#######################################################################= #############=0A= +ZIMFLAGS =3D s/IMSTART/$(ZIMSTART)/;s/BSS_START/$(ZBSS)/=0A= +RIMFLAGS =3D s/IMSTART/$(RIMSTART)/;s/BSS_START/$(ZBSS)/=0A= +CFLAGS :=3D -fno-pic -nostdinc -G 0 -mno-abicalls -fno-pic -pipe = -I$(TOPDIR)/include=0A= +AFLAGS :=3D -D__ASSEMBLY__ $(CFLAGS)=0A= +=0A= +#######################################################################= #############=0A= +OBJECTS=3D $(obj)/piggy.o $(obj)/head.o $(obj)/misc.o=0A= +ifneq ($(ZDEBUG),0)=0A= +OBJECTS +=3D $(obj)/uart16550.o=0A= +endif=0A= +=0A= +$(obj)/zImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)=0A= + @sed "$(ZIMFLAGS)" < $< > $@=0A= +=0A= +$(obj)/rImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)=0A= + @sed "$(RIMFLAGS)" < $< > $@=0A= +=0A= +$(obj)/piggy.o: $(SYSTEM) $(obj)/Makefile=0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(SYSTEM) = $(SYSTEM).bin=0A= + gzip -f -9 < $(SYSTEM).bin > $(SYSTEM).gz=0A= + echo "O_FORMAT: " $(O_FORMAT); =0A= + $(LD) -r -b binary --oformat $(O_FORMAT) -o $(obj)/piggy.o = $(SYSTEM).gz=0A= + rm -f $(SYSTEM).bin $(SYSTEM).gz=0A= +=0A= +$(obj)/head.o: $(obj)/head.S $(SYSTEM) $(obj)/Makefile=0A= + $(CC) $(AFLAGS) -DKERNEL_ENTRY=3D$(KERNEL_ENTRY) -c $(obj)/head.S -o = $(obj)/head.o=0A= +=0A= +$(obj)/misc.o: $(obj)/misc.c $(obj)/Makefile=0A= + $(CC) $(CFLAGS) -DLOADADDR=3D$(LOADADDR) -DFREE_RAM=3D$(FREE_RAM) = -DEND_RAM=3D$(END_RAM) \=0A= + -c $< -DZDEBUG=3D$(ZDEBUG) -o $(obj)/misc.o=0A= +=0A= +$(obj)/uart16550.o: $(obj)/uart16550.c $(KERNELCONFIG)=0A= + $(CC) $(CFLAGS) -c $< -o $(obj)/uart16550.o=0A= +=0A= +$(obj)/csu_idt.o: $(obj)/csu_idt.S Makefile $(SYSTEM)=0A= + $(CC) $(AFLAGS) $(COMMSWITCHES) -c $< -o $(obj)/csu_idt.o=0A= +=0A= +zImage: $(obj)/zImage.lds $(SYSTEM) $(OBJECTS)=0A= + $(LD) -T$(obj)/zImage.lds -o $(TOPDIR)/zImage $(OBJECTS)=0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/zImage = $(TOPDIR)/zImage.bin=0A= + $(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 \=0A= + $(TOPDIR)/zImage.bin $(TOPDIR)/zImage.prm=0A= + $(SIZE) $(TOPDIR)/zImage |awk -F" " '{ print $$4 "\t" $$5 }' > = $(TOPDIR)/zImage.size=0A= + rm -f *.o=0A= +=0A= +rImage: $(obj)/rImage.lds $(OBJECTS) $(obj)/csu_idt.o $(SYSTEM)=0A= + @rm -f $(TOPDIR)/*.prm=0A= + $(LD) -T$(obj)/rImage.lds -o $(TOPDIR)/rImage $(obj)/csu_idt.o = $(OBJECTS) =0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/rImage = $(TOPDIR)/rImage.bin=0A= + $(OBJCOPY) -I binary -S -O srec -b 0 --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 $(TOPDIR)/rImage.bin = $(TOPDIR)/rImage0.prm=0A= + $(OBJCOPY) -I binary -S -O srec -b 1 --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 $(TOPDIR)/rImage.bin = $(TOPDIR)/rImage1.prm=0A= + $(OBJCOPY) -I binary -S -O srec -b 2 --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 $(TOPDIR)/rImage.bin = $(TOPDIR)/rImage2.prm=0A= + $(OBJCOPY) -I binary -S -O srec -b 3 --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 $(TOPDIR)/rImage.bin = $(TOPDIR)/rImage3.prm=0A= + $(SIZE) $(TOPDIR)/rImage |awk -F" " '{ print $$4 "\t" $$5 }' > = $(TOPDIR)/rImage.size=0A= + rm -f *.o=0A= +=0A= +clean:=0A= + rm -f *.o $(TOPDIR)/zImage $(TOPDIR)/rImage $(TOPDIR)/*.prm = $(TOPDIR)/rImage.size $(TOPDIR)/zImage.size=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/misc.c = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/misc.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/misc.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/misc.c 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,339 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Code to un-compress linux image=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +=0A= +/*=0A= + * gzip declarations=0A= + */=0A= +#define OF(args) args=0A= +#define STATIC static=0A= +#define memzero(s, n) memset ((s), 0, (n))=0A= +typedef unsigned char uch;=0A= +typedef unsigned short ush;=0A= +typedef unsigned long ulg;=0A= +#define WSIZE 0x8000 /* Window size must be at least 32k, */=0A= + /* and a power of two */=0A= +static uch *inbuf; /* input buffer */=0A= +static uch window[WSIZE]; /* Sliding window buffer */=0A= +=0A= +/* gzip flag byte */=0A= +#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */=0A= +#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part = gzip file */=0A= +#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */=0A= +#define ORIG_NAME 0x08 /* bit 3 set: original file name present = */=0A= +#define COMMENT 0x10 /* bit 4 set: file comment present */=0A= +#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */=0A= +#define RESERVED 0xC0 /* bit 6,7: reserved */=0A= +=0A= +=0A= +static unsigned insize; /* valid bytes in inbuf */=0A= +static unsigned inptr; /* index of next byte to be processed in inbuf = */=0A= +static unsigned outcnt; /* bytes in output buffer */=0A= +=0A= +void variable_init(void);=0A= +#if ZDEBUG > 0=0A= +static void puts(const char *);=0A= +extern void putc_init(void);=0A= +extern void putc(unsigned char c);=0A= +#endif=0A= +static int fill_inbuf(void);=0A= +static void flush_window(void);=0A= +static void error(char *m);=0A= +static void gzip_mark(void **);=0A= +static void gzip_release(void **);=0A= +=0A= +extern char input_data[];=0A= +=0A= +extern char input_data_end[];=0A= +=0A= +#if ZDEBUG > 0=0A= +void int2hex(unsigned long val)=0A= +{=0A= + unsigned char buf[10];=0A= + int i;=0A= + for (i =3D 7; i >=3D 0; i--)=0A= + {=0A= + buf[i] =3D "0123456789ABCDEF"[val & 0x0F];=0A= + val >>=3D 4;=0A= + }=0A= + buf[8] =3D '\0';=0A= + puts(buf);=0A= +}=0A= +#endif=0A= +=0A= +static unsigned long byte_count;=0A= +=0A= +int get_byte(void)=0A= +{=0A= +#if ZDEBUG > 1=0A= + static int printCnt;=0A= +#endif=0A= + unsigned char c =3D (inptr < insize ? inbuf[inptr++] : = fill_inbuf());=0A= + byte_count++;=0A= +=0A= +#if ZDEBUG > 1=0A= + if (printCnt++ < 32)=0A= + {=0A= + puts("byte count =3D ");=0A= + int2hex(byte_count);=0A= + puts(" byte val =3D ");=0A= + int2hex(c);=0A= + puts("\n");=0A= + }=0A= +#endif=0A= + return c;=0A= +}=0A= +=0A= +/* Diagnostic functions */=0A= +#ifdef DEBUG=0A= +# define Assert(cond,msg) {if(!(cond)) error(msg);}=0A= +# define Trace(x) fprintf x=0A= +# define Tracev(x) {if (verbose) fprintf x ;}=0A= +# define Tracevv(x) {if (verbose>1) fprintf x ;}=0A= +# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}=0A= +# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}=0A= +#else=0A= +# define Assert(cond,msg)=0A= +# define Trace(x)=0A= +# define Tracev(x)=0A= +# define Tracevv(x)=0A= +# define Tracec(c,x)=0A= +# define Tracecv(c,x)=0A= +#endif=0A= +=0A= +/*=0A= + * This is set up by the setup-routine at boot-time=0A= + */=0A= +=0A= +static long bytes_out;=0A= +static uch *output_data;=0A= +static unsigned long output_ptr;=0A= +=0A= +=0A= +static void *malloc(int size);=0A= +static void free(void *where);=0A= +static void error(char *m);=0A= +static void gzip_mark(void **);=0A= +static void gzip_release(void **);=0A= +=0A= +static unsigned long free_mem_ptr;=0A= +static unsigned long free_mem_end_ptr;=0A= +=0A= +#include "../../../../../../lib/inflate.c"=0A= +=0A= +static void *malloc(int size)=0A= +{=0A= + void *p;=0A= +=0A= + if (size < 0)=0A= + error("Malloc error\n");=0A= + if (free_mem_ptr <=3D 0) error("Memory error\n");=0A= +=0A= + free_mem_ptr =3D (free_mem_ptr + 3) & ~3; /* Align */=0A= +=0A= + p =3D (void *) free_mem_ptr;=0A= + free_mem_ptr +=3D size;=0A= +=0A= + if (free_mem_ptr >=3D free_mem_end_ptr)=0A= + error("\nOut of memory\n");=0A= +=0A= + return p;=0A= +}=0A= +=0A= +static void free(void *where)=0A= +{ /* Don't care */=0A= +}=0A= +=0A= +static void gzip_mark(void **ptr)=0A= +{=0A= + *ptr =3D (void *) free_mem_ptr;=0A= +}=0A= +=0A= +static void gzip_release(void **ptr)=0A= +{=0A= + free_mem_ptr =3D (long) *ptr;=0A= +}=0A= +#if ZDEBUG > 0=0A= +static void puts(const char *s)=0A= +{=0A= + while (*s) {=0A= + if (*s =3D=3D 10)=0A= + putc(13);=0A= + putc(*s++);=0A= + }=0A= +}=0A= +#endif=0A= +void *memset(void *s, int c, size_t n)=0A= +{=0A= + int i;=0A= + char *ss =3D (char *) s;=0A= +=0A= + for (i =3D 0; i < n; i++)=0A= + ss[i] =3D c;=0A= + return s;=0A= +}=0A= +=0A= +void *memcpy(void *__dest, __const void *__src, size_t __n)=0A= +{=0A= + int i;=0A= + char *d =3D (char *) __dest, *s =3D (char *) __src;=0A= +=0A= + for (i =3D 0; i < __n; i++)=0A= + d[i] =3D s[i];=0A= + return __dest;=0A= +}=0A= +=0A= +/* = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=0A= + * Fill the input buffer. This is called only when the buffer is = empty=0A= + * and at least one byte is really needed.=0A= + */=0A= +static int fill_inbuf(void)=0A= +{=0A= + if (insize !=3D 0) {=0A= + error("ran out of input data\n");=0A= + }=0A= +=0A= + inbuf =3D input_data;=0A= + insize =3D &input_data_end[0] - &input_data[0];=0A= + inptr =3D 1;=0A= + return inbuf[0];=0A= +}=0A= +=0A= +/* = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=0A= + * Write the output window window[0..outcnt-1] and update crc and = bytes_out.=0A= + * (Used for the decompressed data only.)=0A= + */=0A= +static void flush_window(void)=0A= +{=0A= + ulg c =3D crc; /* temporary variable */=0A= + unsigned n;=0A= + uch *in, *out, ch;=0A= +=0A= + in =3D window;=0A= + out =3D &output_data[output_ptr];=0A= + for (n =3D 0; n < outcnt; n++) {=0A= + ch =3D *out++ =3D *in++;=0A= + c =3D crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8);=0A= + }=0A= + crc =3D c;=0A= + bytes_out +=3D (ulg) outcnt;=0A= + output_ptr +=3D (ulg) outcnt;=0A= + outcnt =3D 0;=0A= +}=0A= +=0A= +#if ZDEBUG > 0=0A= +void check_mem(void)=0A= +{=0A= + int i;=0A= +=0A= + puts("\ncplens =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(cplens[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\ncplext =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(cplext[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\nborder =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(border[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\n");=0A= +}=0A= +#endif=0A= +static void error(char *x)=0A= +{=0A= +#if ZDEBUG > 1=0A= + check_mem();=0A= + puts("\n\n");=0A= + puts(x);=0A= + puts("byte_count =3D ");=0A= + int2hex(byte_count);=0A= + puts("\n");=0A= + puts("\n\n -- Error. System halted");=0A= +#endif=0A= + while (1); /* Halt */=0A= +}=0A= +=0A= +void variable_init(void)=0A= +{=0A= + byte_count =3D 0;=0A= + output_data =3D (char *) LOADADDR;=0A= + free_mem_ptr =3D FREE_RAM;=0A= + free_mem_end_ptr =3D END_RAM;=0A= +#if ZDEBUG > 1=0A= + puts("output_data 0x");=0A= + int2hex((unsigned long)output_data); puts("\n");=0A= + puts("free_mem_ptr 0x");=0A= + int2hex(free_mem_ptr); puts("\n");=0A= + puts("free_mem_end_ptr 0x");=0A= + int2hex(free_mem_end_ptr); puts("\n");=0A= + puts("input_data 0x");=0A= + int2hex((unsigned long)input_data); puts("\n");=0A= +#endif=0A= +}=0A= +=0A= +int decompress_kernel(void)=0A= +{=0A= +#if ZDEBUG > 0=0A= + putc_init();=0A= +#if ZDEBUG > 2=0A= + check_mem();=0A= +#endif=0A= +#endif=0A= +=0A= + variable_init();=0A= +=0A= + makecrc();=0A= +#if ZDEBUG > 0=0A= + puts("\n");=0A= + puts("Uncompressing Linux... \n");=0A= +#endif=0A= + gunzip(); // ...see inflate.c=0A= +#if ZDEBUG > 0=0A= + puts("Ok, booting the kernel.\n");=0A= +#endif=0A= +=0A= +#if ZDEBUG > 1=0A= + {=0A= + unsigned long *p =3D (unsigned long *)LOADADDR;=0A= + int2hex(p[0]); puts("\n");=0A= + int2hex(p[1]); puts("\n");=0A= + int2hex(p[2]); puts("\n");=0A= + int2hex(p[3]); puts("\n");=0A= + }=0A= +#endif=0A= +=0A= + return 0;=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/rImage.lds = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/rImage.lds=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/rImage.lds = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/rImage.lds = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D 0x9FC00000;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32300/S334/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D 0x800A0000;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s334aram.h = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s334aram.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s334aram.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s334aram.h = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,330 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT S334 SDRAM setup values.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef __S334RAM__=0A= +#define __S334RAM__=0A= +/******************************** D E F I N E S = *******************************/=0A= +=0A= +#define SRAM_ONLY 1=0A= +#define SDRAM_ONLY 2=0A= +/* #define EDO_ONLY 3 */=0A= +#define SRAM_N_SDRAM 4=0A= +/* #define SRAM_N_EDO 5 */=0A= +#define SDRAM_N_SRAM 6=0A= +/* #define EDO_N_SRAM 7 */=0A= +=0A= +#define APATTERN 0xa5a5a5a5=0A= +=0A= +#define MB32 1=0A= +#define MB64 2=0A= +#define MB128 3=0A= +#define MB32SO 4=0A= +=0A= +#define EP8 1=0A= +#define EP32 2=0A= +=0A= +#define EXTU 1=0A= +#define INTU 2=0A= +=0A= +#ifndef LED_BASE=0A= +=0A= +#if defined(EB332)=0A= +#define LED_BASE PHYS_TO_K1(0x10000000)=0A= +#else=0A= +#define LED_BASE PHYS_TO_K1(0x14000000)=0A= +#endif /* EB332 */=0A= +=0A= +#define LED_DIGIT0 0xf=0A= +#define LED_DIGIT1 0xb=0A= +#define LED_DIGIT2 0x7=0A= +#define LED_DIGIT3 0x3=0A= +#define LED_CLEAR 0x400=0A= +=0A= +#endif=0A= +=0A= +#define SYS_BTA_CTRL PHYS_TO_K1(0x18000000)=0A= +#define SYS_ALT_CTRL PHYS_TO_K1(0x18000004)=0A= +=0A= +#if MHZ < 66000000=0A= +#define SYS_ALT_SETUP 0x00000003 =0A= +#define TRCD 0x00500000 /* used in SDRAM set-up (RCD value) */ =0A= +#else=0A= +#define SYS_ALT_SETUP 0x00000007 =0A= +#define TRCD 0x00600000 /* used in SDRAM set-up (RCD value) */ =0A= +#endif=0A= +=0A= +#define PORT_WIDTH_CONTROL 0xffffe200 /* port width control register = address */=0A= +#define BTA_CONTROL 0xffffe204 /* was 0xffffe240 - hak 06-16-98 = - BTA control register address */=0A= +#define BTA_SETUP 0x3FFFFFFF /* 3 turnaround cycles for all = regions */=0A= +=0A= +#if EPRMPRTWD =3D=3D EP8=0A= +=0A= +#define PORT_SETUP 0xaa822aaa /* changed for 8-bit wide NVRAM = at physical 1200_0000: Upen-000530*/=0A= +=0A= +#elif EPRMPRTWD =3D=3D EP32=0A= +#define PORT_SETUP 0xaa82aaaa /* boot EPROM space port width =3D 32 = bits */=0A= +#else=0A= +#error "illegal value for eprom port width"=0A= +#endif=0A= +=0A= +#define MEM_CTL_BASE PHYS_TO_K1(0x18000200) /* base address of all = (0-5) Memory Control Registers */=0A= +#define MEM_BASE_BASE PHYS_TO_K1(0x18000080) /* base address of 2 = (0-1) Base Address Registers */=0A= +#define R32134_IREG_BASE PHYS_TO_K1(0x18000000) /* all R32134 internal = registers' base address */=0A= +=0A= +/* =0A= +** b14:13=3D>01=3DPROM;b12=3D>1=3D do not assert CS during writes; = b11:10=3D>00=3D8 bit port =0A= +** b09:05=3D>08=3D8 wait states; b04:00=3D>08=3D 8 wait states=0A= +*/=0A= +=0A= +#define MCR_CS0_BS 0x31083108 =0A= +=0A= +=0A= +/* =0A= +** b14:13=3D>00=3DSRAM;b12=3D>0=3D assert CS during writes; = b11:10=3D>10=3D32 bit port =0A= +** b09:05=3D>FF=3D31 wait states; b04:00=3D>FF=3D 31 wait states.=0A= +** NOTE: wait states should be tuned.=0A= +*/=0A= +=0A= +#if defined(EB332)=0A= +#define MCR_CS1_BS 0x60e760e7=0A= +#else=0A= +#define MCR_CS1_BS 0x28632863=0A= +#endif /* EB332 */=0A= +#define MCR_CS2_BS 0x60e760e7=0A= +#define MCR_CS3_BS 0x60e760e7=0A= +#define MCR_CS4_BS 0x60e760e7 /* S334 LED */=0A= +=0A= +/* =0A= +** b14:13=3D>01=3DI Type;b12=3D>0=3D assert CS during writes; = b11:10=3D>00=3D8 bit port =0A= +** b09:05=3D>FF=3D31 wait states; b04:00=3D>FF=3D 31 wait states=0A= +*/=0A= +=0A= +#define MCR_CS5_BS 0x60E760E7=0A= +=0A= +#define MBA_REG0 0x1FC00000 /* phys mem base addr reg val for CS 0 - = EPROM */=0A= +#define MBM_REG0 0xFFC00000 /* mem base mask reg for CS0 -EPROM-4MB = */=0A= +#define CPU_BERR_BS 0xFF=0A= +#define IP_BERR_BS 0xFF=0A= +=0A= +=0A= +=0A= +/*********************************=0A= +* SRAM_ONLY section *=0A= +*********************************/=0A= +=0A= +#if MEMCFG =3D=3D SRAM_ONLY=0A= +=0A= +#define MBA_REG1 0x00000000 /* physical mem bas addr fir CS-1 */=0A= +#define MBM_REG1 0xFFF00000 /* mem bas mask for CS1 */=0A= +=0A= +/****************************************=0A= +* SDRAM_ONLY or SDRAM_N_SRAM section *=0A= +****************************************/=0A= +=0A= +#elif MEMCFG =3D=3D SDRAM_ONLY || MEMCFG =3D=3D SDRAM_N_SRAM=0A= +=0A= +/* =3D=3D=3D=3D=3D=3D=3D 128 MB DIMM section = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/=0A= +=0A= +#if DRAMSZ =3D=3D MB128=0A= +=0A= +#define DRAM_BNK0_BASE 0x00000000 /* 0 MB */=0A= +#define DRAM_BNK1_BASE 0x02000000 /* 32 MB */=0A= +#define DRAM_BNK2_BASE 0x04000000 /* 64 MB */=0A= +#define DRAM_BNK3_BASE 0x06000000 /* 96 MB */=0A= +=0A= +#define DRAM_BNK0_MASK 0xFE000000 /* masks for other banks are = defined at the end */=0A= +=0A= +#define SDRAM_CR_BS 0xB90500FF | TRCD /* SDRAM enable */=0A= +#define SDRAM_DS_BS 0x390500FF | TRCD /* SDRAM disable */=0A= +#define SDRAM_PC_VAL 0xB90501A0 | TRCD /* precharge value */=0A= +#define SDRAM_RFRSH_CMD 0xB9050090 | TRCD /* refresh command */=0A= +#define SDRAM_MODE_REG 0xB9050080 | TRCD /* mode register */=0A= +=0A= +#if MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/* leave a gap of one SDRAM bank's worth of space between end of SDRAM = and start of SRAM */=0A= +#define MBA_REG1 0x0A000000 /* physical mem bas add for CS1 - = 128MB + 32MB*/=0A= +#define MBM_REG1 0xFFF00000 /* mem bas mask for CS1 - SRAM */=0A= +#endif /* #if MEMCFG =3D=3D SDRAM_N_SRAM */=0A= +=0A= +/* =3D=3D=3D=3D=3D=3D=3D=3D 32MB DIMM section = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/=0A= +=0A= +#elif DRAMSZ =3D=3D MB32=0A= +=0A= +#define DRAM_BNK0_BASE 0x00000000 /* 0 MB */=0A= +#define DRAM_BNK1_BASE 0x00800000 /* 8 MB */=0A= +#define DRAM_BNK2_BASE 0x01000000 /* 16 MB */=0A= +#define DRAM_BNK3_BASE 0x01800000 /* 24 MB */=0A= +=0A= +#define DRAM_BNK0_MASK 0xFF800000 /* masks for other banks are = defined at the end */=0A= +=0A= +#define SDRAM_CR_BS 0xB90500FF | TRCD /* SDRAM enable */=0A= +#define SDRAM_DS_BS 0x390500FF | TRCD /* SDRAM disable */=0A= +#define SDRAM_PC_VAL 0xB90501A0 | TRCD /* precharge value */=0A= +#define SDRAM_RFRSH_CMD 0xB9050090 | TRCD /* refresh command */=0A= +#define SDRAM_MODE_REG 0xB9050080 | TRCD /* mode register */=0A= +=0A= +#if MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/* leave a gap of one SDRAM bank's worth of space between end of SDRAM = and start of SRAM */=0A= +#define MBA_REG1 0x04000000 /* physical mem bas add for CS1 - = 32MB*/=0A= +#define MBM_REG1 0xFFF00000 /* mem bas mask for CS1 - SRAM */=0A= +#endif /* MEMCFG =3D=3D SDRAM_N_SRAM */=0A= +=0A= +/* =3D=3D=3D=3D=3D=3D=3D 32MB or 64 MB SODIMM section = =3D=3D=3D=3D=3D=3D=3D=3D */=0A= +=0A= +#elif DRAMSZ =3D=3D MB32SO=0A= +=0A= +#define DRAM_BNK0_BASE 0x00000000 /* 0 MB */=0A= +#define DRAM_BNK1_BASE 0x01000000 /* 8 MB */=0A= +#define DRAM_BNK2_BASE 0x02000000 /* 16 MB */=0A= +#define DRAM_BNK3_BASE 0x03000000 /* 24 MB */=0A= +=0A= +#define DRAM_BNK0_MASK 0xFF000000 /* masks for other banks are = defined at the end */=0A= +=0A= +#define SDRAM_CR_BS 0x890580FF | TRCD /* SDRAM enable */=0A= +#define SDRAM_DS_BS 0x090580FF | TRCD /* SDRAM disable */=0A= +#define SDRAM_PC_VAL 0x890580A0 | TRCD /* Precharge value */=0A= +#define SDRAM_RFRSH_CMD 0x89058090 | TRCD /* Refresh command */=0A= +#define SDRAM_MODE_REG 0x89058080 | TRCD /* Mode register */=0A= +=0A= +#if MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/* leave a gap of one SDRAM bank's worth of space between end of SDRAM = and start of SRAM */=0A= +#define MBA_REG1 0x04000000 /* physical mem bas add for CS1 - = 32MB*/=0A= +#define MBM_REG1 0xFFF00000 /* mem bas mask for CS1 - SRAM */=0A= +#endif /* MEMCFG =3D=3D SDRAM_N_SRAM */=0A= +=0A= +#endif /* DRAMSZ =3D=3D MB32SO */=0A= +=0A= +/***************************************************=0A= +* SRAM_N_SDRAM section (assumes 1 MB SRAM) *=0A= +***************************************************/=0A= +=0A= +#elif MEMCFG =3D=3D SRAM_N_SDRAM=0A= +=0A= +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D 128MB DIMM section = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */=0A= +=0A= +#if DRAMSZ =3D=3D MB128=0A= +=0A= +#define MBA_REG1 0x00000000 /* physical mem bas addr for CS1 */=0A= +#define MBM_REG1 0xFFF00000 /* mem nase mask for CS1 */=0A= +=0A= +/* leave a gap of one SDRAM bank's worth of space between end of SRAM = and start of SDRAM */=0A= +#define DRAM_BNK0_BASE 0x02000000 /* bank 0 at 32 MB */=0A= +#define DRAM_BNK1_BASE 0x04000000 /* 64 MB */=0A= +#define DRAM_BNK2_BASE 0x06000000 /* 96 MB */=0A= +#define DRAM_BNK3_BASE 0x08000000 /* 128 MB */=0A= +=0A= +#define DRAM_BNK0_MASK 0xFE000000 /* masks for other banks are = defined at the end */=0A= +=0A= +#define SDRAM_CR_BS 0xB95500FF | TRCD /* SDRAM enable */=0A= +#define SDRAM_DS_BS 0x395500FF | TRCD /* SDRAM disable */=0A= +#define SDRAM_PC_VAL 0xB95501A0 | TRCD /* precharge value */=0A= +#define SDRAM_RFRSH_CMD 0xB9550090 | TRCD /* refresh command */=0A= +#define SDRAM_MODE_REG 0xB9550080 | TRCD /* mode register */=0A= +=0A= +=0A= +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D 32MB DIMM section = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */=0A= +=0A= +#elif DRAMSZ =3D=3D MB32=0A= +=0A= +#define MBA_REG1 0x00000000 /* physical mem bas addr for CS1 */=0A= +#define MBM_REG1 0xFFF00000 /* mem nase mask for CS1 */=0A= +=0A= +/* leave a gap of one SDRAM bank's worth of space between end of SRAM = and start of SDRAM */=0A= +#define DRAM_BNK0_BASE 0x00800000=0A= +#define DRAM_BNK1_BASE 0x01000000=0A= +#define DRAM_BNK2_BASE 0x01800000=0A= +#define DRAM_BNK3_BASE 0x02000000=0A= +=0A= +#define DRAM_BNK0_MASK 0xFF800000 /* masks for other banks are = defined at the end */=0A= +=0A= +#define SDRAM_CR_BS 0xB95500FF | TRCD /* SDRAM enable */=0A= +#define SDRAM_DS_BS 0x395500FF | TRCD /* SDRAM disable */=0A= +#define SDRAM_PC_VAL 0xB95501A0 | TRCD /* precharge value */=0A= +#define SDRAM_RFRSH_CMD 0xB9550090 | TRCD /* refresh command */=0A= +#define SDRAM_MODE_REG 0xB9550080 | TRCD /* mode register */=0A= +=0A= +/* =3D=3D=3D=3D=3D=3D=3D 32MB or 64 MB SODIMM section = =3D=3D=3D=3D=3D=3D=3D=3D */=0A= +=0A= +#elif DRAMSZ =3D=3D MB32SO=0A= +=0A= +#define MBA_REG1 0x00000000 /* physical mem bas addr for CS1 */=0A= +#define MBM_REG1 0xFFF00000 /* mem nase mask for CS1 */=0A= +=0A= +/* leave a gap of one SDRAM bank's worth of space between end of SRAM = and start of SDRAM */=0A= +#define DRAM_BNK0_BASE 0x01000000=0A= +#define DRAM_BNK1_BASE 0x02000000=0A= +#define DRAM_BNK2_BASE 0x03000000=0A= +#define DRAM_BNK3_BASE 0x04000000=0A= +=0A= +#define DRAM_BNK0_MASK 0xFF000000 /* masks for other banks are = defined at the end */=0A= +=0A= +#define SDRAM_CR_BS 0x8955C0FF | TRCD /* SDRAM enable */=0A= +#define SDRAM_DS_BS 0x0955C0FF | TRCD /* SDRAM disable */=0A= +#define SDRAM_PC_VAL 0x8955C0A0 | TRCD /* precharge value */=0A= +#define SDRAM_RFRSH_CMD 0x8955C090 | TRCD /* refresh command */=0A= +#define SDRAM_MODE_REG 0x8955C080 | TRCD /* mode register */=0A= +=0A= +#else=0A= +#error "unrecognized dram size"=0A= +#endif /* DRAMSZ */=0A= +=0A= +#else=0A= +#error "unrecogized memory configuration parameter"=0A= +#endif /* error */=0A= +=0A= +/* These settings apply to all types of SDRAM modules */=0A= +#if MEMCFG !=3D SRAM_ONLY=0A= +=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +#define DRAM_BNK2_MASK DRAM_BNK0_MASK=0A= +#define DRAM_BNK3_MASK DRAM_BNK0_MASK=0A= +=0A= +#define DRAM_RF_CNT_BS 0x00000000 /* Refresh Count Reg setting*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040 /* Refresh Compare Reg: fast = expiration */=0A= +=0A= +#if MHZ =3D=3D 50000000=0A= +#define DRAM_RF_CMPR_SE_BS 0x000002E8 /* Refresh Compare Reg: = standard expiration */=0A= +#elif MHZ =3D=3D 66500000=0A= +#define DRAM_RF_CMPR_SE_BS 0x000003E0 /* Refresh Compare Reg: = standard expiration */=0A= +#elif MHZ =3D=3D 75000000=0A= +#define DRAM_RF_CMPR_SE_BS 0x00000460 /* Refresh Compare Reg: = standard expiration */=0A= +#else=0A= +#error "MHZ setting in the Makefile must be equal to 50000000, = 66500000 or 75000000 "=0A= +#endif=0A= +=0A= +#endif=0A= +/* parameters for initialising the S134 board EEPROM */=0A= +#define DESTRUCTIVE 1=0A= +#define NONDESTRUCTIVE 0=0A= +=0A= +#endif /* __S334RAM__ */=0A= +=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s334ram.h = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s334ram.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s334ram.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s334ram.h = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,836 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT S334 SDRAM setup values.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef __S334RAM__=0A= +#define __S334RAM__=0A= +/******************************** D E F I N E S = *******************************/=0A= +=0A= +#define SRAM_ONLY 1=0A= +#define SDRAM_ONLY 2=0A= +#define EDO_ONLY 3=0A= +#define SRAM_N_SDRAM 4=0A= +#define SRAM_N_EDO 5=0A= +#define SDRAM_N_SRAM 6=0A= +#define EDO_N_SRAM 7=0A= +=0A= +#define MB32 1=0A= +#define MB64 2=0A= +#define MB128 3=0A= +#define MB32SO 4=0A= +=0A= +#define EP8 1=0A= +#define EP32 2=0A= +=0A= +#define EXTU 1=0A= +#define INTU 2=0A= +=0A= +#ifndef LED_BASE=0A= +=0A= +#if defined(EB332)=0A= +#define LED_BASE PHYS_TO_K1(0x10000000)=0A= +#define LED_DIGIT0 0xC=0A= +#define LED_DIGIT1 0x8=0A= +#define LED_DIGIT2 0x4=0A= +#define LED_DIGIT3 0x0=0A= +#define LED_CLEAR 0x400=0A= +#else=0A= +#define LED_BASE PHYS_TO_K1(0x14000000)=0A= +#define LED_DIGIT0 0xf=0A= +#define LED_DIGIT1 0xb=0A= +#define LED_DIGIT2 0x7=0A= +#define LED_DIGIT3 0x3=0A= +#define LED_CLEAR 0x400=0A= +#endif=0A= +=0A= +#endif=0A= +=0A= +#define SYS_BTA_CTRL PHYS_TO_K1(0x18000000)=0A= +#define SYS_ALT_CTRL PHYS_TO_K1(0x18000004)=0A= +#if MHZ < 67000000=0A= +#warning : compiling for less than 67 MHz=0A= +#define SYS_ALT_SETUP 0x00000003 =0A= +#else=0A= +#warning : compiling for more than 67 MHz=0A= +#define SYS_ALT_SETUP 0x00000007 =0A= +#endif=0A= +#define PORT_WIDTH_CONTROL 0xffffe200 /* port width control register = address */=0A= +#define BTA_CONTROL 0xffffe204 /* was 0xffffe240 - hak 06-16-98 = - BTA control register address */=0A= +#define BTA_SETUP 0x3fffffff /* 3 turnaround cycles for all = regions */=0A= +=0A= +#if EPRMPRTWD =3D=3D EP8=0A= +/*#define PORT_SETUP 0xaaa22aaa was 0xaaa82aaa - hak 06-16-98, = today 22 is for boot prom and external UART 1-4-99 */=0A= +#if defined(EB332)=0A= +#define PORT_SETUP 0xaaa22aaa=0A= +#else=0A= +#define PORT_SETUP 0xaa822aaa /* changed for 8-bit wide NVRAM = at physical 1200_0000: Upen-000530*/=0A= +#endif /* EB332 */=0A= +#elif EPRMPRTWD =3D=3D EP32=0A= +#define PORT_SETUP 0xaaa2aaaa /* boot EPROM space port width =3D 32 = bits */=0A= +#else=0A= +#error "illegal value for eprom port width"=0A= +#endif=0A= +=0A= +#define MEM_CTL_BASE PHYS_TO_K1(0x18000200) /* base address of all = (0-5) Memory Control Registers */=0A= +#define MEM_BASE_BASE PHYS_TO_K1(0x18000080) /* base address of 2 = (0-1) Base Address Registers */=0A= +#define R32134_IREG_BASE PHYS_TO_K1(0x18000000) /* all R32134 = internal registers' base address */=0A= +=0A= +/* =0A= +** b14:13=3D>01=3DPROM;b12=3D>1=3D do not assert CS during writes; = b11:10=3D>00=3D8 bit port =0A= +** b09:05=3D>0A=3D10 wait states; b04:00=3D>0A=3D 10 wait states=0A= +*/=0A= +=0A= +=0A= +/*#define MCR_CS0_BS 0x31ef31ef*/=0A= +#define MCR_CS0_BS 0x30843084=0A= +=0A= +/* =0A= +** b14:13=3D>00=3DSRAM;b12=3D>0=3D assert CS during writes; = b11:10=3D>10=3D32 bit port =0A= +** b09:05=3D>FF=3D31 wait states; b04:00=3D>FF=3D 31 wait states.=0A= +** NOTE: wait states should be tuned.=0A= +*/=0A= +=0A= +=0A= +/*#define MCR_CS1_BS 0x28e728e7*/=0A= +#define MCR_CS1_BS 0x28a528a5=0A= +=0A= +#define MCR_CS2_BS 0xa0e7a0e7=0A= +=0A= +#define MCR_CS3_BS 0xa0e7a0e7=0A= +=0A= +#define MCR_CS4_BS 0xa0e7a0e7 /* S334 LED */=0A= +=0A= +=0A= +/* =0A= +** b14:13=3D>01=3DI Type;b12=3D>0=3D assert CS during writes; = b11:10=3D>00=3D8 bit port =0A= +** b09:05=3D>FF=3D31 wait states; b04:00=3D>FF=3D 31 wait states=0A= +*/=0A= +=0A= +#define MCR_CS5_BS 0xa0E7a0E7=0A= +/*#define MCR_CS5_BS 0x21EF21EF*/=0A= +=0A= +/*=0A= +** physical memory base address register value for Chip Select 0 - = EPROM=0A= +** NOTE: for starters see if you can just set the default value: = 0x1FC00000=0A= +*/=0A= +#define MBA_REG0 0x1FC00000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 0 - EPROM - 4MB=0A= +*/=0A= +#define MBM_REG0 0xFFC00000=0A= +=0A= +=0A= +#define CPU_BERR_BS 0xFF=0A= +#define IP_BERR_BS 0xFF=0A= +=0A= +=0A= +=0A= +#if MEMCFG =3D=3D SRAM_ONLY=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +*/=0A= +#define MBA_REG1 0x00000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +#elif MEMCFG =3D=3D SDRAM_ONLY || MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/*=0A= +*************************************=0A= +** SDRAM_ONLY or SDRAM_N_SRAM section=0A= +*************************************=0A= +*/=0A= +=0A= +#define APATTERN 0xa5a5a5a5=0A= +=0A= +#if DRAMSZ =3D=3D MB128=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 128MB section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 0MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x00000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 32MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x02000000=0A= +/*=0A= +** DRAM BANK2 BASE. 3rd bank at 64MB:=0A= +*/=0A= +#define DRAM_BNK2_BASE 0x04000000=0A= +/*=0A= +** DRAM BANK3 BASE. 4th bank at 96MB:=0A= +*/=0A= +#define DRAM_BNK3_BASE 0x06000000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFFF00000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 2 Mask=0A= +*/=0A= +#define DRAM_BNK2_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 3 Mask=0A= +*/=0A= +#define DRAM_BNK3_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +#define SDRAM_CR_BS 0xb95500FF /* old: 0x9EFBOOFF */=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +#define SDRAM_DS_BS 0x2AF800FF=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +#define SDRAM_PC_VAL 0xb95501a0=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +#define SDRAM_RFRSH_CMD 0xb9550090=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +#define SDRAM_MODE_REG 0xAAF80080=0A= +=0A= +#if MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +** at 128MB:=0A= +*/=0A= +#define MBA_REG1 0x08000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +#endif /* #if MEMCFG =3D=3D SDRAM_N_SRAM */=0A= +=0A= +#elif DRAMSZ =3D=3D MB32=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 32MB section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 0MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x00000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 8MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x00800000=0A= +/*=0A= +** DRAM BANK2 BASE. 3rd bank at 16MB:=0A= +*/=0A= +#define DRAM_BNK2_BASE 0x01000000=0A= +/*=0A= +** DRAM BANK3 BASE. 4th bank at 24MB:=0A= +*/=0A= +#define DRAM_BNK3_BASE 0x01800000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFF800000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 2 Mask=0A= +*/=0A= +#define DRAM_BNK2_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 3 Mask=0A= +*/=0A= +#define DRAM_BNK3_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +#define SDRAM_CR_BS 0xB95500FF /* 11:18:99 0xBAF800FF */=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +#define SDRAM_DS_BS 0x395500FF /* 11:18:99 0x3AF800FF */=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +#define SDRAM_PC_VAL 0xB95501A0 /* 11:18:99 0xBAF801A0 */=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +#define SDRAM_RFRSH_CMD 0xB9550090 /* 11:18:99 0xBAF80090 */=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +#define SDRAM_MODE_REG 0xB9550080 /* 11:18:99 0xBAF80080 */=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x000002A0=0A= +=0A= +#if MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +** at 32MB:=0A= +*/=0A= +#define MBA_REG1 0x04000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +#endif /* MEMCFG =3D=3D SDRAM_N_SRAM */=0A= +=0A= +#elif DRAMSZ =3D=3D MB32SO=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 32MB SODIMM section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 0MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x03000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 8MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x02000000=0A= +/*=0A= +** DRAM BANK2 BASE. 3rd bank at 16MB:=0A= +*/=0A= +#define DRAM_BNK2_BASE 0x01000000=0A= +/*=0A= +** DRAM BANK3 BASE. 4th bank at 24MB:=0A= +*/=0A= +#define DRAM_BNK3_BASE 0x00000000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFF000000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 2 Mask=0A= +*/=0A= +#define DRAM_BNK2_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 3 Mask=0A= +*/=0A= +#define DRAM_BNK3_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +/*#define SDRAM_CR_BS 0x8E78C0FF */ /* 11:18:99 0xBAF800FF */=0A= +#define SDRAM_CR_BS 0x895580FF=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +/* #define SDRAM_DS_BS 0x0E78C0FF*/ /* 11:18:99 0x3AF800FF */=0A= +#define SDRAM_DS_BS 0x095580FF=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +/* #define SDRAM_PC_VAL 0x8E78C0A0*/ /* 11:18:99 0xBAF801A0 */=0A= +#define SDRAM_PC_VAL 0x895580A0=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +/* #define SDRAM_RFRSH_CMD 0x8E78C090*/ /* 11:18:99 0xBAF80090 */=0A= +#define SDRAM_RFRSH_CMD 0x89558090=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +/*#define SDRAM_MODE_REG 0x8E78C080*/ /* 11:18:99 0xBAF80080 */=0A= +#define SDRAM_MODE_REG 0x89558080=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x000002A0=0A= +=0A= +#if MEMCFG =3D=3D SDRAM_N_SRAM=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +** at 32MB:=0A= +*/=0A= +#define MBA_REG1 0x04000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +#endif /* MEMCFG =3D=3D SDRAM_N_SRAM */=0A= +=0A= +#endif /* DRAMSZ =3D=3D MB32SO */=0A= +=0A= +#elif MEMCFG =3D=3D EDO_ONLY || MEMCFG =3D=3D EDO_N_SRAM=0A= +/*=0A= +*****************************************=0A= +** EDO only section or EDO_N_SRAM section=0A= +*****************************************=0A= +*/=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 0MB=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x00000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 16MB=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x01000000=0A= +/*=0A= +** DRAM BANK2 BASE. 3rd bank at 32MB:=0A= +*/=0A= +#define DRAM_BNK2_BASE 0x02000000=0A= +/*=0A= +** DRAM BANK3 BASE. 4th bank at 48MB:=0A= +*/=0A= +#define DRAM_BNK3_BASE 0x03000000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFF000000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 2 Mask=0A= +*/=0A= +#define DRAM_BNK2_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 3 Mask=0A= +*/=0A= +#define DRAM_BNK3_MASK DRAM_BNK0_MASK=0A= +=0A= +/*=0A= +** EDO control register bit settings=0A= +*/=0A= +=0A= +#define EDO_CR_BS 0x80000BA8 /* 0x80000E02 */=0A= +=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x000000A0=0A= +=0A= +/*=0A= +** EDO control register bit settings=0A= +*/=0A= +=0A= +#define EDO_CR_BS 0x80000BA8 /* 0x80000E02 */=0A= +=0A= +#if MEMCFG =3D=3D EDO_N_SRAM=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +** at 64MB:=0A= +*/=0A= +#define MBA_REG1 0x04000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +#endif /* MEMCFG =3D=3D EDO_N_SRAM */=0A= +=0A= +#elif MEMCFG =3D=3D SRAM_N_SDRAM=0A= +=0A= +#define APATTERN 0xa5a5a5a5=0A= +=0A= +/*=0A= +*******************************=0A= +** SRAM and SDRAM section=0A= +*******************************=0A= +*/=0A= +#if DRAMSZ =3D=3D MB128=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 128MB section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +*/=0A= +#define MBA_REG1 0x00000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 32MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x02000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 64MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x04000000=0A= +/*=0A= +** DRAM BANK2 BASE. 3rd bank at 96MB:=0A= +*/=0A= +#define DRAM_BNK2_BASE 0x06000000=0A= +/*=0A= +** DRAM BANK3 BASE. 4th bank at 128MB:=0A= +*/=0A= +#define DRAM_BNK3_BASE 0x08000000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFE000000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 2 Mask=0A= +*/=0A= +#define DRAM_BNK2_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 3 Mask=0A= +*/=0A= +#define DRAM_BNK3_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +#define SDRAM_CR_BS 0xAAF800FF /* old: 0x9EFBOOFF */=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +#define SDRAM_DS_BS 0x2AF800FF=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +#define SDRAM_PC_VAL 0xAAF801A0=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +#define SDRAM_RFRSH_CMD 0xAAF80090=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +#define SDRAM_MODE_REG 0xAAF80080=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x000000A0=0A= +=0A= +#elif DRAMSZ =3D=3D MB32=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 32MB section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +*/=0A= +#define MBA_REG1 0x00000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 8MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x00800000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 16MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x01000000=0A= +/*=0A= +** DRAM BANK2 BASE. 3rd bank at 24MB:=0A= +*/=0A= +#define DRAM_BNK2_BASE 0x01800000=0A= +/*=0A= +** DRAM BANK3 BASE. 4th bank at 64MB:=0A= +*/=0A= +#define DRAM_BNK3_BASE 0x02000000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFF800000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 2 Mask=0A= +*/=0A= +#define DRAM_BNK2_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 3 Mask=0A= +*/=0A= +#define DRAM_BNK3_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +#define SDRAM_CR_BS 0xB95500FF /* 11:18:99 0xBAF800FF */=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +#define SDRAM_DS_BS 0x395500FF /* 11:18:99 0x3AF800FF */=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +#define SDRAM_PC_VAL 0xB95501A0 /* 11:18:99 0xBAF801A0 */=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +#define SDRAM_RFRSH_CMD 0xB9550090 /* 11:18:99 0xBAF80090 */=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +#define SDRAM_MODE_REG 0xB9550080 /* 11:18:99 0xBAF80080 */=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x000001A0 /* 11:18:99 0x000000A0 */=0A= +=0A= +#elif DRAMSZ =3D=3D MB32SO=0A= +/*=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +=3D=3D 32MB section=0A= +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=0A= +*/=0A= +=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +*/=0A= +#define MBA_REG1 0x00000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 8MB:=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x04000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 16MB:=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x03000000=0A= +/*=0A= +** DRAM BANK2 BASE. 3rd bank at 24MB:=0A= +*/=0A= +#define DRAM_BNK2_BASE 0x02000000=0A= +/*=0A= +** DRAM BANK3 BASE. 4th bank at 64MB:=0A= +*/=0A= +#define DRAM_BNK3_BASE 0x01000000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFF000000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 2 Mask=0A= +*/=0A= +#define DRAM_BNK2_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 3 Mask=0A= +*/=0A= +#define DRAM_BNK3_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** SDRAM ENABLE Settings=0A= +*/=0A= +/* #define SDRAM_CR_BS 0x8E78C0FF*/ /* 11:18:99 0xBAF800FF */=0A= +#define SDRAM_CR_BS 0x8955C0FF=0A= +/*=0A= +** SDRAM DISABLE Settings=0A= +*/=0A= +/* #define SDRAM_DS_BS 0x0E78C0FF*/ /* 11:18:99 0x3AF800FF */=0A= +#define SDRAM_DS_BS 0x0955C0FF=0A= +/*=0A= +** Precharge Value=0A= +*/=0A= +/* #define SDRAM_PC_VAL 0x8E78C0A0*/ /* 11:18:99 0xBAF801A0 */=0A= +#define SDRAM_PC_VAL 0x8955C0A0=0A= +/*=0A= +** Refresh Cmd=0A= +*/=0A= +/*#define SDRAM_RFRSH_CMD 0x8E78C090*/ /* 11:18:99 0xBAF80090 */=0A= +#define SDRAM_RFRSH_CMD 0x8955C090=0A= +/*=0A= +** Mode Register=0A= +*/=0A= +/*#define SDRAM_MODE_REG 0x8E78C080*/ /* 11:18:99 0xBAF80080 = */=0A= +#define SDRAM_MODE_REG 0x8955C080=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x000001A0 /* 11:18:99 0x000000A0 */=0A= +=0A= +#else=0A= +#error "unrecognized dram size"=0A= +#endif /* DRAMSZ */=0A= +=0A= +#elif MEMCFG =3D=3D SRAM_N_EDO=0A= +/*=0A= +** physical memory base address register value for Chip Select 1 - = SRAM=0A= +*/=0A= +#define MBA_REG1 0x00000000=0A= +=0A= +/*=0A= +** memory base mask register value for Chip Select 1 - SRAM - 1MB=0A= +*/=0A= +#define MBM_REG1 0xFFF00000=0A= +=0A= +/*=0A= +** DRAM BANK0 BASE. Starting Bank at 16MB=0A= +*/=0A= +#define DRAM_BNK0_BASE 0x01000000=0A= +/*=0A= +** DRAM BANK1 BASE. 2nd bank at 32MB=0A= +*/=0A= +#define DRAM_BNK1_BASE 0x02000000=0A= +/*=0A= +** DRAM BANK2 BASE. 3rd bank at 48MB:=0A= +*/=0A= +#define DRAM_BNK2_BASE 0x03000000=0A= +/*=0A= +** DRAM BANK3 BASE. 4th bank at 64MB:=0A= +*/=0A= +#define DRAM_BNK3_BASE 0x04000000=0A= +/*=0A= +** DRAM Bank 0 Mask=0A= +*/=0A= +#define DRAM_BNK0_MASK 0xFF000000=0A= +/*=0A= +** DRAM Bank 1 Mask=0A= +*/=0A= +#define DRAM_BNK1_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 2 Mask=0A= +*/=0A= +#define DRAM_BNK2_MASK DRAM_BNK0_MASK=0A= +/*=0A= +** DRAM Bank 3 Mask=0A= +*/=0A= +#define DRAM_BNK3_MASK DRAM_BNK0_MASK=0A= +=0A= +/*=0A= +** EDO control register bit settings=0A= +*/=0A= +#define EDO_CR_BS 0x80000BA8 /* 0x80000E02 */=0A= +=0A= +/*=0A= +** Refresh Count Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CNT_BS 0x00000000=0A= +/*=0A= +** Refresh Compare Register Bit Settings=0A= +*/=0A= +#define DRAM_RF_CMPR_BS 0x00000040=0A= +/*=0A= +** Refresh Compare Register Bit Settings for Slow Expiration=0A= +*/=0A= +#define DRAM_RF_CMPR_SE_BS 0x000000A0=0A= +=0A= +#else=0A= +#error "unrecogized memory configuration parameter"=0A= +#endif /* error */=0A= +=0A= +/* parameters for initialising the S134 board EEPROM */=0A= +#define DESTRUCTIVE 1=0A= +#define NONDESTRUCTIVE 0=0A= +=0A= +#endif /* __S334RAM__ */=0A= +=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s364.h = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s364.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/s364.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/s364.h 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,155 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT S334 definitions=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef __S364134__=0A= +#define __S364134__=0A= +/******************************** D E F I N E S = *******************************/=0A= +#ifndef GPIO_BASE=0A= +#ifdef S355=0A= +#define GPIO_BASE PHYS_TO_K1(0x18040000)=0A= +#else=0A= +#define GPIO_BASE PHYS_TO_K1(0x18000600)=0A= +#endif=0A= +#endif=0A= +/*=0A= +** following defines simple and uniform to save and restore context=0A= +** when enrtering and leaving as assemblu language program when = memory=0A= +** and registers are both premiunm.=0A= +*/=0A= +#define SAVE_CNTXT \=0A= + subu sp,64; \=0A= + sw t0,60(sp); \=0A= + sw t1,56(sp); \=0A= + sw t2,52(sp); \=0A= + sw t3,48(sp); \=0A= + sw t4,44(sp); \=0A= + sw t5,40(sp); \=0A= + sw t6,36(sp); \=0A= + sw t7,32(sp); \=0A= + sw t8,28(sp); \=0A= + sw t9,24(sp); \=0A= + sw a0,20(sp); \=0A= + sw a1,16(sp); \=0A= + sw a2,12(sp); \=0A= + sw a3,8(sp); \=0A= + sw ra,4(sp)=0A= +=0A= +#define RSTR_CNTXT \=0A= + lw t0,60(sp); \=0A= + lw t1,56(sp); \=0A= + lw t2,52(sp); \=0A= + lw t3,48(sp); \=0A= + lw t4,44(sp); \=0A= + lw t5,40(sp); \=0A= + lw t6,36(sp); \=0A= + lw t7,32(sp); \=0A= + lw t8,28(sp); \=0A= + lw t9,24(sp); \=0A= + lw a0,20(sp); \=0A= + lw a1,16(sp); \=0A= + lw a2,12(sp); \=0A= + lw a3,8(sp); \=0A= + lw ra,4(sp); \=0A= + add sp,64=0A= +=0A= +/*=0A= +** Following define is to specify a maximum value for a software=0A= +** busy wait counter.=0A= +*/=0A= +=0A= +#define LP_CNT_100NS 1000 /* set this based on processor speed = */=0A= +#define LP_CNT_3S 1000000 /* set this based on processor speed = */=0A= +=0A= +/*=0A= +** Following are other common timer definitions.=0A= +*/=0A= +#ifdef S355=0A= +#define TIMER_BASE PHYS_TO_K1(0x18028000) =0A= +#define TIMEOUT_COUNT 0x00000FFF=0A= +#else=0A= +#define TIMER_BASE PHYS_TO_K1(0x18000700) =0A= +#endif=0A= +#define ENABLE_TIMER 0x1=0A= +#define DISABLE_TIMER 0x0=0A= +#define BIG_VALUE 0xFFFFFFFF=0A= +=0A= +#ifdef S355=0A= +/* There is no DISPLAY on 355 boards*/=0A= +#elif defined(S334)=0A= +/*=0A= +** following few lines define a macro DISPLAY=0A= +** which is used to write a set of 4 characters=0A= +** onto the S334 LED.=0A= +*/=0A= +=0A= +#if defined(EB332)=0A= +#define LED_BASE PHYS_TO_K1(0x10000000)=0A= +#define LED_DIGIT0 0xc=0A= +#define LED_DIGIT1 0x8=0A= +#define LED_DIGIT2 0x4=0A= +#define LED_DIGIT3 0x0=0A= +=0A= +#define LED_CLEAR 0x400=0A= +=0A= +#else=0A= +#define LED_BASE PHYS_TO_K1(0x14000000)=0A= +#define LED_DIGIT0 0xf=0A= +#define LED_DIGIT1 0xb=0A= +#define LED_DIGIT2 0x7=0A= +#define LED_DIGIT3 0x3=0A= +=0A= +#define LED_CLEAR 0x400=0A= +=0A= +#endif=0A= +=0A= +#define DISPLAY(d0, d1, d2, d3) \=0A= + li t6, LED_BASE ;\=0A= + lb t7, LED_CLEAR(t6) ;\=0A= + nop ;\=0A= + li t7, (d0) & 0xff ;\=0A= + sb t7, LED_DIGIT0(t6) ;\=0A= + li t7, (d1) & 0xff ;\=0A= + sb t7, LED_DIGIT1(t6) ;\=0A= + li t7, (d2) & 0xff ;\=0A= + sb t7, LED_DIGIT2(t6) ;\=0A= + li t7, (d3) & 0xff ;\=0A= + sb t7, LED_DIGIT3(t6)=0A= +=0A= +#define LEDCLEAR() \=0A= + li t6, LED_BASE ;\=0A= + lb t7, LED_CLEAR(t6) ;\=0A= + nop=0A= +=0A= +#endif=0A= +=0A= +#define DESTRUCTIVE 1=0A= +#define NONDESTRUCTIVE 0=0A= +=0A= +#endif=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/uart16550.c = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/uart16550.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/uart16550.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/uart16550.c = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,178 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * UART code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +=0A= +#define RC32334_REG_BASE 0xb8000000=0A= +#ifdef __MIPSEB__=0A= +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)=0A= +#else=0A= +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)=0A= +#endif=0A= +=0A= +#define BASE RC32300_UART0_BASE=0A= +=0A= +#define MAX_BAUD (CONFIG_IDT_BOARD_FREQ / 16)=0A= +#define REG_OFFSET 0x4=0A= +=0A= +/* =3D=3D=3D CONFIG =3D=3D=3D */=0A= +=0A= +/*=0A= + * #define BASE 0xb2001000=0A= + * #define MAX_BAUD 1152000=0A= + * #define REG_OFFSET 0x10=0A= + */=0A= +#if (!defined(BASE) || !defined(MAX_BAUD) || !defined(REG_OFFSET))=0A= +#error You must define BASE, MAX_BAUD and REG_OFFSET in the = Makefile.=0A= +#endif=0A= +=0A= +#ifndef INIT_SERIAL_PORT=0A= +#define INIT_SERIAL_PORT 1=0A= +#endif=0A= +=0A= +#ifndef DEFAULT_BAUD=0A= +//#define DEFAULT_BAUD UART16550_BAUD_115200=0A= +#define DEFAULT_BAUD UART16550_BAUD_9600=0A= +#endif=0A= +#ifndef DEFAULT_PARITY=0A= +#define DEFAULT_PARITY UART16550_PARITY_NONE=0A= +#endif=0A= +#ifndef DEFAULT_DATA=0A= +#define DEFAULT_DATA UART16550_DATA_8BIT=0A= +#endif=0A= +#ifndef DEFAULT_STOP=0A= +#define DEFAULT_STOP UART16550_STOP_1BIT=0A= +#endif=0A= +=0A= +/* =3D=3D=3D END OF CONFIG =3D=3D=3D */=0A= +=0A= +typedef unsigned char uint8;=0A= +typedef unsigned int uint32;=0A= +=0A= +#define UART16550_BAUD_2400 2400=0A= +#define UART16550_BAUD_4800 4800=0A= +#define UART16550_BAUD_9600 9600=0A= +#define UART16550_BAUD_19200 19200=0A= +#define UART16550_BAUD_38400 38400=0A= +#define UART16550_BAUD_57600 57600=0A= +#define UART16550_BAUD_115200 115200=0A= +=0A= +#define UART16550_PARITY_NONE 0=0A= +#define UART16550_PARITY_ODD 0x08=0A= +#define UART16550_PARITY_EVEN 0x18=0A= +#define UART16550_PARITY_MARK 0x28=0A= +#define UART16550_PARITY_SPACE 0x38=0A= +=0A= +#define UART16550_DATA_5BIT 0x0=0A= +#define UART16550_DATA_6BIT 0x1=0A= +#define UART16550_DATA_7BIT 0x2=0A= +#define UART16550_DATA_8BIT 0x3=0A= +=0A= +#define UART16550_STOP_1BIT 0x0=0A= +#define UART16550_STOP_2BIT 0x4=0A= +=0A= +/* register offset */=0A= +#define OFS_RCV_BUFFER (0*REG_OFFSET)=0A= +#define OFS_TRANS_HOLD (0*REG_OFFSET)=0A= +#define OFS_SEND_BUFFER (0*REG_OFFSET)=0A= +#define OFS_INTR_ENABLE (1*REG_OFFSET)=0A= +#define OFS_INTR_ID (2*REG_OFFSET)=0A= +#define OFS_DATA_FORMAT (3*REG_OFFSET)=0A= +#define OFS_LINE_CONTROL (3*REG_OFFSET)=0A= +#define OFS_MODEM_CONTROL (4*REG_OFFSET)=0A= +#define OFS_RS232_OUTPUT (4*REG_OFFSET)=0A= +#define OFS_LINE_STATUS (5*REG_OFFSET)=0A= +#define OFS_MODEM_STATUS (6*REG_OFFSET)=0A= +#define OFS_RS232_INPUT (6*REG_OFFSET)=0A= +#define OFS_SCRATCH_PAD (7*REG_OFFSET)=0A= +=0A= +#define OFS_DIVISOR_LSB (0*REG_OFFSET)=0A= +#define OFS_DIVISOR_MSB (1*REG_OFFSET)=0A= +=0A= +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))=0A= +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) =3D = z)=0A= +=0A= +static void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 = stop)=0A= +{=0A= + /* disable interrupts */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x0);=0A= + UART16550_WRITE(OFS_INTR_ENABLE, 0);=0A= +=0A= + /* set up baud rate */=0A= + {=0A= + uint32 divisor;=0A= +=0A= + /* set DIAB bit */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x80);=0A= +=0A= + /* set divisor */=0A= + divisor =3D MAX_BAUD / baud;=0A= + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);=0A= + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);=0A= +=0A= + /* clear DIAB bit */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x0);=0A= + }=0A= +=0A= + /* set data format */=0A= + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);=0A= +}=0A= +=0A= +=0A= +void=0A= +putc_init(void)=0A= +{=0A= +#if INIT_SERIAL_PORT=0A= + Uart16550Init(DEFAULT_BAUD, DEFAULT_DATA, DEFAULT_PARITY, = DEFAULT_STOP);=0A= +#endif=0A= +}=0A= +=0A= +void=0A= +putc(unsigned char c)=0A= +{=0A= + while ((UART16550_READ(OFS_LINE_STATUS) &0x20) =3D=3D 0);=0A= + UART16550_WRITE(OFS_SEND_BUFFER, c);=0A= +}=0A= +=0A= +#if 0=0A= +unsigned char=0A= +getc(void)=0A= +{=0A= + while((UART16550_READ(OFS_LINE_STATUS) & 0x1) =3D=3D 0);=0A= + return UART16550_READ(OFS_RCV_BUFFER);=0A= +}=0A= +=0A= +int=0A= +tstc(void)=0A= +{=0A= + return((UART16550_READ(OFS_LINE_STATUS) & 0x01) !=3D 0);=0A= +}=0A= +#endif=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/zImage.lds = idtlinux/arch/mips/idt-boards/rc32300/S334/boot/zImage.lds=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/boot/zImage.lds = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/boot/zImage.lds = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D 0x80800000;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32300/S334/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D 0x800A0000;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/idtIRQ.S = idtlinux/arch/mips/idt-boards/rc32300/S334/idtIRQ.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/idtIRQ.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/idtIRQ.S 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,68 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Interrupt dispatcher code for IDT boards=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= + =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= + .text=0A= + .set noreorder=0A= + .set noat=0A= + .align 5=0A= + NESTED(rc32300_IRQ, PT_SIZE, sp)=0A= + SAVE_ALL=0A= + CLI=0A= +=0A= + .set at=0A= + .set noreorder=0A= +=0A= + mfc0 t0, CP0_CAUSE=0A= + move a1, sp=0A= + =0A= + /* check for r4k counter/timer IRQ. */=0A= + =0A= + andi t1, t0, CAUSEF_IP7=0A= + beqz t1, 1f=0A= + nop=0A= +=0A= + jal idt_timer_interrupt=0A= + li a0, 7=0A= + j ret_from_irq=0A= + nop=0A= +1:=0A= + jal rc32300_irqdispatch=0A= + move a0, t0=0A= + j ret_from_irq=0A= + nop=0A= +=0A= + END(rc32300_IRQ)=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/irq.c = idtlinux/arch/mips/idt-boards/rc32300/S334/irq.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/irq.c 1969-12-31 = 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/irq.c 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,429 @@=0A= +/*=0A= + * BRIEF MODULE DESCRIPTION=0A= + * RC32334 interrupt routines.=0A= + *=0A= + * Copyright 2001 MontaVista Software Inc.=0A= + * Author: MontaVista Software, Inc.=0A= + * stevel@mvista.com or source@mvista.com=0A= + *=0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or (at = your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + */=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +=0A= +#undef DEBUG_IRQ=0A= +//#define DEBUG_IRQ=0A= +#ifdef DEBUG_IRQ=0A= +/* note: prints function name for you */=0A= +#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## = args)=0A= +#else=0A= +#define DPRINTK(fmt, args...)=0A= +#endif=0A= +=0A= +extern asmlinkage void rc32300_IRQ(void);=0A= +=0A= +static unsigned int startup_irq(unsigned int irq);=0A= +static void end_irq(unsigned int irq_nr);=0A= +static void mask_and_ack_irq(unsigned int irq_nr);=0A= +static void rc32300_enable_irq(unsigned int irq_nr);=0A= +static void rc32300_disable_irq(unsigned int irq_nr);=0A= +=0A= +extern void __init init_generic_irq(void);=0A= +=0A= +#ifdef CONFIG_PM=0A= +extern void counter0_irq(int irq, void *dev_id, struct pt_regs = *regs);=0A= +#endif=0A= +=0A= +=0A= +typedef struct {=0A= + int irq_base; /* Base IRQ # of this interrupt group */=0A= + int num_irqs; /* Number of IRQs in this group */=0A= + u32 mask; /* mask of valid bits in pending/mask/clear=0A= + registers */=0A= +} intr_group_t;=0A= +=0A= +static const intr_group_t intr_group[NUM_INTR_GROUPS] =3D {=0A= + { -1, NUM_INTR_GROUPS, 0x00007ffe }, /* Group 0 indicates intrs = in=0A= + groups 1-14 */=0A= + { GROUP1_IRQ_BASE, 1, 0x00000001 }, // bus error intr=0A= + { GROUP2_IRQ_BASE, 12, 0x00000ffb }, // PIO active low intrs=0A= + { GROUP3_IRQ_BASE, 8, 0x000000fb }, // PIO active high intrs=0A= + { GROUP4_IRQ_BASE, 8, 0x000000ff }, // Timer Rollover intrs=0A= + { GROUP5_IRQ_BASE, 3, 0x00000007 }, // UART0 intrs=0A= + { GROUP6_IRQ_BASE, 3, 0x00000007 }, // UART1 intrs=0A= + { GROUP7_IRQ_BASE, 5, 0x0000001f }, // DMA Ch0 intrs=0A= + { GROUP8_IRQ_BASE, 5, 0x0000001f }, // DMA Ch1 intrs=0A= + { GROUP9_IRQ_BASE, 5, 0x0000001f }, // DMA Ch2 intrs=0A= + { GROUP10_IRQ_BASE, 5, 0x0000001f }, // DMA Ch3 intrs=0A= + { GROUP11_IRQ_BASE, 4, 0x0000000f }, // PCI Ctlr error intrs=0A= + { GROUP12_IRQ_BASE, 16, 0x0000ffff }, // PCI Satellite intrs=0A= + { GROUP13_IRQ_BASE, 4, 0x0000000f }, // PCI to CPU mailbox intrs=0A= + { GROUP14_IRQ_BASE, 1, 0x00000001 } // SPI intr=0A= +};=0A= +=0A= +#define READ_PEND(g) \=0A= + rc32300_readl(IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)=0A= +#define WRITE_PEND(g,val) \=0A= + rc32300_writel((val), IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)=0A= +#define READ_MASK(g) \=0A= + rc32300_readl(IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)=0A= +#define WRITE_MASK(g,val) \=0A= + rc32300_writel((val), IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)=0A= +#define READ_CLEAR(g) \=0A= + rc32300_readl(IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)=0A= +#define WRITE_CLEAR(g,val) \=0A= + rc32300_writel((val), IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)=0A= +=0A= +static inline int irq_to_group(unsigned int irq_nr)=0A= +{=0A= + int i;=0A= + for (i=3DNUM_INTR_GROUPS-1; i > 0; i--) {=0A= + if (irq_nr >=3D intr_group[i].irq_base)=0A= + break;=0A= + }=0A= +=0A= + return i;=0A= +}=0A= +=0A= +static inline int ip_to_irq(int ipnum)=0A= +{=0A= + return ipnum;=0A= +}=0A= +=0A= +static inline int irq_to_ip(int irq)=0A= +{=0A= + return (irq < GROUP1_IRQ_BASE) ? irq : 5;=0A= +}=0A= +=0A= +static inline void enable_local_irq(unsigned int irq_nr)=0A= +{=0A= + int ipnum =3D irq_to_ip(irq_nr);=0A= + clear_c0_cause(1 << (ipnum + 8));=0A= + set_c0_status(1 << (ipnum + 8));=0A= +}=0A= +=0A= +static inline void disable_local_irq(unsigned int irq_nr)=0A= +{=0A= + int ipnum =3D irq_to_ip(irq_nr);=0A= + clear_c0_status(1 << (ipnum + 8));=0A= +}=0A= +=0A= +static inline void ack_local_irq(unsigned int irq_nr)=0A= +{=0A= + int ipnum =3D irq_to_ip(irq_nr);=0A= + clear_c0_cause(1 << (ipnum + 8));=0A= +}=0A= +=0A= +static void enable_exp_irq(unsigned int irq_nr, int group)=0A= +{=0A= + const intr_group_t* g =3D &intr_group[group];=0A= + u32 mask, intr_bit;=0A= + =0A= + // calc interrupt bit within group=0A= + intr_bit =3D (1 << (irq_nr - g->irq_base)) & g->mask;=0A= +=0A= + if (!intr_bit)=0A= + return;=0A= + =0A= + DPRINTK("irq %d (group %d, mask %d)\n",=0A= + irq_nr, group, intr_bit);=0A= + =0A= + // first enable IP5 (IRQ3)=0A= + clear_c0_cause(1 << (5 + 8));=0A= + set_c0_status(1 << (5 + 8));=0A= + =0A= + // Clear the pending bit for the group=0A= + WRITE_CLEAR(0, (1 << group));=0A= + =0A= + // unmask appropriate group bit in group 0=0A= + mask =3D READ_MASK(0);=0A= +=0A= + WRITE_MASK(0, mask | (1 << group));=0A= +=0A= + // Clear the pending bit within the group=0A= + WRITE_CLEAR(group, intr_bit);=0A= +=0A= + // unmask intr within group=0A= + mask =3D READ_MASK(group) & g->mask;=0A= +=0A= + WRITE_MASK(group, mask | intr_bit);=0A= +=0A= +}=0A= +=0A= +static void disable_exp_irq(unsigned int irq_nr, int group)=0A= +{=0A= + const intr_group_t* g =3D &intr_group[group];=0A= + u32 mask, intr_bit;=0A= + =0A= + // calc interrupt bit within group=0A= + intr_bit =3D (1 << (irq_nr - g->irq_base)) & g->mask;=0A= + if (!intr_bit)=0A= + return;=0A= + =0A= + DPRINTK("irq%d (group %d, mask %d)\n",=0A= + irq_nr, group, intr_bit);=0A= + =0A= + // mask intr within group=0A= + mask =3D READ_MASK(group) & g->mask;=0A= + mask &=3D ~intr_bit; // mask the intr bit=0A= + WRITE_MASK(group, mask);=0A= + =0A= + /*=0A= + if there are no more interrupts enabled in this=0A= + group, mask appropriate group bit in group 0=0A= + */=0A= + if (!mask) {=0A= + mask =3D READ_MASK(0);=0A= + WRITE_MASK(0, mask & ~(1 << group));=0A= + }=0A= +}=0A= +=0A= +static void ack_exp_irq(unsigned int irq_nr, int group)=0A= +{=0A= + const intr_group_t* g =3D &intr_group[group];=0A= + u32 intr_bit;=0A= + =0A= + // calc interrupt bit within group=0A= + intr_bit =3D (1 << (irq_nr - g->irq_base)) & g->mask;=0A= + if (intr_bit) {=0A= + // clear intr within group=0A= + WRITE_CLEAR(group, intr_bit);=0A= + }=0A= + =0A= + /*=0A= + if there are no more interrupts pending in this=0A= + group, clear appropriate group pending bit in group 0=0A= + */=0A= + if (!(READ_PEND(group) & g->mask)) {=0A= + WRITE_CLEAR(0, 1 << group);=0A= + }=0A= +}=0A= +=0A= +=0A= +static void rc32300_enable_irq(unsigned int irq_nr)=0A= +{=0A= + unsigned long flags;=0A= + local_irq_save(flags);=0A= +=0A= + if (irq_nr < GROUP1_IRQ_BASE)=0A= + enable_local_irq(irq_nr);=0A= + else {=0A= + int group =3D irq_to_group(irq_nr);=0A= + enable_exp_irq(irq_nr, group);=0A= + }=0A= +=0A= + local_irq_restore(flags);=0A= +}=0A= +=0A= +=0A= +static void rc32300_disable_irq(unsigned int irq_nr)=0A= +{=0A= + unsigned long flags;=0A= + local_irq_save(flags);=0A= +=0A= + if (irq_nr < GROUP1_IRQ_BASE)=0A= + disable_local_irq(irq_nr);=0A= + else {=0A= + int group =3D irq_to_group(irq_nr);=0A= + disable_exp_irq(irq_nr, group);=0A= + }=0A= + =0A= + local_irq_restore(flags);=0A= +}=0A= +=0A= +=0A= +void rc32300_ack_irq(unsigned int irq_nr)=0A= +{=0A= + if (irq_nr < GROUP1_IRQ_BASE) {=0A= + ack_local_irq(irq_nr);=0A= + } else {=0A= + int group =3D irq_to_group(irq_nr);=0A= + ack_exp_irq(irq_nr, group);=0A= + }=0A= +}=0A= +=0A= +static unsigned int startup_irq(unsigned int irq_nr)=0A= +{=0A= + rc32300_enable_irq(irq_nr);=0A= + return 0; =0A= +}=0A= +=0A= +=0A= +static void shutdown_irq(unsigned int irq_nr)=0A= +{=0A= + rc32300_disable_irq(irq_nr);=0A= + return;=0A= +}=0A= +=0A= +=0A= +static void mask_and_ack_irq(unsigned int irq_nr)=0A= +{=0A= + unsigned long flags;=0A= + =0A= + local_irq_save(flags);=0A= + if (irq_nr < GROUP1_IRQ_BASE) {=0A= + disable_local_irq(irq_nr);=0A= + ack_local_irq(irq_nr);=0A= + } else {=0A= + int group =3D irq_to_group(irq_nr);=0A= + disable_exp_irq(irq_nr, group);=0A= + ack_exp_irq(irq_nr, group);=0A= + }=0A= + local_irq_restore(flags);=0A= + =0A= +}=0A= +=0A= +static void end_irq(unsigned int irq_nr)=0A= +{=0A= + unsigned long flags;=0A= +=0A= + local_irq_save(flags);=0A= + if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {=0A= + if (irq_nr < GROUP1_IRQ_BASE) {=0A= + ack_local_irq(irq_nr);=0A= + enable_local_irq(irq_nr);=0A= + } else {=0A= + int group =3D irq_to_group(irq_nr);=0A= + ack_exp_irq(irq_nr, group);=0A= + enable_exp_irq(irq_nr, group);=0A= + }=0A= + } else {=0A= + printk("warning: end_irq %d did not enable (%x)\n", =0A= + irq_nr, irq_desc[irq_nr].status);=0A= + }=0A= + local_irq_restore(flags);=0A= +}=0A= +=0A= +static struct hw_interrupt_type rc32300_irq_type =3D {=0A= + "RC32334",=0A= + startup_irq,=0A= + shutdown_irq,=0A= + rc32300_enable_irq,=0A= + rc32300_disable_irq,=0A= + mask_and_ack_irq,=0A= + end_irq,=0A= + NULL=0A= +};=0A= +=0A= +=0A= +void __init arch_init_irq(void)=0A= +{=0A= + int i;=0A= + unsigned long cp0_status;=0A= +=0A= + printk("Initializing IRQ's: %d\n", RC32334_NR_IRQS);=0A= +=0A= + cp0_status =3D read_c0_status();=0A= + memset(irq_desc, 0, sizeof(irq_desc));=0A= + set_except_vector(0, rc32300_IRQ);=0A= +=0A= + for (i =3D 0; i < RC32334_NR_IRQS; i++) {=0A= + irq_desc[i].status =3D IRQ_DISABLED;=0A= + irq_desc[i].action =3D NULL;=0A= + irq_desc[i].depth =3D 1;=0A= + irq_desc[i].handler =3D &rc32300_irq_type;=0A= + spin_lock_init(&irq_desc[i].lock);=0A= + }=0A= +}=0A= +=0A= +/*=0A= + * Interrupts are nested. Even if an interrupt handler is = registered=0A= + * as "fast", we might get another interrupt before we return from=0A= + * *_dispatch().=0A= + */=0A= +=0A= +/* Dispatch to expanded interrupts */=0A= +static void int3_dispatch(struct pt_regs *regs)=0A= +{=0A= + int group, intr;=0A= + const intr_group_t* g;=0A= + u32 pend, group0_pend;=0A= +=0A= + group0_pend =3D READ_PEND(0) & intr_group[0].mask;=0A= + group0_pend &=3D READ_MASK(0); // only unmasked groups=0A= + if (!group0_pend)=0A= + return; // no interrupts in any group!=0A= +=0A= + group =3D 31 - rc32300_clz(group0_pend);=0A= + // group i has pending interrupts=0A= + g =3D &intr_group[group];=0A= + pend =3D READ_PEND(group) & g->mask;=0A= + pend &=3D READ_MASK(group); // only unmasked interrupts=0A= +=0A= + if (!pend)=0A= + return; // no interrupts in this group ???=0A= + =0A= + intr =3D 31 - rc32300_clz(pend);=0A= +#ifdef DEBUG_IRQ=0A= + idtprintf("%02d%02d", group, intr);=0A= +#endif=0A= + do_IRQ(g->irq_base + intr, regs);=0A= +}=0A= +=0A= +static void mips_spurious_interrupt(struct pt_regs *regs)=0A= +{=0A= +#if 0=0A= + return;=0A= +#else=0A= + printk("got spurious interrupt\n");=0A= +#endif=0A= +}=0A= +=0A= +/* Main Interrupt dispatcher */=0A= +void rc32300_irqdispatch(unsigned long cp0_cause, struct pt_regs = *regs)=0A= +{=0A= + unsigned long ip;=0A= + int ipnum;=0A= + =0A= + ip =3D (cp0_cause >> 8) & 0xff;=0A= + =0A= + if (!ip) {=0A= + mips_spurious_interrupt(regs);=0A= + return;=0A= + }=0A= + =0A= + ipnum =3D 31 - rc32300_clz(ip);=0A= + if (ipnum =3D=3D 5) {=0A= + int3_dispatch(regs);=0A= + } else {=0A= + int irq =3D ip_to_irq(ipnum);=0A= + do_IRQ(irq, regs);=0A= + }=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/Makefile = idtlinux/arch/mips/idt-boards/rc32300/S334/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/Makefile 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,42 @@=0A= +#######################################################################= ########=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile for IDT S334A board BSP=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +#=0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +# =0A= +# =0A= +# =0A= +#######################################################################= ########=0A= +=0A= +.S.s:=0A= + $(CPP) $(CFLAGS) $< -o $*.s=0A= +.S.o:=0A= + $(CC) $(CFLAGS) -c $< -o $*.o=0A= +=0A= +obj-y :=3D irq.o setup.o idtIRQ.o reset.o prom.o time.o =0A= +obj-$(CONFIG_KGDB) +=3D serial_gdb.o=0A= +obj-$(CONFIG_SERIAL_8250) +=3D serial.o=0A= +subdir-$(CONFIG_IDT_BOOT_NVRAM) +=3D nvram=0A= +obj-$(CONFIG_IDT_BOOT_NVRAM) +=3D nvram/built-in.o=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/Makefile = idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/Makefile = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,37 @@=0A= +#######################################################################= ########=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile for IDT S334 nvram access routines=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +#=0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +# =0A= +# =0A= +#######################################################################= ########=0A= +=0A= +.S.s: =0A= + $(CPP) $(CFLAGS) $< -o $*.s=0A= +.S.o: =0A= + $(CC) $(CFLAGS) -c $< -o $*.o=0A= +=0A= +=0A= +obj-y :=3D nvram334.o spi.o=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.c = idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.c = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,534 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * nvram interface routines.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + **********************************************************************= ****=0A= + */=0A= +=0A= +#define NVRAM_SPI=0A= +#include =0A= +#include =0A= +#include "nvram334.h"=0A= +=0A= +#if defined(NVRAM_SPI)=0A= +#define WREN 0x0E=0A= +#define WRDI 0x0C=0A= +#define RDSR 0x0D=0A= +#define WRSR 0x09=0A= +#define READ 0x0B=0A= +#define WRITE 0x0A=0A= +=0A= +extern void enable_chipselect_spi(void);=0A= +extern unsigned int send_to_spi(unsigned int);=0A= +extern void disable_chipselect_spi(void);=0A= +=0A= +extern void setenv(char *e, char *v, int rewrite);=0A= +extern char * getenv(char *e);=0A= +extern void unsetenv(char *e);=0A= +extern void mapenv(int (*func)(char *, char *));=0A= +extern void purgeenv(void);=0A= +=0A= +static void NVWR(unsigned int uiAddr, unsigned char ucData) =0A= +{=0A= + unsigned int uiStatus =3D 1;=0A= + =0A= + enable_chipselect_spi();=0A= + send_to_spi((unsigned int)(WREN));=0A= + disable_chipselect_spi();=0A= +=0A= + /* send the Read Status command to AT25256 */=0A= + /* AT25256 EPROM is not ready if LSB=3D1 */=0A= + while (uiStatus & 0x1) {=0A= + enable_chipselect_spi();=0A= + send_to_spi((unsigned int)(RDSR));=0A= + uiStatus =3D send_to_spi(0);=0A= + disable_chipselect_spi();=0A= + }=0A= + /*.........................................................=0A= + send WRITE to SPI (followed by high_addr, low_addr, data)=0A= + .........................................................=0A= + */=0A= + enable_chipselect_spi();=0A= + send_to_spi((unsigned int)(WRITE));=0A= + send_to_spi(uiAddr >> 8); /* offset into EPROM space - high = byte */=0A= + send_to_spi(uiAddr); /* offset into EPROM space - low = byte */=0A= + send_to_spi((unsigned int)(ucData)); /* actual data to write into = EPROM */=0A= + disable_chipselect_spi();=0A= +=0A= + /* send the Read Status command to AT25256 */=0A= + /* AT25256 EPROM is not ready if LSB=3D1 */=0A= + uiStatus =3D 1;=0A= + while (uiStatus & 0x1) {=0A= + enable_chipselect_spi();=0A= + send_to_spi((unsigned int)(RDSR));=0A= + uiStatus =3D send_to_spi(0);=0A= + disable_chipselect_spi();=0A= + }=0A= +}=0A= +=0A= +unsigned char=0A= +NVRD(unsigned int uiAddr) =0A= +{=0A= + unsigned char ret;=0A= + unsigned int uiStatus =3D 1;=0A= + =0A= + /* send the Read Status command to AT25256 */=0A= + /* AT25256 EPROM is not ready if LSB=3D1 */=0A= + while (uiStatus & 0x1) {=0A= + enable_chipselect_spi();=0A= + send_to_spi((unsigned int)(RDSR));=0A= + uiStatus =3D send_to_spi(0);=0A= + disable_chipselect_spi();=0A= + }=0A= + /*.........................................................=0A= + send READ to SPI (followed by high_addr, low_addr)=0A= + .........................................................=0A= + */ =0A= + enable_chipselect_spi(); =0A= + send_to_spi((unsigned int)(READ));=0A= + send_to_spi(uiAddr >> 8); /* offset into EPROM space - high byte = */=0A= + send_to_spi(uiAddr); /* offset into EPROM space - low byte = */=0A= + ret =3D send_to_spi(0); /* dummy write returns data from EPROM, = save it*/=0A= + disable_chipselect_spi();=0A= + return(ret);=0A= +}=0A= +#else=0A= +unsigned char=0A= +NVRD(unsigned int x)=0A= +{=0A= + unsigned char nv_data;=0A= +=0A= + nv_data =3D (unsigned char)(*(((unsigned char*)(NVRAM_BASE))+ = x));=0A= + return(nv_data);=0A= +}=0A= +=0A= +void =0A= +NVWR(unsigned int x , unsigned char v)=0A= +{=0A= + int i =3D 0;=0A= + =0A= + *(((unsigned char*)(NVRAM_BASE)) + x) =3D v;=0A= +=0A= + while (++i < 0x1000) ;=0A= +}=0A= +#endif=0A= +=0A= +/*=0A= + * The *env routines provide wrappers to the nvram_*env=0A= + * routines to allow any special processing of the environment=0A= + * to be carried out=0A= + * Yes this is a bit naff=0A= + */=0A= +=0A= +unsigned char=0A= +nvram_getbyte(int offs)=0A= +{=0A= + return(NVRD(offs));=0A= +}=0A= +=0A= +void=0A= +nvram_setbyte(int offs, unsigned char val)=0A= +{=0A= + NVWR(offs, val);=0A= +}=0A= +=0A= +/*=0A= + * BigEndian!=0A= + */=0A= +unsigned short=0A= +nvram_getshort(int offs)=0A= +{=0A= + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));=0A= +}=0A= +=0A= +void=0A= +nvram_setshort(int offs, unsigned short val)=0A= +{=0A= + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));=0A= + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));=0A= +}=0A= +=0A= +unsigned int=0A= +nvram_getint(int offs)=0A= +{=0A= + unsigned int val;=0A= + val =3D nvram_getbyte(offs) << 24;=0A= + val |=3D nvram_getbyte(offs + 1) << 16;=0A= + val |=3D nvram_getbyte(offs + 2) << 8;=0A= + val |=3D nvram_getbyte(offs + 3);=0A= + return (val);=0A= +}=0A= +=0A= +void=0A= +nvram_setint(int offs, unsigned int val)=0A= +{=0A= + nvram_setbyte(offs, val >> 24);=0A= + nvram_setbyte(offs + 1, val >> 16);=0A= + nvram_setbyte(offs + 2, val >> 8);=0A= + nvram_setbyte(offs + 3, val);=0A= +}=0A= +=0A= +/*=0A= + * calculate NVRAM checksum=0A= + */=0A= +static unsigned short=0A= +nvram_calcsum (void)=0A= +{=0A= + unsigned short sum =3D NV_MAGIC;=0A= + int i;=0A= +=0A= + for (i =3D ENV_BASE; i < ENV_TOP; i +=3D 2)=0A= + sum +=3D nvram_getshort(i);=0A= + return(sum);=0A= +}=0A= +=0A= +/*=0A= + * update the nvram checksum=0A= + */=0A= +static void=0A= +nvram_updatesum (void)=0A= +{=0A= + nvram_setshort(NVOFF_CSUM, nvram_calcsum());=0A= +#if !defined(NVRAM_SPI)=0A= + eeprom_write_s334();=0A= +#endif=0A= +}=0A= +=0A= +/*=0A= + * test validity of nvram by checksumming it=0A= + */=0A= +static int=0A= +nvram_isvalid(void)=0A= +{=0A= + static unsigned int is_valid;=0A= + unsigned short sum =3D NV_MAGIC;=0A= +=0A= + if (is_valid)=0A= + return 1;=0A= +=0A= +#if !defined(NVRAM_SPI)=0A= + eeprom_read_s334();=0A= +#endif=0A= + if (nvram_getshort(NVOFF_MAGIC) !=3D NV_MAGIC)=0A= + return (0);=0A= + sum =3D nvram_calcsum ();=0A= + nvram_setshort(NVOFF_CSUM,sum);=0A= +=0A= + is_valid =3D 1;=0A= + return(1);=0A= +}=0A= +=0A= +/* return nvram address of environment string */=0A= +static int=0A= +nvram_matchenv(char *s)=0A= +{=0A= + int envsize, envp, n, i, varsize;=0A= + char *var;=0A= +=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + if (envsize > ENV_AVAIL)=0A= + return (0); /* sanity */=0A= + envp =3D ENV_BASE;=0A= +=0A= + if ((n =3D strlen (s)) > 255)=0A= + return (0);=0A= + while (envsize > 0) {=0A= + varsize =3D NVRD(envp);=0A= + if (varsize =3D=3D 0 || (envp + varsize) > ENV_TOP)=0A= + return (0); /* sanity */=0A= + for (i =3D envp + 1, var =3D s; i <=3D envp + n; i++, var++) {=0A= + char c1 =3D NVRD(i);=0A= + char c2 =3D *var;=0A= + if (islower (c1))=0A= + c1 =3D toupper (c1);=0A= + if (islower (c2))=0A= + c2 =3D toupper (c2);=0A= + if (c1 !=3D c2)=0A= + break;=0A= + }=0A= + if (i > envp + n) { /* match so far */=0A= + if (n =3D=3D varsize - 1) /* match on boolean */=0A= + return(envp);=0A= + if (NVRD(i) =3D=3D '=3D') /* exact match on variable */=0A= + return(envp);=0A= + }=0A= + envsize -=3D varsize;=0A= + envp +=3D varsize;=0A= + }=0A= + return(0);=0A= +}=0A= +=0A= +void=0A= +nvram_initenv(void)=0A= +{=0A= + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);=0A= + nvram_setshort(NVOFF_ENVSIZE, 0);=0A= + nvram_updatesum();=0A= +}=0A= +=0A= +static void=0A= +nvram_delenv(char *s)=0A= +{=0A= + int nenvp, envp, envsize, nbytes;=0A= +=0A= + envp =3D nvram_matchenv(s);=0A= + if (envp =3D=3D 0)=0A= + return;=0A= + nenvp =3D envp + NVRD(envp);=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + nbytes =3D envsize - (nenvp - ENV_BASE);=0A= + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));=0A= + while (nbytes--) {=0A= + NVWR (envp, NVRD(nenvp));=0A= + envp++;=0A= + nenvp++;=0A= + }=0A= +=0A= + nvram_updatesum();=0A= +}=0A= +=0A= +=0A= +static int=0A= +nvram_setenv(char *s, char *v)=0A= +{=0A= + int ns, nv, total;=0A= + int envp;=0A= +=0A= + if (!nvram_isvalid())=0A= + return (-1);=0A= +=0A= + nvram_delenv(s);=0A= + ns =3D strlen(s);=0A= + if (ns =3D=3D 0)=0A= + return(-1);=0A= + if (v && *v) {=0A= + nv =3D strlen(v);=0A= + total =3D ns + nv + 2;=0A= + }=0A= + else {=0A= + nv =3D 0;=0A= + total =3D ns + 1;=0A= + }=0A= + if (total > 255 || total > ENV_AVAIL - = nvram_getshort(NVOFF_ENVSIZE))=0A= + return(-1);=0A= + envp =3D ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);=0A= + NVWR(envp, (unsigned char) total); envp++;=0A= + while (ns--) {=0A= + NVWR(envp, *s); envp++; s++;=0A= + }=0A= + if (nv) {=0A= + NVWR(envp, '=3D'); envp++;=0A= + while (nv--) {=0A= + NVWR(envp, *v); envp++; v++;=0A= + }=0A= + }=0A= + nvram_setshort(NVOFF_ENVSIZE, envp - ENV_BASE);=0A= + nvram_updatesum();=0A= + return(0);=0A= +}=0A= +=0A= +char *=0A= +nvram_getenv(char *s)=0A= +{=0A= + static char buf[256]; /* FIXME: this cannot be static */=0A= + int envp, ns, nbytes, i;=0A= +=0A= + if (!nvram_isvalid())=0A= + return((char *)0);=0A= +=0A= + envp =3D nvram_matchenv(s);=0A= + if (envp =3D=3D 0)=0A= + return((char *)0);=0A= + ns =3D strlen(s);=0A= + if (NVRD(envp) =3D=3D ns + 1) /* boolean */=0A= + buf[0] =3D '\0';=0A= + else {=0A= + nbytes =3D NVRD(envp) - (ns + 2);=0A= + envp +=3D ns + 2;=0A= + for (i =3D 0; i < nbytes; i++)=0A= + buf[i] =3D NVRD(envp++);=0A= + buf[i] =3D '\0';=0A= + }=0A= + return (buf);=0A= +}=0A= +=0A= +void=0A= +nvram_unsetenv(char *s)=0A= +{=0A= + if (!nvram_isvalid())=0A= + return;=0A= +=0A= + nvram_delenv(s);=0A= +}=0A= +=0A= +/*=0A= + * apply func to each string in environment=0A= + */=0A= +void=0A= +nvram_mapenv(int (*func)(char *, char *))=0A= +{=0A= + int envsize, envp, n, i, seeneql;=0A= + char name[256], value[256];=0A= + char c, *s;=0A= +=0A= + if (!nvram_isvalid())=0A= + return;=0A= +=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + envp =3D ENV_BASE;=0A= +=0A= + while (envsize > 0) {=0A= + value[0] =3D '\0';=0A= + seeneql =3D 0;=0A= + s =3D name;=0A= + n =3D NVRD(envp);=0A= + for (i =3D envp + 1; i < envp + n; i++) {=0A= + c =3D NVRD(i);=0A= + if ((c =3D=3D '=3D') && !seeneql){=0A= + *s =3D '\0';=0A= + s =3D value;=0A= + seeneql =3D 1;=0A= + continue;=0A= + }=0A= + *s++ =3D c;=0A= + }=0A= + *s =3D '\0';=0A= + (*func)(name, value);=0A= + envsize -=3D n;=0A= + envp +=3D n;=0A= + }=0A= +}=0A= +=0A= +#ifdef DEBUG=0A= +void=0A= +nvram_dumpenv(void)=0A= +{=0A= + int envsize, envp, n, i;=0A= + char *var;=0A= +=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + envp =3D ENV_BASE;=0A= +=0A= + printf ("NVRAM Environment:\n");=0A= + while (envsize) {=0A= + n =3D NVRD(envp);=0A= + for (i =3D envp + 1; i < envp + n; i++)=0A= + consputc (NVRD(i));=0A= + consputc('\n');=0A= + envsize -=3D n;=0A= + envp +=3D n;=0A= + }=0A= + consputc('\n');=0A= +}=0A= +#endif=0A= +=0A= +#if 0=0A= +static unsigned int=0A= +digit(char c)=0A= +{=0A= + if ('0' <=3D c && c <=3D '9')=0A= + return(c - '0');=0A= + if ('A' <=3D c && c <=3D 'Z')=0A= + return(10 + c - 'A');=0A= + if ('a' <=3D c && c <=3D 'z')=0A= + return(10 + c - 'a');=0A= + return(~0);=0A= +}=0A= +#endif=0A= +/*=0A= + * Wrappers to allow 'special' environment variables to get = processed=0A= + */=0A= +void=0A= +setenv(char *e, char *v, int rewrite)=0A= +{=0A= + if (nvram_getenv(e) && !rewrite)=0A= + return;=0A= +=0A= + nvram_setenv(e, v);=0A= +}=0A= +=0A= +char *=0A= +getenv(char *e)=0A= +{=0A= + return(nvram_getenv (e));=0A= +}=0A= +=0A= +void=0A= +unsetenv(char *e)=0A= +{=0A= + nvram_unsetenv(e);=0A= +}=0A= +=0A= +void=0A= +mapenv(int (*func)(char *, char *))=0A= +{=0A= + nvram_mapenv(func);=0A= +}=0A= +=0A= +#if !defined(NVRAM_SPI)=0A= +#define WAIT(x) {int i =3D 0; while(++i < (x)) ; }=0A= +void eeprom_read_s334()=0A= +{=0A= + static IsVirgin;=0A= +=0A= + if (IsVirgin)=0A= + return;=0A= +=0A= + IsVirgin =3D 1;=0A= + NVRD(0x401);=0A= + WAIT(0x1000);=0A= + if (nvram_getshort(NVOFF_MAGIC) !=3D NV_MAGIC)=0A= + nvram_initenv();=0A= +}=0A= +=0A= +void eeprom_write_s334()=0A= +{=0A= + NVWR(0x401, 0x20);=0A= + WAIT(0x8000);=0A= +}=0A= +=0A= +extern void=0A= +purgeenv(void)=0A= +{=0A= + int i;=0A= +=0A= + for (i =3D ENV_BASE; i < ENV_TOP; i++)=0A= + *(((unsigned char*)(NVRAM_BASE)) + i) =3D 0;=0A= + nvram_initenv();=0A= + eeprom_write_s334();=0A= +}=0A= +#else=0A= +extern void=0A= +purgeenv(void)=0A= +{=0A= + int i;=0A= +=0A= + for (i =3D ENV_BASE; i < ENV_TOP; i++)=0A= + NVWR(i, 0);=0A= + nvram_initenv();=0A= +}=0A= +#endif=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.h = idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/nvram334.h = 2006-03-09 16:25:49.000000000 -0800=0A= @@ -0,0 +1,81 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * nvram layout definitions=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + *=0A= + **********************************************************************= ****=0A= + */=0A= +=0A= +#ifndef _NVRAM_=0A= +#define _NVRAM_=0A= +=0A= +#define TD_NVRAM_SIZE 512=0A= +=0A= +#if !defined(NVRAM_SPI)=0A= +#define NVRAM_BASE 0xb2000000=0A= +#define NVRAM_WRITE (NVRAM_BASE + 0x00000400)=0A= +#define NVRAM_READ NVRAM_WRITE=0A= +=0A= +void eeprom_read_s334();=0A= +void eeprom_write_s334();=0A= +#endif=0A= +=0A= +/*=0A= + * defining ALGCOMPAT provides backward compatibility=0A= + * with Algorithmics derived PROM monitors=0A= + */=0A= +#define ALGCOMPAT=0A= +#ifdef ALGCOMPAT=0A= +#define NVOFFSET 0 /* use all of NVRAM */=0A= +#else=0A= +#define NVOFFSET 1024 /* first 1Kb reserved for DECelx */=0A= +#endif=0A= +=0A= +/* Offsets to reserved locations */=0A= + /* size description */=0A= +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */=0A= +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum = */=0A= +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 1 size of 'environment' */=0A= +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */=0A= +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address = */=0A= +#define NVOFF_UNUSED (NVOFFSET + c) /* 0 current end of table */=0A= +=0A= +#define NV_MAGIC 0xdeaf /* nvram magic number */=0A= +#define NV_RESERVED 64 /* number of reserved bytes = */=0A= +=0A= +#ifdef ALGCOMPAT=0A= +/* ho hum... */=0A= +#undef NVOFF_ETHADDR=0A= +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)=0A= +#endif=0A= +=0A= +/* number of bytes available for environment */=0A= +#define ENV_BASE (NVOFFSET + NV_RESERVED)=0A= +#define ENV_TOP TD_NVRAM_SIZE=0A= +#define ENV_AVAIL (ENV_TOP - ENV_BASE)=0A= +=0A= +#endif /* _NVRAM_ */=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/spi.c = idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/spi.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/nvram/spi.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/nvram/spi.c 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,205 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * SPI interface routines.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +=0A= +#define SPI_CNT 0xB8000900=0A= +#define SPI_CNTL 0xB8000904=0A= +#define SPI_STAT 0xB8000908=0A= +#define SPI_DATA 0xB800090C=0A= +=0A= +#define SPI_CNT_DIV 0x00000008=0A= +#define SPI_CNTL_VAL 0x0000007C=0A= +#define SPI_STAT_SPIF 0x00000080=0A= +=0A= +#define GPIO_DAT 0xB8000600=0A= +#define GPIO_DIR 0xB8000604=0A= +#define GPIO_FUN 0xB8000608=0A= +=0A= +#define GPIO_SPI_CS 0x00000200=0A= +=0A= +#define CACHED_DLY 0x00003FFF=0A= +#define UNCACHED_DLY 0x000000FF=0A= +=0A= + /* AT25256 command definitions */=0A= +#define WREN 0x0E=0A= +#define WRDI 0x0C=0A= +#define RDSR 0x0D=0A= +#define WRSR 0x09=0A= +#define READ 0x0B=0A= +#define WRITE 0x0A=0A= +=0A= +extern unsigned int send_to_spi(unsigned int uiData);=0A= +extern void enable_chipselect_spi(void);=0A= +extern void disable_chipselect_spi(void);=0A= +extern void initialize_hardware(void);=0A= +=0A= +static void delay(void);=0A= +/* --------------------------------------------------*/=0A= +static void delay(void)=0A= +{=0A= + int i =3D CACHED_DLY; /* we are running cached, longer count for = delay */=0A= + while (i--);=0A= +}=0A= +=0A= +/* --------------------------------------------------=0A= + Initialize the GPIO registers related to SPI functionality=0A= +*/=0A= +static void initialize_GPIO(void)=0A= +{=0A= + unsigned int uiTempReg;=0A= + volatile unsigned int *uipGpioDir;=0A= + volatile unsigned int *uipGpioFun;=0A= + =0A= + uipGpioDir =3D (volatile unsigned int *)GPIO_DIR;=0A= + uipGpioFun =3D (volatile unsigned int *)GPIO_FUN;=0A= + /* .......... set up PIO Direction Register at = GPIO_BASE+4.........=0A= + PIO[10,9,8,7] are used for SPI.=0A= + However, these correspond to bits 11,10,9,8 in PIO DIR REG=0A= + */=0A= + uiTempReg =3D *uipGpioDir;=0A= + *uipGpioDir =3D ((uiTempReg & 0x0F0FF) | 0x0E00); /* bits 11,10,9 = output(1), 8 input(0) - SPI */=0A= + =0A= + /* ........ set up PIO Effect/Function Select Register at = GPIO_BASE+8=0A= + PIO[10,9,8,7] are used for SPI.=0A= + However, these correspond to bits 11,10,9,8 in PIO EFF/FUN REG=0A= + */=0A= + =0A= + uiTempReg =3D *uipGpioFun;=0A= + *uipGpioFun =3D ((uiTempReg & 0x0F0FF) | 0x0D00); /* spi_ss_n (bit9) = is GPIO (0),rest are special/SPI (1)*/=0A= +}=0A= +=0A= +/* --------------------------------------------------=0A= + */=0A= +extern void disable_chipselect_spi(void)=0A= +{=0A= + /* Write a 1 at chip select*/=0A= + *(volatile unsigned int *)GPIO_DAT |=3D GPIO_SPI_CS;=0A= +}=0A= +=0A= +/*****************************************************************=0A= + * Sends data through SPI interface , returns data read from SPI.=0A= + * Input parameter: data to be sent=0A= + * Return value: data read back from SPI=0A= + * SPI always transfers data in both directions simultaneously.=0A= + * To read back data which is in response to the previous command,=0A= + * do a dummy write to SPI which will read back the data you need.=0A= + * The word "data" is used here in a generic sense, it could = actually=0A= + * be a SPI command written to SPI or status read back from SPI.=0A= + ****************************************************************/=0A= +=0A= +extern unsigned int send_to_spi(unsigned int uiData)=0A= +{=0A= + /* write data */=0A= + delay(); /* let AT25256 do its write for awhile */=0A= + *(volatile unsigned int *)SPI_DATA =3D uiData;=0A= + =0A= + /* wait until transfer is finished */=0A= + delay(); /* let AT25256 do its write for awhile */=0A= + while (!(*(volatile unsigned int *)SPI_STAT & SPI_STAT_SPIF))=0A= + ;=0A= + =0A= + /* wait until transfer is finished */=0A= + delay(); /* let AT25256 do its write for awhile */=0A= + =0A= + /* in SPI, reads and writes occur simultaneously */=0A= + return(*(volatile unsigned int *)SPI_DATA); /* return SPI Data = Register */=0A= +}=0A= +=0A= +/* --------------------------------------------------=0A= + */=0A= +=0A= +extern void enable_chipselect_spi(void)=0A= +{=0A= + /* Write a 0 at chip select*/=0A= + *(volatile unsigned int *)GPIO_DAT &=3D ~GPIO_SPI_CS;=0A= +}=0A= +=0A= +/* --------------------------------------------------=0A= + Initialize the various SPI registers=0A= +*/=0A= +static void initialize_SPI(void)=0A= +{=0A= + unsigned int uiTempReg;=0A= + =0A= + /* ........... Initialize SPI Clock Register=0A= + ........... Depends on board's system frequency ........=0A= + */=0A= + =0A= + *(volatile unsigned int *)SPI_CNT =3D SPI_CNT_DIV; /* SPI = prescalar counter */=0A= + /* this is further divided by 2 in the chip.=0A= + AT25256 works at 3 MHz or under */=0A= + =0A= + disable_chipselect_spi();=0A= +=0A= + /* Interrupts disabled, SPI on and Master, CPOL/CPHA=3D1,1, clock/2 = */=0A= + *(volatile unsigned int *)SPI_CNTL =3D SPI_CNTL_VAL;=0A= + =0A= + /* .......... Clearing SPIF bit .............. */=0A= + uiTempReg =3D *(volatile unsigned int *)SPI_STAT; /* dummy read = */=0A= + uiTempReg =3D *(volatile unsigned int *)SPI_DATA; /* dummy read = */=0A= +}=0A= +=0A= +/* --------------------------------------------------=0A= +*/=0A= +static void initialize_AT25256(void)=0A= +{=0A= + unsigned int uiAtmelStatus;=0A= + =0A= + enable_chipselect_spi();=0A= + send_to_spi((unsigned int)(WRSR));=0A= + send_to_spi((unsigned int)(0x82)); /* AT25256 Status info to write = */=0A= + /* 1000_0010: protect no blocks, WPEN,WEN=3D1 */=0A= + /* send the Read Status command to AT25256 */=0A= + send_to_spi((unsigned int)(RDSR));=0A= + =0A= + /* dummy write so we can read AT25256 status info */=0A= + uiAtmelStatus =3D send_to_spi(0);=0A= + disable_chipselect_spi();=0A= + =0A= + /* AT25256 EPROM is not ready if LSB=3D1 */=0A= + while (uiAtmelStatus & 0x1) {=0A= + enable_chipselect_spi();=0A= + send_to_spi((unsigned int)(RDSR));=0A= + uiAtmelStatus =3D send_to_spi(0);=0A= + disable_chipselect_spi();=0A= + }=0A= +}=0A= +/* --------------------------------------------------=0A= + */=0A= +extern void initialize_hardware(void)=0A= +{=0A= + initialize_GPIO();=0A= + initialize_SPI();=0A= + initialize_AT25256();=0A= +}=0A= +EXPORT_SYMBOL(initialize_hardware);=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/prom.c = idtlinux/arch/mips/idt-boards/rc32300/S334/prom.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/prom.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/prom.c 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,117 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * prom interface routines=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +=0A= +unsigned int idt_cpu_freq =3D CONFIG_IDT_BOARD_FREQ;=0A= +EXPORT_SYMBOL(idt_cpu_freq);=0A= +=0A= +extern void setup_serial_port(void);=0A= +=0A= +#ifdef CONFIG_IDT_BOOT_NVRAM=0A= +extern void initialize_hardware(void);=0A= +extern void mapenv(int (*func)(char *, char *));=0A= +=0A= +static int make_bootparm(char *name,char *val)=0A= +{=0A= + if (strncmp(name, "bootparm", 8) =3D=3D 0) {=0A= + strcat(arcs_cmdline,val);=0A= + strcat(arcs_cmdline," ");=0A= + }=0A= + else if(strncmp(name, "HZ", 2) =3D=3D 0) {=0A= + idt_cpu_freq =3D simple_strtoul(val, 0, 10);=0A= + printk("CPU Clock at %d Hz (from HZ environment variable)\n",=0A= + idt_cpu_freq);=0A= + }=0A= + return 0;=0A= +}=0A= +=0A= +static void prom_init_cmdline(void)=0A= +{=0A= + initialize_hardware();=0A= + memset(arcs_cmdline,0,sizeof(arcs_cmdline));=0A= + mapenv(&make_bootparm);=0A= +}=0A= +#endif=0A= +extern unsigned long mips_machgroup;=0A= +extern unsigned long mips_machtype;=0A= +=0A= +const char *get_system_type(void)=0A= +{=0A= + return "IDT 79S334A";=0A= +}=0A= +=0A= +struct resource rc32300_res_ram =3D {=0A= + "RAM",=0A= + 0,=0A= + RAM_SIZE,=0A= + IORESOURCE_MEM=0A= +};=0A= +=0A= +char * __init prom_getcmdline(void)=0A= +{=0A= + return &(arcs_cmdline[0]);=0A= +}=0A= +=0A= +void prom_init(void)=0A= +{=0A= +#ifdef CONFIG_IDT_BOOT_NVRAM=0A= + prom_init_cmdline();=0A= +#endif=0A= +=0A= + setup_serial_port();=0A= + /* set our arch type */=0A= + mips_machgroup =3D MACH_GROUP_IDT;=0A= + mips_machtype =3D MACH_IDT_S334;=0A= + add_memory_region(0,=0A= + rc32300_res_ram.end - rc32300_res_ram.start,=0A= + BOOT_MEM_RAM);=0A= + return;=0A= +}=0A= +=0A= +void prom_free_prom_memory(void)=0A= +{=0A= +}=0A= +=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/reset.c = idtlinux/arch/mips/idt-boards/rc32300/S334/reset.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/reset.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/reset.c 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,71 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Reset EB365 board.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +void rc32300_restart(char *command)=0A= +{=0A= + set_c0_status((ST0_BEV | ST0_ERL));=0A= + set_c0_config(CONF_CM_UNCACHED);=0A= + flush_cache_all();=0A= + write_c0_wired(0);=0A= +=0A= + // Trigger the WatchDog Timer (Timer 3) to warm reset=0A= + rc32300_writel(0, TIMER0_CNTL + 3*TIMER_REG_OFFSET);=0A= + rc32300_writel(0xd8, CPU_IP_BUSERR_CNTL);=0A= + rc32300_writel(0, TIMER0_COUNT + 3*TIMER_REG_OFFSET);=0A= + rc32300_writel(2, TIMER0_COMPARE + 3*TIMER_REG_OFFSET);=0A= + rc32300_writel(1, TIMER0_CNTL + 3*TIMER_REG_OFFSET);=0A= +}=0A= +=0A= +void rc32300_halt(void)=0A= +{=0A= + printk(KERN_NOTICE "\n** You can safely turn off the power\n");=0A= + while (1)=0A= + __asm__(".set\tmips3\n\t"=0A= + "wait\n\t"=0A= + ".set\tmips0");=0A= +}=0A= +=0A= +void rc32300_power_off(void)=0A= +{=0A= + rc32300_halt();=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/serial.c = idtlinux/arch/mips/idt-boards/rc32300/S334/serial.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/serial.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/serial.c 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,72 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Serial port initialisation.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +=0A= +=0A= +extern int __init early_serial_setup(struct uart_port *port);=0A= +=0A= +extern unsigned int idt_cpu_freq;=0A= +=0A= +extern int __init setup_serial_port(void)=0A= +{ =0A= + static struct uart_port serial_req[2];=0A= +=0A= + memset(serial_req, 0, sizeof(serial_req));=0A= + serial_req[0].type =3D PORT_16550A;=0A= + serial_req[0].line =3D 0;=0A= + serial_req[0].irq =3D RC32300_UART0_IRQ;=0A= + serial_req[0].flags =3D STD_COM_FLAGS;=0A= + serial_req[0].uartclk =3D idt_cpu_freq;=0A= + serial_req[0].iotype =3D SERIAL_IO_MEM;=0A= + serial_req[0].membase =3D (char *) = KSEG1ADDR(RC32300_UART0_BASE);=0A= + serial_req[0].mapbase =3D KSEG1ADDR(RC32300_UART0_BASE);=0A= + serial_req[0].regshift =3D 2;=0A= +=0A= + early_serial_setup(&serial_req[0]);=0A= +=0A= + return(0);=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/serial_gdb.c = idtlinux/arch/mips/idt-boards/rc32300/S334/serial_gdb.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/serial_gdb.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/serial_gdb.c 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,272 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * S334A specific polling driver for 16550 UART.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +=0A= +/* set remote gdb baud rate at 115200 */=0A= +=0A= +#define GDB_BAUD 115200=0A= +#define CONS_BAUD 9600=0A= +=0A= +extern unsigned int idt_cpu_freq;=0A= +=0A= +=0A= +/* turn this on to watch the debug protocol echoed on the console port = */=0A= +#undef DEBUG_REMOTE_DEBUG=0A= +=0A= +#ifdef __MIPSEB__=0A= +#define CONS_PORT 0xb8000803u=0A= +#define GDB_PORT 0xb8000823u=0A= +#else=0A= +#define CONS_PORT 0xb8000800u=0A= +#define GDB_PORT 0xb8000820u=0A= +#endif=0A= + =0A= +volatile unsigned char *ports[2] =3D {=0A= + (volatile unsigned char *)CONS_PORT,=0A= + (volatile unsigned char *)GDB_PORT=0A= +};=0A= +=0A= +=0A= +void reset_gdb_port(void);=0A= +void cons_putc(char c);=0A= +int port_getc(int port);=0A= +void port_putc(int port, char c);=0A= +=0A= +int cons_getc(void)=0A= +{=0A= + return port_getc(0);=0A= +}=0A= +=0A= +void cons_putc(char c)=0A= +{=0A= + port_putc(0, c);=0A= +}=0A= +=0A= +void cons_puts(char *s)=0A= +{=0A= + while(*s) {=0A= + if(*s =3D=3D '\n') cons_putc('\r');=0A= + cons_putc(*s);=0A= + s++;=0A= + }=0A= +}=0A= +=0A= +void cons_do_putn(int n)=0A= +{=0A= + if(n) {=0A= + cons_do_putn(n / 10);=0A= + cons_putc(n % 10 + '0');=0A= + }=0A= +}=0A= +=0A= +void cons_putn(int n)=0A= +{=0A= + if(n < 0) {=0A= + cons_putc('-');=0A= + n =3D -n;=0A= + }=0A= +=0A= + if (n =3D=3D 0) {=0A= + cons_putc('0');=0A= + } else {=0A= + cons_do_putn(n);=0A= + }=0A= +}=0A= +=0A= +#ifdef DEBUG_REMOTE_DEBUG=0A= +static enum {HUH, SENDING, GETTING} state;=0A= +=0A= +static void sent(int c)=0A= +{=0A= + switch(state) {=0A= + case HUH:=0A= + case GETTING:=0A= + cons_puts("\nSNT ");=0A= + state =3D SENDING;=0A= + /* fall through */=0A= + case SENDING:=0A= + cons_putc(c);=0A= + break;=0A= + } =0A= +}=0A= +=0A= +static void got(int c)=0A= +{=0A= + switch(state) {=0A= + case HUH:=0A= + case SENDING:=0A= + cons_puts("\nGOT ");=0A= + state =3D GETTING;=0A= + /* fall through */=0A= + case GETTING:=0A= + cons_putc(c);=0A= + break;=0A= + } =0A= +}=0A= +#endif /* DEBUG_REMOTE_DEBUG */=0A= +=0A= +static int first =3D 1;=0A= +=0A= +int getDebugChar(void)=0A= +{=0A= + int c;=0A= +=0A= + if(first) reset_gdb_port();=0A= +=0A= + c =3D port_getc(1);=0A= +=0A= +#ifdef DEBUG_REMOTE_DEBUG=0A= + got(c);=0A= +#endif=0A= +=0A= + return c;=0A= +}=0A= +=0A= +int port_getc(int p)=0A= +{=0A= + volatile unsigned char *port =3D ports[p];=0A= + int c;=0A= +=0A= + while((*(port + UART_LSR * 4) & UART_LSR_DR) =3D=3D 0) {=0A= + continue;=0A= + } =0A= +=0A= + c =3D *(port + UART_RX * 4);=0A= +=0A= + return c;=0A= +}=0A= +=0A= +int port_getc_ready(int p)=0A= +{=0A= + volatile unsigned char *port =3D ports[p];=0A= +=0A= + return *(port + UART_LSR * 4) & UART_LSR_DR;=0A= +}=0A= +=0A= +int isDebugReady(void)=0A= +{=0A= + return port_getc_ready(1);=0A= +}=0A= +=0A= +void putDebugChar(char c)=0A= +{=0A= + if(first) reset_gdb_port();=0A= +=0A= +#ifdef DEBUG_REMOTE_DEBUG=0A= + sent(c);=0A= +#endif=0A= +=0A= + port_putc(1, c);=0A= +}=0A= +=0A= +#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)=0A= +=0A= +void port_putc(int p, char c)=0A= +{=0A= + volatile unsigned char *port =3D ports[p];=0A= + volatile unsigned char *lsr =3D port + UART_LSR * 4;=0A= +=0A= + while((*lsr & OK_TO_XMT) !=3D OK_TO_XMT) {=0A= + continue;=0A= + }=0A= +=0A= + *(port + UART_TX * 4) =3D c;=0A= +}=0A= +=0A= +void reset_gdb_port(void)=0A= +{=0A= + volatile unsigned char *port =3D ports[1];=0A= + unsigned int DIVISOR =3D (idt_cpu_freq / 16 / GDB_BAUD);=0A= +=0A= + first =3D 0;=0A= +=0A= +#ifdef DEBUG_REMOTE_DEBUG=0A= + cons_puts("reset_gdb_port: initializing remote debug serial port = (internal UART 1, ");=0A= + cons_putn(GDB_BAUD);=0A= + cons_puts("baud, MHz=3D");=0A= + cons_putn(idt_cpu_freq);=0A= + cons_puts(", divisor=3D");=0A= + cons_putn(DIVISOR);=0A= + cons_puts(")\n");=0A= +#endif=0A= +=0A= + /* reset the port */=0A= + *(port + UART_CSR * 4) =3D 0;=0A= +=0A= + /* clear and enable the FIFOs */=0A= + *(port + UART_FCR * 4) =3D UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR = | =0A= + UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;=0A= +=0A= + /* set the baud rate */=0A= + *(port + UART_LCR * 4) =3D UART_LCR_DLAB; /* enable DLL, DLM = registers */=0A= + *(port + UART_DLL * 4) =3D DIVISOR;=0A= + *(port + UART_DLM * 4) =3D DIVISOR >> 8;=0A= +=0A= + /* set the line control stuff and disable DLL, DLM regs */=0A= +=0A= + *(port + UART_LCR * 4) =3D UART_LCR_STOP | /* 2 stop bits */=0A= + UART_LCR_WLEN8; /* 8 bit word length */=0A= + =0A= + /* leave interrupts off */=0A= + *(port + UART_IER * 4) =3D 0;=0A= +=0A= + /* the modem controls don't leave the chip on this port, so leave = them alone */=0A= + *(port + UART_MCR * 4) =3D 0;=0A= +}=0A= +=0A= +void reset_cons_port(void)=0A= +{=0A= + volatile unsigned char *port =3D ports[0];=0A= + unsigned int DIVISOR =3D (idt_cpu_freq / 16 / CONS_BAUD);=0A= +=0A= + /* reset the port */=0A= + *(port + UART_CSR * 4) =3D 0;=0A= +=0A= + /* clear and enable the FIFOs */=0A= + *(port + UART_FCR * 4) =3D UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR = | =0A= + UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;=0A= +=0A= + /* set the baud rate */=0A= + *(port + UART_LCR * 4) =3D UART_LCR_DLAB; /* enable DLL, DLM = registers */=0A= +=0A= + *(port + UART_DLL * 4) =3D DIVISOR;=0A= + *(port + UART_DLM * 4) =3D DIVISOR >> 8;=0A= + /* set the line control stuff and disable DLL, DLM regs */=0A= +=0A= + *(port + UART_LCR * 4) =3D UART_LCR_STOP | /* 2 stop bits */=0A= + UART_LCR_WLEN8; /* 8 bit word length */=0A= + =0A= + /* leave interrupts off */=0A= + *(port + UART_IER * 4) =3D 0;=0A= +=0A= + /* the modem controls don't leave the chip on this port, so leave = them alone */=0A= + *(port + UART_MCR * 4) =3D 0;=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/setup.c = idtlinux/arch/mips/idt-boards/rc32300/S334/setup.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/setup.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/setup.c 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,226 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * setup routines for IDT EB365 boards=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +=0A= +#include =0A= +=0A= +extern void (*board_time_init)(void);=0A= +extern void (*board_timer_setup)(struct irqaction *irq);=0A= +extern void rc32300_time_init(void);=0A= +extern void rc32300_timer_setup(struct irqaction *irq);=0A= +extern char * __init prom_getcmdline(void);=0A= +=0A= +extern void rc32300_restart(char *);=0A= +extern void rc32300_halt(void);=0A= +extern void rc32300_power_off(void);=0A= +extern void rc32300_ack_irq(unsigned int);=0A= +#define DIG0 ((volatile unsigned char *)KSEG1ADDR(LCD_DIGIT0))=0A= +#define DIG1 ((volatile unsigned char *)KSEG1ADDR(LCD_DIGIT1))=0A= +#define DIG2 ((volatile unsigned char *)KSEG1ADDR(LCD_DIGIT2))=0A= +#define DIG3 ((volatile unsigned char *)KSEG1ADDR(LCD_DIGIT3))=0A= +=0A= +=0A= +=0A= +void idt_disp_char(int i, char c)=0A= +{ =0A= + switch (i) {=0A= + case 0: *DIG0 =3D c; break;=0A= + case 1: *DIG1 =3D c; break;=0A= + case 2: *DIG2 =3D c; break;=0A= + case 3: *DIG3 =3D c; break;=0A= + default: *DIG0 =3D '?'; break;=0A= + }=0A= +}=0A= +=0A= +=0A= +int idtprintf(const char *fmt, ...)=0A= +{=0A= + va_list args;=0A= + int i, len;=0A= + char str[256];=0A= + static int lcd_digit_reg[4] =3D {=0A= + KSEG1ADDR(LCD_DIGIT0),=0A= + KSEG1ADDR(LCD_DIGIT1),=0A= + KSEG1ADDR(LCD_DIGIT2),=0A= + KSEG1ADDR(LCD_DIGIT3)=0A= + };=0A= +=0A= + va_start(args, fmt);=0A= + len =3D vsprintf(str, fmt, args);=0A= + va_end(args);=0A= +=0A= + len =3D len > 4 ? 4 : len;=0A= + readb(KSEG1ADDR(LCD_CLEAR)); // clear the display=0A= + for (i =3D 0; i < len; i++) {=0A= + if (str[i])=0A= + writeb(str[i], lcd_digit_reg[i]);=0A= + }=0A= + =0A= + return len;=0A= +}=0A= +=0A= +=0A= +int rc32334_be_handler(struct pt_regs *regs,int fixup)=0A= +{=0A= + int data =3D regs->cp0_cause & 4;=0A= + u32 cntl;=0A= + extern void rc32300_ack_irq(unsigned int irq_nr);=0A= + =0A= + printk("RC32334 %s bus error:\n", data ? "Data" : "Instruction");=0A= + printk(" EPC =3D=3D %08lx, RA =3D=3D %08lx\n",=0A= + regs->cp0_epc, regs->regs[31]);=0A= + printk(" CPU bus address =3D=3D %08x\n",=0A= + rc32300_readl(CPU_BUSERR_ADDR));=0A= + printk(" IP bus address =3D=3D %08x\n",=0A= + rc32300_readl(CPU_IP_BUSERR_ADDR));=0A= + cntl =3D rc32300_readl(CPU_IP_BUSERR_CNTL);=0A= + printk(" Bus error occured on a %s on %s bus\n",=0A= + cntl & 1 ? "read" : "write",=0A= + cntl & 4 ? "CPU" : "IP");=0A= +=0A= + // ack the bus errors=0A= + rc32300_ack_irq(GROUP4_IRQ_BASE+4); // ack timer 4 rollover intr=0A= + rc32300_ack_irq(GROUP4_IRQ_BASE+5); // ack timer 5 rollover intr=0A= + rc32300_ack_irq(GROUP1_IRQ_BASE); // ack bus error intr=0A= + rc32300_writel(cntl & ~0x07, CPU_IP_BUSERR_CNTL);=0A= +=0A= + die_if_kernel("Oops", regs);=0A= + force_sig(SIGBUS, current);=0A= + return 0;=0A= +}=0A= +=0A= +void __init bus_error_init(void)=0A= +{=0A= + /*=0A= + * The RC32334 uses two timers to count-out bus=0A= + * timeouts. In addition to bus error exceptions,=0A= + * the timer timeouts can trigger interrupts.=0A= + *=0A= + * On CPU reads, a bus error will cause an exception as well=0A= + * as an interrupt. On CPU writes, a bus error only causes=0A= + * an interrupt.=0A= + */=0A= +=0A= + /*=0A= + * Disable CPU and IP Bus Error exceptions (PCI scan will=0A= + * cause bus timeouts), and disable WatchDog.=0A= + */=0A= + rc32300_writel(0x98, CPU_IP_BUSERR_CNTL);=0A= +=0A= + rc32300_writel(0, TIMER0_CNTL + 4*TIMER_REG_OFFSET);=0A= + rc32300_writel(0, TIMER0_CNTL + 5*TIMER_REG_OFFSET);=0A= + rc32300_writel(0x3fff, TIMER0_COMPARE + 4*TIMER_REG_OFFSET);=0A= + rc32300_writel(0x3fff, TIMER0_COMPARE + 5*TIMER_REG_OFFSET);=0A= + rc32300_writel(1, TIMER0_CNTL + 4*TIMER_REG_OFFSET);=0A= + rc32300_writel(1, TIMER0_CNTL + 5*TIMER_REG_OFFSET);=0A= + =0A= +}=0A= +=0A= +extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);=0A= +=0A= +static int __init idt_setup(void)=0A= +{=0A= + char* argptr;=0A= +=0A= + argptr =3D prom_getcmdline();=0A= +=0A= + board_time_init =3D rc32300_time_init;=0A= + board_timer_setup =3D rc32300_timer_setup;=0A= + board_be_handler =3D rc32334_be_handler;=0A= + _machine_restart =3D rc32300_restart;=0A= + _machine_halt =3D rc32300_halt;=0A= + pm_power_off =3D rc32300_power_off;=0A= +=0A= + set_io_port_base(KSEG1);=0A= +=0A= + // clear out any wired entries=0A= + write_c0_wired(0);=0A= +=0A= + bus_error_init();=0A= +=0A= + readb(KSEG1ADDR(LCD_CLEAR)); // clear the 4-digit LCD display=0A= +=0A= + idtprintf("Unix");=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +int page_is_ram(unsigned long pagenr)=0A= +{=0A= + return 1;=0A= +}=0A= +=0A= +static int __init buserror_enable(void)=0A= +{=0A= + // ack any bus errors=0A= +=0A= + rc32300_ack_irq(GROUP4_IRQ_BASE+4); // ack timer 4 rollover intr=0A= + rc32300_ack_irq(GROUP4_IRQ_BASE+5); // ack timer 5 rollover intr=0A= + rc32300_ack_irq(GROUP1_IRQ_BASE); // ack bus error intr=0A= +=0A= + /*=0A= + * Enable CPU and IP Bus Error exceptions, and disable WatchDog.=0A= + */=0A= + rc32300_writel(0x18, CPU_IP_BUSERR_CNTL);=0A= + return 0;=0A= +}=0A= +=0A= +//early_initcall(idt_setup);=0A= +void __init plat_setup(void){=0A= + idt_setup();=0A= +}=0A= +=0A= +__initcall(buserror_enable);=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/time.c = idtlinux/arch/mips/idt-boards/rc32300/S334/time.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32300/S334/time.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32300/S334/time.c 2006-03-09 = 16:25:49.000000000 -0800=0A= @@ -0,0 +1,149 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT S334 timer routines=0A= + *=0A= + * Copyright 2006 IDT Inc.=0A= + * Author: Integrated Device Technology Inc. rischelp@idt.com=0A= + *=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +=0A= +static unsigned long r4k_offset; /* Amount to incr compare reg each = time */=0A= +static unsigned long r4k_cur; /* What counter should be at next = timer irq */=0A= +=0A= +extern unsigned int idt_cpu_freq;=0A= +#if defined(CONFIG_IDT_79EB365) && defined(CONFIG_MIPS_RTC)=0A= +extern void rtc_ds1553_init(void);=0A= +#elif defined(CONFIG_IDT_79EB355) && defined(CONFIG_MIPS_RTC)=0A= +extern void rtc_ds1501_init(void);=0A= +#endif=0A= +=0A= +/* =0A= + * Figure out the r4k offset, the amount to increment the compare=0A= + * register for each time tick. There is no RTC available.=0A= + *=0A= + * The RC32300 counts at half the CPU *core* speed.=0A= + */=0A= +static unsigned long __init cal_r4koff(void)=0A= +{=0A= + mips_hpt_frequency =3D idt_cpu_freq * IDT_CLOCK_MULT / 2;=0A= + return (mips_hpt_frequency / HZ);=0A= +}=0A= +=0A= +=0A= +void __init rc32300_time_init(void)=0A= +{=0A= + unsigned int est_freq, flags;=0A= + =0A= + local_irq_save(flags);=0A= + =0A= + printk("calculating r4koff... ");=0A= + r4k_offset =3D cal_r4koff();=0A= + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);=0A= + =0A= + est_freq =3D 2*r4k_offset*HZ; =0A= + est_freq +=3D 5000; /* round */=0A= + est_freq -=3D est_freq%10000;=0A= + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, =0A= + (est_freq%1000000)*100/1000000);=0A= + local_irq_restore(flags);=0A= + =0A= +#if defined(CONFIG_IDT_79EB365) && defined(CONFIG_MIPS_RTC)=0A= + rtc_ds1553_init();=0A= +#elif defined(CONFIG_IDT_79EB355) && defined(CONFIG_MIPS_RTC)=0A= + rtc_ds1501_init();=0A= +#endif=0A= +=0A= +}=0A= +=0A= +=0A= +void __init rc32300_timer_setup(struct irqaction *irq)=0A= +{=0A= + /* we are using the cpu counter for timer interrupts */=0A= + setup_irq(MIPS_CPU_TIMER_IRQ, irq);=0A= +=0A= +#if 0 =0A= + /* to generate the first timer interrupt */=0A= + r4k_cur =3D (read_c0_count() + r4k_offset);=0A= + write_c0_compare(r4k_cur);=0A= +#endif=0A= +}=0A= +=0A= +static inline void ack_r4ktimer(unsigned long newval)=0A= +{=0A= + write_c0_compare(newval);=0A= +}=0A= +=0A= +extern void idt_disp_char(int i,char c);=0A= +=0A= +asmlinkage void idt_timer_interrupt(int irq,struct pt_regs *regs)=0A= +{ =0A= +#ifdef CONFIG_KGDB=0A= + void kgdb_check(void);=0A= +#endif=0A= +=0A= + static unsigned int timerCount =3D 0;=0A= + static int toggle =3D 0;=0A= +=0A= + irq_enter();=0A= + kstat_this_cpu.irqs[irq]++;=0A= +=0A= + if( (timerCount++ % HZ) =3D=3D 0)=0A= + { =0A= + toggle ^=3D 1;=0A= + idt_disp_char(0,toggle ? 'u' :'U');=0A= + }=0A= +=0A= + timer_interrupt(irq, NULL, regs);=0A= + irq_exit();=0A= +=0A= +#ifdef CONFIG_KGDB=0A= + kgdb_check();=0A= +#endif=0A= +}=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/csu_idt.S = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/csu_idt.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/csu_idt.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/csu_idt.S = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,345 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Board initialization code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= + =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#define MHZ CONFIG_IDT_BOARD_FREQ=0A= + =0A= +#include "idthdr.h"=0A= +#include "iregdef.h"=0A= +#include "idtcpu.h"=0A= +#include "s434ram.h"=0A= +#include "s434.h"=0A= +=0A= +#define IndexInvalidate_I 0x00=0A= +=0A= +/*--------------------------------------------------------------=0A= +** prom entry point table=0A= +*-------------------------------------------------------------*/=0A= +=0A= +FRAME(start,sp,0,ra)=0A= + j idtstart /* begin monitor from start |00| */=0A= +=0A= +idtstart:=0A= +=0A= + .set noreorder=0A= + mtc0 zero, C0_CAUSE=0A= + nop=0A= + li v0, 0x0=0A= + or v0, (SR_CU0 | SR_BEV)=0A= + mtc0 v0, C0_SR=0A= + nop=0A= + mfc0 v1, C0_CONFIG=0A= + nop=0A= + and v1, ~(0x7)=0A= + ori v1, 0x3=0A= + mtc0 v1, C0_CONFIG=0A= + nop=0A= + nop=0A= + =0A= +/* ------------------- Disable WatchDog Timer = ----------------------------- */=0A= + li t0, WTC_BASE=0A= + sw zero, 0x3C(t0) /* WTC */=0A= +/* ------ Alternate functions for GPIO pins = --------------------------------*/=0A= +/* only UART0, UART1 and mem_addr */=0A= + li t0, GPIO_BASE=0A= + li t1, 0xf3=0A= + sw t1, 0x0(t0)=0A= +=0A= +#if !defined(PCISAT)=0A= +/* ------------------- Assert PCI reset = ----------------------------------- */=0A= + li t0, 0xb8080000=0A= + lw t1, (t0)=0A= + andi t2, t1, 0x1=0A= + beqz t2, 2f=0A= + nop=0A= + andi t2, t1, 0x3fe=0A= + sw t2, (t0)=0A= + li t2, 0x1000=0A= +1:=0A= + addi t2, -1=0A= + bnez t2, 1b=0A= + nop=0A= +2:=0A= + ori t2, t1, 0x1=0A= + sw t2, (t0)=0A= + lui t2, 0x2=0A= +rip:=0A= + lw t1, 4(t0)=0A= + and t1, t1, t2=0A= + bnez t1, rip=0A= + nop=0A= +#endif=0A= +=0A= +/* ------------------- Setup Device Controller ------------------------= ---- */=0A= + li t0, DEV_CTL_BASE /* load 2 base address registers' = base */=0A= + li t1, DEV0_CTRL /* device0 control parameter = */=0A= + sw t1, 0x8(t0) /* set the control register CS0 = */=0A= + li t1, DEV0_TC /* device0 timing config parameter = */=0A= + sw t1, 0xC(t0)=0A= + li t1, DEV1_BASE /* set the device base register for = CS1 */=0A= + sw t1, 0x10(t0)=0A= + li t1, DEV1_MASK /* set the device mask register for = CS1 */=0A= + sw t1, 0x14(t0) =0A= + li t1, DEV1_CTRL /* set the device control register = for CS1*/=0A= + sw t1, 0x18(t0)=0A= + li t1, DEV1_TC /* set the device timing register = for CS1 */=0A= + sw t1, 0x1C(t0) =0A= +=0A= + li t1, DEV2_BASE /* set the device base register for = CS1 */=0A= + sw t1, 0x20(t0)=0A= + li t1, DEV2_MASK /* set the device mask register for = CS1 */=0A= + sw t1, 0x24(t0) =0A= + li t1, DEV2_CTRL /* set the device control register = for CS1*/=0A= + sw t1, 0x28(t0)=0A= + li t1, DEV2_TC /* set the device timing register = for CS1 */=0A= + sw t1, 0x2C(t0) =0A= +=0A= + li t1, DEV3_BASE /* set the device base register for = CS1 */=0A= + sw t1, 0x30(t0)=0A= + li t1, DEV3_MASK /* set the device mask register for = CS1 */=0A= + sw t1, 0x34(t0) =0A= + li t1, DEV3_CTRL /* set the device control register = for CS1*/=0A= + sw t1, 0x38(t0)=0A= + li t1, DEV3_TC /* set the device timing register = for CS1 */=0A= + sw t1, 0x3C(t0) =0A= +=0A= + DISPLAY('I','D','D','R')=0A= +#if MEMCFG !=3D SRAM_ONLY=0A= +=0A= +/* ------------- INITIALIZE DDR SDRAM CONTROLLER = ---------------------------*/=0A= +=0A= + li t1, 0x0 /* Add 200 microseconds of delay = */=0A= + li t2, DELAY_200USEC=0A= +1:=0A= + add t1, 1=0A= + bne t1, t2, 1b=0A= + nop=0A= +=0A= +/*-------------- Initialize DDR Base and Mask Registers = --------------------*/=0A= +=0A= + li t0, DDR_BASE=0A= +=0A= + /* Load the DDRC, reset Refresh Enable */=0A= + li t1, DDRC_VAL_AT_INIT=0A= + sw t1, 0x10(t0)=0A= + =0A= + sw zero, 0x4(t0)=0A= + sw zero, 0xc(t0)=0A= + sw zero, 0x18(t0)=0A= +=0A= + /* Store DDRBASE */=0A= + li t1, DDR_BASE_VAL=0A= + sw t1, 0x0(t0)=0A= +=0A= + /* Store DDRMASK */=0A= + li t1, DDR_MASK_VAL=0A= + sw t1, 0x4(t0)=0A= +=0A= + /* Store DDRABASE */=0A= + li t1, DDR_ABASE_VAL=0A= + sw t1, 0x14(t0)=0A= +=0A= + /* Load DDRAMASK to disable alternate Mapping */=0A= + li t1, DDR_AMASK_VAL=0A= + sw t1, 0x18(t0)=0A= +=0A= + li t1, DDR_CUST_NOP /* Write to DDR Custom transaction = register */=0A= + sw t1, 0x20(t0)=0A= +=0A= + li t2, DATA_PATTERN=0A= + li t1, 0xA0000000 | DDR_BASE_VAL=0A= + sw t2, 0x0(t1)=0A= +=0A= + /* Add 200 microseconds of delay */=0A= + li t1, 0x0=0A= + li t2, DELAY_200USEC=0A= +1:=0A= + add t1, 1=0A= + bne t1, t2, 1b=0A= + nop=0A= + =0A= + /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */=0A= + li t1, DDR_CUST_PRECHARGE=0A= + sw t1, 0x20(t0) /* Write to DDR Custom transaction = register */=0A= +=0A= + /* Generate A10 high to pre-charge both the banks */=0A= + li t2, DATA_PATTERN=0A= + li t1, 0xA0000000 | DDR_PRECHARGE_OFFSET | DDR_BASE_VAL=0A= + sw t2, 0x0(t1)=0A= +=0A= + /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */=0A= + li t1, DDR_LD_EMODE_REG=0A= + sw t1, 0x20(t0) /* Write to DDR Custom transaction = register */=0A= +=0A= + /* Generate EMODE register contents on A15-A2 */=0A= + li t2, DATA_PATTERN=0A= + li t1, 0xA0000000 | DDR_EMODE_VAL | DDR_BASE_VAL=0A= + sw t2, 0x0(t1)=0A= +=0A= + /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */=0A= + li t1, DDR_LD_MODE_REG=0A= + sw t1, 0x20(t0) /* Write to DDR Custom transaction = register */=0A= +=0A= + /* Generate Mode register contents on the address bus A15-A2 */=0A= + li t2, DATA_PATTERN=0A= + li t1, 0xA0000000 | DDR_DLL_RES_MODE_VAL | DDR_BASE_VAL=0A= + sw t2, 0x0(t1)=0A= +=0A= + /* Delay of 1.6 microseconds ~ 300 delay iteration value */=0A= + li t1, 0x0=0A= + li t2, 500=0A= +1:=0A= + add t1, 1=0A= + bne t1, t2, 1b=0A= + nop=0A= +=0A= + /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */=0A= + li t1, DDR_CUST_PRECHARGE=0A= + sw t1, 0x20(t0) /* Write to DDR Custom transaction = register */=0A= +=0A= + /* Generate A10 high to pre-charge both the banks */=0A= + li t2, DATA_PATTERN=0A= + li t1, 0xA0000000 | DDR_PRECHARGE_OFFSET | DDR_BASE_VAL=0A= + sw t2, 0x0(t1)=0A= +=0A= + /* Implements 9 cycles of Auto refresh allowing=0A= + sufficient margin for stability*/=0A= + li t4, 9=0A= + li t3, 0=0A= +1:=0A= + li t1, DDR_CUST_REFRESH=0A= + sw t1, 0x20(t0) /* Write to DDR Custom transaction = register */=0A= +=0A= + /* Read it back to flush CPU write buffers */=0A= + lw t1, 0x20(t0)=0A= +=0A= + /* Access DDR */=0A= + li t2, DATA_PATTERN=0A= + li t1, 0xA0000000 | DDR_BASE_VAL=0A= + sw t2, 0x0(t1)=0A= +=0A= + add t3, 1=0A= + bne t3, t4, 1b=0A= + nop=0A= +=0A= + /* Register t0 carries pointer to the DDR_BASE: 0xB8018000 */=0A= + li t1, DDR_LD_MODE_REG=0A= + sw t1, 0x20(t0) /* Write to DDR Custom transaction = register */=0A= +=0A= + /* Generate Mode Register contents on the address bus A12-A0 */=0A= + li t2, DATA_PATTERN=0A= + li t1, 0xA0000000 | DDR_DLL_MODE_VAL | DDR_BASE_VAL=0A= + sw t2, 0x0(t1)=0A= +=0A= + /* Initialize the refresh timer with fast refresh count */=0A= + li t0, RCOUNT=0A= + li t1, DDR_REF_CMP_FAST=0A= + =0A= + /* Set the RCOMPARE register */=0A= + sw t1, 0x4(t0)=0A= +=0A= + /* Enable the Refresh timer */=0A= + li t1, 0x1 /* CE set to enabled the Refresh = counter */=0A= + sw t1, 0x8(t0)=0A= +=0A= + /* Enable RE-refresh enable in the DDRC register */=0A= + li t0, DDR_BASE=0A= + li t1, DDRC_VAL_NORMAL=0A= + sw t1, 0x10(t0)=0A= +=0A= + /* Add 200 microseconds of delay */=0A= + li t1, 0x0=0A= + li t2, DELAY_200USEC=0A= +1:=0A= + add t1, 1=0A= + bne t1, t2, 1b=0A= + nop=0A= +=0A= + li t0, RCOUNT=0A= +=0A= + /* Disable the refresh counter before changing the compare value = */=0A= + sw zero, 0x8(t0)=0A= +=0A= + /* Set the RCOMPARE register with value gotten above */=0A= + li t3, DDR_REF_CMP_VAL=0A= + sw t3, 0x4(t0)=0A= +=0A= + /* Enable the Refresh timer */=0A= + li t1, 0x1 /* CE set to enabled the Refresh = counter */=0A= + sw t1, 0x8(t0)=0A= +=0A= + /* Add 200 microseconds of delay */=0A= + li t1, 0x0=0A= + li t2, DELAY_200USEC=0A= +1:=0A= + add t1, 1=0A= + bne t1, t2, 1b=0A= + nop=0A= +=0A= +#endif=0A= + li t0, 0xa0000000=0A= + li t1, 0xa0100000=0A= +1:=0A= + sw zero, 0x00(t0)=0A= + sw zero, 0x04(t0)=0A= + sw zero, 0x08(t0)=0A= + sw zero, 0x0c(t0)=0A= + addiu t0, 16=0A= + nop=0A= + blt t0, t1, 1b=0A= + nop=0A= + nop=0A= + nop=0A= +3:=0A= + mfc0 t0, C0_SR=0A= + nop=0A= + nop=0A= + and t0, ~SR_BEV=0A= + mtc0 t0, C0_SR=0A= + nop=0A= + nop=0A= +=0A= +4: =0A= + =0A= +/* Jump to zImage startup */=0A= + =0A= + la k0, zstartup=0A= + j k0=0A= + nop=0A= + nop=0A= +=0A= +ENDFRAME(start)=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/head.S = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/head.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/head.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/head.S 2006-03-09 = 16:25:50.000000000 -0800=0A= @@ -0,0 +1,126 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Board initialisation code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= + =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#define IndexInvalidate_I 0x00=0A= +=0A= + .set noreorder=0A= + .cprestore=0A= + LEAF(zstartup)=0A= +zstartup:=0A= +=0A= + la sp, .stack=0A= + move s0, a0=0A= + move s1, a1=0A= + move s2, a2=0A= + move s3, a3=0A= +=0A= + /* Clear BSS */=0A= + /* Note: when zImage is in ROM, _edata and _bss point to=0A= + * ROM space even when using -Tbss on the linker command line;=0A= + * maybe ld.script needs to be corrected.=0A= + */=0A= + la a0, .stack=0A= + la a2, _end=0A= +1: sw zero, 0(a0)=0A= + bne a2, a0, 1b=0A= + addu a0, 4=0A= +=0A= + /* flush the I-Cache */=0A= + li k0, 0x80000000 # start address=0A= + li k1, 0x80004000 # end address (16KB I-Cache)=0A= + subu k1, 128=0A= +=0A= +2:=0A= + .set mips3=0A= + cache IndexInvalidate_I, 0(k0)=0A= + cache IndexInvalidate_I, 16(k0)=0A= + cache IndexInvalidate_I, 32(k0)=0A= + cache IndexInvalidate_I, 48(k0)=0A= + cache IndexInvalidate_I, 64(k0)=0A= + cache IndexInvalidate_I, 80(k0)=0A= + cache IndexInvalidate_I, 96(k0)=0A= + cache IndexInvalidate_I, 112(k0)=0A= + .set mips0=0A= +=0A= + bne k0, k1, 2b=0A= + addu k0, k0, 128=0A= + /* done */=0A= +=0A= + /* flush the D-Cache */=0A= + li k0, 0x80000000 # start address=0A= + li k1, 0x80004000 # end address (16KB I-Cache)=0A= + subu k1, 128=0A= +=0A= +2:=0A= + .set mips3=0A= + cache Index_Writeback_Inv_D, 0(k0)=0A= + cache Index_Writeback_Inv_D, 16(k0)=0A= + cache Index_Writeback_Inv_D, 32(k0)=0A= + cache Index_Writeback_Inv_D, 48(k0)=0A= + cache Index_Writeback_Inv_D, 64(k0)=0A= + cache Index_Writeback_Inv_D, 80(k0)=0A= + cache Index_Writeback_Inv_D, 96(k0)=0A= + cache Index_Writeback_Inv_D, 112(k0)=0A= + .set mips0=0A= +=0A= + bne k0, k1, 2b=0A= + addu k0, k0, 128=0A= + /* done */=0A= +=0A= + la ra, 3f=0A= + la k0, decompress_kernel=0A= + jr k0=0A= + nop=0A= +3:=0A= +=0A= + move a0, s0=0A= + move a1, s1=0A= + move a2, s2=0A= + move a3, s3=0A= + li k0, KERNEL_ENTRY=0A= + jr k0=0A= + nop=0A= +4:=0A= + b 4b=0A= + END(zstartup)=0A= +=0A= + .bss=0A= + .fill 0x2000=0A= + EXPORT(.stack)=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/idtcpu.h = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/idtcpu.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/idtcpu.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/idtcpu.h = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,336 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT CPU register definitions. Though the registers are already = defined=0A= + * under asm directory, they are once again declared here for the = ease of=0A= + * syncing up with IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +=0A= +#if !defined(__IDTCPU_H__)=0A= +#define __IDTCPU_H__=0A= +/*=0A= +** memory configuration and mapping=0A= +*/=0A= +#define K0BASE 0x80000000=0A= +#define K0SIZE 0x20000000=0A= +#define K1BASE 0xa0000000=0A= +#define K1SIZE 0x20000000=0A= +#define K2BASE 0xc0000000=0A= +#if defined(CPU_R32364)=0A= +#define K2SIZE 0x40000000=0A= +#define ICEBASE 0xff000000=0A= +#define ICESIZE 0x01000000=0A= +#elif defined(CPU_R32438) || defined(CPU_R32434)=0A= +#define K2SIZE 0x20000000=0A= +#define K3BASE 0xe0000000=0A= +#define K3SIZE 0x20000000=0A= +#define ICEBASE 0xff200000=0A= +#define ICESIZE 0x00200000=0A= +#endif=0A= +=0A= +#define KUBASE 0=0A= +#define KUSIZE 0x80000000=0A= +=0A= +/*=0A= +** Exception Vectors=0A= +*/=0A= +=0A= +#define T_VEC (K0BASE + 0x000) /* tlbmiss vector */=0A= +#define X_VEC (K0BASE + 0x080) /* xtlbmiss vector */=0A= +#define C_VEC (K1BASE + 0x100) /* cache error vector */=0A= +#define E_VEC (K0BASE + 0x180) /* exception vector */=0A= +#define I_VEC (K0BASE + 0X200) /* interrupt vector */=0A= +#define R_VEC (K1BASE + 0x1fc00000) /* reset vector */=0A= +=0A= +/*=0A= +** Address conversion macros=0A= +*/=0A= +#ifdef CLANGUAGE=0A= +#define CAST(as) (as)=0A= +#else=0A= +#define CAST(as)=0A= +#endif=0A= +=0A= +#define K0_TO_K1(x) (CAST(unsigned)(x) | 0xA0000000) /* kseg0 to = kseg1 */=0A= +#define K1_TO_K0(x) (CAST(unsigned)(x) & 0x9FFFFFFF) /* kseg1 to = kseg0 */=0A= +#define K0_TO_PHYS(x) (CAST(unsigned)(x) & 0x1FFFFFFF) /* kseg0 to = physical */=0A= +#define K1_TO_PHYS(x) (CAST(unsigned)(x) & 0x1FFFFFFF) /* kseg1 to = physical */=0A= +#define PHYS_TO_K0(x) (CAST(unsigned)(x) | 0x80000000) /* physical to = kseg0 */=0A= +#define PHYS_TO_K1(x) (CAST(unsigned)(x) | 0xA0000000) /* physical to = kseg1 */=0A= +=0A= +#if defined(CPU_R32364) /* Includes RC32332, RC32334 */=0A= +#define CFG_ICE 0x80000000 /* ICE detect */=0A= +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */=0A= +#define CFG_ECBY2 0x00000000 /* divide by 2 */=0A= +#define CFG_ECBY3 0x10000000 /* divide by 3 */=0A= +#define CFG_ECBY4 0x20000000 /* divide by 4 */=0A= +#define CFG_BE 0x00008000 /* Big Endian */=0A= +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */=0A= +#define CFG_ICSHIFT 9=0A= +#define CFG_DCMASK 0x000001c0 /* Data cache size */=0A= +#define CFG_DCSHIFT 6=0A= +#define CFG_IB 0x00000020 /* Instruction cache line size */=0A= +#define CFG_DB 0x00000010 /* Data cache line size */=0A= +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */=0A= +#elif defined(CPU_R32438) || defined(CPU_R32434)=0A= +#define CFG_MM 0x00060000 /* write buffer Merge Mode */=0A= +#define CFG_BM 0x00010000 /* Burst Mode */=0A= +#define CFG_BE 0x00008000 /* Big Endian */=0A= +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */=0A= +#endif=0A= +=0A= +/*=0A= + * Primary cache mode=0A= + */=0A= +#if defined(CPU_R32364)=0A= +#define CFG_C_NCHRNT_WT_NWA 0=0A= +#define CFG_C_NCHRNT_WT 1=0A= +#define CFG_C_UNCACHED 2=0A= +#define CFG_C_NCHRNT_WB 3=0A= +=0A= +/* Cache Operations */=0A= +#define Index_Invalidate_I 0x0 /* 0 0 */=0A= +#define Index_Writeback_Inv_D 0x1 /* 0 1 */=0A= +#define Index_Invalidate_SI 0x2 /* 0 2 */=0A= +#define Index_Writeback_Inv_SD 0x3 /* 0 3 */=0A= +#define Index_Load_Tag_I 0x4 /* 1 0 */=0A= +#define Index_Load_Tag_D 0x5 /* 1 1 */=0A= +#define Index_Load_Tag_SI 0x6 /* 1 2 */=0A= +#define Index_Load_Tag_SD 0x7 /* 1 3 */=0A= +#define Index_Store_Tag_I 0x8 /* 2 0 */=0A= +#define Index_Store_Tag_D 0x9 /* 2 1 */=0A= +#define Index_Store_Tag_SI 0xA /* 2 2 */=0A= +#define Index_Store_Tag_SD 0xB /* 2 3 */=0A= +#define Create_Dirty_Exc_D 0xD /* 3 1 */=0A= +#define Create_Dirty_Exc_SD 0xF /* 3 3 */=0A= +#define Hit_Invalidate_I 0x10 /* 4 0 */=0A= +#define Hit_Invalidate_D 0x11 /* 4 1 */=0A= +#define Hit_Invalidate_SI 0x12 /* 4 2 */=0A= +#define Hit_Invalidate_SD 0x13 /* 4 3 */=0A= +#define Hit_Writeback_Inv_D 0x15 /* 5 1 */=0A= +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */=0A= +#define Fill_I 0x14 /* 5 0 */=0A= +#define Hit_Writeback_D 0x19 /* 6 1 */=0A= +#define Hit_Writeback_SD 0x1B /* 6 3 */=0A= +#define Hit_Writeback_I 0x18 /* 6 0 */=0A= +#define Hit_Set_Virtual_SI 0x1E /* 7 2 */=0A= +#define Hit_Set_Virtual_SD 0x1F /* 7 3 */=0A= +#define CFG_EW32 0x00040000 /* 32 bit */=0A= +#elif defined(CPU_R32438) || defined(CPU_R32434)=0A= +#define CFG_C_UNCACHED 2=0A= +#define CFG_C_NCHRNT_WB 3=0A= +=0A= +/* Cache Operations */=0A= +#define Index_Invalidate_I 0x0 /* 0 0 */=0A= +#define Index_Invalidate_D 0x1 /* 0 0 */=0A= +#define Index_Load_Tag_I 0x4 /* 1 0 */=0A= +#define Index_Load_Tag_D 0x5 /* 1 1 */=0A= +#define Index_Store_Tag_I 0x8 /* 2 0 */=0A= +#define Index_Store_Tag_D 0x9 /* 2 1 */=0A= +#define Hit_Invalidate_I 0x10 /* 4 0 */=0A= +#define Hit_Invalidate_D 0x11 /* 4 1 */=0A= +#define Fill_I 0x14 /* 5 0 */=0A= +#define Fetch_Lock_I 0x1C /* 7 0 */=0A= +#define Fetch_Lock_D 0x1D /* 7 1 */=0A= +#define CFG_EW32 0x00040000 /* 32 bit */=0A= +#endif=0A= +=0A= +/*=0A= +** TLB resource defines=0A= +*/=0A= +=0A= +#define N_TLB_ENTRIES 16=0A= +#define TLBHI_VPN2MASK 0xffffe000=0A= +#define TLBHI_PIDMASK 0x000000ff=0A= +#define TLBHI_NPID 256=0A= +=0A= +#define TLBLO_PFNMASK 0x03ffffc0=0A= +#define TLBLO_PFNSHIFT 6=0A= +#define TLBLO_D 0x00000004 /* writeable */=0A= +#define TLBLO_V 0x00000002 /* valid bit */=0A= +#define TLBLO_G 0x00000001 /* global access bit */=0A= +#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */=0A= +#define TLBLO_CSHIFT 3=0A= +=0A= +#define TLBLO_UNCACHED (CFG_C_UNCACHED << TLBLO_CSHIFT)=0A= +#define TLBLO_NCHRNT_WT_NWA (CFG_C_NCHRNT_WT_NWA << TLBLO_CSHIFT)=0A= +#if defined(CPU_R32364)=0A= +#define TLBLO_NCHRNT_WT (CFG_C_NCHRNT_WT << TLBLO_CSHIFT)=0A= +#define TLBLO_NCHRNT_WB (CFG_C_NCHRNT_WB << TLBLO_CSHIFT)=0A= +#endif=0A= +=0A= +#define TLBINX_PROBE 0x80000000=0A= +#define TLBINX_INXMASK 0x0000003f=0A= +=0A= +#define TLBRAND_RANDMASK 0x0000003f=0A= +=0A= +#define TLBCTXT_BASEMASK 0xff800000=0A= +#define TLBCTXT_BASESHIFT 23=0A= +=0A= +#define TLBCTXT_VPN2MASK 0x007ffff0=0A= +#define TLBCTXT_VPN2SHIFT 4=0A= +=0A= +#define TLBPGMASK_MASK 0x01ffe000=0A= +=0A= +#define SR_CUMASK 0xf0000000 /* coproc usable bits */=0A= +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */=0A= +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */=0A= +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */=0A= +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */=0A= +=0A= +/* #define SR_PE 0x00100000*/ /* cache parity error */=0A= +=0A= +#if defined(CPU_R32364)=0A= +#define SR_RE 0X02000000 /* Reverse Endianness */=0A= +#define SR_DL 0x01000000 /* Data Cache Locking */=0A= +#define SR_IL 0x00800000 /* Instruction Cache Locking */=0A= +=0A= +#define SR_BEV 0x00400000 /* Use boot exception vectors */=0A= +#define SR_SR 0x00100000 /* Soft reset */=0A= +#define SR_CH 0x00040000 /* Cache hit */=0A= +#define SR_CE 0x00020000 /* Use cache ECC */=0A= +#define SR_DE 0x00010000 /* Disable cache exceptions */=0A= +=0A= +#elif defined(CPU_R32438) || defined(CPU_R32434)=0A= +#define SR_RP 0X08000000 /* Reduced Power mode */=0A= +=0A= +#define SR_RE 0X02000000 /* Reverse Endianness */=0A= +=0A= +#define SR_BEV 0x00400000 /* Use boot exception vectors */=0A= +#define SR_TS 0X00200000 /* TLB Shutdown */=0A= +#define SR_SR 0x00100000 /* Soft reset */=0A= +#define SR_NMI 0X00080000 /* NMI */=0A= +#endif=0A= +/*=0A= +** status register interrupt masks and bits=0A= +*/=0A= +=0A= +#define SR_IMASK 0x0000ff00 /* Interrupt mask */=0A= +#define SR_IMASK8 0x00000000 /* mask level 8 */=0A= +#define SR_IMASK7 0x00008000 /* mask level 7 */=0A= +#define SR_IMASK6 0x0000c000 /* mask level 6 */=0A= +#define SR_IMASK5 0x0000e000 /* mask level 5 */=0A= +#define SR_IMASK4 0x0000f000 /* mask level 4 */=0A= +#define SR_IMASK3 0x0000f800 /* mask level 3 */=0A= +#define SR_IMASK2 0x0000fc00 /* mask level 2 */=0A= +#define SR_IMASK1 0x0000fe00 /* mask level 1 */=0A= +#define SR_IMASK0 0x0000ff00 /* mask level 0 */=0A= +=0A= +#define SR_IMASKSHIFT 8=0A= +=0A= +#define SR_IBIT8 0x00008000 /* bit level 8 */=0A= +#define SR_IBIT7 0x00004000 /* bit level 7 */=0A= +#define SR_IBIT6 0x00002000 /* bit level 6 */=0A= +#define SR_IBIT5 0x00001000 /* bit level 5 */=0A= +#define SR_IBIT4 0x00000800 /* bit level 4 */=0A= +#define SR_IBIT3 0x00000400 /* bit level 3 */=0A= +#define SR_IBIT2 0x00000200 /* bit level 2 */=0A= +#define SR_IBIT1 0x00000100 /* bit level 1 */=0A= +=0A= +#define SR_KSMASK 0x00000016 /* Kernel mode mask */=0A= +#define SR_KSUSER 0x00000000 /* User Mode */=0A= +#define SR_KSKERNEL 0x00000016 /* Kernel Mode */=0A= +=0A= +#define SR_ERL 0x00000004 /* Error level */=0A= +#define SR_EXL 0x00000002 /* Exception level */=0A= +#define SR_IE 0x00000001 /* Interrupts enabled */=0A= +#define NOT_SR_IEC 0xfffffffe /* assembler problem with li = ~SR_IEC */=0A= +=0A= +/*=0A= + * Cause Register=0A= + */=0A= +#define CAUSE_BD 0x80000000 /* Branch delay slot */=0A= +#define CAUSE_CEMASK 0x30000000 /* coprocessor error */=0A= +#define CAUSE_CESHIFT 28=0A= +#if defined(CPU_R32364)=0A= +#define CAUSE_IPE 0x04000000 /* Imprecise exception */=0A= +#define CAUSE_DW 0x02000000 /* Data watch */=0A= +#define CAUSE_IW 0x01000000 /* Instruction watch */=0A= +#elif defined(CPU_R32438) || defined(CPU_R32434)=0A= +#define CAUSE_IV 0x00800000 /* Interrupt Vector location */=0A= +#define CAUSE_WP 0x00400000 /* Watch Exception deferred */=0A= +#endif=0A= +=0A= +#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */=0A= +#define CAUSE_IPSHIFT 8=0A= +=0A= +/* Notice: Watch Exception if Exc. Code is 23 is not included in the = mask=0A= + * for R32364.=0A= + */=0A= +#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */=0A= +#define CAUSE_EXCSHIFT 2=0A= +=0A= +#ifndef XDS=0A= +/*=0A= +** Coprocessor 0 registers=0A= +*/=0A= +#define C0_INX $0 /* tlb index */=0A= +#define C0_RANDOM $1=0A= +#define C0_TLBLO0 $2 /* tlb entry low 0 */=0A= +#define C0_TLBLO1 $3 /* tlb entry low 1 */=0A= +#define C0_CTXT $4 /* tlb context */=0A= +#define C0_PAGEMASK $5 /* tlb page mask */=0A= +#define C0_WIRED $6 /* number of wired tlb entries */=0A= +=0A= +#define C0_BADVADDR $8 /* bad virtual address */=0A= +#define C0_COUNT $9 /* timer count */=0A= +#define C0_TLBHI $10 /* tlb entry hi */=0A= +#define C0_COMPARE $11 /* timer comparator */=0A= +#define C0_SR $12 /* status register */=0A= +#define C0_CAUSE $13 /* exception cause */=0A= +#define C0_EPC $14 /* exception pc */=0A= +#define C0_PRID $15 /* revision identifier */=0A= +#define C0_CONFIG $16 /* configuration register */=0A= +=0A= +#if defined(CPU_R32364)=0A= +#define C0_IWATCH $18 /* Instr brk pt Virtual add. */=0A= +#define C0_DWATCH $19 /* Data brk pt Virtual add. */=0A= +=0A= +#define C0_IEPC $22 /* Imprecise Exception pc */=0A= +#define C0_DEPC $23 /* Debug Exception pc */=0A= +#define C0_DEBUG $24 /* Debug control/status reg */=0A= +=0A= +#define C0_ECC $26 /* primary cache Parity control */=0A= +#define C0_CACHEERR $27 /* cache error status */=0A= +#define C0_TAGLO $28 /* cache tag lo */=0A= +#define C0_ERRPC $30 /* cache error pc */=0A= +#elif defined(CPU_R32438) || defined(CPU_R32434)=0A= +#define C0_WATCHLO $18 /* Watchpoint address (low) */=0A= +#define C0_WATCHHI $19 /* Watchpoint address (high) */=0A= +=0A= +#define C0_DEBUG $23 /* Debug control/status reg */=0A= +#define C0_DEPC $24 /* Debug Exception pc */=0A= +=0A= +#define C0_ERRCTL $26 /* Cache Error Control */=0A= +#define C0_TAGLO $28 /* Cache Tag Lo */=0A= +#define C0_ERRPC $30 /* Cache Error PC */=0A= +#define C0_DESAVE $31 /* Debug scratchpad reg. */=0A= +#endif =0A= +=0A= +#endif=0A= +#endif /* defined(__IDTCPU_H__) */=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/idthdr.h = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/idthdr.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/idthdr.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/idthdr.h = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,53 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Some macros. Though they are already defined else where in the = linux=0A= + * tree, they are once again declared here for the ease of syncing = up with=0A= + * IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef XDS=0A= +=0A= +#define FRAME(name,frm_reg,offset,ret_reg) \=0A= + .globl name; \=0A= + .ent name; \=0A= +name:; \=0A= + .frame frm_reg,offset,ret_reg=0A= +=0A= +#define ENDFRAME(name) .end name=0A= +=0A= +#else=0A= +=0A= +#define FRAME(name,frm_reg,offset,ret_reg) \=0A= +name:=0A= +=0A= +#define ENDFRAME(name)=0A= +=0A= +#endif=0A= +=0A= +=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/image.lds.in = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/image.lds.in=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/image.lds.in = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/image.lds.in = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D IMSTART;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32434/EB434/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D BSS_START;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/iregdef.h = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/iregdef.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/iregdef.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/iregdef.h = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,274 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT CPU register definitions. Though the registers are already = defined=0A= + * under asm directory, they are once again declared here for the = ease of=0A= + * syncing up with IDT bootloader code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifdef CLANGUAGE=0A= +struct ireg_desc {=0A= + char *ptr_field_name; /* field name */=0A= + short num_digits; /* number ofdigits to display */=0A= + short num_spaces; /* number of spaces to follow */=0A= + reg_t fld_mask; /* mask to extract value of field */=0A= + int fld_shift; /* shift amount to position field */=0A= + short cpu;=0A= + char *CONST *ptr_enum_list; /* ptr to an enumeration list */=0A= + };=0A= +=0A= +/*=0A= +** reg_name - structure that gives the reg. name, alt. reg name=0A= +** the reg index for fetching the value, the number=0A= +** of spaces req. so a tabular display will align=0A= +** a pointer to a structure defining the fields if=0A= +** required and a flag for the output type.=0A= +*/=0A= +struct reg_name {=0A= + char *register_name;=0A= + char *alt_reg_name;=0A= + short reg_index;=0A= + short space_pad;=0A= + CONST struct ireg_desc *ptr_reg_desc_flds;=0A= + unsigned char format_type;=0A= + unsigned char print_type;=0A= + short reg_group;=0A= + short cpu;=0A= + };=0A= +=0A= +/* print format specifiers */=0A= +#define PRT_HEX 0=0A= +#define PRT_SGL 1=0A= +#define PRT_DBL 2=0A= +=0A= +/* register group classifiers */=0A= +#define GRP_CPU 0x0001=0A= +#define GRP_FPR 0x0002=0A= +#define GRP_FPS 0x0004=0A= +#define GRP_FPD 0x0008=0A= +#define GRP_CP0 0x0010=0A= +#define GRP_CP0R 0x0020=0A= +#endif=0A= +=0A= +/*=0A= +** register names=0A= +*/=0A= +#define r0 $0=0A= +#define r1 $1=0A= +#define r2 $2=0A= +#define r3 $3=0A= +#define r4 $4=0A= +#define r5 $5=0A= +#define r6 $6=0A= +#define r7 $7=0A= +#define r8 $8=0A= +#define r9 $9=0A= +#define r10 $10=0A= +#define r11 $11=0A= +#define r12 $12=0A= +#define r13 $13=0A= +#define r14 $14=0A= +#define r15 $15=0A= +#define r16 $16=0A= +#define r17 $17=0A= +#define r18 $18=0A= +#define r19 $19=0A= +#define r20 $20=0A= +#define r21 $21=0A= +#define r22 $22=0A= +#define r23 $23=0A= +#define r24 $24=0A= +#define r25 $25=0A= +#define r26 $26=0A= +#define r27 $27=0A= +#define r28 $28=0A= +#define r29 $29=0A= +#define r30 $30=0A= +#define r31 $31=0A= +=0A= +#define zero $0 /* wired zero */=0A= +#define AT $at /* assembler temp */=0A= +#define v0 $2 /* return value */=0A= +#define v1 $3=0A= +#define a0 $4 /* argument registers a0-a3 */=0A= +#define a1 $5=0A= +#define a2 $6=0A= +#define a3 $7=0A= +#define t0 $8 /* caller saved t0-t9 */=0A= +#define t1 $9=0A= +#define t2 $10=0A= +#define t3 $11=0A= +#define t4 $12=0A= +#define t5 $13=0A= +#define t6 $14=0A= +#define t7 $15=0A= +#define s0 $16 /* callee saved s0-s8 */=0A= +#define s1 $17=0A= +#define s2 $18=0A= +#define s3 $19=0A= +#define s4 $20=0A= +#define s5 $21=0A= +#define s6 $22=0A= +#define s7 $23=0A= +#define t8 $24=0A= +#define t9 $25=0A= +#define k0 $26 /* kernel usage */=0A= +#define k1 $27 /* kernel usage */=0A= +#define gp $28 /* sdata pointer */=0A= +#define sp $29 /* stack pointer */=0A= +#define s8 $30 /* yet another saved reg for the callee */=0A= +#define fp $30 /* frame pointer - this is being phased out by MIPS = */=0A= +#define ra $31 /* return address */=0A= +=0A= +/*=0A= +** relative position of registers in save reg area=0A= +*/=0A= +#define R_R0 0=0A= +#define R_R1 1=0A= +#define R_R2 2=0A= +#define R_R3 3=0A= +#define R_R4 4=0A= +#define R_R5 5=0A= +#define R_R6 6=0A= +#define R_R7 7=0A= +#define R_R8 8=0A= +#define R_R9 9=0A= +#define R_R10 10=0A= +#define R_R11 11=0A= +#define R_R12 12=0A= +#define R_R13 13=0A= +#define R_R14 14=0A= +#define R_R15 15=0A= +#define R_R16 16=0A= +#define R_R17 17=0A= +#define R_R18 18=0A= +#define R_R19 19=0A= +#define R_R20 20=0A= +#define R_R21 21=0A= +#define R_R22 22=0A= +#define R_R23 23=0A= +#define R_R24 24=0A= +#define R_R25 25=0A= +#define R_R26 26=0A= +#define R_R27 27=0A= +#define R_R28 28=0A= +#define R_R29 29=0A= +#define R_R30 30=0A= +#define R_R31 31=0A= +#define NCLIENTREGS 32=0A= +#define R_EPC 32=0A= +#define R_MDHI 33=0A= +#define R_MDLO 34=0A= +#define R_SR 35=0A= +#define R_CAUSE 36=0A= +#define R_TLBHI 37=0A= +#define R_TLBLO0 38=0A= +#define R_BADVADDR 39=0A= +#define R_INX 40=0A= +#define R_RAND 41=0A= +#define R_CTXT 42=0A= +#define R_EXCTYPE 43=0A= +#define R_MODE 44=0A= +#define R_PRID 45=0A= +#define R_TLBLO1 46=0A= +#define R_PAGEMASK 47=0A= +#define R_WIRED 48=0A= +#define R_COUNT 49=0A= +#define R_COMPARE 50=0A= +#define R_CONFIG 51=0A= +#if defined(CPU_R32434)=0A= +#define R_WATCHLO 52=0A= +#define R_WATCHHI 53=0A= +#elif defined(CPU_R32364)=0A= +#define R_IWATCH 52=0A= +#define R_DWATCH 53=0A= +#define R_ECC 54=0A= +#define R_CACHEERR 55=0A= +#endif=0A= +#define R_TAGLO 56=0A= +#define R_TAGHI 57=0A= +#define R_ERRPC 58=0A= +=0A= +#define NREGS 59=0A= +=0A= +#if __mips >=3D 3=0A= +=0A= +#define R_SZ 8=0A= +#ifndef CLANGUAGE=0A= +#define sreg sd=0A= +#define lreg ld=0A= +#define rmfc0 mfc0=0A= +#define rmtc0 mtc0=0A= +#endif=0A= +=0A= +#else=0A= +=0A= +#define R_SZ 4=0A= +#ifndef CLANGUAGE=0A= +#define sreg sw=0A= +#define lreg lw=0A= +#define rmfc0 mfc0=0A= +#define rmtc0 mtc0=0A= +#endif=0A= +=0A= +#endif=0A= +=0A= +/*=0A= +** For those who like to think in terms of the compiler names for the = regs=0A= +*/=0A= +#define R_ZERO R_R0=0A= +#define R_AT R_R1=0A= +#define R_V0 R_R2=0A= +#define R_V1 R_R3=0A= +#define R_A0 R_R4=0A= +#define R_A1 R_R5=0A= +#define R_A2 R_R6=0A= +#define R_A3 R_R7=0A= +#define R_T0 R_R8=0A= +#define R_T1 R_R9=0A= +#define R_T2 R_R10=0A= +#define R_T3 R_R11=0A= +#define R_T4 R_R12=0A= +#define R_T5 R_R13=0A= +#define R_T6 R_R14=0A= +#define R_T7 R_R15=0A= +#define R_S0 R_R16=0A= +#define R_S1 R_R17=0A= +#define R_S2 R_R18=0A= +#define R_S3 R_R19=0A= +#define R_S4 R_R20=0A= +#define R_S5 R_R21=0A= +#define R_S6 R_R22=0A= +#define R_S7 R_R23=0A= +#define R_T8 R_R24=0A= +#define R_T9 R_R25=0A= +#define R_K0 R_R26=0A= +#define R_K1 R_R27=0A= +#define R_GP R_R28=0A= +#define R_SP R_R29=0A= +#define R_FP R_R30=0A= +#define R_RA R_R31=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/Makefile = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/Makefile = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,134 @@=0A= +#######################################################################= ########=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile create a compressed zImage or Rommable rImage=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +#=0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +# =0A= +#######################################################################= ########=0A= +=0A= +#######################################################################= ########=0A= +# The following is taken from IDT/Sim Makefile=0A= +#######################################################################= ######=0A= +TARGET=3D434=0A= +TARGETDIR=3DS434=0A= +=0A= +#=0A= +# following refers to memory type in use in eval board and if more = than one=0A= +# then the order is implied. These are values for the switch = MEMCFG.=0A= +#=0A= +SRAM_ONLY=3D1=0A= +SDRAM_ONLY=3D2=0A= +SRAM_N_SDRAM=3D3=0A= +SDRAM_N_SRAM=3D4=0A= +=0A= +# following refers to size of the DRAM space.=0A= +# These are values for the switch DRAMSZ.=0A= +=0A= +MB32=3D1=0A= +MB64=3D2=0A= +MB128=3D3=0A= +MB32SO=3D4=0A= +=0A= +MACH=3D -DEB434 -DS434 -DCPU_R32434 -DMIPSEL -DINET = -DMEMCFG=3D$(SDRAM_ONLY) -DDRAMSZ=3D$(MB32) -DIDTSIM -DMHZ=3D$(MHZ) = -DNVRAM_RTC -DUSE_SPI=0A= +COMMSWITCHES =3D $(MACH)=0A= +#***************** END IDT/Sim Makefile = ##################################### =0A= +ZDEBUG=3D1=0A= +export ZDEBUG=0A= +=0A= +# working space for gunzip:=0A= +FREE_RAM :=3D 0x80C00000=0A= +END_RAM :=3D 0x80E00000=0A= +=0A= +KERNELCONFIG :=3D $(TOPDIR)/.config=0A= +include $(KERNELCONFIG)=0A= +=0A= +SIZE =3D $(CROSS_COMPILE)size=0A= +=0A= +O_FORMAT =3D $(shell $(OBJDUMP) -i | head -2 | grep elf32)=0A= +=0A= +SYSTEM :=3D $(TOPDIR)/vmlinux=0A= +ZBSS :=3D 0x800A0000=0A= +=0A= +ZIMSTART :=3D $(CONFIG_IDT_ZIMAGE_ADDR)=0A= +RIMSTART :=3D 0x9FC00000=0A= +=0A= +LOADADDR :=3D 0x$(shell $(NM) $(SYSTEM) | grep "A _text" |cut -f1 = -d' ')=0A= +KERNEL_ENTRY :=3D $(shell $(OBJDUMP) -f $(SYSTEM) | sed -n -e = 's/^start address //p')=0A= +=0A= +#######################################################################= #############=0A= +ZIMFLAGS =3D s/IMSTART/$(ZIMSTART)/;s/BSS_START/$(ZBSS)/=0A= +RIMFLAGS =3D s/IMSTART/$(RIMSTART)/;s/BSS_START/$(ZBSS)/=0A= +CFLAGS :=3D -fno-pic -nostdinc -G 0 -mno-abicalls -fno-pic -pipe = -I$(TOPDIR)/include=0A= +AFLAGS :=3D -D__ASSEMBLY__ $(CFLAGS)=0A= +=0A= +#######################################################################= #############=0A= +OBJECTS=3D $(obj)/piggy.o $(obj)/head.o $(obj)/misc.o=0A= +ifneq ($(ZDEBUG),0)=0A= +OBJECTS +=3D $(obj)/uart16550.o=0A= +endif=0A= +=0A= +$(obj)/zImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)=0A= + @sed "$(ZIMFLAGS)" < $< > $@=0A= +=0A= +$(obj)/rImage.lds: $(obj)/image.lds.in $(KERNELCONFIG)=0A= + @sed "$(RIMFLAGS)" < $< > $@=0A= +=0A= +$(obj)/piggy.o: $(SYSTEM) $(obj)/Makefile=0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(SYSTEM) = $(SYSTEM).bin=0A= + gzip -f -9 < $(SYSTEM).bin > $(SYSTEM).gz=0A= + echo "O_FORMAT: " $(O_FORMAT); =0A= + $(LD) -r -b binary --oformat $(O_FORMAT) -o $(obj)/piggy.o = $(SYSTEM).gz=0A= + rm -f $(SYSTEM).bin $(SYSTEM).gz=0A= +=0A= +$(obj)/head.o: $(obj)/head.S $(SYSTEM) $(obj)/Makefile=0A= + $(CC) $(AFLAGS) -DKERNEL_ENTRY=3D$(KERNEL_ENTRY) -c $(obj)/head.S -o = $(obj)/head.o=0A= +=0A= +$(obj)/misc.o: $(obj)/misc.c $(obj)/Makefile=0A= + $(CC) $(CFLAGS) -DLOADADDR=3D$(LOADADDR) -DFREE_RAM=3D$(FREE_RAM) = -DEND_RAM=3D$(END_RAM) \=0A= + -c $< -DZDEBUG=3D$(ZDEBUG) -o $(obj)/misc.o=0A= +=0A= +$(obj)/uart16550.o: $(obj)/uart16550.c $(KERNELCONFIG)=0A= + $(CC) $(CFLAGS) -c $< -o $(obj)/uart16550.o=0A= +=0A= +$(obj)/csu_idt.o: $(obj)/csu_idt.S Makefile $(SYSTEM)=0A= + $(CC) $(AFLAGS) $(COMMSWITCHES) -c $< -o $(obj)/csu_idt.o=0A= +=0A= +zImage: $(obj)/zImage.lds $(SYSTEM) $(OBJECTS)=0A= + $(LD) -T$(obj)/zImage.lds -o $(TOPDIR)/zImage $(OBJECTS)=0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/zImage = $(TOPDIR)/zImage.bin=0A= + $(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 \=0A= + $(TOPDIR)/zImage.bin $(TOPDIR)/zImage.prm=0A= + $(SIZE) $(TOPDIR)/zImage |awk -F" " '{ print $$4 "\t" $$5 }' > = $(TOPDIR)/zImage.size=0A= + rm -f *.o=0A= +=0A= +rImage: $(obj)/rImage.lds $(SYSTEM) $(OBJECTS) $(obj)/csu_idt.o=0A= + @rm -f $(TOPDIR)/*.prm=0A= + $(LD) -T$(obj)/rImage.lds -o $(TOPDIR)/rImage $(obj)/csu_idt.o = $(OBJECTS) =0A= + $(OBJCOPY) -S -O binary -R .note -R .comment $(TOPDIR)/rImage = $(TOPDIR)/rImage.bin=0A= + $(OBJCOPY) -I binary -S -O srec --srec-forceS3 --srec-len=3D32 = --change-start=3D0x00000000 \=0A= + $(TOPDIR)/rImage.bin $(TOPDIR)/rImage.prm=0A= + $(SIZE) $(TOPDIR)/rImage |awk -F" " '{ print $$4 "\t" $$5 }' > = $(TOPDIR)/rImage.size=0A= + rm -f *.o=0A= +clean:=0A= + rm -f *.o $(TOPDIR)/zImage* $(TOPDIR)/rImage* $(TOPDIR)/*.prm = $(TOPDIR)/rImage.size $(TOPDIR)/zImage.size=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/misc.c = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/misc.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/misc.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/misc.c 2006-03-09 = 16:25:50.000000000 -0800=0A= @@ -0,0 +1,339 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Code to un-compress linux image=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +=0A= +/*=0A= + * gzip declarations=0A= + */=0A= +#define OF(args) args=0A= +#define STATIC static=0A= +#define memzero(s, n) memset ((s), 0, (n))=0A= +typedef unsigned char uch;=0A= +typedef unsigned short ush;=0A= +typedef unsigned long ulg;=0A= +#define WSIZE 0x8000 /* Window size must be at least 32k, */=0A= + /* and a power of two */=0A= +static uch *inbuf; /* input buffer */=0A= +static uch window[WSIZE]; /* Sliding window buffer */=0A= +=0A= +/* gzip flag byte */=0A= +#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */=0A= +#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part = gzip file */=0A= +#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */=0A= +#define ORIG_NAME 0x08 /* bit 3 set: original file name present = */=0A= +#define COMMENT 0x10 /* bit 4 set: file comment present */=0A= +#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */=0A= +#define RESERVED 0xC0 /* bit 6,7: reserved */=0A= +=0A= +=0A= +static unsigned insize; /* valid bytes in inbuf */=0A= +static unsigned inptr; /* index of next byte to be processed in inbuf = */=0A= +static unsigned outcnt; /* bytes in output buffer */=0A= +=0A= +void variable_init(void);=0A= +#if ZDEBUG > 0=0A= +static void puts(const char *);=0A= +extern void putc_init(void);=0A= +extern void putc(unsigned char c);=0A= +#endif=0A= +static int fill_inbuf(void);=0A= +static void flush_window(void);=0A= +static void error(char *m);=0A= +static void gzip_mark(void **);=0A= +static void gzip_release(void **);=0A= +=0A= +extern char input_data[];=0A= +=0A= +extern char input_data_end[];=0A= +=0A= +#if ZDEBUG > 0=0A= +void int2hex(unsigned long val)=0A= +{=0A= + unsigned char buf[10];=0A= + int i;=0A= + for (i =3D 7; i >=3D 0; i--) {=0A= + buf[i] =3D "0123456789ABCDEF"[val & 0x0F];=0A= + val >>=3D 4;=0A= + }=0A= + buf[8] =3D '\0';=0A= + puts(buf);=0A= +}=0A= +#endif=0A= +=0A= +static unsigned long byte_count;=0A= +=0A= +int get_byte(void)=0A= +{=0A= +#if ZDEBUG > 1=0A= + static int printCnt;=0A= +#endif=0A= + unsigned char c =3D (inptr < insize ? inbuf[inptr++] : = fill_inbuf());=0A= + byte_count++;=0A= + =0A= +#if ZDEBUG > 1=0A= + if (printCnt++ < 32) {=0A= + puts("byte count =3D ");=0A= + int2hex(byte_count);=0A= + puts(" byte val =3D ");=0A= + int2hex(c);=0A= + puts("\n");=0A= + }=0A= +#endif=0A= + return c;=0A= +}=0A= +=0A= +/* Diagnostic functions */=0A= +#ifdef DEBUG=0A= +# define Assert(cond,msg) {if(!(cond)) error(msg);}=0A= +# define Trace(x) fprintf x=0A= +# define Tracev(x) {if (verbose) fprintf x ;}=0A= +# define Tracevv(x) {if (verbose>1) fprintf x ;}=0A= +# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}=0A= +# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}=0A= +#else=0A= +# define Assert(cond,msg)=0A= +# define Trace(x)=0A= +# define Tracev(x)=0A= +# define Tracevv(x)=0A= +# define Tracec(c,x)=0A= +# define Tracecv(c,x)=0A= +#endif=0A= +=0A= +/*=0A= + * This is set up by the setup-routine at boot-time=0A= + */=0A= +=0A= +static long bytes_out;=0A= +static uch *output_data;=0A= +static unsigned long output_ptr;=0A= +=0A= +=0A= +static void *malloc(int size);=0A= +static void free(void *where);=0A= +static void error(char *m);=0A= +static void gzip_mark(void **);=0A= +static void gzip_release(void **);=0A= +=0A= +static unsigned long free_mem_ptr;=0A= +static unsigned long free_mem_end_ptr;=0A= +=0A= +#include "../../../../../../lib/inflate.c"=0A= +=0A= +static void *malloc(int size)=0A= +{=0A= + void *p;=0A= + =0A= + if (size < 0)=0A= + error("Malloc error\n");=0A= + if (free_mem_ptr <=3D 0) error("Memory error\n");=0A= + =0A= + free_mem_ptr =3D (free_mem_ptr + 3) & ~3; /* Align */=0A= + =0A= + p =3D (void *) free_mem_ptr;=0A= + free_mem_ptr +=3D size;=0A= + =0A= + if (free_mem_ptr >=3D free_mem_end_ptr)=0A= + error("\nOut of memory\n");=0A= + =0A= + return p;=0A= +}=0A= +=0A= +static void free(void *where)=0A= +{ /* Don't care */=0A= +}=0A= +=0A= +static void gzip_mark(void **ptr)=0A= +{=0A= + *ptr =3D (void *) free_mem_ptr;=0A= +}=0A= +=0A= +static void gzip_release(void **ptr)=0A= +{=0A= + free_mem_ptr =3D (long) *ptr;=0A= +}=0A= +#if ZDEBUG > 0=0A= +static void puts(const char *s)=0A= +{=0A= + while (*s) {=0A= + if (*s =3D=3D 10)=0A= + putc(13);=0A= + putc(*s++);=0A= + }=0A= +}=0A= +#endif=0A= +=0A= +void *memset(void *s, int c, size_t n)=0A= +{=0A= + int i;=0A= + char *ss =3D (char *) s;=0A= + =0A= + for (i =3D 0; i < n; i++)=0A= + ss[i] =3D c;=0A= + return s;=0A= +}=0A= +=0A= +void *memcpy(void *__dest, __const void *__src, size_t __n)=0A= +{=0A= + int i;=0A= + char *d =3D (char *) __dest, *s =3D (char *) __src;=0A= + =0A= + for (i =3D 0; i < __n; i++)=0A= + d[i] =3D s[i];=0A= + return __dest;=0A= +}=0A= +=0A= +/* = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=0A= + * Fill the input buffer. This is called only when the buffer is = empty=0A= + * and at least one byte is really needed.=0A= + */=0A= +static int fill_inbuf(void)=0A= +{=0A= + if (insize !=3D 0) {=0A= + error("ran out of input data\n");=0A= + }=0A= + =0A= + inbuf =3D input_data;=0A= + insize =3D &input_data_end[0] - &input_data[0];=0A= + inptr =3D 1;=0A= + return inbuf[0];=0A= +}=0A= +=0A= +/* = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=0A= + * Write the output window window[0..outcnt-1] and update crc and = bytes_out.=0A= + * (Used for the decompressed data only.)=0A= + */=0A= +static void flush_window(void)=0A= +{=0A= + ulg c =3D crc; /* temporary variable */=0A= + unsigned n;=0A= + uch *in, *out, ch;=0A= + =0A= + in =3D window;=0A= + out =3D &output_data[output_ptr];=0A= + for (n =3D 0; n < outcnt; n++) {=0A= + ch =3D *out++ =3D *in++;=0A= + c =3D crc_32_tab[((int) c ^ ch) & 0xff] ^ (c >> 8);=0A= + }=0A= + crc =3D c;=0A= + bytes_out +=3D (ulg) outcnt;=0A= + output_ptr +=3D (ulg) outcnt;=0A= + outcnt =3D 0;=0A= +}=0A= +=0A= +#if ZDEBUG > 0=0A= +void check_mem(void)=0A= +{=0A= + int i;=0A= + =0A= + puts("\ncplens =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(cplens[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\ncplext =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(cplext[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\nborder =3D ");=0A= + for (i =3D 0; i < 10; i++) {=0A= + int2hex(border[i]);=0A= + puts(" ");=0A= + }=0A= + puts("\n");=0A= +}=0A= +#endif=0A= +=0A= +static void error(char *x)=0A= +{=0A= +#if ZDEBUG > 1=0A= + check_mem();=0A= + puts("\n\n");=0A= + puts(x);=0A= + puts("byte_count =3D ");=0A= + int2hex(byte_count);=0A= + puts("\n");=0A= + puts("\n\n -- Error. System halted");=0A= +#endif=0A= + while (1); /* Halt */=0A= +}=0A= +=0A= +void variable_init(void)=0A= +{=0A= + byte_count =3D 0;=0A= + output_data =3D (char *) LOADADDR;=0A= + free_mem_ptr =3D FREE_RAM;=0A= + free_mem_end_ptr =3D END_RAM;=0A= +#if ZDEBUG > 1=0A= + puts("output_data 0x");=0A= + int2hex((unsigned long)output_data); puts("\n");=0A= + puts("free_mem_ptr 0x");=0A= + int2hex(free_mem_ptr); puts("\n");=0A= + puts("free_mem_end_ptr 0x");=0A= + int2hex(free_mem_end_ptr); puts("\n");=0A= + puts("input_data 0x");=0A= + int2hex((unsigned long)input_data); puts("\n");=0A= +#endif=0A= +}=0A= +=0A= +int decompress_kernel(void)=0A= +{=0A= +#if ZDEBUG > 0=0A= + putc_init();=0A= +#if ZDEBUG > 2=0A= + check_mem();=0A= +#endif=0A= +#endif=0A= + =0A= + variable_init();=0A= + =0A= + makecrc();=0A= +#if ZDEBUG > 0=0A= + puts("\n");=0A= + puts("Uncompressing Linux... \n");=0A= +#endif=0A= + gunzip(); // ...see inflate.c=0A= +#if ZDEBUG > 0=0A= + puts("Ok, booting the kernel.\n");=0A= +#endif=0A= + =0A= +#if ZDEBUG > 1=0A= + {=0A= + unsigned long *p =3D (unsigned long *)LOADADDR;=0A= + int2hex(p[0]); puts("\n");=0A= + int2hex(p[1]); puts("\n");=0A= + int2hex(p[2]); puts("\n");=0A= + int2hex(p[3]); puts("\n");=0A= + }=0A= +#endif=0A= + =0A= + return 0;=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/rImage.lds = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/rImage.lds=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/rImage.lds = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/rImage.lds = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D 0x9FC00000;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32434/EB434/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D 0x800A0000;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/s434.h = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/s434.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/s434.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/s434.h 2006-03-09 = 16:25:50.000000000 -0800=0A= @@ -0,0 +1,137 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Some useful macros.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#ifndef __S434__=0A= +#define __S434__=0A= +/******************************** D E F I N E S = *******************************/=0A= +=0A= +/*=0A= +** following defines simple and uniform to save and restore context=0A= +** when enrtering and leaving as assemblu language program when = memory=0A= +** and registers are both premiunm.=0A= +*/=0A= +#define SAVE_CNTXT \=0A= + subu sp, 64; \=0A= + sw t0, 60(sp); \=0A= + sw t1, 56(sp); \=0A= + sw t2, 52(sp); \=0A= + sw t3, 48(sp); \=0A= + sw t4, 44(sp); \=0A= + sw t5, 40(sp); \=0A= + sw t6, 36(sp); \=0A= + sw t7, 32(sp); \=0A= + sw t8, 28(sp); \=0A= + sw t9, 24(sp); \=0A= + sw a0, 20(sp); \=0A= + sw a1, 16(sp); \=0A= + sw a2, 12(sp); \=0A= + sw a3, 8(sp); \=0A= + sw ra, 4(sp)=0A= +=0A= +#define RSTR_CNTXT \=0A= + lw t0, 60(sp); \=0A= + lw t1, 56(sp); \=0A= + lw t2, 52(sp); \=0A= + lw t3, 48(sp); \=0A= + lw t4, 44(sp); \=0A= + lw t5, 40(sp); \=0A= + lw t6, 36(sp); \=0A= + lw t7, 32(sp); \=0A= + lw t8, 28(sp); \=0A= + lw t9, 24(sp); \=0A= + lw a0, 20(sp); \=0A= + lw a1, 16(sp); \=0A= + lw a2, 12(sp); \=0A= + lw a3, 8(sp); \=0A= + lw ra, 4(sp); \=0A= + add sp, 64=0A= +=0A= +/*=0A= +** Following define is to specify a maximum value for a software=0A= +** busy wait counter.=0A= +*/=0A= +/*=0A= +#define LP_CNT_100NS 1000 =0A= +#define LP_CNT_3S 1000000 =0A= +*/=0A= +=0A= +/*=0A= +** Following are other common timer definitions.=0A= +*/=0A= +#define DDR_BASE PHYS_TO_K1(0x18018000)=0A= +#define TIMER_BASE PHYS_TO_K1(0x18028000) =0A= +#define WTC_BASE PHYS_TO_K1(0x18030000)=0A= +#define INTERRUPT_BASE PHYS_TO_K1(0x18038000)=0A= +#define GPIO_BASE PHYS_TO_K1(0x18050000)=0A= +=0A= +#define TIMEOUT_COUNT 0x00000FFF=0A= +#define ENABLE_TIMER 0x1=0A= +#define DISABLE_TIMER 0x0=0A= +#define BIG_VALUE 0xFFFFFFFF=0A= +=0A= +/*=0A= +** following few lines define a macro DISPLAY=0A= +** which is used to write a set of 4 characters=0A= +** onto the EB434/435 LED.=0A= +*/=0A= +=0A= +#ifndef LED_BASE=0A= +=0A= +#define LED_BASE PHYS_TO_K1(0x19000000)=0A= +#define LED_DIGIT0 0x7=0A= +#define LED_DIGIT1 0x6=0A= +#define LED_DIGIT2 0x5=0A= +#define LED_DIGIT3 0x4=0A= +#define LED_CLEAR 0x0=0A= +=0A= +#endif=0A= +=0A= +#define DISPLAY(d0, d1, d2, d3) \=0A= + li t6, LED_BASE ;\=0A= + lb t7, LED_CLEAR(t6) ;\=0A= + nop ;\=0A= + li t7, (d0) & 0xff ;\=0A= + sb t7, LED_DIGIT0(t6) ;\=0A= + li t7, (d1) & 0xff ;\=0A= + sb t7, LED_DIGIT1(t6) ;\=0A= + li t7, (d2) & 0xff ;\=0A= + sb t7, LED_DIGIT2(t6) ;\=0A= + li t7, (d3) & 0xff ;\=0A= + sb t7, LED_DIGIT3(t6)=0A= +=0A= +#define LEDCLEAR() \=0A= + li t6, LED_BASE ;\=0A= + lb t7, LED_CLEAR(t6) ;\=0A= + nop=0A= +=0A= +#define DESTRUCTIVE 1=0A= +#define NONDESTRUCTIVE 0=0A= +=0A= +#endif=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/s434ram.h = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/s434ram.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/s434ram.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/s434ram.h = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,161 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * IDT EB434/435 DDR setup values.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +=0A= +#ifndef __S434RAM__=0A= +#define __S434RAM__=0A= +/******************************** D E F I N E S = *******************************/=0A= +=0A= +#define MB32 1=0A= +#define MB64 2=0A= +#define MB128 3=0A= +=0A= +#define DEV_CTL_BASE PHYS_TO_K1(0x18010000) /* device = controller regs */=0A= +#define DDR_CTL_BASE PHYS_TO_K1(0x18018010) /* DDR controller = regs */=0A= +=0A= +#define DEV0_BASE 0x1FC00000=0A= +#define DEV0_MASK 0xFFC00000=0A= +#define DEV1_BASE 0x1A000000=0A= +#define DEV1_MASK 0xFE000000=0A= +#define DEV2_BASE 0x19000000=0A= +#define DEV2_MASK 0xFF000000=0A= +#define DEV3_BASE 0x00000000=0A= +#define DEV3_MASK 0x00000000=0A= +=0A= +#if MHZ =3D=3D 100000000=0A= +#define DEV0_CTRL 0x04108324 /* 8-bit devices = */=0A= +#define DEV0_TC 0x00000000=0A= +#define DEV1_CTRL 0x04108324 /* 8-bit devices = */=0A= +#define DEV1_TC 0x00000000=0A= +#define DEV2_CTRL 0x04108324 /* 8-bit devices = */=0A= +#define DEV2_TC 0x00000000=0A= +#define DEV3_CTRL 0x0FFFFFF4 /* 8-bit devices = */=0A= +#define DEV3_TC 0x00001FFF=0A= +=0A= +#elif MHZ =3D=3D 133000000=0A= +#define DEV0_CTRL 0x04108324 /* 8-bit devices = */=0A= +#define DEV0_TC 0x00000000=0A= +#define DEV1_CTRL 0x05208324 /* 8-bit devices = */=0A= +#define DEV1_TC 0x00000000=0A= +#define DEV2_CTRL 0x04108324 /* 8-bit devices = */=0A= +#define DEV2_TC 0x00000000=0A= +#define DEV3_CTRL 0x0FFFFFF4 /* 8-bit devices = */=0A= +#define DEV3_TC 0x00001FFF=0A= +=0A= +#elif MHZ =3D=3D 150000000=0A= +#define DEV0_CTRL 0x04108324 /* 8-bit devices = */=0A= +#define DEV0_TC 0x00000000=0A= +#define DEV1_CTRL 0x05208324 /* 8-bit devices = */=0A= +#define DEV1_TC 0x00000000=0A= +#define DEV2_CTRL 0x04108324 /* 8-bit devices = */=0A= +#define DEV2_TC 0x00000000=0A= +#define DEV3_CTRL 0x0FFFFFF4 /* 8-bit devices = */=0A= +#define DEV3_TC 0x00001FFF=0A= +=0A= +=0A= +#elif MHZ =3D=3D 175000000=0A= +#define DEV0_CTRL 0x04108324 /* 8-bit devices = */=0A= +#define DEV0_TC 0x00000000=0A= +#define DEV1_CTRL 0x05208324 /* 8-bit devices = */=0A= +#define DEV1_TC 0x00000000=0A= +#define DEV2_CTRL 0x04108324 /* 8-bit devices = */=0A= +#define DEV2_TC 0x00000000=0A= +#define DEV3_CTRL 0x0FFFFFF4 /* 8-bit devices = */=0A= +#define DEV3_TC 0x00001FFF=0A= +=0A= +#elif MHZ =3D=3D 200000000=0A= +#define DEV0_CTRL 0x05208324 /* 8-bit devices = */=0A= +#define DEV0_TC 0x00000000=0A= +#define DEV1_CTRL 0x06308324 /* 8-bit devices = */=0A= +#define DEV1_TC 0x00000000=0A= +#define DEV2_CTRL 0x05208324 /* 8-bit devices = */=0A= +#define DEV2_TC 0x00000000=0A= +#define DEV3_CTRL 0x0FFFFFF4 /* 8-bit devices = */=0A= +#define DEV3_TC 0x00001FFF=0A= +#endif=0A= +=0A= +#define DATA_PATTERN 0xA5A5A5A5=0A= +#define RCOUNT PHYS_TO_K1(0x18028030)=0A= +=0A= +#if DRAMSZ =3D=3D MB32=0A= +=0A= +#define DDR_BASE_VAL 0x00000000=0A= +#define DDR_MASK_VAL 0xFE000000=0A= +#define DDR_ABASE_VAL 0x08000000=0A= +#define DDR_AMASK_VAL 0x00000000=0A= +=0A= +#if MHZ =3D=3D 100000000=0A= +#define DDRC_VAL_NORMAL 0x82184800=0A= +#define DDRC_VAL_AT_INIT 0x02184800=0A= +#define DDR_REF_CMP_VAL 0x0000030c=0A= +#elif MHZ =3D=3D 133000000=0A= +#define DDRC_VAL_NORMAL 0x82984800=0A= +#define DDRC_VAL_AT_INIT 0x02984800=0A= +#define DDR_REF_CMP_VAL 0x0000040e=0A= +#elif MHZ =3D=3D 150000000=0A= +#define DDRC_VAL_NORMAL 0x82984800=0A= +#define DDRC_VAL_AT_INIT 0x02984800=0A= +#define DDR_REF_CMP_VAL 0x00000492=0A= +#elif MHZ =3D=3D 175000000=0A= +#define DDRC_VAL_NORMAL 0x82994800=0A= +#define DDRC_VAL_AT_INIT 0x02994800=0A= +#define DDR_REF_CMP_VAL 0x00000516=0A= +#elif MHZ =3D=3D 200000000=0A= +#define DDRC_VAL_NORMAL 0x82994800=0A= +#define DDRC_VAL_AT_INIT 0x02994800=0A= +#define DDR_REF_CMP_VAL 0x00000618=0A= +#else=0A= +#warning illegal value for MHZ=0A= +#endif=0A= +=0A= +#define DDR_REF_CMP_FAST 0x00000080=0A= +=0A= +#define DDR_CUST_NOP 0x0000003F=0A= +#define DDR_CUST_PRECHARGE 0x00000033=0A= +#define DDR_CUST_REFRESH 0x00000027=0A= +#define DDR_LD_MODE_REG 0x00000023=0A= +#define DDR_LD_EMODE_REG 0x00000063=0A= +=0A= +/* =0A= + * All generated addresses for DDR init during custom transactions are = shifted=0A= + * by two address lines - see spec for used DDR chip=0A= + */=0A= +#define DDR_PRECHARGE_OFFSET 0x00001000 /* 0x0400 - 9-bit page*/=0A= +#define DDR_EMODE_VAL 0x00000000 /* 0x0000 */=0A= +#define DDR_DLL_RES_MODE_VAL 0x00000584 /* 0x0161 - Reset DLL, CL2.5 = */=0A= +#define DDR_DLL_MODE_VAL 0x00000184 /* 0x0061 - CL2.5 */=0A= +=0A= +#define DELAY_200USEC 25000 /* not exactly */=0A= +=0A= +#else=0A= +#error "unrecognized dram size"=0A= +#endif=0A= +=0A= +#endif=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/uart16550.c = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/uart16550.c=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/uart16550.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/uart16550.c = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,154 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * UART code.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#define RC32434_REG_BASE 0xb8000000=0A= +#ifdef __MIPSEB__=0A= +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)=0A= +#else=0A= +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)=0A= +#endif=0A= +=0A= +#define BASE RC32434_UART0_BASE=0A= +#define MAX_BAUD (CONFIG_IDT_BOARD_FREQ / 16)=0A= +#define REG_OFFSET 0x4=0A= +=0A= +=0A= +#if (!defined(BASE) || !defined(MAX_BAUD) || !defined(REG_OFFSET))=0A= +#error You must define BASE, MAX_BAUD and REG_OFFSET in the = Makefile.=0A= +#endif=0A= +=0A= +#ifndef INIT_SERIAL_PORT=0A= +#define INIT_SERIAL_PORT 1=0A= +#endif=0A= +=0A= +#ifndef DEFAULT_BAUD=0A= +//#define DEFAULT_BAUD UART16550_BAUD_115200=0A= +#define DEFAULT_BAUD UART16550_BAUD_9600=0A= +#endif=0A= +#ifndef DEFAULT_PARITY=0A= +#define DEFAULT_PARITY UART16550_PARITY_NONE=0A= +#endif=0A= +#ifndef DEFAULT_DATA=0A= +#define DEFAULT_DATA UART16550_DATA_8BIT=0A= +#endif=0A= +#ifndef DEFAULT_STOP=0A= +#define DEFAULT_STOP UART16550_STOP_1BIT=0A= +#endif=0A= +=0A= +/* =3D=3D=3D END OF CONFIG =3D=3D=3D */=0A= +=0A= +typedef unsigned char uint8;=0A= +typedef unsigned int uint32;=0A= +=0A= +#define UART16550_BAUD_2400 2400=0A= +#define UART16550_BAUD_4800 4800=0A= +#define UART16550_BAUD_9600 9600=0A= +#define UART16550_BAUD_19200 19200=0A= +#define UART16550_BAUD_38400 38400=0A= +#define UART16550_BAUD_57600 57600=0A= +#define UART16550_BAUD_115200 115200=0A= +=0A= +#define UART16550_PARITY_NONE 0=0A= +#define UART16550_PARITY_ODD 0x08=0A= +#define UART16550_PARITY_EVEN 0x18=0A= +#define UART16550_PARITY_MARK 0x28=0A= +#define UART16550_PARITY_SPACE 0x38=0A= +=0A= +#define UART16550_DATA_5BIT 0x0=0A= +#define UART16550_DATA_6BIT 0x1=0A= +#define UART16550_DATA_7BIT 0x2=0A= +#define UART16550_DATA_8BIT 0x3=0A= +=0A= +#define UART16550_STOP_1BIT 0x0=0A= +#define UART16550_STOP_2BIT 0x4=0A= +=0A= +/* register offset */=0A= +#define OFS_RCV_BUFFER (0*REG_OFFSET)=0A= +#define OFS_TRANS_HOLD (0*REG_OFFSET)=0A= +#define OFS_SEND_BUFFER (0*REG_OFFSET)=0A= +#define OFS_INTR_ENABLE (1*REG_OFFSET)=0A= +#define OFS_INTR_ID (2*REG_OFFSET)=0A= +#define OFS_DATA_FORMAT (3*REG_OFFSET)=0A= +#define OFS_LINE_CONTROL (3*REG_OFFSET)=0A= +#define OFS_MODEM_CONTROL (4*REG_OFFSET)=0A= +#define OFS_RS232_OUTPUT (4*REG_OFFSET)=0A= +#define OFS_LINE_STATUS (5*REG_OFFSET)=0A= +#define OFS_MODEM_STATUS (6*REG_OFFSET)=0A= +#define OFS_RS232_INPUT (6*REG_OFFSET)=0A= +#define OFS_SCRATCH_PAD (7*REG_OFFSET)=0A= +=0A= +#define OFS_DIVISOR_LSB (0*REG_OFFSET)=0A= +#define OFS_DIVISOR_MSB (1*REG_OFFSET)=0A= +=0A= +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))=0A= +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) =3D = z)=0A= +=0A= +static void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 = stop)=0A= +{=0A= + /* disable interrupts */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x0);=0A= + UART16550_WRITE(OFS_INTR_ENABLE, 0);=0A= + =0A= + /* set up baud rate */=0A= + {=0A= + uint32 divisor;=0A= + =0A= + /* set DIAB bit */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x80);=0A= + =0A= + /* set divisor */=0A= + divisor =3D MAX_BAUD / baud;=0A= + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);=0A= + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);=0A= + =0A= + /* clear DIAB bit */=0A= + UART16550_WRITE(OFS_LINE_CONTROL, 0x0);=0A= + }=0A= + =0A= + /* set data format */=0A= + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);=0A= +}=0A= +=0A= +=0A= +void=0A= +putc_init(void)=0A= +{=0A= +#if INIT_SERIAL_PORT=0A= + Uart16550Init(DEFAULT_BAUD, DEFAULT_DATA, DEFAULT_PARITY, = DEFAULT_STOP);=0A= +#endif=0A= +}=0A= +=0A= +void=0A= +putc(unsigned char c)=0A= +{=0A= + while ((UART16550_READ(OFS_LINE_STATUS) &0x20) =3D=3D 0);=0A= + UART16550_WRITE(OFS_SEND_BUFFER, c);=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/zImage.lds = idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/zImage.lds=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/boot/zImage.lds = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/boot/zImage.lds = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,31 @@=0A= +OUTPUT_ARCH(mips)=0A= +ENTRY(zstartup)=0A= +SECTIONS=0A= +{=0A= + /* Read-only sections, merged into text segment: */=0A= + . =3D 0x9b000000;=0A= + .init : { *(.init) } =3D0=0A= + .text :=0A= + {=0A= + _ftext =3D . ;=0A= + *(.text)=0A= + *(.rodata)=0A= + *(.rodata1)=0A= + . =3D ALIGN(4096);=0A= + input_data =3D .;=0A= + arch/mips/idt-boards/rc32434/EB434/boot/piggy.o=0A= + input_data_end =3D .;=0A= + . =3D ALIGN(4096);=0A= + *(.gnu.warning)=0A= + } =3D0=0A= +=0A= + .reginfo : { *(.reginfo) }=0A= +=0A= + . =3D 0x800A0000;=0A= + __bss_start =3D .;=0A= + .bss :=0A= + {=0A= + *(.bss)=0A= + _end =3D . ;=0A= + }=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/idtIRQ.S = idtlinux/arch/mips/idt-boards/rc32434/EB434/idtIRQ.S=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/idtIRQ.S = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/idtIRQ.S 2006-03-09 = 16:25:50.000000000 -0800=0A= @@ -0,0 +1,79 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Intterrupt dispatcher code for IDT boards=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= + =0A= + =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= + .text=0A= + .set noreorder=0A= + .set noat=0A= + .align 5=0A= + NESTED(idtIRQ, PT_SIZE, sp)=0A= + .set noat=0A= + SAVE_ALL=0A= + CLI=0A= +=0A= + .set at=0A= + .set noreorder=0A= +=0A= + /* Get the pending interrupts */=0A= + mfc0 t0, CP0_CAUSE=0A= + nop=0A= + =0A= + /* Isolate the allowed ones by anding the irq mask */=0A= + mfc0 t2, CP0_STATUS=0A= + move a1, sp /* need a nop here, hence we anticipate */=0A= + andi t0, CAUSEF_IP=0A= + and t0, t2=0A= + =0A= + /* check for r4k counter/timer IRQ. */=0A= + =0A= + andi t1, t0, CAUSEF_IP7=0A= + beqz t1, 1f=0A= + nop=0A= +=0A= + jal idt_timer_interrupt =0A= +=0A= + li a0, 7=0A= +=0A= + j ret_from_irq=0A= + nop=0A= +1:=0A= + jal rc32434_irqdispatch=0A= + move a0, t0=0A= + j ret_from_irq=0A= + nop=0A= +=0A= + END(idtIRQ)=0A= +=0A= +=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/irq.c = idtlinux/arch/mips/idt-boards/rc32434/EB434/irq.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/irq.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/irq.c 2006-03-09 = 16:25:50.000000000 -0800=0A= @@ -0,0 +1,263 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * Interrupt routines for IDT EB434/435 boards=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +#include =0A= +=0A= +#undef DEBUG_IRQ=0A= +#ifdef DEBUG_IRQ=0A= +/* note: prints function name for you */=0A= +#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## = args)=0A= +#else=0A= +#define DPRINTK(fmt, args...)=0A= +#endif=0A= +=0A= +extern asmlinkage void idtIRQ(void);=0A= +static unsigned int startup_irq(unsigned int irq);=0A= +static void end_irq(unsigned int irq_nr);=0A= +static void mask_and_ack_irq(unsigned int irq_nr);=0A= +static void rc32434_enable_irq(unsigned int irq_nr);=0A= +static void rc32434_disable_irq(unsigned int irq_nr);=0A= +=0A= +extern void __init init_generic_irq(void);=0A= +=0A= +typedef struct {=0A= + u32 mask;=0A= + volatile u32 *base_addr;=0A= +} intr_group_t;=0A= +=0A= +static const intr_group_t intr_group[NUM_INTR_GROUPS] =3D {=0A= + { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) = },=0A= + { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) = },=0A= + { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) = },=0A= + { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) = },=0A= + { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) = }=0A= +};=0A= +=0A= +#define READ_PEND(base) (*(base))=0A= +#define READ_MASK(base) (*(base + 2))=0A= +#define WRITE_MASK(base, val) (*(base + 2) =3D (val))=0A= +=0A= +static inline int irq_to_group(unsigned int irq_nr)=0A= +{=0A= + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);=0A= +}=0A= +=0A= +static inline int group_to_ip(unsigned int group)=0A= +{=0A= + return group + 2;=0A= +}=0A= +=0A= +static inline void enable_local_irq(unsigned int ip)=0A= +{=0A= + int ipnum =3D 0x100 << ip;=0A= + clear_c0_cause(ipnum);=0A= + set_c0_status(ipnum);=0A= +}=0A= +=0A= +static inline void disable_local_irq(unsigned int ip)=0A= +{=0A= + int ipnum =3D 0x100 << ip;=0A= + clear_c0_status(ipnum);=0A= +}=0A= +=0A= +static inline void ack_local_irq(unsigned int ip)=0A= +{=0A= + int ipnum =3D 0x100 << ip;=0A= + clear_c0_cause(ipnum);=0A= +}=0A= +=0A= +static void rc32434_enable_irq(unsigned int irq_nr)=0A= +{=0A= + int ip =3D irq_nr - GROUP0_IRQ_BASE;=0A= + unsigned int group, intr_bit;=0A= + volatile unsigned int *addr;=0A= + if (ip < 0) {=0A= + enable_local_irq(irq_nr);=0A= + }=0A= + else {=0A= + // calculate group=0A= + group =3D ip >> 5;=0A= + =0A= + // calc interrupt bit within group=0A= + ip -=3D (group << 5);=0A= + intr_bit =3D 1 << ip;=0A= + =0A= + // first enable the IP mapped to this IRQ=0A= + enable_local_irq(group_to_ip(group));=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + // unmask intr within group=0A= + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);=0A= + }=0A= +}=0A= +=0A= +static void rc32434_disable_irq(unsigned int irq_nr)=0A= +{=0A= + int ip =3D irq_nr - GROUP0_IRQ_BASE;=0A= + unsigned int group, intr_bit, mask;=0A= + volatile unsigned int *addr;=0A= + =0A= + // calculate group=0A= + group =3D ip >> 5;=0A= + =0A= + // calc interrupt bit within group=0A= + ip -=3D group << 5;=0A= + intr_bit =3D 1 << ip;=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + // mask intr within group=0A= + mask =3D READ_MASK(addr);=0A= + mask |=3D intr_bit;=0A= + WRITE_MASK(addr, mask);=0A= + =0A= + /*=0A= + if there are no more interrupts enabled in this=0A= + group, disable corresponding IP=0A= + */=0A= + if (mask =3D=3D intr_group[group].mask)=0A= + disable_local_irq(group_to_ip(group));=0A= +}=0A= +=0A= +static unsigned int startup_irq(unsigned int irq_nr)=0A= +{=0A= + rc32434_enable_irq(irq_nr);=0A= + return 0; =0A= +}=0A= +=0A= +static void shutdown_irq(unsigned int irq_nr)=0A= +{=0A= + rc32434_disable_irq(irq_nr);=0A= + return;=0A= +}=0A= +=0A= +static void mask_and_ack_irq(unsigned int irq_nr)=0A= +{=0A= + rc32434_disable_irq(irq_nr);=0A= + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));=0A= +}=0A= +=0A= +static void end_irq(unsigned int irq_nr)=0A= +{=0A= + =0A= + int ip =3D irq_nr - GROUP0_IRQ_BASE;=0A= + unsigned int intr_bit, group;=0A= + volatile unsigned int *addr;=0A= + =0A= + if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) = {=0A= + if (irq_nr =3D=3D GROUP4_IRQ_BASE + 11)=0A= + gpio->gpioistat =3D 0xfffff7ff;=0A= + =0A= + group =3D ip >> 5;=0A= + =0A= + // calc interrupt bit within group=0A= + ip -=3D (group << 5);=0A= + intr_bit =3D 1 << ip;=0A= + =0A= + // first enable the IP mapped to this IRQ=0A= + enable_local_irq(group_to_ip(group));=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + // unmask intr within group=0A= + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);=0A= + } =0A= + else {=0A= + printk("warning: end_irq %d did not enable (%x)\n", =0A= + irq_nr, irq_desc[irq_nr].status);=0A= + }=0A= +}=0A= +=0A= +static struct hw_interrupt_type rc32434_irq_type =3D {=0A= + .typename =3D "IDT434",=0A= + .startup =3D startup_irq,=0A= + .shutdown =3D shutdown_irq,=0A= + .enable =3D rc32434_enable_irq,=0A= + .disable =3D rc32434_disable_irq,=0A= + .ack =3D mask_and_ack_irq,=0A= + .end =3D end_irq,=0A= +};=0A= +=0A= +void __init arch_init_irq(void)=0A= +{=0A= + int i;=0A= + printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, = NR_IRQS); =0A= + memset(irq_desc, 0, sizeof(irq_desc));=0A= + set_except_vector(0, idtIRQ);=0A= + =0A= + for (i =3D 0; i < RC32434_NR_IRQS; i++) {=0A= + irq_desc[i].status =3D IRQ_DISABLED;=0A= + irq_desc[i].action =3D NULL;=0A= + irq_desc[i].depth =3D 1;=0A= + irq_desc[i].handler =3D &rc32434_irq_type;=0A= + spin_lock_init(&irq_desc[i].lock);=0A= + }=0A= +}=0A= +=0A= +/* Main Interrupt dispatcher */=0A= +void rc32434_irqdispatch(unsigned long cp0_cause, struct pt_regs = *regs)=0A= +{=0A= + unsigned int ip, pend, group;=0A= + volatile unsigned int *addr;=0A= + =0A= + if ((ip =3D (cp0_cause & 0x7c00))) {=0A= + group =3D 21 - rc32434_clz(ip);=0A= + =0A= + addr =3D intr_group[group].base_addr;=0A= + =0A= + pend =3D READ_PEND(addr);=0A= + pend &=3D ~READ_MASK(addr); // only unmasked interrupts=0A= + pend =3D 39 - rc32434_clz(pend);=0A= + do_IRQ((group << 5) + pend, regs);=0A= + return;=0A= + } =0A= + else=0A= + return;=0A= +}=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/Makefile = idtlinux/arch/mips/idt-boards/rc32434/EB434/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/Makefile 2006-03-09 = 16:25:50.000000000 -0800=0A= @@ -0,0 +1,41 @@=0A= +#######################################################################= ########=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile for IDT EB434 BSP=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +#=0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +# =0A= +#######################################################################= ########=0A= +=0A= +=0A= +.S.s:=0A= + $(CPP) $(CFLAGS) $< -o $*.s=0A= +.S.o:=0A= + $(CC) $(CFLAGS) -c $< -o $*.o=0A= +=0A= +obj-y :=3D prom.o setup.o idtIRQ.o reset.o irq.o time.o=0A= +obj-$(CONFIG_KGDB) +=3D serial_gdb.o=0A= +obj-$(CONFIG_SERIAL_8250) +=3D serial.o=0A= +subdir-$(CONFIG_IDT_BOOT_NVRAM) +=3D nvram=0A= +obj-$(CONFIG_IDT_BOOT_NVRAM) +=3D nvram/built-in.o=0A= +=0A= diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/Make= file idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/Makefile=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/Makefile = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/Makefile = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,39 @@=0A= +#######################################################################= ########=0A= +#=0A= +# BRIEF MODULE DESCRIPTION=0A= +# Makefile for IDT EB434/435 nvram access routines=0A= +#=0A= +# Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= +#=0A= +# This program is free software; you can redistribute it and/or = modify it=0A= +# under the terms of the GNU General Public License as published = by the=0A= +# Free Software Foundation; either version 2 of the License, or (at = your=0A= +# option) any later version.=0A= +#=0A= +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= +#=0A= +# You should have received a copy of the GNU General Public License = along=0A= +# with this program; if not, write to the Free Software Foundation, = Inc.,=0A= +# 675 Mass Ave, Cambridge, MA 02139, USA.=0A= +#=0A= +#=0A= +#######################################################################= ########=0A= +=0A= +obj-y :=3D nvram434.o=0A= +obj-m :=3D $(O_TARGET)=0A= +=0A= +=0A= +=0A= +=0A= +=0A= +=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.c = idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.c=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.c = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,382 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * nvram interface routines.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +#include =0A= +#include =0A= +=0A= +//#include =0A= +#include "nvram434.h"=0A= +#include "rtc.h"=0A= +#define NVRAM_BASE RTCLOCK_BASE=0A= +=0A= +extern void setenv (char *e, char *v, int rewrite);=0A= +extern void unsetenv (char *e);=0A= +extern void mapenv (int (*func)(char *, char *));=0A= +extern char *getenv (char *s);=0A= +extern void purgeenv(void);=0A= +=0A= +static void nvram_initenv(void);=0A= +=0A= +static unsigned char=0A= +nvram_getbyte(int offs)=0A= +{=0A= + return(*((unsigned char*)(NVRAM_BASE + offs)));=0A= +}=0A= +=0A= +static void=0A= +nvram_setbyte(int offs, unsigned char val)=0A= +{=0A= + unsigned char* nvramDataPointer =3D (unsigned char*)(NVRAM_BASE + = offs);=0A= +=0A= + *nvramDataPointer =3D val;=0A= +}=0A= +=0A= +/*=0A= + * BigEndian!=0A= + */=0A= +static unsigned short=0A= +nvram_getshort(int offs)=0A= +{=0A= + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));=0A= +}=0A= +=0A= +static void=0A= +nvram_setshort(int offs, unsigned short val)=0A= +{=0A= + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));=0A= + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));=0A= +}=0A= +#if 0=0A= +static unsigned int=0A= +nvram_getint(int offs)=0A= +{=0A= + unsigned int val;=0A= + val =3D nvram_getbyte(offs) << 24;=0A= + val |=3D nvram_getbyte(offs + 1) << 16;=0A= + val |=3D nvram_getbyte(offs + 2) << 8;=0A= + val |=3D nvram_getbyte(offs + 3);=0A= + return(val);=0A= +}=0A= +=0A= +static void=0A= +nvram_setint(int offs, unsigned int val)=0A= +{=0A= + nvram_setbyte(offs, val >> 24);=0A= + nvram_setbyte(offs + 1, val >> 16);=0A= + nvram_setbyte(offs + 2, val >> 8);=0A= + nvram_setbyte(offs + 3, val);=0A= +}=0A= +#endif=0A= +/*=0A= + * calculate NVRAM checksum=0A= + */=0A= +static unsigned short=0A= +nvram_calcsum(void)=0A= +{=0A= + unsigned short sum =3D NV_MAGIC;=0A= + int i;=0A= +=0A= + for (i =3D ENV_BASE; i < ENV_TOP; i +=3D 2)=0A= + sum +=3D nvram_getshort(i);=0A= + return(sum);=0A= +}=0A= +=0A= +/*=0A= + * update the nvram checksum=0A= + */=0A= +static void=0A= +nvram_updatesum (void)=0A= +{=0A= + nvram_setshort(NVOFF_CSUM, nvram_calcsum());=0A= +}=0A= +=0A= +/*=0A= + * test validity of nvram by checksumming it=0A= + */=0A= +static int=0A= +nvram_isvalid(void)=0A= +{=0A= + static int is_valid;=0A= +=0A= + if (is_valid)=0A= + return(1);=0A= +=0A= + if (nvram_getshort(NVOFF_MAGIC) !=3D NV_MAGIC)=0A= + nvram_initenv();=0A= + is_valid =3D 1;=0A= + return(1);=0A= +}=0A= +=0A= +/* return nvram address of environment string */=0A= +static int=0A= +nvram_matchenv(char *s)=0A= +{=0A= + int envsize, envp, n, i, varsize;=0A= + char *var;=0A= +=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + if (envsize > ENV_AVAIL)=0A= + return(0); /* sanity */=0A= + =0A= + envp =3D ENV_BASE;=0A= +=0A= + if ((n =3D strlen (s)) > 255)=0A= + return(0);=0A= + =0A= + while (envsize > 0) {=0A= + varsize =3D nvram_getbyte(envp);=0A= + if (varsize =3D=3D 0 || (envp + varsize) > ENV_TOP)=0A= + return(0); /* sanity */=0A= + for (i =3D envp + 1, var =3D s; i <=3D envp + n; i++, var++) {=0A= + char c1 =3D nvram_getbyte(i);=0A= + char c2 =3D *var;=0A= + if (islower(c1))=0A= + c1 =3D toupper(c1);=0A= + if (islower(c2))=0A= + c2 =3D toupper(c2);=0A= + if (c1 !=3D c2)=0A= + break;=0A= + }=0A= + if (i > envp + n) { /* match so far */=0A= + if (n =3D=3D varsize - 1) /* match on boolean */=0A= + return(envp);=0A= + if (nvram_getbyte(i) =3D=3D '=3D') /* exact match on variable = */=0A= + return(envp);=0A= + }=0A= + envsize -=3D varsize;=0A= + envp +=3D varsize;=0A= + }=0A= + return(0);=0A= +}=0A= +=0A= +static void nvram_initenv(void)=0A= +{=0A= + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);=0A= + nvram_setshort(NVOFF_ENVSIZE, 0);=0A= +=0A= + nvram_updatesum();=0A= +}=0A= +=0A= +static void=0A= +nvram_delenv(char *s)=0A= +{=0A= + int nenvp, envp, envsize, nbytes;=0A= +=0A= + envp =3D nvram_matchenv(s);=0A= + if (envp =3D=3D 0)=0A= + return;=0A= +=0A= + nenvp =3D envp + nvram_getbyte(envp);=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + nbytes =3D envsize - (nenvp - ENV_BASE);=0A= + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));=0A= + while (nbytes--) {=0A= + nvram_setbyte(envp, nvram_getbyte(nenvp));=0A= + envp++;=0A= + nenvp++;=0A= + }=0A= + nvram_updatesum();=0A= +}=0A= +=0A= +static int=0A= +nvram_setenv(char *s, char *v)=0A= +{=0A= + int ns, nv, total;=0A= + int envp;=0A= +=0A= + if (!nvram_isvalid())=0A= + return(-1);=0A= +=0A= + nvram_delenv(s);=0A= + ns =3D strlen(s);=0A= + if (ns =3D=3D 0)=0A= + return (-1);=0A= + if (v && *v) {=0A= + nv =3D strlen(v);=0A= + total =3D ns + nv + 2;=0A= + }=0A= + else {=0A= + nv =3D 0;=0A= + total =3D ns + 1;=0A= + }=0A= + if (total > 255 || total > ENV_AVAIL - = nvram_getshort(NVOFF_ENVSIZE))=0A= + return(-1);=0A= +=0A= + envp =3D ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);=0A= +=0A= + nvram_setbyte(envp, (unsigned char) total); =0A= + envp++;=0A= +=0A= + while (ns--) {=0A= + nvram_setbyte(envp, *s); =0A= + envp++; =0A= + s++;=0A= + }=0A= +=0A= + if (nv) {=0A= + nvram_setbyte(envp, '=3D'); =0A= + envp++;=0A= + while (nv--) {=0A= + nvram_setbyte(envp, *v); =0A= + envp++; =0A= + v++;=0A= + }=0A= + }=0A= + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);=0A= + nvram_updatesum();=0A= + return 0;=0A= +}=0A= +=0A= +static char *=0A= +nvram_getenv(char *s)=0A= +{=0A= + static char buf[256]; /* FIXME: this cannot be static */=0A= + int envp, ns, nbytes, i;=0A= +=0A= + if (!nvram_isvalid())=0A= + return((char *)0);=0A= +=0A= + envp =3D nvram_matchenv(s);=0A= + if (envp =3D=3D 0)=0A= + return((char *)0);=0A= + ns =3D strlen(s);=0A= + if (nvram_getbyte(envp) =3D=3D ns + 1) /* boolean */=0A= + buf[0] =3D '\0';=0A= + else {=0A= + nbytes =3D nvram_getbyte(envp) - (ns + 2);=0A= + envp +=3D ns + 2;=0A= + for (i =3D 0; i < nbytes; i++)=0A= + buf[i] =3D nvram_getbyte(envp++);=0A= + buf[i] =3D '\0';=0A= + }=0A= + return(buf);=0A= +}=0A= +=0A= +static void=0A= +nvram_unsetenv(char *s)=0A= +{=0A= + if (!nvram_isvalid())=0A= + return;=0A= +=0A= + nvram_delenv(s);=0A= +}=0A= +=0A= +/*=0A= + * apply func to each string in environment=0A= + */=0A= +static void=0A= +nvram_mapenv(int (*func)(char *, char *))=0A= +{=0A= + int envsize, envp, n, i, seeneql;=0A= + char name[256], value[256];=0A= + char c, *s;=0A= +=0A= + if (!nvram_isvalid())=0A= + return;=0A= +=0A= + envsize =3D nvram_getshort(NVOFF_ENVSIZE);=0A= + envp =3D ENV_BASE;=0A= +=0A= + while (envsize > 0) {=0A= + value[0] =3D '\0';=0A= + seeneql =3D 0;=0A= + s =3D name;=0A= + n =3D nvram_getbyte(envp);=0A= + for (i =3D envp + 1; i < envp + n; i++) {=0A= + c =3D nvram_getbyte(i);=0A= + if ((c =3D=3D '=3D') && !seeneql) {=0A= + *s =3D '\0';=0A= + s =3D value;=0A= + seeneql =3D 1;=0A= + continue;=0A= + }=0A= + *s++ =3D c;=0A= + }=0A= + *s =3D '\0';=0A= + (*func)(name, value);=0A= + envsize -=3D n;=0A= + envp +=3D n;=0A= + }=0A= +}=0A= +#if 0=0A= +static unsigned int=0A= +digit(char c)=0A= +{=0A= + if ('0' <=3D c && c <=3D '9')=0A= + return (c - '0');=0A= + if ('A' <=3D c && c <=3D 'Z')=0A= + return (10 + c - 'A');=0A= + if ('a' <=3D c && c <=3D 'z')=0A= + return (10 + c - 'a');=0A= + return (~0);=0A= +}=0A= +#endif=0A= +/*=0A= + * Wrappers to allow 'special' environment variables to get = processed=0A= + */=0A= +void=0A= +setenv(char *e, char *v, int rewrite)=0A= +{=0A= + if (nvram_getenv(e) && !rewrite)=0A= + return;=0A= + =0A= + nvram_setenv(e, v);=0A= +}=0A= +=0A= +char *=0A= +getenv(char *e)=0A= +{=0A= + return(nvram_getenv(e));=0A= +}=0A= +=0A= +void=0A= +unsetenv(char *e)=0A= +{=0A= + nvram_unsetenv(e);=0A= +}=0A= +=0A= +void=0A= +purgeenv()=0A= +{=0A= + int i;=0A= + unsigned char* nvramDataPointer =3D (unsigned char*)(NVRAM_BASE);=0A= + =0A= + for (i =3D ENV_BASE; i < ENV_TOP; i++)=0A= + *nvramDataPointer++ =3D 0;=0A= + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);=0A= + nvram_setshort(NVOFF_ENVSIZE, 0);=0A= + nvram_setshort(NVOFF_CSUM, NV_MAGIC);=0A= +}=0A= +=0A= +void=0A= +mapenv(int (*func)(char *, char *))=0A= +{=0A= + nvram_mapenv(func);=0A= +}=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.h = idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.h=0A= --- = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/nvram434.h = 2006-03-09 16:25:50.000000000 -0800=0A= @@ -0,0 +1,58 @@=0A= +/**********************************************************************= ****=0A= + *=0A= + * BRIEF MODULE DESCRIPTION=0A= + * nvram definitions.=0A= + *=0A= + * Copyright 2006 IDT Inc. (rischelp@idt.com)=0A= + * =0A= + * This program is free software; you can redistribute it and/or = modify it=0A= + * under the terms of the GNU General Public License as published = by the=0A= + * Free Software Foundation; either version 2 of the License, or = (at your=0A= + * option) any later version.=0A= + *=0A= + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED=0A= + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF=0A= + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN=0A= + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT,=0A= + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT=0A= + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF=0A= + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON=0A= + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT=0A= + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF=0A= + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE.=0A= + *=0A= + * You should have received a copy of the GNU General Public License = along=0A= + * with this program; if not, write to the Free Software Foundation, = Inc.,=0A= + * 675 Mass Ave, Cambridge, MA 02139, USA.=0A= + *=0A= + = ************************************************************************= **=0A= + */=0A= +=0A= +=0A= +#ifndef _NVRAM_=0A= +#define _NVRAM_=0A= +#define NVOFFSET 0 /* use all of NVRAM */=0A= +=0A= +/* Offsets to reserved locations */=0A= + /* size description */=0A= +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */=0A= +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment = checksum */=0A= +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' = */=0A= +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte = */=0A= +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet = address */=0A= +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table = */=0A= +=0A= +#define NV_MAGIC 0xdeaf /* nvram magic number */=0A= +#define NV_RESERVED 32 /* number of reserved bytes = */=0A= +=0A= +#undef NVOFF_ETHADDR=0A= +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)=0A= +=0A= +/* number of bytes available for environment */=0A= +#define ENV_BASE (NVOFFSET + NV_RESERVED)=0A= +#define ENV_TOP TD_NVRAM_SIZE=0A= +#define ENV_AVAIL (ENV_TOP - ENV_BASE)=0A= +=0A= +#endif /* _NVRAM_ */=0A= +=0A= +=0A= diff -uNr = linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/rtc.h = idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/rtc.h=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/nvram/rtc.h = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/nvram/rtc.h 2006-03-09 = 16:25:50.000000000 -0800=0A= @@ -0,0 +1,72 @@=0A= +/**********************************************************************= **** + * + * BRIEF MODULE DESCRIPTION + * DS1553(Dallas Semiconductor) Real Time Clock and Non-Volatile = RAM. + * + * Copyright 2006 IDT Inc. (rischelp@idt.com) + * =20 + * This program is free software; you can redistribute it and/or = modify it + * under the terms of the GNU General Public License as published = by the + * Free Software Foundation; either version 2 of the License, or = (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR = IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED = WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE = DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, = INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES = (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; = LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, = OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE = USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License = along + * with this program; if not, write to the Free Software Foundation, = Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + = ************************************************************************= ** + */ + + +#define RTCLOCK_BASE 0xBA000000 + +/* + * To maintain endianess independence, make all accesses as 32-bit + * words with appropriate shifting. + */ +#define TD_NVRAM_SIZE 0x1FF0 + +typedef struct td_clock { + unsigned char ram[TD_NVRAM_SIZE]; + unsigned char flags; + unsigned char dummy; + unsigned char alarm_secs; + unsigned char alarm_mins; + unsigned char alarm_hours; + unsigned char alarm_date; + unsigned char interrupts; + unsigned char watchdog; + unsigned char century; + unsigned char secs; + unsigned char mins; + unsigned char hours; + unsigned char weekday; + unsigned char date; + unsigned char month; + unsigned char year; +} RTC; + +#define rtc (*((volatile RTC *)RTCLOCK_BASE)) + +/* + * Control register bit definitions + */ +#define TDC_ENA_READ 0x40 +#define TDC_DIS_READ 0xBF + +#define TDC_ENA_WRITE 0x80 +#define TDC_DIS_WRITE 0x7F + +#define TDC_RUN_OSC 0x80 + diff -uNr linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/prom.c = idtlinux/arch/mips/idt-boards/rc32434/EB434/prom.c=0A= --- linux-2.6.16-rc5/arch/mips/idt-boards/rc32434/EB434/prom.c = 1969-12-31 16:00:00.000000000 -0800=0A= +++ idtlinux/arch/mips/idt-boards/rc32434/EB434/prom.c 2006-03-09 = 16:25:50.000000000 -0800=0A= @@ -0,0 +1,142 @@=0A= +/*******