From cw@f00f.org Thu Dec 1 03:51:40 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Dec 2005 03:51:59 +0000 (GMT) Received: from ylpvm12-ext.prodigy.net ([207.115.57.43]:48609 "EHLO ylpvm12.prodigy.net") by ftp.linux-mips.org with ESMTP id S8133917AbVLADvk (ORCPT ); Thu, 1 Dec 2005 03:51:40 +0000 Received: from ylpvm01.prodigy.net (ylpvm01-int.prodigy.net [207.115.5.207]) by ylpvm12.prodigy.net (8.12.10 outbound/8.12.10) with ESMTP id jB13tTv4030788; Wed, 30 Nov 2005 22:55:30 -0500 X-ORBL: [70.132.51.62] Received: from stupidest.org ([70.132.51.62]) by ylpvm01.prodigy.net (8.13.4 dk-milter linux/8.13.4) with ESMTP id jB13xGZv028324; Wed, 30 Nov 2005 22:59:17 -0500 Received: by taniwha.stupidest.org (Postfix, from userid 38689) id 2CE0B4FE060; Wed, 30 Nov 2005 19:55:07 -0800 (PST) Date: Wed, 30 Nov 2005 19:55:07 -0800 From: Chris Wedgwood To: Ralf Baechle Cc: Matej Kupljen , linux-mips@linux-mips.org, Jordan Crouse Subject: Re: MIPS no FP patch Message-ID: <20051201035507.GA32133@taniwha.stupidest.org> References: <1133348852.24526.31.camel@localhost.localdomain> <20051130112821.GB2694@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20051130112821.GB2694@linux-mips.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9571 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cw@f00f.org Precedence: bulk X-list: linux-mips On Wed, Nov 30, 2005 at 11:28:21AM +0000, Ralf Baechle wrote: > We used to have this option but I eventually got rid of it because > people just don't grok that they must enable it in precense of an > FPU. For cores that have FPUs you could have Kconfig "select" it automatically. From david.sanchez@lexbox.fr Thu Dec 1 13:10:23 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Dec 2005 13:10:40 +0000 (GMT) Received: from laf31-5-82-235-130-100.fbx.proxad.net ([82.235.130.100]:4086 "EHLO lexbox.fr") by ftp.linux-mips.org with ESMTP id S8133932AbVLANKW convert rfc822-to-8bit (ORCPT ); Thu, 1 Dec 2005 13:10:22 +0000 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: RE: DbAu1550 copy file corruption X-MimeOLE: Produced By Microsoft Exchange V6.5.6944.0 Date: Thu, 1 Dec 2005 14:10:12 +0100 Message-ID: <17AB476A04B7C842887E0EB1F268111E0271AB@xpserver.intra.lexbox.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: DbAu1550 copy file corruption thread-index: AcX11en5L2oG8EKjREunsxH0TidH0QAj0nAg From: "David Sanchez" To: "Sergei Shtylylov" , Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9572 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.sanchez@lexbox.fr Precedence: bulk X-list: linux-mips Hi, As all my pci sata controllers operate up to 66Mhz, I add a divider to the pci clock in the board_setup.c of the au1550 to obtain 32 Mhz pci clock. But the problem still appear... (More the bus is slow, less the problem appear: maybe because it is a timing issue ?) I try the HPT371B (which works for us). I try several PCI sata controllers (Promise PDC20779, PDC 20579, SiliconImage Sil3112, etc...). More I try the drivers provided by Promise instead of the libata. But the problem still appear... Sergei, is the PCI clock frequency issue only for the HPT371N or even for PCI sata controller ? Do you mean that all the users of the dbau1550 needs to set the PCI clock to 32Mhz? Have you try my script on your board? Thanks. David -----Message d'origine----- De : Sergei Shtylylov [mailto:sshtylyov@ru.mvista.com] Envoyé : mercredi 30 novembre 2005 18:46 À : Dan Malek Cc : David Sanchez Objet : Re: DbAu1550 copy file corruption Hello. Dan Malek wrote: > Have you tested this on an NFS partition? Does > the on-board HPT371 work? I know the latter two > used to work, but I don't remember testing a 2.6.10 > kernel, I've been using newer ones. Do you mean HPT371N? It shouldn't work (and does not work for us) since the current driver has severe clocking problems with anything but HPT370/374 on a 66 MHz PCI. So with the default 64 MHz Au1550 PCI clock the driver just locks up; it can only work if you plug in a 33 MHz PCI card to get Au1550 PCI clocked at 32 MHz. I was in the process of fixing this but this work is currently preempted by more urgent stuff... :-( WBR, Sergei From conil.christophe@addi-data.com Thu Dec 1 15:03:45 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 01 Dec 2005 15:04:12 +0000 (GMT) Received: from [62.154.208.154] ([62.154.208.154]:63899 "EHLO firewall1.addi-data.de") by ftp.linux-mips.org with ESMTP id S8134039AbVLAPDp convert rfc822-to-8bit (ORCPT ); Thu, 1 Dec 2005 15:03:45 +0000 Received: from [172.16.2.26] (helo=security01.addi-data.intra) by firewall1.addi-data.de with esmtp (Exim 4.43) id 1Ehq1a-0006oU-9I for linux-mips@linux-mips.org; Thu, 01 Dec 2005 16:07:07 +0100 Received: from security1.addi-data.de (exchange01.addi-data.intra) by security01.addi-data.intra (Clearswift SMTPRS 5.0.9) with ESMTP id for ; Thu, 1 Dec 2005 16:07:06 +0100 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: get an usleep() with less than 20ms on 2.4.27 X-MimeOLE: Produced By Microsoft Exchange V6.5 Date: Thu, 1 Dec 2005 16:07:05 +0100 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: get an usleep() with less than 20ms on 2.4.27 Thread-Index: AcX2epQlVpuToN9OS3CENEPXxjXM+QADR/4g From: "Conil.Christophe" To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9573 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Conil.Christophe@addi-data.com Precedence: bulk X-list: linux-mips Hi, I'm using a 2.4.27 Kernel on MIPS. I'm actually programming a USR-Space software which needs high-precision sleep() functions. Actually, by using them, I can't get a sleep time lower than 20 ms. (even with a usleep(1) which should sleep for 1 microsecond) I thought it may came from the Linux default scheduler, so I increased its resolution by modifying HZ and CLOCKS_PER_SEC (I set them to 1000 instead of 100) in the /linux/include/asm-mips/param.h file. I'm now having a minimum usleep time of 2ms, which is better, but still not perfect (since I need at least 1ms) If I continue increasing these 2 values, my kernel doesn't compile because of /linux/include/linux/timex.h. Do you have a clue what could I do to have a non-active (without a while) sleeping time fewer than 2ms? (A sleeping time of 0.5 ms would be perfect) Please excuse my newbieness if I said something not relevant... Thank you very much, Christophe CONIL Content of /linux/include/linux/timex.h -------------------------------------------------------------------------------- #if HZ >= 12 && HZ < 24 # define SHIFT_HZ 4 [...] #elif HZ >= 768 && HZ < 1536 # define SHIFT_HZ 10 #else # error You lose. < #endif -------------------------------------------------------------------------------- Content of /linux/include/asm-mips/param.h -------------------------------------------------------------------------------- #ifndef _ASM_PARAM_H #define _ASM_PARAM_H #ifndef HZ #ifdef __KERNEL__ /* Safeguard against user stupidity  */ #ifdef _SYS_PARAM_H #error Do not include with __KERNEL__ defined! #endif #include /* This is the internal value of HZ, that is the rate at which the jiffies    counter is increasing.  This value is independent from the external value    and can be changed in order to suit the hardware and application    requirements.  */ #  define HZ 1000 /* CC : Previous value was 100 */ #  define hz_to_std(a) (a) #else /* defined(__KERNEL__)  */ /* This is the external value of HZ as seen by user programs.  Don't change    unless you know what you're doing - changing breaks binary compatibility.  */ #define HZ 100  #endif /* defined(__KERNEL__)  */ #endif /* defined(HZ)  */ [...] #ifdef __KERNEL__ # define CLOCKS_PER_SEC     1000     /* frequency at which times() counts */ /* CC : Previous value was 100 */ #endif #endif /* _ASM_PARAM_H */ -------------------------------------------------------------------------------- ********************************************************************** This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the system manager. This footnote confirms that this email message has been scanned for the presence of computer viruses. ********************************************************************** From zzh.hust@gmail.com Fri Dec 2 07:09:01 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 07:09:20 +0000 (GMT) Received: from wproxy.gmail.com ([64.233.184.203]:58473 "EHLO wproxy.gmail.com") by ftp.linux-mips.org with ESMTP id S8133536AbVLBHJB convert rfc822-to-8bit (ORCPT ); Fri, 2 Dec 2005 07:09:01 +0000 Received: by wproxy.gmail.com with SMTP id i11so6275wra for ; Thu, 01 Dec 2005 23:12:35 -0800 (PST) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=d0ntXKGDNs96c1K3P3C3NbsChfQz9FhL2+3NW+RihgoBL3X85Tqg/7QsSpWSsBG1CtdsnmalRj65+M2kFyanWNh5miud16Rz9WPT3s/wFF9dkbe+4m8/CvAiqGsQAM07Gt0cS5JJqCCoC6kfS/QP+VPXEXzKswbqINhglA3Afdo= Received: by 10.54.63.18 with SMTP id l18mr167495wra; Thu, 01 Dec 2005 23:12:35 -0800 (PST) Received: by 10.54.129.5 with HTTP; Thu, 1 Dec 2005 23:12:35 -0800 (PST) Message-ID: <50c9a2250512012312u47bbe09eh9e4f6b8edb0d0d9d@mail.gmail.com> Date: Fri, 2 Dec 2005 15:12:35 +0800 From: zhuzhenhua To: linux-mips@linux-mips.org Subject: where to set the BEV to normal of status in kernel source? MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9574 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zzh.hust@gmail.com Precedence: bulk X-list: linux-mips i don't find it in load_mmu(), who can point out for me? thanks! is that must be set in bootloader? Best regards zhuzhenhua From florian.delizy@sagem.com Fri Dec 2 13:38:58 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 13:39:16 +0000 (GMT) Received: from ns1.sagem.com ([62.160.59.65]:43170 "EHLO mx1.sagem.com") by ftp.linux-mips.org with ESMTP id S8133590AbVLBNi6 (ORCPT ); Fri, 2 Dec 2005 13:38:58 +0000 To: linux-mips@linux-mips.org Subject: Re : where to set the BEV to normal of status in kernel source? MIME-Version: 1.0 Message-ID: From: Florian DELIZY Date: Fri, 2 Dec 2005 14:42:28 +0100 Content-Type: multipart/alternative; boundary="=_alternative 004B4D69C12570CB_=" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9575 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian.delizy@sagem.com Precedence: bulk X-list: linux-mips Message en plusieurs parties au format MIME --=_alternative 004B4D69C12570CB_= Content-Type: text/plain; charset="us-ascii" Subject : where to set the BEV to normal of status in kernel source? > i don't find it in load_mmu(), who can point out for me? > thanks! Well, if you are speaking about the BEV flag from the Status (SR) register (CP0_STATUS aka $12 of the 1st coprocessor) then it controls the interruption/exception handler place, I don't see the relation with mmu ... > is that must be set in bootloader? OK, I see, it should be set to 0 by the boot loader so that the TLB exceptions (related to the MMU) goes in RAM. So the kernel does not change it actually and hope the boot loader did. -- Florian Delizy --=_alternative 004B4D69C12570CB_= Content-Type: text/html; charset="us-ascii"


Subject : where to set the BEV to normal of status in kernel source?
> i don't find it in load_mmu(), who can point out for me?
> thanks!

Well, if you are speaking about the BEV flag from the Status (SR) register (CP0_STATUS aka $12 of the 1st coprocessor)
then it controls the interruption/exception handler place, I don't see the relation with mmu ...

> is that must be set in bootloader?

OK, I see, it should be set to 0 by the boot loader so that the TLB exceptions (related to the MMU) goes in RAM. So
the kernel does not change it actually and hope the boot loader did.

-- Florian Delizy





--=_alternative 004B4D69C12570CB_=-- From kevink@mips.com Fri Dec 2 13:48:09 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 13:48:26 +0000 (GMT) Received: from 209-232-97-206.ded.pacbell.net ([209.232.97.206]:65462 "EHLO dns0.mips.com") by ftp.linux-mips.org with ESMTP id S8133594AbVLBNsJ (ORCPT ); Fri, 2 Dec 2005 13:48:09 +0000 Received: from mercury.mips.com (sbcns-dmz [209.232.97.193]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id jB2Dpd55011699; Fri, 2 Dec 2005 05:51:40 -0800 (PST) Received: from [192.168.236.16] (grendel [192.168.236.16]) by mercury.mips.com (8.12.9/8.12.11) with ESMTP id jB2Dpblk008895; Fri, 2 Dec 2005 05:51:38 -0800 (PST) Message-ID: <439051B5.9060500@mips.com> Date: Fri, 02 Dec 2005 14:52:53 +0100 From: "Kevin D. Kissell" User-Agent: Mozilla Thunderbird 1.0.6 (X11/20050716) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Florian DELIZY CC: linux-mips@linux-mips.org Subject: Re: Re : where to set the BEV to normal of status in kernel source? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.39 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9576 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@mips.com Precedence: bulk X-list: linux-mips The BEV bit of Status is cleared by the macro setup_c0_status_pri which is invoked in kernel_entry. See arch/mips/kernel/head.S. It's of course possible that a bootloader will already have cleared it, but it should not be necessary. grep is your friend. ;o) Regards, Kevin K. Florian DELIZY wrote: > Subject : where to set the BEV to normal of status in kernel source? > >>i don't find it in load_mmu(), who can point out for me? >>thanks! > > > Well, if you are speaking about the BEV flag from the Status (SR) register > (CP0_STATUS aka $12 of the 1st coprocessor) > then it controls the interruption/exception handler place, I don't see the > relation with mmu ... > > >>is that must be set in bootloader? > > > OK, I see, it should be set to 0 by the boot loader so that the TLB > exceptions (related to the MMU) goes in RAM. So > the kernel does not change it actually and hope the boot loader did. > > -- Florian Delizy > > > > > > From jcrouse@cosmic.amd.com Fri Dec 2 18:50:01 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 18:50:21 +0000 (GMT) Received: from amdext4.amd.com ([163.181.251.6]:38566 "EHLO amdext4.amd.com") by ftp.linux-mips.org with ESMTP id S8133864AbVLBSuB (ORCPT ); Fri, 2 Dec 2005 18:50:01 +0000 Received: from SAUSGW01.amd.com (sausgw01.amd.com [163.181.250.21]) by amdext4.amd.com (8.12.11/8.12.11/AMD) with ESMTP id jB2IrSYC030656; Fri, 2 Dec 2005 12:53:28 -0600 Received: from 163.181.250.1 by SAUSGW01.amd.com with ESMTP (AMD SMTP Relay (Email Firewall v6.1.0)); Fri, 02 Dec 2005 12:53:22 -0600 X-Server-Uuid: 8C3DB987-180B-4465-9446-45C15473FD3E Received: from ldcmail.amd.com (ldcmail.amd.com [147.5.200.40]) by amdint2.amd.com (8.12.8/8.12.8/AMD) with ESMTP id jB2IrLTw003922; Fri, 2 Dec 2005 12:53:21 -0600 (CST) Received: from cosmic.amd.com (cosmic.amd.com [147.5.201.206]) by ldcmail.amd.com (Postfix) with ESMTP id 6FAD92026; Fri, 2 Dec 2005 11:53:21 -0700 (MST) Received: from cosmic.amd.com (localhost [127.0.0.1]) by cosmic.amd.com (8.13.4/8.13.4) with ESMTP id jB2J18LJ031378; Fri, 2 Dec 2005 12:01:08 -0700 Received: (from jcrouse@localhost) by cosmic.amd.com ( 8.13.4/8.13.4/Submit) id jB2J188A031377; Fri, 2 Dec 2005 12:01:08 -0700 Date: Fri, 2 Dec 2005 12:01:08 -0700 From: "Jordan Crouse" To: linux-mips@linux-mips.org cc: ralf@linux-mips.org, drzeus-wbsd@drzeus.cx Subject: [PATCH] ALCHEMY: Add SD support to AU1200 MMC/SD driver Message-ID: <20051202190108.GF28227@cosmic.amd.com> MIME-Version: 1.0 User-Agent: Mutt/1.5.11 X-WSS-ID: 6F8E47A840G499976-01-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9577 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jordan.crouse@amd.com Precedence: bulk X-list: linux-mips Add SD support to the AU1200 MMC driver. This can be added post 2.6.15, I'm just sending them out today so the various maintainers can get them queued up. Signed-off-by: Jordan Crouse --- drivers/mmc/au1xmmc.c | 124 ++++++++++++++++++++++++++++--------------------- 1 files changed, 71 insertions(+), 53 deletions(-) diff --git a/drivers/mmc/au1xmmc.c b/drivers/mmc/au1xmmc.c index cb32a08..c8c8f29 100644 --- a/drivers/mmc/au1xmmc.c +++ b/drivers/mmc/au1xmmc.c @@ -99,16 +99,24 @@ static inline void IRQ_ON(struct au1xmmc au_sync(); } -static inline void FLUSH_FIFO(struct au1xmmc_host *host) +/* Turn on the FIFO flush - the fifo will be returned to active right + * before data transfer + */ + +static inline void FLUSH_FIFO_ON(struct au1xmmc_host *host) { u32 val = au_readl(HOST_CONFIG2(host)); + val |= SD_CONFIG2_FF; + au_writel(val, HOST_CONFIG2(host)); + au_sync(); +} - au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); - au_sync_delay(1); - - /* SEND_STOP will turn off clock control - this re-enables it */ - val &= ~SD_CONFIG2_DF; +static inline void FIFO_ACTIVE(struct au1xmmc_host *host) +{ + u32 val = au_readl(HOST_CONFIG2(host)); + /* SEND_STOP will turn off clock control - this re-enables it */ + val &= ~(SD_CONFIG2_DF | SD_CONFIG2_FF); au_writel(val, HOST_CONFIG2(host)); au_sync(); } @@ -124,8 +132,8 @@ static inline void IRQ_OFF(struct au1xmm static inline void SEND_STOP(struct au1xmmc_host *host) { - /* We know the value of CONFIG2, so avoid a read we don't need */ - u32 mask = SD_CONFIG2_EN; + /* Penalty box for Jordan - NEVER ASSUME! */ + u32 mask = au_readl(HOST_CONFIG2(host)); WARN_ON(host->status != HOST_S_DATA); host->status = HOST_S_STOP; @@ -169,7 +177,7 @@ static void au1xmmc_finish_request(struc host->flags &= HOST_F_ACTIVE; host->dma.len = 0; - host->dma.dir = 0; + host->dma.dir = DMA_BIDIRECTIONAL; host->pio.index = 0; host->pio.offset = 0; @@ -179,6 +187,9 @@ static void au1xmmc_finish_request(struc bcsr->disk_leds |= (1 << 8); + /* Flush the FIFO until our next request */ + FLUSH_FIFO_ON(host); + mmc_request_done(host->mmc, mrq); } @@ -196,7 +207,11 @@ static int au1xmmc_send_command(struct a switch(cmd->flags) { case MMC_RSP_R1: - mmccmd |= SD_CMD_RT_1; + if (cmd->opcode == 0x03 && host->mmc->mode == MMC_MODE_SD) + mmccmd |= SD_CMD_RT_6; + else + mmccmd |= SD_CMD_RT_1; + break; case MMC_RSP_R1B: mmccmd |= SD_CMD_RT_1B; @@ -504,8 +519,8 @@ static void au1xmmc_cmd_complete(struct r[3] = au_readl(host->iobase + SD_RESP0); /* The CRC is omitted from the response, so really we only got - * 120 bytes, but the engine expects 128 bits, so we have to shift - * things up + * 120 bytes, but the engine expects 128 bits, so we have to + * shift things up */ for(i = 0; i < 4; i++) { @@ -576,9 +591,8 @@ au1xmmc_prepare_data(struct au1xmmc_host { int datalen = data->blocks * (1 << data->blksz_bits); - - if (dma != 0) - host->flags |= HOST_F_DMA; + int i = 0; + u32 channel; if (data->flags & MMC_DATA_READ) host->flags |= HOST_F_RECV; @@ -588,8 +602,6 @@ au1xmmc_prepare_data(struct au1xmmc_host if (host->mrq->stop) host->flags |= HOST_F_STOP; - host->dma.dir = DMA_BIDIRECTIONAL; - host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); @@ -598,9 +610,21 @@ au1xmmc_prepare_data(struct au1xmmc_host au_writel((1 << data->blksz_bits) - 1, HOST_BLKSIZE(host)); - if (host->flags & HOST_F_DMA) { - int i; - u32 channel = DMA_CHANNEL(host); + if (dma == 0) { + host->pio.index = 0; + host->pio.offset = 0; + host->pio.len = datalen; + + if (host->flags & HOST_F_XMIT) + IRQ_ON(host, SD_CONFIG_TH); + else + IRQ_ON(host, SD_CONFIG_NE); + + return MMC_ERR_NONE; + } + + host->flags |= HOST_F_DMA; + channel = DMA_CHANNEL(host); au1xxx_dbdma_stop(channel); @@ -611,7 +635,7 @@ au1xmmc_prepare_data(struct au1xmmc_host int len = (datalen > sg_len) ? sg_len : datalen; - if (i == host->dma.len - 1) + if (i == (host->dma.len - 1)) flags = DDMA_FLAGS_IE; if (host->flags & HOST_F_XMIT){ @@ -627,23 +651,11 @@ au1xmmc_prepare_data(struct au1xmmc_host len, flags); } - if (!ret) + if (ret == 0) goto dataerr; datalen -= len; } - } - else { - host->pio.index = 0; - host->pio.offset = 0; - host->pio.len = datalen; - - if (host->flags & HOST_F_XMIT) - IRQ_ON(host, SD_CONFIG_TH); - else - IRQ_ON(host, SD_CONFIG_NE); - //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF); - } return MMC_ERR_NONE; @@ -671,7 +683,7 @@ static void au1xmmc_request(struct mmc_h bcsr->disk_leds &= ~(1 << 8); if (mrq->data) { - FLUSH_FIFO(host); + FIFO_ACTIVE(host); ret = au1xmmc_prepare_data(host, mrq->data); } @@ -734,6 +746,20 @@ static void au1xmmc_set_ios(struct mmc_h au1xmmc_set_clock(host, ios->clock); host->clock = ios->clock; } + + /* Set the bus width for SD */ + + if (ios->bus_width != host->bus_width) { + u32 val; + val = au_readl(HOST_CONFIG2(host)); + val &= ~(SD_CONFIG2_WB); + val |= (ios->bus_width == MMC_BUS_WIDTH_4) ? SD_CONFIG2_WB : 0; + + au_writel(val, HOST_CONFIG2(host)); + au_sync(); + + host->bus_width = ios->bus_width; + } } static void au1xmmc_dma_callback(int irq, void *dev_id, struct pt_regs *regs) @@ -778,24 +804,8 @@ static irqreturn_t au1xmmc_irq(int irq, /* In PIO mode, interrupts might still be enabled */ IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); - - //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF); tasklet_schedule(&host->finish_task); } -#if 0 - else if (status & SD_STATUS_DD) { - - /* Sometimes we get a DD before a NE in PIO mode */ - - if (!(host->flags & HOST_F_DMA) && - (status & SD_STATUS_NE)) - au1xmmc_receive_pio(host); - else { - au1xmmc_data_complete(host, status); - //tasklet_schedule(&host->data_task); - } - } -#endif else if (status & (SD_STATUS_CR)) { if (host->status == HOST_S_CMD) au1xmmc_cmd_complete(host,status); @@ -875,9 +885,15 @@ static void au1xmmc_init_dma(struct au1x host->rx_chan = rxchan; } +static int au1xmmc_get_ro(struct mmc_host *mmc) { + struct au1xmmc_host *host = mmc_priv(mmc); + return au1xmmc_card_readonly(host); +} + struct mmc_host_ops au1xmmc_ops = { .request = au1xmmc_request, .set_ios = au1xmmc_set_ios, + .get_ro = au1xmmc_get_ro, }; static int au1xmmc_probe(struct device *dev) @@ -914,6 +930,7 @@ static int au1xmmc_probe(struct device * mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; + mmc->caps = MMC_CAP_4_BIT_DATA; mmc->ocr_avail = AU1XMMC_OCR; host = mmc_priv(mmc); @@ -923,7 +940,9 @@ static int au1xmmc_probe(struct device * host->iobase = au1xmmc_card_table[host->id].iobase; host->clock = 0; host->power_mode = MMC_POWER_OFF; - + + host->bus_width = MMC_BUS_WIDTH_1; + host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0; host->status = HOST_S_IDLE; @@ -1017,4 +1036,3 @@ MODULE_AUTHOR("Advanced Micro Devices, I MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); MODULE_LICENSE("GPL"); #endif - From jcrouse@cosmic.amd.com Fri Dec 2 18:51:12 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 18:51:34 +0000 (GMT) Received: from amdext4.amd.com ([163.181.251.6]:54182 "EHLO amdext4.amd.com") by ftp.linux-mips.org with ESMTP id S8133864AbVLBSvL (ORCPT ); Fri, 2 Dec 2005 18:51:11 +0000 Received: from SAUSGW02.amd.com (sausgw02.amd.com [163.181.250.22]) by amdext4.amd.com (8.12.11/8.12.11/AMD) with ESMTP id jB2Ishmh031036; Fri, 2 Dec 2005 12:54:43 -0600 Received: from 163.181.250.1 by SAUSGW01.amd.com with ESMTP (AMD SMTP Relay (Email Firewall v6.1.0)); Fri, 02 Dec 2005 12:54:37 -0600 X-Server-Uuid: 8C3DB987-180B-4465-9446-45C15473FD3E Received: from ldcmail.amd.com (ldcmail.amd.com [147.5.200.40]) by amdint2.amd.com (8.12.8/8.12.8/AMD) with ESMTP id jB2IsaTw004122; Fri, 2 Dec 2005 12:54:36 -0600 (CST) Received: from cosmic.amd.com (cosmic.amd.com [147.5.201.206]) by ldcmail.amd.com (Postfix) with ESMTP id 75138202D; Fri, 2 Dec 2005 11:54:36 -0700 (MST) Received: from cosmic.amd.com (localhost [127.0.0.1]) by cosmic.amd.com (8.13.4/8.13.4) with ESMTP id jB2J2NDU031398; Fri, 2 Dec 2005 12:02:23 -0700 Received: (from jcrouse@localhost) by cosmic.amd.com ( 8.13.4/8.13.4/Submit) id jB2J2NEF031397; Fri, 2 Dec 2005 12:02:23 -0700 Date: Fri, 2 Dec 2005 12:02:23 -0700 From: "Jordan Crouse" To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Subject: [PATCH] ALCHEMY: SPI driver for Au1200 Message-ID: <20051202190223.GG28227@cosmic.amd.com> MIME-Version: 1.0 User-Agent: Mutt/1.5.11 X-WSS-ID: 6F8E47E740G500239-01-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9578 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jordan.crouse@amd.com Precedence: bulk X-list: linux-mips A SPI driver for the Au1200 processor. Sending now so it can be queued for the post 2.6.15 rush. Signed-off-by: Jordan Crouse --- arch/mips/au1000/common/clocks.c | 2 drivers/char/Kconfig | 4 drivers/char/Makefile | 1 drivers/char/au1xxx_psc_spi.c | 492 +++++++++++++++++++++++++++++ include/asm-mips/mach-au1x00/au1550_spi.h | 38 ++ 5 files changed, 536 insertions(+), 1 deletions(-) diff --git a/arch/mips/au1000/common/clocks.c b/arch/mips/au1000/common/clocks.c index 3ce6cac..6dbc87a 100644 --- a/arch/mips/au1000/common/clocks.c +++ b/arch/mips/au1000/common/clocks.c @@ -46,7 +46,7 @@ unsigned int get_au1x00_speed(void) { return au1x00_clock; } - +EXPORT_SYMBOL(get_au1x00_speed); /* diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 2b0cf62..5501b12 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -351,6 +351,10 @@ config AU1XXX_CIM tristate "Au1200 Camera Interface Module (CIM)" depends on MIPS && SOC_AU1X00 && I2C_AU1550 +config AU1XXX_PSC_SPI + tristate ' Alchemy Au1550/Au1200 PSC SPI support' + depends on MIPS && SOC_AU1X00 && !I2C_AU1550 + config SIBYTE_SB1250_DUART bool "Support for BCM1xxx onchip DUART" depends on MIPS && SIBYTE_SB1xxx_SOC=y diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 6629394..b8bcfeb 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -83,6 +83,7 @@ obj-$(CONFIG_AU1000_GPIO) += au1000_gpio obj-$(CONFIG_AU1000_USB_TTY) += au1000_usbtty.o obj-$(CONFIG_AU1000_USB_RAW) += au1000_usbraw.o obj-$(CONFIG_AU1XXX_CIM) += au1xxx_cim.o +obj-$(CONFIG_AU1XXX_PSC_SPI) += au1xxx_psc_spi.o obj-$(CONFIG_PPDEV) += ppdev.o obj-$(CONFIG_NWBUTTON) += nwbutton.o obj-$(CONFIG_NWFLASH) += nwflash.o diff --git a/drivers/char/au1xxx_psc_spi.c b/drivers/char/au1xxx_psc_spi.c new file mode 100644 index 0000000..66d99e0 --- /dev/null +++ b/drivers/char/au1xxx_psc_spi.c @@ -0,0 +1,492 @@ +/* + * Driver for Alchemy Au1550 SPI on the PSC. + * + * Copyright 2004 Embedded Edge, LLC. + * dan@embeddededge.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MIPS_PB1550 +#include +#endif + +#ifdef CONFIG_MIPS_DB1550 +#include +#endif + +#ifdef CONFIG_MIPS_PB1200 +#include +#endif + +#ifdef CONFIG_MIPS_DB1200 +#include +#endif + +/* This is just a simple programmed I/O SPI interface on the PSC of the 1550. + * We support open, close, write, and ioctl. The SPI is a full duplex + * interface, you can't read without writing. So, the write system call + * copies the bytes out to the SPI, and whatever is returned is placed + * in the same buffer. Kinda weird, maybe we'll change it, but for now + * it works OK. + * I didn't implement any DMA yet, and it's a debate about the necessity. + * The SPI clocks are usually quite fast, so data is sent/received as + * quickly as you can stuff the FIFO. The overhead of DMA and interrupts + * are usually far greater than the data transfer itself. If, however, + * we find applications that move large amounts of data, we may choose + * use the overhead of buffering and DMA to do the work. + */ + +/* The maximum clock rate specified in the manual is 2mHz. +*/ +#define MAX_BAUD_RATE (2 * 1000000) +#define PSC_INTCLK_RATE (32 * 1000000) + +static int inuse; + +/* We have to know what the user requested for the data length + * so we know how to stuff the fifo. The FIFO is 32 bits wide, + * and we have to load it with the bits to go in a single transfer. + */ +static uint spi_datalen; + +static int +au1550spi_master_done( int ms ) +{ + int timeout=ms; + volatile psc_spi_t *sp; + + sp = (volatile psc_spi_t *)SPI_PSC_BASE; + + /* Loop until MD is set or timeout has expired */ + while(!(sp->psc_spievent & PSC_SPIEVNT_MD) && timeout--) udelay(1000); + + if ( !timeout ) + return 0; + else + sp->psc_spievent |= PSC_SPIEVNT_MD; + + return 1; +} + +static int +au1550spi_open(struct inode *inode, struct file *file) +{ + if (inuse) + return -EBUSY; + + inuse = 1; + + + return 0; +} + +static ssize_t +au1550spi_write(struct file *fp, const char *bp, size_t count, loff_t *ppos) +{ + int bytelen, i; + size_t rcount, retval; + unsigned char sb, *rp, *wp; + uint fifoword, pcr, stat; + volatile psc_spi_t *sp; + + /* Get the number of bytes per transfer. + */ + bytelen = ((spi_datalen - 1) / 8) + 1; + + /* User needs to send us multiple of this count. + */ + if ((count % bytelen) != 0) + return -EINVAL; + + rp = wp = (unsigned char *)bp; + retval = rcount = count; + + /* Reset the FIFO. + */ + sp = (volatile psc_spi_t *)SPI_PSC_BASE; + sp->psc_spipcr = (PSC_SPIPCR_RC | PSC_SPIPCR_TC); + au_sync(); + do { + pcr = sp->psc_spipcr; + au_sync(); + } while (pcr != 0); + + /* Prime the transmit FIFO. + */ + while (count > 0) { + fifoword = 0; + for (i=0; ipsc_spitxrx = fifoword; + au_sync(); + stat = sp->psc_spistat; + au_sync(); + if (stat & PSC_SPISTAT_TF) + break; + } + + /* Start the transfer. + */ + sp->psc_spipcr = PSC_SPIPCR_MS; + au_sync(); + + /* Now, just keep the transmit fifo full and empty the receive. + */ + while (count > 0) { + stat = sp->psc_spistat; + au_sync(); + while ((stat & PSC_SPISTAT_RE) == 0) { + fifoword = sp->psc_spitxrx; + au_sync(); + for (i=0; i>= 8; + rp++; + } + rcount -= bytelen; + stat = sp->psc_spistat; + au_sync(); + } + if ((stat & PSC_SPISTAT_TF) == 0) { + fifoword = 0; + for (i=0; ipsc_spitxrx = fifoword; + au_sync(); + } + } + + /* All of the bytes for transmit have been written. Hang + * out waiting for any residual bytes that are yet to be + * read from the fifo. + */ + while (rcount > 0) { + stat = sp->psc_spistat; + au_sync(); + if ((stat & PSC_SPISTAT_RE) == 0) { + fifoword = sp->psc_spitxrx; + au_sync(); + for (i=0; i>= 8; + rp++; + } + rcount -= bytelen; + } + } + + /* Wait for MasterDone event. 30ms timeout */ + if (!au1550spi_master_done(30) ) retval = -EFAULT; + return retval; +} + +static int +au1550spi_release(struct inode *inode, struct file *file) +{ + + inuse = 0; + + return 0; +} + +/* Set the baud rate closest to the request, then return the actual + * value we are using. + */ +static uint +set_baud_rate(uint baud) +{ + uint rate, tmpclk, brg, ctl, stat; + volatile psc_spi_t *sp; + + /* For starters, the input clock is divided by two. + */ + tmpclk = PSC_INTCLK_RATE/2; + + rate = tmpclk / baud; + + /* The dividers work as follows: + * baud = tmpclk / (2 * (brg + 1)) + */ + brg = (rate/2) - 1; + + /* Test BRG to ensure it will fit into the 6 bits allocated. + */ + + /* Make sure the device is disabled while we make the change. + */ + sp = (volatile psc_spi_t *)SPI_PSC_BASE; + ctl = sp->psc_spicfg; + au_sync(); + sp->psc_spicfg = ctl & ~PSC_SPICFG_DE_ENABLE; + au_sync(); + ctl = PSC_SPICFG_CLR_BAUD(ctl); + ctl |= PSC_SPICFG_SET_BAUD(brg); + sp->psc_spicfg = ctl; + au_sync(); + + /* If the device was running prior to getting here, wait for + * it to restart. + */ + if (ctl & PSC_SPICFG_DE_ENABLE) { + do { + stat = sp->psc_spistat; + au_sync(); + } while ((stat & PSC_SPISTAT_DR) == 0); + } + + /* Return the actual value. + */ + rate = tmpclk / (2 * (brg + 1)); + + return(rate); +} + +static uint +set_word_len(uint len) +{ + uint ctl, stat; + volatile psc_spi_t *sp; + + if ((len < 4) || (len > 24)) + return -EINVAL; + + /* Make sure the device is disabled while we make the change. + */ + sp = (volatile psc_spi_t *)SPI_PSC_BASE; + ctl = sp->psc_spicfg; + au_sync(); + sp->psc_spicfg = ctl & ~PSC_SPICFG_DE_ENABLE; + au_sync(); + ctl = PSC_SPICFG_CLR_LEN(ctl); + ctl |= PSC_SPICFG_SET_LEN(len); + sp->psc_spicfg = ctl; + au_sync(); + + /* If the device was running prior to getting here, wait for + * it to restart. + */ + if (ctl & PSC_SPICFG_DE_ENABLE) { + do { + stat = sp->psc_spistat; + au_sync(); + } while ((stat & PSC_SPISTAT_DR) == 0); + } + + return 0; +} + +static uint +set_clk_src(void) +{ + uint clk, rate; + +/* Wire up Freq3 as a clock for the SPI. The PSC does + * factor of 2 divisor, so run a higher rate so we can + * get some granularity to the clock speeds. + * We can't do this in board set up because the frequency + * is computed too late. + */ + rate = get_au1x00_speed(); + rate /= PSC_INTCLK_RATE; + + + + /* The FRDIV in the frequency control is (FRDIV + 1) * 2 + */ + rate /=2; + rate--; + clk = au_readl(SYS_FREQCTRL1); + + au_sync(); + clk &= ~SYS_FC_FRDIV3_MASK; + clk |= (rate << SYS_FC_FRDIV3_BIT); + clk |= SYS_FC_FE3; + au_writel(clk, SYS_FREQCTRL1); + au_sync(); + + /* Set up the clock source routing to get Freq3 to PSC0_intclk. + */ + clk = au_readl(SYS_CLKSRC); + au_sync(); +#if defined(CONFIG_SOC_AU1200) + clk &= ~SYS_CS_ME0_MASK; + clk |= (5 << 22); +#elif defined (CONFIG_SOC_AU1550) + clk &= ~0x03e0; + clk |= (5 << 7); +#endif + au_writel(clk, SYS_CLKSRC); + au_sync(); + + /* Set up GPIO pin function to drive PSC0_SYNC1, which is + * the SPI Select. + */ + clk = au_readl(SYS_PINFUNC); + au_sync(); +#if defined(CONFIG_SOC_AU1200) + clk |= (0x1 <<17); + clk &= ~SYS_PINFUNC_P0B; +#elif defined (CONFIG_SOC_AU1550) + clk |= 1; +#endif + au_writel(clk, SYS_PINFUNC); + au_sync(); + + return 0; +} + +static int +au1550spi_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int status; + u32 val; + + status = 0; + + switch(cmd) { + case AU1550SPI_WORD_LEN: + status = set_word_len(arg); + break; + + case AU1550SPI_SET_BAUD: + if (get_user(val, (u32 *)arg)) + return -EFAULT; + + val = set_baud_rate(val); + if (put_user(val, (u32 *)arg)) + return -EFAULT; + break; + + default: + status = -ENOIOCTLCMD; + + } + + return status; +} + +static struct file_operations au1550spi_fops = +{ .owner = THIS_MODULE, + .write = au1550spi_write, + .ioctl = au1550spi_ioctl, + .open = au1550spi_open, + .release = au1550spi_release, +}; + + +static struct miscdevice au1550spi_miscdev = +{ + .minor = MISC_DYNAMIC_MINOR, + .name = "au1550_spi", + .fops = &au1550spi_fops, +}; + + +int __init +au1550spi_init(void) +{ + uint stat; + volatile psc_spi_t *sp; + + /* Set clock Source*/ + set_clk_src(); + + /* Now, set up the PSC for SPI PIO mode. + */ + sp = (volatile psc_spi_t *)SPI_PSC_BASE; + sp->psc_ctrl = PSC_CTRL_DISABLE; + au_sync(); + sp->psc_sel = PSC_SEL_PS_SPIMODE; + sp->psc_spicfg = 0; + au_sync(); + sp->psc_ctrl = PSC_CTRL_ENABLE; + au_sync(); + + do { + stat = sp->psc_spistat; + au_sync(); + } while ((stat & PSC_SPISTAT_SR) == 0); + + + sp->psc_spicfg = (PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8 | + PSC_SPICFG_DD_DISABLE | PSC_SPICFG_MO); + sp->psc_spicfg |= PSC_SPICFG_SET_LEN(8); + spi_datalen = 8; + sp->psc_spimsk = PSC_SPIMSK_ALLMASK; + au_sync(); + + set_baud_rate(1000000); + + sp->psc_spicfg |= PSC_SPICFG_DE_ENABLE; + + do { + stat = sp->psc_spistat; + au_sync(); + } while ((stat & PSC_SPISTAT_DR) == 0); + + + misc_register(&au1550spi_miscdev); + return 0; +} + +void __exit +au1550spi_exit(void) +{ + misc_deregister(&au1550spi_miscdev); +} + +module_init(au1550spi_init); +module_exit(au1550spi_exit); diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/include/asm-mips/mach-au1x00/au1550_spi.h new file mode 100644 index 0000000..d956145 --- /dev/null +++ b/include/asm-mips/mach-au1x00/au1550_spi.h @@ -0,0 +1,38 @@ +/* + * API to Alchemy Au1550 SPI device. + * + * Copyright 2004 Embedded Edge, LLC. + * dan@embeddededge.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __AU1550_SPI_H +#define __AU1550_SPI_H + +#include + +#define AU1550SPI_IOC_MAGIC 'S' + +#define AU1550SPI_SET_BAUD _IOW(AU1550SPI_IOC_MAGIC, 0, int *) +#define AU1550SPI_WORD_LEN _IOW(AU1550SPI_IOC_MAGIC, 1, int) + +#endif /* __AU1000_SPI_H */ From jcrouse@cosmic.amd.com Fri Dec 2 18:52:20 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 18:52:40 +0000 (GMT) Received: from amdext4.amd.com ([163.181.251.6]:11687 "EHLO amdext4.amd.com") by ftp.linux-mips.org with ESMTP id S8133484AbVLBSwU (ORCPT ); Fri, 2 Dec 2005 18:52:20 +0000 Received: from SAUSGW02.amd.com (sausgw02.amd.com [163.181.250.22]) by amdext4.amd.com (8.12.11/8.12.11/AMD) with ESMTP id jB2Itsmw031880; Fri, 2 Dec 2005 12:55:54 -0600 Received: from 163.181.250.1 by SAUSGW02.amd.com with ESMTP (AMD SMTP Relay (Email Firewall v6.1.0)); Fri, 02 Dec 2005 12:55:49 -0600 X-Server-Uuid: 5FC0E2DF-CD44-48CD-883A-0ED95B391E89 Received: from ldcmail.amd.com (ldcmail.amd.com [147.5.200.40]) by amdint2.amd.com (8.12.8/8.12.8/AMD) with ESMTP id jB2ItmTw004426; Fri, 2 Dec 2005 12:55:48 -0600 (CST) Received: from cosmic.amd.com (cosmic.amd.com [147.5.201.206]) by ldcmail.amd.com (Postfix) with ESMTP id 0C7782026; Fri, 2 Dec 2005 11:55:48 -0700 (MST) Received: from cosmic.amd.com (localhost [127.0.0.1]) by cosmic.amd.com (8.13.4/8.13.4) with ESMTP id jB2J3Z0P031409; Fri, 2 Dec 2005 12:03:35 -0700 Received: (from jcrouse@localhost) by cosmic.amd.com ( 8.13.4/8.13.4/Submit) id jB2J3ZVS031408; Fri, 2 Dec 2005 12:03:35 -0700 Date: Fri, 2 Dec 2005 12:03:35 -0700 From: "Jordan Crouse" To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Subject: [PATCH] ALCHEMY: AU1200 I2C modifications Message-ID: <20051202190335.GH28227@cosmic.amd.com> MIME-Version: 1.0 User-Agent: Mutt/1.5.11 X-WSS-ID: 6F8E473F2MW515595-01-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9579 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jordan.crouse@amd.com Precedence: bulk X-list: linux-mips Modifications to the existing AU1XXX I2C controller for the Au1200. Sending now to be included in the post 2.6.15 rush. Signed-off-by: Jordan Crouse --- arch/mips/au1000/db1x00/board_setup.c | 37 +++++++++++++++++++++++++++++ drivers/i2c/busses/Kconfig | 2 +- drivers/i2c/busses/i2c-au1550.c | 29 ++++++++++++++++++----- include/asm-mips/mach-au1x00/au1xxx_psc.h | 7 +++++ 4 files changed, 67 insertions(+), 8 deletions(-) diff --git a/arch/mips/au1000/db1x00/board_setup.c b/arch/mips/au1000/db1x00/board_setup.c index f00ec3b..a2638c8 100644 --- a/arch/mips/au1000/db1x00/board_setup.c +++ b/arch/mips/au1000/db1x00/board_setup.c @@ -76,6 +76,43 @@ void __init board_setup(void) #endif bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */ +#if defined(CONFIG_I2C_AU1550) && defined(CONFIG_MIPS_DB1200) + { + u32 freq0, clksrc; + + /* Select SMBUS in CPLD */ + bcsr->resets &= ~(BCSR_RESETS_PCS0MUX); + + pin_func = au_readl(SYS_PINFUNC); + au_sync(); + pin_func &= ~(3<<17 | 1<<4); + /* Set GPIOs correctly */ + pin_func |= 2<<17; + au_writel(pin_func, SYS_PINFUNC); + au_sync(); + + /* The i2c driver depends on 50Mhz clock */ + freq0 = au_readl(SYS_FREQCTRL0); + au_sync(); + freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); + freq0 |= (3< #include -#include +#if defined(CONFIG_MIPS_PB1550) + #include +#endif +#if defined(CONFIG_MIPS_PB1200) + #include +#endif +#if defined(CONFIG_MIPS_DB1200) + #include +#endif #include #include "i2c-au1550.h" @@ -118,13 +126,20 @@ do_address(struct i2c_au1550_data *adap, /* Reset the FIFOs, clear events. */ - sp->psc_smbpcr = PSC_SMBPCR_DC; + stat = sp->psc_smbstat; sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR; au_sync(); - do { - stat = sp->psc_smbpcr; + + if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) + { + sp->psc_smbpcr = PSC_SMBPCR_DC; au_sync(); - } while ((stat & PSC_SMBPCR_DC) != 0); + do { + stat = sp->psc_smbpcr; + au_sync(); + } while ((stat & PSC_SMBPCR_DC) != 0); + udelay(50); + } /* Write out the i2c chip address and specify operation */ @@ -367,7 +382,7 @@ static struct i2c_au1550_data pb1550_i2c SMBUS_PSC_BASE, 200, 200 }; -static struct i2c_adapter pb1550_board_adapter = { +struct i2c_adapter pb1550_board_adapter = { name: "pb1550 adapter", id: I2C_HW_AU1550_PSC, algo: NULL, @@ -376,6 +391,8 @@ static struct i2c_adapter pb1550_board_a client_unregister: pb1550_unreg, }; +EXPORT_SYMBOL(pb1550_board_adapter); + /* BIG hack to support the control interface on the Wolfson WM8731 * audio codec on the Pb1550 board. We get an address and two data * bytes to write, create an i2c message, and send it across the diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h index 8e5fb3c..45a05c8 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_psc.h +++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h @@ -43,6 +43,11 @@ #define PSC3_BASE_ADDR 0xb0d00000 #endif +#ifdef CONFIG_SOC_AU1200 +#define PSC0_BASE_ADDR 0xb1a00000 +#define PSC1_BASE_ADDR 0xb1b00000 +#endif + /* The PSC select and control registers are common to * all protocols. */ @@ -506,7 +511,7 @@ typedef struct psc_smb { /* Transmit register control. */ -#define PSC_SMBTXRX_RSR (1 << 30) +#define PSC_SMBTXRX_RSR (1 << 28) #define PSC_SMBTXRX_STP (1 << 29) #define PSC_SMBTXRX_DATAMASK (0xff) From jcrouse@cosmic.amd.com Fri Dec 2 18:55:32 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 18:55:59 +0000 (GMT) Received: from amdext3.amd.com ([139.95.251.6]:49116 "EHLO amdext3.amd.com") by ftp.linux-mips.org with ESMTP id S8133871AbVLBSzc (ORCPT ); Fri, 2 Dec 2005 18:55:32 +0000 Received: from SSVLGW02.amd.com (ssvlgw02.amd.com [139.95.250.170]) by amdext3.amd.com (8.12.11/8.12.11/AMD) with ESMTP id jB2Iwl12009988; Fri, 2 Dec 2005 10:59:07 -0800 Received: from 139.95.250.1 by SSVLGW02.amd.com with ESMTP (AMD SMTP Relay (Email Firewall v6.1.0)); Fri, 02 Dec 2005 10:58:50 -0800 X-Server-Uuid: 519AC16A-9632-469E-B354-112C592D09E8 Received: from ldcmail.amd.com (ldcmail.amd.com [147.5.200.40]) by amdint.amd.com (8.12.8/8.12.8/AMD) with ESMTP id jB2IwnQe022259; Fri, 2 Dec 2005 10:58:49 -0800 (PST) Received: from cosmic.amd.com (cosmic.amd.com [147.5.201.206]) by ldcmail.amd.com (Postfix) with ESMTP id DAF6B2026; Fri, 2 Dec 2005 11:58:48 -0700 (MST) Received: from cosmic.amd.com (localhost [127.0.0.1]) by cosmic.amd.com (8.13.4/8.13.4) with ESMTP id jB2J6aZW031451; Fri, 2 Dec 2005 12:06:36 -0700 Received: (from jcrouse@localhost) by cosmic.amd.com ( 8.13.4/8.13.4/Submit) id jB2J6Zl5031450; Fri, 2 Dec 2005 12:06:35 -0700 Date: Fri, 2 Dec 2005 12:06:35 -0700 From: "Jordan Crouse" To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Subject: [PATCH] ALCHEMY: Alchemy Camera Interface (CIM) driver Message-ID: <20051202190635.GI28227@cosmic.amd.com> MIME-Version: 1.0 User-Agent: Mutt/1.5.11 X-WSS-ID: 6F8E46E01IW1436034-01-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9580 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jordan.crouse@amd.com Precedence: bulk X-list: linux-mips A driver for the AU1200 Camera Interface (CIM). Definately should be postponed post 2.6.15. This is the most complex one I'm sending up right now, so comments and flames are definately welcome. Signed-off-by: Jordan Crouse --- drivers/Makefile | 2 drivers/char/Kconfig | 4 drivers/char/Makefile | 1 drivers/char/au1xxx_cameras.h | 572 ++++++++++++++++++++++++++ drivers/char/au1xxx_cim.c | 647 +++++++++++++++++++++++++++++ include/asm-mips/mach-au1x00/au1xxx_cim.h | 190 +++++++++ 6 files changed, 1415 insertions(+), 1 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index fac1e16..7ab1608 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PNP) += pnp/ # char/ comes before serial/ etc so that the VT console is the boot-time # default. +obj-$(CONFIG_I2C) += i2c/ obj-y += char/ obj-$(CONFIG_CONNECTOR) += connector/ @@ -53,7 +54,6 @@ obj-$(CONFIG_USB_GADGET) += usb/gadget/ obj-$(CONFIG_GAMEPORT) += input/gameport/ obj-$(CONFIG_INPUT) += input/ obj-$(CONFIG_I2O) += message/ -obj-$(CONFIG_I2C) += i2c/ obj-$(CONFIG_W1) += w1/ obj-$(CONFIG_HWMON) += hwmon/ obj-$(CONFIG_PHONE) += telephony/ diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 9424f62..2b0cf62 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -347,6 +347,10 @@ config AU1X00_USB_RAW tristate "Au1000 USB Raw Device support" depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_TTY!=y && AU1X00_USB_DEVICE +config AU1XXX_CIM + tristate "Au1200 Camera Interface Module (CIM)" + depends on MIPS && SOC_AU1X00 && I2C_AU1550 + config SIBYTE_SB1250_DUART bool "Support for BCM1xxx onchip DUART" depends on MIPS && SIBYTE_SB1xxx_SOC=y diff --git a/drivers/char/Makefile b/drivers/char/Makefile index ecc5670..6629394 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -82,6 +82,7 @@ obj-$(CONFIG_ITE_GPIO) += ite_gpio.o obj-$(CONFIG_AU1000_GPIO) += au1000_gpio.o obj-$(CONFIG_AU1000_USB_TTY) += au1000_usbtty.o obj-$(CONFIG_AU1000_USB_RAW) += au1000_usbraw.o +obj-$(CONFIG_AU1XXX_CIM) += au1xxx_cim.o obj-$(CONFIG_PPDEV) += ppdev.o obj-$(CONFIG_NWBUTTON) += nwbutton.o obj-$(CONFIG_NWFLASH) += nwflash.o diff --git a/drivers/char/au1xxx_cameras.h b/drivers/char/au1xxx_cameras.h new file mode 100644 index 0000000..3ecfa30 --- /dev/null +++ b/drivers/char/au1xxx_cameras.h @@ -0,0 +1,572 @@ +#ifndef AU1XXX_CAMERAS_H_ +#define AU1XXX_CAMERAS_H_ + +/* List of cameras to be used with the AU1XXX Camera interface + Copyright 2005, Advanced Micro Devices, Inc. + + This software may be used and distributed according to the terms + of the GNU General Public License, incorporated herein by reference. +*/ + + +typedef struct cim_cmos_camera_config { + uint32_t frame_width; /* Frame Width (Pixel per Line) */ + uint32_t frame_height; /* Frame Height */ + unsigned char camera_name[32]; /* Camera Name (Display/Debug) */ + unsigned char camera_mode[32]; /* Camera Mode(Display/Debug) */ + uint32_t cmos_output_format; /* CMOS Camera output */ + uint32_t camera_resformat; /* Camera Mode(Display/Debug) */ + uint32_t au1200_dpsmode; /* Data Pattern Select */ + uint32_t au1200_baymode; /* Mode within BAYER mode */ + uint32_t dbdma_channel; /* Number of channels to be used */ + u8 device_addr; /* Camera Device address */ + uint32_t cmd_size; /* Number of device sub register */ + u8 config_cmd[MAX_DEVICE_CMD][2]; /* Sub device address and values */ +} CAMERA; + + + +static CAMERA au1xxx_cameras[] = { + /* Omnivision OV9640 Camera 1280x960 Mode (SXGA) in "Pass Thru Mode" + 1.3 MP at 15 Fps + */ + + { 1280, 960, "omnivision", "raw_SXGA", CMOS_RAW, + RAW_SXGA, CIM_CONFIG_RAW, CIM_CONFIG_BGGR, + 1, 0x30, 50, + { + {0x12, 0x80}, {0x12, 0x05}, {0x11, 0x80}, + {0x3b, 0x00}, {0x33, 0x02}, + {0x37, 0x02}, {0x38, 0x13}, {0x39, 0xf0}, + {0x6c, 0x40}, {0x6d, 0x30}, + {0x6e, 0x4b}, {0x6f, 0x60}, {0x70, 0x70}, + {0x71, 0x70}, {0x74, 0x60}, + {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48}, + {0x78, 0x3a}, {0x79, 0x2e}, + {0x7a, 0x2a}, {0x7b, 0x22}, {0x7c, 0x04}, + {0x7d, 0x07}, {0x7e, 0x10}, + {0x7f, 0x28}, {0x80, 0x36}, {0x81, 0x44}, + {0x82, 0x52}, {0x83, 0x60}, + {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, + {0x87, 0x9e}, {0x88, 0xbb}, + {0x89, 0xd2}, {0x8a, 0xe6}, {0x0f, 0x4f}, + {0x3c, 0x40}, {0x14, 0xca}, + {0x42, 0x89}, {0x24, 0x78}, {0x25, 0x68}, + {0x26, 0xd4}, {0x27, 0x90}, + {0x2a, 0x00}, {0x2b, 0x00}, {0x3d, 0x80}, + {0x41, 0x00}, {0x60, 0x8d}, + } + }, + + /* Omnivision OV9640 Camera 640x480 Mode (VGA) in "Pass Through Mode" */ + { 640, 480, "omnivision", "raw_VGA", CMOS_RAW, + RAW_VGA,CIM_CONFIG_RAW,CIM_CONFIG_BGGR, + 1, 0x30, 54, + { + {0x12, 0x80}, {0x12, 0x45}, {0x11, 0x81}, + {0x0c, 0x04}, {0x0d, 0x40}, {0x3b, 0x00}, + {0x33, 0x02}, + {0x37, 0x02}, {0x38, 0x13}, {0x39, 0xf0}, + {0x6c, 0x40}, {0x6d, 0x30}, + {0x6e, 0x4b}, {0x6f, 0x60}, {0x70, 0x70}, + {0x71, 0x70}, {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, + {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48}, + {0x78, 0x3a}, {0x79, 0x2e}, + {0x7a, 0x28}, {0x7b, 0x22}, {0x7c, 0x04}, + {0x7d, 0x07}, {0x7e, 0x2e}, + {0x7f, 0x28}, {0x80, 0x36}, {0x81, 0x44}, + {0x82, 0x52}, {0x83, 0x60}, + {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, + {0x87, 0x9e}, {0x88, 0xbb}, + {0x89, 0xd2}, {0x8a, 0xe6}, {0x0f, 0x4f}, + {0x3c, 0x40}, {0x14, 0xca}, + {0x42, 0x89}, {0x24, 0x78}, {0x25, 0x68}, + {0x26, 0xd4}, {0x27, 0x90}, + {0x2a, 0x00}, {0x2b, 0x00}, {0x3d, 0x80}, + {0x41, 0x00}, {0x60, 0x8d}, + } + }, + + /* Omnivision OV9640 Camera 352x288 Mode CIF "Pass Through Mode" */ + { 352, 288, "omnivision", "raw_CIF", CMOS_RAW, + RAW_CIF, CIM_CONFIG_RAW, CIM_CONFIG_BGGR, + 1, 0x30, 54, + { + {0x12, 0x80}, {0x12, 0x25}, {0x11, 0x80}, + {0x0c, 0x04}, {0x0d, 0x40}, {0x3b, 0x00}, + {0x33, 0x02}, + {0x37, 0x02}, {0x38, 0x13}, {0x39, 0xf0}, + {0x6c, 0x40}, {0x6d, 0x30}, + {0x6e, 0x4b}, {0x6f, 0x60}, {0x70, 0x70}, + {0x71, 0x70}, {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, + {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48}, + {0x78, 0x3a}, {0x79, 0x2e}, + {0x7a, 0x28}, {0x7b, 0x22}, {0x7c, 0x04}, + {0x7d, 0x07}, {0x7e, 0x10}, + {0x7f, 0x28}, {0x80, 0x36}, {0x81, 0x44}, + {0x82, 0x52}, {0x83, 0x60}, + {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, + {0x87, 0x9e}, {0x88, 0xbb}, + {0x89, 0xd2}, {0x8a, 0xe6}, {0x0f, 0x4f}, + {0x3c, 0x40}, {0x14, 0xca}, + {0x42, 0x89}, {0x24, 0x78}, {0x25, 0x68}, + {0x26, 0xd4}, {0x27, 0x90}, + {0x2a, 0x00}, {0x2b, 0x00}, {0x3d, 0x80}, + {0x41, 0x00}, {0x60, 0x8d}, + } + + }, + + /* Omnivision OV9640 Camera 320x240 Mode (QVGA) in "Pass Through Mode" */ + { 320, 240, "omnivision", "raw_QVGA", CMOS_RAW, + RAW_QVGA, CIM_CONFIG_RAW, CIM_CONFIG_BGGR, + 1, 0x30, 54, + { + {0x12, 0x80}, {0x12, 0x15}, {0x11, 0x83}, + {0x0c, 0x04}, {0x0d, 0xc0}, {0x3b, 0x00}, + {0x33, 0x02}, + {0x37, 0x02}, {0x38, 0x13}, {0x39, 0xf0}, + {0x6c, 0x40}, {0x6d, 0x30}, + {0x6e, 0x4b}, {0x6f, 0x60}, {0x70, 0x70}, + {0x71, 0x70}, {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, + {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48}, + {0x78, 0x3a}, {0x79, 0x2e}, + {0x7a, 0x28}, {0x7b, 0x22}, {0x7c, 0x04}, + {0x7d, 0x07}, {0x7e, 0x10}, + {0x7f, 0x28}, {0x80, 0x36}, {0x81, 0x44}, + {0x82, 0x52}, {0x83, 0x60}, + {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, + {0x87, 0x9e}, {0x88, 0xbb}, + {0x89, 0xd2}, {0x8a, 0xe6}, {0x0f, 0x4f}, + {0x3c, 0x40}, {0x14, 0xca}, + {0x42, 0x89}, {0x24, 0x78}, {0x25, 0x68}, + {0x26, 0xd4}, {0x27, 0x90}, + {0x2a, 0x00}, {0x2b, 0x00}, {0x3d, 0x80}, + {0x41, 0x00}, {0x60, 0x8d}, + } + }, + + /* Omnivision OV9640 Camera 176x144 QCIF Mode "Pass Through Mode" */ + { 176, 144, "omnivision", "raw_QCIF", CMOS_RAW, + RAW_QCIF, CIM_CONFIG_RAW, CIM_CONFIG_BGGR, + 1, 0x30, 54, + { + {0x12, 0x80}, {0x12, 0x0D}, {0x11, 0x80}, + {0x0c, 0x04}, {0x0d, 0xc0}, {0x3b, 0x00}, + {0x33, 0x02}, + {0x37, 0x02}, {0x38, 0x13}, {0x39, 0xf0}, + {0x6c, 0x40}, {0x6d, 0x30}, + {0x6e, 0x4b}, {0x6f, 0x60}, {0x70, 0x70}, + {0x71, 0x70}, {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, + {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48}, + {0x78, 0x3a}, {0x79, 0x2e}, + {0x7a, 0x28}, {0x7b, 0x22}, {0x7c, 0x04}, + {0x7d, 0x07}, {0x7e, 0x10}, + {0x7f, 0x28}, {0x80, 0x36}, {0x81, 0x44}, + {0x82, 0x52}, {0x83, 0x60}, + {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, + {0x87, 0x9e}, {0x88, 0xbb}, + {0x89, 0xd2}, {0x8a, 0xe6}, {0x0f, 0x6f}, + {0x3c, 0x60}, {0x14, 0xca}, + {0x42, 0x89}, {0x24, 0x78}, {0x25, 0x68}, + {0x26, 0xd4}, {0x27, 0x90}, + {0x2a, 0x00}, {0x2b, 0x00}, {0x3d, 0x80}, + {0x41, 0x00}, {0x60, 0x8d}, + } + }, + + + /* Omnivision OV9640 Camera 1280x960 Mode (SXGA) in BAYER Mode (Planar) */ + { 1280, 960, "omnivision", "bayer_SXGA", CMOS_RAW, + BAYER_SXGA, CIM_CONFIG_BAYER, CIM_CONFIG_BGGR, + 3, 0x30, 50, + { + {0x12, 0x80}, {0x12, 0x05}, {0x11, 0x80}, + {0x3b, 0x00}, {0x33, 0x02}, + {0x37, 0x02}, {0x38, 0x13}, {0x39, 0xf0}, + {0x6c, 0x40}, {0x6d, 0x30}, + {0x6e, 0x4b}, {0x6f, 0x60}, {0x70, 0x70}, + {0x71, 0x70}, {0x74, 0x60}, + {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48}, + {0x78, 0x3a}, {0x79, 0x2e}, + {0x7a, 0x2a}, {0x7b, 0x22}, {0x7c, 0x04}, + {0x7d, 0x07}, {0x7e, 0x10}, + {0x7f, 0x28}, {0x80, 0x36}, {0x81, 0x44}, + {0x82, 0x52}, {0x83, 0x60}, + {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, + {0x87, 0x9e}, {0x88, 0xbb}, + {0x89, 0xd2}, {0x8a, 0xe6}, {0x0f, 0x4f}, + {0x3c, 0x40}, {0x14, 0xca}, + {0x42, 0x89}, {0x24, 0x78}, {0x25, 0x68}, + {0x26, 0xd4}, {0x27, 0x90}, + {0x2a, 0x00}, {0x2b, 0x00}, {0x3d, 0x80}, + {0x41, 0x00}, {0x60, 0x8d}, + } + }, + + /* Omnivision OV9640 Camera 640x480 Mode (VGA) in BAYER Mode (Planar) */ + { 640, 480, "omnivision", "bayer_VGA", CMOS_RAW, + BAYER_VGA, CIM_CONFIG_BAYER, CIM_CONFIG_BGGR, + 3, 0x30, 54, + { + {0x12, 0x80}, {0x12, 0x45}, {0x11, 0x81}, + {0x0c, 0x04}, {0x0d, 0x40}, {0x3b, 0x00}, + {0x33, 0x02}, + {0x37, 0x02}, {0x38, 0x13}, {0x39, 0xf0}, + {0x6c, 0x40}, {0x6d, 0x30}, + {0x6e, 0x4b}, {0x6f, 0x60}, {0x70, 0x70}, + {0x71, 0x70}, {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, + {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48}, + {0x78, 0x3a}, {0x79, 0x2e}, + {0x7a, 0x28}, {0x7b, 0x22}, {0x7c, 0x04}, + {0x7d, 0x07}, {0x7e, 0x2e}, + {0x7f, 0x28}, {0x80, 0x36}, {0x81, 0x44}, + {0x82, 0x52}, {0x83, 0x60}, + {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, + {0x87, 0x9e}, {0x88, 0xbb}, + {0x89, 0xd2}, {0x8a, 0xe6}, {0x0f, 0x4f}, + {0x3c, 0x40}, {0x14, 0xca}, + {0x42, 0x89}, {0x24, 0x78}, {0x25, 0x68}, + {0x26, 0xd4}, {0x27, 0x90}, + {0x2a, 0x00}, {0x2b, 0x00}, {0x3d, 0x80}, + {0x41, 0x00}, {0x60, 0x8d}, + } + }, + + /* Omnivision OV9640 Camera 352x288 CIF Mode in BAYER Mode (Planar) */ + { 352, 288, "omnivision", "bayer_CIF", CMOS_RAW, + BAYER_CIF, CIM_CONFIG_BAYER, CIM_CONFIG_BGGR, + 3, 0x30, 54, + { + {0x12, 0x80}, {0x12, 0x25}, {0x11, 0x80}, + {0x0c, 0x04}, {0x0d, 0x40}, {0x3b, 0x00}, + {0x33, 0x02}, + {0x37, 0x02}, {0x38, 0x13}, {0x39, 0xf0}, + {0x6c, 0x40}, {0x6d, 0x30}, + {0x6e, 0x4b}, {0x6f, 0x60}, {0x70, 0x70}, + {0x71, 0x70}, {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, + {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48}, + {0x78, 0x3a}, {0x79, 0x2e}, + {0x7a, 0x28}, {0x7b, 0x22}, {0x7c, 0x04}, + {0x7d, 0x07}, {0x7e, 0x10}, + {0x7f, 0x28}, {0x80, 0x36}, {0x81, 0x44}, + {0x82, 0x52}, {0x83, 0x60}, + {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, + {0x87, 0x9e}, {0x88, 0xbb}, + {0x89, 0xd2}, {0x8a, 0xe6}, {0x0f, 0x4f}, + {0x3c, 0x40}, {0x14, 0xca}, + {0x42, 0x89}, {0x24, 0x78}, {0x25, 0x68}, + {0x26, 0xd4}, {0x27, 0x90}, + {0x2a, 0x00}, {0x2b, 0x00}, {0x3d, 0x80}, + {0x41, 0x00}, {0x60, 0x8d}, + } + }, + + /* Omnivision OV9640 Camera 320x240 Mode (QVGA) in BAYER Mode (Planar) */ + { 320, 240, "omnivision", "bayer_QVGA", CMOS_RAW, + BAYER_QVGA, CIM_CONFIG_BAYER, CIM_CONFIG_BGGR, + 3, 0x30, 54, + { + {0x12, 0x80}, {0x12, 0x15}, {0x11, 0x83}, + {0x0c, 0x04}, {0x0d, 0xc0}, {0x3b, 0x00}, + {0x33, 0x02}, + {0x37, 0x02}, {0x38, 0x13}, {0x39, 0xf0}, + {0x6c, 0x40}, {0x6d, 0x30}, + {0x6e, 0x4b}, {0x6f, 0x60}, {0x70, 0x70}, + {0x71, 0x70}, {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, + {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48}, + {0x78, 0x3a}, {0x79, 0x2e}, + {0x7a, 0x28}, {0x7b, 0x22}, {0x7c, 0x04}, + {0x7d, 0x07}, {0x7e, 0x10}, + {0x7f, 0x28}, {0x80, 0x36}, {0x81, 0x44}, + {0x82, 0x52}, {0x83, 0x60}, + {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, + {0x87, 0x9e}, {0x88, 0xbb}, + {0x89, 0xd2}, {0x8a, 0xe6}, {0x0f, 0x4f}, + {0x3c, 0x40}, {0x14, 0xca}, + {0x42, 0x89}, {0x24, 0x78}, {0x25, 0x68}, + {0x26, 0xd4}, {0x27, 0x90}, + {0x2a, 0x00}, {0x2b, 0x00}, {0x3d, 0x80}, + {0x41, 0x00}, {0x60, 0x8d}, + } + }, + + /* Omnivision OV9640 Camera 640x480 Mode (QCIF) in BAYER Mode (Planar) */ + { 176, 144, "omnivision", "bayer_QCIF", CMOS_RAW, + BAYER_QCIF, CIM_CONFIG_BAYER, CIM_CONFIG_BGGR, + 3, 0x30, 54, + { + {0x12, 0x80}, {0x12, 0x0D}, {0x11, 0x80}, + {0x0c, 0x04}, {0x0d, 0xc0}, {0x3b, 0x00}, + {0x33, 0x02}, + {0x37, 0x02}, {0x38, 0x13}, {0x39, 0xf0}, + {0x6c, 0x40}, {0x6d, 0x30}, + {0x6e, 0x4b}, {0x6f, 0x60}, {0x70, 0x70}, + {0x71, 0x70}, {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, + {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48}, + {0x78, 0x3a}, {0x79, 0x2e}, + {0x7a, 0x28}, {0x7b, 0x22}, {0x7c, 0x04}, + {0x7d, 0x07}, {0x7e, 0x10}, + {0x7f, 0x28}, {0x80, 0x36}, {0x81, 0x44}, + {0x82, 0x52}, {0x83, 0x60}, + {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, + {0x87, 0x9e}, {0x88, 0xbb}, + {0x89, 0xd2}, {0x8a, 0xe6}, {0x0f, 0x6f}, + {0x3c, 0x60}, {0x14, 0xca}, + {0x42, 0x89}, {0x24, 0x78}, {0x25, 0x68}, + {0x26, 0xd4}, {0x27, 0x90}, + {0x2a, 0x00}, {0x2b, 0x00}, {0x3d, 0x80}, + {0x41, 0x00}, {0x60, 0x8d}, + } + }, + + /* Omnivision OV9640 Camera 1280x960 Mode (SXGA) in YCbCr Camera pass Thru Mode */ + { 1280, 960, "omnivision", "YCbCr_SXGA", CMOS_CCIR656, + YCbCr_SXGA_RAW, CIM_CONFIG_RAW, CIM_CONFIG_BGGR, + 1, 0x30, 115, + { + {0x12, 0x80}, {0x11, 0x80}, {0x12, 0x00}, + {0x13, 0xA8}, {0x01, 0x80}, + {0x02, 0x80}, {0x04, 0x40}, {0x0C, 0x04}, + {0x0D, 0xC0}, {0x0E, 0x81}, + {0x0f, 0x4F}, {0x14, 0x4A}, {0x16, 0x02}, + {0x1B, 0x01}, {0x24, 0x70}, + {0x25, 0x68}, {0x26, 0xD3}, {0x27, 0x90}, + {0x2A, 0x00}, {0x2B, 0x00}, + {0x33, 0x28}, {0x37, 0x02}, {0x38, 0x13}, + {0x39, 0xF0}, {0x3A, 0x00}, + {0x3B, 0x01}, {0x3C, 0x46}, {0x3D, 0x90}, + {0x3E, 0x02}, {0x3F, 0xF2}, + {0x41, 0x02}, {0x42, 0xC9}, {0x43, 0xF0}, + {0x44, 0x10}, {0x45, 0x6C}, + {0x46, 0x6C}, {0x47, 0x44}, {0x48, 0x44}, + {0x49, 0x03}, {0x4F, 0x50}, + {0x50, 0x43}, {0x51, 0x0D}, {0x52, 0x19}, + {0x53, 0x4C}, {0x54, 0x65}, + {0x59, 0x49}, {0x5A, 0x94}, {0x5B, 0x46}, + {0x5C, 0x84}, {0x5D, 0x5C}, + {0x5E, 0x08}, {0x5F, 0x00}, {0x60, 0x14}, + {0x61, 0xCE}, {0x62, 0x70}, + {0x63, 0x00}, {0x64, 0x04}, {0x65, 0x00}, + {0x66, 0x00}, {0x69, 0x00}, + {0x6A, 0x3E}, {0x6B, 0x3F}, {0x6C, 0x40}, + {0x6D, 0x30}, {0x6E, 0x4B}, + {0x6F, 0x60}, {0x70, 0x70}, {0x71, 0x70}, + {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x70}, {0x75, 0x60}, {0x76, 0x50}, + {0x77, 0x48}, {0x78, 0x3A}, + {0x79, 0x2E}, {0x7A, 0x28}, {0x7B, 0x22}, + {0x7C, 0x04}, {0x7D, 0x07}, + {0x7E, 0x10}, {0x7F, 0x28}, {0x80, 0x36}, + {0x81, 0x44}, {0x82, 0x52}, + {0x83, 0x60}, {0x84, 0x6C}, {0x85, 0x78}, + {0x86, 0x8C}, {0x87, 0x9E}, + {0x88, 0xBB}, {0x89, 0xD2}, {0x8A, 0xE6}, + {0x13, 0xAF}, {0x13, 0x8D}, + {0x01, 0x80}, {0x02, 0x80}, {0x42, 0xC9}, + {0x16, 0x02}, {0x43, 0xF0}, + {0x44, 0x10}, {0x45, 0x20}, {0x46, 0x20}, + {0x47, 0x20}, {0x48, 0x20}, + {0x59, 0x17}, {0x5A, 0x71}, {0x5B, 0x56}, + {0x5C, 0x74}, {0x5D, 0x68}, + {0x5e, 0x10}, {0x5f, 0x00}, {0x60, 0x14}, + {0x61, 0xCE}, {0x13, 0x8F}, + } + }, + + /* Omnivision OV9640 Camera 640x480 Mode (SXGA) in YCbCr Camera pass Thru Mode */ + { 640, 480, "omnivision", "YCbCr_VGA_raw", CMOS_CCIR656, + YCbCr_VGA_RAW, CIM_CONFIG_RAW, CIM_CONFIG_BGGR, + 1, 0x30, 94, + { + {0x12, 0x80}, {0x11, 0x81}, {0x12, 0x40}, + {0x13, 0xA8}, {0x01, 0x80}, + {0x02, 0x80}, {0x04, 0x40}, {0x0C, 0x04}, + {0x0D, 0xC0}, {0x0E, 0x81}, + {0x0f, 0x4F}, {0x14, 0x4A}, {0x16, 0x02}, + {0x1B, 0x01}, {0x24, 0x70}, + {0x25, 0x68}, {0x26, 0xD3}, {0x27, 0x90}, + {0x2A, 0x00}, {0x2B, 0x00}, + {0x33, 0x02}, {0x37, 0x02}, {0x38, 0x13}, + {0x39, 0xF0}, {0x3A, 0x00}, + {0x3B, 0x01}, {0x3C, 0x46}, {0x3D, 0x90}, + {0x3E, 0x02}, {0x3F, 0xF2}, + {0x41, 0x02}, {0x42, 0xC9}, {0x43, 0xF0}, + {0x44, 0x10}, {0x45, 0x6C}, + {0x46, 0x6C}, {0x47, 0x44}, {0x48, 0x44}, + {0x49, 0x03}, {0x4F, 0x50}, + {0x50, 0x43}, {0x51, 0x0D}, {0x52, 0x19}, + {0x53, 0x4C}, {0x54, 0x65}, + {0x59, 0x49}, {0x5A, 0x94}, {0x5B, 0x46}, + {0x5C, 0x84}, {0x5D, 0x5C}, + {0x5E, 0x08}, {0x5F, 0x00}, {0x60, 0x14}, + {0x61, 0xCE}, {0x62, 0x70}, + {0x63, 0x00}, {0x64, 0x04}, {0x65, 0x00}, + {0x66, 0x00}, {0x69, 0x00}, + {0x6A, 0x3E}, {0x6B, 0x3F}, {0x6C, 0x40}, + {0x6D, 0x30}, {0x6E, 0x4B}, + {0x6F, 0x60}, {0x70, 0x70}, {0x71, 0x70}, + {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, {0x75, 0x60}, {0x76, 0x50}, + {0x77, 0x48}, {0x78, 0x3A}, + {0x79, 0x2E}, {0x7A, 0x28}, {0x7B, 0x22}, + {0x7C, 0x04}, {0x7D, 0x07}, + {0x7E, 0x10}, {0x7F, 0x28}, {0x80, 0x36}, + {0x81, 0x44}, {0x82, 0x52}, + {0x83, 0x60}, {0x84, 0x6C}, {0x85, 0x78}, + {0x86, 0x8C}, {0x87, 0x9E}, + {0x88, 0xBB}, {0x89, 0xD2}, {0x8A, 0xE6}, + {0x13, 0xAF}, + } + }, + + /* Omnivision OV9640 Camera 352x288 Mode (CIF) in YCbCr Camera pass Thru Mode */ + { 352, 288, "omnivision", "YCbCr_CIF_raw", CMOS_CCIR656, + YCbCr_CIF_RAW, CIM_CONFIG_RAW, CIM_CONFIG_BGGR, + 1, 0x30, 94, + { + {0x12, 0x80}, {0x11, 0x81}, {0x12, 0x20}, + {0x13, 0xA8}, {0x01, 0x80}, + {0x02, 0x80}, {0x04, 0x40}, {0x0C, 0x04}, + {0x0D, 0xC0}, {0x0E, 0x81}, + {0x0f, 0x4F}, {0x14, 0x4A}, {0x16, 0x02}, + {0x1B, 0x01}, {0x24, 0x70}, + {0x25, 0x68}, {0x26, 0xD3}, {0x27, 0x90}, + {0x2A, 0x00}, {0x2B, 0x00}, + {0x33, 0x02}, {0x37, 0x02}, {0x38, 0x13}, + {0x39, 0xF0}, {0x3A, 0x00}, + {0x3B, 0x01}, {0x3C, 0x46}, {0x3D, 0x90}, + {0x3E, 0x02}, {0x3F, 0xF2}, + {0x41, 0x02}, {0x42, 0xC9}, {0x43, 0xF0}, + {0x44, 0x10}, {0x45, 0x6C}, + {0x46, 0x6C}, {0x47, 0x44}, {0x48, 0x44}, + {0x49, 0x03}, {0x4F, 0x50}, + {0x50, 0x43}, {0x51, 0x0D}, {0x52, 0x19}, + {0x53, 0x4C}, {0x54, 0x65}, + {0x59, 0x49}, {0x5A, 0x94}, {0x5B, 0x46}, + {0x5C, 0x84}, {0x5D, 0x5C}, + {0x5E, 0x08}, {0x5F, 0x00}, {0x60, 0x14}, + {0x61, 0xCE}, {0x62, 0x70}, + {0x63, 0x00}, {0x64, 0x04}, {0x65, 0x00}, + {0x66, 0x00}, {0x69, 0x00}, + {0x6A, 0x3E}, {0x6B, 0x3F}, {0x6C, 0x40}, + {0x6D, 0x30}, {0x6E, 0x4B}, + {0x6F, 0x60}, {0x70, 0x70}, {0x71, 0x70}, + {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, {0x75, 0x60}, {0x76, 0x50}, + {0x77, 0x48}, {0x78, 0x3A}, + {0x79, 0x2E}, {0x7A, 0x28}, {0x7B, 0x22}, + {0x7C, 0x04}, {0x7D, 0x07}, + {0x7E, 0x10}, {0x7F, 0x28}, {0x80, 0x36}, + {0x81, 0x44}, {0x82, 0x52}, + {0x83, 0x60}, {0x84, 0x6C}, {0x85, 0x78}, + {0x86, 0x8C}, {0x87, 0x9E}, + {0x88, 0xBB}, {0x89, 0xD2}, {0x8A, 0xE6}, + {0x13, 0xAF}, + } + }, + + /* Omnivision OV9640 Camera 320x240 Mode QVGA in YCbCr Camera pass Thru Mode */ + { 320, 240, "omnivision", "YCbCr_QVGA_raw", CMOS_CCIR656, + YCbCr_QVGA_RAW, CIM_CONFIG_RAW, CIM_CONFIG_BGGR, + 1, 0x30, 94, + { + {0x12, 0x80}, {0x11, 0x81}, {0x12, 0x10}, + {0x13, 0xA8}, {0x01, 0x80}, + {0x02, 0x80}, {0x04, 0x40}, {0x0C, 0x04}, + {0x0D, 0xC0}, {0x0E, 0x81}, + {0x0f, 0x4F}, {0x14, 0x4A}, {0x16, 0x02}, + {0x1B, 0x01}, {0x24, 0x70}, + {0x25, 0x68}, {0x26, 0xD3}, {0x27, 0x90}, + {0x2A, 0x00}, {0x2B, 0x00}, + {0x33, 0x02}, {0x37, 0x02}, {0x38, 0x13}, + {0x39, 0xF0}, {0x3A, 0x00}, + {0x3B, 0x01}, {0x3C, 0x46}, {0x3D, 0x90}, + {0x3E, 0x02}, {0x3F, 0xF2}, + {0x41, 0x02}, {0x42, 0xC9}, {0x43, 0xF0}, + {0x44, 0x10}, {0x45, 0x6C}, + {0x46, 0x6C}, {0x47, 0x44}, {0x48, 0x44}, + {0x49, 0x03}, {0x4F, 0x50}, + {0x50, 0x43}, {0x51, 0x0D}, {0x52, 0x19}, + {0x53, 0x4C}, {0x54, 0x65}, + {0x59, 0x49}, {0x5A, 0x94}, {0x5B, 0x46}, + {0x5C, 0x84}, {0x5D, 0x5C}, + {0x5E, 0x08}, {0x5F, 0x00}, {0x60, 0x14}, + {0x61, 0xCE}, {0x62, 0x70}, + {0x63, 0x00}, {0x64, 0x04}, {0x65, 0x00}, + {0x66, 0x00}, {0x69, 0x00}, + {0x6A, 0x3E}, {0x6B, 0x3F}, {0x6C, 0x40}, + {0x6D, 0x30}, {0x6E, 0x4B}, + {0x6F, 0x60}, {0x70, 0x70}, {0x71, 0x70}, + {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, {0x75, 0x60}, {0x76, 0x50}, + {0x77, 0x48}, {0x78, 0x3A}, + {0x79, 0x2E}, {0x7A, 0x28}, {0x7B, 0x22}, + {0x7C, 0x04}, {0x7D, 0x07}, + {0x7E, 0x10}, {0x7F, 0x28}, {0x80, 0x36}, + {0x81, 0x44}, {0x82, 0x52}, + {0x83, 0x60}, {0x84, 0x6C}, {0x85, 0x78}, + {0x86, 0x8C}, {0x87, 0x9E}, + {0x88, 0xBB}, {0x89, 0xD2}, {0x8A, 0xE6}, + {0x13, 0xAF}, + } + }, + + /* Omnivision OV9640 Camera 176x144 Mode (QCIF) in YCbCr Camera pass Thru Mode */ + { 176, 144, "omnivision", "YCbCr_QCIF_raw", CMOS_CCIR656, + YCbCr_QCIF_RAW, CIM_CONFIG_RAW, CIM_CONFIG_BGGR, + 1, 0x30, 94, + { + {0x12, 0x80}, {0x11, 0x81}, {0x12, 0x08}, + {0x13, 0xA8}, {0x01, 0x80}, + {0x02, 0x80}, {0x04, 0x40}, {0x0C, 0x04}, + {0x0D, 0xC0}, {0x0E, 0x81}, + {0x0f, 0x4F}, {0x14, 0x4A}, {0x16, 0x02}, + {0x1B, 0x01}, {0x24, 0x70}, + {0x25, 0x68}, {0x26, 0xD3}, {0x27, 0x90}, + {0x2A, 0x00}, {0x2B, 0x00}, + {0x33, 0x02}, {0x37, 0x02}, {0x38, 0x13}, + {0x39, 0xF0}, {0x3A, 0x00}, + {0x3B, 0x01}, {0x3C, 0x46}, {0x3D, 0x90}, + {0x3E, 0x02}, {0x3F, 0xF2}, + {0x41, 0x02}, {0x42, 0xC9}, {0x43, 0xF0}, + {0x44, 0x10}, {0x45, 0x6C}, + {0x46, 0x6C}, {0x47, 0x44}, {0x48, 0x44}, + {0x49, 0x03}, {0x4F, 0x50}, + {0x50, 0x43}, {0x51, 0x0D}, {0x52, 0x19}, + {0x53, 0x4C}, {0x54, 0x65}, + {0x59, 0x49}, {0x5A, 0x94}, {0x5B, 0x46}, + {0x5C, 0x84}, {0x5D, 0x5C}, + {0x5E, 0x08}, {0x5F, 0x00}, {0x60, 0x14}, + {0x61, 0xCE}, {0x62, 0x70}, + {0x63, 0x00}, {0x64, 0x04}, {0x65, 0x00}, + {0x66, 0x00}, {0x69, 0x00}, + {0x6A, 0x3E}, {0x6B, 0x3F}, {0x6C, 0x40}, + {0x6D, 0x30}, {0x6E, 0x4B}, + {0x6F, 0x60}, {0x70, 0x70}, {0x71, 0x70}, + {0x72, 0x70}, {0x73, 0x70}, + {0x74, 0x60}, {0x75, 0x60}, {0x76, 0x50}, + {0x77, 0x48}, {0x78, 0x3A}, + {0x79, 0x2E}, {0x7A, 0x28}, {0x7B, 0x22}, + {0x7C, 0x04}, {0x7D, 0x07}, + {0x7E, 0x10}, {0x7F, 0x28}, {0x80, 0x36}, + {0x81, 0x44}, {0x82, 0x52}, + {0x83, 0x60}, {0x84, 0x6C}, {0x85, 0x78}, + {0x86, 0x8C}, {0x87, 0x9E}, + {0x88, 0xBB}, {0x89, 0xD2}, {0x8A, 0xE6}, + {0x13, 0xAF}, + } + } +}; + +#define CAMERA_COUNT (sizeof(au1xxx_cameras) / sizeof(au1xxx_cameras[0])) + +#endif diff --git a/drivers/char/au1xxx_cim.c b/drivers/char/au1xxx_cim.c new file mode 100644 index 0000000..0890986 --- /dev/null +++ b/drivers/char/au1xxx_cim.c @@ -0,0 +1,647 @@ +/* + * Alchemy Camera Interface (CIM) driver + * + * Copyright 2004 Advanced Micro Devices, Inc + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MIPS_PB1200 +#include +#endif + +#ifdef CONFIG_MIPS_DB1200 +#include +#endif + +/* + Camera Interface Driver will always work in DBDMA Mode. + PIO Mode will result in OverFlow Error +*/ + +/* + * Global Variables + */ + +#define CIM_NAME "au1xxx_cim" +#define CIM_MAJOR 238 +#define VERSION "1.2" + +/* Number of DMA channel used by CIM interface */ +#define MAX_DBDMA_CHANNEL 3 + +/*Max Command Send over SMbus to configure external camera */ +#define MAX_DEVICE_CMD 115 + +/* Number of descriptor used */ +#define NUM_DBDMA_DESCRIPTORS 1 +#define MAX_FRAME_SIZE (1280*960) + +#undef DEBUG + +#ifdef DEBUG +#define DPRINTK(fmt,args...) \ +printk(KERN_DEBUG "%s: " fmt,__FUNCTION__, ## args) +#else +#define DPRINTK(fmt, args...) +#endif + +static uint32_t nInterruptDoneNumber; +static uint32_t ciminterruptcheck; +static uint32_t prev_mode; +static uint32_t DBDMA_SourceID[] = + { DSCR_CMD0_CIM_RXA, DSCR_CMD0_CIM_RXB, DSCR_CMD0_CIM_RXC }; +static void *mem_buf; + +extern int pb1550_wm_codec_write(u8, u8, u8); + +static volatile AU1200_CIM *au1200_cim = (AU1200_CIM *) CIM_BASE_ADDRESS; + +/* Get the array of camera modes */ +#include "au1xxx_cameras.h" + +typedef struct cim_camera_runtime { + chan_tab_t **ChannelArray[MAX_DBDMA_CHANNEL]; + void *memory[MAX_DBDMA_CHANNEL] ; + uint32_t nTransferSize[MAX_DBDMA_CHANNEL]; + CAMERA *cmos_camera; +} CAMERA_RUNTIME; + +static CAMERA_RUNTIME cam_base; +static CAMERA *OrigCimArryPtr = au1xxx_cameras; + +static int +find_mode_index(uint32_t res_format) +{ + int i; + CAMERA_RUNTIME *findex; + + findex = &cam_base; + findex->cmos_camera = OrigCimArryPtr; + + for (i = 0; i < CAMERA_COUNT; i++) { + if (res_format == (findex->cmos_camera->camera_resformat)) { + + return i; + } + (findex->cmos_camera)++; + } + printk(KERN_ERR " Au1xxx_CIM: ERROR: Camera Index Failed \n"); + return -1; +} + +static void +Cim_DDMA_Done_Interrupt(int irq, void *param, struct pt_regs *regs) +{ + nInterruptDoneNumber++; +} + +static int +Capture_Image(void) +{ + au1200_cim->capture = 0; + au1200_cim->capture = CIM_CAPTURE_CLR; + au1200_cim->capture = CIM_CAPTURE_SCE; + return 1; +} + +static void +Camera_pwr_down(void) +{ + /* Power shut to Camera */ + bcsr->board |= BCSR_BOARD_CAMPWR; +} + +static void +Camera_pwr_up(void) +{ + bcsr->board &= ~BCSR_BOARD_CAMPWR; +} + +static void +CIM_Cleanup(CAMERA_RUNTIME * cim_cleanup) +{ + CAMERA *cim_ptr; + uint32_t frame_size; + int i; + cim_ptr = cim_cleanup->cmos_camera; + frame_size = (cim_ptr->frame_width) * (cim_ptr->frame_height); + + for (i = 0; i < cim_ptr->dbdma_channel; i++) { + if (cim_cleanup->ChannelArray[i]) { + + au1xxx_dbdma_stop((u32) (cim_cleanup->ChannelArray[i])); + au1xxx_dbdma_reset((u32) + (cim_cleanup->ChannelArray[i])); + au1xxx_dbdma_chan_free((u32) + (cim_cleanup->ChannelArray[i])); + } + + if ((cim_cleanup->memory[i]) != NULL) { + free_pages((unsigned long)cim_cleanup->memory[i], + get_order(frame_size)); + } + } + +} + +static int +Camera_Config(CAMERA_RUNTIME * cim_config) +{ + uint32_t nAckCount = 0; + int i, ErrorCheck; + ErrorCheck = 0; + uint32_t nCameraModeConfig = 0; + uint32_t nClearSetInterrupt = 0; + CAMERA *cim_config_ptr; + + cim_config_ptr = cim_config->cmos_camera; + + /* To get rid of hard coded number from Transfer Size */ + /* Now transfer size will be calulated on the on the fly */ + /******************************************************************* + In YCbCr 4:2:2 data size is twice the frame size + Y=Frame Size + Cb=Frame Size/2 + Cr=Frame Size/2 + Total size of Frame: Y+Cb+Cr effectively 2*FrameSize + *********************************************************************/ + + if ((cim_config_ptr->au1200_dpsmode) == CIM_CONFIG_RAW) { + if (cim_config_ptr->cmos_output_format == CMOS_CCIR656) { + + cim_config->nTransferSize[0] = + 2 * (cim_config_ptr->frame_width) * + (cim_config_ptr->frame_height); + DPRINTK("FIFO-A YCbCR Transfer Size in Raw mode %d \n", + cim_config->nTransferSize[0]); + } else { + cim_config->nTransferSize[0] = + (cim_config_ptr->frame_width) * + (cim_config_ptr->frame_height); + DPRINTK("FIFO-A Transfer Size in Raw mode %d \n", + cim_config->nTransferSize[0]); + } + cim_config->memory[0] = mem_buf; + } else if ((cim_config_ptr->au1200_dpsmode) == CIM_CONFIG_BAYER) { + /* FIFO A Hold Red Pixels which is Total Pixels/4 */ + cim_config->nTransferSize[0] = + ((cim_config_ptr->frame_width) * + (cim_config_ptr->frame_height)) / 4; + cim_config->nTransferSize[1] = + ((cim_config_ptr->frame_width) * + (cim_config_ptr->frame_height)) / 2; + cim_config->nTransferSize[2] = + ((cim_config_ptr->frame_width) * + (cim_config_ptr->frame_height)) / 4; + + cim_config->memory[0] = mem_buf; + cim_config->memory[1] = mem_buf + cim_config->nTransferSize[0]; + cim_config->memory[2] = mem_buf + cim_config->nTransferSize[0] + + cim_config->nTransferSize[1]; + } else { + cim_config->nTransferSize[0] = + ((cim_config_ptr->frame_width) * + (cim_config_ptr->frame_height)); + cim_config->nTransferSize[1] = + ((cim_config_ptr->frame_width) * + (cim_config_ptr->frame_height)) / 2; + cim_config->nTransferSize[2] = + ((cim_config_ptr->frame_width) * + (cim_config_ptr->frame_height)) / 2; + + cim_config->memory[0] = mem_buf; + cim_config->memory[1] = mem_buf + cim_config->nTransferSize[0]; + cim_config->memory[2] = mem_buf + cim_config->nTransferSize[0] + + cim_config->nTransferSize[1]; + + } + + for (i = 0; i < cim_config->cmos_camera->dbdma_channel; i++) { + /* Allocate Channel */ + cim_config->ChannelArray[i] = + (chan_tab_t **) au1xxx_dbdma_chan_alloc(DBDMA_SourceID[i], + DSCR_CMD0_ALWAYS, + Cim_DDMA_Done_Interrupt, + (void *)NULL); + + if (cim_config->ChannelArray[i] != NULL) { + au1xxx_dbdma_set_devwidth((u32) + (cim_config->ChannelArray[i]), + 32); + if (au1xxx_dbdma_ring_alloc + ((u32) (cim_config->ChannelArray[i]), 16) == 0) { + printk(KERN_ERR \ + "Failed to allocate a DDMA channel\n"); + + ErrorCheck++; + goto error_ch_alloc; + } + au1xxx_dbdma_start((u32) (cim_config->ChannelArray[i])); + int j = 0; + for (j = 0; j < NUM_DBDMA_DESCRIPTORS; j++) { + + if (!au1xxx_dbdma_put_dest + ((u32) (cim_config->ChannelArray[i]), + cim_config->memory[i], + cim_config->nTransferSize[i])) { + printk(KERN_ERR \ + "Error while putting descriptor on DBDMA channnel.\n"); + } + } + + } else { + ErrorCheck++; + goto error_ch_alloc; + } + + } + + for (i = 0; i < cim_config_ptr->cmd_size; i++) { + while ((pb1550_wm_codec_write(cim_config_ptr->device_addr, + cim_config_ptr->config_cmd[i][0], + cim_config_ptr-> + config_cmd[i][1]) != 1) + && (nAckCount < 50)) { + nAckCount++; + } + if (i == 0) { + mdelay(1); + } + + } + if (nAckCount == 50) { + printk(KERN_ERR "External CMOS Camera Not Present or not properly connected !!!! !\n"); + goto error_ch_alloc; + } + + au1200_cim->enable = CIM_ENABLE_EN; + au1200_cim->capture = CIM_CAPTURE_CLR; + + if (cim_config_ptr->au1200_dpsmode == 1) { + nCameraModeConfig = + CIM_CONFIG_DPS_N(cim_config_ptr-> + au1200_dpsmode) | CIM_CONFIG_FS | + CIM_CONFIG_BAY_N(cim_config_ptr-> + au1200_baymode) | CIM_CONFIG_BYT | + CIM_CONFIG_LEN(CIM_CONFIG_LEN_10BIT); + } else if (cim_config_ptr->au1200_dpsmode == 0) { + nCameraModeConfig = + CIM_CONFIG_DPS_N(cim_config_ptr-> + au1200_dpsmode) | CIM_CONFIG_FS | + CIM_CONFIG_BYT | CIM_CONFIG_LEN(CIM_CONFIG_LEN_10BIT) | + CIM_CONFIG_BAY_N(cim_config_ptr-> + au1200_baymode) | CIM_CONFIG_PM; + } else { + /* Need to re check........ */ + nCameraModeConfig = + CIM_CONFIG_DPS_N(cim_config_ptr-> + au1200_dpsmode) | CIM_CONFIG_FS | + CIM_CONFIG_BYT | CIM_CONFIG_LEN(CIM_CONFIG_LEN_10BIT) | + CIM_CONFIG_FSEL_N(CIM_CONFIG_FIELD12); + } + + au1200_cim->config = nCameraModeConfig; + nClearSetInterrupt = CIM_INSTAT_CD | CIM_INSTAT_FD | + CIM_INSTAT_UFA | CIM_INSTAT_OFA | + CIM_INSTAT_UFB | CIM_INSTAT_OFB | CIM_INSTAT_UFB | CIM_INSTAT_OFC; + + au1200_cim->instat = nClearSetInterrupt; + au1200_cim->inten = nClearSetInterrupt; + + for (i = 0; i < 6; i++) { + mdelay(1); + } + + error_ch_alloc: + if (ErrorCheck) { + CIM_Cleanup(cim_config); + return -1; + } + return 0; +} + +#define MAX_GFP 0x00200000 + +/* To get contigious Memroy location using GetFree pages*/ + +static unsigned long +Camera_mem_alloc(unsigned long size) +{ + /* __get_free_pages() fulfills a max request of 2MB */ + /* do multiple requests to obtain large contigous mem */ + + unsigned long mem, amem, alloced = 0, allocsize; + + size += 0x1000; + allocsize = (size < MAX_GFP) ? size : MAX_GFP; + + /* Get first chunk */ + mem = (unsigned long) + __get_free_pages(GFP_ATOMIC | GFP_DMA, get_order(allocsize)); + if (mem != 0) + alloced = allocsize; + + /* Get remaining, contiguous chunks */ + while (alloced < size) { + amem = (unsigned long) + __get_free_pages(GFP_ATOMIC | GFP_DMA, + get_order(allocsize)); + if (amem != 0) + alloced += allocsize; + + /* check for contiguous mem alloced */ + if ((amem == 0) || (amem + allocsize) != mem) + break; + else + mem = amem; + } + return mem; +} + +static irqreturn_t +Cim_Interrupt_Handler(int irq, void *dev_id,struct pt_regs *regs) +{ + + uint32_t nStatus; + + disable_irq(AU1200_CAMERA_INT); + nStatus = au1200_cim->instat; + + if (nStatus & CIM_INSTAT_CD) { + au1200_cim->instat = CIM_INSTAT_CD; + } else if (nStatus & CIM_INSTAT_FD) { + au1200_cim->instat = CIM_INSTAT_FD; + } else if (nStatus & CIM_INSTAT_UFA) { + au1200_cim->instat = CIM_INSTAT_UFA; + ciminterruptcheck = 1; + } else if (nStatus & CIM_INSTAT_OFA) { + au1200_cim->instat = CIM_INSTAT_OFA; + ciminterruptcheck = 1; + } else if (nStatus & CIM_INSTAT_UFB) { + au1200_cim->instat = CIM_INSTAT_UFB; + ciminterruptcheck = 1; + } else if (nStatus & CIM_INSTAT_OFB) { + au1200_cim->instat = CIM_INSTAT_OFB; + ciminterruptcheck = 1; + } else if (nStatus & CIM_INSTAT_UFC) { + au1200_cim->instat = CIM_INSTAT_UFC; + ciminterruptcheck = 1; + } else if (nStatus & CIM_INSTAT_OFC) { + au1200_cim->instat = CIM_INSTAT_OFC; + ciminterruptcheck = 1; + } else if (nStatus & CIM_INSTAT_ERR) { + au1200_cim->instat = CIM_INSTAT_ERR; + } + + enable_irq(AU1200_CAMERA_INT); + return IRQ_HANDLED; +} + +static int +au1xxxcim_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + nInterruptDoneNumber = 0; + uint32_t mode_index, i; + CAMERA_RUNTIME *capture; + CAMERA *capture_ptr; + + capture = &cam_base; + + switch (cmd) { + + case AU1XXXCIM_QUERY:{ + /*returing previous mode */ + DPRINTK + ("QUERY Mode- Return Camera Index to Application is %d \n", + prev_mode); + return prev_mode; + } + case AU1XXXCIM_CONFIGURE:{ + DPRINTK(" CONFIGURE Mode\n"); + mode_index = find_mode_index(arg); + capture->cmos_camera = OrigCimArryPtr + prev_mode; + capture_ptr = capture->cmos_camera; + DPRINTK + ("CONFIGURE Mode: Calling CleanUP as Camera needs to be re-configured \n"); + CIM_Cleanup(capture); + DPRINTK("CONFIGURE:Camera Array Index value is %d \n", + mode_index); + capture->cmos_camera = OrigCimArryPtr + mode_index; + capture_ptr = capture->cmos_camera; + DPRINTK + (" CONFIGURE: Camera configured in ** %s ** Mode \n", + capture_ptr->camera_mode); + au1200_cim->enable &= ~CIM_ENABLE_EN; + Camera_Config(capture); + Camera_pwr_down(); + mdelay(1); + Camera_pwr_up(); + mdelay(6); + prev_mode = mode_index; + return mode_index; + } + case AU1XXXCIM_CAPTURE:{ + capture->cmos_camera = OrigCimArryPtr + prev_mode; + capture_ptr = capture->cmos_camera; + DPRINTK("CAPTURE: Camera Array Index # %d \n", + prev_mode); + DPRINTK("CAPTURE:Picture taken in **%s** Mode \n", + capture_ptr->camera_mode); + Capture_Image(); + DPRINTK("CAPTURE:Status Reg %x Capture Reg %x \n", + au1200_cim->stat, au1200_cim->capture); + DPRINTK("Waiting for %d DMA Interrupt \n", + capture_ptr->dbdma_channel); + while ((nInterruptDoneNumber != + (capture_ptr->dbdma_channel)) + && (!ciminterruptcheck)) ; + + if (ciminterruptcheck) { + printk(" !! ERROR: DMA Transfer Error \n"); + ciminterruptcheck = 0; + return 0; + } + + DPRINTK + ("CAPTURE:Putting back descriptor back to ring\n"); + for (i = 0; i < capture_ptr->dbdma_channel; i++) { + if (!au1xxx_dbdma_put_dest + ((u32) (capture->ChannelArray[i]), + capture->memory[i], + capture->nTransferSize[i])) { + printk + ("DBDMA Error..Putting Descriptor on Buffer Ring Channel A in Single Channel \n"); + } + } + DPRINTK(" CAPTURE: Exiting Capture \n"); + + return 1; + break; + } + + } + + return -EINVAL; +} + +static int +au1xxxcim_mmap(struct file *file, struct vm_area_struct *vma) +{ + unsigned int len; + unsigned long start = 0, off; + + if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) { + printk(" Error vma->vm_pgoff > !OUL PAGE_SHIFT \n"); + return -EINVAL; + } + + start = virt_to_phys(mem_buf) & PAGE_MASK; + len = PAGE_ALIGN((start & ~PAGE_MASK) + 2 * MAX_FRAME_SIZE); + off = vma->vm_pgoff << PAGE_SHIFT; + + if ((vma->vm_end - vma->vm_start + off) > len) { + printk(" Error vma->vm_end-vma->vm_start\n"); + return -EINVAL; + } + + off += start; + vma->vm_pgoff = off >> PAGE_SHIFT; + pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK; + pgprot_val(vma->vm_page_prot) |= PAGE_CACHABLE_DEFAULT; + + /* This is an IO map - tell maydump to skip this VMA */ + vma->vm_flags |= VM_IO; + + return io_remap_pfn_range(vma, vma->vm_start, off, + vma->vm_end - vma->vm_start, + vma->vm_page_prot); +} + +static struct file_operations au1xxxcim_fops = { + owner:THIS_MODULE, + ioctl:au1xxxcim_ioctl, + mmap:au1xxxcim_mmap +}; + +int __init +au1xxxcim_init(void) +{ + int retval, error; + unsigned long page; + CAMERA_RUNTIME *cam_init; + CAMERA *cim_ptr; + + cam_init = &cam_base; + cam_init->cmos_camera = OrigCimArryPtr + prev_mode; + cim_ptr = cam_init->cmos_camera; + + /*Allocating memory for MMAP */ + mem_buf = (unsigned long *)Camera_mem_alloc(2 * MAX_FRAME_SIZE); + if (mem_buf == NULL) { + printk(KERN_ERR "MMAP unable to allocate memory \n"); + } + + for (page = (unsigned long)mem_buf; + page < PAGE_ALIGN((unsigned long)mem_buf + MAX_FRAME_SIZE); + page += PAGE_SIZE) { + SetPageReserved(virt_to_page(page)); + } + Camera_pwr_up(); + error = Camera_Config(cam_init); + if (error == -1) { + DPRINTK + ("Camera Config Un-Sucessful: Calling Clean Up function \n"); + CIM_Cleanup(cam_init); + } + + Camera_pwr_down(); + mdelay(1); + Camera_pwr_up(); + + /* Register Device */ + retval = register_chrdev(CIM_MAJOR, CIM_NAME, &au1xxxcim_fops); + if (retval < 0) { + printk(KERN_ERR "Could not register CIM device\n"); + return 0; + } + printk(KERN_INFO "Au1XXX CIM driver registered Sucessfully v%s\n", + VERSION); + if ((retval = + request_irq(AU1200_CAMERA_INT, Cim_Interrupt_Handler, + SA_SHIRQ | SA_INTERRUPT, CIM_NAME, + (void *)au1200_cim))) { + printk(KERN_ERR "CIM: Could not get IRQ %d.\n", + AU1200_CAMERA_INT); + CIM_Cleanup(cam_init); + return retval; + } + + return 0; + +} + +void __exit +au1xxxcim_exit(void) +{ + int retval; + CAMERA_RUNTIME *cam_exit; + CAMERA *cam_exit_ptr; + + cam_exit = &cam_base; + cam_exit->cmos_camera = OrigCimArryPtr + prev_mode; + cam_exit_ptr = cam_exit->cmos_camera; + + /* Cleanup funtion will clean allocated memory, free DMA channels */ + CIM_Cleanup(cam_exit); + + /*Unregister Device */ + retval = unregister_chrdev(CIM_MAJOR, CIM_NAME); + if (retval != -EINVAL) { + printk(KERN_INFO "CIM driver unregistered Sucessfully \n"); + } +} + +module_init(au1xxxcim_init); +module_exit(au1xxxcim_exit); + +MODULE_AUTHOR("AMD"); +MODULE_DESCRIPTION("AMD CIM Interface Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/asm-mips/mach-au1x00/au1xxx_cim.h b/include/asm-mips/mach-au1x00/au1xxx_cim.h new file mode 100644 index 0000000..50fe557 --- /dev/null +++ b/include/asm-mips/mach-au1x00/au1xxx_cim.h @@ -0,0 +1,190 @@ + /* Defines for using the Camera Interfaces on the + * Alchemy Au1100 mips processor. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef AUXXX_CIM_H +#define AUXXX_CIM_H + +#include + +#define AU1XXXCIM_IOC_MAGIC 'C' + +#define RAW_SXGA _IOW(AU1XXXCIM_IOC_MAGIC,1, int *) +#define RAW_VGA _IOW(AU1XXXCIM_IOC_MAGIC,2, int *) +#define RAW_CIF _IOW(AU1XXXCIM_IOC_MAGIC,3, int *) +#define RAW_QVGA _IOW(AU1XXXCIM_IOC_MAGIC,4, int *) +#define RAW_QCIF _IOW(AU1XXXCIM_IOC_MAGIC,5, int *) +#define RAW_QQVGA _IOW(AU1XXXCIM_IOC_MAGIC,6, int *) +#define RAW_QQCIF _IOW(AU1XXXCIM_IOC_MAGIC,7, int *) +#define BAYER_SXGA _IOW(AU1XXXCIM_IOC_MAGIC,8, int *) +#define BAYER_VGA _IOW(AU1XXXCIM_IOC_MAGIC,9, int *) +#define BAYER_CIF _IOW(AU1XXXCIM_IOC_MAGIC,10, int *) +#define BAYER_QVGA _IOW(AU1XXXCIM_IOC_MAGIC,11, int *) +#define BAYER_QCIF _IOW(AU1XXXCIM_IOC_MAGIC,12, int *) +#define BAYER_QQVG _IOW(AU1XXXCIM_IOC_MAGIC,13, int *) +#define BAYER_QQCI _IOW(AU1XXXCIM_IOC_MAGIC,14, int *) +#define YCbCr_SXGA_RAW _IOW(AU1XXXCIM_IOC_MAGIC,18, int *) +#define YCbCr_VGA_RAW _IOW(AU1XXXCIM_IOC_MAGIC,19, int *) +#define YCbCr_CIF_RAW _IOW(AU1XXXCIM_IOC_MAGIC,20, int *) +#define YCbCr_QVGA_RAW _IOW(AU1XXXCIM_IOC_MAGIC,21, int *) +#define YCbCr_QCIF_RAW _IOW(AU1XXXCIM_IOC_MAGIC,22, int *) +#define YCbCr_SXGA _IOW(AU1XXXCIM_IOC_MAGIC,23, int *) +#define YCbCr_VGA _IOW(AU1XXXCIM_IOC_MAGIC,24, int *) +#define YCbCr_CIF _IOW(AU1XXXCIM_IOC_MAGIC,25, int *) +#define YCbCr_QVGA _IOW(AU1XXXCIM_IOC_MAGIC,26, int *) +#define YCbCr_QCIF _IOW(AU1XXXCIM_IOC_MAGIC,27, int *) +#define AU1XXXCIM_CAPTURE _IOW(AU1XXXCIM_IOC_MAGIC, 100, int *) +#define AU1XXXCIM_QUERY _IOW(AU1XXXCIM_IOC_MAGIC, 50, int *) +#define AU1XXXCIM_CONFIGURE _IOW(AU1XXXCIM_IOC_MAGIC, 75, int *) + +#define CMOS_RAW 0 +#define CMOS_CCIR656 1 + +#define CIM_BASE_ADDRESS 0xB4004000 + +#define CIM_FIFOA 0xB4004020 +#define CIM_FIFOB 0xB4004040 +#define CIM_FIFOC 0xB4004060 + +typedef struct +{ + unsigned long enable; /* 00 */ + unsigned long config; /* 04 */ + unsigned long reserve0; /* 08 */ + unsigned long reserve1; /* 0C */ + unsigned long capture; /* 10 */ + unsigned long stat; /* 14 */ + unsigned long inten; /* 18 */ + unsigned long instat; /* 1C */ + unsigned long fifoa; /* 20 */ + unsigned long reserve2; /* 24 */ + unsigned long reserve3; /* 28 */ + unsigned long reserve4; /* 2C */ + unsigned long reserve5; /* 30 */ + unsigned long reserve6; /* 34 */ + unsigned long reserve7; /* 38 */ + unsigned long reserve8; /* 3C */ + unsigned long fifob; /* 40 */ + unsigned long reserve9; /* 44 */ + unsigned long reserve10; /* 48 */ + unsigned long reserve11; /* 4C */ + unsigned long reserve12; /* 50 */ + unsigned long reserve13; /* 54 */ + unsigned long reserve14; /* 58 */ + unsigned long reserve15; /* 5C */ + unsigned long fifoc; /* 60 */ +}AU1200_CIM; + + +#define CIM_ENABLE 0x00000000 +#define CIM_CONFIG 0x00000004 +#define CIM_CAPTURE 0x00000010 +#define CIM_STAT 0x00000014 +#define CIM_INTEN 0x00000018 +#define CIM_INSTAT 0x0000001C + +#define CIM_ENABLE_EN (1<<0) /* enable/disable/reset the block*/ + +/* CIM Configuration Register */ + +#define CIM_CONFIG_PM (1<<0) +#define CIM_CONFIG_CLK (1<<1) /* Rising Edge of the Clock */ +#define CIM_CONFIG_LS (1<<2) /* Line Sync Active Low */ +#define CIM_CONFIG_FS (1<<3) /* Frame Sync is Active Low */ + +#define CIM_CONFIG_RAW 0 /* RAW MODE */ +#define CIM_CONFIG_BAYER 1 /*Bayer Mode*/ +#define CIM_CONFIG_656 2 /* 656 YCbCr Mode*/ + +#define CIM_CONFIG_DPS_N(n) (((n) & 0x03)<<6) + + +#define CIM_CONFIG_RGGB 0 +#define CIM_CONFIG_GRBG 1 +#define CIM_CONFIG_BGGR 2 +#define CIM_CONFIG_GBRG 3 + +#define CIM_CONFIG_BAY_N(n) (((n) & 0x03)<<8) + +#define CIM_CONFIG_LEN_8BIT 0 +#define CIM_CONFIG_LEN_9BIT 1 +#define CIM_CONFIG_LEN_10BIT 2 + + +#define CIM_CONFIG_LEN(n) (((n) & 0x0f)<<10) +#define CIM_CONFIG_BYT (1<<14) +#define CIM_CONFIG_SF (1<<15) + +#define CIM_CONFIG_FIELD1 0 /* Capture from Field 1*/ +#define CIM_CONFIG_FIELD2 1 /*Capture from Field 2*/ +#define CIM_CONFIG_FIELD12 2 /*Capture from Either Field*/ + +#define CIM_CONFIG_FSEL_N(n) (((n) & 0x03)<<16) + +#define CIM_CONFIG_SI (1<<18) + +/* CIM Capture Control Register */ + +#define CIM_CAPTURE_VCE (1<<0) +#define CIM_CAPTURE_SCE (1<<1) +#define CIM_CAPTURE_CLR (1<<2) + +/* CIM Status Register */ + +#define CIM_STATUS_VC (1<<0) +#define CIM_STATUS_SC (1<<1) +#define CIM_STATUS_AF (1<<2) +#define CIM_STATUS_AE (1<<3) +#define CIM_STATUS_AR (1<<4) +#define CIM_STATUS_BF (1<<5) +#define CIM_STATUS_BE (1<<6) +#define CIM_STATUS_BR (1<<7) +#define CIM_STATUS_CF (1<<8) +#define CIM_STATUS_CE (1<<9) +#define CIM_STATUS_CR (1<<10) + + +/* Interrupt Rgister */ +#define CIM_INTEN_CD (1<<0) +#define CIM_INTEN_FD (1<<1) +#define CIM_INTEN_UFA (1<<2) +#define CIM_INTEN_OFA (1<<3) +#define CIM_INTEN_UFB (1<<4) +#define CIM_INTEN_OFB (1<<5) +#define CIM_INTEN_UFC (1<<6) +#define CIM_INTEN_OFC (1<<7) +#define CIM_INTEN_ERR (1<<8) + + +/* Interrupt Status Rgister */ + +#define CIM_INSTAT_CD (1<<0) +#define CIM_INSTAT_FD (1<<1) +#define CIM_INSTAT_UFA (1<<2) +#define CIM_INSTAT_OFA (1<<3) +#define CIM_INSTAT_UFB (1<<4) +#define CIM_INSTAT_OFB (1<<5) +#define CIM_INSTAT_UFC (1<<6) +#define CIM_INSTAT_OFC (1<<7) +#define CIM_INSTAT_ERR (1<<8) + +#endif From drzeus@drzeus.cx Fri Dec 2 19:38:33 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 19:38:51 +0000 (GMT) Received: from [85.8.13.51] ([85.8.13.51]:9896 "EHLO smtp.drzeus.cx") by ftp.linux-mips.org with ESMTP id S8133868AbVLBTid (ORCPT ); Fri, 2 Dec 2005 19:38:33 +0000 Received: from [10.100.1.247] ([::ffff:213.115.244.31]) (AUTH: PLAIN drzeus, TLS: TLSv1/SSLv3,256bits,AES256-SHA) by smtp.drzeus.cx with esmtp; Fri, 02 Dec 2005 20:42:07 +0100 id 0006271A.4390A390.00006C1A Message-ID: <4390A38A.1010907@drzeus.cx> Date: Fri, 02 Dec 2005 20:42:02 +0100 From: Pierre Ossman User-Agent: Mail/News 1.5 (X11/20051129) MIME-Version: 1.0 To: Jordan Crouse CC: linux-mips@linux-mips.org, ralf@linux-mips.org, Russell King Subject: Re: [PATCH] ALCHEMY: Add SD support to AU1200 MMC/SD driver References: <20051202190108.GF28227@cosmic.amd.com> In-Reply-To: <20051202190108.GF28227@cosmic.amd.com> X-Enigmail-Version: 0.93.0.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9581 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: drzeus@drzeus.cx Precedence: bulk X-list: linux-mips Jordan Crouse wrote: > Add SD support to the AU1200 MMC driver. This can > be added post 2.6.15, I'm just sending them out today so the various > maintainers can get them queued up. > > Signed-off-by: Jordan Crouse > --- > > drivers/mmc/au1xmmc.c | 124 ++++++++++++++++++++++++++++--------------------- > 1 files changed, 71 insertions(+), 53 deletions(-) > Russell is still the maintainer of the MMC layer. :) I still have some comments though. > @@ -124,8 +132,8 @@ static inline void IRQ_OFF(struct au1xmm > static inline void SEND_STOP(struct au1xmmc_host *host) > { > > - /* We know the value of CONFIG2, so avoid a read we don't need */ > - u32 mask = SD_CONFIG2_EN; > + /* Penalty box for Jordan - NEVER ASSUME! */ > + u32 mask = au_readl(HOST_CONFIG2(host)); > > WARN_ON(host->status != HOST_S_DATA); > host->status = HOST_S_STOP; This comment will be terribly confusing to anyone reading your code. > @@ -196,7 +207,11 @@ static int au1xmmc_send_command(struct a > > switch(cmd->flags) { > case MMC_RSP_R1: > - mmccmd |= SD_CMD_RT_1; > + if (cmd->opcode == 0x03 && host->mmc->mode == MMC_MODE_SD) > + mmccmd |= SD_CMD_RT_6; > + else > + mmccmd |= SD_CMD_RT_1; > + > break; > case MMC_RSP_R1B: > mmccmd |= SD_CMD_RT_1B; No, no, no! Even if this wasn't already fixed in the current kernel you never hack around bugs in other parts of the kernel, you fix them! > @@ -504,8 +519,8 @@ static void au1xmmc_cmd_complete(struct > r[3] = au_readl(host->iobase + SD_RESP0); > > /* The CRC is omitted from the response, so really we only got > - * 120 bytes, but the engine expects 128 bits, so we have to shift > - * things up > + * 120 bytes, but the engine expects 128 bits, so we have to > + * shift things up > */ > > for(i = 0; i < 4; i++) { s/bytes/bits/ > @@ -611,7 +635,7 @@ au1xmmc_prepare_data(struct au1xmmc_host > > int len = (datalen > sg_len) ? sg_len : datalen; > > - if (i == host->dma.len - 1) > + if (i == (host->dma.len - 1)) > flags = DDMA_FLAGS_IE; > > if (host->flags & HOST_F_XMIT){ broken indentation. > @@ -627,23 +651,11 @@ au1xmmc_prepare_data(struct au1xmmc_host > len, flags); > } > > - if (!ret) > + if (ret == 0) > goto dataerr; > > datalen -= len; > } > - } > - else { > - host->pio.index = 0; > - host->pio.offset = 0; > - host->pio.len = datalen; > - > - if (host->flags & HOST_F_XMIT) > - IRQ_ON(host, SD_CONFIG_TH); > - else > - IRQ_ON(host, SD_CONFIG_NE); > - //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF); > - } > > return MMC_ERR_NONE; > Here aswell. And it seems the block above will get the wrong indentation. Rgds Pierre From rmk+linux-mips=linux-mips.org@arm.linux.org.uk Fri Dec 2 19:42:10 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 19:42:29 +0000 (GMT) Received: from caramon.arm.linux.org.uk ([212.18.232.186]:18187 "EHLO caramon.arm.linux.org.uk") by ftp.linux-mips.org with ESMTP id S8133874AbVLBTmK (ORCPT ); Fri, 2 Dec 2005 19:42:10 +0000 Received: from flint.arm.linux.org.uk ([2002:d412:e8ba:1:201:2ff:fe14:8fad]) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:DES-CBC3-SHA:168) (Exim 4.52) id 1EiGqn-0007Up-6j; Fri, 02 Dec 2005 19:45:45 +0000 Received: from rmk by flint.arm.linux.org.uk with local (Exim 4.52) id 1EiGqd-00036l-VQ; Fri, 02 Dec 2005 19:45:36 +0000 Date: Fri, 2 Dec 2005 19:45:35 +0000 From: Russell King To: Pierre Ossman Cc: Jordan Crouse , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] ALCHEMY: Add SD support to AU1200 MMC/SD driver Message-ID: <20051202194534.GB3780@flint.arm.linux.org.uk> References: <20051202190108.GF28227@cosmic.amd.com> <4390A38A.1010907@drzeus.cx> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4390A38A.1010907@drzeus.cx> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9582 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rmk@arm.linux.org.uk Precedence: bulk X-list: linux-mips On Fri, Dec 02, 2005 at 08:42:02PM +0100, Pierre Ossman wrote: > Jordan Crouse wrote: > > Add SD support to the AU1200 MMC driver. This can > > be added post 2.6.15, I'm just sending them out today so the various > > maintainers can get them queued up. > > > > Signed-off-by: Jordan Crouse > > --- > > > > drivers/mmc/au1xmmc.c | 124 ++++++++++++++++++++++++++++--------------------- > > 1 files changed, 71 insertions(+), 53 deletions(-) > > > > Russell is still the maintainer of the MMC layer. :) Indeed. Jordan - please send me a copy of the patch. Thanks. Note that I agree with Pierre's comments. -- Russell King Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/ maintainer of: 2.6 Serial core From jcrouse@cosmic.amd.com Fri Dec 2 21:07:59 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 21:08:21 +0000 (GMT) Received: from amdext3.amd.com ([139.95.251.6]:21658 "EHLO amdext3.amd.com") by ftp.linux-mips.org with ESMTP id S8133539AbVLBVH7 (ORCPT ); Fri, 2 Dec 2005 21:07:59 +0000 Received: from SSVLGW01.amd.com (ssvlgw01.amd.com [139.95.250.169]) by amdext3.amd.com (8.12.11/8.12.11/AMD) with ESMTP id jB2LBCqU017942; Fri, 2 Dec 2005 13:11:13 -0800 Received: from 139.95.250.1 by SSVLGW02.amd.com with ESMTP (AMD SMTP Relay (Email Firewall v6.1.0)); Fri, 02 Dec 2005 13:09:22 -0800 X-Server-Uuid: 519AC16A-9632-469E-B354-112C592D09E8 Received: from ldcmail.amd.com (ldcmail.amd.com [147.5.200.40]) by amdint.amd.com (8.12.8/8.12.8/AMD) with ESMTP id jB2L9LQe028963; Fri, 2 Dec 2005 13:09:21 -0800 (PST) Received: from cosmic.amd.com (cosmic.amd.com [147.5.201.206]) by ldcmail.amd.com (Postfix) with ESMTP id 106FC2026; Fri, 2 Dec 2005 14:09:21 -0700 (MST) Received: from cosmic.amd.com (localhost [127.0.0.1]) by cosmic.amd.com (8.13.4/8.13.4) with ESMTP id jB2LH96p000345; Fri, 2 Dec 2005 14:17:09 -0700 Received: (from jcrouse@localhost) by cosmic.amd.com ( 8.13.4/8.13.4/Submit) id jB2LH9Uo000344; Fri, 2 Dec 2005 14:17:09 -0700 Date: Fri, 2 Dec 2005 14:17:09 -0700 From: "Jordan Crouse" To: "Pierre Ossman" cc: linux-mips@linux-mips.org, ralf@linux-mips.org, "Russell King" Subject: Re: ALCHEMY: Add SD support to AU1200 MMC/SD driver Message-ID: <20051202211709.GL28227@cosmic.amd.com> References: <20051202190108.GF28227@cosmic.amd.com> <4390A38A.1010907@drzeus.cx> MIME-Version: 1.0 In-Reply-To: <4390A38A.1010907@drzeus.cx> User-Agent: Mutt/1.5.11 X-WSS-ID: 6F8E67881IW1481965-01-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9583 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jordan.crouse@amd.com Precedence: bulk X-list: linux-mips On 02/12/05 20:42 +0100, Pierre Ossman wrote: > Jordan Crouse wrote: > > @@ -196,7 +207,11 @@ static int au1xmmc_send_command(struct a > > > > switch(cmd->flags) { > > case MMC_RSP_R1: > > - mmccmd |= SD_CMD_RT_1; > > + if (cmd->opcode == 0x03 && host->mmc->mode == MMC_MODE_SD) > > + mmccmd |= SD_CMD_RT_6; > > + else > > + mmccmd |= SD_CMD_RT_1; > > + > > break; > > case MMC_RSP_R1B: > > mmccmd |= SD_CMD_RT_1B; > > No, no, no! Even if this wasn't already fixed in the current kernel you > never hack around bugs in other parts of the kernel, you fix them! As of a git pull about 30 minutes ago, both MMC_RSP_R1 and MMC_RSP_R6 resolve to (MMC_RSP_SHORT|MMC_RSP_CRC). Now, I really wouldn't call that a bug in the subsystem, because it is technically correct, but the Au1200 needs us to specifically specify if the required response is an R1 or an R6, thus the specified logic. Jordan -- Jordan Crouse Senior Linux Engineer AMD - Personal Connectivity Solutions Group From drzeus@drzeus.cx Fri Dec 2 22:02:08 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Dec 2005 22:02:26 +0000 (GMT) Received: from [85.8.13.51] ([85.8.13.51]:13736 "EHLO smtp.drzeus.cx") by ftp.linux-mips.org with ESMTP id S8133598AbVLBWCI (ORCPT ); Fri, 2 Dec 2005 22:02:08 +0000 Received: from [10.100.1.247] ([::ffff:213.115.244.31]) (AUTH: PLAIN drzeus, TLS: TLSv1/SSLv3,256bits,AES256-SHA) by smtp.drzeus.cx with esmtp; Fri, 02 Dec 2005 23:05:48 +0100 id 00062717.4390C53C.00007287 Message-ID: <4390C53A.70606@drzeus.cx> Date: Fri, 02 Dec 2005 23:05:46 +0100 From: Pierre Ossman User-Agent: Mail/News 1.5 (X11/20051129) MIME-Version: 1.0 To: Jordan Crouse CC: linux-mips@linux-mips.org, ralf@linux-mips.org, Russell King Subject: Re: ALCHEMY: Add SD support to AU1200 MMC/SD driver References: <20051202190108.GF28227@cosmic.amd.com> <4390A38A.1010907@drzeus.cx> <20051202211709.GL28227@cosmic.amd.com> In-Reply-To: <20051202211709.GL28227@cosmic.amd.com> X-Enigmail-Version: 0.93.0.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9584 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: drzeus@drzeus.cx Precedence: bulk X-list: linux-mips Jordan Crouse wrote: > On 02/12/05 20:42 +0100, Pierre Ossman wrote: >> Jordan Crouse wrote: >>> @@ -196,7 +207,11 @@ static int au1xmmc_send_command(struct a >>> >>> switch(cmd->flags) { >>> case MMC_RSP_R1: >>> - mmccmd |= SD_CMD_RT_1; >>> + if (cmd->opcode == 0x03 && host->mmc->mode == MMC_MODE_SD) >>> + mmccmd |= SD_CMD_RT_6; >>> + else >>> + mmccmd |= SD_CMD_RT_1; >>> + >>> break; >>> case MMC_RSP_R1B: >>> mmccmd |= SD_CMD_RT_1B; >> No, no, no! Even if this wasn't already fixed in the current kernel you >> never hack around bugs in other parts of the kernel, you fix them! > > As of a git pull about 30 minutes ago, both MMC_RSP_R1 and MMC_RSP_R6 resolve > to (MMC_RSP_SHORT|MMC_RSP_CRC). Now, I really wouldn't call that a > bug in the subsystem, because it is technically correct, but the Au1200 > needs us to specifically specify if the required response is an R1 or > an R6, thus the specified logic. > Point, but then you should figure out the distinction and why the controller requires it (I assume you have tried giving the controller "incorrect" settings). At that point the MMC layer can be extended to handle this in a general manner instead of hacks in every other driver. Judging from your email address you seem to be at a good position to find out what the problem is. Rgds Pierre From Philippedeswert@scarlet.be Sun Dec 4 23:28:08 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 04 Dec 2005 23:28:36 +0000 (GMT) Received: from p549F6917.dip.t-dialin.net ([84.159.105.23]:27880 "EHLO p549F6917.dip.t-dialin.net") by ftp.linux-mips.org with ESMTP id S8133543AbVLDX2I (ORCPT ); Sun, 4 Dec 2005 23:28:08 +0000 Received: from fep32-0.kolumbus.fi ([IPv6:::ffff:193.229.0.63]:36303 "EHLO fep32-app.kolumbus.fi") by linux-mips.net with ESMTP id ; Sun, 4 Dec 2005 19:25:55 +0100 Received: from [192.168.0.102] (really [81.197.102.144]) by fep32-app.kolumbus.fi with ESMTP id <20051204182210.DYIF18068.fep32-app.kolumbus.fi@[192.168.0.102]> for ; Sun, 4 Dec 2005 20:22:10 +0200 Subject: SOT: Looking for Free Software developers willing to give a talk at the Fosdem embedded devroom From: Philippe De Swert To: linux-mips@linux-mips.org Content-Type: text/plain Date: Sun, 04 Dec 2005 20:21:56 +0200 Message-Id: <1133720516.6478.39.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.0.4 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9585 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Philippedeswert@scarlet.be Precedence: bulk X-list: linux-mips Hello all, I hope you will all forgive me for posting this slightly off-topic request. In february it will be time for another embedded track at Fosdem (www.fosdem.org) and to fill this we are looking for people willing to present their embedded projects or talk about their experiences. Before you all flame me (preferably off-list) know that Fosdem is non-profit and organized for and by the community. See it as a chance to present the work done by the embedded (and MIPS in this case) community. Thanks, Philippe PS: Call for papers with more info for the ones that are interested. CALL FOR PAPERS for the 4th EMBEDDED track at FOSDEM 2005 ========================================================== sat 25 - sun 26 February 2006, Brussels Call for papers ---------------- The 2006 edition of FOSDEM (Free and Open Source Developers' European Meeting; http://www.fosdem.org) will take place in Brussels, Belgium on 25 and 26 February 2006. For the fourth time, a track on Embedded Systems and Operating Systems will be organized. The third edition was quite succesful and attracted up to 150 attendants for certain topics. For last years program see: http://www.embedded-kernel-track.org/2005/papers.html The use of Free Software in the infrastructure of Embedded Systems is booming, e.g. by the use of Linux, uClinux, eCos, RedBoot, RTEMS and many other Free Software components. More companies are supporting Embedded Free Software each day because of the reliability and cheap licensing. This can be confirmed from looking at some high profile releases of embedded GNU/Linux systems. Some examples are the Nokia 770, some models of Motorola's smartphones, Archos players and the move from palmsource to build on a Linux subsystem Operating System development has always been a very important topic in Free Software. As embedded and real-time systems typically have special OS requirements, we organise this Free Embedded and OS development track at FOSDEM to give people the opportunity to present their (or their teams) achievements. This track at FOSDEM provides a remarkable opportunity to present and discuss the ongoing work in these areas, and we invite developers to present their current projects. Technical topics of the conference include but are not limited to : * OS Development : kernel architecture and implementation, libraries (e.g. Linux, BSD, uClinux, uClibc, newlib, ...) * Practical experiences in implementing Free Software in embedded systems (e.g. reverse engineering, porting too (and adapting of) commercial devices like the Ipaq, linksys WRT54G, nlsu2 .... ) * Toolchain, performance testing and build environment (e.g. crosstool, emdebian, openembedded, PTX dist, packaging, scratchbox, Eclipse, Valgrind,...) * GUI's for embedded systems (Gtk, Qt-(embedded), GPE, Qtopia, UI design with touchscreen, ...) * Multimedia applications for embedded systems (e.g. integer only decoders, Opieplayer, gstreamer... ) * Real-time extensions, nanokernels and hardware virtualization software (e.g. RTAI, Adeos, KURT, L4, Qemu, User Mode Linux, ...) * Hard real-time OS's (eCos, RTEMS, ...) * Open hardware, DSP, softcores and general hardware management (e.g opencores.org, OpenRISC, leonSparc, FPGA's, specific design restrictions for free systems, DSP, Power management...) * Safety and security certifications applied to Free software (e.g. security measures in Embedded systems, SSL libraries, ...) * Free software licenses and embedded systems Authors that wish to present a topic are requested to submit their abstracts online to embedded@fosdem.org before 31/12/2005. Notification of receipt will be sent within 48 hours. Authors wishing to submit a full paper (between 6 and 12 A4 pages), can do so in PS or PDF format. The Program Committee will evaluate the abstracts and consists of: * Geert Uytterhoeven, Sony NSCE, Belgium * Peter De Schrijver (p2), Mind, Belgium * Philippe De Swert, Nokia (OSSO), Finland -- | Philippe De Swert | | GPE developer: http://gpe.handhelds.org | Emdebian developer: http://www.emdebian.org | | Please do not send me documents in a closed | format.(*.doc,*.xls,*.ppt) | Use the open alternatives. (*.pdf,*.ps,*.html,*.txt) | http://www.gnu.org/philosophy/no-word-attachments.html From maillist@jg555.com Mon Dec 5 05:16:12 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Dec 2005 05:16:38 +0000 (GMT) Received: from Jg555.com ([64.30.195.78]:56792 "EHLO jg555.com") by ftp.linux-mips.org with ESMTP id S8133428AbVLEFQM (ORCPT ); Mon, 5 Dec 2005 05:16:12 +0000 Received: from [172.16.0.55] ([::ffff:172.16.0.55]) (AUTH: PLAIN root, TLS: TLSv1/SSLv3,256bits,AES256-SHA) by jg555.com with esmtp; Sun, 04 Dec 2005 21:15:44 -0800 id 00098008.4393CD00.00006FED Message-ID: <4393CCEE.2080107@jg555.com> Date: Sun, 04 Dec 2005 21:15:26 -0800 From: Jim Gifford User-Agent: Mozilla Thunderbird 1.0.7 (Windows/20050923) X-Accept-Language: en-us, en Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=_server-28653-1133759744-0001-2" To: Linux MIPS List Subject: Patch for RaQ2 - cpu features.h Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9586 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maillist@jg555.com Precedence: bulk X-list: linux-mips This is a MIME-formatted message. If you see this text it means that your E-mail software does not support MIME-formatted messages. --=_server-28653-1133759744-0001-2 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 7bit This replaces the cpu-probe.c hack we had before, which disabled ll_sc.. I followed the format of theother cpu-feature-overrides.h. -- ---- Jim Gifford maillist@jg555.com --=_server-28653-1133759744-0001-2 Content-Type: text/x-diff; name="cobalt_override.patch"; charset=iso-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="cobalt_override.patch" diff -Naur linux-2.6.14.orig/include/asm-mips/cobalt/cpu-feature-overrides.h linux-2.6.14/include/asm-mips/cobalt/cpu-feature-overrides.h --- linux-2.6.14.orig/include/asm-mips/cobalt/cpu-feature-overrides.h 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.14/include/asm-mips/cobalt/cpu-feature-overrides.h 2005-11-29 23:02:33.000000000 +0000 @@ -0,0 +1,24 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Chris Dearman + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_COBALT_MIPS_CPU_FEATURE_OVERRIDES_H +#define __ASM_COBALT_MIPS_CPU_FEATURE_OVERRIDES_H + +#include + +/* + * CPU feature overrides for Cobalt Servers + */ + +#ifdef CONFIG_64BIT +#define cpu_has_llsc 0 +#else +#define cpu_has_llsc 1 +#endif + +#endif /* __ASM_COBALT_MIPS_CPU_FEATURE_OVERRIDES_H */ --=_server-28653-1133759744-0001-2-- From maillist@jg555.com Mon Dec 5 05:19:09 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Dec 2005 05:19:41 +0000 (GMT) Received: from Jg555.com ([64.30.195.78]:57560 "EHLO jg555.com") by ftp.linux-mips.org with ESMTP id S8133576AbVLEFTJ (ORCPT ); Mon, 5 Dec 2005 05:19:09 +0000 Received: from [172.16.0.55] ([::ffff:172.16.0.55]) (AUTH: PLAIN root, TLS: TLSv1/SSLv3,256bits,AES256-SHA) by jg555.com with esmtp; Sun, 04 Dec 2005 21:18:40 -0800 id 00098008.4393CDB1.00007037 Message-ID: <4393CD9F.3090305@jg555.com> Date: Sun, 04 Dec 2005 21:18:23 -0800 From: Jim Gifford User-Agent: Mozilla Thunderbird 1.0.7 (Windows/20050923) X-Accept-Language: en-us, en Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=_server-28727-1133759921-0001-2" To: Linux MIPS List Subject: Tulip RaQ2 64 Bit Fix Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 9587 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maillist@jg555.com Precedence: bulk X-list: linux-mips This is a MIME-formatted message. If you see this text it means that your E-mail software does not support MIME-formatted messages. --=_server-28727-1133759921-0001-2 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 7bit The attached patch allows the tulip driver to work with the RaQ2's network adapter. Without the patch under a 64 bit build, it will never negotiate and will drop packets. This driver is part of Linux Parisc, by Grant Grundler. It's currently in -mm, but Jeff Garzick will not apply it to the main tree. When Grant modified this driver, he used the manufactures specs on the tulip chip. -- ---- Jim Gifford maillist@jg555.com --=_server-28727-1133759921-0001-2 Content-Type: text/x-diff; name="tulip.patch"; charset=iso-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="tulip.patch" diff -Naur linux-mips-2.6.14.orig/drivers/net/tulip/21142.c linux-mips-2.6.14/drivers/net/tulip/21142.c --- linux-mips-2.6.14.orig/drivers/net/tulip/21142.c 2005-11-17 11:43:12.000000000 -0800 +++ linux-mips-2.6.14/drivers/net/tulip/21142.c 2005-11-17 21:52:47.000000000 -0800 @@ -172,7 +172,7 @@ int i; for (i = 0; i < tp->mtable->leafcount; i++) if (tp->mtable->mleaf[i].media == dev->if_port) { - int startup = ! ((tp->chip_id == DC21143 && (tp->revision == 48 || tp->revision == 65))); + int startup = ! ((tp->chip_id == DC21143 && tp->revision == 65)); tp->cur_index = i; tulip_select_media(dev, startup); setup_done = 1; diff -Naur linux-mips-2.6.14.orig/drivers/net/tulip/media.c linux-mips-2.6.14/drivers/net/tulip/media.c --- linux-mips-2.6.14.orig/drivers/net/tulip/media.c 2005-11-17 11:43:13.000000000 -0800 +++ linux-mips-2.6.14/drivers/net/tulip/media.c 2005-11-17 21:52:47.000000000 -0800 @@ -44,8 +44,10 @@ /* MII transceiver control section. Read and write the MII registers using software-generated serial - MDIO protocol. See the MII specifications or DP83840A data sheet - for details. */ + MDIO protocol. + See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions") + or DP83840A data sheet for more details. + */ int tulip_mdio_read(struct net_device *dev, int phy_id, int location) { @@ -261,24 +263,56 @@ u16 *reset_sequence = &((u16*)(p+3))[init_length]; int reset_length = p[2 + init_length*2]; misc_info = reset_sequence + reset_length; - if (startup) + if (startup) { + int timeout = 10; /* max 1 ms */ for (i = 0; i < reset_length; i++) iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15); + + /* flush posted writes */ + ioread32(ioaddr + CSR15); + + /* Sect 3.10.3 in DP83840A.pdf (p39) */ + udelay(500); + + /* Section 4.2 in DP83840A.pdf (p43) */ + /* and IEEE 802.3 "22.2.4.1.1 Reset" */ + while (timeout-- && + (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET)) + udelay(100); + } for (i = 0; i < init_length; i++) iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15); + + ioread32(ioaddr + CSR15); /* flush posted writes */ } else { u8 *init_sequence = p + 2; u8 *reset_sequence = p + 3 + init_length; int reset_length = p[2 + init_length]; misc_info = (u16*