From ralf@linux-mips.org Thu Jun 2 13:59:24 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jun 2005 13:59:40 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:8461 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Thu, 2 Jun 2005 13:59:24 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j52CvixX014518; Thu, 2 Jun 2005 13:57:44 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j52Cvh0r014517; Thu, 2 Jun 2005 13:57:43 +0100 Date: Thu, 2 Jun 2005 13:57:43 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [RFC] remove NEC Osprey Message-ID: <20050602125742.GA12594@linux-mips.org> References: <20050526235125.636bd22a.yuasa@hh.iij4u.or.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20050526235125.636bd22a.yuasa@hh.iij4u.or.jp> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8036 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, May 26, 2005 at 11:51:25PM +0900, Yoichi Yuasa wrote: > I think that NEC Osprey is not maintained on v2.6. > If there is no objection, I'll send a patch for removing NEC Osprey next week. Nobody raised objections, so please go ahead. After all Osprey code will remain in CVS for anybody who should still have interest. Ralf From jerry@wicomtechnologies.com Thu Jun 2 14:39:32 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jun 2005 14:39:46 +0100 (BST) Received: from smtp.wicomtechnologies.com ([IPv6:::ffff:195.234.214.162]:50119 "EHLO smtp.wicomtechnologies.com") by linux-mips.org with ESMTP id ; Thu, 2 Jun 2005 14:39:32 +0100 Received: from [192.168.0.24] (wcm-24.wicom.kiev.ua [192.168.0.24] (may be forged)) by smtp.wicomtechnologies.com (8.12.10/8.12.10) with ESMTP id j52DdP5K046186 for ; Thu, 2 Jun 2005 16:39:25 +0300 (EEST) (envelope-from jerry@wicomtechnologies.com) Date: Thu, 2 Jun 2005 16:40:49 +0300 From: Jerry X-Mailer: The Bat! (v3.0.1.33) Professional Reply-To: Jerry X-Priority: 3 (Normal) Message-ID: <685359936.20050602164049@wicomtechnologies.com> To: linux-mips Subject: fb documentation MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8037 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jerry@wicomtechnologies.com Precedence: bulk X-list: linux-mips Hello. Can anyone point me out to any available information about writing framebuffer drivers, fb structure, internals, interactions, driver requirements, etc...? Documentation/fb is very user-level... ()_() -( ^,^ )- -[21398845]- -- -<02/06/2005 16:32>- (") (") From ralf@linux-mips.org Thu Jun 2 15:33:39 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jun 2005 15:33:53 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:47898 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Thu, 2 Jun 2005 15:33:38 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j52EVx57018020; Thu, 2 Jun 2005 15:31:59 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j52EVxqt018019; Thu, 2 Jun 2005 15:31:59 +0100 Date: Thu, 2 Jun 2005 15:31:58 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH 2.6] vr41xx: update IRQ handling Message-ID: <20050602143158.GC16551@linux-mips.org> References: <20050530000546.5b7da65d.yuasa@hh.iij4u.or.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20050530000546.5b7da65d.yuasa@hh.iij4u.or.jp> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8038 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, May 30, 2005 at 12:05:46AM +0900, Yoichi Yuasa wrote: > This patch had updated IRQ handling for vr41xx. > o added common IRQ dispatch > o changed IRQ number in int-handler.S > o added resource management to icu.c Thanks, applied. Ralf From eckhardt@satorlaser.com Thu Jun 2 16:32:45 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jun 2005 16:33:03 +0100 (BST) Received: from moutng.kundenserver.de ([IPv6:::ffff:212.227.126.187]:15304 "EHLO moutng.kundenserver.de") by linux-mips.org with ESMTP id ; Thu, 2 Jun 2005 16:32:45 +0100 Received: from [213.39.254.68] (helo=tuxator.satorlaser-intern.com) by mrelayeu.kundenserver.de with ESMTP (Nemesis), id 0MKwtQ-1Ddrga0krH-0005HQ; Thu, 02 Jun 2005 17:32:44 +0200 From: Ulrich Eckhardt Organization: Sator Laser GmbH To: linux-mips@linux-mips.org Subject: Re: fb documentation Date: Thu, 2 Jun 2005 17:34:47 +0200 User-Agent: KMail/1.7.2 References: <685359936.20050602164049@wicomtechnologies.com> In-Reply-To: <685359936.20050602164049@wicomtechnologies.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200506021734.47704.eckhardt@satorlaser.com> X-Provags-ID: kundenserver.de abuse@kundenserver.de login:e35cee35a663f5c944b9750a965814ae Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8039 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: eckhardt@satorlaser.com Precedence: bulk X-list: linux-mips Jerry wrote: > Can anyone point me out to any available information about writing > framebuffer drivers, fb structure, internals, interactions, driver > requirements, etc...? There is a whole mailinglist devoted to writing framebuffer which is hosted at sourceforge's called fbdev[1], you should try there. Uli [1]: linux-fbdev-devel@lists.sourceforge.net From yuasa@hh.iij4u.or.jp Thu Jun 2 23:34:04 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jun 2005 23:34:31 +0100 (BST) Received: from mo00.iij4u.or.jp ([IPv6:::ffff:210.130.0.19]:24522 "EHLO mo00.iij4u.or.jp") by linux-mips.org with ESMTP id ; Thu, 2 Jun 2005 23:34:04 +0100 Received: MO(mo00)id j52MXwbV013589; Fri, 3 Jun 2005 07:33:58 +0900 (JST) Received: MDO(mdo01) id j52MXv4j000232; Fri, 3 Jun 2005 07:33:57 +0900 (JST) Received: from stratos (h042.p502.iij4u.or.jp [210.149.246.42]) by mbox.iij4u.or.jp (4U-MR/mbox01) id j52MXtVc006408 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NOT); Fri, 3 Jun 2005 07:33:56 +0900 (JST) Date: Fri, 3 Jun 2005 07:33:49 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@hh.iij4u.or.jp, linux-mips Subject: [PATCH 2.6] remove NEC Osprey Message-Id: <20050603073349.28f1a533.yuasa@hh.iij4u.or.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8040 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@hh.iij4u.or.jp Precedence: bulk X-list: linux-mips Hi, This patch had removed NEC Opsrey support from v2.6. Please apply. Thanks, Yoichi diff -urN -X dontdiff b-orig/arch/mips/Kconfig b/arch/mips/Kconfig --- b-orig/arch/mips/Kconfig Sat Mar 19 11:14:22 2005 +++ b/arch/mips/Kconfig Fri Jun 3 07:10:31 2005 @@ -431,15 +431,6 @@ Features : kernel debugging, serial terminal, NFS root fs, on-board ether port USB, AC97, PCI, etc. -config NEC_OSPREY - bool "Support for NEC Osprey board" - select DMA_NONCOHERENT - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_LITTLE_ENDIAN - select VR4181 - config MACH_VR41XX bool "Support for NEC VR41XX-based machines" diff -urN -X dontdiff b-orig/arch/mips/Makefile b/arch/mips/Makefile --- b-orig/arch/mips/Makefile Fri May 20 00:18:17 2005 +++ b/arch/mips/Makefile Fri Jun 3 07:10:31 2005 @@ -495,13 +495,6 @@ load-$(CONFIG_LASAT) += 0xffffffff80000000 # -# NEC Osprey (vr4181) board -# -core-$(CONFIG_NEC_OSPREY) += arch/mips/vr4181/common/ \ - arch/mips/vr4181/osprey/ -load-$(CONFIG_NEC_OSPREY) += 0xffffffff80002000 - -# # Common VR41xx # core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ diff -urN -X dontdiff b-orig/arch/mips/vr4181/Kconfig b/arch/mips/vr4181/Kconfig --- b-orig/arch/mips/vr4181/Kconfig Sat Mar 19 11:14:31 2005 +++ b/arch/mips/vr4181/Kconfig Thu Jan 1 09:00:00 1970 @@ -1,61 +0,0 @@ -config NEC_CMBVR4133 - bool "Support for NEC CMB-VR4133" - depends on MACH_VR41XX - select CPU_VR41XX - select DMA_NONCOHERENT - select IRQ_CPU - select HW_HAS_PCI - select PCI_VR41XX - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - -config ROCKHOPPER - bool "Support for Rockhopper baseboard" - depends on NEC_CMBVR4133 - select I8259 - select HAVE_STD_PC_SERIAL_PORT - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - -config CASIO_E55 - bool "Support for CASIO CASSIOPEIA E-10/15/55/65" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select IRQ_CPU - select ISA - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - -config IBM_WORKPAD - bool "Support for IBM WorkPad z50" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select IRQ_CPU - select ISA - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - -config TANBAC_TB0226 - bool "Support for TANBAC TB0226 (Mbase)" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - help - The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by - TANBAC. Please refer to about Mbase. - -config TANBAC_TB0229 - bool "Support for TANBAC TB0229 (VR4131DIMM)" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - help - The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured - by TANBAC. Please refer to about - VR4131DIMM. diff -urN -X dontdiff b-orig/arch/mips/vr4181/common/Makefile b/arch/mips/vr4181/common/Makefile --- b-orig/arch/mips/vr4181/common/Makefile Tue Jan 7 22:25:00 2003 +++ b/arch/mips/vr4181/common/Makefile Thu Jan 1 09:00:00 1970 @@ -1,7 +0,0 @@ -# -# Makefile for common code of NEC vr4181 based boards -# - -obj-y := irq.o int_handler.o serial.o time.o - -EXTRA_AFLAGS := $(CFLAGS) diff -urN -X dontdiff b-orig/arch/mips/vr4181/common/int_handler.S b/arch/mips/vr4181/common/int_handler.S --- b-orig/arch/mips/vr4181/common/int_handler.S Wed Oct 3 08:27:11 2001 +++ b/arch/mips/vr4181/common/int_handler.S Thu Jan 1 09:00:00 1970 @@ -1,206 +0,0 @@ -/* - * arch/mips/vr4181/common/int_handler.S - * - * Adapted to the VR4181 and almost entirely rewritten: - * Copyright (C) 1999 Bradley D. LaRonde and Michael Klar - * - * Clean up to conform to the new IRQ - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include -#include -#include -#include - -#include - -/* - * [jsun] - * See include/asm/vr4181/irq.h for IRQ assignment and strategy. - */ - - .text - .set noreorder - - .align 5 - NESTED(vr4181_handle_irq, PT_SIZE, ra) - - .set noat - SAVE_ALL - CLI - - .set at - .set noreorder - - mfc0 t0, CP0_CAUSE - mfc0 t2, CP0_STATUS - - and t0, t2 - - /* we check IP3 first; it happens most frequently */ - andi t1, t0, STATUSF_IP3 - bnez t1, ll_cpu_ip3 - andi t1, t0, STATUSF_IP2 - bnez t1, ll_cpu_ip2 - andi t1, t0, STATUSF_IP7 /* cpu timer */ - bnez t1, ll_cputimer_irq - andi t1, t0, STATUSF_IP4 - bnez t1, ll_cpu_ip4 - andi t1, t0, STATUSF_IP5 - bnez t1, ll_cpu_ip5 - andi t1, t0, STATUSF_IP6 - bnez t1, ll_cpu_ip6 - andi t1, t0, STATUSF_IP0 /* software int 0 */ - bnez t1, ll_cpu_ip0 - andi t1, t0, STATUSF_IP1 /* software int 1 */ - bnez t1, ll_cpu_ip1 - nop - - .set reorder -do_spurious: - j spurious_interrupt - -/* - * regular CPU irqs - */ -ll_cputimer_irq: - li a0, VR4181_IRQ_TIMER - move a1, sp - jal do_IRQ - j ret_from_irq - - -ll_cpu_ip0: - li a0, VR4181_IRQ_SW1 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip1: - li a0, VR4181_IRQ_SW2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip3: - li a0, VR4181_IRQ_INT1 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip4: - li a0, VR4181_IRQ_INT2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip5: - li a0, VR4181_IRQ_INT3 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip6: - li a0, VR4181_IRQ_INT4 - move a1, sp - jal do_IRQ - j ret_from_irq - -/* - * One of the sys irq has happend. - * - * In the interest of speed, we first determine in the following order - * which 16-irq block have pending interrupts: - * sysint1 (16 sources, including cascading intrs from GPIO) - * sysint2 - * gpio (16 intr sources) - * - * Then we do binary search to find the exact interrupt source. - */ -ll_cpu_ip2: - - lui t3,%hi(VR4181_SYSINT1REG) - lhu t0,%lo(VR4181_SYSINT1REG)(t3) - lhu t2,%lo(VR4181_MSYSINT1REG)(t3) - and t0, 0xfffb /* hack - remove RTC Long 1 intr */ - and t0, t2 - beqz t0, check_sysint2 - - /* check for GPIO interrupts */ - andi t1, t0, 0x0100 - bnez t1, check_gpio_int - - /* so we have an interrupt in sysint1 which is not gpio int */ - li a0, VR4181_SYS_IRQ_BASE - 1 - j check_16 - -check_sysint2: - - lhu t0,%lo(VR4181_SYSINT2REG)(t3) - lhu t2,%lo(VR4181_MSYSINT2REG)(t3) - and t0, 0xfffe /* hack - remove RTC Long 2 intr */ - and t0, t2 - li a0, VR4181_SYS_IRQ_BASE + 16 - 1 - j check_16 - -check_gpio_int: - lui t3,%hi(VR4181_GPINTMSK) - lhu t0,%lo(VR4181_GPINTMSK)(t3) - lhu t2,%lo(VR4181_GPINTSTAT)(t3) - xori t0, 0xffff /* why? reverse logic? */ - and t0, t2 - li a0, VR4181_GPIO_IRQ_BASE - 1 - j check_16 - -/* - * When we reach check_16, we have 16-bit status in t0 and base irq number - * in a0. - */ -check_16: - andi t1, t0, 0xff - bnez t1, check_8 - - srl t0, 8 - addi a0, 8 - j check_8 - -/* - * When we reach check_8, we have 8-bit status in t0 and base irq number - * in a0. - */ -check_8: - andi t1, t0, 0xf - bnez t1, check_4 - - srl t0, 4 - addi a0, 4 - j check_4 - -/* - * When we reach check_4, we have 4-bit status in t0 and base irq number - * in a0. - */ -check_4: - andi t0, t0, 0xf - beqz t0, do_spurious - -loop: - andi t2, t0, 0x1 - srl t0, 1 - addi a0, 1 - beqz t2, loop - -found_it: - move a1, sp - jal do_IRQ - - j ret_from_irq - - END(vr4181_handle_irq) diff -urN -X dontdiff b-orig/arch/mips/vr4181/common/irq.c b/arch/mips/vr4181/common/irq.c --- b-orig/arch/mips/vr4181/common/irq.c Wed Mar 2 00:15:41 2005 +++ b/arch/mips/vr4181/common/irq.c Thu Jan 1 09:00:00 1970 @@ -1,237 +0,0 @@ -/* - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * linux/arch/mips/vr4181/common/irq.c - * Completely re-written to use the new irq.c - * - * Credits to Bradley D. LaRonde and Michael Klar for writing the original - * irq.c file which was derived from the common irq.c file. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -/* - * Strategy: - * - * We essentially have three irq controllers, CPU, system, and gpio. - * - * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and - * CONFIG_IRQ_CPU config option. - * - * We here provide sys_irq and gpio_irq controller code. - */ - -static int sys_irq_base; -static int gpio_irq_base; - -/* ---------------------- sys irq ------------------------ */ -static void -sys_irq_enable(unsigned int irq) -{ - irq -= sys_irq_base; - if (irq < 16) { - *VR4181_MSYSINT1REG |= (u16)(1 << irq); - } else { - irq -= 16; - *VR4181_MSYSINT2REG |= (u16)(1 << irq); - } -} - -static void -sys_irq_disable(unsigned int irq) -{ - irq -= sys_irq_base; - if (irq < 16) { - *VR4181_MSYSINT1REG &= ~((u16)(1 << irq)); - } else { - irq -= 16; - *VR4181_MSYSINT2REG &= ~((u16)(1 << irq)); - } - -} - -static unsigned int -sys_irq_startup(unsigned int irq) -{ - sys_irq_enable(irq); - return 0; -} - -#define sys_irq_shutdown sys_irq_disable -#define sys_irq_ack sys_irq_disable - -static void -sys_irq_end(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - sys_irq_enable(irq); -} - -static hw_irq_controller sys_irq_controller = { - .typename = "vr4181_sys_irq", - .startup = sys_irq_startup, - .shutdown = sys_irq_shutdown, - .enable = sys_irq_enable, - .disable = sys_irq_disable, - .ack = sys_irq_ack, - .end = sys_irq_end, -}; - -/* ---------------------- gpio irq ------------------------ */ -/* gpio irq lines use reverse logic */ -static void -gpio_irq_enable(unsigned int irq) -{ - irq -= gpio_irq_base; - *VR4181_GPINTMSK &= ~((u16)(1 << irq)); -} - -static void -gpio_irq_disable(unsigned int irq) -{ - irq -= gpio_irq_base; - *VR4181_GPINTMSK |= (u16)(1 << irq); -} - -static unsigned int -gpio_irq_startup(unsigned int irq) -{ - gpio_irq_enable(irq); - - irq -= gpio_irq_base; - *VR4181_GPINTEN |= (u16)(1 << irq ); - - return 0; -} - -static void -gpio_irq_shutdown(unsigned int irq) -{ - gpio_irq_disable(irq); - - irq -= gpio_irq_base; - *VR4181_GPINTEN &= ~((u16)(1 << irq )); -} - -static void -gpio_irq_ack(unsigned int irq) -{ - u16 irqtype; - u16 irqshift; - - gpio_irq_disable(irq); - - /* we clear interrupt if it is edge triggered */ - irq -= gpio_irq_base; - if (irq < 8) { - irqtype = *VR4181_GPINTTYPL; - irqshift = 2 << (irq*2); - } else { - irqtype = *VR4181_GPINTTYPH; - irqshift = 2 << ((irq-8)*2); - } - if ( ! (irqtype & irqshift) ) { - *VR4181_GPINTSTAT = (u16) (1 << irq); - } -} - -static void -gpio_irq_end(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - gpio_irq_enable(irq); -} - -static hw_irq_controller gpio_irq_controller = { - .typename = "vr4181_gpio_irq", - .startup = gpio_irq_startup, - .shutdown = gpio_irq_shutdown, - .enable = gpio_irq_enable, - .disable = gpio_irq_disable, - .ack = gpio_irq_ack, - .end = gpio_irq_end, -}; - -/* --------------------- IRQ init stuff ---------------------- */ - -extern asmlinkage void vr4181_handle_irq(void); -extern void breakpoint(void); -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); -extern void mips_cpu_irq_init(u32 irq_base); - -static struct irqaction cascade = - { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL }; -static struct irqaction reserved = - { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL }; - -void __init arch_init_irq(void) -{ - int i; - - set_except_vector(0, vr4181_handle_irq); - - /* init CPU irqs */ - mips_cpu_irq_init(VR4181_CPU_IRQ_BASE); - - /* init sys irqs */ - sys_irq_base = VR4181_SYS_IRQ_BASE; - for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &sys_irq_controller; - } - - /* init gpio irqs */ - gpio_irq_base = VR4181_GPIO_IRQ_BASE; - for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &gpio_irq_controller; - } - - /* Default all ICU IRQs to off ... */ - *VR4181_MSYSINT1REG = 0; - *VR4181_MSYSINT2REG = 0; - - /* We initialize the level 2 ICU registers to all bits disabled. */ - *VR4181_MPIUINTREG = 0; - *VR4181_MAIUINTREG = 0; - *VR4181_MKIUINTREG = 0; - - /* disable all GPIO intrs */ - *VR4181_GPINTMSK = 0xffff; - - /* vector handler. What these do is register the IRQ as non-sharable */ - setup_irq(VR4181_IRQ_INT0, &cascade); - setup_irq(VR4181_IRQ_GIU, &cascade); - - /* - * RTC interrupts are interesting. They have two destinations. - * One is at sys irq controller, and the other is at CPU IP3 and IP4. - * RTC timer is used as system timer. - * We enable them here, but timer routine will register later - * with CPU IP3/IP4. - */ - setup_irq(VR4181_IRQ_RTCL1, &reserved); - setup_irq(VR4181_IRQ_RTCL2, &reserved); -} diff -urN -X dontdiff b-orig/arch/mips/vr4181/common/serial.c b/arch/mips/vr4181/common/serial.c --- b-orig/arch/mips/vr4181/common/serial.c Tue Aug 6 09:08:57 2002 +++ b/arch/mips/vr4181/common/serial.c Thu Jan 1 09:00:00 1970 @@ -1,51 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/vr4181/common/serial.c - * initialize serial port on vr4181. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * [jsun, 010925] - * You need to make sure rs_table has at least one element in - * drivers/char/serial.c file. There is no good way to do it right - * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your - * configure file, which would gives you 64 ports and wastes 11K ram. - */ - -#include -#include -#include -#include - -#include - -void __init vr4181_init_serial(void) -{ - struct serial_struct s; - - /* turn on UART clock */ - *VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU; - - /* clear memory */ - memset(&s, 0, sizeof(s)); - - s.line = 0; /* we set the first one */ - s.baud_base = 1152000; - s.irq = VR4181_IRQ_SIU; - s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */ - s.iomem_base = (u8*)VR4181_SIURB; - s.iomem_reg_shift = 0; - s.io_type = SERIAL_IO_MEM; - if (early_serial_setup(&s) != 0) { - panic("vr4181_init_serial() failed!"); - } -} - diff -urN -X dontdiff b-orig/arch/mips/vr4181/common/time.c b/arch/mips/vr4181/common/time.c --- b-orig/arch/mips/vr4181/common/time.c Fri Jan 14 14:32:38 2005 +++ b/arch/mips/vr4181/common/time.c Thu Jan 1 09:00:00 1970 @@ -1,145 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * rtc and time ops for vr4181. Part of code is drived from - * linux-vr, originally written by Bradley D. LaRonde & Michael Klar. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include /* for HZ */ -#include -#include - -#include -#include - -#include - -#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ) - -/* - * RTC ops - */ - -DEFINE_SPINLOCK(rtc_lock); - -/* per VR41xx docs, bad data can be read if between 2 counts */ -static inline unsigned short -read_time_reg(volatile unsigned short *reg) -{ - unsigned short value; - do { - value = *reg; - barrier(); - } while (value != *reg); - return value; -} - -static unsigned long -vr4181_rtc_get_time(void) -{ - unsigned short regh, regm, regl; - - // why this crazy order, you ask? to guarantee that neither m - // nor l wrap before all 3 read - do { - regm = read_time_reg(VR4181_ETIMEMREG); - barrier(); - regh = read_time_reg(VR4181_ETIMEHREG); - barrier(); - regl = read_time_reg(VR4181_ETIMELREG); - } while (regm != read_time_reg(VR4181_ETIMEMREG)); - return ((regh << 17) | (regm << 1) | (regl >> 15)); -} - -static int -vr4181_rtc_set_time(unsigned long timeval) -{ - unsigned short intreg; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - intreg = *VR4181_RTCINTREG & 0x05; - barrier(); - *VR4181_ETIMELREG = timeval << 15; - *VR4181_ETIMEMREG = timeval >> 1; - *VR4181_ETIMEHREG = timeval >> 17; - barrier(); - // assume that any ints that just triggered are invalid, since the - // time value is written non-atomically in 3 separate regs - *VR4181_RTCINTREG = 0x05 ^ intreg; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - - -/* - * timer interrupt routine (wrapper) - * - * we need our own interrupt routine because we need to clear - * RTC1 interrupt. - */ -static void -vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - /* Clear the interrupt. */ - *VR4181_RTCINTREG = 0x2; - - /* call the generic one */ - timer_interrupt(irq, dev_id, regs); -} - - -/* - * vr4181_time_init: - * - * We pick the following choices: - * . we use elapsed timer as the RTC. We set some reasonable init data since - * it does not persist across reset - * . we use RTC1 as the system timer interrupt source. - * . we use CPU counter for fast_gettimeoffset and we calivrate the cpu - * frequency. In other words, we use calibrate_div64_gettimeoffset(). - * . we use our own timer interrupt routine which clears the interrupt - * and then calls the generic high-level timer interrupt routine. - * - */ - -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); - -static void -vr4181_timer_setup(struct irqaction *irq) -{ - /* over-write the handler to be our own one */ - irq->handler = vr4181_timer_interrupt; - - /* sets up the frequency */ - *VR4181_RTCL1LREG = COUNTS_PER_JIFFY; - *VR4181_RTCL1HREG = 0; - - /* and ack any pending ints */ - *VR4181_RTCINTREG = 0x2; - - /* setup irqaction */ - setup_irq(VR4181_IRQ_INT1, irq); - -} - -void -vr4181_init_time(void) -{ - /* setup hookup functions */ - rtc_get_time = vr4181_rtc_get_time; - rtc_set_time = vr4181_rtc_set_time; - - board_timer_setup = vr4181_timer_setup; -} - diff -urN -X dontdiff b-orig/arch/mips/vr4181/osprey/Makefile b/arch/mips/vr4181/osprey/Makefile --- b-orig/arch/mips/vr4181/osprey/Makefile Fri Feb 28 01:20:25 2003 +++ b/arch/mips/vr4181/osprey/Makefile Thu Jan 1 09:00:00 1970 @@ -1,7 +0,0 @@ -# -# Makefile for common code of NEC Osprey board -# - -obj-y := setup.o prom.o reset.o - -obj-$(CONFIG_KGDB) += dbg_io.o diff -urN -X dontdiff b-orig/arch/mips/vr4181/osprey/dbg_io.c b/arch/mips/vr4181/osprey/dbg_io.c --- b-orig/arch/mips/vr4181/osprey/dbg_io.c Sun Feb 3 17:09:17 2002 +++ b/arch/mips/vr4181/osprey/dbg_io.c Thu Jan 1 09:00:00 1970 @@ -1,136 +0,0 @@ -/* - * kgdb io functions for osprey. We use the serial port on debug board. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* ======================= CONFIG ======================== */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE 0xb7fffff0 -#define MAX_BAUD 115200 - -/* distance in bytes between two serial registers */ -#define REG_OFFSET 1 - -/* - * 0 - kgdb does serial init - * 1 - kgdb skip serial init - */ -static int remoteDebugInitialized = 1; - -/* - * the default baud rate *if* kgdb does serial init - */ -#define BAUD_DEFAULT UART16550_BAUD_38400 - -/* ======================= END OF CONFIG ======================== */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up buad rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} diff -urN -X dontdiff b-orig/arch/mips/vr4181/osprey/prom.c b/arch/mips/vr4181/osprey/prom.c --- b-orig/arch/mips/vr4181/osprey/prom.c Thu Jan 29 23:17:19 2004 +++ b/arch/mips/vr4181/osprey/prom.c Thu Jan 1 09:00:00 1970 @@ -1,49 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * arch/mips/vr4181/osprey/prom.c - * prom code for osprey. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include -#include -#include - -const char *get_system_type(void) -{ - return "NEC_Vr41xx Osprey"; -} - -/* - * [jsun] right now we assume it is the nec debug monitor, which does - * not pass any arguments. - */ -void __init prom_init(void) -{ - // cmdline is now set in default config - // strcpy(arcs_cmdline, "ip=bootp "); - // strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 "); - // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 " - // strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 "); - - mips_machgroup = MACH_GROUP_NEC_VR41XX; - mips_machtype = MACH_NEC_OSPREY; - - /* 16MB fixed */ - add_memory_region(0, 16 << 20, BOOT_MEM_RAM); -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff -urN -X dontdiff b-orig/arch/mips/vr4181/osprey/reset.c b/arch/mips/vr4181/osprey/reset.c --- b-orig/arch/mips/vr4181/osprey/reset.c Sun Dec 29 23:50:55 2002 +++ b/arch/mips/vr4181/osprey/reset.c Thu Jan 1 09:00:00 1970 @@ -1,40 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - */ -#include -#include -#include -#include -#include -#include -#include - -void nec_osprey_restart(char *command) -{ - set_c0_status(ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -void nec_osprey_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void nec_osprey_power_off(void) -{ - nec_osprey_halt(); -} diff -urN -X dontdiff b-orig/arch/mips/vr4181/osprey/setup.c b/arch/mips/vr4181/osprey/setup.c --- b-orig/arch/mips/vr4181/osprey/setup.c Sun Jan 16 22:34:31 2005 +++ b/arch/mips/vr4181/osprey/setup.c Thu Jan 1 09:00:00 1970 @@ -1,68 +0,0 @@ -/* - * linux/arch/mips/vr4181/setup.c - * - * VR41xx setup routines - * - * Copyright (C) 1999 Bradley D. LaRonde - * Copyright (C) 1999, 2000 Michael Klar - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include -#include -#include -#include -#include -#include - - -extern void nec_osprey_restart(char* c); -extern void nec_osprey_halt(void); -extern void nec_osprey_power_off(void); - -extern void vr4181_init_serial(void); -extern void vr4181_init_time(void); - -static void __init nec_osprey_setup(void) -{ - set_io_port_base(VR4181_PORT_BASE); - isa_slot_offset = VR4181_ISAMEM_BASE; - - vr4181_init_serial(); - vr4181_init_time(); - - _machine_restart = nec_osprey_restart; - _machine_halt = nec_osprey_halt; - _machine_power_off = nec_osprey_power_off; - - /* setup resource limit */ - ioport_resource.end = 0xffffffff; - iomem_resource.end = 0xffffffff; - - /* [jsun] hack */ - /* - printk("[jsun] hack to change external ISA control register, %x -> %x\n", - (*VR4181_XISACTL), - (*VR4181_XISACTL) | 0x2); - *VR4181_XISACTL |= 0x2; - */ - - // *VR4181_GPHIBSTH = 0x2000; - // *VR4181_GPMD0REG = 0x00c0; - // *VR4181_GPINTEN = 1<<6; - - /* [jsun] I believe this will get the interrupt type right - * for the ether port. - */ - *VR4181_GPINTTYPL = 0x3000; -} - -early_initcall(nec_osprey_setup); diff -urN -X dontdiff b-orig/include/asm-mips/vr4181/irq.h b/include/asm-mips/vr4181/irq.h --- b-orig/include/asm-mips/vr4181/irq.h Tue Aug 6 09:09:00 2002 +++ b/include/asm-mips/vr4181/irq.h Thu Jan 1 09:00:00 1970 @@ -1,122 +0,0 @@ -/* - * Macros for vr4181 IRQ numbers. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * Strategy: - * - * Vr4181 has conceptually three levels of interrupt controllers: - * 1. the CPU itself with 8 intr level. - * 2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs - * 3. GPIO interrupts : forwarding external interrupts to sys intr controller - */ - -/* decide the irq block assignment */ -#define VR4181_NUM_CPU_IRQ 8 -#define VR4181_NUM_SYS_IRQ 32 -#define VR4181_NUM_GPIO_IRQ 16 - -#define VR4181_IRQ_BASE 0 - -#define VR4181_CPU_IRQ_BASE VR4181_IRQ_BASE -#define VR4181_SYS_IRQ_BASE (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ) -#define VR4181_GPIO_IRQ_BASE (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ) - -/* CPU interrupts */ - -/* - IP0 - Software interrupt - IP1 - Software interrupt - IP2 - All but battery, high speed modem, and real time clock - IP3 - RTC Long1 (system timer) - IP4 - RTC Long2 - IP5 - High Speed Modem (unused on VR4181) - IP6 - Unused - IP7 - Timer interrupt from CPO_COMPARE -*/ - -#define VR4181_IRQ_SW1 (VR4181_CPU_IRQ_BASE + 0) -#define VR4181_IRQ_SW2 (VR4181_CPU_IRQ_BASE + 1) -#define VR4181_IRQ_INT0 (VR4181_CPU_IRQ_BASE + 2) -#define VR4181_IRQ_INT1 (VR4181_CPU_IRQ_BASE + 3) -#define VR4181_IRQ_INT2 (VR4181_CPU_IRQ_BASE + 4) -#define VR4181_IRQ_INT3 (VR4181_CPU_IRQ_BASE + 5) -#define VR4181_IRQ_INT4 (VR4181_CPU_IRQ_BASE + 6) -#define VR4181_IRQ_TIMER (VR4181_CPU_IRQ_BASE + 7) - - -/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */ - -/* - IP2 - same as VR4181_IRQ_INT1 - IP8 - This is a cascade to GPIO IRQ's. Do not use. - IP16 - same as VR4181_IRQ_INT2 - IP18 - CompactFlash -*/ - -#define VR4181_IRQ_BATTERY (VR4181_SYS_IRQ_BASE + 0) -#define VR4181_IRQ_POWER (VR4181_SYS_IRQ_BASE + 1) -#define VR4181_IRQ_RTCL1 (VR4181_SYS_IRQ_BASE + 2) -#define VR4181_IRQ_ETIMER (VR4181_SYS_IRQ_BASE + 3) -#define VR4181_IRQ_RFU12 (VR4181_SYS_IRQ_BASE + 4) -#define VR4181_IRQ_PIU (VR4181_SYS_IRQ_BASE + 5) -#define VR4181_IRQ_AIU (VR4181_SYS_IRQ_BASE + 6) -#define VR4181_IRQ_KIU (VR4181_SYS_IRQ_BASE + 7) -#define VR4181_IRQ_GIU (VR4181_SYS_IRQ_BASE + 8) -#define VR4181_IRQ_SIU (VR4181_SYS_IRQ_BASE + 9) -#define VR4181_IRQ_RFU18 (VR4181_SYS_IRQ_BASE + 10) -#define VR4181_IRQ_SOFT (VR4181_SYS_IRQ_BASE + 11) -#define VR4181_IRQ_RFU20 (VR4181_SYS_IRQ_BASE + 12) -#define VR4181_IRQ_DOZEPIU (VR4181_SYS_IRQ_BASE + 13) -#define VR4181_IRQ_RFU22 (VR4181_SYS_IRQ_BASE + 14) -#define VR4181_IRQ_RFU23 (VR4181_SYS_IRQ_BASE + 15) -#define VR4181_IRQ_RTCL2 (VR4181_SYS_IRQ_BASE + 16) -#define VR4181_IRQ_LED (VR4181_SYS_IRQ_BASE + 17) -#define VR4181_IRQ_ECU (VR4181_SYS_IRQ_BASE + 18) -#define VR4181_IRQ_CSU (VR4181_SYS_IRQ_BASE + 19) -#define VR4181_IRQ_USB (VR4181_SYS_IRQ_BASE + 20) -#define VR4181_IRQ_DMA (VR4181_SYS_IRQ_BASE + 21) -#define VR4181_IRQ_LCD (VR4181_SYS_IRQ_BASE + 22) -#define VR4181_IRQ_RFU31 (VR4181_SYS_IRQ_BASE + 23) -#define VR4181_IRQ_RFU32 (VR4181_SYS_IRQ_BASE + 24) -#define VR4181_IRQ_RFU33 (VR4181_SYS_IRQ_BASE + 25) -#define VR4181_IRQ_RFU34 (VR4181_SYS_IRQ_BASE + 26) -#define VR4181_IRQ_RFU35 (VR4181_SYS_IRQ_BASE + 27) -#define VR4181_IRQ_RFU36 (VR4181_SYS_IRQ_BASE + 28) -#define VR4181_IRQ_RFU37 (VR4181_SYS_IRQ_BASE + 29) -#define VR4181_IRQ_RFU38 (VR4181_SYS_IRQ_BASE + 30) -#define VR4181_IRQ_RFU39 (VR4181_SYS_IRQ_BASE + 31) - -/* Cascaded from VR4181_IRQ_GIU */ -#define VR4181_IRQ_GPIO0 (VR4181_GPIO_IRQ_BASE + 0) -#define VR4181_IRQ_GPIO1 (VR4181_GPIO_IRQ_BASE + 1) -#define VR4181_IRQ_GPIO2 (VR4181_GPIO_IRQ_BASE + 2) -#define VR4181_IRQ_GPIO3 (VR4181_GPIO_IRQ_BASE + 3) -#define VR4181_IRQ_GPIO4 (VR4181_GPIO_IRQ_BASE + 4) -#define VR4181_IRQ_GPIO5 (VR4181_GPIO_IRQ_BASE + 5) -#define VR4181_IRQ_GPIO6 (VR4181_GPIO_IRQ_BASE + 6) -#define VR4181_IRQ_GPIO7 (VR4181_GPIO_IRQ_BASE + 7) -#define VR4181_IRQ_GPIO8 (VR4181_GPIO_IRQ_BASE + 8) -#define VR4181_IRQ_GPIO9 (VR4181_GPIO_IRQ_BASE + 9) -#define VR4181_IRQ_GPIO10 (VR4181_GPIO_IRQ_BASE + 10) -#define VR4181_IRQ_GPIO11 (VR4181_GPIO_IRQ_BASE + 11) -#define VR4181_IRQ_GPIO12 (VR4181_GPIO_IRQ_BASE + 12) -#define VR4181_IRQ_GPIO13 (VR4181_GPIO_IRQ_BASE + 13) -#define VR4181_IRQ_GPIO14 (VR4181_GPIO_IRQ_BASE + 14) -#define VR4181_IRQ_GPIO15 (VR4181_GPIO_IRQ_BASE + 15) - - -// Alternative to above GPIO IRQ defines -#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin)) - -#define VR4181_IRQ_MAX (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \ - VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ) diff -urN -X dontdiff b-orig/include/asm-mips/vr4181/vr4181.h b/include/asm-mips/vr4181/vr4181.h --- b-orig/include/asm-mips/vr4181/vr4181.h Tue Aug 6 09:09:00 2002 +++ b/include/asm-mips/vr4181/vr4181.h Thu Jan 1 09:00:00 1970 @@ -1,413 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 by Michael Klar - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - */ -#ifndef __ASM_VR4181_VR4181_H -#define __ASM_VR4181_VR4181_H - -#include - -#include - -#ifndef __ASSEMBLY__ -#define __preg8 (volatile unsigned char*) -#define __preg16 (volatile unsigned short*) -#define __preg32 (volatile unsigned int*) -#else -#define __preg8 -#define __preg16 -#define __preg32 -#endif - -// Embedded CPU peripheral registers -// Note that many of the registers have different physical address for VR4181 - -// Bus Control Unit (BCU) -#define VR4181_BCUCNTREG1 __preg16(KSEG1 + 0x0A000000) /* BCU control register 1 (R/W) */ -#define VR4181_CMUCLKMSK __preg16(KSEG1 + 0x0A000004) /* Clock mask register (R/W) */ -#define VR4181_CMUCLKMSK_MSKCSUPCLK 0x0040 -#define VR4181_CMUCLKMSK_MSKAIUPCLK 0x0020 -#define VR4181_CMUCLKMSK_MSKPIUPCLK 0x0010 -#define VR4181_CMUCLKMSK_MSKADUPCLK 0x0008 -#define VR4181_CMUCLKMSK_MSKSIU18M 0x0004 -#define VR4181_CMUCLKMSK_MSKADU18M 0x0002 -#define VR4181_CMUCLKMSK_MSKUSB 0x0001 -#define VR4181_CMUCLKMSK_MSKSIU VR4181_CMUCLKMSK_MSKSIU18M -#define VR4181_BCUSPEEDREG __preg16(KSEG1 + 0x0A00000C) /* BCU access time parameter (R/W) */ -#define VR4181_BCURFCNTREG __preg16(KSEG1 + 0x0A000010) /* BCU refresh control register (R/W) */ -#define VR4181_REVIDREG __preg16(KSEG1 + 0x0A000014) /* Revision ID register (R) */ -#define VR4181_CLKSPEEDREG __preg16(KSEG1 + 0x0A000018) /* Clock speed register (R) */ -#define VR4181_EDOMCYTREG __preg16(KSEG1 + 0x0A000300) /* Memory cycle timing register (R/W) */ -#define VR4181_MEMCFG_REG __preg16(KSEG1 + 0x0A000304) /* Memory configuration register (R/W) */ -#define VR4181_MODE_REG __preg16(KSEG1 + 0x0A000308) /* SDRAM mode register (R/W) */ -#define VR4181_SDTIMINGREG __preg16(KSEG1 + 0x0A00030C) /* SDRAM timing register (R/W) */ - -// DMA Control Unit (DCU) -#define VR4181_MICDEST1REG1 __preg16(KSEG1 + 0x0A000020) /* Microphone destination 1 address register 1 (R/W) */ -#define VR4181_MICDEST1REG2 __preg16(KSEG1 + 0x0A000022) /* Microphone destination 1 address register 2 (R/W) */ -#define VR4181_MICDEST2REG1 __preg16(KSEG1 + 0x0A000024) /* Microphone destination 2 address register 1 (R/W) */ -#define VR4181_MICDEST2REG2 __preg16(KSEG1 + 0x0A000026) /* Microphone destination 2 address register 2 (R/W) */ -#define VR4181_SPKRRC1REG1 __preg16(KSEG1 + 0x0A000028) /* Speaker Source 1 address register 1 (R/W) */ -#define VR4181_SPKRRC1REG2 __preg16(KSEG1 + 0x0A00002A) /* Speaker Source 1 address register 2 (R/W) */ -#define VR4181_SPKRRC2REG1 __preg16(KSEG1 + 0x0A00002C) /* Speaker Source 2 address register 1 (R/W) */ -#define VR4181_SPKRRC2REG2 __preg16(KSEG1 + 0x0A00002E) /* Speaker Source 2 address register 2 (R/W) */ -#define VR4181_DMARSTREG __preg16(KSEG1 + 0x0A000040) /* DMA Reset register (R/W) */ -#define VR4181_AIUDMAMSKREG __preg16(KSEG1 + 0x0A000046) /* Audio DMA mask register (R/W) */ -#define VR4181_USBDMAMSKREG __preg16(KSEG1 + 0x0A000600) /* USB DMA Mask register (R/W) */ -#define VR4181_USBRXS1AREG1 __preg16(KSEG1 + 0x0A000602) /* USB Rx source 1 address register 1 (R/W) */ -#define VR4181_USBRXS1AREG2 __preg16(KSEG1 + 0x0A000604) /* USB Rx source 1 address register 2 (R/W) */ -#define VR4181_USBRXS2AREG1 __preg16(KSEG1 + 0x0A000606) /* USB Rx source 2 address register 1 (R/W) */ -#define VR4181_USBRXS2AREG2 __preg16(KSEG1 + 0x0A000608) /* USB Rx source 2 address register 2 (R/W) */ -#define VR4181_USBTXS1AREG1 __preg16(KSEG1 + 0x0A00060A) /* USB Tx source 1 address register 1 (R/W) */ -#define VR4181_USBTXS1AREG2 __preg16(KSEG1 + 0x0A00060C) /* USB Tx source 1 address register 2 (R/W) */ -#define VR4181_USBTXS2AREG1 __preg16(KSEG1 + 0x0A00060E) /* USB Tx source 2 address register 1 (R/W) */ -#define VR4181_USBTXS2AREG2 __preg16(KSEG1 + 0x0A000610) /* USB Tx source 2 address register 2 (R/W) */ -#define VR4181_USBRXD1AREG1 __preg16(KSEG1 + 0x0A00062A) /* USB Rx destination 1 address register 1 (R/W) */ -#define VR4181_USBRXD1AREG2 __preg16(KSEG1 + 0x0A00062C) /* USB Rx destination 1 address register 2 (R/W) */ -#define VR4181_USBRXD2AREG1 __preg16(KSEG1 + 0x0A00062E) /* USB Rx destination 2 address register 1 (R/W) */ -#define VR4181_USBRXD2AREG2 __preg16(KSEG1 + 0x0A000630) /* USB Rx destination 2 address register 2 (R/W) */ -#define VR4181_USBTXD1AREG1 __preg16(KSEG1 + 0x0A000632) /* USB Tx destination 1 address register 1 (R/W) */ -#define VR4181_USBTXD1AREG2 __preg16(KSEG1 + 0x0A000634) /* USB Tx destination 1 address register 2 (R/W) */ -#define VR4181_USBTXD2AREG1 __preg16(KSEG1 + 0x0A000636) /* USB Tx destination 2 address register 1 (R/W) */ -#define VR4181_USBTXD2AREG2 __preg16(KSEG1 + 0x0A000638) /* USB Tx destination 2 address register 2 (R/W) */ -#define VR4181_RxRCLENREG __preg16(KSEG1 + 0x0A000652) /* USB Rx record length register (R/W) */ -#define VR4181_TxRCLENREG __preg16(KSEG1 + 0x0A000654) /* USB Tx record length register (R/W) */ -#define VR4181_MICRCLENREG __preg16(KSEG1 + 0x0A000658) /* Microphone record length register (R/W) */ -#define VR4181_SPKRCLENREG __preg16(KSEG1 + 0x0A00065A) /* Speaker record length register (R/W) */ -#define VR4181_USBCFGREG __preg16(KSEG1 + 0x0A00065C) /* USB configuration register (R/W) */ -#define VR4181_MICDMACFGREG __preg16(KSEG1 + 0x0A00065E) /* Microphone DMA configuration register (R/W) */ -#define VR4181_SPKDMACFGREG __preg16(KSEG1 + 0x0A000660) /* Speaker DMA configuration register (R/W) */ -#define VR4181_DMAITRQREG __preg16(KSEG1 + 0x0A000662) /* DMA interrupt request register (R/W) */ -#define VR4181_DMACLTREG __preg16(KSEG1 + 0x0A000664) /* DMA control register (R/W) */ -#define VR4181_DMAITMKREG __preg16(KSEG1 + 0x0A000666) /* DMA interrupt mask register (R/W) */ - -// ISA Bridge -#define VR4181_ISABRGCTL __preg16(KSEG1 + 0x0B0002C0) /* ISA Bridge Control Register (R/W) */ -#define VR4181_ISABRGSTS __preg16(KSEG1 + 0x0B0002C2) /* ISA Bridge Status Register (R/W) */ -#define VR4181_XISACTL __preg16(KSEG1 + 0x0B0002C4) /* External ISA Control Register (R/W) */ - -// Clocked Serial Interface (CSI) -#define VR4181_CSIMODE __preg16(KSEG1 + 0x0B000900) /* CSI Mode Register (R/W) */ -#define VR4181_CSIRXDATA __preg16(KSEG1 + 0x0B000902) /* CSI Receive Data Register (R) */ -#define VR4181_CSITXDATA __preg16(KSEG1 + 0x0B000904) /* CSI Transmit Data Register (R/W) */ -#define VR4181_CSILSTAT __preg16(KSEG1 + 0x0B000906) /* CSI Line Status Register (R/W) */ -#define VR4181_CSIINTMSK __preg16(KSEG1 + 0x0B000908) /* CSI Interrupt Mask Register (R/W) */ -#define VR4181_CSIINTSTAT __preg16(KSEG1 + 0x0B00090a) /* CSI Interrupt Status Register (R/W) */ -#define VR4181_CSITXBLEN __preg16(KSEG1 + 0x0B00090c) /* CSI Transmit Burst Length Register (R/W) */ -#define VR4181_CSIRXBLEN __preg16(KSEG1 + 0x0B00090e) /* CSI Receive Burst Length Register (R/W) */ - -// Interrupt Control Unit (ICU) -#define VR4181_SYSINT1REG __preg16(KSEG1 + 0x0A000080) /* Level 1 System interrupt register 1 (R) */ -#define VR4181_MSYSINT1REG __preg16(KSEG1 + 0x0A00008C) /* Level 1 mask system interrupt register 1 (R/W) */ -#define VR4181_NMIREG __preg16(KSEG1 + 0x0A000098) /* NMI register (R/W) */ -#define VR4181_SOFTINTREG __preg16(KSEG1 + 0x0A00009A) /* Software interrupt register (R/W) */ -#define VR4181_SYSINT2REG __preg16(KSEG1 + 0x0A000200) /* Level 1 System interrupt register 2 (R) */ -#define VR4181_MSYSINT2REG __preg16(KSEG1 + 0x0A000206) /* Level 1 mask system interrupt register 2 (R/W) */ -#define VR4181_PIUINTREGro __preg16(KSEG1 + 0x0B000082) /* Level 2 PIU interrupt register (R) */ -#define VR4181_AIUINTREG __preg16(KSEG1 + 0x0B000084) /* Level 2 AIU interrupt register (R) */ -#define VR4181_MPIUINTREG __preg16(KSEG1 + 0x0B00008E) /* Level 2 mask PIU interrupt register (R/W) */ -#define VR4181_MAIUINTREG __preg16(KSEG1 + 0x0B000090) /* Level 2 mask AIU interrupt register (R/W) */ -#define VR4181_MKIUINTREG __preg16(KSEG1 + 0x0B000092) /* Level 2 mask KIU interrupt register (R/W) */ -#define VR4181_KIUINTREG __preg16(KSEG1 + 0x0B000198) /* Level 2 KIU interrupt register (R) */ - -// Power Management Unit (PMU) -#define VR4181_PMUINTREG __preg16(KSEG1 + 0x0B0000A0) /* PMU Status Register (R/W) */ -#define VR4181_PMUINT_POWERSW 0x1 /* Power switch */ -#define VR4181_PMUINT_BATT 0x2 /* Low batt during normal operation */ -#define VR4181_PMUINT_DEADMAN 0x4 /* Deadman's switch */ -#define VR4181_PMUINT_RESET 0x8 /* Reset switch */ -#define VR4181_PMUINT_RTCRESET 0x10 /* RTC Reset */ -#define VR4181_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */ -#define VR4181_PMUINT_BATTLOW 0x100 /* Battery low */ -#define VR4181_PMUINT_RTC 0x200 /* RTC Alarm */ -#define VR4181_PMUINT_DCD 0x400 /* DCD# */ -#define VR4181_PMUINT_GPIO0 0x1000 /* GPIO0 */ -#define VR4181_PMUINT_GPIO1 0x2000 /* GPIO1 */ -#define VR4181_PMUINT_GPIO2 0x4000 /* GPIO2 */ -#define VR4181_PMUINT_GPIO3 0x8000 /* GPIO3 */ - -#define VR4181_PMUCNTREG __preg16(KSEG1 + 0x0B0000A2) /* PMU Control Register (R/W) */ -#define VR4181_PMUWAITREG __preg16(KSEG1 + 0x0B0000A8) /* PMU Wait Counter Register (R/W) */ -#define VR4181_PMUDIVREG __preg16(KSEG1 + 0x0B0000AC) /* PMU Divide Mode Register (R/W) */ -#define VR4181_DRAMHIBCTL __preg16(KSEG1 + 0x0B0000B2) /* DRAM Hibernate Control Register (R/W) */ - -// Real Time Clock Unit (RTC) -#define VR4181_ETIMELREG __preg16(KSEG1 + 0x0B0000C0) /* Elapsed Time L Register (R/W) */ -#define VR4181_ETIMEMREG __preg16(KSEG1 + 0x0B0000C2) /* Elapsed Time M Register (R/W) */ -#define VR4181_ETIMEHREG __preg16(KSEG1 + 0x0B0000C4) /* Elapsed Time H Register (R/W) */ -#define VR4181_ECMPLREG __preg16(KSEG1 + 0x0B0000C8) /* Elapsed Compare L Register (R/W) */ -#define VR4181_ECMPMREG __preg16(KSEG1 + 0x0B0000CA) /* Elapsed Compare M Register (R/W) */ -#define VR4181_ECMPHREG __preg16(KSEG1 + 0x0B0000CC) /* Elapsed Compare H Register (R/W) */ -#define VR4181_RTCL1LREG __preg16(KSEG1 + 0x0B0000D0) /* RTC Long 1 L Register (R/W) */ -#define VR4181_RTCL1HREG __preg16(KSEG1 + 0x0B0000D2) /* RTC Long 1 H Register (R/W) */ -#define VR4181_RTCL1CNTLREG __preg16(KSEG1 + 0x0B0000D4) /* RTC Long 1 Count L Register (R) */ -#define VR4181_RTCL1CNTHREG __preg16(KSEG1 + 0x0B0000D6) /* RTC Long 1 Count H Register (R) */ -#define VR4181_RTCL2LREG __preg16(KSEG1 + 0x0B0000D8) /* RTC Long 2 L Register (R/W) */ -#define VR4181_RTCL2HREG __preg16(KSEG1 + 0x0B0000DA) /* RTC Long 2 H Register (R/W) */ -#define VR4181_RTCL2CNTLREG __preg16(KSEG1 + 0x0B0000DC) /* RTC Long 2 Count L Register (R) */ -#define VR4181_RTCL2CNTHREG __preg16(KSEG1 + 0x0B0000DE) /* RTC Long 2 Count H Register (R) */ -#define VR4181_RTCINTREG __preg16(KSEG1 + 0x0B0001DE) /* RTC Interrupt Register (R/W) */ - -// Deadman's Switch Unit (DSU) -#define VR4181_DSUCNTREG __preg16(KSEG1 + 0x0B0000E0) /* DSU Control Register (R/W) */ -#define VR4181_DSUSETREG __preg16(KSEG1 + 0x0B0000E2) /* DSU Dead Time Set Register (R/W) */ -#define VR4181_DSUCLRREG __preg16(KSEG1 + 0x0B0000E4) /* DSU Clear Register (W) */ -#define VR4181_DSUTIMREG __preg16(KSEG1 + 0x0B0000E6) /* DSU Elapsed Time Register (R/W) */ - -// General Purpose I/O Unit (GIU) -#define VR4181_GPMD0REG __preg16(KSEG1 + 0x0B000300) /* GPIO Mode 0 Register (R/W) */ -#define VR4181_GPMD1REG __preg16(KSEG1 + 0x0B000302) /* GPIO Mode 1 Register (R/W) */ -#define VR4181_GPMD2REG __preg16(KSEG1 + 0x0B000304) /* GPIO Mode 2 Register (R/W) */ -#define VR4181_GPMD3REG __preg16(KSEG1 + 0x0B000306) /* GPIO Mode 3 Register (R/W) */ -#define VR4181_GPDATHREG __preg16(KSEG1 + 0x0B000308) /* GPIO Data High Register (R/W) */ -#define VR4181_GPDATHREG_GPIO16 0x0001 -#define VR4181_GPDATHREG_GPIO17 0x0002 -#define VR4181_GPDATHREG_GPIO18 0x0004 -#define VR4181_GPDATHREG_GPIO19 0x0008 -#define VR4181_GPDATHREG_GPIO20 0x0010 -#define VR4181_GPDATHREG_GPIO21 0x0020 -#define VR4181_GPDATHREG_GPIO22 0x0040 -#define VR4181_GPDATHREG_GPIO23 0x0080 -#define VR4181_GPDATHREG_GPIO24 0x0100 -#define VR4181_GPDATHREG_GPIO25 0x0200 -#define VR4181_GPDATHREG_GPIO26 0x0400 -#define VR4181_GPDATHREG_GPIO27 0x0800 -#define VR4181_GPDATHREG_GPIO28 0x1000 -#define VR4181_GPDATHREG_GPIO29 0x2000 -#define VR4181_GPDATHREG_GPIO30 0x4000 -#define VR4181_GPDATHREG_GPIO31 0x8000 -#define VR4181_GPDATLREG __preg16(KSEG1 + 0x0B00030A) /* GPIO Data Low Register (R/W) */ -#define VR4181_GPDATLREG_GPIO0 0x0001 -#define VR4181_GPDATLREG_GPIO1 0x0002 -#define VR4181_GPDATLREG_GPIO2 0x0004 -#define VR4181_GPDATLREG_GPIO3 0x0008 -#define VR4181_GPDATLREG_GPIO4 0x0010 -#define VR4181_GPDATLREG_GPIO5 0x0020 -#define VR4181_GPDATLREG_GPIO6 0x0040 -#define VR4181_GPDATLREG_GPIO7 0x0080 -#define VR4181_GPDATLREG_GPIO8 0x0100 -#define VR4181_GPDATLREG_GPIO9 0x0200 -#define VR4181_GPDATLREG_GPIO10 0x0400 -#define VR4181_GPDATLREG_GPIO11 0x0800 -#define VR4181_GPDATLREG_GPIO12 0x1000 -#define VR4181_GPDATLREG_GPIO13 0x2000 -#define VR4181_GPDATLREG_GPIO14 0x4000 -#define VR4181_GPDATLREG_GPIO15 0x8000 -#define VR4181_GPINTEN __preg16(KSEG1 + 0x0B00030C) /* GPIO Interrupt Enable Register (R/W) */ -#define VR4181_GPINTMSK __preg16(KSEG1 + 0x0B00030E) /* GPIO Interrupt Mask Register (R/W) */ -#define VR4181_GPINTTYPH __preg16(KSEG1 + 0x0B000310) /* GPIO Interrupt Type High Register (R/W) */ -#define VR4181_GPINTTYPL __preg16(KSEG1 + 0x0B000312) /* GPIO Interrupt Type Low Register (R/W) */ -#define VR4181_GPINTSTAT __preg16(KSEG1 + 0x0B000314) /* GPIO Interrupt Status Register (R/W) */ -#define VR4181_GPHIBSTH __preg16(KSEG1 + 0x0B000316) /* GPIO Hibernate Pin State High Register (R/W) */ -#define VR4181_GPHIBSTL __preg16(KSEG1 + 0x0B000318) /* GPIO Hibernate Pin State Low Register (R/W) */ -#define VR4181_GPSICTL __preg16(KSEG1 + 0x0B00031A) /* GPIO Serial Interface Control Register (R/W) */ -#define VR4181_KEYEN __preg16(KSEG1 + 0x0B00031C) /* Keyboard Scan Pin Enable Register (R/W) */ -#define VR4181_PCS0STRA __preg16(KSEG1 + 0x0B000320) /* Programmable Chip Select [0] Start Address Register (R/W) */ -#define VR4181_PCS0STPA __preg16(KSEG1 + 0x0B000322) /* Programmable Chip Select [0] Stop Address Register (R/W) */ -#define VR4181_PCS0HIA __preg16(KSEG1 + 0x0B000324) /* Programmable Chip Select [0] High Address Register (R/W) */ -#define VR4181_PCS1STRA __preg16(KSEG1 + 0x0B000326) /* Programmable Chip Select [1] Start Address Register (R/W) */ -#define VR4181_PCS1STPA __preg16(KSEG1 + 0x0B000328) /* Programmable Chip Select [1] Stop Address Register (R/W) */ -#define VR4181_PCS1HIA __preg16(KSEG1 + 0x0B00032A) /* Programmable Chip Select [1] High Address Register (R/W) */ -#define VR4181_PCSMODE __preg16(KSEG1 + 0x0B00032C) /* Programmable Chip Select Mode Register (R/W) */ -#define VR4181_LCDGPMODE __preg16(KSEG1 + 0x0B00032E) /* LCD General Purpose Mode Register (R/W) */ -#define VR4181_MISCREG0 __preg16(KSEG1 + 0x0B000330) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG1 __preg16(KSEG1 + 0x0B000332) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG2 __preg16(KSEG1 + 0x0B000334) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG3 __preg16(KSEG1 + 0x0B000336) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG4 __preg16(KSEG1 + 0x0B000338) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG5 __preg16(KSEG1 + 0x0B00033A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG6 __preg16(KSEG1 + 0x0B00033C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG7 __preg16(KSEG1 + 0x0B00033D) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG8 __preg16(KSEG1 + 0x0B000340) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG9 __preg16(KSEG1 + 0x0B000342) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG10 __preg16(KSEG1 + 0x0B000344) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG11 __preg16(KSEG1 + 0x0B000346) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG12 __preg16(KSEG1 + 0x0B000348) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG13 __preg16(KSEG1 + 0x0B00034A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG14 __preg16(KSEG1 + 0x0B00034C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG15 __preg16(KSEG1 + 0x0B00034E) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_SECIRQMASKL VR4181_GPINTEN -// No SECIRQMASKH for VR4181 - -// Touch Panel Interface Unit (PIU) -#define VR4181_PIUCNTREG __preg16(KSEG1 + 0x0B000122) /* PIU Control register (R/W) */ -#define VR4181_PIUCNTREG_PIUSEQEN 0x0004 -#define VR4181_PIUCNTREG_PIUPWR 0x0002 -#define VR4181_PIUCNTREG_PADRST 0x0001 - -#define VR4181_PIUINTREG __preg16(KSEG1 + 0x0B000124) /* PIU Interrupt cause register (R/W) */ -#define VR4181_PIUINTREG_OVP 0x8000 -#define VR4181_PIUINTREG_PADCMD 0x0040 -#define VR4181_PIUINTREG_PADADP 0x0020 -#define VR4181_PIUINTREG_PADPAGE1 0x0010 -#define VR4181_PIUINTREG_PADPAGE0 0x0008 -#define VR4181_PIUINTREG_PADDLOST 0x0004 -#define VR4181_PIUINTREG_PENCHG 0x0001 - -#define VR4181_PIUSIVLREG __preg16(KSEG1 + 0x0B000126) /* PIU Data sampling interval register (R/W) */ -#define VR4181_PIUSTBLREG __preg16(KSEG1 + 0x0B000128) /* PIU A/D converter start delay register (R/W) */ -#define VR4181_PIUCMDREG __preg16(KSEG1 + 0x0B00012A) /* PIU A/D command register (R/W) */ -#define VR4181_PIUASCNREG __preg16(KSEG1 + 0x0B000130) /* PIU A/D port scan register (R/W) */ -#define VR4181_PIUAMSKREG __preg16(KSEG1 + 0x0B000132) /* PIU A/D scan mask register (R/W) */ -#define VR4181_PIUCIVLREG __preg16(KSEG1 + 0x0B00013E) /* PIU Check interval register (R) */ -#define VR4181_PIUPB00REG __preg16(KSEG1 + 0x0B0002A0) /* PIU Page 0 Buffer 0 register (R/W) */ -#define VR4181_PIUPB01REG __preg16(KSEG1 + 0x0B0002A2) /* PIU Page 0 Buffer 1 register (R/W) */ -#define VR4181_PIUPB02REG __preg16(KSEG1 + 0x0B0002A4) /* PIU Page 0 Buffer 2 register (R/W) */ -#define VR4181_PIUPB03REG __preg16(KSEG1 + 0x0B0002A6) /* PIU Page 0 Buffer 3 register (R/W) */ -#define VR4181_PIUPB10REG __preg16(KSEG1 + 0x0B0002A8) /* PIU Page 1 Buffer 0 register (R/W) */ -#define VR4181_PIUPB11REG __preg16(KSEG1 + 0x0B0002AA) /* PIU Page 1 Buffer 1 register (R/W) */ -#define VR4181_PIUPB12REG __preg16(KSEG1 + 0x0B0002AC) /* PIU Page 1 Buffer 2 register (R/W) */ -#define VR4181_PIUPB13REG __preg16(KSEG1 + 0x0B0002AE) /* PIU Page 1 Buffer 3 register (R/W) */ -#define VR4181_PIUAB0REG __preg16(KSEG1 + 0x0B0002B0) /* PIU A/D scan Buffer 0 register (R/W) */ -#define VR4181_PIUAB1REG __preg16(KSEG1 + 0x0B0002B2) /* PIU A/D scan Buffer 1 register (R/W) */ -#define VR4181_PIUAB2REG __preg16(KSEG1 + 0x0B0002B4) /* PIU A/D scan Buffer 2 register (R/W) */ -#define VR4181_PIUAB3REG __preg16(KSEG1 + 0x0B0002B6) /* PIU A/D scan Buffer 3 register (R/W) */ -#define VR4181_PIUPB04REG __preg16(KSEG1 + 0x0B0002BC) /* PIU Page 0 Buffer 4 register (R/W) */ -#define VR4181_PIUPB14REG __preg16(KSEG1 + 0x0B0002BE) /* PIU Page 1 Buffer 4 register (R/W) */ - -// Audio Interface Unit (AIU) -#define VR4181_SODATREG __preg16(KSEG1 + 0x0B000166) /* Speaker Output Data Register (R/W) */ -#define VR4181_SCNTREG __preg16(KSEG1 + 0x0B000168) /* Speaker Output Control Register (R/W) */ -#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Mike Input Data Register (R/W) */ -#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Mike Input Control Register (R/W) */ -#define VR4181_DVALIDREG __preg16(KSEG1 + 0x0B000178) /* Data Valid Register (R/W) */ -#define VR4181_SEQREG __preg16(KSEG1 + 0x0B00017A) /* Sequential Register (R/W) */ -#define VR4181_INTREG __preg16(KSEG1 + 0x0B00017C) /* Interrupt Register (R/W) */ -#define VR4181_SDMADATREG __preg16(KSEG1 + 0x0B000160) /* Speaker DMA Data Register (R/W) */ -#define VR4181_MDMADATREG __preg16(KSEG1 + 0x0B000162) /* Microphone DMA Data Register (R/W) */ -#define VR4181_DAVREF_SETUP __preg16(KSEG1 + 0x0B000164) /* DAC Vref setup register (R/W) */ -#define VR4181_SCNVC_END __preg16(KSEG1 + 0x0B00016E) /* Speaker sample rate control (R/W) */ -#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Microphone Input Data Register (R/W) */ -#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Microphone Input Control Register (R/W) */ -#define VR4181_MCNVC_END __preg16(KSEG1 + 0x0B00017E) /* Microphone sample rate control (R/W) */ - -// Keyboard Interface Unit (KIU) -#define VR4181_KIUDAT0 __preg16(KSEG1 + 0x0B000180) /* KIU Data0 Register (R/W) */ -#define VR4181_KIUDAT1 __preg16(KSEG1 + 0x0B000182) /* KIU Data1 Register (R/W) */ -#define VR4181_KIUDAT2 __preg16(KSEG1 + 0x0B000184) /* KIU Data2 Register (R/W) */ -#define VR4181_KIUDAT3 __preg16(KSEG1 + 0x0B000186) /* KIU Data3 Register (R/W) */ -#define VR4181_KIUDAT4 __preg16(KSEG1 + 0x0B000188) /* KIU Data4 Register (R/W) */ -#define VR4181_KIUDAT5 __preg16(KSEG1 + 0x0B00018A) /* KIU Data5 Register (R/W) */ -#define VR4181_KIUSCANREP __preg16(KSEG1 + 0x0B000190) /* KIU Scan/Repeat Register (R/W) */ -#define VR4181_KIUSCANREP_KEYEN 0x8000 -#define VR4181_KIUSCANREP_SCANSTP 0x0008 -#define VR4181_KIUSCANREP_SCANSTART 0x0004 -#define VR4181_KIUSCANREP_ATSTP 0x0002 -#define VR4181_KIUSCANREP_ATSCAN 0x0001 -#define VR4181_KIUSCANS __preg16(KSEG1 + 0x0B000192) /* KIU Scan Status Register (R) */ -#define VR4181_KIUWKS __preg16(KSEG1 + 0x0B000194) /* KIU Wait Keyscan Stable Register (R/W) */ -#define VR4181_KIUWKI __preg16(KSEG1 + 0x0B000196) /* KIU Wait Keyscan Interval Register (R/W) */ -#define VR4181_KIUINT __preg16(KSEG1 + 0x0B000198) /* KIU Interrupt Register (R/W) */ -#define VR4181_KIUINT_KDATLOST 0x0004 -#define VR4181_KIUINT_KDATRDY 0x0002 -#define VR4181_KIUINT_SCANINT 0x0001 -#define VR4181_KIUDAT6 __preg16(KSEG1 + 0x0B00018C) /* Scan Line 6 Key Data Register (R) */ -#define VR4181_KIUDAT7 __preg16(KSEG1 + 0x0B00018E) /* Scan Line 7 Key Data Register (R) */ - -// CompactFlash Controller -#define VR4181_PCCARDINDEX __preg8(KSEG1 + 0x0B0008E0) /* PC Card Controller Index Register */ -#define VR4181_PCCARDDATA __preg8(KSEG1 + 0x0B0008E1) /* PC Card Controller Data Register */ -#define VR4181_INTSTATREG __preg16(KSEG1 + 0x0B0008F8) /* Interrupt Status Register (R/W) */ -#define VR4181_INTMSKREG __preg16(KSEG1 + 0x0B0008FA) /* Interrupt Mask Register (R/W) */ -#define VR4181_CFG_REG_1 __preg16(KSEG1 + 0x0B0008FE) /* Configuration Register 1 */ - -// LED Control Unit (LED) -#define VR4181_LEDHTSREG __preg16(KSEG1 + 0x0B000240) /* LED H Time Set register (R/W) */ -#define VR4181_LEDLTSREG __preg16(KSEG1 + 0x0B000242) /* LED L Time Set register (R/W) */ -#define VR4181_LEDCNTREG __preg16(KSEG1 + 0x0B000248) /* LED Control register (R/W) */ -#define VR4181_LEDASTCREG __preg16(KSEG1 + 0x0B00024A) /* LED Auto Stop Time Count register (R/W) */ -#define VR4181_LEDINTREG __preg16(KSEG1 + 0x0B00024C) /* LED Interrupt register (R/W) */ - -// Serial Interface Unit (SIU / SIU1 and SIU2) -#define VR4181_SIURB __preg8(KSEG1 + 0x0C000010) /* Receiver Buffer Register (Read) DLAB = 0 (R) */ -#define VR4181_SIUTH __preg8(KSEG1 + 0x0C000010) /* Transmitter Holding Register (Write) DLAB = 0 (W) */ -#define VR4181_SIUDLL __preg8(KSEG1 + 0x0C000010) /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */ -#define VR4181_SIUIE __preg8(KSEG1 + 0x0C000011) /* Interrupt Enable DLAB = 0 (R/W) */ -#define VR4181_SIUDLM __preg8(KSEG1 + 0x0C000011) /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */ -#define VR4181_SIUIID __preg8(KSEG1 + 0x0C000012) /* Interrupt Identification Register (Read) (R) */ -#define VR4181_SIUFC __preg8(KSEG1 + 0x0C000012) /* FIFO Control Register (Write) (W) */ -#define VR4181_SIULC __preg8(KSEG1 + 0x0C000013) /* Line Control Register (R/W) */ -#define VR4181_SIUMC __preg8(KSEG1 + 0x0C000014) /* MODEM Control Register (R/W) */ -#define VR4181_SIULS __preg8(KSEG1 + 0x0C000015) /* Line Status Register (R/W) */ -#define VR4181_SIUMS __preg8(KSEG1 + 0x0C000016) /* MODEM Status Register (R/W) */ -#define VR4181_SIUSC __preg8(KSEG1 + 0x0C000017) /* Scratch Register (R/W) */ -#define VR4181_SIURESET __preg8(KSEG1 + 0x0C000019) /* SIU Reset Register (R/W) */ -#define VR4181_SIUACTMSK __preg8(KSEG1 + 0x0C00001C) /* SIU Activity Mask (R/W) */ -#define VR4181_SIUACTTMR __preg8(KSEG1 + 0x0C00001E) /* SIU Activity Timer (R/W) */ -#define VR4181_SIURB_2 __preg8(KSEG1 + 0x0C000000) /* Receive Buffer Register (Read) (R) */ -#define VR4181_SIUTH_2 __preg8(KSEG1 + 0x0C000000) /* Transmitter Holding Register (Write) (W) */ -#define VR4181_SIUDLL_2 __preg8(KSEG1 + 0x0C000000) /* Divisor Latch (Least Significant Byte) (R/W) */ -#define VR4181_SIUIE_2 __preg8(KSEG1 + 0x0C000001) /* Interrupt Enable (DLAB = 0) (R/W) */ -#define VR4181_SIUDLM_2 __preg8(KSEG1 + 0x0C000001) /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */ -#define VR4181_SIUIID_2 __preg8(KSEG1 + 0x0C000002) /* Interrupt Identification Register (Read) (R) */ -#define VR4181_SIUFC_2 __preg8(KSEG1 + 0x0C000002) /* FIFO Control Register (Write) (W) */ -#define VR4181_SIULC_2 __preg8(KSEG1 + 0x0C000003) /* Line Control Register (R/W) */ -#define VR4181_SIUMC_2 __preg8(KSEG1 + 0x0C000004) /* Modem Control Register (R/W) */ -#define VR4181_SIULS_2 __preg8(KSEG1 + 0x0C000005) /* Line Status Register (R/W) */ -#define VR4181_SIUMS_2 __preg8(KSEG1 + 0x0C000006) /* Modem Status Register (R/W) */ -#define VR4181_SIUSC_2 __preg8(KSEG1 + 0x0C000007) /* Scratch Register (R/W) */ -#define VR4181_SIUIRSEL_2 __preg8(KSEG1 + 0x0C000008) /* SIU IrDA Selectot (R/W) */ -#define VR4181_SIURESET_2 __preg8(KSEG1 + 0x0C000009) /* SIU Reset Register (R/W) */ -#define VR4181_SIUCSEL_2 __preg8(KSEG1 + 0x0C00000A) /* IrDA Echo-back Control (R/W) */ -#define VR4181_SIUACTMSK_2 __preg8(KSEG1 + 0x0C00000C) /* SIU Activity Mask Register (R/W) */ -#define VR4181_SIUACTTMR_2 __preg8(KSEG1 + 0x0C00000E) /* SIU Activity Timer Register (R/W) */ - - -// USB Module -#define VR4181_USBINFIFO __preg16(KSEG1 + 0x0B000780) /* USB Bulk Input FIFO (Bulk In End Point) (W) */ -#define VR4181_USBOUTFIFO __preg16(KSEG1 + 0x0B000782) /* USB Bulk Output FIFO (Bulk Out End Point) (R) */ -#define VR4181_USBCTLFIFO __preg16(KSEG1 + 0x0B000784) /* USB Control FIFO (Control End Point) (W) */ -#define VR4181_USBSTAT __preg16(KSEG1 + 0x0B000786) /* Interrupt Status Register (R/W) */ -#define VR4181_USBINTMSK __preg16(KSEG1 + 0x0B000788) /* Interrupt Mask Register (R/W) */ -#define VR4181_USBCTLREG __preg16(KSEG1 + 0x0B00078A) /* Control Register (R/W) */ -#define VR4181_USBSTPREG __preg16(KSEG1 + 0x0B00078C) /* USB Transfer Stop Register (R/W) */ - -// LCD Controller -#define VR4181_HRTOTALREG __preg16(KSEG1 + 0x0A000400) /* Horizontal total Register (R/W) */ -#define VR4181_HRVISIBREG __preg16(KSEG1 + 0x0A000402) /* Horizontal Visible Register (R/W) */ -#define VR4181_LDCLKSTREG __preg16(KSEG1 + 0x0A000404) /* Load clock start Register (R/W) */ -#define VR4181_LDCLKNDREG __preg16(KSEG1 + 0x0A000406) /* Load clock end Register (R/W) */ -#define VR4181_VRTOTALREG __preg16(KSEG1 + 0x0A000408) /* Vertical Total Register (R/W) */ -#define VR4181_VRVISIBREG __preg16(KSEG1 + 0x0A00040A) /* Vertical Visible Register (R/W) */ -#define VR4181_FVSTARTREG __preg16(KSEG1 + 0x0A00040C) /* FLM vertical start Register (R/W) */ -#define VR4181_FVENDREG __preg16(KSEG1 + 0x0A00040E) /* FLM vertical end Register (R/W) */ -#define VR4181_LCDCTRLREG __preg16(KSEG1 + 0x0A000410) /* LCD control Register (R/W) */ -#define VR4181_LCDINRQREG __preg16(KSEG1 + 0x0A000412) /* LCD Interrupt request Register (R/W) */ -#define VR4181_LCDCFGREG0 __preg16(KSEG1 + 0x0A000414) /* LCD Configuration Register 0 (R/W) */ -#define VR4181_LCDCFGREG1 __preg16(KSEG1 + 0x0A000416) /* LCD Configuration Register 1 (R/W) */ -#define VR4181_FBSTAD1REG __preg16(KSEG1 + 0x0A000418) /* Frame Buffer Start Address 1 Register (R/W) */ -#define VR4181_FBSTAD2REG __preg16(KSEG1 + 0x0A00041A) /* Frame Buffer Start Address 2 Register (R/W) */ -#define VR4181_FBNDAD1REG __preg16(KSEG1 + 0x0A000420) /* Frame Buffer End Address 1 Register (R/W) */ -#define VR4181_FBNDAD2REG __preg16(KSEG1 + 0x0A000422) /* Frame Buffer End Address 2 register (R/W) */ -#define VR4181_FHSTARTREG __preg16(KSEG1 + 0x0A000424) /* FLM horizontal Start Register (R/W) */ -#define VR4181_FHENDREG __preg16(KSEG1 + 0x0A000426) /* FLM horizontal End Register (R/W) */ -#define VR4181_PWRCONREG1 __preg16(KSEG1 + 0x0A000430) /* Power Control register 1 (R/W) */ -#define VR4181_PWRCONREG2 __preg16(KSEG1 + 0x0A000432) /* Power Control register 2 (R/W) */ -#define VR4181_LCDIMSKREG __preg16(KSEG1 + 0x0A000434) /* LCD Interrupt Mask register (R/W) */ -#define VR4181_CPINDCTREG __preg16(KSEG1 + 0x0A00047E) /* Color palette Index and control Register (R/W) */ -#define VR4181_CPALDATREG __preg32(KSEG1 + 0x0A000480) /* Color palette data register (32bits Register) (R/W) */ - -// physical address spaces -#define VR4181_LCD 0x0a000000 -#define VR4181_INTERNAL_IO_2 0x0b000000 -#define VR4181_INTERNAL_IO_1 0x0c000000 -#define VR4181_ISA_MEM 0x10000000 -#define VR4181_ISA_IO 0x14000000 -#define VR4181_ROM 0x18000000 - -// This is the base address for IO port decoding to which the 16 bit IO port address -// is added. Defining it to 0 will usually cause a kernel oops any time port IO is -// attempted, which can be handy for turning up parts of the kernel that make -// incorrect architecture assumptions (by assuming that everything acts like a PC), -// but we need it correctly defined to use the PCMCIA/CF controller: -#define VR4181_PORT_BASE (KSEG1 + VR4181_ISA_IO) -#define VR4181_ISAMEM_BASE (KSEG1 + VR4181_ISA_MEM) - -#endif /* __ASM_VR4181_VR4181_H */ From bprasad@CS.Arizona.EDU Fri Jun 3 06:19:52 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jun 2005 06:20:11 +0100 (BST) Received: from optima.cs.arizona.edu ([IPv6:::ffff:192.12.69.5]:64264 "EHLO optima.cs.arizona.edu") by linux-mips.org with ESMTP id ; Fri, 3 Jun 2005 06:19:52 +0100 Received: from lectura.CS.Arizona.EDU (lectura.cs.arizona.edu [192.12.69.186]) by optima.cs.arizona.edu (8.13.3/8.13.3) with ESMTP id j535JiUZ064250 for ; Thu, 2 Jun 2005 22:19:45 -0700 (MST) (envelope-from bprasad@CS.Arizona.EDU) Date: Thu, 2 Jun 2005 22:19:44 -0700 (MST) From: Prasad Venkata Boddupalli To: linux-mips@linux-mips.org Subject: Reg checksum computation Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8041 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bprasad@CS.Arizona.EDU Precedence: bulk X-list: linux-mips Hi, this regards the function 'csum_partial' that is in the file linux/arch/mips/lib-64/csum_partial.S. Towards the end, we label maybe_end_cruft: andi ta2, a1, 0x3 and then small_memcpy: ... The comments for small_csumcpy says: 'unknown src alignment and < 8 bytes to go'. But as I see the checksum computation for buffers containing fewer than 8 bytes is taken care at the beginning of the 'csum_partial' function. So, what purpose is it serving at the end of 'csum_partial' ? Can someone please clarify ? thank you, Prasad ----------------------------------------------------------------------------- /* * a0: source address * a1: length of the area to checksum * a2: partial checksum */ #define src a0 #define sum v0 .text .set noreorder /* unknown src alignment and < 8 bytes to go */ small_csumcpy: move a1, ta2 andi ta0, a1, 4 beqz ta0, 1f andi ta0, a1, 2 /* Still a full word to go */ ulw ta1, (src) daddiu src, 4 ADDC(sum, ta1) 1: move ta1, zero beqz ta0, 1f andi ta0, a1, 1 /* Still a halfword to go */ ulhu ta1, (src) daddiu src, 2 1: beqz ta0, 1f sll ta1, ta1, 16 lbu ta2, (src) nop #ifdef __MIPSEB__ sll ta2, ta2, 8 #endif or ta1, ta2 1: ADDC(sum, ta1) /* fold checksum */ sll v1, sum, 16 addu sum, v1 sltu v1, sum, v1 srl sum, sum, 16 addu sum, v1 /* odd buffer alignment? */ beqz t3, 1f nop sll v1, sum, 8 srl sum, sum, 8 or sum, v1 andi sum, 0xffff 1: .set reorder /* Add the passed partial csum. */ ADDC(sum, a2) jr ra .set noreorder /* ------------------------------------------------------------------------- */ .align 5 LEAF(csum_partial) move sum, zero move t3, zero sltiu t8, a1, 0x8 bnez t8, small_csumcpy /* < 8 bytes to copy */ move ta2, a1 beqz a1, out andi t3, src, 0x1 /* odd buffer? */ hword_align: beqz t3, word_align andi t8, src, 0x2 lbu ta0, (src) dsubu a1, a1, 0x1 #ifdef __MIPSEL__ sll ta0, ta0, 8 #endif ADDC(sum, ta0) daddu src, src, 0x1 andi t8, src, 0x2 word_align: beqz t8, dword_align sltiu t8, a1, 56 lhu ta0, (src) dsubu a1, a1, 0x2 ADDC(sum, ta0) sltiu t8, a1, 56 daddu src, src, 0x2 dword_align: bnez t8, do_end_words move t8, a1 andi t8, src, 0x4 beqz t8, qword_align andi t8, src, 0x8 lw ta0, 0x00(src) dsubu a1, a1, 0x4 ADDC(sum, ta0) daddu src, src, 0x4 andi t8, src, 0x8 qword_align: beqz t8, oword_align andi t8, src, 0x10 lw ta0, 0x00(src) lw ta1, 0x04(src) dsubu a1, a1, 0x8 ADDC(sum, ta0) ADDC(sum, ta1) daddu src, src, 0x8 andi t8, src, 0x10 oword_align: beqz t8, begin_movement dsrl t8, a1, 0x7 lw ta3, 0x08(src) lw t0, 0x0c(src) lw ta0, 0x00(src) lw ta1, 0x04(src) ADDC(sum, ta3) ADDC(sum, t0) ADDC(sum, ta0) ADDC(sum, ta1) dsubu a1, a1, 0x10 daddu src, src, 0x10 dsrl t8, a1, 0x7 begin_movement: beqz t8, 1f andi ta2, a1, 0x40 move_128bytes: CSUM_BIGCHUNK(src, 0x00, sum, ta0, ta1, ta3, t0) CSUM_BIGCHUNK(src, 0x20, sum, ta0, ta1, ta3, t0) CSUM_BIGCHUNK(src, 0x40, sum, ta0, ta1, ta3, t0) CSUM_BIGCHUNK(src, 0x60, sum, ta0, ta1, ta3, t0) dsubu t8, t8, 0x01 bnez t8, move_128bytes daddu src, src, 0x80 1: beqz ta2, 1f andi ta2, a1, 0x20 move_64bytes: CSUM_BIGCHUNK(src, 0x00, sum, ta0, ta1, ta3, t0) CSUM_BIGCHUNK(src, 0x20, sum, ta0, ta1, ta3, t0) daddu src, src, 0x40 1: beqz ta2, do_end_words andi t8, a1, 0x1c move_32bytes: CSUM_BIGCHUNK(src, 0x00, sum, ta0, ta1, ta3, t0) andi t8, a1, 0x1c daddu src, src, 0x20 do_end_words: beqz t8, maybe_end_cruft dsrl t8, t8, 0x2 end_words: lw ta0, (src) dsubu t8, t8, 0x1 ADDC(sum, ta0) bnez t8, end_words daddu src, src, 0x4 maybe_end_cruft: andi ta2, a1, 0x3 small_memcpy: j small_csumcpy; move a1, ta2 /* XXX ??? */ beqz t2, out move a1, ta2 end_bytes: lb ta0, (src) dsubu a1, a1, 0x1 bnez a2, end_bytes daddu src, src, 0x1 out: jr ra move v0, sum END(csum_partial) From mile.davidovic@micronasnit.com Fri Jun 3 08:15:16 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jun 2005 08:15:36 +0100 (BST) Received: from krt.tmd.ns.ac.yu ([IPv6:::ffff:147.91.177.65]:12691 "EHLO krt.neobee.net") by linux-mips.org with ESMTP id ; Fri, 3 Jun 2005 08:15:16 +0100 Received: from localhost (localhost [127.0.0.1]) by krt.neobee.net (8.12.7/8.12.7/SuSE Linux 0.6) with ESMTP id j538PjjX022032 for ; Fri, 3 Jun 2005 10:25:45 +0200 Received: from krt.neobee.net ([127.0.0.1]) by localhost (krt.neobee.net [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 21494-08 for ; Fri, 3 Jun 2005 10:25:45 +0200 (CEST) Received: from davidovic ([192.168.0.89]) by krt.neobee.net (8.12.7/8.12.7/SuSE Linux 0.6) with ESMTP id j538Pgb4022024 for ; Fri, 3 Jun 2005 10:25:42 +0200 Message-Id: <200506030825.j538Pgb4022024@krt.neobee.net> Reply-To: From: "Mile Davidovic" To: "'Linux/MIPS Development'" Subject: MIPS 4KECr2 trouble again Date: Fri, 3 Jun 2005 09:13:53 +0200 Organization: MicronasNIT MIME-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-2" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Office Outlook, Build 11.0.6353 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2527 Thread-Index: AcVoC8r8U0jk8QAGTjm57JmkG2xTNw== X-Virus-Scanned: by amavisd-new at krt.neobee.net Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8042 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mile.davidovic@micronasnit.com Precedence: bulk X-list: linux-mips Hello all I finaly pass all hw problems and problems with external int. controller but I stuck on next: Linux version 2.6.12-rc3-md (davidovic@rhel.micronasnit.com) (gcc version 3.4.2) #591 Thu Jun 2 17:05:44 CEST 2005 CPU revision is: 00019064 Determined physical RAM map: memory: 04000000 @ 00000000 (usable) Built 1 zonelists Kernel command line: rootfstype=ramfs console=ttyS0,115200 Primary instruction cache 16kB, physically tagged, 4-way, linesize 16 bytes. Primary data cache 8kB, 2-way, linesize 16 bytes. Synthesized TLB refill handler (20 instructions). Synthesized TLB load handler fastpath (32 instructions). Synthesized TLB store handler fastpath (32 instructions). Synthesized TLB modify handler fastpath (31 instructions). PID hash table entries: 512 (order: 9, 8192 bytes) Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 63216k/65536k available (1029k kernel code, 2284k reserved, 158k data, 400k init, 0k highmem) Calibrating delay loop... 808.96 BogoMIPS (lpj=404480) Mount-cache hash table entries: 512 Checking for 'wait' instruction... available. Linux NoNET1.0 for Linux 2.6 Micronas VGCA on-chip UART io scheduler noop registered RAMDISK driver initialized: 1 RAM disks of 4096K size 1024 blocksize loop: loaded (max 8 devices) Freeing unused kernel memory: 400k freed Warning: unable to open an initial console.err = -6 Kernel panic - not syncing: Attempted to kill init! This is my initramfs_list: dir /dev 0755 0 0 nod /dev/console 0644 0 0 c 5 1 nod /dev/ttyS0 0622 0 0 c 5 1 dir /etc 0755 0 0 dir /etc/init.d 0755 0 0 dir /tmp 0755 0 0 dir /var 0755 0 0 dir /proc 0755 0 0 dir /mnt 0755 0 0 dir /home 0755 0 0 dir /root 755 0 0 dir /lib 0755 0 0 dir /lost+found 0755 0 0 dir /sbin 0755 0 0 file /init /home/davidovic/vgclinux/klibc-1.0/kinit/kinit 0755 0 0 file /bin/kinit /home/davidovic/vgclinux/klibc-1.0/kinit/kinit 0755 0 0 In errno-base.h err = -6 means ENXIO, no such device or address. I tried with some googling and I found similar problem with arm-linux (see http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2005-April/028467.h tml). Is it problem with creating initramfs_data.cpio because I created this file: cd usr ./gen_init_cpio initramfs_list > initramfs_data.cpio cd .. make I am pretty shure init process is loaded on 0x004000b0 (this is ok, I dumped kinit) but I can not figure why is killed, except that in fist couple of lines kinit also try to open /dev/console. Any help or comment will be most welcomed. Here is context of my .config file: # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc3 # Thu Jun 2 17:01:12 2005 # CONFIG_MIPS=y # # Code maturity level options # # CONFIG_EXPERIMENTAL is not set CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="-md" CONFIG_SWAP=y # CONFIG_SYSVIPC is not set # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set # CONFIG_HOTPLUG is not set # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y # CONFIG_BASE_FULL is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SHMEM is not set CONFIG_CC_ALIGN_FUNCTIONS=0 CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=1 # # Loadable module support # # CONFIG_MODULES is not set # # Machine selection # # CONFIG_MIPS_MTX1 is not set # CONFIG_MIPS_BOSPORUS is not set # CONFIG_MIPS_PB1000 is not set # CONFIG_MIPS_PB1100 is not set # CONFIG_MIPS_PB1500 is not set # CONFIG_MIPS_PB1550 is not set # CONFIG_MIPS_PB1200 is not set # CONFIG_MIPS_DB1000 is not set # CONFIG_MIPS_DB1100 is not set # CONFIG_MIPS_DB1500 is not set # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set # CONFIG_MIPS_ITE8172 is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set CONFIG_MIPS_VGCA_EVA=y # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_MOMENCO_OCELOT_3 is not set # CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_G is not set # CONFIG_MIPS_XXS1500 is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_VGCA_HW_TOGGLE_BUG is not set # CONFIG_VGCA_HW_RELOAD_BUG is not set CONFIG_VGCA_UNCACHED=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_SWAP_IO_SPACE=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y # # Kernel type # CONFIG_MIPS32=y # CONFIG_MIPS64 is not set # CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y # CONFIG_64BIT_PHYS_ADDR is not set CONFIG_CPU_ADVANCED=y CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_LLDSCD is not set # CONFIG_CPU_HAS_WB is not set CONFIG_CPU_HAS_SYNC=y # CONFIG_PREEMPT is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_MMU=y # # PCCARD (PCMCIA/CardBus) support # # CONFIG_PCCARD is not set # # PCI Hotplug Support # # # Executable file formats # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y # # Device Drivers # # # Generic Driver Options # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # CONFIG_DEBUG_DRIVER is not set # # Memory Technology Devices (MTD) # # CONFIG_MTD is not set # # Parallel port support # # CONFIG_PARPORT is not set # # Plug and Play support # # # Block devices # # CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_INITRD is not set CONFIG_INITRAMFS_SOURCE="/home/davidovic/vgclinux/linux/linux-2.6.12/usr/ini tramfs_data.cpio" CONFIG_INITRAMFS_ROOT_UID=0 CONFIG_INITRAMFS_ROOT_GID=0 # CONFIG_LBD is not set # CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y # CONFIG_IOSCHED_AS is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set # # ATA/ATAPI/MFM/RLL support # # CONFIG_IDE is not set # # SCSI device support # # CONFIG_SCSI is not set # # Multi-device support (RAID and LVM) # # CONFIG_MD is not set # # Fusion MPT device support # # # IEEE 1394 (FireWire) support # # # I2O device support # # # Networking support # # CONFIG_NET is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem # # # Telephony Support # # CONFIG_PHONE is not set # # Input device support # CONFIG_INPUT=y # # Userland interfaces # # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set # # Hardware I/O ports # # CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set CONFIG_SOUND_GAMEPORT=y # # Character devices # # CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set # # Serial drivers # # CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # CONFIG_SERIAL_VGCA=y CONFIG_SERIAL_VGCA_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_UNIX98_PTYS is not set # CONFIG_LEGACY_PTYS is not set # # IPMI # # CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set # CONFIG_RTC is not set # CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # # Ftape, the floppy tape device driver # # CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # # TPM devices # # # I2C support # # CONFIG_I2C is not set # # Dallas's 1-wire bus # # CONFIG_W1 is not set # # Misc devices # # # Multimedia devices # # CONFIG_VIDEO_DEV is not set # # Digital Video Broadcasting Devices # # # Graphics support # # CONFIG_FB is not set # # Sound # # CONFIG_SOUND is not set # # USB support # # CONFIG_USB_ARCH_HAS_HCD is not set # CONFIG_USB_ARCH_HAS_OHCI is not set # # USB Gadget Support # # CONFIG_USB_GADGET is not set # # MMC/SD Card support # # CONFIG_MMC is not set # # InfiniBand support # # CONFIG_INFINIBAND is not set # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # # XFS support # # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set CONFIG_ROMFS_FS=y # CONFIG_QUOTA is not set # CONFIG_DNOTIFY is not set CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # # CONFIG_MSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # # Pseudo filesystems # CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_XATTR=y # CONFIG_TMPFS_SECURITY is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y # # Miscellaneous filesystems # # CONFIG_HFSPLUS_FS is not set # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y # # Native Language Support # # CONFIG_NLS is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set CONFIG_DEBUG_KERNEL=y CONFIG_MAGIC_SYSRQ=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_SCHEDSTATS is not set # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_FS is not set CONFIG_CROSSCOMPILE=y CONFIG_CMDLINE="rootfstype=ramfs console=ttyS0,115200" # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_KGDB is not set # CONFIG_RUNTIME_DEBUG is not set # CONFIG_MIPS_UNCACHED is not set # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # # Cryptographic options # # CONFIG_CRYPTO is not set # # Hardware crypto devices # # # Library routines # # CONFIG_CRC_CCITT is not set # CONFIG_CRC32 is not set # CONFIG_LIBCRC32C is not set CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y From ralf@linux-mips.org Fri Jun 3 10:23:40 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jun 2005 10:23:55 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:43802 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Fri, 3 Jun 2005 10:23:40 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j539M5Sd008819 for ; Fri, 3 Jun 2005 10:22:05 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j539M5rD008818 for linux-mips@linux-mips.org; Fri, 3 Jun 2005 10:22:05 +0100 Date: Fri, 3 Jun 2005 10:22:05 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: Re: CVS Update@linux-mips.org: linux Message-ID: <20050603092205.GA4573@linux-mips.org> References: <20050603022113Z8226140-1340+8064@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20050603022113Z8226140-1340+8064@linux-mips.org> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8043 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jun 03, 2005 at 03:21:13AM +0100, ths@linux-mips.org wrote: > Log message: > Fix R4[04]00 hazards breakage. > > diff -urN linux/arch/mips/mm/tlbex-r4k.S linux/arch/mips/mm/tlbex-r4k.S > --- linux/arch/mips/mm/Attic/tlbex-r4k.S 2004/11/25 22:18:38 1.2.2.19 > +++ linux/arch/mips/mm/Attic/tlbex-r4k.S 2005/06/03 02:21:06 1.2.2.20 > @@ -186,6 +186,7 @@ > P_MTC0 k1, CP0_ENTRYLO1 # load it > mtc0_tlbw_hazard > tlbwr # write random tlb entry > + nop > tlbw_eret_hazard I did previously object to a similar patch - why not fix tlbw_eret_hazard instead. Ralf From ths@networkno.de Fri Jun 3 11:21:49 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jun 2005 11:22:05 +0100 (BST) Received: from mx01.qsc.de ([IPv6:::ffff:213.148.129.14]:47255 "EHLO mx01.qsc.de") by linux-mips.org with ESMTP id ; Fri, 3 Jun 2005 11:21:49 +0100 Received: from port-195-158-167-89.dynamic.qsc.de ([195.158.167.89] helo=hattusa.textio) by mx01.qsc.de with esmtp (Exim 3.35 #1) id 1De9J6-0000ck-00; Fri, 03 Jun 2005 12:21:40 +0200 Received: from ths by hattusa.textio with local (Exim 4.50) id 1De9J6-00024Y-L0; Fri, 03 Jun 2005 12:21:40 +0200 Date: Fri, 3 Jun 2005 12:21:40 +0200 To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Re: CVS Update@linux-mips.org: linux Message-ID: <20050603102140.GA1610@hattusa.textio> References: <20050603022113Z8226140-1340+8064@linux-mips.org> <20050603092205.GA4573@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20050603092205.GA4573@linux-mips.org> User-Agent: Mutt/1.5.9i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8044 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > On Fri, Jun 03, 2005 at 03:21:13AM +0100, ths@linux-mips.org wrote: > > > Log message: > > Fix R4[04]00 hazards breakage. > > > > diff -urN linux/arch/mips/mm/tlbex-r4k.S linux/arch/mips/mm/tlbex-r4k.S > > --- linux/arch/mips/mm/Attic/tlbex-r4k.S 2004/11/25 22:18:38 1.2.2.19 > > +++ linux/arch/mips/mm/Attic/tlbex-r4k.S 2005/06/03 02:21:06 1.2.2.20 > > @@ -186,6 +186,7 @@ > > P_MTC0 k1, CP0_ENTRYLO1 # load it > > mtc0_tlbw_hazard > > tlbwr # write random tlb entry > > + nop > > tlbw_eret_hazard > > I did previously object to a similar patch I didn't know that, IIRC a similiar patch went in 2.6 before the synthesized TLB handlers were done. > - why not fix tlbw_eret_hazard instead. Like this? Thiemo Index: arch/mips/mm/tlbex-r4k.S =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/Attic/tlbex-r4k.S,v retrieving revision 1.2.2.20 diff -u -p -r1.2.2.20 tlbex-r4k.S --- arch/mips/mm/tlbex-r4k.S 3 Jun 2005 02:21:06 -0000 1.2.2.20 +++ arch/mips/mm/tlbex-r4k.S 3 Jun 2005 10:16:28 -0000 @@ -186,7 +186,6 @@ P_MTC0 k1, CP0_ENTRYLO1 # load it mtc0_tlbw_hazard tlbwr # write random tlb entry - nop tlbw_eret_hazard eret END(except_vec0_r4000) @@ -468,7 +467,6 @@ invalid_tlbl: PTE_RELOAD(k1, k0) mtc0_tlbw_hazard tlbwi - nop tlbw_eret_hazard .set mips3 eret @@ -493,7 +491,6 @@ nopage_tlbl: PTE_RELOAD(k1, k0) mtc0_tlbw_hazard tlbwi - nop tlbw_eret_hazard .set mips3 eret @@ -523,7 +520,6 @@ nopage_tlbs: PTE_RELOAD(k1, k0) mtc0_tlbw_hazard tlbwi - nop tlbw_eret_hazard .set mips3 eret Index: arch/mips64/mm/tlbex-r4k.S =================================================================== RCS file: /home/cvs/linux/arch/mips64/mm/Attic/tlbex-r4k.S,v retrieving revision 1.1.2.20 diff -u -p -r1.1.2.20 tlbex-r4k.S --- arch/mips64/mm/tlbex-r4k.S 3 Jun 2005 02:21:07 -0000 1.1.2.20 +++ arch/mips64/mm/tlbex-r4k.S 3 Jun 2005 10:16:28 -0000 @@ -125,6 +125,33 @@ LEAF(except_vec1_r4k) nop END(except_vec1_r4k) + __FINIT + + .align 5 +LEAF(handle_vec1_r4k) + .set noat + LOAD_PTE2 k1 k0 9f + ld k0, 0(k1) # get even pte + ld k1, 8(k1) # get odd pte + PTE_RELOAD k0 k1 + mtc0_tlbw_hazard + tlbwr + tlbw_eret_hazard + eret + +9: # handle the vmalloc range + LOAD_KPTE2 k1 k0 invalid_vmalloc_address + ld k0, 0(k1) # get even pte + ld k1, 8(k1) # get odd pte + PTE_RELOAD k0 k1 + mtc0_tlbw_hazard + tlbwr + tlbw_eret_hazard + eret +END(handle_vec1_r4k) + + __INIT + LEAF(except_vec1_sb1) #if BCM1250_M3_WAR dmfc0 k0, CP0_BADVADDR @@ -134,18 +161,17 @@ LEAF(except_vec1_sb1) bnez k0, 1f #endif .set noat - dla k0, handle_vec1_r4k + dla k0, handle_vec1_sb1 jr k0 nop 1: eret - nop END(except_vec1_sb1) __FINIT .align 5 -LEAF(handle_vec1_r4k) +LEAF(handle_vec1_sb1) .set noat LOAD_PTE2 k1 k0 9f ld k0, 0(k1) # get even pte @@ -153,7 +179,6 @@ LEAF(handle_vec1_r4k) PTE_RELOAD k0 k1 mtc0_tlbw_hazard tlbwr -1: tlbw_eret_hazard eret 9: # handle the vmalloc range @@ -163,10 +188,8 @@ LEAF(handle_vec1_r4k) PTE_RELOAD k0 k1 mtc0_tlbw_hazard tlbwr - nop -1: tlbw_eret_hazard eret -END(handle_vec1_r4k) +END(handle_vec1_sb1) __INIT @@ -194,7 +217,6 @@ LEAF(handle_vec1_r10k) PTE_RELOAD k0 k1 mtc0_tlbw_hazard tlbwr - tlbw_eret_hazard eret 9: # handle the vmalloc range @@ -204,7 +226,6 @@ LEAF(handle_vec1_r10k) PTE_RELOAD k0 k1 mtc0_tlbw_hazard tlbwr - tlbw_eret_hazard eret END(handle_vec1_r10k) Index: include/asm-mips/hazards.h =================================================================== RCS file: /home/cvs/linux/include/asm-mips/hazards.h,v retrieving revision 1.1.2.3 diff -u -p -r1.1.2.3 hazards.h --- include/asm-mips/hazards.h 3 Jun 2005 02:21:07 -0000 1.1.2.3 +++ include/asm-mips/hazards.h 3 Jun 2005 10:16:28 -0000 @@ -46,6 +46,7 @@ #define mtc0_tlbw_hazard \ b . + 8 #define tlbw_eret_hazard + nop #endif /* Index: include/asm-mips64/hazards.h =================================================================== RCS file: /home/cvs/linux/include/asm-mips64/Attic/hazards.h,v retrieving revision 1.1.2.3 diff -u -p -r1.1.2.3 hazards.h --- include/asm-mips64/hazards.h 3 Jun 2005 02:21:07 -0000 1.1.2.3 +++ include/asm-mips64/hazards.h 3 Jun 2005 10:16:28 -0000 @@ -46,6 +46,7 @@ #define mtc0_tlbw_hazard \ b . + 8 #define tlbw_eret_hazard + nop #endif /* From ralf@linux-mips.org Fri Jun 3 11:57:05 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jun 2005 11:57:19 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:5646 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Fri, 3 Jun 2005 11:57:05 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j53AtTks012693; Fri, 3 Jun 2005 11:55:29 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j53AtSn1012692; Fri, 3 Jun 2005 11:55:28 +0100 Date: Fri, 3 Jun 2005 11:55:28 +0100 From: Ralf Baechle To: Thiemo Seufer Cc: linux-mips@linux-mips.org Subject: Re: CVS Update@linux-mips.org: linux Message-ID: <20050603105528.GA11061@linux-mips.org> References: <20050603022113Z8226140-1340+8064@linux-mips.org> <20050603092205.GA4573@linux-mips.org> <20050603102140.GA1610@hattusa.textio> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20050603102140.GA1610@hattusa.textio> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8045 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jun 03, 2005 at 12:21:40PM +0200, Thiemo Seufer wrote: > > I did previously object to a similar patch > > I didn't know that, IIRC a similiar patch went in 2.6 before the synthesized > TLB handlers were done. > > > - why not fix tlbw_eret_hazard instead. > > Like this? Yes, that seems more like it. Ralf From geert@linux-m68k.org Fri Jun 3 12:12:09 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jun 2005 12:12:26 +0100 (BST) Received: from witte.sonytel.be ([IPv6:::ffff:80.88.33.193]:41135 "EHLO witte.sonytel.be") by linux-mips.org with ESMTP id ; Fri, 3 Jun 2005 12:12:09 +0100 Received: from numbat.sonytel.be (mail.sonytel.be [43.221.60.197]) by witte.sonytel.be (8.12.10/8.12.10) with ESMTP id j53BC4Ee029417; Fri, 3 Jun 2005 13:12:04 +0200 (MEST) Date: Fri, 3 Jun 2005 13:12:03 +0200 (CEST) From: Geert Uytterhoeven To: Thiemo Seufer cc: Ralf Baechle , Linux/MIPS Development Subject: Re: CVS Update@linux-mips.org: linux In-Reply-To: <20050603102140.GA1610@hattusa.textio> Message-ID: References: <20050603022113Z8226140-1340+8064@linux-mips.org> <20050603092205.GA4573@linux-mips.org> <20050603102140.GA1610@hattusa.textio> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8046 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips On Fri, 3 Jun 2005, Thiemo Seufer wrote: > --- include/asm-mips/hazards.h 3 Jun 2005 02:21:07 -0000 1.1.2.3 > +++ include/asm-mips/hazards.h 3 Jun 2005 10:16:28 -0000 > @@ -46,6 +46,7 @@ > #define mtc0_tlbw_hazard \ > b . + 8 > #define tlbw_eret_hazard Missing backslash at end of line? > + nop > #endif > > /* > Index: include/asm-mips64/hazards.h > =================================================================== > RCS file: /home/cvs/linux/include/asm-mips64/Attic/hazards.h,v > retrieving revision 1.1.2.3 > diff -u -p -r1.1.2.3 hazards.h > --- include/asm-mips64/hazards.h 3 Jun 2005 02:21:07 -0000 1.1.2.3 > +++ include/asm-mips64/hazards.h 3 Jun 2005 10:16:28 -0000 > @@ -46,6 +46,7 @@ > #define mtc0_tlbw_hazard \ > b . + 8 > #define tlbw_eret_hazard Missing backslash at end of line? > + nop > #endif Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From ralf@linux-mips.org Fri Jun 3 12:32:36 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jun 2005 12:32:51 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:9240 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Fri, 3 Jun 2005 12:32:36 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j53BUn84014007; Fri, 3 Jun 2005 12:30:49 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j53BUl2R014006; Fri, 3 Jun 2005 12:30:47 +0100 Date: Fri, 3 Jun 2005 12:30:47 +0100 From: Ralf Baechle To: Geert Uytterhoeven Cc: Thiemo Seufer , Linux/MIPS Development Subject: Re: CVS Update@linux-mips.org: linux Message-ID: <20050603113047.GB11061@linux-mips.org> References: <20050603022113Z8226140-1340+8064@linux-mips.org> <20050603092205.GA4573@linux-mips.org> <20050603102140.GA1610@hattusa.textio> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8047 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jun 03, 2005 at 01:12:03PM +0200, Geert Uytterhoeven wrote: > On Fri, 3 Jun 2005, Thiemo Seufer wrote: > > --- include/asm-mips/hazards.h 3 Jun 2005 02:21:07 -0000 1.1.2.3 > > +++ include/asm-mips/hazards.h 3 Jun 2005 10:16:28 -0000 > > @@ -46,6 +46,7 @@ > > #define mtc0_tlbw_hazard \ > > b . + 8 > > #define tlbw_eret_hazard > > Missing backslash at end of line? Some processors have a 0-cycle hazard between a tlb write and eret. Ralf From geert@linux-m68k.org Fri Jun 3 12:37:41 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jun 2005 12:37:57 +0100 (BST) Received: from witte.sonytel.be ([IPv6:::ffff:80.88.33.193]:47800 "EHLO witte.sonytel.be") by linux-mips.org with ESMTP id ; Fri, 3 Jun 2005 12:37:41 +0100 Received: from numbat.sonytel.be (mail.sonytel.be [43.221.60.197]) by witte.sonytel.be (8.12.10/8.12.10) with ESMTP id j53BbeEe000978; Fri, 3 Jun 2005 13:37:40 +0200 (MEST) Date: Fri, 3 Jun 2005 13:37:39 +0200 (CEST) From: Geert Uytterhoeven To: Ralf Baechle cc: Thiemo Seufer , Linux/MIPS Development Subject: Re: CVS Update@linux-mips.org: linux In-Reply-To: <20050603113047.GB11061@linux-mips.org> Message-ID: References: <20050603022113Z8226140-1340+8064@linux-mips.org> <20050603092205.GA4573@linux-mips.org> <20050603102140.GA1610@hattusa.textio> <20050603113047.GB11061@linux-mips.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8048 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips On Fri, 3 Jun 2005, Ralf Baechle wrote: > On Fri, Jun 03, 2005 at 01:12:03PM +0200, Geert Uytterhoeven wrote: > > On Fri, 3 Jun 2005, Thiemo Seufer wrote: > > > --- include/asm-mips/hazards.h 3 Jun 2005 02:21:07 -0000 1.1.2.3 > > > +++ include/asm-mips/hazards.h 3 Jun 2005 10:16:28 -0000 > > > @@ -46,6 +46,7 @@ > > > #define mtc0_tlbw_hazard \ > > > b . + 8 > > > #define tlbw_eret_hazard > > > > Missing backslash at end of line? > > > Some processors have a 0-cycle hazard between a tlb write and eret. I understand. But unless I'm mistaken, the compiler will complain about the lonely `nop' if the preceding line doesn't end with a backslash. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From ralf@linux-mips.org Fri Jun 3 14:09:06 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jun 2005 14:09:21 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:12048 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Fri, 3 Jun 2005 14:09:06 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j53D7OGF025516; Fri, 3 Jun 2005 14:07:24 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j53D7Mnb025515; Fri, 3 Jun 2005 14:07:22 +0100 Date: Fri, 3 Jun 2005 14:07:22 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH 2.6] remove NEC Osprey Message-ID: <20050603130722.GF11061@linux-mips.org> References: <20050603073349.28f1a533.yuasa@hh.iij4u.or.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20050603073349.28f1a533.yuasa@hh.iij4u.or.jp> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8049 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jun 03, 2005 at 07:33:49AM +0900, Yoichi Yuasa wrote: > This patch had removed NEC Opsrey support from v2.6. Thank, applied. I also removed osprey_defconfig. Ralf From yuasa@hh.iij4u.or.jp Fri Jun 3 16:59:53 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jun 2005 17:00:13 +0100 (BST) Received: from mo00.iij4u.or.jp ([IPv6:::ffff:210.130.0.19]:54980 "EHLO mo00.iij4u.or.jp") by linux-mips.org with ESMTP id ; Fri, 3 Jun 2005 16:59:53 +0100 Received: MO(mo00)id j53FxnXr023885; Sat, 4 Jun 2005 00:59:49 +0900 (JST) Received: MDO(mdo01) id j53Fxms7010110; Sat, 4 Jun 2005 00:59:48 +0900 (JST) Received: from stratos (h042.p502.iij4u.or.jp [210.149.246.42]) by mbox.iij4u.or.jp (4U-MR/mbox01) id j53FxlZ2025863 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NOT); Sat, 4 Jun 2005 00:59:48 +0900 (JST) Date: Sat, 4 Jun 2005 00:59:45 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@hh.iij4u.or.jp, linux-mips Subject: [PATCH 2.6] vr41xx: update vr41xx commons Message-Id: <20050604005945.278809f7.yuasa@hh.iij4u.or.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8050 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@hh.iij4u.or.jp Precedence: bulk X-list: linux-mips Hi, This patch had updated vr41xx commons. o Cleaning of include files o add EXPORT_SYMBOL to irq.c diff -urN -X dontdiff a-orig/arch/mips/vr41xx/common/icu.c a/arch/mips/vr41xx/common/icu.c --- a-orig/arch/mips/vr41xx/common/icu.c Fri Jun 3 00:59:04 2005 +++ a/arch/mips/vr41xx/common/icu.c Fri Jun 3 23:56:25 2005 @@ -30,7 +30,6 @@ */ #include #include -#include #include #include #include @@ -39,8 +38,6 @@ #include #include -#include -#include #include static void __iomem *icu1_base; diff -urN -X dontdiff a-orig/arch/mips/vr41xx/common/irq.c a/arch/mips/vr41xx/common/irq.c --- a-orig/arch/mips/vr41xx/common/irq.c Thu Jun 2 23:37:13 2005 +++ a/arch/mips/vr41xx/common/irq.c Fri Jun 3 23:58:17 2005 @@ -18,6 +18,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include +#include #include #include @@ -55,6 +56,8 @@ return retval; } + +EXPORT_SYMBOL_GPL(cascade_irq); asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs) { From ralf@linux-mips.org Mon Jun 6 13:18:37 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Jun 2005 13:18:52 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:25631 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Mon, 6 Jun 2005 13:18:37 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j56CGfd1013326 for ; Mon, 6 Jun 2005 13:16:41 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j56CGegM013325 for linux-mips@linux-mips.org; Mon, 6 Jun 2005 13:16:40 +0100 Date: Mon, 6 Jun 2005 13:16:40 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: Re: CVS Update@linux-mips.org: linux Message-ID: <20050606121640.GB6651@linux-mips.org> References: <20050605035727Z8225003-1340+8177@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20050605035727Z8225003-1340+8177@linux-mips.org> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8051 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Jun 05, 2005 at 04:57:20AM +0100, sjhill@linux-mips.org wrote: > Modified files: > arch/mips : Kconfig > > Log message: > The DbAu1500 board also support big endian. Gee, imagine that. Maybe. In the past our Kconfig rsp. Config.in was not endianess-aware, so I did make a few mistakes when I added that. Ralf From jrc@skylon.demon.co.uk Mon Jun 6 13:20:10 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Jun 2005 13:20:27 +0100 (BST) Received: from anchor-post-36.mail.demon.net ([IPv6:::ffff:194.217.242.86]:60934 "EHLO anchor-post-36.mail.demon.net") by linux-mips.org with ESMTP id ; Mon, 6 Jun 2005 13:20:10 +0100 Received: from pr-webmail-1.demon.net ([194.159.244.51] helo=pr-webmail-1.mail.demon.net) by anchor-post-36.mail.demon.net with esmtp (Exim 4.42) id 1DfGaO-000PVb-JZ; Mon, 06 Jun 2005 12:20:08 +0000 Received: from localhost ([127.0.0.1] helo=web.mail.demon.net) by pr-webmail-1.mail.demon.net with smtp (Exim 4.42) id 1DfGaN-0006EN-Qk; Mon, 06 Jun 2005 13:20:07 +0100 Received: from skylon.demon.co.uk ([194.130.136.219]) by web.mail.demon.net with http; Mon, 06 Jun 2005 13:20:07 +0100 From: jrc@skylon.demon.co.uk To: linux-mips@linux-mips.org Subject: RMI XLR Processor Family support? Date: Mon, 06 Jun 2005 13:20:07 +0100 User-Agent: Demon-WebMail/2.0 MIME-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 7bit Message-Id: <20050606122010Z8225348-1340+8238@linux-mips.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8052 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jrc@skylon.demon.co.uk Precedence: bulk X-list: linux-mips I'm probably jumping the gun as they have only recently been announced but what support is available for the RMI XLR Family of Thread Processors? The RMI web site is http://www.razamicroelectronics.com. The following snippets have been lifted from documents available from that web site: "XLR-enhanced 64-bit MIPS64 ISA" [1]. "an operating system such as Linux requires no software changes to allow it to run as a multi-way SMP operation system on the XLR processor. This allows software engineers to develop code while leveraging the same standard tool chains and operating systems that have been use in the past development efforts" [2]. "ArizonaATX-I is initially enabled by two standard operating systems including 32-bit Linux 2.6 with complete support for the XLR processor. Full source code is available and SMP support is standard. Customers will have early access to RMI's kernel improvements" [3]. -- John Connett [1] "RMI XLR Processor Family Product Brief", Document # PB2001, Raza Microelectronics, Inc.. [2] "XLR Processor Product Overview", Document 2PO001100, Raza Microelectronics, Inc., May 2005. [3] "ArizonaATX-I Evaluation Board Product Brief", Document # PB2005, Raza Microelectronics, Inc.. From ralf@linux-mips.org Mon Jun 6 14:07:51 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Jun 2005 14:08:06 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:53511 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Mon, 6 Jun 2005 14:07:51 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j56D5tgh014982; Mon, 6 Jun 2005 14:05:55 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j56D5t7R014981; Mon, 6 Jun 2005 14:05:55 +0100 Date: Mon, 6 Jun 2005 14:05:55 +0100 From: Ralf Baechle To: jrc@skylon.demon.co.uk Cc: linux-mips@linux-mips.org Subject: Re: RMI XLR Processor Family support? Message-ID: <20050606130555.GD6651@linux-mips.org> References: <20050606122010Z8225348-1340+8238@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20050606122010Z8225348-1340+8238@linux-mips.org> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8053 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 06, 2005 at 01:20:07PM +0100, jrc@skylon.demon.co.uk wrote: > I'm probably jumping the gun as they have only recently been announced > but what support is available for the RMI XLR Family of Thread > Processors? Speaking about the code available on linux-mips.org the answer is: nothing. Ralf From linux@cantastic.de Mon Jun 6 16:56:05 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 06 Jun 2005 16:56:20 +0100 (BST) Received: from moutng.kundenserver.de ([IPv6:::ffff:212.227.126.171]:6394 "EHLO moutng.kundenserver.de") by linux-mips.org with ESMTP id ; Mon, 6 Jun 2005 16:56:04 +0100 Received: from p54A2929F.dip0.t-ipconnect.de [84.162.146.159] (helo=[192.168.178.44]) by mrelayeu.kundenserver.de with ESMTP (Nemesis), id 0MKwh2-1DfJxK2Cy7-0007Gr; Mon, 06 Jun 2005 17:56:02 +0200 Message-ID: <42A47252.2010906@cantastic.de> Date: Mon, 06 Jun 2005 17:57:06 +0200 From: =?ISO-8859-15?Q?Ralf_R=F6sch?= User-Agent: Mozilla Thunderbird 1.0.2 (Windows/20050317) X-Accept-Language: de-DE, de, en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Compiler warnings / linux-2.6 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Provags-ID: kundenserver.de abuse@kundenserver.de login:fe0074b40cafaf3a4e4a4699a3836908 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8054 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux@cantastic.de Precedence: bulk X-list: linux-mips Since a few days I get a lot of compiler warnings: include2/asm/dsp.h: In function `__init_dsp': include2/asm/dsp.h:34: warning: statement with no effect What could I do to prevent these? Thanks Ralf From Hiroshi_DOYU@montavista.co.jp Tue Jun 7 06:56:10 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Jun 2005 06:56:29 +0100 (BST) Received: from sonicwall.montavista.co.jp ([IPv6:::ffff:202.232.97.131]:62961 "EHLO yuubin.montavista.co.jp") by linux-mips.org with ESMTP id ; Tue, 7 Jun 2005 06:56:10 +0100 Received: from localhost.localdomain (oreo.jp.mvista.com [10.200.16.31]) by yuubin.montavista.co.jp (8.12.5/8.12.5) with SMTP id j575u4S5007637; Tue, 7 Jun 2005 14:56:04 +0900 Date: Tue, 7 Jun 2005 14:57:24 +0900 From: Hiroshi DOYU To: Ralf Baechle Cc: linux-mips , Manish Lachwani Subject: [patch 1/1] MIPS 2.6 : minor updates on TX4938(RBHMA4500) Message-Id: <20050607145724.18d61544.Hiroshi_DOYU@montavista.co.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="Multipart=_Tue__7_Jun_2005_14_57_24_+0900_KKDQd=tq+tNPaeRM" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8055 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Hiroshi_DOYU@montavista.co.jp Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --Multipart=_Tue__7_Jun_2005_14_57_24_+0900_KKDQd=tq+tNPaeRM Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Hello, Attached patch includes support of RBHMA4500(TX4938) against latest mips CVS. This patch was originally Manish's work but it has not been incorporated in CVS yet. So I have just tweaked it against latest CVS and I confirmed that this worked correctly on RBHMA4500. If you have any questions, please let me know. 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--Multipart=_Tue__7_Jun_2005_14_57_24_+0900_KKDQd=tq+tNPaeRM-- From ralf@linux-mips.org Tue Jun 7 12:39:35 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Jun 2005 12:39:51 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:62985 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Tue, 7 Jun 2005 12:39:35 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j57BbVKL016081; Tue, 7 Jun 2005 12:37:31 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j57BbVul016080; Tue, 7 Jun 2005 12:37:31 +0100 Date: Tue, 7 Jun 2005 12:37:31 +0100 From: Ralf Baechle To: Ralf =?iso-8859-1?Q?R=F6sch?= Cc: linux-mips@linux-mips.org Subject: Re: Compiler warnings / linux-2.6 Message-ID: <20050607113731.GB4654@linux-mips.org> References: <42A47252.2010906@cantastic.de> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <42A47252.2010906@cantastic.de> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8056 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 06, 2005 at 05:57:06PM +0200, Ralf Rösch wrote: > Since a few days I get a lot of compiler warnings: > > include2/asm/dsp.h: In function `__init_dsp': > include2/asm/dsp.h:34: warning: statement with no effect > > What could I do to prevent these? Reporting them. A fairly obvious and harmless problem. I'm surprised my compiler (gcc 3.4) doesn't throw these warnings. Ralf Index: include/asm-mips/mipsregs.h =================================================================== RCS file: /home/cvs/linux/include/asm-mips/mipsregs.h,v retrieving revision 1.73 diff -u -r1.73 mipsregs.h --- include/asm-mips/mipsregs.h 31 May 2005 11:49:19 -0000 1.73 +++ include/asm-mips/mipsregs.h 7 Jun 2005 11:39:10 -0000 @@ -1010,8 +1010,6 @@ #define wrdsp(val, mask) \ do { \ - unsigned int __res; \ - \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ @@ -1021,7 +1019,6 @@ " .set pop \n" \ : \ : "r" (val), "i" (mask)); \ - __res; \ } while (0) #if 0 /* Need DSP ASE capable assembler ... */ From spodstavin@ru.mvista.com Tue Jun 7 13:41:33 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 07 Jun 2005 13:42:07 +0100 (BST) Received: from RT-soft-1.Moscow.itn.ru ([IPv6:::ffff:80.240.96.90]:61618 "EHLO buildserver.ru.mvista.com") by linux-mips.org with ESMTP id ; Tue, 7 Jun 2005 13:41:30 +0100 Received: from 192.168.1.226 ([10.150.0.9]) by buildserver.ru.mvista.com (8.11.6/8.11.6) with ESMTP id j57CfDt18283; Tue, 7 Jun 2005 17:41:13 +0500 Subject: [PATCH] A video driver for Lynx3DM on NEC VR5701-SG2 Board. From: Sergey Podstavin Reply-To: spodstavin@ru.mvista.com To: adaplas@pol.net Cc: linux-mips , Ralf Baechle Content-Type: multipart/mixed; boundary="=-1OTNIHCDhI57qNjTrRiv" Organization: MontaVista Date: Tue, 07 Jun 2005 16:41:16 +0400 Message-Id: <1118148077.5444.14.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.0.2 (2.0.2-3) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8057 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: spodstavin@ru.mvista.com Precedence: bulk X-list: linux-mips --=-1OTNIHCDhI57qNjTrRiv Content-Type: text/plain Content-Transfer-Encoding: 7bit Hi Antonio! Attached is a video driver for Lynx3DM SM722, Silicon Motion Inc. It was designed for NEC VR5701-SG2 Board, MIPS-CPU Vr5701. Please review it. Best wishes, Sergey Podstavin. --=-1OTNIHCDhI57qNjTrRiv Content-Disposition: attachment; filename=nec_framebuffer.patch Content-Type: text/x-patch; name=nec_framebuffer.patch; charset=UTF-8 Content-Transfer-Encoding: 7bit diff -burP -X /home/yadviga/bin/exclude -I '\$Id:.*Exp \$' -I '\$Source:.*' -I '\$SOURCE.*' -I '\$Revision.*' -I '\$Date' -I '\$Author' /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/Kconfig drivers/video/Kconfig --- /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/Kconfig Sat Dec 25 00:33:49 2004 +++ drivers/video/Kconfig Wed May 18 17:54:22 2005 @@ -795,6 +795,27 @@ is at . +config FB_SM + tristate "Silicon Motion SM722 support" + depends on FB && PCI + help + SM722 + +choice + prompt "Display size" + depends on FB_SM + default DISPLAY_640x480 + +config DISPLAY_640x480 + bool "640x480" + select DISPLAY_640x480 + +config DISPLAY_1024x768 + bool "1024x768" + select DISPLAY_1024x768 + +endchoice + config FB_SAVAGE tristate "S3 Savage support" depends on FB && PCI && EXPERIMENTAL diff -burP -X /home/yadviga/bin/exclude -I '\$Id:.*Exp \$' -I '\$Source:.*' -I '\$SOURCE.*' -I '\$Revision.*' -I '\$Date' -I '\$Author' /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/Makefile drivers/video/Makefile --- /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/Makefile Sat Dec 25 00:33:59 2004 +++ drivers/video/Makefile Wed May 11 16:44:31 2005 @@ -36,6 +36,7 @@ vgastate.o obj-$(CONFIG_FB_INTEL) += cfbfillrect.o cfbcopyarea.o \ cfbimgblt.o +obj-$(CONFIG_FB_SM) += smi/ cfbfillrect.o cfbcopyarea.o cfbimgblt.o obj-$(CONFIG_FB_RADEON_OLD) += radeonfb.o cfbfillrect.o cfbcopyarea.o cfbimgblt.o obj-$(CONFIG_FB_NEOMAGIC) += neofb.o cfbfillrect.o cfbcopyarea.o cfbimgblt.o vgastate.o diff -burP -X /home/yadviga/bin/exclude -I '\$Id:.*Exp \$' -I '\$Source:.*' -I '\$SOURCE.*' -I '\$Revision.*' -I '\$Date' -I '\$Author' /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/Makefile drivers/video/smi/Makefile --- /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/Makefile Thu Jan 1 03:00:00 1970 +++ drivers/video/smi/Makefile Wed May 11 16:44:31 2005 @@ -0,0 +1,5 @@ + +obj-$(CONFIG_FB_SM) += smfb.o + +smfb-objs := smi_base.o smi_hw.o + diff -burP -X /home/yadviga/bin/exclude -I '\$Id:.*Exp \$' -I '\$Source:.*' -I '\$SOURCE.*' -I '\$Revision.*' -I '\$Date' -I '\$Author' /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/smi_base.c drivers/video/smi/smi_base.c --- /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/smi_base.c Thu Jan 1 03:00:00 1970 +++ drivers/video/smi/smi_base.c Wed May 18 18:42:57 2005 @@ -0,0 +1,561 @@ +/* + * LynxEM+/EM4+(Silicon Motion Inc.) fb driver + * for VR41xx/VR5xxx. + * + * Copyright (C) NEC Corporation 2001, 2002. + * Author: t-miwa@pi.jp.nec.co.jp + * + * THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF + * ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A + * PARTICULAR PURPOSE. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../console/fbcon.h" + +#include "smifb.h" +#include "smi_hw.h" + + +#define DPPORT_BASE_OFFSET 0x400000 +#define DP_BASE_OFFSET 0x408000 +#define VP_BASE_OFFSET 0x40c000 +#define CP_BASE_OFFSET 0x40e000 +#define IO_BASE_OFFSET 0x700000 + + +#define DPPORT_REGION_SIZE (32*1024) +#define DPREG_REGION_SIZE (16*1024) +#define VPREG_REGION_SIZE (8*1024) +#define CPREG_REGION_SIZE (8*1024) +#define MMIO_REGION_SIZE (1*1024*1024) + + +#define LYNX3DM_DPPORT_BASE_OFFSET 0x100000 +#define LYNX3DM_DP_BASE_OFFSET 0x000000 +#define LYNX3DM_VP_BASE_OFFSET 0x000800 +#define LYNX3DM_CP_BASE_OFFSET 0x001000 +#define LYNX3DM_IO_BASE_OFFSET 0x0c0000 +#define LYNX3DM_FB_BASE_OFFSET 0x200000 + + +#define LYNX3DM_DPPORT_REGION_SIZE (1024*1024) +#define LYNX3DM_DPREG_REGION_SIZE (2*1024) +#define LYNX3DM_VPREG_REGION_SIZE (2*1024) +#define LYNX3DM_CPREG_REGION_SIZE (2*1024) +#define LYNX3DM_MMIO_REGION_SIZE (256*1024) + +/* + * Card Identification + * + */ +static struct pci_device_id smifb_pci_tbl[] __devinitdata = { + {PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_LYNX_EM_PLUS, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, /* Lynx EM+/EM4+ */ + {PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_LYNX_3DM, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, /* Lynx 3DM/3DM+/3DM4+ */ + {0, } /* terminate list */ +}; +MODULE_DEVICE_TABLE(pci, smifb_pci_tbl); + +/* + * + * global variables + * + */ + +#ifdef CONFIG_DISPLAY_1024x768 +/* 1024x768, 16bpp, 60Hz */ +static struct fb_var_screeninfo smifb_default_var = { + .xres = 1024, + .yres = 768, + .xres_virtual = 1024, + .yres_virtual = 768, + .xoffset = 0, + .yoffset = 0, + .bits_per_pixel = 16, + .grayscale = 0, + .red = {11, 5, 0}, + .green = { 5, 6, 0}, + .blue = { 0, 5, 0}, + .transp = { 0, 0, 0}, + .nonstd = 0, + .activate = 0, + .height = -1, + .width = -1, + .accel_flags = 0, + .pixclock = 39721, /* D */ + .left_margin = 138, + .right_margin = 24, + .upper_margin = 24, + .lower_margin = 4, + .hsync_len = 160, + .vsync_len = 6, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +}; +#else +/* 640x480, 16bpp, 60Hz */ +static struct fb_var_screeninfo smifb_default_var = { + .xres = 640, + .yres = 480, + .xres_virtual = 640, + .yres_virtual = 480, + .xoffset = 0, + .yoffset = 0, + .bits_per_pixel = 16, + .grayscale = 0, + .red = {11, 5, 0}, + .green = { 5, 6, 0}, + .blue = { 0, 5, 0}, + .transp = {0, 0, 0}, + .nonstd = 0, + .activate = 0, + .height = -1, + .width = -1, + .accel_flags = 0, + .pixclock = 39721, /* D */ + .left_margin = 82, + .right_margin = 16, + .upper_margin = 19, + .lower_margin = 1, + .hsync_len = 152, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +}; +#endif + +static char drvrname[] = "NEC video driver for SMI LynxEM+"; + +/* + * + * general utility functions + * + */ + +PRIVATE void +smi_load_video_mode(struct smifb_info *sinfo, struct fb_var_screeninfo *video_mode) +{ + int bpp, width, height; + int hDisplaySize, hDisplay, hStart, hEnd, hTotal; + int vDisplay, vStart, vEnd, vTotal; + int dotClock; + + + SMI_MSG("smi_load_video_mode: video_mode->xres = %d\n", video_mode->xres); + SMI_MSG(" : yres = %d\n", video_mode->yres); + SMI_MSG(" : xres_virtual = %d\n", video_mode->xres_virtual); + SMI_MSG(" : yres_virtual = %d\n", video_mode->yres_virtual); + SMI_MSG(" : xoffset = %d\n", video_mode->xoffset); + SMI_MSG(" : yoffset = %d\n", video_mode->yoffset); + SMI_MSG(" : bits_per_pixel = %d\n", video_mode->bits_per_pixel); + + /* smifb_blank(1, (struct fb_info*)sinfo); */ + + bpp = video_mode->bits_per_pixel; + if(bpp == 16 && video_mode->green.length == 5) + bpp = 15; + + /* horizontal params */ + width = video_mode->xres_virtual; + hDisplaySize = video_mode->xres; /* number of pixels for one horizontal line */ + hDisplay = (hDisplaySize /8) -1; /* number of character clocks */ + hStart = (hDisplaySize + video_mode->right_margin)/8 +2; /* h-blank start character clocks */ + hEnd = (hDisplaySize + video_mode->right_margin + + video_mode->hsync_len) / 8 - 1; /* h-sync end */ + hTotal = (hDisplaySize + video_mode->right_margin + + video_mode->hsync_len + + video_mode->left_margin) / 8 - 1; /* character clock from h-sync to next h-sync */ + + /* vertical params */ + height = video_mode->yres_virtual; + vDisplay = video_mode->yres - 1; /* number of lines */ + vStart = video_mode->yres + video_mode->lower_margin - 1; /* v-sync pulse start*/ + vEnd = video_mode->yres + video_mode->lower_margin + + video_mode->vsync_len - 1; /* v-sync end */ + vTotal = video_mode->yres + video_mode->lower_margin + + video_mode->vsync_len + video_mode->upper_margin + 2; /* number of scanlines (v-blank end) */ + + dotClock = 1000000000 / video_mode->pixclock; + + smi_set_moderegs(sinfo, bpp, width, height, + hDisplaySize, + hDisplay, hStart, hEnd, hTotal, + vDisplay, vStart, vEnd, vTotal, + dotClock, video_mode->sync); +} + + +/* + * + * framebuffer operations + * + */ +PRIVATE int +smifb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *info) +{ + struct smifb_info *sinfo = (struct smifb_info *)info; + + SMI_DBG("smifb_get_fix"); + + fix->smem_start = sinfo->fb_base_phys; + fix->smem_len = sinfo->fbsize; + fix->mmio_start = sinfo->dpr_base_phys; + fix->mmio_len = sinfo->dpport_size; + + fix->xpanstep = 0; /* FIXME: no xpanstep for now */ + fix->ypanstep = 1; /* FIXME: no ypanstep for now */ + fix->ywrapstep = 0; /* FIXME: no ywrap for now */ + + return 0; +} + + + + +static int vgxfb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info) +{ + if (regno > 15) + return 1; + + ((u16 *)(info->pseudo_palette))[regno] = (red & 0xf800) | (green & 0xfc00 >> 5) | (blue & 0xf800 >> 11); + return 0; +} + +/* + * Initialization helper functions + * + */ +/* kernel interface */ +static struct fb_ops smifb_ops = { + .owner = THIS_MODULE, + .fb_setcolreg = vgxfb_setcolreg, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_cursor = soft_cursor, +}; + +/* + * VGA registers + * + */ +PRIVATE void +Unlock(struct smifb_info *sinfo) +{ + SMI_DBG("Unlock"); + regSR_write(sinfo->mmio, 0x33, regSR_read(sinfo->mmio, 0x33) & 0x20); +} + +PRIVATE void +UnlockVGA(struct smifb_info *sinfo) +{ + SMI_DBG("UnlockVGA"); + regCR_write(sinfo->mmio, 0x11, regCR_read(sinfo->mmio, 0x11) & 0x7f); +} + +static struct fb_fix_screeninfo vgxfb_fix = { + .id = "vgxFB", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_TRUECOLOR, +#ifdef CONFIG_DISPLAY_1024x768 + .line_length = 1024*2, +#else + .line_length = 640*2, +#endif + .accel = FB_ACCEL_NONE, +}; + +static u32 colreg[17]; + +/* + * PCI bus + * + */ +PRIVATE int __devinit +smifb_probe( struct pci_dev *pd, const struct pci_device_id *ent ) +{ + int len; + int res; + u16 cmd; + struct smifb_info *sinfo; + struct fb_info *info; + + SMI_DBG("smifb_probe"); + + SMI_MSG("vendor id %04x\n", pd->vendor); + SMI_MSG("device id %04x\n", pd->device); + SMI_MSG("sub vendor id %04x\n", pd->subsystem_vendor); + SMI_MSG("sub device id %04x\n", pd->subsystem_device); + + SMI_MSG("base0 start addr %08x\n", (unsigned int)pci_resource_start(pd, 0)); + SMI_MSG("base0 end addr %08x\n", (unsigned int)pci_resource_end(pd, 0)); + SMI_MSG("base0 region len %08x\n", (unsigned int)pci_resource_len(pd, 0)); + SMI_MSG("base0 flags %08x\n", (unsigned int)pci_resource_flags(pd, 0)); + + pci_read_config_word(pd, PCI_STATUS, &cmd); + SMI_MSG("PCI status %04x\n", cmd); + + pci_read_config_word(pd, PCI_COMMAND, &cmd); + SMI_MSG("PCI command %04x\n", cmd); + + cmd |= PCI_COMMAND_MEMORY|PCI_COMMAND_IO; + pci_write_config_word(pd, PCI_COMMAND, cmd); + + pci_read_config_word(pd, PCI_STATUS, &cmd); + SMI_MSG("PCI status %04x\n", cmd); + pci_read_config_word(pd, PCI_COMMAND, &cmd); + SMI_MSG("PCI command %04x\n", cmd); + + + /* allocate memory resources */ + sinfo = kmalloc(sizeof(struct smifb_info), GFP_KERNEL); + if(!sinfo){ + goto err_out; + } + memset(sinfo, 0, sizeof(struct smifb_info)); + + /* driver name */ + sinfo->drvr_name = drvrname; + + sinfo->pd = pd; + sinfo->base_phys = pci_resource_start(sinfo->pd, 0); /* Frame Buffer base address */ + len = pci_resource_len(sinfo->pd, 0); + SMI_MSG("len = %lX\n", len); + if(!request_mem_region(sinfo->base_phys, len, "smifb")){ + printk(KERN_ERR "cannot reserve FrameBuffer and MMIO region\n"); + goto err_out_kfree; + } + + if((res = pci_enable_device(sinfo->pd)) < 0){ + printk("smifb: failed to enable -- err %d\n", res); + goto err_out_free_base; + } + + pci_read_config_word(pd, PCI_COMMAND, &cmd); + SMI_MSG("PCI command %04x\n", cmd); + + + { + unsigned int pseudo_io, pseudo_io_len; + unsigned char *pseudo_io_p; + + *(unsigned long *)0xbe000610 = 0x10000012 ; /* CHANGE to PCI IO ACCESS */ + asm("sync"); + pseudo_io = pci_resource_start(sinfo->pd, 0); + pseudo_io_len = pci_resource_len(sinfo->pd, 0); + pseudo_io_p = ioremap(pseudo_io, pseudo_io_len); + + VGA_WRITE8(pseudo_io_p, 0x3c3, 0x40); + regSR_write(pseudo_io_p, 0x00, 0x00); + regSR_write(pseudo_io_p, 0x17, 0xe2); + regSR_write(pseudo_io_p, 0x18, 0xff); + + iounmap(pseudo_io_p); + *(unsigned long *)0xbe000610 = 0x10000016 ; /* PCI MEM ACCESS */ + asm("sync"); + } + sinfo->base = ioremap(sinfo->base_phys, len); /* FB+DPD+DPR+VPR+CPR+MMIO */ + if(!sinfo->base){ + goto err_out_free_base; + } + switch((sinfo->pd)->device){ + case PCI_DEVICE_ID_SMI_LYNX_EM_PLUS: + sinfo->dpport = (caddr_t)(sinfo->base + DPPORT_BASE_OFFSET); + sinfo->dpr = (caddr_t)(sinfo->base + DP_BASE_OFFSET); + sinfo->vpr = (caddr_t)(sinfo->base + VP_BASE_OFFSET); + sinfo->cpr = (caddr_t)(sinfo->base + CP_BASE_OFFSET); + sinfo->mmio = (caddr_t)(sinfo->base + IO_BASE_OFFSET); + sinfo->fb_base = (caddr_t)(sinfo->base + 0); + break; + case PCI_DEVICE_ID_SMI_LYNX_3DM: + sinfo->dpport = (caddr_t)(sinfo->base + LYNX3DM_DPPORT_BASE_OFFSET); + sinfo->dpr = (caddr_t)(sinfo->base + LYNX3DM_DP_BASE_OFFSET); + sinfo->vpr = (caddr_t)(sinfo->base + LYNX3DM_VP_BASE_OFFSET); + sinfo->cpr = (caddr_t)(sinfo->base + LYNX3DM_CP_BASE_OFFSET); + sinfo->mmio = (caddr_t)(sinfo->base + LYNX3DM_IO_BASE_OFFSET); + sinfo->fb_base = (caddr_t)(sinfo->base + LYNX3DM_FB_BASE_OFFSET); + break; + } + regSR_write(sinfo->mmio, 0x18, 0x11); + + SMI_MSG("sinfo->dpport = 0x%08x\n", (u_int32_t)sinfo->dpport); + SMI_MSG("sinfo->dpr = 0x%08x, sinfo->vpr = 0x%08x\n", + (unsigned int)sinfo->dpr, (unsigned int)sinfo->vpr); + SMI_MSG("sinfo->cpr = 0x%08x, sinfo->mmio = 0x%08x\n", + (unsigned int)sinfo->cpr, (unsigned int)sinfo->mmio); + + /* Set the chip in color mode and unlock the registers */ + VGA_WRITE8(sinfo->mmio, 0x3c2, 0x2b); /* Miscellaneous Output Register ( write 0x3c2, read 0x3cc ) */ + + Unlock(sinfo); + UnlockVGA(sinfo); + + /* save the current chip status */ + + switch((sinfo->pd)->device){ + case PCI_DEVICE_ID_SMI_LYNX_EM_PLUS: + regSR_write(sinfo->mmio, 0x62, 0xff); + regSR_write(sinfo->mmio, 0x6a, 0x0c); + regSR_write(sinfo->mmio, 0x6b, 0x02); + + *(u32 *)(sinfo->fb_base +4) = 0xaa551133; + SMI_MSG(" *(u32 *)(sinfo->fb_base +4) = 0x%08x\n", *(u32 *)(sinfo->fb_base +4)); + if(*(u32 *)(sinfo->fb_base +4) != 0xaa551133){ + /* Program the MCLK to 130MHz */ + regSR_write(sinfo->mmio, 0x6a, 0x10); + regSR_write(sinfo->mmio, 0x6b, 0x02); + regSR_write(sinfo->mmio, 0x62, 0x3e); + sinfo->fbsize = 2*1024*1024; /* LynxEM+ */ + SMI_MSG("ChipID = LynxEM+. Force the MCLK to 85MHz and the memory size to 2MiB\n"); + } + else{ + sinfo->fbsize = 4*1024*1024; /* LynxEM4+ */ + SMI_MSG("ChipID = LynxEM4+. Force the MCLK to 85MHz and the memory size to 4MiB\n"); + } + sinfo->fb_base_phys = sinfo->base_phys; + break; + case PCI_DEVICE_ID_SMI_LYNX_3DM: + { + int tmp; + int mem_table[4] = { 8, 16, 0, 4 }; + tmp = (regSR_read(sinfo->mmio, 0x76) & 0xff); + SMI_MSG("%02x\n", tmp); + sinfo->fbsize = mem_table[(tmp >> 6)] * 1024 * 1024; + + regSR_write(sinfo->mmio, 0x62, 0xff); + regSR_write(sinfo->mmio, 0x6a, 0x0c); + regSR_write(sinfo->mmio, 0x6b, 0x02); + + sinfo->fb_base_phys = sinfo->base_phys + LYNX3DM_FB_BASE_OFFSET; + } + break; + default: + /* this driver supports only LynxEM+/EM4+ */ + goto err_out_free_base; + }; + + + info = &(sinfo->info); + + smifb_get_fix(&vgxfb_fix, -1, info); + + info->flags = FBINFO_FLAG_DEFAULT; + info->fbops = &smifb_ops; + info->var = smifb_default_var; + info->fix = vgxfb_fix; + info->pseudo_palette = colreg; + info->screen_base = sinfo->fb_base; + + smi_load_video_mode(sinfo, &smifb_default_var); + + if(register_framebuffer(&sinfo->info) < 0){ + goto err_out_free_base; + } + pci_set_drvdata(pd, sinfo); + + printk( "smifb: " "framebuffer (%s)\n", + sinfo->drvr_name); + + return 0; + + err_out_free_base: + release_mem_region(sinfo->base_phys, len); + err_out_kfree: + kfree(sinfo); + err_out: + return -ENODEV; +} + +PRIVATE void __devexit +smifb_remove( struct pci_dev *pd ) +{ + struct smifb_info *sinfo = pci_get_drvdata(pd); + SMI_DBG("smifb_remove"); + + if(!sinfo) + return; + + unregister_framebuffer(&sinfo->info); + + /* stop the lynx chip */ + + release_mem_region(sinfo->base_phys, pci_resource_len(sinfo->pd, 0)); + kfree(sinfo); + pci_set_drvdata(pd, NULL); +} + + +/* + * Initialization + * + */ +#ifndef MODULE +int __init +smifb_setup(char *options) +{ + SMI_DBG("smifb_setup"); + + if(!options || options) + return 0; + + return 0; +} +#endif /* not MODULE */ + + +static struct pci_driver smifb_driver = { + .name= "smifb", + .id_table= smifb_pci_tbl, + .probe= smifb_probe, + .remove= __devexit_p(smifb_remove), +}; + + +/* + * Driver initialization + */ +int __init +smifb_init(void) +{ + SMI_DBG("smifb_init"); + + return pci_module_init(&smifb_driver); +} + +/* + * modularization + * + */ +#ifdef MODULE +PRIVATE void __exit smifb_exit(void) +{ + pci_unregister_driver(&smifb_driver); +} + +module_init(smifb_init); +module_exit(smifb_exit); + +#endif /* MODULE */ + +module_init(smifb_init); + +MODULE_AUTHOR("Takeshi Tsukada"); +MODULE_DESCRIPTION("Framebuffer driver for Silicon Motion, Inc. Lynx 3DM+"); +MODULE_LICENSE("GPL"); diff -burP -X /home/yadviga/bin/exclude -I '\$Id:.*Exp \$' -I '\$Source:.*' -I '\$SOURCE.*' -I '\$Revision.*' -I '\$Date' -I '\$Author' /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/smi_hw.c drivers/video/smi/smi_hw.c --- /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/smi_hw.c Thu Jan 1 03:00:00 1970 +++ drivers/video/smi/smi_hw.c Wed May 18 16:58:10 2005 @@ -0,0 +1,183 @@ +/* + * LynxEM+/EM4+(Silicon Motion Inc.) fb driver + * for VR41xx/VR5xxx. + * + * Copyright (C) NEC Corporation 2001, 2002. + * Author: t-miwa@pi.jp.nec.co.jp + * + * THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF + * ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A + * PARTICULAR PURPOSE. + * + * + * Lynx H/W control routines. + * + */ +#include +#include +#include + + +#include +#include "smifb.h" +#include "smi_hw.h" +#include "smi_params.h" + + +/* + * set mode registers + */ +void +smi_set_moderegs(struct smifb_info *sinfo, + int bpp, int width, int height, + int hDisplaySize, + int hDisplay, int hStart, int hEnd, int hTotal, + int vDisplay, int vStart, int vEnd, int vTotal, + int dotClock, int sync) +{ + int i; + int tmp_mode = SMI_DEFAULT_MODE; + int lineLength; + struct smi_mode_regs curMode; + + SMI_DBG("smi_set_moderegs"); + + SMI_MSG("bpp = %d, width = %d, height = %d\n", bpp, width, height); + SMI_MSG("hDisplaySize = %d\n", hDisplaySize); + SMI_MSG("hDisplay = %d, hStart = %d, hEnd = %d, hTotal = %d\n", + hDisplay, hStart, hEnd, hTotal); + SMI_MSG("vDisplay = %d, vStart = %d, vEnd = %d, vTotal = %d\n", + vDisplay, vStart, vEnd, vTotal); + SMI_MSG("dotClock = %d\n", dotClock); + + lineLength = width * bpp / 8; + + switch(bpp){ + case 16: + if(hDisplaySize <= 400) + tmp_mode = DISPLAY_LCD_400x232x16; + if(hDisplaySize <= 640) + tmp_mode = DISPLAY_640x480x16; + else if(width <= 800) + tmp_mode = DISPLAY_800x600x16; + else if(width <= 1024) + tmp_mode = DISPLAY_1024x768x16; + reg_DPR10(sinfo) = (lineLength/2 << 16) | lineLength/2; /* RowPitch */ + reg_DPR1E(sinfo) = 0x0015; + reg_DPR3C(sinfo) = (lineLength/2 << 16) | lineLength/2; /* Dst & Src Window Width */ + reg_VPR00(sinfo) = 0x2 << 16; + break; + case 24: + if(hDisplaySize <= 640) + tmp_mode = DISPLAY_640x480x24; + else if(width <= 800) + tmp_mode = DISPLAY_800x600x24; + reg_DPR10(sinfo) = (lineLength/3 << 16) | lineLength/3; /* RowPitch */ + reg_DPR1E(sinfo) = 0x0035; + reg_DPR3C(sinfo) = (lineLength/3 << 16) | lineLength/3; /* Dst & Src Window Width */ + reg_VPR00(sinfo) = 0x4 << 16; + break; + }; + + for(i = 0; i < modeNums; i++){ + if(ModeInitParams[i].mode == tmp_mode) + break; + } + if(i == modeNums) + tmp_mode = SMI_DEFAULT_MODE; + + memcpy(&curMode, &ModeInitParams[tmp_mode], sizeof(struct smi_mode_regs)); + + /* + * Override some Mode Params + */ + /* MISC Reg */ + curMode.reg_MISC = 0x30 | (hDisplay == 640) ? 0x03 : 0x0b; + if(sync & FB_SYNC_HOR_HIGH_ACT) + curMode.reg_MISC |= 0x40; + if(sync & FB_SYNC_VERT_HIGH_ACT) + curMode.reg_MISC |= 0x80; + + /* CRTC */ + curMode.reg_CR00_CR18[0x00] = (u8)(hTotal - 4); + curMode.reg_CR00_CR18[0x01] = (u8)hDisplay; + curMode.reg_CR00_CR18[0x02] = (u8)hDisplay; + curMode.reg_CR00_CR18[0x03] = 0x00; + curMode.reg_CR00_CR18[0x04] = (u8)hStart; + curMode.reg_CR00_CR18[0x05] = (hEnd & 0x1f); + curMode.reg_CR00_CR18[0x06] = (u8)(vTotal & 0xff); + curMode.reg_CR00_CR18[0x07] = (u8)(((vStart >> 9) & 0x01) << 7) + | (u8)(((vDisplay >> 9) & 0x01) << 6) + | (u8)(((vTotal >> 9) & 0x01) << 5) + | 1 << 4 /* D (LC) */ + | (u8)(((vStart >> 8) & 0x01) << 2) + | (u8)(((vDisplay >> 8) & 0x01) << 1) + | (u8)((vTotal >> 8) & 0x01); + + curMode.reg_CR00_CR18[0x09] = (u8)(vDisplay >> 9) << 5 | 1 << 6; /* D (LC bit9) */ + curMode.reg_CR00_CR18[0x10] = (u8)(vStart & 0xff); + curMode.reg_CR00_CR18[0x11] = (u8)(vEnd & 0xf); + curMode.reg_CR00_CR18[0x12] = (u8)(vDisplay & 0xff); + curMode.reg_CR00_CR18[0x13] = ((width / 8) * ((bpp + 1) / 8)) & 0xFF; + curMode.reg_CR00_CR18[0x15] = (u8)(vDisplay & 0xff); + curMode.reg_CR00_CR18[0x16] = 0x00; + + curMode.reg_CR00_CR18[0x14] = (hDisplaySize > 1024)? 0x00: 0x40; /* D */ /* Underline Location */ + + /* Extended CRTC */ + curMode.reg_CR30_CR4D[0x30-0x30] = (u8)(((vTotal >> 10) & 0x01) << 3) + | (u8)(((vDisplay >> 10) & 0x01) << 1) + | (u8)((vStart >> 10) & 0x1); /* D (CRTD) (CVDER)*/ + + + curMode.reg_SR30_SR75[0x32] = 0xff; /* (Memory Type and Timig Control Reg) */ + + for(i = 0; i <= SIZE_SR00_SR04; i++) + regSR_write(sinfo->mmio, 0x00+i, curMode.reg_SR00_SR04[i]); + for(i = 0; i <= SIZE_SR10_SR24; i++) + regSR_write(sinfo->mmio, 0x10+i, curMode.reg_SR10_SR24[i]); + for(i = 0; i <= SIZE_SR30_SR75; i++) { + regSR_write(sinfo->mmio, 0x30+i, curMode.reg_SR30_SR75[i]); + } + for(i = 0; i <= SIZE_SR80_SR93; i++) + regSR_write(sinfo->mmio, 0x80+i, curMode.reg_SR80_SR93[i]); + for(i = 0; i <= SIZE_SRA0_SRAF; i++) + regSR_write(sinfo->mmio, 0xA0+i, curMode.reg_SRA0_SRAF[i]); + for(i = 0; i <= SIZE_GR00_GR08; i++) + regGR_write(sinfo->mmio, 0x00+i, curMode.reg_GR00_GR08[i]); + for(i = 0; i <= SIZE_AR00_AR14; i++) + regAR_write(sinfo->mmio, 0x00+i, curMode.reg_AR00_AR14[i]); + for(i = 0; i <= SIZE_CR00_CR18; i++) + regCR_write(sinfo->mmio, 0x00+i, curMode.reg_CR00_CR18[i]); + for(i = 0; i <= SIZE_CR30_CR4D; i++) + regCR_write(sinfo->mmio, 0x30+i, curMode.reg_CR30_CR4D[i]); + for(i = 0; i <= SIZE_CR90_CRA7; i++) + regCR_write(sinfo->mmio, 0x90+i, curMode.reg_CR90_CRA7[i]); + + + /* SetMemoryMapRegisters */ + reg_DPR14(sinfo) = 0xffffffff; /* FG color */ + reg_DPR18(sinfo) = 0x00000000; /* BG color */ + reg_DPR24(sinfo) = 0xffffffff; /* Color Mask */ + reg_DPR28(sinfo) = 0xffff; /* Masks */ + reg_DPR2C(sinfo) = 0; + reg_DPR30(sinfo) = 0; + reg_DPR34(sinfo) = 0xffffffff; + reg_DPR38(sinfo) = 0xffffffff; + reg_DPR40(sinfo) = 0; + reg_DPR44(sinfo) = 0; + + reg_VPR0C(sinfo) = 0; + + reg_VPR10(sinfo) = ((lineLength/8+2)<<16) | (lineLength/8); + + reg_VPR40(sinfo) = 0; + + reg_VPR28(sinfo) = 0x00000000; + reg_VPR2C(sinfo) = ((hDisplaySize-1)<<16) | (vDisplay); + reg_VPR30(sinfo) = 0x00000000; + reg_VPR34(sinfo) = (lineLength << 16) | lineLength; +} + + @@ -0,0 +1,181 @@ +/* + * LynxEM+/EM4+(Silicon Motion Inc.) fb driver + * for VR41xx/VR5xxx. + * + * Copyright (C) NEC Corporation 2001, 2002. + * Author: t-miwa@pi.jp.nec.co.jp + * + * THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF + * ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A + * PARTICULAR PURPOSE. + * + * + * Lynx H/W control routines. + * + */ +#include +#include +#include + + +#include +#include "smifb.h" +#include "smi_hw.h" +#include "smi_params.h" + + +/* + * set mode registers + */ +void +smi_set_moderegs(struct smifb_info *sinfo, + int bpp, int width, int height, + int hDisplaySize, + int hDisplay, int hStart, int hEnd, int hTotal, + int vDisplay, int vStart, int vEnd, int vTotal, + int dotClock, int sync) +{ + int i; + int tmp_mode = SMI_DEFAULT_MODE; + int lineLength; + struct smi_mode_regs curMode; + + SMI_DBG("smi_set_moderegs"); + + SMI_MSG("bpp = %d, width = %d, height = %d\n", bpp, width, height); + SMI_MSG("hDisplaySize = %d\n", hDisplaySize); + SMI_MSG("hDisplay = %d, hStart = %d, hEnd = %d, hTotal = %d\n", + hDisplay, hStart, hEnd, hTotal); + SMI_MSG("vDisplay = %d, vStart = %d, vEnd = %d, vTotal = %d\n", + vDisplay, vStart, vEnd, vTotal); + SMI_MSG("dotClock = %d\n", dotClock); + + lineLength = width * bpp / 8; + + switch(bpp){ + case 16: + if(hDisplaySize <= 400) + tmp_mode = DISPLAY_LCD_400x232x16; + if(hDisplaySize <= 640) + tmp_mode = DISPLAY_640x480x16; + else if(width <= 800) + tmp_mode = DISPLAY_800x600x16; + else if(width <= 1024) + tmp_mode = DISPLAY_1024x768x16; + reg_DPR10(sinfo) = (lineLength/2 << 16) | lineLength/2; /* RowPitch */ + reg_DPR1E(sinfo) = 0x0015; + reg_DPR3C(sinfo) = (lineLength/2 << 16) | lineLength/2; /* Dst & Src Window Width */ + reg_VPR00(sinfo) = 0x2 << 16; + break; + case 24: + if(hDisplaySize <= 640) + tmp_mode = DISPLAY_640x480x24; + else if(width <= 800) + tmp_mode = DISPLAY_800x600x24; + reg_DPR10(sinfo) = (lineLength/3 << 16) | lineLength/3; /* RowPitch */ + reg_DPR1E(sinfo) = 0x0035; + reg_DPR3C(sinfo) = (lineLength/3 << 16) | lineLength/3; /* Dst & Src Window Width */ + reg_VPR00(sinfo) = 0x4 << 16; + break; + }; + + for(i = 0; i < modeNums; i++){ + if(ModeInitParams[i].mode == tmp_mode) + break; + } + if(i == modeNums) + tmp_mode = SMI_DEFAULT_MODE; + + memcpy(&curMode, &ModeInitParams[tmp_mode], sizeof(struct smi_mode_regs)); + + /* + * Override some Mode Params + */ + /* MISC Reg */ + curMode.reg_MISC = 0x30 | (hDisplay == 640) ? 0x03 : 0x0b; + if(sync & FB_SYNC_HOR_HIGH_ACT) + curMode.reg_MISC |= 0x40; + if(sync & FB_SYNC_VERT_HIGH_ACT) + curMode.reg_MISC |= 0x80; + + /* CRTC */ + curMode.reg_CR00_CR18[0x00] = (u8)(hTotal - 4); + curMode.reg_CR00_CR18[0x01] = (u8)hDisplay; + curMode.reg_CR00_CR18[0x02] = (u8)hDisplay; + curMode.reg_CR00_CR18[0x03] = 0x00; + curMode.reg_CR00_CR18[0x04] = (u8)hStart; + curMode.reg_CR00_CR18[0x05] = (hEnd & 0x1f); + curMode.reg_CR00_CR18[0x06] = (u8)(vTotal & 0xff); + curMode.reg_CR00_CR18[0x07] = (u8)(((vStart >> 9) & 0x01) << 7) + | (u8)(((vDisplay >> 9) & 0x01) << 6) + | (u8)(((vTotal >> 9) & 0x01) << 5) + | 1 << 4 /* D (LC) */ + | (u8)(((vStart >> 8) & 0x01) << 2) + | (u8)(((vDisplay >> 8) & 0x01) << 1) + | (u8)((vTotal >> 8) & 0x01); + + curMode.reg_CR00_CR18[0x09] = (u8)(vDisplay >> 9) << 5 | 1 << 6; /* D (LC bit9) */ + curMode.reg_CR00_CR18[0x10] = (u8)(vStart & 0xff); + curMode.reg_CR00_CR18[0x11] = (u8)(vEnd & 0xf); + curMode.reg_CR00_CR18[0x12] = (u8)(vDisplay & 0xff); + curMode.reg_CR00_CR18[0x13] = ((width / 8) * ((bpp + 1) / 8)) & 0xFF; + curMode.reg_CR00_CR18[0x15] = (u8)(vDisplay & 0xff); + curMode.reg_CR00_CR18[0x16] = 0x00; + + curMode.reg_CR00_CR18[0x14] = (hDisplaySize > 1024)? 0x00: 0x40; /* D */ /* Underline Location */ + + /* Extended CRTC */ + curMode.reg_CR30_CR4D[0x30-0x30] = (u8)(((vTotal >> 10) & 0x01) << 3) + | (u8)(((vDisplay >> 10) & 0x01) << 1) + | (u8)((vStart >> 10) & 0x1); /* D (CRTD) (CVDER)*/ + + + curMode.reg_SR30_SR75[0x32] = 0xff; /* (Memory Type and Timig Control Reg) */ + + for(i = 0; i <= SIZE_SR00_SR04; i++) + regSR_write(sinfo->mmio, 0x00+i, curMode.reg_SR00_SR04[i]); + for(i = 0; i <= SIZE_SR10_SR24; i++) + regSR_write(sinfo->mmio, 0x10+i, curMode.reg_SR10_SR24[i]); + for(i = 0; i <= SIZE_SR30_SR75; i++) { + regSR_write(sinfo->mmio, 0x30+i, curMode.reg_SR30_SR75[i]); + } + for(i = 0; i <= SIZE_SR80_SR93; i++) + regSR_write(sinfo->mmio, 0x80+i, curMode.reg_SR80_SR93[i]); + for(i = 0; i <= SIZE_SRA0_SRAF; i++) + regSR_write(sinfo->mmio, 0xA0+i, curMode.reg_SRA0_SRAF[i]); + for(i = 0; i <= SIZE_GR00_GR08; i++) + regGR_write(sinfo->mmio, 0x00+i, curMode.reg_GR00_GR08[i]); + for(i = 0; i <= SIZE_AR00_AR14; i++) + regAR_write(sinfo->mmio, 0x00+i, curMode.reg_AR00_AR14[i]); + for(i = 0; i <= SIZE_CR00_CR18; i++) + regCR_write(sinfo->mmio, 0x00+i, curMode.reg_CR00_CR18[i]); + for(i = 0; i <= SIZE_CR30_CR4D; i++) + regCR_write(sinfo->mmio, 0x30+i, curMode.reg_CR30_CR4D[i]); + for(i = 0; i <= SIZE_CR90_CRA7; i++) + regCR_write(sinfo->mmio, 0x90+i, curMode.reg_CR90_CRA7[i]); + + + /* SetMemoryMapRegisters */ + reg_DPR14(sinfo) = 0xffffffff; /* FG color */ + reg_DPR18(sinfo) = 0x00000000; /* BG color */ + reg_DPR24(sinfo) = 0xffffffff; /* Color Mask */ + reg_DPR28(sinfo) = 0xffff; /* Masks */ + reg_DPR2C(sinfo) = 0; + reg_DPR30(sinfo) = 0; + reg_DPR34(sinfo) = 0xffffffff; + reg_DPR38(sinfo) = 0xffffffff; + reg_DPR40(sinfo) = 0; + reg_DPR44(sinfo) = 0; + + reg_VPR0C(sinfo) = 0; + + reg_VPR10(sinfo) = ((lineLength/8+2)<<16) | (lineLength/8); + + reg_VPR40(sinfo) = 0; + + reg_VPR28(sinfo) = 0x00000000; + reg_VPR2C(sinfo) = ((hDisplaySize-1)<<16) | (vDisplay); + reg_VPR30(sinfo) = 0x00000000; + reg_VPR34(sinfo) = (lineLength << 16) | lineLength; +} diff -burP -X /home/yadviga/bin/exclude -I '\$Id:.*Exp \$' -I '\$Source:.*' -I '\$SOURCE.*' -I '\$Revision.*' -I '\$Date' -I '\$Author' /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/smi_hw.h drivers/video/smi/smi_hw.h --- /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/smi_hw.h Thu Jan 1 03:00:00 1970 +++ drivers/video/smi/smi_hw.h Wed May 11 16:44:31 2005 @@ -0,0 +1,193 @@ +/* + * LynxEM+/EM4+(Silicon Motion Inc.) fb driver + * for VR41xx/VR5xxx. + * + * Copyright (C) NEC Corporation 2001, 2002. + * Author: t-miwa@pi.jp.nec.co.jp + * + * THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF + * ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A + * PARTICULAR PURPOSE. + * + */ +#ifndef __SMI_HW_H__ +#define __SMI_HW_H__ + +#include "smifb.h" + +extern void smi_set_moderegs(struct smifb_info *sinfo, + int bpp, int width, int height, + int hDisplaySize, + int hDisplay, int hStart, int hEnd, int hTotal, + int vDisplay, int vStart, int vEnd, int vTotal, + int dotClock, int sync); + + + +#define MMIO_OUT8(p, r, d) (((volatile u8 *)(p))[r] = (d)) +#define MMIO_OUT16(p, r, d) (((volatile u16 *)(p))[(r)>>1] = (d)) +#define MMIO_OUT32(p, r, d) (((volatile u32 *)(p))[(r)>>2] = (d)) +#define MMIO_IN8(p, r) (((volatile u8 *)(p))[(r)]) +#define MMIO_IN16(p, r) (((volatile u16 *)(p))[(r)>>1]) +#define MMIO_IN32(p, r) (((volatile u32 *)(p))[(r)>>2]) + +static inline u8 +VGA_READ8( u8 *base, uint reg ) +{ + return MMIO_IN8( base, reg ); +} + +static inline void +VGA_WRITE8( u8 *base, uint reg, u8 data ) +{ + MMIO_OUT8(base, reg, data); +} + +static inline u8 +VGA_READ8_INDEX( u8 *base, u8 index ) +{ + VGA_WRITE8(base, 0x3c4, index); + return VGA_READ8(base, 0x3c5); +} + +static inline void +VGA_WRITE8_INDEX( u8 *base, u8 index, u8 data ) +{ + VGA_WRITE8(base, 0x3c4, index); + VGA_WRITE8(base, 0x3c5, data); +} + +static inline u8 +regSR_read( u8 *base, u8 index ) +{ + VGA_WRITE8(base, 0x3c4, index); + return VGA_READ8(base, 0x3c5); +} + +static inline void +regSR_write( u8 *base, u8 index, u8 data ) +{ + VGA_WRITE8(base, 0x3c4, index); + VGA_WRITE8(base, 0x3c5, data); +} + +static inline u8 +regCR_read( u8 *base, u8 index ) +{ + VGA_WRITE8(base, 0x3d4, index); + return VGA_READ8(base, 0x3d5); +} + +static inline void +regCR_write( u8 *base, u8 index, u8 data ) +{ + VGA_WRITE8(base, 0x3d4, index); + VGA_WRITE8(base, 0x3d5, data); +} + +static inline u8 +regGR_read( u8 *base, u8 index ) +{ + VGA_WRITE8(base, 0x3ce, index); + return VGA_READ8(base, 0x3cf); +} + +static inline void +regGR_write( u8 *base, u8 index, u8 data ) +{ + VGA_WRITE8(base, 0x3ce, index); + VGA_WRITE8(base, 0x3cf, data); +} + +static inline u8 +regAR_read( u8 *base, u8 index ) +{ + (void)VGA_READ8(base, 0x3da); /* reset flip-flop */ + VGA_WRITE8(base, 0x3c0, index); + return VGA_READ8(base, 0x3c1); +} + +static inline void +regAR_write( u8 *base, u8 index, u8 data ) +{ + (void)VGA_READ8(base, 0x3da); /* reset flip-flop */ + VGA_WRITE8(base, 0x3c0, index); + VGA_WRITE8(base, 0x3c0, data); +} + + + + + +/* + * LynxEM+ registers + */ + + +/* Drawing Engine Control Registers */ +#define reg_DPR00(x) *(u16 *)((x)->dpr+0x00) /* Source Y or K2 */ +#define reg_DPR02(x) *(u16 *)((x)->dpr+0x02) /* Source X or K1 */ +#define reg_DPR04(x) *(u16 *)((x)->dpr+0x04) /* Destination Y or Start Y */ +#define reg_DPR06(x) *(u16 *)((x)->dpr+0x06) /* Destination X or Start X */ +#define reg_DPR08(x) *(u16 *)((x)->dpr+0x08) /* Dimension Y or Error Term */ +#define reg_DPR0A(x) *(u16 *)((x)->dpr+0x0A) /* Dimension X or Vector Length */ +#define reg_DPR0C(x) *(u16 *)((x)->dpr+0x0C) /* ROP and Miscellaneous Control */ +#define reg_DPR0E(x) *(u16 *)((x)->dpr+0x0E) /* Drawing Engine Commands and Control */ +#define reg_DPR10(x) *(u16 *)((x)->dpr+0x10) /* Source Row Pitch */ +#define reg_DPR12(x) *(u16 *)((x)->dpr+0x12) /* Destination Row Picth */ +#define reg_DPR14(x) *(u32 *)((x)->dpr+0x14) /* Foreground Colors */ +#define reg_DPR18(x) *(u32 *)((x)->dpr+0x18) /* Background Colors */ +#define reg_DPR1C(x) *(u16 *)((x)->dpr+0x1C) /* Stretch Source Height Y */ +#define reg_DPR1E(x) *(u16 *)((x)->dpr+0x1E) /* Drawing Engine DataFormat and Location Format Select */ +#define reg_DPR20(x) *(u32 *)((x)->dpr+0x20) /* Color Compare */ +#define reg_DPR24(x) *(u32 *)((x)->dpr+0x24) /* Color Compare Mask */ +#define reg_DPR28(x) *(u16 *)((x)->dpr+0x28) /* Bit Mask */ +#define reg_DPR2A(x) *(u16 *)((x)->dpr+0x2A) /* Byte Mask Enable */ +#define reg_DPR2C(x) *(u16 *)((x)->dpr+0x2C) /* Scisors Left and Control */ +#define reg_DPR2E(x) *(u16 *)((x)->dpr+0x2E) /* Scisors Top */ +#define reg_DPR30(x) *(u16 *)((x)->dpr+0x30) /* Scisors Right */ +#define reg_DPR32(x) *(u16 *)((x)->dpr+0x32) /* Scisors Bottom */ +#define reg_DPR34(x) *(u32 *)((x)->dpr+0x34) /* Mono Pattern Low */ +#define reg_DPR38(x) *(u32 *)((x)->dpr+0x38) /* Mono Pattern High */ +#define reg_DPR3C(x) *(u32 *)((x)->dpr+0x3C) /* XY Addressing Destination & Source Window Widths */ +#define reg_DPR40(x) *(u32 *)((x)->dpr+0x40) /* Source Base Address */ +#define reg_DPR44(x) *(u32 *)((x)->dpr+0x44) /* Destination Base Address */ + +/* Video Processor Control Registers */ +#define reg_VPR00(x) *(u32 *)((x)->vpr+0x00) /* Miscellaneous Graphics and Video Control */ +#define reg_VPR04(x) *(u32 *)((x)->vpr+0x04) /* Color Keys */ +#define reg_VPR08(x) *(u32 *)((x)->vpr+0x08) /* Color Key Masks */ +#define reg_VPR0C(x) *(u32 *)((x)->vpr+0x0C) /* Data Source Start Address for Extended Graphics Modes */ +#define reg_VPR10(x) *(u32 *)((x)->vpr+0x10) /* Data Source Width and Offset for Extended Graphics Modes */ +#define reg_VPR14(x) *(u32 *)((x)->vpr+0x14) /* Video Window I Left and Top Boundaries */ +#define reg_VPR18(x) *(u32 *)((x)->vpr+0x18) /* Video Window I Right and Bottom Boundaries */ +#define reg_VPR1C(x) *(u32 *)((x)->vpr+0x1C) /* Video Window I Source Start Address */ +#define reg_VPR20(x) *(u32 *)((x)->vpr+0x20) /* Video Window I Source Width and Offset */ +#define reg_VPR24(x) *(u32 *)((x)->vpr+0x24) /* Video Window I Stretch Factor */ +#define reg_VPR28(x) *(u32 *)((x)->vpr+0x28) /* Video Window II Left and Top Boundaries */ +#define reg_VPR2C(x) *(u32 *)((x)->vpr+0x2C) /* Video Window II Right and Bottom Boundaries */ +#define reg_VPR30(x) *(u32 *)((x)->vpr+0x30) /* Video Window II Source Start Address */ +#define reg_VPR34(x) *(u32 *)((x)->vpr+0x34) /* Video Window II Source Width and Offset */ +#define reg_VPR38(x) *(u32 *)((x)->vpr+0x38) /* Video Window II Stretch Factor */ +#define reg_VPR3C(x) *(u32 *)((x)->vpr+0x3C) /* Graphics and Video Controll II */ +#define reg_VPR40(x) *(u32 *)((x)->vpr+0x40) /* Graphic Scale Factor */ +#define reg_VPR54(x) *(u32 *)((x)->vpr+0x54) /* FIFO Priority Control */ +#define reg_VPR58(x) *(u32 *)((x)->vpr+0x58) /* FIFO Empty Request level Control */ +#define reg_VPR5C(x) *(u32 *)((x)->vpr+0x5C) /* YUV to RGB Conversion Constant */ +#define reg_VPR60(x) *(u32 *)((x)->vpr+0x60) /* Current Scan Line Position */ +#define reg_VPR64(x) *(u32 *)((x)->vpr+0x64) /* Signature Analyzer Control and Status */ +#define reg_VPR68(x) *(u32 *)((x)->vpr+0x68) /* Video Window I Stretch Factor */ +#define reg_VPR6C(x) *(u32 *)((x)->vpr+0x6C) /* Video Window II Stretch Factor */ + +/* Capture Processor Control Registers */ +#define reg_CPR00(x) *(u32 *)((x)->cpr+0x00) /* Capture Port Control */ +#define reg_CPR04(x) *(u32 *)((x)->cpr+0x04) /* Video Source Clipping Control */ +#define reg_CPR08(x) *(u32 *)((x)->cpr+0x08) /* Video Source Capture Size Control */ +#define reg_CPR0C(x) *(u32 *)((x)->cpr+0x0C) /* Capture Port Buffer I Source Start Address */ +#define reg_CPR10(x) *(u32 *)((x)->cpr+0x10) /* Capture Port Buffer II Source Start Address */ +#define reg_CPR14(x) *(u32 *)((x)->cpr+0x14) /* Capture Port Source Offset Address */ +#define reg_CPR18(x) *(u32 *)((x)->cpr+0x18) /* Capture FIFO Empty Request level Control */ + + +#endif /* __SMI_HW_H__ */ diff -burP -X /home/yadviga/bin/exclude -I '\$Id:.*Exp \$' -I '\$Source:.*' -I '\$SOURCE.*' -I '\$Revision.*' -I '\$Date' -I '\$Author' /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/smi_params.h drivers/video/smi/smi_params.h --- /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/smi_params.h Thu Jan 1 03:00:00 1970 +++ drivers/video/smi/smi_params.h Tue May 17 20:56:42 2005 @@ -0,0 +1,444 @@ +/* + * LynxEM+/EM4+(Silicon Motion Inc.) fb driver + * for VR41xx/VR5xxx. + * + * Copyright (C) NEC Corporation 2001, 2002. + * Author: t-miwa@pi.jp.nec.co.jp + * + * THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF + * ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A + * PARTICULAR PURPOSE. + * + */ +#ifndef __SMI_REGS_H__ +#define __SMI_REGS_H__ + +/* register settings */ +struct smi_mode_regs ModeInitParams[modeNums] = { + /* mode#4 640 x 480 16Bpp 60Hz */ + { + DISPLAY_640x480x16, + /* reg_MISC */ + 0xE3, + /* reg_SR00_SR04 */ + { + 0x03, 0x01, 0x0F, 0x00, 0x0E, + }, + /* reg_SR10_SR24 */ + { + 0x03, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x10, 0x2C, + 0x59, 0x00, 0x20, 0x00, 0x00, 0x0F, 0x0F, 0x00, + 0xC4, 0x30, 0x02, 0x01, 0x01, + }, + + /* reg_SR30_SR75 */ + { + 0xAA, 0x03, 0xA0, 0x89, 0xC0, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0x00, 0x00, 0x03, 0xFF, + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC, + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0xAA, + 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, + 0x04, 0x50, 0x19, 0xAA, 0xAA, 0x00, 0x00, 0xAA, + 0x01, 0x80, 0xFF, 0x1A, 0x1A, 0x00, 0x03, 0x00, + 0x50, 0x03, 0x0D, 0x02, 0x07, 0x82, 0x07, 0x04, + 0x00, 0x45, 0x30, 0x0C, 0x40, 0x30, + }, + /* reg_SR80_SR93 */ + { + 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0xAA, + 0x40, 0x01, 0xF0, 0x00, 0xFF, 0x00, 0xAA, 0xAA, + 0x00, 0x00, 0x00, 0x00, + }, + /* reg_SRA0_SRAF */ + { + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, + }, + /* reg_GR00_GR08 */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, + 0xFF, + }, + /* reg_AR00_AR14 */ + { + 0x3F, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x00, 0x12, 0x00, 0x04, + }, + /* reg_CR00_CR18 */ + { + 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, + 0xFF, + }, + /* reg_CR30_CR4D */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, + 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, + 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, + 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, + }, + /* reg_CR90_CRA7 */ + { + 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, + 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, + 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, + }, + }, + /* mode#5 800 x 600 16Bpp 60Hz */ + { + DISPLAY_800x600x16, + /* reg_MISC */ + 0x2B, + /* reg_SR00_SR04 */ + { + 0x03, 0x01, 0x0F, 0x03, 0x0E, + }, + /* reg_SR10_SR24 */ + { + 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0xe2, + 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC4, 0x30, 0x02, 0x01, 0x01, + }, + /* reg_SR30_SR75 */ + { + 0x36, 0x03, 0x20, 0x09, 0xC0, 0x36, 0x36, 0x36, + 0x36, 0x36, 0x36, 0x36, 0x00, 0x00, 0x03, 0xFF, + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x36, 0x36, 0x36, + 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, + 0x04, 0x55, 0x59, 0x36, 0x36, 0x00, 0x00, 0x36, + 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, + 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, + 0x02, 0x45, 0x30, 0x30, 0x40, 0x20, + }, + /* reg_SR80_SR93 */ + { + 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x36, + 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x36, 0x36, + 0x00, 0x00, 0x00, 0x00, + }, + /* reg_SRA0_SRAF */ + { + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, + }, + /* reg_GR00_GR08 */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, + 0xFF, + }, + /* reg_AR00_AR14 */ + { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x41, 0x00, 0x0F, 0x00, 0x00, + }, + /* reg_CR00_CR18 */ + { + 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, + 0xFF, + }, + /* reg_CR30_CR4D */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, + 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, + 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, + 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, + }, + /* reg_CR90_CRA7 */ + { + 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, + 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, + 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, + }, + }, + /* mode#6 1024 x 768 16Bpp 60Hz **/ + { + DISPLAY_1024x768x16, + /* reg_MISC */ + 0xEB, + /* reg_SR00_SR04 */ + { + 0x03, 0x01, 0x0F, 0x03, 0x0E, + }, + /* reg_SR10_SR24 */ + { + 0x03, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x10, 0x2c, + 0x59, 0x02, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x00, + 0xC4, 0x30, 0x02, 0x01, 0x01, + }, + /* reg_SR30_SR75 */ + { + 0xAA, 0x03, 0x20, 0x89, 0xC0, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0x00, 0x00, 0x03, 0xFF, + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC, + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0xAA, + 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, + 0x00, 0x60, 0x59, 0xAA, 0xAA, 0x00, 0x00, 0xAA, + 0x01, 0x80, 0xFF, 0x1A, 0x1A, 0x00, 0x03, 0x00, + 0x50, 0x03, 0x0D, 0x02, 0x12, 0x82, 0x09, 0x02, + 0x04, 0x45, 0x30, 0x0C, 0x40, 0x20, + }, + /* reg_SR80_SR93 */ + { + 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xAA, + 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xAA, 0xAA, + 0x00, 0x00, 0x00, 0x00, + }, + /* reg_SRA0_SRAF */ + { + 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, + 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, + }, + /* reg_GR00_GR08 */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, + 0xFF, + }, + /* reg_AR00_AR14 */ + { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x41, 0x11, 0x0F, 0x13, 0x00, + }, + /* reg_CR00_CR18 */ + { + 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, + 0xFF, + }, + /* reg_CR30_CR4D */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, + 0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF, + 0xA3, 0x7F, 0x00, 0x86, 0x15, 0x24, 0xFF, 0x00, + 0x01, 0x07, 0xE5, 0x20, 0x7F, 0xFF, + }, + /* reg_CR90_CRA7 */ + { + 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, + 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, + 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, + }, + }, + /* mode#7 640 x 480 24Bpp 60Hz */ + { + DISPLAY_640x480x24, + /* reg_MISC */ + 0xE3, + /* reg_SR00_SR04 */ + { + 0x03, 0x01, 0x0F, 0x00, 0x0E, + }, + /* reg_SR10_SR24 */ + { + 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0xe2, + 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC4, 0x30, 0x02, 0x01, 0x01, + }, + /* reg_SR30_SR75 */ + { + 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32, + 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF, + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32, + 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, + 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32, + 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, + 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04, + 0x00, 0x45, 0x30, 0x30, 0x40, 0x30, + }, + /* reg_SR80_SR93 */ + { + 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32, + 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32, + 0x00, 0x00, 0x00, 0x00, + }, + /* reg_SRA0_SRAF */ + { + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, + }, + /* reg_GR00_GR08 */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, + 0xFF, + }, + /* reg_AR00_AR14 */ + { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x41, 0x00, 0x0F, 0x00, 0x00, + }, + /* reg_CR00_CR18 */ + { + 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, + 0xFF, + }, + /* reg_CR30_CR4D */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, + 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, + 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, + 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, + }, + /* reg_CR90_CRA7 */ + { + 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, + 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, + 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, + }, + }, + /* mode#8 800 x 600 24Bpp 60Hz */ + { + DISPLAY_800x600x24, + /* reg_MISC */ + 0x2B, + /* reg_SR00_SR04 */ + { + 0x03, 0x01, 0x0F, 0x03, 0x0E, + }, + /* reg_SR10_SR24 */ + { + 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0xe2, + 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC4, 0x30, 0x02, 0x01, 0x01, + }, + /* reg_SR30_SR75 */ + { + 0x36, 0x03, 0x20, 0x09, 0xC0, 0x36, 0x36, 0x36, + 0x36, 0x36, 0x36, 0x36, 0x00, 0x00, 0x03, 0xFF, + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x36, 0x36, 0x36, + 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, + 0x04, 0x55, 0x59, 0x36, 0x36, 0x00, 0x00, 0x36, + 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, + 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, + 0x02, 0x45, 0x30, 0x30, 0x40, 0x20, + }, + /* reg_SR80_SR93 */ + { + 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x36, + 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x36, 0x36, + 0x00, 0x00, 0x00, 0x00, + }, + /* reg_SRA0_SRAF */ + { + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, + }, + /* reg_GR00_GR08 */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, + 0xFF, + }, + /* reg_AR00_AR14 */ + { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x41, 0x00, 0x0F, 0x00, 0x00, + }, + /* reg_CR00_CR18 */ + { + 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, + 0xFF, + }, + /* reg_CR30_CR4D */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, + 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, + 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, + 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, + }, + /* reg_CR90_CRA7 */ + { + 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, + 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, + 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, + }, + }, + /* mode#9 400 x 232 16Bpp 60Hz */ + { + DISPLAY_LCD_400x232x16, + /* reg_MISC */ + 0x2B, + /* reg_SR00_SR04 */ + { + 0x03, 0x01, 0x0F, 0x03, 0x0E, + }, + /* reg_SR10_SR24 */ + { + 0x03, 0x00, 0x00, 0x00, 0x00, 0x08, 0x10, 0x2C, + 0x59, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x00, + 0x84, 0x00, 0x02, 0x00, 0x31, + }, + /* reg_SR30_SR75 */ + { + 0xB7, 0x43, 0x98, 0x01, 0xC0, 0xB7, 0xB7, 0xB7, + 0xB7, 0xB7, 0xB7, 0xB7, 0x00, 0x00, 0x85, 0x2C, + 0xC0, 0xE1, 0x00, 0x00, 0x40, 0xF0, 0x80, 0xC4, + 0x40, 0x3C, 0xA1, 0x40, 0x00, 0x00, 0x01, 0xB7, + 0x02, 0x24, 0xD9, 0xC7, 0xCC, 0x31, 0x2C, 0x2D, + 0x07, 0x57, 0x19, 0xB7, 0xB7, 0x00, 0x00, 0xB7, + 0x01, 0x00, 0xFF, 0x1A, 0x1A, 0x01, 0x03, 0x00, + 0xD4, 0x07, 0x0D, 0x02, 0x23, 0x3F, 0x35, 0x13, + 0x83, 0xDD, 0x02, 0x0C, 0x05, 0x00, + }, + /* reg_SR80_SR93 */ + { + 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x09, 0xB7, + 0x48, 0x00, 0x36, 0x00, 0xFF, 0x00, 0xB7, 0xB7, + 0x00, 0x00, 0x00, 0x00, + }, + /* reg_SRA0_SRAF */ + { + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, + }, + /* reg_GR00_GR08 */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, + 0xFF, + }, + /* reg_AR00_AR14 */ + { + 0x00, 0x02, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x00, 0x12, 0x00, 0x04, + }, + /* reg_CR00_CR18 */ + { + 0x3B, 0x31, 0x31, 0x00, 0x3A, 0x00, 0x06, 0x11, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xF1, 0x85, 0xE9, 0x32, 0x40, 0xE9, 0x00, 0xEB, + 0xFF, + }, + /* reg_CR30_CR4D */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x02, 0x10, + 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x00, + 0x3B, 0x31, 0x00, 0x3A, 0x00, 0x06, 0xEA, 0x00, + 0xF2, 0x05, 0x01, 0x00, 0x31, 0xE9, + }, + /* reg_CR90_CRA7 */ + { + 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, + 0xDB, 0x2A, 0xDF, 0x33, 0xFF, 0xFF, 0x1B, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }, + }, +}; + + + +#endif /* __SMI_REGS_H__ */ diff -burP -X /home/yadviga/bin/exclude -I '\$Id:.*Exp \$' -I '\$Source:.*' -I '\$SOURCE.*' -I '\$Revision.*' -I '\$Date' -I '\$Author' /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/smifb.h drivers/video/smi/smifb.h --- /home/yadviga/nec/SOURCES/linux-2.6.10/drivers/video/smi/smifb.h Thu Jan 1 03:00:00 1970 +++ drivers/video/smi/smifb.h Wed May 18 17:15:31 2005 @@ -0,0 +1,112 @@ +/* + * LynxEM+/EM4+(Silicon Motion Inc.) fb driver + * for VR41xx/VR5xxx. + * + * Copyright (C) NEC Corporation 2001, 2002. + * Author: t-miwa@pi.jp.nec.co.jp + * + * THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF + * ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A + * PARTICULAR PURPOSE. + * + */ +#ifndef __SMIFB_H__ +#define __SMIFB_H__ + +#undef SMIFB_DEBUG + +#ifdef SMIFB_DEBUG +#define SMI_DBG(x) printk(/*KERN_DEBUG*/ "smifb: %s\n", x) +#define SMI_MSG(fmt, args...) printk(/*KERN_DEBUG*/ "smifb: " fmt, ##args) +#define PRIVATE +#else +#define SMI_DBG(x) +#define SMI_MSG(fmt, args...) +#define PRIVATE static +#endif + +#define FBCON_HAS_CFB16 + +#define PCI_VENDOR_ID_SMI 0x126f + +#define PCI_DEVICE_ID_SMI_LYNX_EM 0x710 +#define PCI_DEVICE_ID_SMI_LYNX_EM_PLUS 0x712 +#define PCI_DEVICE_ID_SMI_LYNX_3DM 0x720 + + +enum ScreenModes { + DISPLAY_640x480x16, + DISPLAY_800x600x16, + DISPLAY_1024x768x16, + DISPLAY_640x480x24, + DISPLAY_800x600x24, + DISPLAY_LCD_400x232x16, + modeNums, +}; + +#define SMI_DEFAULT_MODE DISPLAY_640x480x16 + +#define SIZE_SR00_SR04 (0x04 - 0x00 + 1) +#define SIZE_SR10_SR24 (0x24 - 0x10 + 1) +#define SIZE_SR30_SR75 (0x75 - 0x30 + 1) +#define SIZE_SR80_SR93 (0x93 - 0x80 + 1) +#define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1) +#define SIZE_GR00_GR08 (0x08 - 0x00 + 1) +#define SIZE_AR00_AR14 (0x14 - 0x00 + 1) +#define SIZE_CR00_CR18 (0x18 - 0x00 + 1) +#define SIZE_CR30_CR4D (0x4D - 0x30 + 1) +#define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1) + + +struct smi_mode_regs { + int mode; + u8 reg_MISC; + u8 reg_SR00_SR04[SIZE_SR00_SR04]; /* SEQ00--04 (SEQ) */ + u8 reg_SR10_SR24[SIZE_SR10_SR24]; /* SCR10--1F, PDR20--24 (SYS),(PWR) */ + u8 reg_SR30_SR75[SIZE_SR30_SR75]; /* FPR30--5A, MCR60--62, CCR65--6F GPR70--75 (LCD),(MEM),(CLK),(GP) */ + u8 reg_SR80_SR93[SIZE_SR80_SR93]; /* PHR80-81, POP82--86, HCR88-8D, POP90--93 (CURS),(ICON),(CURS),(ICON) */ + u8 reg_SRA0_SRAF[SIZE_SRA0_SRAF]; /* FPRA0--AF (LCD) */ + u8 reg_GR00_GR08[SIZE_GR00_GR08]; /* GR00--08 (GC) */ + u8 reg_AR00_AR14[SIZE_AR00_AR14]; /* ATR00--14 (ATTR) */ + u8 reg_CR00_CR18[SIZE_CR00_CR18]; /* CRT00--18 (CRTC)*/ + u8 reg_CR30_CR4D[SIZE_CR30_CR4D]; /* CRT30--3F, SVR40--4D (ECRTC),(SHADOW) */ + u8 reg_CR90_CRA7[SIZE_CR90_CRA7]; /* CRT90--9B,9E,9F,A0--A5,A6,A7, (DDA),(EC2),(EC1)(VCLUT),(VC),(HC)*/ +}; + + + +typedef struct { + unsigned char red, green, blue, transp; +}smi_cfb8_cmap_t; + +struct smifb_info { + struct fb_info info; /* kernel framebuffer info */ + const char *drvr_name; /* Silicon Motion hardware board type */ + struct pci_dev *pd; /* descripbe the PCI device */ + + unsigned long base_phys; /* physical base address */ + /* PCI base physical addresses */ + unsigned long fb_base_phys; /* physical Frame Buffer base address */ + unsigned long dpr_base_phys; /* physical Drawing Processor base address */ + unsigned long vpr_base_phys; /* physical Video Processor base address */ + unsigned long cpr_base_phys; /* physical Capture Processor base address */ + unsigned long mmio_base_phys; /* physical MMIO spase (VGA + SMI regs ?) base address */ + + unsigned long dpport_base_phys; /* physical Drawing Processor Data Port base address */ + int dpport_size; /* size of Drawin Processor Data Port memory space */ + + /* PCI base virtual addresses */ + volatile caddr_t base; /* address of base */ + volatile caddr_t fb_base; /* address of frame buffer base */ + volatile caddr_t dpr; /* Drawing Processor Registers */ + volatile caddr_t vpr; /* Video Processor Registers */ + volatile caddr_t cpr; /* Capture Processor Registers */ + volatile caddr_t mmio; /* Memory Mapped I/O Port */ + volatile caddr_t dpport; /* Drawing Processor Data */ + + int fbsize; /* Frame-Buffer memory size */ +}; + + +#endif /* __SMIFB_H__ */ --=-1OTNIHCDhI57qNjTrRiv-- From Hiroshi_DOYU@montavista.co.jp Thu Jun 9 05:57:52 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Jun 2005 05:58:13 +0100 (BST) Received: from sonicwall.montavista.co.jp ([IPv6:::ffff:202.232.97.131]:3589 "EHLO yuubin.montavista.co.jp") by linux-mips.org with ESMTP id ; Thu, 9 Jun 2005 05:57:51 +0100 Received: from localhost.localdomain (oreo.jp.mvista.com [10.200.16.31]) by yuubin.montavista.co.jp (8.12.5/8.12.5) with SMTP id j594vkS5003815; Thu, 9 Jun 2005 13:57:47 +0900 Date: Thu, 9 Jun 2005 13:59:10 +0900 From: Hiroshi DOYU To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mlachwani@mvista.com Subject: [PATCH 1/1] MIPS 2.6 : kgdb on TX4938(RBHMA4500) Message-Id: <20050609135910.65bdc50c.Hiroshi_DOYU@montavista.co.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8058 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Hiroshi_DOYU@montavista.co.jp Precedence: bulk X-list: linux-mips Hello, This patch includes kgdb support on TX4938(RBHMA4500). Please review it. Hiroshi DOYU ----- --- linux.orig/arch/mips/tx4938/common/dbgio.c 1970-01-01 09:00:00.000000000 +0900 +++ linux/arch/mips/tx4938/common/dbgio.c 2005-06-09 13:49:38.674565752 +0900 @@ -0,0 +1,47 @@ +/* + * linux/arch/mips/tx4938/common/dbgio.c + * + * kgdb interface for gdb + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +u8 getDebugChar(void) +{ + extern u8 txx9_sio_kdbg_rd(void); + return (txx9_sio_kdbg_rd()); +} + + +int putDebugChar(u8 byte) +{ + extern int txx9_sio_kdbg_wr( u8 ch ); + return (txx9_sio_kdbg_wr(byte)); +} --- linux.orig/drivers/serial/serial_txx9.c 2005-05-26 18:12:46.000000000 +0900 +++ linux/drivers/serial/serial_txx9.c 2005-06-09 11:17:34.000000000 +0900 @@ -1129,6 +1129,96 @@ MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl); #endif /* ENABLE_SERIAL_TXX9_PCI */ +/******************************************************************************/ +/* BEG: KDBG Routines */ +/******************************************************************************/ + +#ifdef CONFIG_KGDB +int kgdb_init_count = 0; + +void txx9_sio_kgdb_hook(unsigned int port, unsigned int baud_rate) +{ + static struct resource kgdb_resource; + int ret; + struct uart_txx9_port *up = &serial_txx9_ports[port]; + + /* prevent initialization by driver */ + kgdb_resource.name = "serial_txx9(debug)"; + kgdb_resource.start = up->port.membase; + kgdb_resource.end = up->port.membase + 36 - 1; + kgdb_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; + + ret = request_resource(&iomem_resource, &kgdb_resource); + if(ret == -EBUSY) + printk(" serial_txx9(debug): request_resource failed\n"); + + return; +} +void +txx9_sio_kdbg_init( unsigned int port_number ) +{ + if (port_number == 1) { + txx9_sio_kgdb_hook(port_number, 38400); + } else { + printk("Bad Port Number [%u] != [1]\n",port_number); + } + return; +} + +u8 +txx9_sio_kdbg_rd( void ) +{ + unsigned int status,ch; + struct uart_txx9_port *up = &serial_txx9_ports[1]; + + if (kgdb_init_count == 0) { + txx9_sio_kdbg_init(1); + kgdb_init_count = 1; + } + + while (1) { + status = sio_in(up, TXX9_SIDISR); + if ( status & 0x1f ) { + ch = sio_in(up, TXX9_SIRFIFO ); + break; + } + } + + return (ch); +} + +int +txx9_sio_kdbg_wr( u8 ch ) +{ + unsigned int status; + struct uart_txx9_port *up = &serial_txx9_ports[1]; + + if (kgdb_init_count == 0) { + txx9_sio_kdbg_init(1); + kgdb_init_count = 1; + } + + while (1) { + status = sio_in(up, TXX9_SICISR); + if (status & TXX9_SICISR_TRDY) { + if ( ch == '\n' ) { + txx9_sio_kdbg_wr( '\r' ); + } + sio_out(up, TXX9_SITFIFO, (u32)ch ); + + break; + } + } + + return (1); +} +#endif /* CONFIG_KGDB */ + + +/******************************************************************************/ +/* END: KDBG Routines */ +/******************************************************************************/ + static int __init serial_txx9_init(void) { int ret; From Hiroshi_DOYU@montavista.co.jp Thu Jun 9 05:58:36 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Jun 2005 05:58:57 +0100 (BST) Received: from sonicwall.montavista.co.jp ([IPv6:::ffff:202.232.97.131]:7941 "EHLO yuubin.montavista.co.jp") by linux-mips.org with ESMTP id ; Thu, 9 Jun 2005 05:58:05 +0100 Received: from localhost.localdomain (oreo.jp.mvista.com [10.200.16.31]) by yuubin.montavista.co.jp (8.12.5/8.12.5) with SMTP id j594w0S5003819; Thu, 9 Jun 2005 13:58:00 +0900 Date: Thu, 9 Jun 2005 13:59:23 +0900 From: Hiroshi DOYU To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mlachwani@mvista.com Subject: Re: [PATCH 1/1] MIPS 2.6 : minor updates on TX4938(RBHMA4500) Message-Id: <20050609135923.210ebe3e.Hiroshi_DOYU@montavista.co.jp> In-Reply-To: <20050607145724.18d61544.Hiroshi_DOYU@montavista.co.jp> References: <20050607145724.18d61544.Hiroshi_DOYU@montavista.co.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="Multipart=_Thu__9_Jun_2005_13_59_23_+0900_QS36Ed3C71JhyReC" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8059 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Hiroshi_DOYU@montavista.co.jp Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --Multipart=_Thu__9_Jun_2005_13_59_23_+0900_QS36Ed3C71JhyReC Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Hello, I have updated the patch against 2.6.12-rc6 in mips cvs. Hiroshi DOYU On Tue, 7 Jun 2005 14:57:24 +0900 Hiroshi DOYU wrote: > Hello, > > Attached patch includes support of RBHMA4500(TX4938) against > latest mips CVS. > > This patch was originally Manish's work but it has not been > incorporated in CVS yet. So I have just tweaked it against latest > CVS and I confirmed that this worked correctly on RBHMA4500. > > If you have any questions, please let me know. > > Thanks, > -doyu > --Multipart=_Thu__9_Jun_2005_13_59_23_+0900_QS36Ed3C71JhyReC Content-Type: application/octet-stream; name="rbhma4500-main.patch" Content-Disposition: attachment; filename="rbhma4500-main.patch" Content-Transfer-Encoding: base64 ZGlmZiAtWCAvaG9tZS9kb3l1Ly5kb250ZGlmZiAtdXJOYkJ3IGxpbnV4Lm9yaWcvYXJjaC9taXBz L0tjb25maWcgbGludXgvYXJjaC9taXBzL0tjb25maWcKLS0tIGxpbnV4Lm9yaWcvYXJjaC9taXBz L0tjb25maWcJMjAwNS0wNi0wNSAxMjo1NzoyMC4wMDAwMDAwMDAgKzA5MDAKKysrIGxpbnV4L2Fy Y2gvbWlwcy9LY29uZmlnCTIwMDUtMDYtMDcgMTI6MjY6NDcuMDAwMDAwMDAwICswOTAwCkBAIC02 MjgsNiArNjI4LDIzIEBACiAJICBUaGlzIFRvc2hpYmEgYm9hcmQgaXMgYmFzZWQgb24gdGhlIFRY NDkyNyBwcm9jZXNzb3IuIFNheSBZIGhlcmUgdG8KIAkgIHN1cHBvcnQgdGhpcyBtYWNoaW5lIHR5 cGUKIAorY29uZmlnIFRPU0hJQkFfUkJUWDQ5MzgKKwlib29sICJTdXBwb3J0IGZvciBUb3NoaWJh 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b=EZEf6e5Bm4UrkVqKx+Sz67xDOshjrMN5Opm24C4ecjwQfW4YK9+LDouJF0Juv/lTiengeQgcafUnC6tXuOT65TeJlJeOJ9GJGVe2PFPIGyyc4iz7S7HXyxynlK2s2vDXwjxR4CCLgxvFAbbPtP0kX82htPPYtBHrG13Q3lFDQyg= Received: by 10.36.222.24 with SMTP id u24mr411396nzg; Thu, 09 Jun 2005 06:00:22 -0700 (PDT) Received: by 10.36.68.6 with HTTP; Thu, 9 Jun 2005 06:00:22 -0700 (PDT) Message-ID: <6097c4905060906003ca15ec@mail.gmail.com> Date: Thu, 9 Jun 2005 17:00:22 +0400 From: Maxim Osipov Reply-To: maxim@mox.ru To: linux-mips@linux-mips.org Subject: gdb problem Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8060 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maxim.osipov@gmail.com Precedence: bulk X-list: linux-mips Hello, Probably a little off-topic here, but do anyone have a recipe to get remote debugging with gdb + gdbserver working? I have gdb-6.3 build for mips64-linux-gnu and when I try to connect the following error appears: /home/maxim # ./gdbserver 192.168.0.2:5339 /bin/busybox Process /bin/busybox created; pid = 34 Listening on port 5339 Remote debugging from host 192.168.0.2 readchar: Got EOF Remote side has terminated connection. GDBserver will reopen the connection. Listening on port 5339 (gdb) target remote 192.168.0.10:5339 Remote debugging using 192.168.0.10:5339 Couldn't establish connection to remote target Reply contains invalid hex digit 59 Googling for similar problem shows, what some people also faced it, but no solution. Thank you, Maxim From ttruong@broadcom.com Thu Jun 9 18:38:19 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Jun 2005 18:38:42 +0100 (BST) Received: from mms2.broadcom.com ([IPv6:::ffff:216.31.210.18]:48656 "EHLO MMS2.broadcom.com") by linux-mips.org with ESMTP id ; Thu, 9 Jun 2005 18:38:19 +0100 Received: from 10.10.64.121 by MMS2.broadcom.com with SMTP (Broadcom SMTP Relay (Email Firewall v6.1.0)); Thu, 09 Jun 2005 10:37:56 -0700 X-Server-Uuid: 1F20ACF3-9CAF-44F7-AB47-F294E2D5B4EA Received: from mail-irva-8.broadcom.com ([10.10.64.221]) by mail-irva-1.broadcom.com (Post.Office MTA v3.5.3 release 223 ID# 0-72233U7200L2200S0V35) with ESMTP id com for ; Thu, 9 Jun 2005 10:37:54 -0700 Received: from mon-irva-10.broadcom.com (mon-irva-10.broadcom.com [10.10.64.171]) by mail-irva-8.broadcom.com (MOS 3.5.6-GR) with ESMTP id BDD75905; Thu, 9 Jun 2005 10:37:52 -0700 (PDT) Received: from pcirvcttruong2 (dhcp-10-3-136-70.broadcom.com [10.3.136.70]) by mon-irva-10.broadcom.com (8.9.1/8.9.1) with ESMTP id KAA22310 for ; Thu, 9 Jun 2005 10:37:52 -0700 (PDT) Message-ID: <200506091737.KAA22310@mon-irva-10.broadcom.com> From: "Ton Truong" To: linux-mips@linux-mips.org Subject: Member sc_sigset gone in latest 2.6.12-rc5 breaks strace. Date: Thu, 9 Jun 2005 10:37:49 -0700 MIME-Version: 1.0 X-Mailer: Microsoft Office Outlook, Build 11.0.6353 In-Reply-To: <20050606121640.GB6651@linux-mips.org> X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2527 Thread-Index: AcVqkgC7jC5qXNd9RRyydNehJKhNKgChoSWg X-WSS-ID: 6EB6A1FE1VO7019659-01-01 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8061 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ttruong@broadcom.com Precedence: bulk X-list: linux-mips I see that in the rc5 update, MIPS codes have now dropped sc_sigset[4] from struct sigcontext, defined in asm-mips/sigcontext.h. I'd appreciate it if someone provide a brief summary of what needs to be changed for strace to compile or where I can find an strace port that work with the new MIPS codes? Much appreciated. //TT From ralf@linux-mips.org Thu Jun 9 21:51:56 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 09 Jun 2005 21:52:19 +0100 (BST) Received: from alg138.algor.co.uk ([IPv6:::ffff:62.254.210.138]:55530 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Thu, 9 Jun 2005 21:51:56 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j59Kndpp029474; Thu, 9 Jun 2005 21:49:39 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j59Kncjq029473; Thu, 9 Jun 2005 21:49:38 +0100 Date: Thu, 9 Jun 2005 21:49:37 +0100 From: Ralf Baechle To: Ton Truong Cc: linux-mips@linux-mips.org Subject: Re: Member sc_sigset gone in latest 2.6.12-rc5 breaks strace. Message-ID: <20050609204937.GK4927@linux-mips.org> References: <20050606121640.GB6651@linux-mips.org> <200506091737.KAA22310@mon-irva-10.broadcom.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200506091737.KAA22310@mon-irva-10.broadcom.com> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8062 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jun 09, 2005 at 10:37:49AM -0700, Ton Truong wrote: > I see that in the rc5 update, MIPS codes have now dropped > sc_sigset[4] from struct sigcontext, defined in asm-mips/sigcontext.h. I'd > appreciate it if someone provide a brief summary of what needs to be changed > for strace to compile or where I can find an strace port that work with the > new MIPS codes? sc_sigset and the other members that were changed have been unused by the kernel since a very, very long time so whatever strace may have done with that field was probably bogus. Thanks for reporting, something I'm going to look at tomorrow. Ralf From kumba@gentoo.org Fri Jun 10 06:15:20 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Jun 2005 06:15:37 +0100 (BST) Received: from sccrmhc12.comcast.net ([IPv6:::ffff:204.127.202.56]:24477 "EHLO sccrmhc12.comcast.net") by linux-mips.org with ESMTP id ; Fri, 10 Jun 2005 06:15:20 +0100 Received: from [192.168.1.4] (pcp0011842295pcs.waldrf01.md.comcast.net[69.251.97.45]) by comcast.net (sccrmhc12) with ESMTP id <20050610051512012000ute6e>; Fri, 10 Jun 2005 05:15:13 +0000 Message-ID: <42A922A3.9020304@gentoo.org> Date: Fri, 10 Jun 2005 01:18:27 -0400 From: Kumba User-Agent: Mozilla Thunderbird 1.0.2 (Windows/20050317) X-Accept-Language: en-us, en MIME-Version: 1.0 To: gentoo-mips@gentoo.org, gentoo-dev@gentoo.org CC: Linux MIPS List Subject: Gentoo/MIPS SGI LiveCD RC4 (a.k.a., Round 2) Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8063 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips Alright ladies and germs^Wgentlemen, here we go, round #2 of the Mips LiveCD attempt. This time, it works a heck of a lot better than before. Most of theory behind this CD is made possible by Stanislaw Skowronek and his rather revolutionary new bootloader, ARCLoad. Coming soon to a portage tree near you! See the README file at the top level of the livecd directory for a far more thorough description of how it works, how it boots, and how it's more or less put together. the cdboort-ip* files are example sof how the CD boots on my available systems. Your's should more or less closely follow what's shown there. Please report bugs, glitches, feedback, suggestions for improvementm etc, to Bug #95631 at http://bugs.gentoo.org All that said, you can find everything here: http://dev.gentoo.org/~kumba/mips/releases/livecd-rc4/ Tools, mainly just the miniroot (embedded into the kernel) and the CD "real root" can be found in the tools/ subfolder. Other bits and pieces used to make this CD Image will probably appear there over time as well. --Kumba -- Gentoo/MIPS Team Lead Gentoo Foundation Board of Trustees "Such is oft the course of deeds that move the wheels of the world: small hands do them because they must, while the eyes of the great are elsewhere." --Elrond From cw@f00f.org Fri Jun 10 17:39:32 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Jun 2005 17:39:49 +0100 (BST) Received: from ylpvm43-ext.prodigy.net ([IPv6:::ffff:207.115.57.74]:17037 "EHLO ylpvm43.prodigy.net") by linux-mips.org with ESMTP id ; Fri, 10 Jun 2005 17:39:32 +0100 Received: from pimout2-ext.prodigy.net (pimout2-int.prodigy.net [207.115.4.217]) by ylpvm43.prodigy.net (8.12.10 outbound/8.12.10) with ESMTP id j5AGddKd011675; Fri, 10 Jun 2005 12:39:39 -0400 X-ORBL: [63.202.173.158] Received: from taniwha.stupidest.org (adsl-63-202-173-158.dsl.snfc21.pacbell.net [63.202.173.158]) by pimout2-ext.prodigy.net (8.12.10 milter /8.12.10) with ESMTP id j5AGdOM3371188; Fri, 10 Jun 2005 12:39:24 -0400 Received: by taniwha.stupidest.org (Postfix, from userid 38689) id 656CC528F22; Fri, 10 Jun 2005 09:39:24 -0700 (PDT) Date: Fri, 10 Jun 2005 09:39:24 -0700 From: Chris Wedgwood To: Greg Weeks Cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: another 4kc machine check. Message-ID: <494028.547d3e99fefb72449a89b8d1daf681ec.ANY@taniwha.stupidest.org> References: <42553E49.7080004@timesys.com> <4256991C.4020601@timesys.com> <20050408161357.GB19166@linux-mips.org> <4256B524.2080509@timesys.com> <425AD440.5050600@timesys.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <425AD440.5050600@timesys.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8064 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cw@f00f.org Precedence: bulk X-list: linux-mips On Mon, Apr 11, 2005 at 03:47:12PM -0400, Greg Weeks wrote: > This patch appears to fix my machine check problem on the 4kc. The > 4kc shouldn't need an ssnop here, but this appears to fix it. This fix is working for me too --- but I've not heard what the official status of this is and what (if anything) will eventually be committed. Does anyone havean update on this from the MIPS people? From sskowron@ET.PUT.Poznan.PL Fri Jun 10 19:18:00 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Jun 2005 19:18:16 +0100 (BST) Received: from corvus.et.put.poznan.pl ([IPv6:::ffff:150.254.11.9]:29153 "EHLO corvus.et.put.poznan.pl") by linux-mips.org with ESMTP id ; Fri, 10 Jun 2005 19:18:00 +0100 Received: from corvus (corvus.et.put.poznan.pl [150.254.11.9]) by corvus.et.put.poznan.pl (8.11.6+Sun/8.11.6) with ESMTP id j5AIHvQ11244; Fri, 10 Jun 2005 20:17:57 +0200 (MET DST) Received: from helios.et.put.poznan.pl ([150.254.29.65]) by corvus.et.put.poznan.pl (MailMonitor for SMTP v1.2.2 ) ; Fri, 10 Jun 2005 20:17:53 +0200 (MET DST) Received: from localhost (sskowron@localhost) by helios.et.put.poznan.pl (8.11.6+Sun/8.11.6) with ESMTP id j5AIHoa19265; Fri, 10 Jun 2005 20:17:50 +0200 (MET DST) X-Authentication-Warning: helios.et.put.poznan.pl: sskowron owned process doing -bs Date: Fri, 10 Jun 2005 20:17:50 +0200 (MET DST) From: Stanislaw Skowronek To: Kumba cc: gentoo-mips@gentoo.org, gentoo-dev@gentoo.org, Linux MIPS List Subject: Re: Gentoo/MIPS SGI LiveCD RC4 (a.k.a., Round 2) In-Reply-To: <42A922A3.9020304@gentoo.org> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8065 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sskowron@ET.PUT.Poznan.PL Precedence: bulk X-list: linux-mips ARCLoad 0.41 now supports IP27. Kumba, fix your CD :) Stanislaw Skowronek --<=>-- "There is no pain, you are receding... A distant ship, smoke on the horizon. You are only coming through in waves, Your lips move, but I can't hear what you're saying." From kevin.m.turner@pobox.com Fri Jun 10 22:05:58 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Jun 2005 22:06:14 +0100 (BST) Received: from orb.pobox.com ([IPv6:::ffff:207.8.226.5]:11718 "EHLO orb.pobox.com") by linux-mips.org with ESMTP id ; Fri, 10 Jun 2005 22:05:58 +0100 Received: from orb (localhost [127.0.0.1]) by orb.pobox.com (Postfix) with ESMTP id D46161E9D for ; Fri, 10 Jun 2005 17:05:48 -0400 (EDT) Received: from troglodyte.asianpear (c-24-21-141-200.hsd1.or.comcast.net [24.21.141.200]) (using SSLv3 with cipher RC4-MD5 (128/128 bits)) (No client certificate requested) by orb.sasl.smtp.pobox.com (Postfix) with ESMTP id 8C7FD8B for ; Fri, 10 Jun 2005 17:05:48 -0400 (EDT) Subject: [PATCH 2.4] cleanup printk __FUNCTION__ in clocks.c From: Kevin Turner To: linux-mips Content-Type: text/plain Date: Fri, 10 Jun 2005 14:05:53 -0700 Message-Id: <1118437553.1513.22.camel@troglodyte.asianpear> Mime-Version: 1.0 X-Mailer: Evolution 2.2.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8066 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevin.m.turner@pobox.com Precedence: bulk X-list: linux-mips The following patch against linux_2_4 cleans up this little compilation error: clocks.c: In function `set_au1x00_lcd_clock': clocks.c:89: error: parse error before string constant clocks.c:90: warning: left-hand operand of comma expression has no effect clocks.c:90: error: parse error before ')' token Index: arch/mips/au1000/common/clocks.c =================================================================== RCS file: /home/kevint/whdd/linux-mips-cvs/linux/arch/mips/au1000/common/clocks.c,v retrieving revision 1.2.2.5 diff -u -r1.2.2.5 clocks.c --- arch/mips/au1000/common/clocks.c 12 May 2004 07:31:08 -0000 1.2.2.5 +++ arch/mips/au1000/common/clocks.c 10 Jun 2005 20:55:59 -0000 @@ -85,9 +85,8 @@ lcd_clock = sys_busclk / 4; if (lcd_clock > 50000) /* Epson MAX */ - printk(__FUNCTION__ - ": warning: LCD clock too high (%d KHz)\n", - lcd_clock); + printk("%s: warning: LCD clock too high (%d KHz)\n", + __FUNCTION__, lcd_clock); } unsigned int get_au1x00_lcd_clock(void) -- The moon is waxing crescent, 12.3% illuminated, 3.4 days old. From kevin.m.turner@pobox.com Fri Jun 10 22:22:08 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 10 Jun 2005 22:22:23 +0100 (BST) Received: from orb.pobox.com ([IPv6:::ffff:207.8.226.5]:57543 "EHLO orb.pobox.com") by linux-mips.org with ESMTP id ; Fri, 10 Jun 2005 22:22:08 +0100 Received: from orb (localhost [127.0.0.1]) by orb.pobox.com (Postfix) with ESMTP id 9FD2D1E12 for ; Fri, 10 Jun 2005 17:21:59 -0400 (EDT) Received: from troglodyte.asianpear (c-24-21-141-200.hsd1.or.comcast.net [24.21.141.200]) (using SSLv3 with cipher RC4-MD5 (128/128 bits)) (No client certificate requested) by orb.sasl.smtp.pobox.com (Postfix) with ESMTP id 55D498B for ; Fri, 10 Jun 2005 17:21:59 -0400 (EDT) Subject: [PATCH 2.4] inlines in au1000_eth.c From: Kevin Turner To: linux-mips Content-Type: text/plain Date: Fri, 10 Jun 2005 14:22:04 -0700 Message-Id: <1118438524.1513.28.camel@troglodyte.asianpear> Mime-Version: 1.0 X-Mailer: Evolution 2.2.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8067 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevin.m.turner@pobox.com Precedence: bulk X-list: linux-mips The following patch against linux_2_4 fixes this sort of compilation error with gcc 3.4: au1000_eth.c: In function `au1000_init_module': au1000_eth.c:97: sorry, unimplemented: inlining failed in call to 'str2eaddr': function body not available au1000_eth.c:1219: sorry, unimplemented: called from here I'm not wholly sure it's the Right Thing, as I define str2eaddr in au1000_eth.c, which makes for more code duplication. Index: drivers/net/au1000_eth.c =================================================================== RCS file: /home/kevint/whdd/linux-mips-cvs/linux/drivers/net/au1000_eth.c,v retrieving revision 1.5.2.33 diff -u -r1.5.2.33 au1000_eth.c --- drivers/net/au1000_eth.c 26 Nov 2004 08:40:13 -0000 1.5.2.33 +++ drivers/net/au1000_eth.c 10 Jun 2005 20:56:19 -0000 @@ -90,12 +90,12 @@ static int mdio_read(struct net_device *, int, int); static void mdio_write(struct net_device *, int, int, u16); static void dump_mii(struct net_device *dev, int phy_id); +static inline void str2eaddr(unsigned char *ea, unsigned char *str); +static inline unsigned char str2hexnum(unsigned char c); // externs extern void ack_rise_edge_irq(unsigned int); extern int get_ethernet_addr(char *ethernet_addr); -extern inline void str2eaddr(unsigned char *ea, unsigned char *str); -extern inline unsigned char str2hexnum(unsigned char c); extern char * __init prom_getcmdline(void); /* @@ -146,6 +146,32 @@ "100BaseT", "100BaseTX", "100BaseFX" }; +static inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for (i = 0; i < 6; i++) { + unsigned char num; + + if ((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +static inline unsigned char str2hexnum(unsigned char c) +{ + if(c >= '0' && c <= '9') + return c - '0'; + if(c >= 'a' && c <= 'f') + return c - 'a' + 10; + if(c >= 'A' && c <= 'F') + return c - 'A' + 10; + return 0; /* foo */ +} + int bcm_5201_init(struct net_device *dev, int phy_addr) { s16 data; -- The moon is waxing crescent, 12.3% illuminated, 3.4 days old. From maillist@jg555.com Sat Jun 11 19:54:57 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 11 Jun 2005 19:55:13 +0100 (BST) Received: from 64-30-195-78.dsl.linkline.com ([IPv6:::ffff:64.30.195.78]:1731 "EHLO jg555.com") by linux-mips.org with ESMTP id ; Sat, 11 Jun 2005 19:54:57 +0100 Received: from [172.16.0.55] ([::ffff:172.16.0.55]) (AUTH: PLAIN root, TLS: TLSv1/SSLv3,256bits,AES256-SHA) by jg555.com with esmtp; Sat, 11 Jun 2005 11:54:53 -0700 id 001CCECD.42AB337D.00003CD5 Message-ID: <42AB3366.8030206@jg555.com> Date: Sat, 11 Jun 2005 11:54:30 -0700 From: Jim Gifford User-Agent: Mozilla Thunderbird 1.0 (Windows/20041206) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Linux MIPS List Subject: Building o32 glibc on mips64 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8068 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maillist@jg555.com Precedence: bulk X-list: linux-mips Anyone got any ideas on how to fix this. I'm using binutils 2.16, gcc 3.4.4, and glibc-2.3.5 with the syscall patch. Looks like socket.S is not being generated. mips64el-unknown-linux-gnu-gcc -mabi=32 ../sysdeps/unix/sysv/linux/recv.S -c - I../include -I. -I/usr/src/glibc-build/socket -I.. -I../libio -I/usr/src/glibc- build -I../sysdeps/mips/elf -I../libidn/sysdeps/unix -I../linuxthreads/sysdeps/u nix/sysv/linux/mips -I../linuxthreads/sysdeps/unix/sysv/linux -I../linuxthreads/ sysdeps/pthread -I../sysdeps/pthread -I../linuxthreads/sysdeps/unix/sysv -I../li nuxthreads/sysdeps/unix -I../linuxthreads/sysdeps/mips -I../sysdeps/unix/sysv/li nux/mips/mips32 -I../sysdeps/unix/sysv/linux/mips -I../sysdeps/unix/sysv/linux - I../sysdeps/gnu -I../sysdeps/unix/common -I../sysdeps/unix/mman -I../sysdeps/uni x/inet -I../sysdeps/unix/sysv -I../sysdeps/unix/mips/mips32 -I../sysdeps/unix/mi ps -I../sysdeps/unix -I../sysdeps/posix -I../sysdeps/mips/mips32 -I../sysdeps/mi ps -I../sysdeps/ieee754/flt-32 -I../sysdeps/ieee754/dbl-64 -I../sysdeps/wordsize -32 -I../sysdeps/mips/fpu -I../sysdeps/ieee754 -I../sysdeps/generic/elf -I../sys deps/generic -D_LIBC_REENTRANT -include ../include/libc-symbols.h -DPIC -D ASSEMBLER -g -o /usr/src/glibc-build/socket/recv.o -MD -MP -MF /usr/src/glibc -build/socket/recv.o.dt -MT /usr/src/glibc-build/socket/recv.o ../sysdeps/unix/sysv/linux/recv.S:5:20: socket.S: No such file or directory make[2]: *** [/usr/src/glibc-build/socket/recv.o] Error 1 make[2]: Leaving directory `/usr/src/glibc-2.3.5/socket' make[1]: *** [socket/subdir_lib] Error 2 make[1]: Leaving directory `/usr/src/glibc-2.3.5' make: *** [all] Error 2 root:/usr/src/glibc-build# -- ---- Jim Gifford maillist@jg555.com From sundarapandian.andithevar@philips.com Mon Jun 13 06:15:14 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 06:15:30 +0100 (BST) Received: from gw-eur4.philips.com ([IPv6:::ffff:161.85.125.10]:38048 "EHLO gw-eur4.philips.com") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 06:15:14 +0100 Received: from smtpscan-eur4.philips.com (smtpscan-eur4.mail.philips.com [130.144.57.167]) by gw-eur4.philips.com (Postfix) with ESMTP id F08D74971E for ; Mon, 13 Jun 2005 05:15:02 +0000 (UTC) Received: from smtpscan-eur4.philips.com (localhost [127.0.0.1]) by localhost.philips.com (Postfix) with ESMTP id C7A659C for ; Mon, 13 Jun 2005 05:15:02 +0000 (GMT) Received: from smtprelay-eur2.philips.com (smtprelay-eur2.philips.com [130.144.57.171]) by smtpscan-eur4.philips.com (Postfix) with ESMTP id A6C51A1 for ; Mon, 13 Jun 2005 05:15:02 +0000 (GMT) Received: from ehvrmh02.diamond.philips.com (ehvrmh02-srv.diamond.philips.com [130.139.27.125]) by smtprelay-eur2.philips.com (Postfix) with ESMTP id 6FD2940 for ; Mon, 13 Jun 2005 05:15:02 +0000 (GMT) Subject: XIO driver development To: linux-mips@linux-mips.org X-Mailer: Lotus Notes Release 6.0.3 September 26, 2003 Message-ID: From: Sundarapandian Andithevar Date: Mon, 13 Jun 2005 10:38:48 +0530 X-MIMETrack: Serialize by Router on ehvrmh02/H/SERVER/PHILIPS(Release 6.5.3FP1HF80 | March 11, 2005) at 13/06/2005 07:14:22 MIME-Version: 1.0 Content-type: text/plain; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8069 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sundarapandian.andithevar@philips.com Precedence: bulk X-list: linux-mips Hi, I came across XIO layer development in MIPS at http://www.linux-mips.org/wiki/index.php/XIO. Does anybody know the current status of the development??? Regards, Sundar. From sskowron@ET.PUT.Poznan.PL Mon Jun 13 06:46:38 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 06:46:54 +0100 (BST) Received: from corvus.et.put.poznan.pl ([IPv6:::ffff:150.254.11.9]:3029 "EHLO corvus.et.put.poznan.pl") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 06:46:38 +0100 Received: from corvus (corvus.et.put.poznan.pl [150.254.11.9]) by corvus.et.put.poznan.pl (8.11.6+Sun/8.11.6) with ESMTP id j5D5kZQ05371; Mon, 13 Jun 2005 07:46:35 +0200 (MET DST) Received: from helios.et.put.poznan.pl ([150.254.29.65]) by corvus.et.put.poznan.pl (MailMonitor for SMTP v1.2.2 ) ; Mon, 13 Jun 2005 07:46:32 +0200 (MET DST) Received: from localhost (sskowron@localhost) by helios.et.put.poznan.pl (8.11.6+Sun/8.11.6) with ESMTP id j5D5kUX17076; Mon, 13 Jun 2005 07:46:30 +0200 (MET DST) X-Authentication-Warning: helios.et.put.poznan.pl: sskowron owned process doing -bs Date: Mon, 13 Jun 2005 07:46:30 +0200 (MET DST) From: Stanislaw Skowronek To: Sundarapandian Andithevar cc: linux-mips@linux-mips.org Subject: Re: XIO driver development In-Reply-To: Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8070 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sskowron@ET.PUT.Poznan.PL Precedence: bulk X-list: linux-mips Currently - on hold. However, seeing the company you represent... this is not the XIO you are looking for (probably). This is SGI XIO, not Philips XIO ("Hey, X is a cool letter, how do we call our bus?"). Stanislaw Skowronek From ralf@linux-mips.org Mon Jun 13 11:10:46 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 11:11:01 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:5917 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 11:10:46 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j5DA84Ob011259; Mon, 13 Jun 2005 11:08:04 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j59M1lv1004830; Thu, 9 Jun 2005 23:01:47 +0100 Date: Thu, 9 Jun 2005 23:01:47 +0100 From: Ralf Baechle To: Ton Truong Cc: linux-mips@linux-mips.org Subject: Re: Member sc_sigset gone in latest 2.6.12-rc5 breaks strace. Message-ID: <20050609220147.GA4802@linux-mips.org> References: <20050606121640.GB6651@linux-mips.org> <200506091737.KAA22310@mon-irva-10.broadcom.com> <20050609204937.GK4927@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20050609204937.GK4927@linux-mips.org> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8071 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jun 09, 2005 at 09:49:37PM +0100, Ralf Baechle wrote: > > I see that in the rc5 update, MIPS codes have now dropped > > sc_sigset[4] from struct sigcontext, defined in asm-mips/sigcontext.h. I'd > > appreciate it if someone provide a brief summary of what needs to be changed > > for strace to compile or where I can find an strace port that work with the > > new MIPS codes? > > sc_sigset and the other members that were changed have been unused by the > kernel since a very, very long time so whatever strace may have done with > that field was probably bogus. > > Thanks for reporting, something I'm going to look at tomorrow. Ok, it was just too trivial. Here's an untested patch. Ralf signal.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: strace-cvs/signal.c =================================================================== --- strace-cvs.orig/signal.c 2005-06-09 22:56:14.000000000 +0100 +++ strace-cvs/signal.c 2005-06-09 22:56:27.000000000 +0100 @@ -1420,7 +1420,7 @@ if (umove(tcp, sp, &sc) < 0) return 0; tcp->u_arg[0] = 1; - tcp->u_arg[1] = sc.sc_sigset; + tcp->u_arg[1] = &sc + 1; } else { tcp->u_rval = tcp->u_error = 0; if(tcp->u_arg[0] == 0) From ralf@linux-mips.org Mon Jun 13 12:02:24 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 12:02:51 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:48924 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 12:02:24 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j5DAxjPh020970; Mon, 13 Jun 2005 11:59:45 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j5DAxjYF020943; Mon, 13 Jun 2005 11:59:45 +0100 Date: Mon, 13 Jun 2005 11:59:44 +0100 From: Ralf Baechle To: qemu-devel@nongnu.org, linux-mips@linux-mips.org Cc: Jocelyn Mayer , Fabrice Bellard Subject: Qemu for MIPS Message-ID: <20050613105944.GA19704@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8072 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips I've posted updated Qemu patches on ftp://ftp.linux-mips.org/pub/linux/mips/qemu http://www.linux-mips.org/wiki/index.php/Qemu Enhancements over last week's patches: o The count/compare interrupt will now properly be delivered. o mfc0 will now return the proper value for the EXL and ERL flags o eret will now consider the value of ERL and EXL. o i8259 PIC is now properly cascaded to a CPU interrupt. o An ISA NE2000 card will now be emulated. o The CPU's random register now considers the value of the wired register The new kernel patch is against the latest Linux/MIPS CVS kernel du jour 2.6.12-rc6 and has been updated to match Qemu's improvments. Known bugs: o ll/sc don't use a ll_bit like the real hardware thus right now any atomic functions aren't really atomic. o ll/sc really should be watching a physical not a virtual address or they won't do much useful on any kind of shared memory structure. o MIPS documentation documents the lladdr register to contain the virtual address of the location being watched but about every implementation since the R4000 actually keeps the physical address there - and documents that as an erratum even though it actually the sensible thing to do. We should do the same. Fortunately nothing that I know of actually relies on the content of the lladdr register, so this one is cosmetic. Last, not least, this is what you've been waiting for: [root@dea qemu-mips]# mips-softmmu/qemu-system-mips -kernel ~ralf/src/linux/linux-cvs/arch/mips/boot/vmlinux.bin -m 16 -nographic nb_nics = 1 Connected to host network interface: tun0 /etc/qemu-ifup tun0 + ifconfig tun0 up + brctl addbr qnet device qnet already exists; can't create bridge with the same name + brctl addif qnet tun0 + ifconfig qnet 172.20.0.1 (qemu) mips_r4k_init: start mips_r4k_init: load BIOS '/usr/local/share/qemu/mips_bios.bin' size 131072 Linux version 2.6.12-rc5 (ralf@dea.linux-mips.net) (gcc version 3.4.3) #257 Mon Jun 13 02:58:23 BST 2005 CPU revision is: 00018000 Determined physical RAM map: memory: 01000000 @ 00000000 (usable) On node 0 totalpages: 4096 DMA zone: 4096 pages, LIFO batch:1 Normal zone: 0 pages, LIFO batch:1 HighMem zone: 0 pages, LIFO batch:1 Built 1 zonelists Kernel command line: console=ttyS0 debug ip=172.20.0.2:172.20.0.1::255.255.0.0 Primary instruction cache 2kB, physically tagged, 2-way, linesize 16 bytes. Primary data cache 2kB, 2-way, linesize 16 bytes. Synthesized TLB refill handler (19 instructions). Synthesized TLB load handler fastpath (31 instructions). Synthesized TLB store handler fastpath (31 instructions). Synthesized TLB modify handler fastpath (30 instructions). PID hash table entries: 128 (order: 7, 2048 bytes) Using 100.000 MHz high precision timer. Console: colour VGA+ 80x25 Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory: 14464k/16384k available (1293k kernel code, 1900k reserved, 190k data, 104k init, 0k highmem) Calibrating delay loop... 144.58 BogoMIPS (lpj=722944) Mount-cache hash table entries: 512 Checking for 'wait' instruction... available. NET: Registered protocol family 16 Serial: 8250/16550 driver $Revision: 1.90 $ 8 ports, IRQ sharing disabled ttyS0 at I/O 0x3f8 (irq = 4) is a 16450 io scheduler noop registered ne.c:v1.10 9/23/94 Donald Becker (becker@scyld.com) Last modified Nov 1, 2000 by Paul Gortmaker NE*000 ethercard probe at 0x300: 52 54 00 12 34 56 eth0: NE2000 found at 0x300, using IRQ 9. NET: Registered protocol family 2 IP: routing cache hash table of 512 buckets, 4Kbytes TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes) TCP: Hash tables configured (established 1024 bind 1024) NET: Registered protocol family 1 NET: Registered protocol family 17 IP-Config: Complete: device=eth0, addr=172.20.0.2, mask=255.255.0.0, gw=255.255.255.255, host=172.20.0.2, domain=, nis-domain=(none), bootserver=172.20.0.1, rootserver=172.20.0.1, rootpath= Looking up port of RPC 100003/2 on 172.20.0.1 Looking up port of RPC 100005/1 on 172.20.0.1 VFS: Mounted root (nfs filesystem) readonly. Freeing unused kernel memory: 104k freed Kernel panic - not syncing: No init found. Try passing init= option to kernel. Which is a bug - there is a valid root filesystem. Something for tomorrow. Enjoy, Ralf From dom@mips.com Mon Jun 13 12:44:40 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 12:44:58 +0100 (BST) Received: from alg145.algor.co.uk ([IPv6:::ffff:62.254.210.145]:27400 "EHLO dmz.algor.co.uk") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 12:44:40 +0100 Received: from alg158.algor.co.uk ([62.254.210.158] helo=olympia.mips.com) by dmz.algor.co.uk with esmtp (Exim 3.35 #1 (Debian)) id 1Dhnem-0007Mc-00; Mon, 13 Jun 2005 13:03:08 +0100 Received: from gladsmuir.algor.co.uk ([172.20.192.66] helo=gladsmuir) by olympia.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1DhnML-0003ng-00; Mon, 13 Jun 2005 12:44:05 +0100 From: Dominic Sweetman MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <17069.29065.124810.728626@gargle.gargle.HOWL> Date: Mon, 13 Jun 2005 12:44:09 +0100 To: Ralf Baechle Cc: qemu-devel@nongnu.org, linux-mips@linux-mips.org, Jocelyn Mayer , Fabrice Bellard Subject: Re: Qemu for MIPS In-Reply-To: <20050613105944.GA19704@linux-mips.org> References: <20050613105944.GA19704@linux-mips.org> X-Mailer: VM 7.17 under 21.4 (patch 15) "Security Through Obscurity" XEmacs Lucid X-MTUK-Scanner: Found to be clean X-MTUK-SpamCheck: not spam (whitelisted), SpamAssassin (score=-4.834, required 4, AWL, BAYES_00) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8073 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dom@mips.com Precedence: bulk X-list: linux-mips Ralf Baechle (ralf@linux-mips.org) writes: > I've posted updated Qemu patches on > > ftp://ftp.linux-mips.org/pub/linux/mips/qemu > http://www.linux-mips.org/wiki/index.php/Qemu > > Enhancements over last week's patches: > > o The count/compare interrupt will now properly be delivered. > o mfc0 will now return the proper value for the EXL and ERL flags > o eret will now consider the value of ERL and EXL. > o i8259 PIC is now properly cascaded to a CPU interrupt. > o An ISA NE2000 card will now be emulated. > o The CPU's random register now considers the value of the wired register Great stuff... > Known bugs: > > o ll/sc don't use a ll_bit like the real hardware thus right now any atomic > functions aren't really atomic. I suppose you know that the CPUs all implement "break link on exception" by zeroing the link bit on an 'eret'? That doesn't sound too hard... > o ll/sc really should be watching a physical not a virtual address or they > won't do much useful on any kind of shared memory structure. > o MIPS documentation documents the lladdr register to contain the virtual > address of the location being watched but about every implementation > since the R4000 actually keeps the physical address there - and documents > that as an erratum even though it actually the sensible thing to do. We > should do the same. Fortunately nothing that I know of actually relies > on the content of the lladdr register, so this one is cosmetic. Arguably, an emulator should not provide the LLaddr register at all. It's optional and "only available for debug" - and probably such debugging is possible another way in an emulator. Robust software shouldn't depend on assuming the contents make sense. > ... > Kernel panic - not syncing: No init found. Try passing init= option to kernel. > > Which is a bug - there is a valid root filesystem. Something for tomorrow. Not quite there yet... but well done, again. -- Dominic From ralf@linux-mips.org Mon Jun 13 13:43:59 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 13:44:15 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:25614 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 13:43:59 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j5DCfMNC024168; Mon, 13 Jun 2005 13:41:22 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j5DCfM2F024167; Mon, 13 Jun 2005 13:41:22 +0100 Date: Mon, 13 Jun 2005 13:41:22 +0100 From: Ralf Baechle To: qemu-devel@nongnu.org, linux-mips@linux-mips.org Cc: Jocelyn Mayer Subject: Re: [Qemu-devel] Qemu for MIPS Message-ID: <20050613124121.GA23326@linux-mips.org> References: <20050613105944.GA19704@linux-mips.org> <1118663437.8329.4.camel@sd023.hel.movial.fi> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1118663437.8329.4.camel@sd023.hel.movial.fi> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8074 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 13, 2005 at 02:50:37PM +0300, Timo Savola wrote: > Are there any plans for supporting user-mode MIPS emulation? At some point certainly but right now my priority is full system emulation. Ralf From ralf@linux-mips.org Mon Jun 13 13:58:50 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 13:59:06 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:27929 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 13:58:50 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j5DCuBD9024666; Mon, 13 Jun 2005 13:56:11 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j5DCuA15024665; Mon, 13 Jun 2005 13:56:10 +0100 Date: Mon, 13 Jun 2005 13:56:10 +0100 From: Ralf Baechle To: Dominic Sweetman Cc: qemu-devel@nongnu.org, linux-mips@linux-mips.org, Jocelyn Mayer , Fabrice Bellard Subject: Re: Qemu for MIPS Message-ID: <20050613125610.GB4890@linux-mips.org> References: <20050613105944.GA19704@linux-mips.org> <17069.29065.124810.728626@gargle.gargle.HOWL> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <17069.29065.124810.728626@gargle.gargle.HOWL> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8075 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 13, 2005 at 12:44:09PM +0100, Dominic Sweetman wrote: > > Known bugs: > > > > o ll/sc don't use a ll_bit like the real hardware thus right now any atomic > > functions aren't really atomic. > > I suppose you know that the CPUs all implement "break link on > exception" by zeroing the link bit on an 'eret'? That doesn't sound > too hard... It's not hard to add the llbit indeed - maybe I'm trying to hard to be obscure use compatible. Generally Qemu is trading the highest accuracy of emulation for speed ... > Arguably, an emulator should not provide the LLaddr register at all. > It's optional and "only available for debug" - and probably such > debugging is possible another way in an emulator. Robust software > shouldn't depend on assuming the contents make sense. The only use I've seen for this register is having it being used as a cp0 scratch register allowing to save the entire 31 GPRs. Very old Linux/MIPS used to do that but it doesn't match the reality of MIPS ABIs, so I gave up on that very soon. Like 11 years agp :) > Not quite there yet... but well done, again. Ralf From madprops@gmx.net Mon Jun 13 15:06:41 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 15:06:58 +0100 (BST) Received: from mail.gmx.net ([IPv6:::ffff:213.165.64.20]:20150 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Mon, 13 Jun 2005 15:06:41 +0100 Received: (qmail 28575 invoked by uid 0); 13 Jun 2005 14:06:34 -0000 Received: from 129.13.186.3 by www68.gmx.net with HTTP; Mon, 13 Jun 2005 16:06:34 +0200 (MEST) Date: Mon, 13 Jun 2005 16:06:34 +0200 (MEST) From: "Mad Props" To: linux-mips@linux-mips.org MIME-Version: 1.0 Subject: tlb magic X-Priority: 3 (Normal) X-Authenticated: #24801140 Message-ID: <31886.1118671594@www68.gmx.net> X-Mailer: WWW-Mail 1.6 (Global Message Exchange) X-Flags: 0001 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8076 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: madprops@gmx.net Precedence: bulk X-list: linux-mips Hi, I'm trying to understand how to implement an TLB Exception handler for a MIPS32 ( 4KC ). As far as I got it, it makes sense to locate the user process page tables in kseg2 to save physical memory. The book I'm reading states another advantage using kseg2. I'm not quite sure what they mean, stating that "It provides an easy mechanism for remapping a new user page table when changing context, without having to find enough virtual addresses in the OS to map all the page tables at once. Instead, you just change the ASID value, and the kseg2 pointer to the page table is now automatically remapped onto the correct page table. It's nearly magic." 1. Is there only one kseg2 containing all page tables for 256 processes, i.e. only one ASID is used or 2. Has each page table it's own address space ( using different ASID for those addresses in kseg2 ) 3. Will I need another untranslated page table in kseg0/kseg1 to translate kseg2 addresses ? 4. What is this kseg2 pointer they are talking about ? 5. Are they talking about the ASID in EntryHi ? 6. Where is the magic ? Would be smashing if anybody could help me out. Kind regards, Thomas -- Geschenkt: 3 Monate GMX ProMail gratis + 3 Ausgaben stern gratis ++ Jetzt anmelden & testen ++ http://www.gmx.net/de/go/promail ++ From macro@linux-mips.org Mon Jun 13 20:47:27 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 20:47:42 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([IPv6:::ffff:153.19.208.7]:2066 "EHLO pollux.ds.pg.gda.pl") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 20:47:26 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id DD2CDF5981; Mon, 13 Jun 2005 21:47:19 +0200 (CEST) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 01017-05; Mon, 13 Jun 2005 21:47:19 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id AB577F596E; Mon, 13 Jun 2005 21:47:19 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.3/8.13.1) with ESMTP id j5DJlOLS026668; Mon, 13 Jun 2005 21:47:24 +0200 Date: Mon, 13 Jun 2005 20:47:35 +0100 (BST) From: "Maciej W. Rozycki" To: Kevin Turner Cc: linux-mips Subject: Re: [PATCH 2.4] inlines in au1000_eth.c In-Reply-To: <1118438524.1513.28.camel@troglodyte.asianpear> Message-ID: References: <1118438524.1513.28.camel@troglodyte.asianpear> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.85.1/935/Mon Jun 13 18:27:50 2005 on piorun.ds.pg.gda.pl X-Virus-Status: Clean X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8077 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, 10 Jun 2005, Kevin Turner wrote: > The following patch against linux_2_4 fixes this sort of compilation > error with gcc 3.4: > > au1000_eth.c: In function `au1000_init_module': > au1000_eth.c:97: sorry, unimplemented: inlining failed in call to 'str2eaddr': function body not available > au1000_eth.c:1219: sorry, unimplemented: called from here > > I'm not wholly sure it's the Right Thing, as I define str2eaddr in > au1000_eth.c, which makes for more code duplication. Note that by somebody's "brillant" idea "inline" is a macro that expands to "inline __attribute__((always_inline))". That said, "inline" in a function prototype doesn't make much sense anyway. In this case simply removing the qualifier will let code use the implementation from arch/mips/au1000/common/prom.c. As a side note it's quite amazing how duplicate copies of a function get scattered throughout the tree... Maciej From drow@nevyn.them.org Mon Jun 13 20:56:07 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 20:56:22 +0100 (BST) Received: from nevyn.them.org ([IPv6:::ffff:66.93.172.17]:54718 "EHLO nevyn.them.org") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 20:56:07 +0100 Received: from drow by nevyn.them.org with local (Exim 4.50) id 1Dhv2Q-0000z9-7Y; Mon, 13 Jun 2005 15:56:02 -0400 Date: Mon, 13 Jun 2005 15:56:02 -0400 From: Daniel Jacobowitz To: Jim Gifford Cc: Linux MIPS List Subject: Re: Building o32 glibc on mips64 Message-ID: <20050613195602.GA3739@nevyn.them.org> References: <42AB3366.8030206@jg555.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <42AB3366.8030206@jg555.com> User-Agent: Mutt/1.5.8i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8078 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@debian.org Precedence: bulk X-list: linux-mips On Sat, Jun 11, 2005 at 11:54:30AM -0700, Jim Gifford wrote: > Anyone got any ideas on how to fix this. I'm using binutils 2.16, gcc > 3.4.4, and glibc-2.3.5 with the syscall patch. Looks like socket.S is > not being generated. I have not tried the 2.3.x series glibcs on MIPS64. I recommend you use glibc HEAD for now instead, unless you're interested in tracking down this sort of problem. -- Daniel Jacobowitz CodeSourcery, LLC From macro@linux-mips.org Mon Jun 13 21:05:50 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 21:06:04 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([IPv6:::ffff:153.19.208.7]:44295 "EHLO pollux.ds.pg.gda.pl") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 21:05:50 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 7A3E6F5991; Mon, 13 Jun 2005 22:05:43 +0200 (CEST) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 00896-07; Mon, 13 Jun 2005 22:05:43 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 30E74F598B; Mon, 13 Jun 2005 22:05:43 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.3/8.13.1) with ESMTP id j5DK5m3u027731; Mon, 13 Jun 2005 22:05:48 +0200 Date: Mon, 13 Jun 2005 21:05:59 +0100 (BST) From: "Maciej W. Rozycki" To: Daniel Jacobowitz Cc: Jim Gifford , Linux MIPS List Subject: Re: Building o32 glibc on mips64 In-Reply-To: <20050613195602.GA3739@nevyn.them.org> Message-ID: References: <42AB3366.8030206@jg555.com> <20050613195602.GA3739@nevyn.them.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.85.1/935/Mon Jun 13 18:27:50 2005 on piorun.ds.pg.gda.pl X-Virus-Status: Clean X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8079 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 13 Jun 2005, Daniel Jacobowitz wrote: > I have not tried the 2.3.x series glibcs on MIPS64. I recommend you > use glibc HEAD for now instead, unless you're interested in tracking > down this sort of problem. FYI, I've been able to build glibc 2.3.5 with GCC 4.0.0 for mips64el-linux (n64) with minimal patching. I think what's only really required is that patch by Richard Sandiford that stays suspended in the glibc Bugzilla. For o32 glibc may have to be configured for "mips{,el}-linux" (as o32 isn't MIPS64 at all), but that's a pure guess -- I haven't checked the scripts for that requirement. Do you think HEAD is stable enough for a non-glibc developer? It's soon after a fork after all, so I'd expect more serious changes to be applied nowadays. Maciej From hch@lst.de Mon Jun 13 21:08:32 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 21:08:47 +0100 (BST) Received: from verein.lst.de ([IPv6:::ffff:213.95.11.210]:56978 "EHLO mail.lst.de") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 21:08:32 +0100 Received: from verein.lst.de (localhost [127.0.0.1]) by mail.lst.de (8.12.3/8.12.3/Debian-7.1) with ESMTP id j5DK8K6t029893 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Mon, 13 Jun 2005 22:08:21 +0200 Received: (from hch@localhost) by verein.lst.de (8.12.3/8.12.3/Debian-6.6) id j5DK8KUn029891; Mon, 13 Jun 2005 22:08:20 +0200 Date: Mon, 13 Jun 2005 22:08:20 +0200 From: Christoph Hellwig To: "Maciej W. Rozycki" Cc: Daniel Jacobowitz , Jim Gifford , Linux MIPS List Subject: Re: Building o32 glibc on mips64 Message-ID: <20050613200820.GA29872@lst.de> References: <42AB3366.8030206@jg555.com> <20050613195602.GA3739@nevyn.them.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.3.28i X-Scanned-By: MIMEDefang 2.39 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8080 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hch@lst.de Precedence: bulk X-list: linux-mips On Mon, Jun 13, 2005 at 09:05:59PM +0100, Maciej W. Rozycki wrote: > On Mon, 13 Jun 2005, Daniel Jacobowitz wrote: > > > I have not tried the 2.3.x series glibcs on MIPS64. I recommend you > > use glibc HEAD for now instead, unless you're interested in tracking > > down this sort of problem. > > FYI, I've been able to build glibc 2.3.5 with GCC 4.0.0 for > mips64el-linux (n64) with minimal patching. I think what's only really > required is that patch by Richard Sandiford that stays suspended in the > glibc Bugzilla. > > For o32 glibc may have to be configured for "mips{,el}-linux" (as o32 > isn't MIPS64 at all), but that's a pure guess -- I haven't checked the > scripts for that requirement. > > Do you think HEAD is stable enough for a non-glibc developer? It's soon > after a fork after all, so I'd expect more serious changes to be applied > nowadays. Btw, what is the chance to see a biarch toolchain for mips? It seems all linux architectures with 32bit and 64bit variants seem to have one these days, except mips. From macro@linux-mips.org Mon Jun 13 21:18:49 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 21:19:04 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([IPv6:::ffff:153.19.208.7]:10756 "EHLO pollux.ds.pg.gda.pl") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 21:18:49 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id D1FEEF598B; Mon, 13 Jun 2005 22:18:38 +0200 (CEST) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 25845-10; Mon, 13 Jun 2005 22:18:38 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 15C17F5981; Mon, 13 Jun 2005 22:18:38 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.3/8.13.1) with ESMTP id j5DKIQK4028469; Mon, 13 Jun 2005 22:18:26 +0200 Date: Mon, 13 Jun 2005 21:18:38 +0100 (BST) From: "Maciej W. Rozycki" To: Christoph Hellwig Cc: Daniel Jacobowitz , Jim Gifford , Linux MIPS List Subject: Re: Building o32 glibc on mips64 In-Reply-To: <20050613200820.GA29872@lst.de> Message-ID: References: <42AB3366.8030206@jg555.com> <20050613195602.GA3739@nevyn.them.org> <20050613200820.GA29872@lst.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.85.1/935/Mon Jun 13 18:27:50 2005 on piorun.ds.pg.gda.pl X-Virus-Status: Clean X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8081 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 13 Jun 2005, Christoph Hellwig wrote: > > Do you think HEAD is stable enough for a non-glibc developer? It's soon > > after a fork after all, so I'd expect more serious changes to be applied > > nowadays. > > Btw, what is the chance to see a biarch toolchain for mips? It seems > all linux architectures with 32bit and 64bit variants seem to have one > these days, except mips. What do you mean? Multilib, per chance? If so, please feel free to build one yourself -- as of 4.0.0 GCC will build libraries for all three ABIs (o32, (n)64 and n32) if configured for mips64{,el}-linux and --enable-multilib is in effect (I think it is by default). Bi-endian is probably tougher, but it should be possible -- GCC itself supports the "-mabi=" and "-mel" and "-meb" switches all the time AFAIK. Of course you may need to have system libraries installed in place for all requested configurations as appropriate; at least glibc, but perhaps others as well (gmp, mpfr for Fortran; zlib for Java). Maciej From macro@linux-mips.org Mon Jun 13 21:40:14 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 21:40:33 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([IPv6:::ffff:153.19.208.7]:7696 "EHLO pollux.ds.pg.gda.pl") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 21:40:14 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 15B14F598B; Mon, 13 Jun 2005 22:40:04 +0200 (CEST) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 24973-01; Mon, 13 Jun 2005 22:40:03 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 64EC9F5981; Mon, 13 Jun 2005 22:40:03 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.3/8.13.1) with ESMTP id j5DKe8dF029537; Mon, 13 Jun 2005 22:40:08 +0200 Date: Mon, 13 Jun 2005 21:40:20 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Fix fallback atomic operations Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.85.1/935/Mon Jun 13 18:27:50 2005 on piorun.ds.pg.gda.pl X-Virus-Status: Clean X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8082 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Ralf, You may argue it's best to define a private copy of "cpu_has_llsc" expanding to a constant for selecting the right set of atomic operations at the compilation time and I would agree, but AFAIK the whole idea behind our current implementation is to provide a snail-speed fallback or perhaps to support more generic configurations at one point (e.g. one kernel for all DECstations). For most processor settings the current setup already works, as they provide ll/sc anyway, but not for MIPS I ones, like the R3k. Here's a patch that makes the affected code work for such processors as well. OK to apply? Maciej patch-mips-2.6.12-rc4-20050526-atomic-3 diff -up --recursive --new-file linux-mips-2.6.12-rc4-20050526.macro/arch/mips/kernel/semaphore.c linux-mips-2.6.12-rc4-20050526/arch/mips/kernel/semaphore.c --- linux-mips-2.6.12-rc4-20050526.macro/arch/mips/kernel/semaphore.c 2005-01-15 05:56:03.000000000 +0000 +++ linux-mips-2.6.12-rc4-20050526/arch/mips/kernel/semaphore.c 2005-06-12 18:31:35.000000000 +0000 @@ -42,24 +42,28 @@ static inline int __sem_update_count(str if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - "1: ll %0, %2 \n" + " .set mips2 \n" + "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" " and %1, %0, %1 \n" - " add %1, %1, %3 \n" + " addu %1, %1, %3 \n" " sc %1, %2 \n" " beqzl %1, 1b \n" + " .set mips0 \n" : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) : "r" (incr), "m" (sem->count)); } else if (cpu_has_llsc) { __asm__ __volatile__( - "1: ll %0, %2 \n" + " .set mips2 \n" + "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" " and %1, %0, %1 \n" - " add %1, %1, %3 \n" + " addu %1, %1, %3 \n" " sc %1, %2 \n" " beqz %1, 1b \n" + " .set mips0 \n" : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) : "r" (incr), "m" (sem->count)); } else { diff -up --recursive --new-file linux-mips-2.6.12-rc4-20050526.macro/include/asm-mips/atomic.h linux-mips-2.6.12-rc4-20050526/include/asm-mips/atomic.h --- linux-mips-2.6.12-rc4-20050526.macro/include/asm-mips/atomic.h 2004-08-20 03:58:10.000000000 +0000 +++ linux-mips-2.6.12-rc4-20050526/include/asm-mips/atomic.h 2005-06-12 18:16:22.000000000 +0000 @@ -62,20 +62,24 @@ static __inline__ void atomic_add(int i, unsigned long temp; __asm__ __volatile__( + " .set mips2 \n" "1: ll %0, %1 # atomic_add \n" " addu %0, %2 \n" " sc %0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { unsigned long temp; __asm__ __volatile__( + " .set mips2 \n" "1: ll %0, %1 # atomic_add \n" " addu %0, %2 \n" " sc %0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else { @@ -100,20 +104,24 @@ static __inline__ void atomic_sub(int i, unsigned long temp; __asm__ __volatile__( + " .set mips2 \n" "1: ll %0, %1 # atomic_sub \n" " subu %0, %2 \n" " sc %0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { unsigned long temp; __asm__ __volatile__( + " .set mips2 \n" "1: ll %0, %1 # atomic_sub \n" " subu %0, %2 \n" " sc %0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else { @@ -136,12 +144,14 @@ static __inline__ int atomic_add_return( unsigned long temp; __asm__ __volatile__( + " .set mips2 \n" "1: ll %1, %2 # atomic_add_return \n" " addu %0, %1, %3 \n" " sc %0, %2 \n" " beqzl %0, 1b \n" " addu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -149,12 +159,14 @@ static __inline__ int atomic_add_return( unsigned long temp; __asm__ __volatile__( + " .set mips2 \n" "1: ll %1, %2 # atomic_add_return \n" " addu %0, %1, %3 \n" " sc %0, %2 \n" " beqz %0, 1b \n" " addu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -179,12 +191,14 @@ static __inline__ int atomic_sub_return( unsigned long temp; __asm__ __volatile__( + " .set mips2 \n" "1: ll %1, %2 # atomic_sub_return \n" " subu %0, %1, %3 \n" " sc %0, %2 \n" " beqzl %0, 1b \n" " subu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -192,12 +206,14 @@ static __inline__ int atomic_sub_return( unsigned long temp; __asm__ __volatile__( + " .set mips2 \n" "1: ll %1, %2 # atomic_sub_return \n" " subu %0, %1, %3 \n" " sc %0, %2 \n" " beqz %0, 1b \n" " subu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -229,6 +245,7 @@ static __inline__ int atomic_sub_if_posi unsigned long temp; __asm__ __volatile__( + " .set mips2 \n" "1: ll %1, %2 # atomic_sub_if_positive\n" " subu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -236,6 +253,7 @@ static __inline__ int atomic_sub_if_posi " beqzl %0, 1b \n" " sync \n" "1: \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -243,6 +261,7 @@ static __inline__ int atomic_sub_if_posi unsigned long temp; __asm__ __volatile__( + " .set mips2 \n" "1: ll %1, %2 # atomic_sub_if_positive\n" " subu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -250,6 +269,7 @@ static __inline__ int atomic_sub_if_posi " beqz %0, 1b \n" " sync \n" "1: \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -367,20 +387,24 @@ static __inline__ void atomic64_add(long unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %1 # atomic64_add \n" " addu %0, %2 \n" " scd %0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %1 # atomic64_add \n" " addu %0, %2 \n" " scd %0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else { @@ -405,20 +429,24 @@ static __inline__ void atomic64_sub(long unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %1 # atomic64_sub \n" " subu %0, %2 \n" " scd %0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %1 # atomic64_sub \n" " subu %0, %2 \n" " scd %0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else { @@ -441,12 +469,14 @@ static __inline__ long atomic64_add_retu unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_add_return \n" " addu %0, %1, %3 \n" " scd %0, %2 \n" " beqzl %0, 1b \n" " addu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -454,12 +484,14 @@ static __inline__ long atomic64_add_retu unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_add_return \n" " addu %0, %1, %3 \n" " scd %0, %2 \n" " beqz %0, 1b \n" " addu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -484,12 +516,14 @@ static __inline__ long atomic64_sub_retu unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_sub_return \n" " subu %0, %1, %3 \n" " scd %0, %2 \n" " beqzl %0, 1b \n" " subu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -497,12 +531,14 @@ static __inline__ long atomic64_sub_retu unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_sub_return \n" " subu %0, %1, %3 \n" " scd %0, %2 \n" " beqz %0, 1b \n" " subu %0, %1, %3 \n" " sync \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -534,6 +570,7 @@ static __inline__ long atomic64_sub_if_p unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_sub_if_positive\n" " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -541,6 +578,7 @@ static __inline__ long atomic64_sub_if_p " beqzl %0, 1b \n" " sync \n" "1: \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -548,6 +586,7 @@ static __inline__ long atomic64_sub_if_p unsigned long temp; __asm__ __volatile__( + " .set mips3 \n" "1: lld %1, %2 # atomic64_sub_if_positive\n" " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -555,6 +594,7 @@ static __inline__ long atomic64_sub_if_p " beqz %0, 1b \n" " sync \n" "1: \n" + " .set mips0 \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); diff -up --recursive --new-file linux-mips-2.6.12-rc4-20050526.macro/include/asm-mips/bitops.h linux-mips-2.6.12-rc4-20050526/include/asm-mips/bitops.h --- linux-mips-2.6.12-rc4-20050526.macro/include/asm-mips/bitops.h 2005-01-09 05:55:44.000000000 +0000 +++ linux-mips-2.6.12-rc4-20050526/include/asm-mips/bitops.h 2005-06-12 18:11:49.000000000 +0000 @@ -18,14 +18,16 @@ #if (_MIPS_SZLONG == 32) #define SZLONG_LOG 5 #define SZLONG_MASK 31UL -#define __LL "ll " -#define __SC "sc " +#define __LL "ll " +#define __SC "sc " +#define __SET_MIPS ".set mips2 " #define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) #elif (_MIPS_SZLONG == 64) #define SZLONG_LOG 6 #define SZLONG_MASK 63UL -#define __LL "lld " -#define __SC "scd " +#define __LL "lld " +#define __SC "scd " +#define __SET_MIPS ".set mips3 " #define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) #endif @@ -72,18 +74,22 @@ static inline void set_bit(unsigned long if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else if (cpu_has_llsc) { __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else { @@ -132,18 +138,22 @@ static inline void clear_bit(unsigned lo if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); } else if (cpu_has_llsc) { __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); } else { @@ -191,10 +201,12 @@ static inline void change_bit(unsigned l unsigned long temp; __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqzl %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else if (cpu_has_llsc) { @@ -202,10 +214,12 @@ static inline void change_bit(unsigned l unsigned long temp; __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" - " "__SC "%0, %1 \n" + " " __SC "%0, %1 \n" " beqz %0, 1b \n" + " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } else { @@ -253,14 +267,16 @@ static inline int test_and_set_bit(unsig unsigned long temp, res; __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP - "sync \n" + " sync \n" #endif + " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -271,16 +287,18 @@ static inline int test_and_set_bit(unsig unsigned long temp, res; __asm__ __volatile__( - " .set noreorder # test_and_set_bit \n" - "1: " __LL "%0, %1 \n" + " .set push \n" + " .set noreorder \n" + " " __SET_MIPS " \n" + "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqz %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP - "sync \n" + " sync \n" #endif - ".set\treorder" + " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -343,15 +361,17 @@ static inline int test_and_clear_bit(uns unsigned long temp, res; __asm__ __volatile__( + " " __SET_MIPS " \n" "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" - __SC "%2, %1 \n" + " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -362,17 +382,19 @@ static inline int test_and_clear_bit(uns unsigned long temp, res; __asm__ __volatile__( - " .set noreorder # test_and_clear_bit \n" - "1: " __LL "%0, %1 \n" + " .set push \n" + " .set noreorder \n" + " " __SET_MIPS " \n" + "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" - __SC "%2, %1 \n" + " " __SC "%2, %1 \n" " beqz %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif - " .set reorder \n" + " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -435,14 +457,16 @@ static inline int test_and_change_bit(un unsigned long temp, res; __asm__ __volatile__( - "1: " __LL " %0, %1 # test_and_change_bit \n" + " " __SET_MIPS " \n" + "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" - " "__SC "%2, %1 \n" + " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); @@ -453,16 +477,18 @@ static inline int test_and_change_bit(un unsigned long temp, res; __asm__ __volatile__( - " .set noreorder # test_and_change_bit \n" - "1: " __LL " %0, %1 \n" + " .set push \n" + " .set noreorder \n" + " " __SET_MIPS " \n" + "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" - " "__SC "\t%2, %1 \n" + " " __SC "\t%2, %1 \n" " beqz %2, 1b \n" " and %2, %0, %3 \n" #ifdef CONFIG_SMP " sync \n" #endif - " .set reorder \n" + " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); diff -up --recursive --new-file linux-mips-2.6.12-rc4-20050526.macro/include/asm-mips/system.h linux-mips-2.6.12-rc4-20050526/include/asm-mips/system.h --- linux-mips-2.6.12-rc4-20050526.macro/include/asm-mips/system.h 2005-03-19 05:58:17.000000000 +0000 +++ linux-mips-2.6.12-rc4-20050526/include/asm-mips/system.h 2005-06-12 18:08:04.000000000 +0000 @@ -171,6 +171,7 @@ static inline unsigned long __xchg_u32(v unsigned long dummy; __asm__ __volatile__( + " .set mips2 \n" "1: ll %0, %3 # xchg_u32 \n" " move %2, %z4 \n" " sc %2, %1 \n" @@ -179,6 +180,7 @@ static inline unsigned long __xchg_u32(v #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) : "memory"); @@ -186,6 +188,7 @@ static inline unsigned long __xchg_u32(v unsigned long dummy; __asm__ __volatile__( + " .set mips2 \n" "1: ll %0, %3 # xchg_u32 \n" " move %2, %z4 \n" " sc %2, %1 \n" @@ -193,6 +196,7 @@ static inline unsigned long __xchg_u32(v #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) : "memory"); @@ -217,6 +221,7 @@ static inline __u64 __xchg_u64(volatile unsigned long dummy; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %3 # xchg_u64 \n" " move %2, %z4 \n" " scd %2, %1 \n" @@ -225,6 +230,7 @@ static inline __u64 __xchg_u64(volatile #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) : "memory"); @@ -232,6 +238,7 @@ static inline __u64 __xchg_u64(volatile unsigned long dummy; __asm__ __volatile__( + " .set mips3 \n" "1: lld %0, %3 # xchg_u64 \n" " move %2, %z4 \n" " scd %2, %1 \n" @@ -239,6 +246,7 @@ static inline __u64 __xchg_u64(volatile #ifdef CONFIG_SMP " sync \n" #endif + " .set mips0 \n" : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) : "memory"); @@ -286,7 +294,9 @@ static inline unsigned long __cmpxchg_u3 if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( + " .set push \n" " .set noat \n" + " .set mips2 \n" "1: ll %0, %2 # __cmpxchg_u32 \n" " bne %0, %z3, 2f \n" " move $1, %z4 \n" @@ -297,13 +307,15 @@ static inline unsigned long __cmpxchg_u3 " sync \n" #endif "2: \n" - " .set at \n" + " .set pop \n" : "=&r" (retval), "=m" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( + " .set push \n" " .set noat \n" + " .set mips2 \n" "1: ll %0, %2 # __cmpxchg_u32 \n" " bne %0, %z3, 2f \n" " move $1, %z4 \n" @@ -313,7 +325,7 @@ static inline unsigned long __cmpxchg_u3 " sync \n" #endif "2: \n" - " .set at \n" + " .set pop \n" : "=&r" (retval), "=m" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); @@ -338,7 +350,9 @@ static inline unsigned long __cmpxchg_u6 if (cpu_has_llsc) { __asm__ __volatile__( + " .set push \n" " .set noat \n" + " .set mips3 \n" "1: lld %0, %2 # __cmpxchg_u64 \n" " bne %0, %z3, 2f \n" " move $1, %z4 \n" @@ -349,13 +363,15 @@ static inline unsigned long __cmpxchg_u6 " sync \n" #endif "2: \n" - " .set at \n" + " .set pop \n" : "=&r" (retval), "=m" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( + " .set push \n" " .set noat \n" + " .set mips2 \n" "1: lld %0, %2 # __cmpxchg_u64 \n" " bne %0, %z3, 2f \n" " move $1, %z4 \n" @@ -365,7 +381,7 @@ static inline unsigned long __cmpxchg_u6 " sync \n" #endif "2: \n" - " .set at \n" + " .set pop \n" : "=&r" (retval), "=m" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); From drow@nevyn.them.org Mon Jun 13 21:56:03 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 21:56:19 +0100 (BST) Received: from nevyn.them.org ([IPv6:::ffff:66.93.172.17]:20930 "EHLO nevyn.them.org") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 21:56:03 +0100 Received: from drow by nevyn.them.org with local (Exim 4.50) id 1DhvyQ-0006zr-WE; Mon, 13 Jun 2005 16:55:59 -0400 Date: Mon, 13 Jun 2005 16:55:58 -0400 From: Daniel Jacobowitz To: Christoph Hellwig Cc: "Maciej W. Rozycki" , Jim Gifford , Linux MIPS List Subject: Re: Building o32 glibc on mips64 Message-ID: <20050613205558.GA26829@nevyn.them.org> References: <42AB3366.8030206@jg555.com> <20050613195602.GA3739@nevyn.them.org> <20050613200820.GA29872@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20050613200820.GA29872@lst.de> User-Agent: Mutt/1.5.8i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8083 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@debian.org Precedence: bulk X-list: linux-mips On Mon, Jun 13, 2005 at 10:08:20PM +0200, Christoph Hellwig wrote: > Btw, what is the chance to see a biarch toolchain for mips? It seems > all linux architectures with 32bit and 64bit variants seem to have one > these days, except mips. As Maciej wrote, mips64-linux is already triarch. It's possible to build a multiarch mips-linux toolchain, or a mips64-linux toolchain which supports multilibs but defaults to o32, but neither's real easy. I build mips64-linux toolchains all the time, though. -- Daniel Jacobowitz CodeSourcery, LLC From dom@mips.com Mon Jun 13 22:01:46 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 13 Jun 2005 22:02:02 +0100 (BST) Received: from alg145.algor.co.uk ([IPv6:::ffff:62.254.210.145]:31757 "EHLO dmz.algor.co.uk") by linux-mips.org with ESMTP id ; Mon, 13 Jun 2005 22:01:46 +0100 Received: from alg158.algor.co.uk ([62.254.210.158] helo=olympia.mips.com) by dmz.algor.co.uk with esmtp (Exim 3.35 #1 (Debian)) id 1DhwLz-0002ns-00; Mon, 13 Jun 2005 22:20:19 +0100 Received: from olympia.mips.com ([192.168.192.128] helo=boris) by olympia.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1Dhw2y-0007c6-00; Mon, 13 Jun 2005 22:00:41 +0100 From: Dominic Sweetman MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <17069.62407.584863.185198@mips.com> Date: Mon, 13 Jun 2005 21:59:51 +0100 To: "Mad Props" Cc: linux-mips@linux-mips.org Subject: Re: tlb magic In-Reply-To: <31886.1118671594@www68.gmx.net> References: <31886.1118671594@www68.gmx.net> X-Mailer: VM 7.17 under 21.4 (patch 15) "Security Through Obscurity" XEmacs Lucid X-MTUK-Scanner: Found to be clean X-MTUK-SpamCheck: not spam (whitelisted), SpamAssassin (score=-4.835, required 4, AWL, BAYES_00) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8084 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dom@mips.com Precedence: bulk X-list: linux-mips Thomas, > I'm trying to understand how to implement an TLB Exception handler for a > MIPS32 ( 4KC ). As far as I got it, it makes sense to locate the user > process page tables in kseg2 to save physical memory. The book I'm reading > states another advantage using kseg2. I'm not quite sure what they mean, > stating that > > "It provides an easy mechanism for remapping a new user page table when > changing context, without having to find enough virtual addresses in the OS > to map all the page tables at once. Instead, you just change the ASID value, > and the kseg2 pointer to the page table is now automatically remapped onto > the correct page table. It's nearly magic." Sounds familiar. Are you reading "See MIPS Run"? If so, it has pictures and further explanation. If not - well, no wonder you're confused (run down to Amazon and see if they have any copies left!) > 1. Is there only one kseg2 containing all page tables for 256 processes, > i.e. only one ASID is used or > > 2. Has each page table it's own address space ( using different ASID for > those addresses in kseg2 ) MIPS TLBs can be loaded with "global" entries which map regardless of ASID. Linux (which doesn't use kseg2 for page tables) only ever uses global mappings to kseg2, which is therefore a shared space for all kernel threads. I think the early BSD ports, for which the kseg2 trick was invented, did use per-process mappings in kseg2 for BSD's per-process data area and the page table. The idea of using software to maintain the TLB freaked out potential customers back in 1987, so it was important to be able to show them a very short user-address TLB miss handler. > 3. Will I need another untranslated page table in kseg0/kseg1 to translate > kseg2 addresses ? Well, of course you don't *need* any particular format of page table, it's all done by software. The only constraint here is that while special tricks on the R3000 allow the user-mode-address TLB-miss handler to take a nested exception (to fix up a missing translation for the page table), those tricks won't work for the kernel-mode-address TLB miss handler. The BSD systems used kseg0 information to resolve kseg2 translation misses, or kept the crucial 2nd-level information in places accessible through 'wired' (non-replaceable) TLB entries. > 4. What is this kseg2 pointer they are talking about ? It's probably a reference to the base of the page table, which is kept in the high-order bits of the CP0 register "Context". > 5. Are they talking about the ASID in EntryHi ? Yes. The ASID in EntryHi does double-duty: it is the "current" ASID for the running process, and also the place where the ASID field of a TLB entry gets lodged when the TLB is read/written. > 6. Where is the magic ? In the eye of the beholder. Was that any help? -- Dominic Sweetman MIPS Technologies From ralf@linux-mips.org Tue Jun 14 08:26:23 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Jun 2005 08:26:38 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:60422 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Tue, 14 Jun 2005 08:26:23 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j5E7NeAT005394; Tue, 14 Jun 2005 08:23:40 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j5E7NdFo005393; Tue, 14 Jun 2005 08:23:39 +0100 Date: Tue, 14 Jun 2005 08:23:39 +0100 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@linux-mips.org Subject: Re: Fix fallback atomic operations Message-ID: <20050614072339.GA5183@linux-mips.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8085 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 13, 2005 at 09:40:20PM +0100, Maciej W. Rozycki wrote: > You may argue it's best to define a private copy of "cpu_has_llsc" > expanding to a constant for selecting the right set of atomic operations > at the compilation time and I would agree, but AFAIK the whole idea behind > our current implementation is to provide a snail-speed fallback or perhaps > to support more generic configurations at one point (e.g. one kernel for > all DECstations). > > For most processor settings the current setup already works, as they > provide ll/sc anyway, but not for MIPS I ones, like the R3k. Here's a > patch that makes the affected code work for such processors as well. > > OK to apply? Go ahead. Al had a bunch of other complaints which I'll try to take care of asap. Ralf From maillist@jg555.com Tue Jun 14 09:00:44 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Jun 2005 09:00:59 +0100 (BST) Received: from 64-30-195-78.dsl.linkline.com ([IPv6:::ffff:64.30.195.78]:13517 "EHLO jg555.com") by linux-mips.org with ESMTP id ; Tue, 14 Jun 2005 09:00:44 +0100 Received: from [172.16.0.55] ([::ffff:172.16.0.55]) (AUTH: PLAIN root, TLS: TLSv1/SSLv3,256bits,AES256-SHA) by jg555.com with esmtp; Tue, 14 Jun 2005 01:00:39 -0700 id 001DC0AC.42AE8EA7.00007085 Message-ID: <42AE8E85.4080708@jg555.com> Date: Tue, 14 Jun 2005 01:00:05 -0700 From: Jim Gifford User-Agent: Mozilla Thunderbird 1.0 (Windows/20041206) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Daniel Jacobowitz CC: Christoph Hellwig , "Maciej W. Rozycki" , Linux MIPS List Subject: Re: Building o32 glibc on mips64 References: <42AB3366.8030206@jg555.com> <20050613195602.GA3739@nevyn.them.org> <20050613200820.GA29872@lst.de> <20050613205558.GA26829@nevyn.them.org> In-Reply-To: <20050613205558.GA26829@nevyn.them.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8086 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maillist@jg555.com Precedence: bulk X-list: linux-mips From my understanding it's only supported when using IRIX shared libraries, but the standard MIPS64 still only builds n32 and n64 only, and not the o32 libraries. I don't see why GCC didn't just allow all MIPS have that capability. -- ---- Jim Gifford maillist@jg555.com From richard@codesourcery.com Tue Jun 14 11:35:54 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Jun 2005 11:36:09 +0100 (BST) Received: from admin.voldemort.codesourcery.com ([IPv6:::ffff:65.74.133.9]:33731 "EHLO mail.codesourcery.com") by linux-mips.org with ESMTP id ; Tue, 14 Jun 2005 11:35:54 +0100 Received: (qmail 28295 invoked from network); 14 Jun 2005 10:35:50 -0000 Received: from localhost (127.0.0.1) by mail.codesourcery.com with SMTP; 14 Jun 2005 10:35:50 -0000 From: Richard Sandiford To: Jim Gifford Mail-Followup-To: Jim Gifford ,Daniel Jacobowitz , Christoph Hellwig , "Maciej W. Rozycki" , Linux MIPS List , richard@codesourcery.com Cc: Daniel Jacobowitz , Christoph Hellwig , "Maciej W. Rozycki" , Linux MIPS List Subject: Re: Building o32 glibc on mips64 References: <42AB3366.8030206@jg555.com> <20050613195602.GA3739@nevyn.them.org> <20050613200820.GA29872@lst.de> <20050613205558.GA26829@nevyn.them.org> <42AE8E85.4080708@jg555.com> Date: Tue, 14 Jun 2005 11:36:12 +0100 In-Reply-To: <42AE8E85.4080708@jg555.com> (Jim Gifford's message of "Tue, 14 Jun 2005 01:00:05 -0700") Message-ID: <87vf4hb4yr.fsf@firetop.home> User-Agent: Gnus/5.110003 (No Gnus v0.3) Emacs/21.4 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8087 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: richard@codesourcery.com Precedence: bulk X-list: linux-mips Jim Gifford writes: > From my understanding it's only supported when using IRIX shared > libraries, but the standard MIPS64 still only builds n32 and n64 only, > and not the o32 libraries. No, that's not true (assuming "MIPS64" == mips64-linux-gnu). What makes you think so? Richard From madprops@gmx.net Tue Jun 14 17:00:32 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Jun 2005 17:00:50 +0100 (BST) Received: from pop.gmx.de ([IPv6:::ffff:213.165.64.20]:10379 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Tue, 14 Jun 2005 17:00:32 +0100 Received: (qmail 21476 invoked by uid 0); 14 Jun 2005 16:00:25 -0000 Received: from 129.13.186.3 by www21.gmx.net with HTTP; Tue, 14 Jun 2005 18:00:26 +0200 (MEST) Date: Tue, 14 Jun 2005 18:00:26 +0200 (MEST) From: madprops@gmx.net To: linux-mips@linux-mips.org MIME-Version: 1.0 References: <17069.62407.584863.185198@mips.com> Subject: Re: tlb magic X-Priority: 3 (Normal) X-Authenticated: #24801140 Message-ID: <18788.1118764826@www21.gmx.net> X-Mailer: WWW-Mail 1.6 (Global Message Exchange) X-Flags: 0001 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8088 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: madprops@gmx.net Precedence: bulk X-list: linux-mips > > Thomas, > > > I'm trying to understand how to implement an TLB Exception handler for a > > MIPS32 ( 4KC ). As far as I got it, it makes sense to locate the user > > process page tables in kseg2 to save physical memory. The book I'm > reading > > states another advantage using kseg2. I'm not quite sure what they mean, > > stating that > > > > "It provides an easy mechanism for remapping a new user page table when > > changing context, without having to find enough virtual addresses in the > OS > > to map all the page tables at once. Instead, you just change the ASID > value, > > and the kseg2 pointer to the page table is now automatically remapped > onto > > the correct page table. It's nearly magic." > > Sounds familiar. Are you reading "See MIPS Run"? If so, it has > pictures and further explanation. If not - well, no wonder you're > confused (run down to Amazon and see if they have any copies left!) > > > 1. Is there only one kseg2 containing all page tables for 256 processes, > > i.e. only one ASID is used or > > > > 2. Has each page table it's own address space ( using different ASID for > > those addresses in kseg2 ) > > MIPS TLBs can be loaded with "global" entries which map regardless of > ASID. Linux (which doesn't use kseg2 for page tables) only ever uses > global mappings to kseg2, which is therefore a shared space for all > kernel threads. > > I think the early BSD ports, for which the kseg2 trick was invented, > did use per-process mappings in kseg2 for BSD's per-process data area > and the page table. The idea of using software to maintain the TLB > freaked out potential customers back in 1987, so it was important to > be able to show them a very short user-address TLB miss handler. > > > 3. Will I need another untranslated page table in kseg0/kseg1 to > translate > > kseg2 addresses ? > > Well, of course you don't *need* any particular format of page table, > it's all done by software. The only constraint here is that while > special tricks on the R3000 allow the user-mode-address TLB-miss > handler to take a nested exception (to fix up a missing translation > for the page table), those tricks won't work for the > kernel-mode-address TLB miss handler. > > The BSD systems used kseg0 information to resolve kseg2 > translation misses, or kept the crucial 2nd-level information in > places accessible through 'wired' (non-replaceable) TLB entries. > > > 4. What is this kseg2 pointer they are talking about ? > > It's probably a reference to the base of the page table, which is kept > in the high-order bits of the CP0 register "Context". > > > 5. Are they talking about the ASID in EntryHi ? > > Yes. The ASID in EntryHi does double-duty: it is the "current" ASID > for the running process, and also the place where the ASID field of a > TLB entry gets lodged when the TLB is read/written. > > > 6. Where is the magic ? > > In the eye of the beholder. > > Was that any help? > > -- > Dominic Sweetman > MIPS Technologies > Hi, yes, I'm reading "See MIPS Run". So thanks for the online support that comes with it. Now, if I got it correctly, the exception routing described in section 6.7 uses per-process mappings for kseg2, i.e. that e.g. the first 2MB of (each) kseg2 are used as page table of the corresponding process and maybe another few kb for process related stuff. Provided the page tables are continuously at the same address ( e.g. KSEG2_BASE ) a change of ASID in EntryHi would indeed make a change of the kseg2 pointer in Context unnecessary ( it always points to KSEG2_BASE ). The mapping of kseg2 would automatically change as the global bit is set to zero. Using the standard page table approach I would now need an additional page table for each process in order to map those 2+x MB in kseg2 which I could put in kseg0/1 or in kseg2 with 'wired' TLB entries. If that's the way to go - why is it only used in early BSD ports of like 1987 ? Are there any troubles with it or have other mechanisms turned out to be better for any reason ? Regards, Thomas -- Geschenkt: 3 Monate GMX ProMail gratis + 3 Ausgaben stern gratis ++ Jetzt anmelden & testen ++ http://www.gmx.net/de/go/promail ++ From ralf@linux-mips.org Tue Jun 14 17:09:14 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Jun 2005 17:09:36 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:60165 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Tue, 14 Jun 2005 17:09:14 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j5EG6OdA026292; Tue, 14 Jun 2005 17:06:24 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j5EG6N7X026291; Tue, 14 Jun 2005 17:06:23 +0100 Date: Tue, 14 Jun 2005 17:06:23 +0100 From: Ralf Baechle To: Ton Truong Cc: linux-mips@linux-mips.org Subject: Re: Member sc_sigset gone in latest 2.6.12-rc5 breaks strace. Message-ID: <20050614160623.GE5183@linux-mips.org> References: <20050606121640.GB6651@linux-mips.org> <200506091737.KAA22310@mon-irva-10.broadcom.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200506091737.KAA22310@mon-irva-10.broadcom.com> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8089 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jun 09, 2005 at 10:37:49AM -0700, Ton Truong wrote: > I see that in the rc5 update, MIPS codes have now dropped > sc_sigset[4] from struct sigcontext, defined in asm-mips/sigcontext.h. I'd > appreciate it if someone provide a brief summary of what needs to be changed > for strace to compile or where I can find an strace port that work with the > new MIPS codes? > > Much appreciated. Things turned a little more complicated, unfortunately. So the recent support for the DSP ASE broke compilation of some code in strace that wasn't functioning anyway. Fixing that did collide with a RM9000 bug workaround ... So this is something that hopefully will work for any processor and re-establish binary compatibility with debuggers. Strace will need a separate patch. Comments? Ralf arch/mips/kernel/signal-common.h | 34 ++++++++- arch/mips/kernel/signal.c | 59 +++++++---------- arch/mips/kernel/signal32.c | 16 ++++ arch/mips/kernel/signal_n32.c | 32 +++------ include/asm-mips/cpu-features.h | 11 --- include/asm-mips/mach-ja/cpu-feature-overrides.h | 6 - include/asm-mips/mach-ocelot3/cpu-feature-overrides.h | 6 - include/asm-mips/mach-yosemite/cpu-feature-overrides.h | 6 - include/asm-mips/war.h | 14 ++++ 9 files changed, 98 insertions(+), 86 deletions(-) Index: linux-qa/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h =================================================================== --- linux-qa.orig/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h 2005-06-14 12:53:28.000000000 +0100 +++ linux-qa/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h 2005-06-14 14:25:12.000000000 +0100 @@ -40,10 +40,4 @@ #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 -/* - * On the RM9000 we need to ensure that I-cache lines being fetches only - * contain valid instructions are funny things will happen. - */ -#define PLAT_TRAMPOLINE_STUFF_LINE 32UL - #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ Index: linux-qa/include/asm-mips/cpu-features.h =================================================================== --- linux-qa.orig/include/asm-mips/cpu-features.h 2005-06-14 12:53:28.000000000 +0100 +++ linux-qa/include/asm-mips/cpu-features.h 2005-06-14 14:25:12.000000000 +0100 @@ -109,17 +109,6 @@ #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif -/* - * Certain CPUs may throw bizarre exceptions if not the whole cacheline - * contains valid instructions. For these we ensure proper alignment of - * signal trampolines and pad them to the size of a full cache lines with - * nops. This is also used in structure definitions so can't be a test macro - * like the others. - */ -#ifndef PLAT_TRAMPOLINE_STUFF_LINE -#define PLAT_TRAMPOLINE_STUFF_LINE 0UL -#endif - #ifdef CONFIG_MIPS32 # ifndef cpu_has_nofpuex # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) Index: linux-qa/include/asm-mips/mach-yosemite/cpu-feature-overrides.h =================================================================== --- linux-qa.orig/include/asm-mips/mach-yosemite/cpu-feature-overrides.h 2005-06-14 12:53:28.000000000 +0100 +++ linux-qa/include/asm-mips/mach-yosemite/cpu-feature-overrides.h 2005-06-14 14:25:12.000000000 +0100 @@ -37,10 +37,4 @@ #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 -/* - * On the RM9000 we need to ensure that I-cache lines being fetches only - * contain valid instructions are funny things will happen. - */ -#define PLAT_TRAMPOLINE_STUFF_LINE 32UL - #endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */ Index: linux-qa/arch/mips/kernel/signal_n32.c =================================================================== --- linux-qa.orig/arch/mips/kernel/signal_n32.c 2005-06-14 12:53:28.000000000 +0100 +++ linux-qa/arch/mips/kernel/signal_n32.c 2005-06-14 15:47:37.000000000 +0100 @@ -15,6 +15,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include +#include #include #include #include @@ -36,6 +38,7 @@ #include #include #include +#include #include "signal-common.h" @@ -62,17 +65,18 @@ sigset_t uc_sigmask; /* mask last for extensibility */ }; -#if PLAT_TRAMPOLINE_STUFF_LINE -#define __tramp __attribute__((aligned(PLAT_TRAMPOLINE_STUFF_LINE))) -#else -#define __tramp -#endif - struct rt_sigframe_n32 { u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_code[2] __tramp; /* signal trampoline */ - struct siginfo rs_info __tramp; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_pad[2]; +#else + u32 rs_code[2]; /* signal trampoline */ +#endif + struct siginfo rs_info; struct ucontextn32 rs_uc; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; save_static_function(sysn32_rt_sigreturn); @@ -137,17 +141,7 @@ if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* - * Set up the return code ... - * - * li v0, __NR_rt_sigreturn - * syscall - */ - if (PLAT_TRAMPOLINE_STUFF_LINE) - __clear_user(frame->rs_code, PLAT_TRAMPOLINE_STUFF_LINE); - err |= __put_user(0x24020000 + __NR_N32_rt_sigreturn, frame->rs_code + 0); - err |= __put_user(0x0000000c , frame->rs_code + 1); - flush_cache_sigtramp((unsigned long) frame->rs_code); + install_sigtramp(frame->rs_code, __NR_N32_rt_sigreturn); /* Create siginfo. */ err |= copy_siginfo_to_user(&frame->rs_info, info); Index: linux-qa/arch/mips/kernel/signal.c =================================================================== --- linux-qa.orig/arch/mips/kernel/signal.c 2005-06-14 12:53:28.000000000 +0100 +++ linux-qa/arch/mips/kernel/signal.c 2005-06-14 16:37:36.000000000 +0100 @@ -8,6 +8,7 @@ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #include +#include #include #include #include @@ -30,6 +31,7 @@ #include #include #include +#include #include "signal-common.h" @@ -157,26 +159,39 @@ return do_sigaltstack(uss, uoss, usp); } -#if PLAT_TRAMPOLINE_STUFF_LINE -#define __tramp __attribute__((aligned(PLAT_TRAMPOLINE_STUFF_LINE))) -#else -#define __tramp -#endif - +/* + * Horribly complicated - with the bloody RM9000 workarounds enabled + * the signal trampolines is moving to the end of the structure so we can + * increase the alignment without breaking software compatibility. + */ #ifdef CONFIG_TRAD_SIGNALS struct sigframe { u32 sf_ass[4]; /* argument save space for o32 */ - u32 sf_code[2] __tramp; /* signal trampoline */ - struct sigcontext sf_sc __tramp; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_pad[2]; +#else + u32 sf_code[2]; /* signal trampoline */ +#endif + struct sigcontext sf_sc; sigset_t sf_mask; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; #endif struct rt_sigframe { u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_code[2] __tramp; /* signal trampoline */ - struct siginfo rs_info __tramp; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_pad[2]; +#else + u32 rs_code[2]; /* signal trampoline */ +#endif + struct siginfo rs_info; struct ucontext rs_uc; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; #ifdef CONFIG_TRAD_SIGNALS @@ -273,17 +288,7 @@ if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* - * Set up the return code ... - * - * li v0, __NR_sigreturn - * syscall - */ - if (PLAT_TRAMPOLINE_STUFF_LINE) - __clear_user(frame->sf_code, PLAT_TRAMPOLINE_STUFF_LINE); - err |= __put_user(0x24020000 + __NR_sigreturn, frame->sf_code + 0); - err |= __put_user(0x0000000c , frame->sf_code + 1); - flush_cache_sigtramp((unsigned long) frame->sf_code); + install_sigtramp(frame->sf_code, __NR_sigreturn); err |= setup_sigcontext(regs, &frame->sf_sc); err |= __copy_to_user(&frame->sf_mask, set, sizeof(*set)); @@ -329,17 +334,7 @@ if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* - * Set up the return code ... - * - * li v0, __NR_rt_sigreturn - * syscall - */ - if (PLAT_TRAMPOLINE_STUFF_LINE) - __clear_user(frame->rs_code, PLAT_TRAMPOLINE_STUFF_LINE); - err |= __put_user(0x24020000 + __NR_rt_sigreturn, frame->rs_code + 0); - err |= __put_user(0x0000000c , frame->rs_code + 1); - flush_cache_sigtramp((unsigned long) frame->rs_code); + install_sigtramp(frame->rs_code, __NR_rt_sigreturn); /* Create siginfo. */ err |= copy_siginfo_to_user(&frame->rs_info, info); Index: linux-qa/include/asm-mips/mach-ja/cpu-feature-overrides.h =================================================================== --- linux-qa.orig/include/asm-mips/mach-ja/cpu-feature-overrides.h 2005-06-14 12:53:28.000000000 +0100 +++ linux-qa/include/asm-mips/mach-ja/cpu-feature-overrides.h 2005-06-14 14:25:12.000000000 +0100 @@ -37,10 +37,4 @@ #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 -/* - * On the RM9000 we need to ensure that I-cache lines being fetches only - * contain valid instructions are funny things will happen. - */ -#define PLAT_TRAMPOLINE_STUFF_LINE 32UL - #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ Index: linux-qa/arch/mips/kernel/signal-common.h =================================================================== --- linux-qa.orig/arch/mips/kernel/signal-common.h 2005-06-14 12:53:28.000000000 +0100 +++ linux-qa/arch/mips/kernel/signal-common.h 2005-06-14 14:25:12.000000000 +0100 @@ -160,7 +160,7 @@ static inline void * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) { - unsigned long sp, almask; + unsigned long sp; /* Default to using normal stack */ sp = regs->regs[29]; @@ -176,10 +176,32 @@ if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0)) sp = current->sas_ss_sp + current->sas_ss_size; - if (PLAT_TRAMPOLINE_STUFF_LINE) - almask = ~(PLAT_TRAMPOLINE_STUFF_LINE - 1); - else - almask = ALMASK; + return (void *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? 32 : ALMASK)); +} + +static inline int install_sigtramp(unsigned int __user *tramp, + unsigned int syscall) +{ + int err; + + /* + * Set up the return code ... + * + * li v0, __NR__foo_sigreturn + * syscall + */ + + err |= __put_user(0x24020000 + syscall, tramp + 0); + err |= __put_user(0x0000000c , tramp + 1); + if (ICACHE_REFILLS_WORKAROUND_WAR) { + err |= __put_user(0, tramp + 2); + err |= __put_user(0, tramp + 3); + err |= __put_user(0, tramp + 4); + err |= __put_user(0, tramp + 5); + err |= __put_user(0, tramp + 6); + err |= __put_user(0, tramp + 7); + } + flush_cache_sigtramp((unsigned long) tramp); - return (void *)((sp - frame_size) & almask); + return err; } Index: linux-qa/include/asm-mips/war.h =================================================================== --- linux-qa.orig/include/asm-mips/war.h 2005-06-14 12:53:28.000000000 +0100 +++ linux-qa/include/asm-mips/war.h 2005-06-14 14:25:12.000000000 +0100 @@ -177,6 +177,17 @@ #endif /* + * The RM9000 has a bug (though PMC-Sierra opposes it being called that) + * where invalid instructions in the same I-cache line worth of instructions + * being fetched may case spurious exceptions. + */ +#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ + defined(CONFIG_PMC_YOSEMITE) +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#endif + + +/* * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ @@ -187,6 +198,9 @@ /* * Workarounds default to off */ +#ifndef ICACHE_REFILLS_WORKAROUND_WAR +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#endif #ifndef R4600_V1_INDEX_ICACHEOP_WAR #define R4600_V1_INDEX_ICACHEOP_WAR 0 #endif Index: linux-qa/arch/mips/kernel/signal32.c =================================================================== --- linux-qa.orig/arch/mips/kernel/signal32.c 2005-06-14 12:53:28.000000000 +0100 +++ linux-qa/arch/mips/kernel/signal32.c 2005-06-14 15:47:24.000000000 +0100 @@ -7,6 +7,7 @@ * Copyright (C) 1994 - 2000 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ +#include #include #include #include @@ -30,6 +31,7 @@ #include #include #include +#include #define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3) @@ -392,16 +394,30 @@ struct sigframe { u32 sf_ass[4]; /* argument save space for o32 */ +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_pad[2]; +#else u32 sf_code[2]; /* signal trampoline */ +#endif struct sigcontext32 sf_sc; sigset_t sf_mask; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */ +#endif }; struct rt_sigframe32 { u32 rs_ass[4]; /* argument save space for o32 */ +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_pad[2]; +#else u32 rs_code[2]; /* signal trampoline */ +#endif compat_siginfo_t rs_info; struct ucontext32 rs_uc; +#if ICACHE_REFILLS_WORKAROUND_WAR + u32 rs_code[8] __attribute__((aligned(32))); /* signal trampoline */ +#endif }; int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from) From ralf@linux-mips.org Tue Jun 14 18:21:36 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Jun 2005 18:21:52 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:58132 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Tue, 14 Jun 2005 18:21:36 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j5EHInh1028589; Tue, 14 Jun 2005 18:18:49 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j5EHInO8028588; Tue, 14 Jun 2005 18:18:49 +0100 Date: Tue, 14 Jun 2005 18:18:49 +0100 From: Ralf Baechle To: madprops@gmx.net Cc: linux-mips@linux-mips.org Subject: Re: tlb magic Message-ID: <20050614171848.GF5183@linux-mips.org> References: <17069.62407.584863.185198@mips.com> <18788.1118764826@www21.gmx.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <18788.1118764826@www21.gmx.net> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8090 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 14, 2005 at 06:00:26PM +0200, madprops@gmx.net wrote: > yes, I'm reading "See MIPS Run". So thanks for the online support that comes > with it. Now, if I got it correctly, the exception routing described in > section 6.7 uses per-process mappings for kseg2, i.e. that e.g. the first > 2MB of (each) kseg2 are used as page table of the corresponding process and > maybe another few kb for process related stuff. Provided the page tables are > continuously at the same address ( e.g. KSEG2_BASE ) a change of ASID in > EntryHi would indeed make a change of the kseg2 pointer in Context > unnecessary ( it always points to KSEG2_BASE ). The mapping of kseg2 would > automatically change as the global bit is set to zero. > > Using the standard page table approach I would now need an additional page > table for each process in order to map those 2+x MB in kseg2 which I could > put in kseg0/1 or in kseg2 with 'wired' TLB entries. > > If that's the way to go - why is it only used in early BSD ports of like > 1987 ? Are there any troubles with it or have other mechanisms turned out to > be better for any reason ? I don't know the details of how it was used in BSD. But this is how very early Linux/MIPS kernels were doing it on R4000 class processors: - the entire 4MB of pagetables are mapped into KSEG2 at 0xe4000000 - Linux likes to think of pagetables as 2-level trees (simplifying things a little here). - So at 4kB pagesize and 4 byte entries for each page the root of the tree will end up at root = (base + (base >> (12 - 2)) where base is 0xe4000000; 12 the log2 of the pagesize and 2 the log2 of 4. So root compute to 0xe4390000. Now let's see how we handle a pagefault in this scheme: - we take an exception and go to the reload handler at 0x80000000. - The CPU tries to help us [1] by with the value in the context register which with a little munging (see [1]) we use to index the 4MB of pagetables and load the right pagetable entry, then eret. That's the fast path. Now for the slow path. We enter it if indexing the mapped pagetable array at 0xe4000000 results in a TLB miss exception. But we're already in a TLB exception handler running with the EXL flag in the status register set: - we jump to 0x80000180 - we see it's a TLB exception, so branch to the TLB exception handler - The TLB exception handler figures out what kind of work it has to do. I only cover the TLB reload case here. - By now we know it must have been an access to the pagetable mapping that has failed. - We start all over by first indexing the 4kB of the root at 0xe439000 with the upper 10 bits of the virtual address and loading the entry found there into the TLB. At this point we can guarantee that if we resume execution will take an exception again but we'll only use the fast path part of the handlers. So I guess by this point you're asking why this magic address for the TLB root. As mentioned previously Linux consideres pagetables a two level tree and the root of that tree (the first level) data structure happens to be suitable as the pagetable to map the 4MB of second level data. So on a context switch all that's needed is swapping the content of this one wired entry holding the root pointer and ASID and voilla, we've magically changed the mappings for the entire 4MB of pagetables. I eventually removed that code because it was resulting in cache aliases and felt that fixing them would eleminate the performance advantage of this relativly complicated scheme. It certainly was too funky for an early stage OS and we may reconsider. Ralf [1] but doesn't really succeed because for 4-byte pagetable entries the values in the context and xcontext registers are not formed the way we'd prefer them ... From macro@linux-mips.org Tue Jun 14 19:25:57 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Jun 2005 19:26:14 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([IPv6:::ffff:153.19.208.7]:33289 "EHLO pollux.ds.pg.gda.pl") by linux-mips.org with ESMTP id ; Tue, 14 Jun 2005 19:25:57 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id CF991F59DA for ; Tue, 14 Jun 2005 20:25:50 +0200 (CEST) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 22814-08 for ; Tue, 14 Jun 2005 20:25:50 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 9E77FF59D8 for ; Tue, 14 Jun 2005 20:25:50 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.3/8.13.1) with ESMTP id j5EIPtVc032249 for ; Tue, 14 Jun 2005 20:25:55 +0200 Date: Tue, 14 Jun 2005 19:26:05 +0100 (BST) From: "Maciej W. Rozycki" To: linux-mips@linux-mips.org Subject: [announce] GCC 4.0.0 packages available Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.85.1/939/Tue Jun 14 16:29:23 2005 on piorun.ds.pg.gda.pl X-Virus-Status: Clean X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8091 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Hello, I have updated my RPM package archive to include sources and binaries of the 4.0.0 release of GCC. The following compilers are available: 1. A mipsel-linux cross-compiler hosted on i386-linux. 2. A mips64el-linux cross-compiler hosted on i386-linux. 3. A native mipsel-linux compiler. 4. A native mips64el-linux compiler. 5. There may be others, but I will not tell you. ;-) All compilers include all frontends, that is for Ada, C, C++, Fortran, Java and Objective-C. Note the mips64el-linux toolchains include local changes that make them produce (n)64 binaries by default and libraries are only (n)64. The native mips64el-linux environment is still limited, but usable. As a part of the transition to newer GCC glibc has been also updated to a more recent version, which is now 2.3.5. Unfortunately this version has binary incompatibilities with 2.2.x, which for mipsel-linux affects rpm, coreutils and tar, making their old binaries unusable. Also all static libraries need to be rebuilt. Packages are available at the usual location, i.e.: "ftp://ftp3.ds.pg.gda.pl/people/macro/". Maciej From Hiroshi_DOYU@montavista.co.jp Wed Jun 15 07:49:00 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Jun 2005 07:49:17 +0100 (BST) Received: from sonicwall.montavista.co.jp ([IPv6:::ffff:202.232.97.131]:62233 "EHLO yuubin.montavista.co.jp") by linux-mips.org with ESMTP id ; Wed, 15 Jun 2005 07:49:00 +0100 Received: from localhost.localdomain (oreo.jp.mvista.com [10.200.16.31]) by yuubin.montavista.co.jp (8.12.5/8.12.5) with SMTP id j5F6mrS5008043; Wed, 15 Jun 2005 15:48:54 +0900 Date: Wed, 15 Jun 2005 15:50:27 +0900 From: Hiroshi DOYU To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mlachwani@mvista.com Subject: [PATCH 1/1] MIPS 2.6 : NAND on TX4938(RBHMA4500) Message-Id: <20050615155027.24c7049e.Hiroshi_DOYU@montavista.co.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8092 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Hiroshi_DOYU@montavista.co.jp Precedence: bulk X-list: linux-mips Hello, This patch just enables NAND support on TX4938(RBHMA4500). Please review it. Hiroshi DOYU ----- Index: linux/arch/mips/Kconfig =================================================================== --- linux.orig/arch/mips/Kconfig 2005-06-15 14:33:22.754953832 +0900 +++ linux/arch/mips/Kconfig 2005-06-15 14:56:23.659024504 +0900 @@ -657,6 +657,7 @@ source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" source "arch/mips/tx4927/Kconfig" +source "arch/mips/tx4938/Kconfig" source "arch/mips/vr41xx/Kconfig" endmenu Index: linux/arch/mips/tx4938/Kconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/Kconfig 2005-06-15 15:29:03.284116208 +0900 @@ -0,0 +1,23 @@ +comment "Multiplex Pin Select" +choice + prompt "PIO[58:61]" + default TOSHIBA_RBTX4938_MPLEX_PIO58_61 + +config TOSHIBA_RBTX4938_MPLEX_PIO58_61 + bool "PIO" +config TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND" +config TOSHIBA_RBTX4938_MPLEX_ATA + bool "ATA" + +endchoice + +config TX4938_NAND_BOOT + depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND Boot Support (EXPERIMENTAL)" + help + This is only for Toshiba RBTX4938 reference board, which has NAND IPL. + Select this option if you need to use NAND boot. + + + Index: linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c =================================================================== --- linux.orig/arch/mips/tx4938/toshiba_rbtx4938/prom.c 2005-06-15 14:33:22.759953072 +0900 +++ linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c 2005-06-15 15:31:25.357517768 +0900 @@ -45,9 +45,9 @@ { extern int tx4938_get_mem_size(void); int msize; - +#ifndef CONFIG_TX4938_NAND_BOOT prom_init_cmdline(); - +#endif mips_machgroup = MACH_GROUP_TOSHIBA; mips_machtype = MACH_TOSHIBA_RBTX4938; From tsattler@gmx.de Wed Jun 15 14:46:31 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Jun 2005 14:46:48 +0100 (BST) Received: from imap.gmx.net ([IPv6:::ffff:213.165.64.20]:10957 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Wed, 15 Jun 2005 14:46:31 +0100 Received: (qmail invoked by alias); 15 Jun 2005 13:46:22 -0000 Received: from p54B09D19.dip0.t-ipconnect.de (EHLO nancy.sattler.local) [84.176.157.25] by mail.gmx.net (mp028) with SMTP; 15 Jun 2005 15:46:22 +0200 X-Authenticated: #1474915 Received: from localhost (localhost [127.0.0.1]) by nancy.sattler.local (Postfix) with ESMTP id D7EA327518; Wed, 15 Jun 2005 15:46:22 +0200 (CEST) Received: from nancy.sattler.local ([127.0.0.1]) by localhost (nancy [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 07475-01; Wed, 15 Jun 2005 15:46:10 +0200 (CEST) Received: by nancy.sattler.local (Postfix, from userid 9682) id 19C6B2751B; Wed, 15 Jun 2005 15:46:07 +0200 (CEST) Date: Wed, 15 Jun 2005 15:46:07 +0200 From: Thomas Sattler To: linux-mips@linux-mips.org Subject: no power on USB on linux 2.6? Message-ID: <20050615134607.GA19510@nancy.sattler.local> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Virus-Scanned: by amavisd-new-20030616-p10 (Debian) at sattler.local X-Y-GMX-Trusted: 0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8093 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsattler@gmx.de Precedence: bulk X-list: linux-mips Hi there ... My name is Thomas I'm trying to use an USB-headset on a meshcube, a MIPS based embedded device (http://meshcube.org/meshwiki/). If I plug in the headset while running 2.4.27 a led on the headset turns on. If I do the same with 2.6.12-rc6 (latest MIPS CVS) nothing happens. I also tried an optical USB-mouse with the same result. All these tests are done with Debian GNU/Linux Sarge 3.1 on NFS-root. My kernelconfig is: $ sed '/^#/d;/USB/!d' .config CONFIG_SND_USB_AUDIO=m CONFIG_USB=y CONFIG_USB_DEBUG=y CONFIG_USB_DEVICEFS=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_EHCI_HCD=m CONFIG_USB_OHCI_HCD=y CONFIG_USB_HID=y CONFIG_USB_HIDINPUT=y kernel boot messages are: usbcore: registered new driver usbfs usbcore: registered new driver hub [...] au1xxx-ohci au1xxx-ohci.0: Au1xxx OHCI au1xxx-ohci au1xxx-ohci.0: new USB bus registered, assigned bus number 1 au1xxx-ohci au1xxx-ohci.0: irq 26, io mem 0x10100000 usb usb1: Product: Au1xxx OHCI usb usb1: Manufacturer: Linux 2.6.12-rc6 ohci_hcd usb usb1: SerialNumber: Au1xxx hub 1-0:1.0: USB hub found hub 1-0:1.0: 2 ports detected USB Universal Host Controller Interface driver v2.2 sl811: driver sl811-hcd, 19 May 2005 FYI 2.4.27 messages: usb.c: registered new driver usbdevfs usb.c: registered new driver hub host/usb-ohci.c: USB OHCI at membase 0xb0100000, IRQ 26 host/usb-ohci.c: usb-builtin, non-PCI OHCI usb.c: new USB bus registered, assigned bus number 1 hub.c: USB hub found hub.c: 2 ports detected hotplug (initscripts) report: Starting hotplug subsystem: pci pci [success] usb usb [success] isapnp isapnp [success] ide ide [success] input input [success] scsi scsi [success] done. the proc-filesystem tells: $ cat /proc/bus/usb/devices T: Bus=01 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=12 MxCh= 2 B: Alloc= 0/900 us ( 0%), #Int= 0, #Iso= 0 D: Ver= 1.10 Cls=09(hub ) Sub=00 Prot=00 MxPS= 8 #Cfgs= 1 P: Vendor=0000 ProdID=0000 Rev= 2.06 S: Manufacturer=Linux 2.6.11 ohci_hcd S: Product=Au1xxx OHCI S: SerialNumber=au1xxx C:* #Ifs= 1 Cfg#= 1 Atr=c0 MxPwr= 0mA I: If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub E: Ad=81(I) Atr=03(Int.) MxPS= 2 Ivl=255ms As far as I can see USB drivers are working correctly, hardware is detected but the USB is not working. Any hints? TIA Thomas -- Please keep mailinglists in english as they are meant to be read in the whole world. -- Feel free to send PM in german. From bruno.randolf@4g-systems.biz Wed Jun 15 14:57:46 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Jun 2005 14:58:02 +0100 (BST) Received: from grey.subnet.at ([IPv6:::ffff:193.170.141.20]:41230 "EHLO grey.subnet.at") by linux-mips.org with ESMTP id ; Wed, 15 Jun 2005 14:57:46 +0100 Received: from ip6-localhost ([193.170.141.4]) by grey.subnet.at ; Wed, 15 Jun 2005 15:57:33 +0200 From: Bruno Randolf To: Thomas Sattler Subject: Re: no power on USB on linux 2.6? Date: Wed, 15 Jun 2005 15:57:12 +0200 User-Agent: KMail/1.7.2 References: <20050615134607.GA19510@nancy.sattler.local> In-Reply-To: <20050615134607.GA19510@nancy.sattler.local> Organization: 4G Systems Cc: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart2399852.cK5e4SeS4U"; protocol="application/pgp-signature"; micalg=pgp-sha1 Content-Transfer-Encoding: 7bit Message-Id: <200506151557.17731.bruno.randolf@4g-systems.biz> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8094 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bruno.randolf@4g-systems.biz Precedence: bulk X-list: linux-mips --nextPart2399852.cK5e4SeS4U Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline hi thomas! i think the problem is that in arch/mips/au1000/mtx-1/board_setup.c the pow= er=20 switch for USB is turned on if CONFIG_USB_OHCI is defined. this seems to ha= ve=20 changed to CONFIG_USB_OHCI_HCD. bruno On Wednesday 15 June 2005 15:46, you wrote: > Hi there ... > > My name is Thomas I'm trying to use an USB-headset on a meshcube, a MIPS > based embedded device (http://meshcube.org/meshwiki/). If I plug in the > headset while running 2.4.27 a led on the headset turns on. If I do the > same with 2.6.12-rc6 (latest MIPS CVS) nothing happens. I also tried an > optical USB-mouse with the same result. All these tests are done with > Debian GNU/Linux Sarge 3.1 on NFS-root. > > My kernelconfig is: > $ sed '/^#/d;/USB/!d' .config > CONFIG_SND_USB_AUDIO=3Dm > CONFIG_USB=3Dy > CONFIG_USB_DEBUG=3Dy > CONFIG_USB_DEVICEFS=3Dy > CONFIG_USB_ARCH_HAS_HCD=3Dy > CONFIG_USB_ARCH_HAS_OHCI=3Dy > CONFIG_USB_EHCI_HCD=3Dm > CONFIG_USB_OHCI_HCD=3Dy > CONFIG_USB_HID=3Dy > CONFIG_USB_HIDINPUT=3Dy > > kernel boot messages are: > usbcore: registered new driver usbfs > usbcore: registered new driver hub > [...] > au1xxx-ohci au1xxx-ohci.0: Au1xxx OHCI > au1xxx-ohci au1xxx-ohci.0: new USB bus registered, assigned bus number 1 > au1xxx-ohci au1xxx-ohci.0: irq 26, io mem 0x10100000 > usb usb1: Product: Au1xxx OHCI > usb usb1: Manufacturer: Linux 2.6.12-rc6 ohci_hcd > usb usb1: SerialNumber: Au1xxx > hub 1-0:1.0: USB hub found > hub 1-0:1.0: 2 ports detected > USB Universal Host Controller Interface driver v2.2 > sl811: driver sl811-hcd, 19 May 2005 > > FYI 2.4.27 messages: > usb.c: registered new driver usbdevfs > usb.c: registered new driver hub > host/usb-ohci.c: USB OHCI at membase 0xb0100000, IRQ 26 > host/usb-ohci.c: usb-builtin, non-PCI OHCI > usb.c: new USB bus registered, assigned bus number 1 > hub.c: USB hub found > hub.c: 2 ports detected > > hotplug (initscripts) report: > Starting hotplug subsystem: > pci > pci [success] > usb > usb [success] > isapnp > isapnp [success] > ide > ide [success] > input > input [success] > scsi > scsi [success] > done. > > the proc-filesystem tells: > $ cat /proc/bus/usb/devices > T: Bus=3D01 Lev=3D00 Prnt=3D00 Port=3D00 Cnt=3D00 Dev#=3D 1 Spd=3D12 = MxCh=3D 2 > B: Alloc=3D 0/900 us ( 0%), #Int=3D 0, #Iso=3D 0 > D: Ver=3D 1.10 Cls=3D09(hub ) Sub=3D00 Prot=3D00 MxPS=3D 8 #Cfgs=3D 1 > P: Vendor=3D0000 ProdID=3D0000 Rev=3D 2.06 > S: Manufacturer=3DLinux 2.6.11 ohci_hcd > S: Product=3DAu1xxx OHCI > S: SerialNumber=3Dau1xxx > C:* #Ifs=3D 1 Cfg#=3D 1 Atr=3Dc0 MxPwr=3D 0mA > I: If#=3D 0 Alt=3D 0 #EPs=3D 1 Cls=3D09(hub ) Sub=3D00 Prot=3D00 Driv= er=3Dhub > E: Ad=3D81(I) Atr=3D03(Int.) MxPS=3D 2 Ivl=3D255ms > > As far as I can see USB drivers are working correctly, hardware is > detected but the USB is not working. Any hints? > > TIA > Thomas --nextPart2399852.cK5e4SeS4U Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (GNU/Linux) iD8DBQBCsDO9fg2jtUL97G4RAqoiAKCNy0KQ/7hjMy35y2uFoqESJTCs1ACgkbvL tohY3jOb9jPGgc/KaMghHqo= =hk95 -----END PGP SIGNATURE----- --nextPart2399852.cK5e4SeS4U-- From bruno.randolf@4g-systems.biz Wed Jun 15 15:36:05 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Jun 2005 15:36:20 +0100 (BST) Received: from grey.subnet.at ([IPv6:::ffff:193.170.141.20]:55310 "EHLO grey.subnet.at") by linux-mips.org with ESMTP id ; Wed, 15 Jun 2005 15:36:05 +0100 Received: from ip6-localhost ([193.170.141.4]) by grey.subnet.at ; Wed, 15 Jun 2005 16:36:02 +0200 From: Bruno Randolf To: linux-mips@linux-mips.org Subject: au1xxx MTD with 2.6 Date: Wed, 15 Jun 2005 16:35:48 +0200 User-Agent: KMail/1.7.2 Organization: 4G Systems MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart1733115.dtjvy5rAhf"; protocol="application/pgp-signature"; micalg=pgp-sha1 Content-Transfer-Encoding: 7bit Message-Id: <200506151635.52261.bruno.randolf@4g-systems.biz> X-Rcpt-To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8095 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bruno.randolf@4g-systems.biz Precedence: bulk X-list: linux-mips --nextPart1733115.dtjvy5rAhf Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline hi! speaking of linux 2.6 on the meshcube: the last major problem i have with 2= =2E6=20 support is MTD: the flash size is not recognized correctly. i added=20 +#ifdef CONFIG_MIPS_MTX1 +#define BOARD_MAP_NAME "MTX-1 Flash" +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif to drivers/mtd/maps/alchemy-flash.c, which is about the aequivalent of what= =20 was necessary for the 2.4 kernel. but now flash is not recognized correctly anymore, it seems only half of it= is=20 recognized. here is the output (with some debugging printk's from me): MTX-1 Flash: probing 32-bit flash bus 1e000000 2000000 bla be000000 *** map_info size: 2000000 MTX-1 Flash: Found 1 x32 devices at 0x0 in 32-bit bank Amd/Fujitsu Extended Query Table at 0x0040 Using buffer write method MTX-1 Flash: CFI does not contain boot bank location. Assuming top. number of CFI chips: 1 cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness. *** mtd_info size: 1000000 Creating 4 MTD partitions on "MTX-1 Flash": 0x00000000-0x01c00000 : "User FS" mtd: partition "User FS" extends beyond the end of device "MTX-1 Flash" --= =20 size truncated to 0x1000000 mtd: Giving out device 0 to User FS 0x01c00000-0x01d00000 : "YAMON" mtd: partition "YAMON" is out of reach -- disabled mtd: Giving out device 1 to YAMON 0x01d00000-0x01fc0000 : "raw kernel" mtd: partition "raw kernel" is out of reach -- disabled mtd: Giving out device 2 to raw kernel 0x01fc0000-0x02000000 : "YAMON env" mtd: partition "YAMON env" is out of reach -- disabled mtd: Giving out device 3 to YAMON env mice: PS/2 mouse device common for all mice NET: Registered protocol family 2 since we have two AMDL128ML flash chips (which are 16bit) on board, i also= =20 tried it with BOARD_FLASH_WIDTH 2, but this leads to the same errors. does the alchemy-flash mapping work for the other au1xxx users? any ideas w= hat=20 might be the problem? thanks for any hints, bruno --nextPart1733115.dtjvy5rAhf Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (GNU/Linux) iD8DBQBCsDzIfg2jtUL97G4RAkauAJ9Rxs71nxxOJA7FMGJE9LMAnWRLEACgrZcA 9o8azdLhPC8KCtSDbj+Y/mg= =pAr5 -----END PGP SIGNATURE----- --nextPart1733115.dtjvy5rAhf-- From tsattler@gmx.de Wed Jun 15 19:12:45 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Jun 2005 19:13:03 +0100 (BST) Received: from pop.gmx.de ([IPv6:::ffff:213.165.64.20]:49092 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Wed, 15 Jun 2005 19:12:45 +0100 Received: (qmail invoked by alias); 15 Jun 2005 18:12:36 -0000 Received: from p54B09D19.dip0.t-ipconnect.de (EHLO nancy.sattler.local) [84.176.157.25] by mail.gmx.net (mp011) with SMTP; 15 Jun 2005 20:12:36 +0200 X-Authenticated: #1474915 Received: from localhost (localhost [127.0.0.1]) by nancy.sattler.local (Postfix) with ESMTP id 565C327527; Wed, 15 Jun 2005 20:12:36 +0200 (CEST) Received: from nancy.sattler.local ([127.0.0.1]) by localhost (nancy [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 13440-02; Wed, 15 Jun 2005 20:12:23 +0200 (CEST) Received: by nancy.sattler.local (Postfix, from userid 9682) id 7FECF27540; Wed, 15 Jun 2005 20:12:22 +0200 (CEST) Date: Wed, 15 Jun 2005 20:12:22 +0200 From: Thomas Sattler To: Bruno Randolf Cc: linux-mips@linux-mips.org Subject: Re: no power on USB on linux 2.6? Message-ID: <20050615181221.GA26155@nancy.sattler.local> References: <20050615134607.GA19510@nancy.sattler.local> <200506151557.17731.bruno.randolf@4g-systems.biz> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="a8Wt8u1KmwUX3Y2C" Content-Disposition: inline In-Reply-To: <200506151557.17731.bruno.randolf@4g-systems.biz> X-Virus-Scanned: by amavisd-new-20030616-p10 (Debian) at sattler.local X-Y-GMX-Trusted: 0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8096 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsattler@gmx.de Precedence: bulk X-list: linux-mips --a8Wt8u1KmwUX3Y2C Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi there ... If Bruno is right and CONFIG_USB_OHCI simply was renamed to CONFIG_USB_OHCI_HCD than there are currently six files in the CVS that sould be patched (patch attached): arch/mips/au1000/csb250/board_setup.c arch/mips/au1000/mtx-1/board_setup.c arch/mips/au1000/pb1000/board_setup.c arch/mips/au1000/pb1100/board_setup.c arch/mips/au1000/pb1500/board_setup.c drivers/char/au1000_gpio.c BTW: My cube is playing ABBA 'Dancing Queen' right now! :-) Thomas --a8Wt8u1KmwUX3Y2C Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="usbohci2usbohcihcd.patch" diff -Nur linux-latest/arch/mips/au1000/csb250/board_setup.c linux-patched/arch/mips/au1000/csb250/board_setup.c --- linux-latest/arch/mips/au1000/csb250/board_setup.c 2005-01-15 00:59:07.000000000 +0100 +++ linux-patched/arch/mips/au1000/csb250/board_setup.c 2005-06-15 19:53:17.000000000 +0200 @@ -59,7 +59,7 @@ au_writel(0, SYS_PINSTATERD); udelay(100); -#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#if defined (CONFIG_USB_OHCI_HCD) || defined (CONFIG_AU1X00_USB_DEVICE) /* GPIO201 is input for PCMCIA card detect */ /* GPIO203 is input for PCMCIA interrupt request */ @@ -88,7 +88,7 @@ /* * Route 48MHz FREQ2 into USB Host and/or Device */ -#ifdef CONFIG_USB_OHCI +#ifdef CONFIG_USB_OHCI_HCD sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); #endif #ifdef CONFIG_AU1X00_USB_DEVICE @@ -103,7 +103,7 @@ pin_func |= 0x8000; #endif au_writel(pin_func, SYS_PINFUNC); -#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#endif // defined (CONFIG_USB_OHCI_HCD) || defined (CONFIG_AU1X00_USB_DEVICE) /* Configure GPIO2....it's used by PCI among other things. */ diff -Nur linux-latest/arch/mips/au1000/mtx-1/board_setup.c linux-patched/arch/mips/au1000/mtx-1/board_setup.c --- linux-latest/arch/mips/au1000/mtx-1/board_setup.c 2005-06-15 17:35:59.000000000 +0200 +++ linux-patched/arch/mips/au1000/mtx-1/board_setup.c 2005-06-15 19:53:17.000000000 +0200 @@ -52,7 +52,7 @@ void __init board_setup(void) { -#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#if defined (CONFIG_USB_OHCI_HCD) || defined (CONFIG_AU1X00_USB_DEVICE) #ifdef CONFIG_AU1X00_USB_DEVICE // 2nd USB port is USB device au_writel(au_readl(SYS_PINFUNC) & (u32)(~0x8000), SYS_PINFUNC); @@ -60,7 +60,7 @@ // enable USB power switch au_writel( au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR ); au_writel( 0x100000, GPIO2_OUTPUT ); -#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#endif // defined (CONFIG_USB_OHCI_HCD) || defined (CONFIG_AU1X00_USB_DEVICE) #ifdef CONFIG_PCI #if defined(__MIPSEB__) diff -Nur linux-latest/arch/mips/au1000/pb1000/board_setup.c linux-patched/arch/mips/au1000/pb1000/board_setup.c --- linux-latest/arch/mips/au1000/pb1000/board_setup.c 2005-01-19 03:18:44.000000000 +0100 +++ linux-patched/arch/mips/au1000/pb1000/board_setup.c 2005-06-15 19:53:17.000000000 +0200 @@ -55,7 +55,7 @@ au_writel(0, SYS_PINSTATERD); udelay(100); -#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#if defined (CONFIG_USB_OHCI_HCD) || defined (CONFIG_AU1X00_USB_DEVICE) /* zero and disable FREQ2 */ sys_freqctrl = au_readl(SYS_FREQCTRL0); sys_freqctrl &= ~0xFFF00000; @@ -103,7 +103,7 @@ /* * Route 48MHz FREQ2 into USB Host and/or Device */ -#ifdef CONFIG_USB_OHCI +#ifdef CONFIG_USB_OHCI_HCD sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); #endif #ifdef CONFIG_AU1X00_USB_DEVICE @@ -121,7 +121,7 @@ au_writel(pin_func, SYS_PINFUNC); au_writel(0x2800, SYS_TRIOUTCLR); au_writel(0x0030, SYS_OUTPUTCLR); -#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#endif // defined (CONFIG_USB_OHCI_HCD) || defined (CONFIG_AU1X00_USB_DEVICE) // make gpio 15 an input (for interrupt line) pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100); diff -Nur linux-latest/arch/mips/au1000/pb1100/board_setup.c linux-patched/arch/mips/au1000/pb1100/board_setup.c --- linux-latest/arch/mips/au1000/pb1100/board_setup.c 2005-01-15 00:56:38.000000000 +0100 +++ linux-patched/arch/mips/au1000/pb1100/board_setup.c 2005-06-15 19:53:17.000000000 +0200 @@ -56,7 +56,7 @@ au_writel(0, SYS_PININPUTEN); udelay(100); -#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#if defined (CONFIG_USB_OHCI_HCD) || defined (CONFIG_AU1X00_USB_DEVICE) // configure pins GPIO[14:9] as GPIO pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x80); @@ -98,7 +98,7 @@ pin_func |= 0x8000; #endif au_writel(pin_func, SYS_PINFUNC); -#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#endif // defined (CONFIG_USB_OHCI_HCD) || defined (CONFIG_AU1X00_USB_DEVICE) /* Enable sys bus clock divider when IDLE state or no bus activity. */ au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); diff -Nur linux-latest/arch/mips/au1000/pb1500/board_setup.c linux-patched/arch/mips/au1000/pb1500/board_setup.c --- linux-latest/arch/mips/au1000/pb1500/board_setup.c 2005-01-15 00:56:38.000000000 +0100 +++ linux-patched/arch/mips/au1000/pb1500/board_setup.c 2005-06-15 19:53:17.000000000 +0200 @@ -57,7 +57,7 @@ au_writel(0, SYS_PINSTATERD); udelay(100); -#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#if defined (CONFIG_USB_OHCI_HCD) || defined (CONFIG_AU1X00_USB_DEVICE) /* GPIO201 is input for PCMCIA card detect */ /* GPIO203 is input for PCMCIA interrupt request */ @@ -86,7 +86,7 @@ /* * Route 48MHz FREQ2 into USB Host and/or Device */ -#ifdef CONFIG_USB_OHCI +#ifdef CONFIG_USB_OHCI_HCD sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); #endif #ifdef CONFIG_AU1X00_USB_DEVICE @@ -101,7 +101,7 @@ pin_func |= 0x8000; #endif au_writel(pin_func, SYS_PINFUNC); -#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#endif // defined (CONFIG_USB_OHCI_HCD) || defined (CONFIG_AU1X00_USB_DEVICE) diff -Nur linux-latest/drivers/char/au1000_gpio.c linux-patched/drivers/char/au1000_gpio.c --- linux-latest/drivers/char/au1000_gpio.c 2005-02-28 14:35:57.000000000 +0100 +++ linux-patched/drivers/char/au1000_gpio.c 2005-06-15 19:53:17.000000000 +0200 @@ -84,7 +84,7 @@ avail_mask &= ~(inl(IC1_MASKRD) & (inl(IC1_CFG0RD) | inl(IC1_CFG1RD))); -#ifdef CONFIG_USB_OHCI +#ifdef CONFIG_USB_OHCI_HCD avail_mask &= ~((1<<4) | (1<<11)); #ifndef CONFIG_AU1X00_USB_DEVICE avail_mask &= ~((1<<5) | (1<<13)); --a8Wt8u1KmwUX3Y2C-- From tom@voda.cz Wed Jun 15 22:54:21 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 15 Jun 2005 22:54:38 +0100 (BST) Received: from gw.voda.cz ([IPv6:::ffff:212.24.154.90]:4499 "EHLO smtp.voda.cz") by linux-mips.org with ESMTP id ; Wed, 15 Jun 2005 22:54:21 +0100 Received: from [10.1.1.77] (unknown [213.151.77.162]) by smtp.voda.cz (Postfix) with ESMTP id DC11F13C5B for ; Wed, 15 Jun 2005 23:54:18 +0200 (CEST) Message-ID: <42B0A38A.6050504@voda.cz> Date: Wed, 15 Jun 2005 23:54:18 +0200 From: =?ISO-8859-2?Q?Tom_Vr=E1na?= Organization: VODA IT consulting User-Agent: Mozilla Thunderbird 0.6 (X11/20040502) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: kernel compilation fails Content-Type: text/plain; charset=ISO-8859-2; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8097 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tom@voda.cz Precedence: bulk X-list: linux-mips Hi, I am desperately trying to compile 2.4.30 mips kernel using uclibc buildroot gcc 3.3.4 It fails in the following manner: mipsel-linux-gcc -D__KERNEL__ -I/store/devel/adm/linux-2.4.30-mipscvs-20050614/include -Wall -Wstrict-prototypes -Wno-trigraphs -O2 -fno-strict-aliasing -fno-common -fomit-frame-pointer -I /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/gcc -G 0 -mno-abicalls -fno-pic -pipe -finline-limit=100000 -mabi=32 -march=r4600 -Wa,-32 -Wa,-march=r4600 -Wa,-mips3 -Wa,--trap -c mipsIRQ.S -o mipsIRQ.o /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h: Assembler messages: /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:172: Error: unrecognized opcode `__asm__(' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:173: Warning: rest of line ignored; first ignored character is `"' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:174: Warning: rest of line ignored; first ignored character is `"' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:175: Warning: rest of line ignored; first ignored character is `"' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:176: Warning: rest of line ignored; first ignored character is `"' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:177: Warning: rest of line ignored; first ignored character is `"' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:178: Warning: rest of line ignored; first ignored character is `"' Looks like a stupid typo somewhere, but I lack experience to find. BTW, the some code is taken from 2.4.18 kernel... Can anyone please tell me where to look ? Thanks, Tom -- Tomas Vrana -------------------------- VODA IT consulting, Borkovany 48, 691 75 http://www.voda.cz/ phone: +420 519 419 416 mobile: +420 603 469 305 UIN: 105142752 From sundarapandian.andithevar@philips.com Thu Jun 16 06:23:08 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Jun 2005 06:23:42 +0100 (BST) Received: from gw-eur4.philips.com ([IPv6:::ffff:161.85.125.10]:33162 "EHLO gw-eur4.philips.com") by linux-mips.org with ESMTP id ; Thu, 16 Jun 2005 06:23:08 +0100 Received: from smtpscan-eur4.philips.com (smtpscan-eur4.mail.philips.com [130.144.57.167]) by gw-eur4.philips.com (Postfix) with ESMTP id 54EA14970B; Thu, 16 Jun 2005 05:23:02 +0000 (UTC) Received: from smtpscan-eur4.philips.com (localhost [127.0.0.1]) by localhost.philips.com (Postfix) with ESMTP id 27CE29B; Thu, 16 Jun 2005 05:23:02 +0000 (GMT) Received: from smtprelay-eur2.philips.com (smtprelay-eur2.philips.com [130.144.57.171]) by smtpscan-eur4.philips.com (Postfix) with ESMTP id 0D8A3EF; Thu, 16 Jun 2005 05:23:02 +0000 (GMT) Received: from ehvrmh02.diamond.philips.com (ehvrmh02-srv.diamond.philips.com [130.139.27.125]) by smtprelay-eur2.philips.com (Postfix) with ESMTP id B02E93F; Thu, 16 Jun 2005 05:23:01 +0000 (GMT) In-Reply-To: Subject: Re: XIO driver development To: Stanislaw Skowronek Cc: linux-mips@linux-mips.org X-Mailer: Lotus Notes Release 6.0.3 September 26, 2003 Message-ID: From: Sundarapandian Andithevar Date: Thu, 16 Jun 2005 10:52:15 +0530 X-MIMETrack: Serialize by Router on ehvrmh02/H/SERVER/PHILIPS(Release 6.5.3FP1HF80 | March 11, 2005) at 16/06/2005 07:22:23 MIME-Version: 1.0 Content-type: text/plain; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8098 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sundarapandian.andithevar@philips.com Precedence: bulk X-list: linux-mips Hi Stanislaw, I've gone through the APIs given at http://www.linux-mips.org/wiki/index.php/XIO_API, I believe that this may be suitable for what we are about to do!!! Regards, Sundar. To Sundarapandian Andithevar/BTC/SC/PHILIPS@PHILIPS Stanislaw Skowronek cc linux-mips@linux-mips.org Sent by: Subject linux-mips-bounce@li Re: XIO driver development nux-mips.org Classification 06/13/2005 11:16 AM Currently - on hold. However, seeing the company you represent... this is not the XIO you are looking for (probably). This is SGI XIO, not Philips XIO ("Hey, X is a cool letter, how do we call our bus?"). Stanislaw Skowronek From tom@voda.cz Thu Jun 16 10:37:57 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Jun 2005 10:38:15 +0100 (BST) Received: from gw.voda.cz ([IPv6:::ffff:212.24.154.90]:15048 "EHLO smtp.voda.cz") by linux-mips.org with ESMTP id ; Thu, 16 Jun 2005 10:37:57 +0100 Received: from [10.1.1.111] (unknown [213.151.77.162]) by smtp.voda.cz (Postfix) with ESMTP id 7EFDA148D0 for ; Thu, 16 Jun 2005 11:37:55 +0200 (CEST) Message-ID: <42B14872.8080103@voda.cz> Date: Thu, 16 Jun 2005 11:37:54 +0200 From: =?ISO-8859-2?Q?Tom=E1=B9_Vr=E1na?= User-Agent: Mozilla Thunderbird 0.9 (X11/20041103) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: [Fwd: kernel compilation fails] Content-Type: text/plain; charset=ISO-8859-2; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8099 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tom@voda.cz Precedence: bulk X-list: linux-mips Hi, did I just ask a real stupid question, or is my question unclear ? or... just give some feedback, please. TIA, Tom -------- Original Message -------- Subject: kernel compilation fails Date: Wed, 15 Jun 2005 23:54:18 +0200 From: Tom Vrána Organization: VODA IT consulting To: linux-mips@linux-mips.org Hi, I am desperately trying to compile 2.4.30 mips kernel using uclibc buildroot gcc 3.3.4 It fails in the following manner: mipsel-linux-gcc -D__KERNEL__ -I/store/devel/adm/linux-2.4.30-mipscvs-20050614/include -Wall -Wstrict-prototypes -Wno-trigraphs -O2 -fno-strict-aliasing -fno-common -fomit-frame-pointer -I /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/gcc -G 0 -mno-abicalls -fno-pic -pipe -finline-limit=100000 -mabi=32 -march=r4600 -Wa,-32 -Wa,-march=r4600 -Wa,-mips3 -Wa,--trap -c mipsIRQ.S -o mipsIRQ.o /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h: Assembler messages: /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:172: Error: unrecognized opcode `__asm__(' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:173: Warning: rest of line ignored; first ignored character is `"' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:174: Warning: rest of line ignored; first ignored character is `"' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:175: Warning: rest of line ignored; first ignored character is `"' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:176: Warning: rest of line ignored; first ignored character is `"' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:177: Warning: rest of line ignored; first ignored character is `"' /store/devel/adm/linux-2.4.30-mipscvs-20050614/include/asm/hazards.h:178: Warning: rest of line ignored; first ignored character is `"' Looks like a stupid typo somewhere, but I lack experience to find. BTW, the some code is taken from 2.4.18 kernel... Can anyone please tell me where to look ? Thanks, Tom -- Tomas Vrana -------------------------- VODA IT consulting, Borkovany 48, 691 75 http://www.voda.cz/ phone: +420 519 419 416 mobile: +420 603 469 305 UIN: 105142752 From philippedeswert@scarlet.be Thu Jun 16 10:54:45 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Jun 2005 10:55:02 +0100 (BST) Received: from guri.is.scarlet.be ([IPv6:::ffff:193.74.71.22]:56549 "EHLO guri.is.scarlet.be") by linux-mips.org with ESMTP id convert rfc822-to-8bit; Thu, 16 Jun 2005 10:54:45 +0100 Received: from (everest.is.scarlet.be [193.74.71.40]) by guri.is.scarlet.be with ESMTP id j5G9sgn31505; Thu, 16 Jun 2005 11:54:43 +0200 Date: Thu, 16 Jun 2005 10:54:43 +0100 Message-Id: Subject: Re:[Fwd: kernel compilation fails] MIME-Version: 1.0 X-Sensitivity: 3 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT From: "Philippe De Swert" To: "tom" Cc: "linux-mips" X-XaM3-API-Version: 4.1 (B54) X-type: 0 X-SenderIP: 195.144.76.34 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-Envid: I am desperately trying to compile 2.4.30 mips kernel using uclibc > buildroot gcc 3.3.4 It fails in the following manner: relevant error output > > Looks like a stupid typo somewhere, but I lack experience to find. BTW, > the some code is taken from 2.4.18 kernel... > Can anyone please tell me where to look ? Basically 2.4.18 code is too old to compile as is with gcc 3.3.4. The assembler code needs to be inlined with a different syntax. Just look at similar files to see how it is done. As a quick hint here is some code to show how it should look like. __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0"); Notice the \n and \t parts. You are probabely missing those. Otherwise use an older compiler (2.95). Cheers, Philippe | Philippe De Swert | | Stag developer http://stag.mind.be/ | Emdebian developer: http://www.emdebian.org | | Please do not send me documents in a closed | format.(*.doc,*.xls,*.ppt) | Use the open alternatives. (*.pdf,*.ps,*.html,*.txt) | http://www.gnu.org/philosophy/no-word-attachments.html ------------------------------------------------------- NOTE! My email address is changing to ... @scarlet.be Please make the necessary changes in your address book. From ralf@linux-mips.org Thu Jun 16 11:19:08 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Jun 2005 11:19:23 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:5393 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Thu, 16 Jun 2005 11:19:08 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j5GAG84J014165; Thu, 16 Jun 2005 11:16:08 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j5GAG7UV014164; Thu, 16 Jun 2005 11:16:07 +0100 Date: Thu, 16 Jun 2005 11:16:07 +0100 From: Ralf Baechle To: Tom =?iso-8859-1?Q?Vr=E1na?= Cc: linux-mips@linux-mips.org Subject: Re: kernel compilation fails Message-ID: <20050616101607.GF5202@linux-mips.org> References: <42B0A38A.6050504@voda.cz> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <42B0A38A.6050504@voda.cz> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8101 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 15, 2005 at 11:54:18PM +0200, Tom Vrána wrote: > I am desperately trying to compile 2.4.30 mips kernel using uclibc > buildroot gcc 3.3.4 It fails in the following manner: > > mipsel-linux-gcc -D__KERNEL__ > -I/store/devel/adm/linux-2.4.30-mipscvs-20050614/include -Wall > -Wstrict-prototypes -Wno-trigraphs -O2 -fno-strict-aliasing -fno-common > -fomit-frame-pointer -I > Looks like a stupid typo somewhere, but I lack experience to find. BTW, > the some code is taken from 2.4.18 kernel... > Can anyone please tell me where to look ? Sympthoms of a botched makefile transplant, it's lacking the USE_STANDARD_AS_RULE thing. Ralf From ralf@linux-mips.org Thu Jun 16 11:23:53 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 16 Jun 2005 11:24:07 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:13 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Thu, 16 Jun 2005 11:23:53 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j5GAKt41014383; Thu, 16 Jun 2005 11:20:55 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j5GAKtCT014382; Thu, 16 Jun 2005 11:20:55 +0100 Date: Thu, 16 Jun 2005 11:20:55 +0100 From: Ralf Baechle To: Philippe De Swert Cc: tom , linux-mips Subject: Re: [Fwd: kernel compilation fails] Message-ID: <20050616102054.GG5202@linux-mips.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8102 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jun 16, 2005 at 10:54:43AM +0100, Philippe De Swert wrote: > Basically 2.4.18 code is too old to compile as is with gcc 3.3.4. The > assembler code needs to be inlined with a different syntax. Just look at > similar files to see how it is done. Not true. Gcc 3.3 is probably even is the most commonly used compiler with 2.4-based systems. Builds with gcc 3.4 will fail for some 2.4 kernel configurations but at the very least throw loads of warnings. > As a quick hint here is some code to show how it should look like. > > > __asm__(".set\tmips3\n\t" > "wait\n\t" > ".set\tmips0"); > > Notice the \n and \t parts. You are probabely missing those. Actually more and more code it being formatted using tabs instead of the \t escape sequence for readability. Ralf From pf@net.alphadv.de Fri Jun 17 17:06:50 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 17 Jun 2005 17:07:08 +0100 (BST) Received: from mail.alphastar.de ([IPv6:::ffff:194.59.236.179]:41999 "EHLO mail.alphastar.de") by linux-mips.org with ESMTP id ; Fri, 17 Jun 2005 17:06:49 +0100 Received: from Snailmail (217.249.197.192) by mail.alphastar.de with MERCUR Mailserver (v4.02.28 MTIxLTIxODAtNjY2OA==) for ; Fri, 17 Jun 2005 18:04:22 +0200 Received: from Opal.Peter (pf@Opal.Peter [192.168.1.1]) by SNaIlmail.Peter (8.12.6/8.12.6/Sendmail/Linux 2.0.32) with ESMTP id j5HG609J000549 for ; Fri, 17 Jun 2005 18:06:01 +0200 Received: from localhost (pf@localhost) by Opal.Peter (8.9.3/8.9.3/Sendmail/Linux 2.2.5-15) with ESMTP id SAA00798 for ; Fri, 17 Jun 2005 18:05:47 +0200 Date: Fri, 17 Jun 2005 18:05:47 +0200 (CEST) From: peter fuerst To: linux-mips@linux-mips.org Subject: Updated Indigo2 IP28 patches. Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Reply-To: pf@net.alphadv.de Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8103 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pf@net.alphadv.de Precedence: bulk X-list: linux-mips Hello ! There are updated patches for SGI Indigo2 IP28 available at "http://home.alphastar.de/fuerst/download.html": 1) An extended bus error handler, which allows to avoid the too many cache-barriers (introduced with the last compiler-patch) before critical load instructions. 2) Stanislaw Skowronek's ImpactSR-graphics driver (many thanks...) could be adapted to IP28 Impact-graphics. kind regards pf From kevin.m.turner@pobox.com Sat Jun 18 23:56:45 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 18 Jun 2005 23:57:01 +0100 (BST) Received: from orb.pobox.com ([IPv6:::ffff:207.8.226.5]:18412 "EHLO orb.pobox.com") by linux-mips.org with ESMTP id ; Sat, 18 Jun 2005 23:56:45 +0100 Received: from orb (localhost [127.0.0.1]) by orb.pobox.com (Postfix) with ESMTP id CD3451FB3 for ; Sat, 18 Jun 2005 18:56:33 -0400 (EDT) Received: from troglodyte.asianpear (c-24-21-141-200.hsd1.or.comcast.net [24.21.141.200]) (using SSLv3 with cipher RC4-MD5 (128/128 bits)) (No client certificate requested) by orb.sasl.smtp.pobox.com (Postfix) with ESMTP id 84BAD87 for ; Sat, 18 Jun 2005 18:56:33 -0400 (EDT) Subject: xxs1500 hangs on CF wifi card insertion From: Kevin Turner To: linux-mips Content-Type: text/plain Date: Sat, 18 Jun 2005 15:57:17 -0700 Message-Id: <1119135438.1513.259.camel@troglodyte.asianpear> Mime-Version: 1.0 X-Mailer: Evolution 2.2.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8104 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevin.m.turner@pobox.com Precedence: bulk X-list: linux-mips running linux-mips.org linux_2_4 CVS on an xxs1500, compiled with gcc 3.4.3 with Pete's 64bit_pcmcia.patch and the corresponding patch to pcmcia-cs's copies of those include files. When I insert my sandisk connectplus wifi card, the hostap drivers load and start saying: kernel: wifi0: Interrupt, but dev not OK kernel: NET: 3067338 messages suppressed. and the system is unresponsive until I eject the card. With CONFIG_PM enabled, it seems to log somewhat fewer "Interrupt, but dev not OK" messages but has a lot of huge offset 12c992, last_pc0 47e3e1 last_match20 47e3e1 pc0 5aad73 huge offset 12ca53, last_pc0 47e3e1 last_match20 47e3e1 pc0 5aae34 messages with continuously growing values. here's the log prior to when it hangs: cardmgr[247]: socket 0: SanDisk ConnectPlus w/ Memory kernel: hostap_crypt: registered algorithm 'NULL' kernel: hostap_cs: 0.3.7 - 2005-02-12 (Jouni Malinen ) kernel: hostap_cs: setting Vcc=33 (constant) kernel: hostap_cs: CS_EVENT_CARD_INSERTION kernel: hostap_cs: ignoring Vcc=33 (from config) kernel: Checking CFTABLE_ENTRY 0x01 (default 0x01) kernel: IO window settings: cfg->io.nwin=1 dflt.io.nwin=1 kernel: io->flags = 0x0047, io.base=0x0000, len=128 kernel: hostap_cs: Registered netdevice wifi0 Any suggestions? Thanks, - Kevin -- The moon is waxing gibbous, 83.5% illuminated, 10.8 days old. From macro@linux-mips.org Mon Jun 20 11:27:47 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Jun 2005 11:28:05 +0100 (BST) Received: from pollux.ds.pg.gda.pl ([IPv6:::ffff:153.19.208.7]:56589 "EHLO pollux.ds.pg.gda.pl") by linux-mips.org with ESMTP id ; Mon, 20 Jun 2005 11:27:47 +0100 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id C3451F5992 for ; Mon, 20 Jun 2005 12:27:35 +0200 (CEST) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 15883-09 for ; Mon, 20 Jun 2005 12:27:35 +0200 (CEST) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 71233F598F for ; Mon, 20 Jun 2005 12:27:35 +0200 (CEST) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.3/8.13.1) with ESMTP id j5KARTCj011265 for ; Mon, 20 Jun 2005 12:27:29 +0200 Date: Mon, 20 Jun 2005 11:27:34 +0100 (BST) From: "Maciej W. Rozycki" To: linux-mips@linux-mips.org Subject: Re: CVS Update@linux-mips.org: linux In-Reply-To: <20050618135450Z8225248-1340+9141@linux-mips.org> Message-ID: References: <20050618135450Z8225248-1340+9141@linux-mips.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.85.1/946/Sun Jun 19 10:41:16 2005 on piorun.ds.pg.gda.pl X-Virus-Status: Clean X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8105 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, 18 Jun 2005 ralf@linux-mips.org wrote: > Modified files: > arch/mips/configs: decstation_defconfig > > Log message: > Grrr.. Update the bloody thing when you change the kconfig files. Who cares at this point, anyway?... ;-) Maciej From sjr@debian.org Mon Jun 20 12:33:50 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Jun 2005 12:34:17 +0100 (BST) Received: from kleinhenz.com ([IPv6:::ffff:213.239.205.196]:13784 "EHLO kleinhenz.com") by linux-mips.org with ESMTP id ; Mon, 20 Jun 2005 12:33:50 +0100 Received: from [192.168.115.33] (p549972E0.dip.t-dialin.net [84.153.114.224]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "Simon Richter", Issuer "Kleinhenz Elektronik CA" (verified OK)) by kleinhenz.com (Postfix) with ESMTP id 74A684A8003; Mon, 20 Jun 2005 13:33:48 +0200 (CEST) Message-ID: <42B6A990.2040001@debian.org> Date: Mon, 20 Jun 2005 13:33:36 +0200 From: Simon Richter User-Agent: Mozilla Thunderbird 1.0.2 (Windows/20050317) X-Accept-Language: de-DE, de, en-us, en MIME-Version: 1.0 To: debian-mips@lists.debian.org, linux-mips@linux-mips.org Subject: anyone want a DecStation? X-Enigmail-Version: 0.92.0.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enigFE2C75CD1E52AB6FAA918177" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8106 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjr@debian.org Precedence: bulk X-list: linux-mips This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enigFE2C75CD1E52AB6FAA918177 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Hi, as a non-stereotypical geek I no longer live in my parents' basement, however a bunch of my DecStations still do, and my parents have asked me to move them out. I have a lot of stuff that I'm willing to give into caring hands, as it is highly unlikely that I will do anything with them soonish: - around 3 or 4 DS5000/125, with some luck maybe a /250. - bunch of PMAG-A and PMAG-D plus cabling - 6 Maxines - 2 storage extension boxen - 6 DEC Monitors, one broken (doesn't get sync correctly) - lots of puck mice and 401 keyboards - lots of AUI cabling I'd be willing to bring stuff to LinuxTag on Saturday. If anyone wants something, please reply and I will put in in the car. Simon PS: I'm also going to bring two VAXstation II, from which one working one can be built IMO. If you have a VAX and need spare parts, be there on Saturday and we'll try to get one working so it is clear which parts are spare. --------------enigFE2C75CD1E52AB6FAA918177 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (MingW32) Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org iQCVAwUBQraplVYr4CN7gCINAQL1FAQAj/5XWZgu2lX9Lg2CTPMtu/D/MBMeJZ7z e79UlCn9qnEK1QpTcC0UasAFxw9cK72aW+qHvjEfjL3LCpihQIenaYpoo2SMXpnE Vnj7GjX7Em5s0XgVr7263x29CixyaA8RQggW9040voGdKcA22hBbartNV7ajC8TA Yq6sWP+qGUc= =y4OY -----END PGP SIGNATURE----- --------------enigFE2C75CD1E52AB6FAA918177-- From domen@nd47.coderock.org Mon Jun 20 22:50:41 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Jun 2005 22:51:00 +0100 (BST) Received: from coderock.org ([IPv6:::ffff:193.77.147.115]:2968 "EHLO trashy.coderock.org") by linux-mips.org with ESMTP id ; Mon, 20 Jun 2005 22:50:40 +0100 Received: by trashy.coderock.org (Postfix, from userid 780) id 97D741EDCD; Mon, 20 Jun 2005 23:50:32 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 686C21E8EF; Mon, 20 Jun 2005 23:50:30 +0200 (CEST) Received: from nd47.coderock.org (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 5BF801ED16; Mon, 20 Jun 2005 23:49:52 +0200 (CEST) Received: (from domen@localhost) by nd47.coderock.org (8.13.3/8.13.3/Submit) id j5KLnpX2021538; Mon, 20 Jun 2005 23:49:51 +0200 Message-Id: <20050620214951.416375000@nd47.coderock.org> Date: Mon, 20 Jun 2005 23:49:52 +0200 From: domen@coderock.org To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, domen@coderock.org Subject: [patch 1/8] delete arch/mips/arc/salone.c Content-Disposition: inline; filename=remove_file-arch_mips_arc_salone.c.patch Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8107 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen@coderock.org Precedence: bulk X-list: linux-mips Remove nowhere referenced file. (egrep "filename\." didn't find anything) Signed-off-by: Domen Puncer --- salone.c | 24 ------------------------ 1 files changed, 24 deletions(-) Index: quilt/arch/mips/arc/salone.c =================================================================== --- quilt.orig/arch/mips/arc/salone.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Routines to load into memory and execute stand-along program images using - * ARCS PROM firmware. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include - -LONG __init ArcLoad(CHAR *Path, ULONG TopAddr, ULONG *ExecAddr, ULONG *LowAddr) -{ - return ARC_CALL4(load, Path, TopAddr, ExecAddr, LowAddr); -} - -LONG __init ArcInvoke(ULONG ExecAddr, ULONG StackAddr, ULONG Argc, CHAR *Argv[], - CHAR *Envp[]) -{ - return ARC_CALL5(invoke, ExecAddr, StackAddr, Argc, Argv, Envp); -} - -LONG __init ArcExecute(CHAR *Path, LONG Argc, CHAR *Argv[], CHAR *Envp[]) -{ - return ARC_CALL4(exec, Path, Argc, Argv, Envp); -} -- From domen@nd47.coderock.org Mon Jun 20 22:51:27 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Jun 2005 22:51:55 +0100 (BST) Received: from coderock.org ([IPv6:::ffff:193.77.147.115]:4760 "EHLO trashy.coderock.org") by linux-mips.org with ESMTP id ; Mon, 20 Jun 2005 22:50:43 +0100 Received: by trashy.coderock.org (Postfix, from userid 780) id EC6731EDCD; Mon, 20 Jun 2005 23:50:41 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 298A61EDC7; Mon, 20 Jun 2005 23:50:40 +0200 (CEST) Received: from nd47.coderock.org (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 79AD01EDBE; Mon, 20 Jun 2005 23:49:53 +0200 (CEST) Received: (from domen@localhost) by nd47.coderock.org (8.13.3/8.13.3/Submit) id j5KLnrKg021582; Mon, 20 Jun 2005 23:49:53 +0200 Message-Id: <20050620214952.761755000@nd47.coderock.org> Date: Mon, 20 Jun 2005 23:49:53 +0200 From: domen@coderock.org To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, domen@coderock.org Subject: [patch 2/8] delete arch/mips/pmc-sierra/yosemite/ht-irq.c Content-Disposition: inline; filename=remove_file-arch_mips_pmc_sierra_yosemite_ht_irq.c.patch Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8108 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen@coderock.org Precedence: bulk X-list: linux-mips Remove nowhere referenced file. (egrep "filename\." didn't find anything) Signed-off-by: Domen Puncer --- ht-irq.c | 53 ----------------------------------------------------- 1 files changed, 53 deletions(-) Index: quilt/arch/mips/pmc-sierra/yosemite/ht-irq.c =================================================================== --- quilt.orig/arch/mips/pmc-sierra/yosemite/ht-irq.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2003 PMC-Sierra - * Author: Manish Lachwani (lachwani@pmc-sierra.com) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include - -/* - * HT Bus fixup for the Titan - * XXX IRQ values need to change based on the board layout - */ -void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus) -{ - struct pci_bus *current_bus = bus; - struct pci_dev *devices; - struct list_head *devices_link; - - list_for_each(devices_link, &(current_bus->devices)) { - devices = pci_dev_b(devices_link); - if (devices == NULL) - continue; - } - - /* - * PLX and SPKT related changes go here - */ - -} -- From domen@nd47.coderock.org Mon Jun 20 22:52:19 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Jun 2005 22:52:53 +0100 (BST) Received: from coderock.org ([IPv6:::ffff:193.77.147.115]:6296 "EHLO trashy.coderock.org") by linux-mips.org with ESMTP id ; Mon, 20 Jun 2005 22:50:49 +0100 Received: by trashy.coderock.org (Postfix, from userid 780) id 616031EDCD; Mon, 20 Jun 2005 23:50:48 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 686AE1ED15; Mon, 20 Jun 2005 23:50:46 +0200 (CEST) Received: from nd47.coderock.org (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 938C21ED19; Mon, 20 Jun 2005 23:49:54 +0200 (CEST) Received: (from domen@localhost) by nd47.coderock.org (8.13.3/8.13.3/Submit) id j5KLnsRs021626; Mon, 20 Jun 2005 23:49:54 +0200 Message-Id: <20050620214953.952800000@nd47.coderock.org> Date: Mon, 20 Jun 2005 23:49:54 +0200 From: domen@coderock.org To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, domen@coderock.org Subject: [patch 3/8] delete include/asm-mips/gfx.h Content-Disposition: inline; filename=remove_file-include_asm_mips_gfx.h.patch Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8109 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen@coderock.org Precedence: bulk X-list: linux-mips Remove nowhere referenced file. (egrep "filename\." didn't find anything) Signed-off-by: Domen Puncer --- gfx.h | 55 ------------------------------------------------------- 1 files changed, 55 deletions(-) Index: quilt/include/asm-mips/gfx.h =================================================================== --- quilt.orig/include/asm-mips/gfx.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This is the user-visible SGI GFX interface. - * - * This must be used verbatim into the GNU libc. It does not include - * any kernel-only bits on it. - * - * miguel@nuclecu.unam.mx - */ -#ifndef _ASM_GFX_H -#define _ASM_GFX_H - -/* The iocls, yes, they do not make sense, but such is life */ -#define GFX_BASE 100 -#define GFX_GETNUM_BOARDS (GFX_BASE + 1) -#define GFX_GETBOARD_INFO (GFX_BASE + 2) -#define GFX_ATTACH_BOARD (GFX_BASE + 3) -#define GFX_DETACH_BOARD (GFX_BASE + 4) -#define GFX_IS_MANAGED (GFX_BASE + 5) - -#define GFX_MAPALL (GFX_BASE + 10) -#define GFX_LABEL (GFX_BASE + 11) - -#define GFX_INFO_NAME_SIZE 16 -#define GFX_INFO_LABEL_SIZE 16 - -struct gfx_info { - char name [GFX_INFO_NAME_SIZE]; /* board name */ - char label [GFX_INFO_LABEL_SIZE]; /* label name */ - unsigned short int xpmax, ypmax; /* screen resolution */ - unsigned int lenght; /* size of a complete gfx_info for this board */ -}; - -struct gfx_getboardinfo_args { - unsigned int board; /* board number. starting from zero */ - void *buf; /* pointer to gfx_info */ - unsigned int len; /* buffer size of buf */ -}; - -struct gfx_attach_board_args { - unsigned int board; /* board number, starting from zero */ - void *vaddr; /* address where the board registers should be mapped */ -}; - -#ifdef __KERNEL__ -/* umap.c */ -extern void remove_mapping (struct vm_area_struct *vma, struct task_struct *, unsigned long, unsigned long); -extern void *vmalloc_uncached (unsigned long size); -extern int vmap_page_range (struct vm_area_struct *vma, unsigned long from, unsigned long size, unsigned long vaddr); -#endif - -#endif /* _ASM_GFX_H */ -- From domen@nd47.coderock.org Mon Jun 20 22:53:16 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Jun 2005 22:53:54 +0100 (BST) Received: from coderock.org ([IPv6:::ffff:193.77.147.115]:9624 "EHLO trashy.coderock.org") by linux-mips.org with ESMTP id ; Mon, 20 Jun 2005 22:51:01 +0100 Received: by trashy.coderock.org (Postfix, from userid 780) id 40C991EDCC; Mon, 20 Jun 2005 23:50:59 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id F127D1EDCD; Mon, 20 Jun 2005 23:50:57 +0200 (CEST) Received: from nd47.coderock.org (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 87C7A1EDC0; Mon, 20 Jun 2005 23:49:56 +0200 (CEST) Received: (from domen@localhost) by nd47.coderock.org (8.13.3/8.13.3/Submit) id j5KLnuUW021714; Mon, 20 Jun 2005 23:49:56 +0200 Message-Id: <20050620214956.047366000@nd47.coderock.org> Date: Mon, 20 Jun 2005 23:49:56 +0200 From: domen@coderock.org To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, domen@coderock.org Subject: [patch 5/8] delete include/asm-mips/mipsprom.h Content-Disposition: inline; filename=remove_file-include_asm_mips_mipsprom.h.patch Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8110 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen@coderock.org Precedence: bulk X-list: linux-mips Remove nowhere referenced file. (egrep "filename\." didn't find anything) Signed-off-by: Domen Puncer --- mipsprom.h | 74 ------------------------------------------------------------- 1 files changed, 74 deletions(-) Index: quilt/include/asm-mips/mipsprom.h =================================================================== --- quilt.orig/include/asm-mips/mipsprom.h +++ /dev/null @@ -1,74 +0,0 @@ -#ifndef __ASM_MIPS_PROM_H -#define __ASM_MIPS_PROM_H - -#define PROM_RESET 0 -#define PROM_EXEC 1 -#define PROM_RESTART 2 -#define PROM_REINIT 3 -#define PROM_REBOOT 4 -#define PROM_AUTOBOOT 5 -#define PROM_OPEN 6 -#define PROM_READ 7 -#define PROM_WRITE 8 -#define PROM_IOCTL 9 -#define PROM_CLOSE 10 -#define PROM_GETCHAR 11 -#define PROM_PUTCHAR 12 -#define PROM_SHOWCHAR 13 /* XXX */ -#define PROM_GETS 14 /* XXX */ -#define PROM_PUTS 15 /* XXX */ -#define PROM_PRINTF 16 /* XXX */ - -/* What are these for? */ -#define PROM_INITPROTO 17 /* XXX */ -#define PROM_PROTOENABLE 18 /* XXX */ -#define PROM_PROTODISABLE 19 /* XXX */ -#define PROM_GETPKT 20 /* XXX */ -#define PROM_PUTPKT 21 /* XXX */ - -/* More PROM shit. Probably has to do with VME RMW cycles??? */ -#define PROM_ORW_RMW 22 /* XXX */ -#define PROM_ORH_RMW 23 /* XXX */ -#define PROM_ORB_RMW 24 /* XXX */ -#define PROM_ANDW_RMW 25 /* XXX */ -#define PROM_ANDH_RMW 26 /* XXX */ -#define PROM_ANDB_RMW 27 /* XXX */ - -/* Cache handling stuff */ -#define PROM_FLUSHCACHE 28 /* XXX */ -#define PROM_CLEARCACHE 29 /* XXX */ - -/* Libc alike stuff */ -#define PROM_SETJMP 30 /* XXX */ -#define PROM_LONGJMP 31 /* XXX */ -#define PROM_BEVUTLB 32 /* XXX */ -#define PROM_GETENV 33 /* XXX */ -#define PROM_SETENV 34 /* XXX */ -#define PROM_ATOB 35 /* XXX */ -#define PROM_STRCMP 36 /* XXX */ -#define PROM_STRLEN 37 /* XXX */ -#define PROM_STRCPY 38 /* XXX */ -#define PROM_STRCAT 39 /* XXX */ - -/* Misc stuff */ -#define PROM_PARSER 40 /* XXX */ -#define PROM_RANGE 41 /* XXX */ -#define PROM_ARGVIZE 42 /* XXX */ -#define PROM_HELP 43 /* XXX */ - -/* Entry points for some PROM commands */ -#define PROM_DUMPCMD 44 /* XXX */ -#define PROM_SETENVCMD 45 /* XXX */ -#define PROM_UNSETENVCMD 46 /* XXX */ -#define PROM_PRINTENVCMD 47 /* XXX */ -#define PROM_BEVEXCEPT 48 /* XXX */ -#define PROM_ENABLECMD 49 /* XXX */ -#define PROM_DISABLECMD 50 /* XXX */ - -#define PROM_CLEARNOFAULT 51 /* XXX */ -#define PROM_NOTIMPLEMENT 52 /* XXX */ - -#define PROM_NV_GET 53 /* XXX */ -#define PROM_NV_SET 54 /* XXX */ - -#endif /* __ASM_MIPS_PROM_H */ -- From domen@nd47.coderock.org Mon Jun 20 22:54:17 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Jun 2005 22:54:43 +0100 (BST) Received: from coderock.org ([IPv6:::ffff:193.77.147.115]:11416 "EHLO trashy.coderock.org") by linux-mips.org with ESMTP id ; Mon, 20 Jun 2005 22:51:08 +0100 Received: by trashy.coderock.org (Postfix, from userid 780) id EF5041EDD2; Mon, 20 Jun 2005 23:51:06 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id CB7F51EDCC; Mon, 20 Jun 2005 23:51:04 +0200 (CEST) Received: from nd47.coderock.org (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 235FC1EDC5; Mon, 20 Jun 2005 23:49:59 +0200 (CEST) Received: (from domen@localhost) by nd47.coderock.org (8.13.3/8.13.3/Submit) id j5KLnwrt021803; Mon, 20 Jun 2005 23:49:58 +0200 Message-Id: <20050620214958.810995000@nd47.coderock.org> Date: Mon, 20 Jun 2005 23:49:58 +0200 From: domen@coderock.org To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Nishanth Aravamudan , domen@coderock.org Subject: [patch 7/8] mips/bcm1250_tbprof: remove interruptible_sleep_on() usage Content-Disposition: inline; filename=int_sleep_on-arch_mips_sibyte_sb1250_bcm1250_tbprof.patch Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8111 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen@coderock.org Precedence: bulk X-list: linux-mips From: Nishanth Aravamudan Remove deprecated interruptible_sleep_on() function call and replace with direct wait-queue usage. Signed-off-by: Nishanth Aravamudan Signed-off-by: Domen Puncer --- bcm1250_tbprof.c | 11 +++++++++-- 1 files changed, 9 insertions(+), 2 deletions(-) Index: quilt/arch/mips/sibyte/sb1250/bcm1250_tbprof.c =================================================================== --- quilt.orig/arch/mips/sibyte/sb1250/bcm1250_tbprof.c +++ quilt/arch/mips/sibyte/sb1250/bcm1250_tbprof.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -231,6 +232,7 @@ int sbprof_zbprof_start(struct file *fil int sbprof_zbprof_stop(void) { + DEFINE_WAIT(wait); DBG(printk(DEVNAME ": stopping\n")); if (sbp.tb_enable) { @@ -240,7 +242,9 @@ int sbprof_zbprof_stop(void) this sleep happens. */ if (sbp.tb_armed) { DBG(printk(DEVNAME ": wait for disarm\n")); - interruptible_sleep_on(&sbp.tb_sync); + prepare_to_wait(&sbp.tb_sync, &wait, TASK_INTERRUPTIBLE); + schedule(); + finish_wait(&sbp.tb_sync, &wait); DBG(printk(DEVNAME ": disarm complete\n")); } free_irq(K_INT_TRACE_FREEZE, &sbp); @@ -339,6 +343,7 @@ static int sbprof_tb_ioctl(struct inode unsigned long arg) { int error = 0; + DEFINE_WAIT(wait); switch (command) { case SBPROF_ZBSTART: @@ -348,7 +353,9 @@ static int sbprof_tb_ioctl(struct inode error = sbprof_zbprof_stop(); break; case SBPROF_ZBWAITFULL: - interruptible_sleep_on(&sbp.tb_read); + prepare_to_wait(&sbp.tb_read, &wait, TASK_INTERRUPTIBLE); + schedule(); + finish_wait(&sbp.tb_read, &wait); /* XXXKW check if interrupted? */ return put_user(TB_FULL, (int *) arg); default: -- From domen@nd47.coderock.org Mon Jun 20 22:55:07 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Jun 2005 22:55:31 +0100 (BST) Received: from coderock.org ([IPv6:::ffff:193.77.147.115]:13208 "EHLO trashy.coderock.org") by linux-mips.org with ESMTP id ; Mon, 20 Jun 2005 22:51:15 +0100 Received: by trashy.coderock.org (Postfix, from userid 780) id EA4371EDD3; Mon, 20 Jun 2005 23:51:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 59B231EDD1; Mon, 20 Jun 2005 23:51:10 +0200 (CEST) Received: from nd47.coderock.org (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 8A1081EDC3; Mon, 20 Jun 2005 23:49:55 +0200 (CEST) Received: (from domen@localhost) by nd47.coderock.org (8.13.3/8.13.3/Submit) id j5KLntsP021670; Mon, 20 Jun 2005 23:49:55 +0200 Message-Id: <20050620214955.142371000@nd47.coderock.org> Date: Mon, 20 Jun 2005 23:49:55 +0200 From: domen@coderock.org To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, domen@coderock.org Subject: [patch 4/8] delete include/asm-mips/mach-au1x00/au1100_mmc.h Content-Disposition: inline; filename=remove_file-include_asm_mips_mach_au1x00_au1100_mmc.h.patch Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8112 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen@coderock.org Precedence: bulk X-list: linux-mips Remove nowhere referenced file. (egrep "filename\." didn't find anything) Signed-off-by: Domen Puncer --- au1100_mmc.h | 205 ----------------------------------------------------------- 1 files changed, 205 deletions(-) Index: quilt/include/asm-mips/mach-au1x00/au1100_mmc.h =================================================================== --- quilt.orig/include/asm-mips/mach-au1x00/au1100_mmc.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Defines for using the MMC/SD controllers on the - * Alchemy Au1100 mips processor. - * - * Copyright (c) 2003 Embedded Edge, LLC. - * Author: Embedded Edge, LLC. - * dan@embeddededge.com or tim@embeddededge.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -/* - * AU1100 MMC/SD definitions. - * - * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary" - * June, 2003 - */ - -#ifndef __ASM_AU1100_MMC_H -#define __ASM_AU1100_MMC_H - - -#define NUM_AU1100_MMC_CONTROLLERS 2 - - -#define AU1100_SD_IRQ 2 - - -#define SD0_BASE 0xB0600000 -#define SD1_BASE 0xB0680000 - - -/* - * Register offsets. - */ -#define SD_TXPORT (0x0000) -#define SD_RXPORT (0x0004) -#define SD_CONFIG (0x0008) -#define SD_ENABLE (0x000C) -#define SD_CONFIG2 (0x0010) -#define SD_BLKSIZE (0x0014) -#define SD_STATUS (0x0018) -#define SD_DEBUG (0x001C) -#define SD_CMD (0x0020) -#define SD_CMDARG (0x0024) -#define SD_RESP3 (0x0028) -#define SD_RESP2 (0x002C) -#define SD_RESP1 (0x0030) -#define SD_RESP0 (0x0034) -#define SD_TIMEOUT (0x0038) - - -/* - * SD_TXPORT bit definitions. - */ -#define SD_TXPORT_TXD (0x000000ff) - - -/* - * SD_RXPORT bit definitions. - */ -#define SD_RXPORT_RXD (0x000000ff) - - -/* - * SD_CONFIG bit definitions. - */ -#define SD_CONFIG_DIV (0x000001ff) -#define SD_CONFIG_DE (0x00000200) -#define SD_CONFIG_NE (0x00000400) -#define SD_CONFIG_TU (0x00000800) -#define SD_CONFIG_TO (0x00001000) -#define SD_CONFIG_RU (0x00002000) -#define SD_CONFIG_RO (0x00004000) -#define SD_CONFIG_I (0x00008000) -#define SD_CONFIG_CR (0x00010000) -#define SD_CONFIG_RAT (0x00020000) -#define SD_CONFIG_DD (0x00040000) -#define SD_CONFIG_DT (0x00080000) -#define SD_CONFIG_SC (0x00100000) -#define SD_CONFIG_RC (0x00200000) -#define SD_CONFIG_WC (0x00400000) -#define SD_CONFIG_xxx (0x00800000) -#define SD_CONFIG_TH (0x01000000) -#define SD_CONFIG_TE (0x02000000) -#define SD_CONFIG_TA (0x04000000) -#define SD_CONFIG_RH (0x08000000) -#define SD_CONFIG_RA (0x10000000) -#define SD_CONFIG_RF (0x20000000) -#define SD_CONFIG_CD (0x40000000) -#define SD_CONFIG_SI (0x80000000) - - -/* - * SD_ENABLE bit definitions. - */ -#define SD_ENABLE_CE (0x00000001) -#define SD_ENABLE_R (0x00000002) - - -/* - * SD_CONFIG2 bit definitions. - */ -#define SD_CONFIG2_EN (0x00000001) -#define SD_CONFIG2_FF (0x00000002) -#define SD_CONFIG2_xx1 (0x00000004) -#define SD_CONFIG2_DF (0x00000008) -#define SD_CONFIG2_DC (0x00000010) -#define SD_CONFIG2_xx2 (0x000000e0) -#define SD_CONFIG2_WB (0x00000100) -#define SD_CONFIG2_RW (0x00000200) - - -/* - * SD_BLKSIZE bit definitions. - */ -#define SD_BLKSIZE_BS (0x000007ff) -#define SD_BLKSIZE_BS_SHIFT (0) -#define SD_BLKSIZE_BC (0x01ff0000) -#define SD_BLKSIZE_BC_SHIFT (16) - - -/* - * SD_STATUS bit definitions. - */ -#define SD_STATUS_DCRCW (0x00000007) -#define SD_STATUS_xx1 (0x00000008) -#define SD_STATUS_CB (0x00000010) -#define SD_STATUS_DB (0x00000020) -#define SD_STATUS_CF (0x00000040) -#define SD_STATUS_D3 (0x00000080) -#define SD_STATUS_xx2 (0x00000300) -#define SD_STATUS_NE (0x00000400) -#define SD_STATUS_TU (0x00000800) -#define SD_STATUS_TO (0x00001000) -#define SD_STATUS_RU (0x00002000) -#define SD_STATUS_RO (0x00004000) -#define SD_STATUS_I (0x00008000) -#define SD_STATUS_CR (0x00010000) -#define SD_STATUS_RAT (0x00020000) -#define SD_STATUS_DD (0x00040000) -#define SD_STATUS_DT (0x00080000) -#define SD_STATUS_SC (0x00100000) -#define SD_STATUS_RC (0x00200000) -#define SD_STATUS_WC (0x00400000) -#define SD_STATUS_xx3 (0x00800000) -#define SD_STATUS_TH (0x01000000) -#define SD_STATUS_TE (0x02000000) -#define SD_STATUS_TA (0x04000000) -#define SD_STATUS_RH (0x08000000) -#define SD_STATUS_RA (0x10000000) -#define SD_STATUS_RF (0x20000000) -#define SD_STATUS_CD (0x40000000) -#define SD_STATUS_SI (0x80000000) - - -/* - * SD_CMD bit definitions. - */ -#define SD_CMD_GO (0x00000001) -#define SD_CMD_RY (0x00000002) -#define SD_CMD_xx1 (0x0000000c) -#define SD_CMD_CT_MASK (0x000000f0) -#define SD_CMD_CT_0 (0x00000000) -#define SD_CMD_CT_1 (0x00000010) -#define SD_CMD_CT_2 (0x00000020) -#define SD_CMD_CT_3 (0x00000030) -#define SD_CMD_CT_4 (0x00000040) -#define SD_CMD_CT_5 (0x00000050) -#define SD_CMD_CT_6 (0x00000060) -#define SD_CMD_CT_7 (0x00000070) -#define SD_CMD_CI (0x0000ff00) -#define SD_CMD_CI_SHIFT (8) -#define SD_CMD_RT_MASK (0x00ff0000) -#define SD_CMD_RT_0 (0x00000000) -#define SD_CMD_RT_1 (0x00010000) -#define SD_CMD_RT_2 (0x00020000) -#define SD_CMD_RT_3 (0x00030000) -#define SD_CMD_RT_4 (0x00040000) -#define SD_CMD_RT_5 (0x00050000) -#define SD_CMD_RT_6 (0x00060000) -#define SD_CMD_RT_1B (0x00810000) - - -#endif /* __ASM_AU1100_MMC_H */ - -- From domen@nd47.coderock.org Mon Jun 20 22:55:54 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Jun 2005 22:56:25 +0100 (BST) Received: from coderock.org ([IPv6:::ffff:193.77.147.115]:15768 "EHLO trashy.coderock.org") by linux-mips.org with ESMTP id ; Mon, 20 Jun 2005 22:51:22 +0100 Received: by trashy.coderock.org (Postfix, from userid 780) id 9E0391EDD6; Mon, 20 Jun 2005 23:51:20 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 5FC191EDD3; Mon, 20 Jun 2005 23:51:17 +0200 (CEST) Received: from nd47.coderock.org (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 0FD1E1EDC6; Mon, 20 Jun 2005 23:50:00 +0200 (CEST) Received: (from domen@localhost) by nd47.coderock.org (8.13.3/8.13.3/Submit) id j5KLnxuv021847; Mon, 20 Jun 2005 23:49:59 +0200 Message-Id: <20050620214959.594768000@nd47.coderock.org> Date: Mon, 20 Jun 2005 23:49:59 +0200 From: domen@coderock.org To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Clemens Buchacher , Maximilian Attems , domen@coderock.org Subject: [patch 8/8] __FUNCTION__ string concatenation deprecated Content-Disposition: inline; filename=function-string-arch-mips.patch Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8113 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen@coderock.org Precedence: bulk X-list: linux-mips From: Clemens Buchacher __FUNCTION__ string concatenation is deprecated Signed-off-by: Clemens Buchacher Signed-off-by: Maximilian Attems Signed-off-by: Domen Puncer --- arch/mips/au1000/common/usbdev.c | 4 ++-- drivers/net/gt96100eth.c | 10 +++++----- sound/oss/au1000.c | 2 +- sound/oss/ite8172.c | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) Index: quilt/arch/mips/au1000/common/usbdev.c =================================================================== --- quilt.orig/arch/mips/au1000/common/usbdev.c +++ quilt/arch/mips/au1000/common/usbdev.c @@ -348,7 +348,7 @@ endpoint_stall(endpoint_t * ep) { u32 cs; - warn(__FUNCTION__); + warn("%s", __FUNCTION__); cs = au_readl(ep->reg->ctrl_stat) | USBDEV_CS_STALL; au_writel(cs, ep->reg->ctrl_stat); @@ -360,7 +360,7 @@ endpoint_unstall(endpoint_t * ep) { u32 cs; - warn(__FUNCTION__); + warn("%s", __FUNCTION__); cs = au_readl(ep->reg->ctrl_stat) & ~USBDEV_CS_STALL; au_writel(cs, ep->reg->ctrl_stat); Index: quilt/drivers/net/gt96100eth.c =================================================================== --- quilt.orig/drivers/net/gt96100eth.c +++ quilt/drivers/net/gt96100eth.c @@ -73,7 +73,7 @@ static void dump_rx_desc(int dbg_lvl, st static void dump_skb(int dbg_lvl, struct net_device *dev, struct sk_buff *skb); static void dump_hw_addr(int dbg_lvl, struct net_device *dev, - const char* pfx, unsigned char* addr_str); + const char* pfx, const char* func, unsigned char* addr_str); static void update_stats(struct gt96100_private *gp); static void abort(struct net_device *dev, u32 abort_bits); static void hard_stop(struct net_device *dev); @@ -334,13 +334,13 @@ dump_MII(int dbg_lvl, struct net_device static void dump_hw_addr(int dbg_lvl, struct net_device *dev, const char* pfx, - unsigned char* addr_str) + const char* func, unsigned char* addr_str) { int i; char buf[100], octet[5]; if (dbg_lvl <= GT96100_DEBUG) { - strcpy(buf, pfx); + sprintf(buf, pfx, func); for (i = 0; i < 6; i++) { sprintf(octet, "%2.2x%s", addr_str[i], i<5 ? ":" : "\n"); @@ -708,7 +708,7 @@ static int __init gt96100_probe1(struct info("%s found at 0x%x, irq %d\n", chip_name(gp->chip_rev), gtif->iobase, gtif->irq); - dump_hw_addr(0, dev, "HW Address ", dev->dev_addr); + dump_hw_addr(0, dev, "%s: HW Address ", __FUNCTION__, dev->dev_addr); info("%s chip revision=%d\n", chip_name(gp->chip_rev), gp->chip_rev); info("%s ethernet port %d\n", chip_name(gp->chip_rev), gp->port_num); info("external PHY ID1=0x%04x, ID2=0x%04x\n", phy_id1, phy_id2); @@ -1488,7 +1488,7 @@ gt96100_set_rx_mode(struct net_device *d gt96100_add_hash_entry(dev, dev->dev_addr); for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) { - dump_hw_addr(2, dev, __FUNCTION__ ": addr=", + dump_hw_addr(2, dev, "%s: addr=", __FUNCTION__, mcptr->dmi_addr); gt96100_add_hash_entry(dev, mcptr->dmi_addr); } Index: quilt/sound/oss/au1000.c =================================================================== --- quilt.orig/sound/oss/au1000.c +++ quilt/sound/oss/au1000.c @@ -1295,7 +1295,7 @@ static int au1000_mmap(struct file *file unsigned long size; int ret = 0; - dbg(__FUNCTION__); + dbg("%s", __FUNCTION__); lock_kernel(); down(&s->sem); Index: quilt/sound/oss/ite8172.c =================================================================== --- quilt.orig/sound/oss/ite8172.c +++ quilt/sound/oss/ite8172.c @@ -1859,7 +1859,7 @@ static int it8172_release(struct inode * struct it8172_state *s = (struct it8172_state *)file->private_data; #ifdef IT8172_VERBOSE_DEBUG - dbg(__FUNCTION__); + dbg("%s", __FUNCTION__); #endif lock_kernel(); if (file->f_mode & FMODE_WRITE) -- From domen@nd47.coderock.org Mon Jun 20 22:56:49 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 20 Jun 2005 22:57:20 +0100 (BST) Received: from coderock.org ([IPv6:::ffff:193.77.147.115]:57496 "EHLO trashy.coderock.org") by linux-mips.org with ESMTP id ; Mon, 20 Jun 2005 22:54:11 +0100 Received: by trashy.coderock.org (Postfix, from userid 780) id AFDF21EF6C; Mon, 20 Jun 2005 23:54:07 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id 4AC441EF63; Mon, 20 Jun 2005 23:53:55 +0200 (CEST) Received: from nd47.coderock.org (localhost [127.0.0.1]) by trashy.coderock.org (Postfix) with ESMTP id A01881EDC4; Mon, 20 Jun 2005 23:49:57 +0200 (CEST) Received: (from domen@localhost) by nd47.coderock.org (8.13.3/8.13.3/Submit) id j5KLnvph021758; Mon, 20 Jun 2005 23:49:57 +0200 Message-Id: <20050620214957.042411000@nd47.coderock.org> Date: Mon, 20 Jun 2005 23:49:57 +0200 From: domen@coderock.org To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, domen@coderock.org Subject: [patch 6/8] delete include/asm-mips/riscos-syscall.h Content-Disposition: inline; filename=remove_file-include_asm_mips_riscos_syscall.h.patch Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8114 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: domen@coderock.org Precedence: bulk X-list: linux-mips Remove nowhere referenced file. (egrep "filename\." didn't find anything) Signed-off-by: Domen Puncer --- riscos-syscall.h | 979 ------------------------------------------------------- 1 files changed, 979 deletions(-) Index: quilt/include/asm-mips/riscos-syscall.h =================================================================== --- quilt.orig/include/asm-mips/riscos-syscall.h +++ /dev/null @@ -1,979 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle - */ -#ifndef _ASM_RISCOS_SYSCALL_H -#define _ASM_RISCOS_SYSCALL_H - -/* - * The syscalls 0 - 3999 are reserved for a down to the root syscall - * compatibility with RISC/os and IRIX. We'll see how to deal with the - * various "real" BSD variants like Ultrix, NetBSD ... - */ - -/* - * SVR4 syscalls are in the range from 1 to 999 - */ -#define __NR_SVR4 0 -#define __NR_SVR4_syscall (__NR_SVR4 + 0) -#define __NR_SVR4_exit (__NR_SVR4 + 1) -#define __NR_SVR4_fork (__NR_SVR4 + 2) -#define __NR_SVR4_read (__NR_SVR4 + 3) -#define __NR_SVR4_write (__NR_SVR4 + 4) -#define __NR_SVR4_open (__NR_SVR4 + 5) -#define __NR_SVR4_close (__NR_SVR4 + 6) -#define __NR_SVR4_wait (__NR_SVR4 + 7) -#define __NR_SVR4_creat (__NR_SVR4 + 8) -#define __NR_SVR4_link (__NR_SVR4 + 9) -#define __NR_SVR4_unlink (__NR_SVR4 + 10) -#define __NR_SVR4_exec (__NR_SVR4 + 11) -#define __NR_SVR4_chdir (__NR_SVR4 + 12) -#define __NR_SVR4_gtime (__NR_SVR4 + 13) -#define __NR_SVR4_mknod (__NR_SVR4 + 14) -#define __NR_SVR4_chmod (__NR_SVR4 + 15) -#define __NR_SVR4_chown (__NR_SVR4 + 16) -#define __NR_SVR4_sbreak (__NR_SVR4 + 17) -#define __NR_SVR4_stat (__NR_SVR4 + 18) -#define __NR_SVR4_lseek (__NR_SVR4 + 19) -#define __NR_SVR4_getpid (__NR_SVR4 + 20) -#define __NR_SVR4_mount (__NR_SVR4 + 21) -#define __NR_SVR4_umount (__NR_SVR4 + 22) -#define __NR_SVR4_setuid (__NR_SVR4 + 23) -#define __NR_SVR4_getuid (__NR_SVR4 + 24) -#define __NR_SVR4_stime (__NR_SVR4 + 25) -#define __NR_SVR4_ptrace (__NR_SVR4 + 26) -#define __NR_SVR4_alarm (__NR_SVR4 + 27) -#define __NR_SVR4_fstat (__NR_SVR4 + 28) -#define __NR_SVR4_pause (__NR_SVR4 + 29) -#define __NR_SVR4_utime (__NR_SVR4 + 30) -#define __NR_SVR4_stty (__NR_SVR4 + 31) -#define __NR_SVR4_gtty (__NR_SVR4 + 32) -#define __NR_SVR4_access (__NR_SVR4 + 33) -#define __NR_SVR4_nice (__NR_SVR4 + 34) -#define __NR_SVR4_statfs (__NR_SVR4 + 35) -#define __NR_SVR4_sync (__NR_SVR4 + 36) -#define __NR_SVR4_kill (__NR_SVR4 + 37) -#define __NR_SVR4_fstatfs (__NR_SVR4 + 38) -#define __NR_SVR4_setpgrp (__NR_SVR4 + 39) -#define __NR_SVR4_cxenix (__NR_SVR4 + 40) -#define __NR_SVR4_dup (__NR_SVR4 + 41) -#define __NR_SVR4_pipe (__NR_SVR4 + 42) -#define __NR_SVR4_times (__NR_SVR4 + 43) -#define __NR_SVR4_profil (__NR_SVR4 + 44) -#define __NR_SVR4_plock (__NR_SVR4 + 45) -#define __NR_SVR4_setgid (__NR_SVR4 + 46) -#define __NR_SVR4_getgid (__NR_SVR4 + 47) -#define __NR_SVR4_sig (__NR_SVR4 + 48) -#define __NR_SVR4_msgsys (__NR_SVR4 + 49) -#define __NR_SVR4_sysmips (__NR_SVR4 + 50) -#define __NR_SVR4_sysacct (__NR_SVR4 + 51) -#define __NR_SVR4_shmsys (__NR_SVR4 + 52) -#define __NR_SVR4_semsys (__NR_SVR4 + 53) -#define __NR_SVR4_ioctl (__NR_SVR4 + 54) -#define __NR_SVR4_uadmin (__NR_SVR4 + 55) -#define __NR_SVR4_exch (__NR_SVR4 + 56) -#define __NR_SVR4_utssys (__NR_SVR4 + 57) -#define __NR_SVR4_fsync (__NR_SVR4 + 58) -#define __NR_SVR4_exece (__NR_SVR4 + 59) -#define __NR_SVR4_umask (__NR_SVR4 + 60) -#define __NR_SVR4_chroot (__NR_SVR4 + 61) -#define __NR_SVR4_fcntl (__NR_SVR4 + 62) -#define __NR_SVR4_ulimit (__NR_SVR4 + 63) -#define __NR_SVR4_reserved1 (__NR_SVR4 + 64) -#define __NR_SVR4_reserved2 (__NR_SVR4 + 65) -#define __NR_SVR4_reserved3 (__NR_SVR4 + 66) -#define __NR_SVR4_reserved4 (__NR_SVR4 + 67) -#define __NR_SVR4_reserved5 (__NR_SVR4 + 68) -#define __NR_SVR4_reserved6 (__NR_SVR4 + 69) -#define __NR_SVR4_advfs (__NR_SVR4 + 70) -#define __NR_SVR4_unadvfs (__NR_SVR4 + 71) -#define __NR_SVR4_unused1 (__NR_SVR4 + 72) -#define __NR_SVR4_unused2 (__NR_SVR4 + 73) -#define __NR_SVR4_rfstart (__NR_SVR4 + 74) -#define __NR_SVR4_unused3 (__NR_SVR4 + 75) -#define __NR_SVR4_rdebug (__NR_SVR4 + 76) -#define __NR_SVR4_rfstop (__NR_SVR4 + 77) -#define __NR_SVR4_rfsys (__NR_SVR4 + 78) -#define __NR_SVR4_rmdir (__NR_SVR4 + 79) -#define __NR_SVR4_mkdir (__NR_SVR4 + 80) -#define __NR_SVR4_getdents (__NR_SVR4 + 81) -#define __NR_SVR4_libattach (__NR_SVR4 + 82) -#define __NR_SVR4_libdetach (__NR_SVR4 + 83) -#define __NR_SVR4_sysfs (__NR_SVR4 + 84) -#define __NR_SVR4_getmsg (__NR_SVR4 + 85) -#define __NR_SVR4_putmsg (__NR_SVR4 + 86) -#define __NR_SVR4_poll (__NR_SVR4 + 87) -#define __NR_SVR4_lstat (__NR_SVR4 + 88) -#define __NR_SVR4_symlink (__NR_SVR4 + 89) -#define __NR_SVR4_readlink (__NR_SVR4 + 90) -#define __NR_SVR4_setgroups (__NR_SVR4 + 91) -#define __NR_SVR4_getgroups (__NR_SVR4 + 92) -#define __NR_SVR4_fchmod (__NR_SVR4 + 93) -#define __NR_SVR4_fchown (__NR_SVR4 + 94) -#define __NR_SVR4_sigprocmask (__NR_SVR4 + 95) -#define __NR_SVR4_sigsuspend (__NR_SVR4 + 96) -#define __NR_SVR4_sigaltstack (__NR_SVR4 + 97) -#define __NR_SVR4_sigaction (__NR_SVR4 + 98) -#define __NR_SVR4_sigpending (__NR_SVR4 + 99) -#define __NR_SVR4_setcontext (__NR_SVR4 + 100) -#define __NR_SVR4_evsys (__NR_SVR4 + 101) -#define __NR_SVR4_evtrapret (__NR_SVR4 + 102) -#define __NR_SVR4_statvfs (__NR_SVR4 + 103) -#define __NR_SVR4_fstatvfs (__NR_SVR4 + 104) -#define __NR_SVR4_reserved7 (__NR_SVR4 + 105) -#define __NR_SVR4_nfssys (__NR_SVR4 + 106) -#define __NR_SVR4_waitid (__NR_SVR4 + 107) -#define __NR_SVR4_sigsendset (__NR_SVR4 + 108) -#define __NR_SVR4_hrtsys (__NR_SVR4 + 109) -#define __NR_SVR4_acancel (__NR_SVR4 + 110) -#define __NR_SVR4_async (__NR_SVR4 + 111) -#define __NR_SVR4_priocntlset (__NR_SVR4 + 112) -#define __NR_SVR4_pathconf (__NR_SVR4 + 113) -#define __NR_SVR4_mincore (__NR_SVR4 + 114) -#define __NR_SVR4_mmap (__NR_SVR4 + 115) -#define __NR_SVR4_mprotect (__NR_SVR4 + 116) -#define __NR_SVR4_munmap (__NR_SVR4 + 117) -#define __NR_SVR4_fpathconf (__NR_SVR4 + 118) -#define __NR_SVR4_vfork (__NR_SVR4 + 119) -#define __NR_SVR4_fchdir (__NR_SVR4 + 120) -#define __NR_SVR4_readv (__NR_SVR4 + 121) -#define __NR_SVR4_writev (__NR_SVR4 + 122) -#define __NR_SVR4_xstat (__NR_SVR4 + 123) -#define __NR_SVR4_lxstat (__NR_SVR4 + 124) -#define __NR_SVR4_fxstat (__NR_SVR4 + 125) -#define __NR_SVR4_xmknod (__NR_SVR4 + 126) -#define __NR_SVR4_clocal (__NR_SVR4 + 127) -#define __NR_SVR4_setrlimit (__NR_SVR4 + 128) -#define __NR_SVR4_getrlimit (__NR_SVR4 + 129) -#define __NR_SVR4_lchown (__NR_SVR4 + 130) -#define __NR_SVR4_memcntl (__NR_SVR4 + 131) -#define __NR_SVR4_getpmsg (__NR_SVR4 + 132) -#define __NR_SVR4_putpmsg (__NR_SVR4 + 133) -#define __NR_SVR4_rename (__NR_SVR4 + 134) -#define __NR_SVR4_nuname (__NR_SVR4 + 135) -#define __NR_SVR4_setegid (__NR_SVR4 + 136) -#define __NR_SVR4_sysconf (__NR_SVR4 + 137) -#define __NR_SVR4_adjtime (__NR_SVR4 + 138) -#define __NR_SVR4_sysinfo (__NR_SVR4 + 139) -#define __NR_SVR4_reserved8 (__NR_SVR4 + 140) -#define __NR_SVR4_seteuid (__NR_SVR4 + 141) -#define __NR_SVR4_PYRAMID_statis (__NR_SVR4 + 142) -#define __NR_SVR4_PYRAMID_tuning (__NR_SVR4 + 143) -#define __NR_SVR4_PYRAMID_forcerr (__NR_SVR4 + 144) -#define __NR_SVR4_PYRAMID_mpcntl (__NR_SVR4 + 145) -#define __NR_SVR4_reserved9 (__NR_SVR4 + 146) -#define __NR_SVR4_reserved10 (__NR_SVR4 + 147) -#define __NR_SVR4_reserved11 (__NR_SVR4 + 148) -#define __NR_SVR4_reserved12 (__NR_SVR4 + 149) -#define __NR_SVR4_reserved13 (__NR_SVR4 + 150) -#define __NR_SVR4_reserved14 (__NR_SVR4 + 151) -#define __NR_SVR4_reserved15 (__NR_SVR4 + 152) -#define __NR_SVR4_reserved16 (__NR_SVR4 + 153) -#define __NR_SVR4_reserved17 (__NR_SVR4 + 154) -#define __NR_SVR4_reserved18 (__NR_SVR4 + 155) -#define __NR_SVR4_reserved19 (__NR_SVR4 + 156) -#define __NR_SVR4_reserved20 (__NR_SVR4 + 157) -#define __NR_SVR4_reserved21 (__NR_SVR4 + 158) -#define __NR_SVR4_reserved22 (__NR_SVR4 + 159) -#define __NR_SVR4_reserved23 (__NR_SVR4 + 160) -#define __NR_SVR4_reserved24 (__NR_SVR4 + 161) -#define __NR_SVR4_reserved25 (__NR_SVR4 + 162) -#define __NR_SVR4_reserved26 (__NR_SVR4 + 163) -#define __NR_SVR4_reserved27 (__NR_SVR4 + 164) -#define __NR_SVR4_reserved28 (__NR_SVR4 + 165) -#define __NR_SVR4_reserved29 (__NR_SVR4 + 166) -#define __NR_SVR4_reserved30 (__NR_SVR4 + 167) -#define __NR_SVR4_reserved31 (__NR_SVR4 + 168) -#define __NR_SVR4_reserved32 (__NR_SVR4 + 169) -#define __NR_SVR4_reserved33 (__NR_SVR4 + 170) -#define __NR_SVR4_reserved34 (__NR_SVR4 + 171) -#define __NR_SVR4_reserved35 (__NR_SVR4 + 172) -#define __NR_SVR4_reserved36 (__NR_SVR4 + 173) -#define __NR_SVR4_reserved37 (__NR_SVR4 + 174) -#define __NR_SVR4_reserved38 (__NR_SVR4 + 175) -#define __NR_SVR4_reserved39 (__NR_SVR4 + 176) -#define __NR_SVR4_reserved40 (__NR_SVR4 + 177) -#define __NR_SVR4_reserved41 (__NR_SVR4 + 178) -#define __NR_SVR4_reserved42 (__NR_SVR4 + 179) -#define __NR_SVR4_reserved43 (__NR_SVR4 + 180) -#define __NR_SVR4_reserved44 (__NR_SVR4 + 181) -#define __NR_SVR4_reserved45 (__NR_SVR4 + 182) -#define __NR_SVR4_reserved46 (__NR_SVR4 + 183) -#define __NR_SVR4_reserved47 (__NR_SVR4 + 184) -#define __NR_SVR4_reserved48 (__NR_SVR4 + 185) -#define __NR_SVR4_reserved49 (__NR_SVR4 + 186) -#define __NR_SVR4_reserved50 (__NR_SVR4 + 187) -#define __NR_SVR4_reserved51 (__NR_SVR4 + 188) -#define __NR_SVR4_reserved52 (__NR_SVR4 + 189) -#define __NR_SVR4_reserved53 (__NR_SVR4 + 190) -#define __NR_SVR4_reserved54 (__NR_SVR4 + 191) -#define __NR_SVR4_reserved55 (__NR_SVR4 + 192) -#define __NR_SVR4_reserved56 (__NR_SVR4 + 193) -#define __NR_SVR4_reserved57 (__NR_SVR4 + 194) -#define __NR_SVR4_reserved58 (__NR_SVR4 + 195) -#define __NR_SVR4_reserved59 (__NR_SVR4 + 196) -#define __NR_SVR4_reserved60 (__NR_SVR4 + 197) -#define __NR_SVR4_reserved61 (__NR_SVR4 + 198) -#define __NR_SVR4_reserved62 (__NR_SVR4 + 199) -#define __NR_SVR4_reserved63 (__NR_SVR4 + 200) -#define __NR_SVR4_aread (__NR_SVR4 + 201) -#define __NR_SVR4_awrite (__NR_SVR4 + 202) -#define __NR_SVR4_listio (__NR_SVR4 + 203) -#define __NR_SVR4_mips_acancel (__NR_SVR4 + 204) -#define __NR_SVR4_astatus (__NR_SVR4 + 205) -#define __NR_SVR4_await (__NR_SVR4 + 206) -#define __NR_SVR4_areadv (__NR_SVR4 + 207) -#define __NR_SVR4_awritev (__NR_SVR4 + 208) -#define __NR_SVR4_MIPS_reserved1 (__NR_SVR4 + 209) -#define __NR_SVR4_MIPS_reserved2 (__NR_SVR4 + 210) -#define __NR_SVR4_MIPS_reserved3 (__NR_SVR4 + 211) -#define __NR_SVR4_MIPS_reserved4 (__NR_SVR4 + 212) -#define __NR_SVR4_MIPS_reserved5 (__NR_SVR4 + 213) -#define __NR_SVR4_MIPS_reserved6 (__NR_SVR4 + 214) -#define __NR_SVR4_MIPS_reserved7 (__NR_SVR4 + 215) -#define __NR_SVR4_MIPS_reserved8 (__NR_SVR4 + 216) -#define __NR_SVR4_MIPS_reserved9 (__NR_SVR4 + 217) -#define __NR_SVR4_MIPS_reserved10 (__NR_SVR4 + 218) -#define __NR_SVR4_MIPS_reserved11 (__NR_SVR4 + 219) -#define __NR_SVR4_MIPS_reserved12 (__NR_SVR4 + 220) -#define __NR_SVR4_CDC_reserved1 (__NR_SVR4 + 221) -#define __NR_SVR4_CDC_reserved2 (__NR_SVR4 + 222) -#define __NR_SVR4_CDC_reserved3 (__NR_SVR4 + 223) -#define __NR_SVR4_CDC_reserved4 (__NR_SVR4 + 224) -#define __NR_SVR4_CDC_reserved5 (__NR_SVR4 + 225) -#define __NR_SVR4_CDC_reserved6 (__NR_SVR4 + 226) -#define __NR_SVR4_CDC_reserved7 (__NR_SVR4 + 227) -#define __NR_SVR4_CDC_reserved8 (__NR_SVR4 + 228) -#define __NR_SVR4_CDC_reserved9 (__NR_SVR4 + 229) -#define __NR_SVR4_CDC_reserved10 (__NR_SVR4 + 230) -#define __NR_SVR4_CDC_reserved11 (__NR_SVR4 + 231) -#define __NR_SVR4_CDC_reserved12 (__NR_SVR4 + 232) -#define __NR_SVR4_CDC_reserved13 (__NR_SVR4 + 233) -#define __NR_SVR4_CDC_reserved14 (__NR_SVR4 + 234) -#define __NR_SVR4_CDC_reserved15 (__NR_SVR4 + 235) -#define __NR_SVR4_CDC_reserved16 (__NR_SVR4 + 236) -#define __NR_SVR4_CDC_reserved17 (__NR_SVR4 + 237) -#define __NR_SVR4_CDC_reserved18 (__NR_SVR4 + 238) -#define __NR_SVR4_CDC_reserved19 (__NR_SVR4 + 239) -#define __NR_SVR4_CDC_reserved20 (__NR_SVR4 + 240) - -/* - * SYS V syscalls are in the range from 1000 to 1999 - */ -#define __NR_SYSV 1000 -#define __NR_SYSV_syscall (__NR_SYSV + 0) -#define __NR_SYSV_exit (__NR_SYSV + 1) -#define __NR_SYSV_fork (__NR_SYSV + 2) -#define __NR_SYSV_read (__NR_SYSV + 3) -#define __NR_SYSV_write (__NR_SYSV + 4) -#define __NR_SYSV_open (__NR_SYSV + 5) -#define __NR_SYSV_close (__NR_SYSV + 6) -#define __NR_SYSV_wait (__NR_SYSV + 7) -#define __NR_SYSV_creat (__NR_SYSV + 8) -#define __NR_SYSV_link (__NR_SYSV + 9) -#define __NR_SYSV_unlink (__NR_SYSV + 10) -#define __NR_SYSV_execv (__NR_SYSV + 11) -#define __NR_SYSV_chdir (__NR_SYSV + 12) -#define __NR_SYSV_time (__NR_SYSV + 13) -#define __NR_SYSV_mknod (__NR_SYSV + 14) -#define __NR_SYSV_chmod (__NR_SYSV + 15) -#define __NR_SYSV_chown (__NR_SYSV + 16) -#define __NR_SYSV_brk (__NR_SYSV + 17) -#define __NR_SYSV_stat (__NR_SYSV + 18) -#define __NR_SYSV_lseek (__NR_SYSV + 19) -#define __NR_SYSV_getpid (__NR_SYSV + 20) -#define __NR_SYSV_mount (__NR_SYSV + 21) -#define __NR_SYSV_umount (__NR_SYSV + 22) -#define __NR_SYSV_setuid (__NR_SYSV + 23) -#define __NR_SYSV_getuid (__NR_SYSV + 24) -#define __NR_SYSV_stime (__NR_SYSV + 25) -#define __NR_SYSV_ptrace (__NR_SYSV + 26) -#define __NR_SYSV_alarm (__NR_SYSV + 27) -#define __NR_SYSV_fstat (__NR_SYSV + 28) -#define __NR_SYSV_pause (__NR_SYSV + 29) -#define __NR_SYSV_utime (__NR_SYSV + 30) -#define __NR_SYSV_stty (__NR_SYSV + 31) -#define __NR_SYSV_gtty (__NR_SYSV + 32) -#define __NR_SYSV_access (__NR_SYSV + 33) -#define __NR_SYSV_nice (__NR_SYSV + 34) -#define __NR_SYSV_statfs (__NR_SYSV + 35) -#define __NR_SYSV_sync (__NR_SYSV + 36) -#define __NR_SYSV_kill (__NR_SYSV + 37) -#define __NR_SYSV_fstatfs (__NR_SYSV + 38) -#define __NR_SYSV_setpgrp (__NR_SYSV + 39) -#define __NR_SYSV_syssgi (__NR_SYSV + 40) -#define __NR_SYSV_dup (__NR_SYSV + 41) -#define __NR_SYSV_pipe (__NR_SYSV + 42) -#define __NR_SYSV_times (__NR_SYSV + 43) -#define __NR_SYSV_profil (__NR_SYSV + 44) -#define __NR_SYSV_plock (__NR_SYSV + 45) -#define __NR_SYSV_setgid (__NR_SYSV + 46) -#define __NR_SYSV_getgid (__NR_SYSV + 47) -#define __NR_SYSV_sig (__NR_SYSV + 48) -#define __NR_SYSV_msgsys (__NR_SYSV + 49) -#define __NR_SYSV_sysmips (__NR_SYSV + 50) -#define __NR_SYSV_acct (__NR_SYSV + 51) -#define __NR_SYSV_shmsys (__NR_SYSV + 52) -#define __NR_SYSV_semsys (__NR_SYSV + 53) -#define __NR_SYSV_ioctl (__NR_SYSV + 54) -#define __NR_SYSV_uadmin (__NR_SYSV + 55) -#define __NR_SYSV_sysmp (__NR_SYSV + 56) -#define __NR_SYSV_utssys (__NR_SYSV + 57) -#define __NR_SYSV_USG_reserved1 (__NR_SYSV + 58) -#define __NR_SYSV_execve (__NR_SYSV + 59) -#define __NR_SYSV_umask (__NR_SYSV + 60) -#define __NR_SYSV_chroot (__NR_SYSV + 61) -#define __NR_SYSV_fcntl (__NR_SYSV + 62) -#define __NR_SYSV_ulimit (__NR_SYSV + 63) -#define __NR_SYSV_SAFARI4_reserved1 (__NR_SYSV + 64) -#define __NR_SYSV_SAFARI4_reserved2 (__NR_SYSV + 65) -#define __NR_SYSV_SAFARI4_reserved3 (__NR_SYSV + 66) -#define __NR_SYSV_SAFARI4_reserved4 (__NR_SYSV + 67) -#define __NR_SYSV_SAFARI4_reserved5 (__NR_SYSV + 68) -#define __NR_SYSV_SAFARI4_reserved6 (__NR_SYSV + 69) -#define __NR_SYSV_advfs (__NR_SYSV + 70) -#define __NR_SYSV_unadvfs (__NR_SYSV + 71) -#define __NR_SYSV_rmount (__NR_SYSV + 72) -#define __NR_SYSV_rumount (__NR_SYSV + 73) -#define __NR_SYSV_rfstart (__NR_SYSV + 74) -#define __NR_SYSV_getrlimit64 (__NR_SYSV + 75) -#define __NR_SYSV_setrlimit64 (__NR_SYSV + 76) -#define __NR_SYSV_nanosleep (__NR_SYSV + 77) -#define __NR_SYSV_lseek64 (__NR_SYSV + 78) -#define __NR_SYSV_rmdir (__NR_SYSV + 79) -#define __NR_SYSV_mkdir (__NR_SYSV + 80) -#define __NR_SYSV_getdents (__NR_SYSV + 81) -#define __NR_SYSV_sginap (__NR_SYSV + 82) -#define __NR_SYSV_sgikopt (__NR_SYSV + 83) -#define __NR_SYSV_sysfs (__NR_SYSV + 84) -#define __NR_SYSV_getmsg (__NR_SYSV + 85) -#define __NR_SYSV_putmsg (__NR_SYSV + 86) -#define __NR_SYSV_poll (__NR_SYSV + 87) -#define __NR_SYSV_sigreturn (__NR_SYSV + 88) -#define __NR_SYSV_accept (__NR_SYSV + 89) -#define __NR_SYSV_bind (__NR_SYSV + 90) -#define __NR_SYSV_connect (__NR_SYSV + 91) -#define __NR_SYSV_gethostid (__NR_SYSV + 92) -#define __NR_SYSV_getpeername (__NR_SYSV + 93) -#define __NR_SYSV_getsockname (__NR_SYSV + 94) -#define __NR_SYSV_getsockopt (__NR_SYSV + 95) -#define __NR_SYSV_listen (__NR_SYSV + 96) -#define __NR_SYSV_recv (__NR_SYSV + 97) -#define __NR_SYSV_recvfrom (__NR_SYSV + 98) -#define __NR_SYSV_recvmsg (__NR_SYSV + 99) -#define __NR_SYSV_select (__NR_SYSV + 100) -#define __NR_SYSV_send (__NR_SYSV + 101) -#define __NR_SYSV_sendmsg (__NR_SYSV + 102) -#define __NR_SYSV_sendto (__NR_SYSV + 103) -#define __NR_SYSV_sethostid (__NR_SYSV + 104) -#define __NR_SYSV_setsockopt (__NR_SYSV + 105) -#define __NR_SYSV_shutdown (__NR_SYSV + 106) -#define __NR_SYSV_socket (__NR_SYSV + 107) -#define __NR_SYSV_gethostname (__NR_SYSV + 108) -#define __NR_SYSV_sethostname (__NR_SYSV + 109) -#define __NR_SYSV_getdomainname (__NR_SYSV + 110) -#define __NR_SYSV_setdomainname (__NR_SYSV + 111) -#define __NR_SYSV_truncate (__NR_SYSV + 112) -#define __NR_SYSV_ftruncate (__NR_SYSV + 113) -#define __NR_SYSV_rename (__NR_SYSV + 114) -#define __NR_SYSV_symlink (__NR_SYSV + 115) -#define __NR_SYSV_readlink (__NR_SYSV + 116) -#define __NR_SYSV_lstat (__NR_SYSV + 117) -#define __NR_SYSV_nfsmount (__NR_SYSV + 118) -#define __NR_SYSV_nfssvc (__NR_SYSV + 119) -#define __NR_SYSV_getfh (__NR_SYSV + 120) -#define __NR_SYSV_async_daemon (__NR_SYSV + 121) -#define __NR_SYSV_exportfs (__NR_SYSV + 122) -#define __NR_SYSV_setregid (__NR_SYSV + 123) -#define __NR_SYSV_setreuid (__NR_SYSV + 124) -#define __NR_SYSV_getitimer (__NR_SYSV + 125) -#define __NR_SYSV_setitimer (__NR_SYSV + 126) -#define __NR_SYSV_adjtime (__NR_SYSV + 127) -#define __NR_SYSV_BSD_getime (__NR_SYSV + 128) -#define __NR_SYSV_sproc (__NR_SYSV + 129) -#define __NR_SYSV_prctl (__NR_SYSV + 130) -#define __NR_SYSV_procblk (__NR_SYSV + 131) -#define __NR_SYSV_sprocsp (__NR_SYSV + 132) -#define __NR_SYSV_sgigsc (__NR_SYSV + 133) -#define __NR_SYSV_mmap (__NR_SYSV + 134) -#define __NR_SYSV_munmap (__NR_SYSV + 135) -#define __NR_SYSV_mprotect (__NR_SYSV + 136) -#define __NR_SYSV_msync (__NR_SYSV + 137) -#define __NR_SYSV_madvise (__NR_SYSV + 138) -#define __NR_SYSV_pagelock (__NR_SYSV + 139) -#define __NR_SYSV_getpagesize (__NR_SYSV + 140) -#define __NR_SYSV_quotactl (__NR_SYSV + 141) -#define __NR_SYSV_libdetach (__NR_SYSV + 142) -#define __NR_SYSV_BSDgetpgrp (__NR_SYSV + 143) -#define __NR_SYSV_BSDsetpgrp (__NR_SYSV + 144) -#define __NR_SYSV_vhangup (__NR_SYSV + 145) -#define __NR_SYSV_fsync (__NR_SYSV + 146) -#define __NR_SYSV_fchdir (__NR_SYSV + 147) -#define __NR_SYSV_getrlimit (__NR_SYSV + 148) -#define __NR_SYSV_setrlimit (__NR_SYSV + 149) -#define __NR_SYSV_cacheflush (__NR_SYSV + 150) -#define __NR_SYSV_cachectl (__NR_SYSV + 151) -#define __NR_SYSV_fchown (__NR_SYSV + 152) -#define __NR_SYSV_fchmod (__NR_SYSV + 153) -#define __NR_SYSV_wait3 (__NR_SYSV + 154) -#define __NR_SYSV_socketpair (__NR_SYSV + 155) -#define __NR_SYSV_sysinfo (__NR_SYSV + 156) -#define __NR_SYSV_nuname (__NR_SYSV + 157) -#define __NR_SYSV_xstat (__NR_SYSV + 158) -#define __NR_SYSV_lxstat (__NR_SYSV + 159) -#define __NR_SYSV_fxstat (__NR_SYSV + 160) -#define __NR_SYSV_xmknod (__NR_SYSV + 161) -#define __NR_SYSV_ksigaction (__NR_SYSV + 162) -#define __NR_SYSV_sigpending (__NR_SYSV + 163) -#define __NR_SYSV_sigprocmask (__NR_SYSV + 164) -#define __NR_SYSV_sigsuspend (__NR_SYSV + 165) -#define __NR_SYSV_sigpoll (__NR_SYSV + 166) -#define __NR_SYSV_swapctl (__NR_SYSV + 167) -#define __NR_SYSV_getcontext (__NR_SYSV + 168) -#define __NR_SYSV_setcontext (__NR_SYSV + 169) -#define __NR_SYSV_waitsys (__NR_SYSV + 170) -#define __NR_SYSV_sigstack (__NR_SYSV + 171) -#define __NR_SYSV_sigaltstack (__NR_SYSV + 172) -#define __NR_SYSV_sigsendset (__NR_SYSV + 173) -#define __NR_SYSV_statvfs (__NR_SYSV + 174) -#define __NR_SYSV_fstatvfs (__NR_SYSV + 175) -#define __NR_SYSV_getpmsg (__NR_SYSV + 176) -#define __NR_SYSV_putpmsg (__NR_SYSV + 177) -#define __NR_SYSV_lchown (__NR_SYSV + 178) -#define __NR_SYSV_priocntl (__NR_SYSV + 179) -#define __NR_SYSV_ksigqueue (__NR_SYSV + 180) -#define __NR_SYSV_readv (__NR_SYSV + 181) -#define __NR_SYSV_writev (__NR_SYSV + 182) -#define __NR_SYSV_truncate64 (__NR_SYSV + 183) -#define __NR_SYSV_ftruncate64 (__NR_SYSV + 184) -#define __NR_SYSV_mmap64 (__NR_SYSV + 185) -#define __NR_SYSV_dmi (__NR_SYSV + 186) -#define __NR_SYSV_pread (__NR_SYSV + 187) -#define __NR_SYSV_pwrite (__NR_SYSV + 188) - -/* - * BSD 4.3 syscalls are in the range from 2000 to 2999 - */ -#define __NR_BSD43 2000 -#define __NR_BSD43_syscall (__NR_BSD43 + 0) -#define __NR_BSD43_exit (__NR_BSD43 + 1) -#define __NR_BSD43_fork (__NR_BSD43 + 2) -#define __NR_BSD43_read (__NR_BSD43 + 3) -#define __NR_BSD43_write (__NR_BSD43 + 4) -#define __NR_BSD43_open (__NR_BSD43 + 5) -#define __NR_BSD43_close (__NR_BSD43 + 6) -#define __NR_BSD43_wait (__NR_BSD43 + 7) -#define __NR_BSD43_creat (__NR_BSD43 + 8) -#define __NR_BSD43_link (__NR_BSD43 + 9) -#define __NR_BSD43_unlink (__NR_BSD43 + 10) -#define __NR_BSD43_exec (__NR_BSD43 + 11) -#define __NR_BSD43_chdir (__NR_BSD43 + 12) -#define __NR_BSD43_time (__NR_BSD43 + 13) -#define __NR_BSD43_mknod (__NR_BSD43 + 14) -#define __NR_BSD43_chmod (__NR_BSD43 + 15) -#define __NR_BSD43_chown (__NR_BSD43 + 16) -#define __NR_BSD43_sbreak (__NR_BSD43 + 17) -#define __NR_BSD43_oldstat (__NR_BSD43 + 18) -#define __NR_BSD43_lseek (__NR_BSD43 + 19) -#define __NR_BSD43_getpid (__NR_BSD43 + 20) -#define __NR_BSD43_oldmount (__NR_BSD43 + 21) -#define __NR_BSD43_umount (__NR_BSD43 + 22) -#define __NR_BSD43_setuid (__NR_BSD43 + 23) -#define __NR_BSD43_getuid (__NR_BSD43 + 24) -#define __NR_BSD43_stime (__NR_BSD43 + 25) -#define __NR_BSD43_ptrace (__NR_BSD43 + 26) -#define __NR_BSD43_alarm (__NR_BSD43 + 27) -#define __NR_BSD43_oldfstat (__NR_BSD43 + 28) -#define __NR_BSD43_pause (__NR_BSD43 + 29) -#define __NR_BSD43_utime (__NR_BSD43 + 30) -#define __NR_BSD43_stty (__NR_BSD43 + 31) -#define __NR_BSD43_gtty (__NR_BSD43 + 32) -#define __NR_BSD43_access (__NR_BSD43 + 33) -#define __NR_BSD43_nice (__NR_BSD43 + 34) -#define __NR_BSD43_ftime (__NR_BSD43 + 35) -#define __NR_BSD43_sync (__NR_BSD43 + 36) -#define __NR_BSD43_kill (__NR_BSD43 + 37) -#define __NR_BSD43_stat (__NR_BSD43 + 38) -#define __NR_BSD43_oldsetpgrp (__NR_BSD43 + 39) -#define __NR_BSD43_lstat (__NR_BSD43 + 40) -#define __NR_BSD43_dup (__NR_BSD43 + 41) -#define __NR_BSD43_pipe (__NR_BSD43 + 42) -#define __NR_BSD43_times (__NR_BSD43 + 43) -#define __NR_BSD43_profil (__NR_BSD43 + 44) -#define __NR_BSD43_msgsys (__NR_BSD43 + 45) -#define __NR_BSD43_setgid (__NR_BSD43 + 46) -#define __NR_BSD43_getgid (__NR_BSD43 + 47) -#define __NR_BSD43_ssig (__NR_BSD43 + 48) -#define __NR_BSD43_reserved1 (__NR_BSD43 + 49) -#define __NR_BSD43_reserved2 (__NR_BSD43 + 50) -#define __NR_BSD43_sysacct (__NR_BSD43 + 51) -#define __NR_BSD43_phys (__NR_BSD43 + 52) -#define __NR_BSD43_lock (__NR_BSD43 + 53) -#define __NR_BSD43_ioctl (__NR_BSD43 + 54) -#define __NR_BSD43_reboot (__NR_BSD43 + 55) -#define __NR_BSD43_mpxchan (__NR_BSD43 + 56) -#define __NR_BSD43_symlink (__NR_BSD43 + 57) -#define __NR_BSD43_readlink (__NR_BSD43 + 58) -#define __NR_BSD43_execve (__NR_BSD43 + 59) -#define __NR_BSD43_umask (__NR_BSD43 + 60) -#define __NR_BSD43_chroot (__NR_BSD43 + 61) -#define __NR_BSD43_fstat (__NR_BSD43 + 62) -#define __NR_BSD43_reserved3 (__NR_BSD43 + 63) -#define __NR_BSD43_getpagesize (__NR_BSD43 + 64) -#define __NR_BSD43_mremap (__NR_BSD43 + 65) -#define __NR_BSD43_vfork (__NR_BSD43 + 66) -#define __NR_BSD43_vread (__NR_BSD43 + 67) -#define __NR_BSD43_vwrite (__NR_BSD43 + 68) -#define __NR_BSD43_sbrk (__NR_BSD43 + 69) -#define __NR_BSD43_sstk (__NR_BSD43 + 70) -#define __NR_BSD43_mmap (__NR_BSD43 + 71) -#define __NR_BSD43_vadvise (__NR_BSD43 + 72) -#define __NR_BSD43_munmap (__NR_BSD43 + 73) -#define __NR_BSD43_mprotect (__NR_BSD43 + 74) -#define __NR_BSD43_madvise (__NR_BSD43 + 75) -#define __NR_BSD43_vhangup (__NR_BSD43 + 76) -#define __NR_BSD43_vlimit (__NR_BSD43 + 77) -#define __NR_BSD43_mincore (__NR_BSD43 + 78) -#define __NR_BSD43_getgroups (__NR_BSD43 + 79) -#define __NR_BSD43_setgroups (__NR_BSD43 + 80) -#define __NR_BSD43_getpgrp (__NR_BSD43 + 81) -#define __NR_BSD43_setpgrp (__NR_BSD43 + 82) -#define __NR_BSD43_setitimer (__NR_BSD43 + 83) -#define __NR_BSD43_wait3 (__NR_BSD43 + 84) -#define __NR_BSD43_swapon (__NR_BSD43 + 85) -#define __NR_BSD43_getitimer (__NR_BSD43 + 86) -#define __NR_BSD43_gethostname (__NR_BSD43 + 87) -#define __NR_BSD43_sethostname (__NR_BSD43 + 88) -#define __NR_BSD43_getdtablesize (__NR_BSD43 + 89) -#define __NR_BSD43_dup2 (__NR_BSD43 + 90) -#define __NR_BSD43_getdopt (__NR_BSD43 + 91) -#define __NR_BSD43_fcntl (__NR_BSD43 + 92) -#define __NR_BSD43_select (__NR_BSD43 + 93) -#define __NR_BSD43_setdopt (__NR_BSD43 + 94) -#define __NR_BSD43_fsync (__NR_BSD43 + 95) -#define __NR_BSD43_setpriority (__NR_BSD43 + 96) -#define __NR_BSD43_socket (__NR_BSD43 + 97) -#define __NR_BSD43_connect (__NR_BSD43 + 98) -#define __NR_BSD43_oldaccept (__NR_BSD43 + 99) -#define __NR_BSD43_getpriority (__NR_BSD43 + 100) -#define __NR_BSD43_send (__NR_BSD43 + 101) -#define __NR_BSD43_recv (__NR_BSD43 + 102) -#define __NR_BSD43_sigreturn (__NR_BSD43 + 103) -#define __NR_BSD43_bind (__NR_BSD43 + 104) -#define __NR_BSD43_setsockopt (__NR_BSD43 + 105) -#define __NR_BSD43_listen (__NR_BSD43 + 106) -#define __NR_BSD43_vtimes (__NR_BSD43 + 107) -#define __NR_BSD43_sigvec (__NR_BSD43 + 108) -#define __NR_BSD43_sigblock (__NR_BSD43 + 109) -#define __NR_BSD43_sigsetmask (__NR_BSD43 + 110) -#define __NR_BSD43_sigpause (__NR_BSD43 + 111) -#define __NR_BSD43_sigstack (__NR_BSD43 + 112) -#define __NR_BSD43_oldrecvmsg (__NR_BSD43 + 113) -#define __NR_BSD43_oldsendmsg (__NR_BSD43 + 114) -#define __NR_BSD43_vtrace (__NR_BSD43 + 115) -#define __NR_BSD43_gettimeofday (__NR_BSD43 + 116) -#define __NR_BSD43_getrusage (__NR_BSD43 + 117) -#define __NR_BSD43_getsockopt (__NR_BSD43 + 118) -#define __NR_BSD43_reserved4 (__NR_BSD43 + 119) -#define __NR_BSD43_readv (__NR_BSD43 + 120) -#define __NR_BSD43_writev (__NR_BSD43 + 121) -#define __NR_BSD43_settimeofday (__NR_BSD43 + 122) -#define __NR_BSD43_fchown (__NR_BSD43 + 123) -#define __NR_BSD43_fchmod (__NR_BSD43 + 124) -#define __NR_BSD43_oldrecvfrom (__NR_BSD43 + 125) -#define __NR_BSD43_setreuid (__NR_BSD43 + 126) -#define __NR_BSD43_setregid (__NR_BSD43 + 127) -#define __NR_BSD43_rename (__NR_BSD43 + 128) -#define __NR_BSD43_truncate (__NR_BSD43 + 129) -#define __NR_BSD43_ftruncate (__NR_BSD43 + 130) -#define __NR_BSD43_flock (__NR_BSD43 + 131) -#define __NR_BSD43_semsys (__NR_BSD43 + 132) -#define __NR_BSD43_sendto (__NR_BSD43 + 133) -#define __NR_BSD43_shutdown (__NR_BSD43 + 134) -#define __NR_BSD43_socketpair (__NR_BSD43 + 135) -#define __NR_BSD43_mkdir (__NR_BSD43 + 136) -#define __NR_BSD43_rmdir (__NR_BSD43 + 137) -#define __NR_BSD43_utimes (__NR_BSD43 + 138) -#define __NR_BSD43_sigcleanup (__NR_BSD43 + 139) -#define __NR_BSD43_adjtime (__NR_BSD43 + 140) -#define __NR_BSD43_oldgetpeername (__NR_BSD43 + 141) -#define __NR_BSD43_gethostid (__NR_BSD43 + 142) -#define __NR_BSD43_sethostid (__NR_BSD43 + 143) -#define __NR_BSD43_getrlimit (__NR_BSD43 + 144) -#define __NR_BSD43_setrlimit (__NR_BSD43 + 145) -#define __NR_BSD43_killpg (__NR_BSD43 + 146) -#define __NR_BSD43_shmsys (__NR_BSD43 + 147) -#define __NR_BSD43_quota (__NR_BSD43 + 148) -#define __NR_BSD43_qquota (__NR_BSD43 + 149) -#define __NR_BSD43_oldgetsockname (__NR_BSD43 + 150) -#define __NR_BSD43_sysmips (__NR_BSD43 + 151) -#define __NR_BSD43_cacheflush (__NR_BSD43 + 152) -#define __NR_BSD43_cachectl (__NR_BSD43 + 153) -#define __NR_BSD43_debug (__NR_BSD43 + 154) -#define __NR_BSD43_reserved5 (__NR_BSD43 + 155) -#define __NR_BSD43_reserved6 (__NR_BSD43 + 156) -#define __NR_BSD43_nfs_mount (__NR_BSD43 + 157) -#define __NR_BSD43_nfs_svc (__NR_BSD43 + 158) -#define __NR_BSD43_getdirentries (__NR_BSD43 + 159) -#define __NR_BSD43_statfs (__NR_BSD43 + 160) -#define __NR_BSD43_fstatfs (__NR_BSD43 + 161) -#define __NR_BSD43_unmount (__NR_BSD43 + 162) -#define __NR_BSD43_async_daemon (__NR_BSD43 + 163) -#define __NR_BSD43_nfs_getfh (__NR_BSD43 + 164) -#define __NR_BSD43_getdomainname (__NR_BSD43 + 165) -#define __NR_BSD43_setdomainname (__NR_BSD43 + 166) -#define __NR_BSD43_pcfs_mount (__NR_BSD43 + 167) -#define __NR_BSD43_quotactl (__NR_BSD43 + 168) -#define __NR_BSD43_oldexportfs (__NR_BSD43 + 169) -#define __NR_BSD43_smount (__NR_BSD43 + 170) -#define __NR_BSD43_mipshwconf (__NR_BSD43 + 171) -#define __NR_BSD43_exportfs (__NR_BSD43 + 172) -#define __NR_BSD43_nfsfh_open (__NR_BSD43 + 173) -#define __NR_BSD43_libattach (__NR_BSD43 + 174) -#define __NR_BSD43_libdetach (__NR_BSD43 + 175) -#define __NR_BSD43_accept (__NR_BSD43 + 176) -#define __NR_BSD43_reserved7 (__NR_BSD43 + 177) -#define __NR_BSD43_reserved8 (__NR_BSD43 + 178) -#define __NR_BSD43_recvmsg (__NR_BSD43 + 179) -#define __NR_BSD43_recvfrom (__NR_BSD43 + 180) -#define __NR_BSD43_sendmsg (__NR_BSD43 + 181) -#define __NR_BSD43_getpeername (__NR_BSD43 + 182) -#define __NR_BSD43_getsockname (__NR_BSD43 + 183) -#define __NR_BSD43_aread (__NR_BSD43 + 184) -#define __NR_BSD43_awrite (__NR_BSD43 + 185) -#define __NR_BSD43_listio (__NR_BSD43 + 186) -#define __NR_BSD43_acancel (__NR_BSD43 + 187) -#define __NR_BSD43_astatus (__NR_BSD43 + 188) -#define __NR_BSD43_await (__NR_BSD43 + 189) -#define __NR_BSD43_areadv (__NR_BSD43 + 190) -#define __NR_BSD43_awritev (__NR_BSD43 + 191) - -/* - * POSIX syscalls are in the range from 3000 to 3999 - */ -#define __NR_POSIX 3000 -#define __NR_POSIX_syscall (__NR_POSIX + 0) -#define __NR_POSIX_exit (__NR_POSIX + 1) -#define __NR_POSIX_fork (__NR_POSIX + 2) -#define __NR_POSIX_read (__NR_POSIX + 3) -#define __NR_POSIX_write (__NR_POSIX + 4) -#define __NR_POSIX_open (__NR_POSIX + 5) -#define __NR_POSIX_close (__NR_POSIX + 6) -#define __NR_POSIX_wait (__NR_POSIX + 7) -#define __NR_POSIX_creat (__NR_POSIX + 8) -#define __NR_POSIX_link (__NR_POSIX + 9) -#define __NR_POSIX_unlink (__NR_POSIX + 10) -#define __NR_POSIX_exec (__NR_POSIX + 11) -#define __NR_POSIX_chdir (__NR_POSIX + 12) -#define __NR_POSIX_gtime (__NR_POSIX + 13) -#define __NR_POSIX_mknod (__NR_POSIX + 14) -#define __NR_POSIX_chmod (__NR_POSIX + 15) -#define __NR_POSIX_chown (__NR_POSIX + 16) -#define __NR_POSIX_sbreak (__NR_POSIX + 17) -#define __NR_POSIX_stat (__NR_POSIX + 18) -#define __NR_POSIX_lseek (__NR_POSIX + 19) -#define __NR_POSIX_getpid (__NR_POSIX + 20) -#define __NR_POSIX_mount (__NR_POSIX + 21) -#define __NR_POSIX_umount (__NR_POSIX + 22) -#define __NR_POSIX_setuid (__NR_POSIX + 23) -#define __NR_POSIX_getuid (__NR_POSIX + 24) -#define __NR_POSIX_stime (__NR_POSIX + 25) -#define __NR_POSIX_ptrace (__NR_POSIX + 26) -#define __NR_POSIX_alarm (__NR_POSIX + 27) -#define __NR_POSIX_fstat (__NR_POSIX + 28) -#define __NR_POSIX_pause (__NR_POSIX + 29) -#define __NR_POSIX_utime (__NR_POSIX + 30) -#define __NR_POSIX_stty (__NR_POSIX + 31) -#define __NR_POSIX_gtty (__NR_POSIX + 32) -#define __NR_POSIX_access (__NR_POSIX + 33) -#define __NR_POSIX_nice (__NR_POSIX + 34) -#define __NR_POSIX_statfs (__NR_POSIX + 35) -#define __NR_POSIX_sync (__NR_POSIX + 36) -#define __NR_POSIX_kill (__NR_POSIX + 37) -#define __NR_POSIX_fstatfs (__NR_POSIX + 38) -#define __NR_POSIX_getpgrp (__NR_POSIX + 39) -#define __NR_POSIX_syssgi (__NR_POSIX + 40) -#define __NR_POSIX_dup (__NR_POSIX + 41) -#define __NR_POSIX_pipe (__NR_POSIX + 42) -#define __NR_POSIX_times (__NR_POSIX + 43) -#define __NR_POSIX_profil (__NR_POSIX + 44) -#define __NR_POSIX_lock (__NR_POSIX + 45) -#define __NR_POSIX_setgid (__NR_POSIX + 46) -#define __NR_POSIX_getgid (__NR_POSIX + 47) -#define __NR_POSIX_sig (__NR_POSIX + 48) -#define __NR_POSIX_msgsys (__NR_POSIX + 49) -#define __NR_POSIX_sysmips (__NR_POSIX + 50) -#define __NR_POSIX_sysacct (__NR_POSIX + 51) -#define __NR_POSIX_shmsys (__NR_POSIX + 52) -#define __NR_POSIX_semsys (__NR_POSIX + 53) -#define __NR_POSIX_ioctl (__NR_POSIX + 54) -#define __NR_POSIX_uadmin (__NR_POSIX + 55) -#define __NR_POSIX_exch (__NR_POSIX + 56) -#define __NR_POSIX_utssys (__NR_POSIX + 57) -#define __NR_POSIX_USG_reserved1 (__NR_POSIX + 58) -#define __NR_POSIX_exece (__NR_POSIX + 59) -#define __NR_POSIX_umask (__NR_POSIX + 60) -#define __NR_POSIX_chroot (__NR_POSIX + 61) -#define __NR_POSIX_fcntl (__NR_POSIX + 62) -#define __NR_POSIX_ulimit (__NR_POSIX + 63) -#define __NR_POSIX_SAFARI4_reserved1 (__NR_POSIX + 64) -#define __NR_POSIX_SAFARI4_reserved2 (__NR_POSIX + 65) -#define __NR_POSIX_SAFARI4_reserved3 (__NR_POSIX + 66) -#define __NR_POSIX_SAFARI4_reserved4 (__NR_POSIX + 67) -#define __NR_POSIX_SAFARI4_reserved5 (__NR_POSIX + 68) -#define __NR_POSIX_SAFARI4_reserved6 (__NR_POSIX + 69) -#define __NR_POSIX_advfs (__NR_POSIX + 70) -#define __NR_POSIX_unadvfs (__NR_POSIX + 71) -#define __NR_POSIX_rmount (__NR_POSIX + 72) -#define __NR_POSIX_rumount (__NR_POSIX + 73) -#define __NR_POSIX_rfstart (__NR_POSIX + 74) -#define __NR_POSIX_reserved1 (__NR_POSIX + 75) -#define __NR_POSIX_rdebug (__NR_POSIX + 76) -#define __NR_POSIX_rfstop (__NR_POSIX + 77) -#define __NR_POSIX_rfsys (__NR_POSIX + 78) -#define __NR_POSIX_rmdir (__NR_POSIX + 79) -#define __NR_POSIX_mkdir (__NR_POSIX + 80) -#define __NR_POSIX_getdents (__NR_POSIX + 81) -#define __NR_POSIX_sginap (__NR_POSIX + 82) -#define __NR_POSIX_sgikopt (__NR_POSIX + 83) -#define __NR_POSIX_sysfs (__NR_POSIX + 84) -#define __NR_POSIX_getmsg (__NR_POSIX + 85) -#define __NR_POSIX_putmsg (__NR_POSIX + 86) -#define __NR_POSIX_poll (__NR_POSIX + 87) -#define __NR_POSIX_sigreturn (__NR_POSIX + 88) -#define __NR_POSIX_accept (__NR_POSIX + 89) -#define __NR_POSIX_bind (__NR_POSIX + 90) -#define __NR_POSIX_connect (__NR_POSIX + 91) -#define __NR_POSIX_gethostid (__NR_POSIX + 92) -#define __NR_POSIX_getpeername (__NR_POSIX + 93) -#define __NR_POSIX_getsockname (__NR_POSIX + 94) -#define __NR_POSIX_getsockopt (__NR_POSIX + 95) -#define __NR_POSIX_listen (__NR_POSIX + 96) -#define __NR_POSIX_recv (__NR_POSIX + 97) -#define __NR_POSIX_recvfrom (__NR_POSIX + 98) -#define __NR_POSIX_recvmsg (__NR_POSIX + 99) -#define __NR_POSIX_select (__NR_POSIX + 100) -#define __NR_POSIX_send (__NR_POSIX + 101) -#define __NR_POSIX_sendmsg (__NR_POSIX + 102) -#define __NR_POSIX_sendto (__NR_POSIX + 103) -#define __NR_POSIX_sethostid (__NR_POSIX + 104) -#define __NR_POSIX_setsockopt (__NR_POSIX + 105) -#define __NR_POSIX_shutdown (__NR_POSIX + 106) -#define __NR_POSIX_socket (__NR_POSIX + 107) -#define __NR_POSIX_gethostname (__NR_POSIX + 108) -#define __NR_POSIX_sethostname (__NR_POSIX + 109) -#define __NR_POSIX_getdomainname (__NR_POSIX + 110) -#define __NR_POSIX_setdomainname (__NR_POSIX + 111) -#define __NR_POSIX_truncate (__NR_POSIX + 112) -#define __NR_POSIX_ftruncate (__NR_POSIX + 113) -#define __NR_POSIX_rename (__NR_POSIX + 114) -#define __NR_POSIX_symlink (__NR_POSIX + 115) -#define __NR_POSIX_readlink (__NR_POSIX + 116) -#define __NR_POSIX_lstat (__NR_POSIX + 117) -#define __NR_POSIX_nfs_mount (__NR_POSIX + 118) -#define __NR_POSIX_nfs_svc (__NR_POSIX + 119) -#define __NR_POSIX_nfs_getfh (__NR_POSIX + 120) -#define __NR_POSIX_async_daemon (__NR_POSIX + 121) -#define __NR_POSIX_exportfs (__NR_POSIX + 122) -#define __NR_POSIX_SGI_setregid (__NR_POSIX + 123) -#define __NR_POSIX_SGI_setreuid (__NR_POSIX + 124) -#define __NR_POSIX_getitimer (__NR_POSIX + 125) -#define __NR_POSIX_setitimer (__NR_POSIX + 126) -#define __NR_POSIX_adjtime (__NR_POSIX + 127) -#define __NR_POSIX_SGI_bsdgettime (__NR_POSIX + 128) -#define __NR_POSIX_SGI_sproc (__NR_POSIX + 129) -#define __NR_POSIX_SGI_prctl (__NR_POSIX + 130) -#define __NR_POSIX_SGI_blkproc (__NR_POSIX + 131) -#define __NR_POSIX_SGI_reserved1 (__NR_POSIX + 132) -#define __NR_POSIX_SGI_sgigsc (__NR_POSIX + 133) -#define __NR_POSIX_SGI_mmap (__NR_POSIX + 134) -#define __NR_POSIX_SGI_munmap (__NR_POSIX + 135) -#define __NR_POSIX_SGI_mprotect (__NR_POSIX + 136) -#define __NR_POSIX_SGI_msync (__NR_POSIX + 137) -#define __NR_POSIX_SGI_madvise (__NR_POSIX + 138) -#define __NR_POSIX_SGI_mpin (__NR_POSIX + 139) -#define __NR_POSIX_SGI_getpagesize (__NR_POSIX + 140) -#define __NR_POSIX_SGI_libattach (__NR_POSIX + 141) -#define __NR_POSIX_SGI_libdetach (__NR_POSIX + 142) -#define __NR_POSIX_SGI_getpgrp (__NR_POSIX + 143) -#define __NR_POSIX_SGI_setpgrp (__NR_POSIX + 144) -#define __NR_POSIX_SGI_reserved2 (__NR_POSIX + 145) -#define __NR_POSIX_SGI_reserved3 (__NR_POSIX + 146) -#define __NR_POSIX_SGI_reserved4 (__NR_POSIX + 147) -#define __NR_POSIX_SGI_reserved5 (__NR_POSIX + 148) -#define __NR_POSIX_SGI_reserved6 (__NR_POSIX + 149) -#define __NR_POSIX_cacheflush (__NR_POSIX + 150) -#define __NR_POSIX_cachectl (__NR_POSIX + 151) -#define __NR_POSIX_fchown (__NR_POSIX + 152) -#define __NR_POSIX_fchmod (__NR_POSIX + 153) -#define __NR_POSIX_wait3 (__NR_POSIX + 154) -#define __NR_POSIX_mmap (__NR_POSIX + 155) -#define __NR_POSIX_munmap (__NR_POSIX + 156) -#define __NR_POSIX_madvise (__NR_POSIX + 157) -#define __NR_POSIX_BSD_getpagesize (__NR_POSIX + 158) -#define __NR_POSIX_setreuid (__NR_POSIX + 159) -#define __NR_POSIX_setregid (__NR_POSIX + 160) -#define __NR_POSIX_setpgid (__NR_POSIX + 161) -#define __NR_POSIX_getgroups (__NR_POSIX + 162) -#define __NR_POSIX_setgroups (__NR_POSIX + 163) -#define __NR_POSIX_gettimeofday (__NR_POSIX + 164) -#define __NR_POSIX_getrusage (__NR_POSIX + 165) -#define __NR_POSIX_getrlimit (__NR_POSIX + 166) -#define __NR_POSIX_setrlimit (__NR_POSIX + 167) -#define __NR_POSIX_waitpid (__NR_POSIX + 168) -#define __NR_POSIX_dup2 (__NR_POSIX + 169) -#define __NR_POSIX_reserved2 (__NR_POSIX + 170) -#define __NR_POSIX_reserved3 (__NR_POSIX + 171) -#define __NR_POSIX_reserved4 (__NR_POSIX + 172) -#define __NR_POSIX_reserved5 (__NR_POSIX + 173) -#define __NR_POSIX_reserved6 (__NR_POSIX + 174) -#define __NR_POSIX_reserved7 (__NR_POSIX + 175) -#define __NR_POSIX_reserved8 (__NR_POSIX + 176) -#define __NR_POSIX_reserved9 (__NR_POSIX + 177) -#define __NR_POSIX_reserved10 (__NR_POSIX + 178) -#define __NR_POSIX_reserved11 (__NR_POSIX + 179) -#define __NR_POSIX_reserved12 (__NR_POSIX + 180) -#define __NR_POSIX_reserved13 (__NR_POSIX + 181) -#define __NR_POSIX_reserved14 (__NR_POSIX + 182) -#define __NR_POSIX_reserved15 (__NR_POSIX + 183) -#define __NR_POSIX_reserved16 (__NR_POSIX + 184) -#define __NR_POSIX_reserved17 (__NR_POSIX + 185) -#define __NR_POSIX_reserved18 (__NR_POSIX + 186) -#define __NR_POSIX_reserved19 (__NR_POSIX + 187) -#define __NR_POSIX_reserved20 (__NR_POSIX + 188) -#define __NR_POSIX_reserved21 (__NR_POSIX + 189) -#define __NR_POSIX_reserved22 (__NR_POSIX + 190) -#define __NR_POSIX_reserved23 (__NR_POSIX + 191) -#define __NR_POSIX_reserved24 (__NR_POSIX + 192) -#define __NR_POSIX_reserved25 (__NR_POSIX + 193) -#define __NR_POSIX_reserved26 (__NR_POSIX + 194) -#define __NR_POSIX_reserved27 (__NR_POSIX + 195) -#define __NR_POSIX_reserved28 (__NR_POSIX + 196) -#define __NR_POSIX_reserved29 (__NR_POSIX + 197) -#define __NR_POSIX_reserved30 (__NR_POSIX + 198) -#define __NR_POSIX_reserved31 (__NR_POSIX + 199) -#define __NR_POSIX_reserved32 (__NR_POSIX + 200) -#define __NR_POSIX_reserved33 (__NR_POSIX + 201) -#define __NR_POSIX_reserved34 (__NR_POSIX + 202) -#define __NR_POSIX_reserved35 (__NR_POSIX + 203) -#define __NR_POSIX_reserved36 (__NR_POSIX + 204) -#define __NR_POSIX_reserved37 (__NR_POSIX + 205) -#define __NR_POSIX_reserved38 (__NR_POSIX + 206) -#define __NR_POSIX_reserved39 (__NR_POSIX + 207) -#define __NR_POSIX_reserved40 (__NR_POSIX + 208) -#define __NR_POSIX_reserved41 (__NR_POSIX + 209) -#define __NR_POSIX_reserved42 (__NR_POSIX + 210) -#define __NR_POSIX_reserved43 (__NR_POSIX + 211) -#define __NR_POSIX_reserved44 (__NR_POSIX + 212) -#define __NR_POSIX_reserved45 (__NR_POSIX + 213) -#define __NR_POSIX_reserved46 (__NR_POSIX + 214) -#define __NR_POSIX_reserved47 (__NR_POSIX + 215) -#define __NR_POSIX_reserved48 (__NR_POSIX + 216) -#define __NR_POSIX_reserved49 (__NR_POSIX + 217) -#define __NR_POSIX_reserved50 (__NR_POSIX + 218) -#define __NR_POSIX_reserved51 (__NR_POSIX + 219) -#define __NR_POSIX_reserved52 (__NR_POSIX + 220) -#define __NR_POSIX_reserved53 (__NR_POSIX + 221) -#define __NR_POSIX_reserved54 (__NR_POSIX + 222) -#define __NR_POSIX_reserved55 (__NR_POSIX + 223) -#define __NR_POSIX_reserved56 (__NR_POSIX + 224) -#define __NR_POSIX_reserved57 (__NR_POSIX + 225) -#define __NR_POSIX_reserved58 (__NR_POSIX + 226) -#define __NR_POSIX_reserved59 (__NR_POSIX + 227) -#define __NR_POSIX_reserved60 (__NR_POSIX + 228) -#define __NR_POSIX_reserved61 (__NR_POSIX + 229) -#define __NR_POSIX_reserved62 (__NR_POSIX + 230) -#define __NR_POSIX_reserved63 (__NR_POSIX + 231) -#define __NR_POSIX_reserved64 (__NR_POSIX + 232) -#define __NR_POSIX_reserved65 (__NR_POSIX + 233) -#define __NR_POSIX_reserved66 (__NR_POSIX + 234) -#define __NR_POSIX_reserved67 (__NR_POSIX + 235) -#define __NR_POSIX_reserved68 (__NR_POSIX + 236) -#define __NR_POSIX_reserved69 (__NR_POSIX + 237) -#define __NR_POSIX_reserved70 (__NR_POSIX + 238) -#define __NR_POSIX_reserved71 (__NR_POSIX + 239) -#define __NR_POSIX_reserved72 (__NR_POSIX + 240) -#define __NR_POSIX_reserved73 (__NR_POSIX + 241) -#define __NR_POSIX_reserved74 (__NR_POSIX + 242) -#define __NR_POSIX_reserved75 (__NR_POSIX + 243) -#define __NR_POSIX_reserved76 (__NR_POSIX + 244) -#define __NR_POSIX_reserved77 (__NR_POSIX + 245) -#define __NR_POSIX_reserved78 (__NR_POSIX + 246) -#define __NR_POSIX_reserved79 (__NR_POSIX + 247) -#define __NR_POSIX_reserved80 (__NR_POSIX + 248) -#define __NR_POSIX_reserved81 (__NR_POSIX + 249) -#define __NR_POSIX_reserved82 (__NR_POSIX + 250) -#define __NR_POSIX_reserved83 (__NR_POSIX + 251) -#define __NR_POSIX_reserved84 (__NR_POSIX + 252) -#define __NR_POSIX_reserved85 (__NR_POSIX + 253) -#define __NR_POSIX_reserved86 (__NR_POSIX + 254) -#define __NR_POSIX_reserved87 (__NR_POSIX + 255) -#define __NR_POSIX_reserved88 (__NR_POSIX + 256) -#define __NR_POSIX_reserved89 (__NR_POSIX + 257) -#define __NR_POSIX_reserved90 (__NR_POSIX + 258) -#define __NR_POSIX_reserved91 (__NR_POSIX + 259) -#define __NR_POSIX_netboot (__NR_POSIX + 260) -#define __NR_POSIX_netunboot (__NR_POSIX + 261) -#define __NR_POSIX_rdump (__NR_POSIX + 262) -#define __NR_POSIX_setsid (__NR_POSIX + 263) -#define __NR_POSIX_getmaxsig (__NR_POSIX + 264) -#define __NR_POSIX_sigpending (__NR_POSIX + 265) -#define __NR_POSIX_sigprocmask (__NR_POSIX + 266) -#define __NR_POSIX_sigsuspend (__NR_POSIX + 267) -#define __NR_POSIX_sigaction (__NR_POSIX + 268) -#define __NR_POSIX_MIPS_reserved1 (__NR_POSIX + 269) -#define __NR_POSIX_MIPS_reserved2 (__NR_POSIX + 270) -#define __NR_POSIX_MIPS_reserved3 (__NR_POSIX + 271) -#define __NR_POSIX_MIPS_reserved4 (__NR_POSIX + 272) -#define __NR_POSIX_MIPS_reserved5 (__NR_POSIX + 273) -#define __NR_POSIX_MIPS_reserved6 (__NR_POSIX + 274) -#define __NR_POSIX_MIPS_reserved7 (__NR_POSIX + 275) -#define __NR_POSIX_MIPS_reserved8 (__NR_POSIX + 276) -#define __NR_POSIX_MIPS_reserved9 (__NR_POSIX + 277) -#define __NR_POSIX_MIPS_reserved10 (__NR_POSIX + 278) -#define __NR_POSIX_MIPS_reserved11 (__NR_POSIX + 279) -#define __NR_POSIX_TANDEM_reserved1 (__NR_POSIX + 280) -#define __NR_POSIX_TANDEM_reserved2 (__NR_POSIX + 281) -#define __NR_POSIX_TANDEM_reserved3 (__NR_POSIX + 282) -#define __NR_POSIX_TANDEM_reserved4 (__NR_POSIX + 283) -#define __NR_POSIX_TANDEM_reserved5 (__NR_POSIX + 284) -#define __NR_POSIX_TANDEM_reserved6 (__NR_POSIX + 285) -#define __NR_POSIX_TANDEM_reserved7 (__NR_POSIX + 286) -#define __NR_POSIX_TANDEM_reserved8 (__NR_POSIX + 287) -#define __NR_POSIX_TANDEM_reserved9 (__NR_POSIX + 288) -#define __NR_POSIX_TANDEM_reserved10 (__NR_POSIX + 289) -#define __NR_POSIX_TANDEM_reserved11 (__NR_POSIX + 290) -#define __NR_POSIX_TANDEM_reserved12 (__NR_POSIX + 291) -#define __NR_POSIX_TANDEM_reserved13 (__NR_POSIX + 292) -#define __NR_POSIX_TANDEM_reserved14 (__NR_POSIX + 293) -#define __NR_POSIX_TANDEM_reserved15 (__NR_POSIX + 294) -#define __NR_POSIX_TANDEM_reserved16 (__NR_POSIX + 295) -#define __NR_POSIX_TANDEM_reserved17 (__NR_POSIX + 296) -#define __NR_POSIX_TANDEM_reserved18 (__NR_POSIX + 297) -#define __NR_POSIX_TANDEM_reserved19 (__NR_POSIX + 298) -#define __NR_POSIX_TANDEM_reserved20 (__NR_POSIX + 299) -#define __NR_POSIX_SGI_reserved7 (__NR_POSIX + 300) -#define __NR_POSIX_SGI_reserved8 (__NR_POSIX + 301) -#define __NR_POSIX_SGI_reserved9 (__NR_POSIX + 302) -#define __NR_POSIX_SGI_reserved10 (__NR_POSIX + 303) -#define __NR_POSIX_SGI_reserved11 (__NR_POSIX + 304) -#define __NR_POSIX_SGI_reserved12 (__NR_POSIX + 305) -#define __NR_POSIX_SGI_reserved13 (__NR_POSIX + 306) -#define __NR_POSIX_SGI_reserved14 (__NR_POSIX + 307) -#define __NR_POSIX_SGI_reserved15 (__NR_POSIX + 308) -#define __NR_POSIX_SGI_reserved16 (__NR_POSIX + 309) -#define __NR_POSIX_SGI_reserved17 (__NR_POSIX + 310) -#define __NR_POSIX_SGI_reserved18 (__NR_POSIX + 311) -#define __NR_POSIX_SGI_reserved19 (__NR_POSIX + 312) -#define __NR_POSIX_SGI_reserved20 (__NR_POSIX + 313) -#define __NR_POSIX_SGI_reserved21 (__NR_POSIX + 314) -#define __NR_POSIX_SGI_reserved22 (__NR_POSIX + 315) -#define __NR_POSIX_SGI_reserved23 (__NR_POSIX + 316) -#define __NR_POSIX_SGI_reserved24 (__NR_POSIX + 317) -#define __NR_POSIX_SGI_reserved25 (__NR_POSIX + 318) -#define __NR_POSIX_SGI_reserved26 (__NR_POSIX + 319) - -#endif /* _ASM_RISCOS_SYSCALL_H */ -- From colin@realtek.com.tw Tue Jun 21 07:56:15 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 07:56:34 +0100 (BST) Received: from mf2.realtek.com.tw ([IPv6:::ffff:220.128.56.22]:60425 "EHLO mf2.realtek.com.tw") by linux-mips.org with ESMTP id ; Tue, 21 Jun 2005 07:56:15 +0100 Received: from msx.realtek.com.tw (unverified [172.21.1.77]) by mf2.realtek.com.tw (Content Technologies SMTPRS 4.3.14) with ESMTP id for ; Tue, 21 Jun 2005 14:58:06 +0800 Received: from rtpdii3098 ([172.21.98.16]) by msx.realtek.com.tw (Lotus Domino Release 6.5.1) with ESMTP id 2005062114583166-5074 ; Tue, 21 Jun 2005 14:58:31 +0800 Message-ID: <006201c5762e$4d7f2ac0$106215ac@realtek.com.tw> From: "colin" To: Subject: The most stable version of 2.6 Date: Tue, 21 Jun 2005 14:56:09 +0800 MIME-Version: 1.0 X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1478 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1478 X-MIMETrack: Itemize by SMTP Server on msx/Realtek(Release 6.5.1|January 28, 2004) at 2005/06/21 =?Bog5?B?pFWkyCAwMjo1ODozMQ==?=, Serialize by Router on msx/Realtek(Release 6.5.1|January 28, 2004) at 2005/06/21 =?Bog5?B?pFWkyCAwMjo1ODozMw==?=, Serialize complete at 2005/06/21 =?Bog5?B?pFWkyCAwMjo1ODozMw==?= Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="big5" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8115 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: colin@realtek.com.tw Precedence: bulk X-list: linux-mips Hi there, We want to run linux on our mips board. Stability is an important issue. For so many linux kernel versions, which one is good for us to work on? What's the difference between 2.6.11 & 2.6.12? Regards, Colin From francis_moreau2000@yahoo.fr Tue Jun 21 10:14:36 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 10:15:00 +0100 (BST) Received: from web25806.mail.ukl.yahoo.com ([IPv6:::ffff:217.12.10.191]:60004 "HELO web25806.mail.ukl.yahoo.com") by linux-mips.org with SMTP id ; Tue, 21 Jun 2005 10:14:36 +0100 Received: (qmail 55714 invoked by uid 60001); 21 Jun 2005 09:14:29 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.fr; h=Message-ID:Received:Date:From:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding; b=yibFwH+p+xnej1oYGpDT1Vek2vpRIU3Ofcsy5hd3AYwZiPn81DRdiyICyNI1ajEFNACXtZLvEH/TyIy9HQmxVAIv3hMFl8YjnchpeYdHcb8WyhPZSTqZyPZZG/FVBoIPqR24ozQLbWf3qSADvb7yUuVsR1+EJeae+QBC63C2iZo= ; Message-ID: <20050621091429.55712.qmail@web25806.mail.ukl.yahoo.com> Received: from [217.167.142.149] by web25806.mail.ukl.yahoo.com via HTTP; Tue, 21 Jun 2005 11:14:28 CEST Date: Tue, 21 Jun 2005 11:14:28 +0200 (CEST) From: moreau francis Subject: Using a hal lib in Linux. To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8116 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: francis_moreau2000@yahoo.fr Precedence: bulk X-list: linux-mips Hi all, I've got a mips board provided with a library that deals with hardware management. This library have been compiled with "sde-lite" gcc. I'm thinking of using this lib into my linux drivers to speed up developement process. Has anyone made kernel modifications (specially in Makefiles) in order to link such hal lib into kernel code ? Thanks Francis ___________________________________________________________________________ Appel audio GRATUIT partout dans le monde avec le nouveau Yahoo! Messenger Téléchargez cette version sur http://fr.messenger.yahoo.com From sjhill@realitydiluted.com Tue Jun 21 11:57:52 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 11:58:16 +0100 (BST) Received: from eth13.com-link.com ([IPv6:::ffff:208.242.241.164]:36038 "EHLO real.realitydiluted.com") by linux-mips.org with ESMTP id ; Tue, 21 Jun 2005 11:57:52 +0100 Received: from localhost ([127.0.0.1]) by real.realitydiluted.com with esmtp (Exim 4.50 #1 (Debian)) id 1DkfW5-0005dd-CU; Tue, 21 Jun 2005 04:58:01 -0500 Message-ID: <42B7F2AB.7030805@realitydiluted.com> Date: Tue, 21 Jun 2005 05:57:47 -0500 From: "Steven J. Hill" User-Agent: Debian Thunderbird 1.0.2 (X11/20050602) X-Accept-Language: en-us, en MIME-Version: 1.0 To: colin@realtek.com.tw, linux-mips@linux-mips.org Subject: Re: The most stable version of 2.6 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8117 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sjhill@realitydiluted.com Precedence: bulk X-list: linux-mips It would help if you could tell us which type of processor and board you are using. -Steve From jbglaw@lug-owl.de Tue Jun 21 12:07:31 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 12:07:48 +0100 (BST) Received: from lug-owl.de ([IPv6:::ffff:195.71.106.12]:15794 "EHLO lug-owl.de") by linux-mips.org with ESMTP id ; Tue, 21 Jun 2005 12:07:31 +0100 Received: by lug-owl.de (Postfix, from userid 1001) id 7E3E5F002E; Tue, 21 Jun 2005 13:07:29 +0200 (CEST) Date: Tue, 21 Jun 2005 13:07:29 +0200 From: Jan-Benedict Glaw To: linux-mips@linux-mips.org Subject: Re: Using a hal lib in Linux. Message-ID: <20050621110729.GP4498@lug-owl.de> Mail-Followup-To: linux-mips@linux-mips.org References: <20050621091429.55712.qmail@web25806.mail.ukl.yahoo.com> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="xexMVKTdXPhpRiVT" Content-Disposition: inline In-Reply-To: <20050621091429.55712.qmail@web25806.mail.ukl.yahoo.com> X-Operating-System: Linux mail 2.6.11.10lug-owl X-gpg-fingerprint: 250D 3BCF 7127 0D8C A444 A961 1DBD 5E75 8399 E1BB X-gpg-key: wwwkeys.de.pgp.net X-Echelon-Enable: howto poison arsenous mail psychological biological nuclear warfare test the bombastical terror of flooding the spy listeners explosion sex drugs and rock'n'roll X-TKUeV: howto poison arsenous mail psychological biological nuclear warfare test the bombastical terror of flooding the spy listeners explosion sex drugs and rock'n'roll User-Agent: Mutt/1.5.9i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8118 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jbglaw@lug-owl.de Precedence: bulk X-list: linux-mips --xexMVKTdXPhpRiVT Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, 2005-06-21 11:14:28 +0200, moreau francis wrote: > I've got a mips board provided with a library that deals with hardware > management. > This library have been compiled with "sde-lite" gcc. I'm thinking of usin= g this > lib into my linux drivers to speed up developement process. Has anyone ma= de > kernel > modifications (specially in Makefiles) in order to link such hal lib into > kernel > code ? Well, usually consensus is to avoid HAL layers or libraries at about any price because they typically add speed penalties and binary-only code, which are both unacceptable. MfG, JBG --=20 Jan-Benedict Glaw jbglaw@lug-owl.de . +49-172-7608481 = _ O _ "Eine Freie Meinung in einem Freien Kopf | Gegen Zensur | Gegen Krieg = _ _ O fuer einen Freien Staat voll Freier B=C3=BCrger" | im Internet! | im Ira= k! O O O ret =3D do_actions((curr | FREE_SPEECH) & ~(NEW_COPYRIGHT_LAW | DRM | TCPA)= ); --xexMVKTdXPhpRiVT Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.1 (GNU/Linux) iD8DBQFCt/TxHb1edYOZ4bsRAvSrAJ4jVk/hGx9B7wOQipk6ecg6BfcFRwCfdHLJ Rn1xZ8OD8THaaDgjsmtqNwQ= =7Oa3 -----END PGP SIGNATURE----- --xexMVKTdXPhpRiVT-- From colin@realtek.com.tw Tue Jun 21 12:48:26 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 12:48:59 +0100 (BST) Received: from mf2.realtek.com.tw ([IPv6:::ffff:220.128.56.22]:47368 "EHLO mf2.realtek.com.tw") by linux-mips.org with ESMTP id ; Tue, 21 Jun 2005 12:48:25 +0100 Received: from msx.realtek.com.tw (unverified [172.21.1.77]) by mf2.realtek.com.tw (Clearswift SMTPRS 5.1.4) with ESMTP id ; Tue, 21 Jun 2005 19:50:16 +0800 Received: from rtpdii3098 ([172.21.98.16]) by msx.realtek.com.tw (Lotus Domino Release 6.5.1) with ESMTP id 2005062119504287-8526 ; Tue, 21 Jun 2005 19:50:42 +0800 Message-ID: <002401c57657$1eecb9b0$106215ac@realtek.com.tw> From: "colin" To: "Steven J. Hill" , References: <42B7F2AB.7030805@realitydiluted.com> Subject: Re: The most stable version of 2.6 Date: Tue, 21 Jun 2005 19:48:20 +0800 MIME-Version: 1.0 X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1478 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1478 X-MIMETrack: Itemize by SMTP Server on msx/Realtek(Release 6.5.1|January 28, 2004) at 2005/06/21 =?Bog5?B?pFWkyCAwNzo1MDo0Mw==?=, Serialize by Router on msx/Realtek(Release 6.5.1|January 28, 2004) at 2005/06/21 =?Bog5?B?pFWkyCAwNzo1MDo0NA==?=, Serialize complete at 2005/06/21 =?Bog5?B?pFWkyCAwNzo1MDo0NA==?= Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="iso-8859-1" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8119 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: colin@realtek.com.tw Precedence: bulk X-list: linux-mips Hi Steve, We are using our own SOC with 4ke core. This will be a commercial product, and it must be very stable... :-) Regards, Colin ----- Original Message ----- From: "Steven J. Hill" To: ; Sent: Tuesday, June 21, 2005 6:57 PM Subject: Re: The most stable version of 2.6 > It would help if you could tell us which type of processor and > board you are using. > > -Steve From francis_moreau2000@yahoo.fr Tue Jun 21 13:17:52 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 13:18:22 +0100 (BST) Received: from web25801.mail.ukl.yahoo.com ([IPv6:::ffff:217.12.10.186]:42585 "HELO web25801.mail.ukl.yahoo.com") by linux-mips.org with SMTP id ; Tue, 21 Jun 2005 13:17:52 +0100 Received: (qmail 13644 invoked by uid 60001); 21 Jun 2005 12:17:44 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.fr; h=Message-ID:Received:Date:From:Subject:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding; b=Bi+kktNfYbNDyRytf9kD9wELZgGu0iBl1jp1OoigQO+sW0FHYkzo1PO/88QQ2H/g1alnjhXJETA8Sh9q0eN8pAppUs9/2y/jJzDSQEhv5IGaxsDmi/oluRmZK4YrTZ3IlCOGofGf0PnVITUdgXFM1LbRfF/5wfsQGrgWFQhLapU= ; Message-ID: <20050621121744.13642.qmail@web25801.mail.ukl.yahoo.com> Received: from [217.167.142.149] by web25801.mail.ukl.yahoo.com via HTTP; Tue, 21 Jun 2005 14:17:44 CEST Date: Tue, 21 Jun 2005 14:17:44 +0200 (CEST) From: moreau francis Subject: Re: Using a hal lib in Linux. To: jbglaw@lug-owl.de Cc: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8120 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: francis_moreau2000@yahoo.fr Precedence: bulk X-list: linux-mips Jan-Benedict Glaw wrote: >On Tue, 2005-06-21 11:14:28 +0200, moreau francis wrote: > >>I've got a mips board provided with a library that deals with hardware >>management. >>This library have been compiled with "sde-lite" gcc. I'm thinking of using this >>lib into my linux drivers to speed up developement process. Has anyone made >>kernel >>modifications (specially in Makefiles) in order to link such hal lib into >>kernel >>code ? > > >Well, usually consensus is to avoid HAL layers or libraries at about any >price because they typically add speed penalties and binary-only code, >which are both unacceptable. > Totally agree with you ! But I was wondering if it was possible for a first implementation. I will try to rewrite drivers to avoid HAL layers once everything will be set up. I'm just trying to get something working very quickly, and the hardware seems to be a very unusual one...but once again I totally agree with you. Cheers, Francis ___________________________________________________________________________ Appel audio GRATUIT partout dans le monde avec le nouveau Yahoo! Messenger Téléchargez cette version sur http://fr.messenger.yahoo.com From ladis@linux-mips.org Tue Jun 21 15:10:10 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 15:10:28 +0100 (BST) Received: from smtp.seznam.cz ([IPv6:::ffff:212.80.76.43]:21656 "HELO smtp.seznam.cz") by linux-mips.org with SMTP id ; Tue, 21 Jun 2005 15:10:09 +0100 Received: (qmail 8222 invoked from network); 21 Jun 2005 14:10:02 -0000 Received: from unknown (HELO orphique) (Ladislav.Michl@62.77.73.201) by smtp.seznam.cz with SMTP; 21 Jun 2005 14:10:02 -0000 Received: from ladis by orphique with local (Exim 3.36 #1 (Debian)) id 1DkjRz-0003Me-00; Tue, 21 Jun 2005 16:10:03 +0200 Date: Tue, 21 Jun 2005 16:10:03 +0200 To: colin Cc: "Steven J. Hill" , linux-mips@linux-mips.org Subject: Re: The most stable version of 2.6 Message-ID: <20050621141003.GA12750@orphique> References: <42B7F2AB.7030805@realitydiluted.com> <002401c57657$1eecb9b0$106215ac@realtek.com.tw> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <002401c57657$1eecb9b0$106215ac@realtek.com.tw> User-Agent: Mutt/1.5.9i From: Ladislav Michl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8121 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ladis@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 21, 2005 at 07:48:20PM +0800, colin wrote: > > Hi Steve, > We are using our own SOC with 4ke core. > > This will be a commercial product, and it must be very stable... :-) In that case you probably want to start with 2.6.12 linux-mips.org CVS. And because you are using your own SOC noone will help you when you experience any instability not reproducible elsewhere. Regards, ladis From sskowron@ET.PUT.Poznan.PL Tue Jun 21 17:03:59 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 17:04:15 +0100 (BST) Received: from athena.et.put.poznan.pl ([IPv6:::ffff:150.254.29.137]:7859 "EHLO athena.et.put.poznan.pl") by linux-mips.org with ESMTP id ; Tue, 21 Jun 2005 17:03:59 +0100 Received: from athena (athena.et.put.poznan.pl [150.254.29.137]) by athena.et.put.poznan.pl (8.11.6+Sun/8.11.6) with ESMTP id j5LG3u922002; Tue, 21 Jun 2005 18:03:56 +0200 (MET DST) Received: from helios.et.put.poznan.pl ([150.254.29.65]) by athena.et.put.poznan.pl (MailMonitor for SMTP v1.2.2 ) ; Tue, 21 Jun 2005 18:03:55 +0200 (MET DST) Received: from localhost (sskowron@localhost) by helios.et.put.poznan.pl (8.11.6+Sun/8.11.6) with ESMTP id j5LG3s623729; Tue, 21 Jun 2005 18:03:55 +0200 (MET DST) X-Authentication-Warning: helios.et.put.poznan.pl: sskowron owned process doing -bs Date: Tue, 21 Jun 2005 18:03:54 +0200 (MET DST) From: Stanislaw Skowronek To: Ladislav Michl cc: colin , "Steven J. Hill" , linux-mips@linux-mips.org Subject: Re: The most stable version of 2.6 In-Reply-To: <20050621141003.GA12750@orphique> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8122 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sskowron@ET.PUT.Poznan.PL Precedence: bulk X-list: linux-mips > In that case you probably want to start with 2.6.12 linux-mips.org CVS. > And because you are using your own SOC noone will help you when you > experience any instability not reproducible elsewhere. Unless you send free samples. Yeah. Stanislaw From maxim.osipov@gmail.com Tue Jun 21 18:49:03 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 18:49:18 +0100 (BST) Received: from zproxy.gmail.com ([IPv6:::ffff:64.233.162.202]:10527 "EHLO zproxy.gmail.com") by linux-mips.org with ESMTP id convert rfc822-to-8bit; Tue, 21 Jun 2005 18:49:03 +0100 Received: by zproxy.gmail.com with SMTP id 13so21627nzp for ; Tue, 21 Jun 2005 10:48:55 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:reply-to:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=tZAmUPyH9k8eJkj/WujoW6b5dGENY6EmWWJUxfadlp+VFsoXAoKsRLvD55EMz/dw4jazxTakFV0M5s9ysfXVVpxQuSAXCUS45QgOzKXbg6v7ODImFZFmM41wkeRbnYY6iHmeDBGy1hZ1YhMcBgEFare+P9If03+cm4JKKoTsGJM= Received: by 10.36.222.3 with SMTP id u3mr3120254nzg; Tue, 21 Jun 2005 10:48:55 -0700 (PDT) Received: by 10.36.68.6 with HTTP; Tue, 21 Jun 2005 10:48:55 -0700 (PDT) Message-ID: <6097c4905062110482288b0a8@mail.gmail.com> Date: Tue, 21 Jun 2005 21:48:55 +0400 From: Maxim Osipov Reply-To: maxim@mox.ru To: linux-mips@linux-mips.org Subject: strace n64 support Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8123 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maxim.osipov@gmail.com Precedence: bulk X-list: linux-mips Hello, I was looking at strace-4.5.12 and noticed, that linux/mips/syscallent.h has syscall numbers only for o32. Are n32 and n64 supported? Google doesn't help ;( Maxim From ralf@linux-mips.org Tue Jun 21 18:59:43 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 19:00:04 +0100 (BST) Received: from extgw-uk.mips.com ([IPv6:::ffff:62.254.210.129]:24332 "EHLO bacchus.net.dhis.org") by linux-mips.org with ESMTP id ; Tue, 21 Jun 2005 18:59:43 +0100 Received: from dea.linux-mips.net (localhost.localdomain [127.0.0.1]) by bacchus.net.dhis.org (8.13.1/8.13.1) with ESMTP id j5LHxbST024133; Tue, 21 Jun 2005 18:59:37 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.13.1/8.13.1/Submit) id j5LHxaTe024132; Tue, 21 Jun 2005 18:59:36 +0100 Date: Tue, 21 Jun 2005 18:59:36 +0100 From: Ralf Baechle To: maxim@mox.ru Cc: linux-mips@linux-mips.org Subject: Re: strace n64 support Message-ID: <20050621175936.GN6461@linux-mips.org> References: <6097c4905062110482288b0a8@mail.gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6097c4905062110482288b0a8@mail.gmail.com> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8124 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 21, 2005 at 09:48:55PM +0400, Maxim Osipov wrote: > I was looking at strace-4.5.12 and noticed, that > linux/mips/syscallent.h has syscall numbers only for o32. Are n32 and > n64 supported? Google doesn't help ;( Strace is currently somewhat broken anyway. I'm looking into getting it going, so thanks for letting me know. Ralf From rolfliu@gmail.com Tue Jun 21 23:59:13 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 21 Jun 2005 23:59:30 +0100 (BST) Received: from wproxy.gmail.com ([IPv6:::ffff:64.233.184.194]:11716 "EHLO wproxy.gmail.com") by linux-mips.org with ESMTP id convert rfc822-to-8bit; Tue, 21 Jun 2005 23:59:13 +0100 Received: by wproxy.gmail.com with SMTP id 57so3196wri for ; Tue, 21 Jun 2005 15:57:59 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:reply-to:to:subject:mime-version:content-type:content-transfer-encoding:content-disposition; b=sbzyWzfqJnl8SRGwxjALrojGVJIeK2bJ6J3v899E/A2LrTSl5d1ddol/q8mxjmOZNaC4lL/3Zw3Ds6W3tSKztDFQya2m8ziZ09D7g7RNjzTBeBpyNVpfRItujzFFHuSntTGQTTMabgyjUS1fK3ThUk9utSLkTfg8f4QjZy40XUo= Received: by 10.54.76.6 with SMTP id y6mr66545wra; Tue, 21 Jun 2005 15:57:59 -0700 (PDT) Received: by 10.54.71.11 with HTTP; Tue, 21 Jun 2005 15:57:59 -0700 (PDT) Message-ID: <2db32b720506211557673163e2@mail.gmail.com> Date: Tue, 21 Jun 2005 15:57:59 -0700 From: rolf liu Reply-To: rolf liu To: linux-mips@linux-mips.org Subject: Error duing compiling 2.4.29 using SDE for Db1550 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8125 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rolfliu@gmail.com Precedence: bulk X-list: linux-mips The error is: ##pci_fixup.c:80: parse error before `prid' pci_fixup.c:80: `__res' undeclared (first use in this function) pci_fixup.c:80: (Each undeclared identifier is reported only once pci_fixup.c:80: for each function it appears in.) pci_fixup.c: At top level: pci_fixup.c:80: parse error before `)' pci_fixup.c:83: parse error before string constant pci_fixup.c:83: warning: type defaults to `int' in declaration of `printk' pci_fixup.c:83: warning: function declaration isn't a prototype pci_fixup.c:83: warning: data definition has no type or storage class pci_fixup.c:85: parse error before string constant pci_fixup.c:85: warning: type defaults to `int' in declaration of `printk' pci_fixup.c:85: warning: function declaration isn't a prototype pci_fixup.c:85: warning: data definition has no type or storage class pci_fixup.c:134: warning: `fixup_resource' defined but not used make[1]: *** [pci_fixup.o] Error 1 make[1]: Leaving directory `/home/rolf/linux/arch/mips/au1000/common' make: *** [_dir_arch/mips/au1000/common] Error 2 # I can't find where __res is used in pci_fixup.c. Any suggestions? Thanks From Hiroshi_DOYU@montavista.co.jp Wed Jun 22 04:33:45 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Jun 2005 04:34:22 +0100 (BST) Received: from sonicwall.montavista.co.jp ([IPv6:::ffff:202.232.97.131]:45422 "EHLO yuubin.montavista.co.jp") by linux-mips.org with ESMTP id ; Wed, 22 Jun 2005 04:33:45 +0100 Received: from localhost.localdomain (oreo.jp.mvista.com [10.200.16.31]) by yuubin.montavista.co.jp (8.12.5/8.12.5) with SMTP id j5M3WWS5026712; Wed, 22 Jun 2005 12:32:32 +0900 Date: Wed, 22 Jun 2005 12:34:17 +0900 From: Hiroshi DOYU To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mlachwani@mvista.com Subject: [patch 2.6.12 1/1] tx4938: Added the new board support for Toshiba RBHMA4500(TX4938) Message-Id: <20050622123417.25cd543c.Hiroshi_DOYU@montavista.co.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8126 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Hiroshi_DOYU@montavista.co.jp Precedence: bulk X-list: linux-mips Hello, This patch is against 2.6.12 and it works fine. Please review it. Hiroshi DOYU ---- Added the new board support for Toshiba RBHMA4500(TX4938) Signed-off-by: Manish Lachwani Signed-off-by: Hiroshi DOYU ---- arch/mips/Kconfig | 17 arch/mips/Makefile | 7 arch/mips/pci/Makefile | 1 arch/mips/pci/fixup-tx4938.c | 95 ++ arch/mips/pci/ops-tx4938.c | 199 ++++ arch/mips/tx4938/common/Makefile | 10 arch/mips/tx4938/common/irq.c | 447 ++++++++++ arch/mips/tx4938/common/irq_handler.S | 86 ++ arch/mips/tx4938/common/prom.c | 129 +++ arch/mips/tx4938/common/rtc_rx5c348.c | 202 ++++ arch/mips/tx4938/common/setup.c | 97 ++ arch/mips/tx4938/toshiba_rbtx4938/Makefile | 9 arch/mips/tx4938/toshiba_rbtx4938/irq.c | 275 ++++++ arch/mips/tx4938/toshiba_rbtx4938/prom.c | 78 + arch/mips/tx4938/toshiba_rbtx4938/setup.c | 1034 +++++++++++++++++++++++++ arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c | 219 +++++ arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c | 159 +++ drivers/net/ne.c | 15 include/asm-mips/bootinfo.h | 1 include/asm-mips/tx4938/rbtx4938.h | 207 +++++ include/asm-mips/tx4938/spi.h | 74 + include/asm-mips/tx4938/tx4938.h | 706 +++++++++++++++++ include/asm-mips/tx4938/tx4938_mips.h | 54 + 23 files changed, 4121 insertions(+) Index: linux/arch/mips/Kconfig =================================================================== --- linux.orig/arch/mips/Kconfig 2005-06-22 12:18:48.167088512 +0900 +++ linux/arch/mips/Kconfig 2005-06-22 12:25:09.887058256 +0900 @@ -628,6 +628,23 @@ This Toshiba board is based on the TX4927 processor. Say Y here to support this machine type +config TOSHIBA_RBTX4938 + bool "Support for Toshiba RBTX4938 board" + select HAVE_STD_PC_SERIAL_PORT + select DMA_NONCOHERENT + select GENERIC_ISA_DMA + select HAS_TXX9_SERIAL + select HW_HAS_PCI + select I8259 + select ISA + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select TOSHIBA_BOARDS + help + This Toshiba board is based on the TX4938 processor. Say Y here to + support this machine type + endchoice source "arch/mips/ddb5xxx/Kconfig" Index: linux/arch/mips/Makefile =================================================================== --- linux.orig/arch/mips/Makefile 2005-06-22 12:18:48.167088512 +0900 +++ linux/arch/mips/Makefile 2005-06-22 12:25:09.888058104 +0900 @@ -658,6 +658,13 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 +# +# Toshiba RBTX4938 board +# +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/ +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/ +load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000 + cflags-y += -Iinclude/asm-mips/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ Index: linux/arch/mips/pci/Makefile =================================================================== --- linux.orig/arch/mips/pci/Makefile 2005-06-22 12:18:48.167088512 +0900 +++ linux/arch/mips/pci/Makefile 2005-06-22 12:25:09.888058104 +0900 @@ -50,5 +50,6 @@ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o Index: linux/arch/mips/pci/fixup-tx4938.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/pci/fixup-tx4938.c 2005-06-22 12:25:09.888058104 +0900 @@ -0,0 +1,95 @@ +/* + * Toshiba rbtx4938 pci routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include + +#include +#include +#include +#include + +#include + +extern struct pci_controller tx4938_pci_controller[]; + +int pci_get_irq(struct pci_dev *dev, int pin) +{ + int irq = pin; + u8 slot = PCI_SLOT(dev->devfn); + struct pci_controller *controller = (struct pci_controller *)dev->sysdata; + + if (controller == &tx4938_pci_controller[1]) { + /* TX4938 PCIC1 */ + switch (slot) { + case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; + break; + case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; + break; + } + return 0; + } + + /* IRQ rotation */ + irq--; /* 0-3 */ + if (dev->bus->parent == NULL && + (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { + /* PCI CardSlot (IDSEL=A23) */ + /* PCIA => PCIA (IDSEL=A23) */ + irq = (irq + 0 + slot) % 4; + } else { + /* PCI Backplane */ + irq = (irq + 33 - slot) % 4; + } + irq++; /* 1-4 */ + + switch (irq) { + case 1: + irq = RBTX4938_IRQ_IOC_PCIA; + break; + case 2: + irq = RBTX4938_IRQ_IOC_PCIB; + break; + case 3: + irq = RBTX4938_IRQ_IOC_PCIC; + break; + case 4: + irq = RBTX4938_IRQ_IOC_PCID; + break; + } + return irq; +} + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + unsigned char irq = 0; + + irq = pci_get_irq(dev, pin); + + printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", + dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn), irq); + + return irq; +} + +/* + * Do platform specific device initialization at pci_enable_device() time + */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + Index: linux/arch/mips/pci/ops-tx4938.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/pci/ops-tx4938.c 2005-06-22 12:25:09.889057952 +0900 @@ -0,0 +1,199 @@ +/* + * Define the pci_ops for the Toshiba rbtx4938 + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +#include +#include + +/* initialize in setup */ +struct resource pci_io_resource = { + .name = "pci IO space", + .start = 0, + .end = 0, + .flags = IORESOURCE_IO +}; + +/* initialize in setup */ +struct resource pci_mem_resource = { + .name = "pci memory space", + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM +}; + +struct resource tx4938_pcic1_pci_io_resource = { + .name = "PCI1 IO", + .start = 0, + .end = 0, + .flags = IORESOURCE_IO +}; +struct resource tx4938_pcic1_pci_mem_resource = { + .name = "PCI1 mem", + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM +}; + +static int mkaddr(int bus, int dev_fn, int where, int *flagsp) +{ + if (bus > 0) { + /* Type 1 configuration */ + tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; + } else { + if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0)) + return -1; + + /* Type 0 configuration */ + tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | (where & 0xfc); + } + /* clear M_ABORT and Disable M_ABORT Int. */ + tx4938_pcicptr->pcistatus = + (tx4938_pcicptr->pcistatus & 0x0000ffff) | + (PCI_STATUS_REC_MASTER_ABORT << 16); + tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; + + return 0; +} + +static int check_abort(int flags) +{ + int code = PCIBIOS_SUCCESSFUL; + /* wait write cycle completion before checking error status */ + while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB) + ; + if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { + tx4938_pcicptr->pcistatus = + (tx4938_pcicptr-> + pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT + << 16); + tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; + code = PCIBIOS_DEVICE_NOT_FOUND; + } + return code; +} + +static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + int flags, retval, dev, busno, func; + + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* check if the bus is top-level */ + if (bus->parent != NULL) + busno = bus->number; + else { + busno = 0; + } + + if (mkaddr(busno, devfn, where, &flags)) + return -1; + + switch (size) { + case 1: + *val = *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 3) ^ 3)); +#else + (where & 3)); +#endif + break; + case 2: + *val = *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 3) ^ 2)); +#else + (where & 3)); +#endif + break; + case 4: + *val = tx4938_pcicptr->g2pcfgdata; + break; + } + + retval = check_abort(flags); + if (retval == PCIBIOS_DEVICE_NOT_FOUND) + *val = 0xffffffff; + + return retval; +} + +static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + int flags, dev, busno, func; + + busno = bus->number; + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* check if the bus is top-level */ + if (bus->parent != NULL) { + busno = bus->number; + } else { + busno = 0; + } + + if (mkaddr(busno, devfn, where, &flags)) + return -1; + + switch (size) { + case 1: + *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 3) ^ 3)) = val; +#else + (where & 3)) = val; +#endif + break; + case 2: + *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | +#ifdef __BIG_ENDIAN + ((where & 0x3) ^ 0x2)) = val; +#else + (where & 3)) = val; +#endif + break; + case 4: + tx4938_pcicptr->g2pcfgdata = val; + break; + } + + return check_abort(flags); +} + +struct pci_ops tx4938_pci_ops = { + tx4938_pcibios_read_config, + tx4938_pcibios_write_config +}; + +struct pci_controller tx4938_pci_controller[] = { + /* h/w only supports devices 0x00 to 0x14 */ + { + .pci_ops = &tx4938_pci_ops, + .io_resource = &pci_io_resource, + .mem_resource = &pci_mem_resource, + }, + /* h/w only supports devices 0x00 to 0x14 */ + { + .pci_ops = &tx4938_pci_ops, + .io_resource = &tx4938_pcic1_pci_io_resource, + .mem_resource = &tx4938_pcic1_pci_mem_resource, + } +}; Index: linux/arch/mips/tx4938/common/Makefile =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/common/Makefile 2005-06-22 12:25:09.889057952 +0900 @@ -0,0 +1,10 @@ +# +# Makefile for common code for Toshiba TX4927 based systems +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +obj-y += prom.o setup.o irq.o irq_handler.o rtc_rx5c348.o + Index: linux/arch/mips/tx4938/common/irq.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/common/irq.c 2005-06-22 12:25:09.890057800 +0900 @@ -0,0 +1,447 @@ +/* + * linux/arch/mps/tx4938/common/irq.c + * + * Common tx4938 irq handler + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/**********************************************************************************/ +/* Forwad definitions for all pic's */ +/**********************************************************************************/ + +static unsigned int tx4938_irq_cp0_startup(unsigned int irq); +static void tx4938_irq_cp0_shutdown(unsigned int irq); +static void tx4938_irq_cp0_enable(unsigned int irq); +static void tx4938_irq_cp0_disable(unsigned int irq); +static void tx4938_irq_cp0_mask_and_ack(unsigned int irq); +static void tx4938_irq_cp0_end(unsigned int irq); + +static unsigned int tx4938_irq_pic_startup(unsigned int irq); +static void tx4938_irq_pic_shutdown(unsigned int irq); +static void tx4938_irq_pic_enable(unsigned int irq); +static void tx4938_irq_pic_disable(unsigned int irq); +static void tx4938_irq_pic_mask_and_ack(unsigned int irq); +static void tx4938_irq_pic_end(unsigned int irq); + +/**********************************************************************************/ +/* Kernel structs for all pic's */ +/**********************************************************************************/ +DEFINE_SPINLOCK(tx4938_cp0_lock); +DEFINE_SPINLOCK(tx4938_pic_lock); + +#define TX4938_CP0_NAME "TX4938-CP0" +static struct hw_interrupt_type tx4938_irq_cp0_type = { + .typename = TX4938_CP0_NAME, + .startup = tx4938_irq_cp0_startup, + .shutdown = tx4938_irq_cp0_shutdown, + .enable = tx4938_irq_cp0_enable, + .disable = tx4938_irq_cp0_disable, + .ack = tx4938_irq_cp0_mask_and_ack, + .end = tx4938_irq_cp0_end, + .set_affinity = NULL +}; + +#define TX4938_PIC_NAME "TX4938-PIC" +static struct hw_interrupt_type tx4938_irq_pic_type = { + .typename = TX4938_PIC_NAME, + .startup = tx4938_irq_pic_startup, + .shutdown = tx4938_irq_pic_shutdown, + .enable = tx4938_irq_pic_enable, + .disable = tx4938_irq_pic_disable, + .ack = tx4938_irq_pic_mask_and_ack, + .end = tx4938_irq_pic_end, + .set_affinity = NULL +}; + +#define TX4938_PIC_ACTION(s) { no_action, 0, 0, s, NULL, NULL } +static struct irqaction tx4938_irq_pic_action = +TX4938_PIC_ACTION(TX4938_PIC_NAME); + +/**********************************************************************************/ +/* Functions for cp0 */ +/**********************************************************************************/ + +#define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) ) + +static void +tx4938_irq_cp0_cause(unsigned clr_bits, unsigned set_bits) +{ + unsigned long val = read_c0_cause(); + + val &= (~clr_bits); + val |= (set_bits); + + write_c0_cause(val); +} + +static void +tx4938_irq_cp0_status(unsigned clr_bits, unsigned set_bits) +{ + unsigned long val = read_c0_status(); + + val &= (~clr_bits); + val |= (set_bits); + + write_c0_status(val); +} + +static void __init +tx4938_irq_cp0_init(void) +{ + int i; + + for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &tx4938_irq_cp0_type; + } + + return; +} + +static unsigned int +tx4938_irq_cp0_startup(unsigned int irq) +{ + tx4938_irq_cp0_enable(irq); + + return (0); +} + +static void +tx4938_irq_cp0_shutdown(unsigned int irq) +{ + tx4938_irq_cp0_disable(irq); + + return; +} + +static void +tx4938_irq_cp0_enable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_cp0_lock, flags); + + tx4938_irq_cp0_status(0, tx4938_irq_cp0_mask(irq)); + + spin_unlock_irqrestore(&tx4938_cp0_lock, flags); + + return; +} + +static void +tx4938_irq_cp0_disable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_cp0_lock, flags); + + tx4938_irq_cp0_status(tx4938_irq_cp0_mask(irq), 0); + + spin_unlock_irqrestore(&tx4938_cp0_lock, flags); + + return; +} + +static void +tx4938_irq_cp0_mask_and_ack(unsigned int irq) +{ + tx4938_irq_cp0_disable(irq); + + return; +} + +static void +tx4938_irq_cp0_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + tx4938_irq_cp0_enable(irq); + } + + return; +} + +/**********************************************************************************/ +/* Functions for pic */ +/**********************************************************************************/ + +u32 +tx4938_irq_pic_addr(int irq) +{ + /* MVMCP -- need to formulize this */ + irq -= TX4938_IRQ_PIC_BEG; + + switch (irq) { + case 17: + case 16: + case 1: + case 0:{ + return (TX4938_MKA(TX4938_IRC_IRLVL0)); + } + case 19: + case 18: + case 3: + case 2:{ + return (TX4938_MKA(TX4938_IRC_IRLVL1)); + } + case 21: + case 20: + case 5: + case 4:{ + return (TX4938_MKA(TX4938_IRC_IRLVL2)); + } + case 23: + case 22: + case 7: + case 6:{ + return (TX4938_MKA(TX4938_IRC_IRLVL3)); + } + case 25: + case 24: + case 9: + case 8:{ + return (TX4938_MKA(TX4938_IRC_IRLVL4)); + } + case 27: + case 26: + case 11: + case 10:{ + return (TX4938_MKA(TX4938_IRC_IRLVL5)); + } + case 29: + case 28: + case 13: + case 12:{ + return (TX4938_MKA(TX4938_IRC_IRLVL6)); + } + case 31: + case 30: + case 15: + case 14:{ + return (TX4938_MKA(TX4938_IRC_IRLVL7)); + } + } + + return (0); +} + +u32 +tx4938_irq_pic_mask(int irq) +{ + /* MVMCP -- need to formulize this */ + irq -= TX4938_IRQ_PIC_BEG; + + switch (irq) { + case 31: + case 29: + case 27: + case 25: + case 23: + case 21: + case 19: + case 17:{ + return (0x07000000); + } + case 30: + case 28: + case 26: + case 24: + case 22: + case 20: + case 18: + case 16:{ + return (0x00070000); + } + case 15: + case 13: + case 11: + case 9: + case 7: + case 5: + case 3: + case 1:{ + return (0x00000700); + } + case 14: + case 12: + case 10: + case 8: + case 6: + case 4: + case 2: + case 0:{ + return (0x00000007); + } + } + return (0x00000000); +} + +static void +tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits) +{ + unsigned long val = 0; + + val = TX4938_RD(pic_reg); + val &= (~clr_bits); + val |= (set_bits); + TX4938_WR(pic_reg, val); + mmiowb(); + TX4938_RD(pic_reg); + + return; +} + +static void __init +tx4938_irq_pic_init(void) +{ + unsigned long flags; + int i; + + for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 2; + irq_desc[i].handler = &tx4938_irq_pic_type; + } + + setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); + + spin_lock_irqsave(&tx4938_pic_lock, flags); + + TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ + TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */ + + spin_unlock_irqrestore(&tx4938_pic_lock, flags); + + return; +} + +static unsigned int +tx4938_irq_pic_startup(unsigned int irq) +{ + tx4938_irq_pic_enable(irq); + + return (0); +} + +static void +tx4938_irq_pic_shutdown(unsigned int irq) +{ + tx4938_irq_pic_disable(irq); + + return; +} + +static void +tx4938_irq_pic_enable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_pic_lock, flags); + + tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0, + tx4938_irq_pic_mask(irq)); + + spin_unlock_irqrestore(&tx4938_pic_lock, flags); + + return; +} + +static void +tx4938_irq_pic_disable(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&tx4938_pic_lock, flags); + + tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), + tx4938_irq_pic_mask(irq), 0); + + spin_unlock_irqrestore(&tx4938_pic_lock, flags); + + return; +} + +static void +tx4938_irq_pic_mask_and_ack(unsigned int irq) +{ + tx4938_irq_pic_disable(irq); + + return; +} + +static void +tx4938_irq_pic_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + tx4938_irq_pic_enable(irq); + } + + return; +} + +/**********************************************************************************/ +/* Main init functions */ +/**********************************************************************************/ + +void __init +tx4938_irq_init(void) +{ + extern asmlinkage void tx4938_irq_handler(void); + + tx4938_irq_cp0_init(); + tx4938_irq_pic_init(); + set_except_vector(0, tx4938_irq_handler); + + return; +} + +int +tx4938_irq_nested(void) +{ + int sw_irq = 0; + u32 level2; + + level2 = TX4938_RD(0xff1ff6a0); + if ((level2 & 0x10000) == 0) { + level2 &= 0x1f; + sw_irq = TX4938_IRQ_PIC_BEG + level2; + if (sw_irq == 26) { + { + extern int toshiba_rbtx4938_irq_nested(int sw_irq); + sw_irq = toshiba_rbtx4938_irq_nested(sw_irq); + } + } + } + + wbflush(); + return (sw_irq); +} Index: linux/arch/mips/tx4938/common/irq_handler.S =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/common/irq_handler.S 2005-06-22 12:25:09.890057800 +0900 @@ -0,0 +1,86 @@ +/* + * linux/arch/mips/tx4938/common/handler.S + * + * Primary interrupt handler for tx4938 based systems + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include +#include +#include + + + .align 5 + NESTED(tx4938_irq_handler, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 t0, CP0_CAUSE + mfc0 t1, CP0_STATUS + and t0, t1 + + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_ip7 + + /* IP6..IP3 multiplexed -- do not use */ + + andi t1, t0, STATUSF_IP2 /* tx4938 pic */ + bnez t1, ll_ip2 + + andi t1, t0, STATUSF_IP1 /* user line 1 */ + bnez t1, ll_ip1 + + andi t1, t0, STATUSF_IP0 /* user line 0 */ + bnez t1, ll_ip0 + + .set reorder + + nop + END(tx4938_irq_handler) + + .align 5 + + +ll_ip7: + li a0, TX4938_IRQ_CPU_TIMER + move a1, sp + jal do_IRQ + j ret_from_irq + + +ll_ip2: + jal tx4938_irq_nested + nop + beqz v0, goto_spurious_interrupt + nop + move a0, v0 + move a1, sp + jal do_IRQ + j ret_from_irq + +goto_spurious_interrupt: + nop + j ret_from_irq + +ll_ip1: + li a0, TX4938_IRQ_USER1 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_ip0: + li a0, TX4938_IRQ_USER0 + move a1, sp + jal do_IRQ + j ret_from_irq Index: linux/arch/mips/tx4938/common/prom.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/common/prom.c 2005-06-22 12:25:09.890057800 +0900 @@ -0,0 +1,129 @@ +/* + * linux/arch/mips/tx4938/common/prom.c + * + * common tx4938 memory interface + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include +#include +#include +#include + +#include +#include +#include + +static unsigned int __init +tx4938_process_sdccr(u64 * addr) +{ + u64 val; + unsigned int sdccr_ce; + unsigned int sdccr_rs; + unsigned int sdccr_cs; + unsigned int sdccr_mw; + unsigned int rs = 0; + unsigned int cs = 0; + unsigned int mw = 0; + unsigned int bc = 4; + unsigned int msize = 0; + + val = (*((vu64 *) (addr))); + + /* MVMCP -- need #defs for these bits masks */ + sdccr_ce = ((val & (1 << 10)) >> 10); + sdccr_rs = ((val & (3 << 5)) >> 5); + sdccr_cs = ((val & (7 << 2)) >> 2); + sdccr_mw = ((val & (1 << 0)) >> 0); + + if (sdccr_ce) { + switch (sdccr_rs) { + case 0:{ + rs = 2048; + break; + } + case 1:{ + rs = 4096; + break; + } + case 2:{ + rs = 8192; + break; + } + default:{ + rs = 0; + break; + } + } + switch (sdccr_cs) { + case 0:{ + cs = 256; + break; + } + case 1:{ + cs = 512; + break; + } + case 2:{ + cs = 1024; + break; + } + case 3:{ + cs = 2048; + break; + } + case 4:{ + cs = 4096; + break; + } + default:{ + cs = 0; + break; + } + } + switch (sdccr_mw) { + case 0:{ + mw = 8; + break; + } /* 8 bytes = 64 bits */ + case 1:{ + mw = 4; + break; + } /* 4 bytes = 32 bits */ + } + } + + /* bytes per chip MB per chip bank count */ + msize = (((rs * cs * mw) / (1024 * 1024)) * (bc)); + + /* MVMCP -- bc hard coded to 4 from table 9.3.1 */ + /* boad supports bc=2 but no way to detect */ + + return (msize); +} + +unsigned int __init +tx4938_get_mem_size(void) +{ + unsigned int c0; + unsigned int c1; + unsigned int c2; + unsigned int c3; + unsigned int total; + + /* MVMCP -- need #defs for these registers */ + c0 = tx4938_process_sdccr((u64 *) 0xff1f8000); + c1 = tx4938_process_sdccr((u64 *) 0xff1f8008); + c2 = tx4938_process_sdccr((u64 *) 0xff1f8010); + c3 = tx4938_process_sdccr((u64 *) 0xff1f8018); + total = c0 + c1 + c2 + c3; + + return (total); +} Index: linux/arch/mips/tx4938/common/rtc_rx5c348.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/common/rtc_rx5c348.c 2005-06-22 12:25:09.891057648 +0900 @@ -0,0 +1,202 @@ +/* + * RTC routines for RICOH Rx5C348 SPI chip. + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include +#include +#include + +#define EPOCH 2000 + +/* registers */ +#define Rx5C348_REG_SECOND 0 +#define Rx5C348_REG_MINUTE 1 +#define Rx5C348_REG_HOUR 2 +#define Rx5C348_REG_WEEK 3 +#define Rx5C348_REG_DAY 4 +#define Rx5C348_REG_MONTH 5 +#define Rx5C348_REG_YEAR 6 +#define Rx5C348_REG_ADJUST 7 +#define Rx5C348_REG_ALARM_W_MIN 8 +#define Rx5C348_REG_ALARM_W_HOUR 9 +#define Rx5C348_REG_ALARM_W_WEEK 10 +#define Rx5C348_REG_ALARM_D_MIN 11 +#define Rx5C348_REG_ALARM_D_HOUR 12 +#define Rx5C348_REG_CTL1 14 +#define Rx5C348_REG_CTL2 15 + +/* register bits */ +#define Rx5C348_BIT_PM 0x20 /* REG_HOUR */ +#define Rx5C348_BIT_Y2K 0x80 /* REG_MONTH */ +#define Rx5C348_BIT_24H 0x20 /* REG_CTL1 */ +#define Rx5C348_BIT_XSTP 0x10 /* REG_CTL2 */ + +/* commands */ +#define Rx5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */ +#define Rx5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */ +#define Rx5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */ +#define Rx5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */ + +static struct spi_dev_desc srtc_dev_desc = { + .baud = 1000000, /* 1.0Mbps @ Vdd 2.0V */ + .tcss = 31, + .tcsh = 1, + .tcsr = 62, + /* 31us for Tcss (62us for Tcsr) is required for carry operation) */ + .byteorder = 1, /* MSB-First */ + .polarity = 0, /* High-Active */ + .phase = 1, /* Shift-Then-Sample */ + +}; +static int srtc_chipid; +static int srtc_24h; + +static inline int +spi_rtc_io(unsigned char *inbuf, unsigned char *outbuf, unsigned int count) +{ + unsigned char *inbufs[1], *outbufs[1]; + unsigned int incounts[2], outcounts[2]; + inbufs[0] = inbuf; + incounts[0] = count; + incounts[1] = 0; + outbufs[0] = outbuf; + outcounts[0] = count; + outcounts[1] = 0; + return txx9_spi_io(srtc_chipid, &srtc_dev_desc, + inbufs, incounts, outbufs, outcounts, 0); +} + +/* + * Conversion between binary and BCD. + */ +#ifndef BCD_TO_BIN +#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) +#endif + +#ifndef BIN_TO_BCD +#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) +#endif + +/* RTC-dependent code for time.c */ + +static int +rtc_rx5c348_set_time(unsigned long t) +{ + unsigned char inbuf[8]; + struct rtc_time tm; + u8 year, month, day, hour, minute, second, century; + + /* convert */ + to_tm(t, &tm); + + year = tm.tm_year % 100; + month = tm.tm_mon+1; /* tm_mon starts from 0 to 11 */ + day = tm.tm_mday; + hour = tm.tm_hour; + minute = tm.tm_min; + second = tm.tm_sec; + century = tm.tm_year / 100; + + inbuf[0] = Rx5C348_CMD_MW(Rx5C348_REG_SECOND); + BIN_TO_BCD(second); + inbuf[1] = second; + BIN_TO_BCD(minute); + inbuf[2] = minute; + + if (srtc_24h) { + BIN_TO_BCD(hour); + inbuf[3] = hour; + } else { + /* hour 0 is AM12, noon is PM12 */ + inbuf[3] = 0; + if (hour >= 12) + inbuf[3] = Rx5C348_BIT_PM; + hour = (hour + 11) % 12 + 1; + BIN_TO_BCD(hour); + inbuf[3] |= hour; + } + inbuf[4] = 0; /* ignore week */ + BIN_TO_BCD(day); + inbuf[5] = day; + BIN_TO_BCD(month); + inbuf[6] = month; + if (century >= 20) + inbuf[6] |= Rx5C348_BIT_Y2K; + BIN_TO_BCD(year); + inbuf[7] = year; + /* write in one transfer to avoid data inconsistency */ + return spi_rtc_io(inbuf, NULL, 8); +} + +static unsigned long +rtc_rx5c348_get_time(void) +{ + unsigned char inbuf[8], outbuf[8]; + unsigned int year, month, day, hour, minute, second; + + inbuf[0] = Rx5C348_CMD_MR(Rx5C348_REG_SECOND); + memset(inbuf + 1, 0, 7); + /* read in one transfer to avoid data inconsistency */ + if (spi_rtc_io(inbuf, outbuf, 8)) + return 0; + second = outbuf[1]; + BCD_TO_BIN(second); + minute = outbuf[2]; + BCD_TO_BIN(minute); + if (srtc_24h) { + hour = outbuf[3]; + BCD_TO_BIN(hour); + } else { + hour = outbuf[3] & ~Rx5C348_BIT_PM; + BCD_TO_BIN(hour); + hour %= 12; + if (outbuf[3] & Rx5C348_BIT_PM) + hour += 12; + } + day = outbuf[5]; + BCD_TO_BIN(day); + month = outbuf[6] & ~Rx5C348_BIT_Y2K; + BCD_TO_BIN(month); + year = outbuf[7]; + BCD_TO_BIN(year); + year += EPOCH; + + return mktime(year, month, day, hour, minute, second); +} + +void __init +rtc_rx5c348_init(int chipid) +{ + unsigned char inbuf[2], outbuf[2]; + srtc_chipid = chipid; + /* turn on RTC if it is not on */ + inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL2); + inbuf[1] = 0; + spi_rtc_io(inbuf, outbuf, 2); + if (outbuf[1] & Rx5C348_BIT_XSTP) { + inbuf[0] = Rx5C348_CMD_W(Rx5C348_REG_CTL2); + inbuf[1] = 0; + spi_rtc_io(inbuf, NULL, 2); + } + + inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL1); + inbuf[1] = 0; + spi_rtc_io(inbuf, outbuf, 2); + if (outbuf[1] & Rx5C348_BIT_24H) + srtc_24h = 1; + + /* set the function pointers */ + rtc_get_time = rtc_rx5c348_get_time; + rtc_set_time = rtc_rx5c348_set_time; +} Index: linux/arch/mips/tx4938/common/setup.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/common/setup.c 2005-06-22 12:25:09.891057648 +0900 @@ -0,0 +1,97 @@ +/* + * linux/arch/mips/tx4938/common/setup.c + * + * common tx4938 setup routines + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void toshiba_rbtx4938_setup(void); +extern void rbtx4938_time_init(void); + +void __init tx4938_setup(void); +void __init tx4938_time_init(void); +void __init tx4938_timer_setup(struct irqaction *irq); +void dump_cp0(char *key); + +void (*__wbflush) (void); + +static void +tx4938_write_buffer_flush(void) +{ + mmiowb(); + + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + "lw $0,%0\n\t" + "nop\n\t" + ".set pop" + : /* no output */ + : "m" (*(int *)KSEG1) + : "memory"); +} + +void __init +plat_setup(void) +{ + board_time_init = tx4938_time_init; + board_timer_setup = tx4938_timer_setup; + __wbflush = tx4938_write_buffer_flush; + toshiba_rbtx4938_setup(); + + return; +} + +void __init +tx4938_time_init(void) +{ + rbtx4938_time_init(); + return; +} + +void __init +tx4938_timer_setup(struct irqaction *irq) +{ + u32 count; + u32 c1; + u32 c2; + + setup_irq(TX4938_IRQ_CPU_TIMER, irq); + + c1 = read_c0_count(); + count = c1 + (mips_hpt_frequency / HZ); + write_c0_compare(count); + c2 = read_c0_count(); + + return; +} + Index: linux/arch/mips/tx4938/toshiba_rbtx4938/Makefile =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/toshiba_rbtx4938/Makefile 2005-06-22 12:25:09.891057648 +0900 @@ -0,0 +1,9 @@ +# +# Makefile for common code for Toshiba TX4927 based systems +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +obj-y += prom.o setup.o irq.o spi_eeprom.o spi_txx9.o Index: linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c 2005-06-22 12:25:09.892057496 +0900 @@ -0,0 +1,275 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c + * + * Toshiba RBTX4938 specific interrupt handlers + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +/* +IRQ Device + +16 TX4938-CP0/00 Software 0 +17 TX4938-CP0/01 Software 1 +18 TX4938-CP0/02 Cascade TX4938-CP0 +19 TX4938-CP0/03 Multiplexed -- do not use +20 TX4938-CP0/04 Multiplexed -- do not use +21 TX4938-CP0/05 Multiplexed -- do not use +22 TX4938-CP0/06 Multiplexed -- do not use +23 TX4938-CP0/07 CPU TIMER + +24 TX4938-PIC/00 +25 TX4938-PIC/01 +26 TX4938-PIC/02 Cascade RBTX4938-IOC +27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet +28 TX4938-PIC/04 +29 TX4938-PIC/05 TX4938 ETH1 +30 TX4938-PIC/06 TX4938 ETH0 +31 TX4938-PIC/07 +32 TX4938-PIC/08 TX4938 SIO 0 +33 TX4938-PIC/09 TX4938 SIO 1 +34 TX4938-PIC/10 TX4938 DMA0 +35 TX4938-PIC/11 TX4938 DMA1 +36 TX4938-PIC/12 TX4938 DMA2 +37 TX4938-PIC/13 TX4938 DMA3 +38 TX4938-PIC/14 +39 TX4938-PIC/15 +40 TX4938-PIC/16 TX4938 PCIC +41 TX4938-PIC/17 TX4938 TMR0 +42 TX4938-PIC/18 TX4938 TMR1 +43 TX4938-PIC/19 TX4938 TMR2 +44 TX4938-PIC/20 +45 TX4938-PIC/21 +46 TX4938-PIC/22 TX4938 PCIERR +47 TX4938-PIC/23 +48 TX4938-PIC/24 +49 TX4938-PIC/25 +50 TX4938-PIC/26 +51 TX4938-PIC/27 +52 TX4938-PIC/28 +53 TX4938-PIC/29 +54 TX4938-PIC/30 +55 TX4938-PIC/31 TX4938 SPI + +56 RBTX4938-IOC/00 PCI-D +57 RBTX4938-IOC/01 PCI-C +58 RBTX4938-IOC/02 PCI-B +59 RBTX4938-IOC/03 PCI-A +60 RBTX4938-IOC/04 RTC +61 RBTX4938-IOC/05 ATA +62 RBTX4938-IOC/06 MODEM +63 RBTX4938-IOC/07 SWINT +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq); + +DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock); + +#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" +static struct hw_interrupt_type toshiba_rbtx4938_irq_ioc_type = { + .typename = TOSHIBA_RBTX4938_IOC_NAME, + .startup = toshiba_rbtx4938_irq_ioc_startup, + .shutdown = toshiba_rbtx4938_irq_ioc_shutdown, + .enable = toshiba_rbtx4938_irq_ioc_enable, + .disable = toshiba_rbtx4938_irq_ioc_disable, + .ack = toshiba_rbtx4938_irq_ioc_mask_and_ack, + .end = toshiba_rbtx4938_irq_ioc_end, + .set_affinity = NULL +}; + +#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000 +#define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a + +u8 +last_bit2num(u8 num) +{ + u8 i = ((sizeof(num)*8)-1); + + do + { + if ( num & (1<pcfg & TX4938_PCFG_SPI_SEL) { + txx9_spi_irqinit(RBTX4938_IRQ_IRC_SPI); + } + + wbflush(); + return; +} Index: linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c 2005-06-22 12:25:09.892057496 +0900 @@ -0,0 +1,78 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c + * + * rbtx4938 specific prom routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +void __init prom_init_cmdline(void) +{ + int argc = (int) fw_arg0; + char **argv = (char **) fw_arg1; + int i; + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) { + *arcs_cmdline = '\0'; + } + + for (i = 1; i < argc; i++) { + if (i != 1) { + strcat(arcs_cmdline, " "); + } + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + extern int tx4938_get_mem_size(void); + int msize; + + prom_init_cmdline(); + + mips_machgroup = MACH_GROUP_TOSHIBA; + mips_machtype = MACH_TOSHIBA_RBTX4938; + + msize = tx4938_get_mem_size(); + add_memory_region(0, msize << 20, BOOT_MEM_RAM); + + return; +} + +unsigned long __init prom_free_prom_memory(void) +{ + return 0; +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ + return; +} + +const char *get_system_type(void) +{ + return "Toshiba RBTX4938"; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} Index: linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c 2005-06-22 12:25:09.894057192 +0900 @@ -0,0 +1,1034 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c + * + * Setup pointers to hardware-dependent routines. + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#include +#include +#endif + +extern void rbtx4938_time_init(void) __init; +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); + +/* These functions are used for rebooting or halting the machine*/ +extern void rbtx4938_machine_restart(char *command); +extern void rbtx4938_machine_halt(void); +extern void rbtx4938_machine_power_off(void); + +/* clocks */ +unsigned int txx9_master_clock; +unsigned int txx9_cpu_clock; +unsigned int txx9_gbus_clock; + +unsigned long rbtx4938_ce_base[8]; +unsigned long rbtx4938_ce_size[8]; +int txboard_pci66_mode = 0; +static int tx4938_ccfg_toeon = 1; +static int tx4938_pcic_trdyto = 0; /* default: disabled */ +static int tx4938_pcic_retryto = 0; /* default: disabled */ + +struct tx4938_pcic_reg *pcicptrs[4] = { + tx4938_pcicptr /* default setting for TX4938 */ +}; + +static struct { + unsigned long base; + unsigned long size; +} phys_regions[16] __initdata; +static int num_phys_regions __initdata; + +#define PHYS_REGION_MINSIZE 0x10000 + +void rbtx4938_machine_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void rbtx4938_machine_power_off(void) +{ + rbtx4938_machine_halt(); + /* no return */ +} + +void rbtx4938_machine_restart(char *command) +{ + local_irq_disable(); + + printk("Rebooting..."); + *rbtx4938_softresetlock_ptr = 1; + *rbtx4938_sfvol_ptr = 1; + *rbtx4938_softreset_ptr = 1; + wbflush(); + + while(1); +} + +void __init +txboard_add_phys_region(unsigned long base, unsigned long size) +{ + if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { + printk("phys_region overflow\n"); + return; + } + phys_regions[num_phys_regions].base = base; + phys_regions[num_phys_regions].size = size; + num_phys_regions++; +} +unsigned long __init +txboard_find_free_phys_region(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + int i; + + for (base = begin / size * size; base < end; base += size) { + for (i = 0; i < num_phys_regions; i++) { + if (phys_regions[i].size && + base <= phys_regions[i].base + (phys_regions[i].size - 1) && + base + (size - 1) >= phys_regions[i].base) + break; + } + if (i == num_phys_regions) + return base; + } + return 0; +} +unsigned long __init +txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, + unsigned long *size) +{ + unsigned long sz, base; + for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { + base = txboard_find_free_phys_region(begin, end, sz); + if (base) { + *size = sz; + return base; + } + } + return 0; +} +unsigned long __init +txboard_request_phys_region_range(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region(unsigned long size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region_shrink(unsigned long *size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region_shrink(begin, end, size); + if (base) + txboard_add_phys_region(base, *size); + return base; +} + +#ifdef CONFIG_PCI +void __init +tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, + struct pci_controller *channel, + unsigned long pci_io_base, + int extarb) +{ + int i; + + /* Disable All Initiator Space */ + pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| + TX4938_PCIC_PCICCFG_G2PMEN(1)| + TX4938_PCIC_PCICCFG_G2PMEN(2)| + TX4938_PCIC_PCICCFG_G2PIOEN); + + /* GB->PCI mappings */ + pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; + pcicptr->g2piogbase = pci_io_base | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PIOGBASE_ECHG +#else + TX4938_PCIC_G2PIOGBASE_BSDIS +#endif + ; + pcicptr->g2piopbase = 0; + for (i = 0; i < 3; i++) { + pcicptr->g2pmmask[i] = 0; + pcicptr->g2pmgbase[i] = 0; + pcicptr->g2pmpbase[i] = 0; + } + if (channel->mem_resource->end) { + pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; + pcicptr->g2pmgbase[0] = channel->mem_resource->start | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PMnGBASE_ECHG +#else + TX4938_PCIC_G2PMnGBASE_BSDIS +#endif + ; + pcicptr->g2pmpbase[0] = channel->mem_resource->start; + } + /* PCI->GB mappings (I/O 256B) */ + pcicptr->p2giopbase = 0; /* 256B */ + pcicptr->p2giogbase = 0; + /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ + pcicptr->p2gm0plbase = 0; + pcicptr->p2gm0pubase = 0; + pcicptr->p2gmgbase[0] = 0 | + TX4938_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4938_PCIC_P2GMnGBASE_TECHG +#else + TX4938_PCIC_P2GMnGBASE_TBSDIS +#endif + ; + /* PCI->GB mappings (MEM 16MB) */ + pcicptr->p2gm1plbase = 0xffffffff; + pcicptr->p2gm1pubase = 0xffffffff; + pcicptr->p2gmgbase[1] = 0; + /* PCI->GB mappings (MEM 1MB) */ + pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ + pcicptr->p2gmgbase[2] = 0; + + pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; + /* Enable Initiator Memory Space */ + if (channel->mem_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); + /* Enable Initiator I/O Space */ + if (channel->io_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; + /* Enable Initiator Config */ + pcicptr->pciccfg |= + TX4938_PCIC_PCICCFG_ICAEN | + TX4938_PCIC_PCICCFG_TCAR; + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + pcicptr->pcicfg1 = 0; + + pcicptr->g2ptocnt &= ~0xffff; + + if (tx4938_pcic_trdyto >= 0) { + pcicptr->g2ptocnt &= ~0xff; + pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); + } + + if (tx4938_pcic_retryto >= 0) { + pcicptr->g2ptocnt &= ~0xff00; + pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); + } + + /* Clear All Local Bus Status */ + pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; + /* Enable All Local Bus Interrupts */ + pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; + /* Clear All Initiator Status */ + pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; + /* Enable All Initiator Interrupts */ + pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; + /* Clear All PCI Status Error */ + pcicptr->pcistatus = + (pcicptr->pcistatus & 0x0000ffff) | + (TX4938_PCIC_PCISTATUS_ALL << 16); + /* Enable All PCI Status Error Interrupts */ + pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; + + if (!extarb) { + /* Reset Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; + pcicptr->pbabm = 0; + /* Enable Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; + } + + /* PCIC Int => IRC IRQ16 */ + pcicptr->pcicfg2 = + (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; + + pcicptr->pcistatus = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; +} + +int __init +tx4938_report_pciclk(void) +{ + unsigned long pcode = TX4938_REV_PCODE(); + int pciclk = 0; + printk("TX%lx PCIC --%s PCICLK:", + pcode, + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + + switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_4: + pciclk = txx9_cpu_clock / 4; break; + case TX4938_CCFG_PCIDIVMODE_4_5: + pciclk = txx9_cpu_clock * 2 / 9; break; + case TX4938_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4938_CCFG_PCIDIVMODE_5_5: + pciclk = txx9_cpu_clock * 2 / 11; break; + case TX4938_CCFG_PCIDIVMODE_8: + pciclk = txx9_cpu_clock / 8; break; + case TX4938_CCFG_PCIDIVMODE_9: + pciclk = txx9_cpu_clock / 9; break; + case TX4938_CCFG_PCIDIVMODE_10: + pciclk = txx9_cpu_clock / 10; break; + case TX4938_CCFG_PCIDIVMODE_11: + pciclk = txx9_cpu_clock / 11; break; + } + printk("Internal(%dMHz)", pciclk / 1000000); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) +{ + pcicptrs[ch] = pcicptr; +} + +struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) +{ + return pcicptrs[ch]; +} + +static struct pci_dev *fake_pci_dev(struct pci_controller *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.sysdata = (void *)hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + bus.parent = NULL; + dev.bus = &bus; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +static int early_##rw##_config_##size(struct pci_controller *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, word, u16 *) + +int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) +{ + u32 pci_devfn; + unsigned short vid; + int devfn_start = 0; + int devfn_stop = 0xff; + int cap66 = -1; + u16 stat; + + printk("PCI: Checking 66MHz capabilities...\n"); + + for (pci_devfn=devfn_start; pci_devfn 0; +} + +int __init +tx4938_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; + /* Double PCICLK (if possible) */ + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = 0; + switch (pcidivmode) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4; + pciclk = txx9_cpu_clock / 4; + break; + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; + pciclk = txx9_cpu_clock * 2 / 9; + break; + case TX4938_CCFG_PCIDIVMODE_10: + case TX4938_CCFG_PCIDIVMODE_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5; + pciclk = txx9_cpu_clock / 5; + break; + case TX4938_CCFG_PCIDIVMODE_11: + case TX4938_CCFG_PCIDIVMODE_5_5: + default: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; + pciclk = txx9_cpu_clock * 2 / 11; + break; + } + tx4938_ccfgptr->ccfg = + (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) + | pcidivmode; + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)tx4938_ccfgptr->ccfg); + } else { + pciclk = -1; + } + return pciclk; +} + +extern struct pci_controller tx4938_pci_controller[]; +static int __init tx4938_pcibios_init(void) +{ + unsigned long mem_base[2]; + unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ + unsigned long io_base[2]; + unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ + /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ + int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); + + PCIBIOS_MIN_IO = 0x00001000UL; + PCIBIOS_MIN_MEM = 0x01000000UL; + + mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); + io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); + + printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + (unsigned short)(tx4938_pcicptr->pciid >> 16), + (unsigned short)(tx4938_pcicptr->pciid & 0xffff), + (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), + extarb ? "External" : "Internal"); + + /* setup PCI area */ + tx4938_pci_controller[0].io_resource->start = io_base[0]; + tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; + tx4938_pci_controller[0].mem_resource->start = mem_base[0]; + tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; + + set_tx4938_pcicptr(0, tx4938_pcicptr); + + register_pci_controller(&tx4938_pci_controller[0]); + + if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { + printk("TX4938_CCFG_PCI66 already configured\n"); + txboard_pci66_mode = -1; /* already configured */ + } + + /* Reset PCI Bus */ + *rbtx4938_pcireset_ptr = 0; + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + if (txboard_pci66_mode > 0) + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + *rbtx4938_pcireset_ptr = 1; + wbflush(); + tx4938_report_pcic_status1(tx4938_pcicptr); + + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + if (txboard_pci66_mode == 0 && + txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { + /* Reset PCI Bus */ + *rbtx4938_pcireset_ptr = 0; + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + *rbtx4938_pcireset_ptr = 1; + wbflush(); + /* Reinitialize PCIC */ + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + } + + mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); + io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); + /* Reset PCIC1 */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; + /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; + else + tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; + mdelay(10); + /* clear PCIC1 reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + tx4938_report_pcic_status1(tx4938_pcic1ptr); + + printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", + (unsigned short)(tx4938_pcic1ptr->pciid >> 16), + (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), + (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); + printk("%s PCICLK:%dMHz\n", + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", + txx9_gbus_clock / + ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / + 1000000); + + /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ + tx4938_pci_controller[1].io_resource->start = + io_base[1] - io_base[0]; + tx4938_pci_controller[1].io_resource->end = + io_base[1] - io_base[0] + io_size[1] - 1; + tx4938_pci_controller[1].mem_resource->start = mem_base[1]; + tx4938_pci_controller[1].mem_resource->end = + mem_base[1] + mem_size[1] - 1; + set_tx4938_pcicptr(1, tx4938_pcic1ptr); + + register_pci_controller(&tx4938_pci_controller[1]); + + tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); + + /* map ioport 0 to PCI I/O space address 0 */ + set_io_port_base(KSEG1 + io_base[0]); + + return 0; +} + +arch_initcall(tx4938_pcibios_init); + +#endif /* CONFIG_PCI */ + +/* SPI support */ + +/* chip select for SPI devices */ +#define SEEPROM1_CS 7 /* PIO7 */ +#define SEEPROM2_CS 0 /* IOC */ +#define SEEPROM3_CS 1 /* IOC */ +#define SRTC_CS 2 /* IOC */ + +static int rbtx4938_spi_cs_func(int chipid, int on) +{ + unsigned char bit; + switch (chipid) { + case RBTX4938_SEEPROM1_CHIPID: + if (on) + tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS); + else + tx4938_pioptr->dout |= (1 << SEEPROM1_CS); + return 0; + break; + case RBTX4938_SEEPROM2_CHIPID: + bit = (1 << SEEPROM2_CS); + break; + case RBTX4938_SEEPROM3_CHIPID: + bit = (1 << SEEPROM3_CS); + break; + case RBTX4938_SRTC_CHIPID: + bit = (1 << SRTC_CS); + break; + default: + return -ENODEV; + } + /* bit1,2,4 are low active, bit3 is high active */ + *rbtx4938_spics_ptr = + (*rbtx4938_spics_ptr & ~bit) | + ((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit); + return 0; +} + +#ifdef CONFIG_PCI +extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); + +int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr) +{ + struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata; + static unsigned char dat[17]; + static int read_dat = 0; + int ch = 0; + + if (channel != &tx4938_pci_controller[1]) + return -ENODEV; + /* TX4938 PCIC1 */ + switch (PCI_SLOT(dev->devfn)) { + case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): + ch = 0; + break; + case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): + ch = 1; + break; + default: + return -ENODEV; + } + if (!read_dat) { + unsigned char sum; + int i; + read_dat = 1; + /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ + if (spi_eeprom_read(RBTX4938_SEEPROM1_CHIPID, + 0, dat, sizeof(dat))) { + printk(KERN_ERR "seeprom: read error.\n"); + } else { + if (strcmp(dat, "MAC") != 0) + printk(KERN_WARNING "seeprom: bad signature.\n"); + for (i = 0, sum = 0; i < sizeof(dat); i++) + sum += dat[i]; + if (sum) + printk(KERN_WARNING "seeprom: bad checksum.\n"); + } + } + memcpy(addr, &dat[4 + 6 * ch], 6); + return 0; +} +#endif /* CONFIG_PCI */ + +extern void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)); +static void __init rbtx4938_spi_setup(void) +{ + /* set SPI_SEL */ + tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; + /* chip selects for SPI devices */ + tx4938_pioptr->dout |= (1 << SEEPROM1_CS); + tx4938_pioptr->dir |= (1 << SEEPROM1_CS); + txx9_spi_init(TX4938_SPI_REG, rbtx4938_spi_cs_func); +} + +static struct resource rbtx4938_fpga_resource; + +static char pcode_str[8]; +static struct resource tx4938_reg_resource = { + pcode_str, TX4938_REG_BASE, TX4938_REG_BASE+TX4938_REG_SIZE, IORESOURCE_MEM +}; + +void __init tx4938_board_setup(void) +{ + int i; + unsigned long divmode; + int cpuclk = 0; + unsigned long pcode = TX4938_REV_PCODE(); + + ioport_resource.start = 0x1000; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0x1000; + iomem_resource.end = 0xffffffff; /* expand to 4GB */ + + sprintf(pcode_str, "TX%lx", pcode); + /* SDRAMC,EBUSC are configured by PROM */ + for (i = 0; i < 8; i++) { + if (!(tx4938_ebuscptr->cr[i] & 0x8)) + continue; /* disabled */ + rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); + txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); + } + + /* clocks */ + if (txx9_master_clock) { + /* calculate gbus_clock and cpu_clock from master_clock */ + divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = txx9_master_clock * 4; break; + default: + txx9_gbus_clock = txx9_master_clock; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + cpuclk = txx9_gbus_clock * 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + cpuclk = txx9_gbus_clock * 5 / 2; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + cpuclk = txx9_gbus_clock * 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + cpuclk = txx9_gbus_clock * 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + cpuclk = txx9_gbus_clock * 9 / 2; break; + } + txx9_cpu_clock = cpuclk; + } else { + if (txx9_cpu_clock == 0) { + txx9_cpu_clock = 300000000; /* 300MHz */ + } + /* calculate gbus_clock and master_clock from cpu_clock */ + cpuclk = txx9_cpu_clock; + divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + txx9_gbus_clock = cpuclk / 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + txx9_gbus_clock = cpuclk * 2 / 5; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + txx9_gbus_clock = cpuclk / 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + txx9_gbus_clock = cpuclk / 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = cpuclk * 2 / 9; break; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_master_clock = txx9_gbus_clock / 4; break; + default: + txx9_master_clock = txx9_gbus_clock; + } + } + /* change default value to udelay/mdelay take reasonable time */ + loops_per_jiffy = txx9_cpu_clock / HZ / 2; + + /* CCFG */ + /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; + /* clear PCIC1 reset */ + if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + + /* enable Timeout BusError */ + if (tx4938_ccfg_toeon) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; + + /* DMA selection */ + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; + + /* Use external clock for external arbiter */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; + + printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", + pcode_str, + cpuclk / 1000000, txx9_master_clock / 1000000, + (unsigned long)tx4938_ccfgptr->crir, + tx4938_ccfgptr->ccfg, + tx4938_ccfgptr->pcfg); + + printk("%s SDRAMC --", pcode_str); + for (i = 0; i < 4; i++) { + unsigned long long cr = tx4938_sdramcptr->cr[i]; + unsigned long ram_base, ram_size; + if (!((unsigned long)cr & 0x00000400)) + continue; /* disabled */ + ram_base = (unsigned long)(cr >> 49) << 21; + ram_size = ((unsigned long)(cr >> 33) + 1) << 21; + if (ram_base >= 0x20000000) + continue; /* high memory (ignore) */ + printk(" CR%d:%016Lx", i, cr); + txboard_add_phys_region(ram_base, ram_size); + } + printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); + + /* SRAM */ + if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { + unsigned int size = 0x800; + unsigned long base = + (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); + txboard_add_phys_region(base, size); + } + + /* IRC */ + /* disable interrupt control */ + tx4938_ircptr->cer = 0; + + /* TMR */ + /* disable all timers */ + for (i = 0; i < TX4938_NR_TMR; i++) { + tx4938_tmrptr(i)->tcr = 0x00000020; + tx4938_tmrptr(i)->tisr = 0; + tx4938_tmrptr(i)->cpra = 0xffffffff; + tx4938_tmrptr(i)->itmr = 0; + tx4938_tmrptr(i)->ccdr = 0; + tx4938_tmrptr(i)->pgmr = 0; + } + + /* enable DMA */ + TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN); + TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN); + + /* PIO */ + tx4938_pioptr->maskcpu = 0; + tx4938_pioptr->maskext = 0; + + /* TX4938 internal registers */ + if (request_resource(&iomem_resource, &tx4938_reg_resource)) + printk("request resource for internal registers failed\n"); +} + +#ifdef CONFIG_PCI +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) +{ + unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); + unsigned long g2pstatus = pcicptr->g2pstatus; + unsigned long pcicstatus = pcicptr->pcicstatus; + static struct { + unsigned long flag; + const char *str; + } pcistat_tbl[] = { + { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, + { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, + { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, + { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, + { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, + { PCI_STATUS_PARITY, "MasterParityError" }, + }, g2pstat_tbl[] = { + { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, + { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, + }, pcicstat_tbl[] = { + { TX4938_PCIC_PCICSTATUS_PME, "PME" }, + { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, + { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, + { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, + { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, + { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, + { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, + { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, + }; + int i; + + printk("pcistat:%04x(", pcistatus); + for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) + if (pcistatus & pcistat_tbl[i].flag) + printk("%s ", pcistat_tbl[i].str); + printk("), g2pstatus:%08lx(", g2pstatus); + for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) + if (g2pstatus & g2pstat_tbl[i].flag) + printk("%s ", g2pstat_tbl[i].str); + printk("), pcicstatus:%08lx(", pcicstatus); + for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) + if (pcicstatus & pcicstat_tbl[i].flag) + printk("%s ", pcicstat_tbl[i].str); + printk(")\n"); +} + +void tx4938_report_pcic_status(void) +{ + int i; + struct tx4938_pcic_reg *pcicptr; + for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) + tx4938_report_pcic_status1(pcicptr); +} + +#endif /* CONFIG_PCI */ + +/* We use onchip r4k counter or TMR timer as our system wide timer + * interrupt running at 100HZ. */ + +extern void __init rtc_rx5c348_init(int chipid); +void __init rbtx4938_time_init(void) +{ + rtc_rx5c348_init(RBTX4938_SRTC_CHIPID); + mips_hpt_frequency = txx9_cpu_clock / 2; +} + +void __init toshiba_rbtx4938_setup(void) +{ + unsigned long long pcfg; + char *argptr; + + iomem_resource.end = 0xffffffff; /* 4GB */ + + if (txx9_master_clock == 0) + txx9_master_clock = 25000000; /* 25MHz */ + tx4938_board_setup(); + /* setup irq stuff */ + TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */ + TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */ + /* setup serial stuff */ + TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */ + TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */ + +#ifndef CONFIG_PCI + set_io_port_base(RBTX4938_ETHER_BASE); +#endif + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)(0xff1ff300 + i * 0x100); + req.mapbase = 0xff1ff300 + i * 0x100; + req.irq = 32 + i; + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = 50000000; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } +#endif +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 + printk("PIOSEL: disabling both ata and nand selection\n"); + tx + local_irq_disable(); + 4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND + printk("PIOSEL: enabling nand selection\n"); + tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA + printk("PIOSEL: enabling ata selection\n"); + tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; +#endif + +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } +#endif + + +#ifdef CONFIG_FB + { + conswitchp = &dummy_con; + } +#endif + + rbtx4938_spi_setup(); + pcfg = tx4938_ccfgptr->pcfg; /* updated */ + /* fixup piosel */ + if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_ATA_SEL) { + *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04; + } + else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_NDF_SEL) { + *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08; + } + else { + *rbtx4938_piosel_ptr &= ~(0x08 | 0x04); + } + + rbtx4938_fpga_resource.name = "FPGA Registers"; + rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); + rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; + rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; + if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) + printk("request resource for fpga failed\n"); + + /* disable all OnBoard I/O interrupts */ + *rbtx4938_imask_ptr = 0; + + _machine_restart = rbtx4938_machine_restart; + _machine_halt = rbtx4938_machine_halt; + _machine_power_off = rbtx4938_machine_power_off; + + *rbtx4938_led_ptr = 0xff; + printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr); + printk(" DIPSW:%02x,%02x\n", + *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr); +} + +#ifdef CONFIG_PROC_FS +extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid); +static int __init tx4938_spi_proc_setup(void) +{ + struct proc_dir_entry *tx4938_spi_eeprom_dir; + + tx4938_spi_eeprom_dir = proc_mkdir("spi_eeprom", 0); + + if (!tx4938_spi_eeprom_dir) + return -ENOMEM; + + /* don't allow user access to RBTX4938_SEEPROM1_CHIPID + * as it contains eth0 and eth1 MAC addresses + */ + spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM2_CHIPID); + spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM3_CHIPID); + + return 0; +} + +__initcall(tx4938_spi_proc_setup); +#endif Index: linux/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c 2005-06-22 12:25:09.894057192 +0900 @@ -0,0 +1,219 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include +#include +#include + +/* ATMEL 250x0 instructions */ +#define ATMEL_WREN 0x06 +#define ATMEL_WRDI 0x04 +#define ATMEL_RDSR 0x05 +#define ATMEL_WRSR 0x01 +#define ATMEL_READ 0x03 +#define ATMEL_WRITE 0x02 + +#define ATMEL_SR_BSY 0x01 +#define ATMEL_SR_WEN 0x02 +#define ATMEL_SR_BP0 0x04 +#define ATMEL_SR_BP1 0x08 + +DEFINE_SPINLOCK(spi_eeprom_lock); + +static struct spi_dev_desc seeprom_dev_desc = { + .baud = 1500000, /* 1.5Mbps */ + .tcss = 1, + .tcsh = 1, + .tcsr = 1, + .byteorder = 1, /* MSB-First */ + .polarity = 0, /* High-Active */ + .phase = 0, /* Sample-Then-Shift */ + +}; +static inline int +spi_eeprom_io(int chipid, + unsigned char **inbufs, unsigned int *incounts, + unsigned char **outbufs, unsigned int *outcounts) +{ + return txx9_spi_io(chipid, &seeprom_dev_desc, + inbufs, incounts, outbufs, outcounts, 0); +} + +int spi_eeprom_write_enable(int chipid, int enable) +{ + unsigned char inbuf[1]; + unsigned char *inbufs[1]; + unsigned int incounts[2]; + unsigned long flags; + int stat; + inbuf[0] = enable ? ATMEL_WREN : ATMEL_WRDI; + inbufs[0] = inbuf; + incounts[0] = sizeof(inbuf); + incounts[1] = 0; + spin_lock_irqsave(&spi_eeprom_lock, flags); + stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL); + spin_unlock_irqrestore(&spi_eeprom_lock, flags); + return stat; +} + +static int spi_eeprom_read_status_nolock(int chipid) +{ + unsigned char inbuf[2], outbuf[2]; + unsigned char *inbufs[1], *outbufs[1]; + unsigned int incounts[2], outcounts[2]; + int stat; + inbuf[0] = ATMEL_RDSR; + inbuf[1] = 0; + inbufs[0] = inbuf; + incounts[0] = sizeof(inbuf); + incounts[1] = 0; + outbufs[0] = outbuf; + outcounts[0] = sizeof(outbuf); + outcounts[1] = 0; + stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts); + if (stat < 0) + return stat; + return outbuf[1]; +} + +int spi_eeprom_read_status(int chipid) +{ + unsigned long flags; + int stat; + spin_lock_irqsave(&spi_eeprom_lock, flags); + stat = spi_eeprom_read_status_nolock(chipid); + spin_unlock_irqrestore(&spi_eeprom_lock, flags); + return stat; +} + +int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len) +{ + unsigned char inbuf[2]; + unsigned char *inbufs[2], *outbufs[2]; + unsigned int incounts[2], outcounts[3]; + unsigned long flags; + int stat; + inbuf[0] = ATMEL_READ; + inbuf[1] = address; + inbufs[0] = inbuf; + inbufs[1] = NULL; + incounts[0] = sizeof(inbuf); + incounts[1] = 0; + outbufs[0] = NULL; + outbufs[1] = buf; + outcounts[0] = 2; + outcounts[1] = len; + outcounts[2] = 0; + spin_lock_irqsave(&spi_eeprom_lock, flags); + stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts); + spin_unlock_irqrestore(&spi_eeprom_lock, flags); + return stat; +} + +int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len) +{ + unsigned char inbuf[2]; + unsigned char *inbufs[2]; + unsigned int incounts[3]; + unsigned long flags; + int i, stat; + + if (address / 8 != (address + len - 1) / 8) + return -EINVAL; + stat = spi_eeprom_write_enable(chipid, 1); + if (stat < 0) + return stat; + stat = spi_eeprom_read_status(chipid); + if (stat < 0) + return stat; + if (!(stat & ATMEL_SR_WEN)) + return -EPERM; + + inbuf[0] = ATMEL_WRITE; + inbuf[1] = address; + inbufs[0] = inbuf; + inbufs[1] = buf; + incounts[0] = sizeof(inbuf); + incounts[1] = len; + incounts[2] = 0; + spin_lock_irqsave(&spi_eeprom_lock, flags); + stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL); + if (stat < 0) + goto unlock_return; + + /* write start. max 10ms */ + for (i = 10; i > 0; i--) { + int stat = spi_eeprom_read_status_nolock(chipid); + if (stat < 0) + goto unlock_return; + if (!(stat & ATMEL_SR_BSY)) + break; + mdelay(1); + } + spin_unlock_irqrestore(&spi_eeprom_lock, flags); + if (i == 0) + return -EIO; + return len; + unlock_return: + spin_unlock_irqrestore(&spi_eeprom_lock, flags); + return stat; +} + +#ifdef CONFIG_PROC_FS +#define MAX_SIZE 0x80 /* for ATMEL 25010 */ +static int spi_eeprom_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + unsigned int size = MAX_SIZE; + if (spi_eeprom_read((int)data, 0, (unsigned char *)page, size) < 0) + size = 0; + return size; +} + +static int spi_eeprom_write_proc(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + unsigned int size = MAX_SIZE; + int i; + if (file->f_pos >= size) + return -EIO; + if (file->f_pos + count > size) + count = size - file->f_pos; + for (i = 0; i < count; i += 8) { + int len = count - i < 8 ? count - i : 8; + if (spi_eeprom_write((int)data, file->f_pos, + (unsigned char *)buffer, len) < 0) { + count = -EIO; + break; + } + buffer += len; + file->f_pos += len; + } + return count; +} + +__init void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) +{ + struct proc_dir_entry *entry; + char name[128]; + sprintf(name, "seeprom-%d", chipid); + entry = create_proc_entry(name, 0600, dir); + if (entry) { + entry->read_proc = spi_eeprom_read_proc; + entry->write_proc = spi_eeprom_write_proc; + entry->data = (void *)chipid; + } +} +#endif /* CONFIG_PROC_FS */ Index: linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c 2005-06-22 12:25:09.894057192 +0900 @@ -0,0 +1,159 @@ +/* + * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int (*txx9_spi_cs_func)(int chipid, int on); +static spinlock_t txx9_spi_lock = SPIN_LOCK_UNLOCKED; + +extern unsigned int txx9_gbus_clock; + +#define SPI_FIFO_SIZE 4 + +void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) +{ + txx9_spi_cs_func = cs_func; + /* enter config mode */ + tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR; +} + +static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait); +static void txx9_spi_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + /* disable rx intr */ + tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE; + wake_up(&txx9_spi_wait); +} +static struct irqaction txx9_spi_action = { + txx9_spi_interrupt, 0, 0, "spi", NULL, NULL, +}; + +void __init txx9_spi_irqinit(int irc_irq) +{ + setup_irq(irc_irq, &txx9_spi_action); +} + +int txx9_spi_io(int chipid, struct spi_dev_desc *desc, + unsigned char **inbufs, unsigned int *incounts, + unsigned char **outbufs, unsigned int *outcounts, + int cansleep) +{ + unsigned int incount, outcount; + unsigned char *inp, *outp; + int ret; + unsigned long flags; + + spin_lock_irqsave(&txx9_spi_lock, flags); + if ((tx4938_spiptr->mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE) { + spin_unlock_irqrestore(&txx9_spi_lock, flags); + return -EBUSY; + } + /* enter config mode */ + tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR; + tx4938_spiptr->cr0 = + (desc->byteorder ? TXx9_SPCR0_SBOS : 0) | + (desc->polarity ? TXx9_SPCR0_SPOL : 0) | + (desc->phase ? TXx9_SPCR0_SPHA : 0) | + 0x08; + tx4938_spiptr->cr1 = + (((TXX9_IMCLK + desc->baud) / (2 * desc->baud) - 1) << 8) | + 0x08 /* 8 bit only */; + /* enter active mode */ + tx4938_spiptr->mcr = TXx9_SPMCR_ACTIVE; + spin_unlock_irqrestore(&txx9_spi_lock, flags); + + /* CS ON */ + if ((ret = txx9_spi_cs_func(chipid, 1)) < 0) { + spin_unlock_irqrestore(&txx9_spi_lock, flags); + return ret; + } + udelay(desc->tcss); + + /* do scatter IO */ + inp = inbufs ? *inbufs : NULL; + outp = outbufs ? *outbufs : NULL; + incount = 0; + outcount = 0; + while (1) { + unsigned char data; + unsigned int count; + int i; + if (!incount) { + incount = incounts ? *incounts++ : 0; + inp = (incount && inbufs) ? *inbufs++ : NULL; + } + if (!outcount) { + outcount = outcounts ? *outcounts++ : 0; + outp = (outcount && outbufs) ? *outbufs++ : NULL; + } + if (!inp && !outp) + break; + count = SPI_FIFO_SIZE; + if (incount) + count = min(count, incount); + if (outcount) + count = min(count, outcount); + + /* now tx must be idle... */ + while (!(tx4938_spiptr->sr & TXx9_SPSR_SIDLE)) + ; + + tx4938_spiptr->cr0 = + (tx4938_spiptr->cr0 & ~TXx9_SPCR0_RXIFL_MASK) | + ((count - 1) << 12); + if (cansleep) { + /* enable rx intr */ + tx4938_spiptr->cr0 |= TXx9_SPCR0_RBSIE; + } + /* send */ + for (i = 0; i < count; i++) + tx4938_spiptr->dr = inp ? *inp++ : 0; + /* wait all rx data */ + if (cansleep) { + wait_event(txx9_spi_wait, + tx4938_spiptr->sr & TXx9_SPSR_SRRDY); + } else { + while (!(tx4938_spiptr->sr & TXx9_SPSR_RBSI)) + ; + } + /* receive */ + for (i = 0; i < count; i++) { + data = tx4938_spiptr->dr; + if (outp) + *outp++ = data; + } + if (incount) + incount -= count; + if (outcount) + outcount -= count; + } + + /* CS OFF */ + udelay(desc->tcsh); + txx9_spi_cs_func(chipid, 0); + udelay(desc->tcsr); + + spin_lock_irqsave(&txx9_spi_lock, flags); + /* enter config mode */ + tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR; + spin_unlock_irqrestore(&txx9_spi_lock, flags); + + return 0; +} Index: linux/drivers/net/ne.c =================================================================== --- linux.orig/drivers/net/ne.c 2005-06-22 12:18:48.169088208 +0900 +++ linux/drivers/net/ne.c 2005-06-22 12:25:09.895057040 +0900 @@ -54,6 +54,10 @@ #include #include +#if defined(CONFIG_TOSHIBA_RBTX4927) || defined(CONFIG_TOSHIBA_RBTX4938) +#include +#endif + #include "8390.h" #define DRV_NAME "ne" @@ -111,6 +115,9 @@ {"E-LAN100", "E-LAN200", {0x00, 0x00, 0x5d}}, /* Broken ne1000 clones */ {"PCM-4823", "PCM-4823", {0x00, 0xc0, 0x6c}}, /* Broken Advantech MoBo */ {"REALTEK", "RTL8019", {0x00, 0x00, 0xe8}}, /* no-name with Realtek chip */ +#if defined(CONFIG_TOSHIBA_RBTX4927) || defined(CONFIG_TOSHIBA_RBTX4938) + {"RBHMA4X00-RTL8019", "RBHMA4X00/RTL8019", {0x00, 0x60, 0x0a}}, /* Toshiba built-in */ +#endif {"LCS-8834", "LCS-8836", {0x04, 0x04, 0x37}}, /* ShinyNet (SET) */ {NULL,} }; @@ -226,6 +233,10 @@ sprintf(dev->name, "eth%d", unit); netdev_boot_setup_check(dev); +#ifdef CONFIG_TOSHIBA_RBTX4938 + dev->base_addr = 0x07f20280; + dev->irq = RBTX4938_RTL_8019_IRQ; +#endif err = do_ne_probe(dev); if (err) goto out; @@ -511,6 +522,10 @@ ei_status.name = name; ei_status.tx_start_page = start_page; ei_status.stop_page = stop_page; +#if defined(CONFIG_TOSHIBA_RBTX4927) || defined(CONFIG_TOSHIBA_RBTX4938) + wordlength = 1; +#endif + #ifdef CONFIG_PLAT_OAKS32R ei_status.word16 = 0; #else Index: linux/include/asm-mips/bootinfo.h =================================================================== --- linux.orig/include/asm-mips/bootinfo.h 2005-06-22 12:18:48.169088208 +0900 +++ linux/include/asm-mips/bootinfo.h 2005-06-22 12:25:09.896056888 +0900 @@ -159,6 +159,7 @@ #define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ #define MACH_TOSHIBA_RBTX4927 4 #define MACH_TOSHIBA_RBTX4937 5 +#define MACH_TOSHIBA_RBTX4938 6 #define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ "RBTX4927", "RBTX4937" } Index: linux/include/asm-mips/tx4938/rbtx4938.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/include/asm-mips/tx4938/rbtx4938.h 2005-06-22 12:25:09.896056888 +0900 @@ -0,0 +1,207 @@ +/* + * linux/include/asm-mips/tx4938/rbtx4938.h + * Definitions for TX4937/TX4938 + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TX_BOARDS_RBTX4938_H +#define __ASM_TX_BOARDS_RBTX4938_H + +#include +#include + +/* CS */ +#define RBTX4938_CE0 0x1c000000 /* 64M */ +#define RBTX4938_CE2 0x17f00000 /* 1M */ + +/* Address map */ +#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) +#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) +#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) +#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) +#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) +#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) +#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) +#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) +#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) +#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) +#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) +#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) +#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) +#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) +#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) +#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) +#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) +#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) +#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) +#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) +#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) +#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) +#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) +#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) + +/* Ethernet port address (Jumperless Mode (W12:Open)) */ +#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) + +/* bits for ISTAT/IMASK/IMSTAT */ +#define RBTX4938_INTB_PCID 0 +#define RBTX4938_INTB_PCIC 1 +#define RBTX4938_INTB_PCIB 2 +#define RBTX4938_INTB_PCIA 3 +#define RBTX4938_INTB_RTC 4 +#define RBTX4938_INTB_ATA 5 +#define RBTX4938_INTB_MODEM 6 +#define RBTX4938_INTB_SWINT 7 +#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) +#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) +#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) +#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) +#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) +#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) +#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) +#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) + +#define rbtx4938_fpga_rev_ptr \ + ((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR) +#define rbtx4938_led_ptr \ + ((volatile unsigned char *)RBTX4938_LED_ADDR) +#define rbtx4938_dipsw_ptr \ + ((volatile unsigned char *)RBTX4938_DIPSW_ADDR) +#define rbtx4938_bdipsw_ptr \ + ((volatile unsigned char *)RBTX4938_BDIPSW_ADDR) +#define rbtx4938_imask_ptr \ + ((volatile unsigned char *)RBTX4938_IMASK_ADDR) +#define rbtx4938_imask2_ptr \ + ((volatile unsigned char *)RBTX4938_IMASK2_ADDR) +#define rbtx4938_intpol_ptr \ + ((volatile unsigned char *)RBTX4938_INTPOL_ADDR) +#define rbtx4938_istat_ptr \ + ((volatile unsigned char *)RBTX4938_ISTAT_ADDR) +#define rbtx4938_istat2_ptr \ + ((volatile unsigned char *)RBTX4938_ISTAT2_ADDR) +#define rbtx4938_imstat_ptr \ + ((volatile unsigned char *)RBTX4938_IMSTAT_ADDR) +#define rbtx4938_imstat2_ptr \ + ((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR) +#define rbtx4938_softint_ptr \ + ((volatile unsigned char *)RBTX4938_SOFTINT_ADDR) +#define rbtx4938_piosel_ptr \ + ((volatile unsigned char *)RBTX4938_PIOSEL_ADDR) +#define rbtx4938_spics_ptr \ + ((volatile unsigned char *)RBTX4938_SPICS_ADDR) +#define rbtx4938_sfpwr_ptr \ + ((volatile unsigned char *)RBTX4938_SFPWR_ADDR) +#define rbtx4938_sfvol_ptr \ + ((volatile unsigned char *)RBTX4938_SFVOL_ADDR) +#define rbtx4938_softreset_ptr \ + ((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR) +#define rbtx4938_softresetlock_ptr \ + ((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR) +#define rbtx4938_pcireset_ptr \ + ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR) + +/* SPI */ +#define RBTX4938_SEEPROM1_CHIPID 0 +#define RBTX4938_SEEPROM2_CHIPID 1 +#define RBTX4938_SEEPROM3_CHIPID 2 +#define RBTX4938_SRTC_CHIPID 3 + +/* + * IRQ mappings + */ + +#define RBTX4938_SOFT_INT0 0 /* not used */ +#define RBTX4938_SOFT_INT1 1 /* not used */ +#define RBTX4938_IRC_INT 2 +#define RBTX4938_TIMER_INT 7 + +/* These are the virtual IRQ numbers, we divide all IRQ's into + * 'spaces', the 'space' determines where and how to enable/disable + * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new + * IRQ hardware is supported. + */ +#define RBTX4938_NR_IRQ_LOCAL 8 +#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ +#define RBTX4938_NR_IRQ_IOC 8 + +#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ +#define MI8259_IRQ_ISA_RAW_END 15 +#define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */ +#define TX4938_IRQ_CP0_RAW_END 7 +#define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */ +#define TX4938_IRQ_PIC_RAW_END 31 + +#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ +#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ + +#define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */ +#define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */ + +#define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */ +#define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */ +#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) +#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) +#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) +#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1) +#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7) + +#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0 +#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7 + +#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */ +#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */ +#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG +#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL) +#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC) +#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) + +#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0) +#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1) +#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT) +#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT) +#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) +#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) +#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) +#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) +#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n)) +#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) +#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) +#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) +#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) +#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) +#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) +#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) +#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) +#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) +#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) +#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) +#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) +#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) +#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) +#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) +#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) +#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) +#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) +#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) + + +/* IOC (PCI, etc) */ +#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) +/* Onboard 10M Ether */ +#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) + +#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) +#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) + +/* IRCR : Int. Control */ +#define TX4938_IRCR_LOW 0x00000000 +#define TX4938_IRCR_HIGH 0x00000001 +#define TX4938_IRCR_DOWN 0x00000002 +#define TX4938_IRCR_UP 0x00000003 + +#endif /* __ASM_TX_BOARDS_RBTX4938_H */ Index: linux/include/asm-mips/tx4938/spi.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/include/asm-mips/tx4938/spi.h 2005-06-22 12:25:09.897056736 +0900 @@ -0,0 +1,74 @@ +/* + * linux/include/asm-mips/tx4938/spi.h + * Definitions for TX4937/TX4938 SPI + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TX_BOARDS_TX4938_SPI_H +#define __ASM_TX_BOARDS_TX4938_SPI_H + +/* SPI */ +struct spi_dev_desc { + unsigned int baud; + unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */ + unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */ + unsigned int polarity:1; /* 0:High-Active */ + unsigned int phase:1; /* 0:Sample-Then-Shift */ +}; + +extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init; +extern void txx9_spi_irqinit(int irc_irq) __init; +extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc, + unsigned char **inbufs, unsigned int *incounts, + unsigned char **outbufs, unsigned int *outcounts, + int cansleep); +extern int spi_eeprom_write_enable(int chipid, int enable); +extern int spi_eeprom_read_status(int chipid); +extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); +extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len); +extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init; + +#define TXX9_IMCLK (txx9_gbus_clock / 2) + +/* +* SPI +*/ + +/* SPMCR : SPI Master Control */ +#define TXx9_SPMCR_OPMODE 0xc0 +#define TXx9_SPMCR_CONFIG 0x40 +#define TXx9_SPMCR_ACTIVE 0x80 +#define TXx9_SPMCR_SPSTP 0x02 +#define TXx9_SPMCR_BCLR 0x01 + +/* SPCR0 : SPI Status */ +#define TXx9_SPCR0_TXIFL_MASK 0xc000 +#define TXx9_SPCR0_RXIFL_MASK 0x3000 +#define TXx9_SPCR0_SIDIE 0x0800 +#define TXx9_SPCR0_SOEIE 0x0400 +#define TXx9_SPCR0_RBSIE 0x0200 +#define TXx9_SPCR0_TBSIE 0x0100 +#define TXx9_SPCR0_IFSPSE 0x0010 +#define TXx9_SPCR0_SBOS 0x0004 +#define TXx9_SPCR0_SPHA 0x0002 +#define TXx9_SPCR0_SPOL 0x0001 + +/* SPSR : SPI Status */ +#define TXx9_SPSR_TBSI 0x8000 +#define TXx9_SPSR_RBSI 0x4000 +#define TXx9_SPSR_TBS_MASK 0x3800 +#define TXx9_SPSR_RBS_MASK 0x0700 +#define TXx9_SPSR_SPOE 0x0080 +#define TXx9_SPSR_IFSD 0x0008 +#define TXx9_SPSR_SIDLE 0x0004 +#define TXx9_SPSR_STRDY 0x0002 +#define TXx9_SPSR_SRRDY 0x0001 + +#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ Index: linux/include/asm-mips/tx4938/tx4938.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/include/asm-mips/tx4938/tx4938.h 2005-06-22 12:25:09.898056584 +0900 @@ -0,0 +1,706 @@ +/* + * linux/include/asm-mips/tx4938/tx4938.h + * Definitions for TX4937/TX4938 + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TX_BOARDS_TX4938_H +#define __ASM_TX_BOARDS_TX4938_H + +#include + +#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) +#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b) + +#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG + +#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC) +#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR) + +#define TX4938_PCIIO_0 0x10000000 +#define TX4938_PCIIO_1 0x01010000 +#define TX4938_PCIMEM_0 0x08000000 +#define TX4938_PCIMEM_1 0x11000000 + +#define TX4938_PCIIO_SIZE_0 0x01000000 +#define TX4938_PCIIO_SIZE_1 0x00010000 +#define TX4938_PCIMEM_SIZE_0 0x08000000 +#define TX4938_PCIMEM_SIZE_1 0x00010000 + +#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */ +#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ + +/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ +#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000) +#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000) +#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000) +#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000) +#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000) +#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800) +#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000) +#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000) +#define TX4938_NR_TMR 3 +#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100) +#define TX4938_NR_SIO 2 +#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100) +#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500) +#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600) +#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) +#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) + +#ifndef _LANGUAGE_ASSEMBLY +#include + +#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) )) + +#define TX4938_RD08( reg ) (*(vu08*)(reg)) +#define TX4938_WR08( reg, val ) ((*(vu08*)(reg))=(val)) + +#define TX4938_RD16( reg ) (*(vu16*)(reg)) +#define TX4938_WR16( reg, val ) ((*(vu16*)(reg))=(val)) + +#define TX4938_RD32( reg ) (*(vu32*)(reg)) +#define TX4938_WR32( reg, val ) ((*(vu32*)(reg))=(val)) + +#define TX4938_RD64( reg ) (*(vu64*)(reg)) +#define TX4938_WR64( reg, val ) ((*(vu64*)(reg))=(val)) + +#define TX4938_RD( reg ) TX4938_RD32( reg ) +#define TX4938_WR( reg, val ) TX4938_WR32( reg, val ) + +#endif /* !__ASSEMBLY__ */ + +#ifdef __ASSEMBLY__ +#define _CONST64(c) c +#else +#define _CONST64(c) c##ull + +#include + +#ifdef __BIG_ENDIAN +#define endian_def_l2(e1,e2) \ + volatile unsigned long e1,e2 +#define endian_def_s2(e1,e2) \ + volatile unsigned short e1,e2 +#define endian_def_sb2(e1,e2,e3) \ + volatile unsigned short e1;volatile unsigned char e2,e3 +#define endian_def_b2s(e1,e2,e3) \ + volatile unsigned char e1,e2;volatile unsigned short e3 +#define endian_def_b4(e1,e2,e3,e4) \ + volatile unsigned char e1,e2,e3,e4 +#else +#define endian_def_l2(e1,e2) \ + volatile unsigned long e2,e1 +#define endian_def_s2(e1,e2) \ + volatile unsigned short e2,e1 +#define endian_def_sb2(e1,e2,e3) \ + volatile unsigned char e3,e2;volatile unsigned short e1 +#define endian_def_b2s(e1,e2,e3) \ + volatile unsigned short e3;volatile unsigned char e2,e1 +#define endian_def_b4(e1,e2,e3,e4) \ + volatile unsigned char e4,e3,e2,e1 +#endif + + +struct tx4938_sdramc_reg { + volatile unsigned long long cr[4]; + volatile unsigned long long unused0[4]; + volatile unsigned long long tr; + volatile unsigned long long unused1[2]; + volatile unsigned long long cmd; + volatile unsigned long long sfcmd; +}; + +struct tx4938_ebusc_reg { + volatile unsigned long long cr[8]; +}; + +struct tx4938_dma_reg { + struct tx4938_dma_ch_reg { + volatile unsigned long long cha; + volatile unsigned long long sar; + volatile unsigned long long dar; + endian_def_l2(unused0, cntr); + endian_def_l2(unused1, sair); + endian_def_l2(unused2, dair); + endian_def_l2(unused3, ccr); + endian_def_l2(unused4, csr); + } ch[4]; + volatile unsigned long long dbr[8]; + volatile unsigned long long tdhr; + volatile unsigned long long midr; + endian_def_l2(unused0, mcr); +}; + +struct tx4938_pcic_reg { + volatile unsigned long pciid; + volatile unsigned long pcistatus; + volatile unsigned long pciccrev; + volatile unsigned long pcicfg1; + volatile unsigned long p2gm0plbase; /* +10 */ + volatile unsigned long p2gm0pubase; + volatile unsigned long p2gm1plbase; + volatile unsigned long p2gm1pubase; + volatile unsigned long p2gm2pbase; /* +20 */ + volatile unsigned long p2giopbase; + volatile unsigned long unused0; + volatile unsigned long pcisid; + volatile unsigned long unused1; /* +30 */ + volatile unsigned long pcicapptr; + volatile unsigned long unused2; + volatile unsigned long pcicfg2; + volatile unsigned long g2ptocnt; /* +40 */ + volatile unsigned long unused3[15]; + volatile unsigned long g2pstatus; /* +80 */ + volatile unsigned long g2pmask; + volatile unsigned long pcisstatus; + volatile unsigned long pcimask; + volatile unsigned long p2gcfg; /* +90 */ + volatile unsigned long p2gstatus; + volatile unsigned long p2gmask; + volatile unsigned long p2gccmd; + volatile unsigned long unused4[24]; /* +a0 */ + volatile unsigned long pbareqport; /* +100 */ + volatile unsigned long pbacfg; + volatile unsigned long pbastatus; + volatile unsigned long pbamask; + volatile unsigned long pbabm; /* +110 */ + volatile unsigned long pbacreq; + volatile unsigned long pbacgnt; + volatile unsigned long pbacstate; + volatile unsigned long long g2pmgbase[3]; /* +120 */ + volatile unsigned long long g2piogbase; + volatile unsigned long g2pmmask[3]; /* +140 */ + volatile unsigned long g2piomask; + volatile unsigned long long g2pmpbase[3]; /* +150 */ + volatile unsigned long long g2piopbase; + volatile unsigned long pciccfg; /* +170 */ + volatile unsigned long pcicstatus; + volatile unsigned long pcicmask; + volatile unsigned long unused5; + volatile unsigned long long p2gmgbase[3]; /* +180 */ + volatile unsigned long long p2giogbase; + volatile unsigned long g2pcfgadrs; /* +1a0 */ + volatile unsigned long g2pcfgdata; + volatile unsigned long unused6[8]; + volatile unsigned long g2pintack; + volatile unsigned long g2pspc; + volatile unsigned long unused7[12]; /* +1d0 */ + volatile unsigned long long pdmca; /* +200 */ + volatile unsigned long long pdmga; + volatile unsigned long long pdmpa; + volatile unsigned long long pdmctr; + volatile unsigned long long pdmcfg; /* +220 */ + volatile unsigned long long pdmsts; +}; + +struct tx4938_aclc_reg { + volatile unsigned long acctlen; + volatile unsigned long acctldis; + volatile unsigned long acregacc; + volatile unsigned long unused0; + volatile unsigned long acintsts; + volatile unsigned long acintmsts; + volatile unsigned long acinten; + volatile unsigned long acintdis; + volatile unsigned long acsemaph; + volatile unsigned long unused1[7]; + volatile unsigned long acgpidat; + volatile unsigned long acgpodat; + volatile unsigned long acslten; + volatile unsigned long acsltdis; + volatile unsigned long acfifosts; + volatile unsigned long unused2[11]; + volatile unsigned long acdmasts; + volatile unsigned long acdmasel; + volatile unsigned long unused3[6]; + volatile unsigned long acaudodat; + volatile unsigned long acsurrdat; + volatile unsigned long accentdat; + volatile unsigned long aclfedat; + volatile unsigned long acaudiat; + volatile unsigned long unused4; + volatile unsigned long acmodoat; + volatile unsigned long acmodidat; + volatile unsigned long unused5[15]; + volatile unsigned long acrevid; +}; + + +struct tx4938_tmr_reg { + volatile unsigned long tcr; + volatile unsigned long tisr; + volatile unsigned long cpra; + volatile unsigned long cprb; + volatile unsigned long itmr; + volatile unsigned long unused0[3]; + volatile unsigned long ccdr; + volatile unsigned long unused1[3]; + volatile unsigned long pgmr; + volatile unsigned long unused2[3]; + volatile unsigned long wtmr; + volatile unsigned long unused3[43]; + volatile unsigned long trr; +}; + +struct tx4938_sio_reg { + volatile unsigned long lcr; + volatile unsigned long dicr; + volatile unsigned long disr; + volatile unsigned long cisr; + volatile unsigned long fcr; + volatile unsigned long flcr; + volatile unsigned long bgr; + volatile unsigned long tfifo; + volatile unsigned long rfifo; +}; + +struct tx4938_pio_reg { + volatile unsigned long dout; + volatile unsigned long din; + volatile unsigned long dir; + volatile unsigned long od; + volatile unsigned long flag[2]; + volatile unsigned long pol; + volatile unsigned long intc; + volatile unsigned long maskcpu; + volatile unsigned long maskext; +}; +struct tx4938_irc_reg { + volatile unsigned long cer; + volatile unsigned long cr[2]; + volatile unsigned long unused0; + volatile unsigned long ilr[8]; + volatile unsigned long unused1[4]; + volatile unsigned long imr; + volatile unsigned long unused2[7]; + volatile unsigned long scr; + volatile unsigned long unused3[7]; + volatile unsigned long ssr; + volatile unsigned long unused4[7]; + volatile unsigned long csr; +}; + +struct tx4938_ndfmc_reg { + endian_def_l2(unused0, dtr); + endian_def_l2(unused1, mcr); + endian_def_l2(unused2, sr); + endian_def_l2(unused3, isr); + endian_def_l2(unused4, imr); + endian_def_l2(unused5, spr); + endian_def_l2(unused6, rstr); +}; + +struct tx4938_spi_reg { + volatile unsigned long mcr; + volatile unsigned long cr0; + volatile unsigned long cr1; + volatile unsigned long fs; + volatile unsigned long unused1; + volatile unsigned long sr; + volatile unsigned long dr; + volatile unsigned long unused2; +}; + +struct tx4938_sramc_reg { + volatile unsigned long long cr; +}; + +struct tx4938_ccfg_reg { + volatile unsigned long long ccfg; + volatile unsigned long long crir; + volatile unsigned long long pcfg; + volatile unsigned long long tear; + volatile unsigned long long clkctr; + volatile unsigned long long unused0; + volatile unsigned long long garbc; + volatile unsigned long long unused1; + volatile unsigned long long unused2; + volatile unsigned long long ramp; + volatile unsigned long long unused3; + volatile unsigned long long jmpadr; +}; + +#undef endian_def_l2 +#undef endian_def_s2 +#undef endian_def_sb2 +#undef endian_def_b2s +#undef endian_def_b4 + +#endif /* __ASSEMBLY__ */ + +/* + * NDFMC + */ + +/* NDFMCR : NDFMC Mode Control */ +#define TX4938_NDFMCR_WE 0x80 +#define TX4938_NDFMCR_ECC_ALL 0x60 +#define TX4938_NDFMCR_ECC_RESET 0x60 +#define TX4938_NDFMCR_ECC_READ 0x40 +#define TX4938_NDFMCR_ECC_ON 0x20 +#define TX4938_NDFMCR_ECC_OFF 0x00 +#define TX4938_NDFMCR_CE 0x10 +#define TX4938_NDFMCR_BSPRT 0x04 +#define TX4938_NDFMCR_ALE 0x02 +#define TX4938_NDFMCR_CLE 0x01 + +/* NDFMCR : NDFMC Status */ +#define TX4938_NDFSR_BUSY 0x80 + +/* NDFMCR : NDFMC Reset */ +#define TX4938_NDFRSTR_RST 0x01 + +/* + * IRC + */ + +#define TX4938_IR_ECCERR 0 +#define TX4938_IR_WTOERR 1 +#define TX4938_NUM_IR_INT 6 +#define TX4938_IR_INT(n) (2 + (n)) +#define TX4938_NUM_IR_SIO 2 +#define TX4938_IR_SIO(n) (8 + (n)) +#define TX4938_NUM_IR_DMA 4 +#define TX4938_IR_DMA(ch,n) ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */ +#define TX4938_IR_PIO 14 +#define TX4938_IR_PDMAC 15 +#define TX4938_IR_PCIC 16 +#define TX4938_NUM_IR_TMR 3 +#define TX4938_IR_TMR(n) (17 + (n)) +#define TX4938_IR_NDFMC 21 +#define TX4938_IR_PCIERR 22 +#define TX4938_IR_PCIPME 23 +#define TX4938_IR_ACLC 24 +#define TX4938_IR_ACLCPME 25 +#define TX4938_IR_PCIC1 26 +#define TX4938_IR_SPI 31 +#define TX4938_NUM_IR 32 +/* multiplex */ +#define TX4938_IR_ETH0 TX4938_IR_INT(4) +#define TX4938_IR_ETH1 TX4938_IR_INT(3) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) +#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) +#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) +#define TX4938_CCFG_TINTDIS 0x01000000 +#define TX4938_CCFG_PCI66 0x00800000 +#define TX4938_CCFG_PCIMODE 0x00400000 +#define TX4938_CCFG_PCI1_66 0x00200000 +#define TX4938_CCFG_DIVMODE_MASK 0x001e0000 +#define TX4938_CCFG_DIVMODE_2 (0x4 << 17) +#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) +#define TX4938_CCFG_DIVMODE_3 (0x5 << 17) +#define TX4938_CCFG_DIVMODE_4 (0x6 << 17) +#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) +#define TX4938_CCFG_DIVMODE_8 (0x0 << 17) +#define TX4938_CCFG_DIVMODE_10 (0xb << 17) +#define TX4938_CCFG_DIVMODE_12 (0x1 << 17) +#define TX4938_CCFG_DIVMODE_16 (0x2 << 17) +#define TX4938_CCFG_DIVMODE_18 (0x9 << 17) +#define TX4938_CCFG_BEOW 0x00010000 +#define TX4938_CCFG_WR 0x00008000 +#define TX4938_CCFG_TOE 0x00004000 +#define TX4938_CCFG_PCIXARB 0x00002000 +#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) +#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) +#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10) +#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10) +#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10) +#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10) +#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10) +#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10) +#define TX4938_CCFG_PCI1DMD 0x00000100 +#define TX4938_CCFG_SYSSP_MASK 0x000000c0 +#define TX4938_CCFG_ENDIAN 0x00000004 +#define TX4938_CCFG_HALT 0x00000002 +#define TX4938_CCFG_ACEHOLD 0x00000001 + +/* PCFG : Pin Configuration */ +#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) +#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) +#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) +#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) +#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) +#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) +#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 +#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) +#define TX4938_PCFG_SYSCLKEN 0x08000000 +#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 +#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) +#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000 +#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) +#define TX4938_PCFG_SEL2 0x00000200 +#define TX4938_PCFG_SEL1 0x00000100 +#define TX4938_PCFG_DMASEL_ALL 0x0000000f +#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000 +#define TX4938_PCFG_DMASEL0_SIO1 0x00000001 +#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000 +#define TX4938_PCFG_DMASEL1_SIO1 0x00000002 +#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000 +#define TX4938_PCFG_DMASEL2_SIO0 0x00000004 +#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000 +#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 + +/* CLKCTR : Clock Control */ +#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) +#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) +#define TX4938_CLKCTR_ETH1CKD 0x80000000 +#define TX4938_CLKCTR_ETH0CKD 0x40000000 +#define TX4938_CLKCTR_SPICKD 0x20000000 +#define TX4938_CLKCTR_SRAMCKD 0x10000000 +#define TX4938_CLKCTR_PCIC1CKD 0x08000000 +#define TX4938_CLKCTR_DMA1CKD 0x04000000 +#define TX4938_CLKCTR_ACLCKD 0x02000000 +#define TX4938_CLKCTR_PIOCKD 0x01000000 +#define TX4938_CLKCTR_DMACKD 0x00800000 +#define TX4938_CLKCTR_PCICKD 0x00400000 +#define TX4938_CLKCTR_TM0CKD 0x00100000 +#define TX4938_CLKCTR_TM1CKD 0x00080000 +#define TX4938_CLKCTR_TM2CKD 0x00040000 +#define TX4938_CLKCTR_SIO0CKD 0x00020000 +#define TX4938_CLKCTR_SIO1CKD 0x00010000 +#define TX4938_CLKCTR_ETH1RST 0x00008000 +#define TX4938_CLKCTR_ETH0RST 0x00004000 +#define TX4938_CLKCTR_SPIRST 0x00002000 +#define TX4938_CLKCTR_SRAMRST 0x00001000 +#define TX4938_CLKCTR_PCIC1RST 0x00000800 +#define TX4938_CLKCTR_DMA1RST 0x00000400 +#define TX4938_CLKCTR_ACLRST 0x00000200 +#define TX4938_CLKCTR_PIORST 0x00000100 +#define TX4938_CLKCTR_DMARST 0x00000080 +#define TX4938_CLKCTR_PCIRST 0x00000040 +#define TX4938_CLKCTR_TM0RST 0x00000010 +#define TX4938_CLKCTR_TM1RST 0x00000008 +#define TX4938_CLKCTR_TM2RST 0x00000004 +#define TX4938_CLKCTR_SIO0RST 0x00000002 +#define TX4938_CLKCTR_SIO1RST 0x00000001 + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4938_PCIC_PBACFG_FIXPA 0x00000008 +#define TX4938_PCIC_PBACFG_RPBA 0x00000004 +#define TX4938_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4938_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for G2PIOGBASE */ +#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8 +#define TX4938_PCIC_PCICSTATUS_PME 0x00000400 +#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200 +#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100 +#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080 +#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020 +#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010 +#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008 +#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002 +#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001 + +/* bits for PCICCFG */ +#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 +#define TX4938_PCIC_PCICCFG_HRST 0x00000800 +#define TX4938_PCIC_PCICCFG_SRST 0x00000400 +#define TX4938_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) +#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100 +#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080 +#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040 +#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020 +#define TX4938_PCIC_PCICCFG_TCAR 0x00000010 +#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) +#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) + +/* bits for P2GIOGBASE */ +#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) +#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) + +#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32) + +/* bits for PDMCFG */ +#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000 +#define TX4938_PCIC_PDMCFG_EXFER 0x00100000 +#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800 +#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11) +#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400 +#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200 +#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100 +#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080 +#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040 +#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020 +#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c +#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 +#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 +#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 +#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002 +#define TX4938_PCIC_PDMCFG_CHRST 0x00000001 + +/* bits for PDMSTS */ +#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 +#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 +#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 +#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000 +#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800 +#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400 +#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200 +#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100 +#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080 +#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040 +#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020 +#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008 +#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004 +#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002 +#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001 +#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0 +#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f + +/* + * DMA + */ +/* bits for MCR */ +#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch)) +#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch)) +#define TX4938_DMA_MCR_RSFIF 0x00000080 +#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) +#define TX4938_DMA_MCR_RPRT 0x00000002 +#define TX4938_DMA_MCR_MSTEN 0x00000001 + +/* bits for CCRn */ +#define TX4938_DMA_CCR_IMMCHN 0x20000000 +#define TX4938_DMA_CCR_USEXFSZ 0x10000000 +#define TX4938_DMA_CCR_LE 0x08000000 +#define TX4938_DMA_CCR_DBINH 0x04000000 +#define TX4938_DMA_CCR_SBINH 0x02000000 +#define TX4938_DMA_CCR_CHRST 0x01000000 +#define TX4938_DMA_CCR_RVBYTE 0x00800000 +#define TX4938_DMA_CCR_ACKPOL 0x00400000 +#define TX4938_DMA_CCR_REQPL 0x00200000 +#define TX4938_DMA_CCR_EGREQ 0x00100000 +#define TX4938_DMA_CCR_CHDN 0x00080000 +#define TX4938_DMA_CCR_DNCTL 0x00060000 +#define TX4938_DMA_CCR_EXTRQ 0x00010000 +#define TX4938_DMA_CCR_INTRQD 0x0000e000 +#define TX4938_DMA_CCR_INTENE 0x00001000 +#define TX4938_DMA_CCR_INTENC 0x00000800 +#define TX4938_DMA_CCR_INTENT 0x00000400 +#define TX4938_DMA_CCR_CHNEN 0x00000200 +#define TX4938_DMA_CCR_XFACT 0x00000100 +#define TX4938_DMA_CCR_SMPCHN 0x00000020 +#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) +#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2) +#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3) +#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4) +#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5) +#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) +#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) +#define TX4938_DMA_CCR_MEMIO 0x00000002 +#define TX4938_DMA_CCR_SNGAD 0x00000001 + +/* bits for CSRn */ +#define TX4938_DMA_CSR_CHNEN 0x00000400 +#define TX4938_DMA_CSR_STLXFER 0x00000200 +#define TX4938_DMA_CSR_CHNACT 0x00000100 +#define TX4938_DMA_CSR_ABCHC 0x00000080 +#define TX4938_DMA_CSR_NCHNC 0x00000040 +#define TX4938_DMA_CSR_NTRNFC 0x00000020 +#define TX4938_DMA_CSR_EXTDN 0x00000010 +#define TX4938_DMA_CSR_CFERR 0x00000008 +#define TX4938_DMA_CSR_CHERR 0x00000004 +#define TX4938_DMA_CSR_DESERR 0x00000002 +#define TX4938_DMA_CSR_SORERR 0x00000001 + +/* TX4938 Interrupt Controller (32-bit registers) */ +#define TX4938_IRC_BASE 0xf510 +#define TX4938_IRC_IRFLAG0 0xf510 +#define TX4938_IRC_IRFLAG1 0xf514 +#define TX4938_IRC_IRPOL 0xf518 +#define TX4938_IRC_IRRCNT 0xf51c +#define TX4938_IRC_IRMASKINT 0xf520 +#define TX4938_IRC_IRMASKEXT 0xf524 +#define TX4938_IRC_IRDEN 0xf600 +#define TX4938_IRC_IRDM0 0xf604 +#define TX4938_IRC_IRDM1 0xf608 +#define TX4938_IRC_IRLVL0 0xf610 +#define TX4938_IRC_IRLVL1 0xf614 +#define TX4938_IRC_IRLVL2 0xf618 +#define TX4938_IRC_IRLVL3 0xf61c +#define TX4938_IRC_IRLVL4 0xf620 +#define TX4938_IRC_IRLVL5 0xf624 +#define TX4938_IRC_IRLVL6 0xf628 +#define TX4938_IRC_IRLVL7 0xf62c +#define TX4938_IRC_IRMSK 0xf640 +#define TX4938_IRC_IREDC 0xf660 +#define TX4938_IRC_IRPND 0xf680 +#define TX4938_IRC_IRCS 0xf6a0 +#define TX4938_IRC_LIMIT 0xf6ff + + +#ifndef __ASSEMBLY__ + +#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) +#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) +#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) +#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) +#define tx4938_ircptr ((struct tx4938_irc_reg *)TX4938_IRC_REG) +#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) +#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) +#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) +#define tx4938_tmrptr(ch) ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch)) +#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) +#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG) +#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) +#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) +#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) + + +#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) +#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) + +#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) +#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) + +#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) +#define TX4938_EBUSC_SIZE(ch) \ + (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) + + +#endif /* !__ASSEMBLY__ */ + +#endif Index: linux/include/asm-mips/tx4938/tx4938_mips.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/include/asm-mips/tx4938/tx4938_mips.h 2005-06-22 12:25:09.898056584 +0900 @@ -0,0 +1,54 @@ +/* + * linux/include/asm-mips/tx4938/tx4938_bitmask.h + * Generic bitmask definitions + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#ifndef TX4938_TX4938_MIPS_H +#define TX4938_TX4938_MIPS_H +#ifndef __ASSEMBLY__ + +#define reg_rd08(r) ((u8 )(*((vu8 *)(r)))) +#define reg_rd16(r) ((u16)(*((vu16*)(r)))) +#define reg_rd32(r) ((u32)(*((vu32*)(r)))) +#define reg_rd64(r) ((u64)(*((vu64*)(r)))) + +#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) +#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) +#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) +#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) + +typedef volatile __signed char vs8; +typedef volatile unsigned char vu8; + +typedef volatile __signed short vs16; +typedef volatile unsigned short vu16; + +typedef volatile __signed int vs32; +typedef volatile unsigned int vu32; + +typedef s8 s08; +typedef vs8 vs08; + +typedef u8 u08; +typedef vu8 vu08; + +#if (_MIPS_SZLONG == 64) + +typedef volatile __signed__ long vs64; +typedef volatile unsigned long vu64; + +#else + +typedef volatile __signed__ long long vs64; +typedef volatile unsigned long long vu64; + +#endif +#endif +#endif From Hiroshi_DOYU@montavista.co.jp Wed Jun 22 04:35:50 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Jun 2005 04:36:07 +0100 (BST) Received: from sonicwall.montavista.co.jp ([IPv6:::ffff:202.232.97.131]:44655 "EHLO yuubin.montavista.co.jp") by linux-mips.org with ESMTP id ; Wed, 22 Jun 2005 04:35:50 +0100 Received: from localhost.localdomain (oreo.jp.mvista.com [10.200.16.31]) by yuubin.montavista.co.jp (8.12.5/8.12.5) with SMTP id j5M3YdS5027071; Wed, 22 Jun 2005 12:34:39 +0900 Date: Wed, 22 Jun 2005 12:36:25 +0900 From: Hiroshi DOYU To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mlachwani@mvista.com Subject: [patch 2.6.12 1/1] tx4938: Added kgdb support for Toshiba RBHMA4500(TX4938) Message-Id: <20050622123625.62caaa36.Hiroshi_DOYU@montavista.co.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8127 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Hiroshi_DOYU@montavista.co.jp Precedence: bulk X-list: linux-mips Hello, This patch is against 2.6.12 and it works fine. Please review it. Hiroshi DOYU ---- Added kgdb support for Toshiba RBHMA4500(TX4938) Signed-off-by: Hiroshi DOYU ---- arch/mips/tx4938/common/Makefile | 1 arch/mips/tx4938/common/dbgio.c | 50 +++++++++++++++++++++ drivers/serial/serial_txx9.c | 90 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+) Index: linux/arch/mips/tx4938/common/Makefile =================================================================== --- linux.orig/arch/mips/tx4938/common/Makefile 2005-06-22 11:59:51.110947320 +0900 +++ linux/arch/mips/tx4938/common/Makefile 2005-06-22 11:59:55.294311352 +0900 @@ -7,4 +7,5 @@ # obj-y += prom.o setup.o irq.o irq_handler.o rtc_rx5c348.o +obj-$(CONFIG_KGDB) += dbgio.o Index: linux/arch/mips/tx4938/common/dbgio.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/common/dbgio.c 2005-06-22 12:03:12.064397752 +0900 @@ -0,0 +1,50 @@ +/* + * linux/arch/mips/tx4938/common/dbgio.c + * + * kgdb interface for gdb + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Support for TX4938 in 2.6 - Hiroshi DOYU + */ + +#include +#include +#include + +extern u8 txx9_sio_kdbg_rd(void); +extern int txx9_sio_kdbg_wr( u8 ch ); + +u8 getDebugChar(void) +{ + return (txx9_sio_kdbg_rd()); +} + +int putDebugChar(u8 byte) +{ + return (txx9_sio_kdbg_wr(byte)); +} + Index: linux/drivers/serial/serial_txx9.c =================================================================== --- linux.orig/drivers/serial/serial_txx9.c 2005-06-22 11:55:50.169575976 +0900 +++ linux/drivers/serial/serial_txx9.c 2005-06-22 11:59:55.295311200 +0900 @@ -1129,6 +1129,96 @@ MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl); #endif /* ENABLE_SERIAL_TXX9_PCI */ +/******************************************************************************/ +/* BEG: KDBG Routines */ +/******************************************************************************/ + +#ifdef CONFIG_KGDB +int kgdb_init_count = 0; + +void txx9_sio_kgdb_hook(unsigned int port, unsigned int baud_rate) +{ + static struct resource kgdb_resource; + int ret; + struct uart_txx9_port *up = &serial_txx9_ports[port]; + + /* prevent initialization by driver */ + kgdb_resource.name = "serial_txx9(debug)"; + kgdb_resource.start = up->port.membase; + kgdb_resource.end = up->port.membase + 36 - 1; + kgdb_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; + + ret = request_resource(&iomem_resource, &kgdb_resource); + if(ret == -EBUSY) + printk(" serial_txx9(debug): request_resource failed\n"); + + return; +} +void +txx9_sio_kdbg_init( unsigned int port_number ) +{ + if (port_number == 1) { + txx9_sio_kgdb_hook(port_number, 38400); + } else { + printk("Bad Port Number [%u] != [1]\n",port_number); + } + return; +} + +u8 +txx9_sio_kdbg_rd( void ) +{ + unsigned int status,ch; + struct uart_txx9_port *up = &serial_txx9_ports[1]; + + if (kgdb_init_count == 0) { + txx9_sio_kdbg_init(1); + kgdb_init_count = 1; + } + + while (1) { + status = sio_in(up, TXX9_SIDISR); + if ( status & 0x1f ) { + ch = sio_in(up, TXX9_SIRFIFO ); + break; + } + } + + return (ch); +} + +int +txx9_sio_kdbg_wr( u8 ch ) +{ + unsigned int status; + struct uart_txx9_port *up = &serial_txx9_ports[1]; + + if (kgdb_init_count == 0) { + txx9_sio_kdbg_init(1); + kgdb_init_count = 1; + } + + while (1) { + status = sio_in(up, TXX9_SICISR); + if (status & TXX9_SICISR_TRDY) { + if ( ch == '\n' ) { + txx9_sio_kdbg_wr( '\r' ); + } + sio_out(up, TXX9_SITFIFO, (u32)ch ); + + break; + } + } + + return (1); +} +#endif /* CONFIG_KGDB */ + + +/******************************************************************************/ +/* END: KDBG Routines */ +/******************************************************************************/ + static int __init serial_txx9_init(void) { int ret; From Hiroshi_DOYU@montavista.co.jp Wed Jun 22 04:39:27 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Jun 2005 04:39:43 +0100 (BST) Received: from sonicwall.montavista.co.jp ([IPv6:::ffff:202.232.97.131]:54640 "EHLO yuubin.montavista.co.jp") by linux-mips.org with ESMTP id ; Wed, 22 Jun 2005 04:39:27 +0100 Received: from localhost.localdomain (oreo.jp.mvista.com [10.200.16.31]) by yuubin.montavista.co.jp (8.12.5/8.12.5) with SMTP id j5M3cIS5027115; Wed, 22 Jun 2005 12:38:18 +0900 Date: Wed, 22 Jun 2005 12:40:04 +0900 From: Hiroshi DOYU To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mlachwani@mvista.com Subject: [patch 2.6.12 1/1] tx4938: Enabled NAND support for Toshiba RBHMA4500(TX4938) Message-Id: <20050622124004.79b09861.Hiroshi_DOYU@montavista.co.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8128 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Hiroshi_DOYU@montavista.co.jp Precedence: bulk X-list: linux-mips Hello, This patch is against 2.6.12 and it works fine. Please review it. Hiroshi DOYU ---- Enabled NAND support for Toshiba RBHMA4500(TX4938) Signed-off-by: Hiroshi DOYU ---- arch/mips/Kconfig | 1 + arch/mips/tx4938/Kconfig | 23 +++++++++++++++++++++++ arch/mips/tx4938/toshiba_rbtx4938/prom.c | 4 ++-- 3 files changed, 26 insertions(+), 2 deletions(-) Index: linux/arch/mips/Kconfig =================================================================== --- linux.orig/arch/mips/Kconfig 2005-06-22 11:29:17.902637344 +0900 +++ linux/arch/mips/Kconfig 2005-06-22 11:29:17.943631112 +0900 @@ -657,6 +657,7 @@ source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" source "arch/mips/tx4927/Kconfig" +source "arch/mips/tx4938/Kconfig" source "arch/mips/vr41xx/Kconfig" endmenu Index: linux/arch/mips/tx4938/Kconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/tx4938/Kconfig 2005-06-22 11:29:17.943631112 +0900 @@ -0,0 +1,23 @@ +comment "Multiplex Pin Select" +choice + prompt "PIO[58:61]" + default TOSHIBA_RBTX4938_MPLEX_PIO58_61 + +config TOSHIBA_RBTX4938_MPLEX_PIO58_61 + bool "PIO" +config TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND" +config TOSHIBA_RBTX4938_MPLEX_ATA + bool "ATA" + +endchoice + +config TX4938_NAND_BOOT + depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND Boot Support (EXPERIMENTAL)" + help + This is only for Toshiba RBTX4938 reference board, which has NAND IPL. + Select this option if you need to use NAND boot. + + + Index: linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c =================================================================== --- linux.orig/arch/mips/tx4938/toshiba_rbtx4938/prom.c 2005-06-22 11:29:17.908636432 +0900 +++ linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c 2005-06-22 11:29:17.944630960 +0900 @@ -45,9 +45,9 @@ { extern int tx4938_get_mem_size(void); int msize; - +#ifndef CONFIG_TX4938_NAND_BOOT prom_init_cmdline(); - +#endif mips_machgroup = MACH_GROUP_TOSHIBA; mips_machtype = MACH_TOSHIBA_RBTX4938; From Hiroshi_DOYU@montavista.co.jp Wed Jun 22 04:41:59 2005 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 22 Jun 2005 04:42:27 +0100 (BST) Received: from sonicwall.montavista.co.jp ([IPv6:::ffff:202.232.97.131]:48497 "EHLO yuubin.montavista.co.jp") by linux-mips.org with ESMTP id ; Wed, 22 Jun 2005 04:41:59 +0100 Received: from localhost.localdomain (oreo.jp.mvista.com [10.200.16.31]) by yuubin.montavista.co.jp (8.12.5/8.12.5) with SMTP id j5M3enS5027453; Wed, 22 Jun 2005 12:40:49 +0900 Date: Wed, 22 Jun 2005 12:42:35 +0900 From: Hiroshi DOYU To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, mlachwani@mvista.com Subject: [patch 2.6.12 1/1] tx4938: Added the default config file for Toshiba RBHMA4500(TX4938) Message-Id: <20050622124235.6229939e.Hiroshi_DOYU@montavista.co.jp> X-Mailer: Sylpheed version 1.0.4 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 8129 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Hiroshi_DOYU@montavista.co.jp Precedence: bulk X-list: linux-mips Hello, This patch is against 2.6.12 and it works fine. Please review it. Hiroshi DOYU ---- Added the default config file for Toshiba RBHMA4500(TX4938) Signed-off-by: Hiroshi DOYU ---- arch/mips/configs/rbhma4500_defconfig | 1147 ++++++++++++++++++++++++++++++++++ 1 files changed, 1147 insertions(+) Index: linux/arch/mips/configs/rbhma4500_defconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux/arch/mips/configs/rbhma4500_defconfig 2005-06-22 11:29:17.958628832 +0900 @@ -0,0 +1,1147 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.12-rc5 +# Tue Jun 7 14:36:19 2005 +# +CONFIG_MIPS=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +# CONFIG_HOTPLUG is not set +# CONFIG_KOBJECT_UEVENT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODULE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +CONFIG_TOSHIBA_RBTX4938=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_HAVE_DEC_LOCK=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_I8259=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_HAVE_STD_PC_SERIAL_PORT=y +CONFIG_TOSHIBA_BOARDS=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +CONFIG_CPU_TX49XX=y +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_ADVANCED=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_WB=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +# CONFIG_PCI_LEGACY_PROC is not set +CONFIG_PCI_NAMES=y +CONFIG_ISA=y +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH