From macro@linux-mips.org Sun Oct 31 23:59:37 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 31 Oct 2004 23:59:41 +0000 (GMT) Received: from pollux.ds.pg.gda.pl ([IPv6:::ffff:153.19.208.7]:15623 "EHLO pollux.ds.pg.gda.pl") by linux-mips.org with ESMTP id ; Sun, 31 Oct 2004 23:59:37 +0000 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id D7E0EF5AC5; Mon, 1 Nov 2004 00:59:26 +0100 (CET) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 15252-10; Mon, 1 Nov 2004 00:59:26 +0100 (CET) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 69403F5AC4; Mon, 1 Nov 2004 00:59:26 +0100 (CET) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.1/8.13.1) with ESMTP id i9VNxjs3019397; Mon, 1 Nov 2004 00:59:45 +0100 Date: Sun, 31 Oct 2004 23:59:31 +0000 (GMT) From: "Maciej W. Rozycki" To: Dennis Grevenstein Cc: linux-mips@linux-mips.org Subject: Re: unable to handle kernel paging request In-Reply-To: <20041031223612.GA15091@aton.pcde.inka.de> Message-ID: References: <20041031184233.GA11120@aton.pcde.inka.de> <20041031191631.GB11681@aton.pcde.inka.de> <20041031192653.GG2094@lug-owl.de> <20041031195550.GA12397@aton.pcde.inka.de> <20041031201335.GH2094@lug-owl.de> <20041031223612.GA15091@aton.pcde.inka.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.80/552/Tue Oct 26 16:28:52 2004 clamav-milter version 0.80j on piorun.ds.pg.gda.pl X-Virus-Status: Clean X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6240 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, 31 Oct 2004, Dennis Grevenstein wrote: > struct tty_struct *tty = up->port.info->tty; /* XXX info==NULL? */ It looks up->port.info is null for some reason (and unhandled as noted in the comment). Maciej From mlachwani@prometheus.mvista.com Mon Nov 1 18:04:56 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Nov 2004 18:05:00 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:45806 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Mon, 1 Nov 2004 18:04:56 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iA1I4sdh011842 for ; Mon, 1 Nov 2004 10:04:54 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iA1I4r7b011840 for linux-mips@linux-mips.org; Mon, 1 Nov 2004 10:04:53 -0800 Date: Mon, 1 Nov 2004 10:04:53 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Subject: [PATCH]MTD Support for Malta in 2.6.10 Message-ID: <20041101180453.GB10943@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="O5XBE6gyVG5Rl6Rj" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6242 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 707 Lines: 30 --O5XBE6gyVG5Rl6Rj Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hello ! Attached patch gets MTD to work on the Malta board in 2.6.10. Please review ... Thanks Manish Lachwani --O5XBE6gyVG5Rl6Rj Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename=patch-mtd-malta --- arch/mips/mips-boards/malta/malta_setup.c.orig 2004-10-29 18:42:24.000000000 -0700 +++ arch/mips/mips-boards/malta/malta_setup.c 2004-10-29 19:19:01.000000000 -0700 @@ -25,6 +25,8 @@ #ifdef CONFIG_MTD #include #include +#include +#include #endif #include --O5XBE6gyVG5Rl6Rj-- From flo@rfc822.org Mon Nov 1 21:51:07 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Nov 2004 21:51:12 +0000 (GMT) Received: from hydra.gt.owl.de ([IPv6:::ffff:195.71.99.218]:45018 "EHLO hydra.gt.owl.de") by linux-mips.org with ESMTP id ; Mon, 1 Nov 2004 21:51:07 +0000 Received: by hydra.gt.owl.de (Postfix, from userid 104) id 1C38C1992CD; Mon, 1 Nov 2004 22:51:05 +0100 (CET) Received: by paradigm.rfc822.org (Postfix, from userid 1000) id 3102C138065; Mon, 1 Nov 2004 22:50:55 +0100 (CET) Date: Mon, 1 Nov 2004 22:50:55 +0100 From: Florian Lohoff To: "Maciej W. Rozycki" Cc: Dennis Grevenstein , linux-mips@linux-mips.org Subject: Re: unable to handle kernel paging request Message-ID: <20041101215055.GA27240@paradigm.rfc822.org> References: <20041031184233.GA11120@aton.pcde.inka.de> <20041031191631.GB11681@aton.pcde.inka.de> <20041031192653.GG2094@lug-owl.de> <20041031195550.GA12397@aton.pcde.inka.de> <20041031201335.GH2094@lug-owl.de> <20041031223612.GA15091@aton.pcde.inka.de> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="IS0zKkzwUGydFO0o" Content-Disposition: inline In-Reply-To: Organization: rfc822 - pure communication User-Agent: Mutt/1.5.4i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6243 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: flo@rfc822.org Precedence: bulk X-list: linux-mips Content-Length: 4241 Lines: 150 --IS0zKkzwUGydFO0o Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Oct 31, 2004 at 11:59:31PM +0000, Maciej W. Rozycki wrote: > On Sun, 31 Oct 2004, Dennis Grevenstein wrote: >=20 > > struct tty_struct *tty =3D up->port.info->tty; /* XXX info= =3D=3DNULL? */ >=20 > It looks up->port.info is null for some reason (and unhandled as noted= =20 > in the comment). I had the same problem and fixed it like this - It fixes some other break/sysrq based problems ... Index: drivers/serial/ip22zilog.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D RCS file: /home/flo/linux-mips-cvs/linux/drivers/serial/ip22zilog.c,v retrieving revision 1.15 diff -u -r1.15 ip22zilog.c --- drivers/serial/ip22zilog.c 28 Sep 2004 19:22:07 -0000 1.15 +++ drivers/serial/ip22zilog.c 3 Oct 2004 19:26:06 -0000 @@ -47,8 +47,6 @@ =20 #include "ip22zilog.h" =20 -void ip22_do_break(void); - /* * On IP22 we need to delay after register accesses but we do not need to * flush writes. @@ -256,17 +254,15 @@ struct zilog_channel *channel, struct pt_regs *regs) { - struct tty_struct *tty =3D up->port.info->tty; /* XXX info=3D=3DNULL? */ + struct tty_struct *tty =3D NULL; + + if (up->port.info !=3D NULL && /* Unopened serial console */ + up->port.info->tty !=3D NULL) /* Keyboard || mouse */ + tty =3D up->port.info->tty; =20 while (1) { unsigned char ch, r1; =20 - if (unlikely(tty->flip.count >=3D TTY_FLIPBUF_SIZE)) { - tty->flip.work.func((void *)tty); - if (tty->flip.count >=3D TTY_FLIPBUF_SIZE) - return; /* XXX Ignores SysRq when we need it most. Fix. */ - } - r1 =3D read_zsreg(channel, R1); if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { writeb(ERR_RES, &channel->control); @@ -288,24 +284,8 @@ =20 ch &=3D up->parity_mask; =20 - if (ZS_IS_CONS(up) && (r1 & BRK_ABRT)) { - /* Wait for BREAK to deassert to avoid potentially - * confusing the PROM. - */ - while (1) { - ch =3D readb(&channel->control); - ZSDELAY(); - if (!(ch & BRK_ABRT)) - break; - } - ip22_do_break(); - return; - } - - /* A real serial line, record the character and status. */ - *tty->flip.char_buf_ptr =3D ch; - *tty->flip.flag_buf_ptr =3D TTY_NORMAL; up->port.icount.rx++; + if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) { if (r1 & BRK_ABRT) { r1 &=3D ~(PAR_ERR | CRC_ERR); @@ -319,6 +299,25 @@ up->port.icount.frame++; if (r1 & Rx_OVR) up->port.icount.overrun++; + } + + if (uart_handle_sysrq_char(&up->port, ch, regs)) + goto next_char; + + if (!tty) + goto next_char; + + if (unlikely(tty->flip.count >=3D TTY_FLIPBUF_SIZE)) { + tty->flip.work.func((void *)tty); + if (tty->flip.count >=3D TTY_FLIPBUF_SIZE) + goto push_tty; /* XXX We drop characters here - Either read or die */ + } + + /* A real serial line, record the character and status. */ + *tty->flip.char_buf_ptr =3D ch; + *tty->flip.flag_buf_ptr =3D TTY_NORMAL; + + if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) { r1 &=3D up->port.read_status_mask; if (r1 & BRK_ABRT) *tty->flip.flag_buf_ptr =3D TTY_BREAK; @@ -327,8 +326,6 @@ else if (r1 & CRC_ERR) *tty->flip.flag_buf_ptr =3D TTY_FRAME; } - if (uart_handle_sysrq_char(&up->port, ch, regs)) - goto next_char; =20 if (up->port.ignore_status_mask =3D=3D 0xff || (r1 & up->port.ignore_status_mask) =3D=3D 0) { @@ -350,7 +347,9 @@ break; } =20 - tty_flip_buffer_push(tty); +push_tty: + if (tty) + tty_flip_buffer_push(tty); } =20 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up, --=20 Florian Lohoff flo@rfc822.org +49-171-2280134 Heisenberg may have been here. --IS0zKkzwUGydFO0o Content-Type: application/pgp-signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.4 (GNU/Linux) iD8DBQFBhq+/Uaz2rXW+gJcRApXvAKCyIrfLx2MkD1s3YjLZ7CWWA0Bb1gCg2tbJ vpJSQWozcCpETZR2jXpuYpg= =M8o8 -----END PGP SIGNATURE----- --IS0zKkzwUGydFO0o-- From thomas.petazzoni@enix.org Tue Nov 2 15:58:25 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2004 15:58:29 +0000 (GMT) Received: from the-doors.enix.org ([IPv6:::ffff:62.210.169.120]:44723 "EHLO the-doors.enix.org") by linux-mips.org with ESMTP id ; Tue, 2 Nov 2004 15:58:25 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by the-doors.enix.org (Postfix) with ESMTP id E855B1EFB0 for ; Tue, 2 Nov 2004 16:58:12 +0100 (CET) Message-ID: <4187AF03.5030606@enix.org> Date: Tue, 02 Nov 2004 17:00:03 +0100 From: Thomas Petazzoni User-Agent: Mozilla Thunderbird 0.8 (Windows/20040913) X-Accept-Language: fr, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Custom kernel crashes X-Enigmail-Version: 0.86.1.0 X-Enigmail-Supports: pgp-inline, pgp-mime Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig8D29ECD0C95DD6BD4372544E" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6244 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@enix.org Precedence: bulk X-list: linux-mips Content-Length: 8147 Lines: 220 This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig8D29ECD0C95DD6BD4372544E Content-Type: multipart/mixed; boundary="------------070705060406000509090507" This is a multi-part message in MIME format. --------------070705060406000509090507 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Hello, I've modified the Linux MIPS CVS kernel to support my board. Modification include platform initialization, serial driver and ethernet driver. When I leave the system alone for a while, it crashes with the error seen in the attached file. It crashes with a Bus error, but I don't know where the bus error occurs. epc and ra respectively points to do_be() and handle_dbe_int(), but I don't get any backtrace, because stack address 0xfe040000 is already the end of the end stack ;( How can I know to what process 0xfe040000 stack address correspond ? How can I have more information on what happened ? I suspect it's a bug in my serial driver, because of the strange characters displayed before "us error", but I'm not sure. I just need advices to be able to debug this problem. Thanks for your help, Thomas -- PETAZZONI Thomas - thomas.petazzoni@enix.org http://thomas.enix.org - Jabber: kos_tom@sourcecode.de KOS: http://kos.enix.org/ - Lolut: http://lolut.utbm.info Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E 1624 F653 CB30 98D3 F7A7 --------------070705060406000509090507 Content-Type: text/plain; name="linux-crash" Content-Transfer-Encoding: 8bit Content-Disposition: inline; filename="linux-crash" # QXºX±us error, epc == 8020c878, ra == 80206708 Oops in arch/mips/kernel/traps.c::do_be, line 333[#1]: Stack (0xfe040000) (0x0) Stack: ----------------Call Trace (0xfe040000) (0x1): Infos: 0xfe040000 - 1 Cpu 0 $ 0 : 00000000 00000000 bb001b00 00000000 $ 4 : fe040030 fe07fe20 00000000 ffffffff $ 8 : 9000ff00 1000001f 9000ff00 00000000 $12 : 00000000 00000000 00000000 00000000 $16 : fe07fe20 fe040030 00000000 00000000 $20 : 00000000 00000000 00000000 00000000 $24 : 00000000 4187a897 $28 : fe040000 fe040000 00000000 80206708 Hi : 00000000 Lo : 00000000 epc : 8020c878 do_be+0x1c/0x13c Not tainted ra : 80206708 handle_dbe_int+0x20/0x38 Status: 9000ff02 KERNEL EXL Cause : 0000841c PrId : 00003430 Modules linked in: CPU 0 Unable to handle kernel paging request at virtual address 00000074, epc == 80214520, ra == 8021688c Oops in arch/mips/mm/fault.c::do_page_fault, line 166[#2]: Stack (0xfe0020d0) (0xd0) Stack: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ... ----------------Call Trace (0xfe0020d0) (0x0): Infos: 0xfe0020d0 - 0 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 [<8021688c>] nopage_tlbl+0xf0/0x104 [<80214520>] do_page_fault+0x40/0x360 Cpu 0 $ 0 : 00000000 9000ff00 00030001 00000000 $ 4 : fe002198 00000000 00000074 fe03e000 $ 8 : 9000ff00 1000001e 00000003 803eb10c $12 : 00000000 00000000 fffffffe ffffffff $16 : 00000000 80376ef8 fe03ff50 00000004 $20 : 00000000 00000000 00000000 00000000 $24 : 00000010 00000003 $28 : fe002000 fe0020d0 00000000 8021688c Hi : 00000240 Lo : 000001f8 epc : 80214520 do_page_fault+0x40/0x360 Not tainted ra : 8021688c nopage_tlbl+0xf0/0x104 Status: 9000ff02 KERNEL EXL Cause : 00008408 BadVA : 00000000 PrId : 00003430 Modules linked in: Data bus error, epc == 802ce6d8, ra == 802cf58c Oops in arch/mips/kernel/traps.c::do_be, line 333[#3]: Stack (0xfe001e70) (0xe70) Stack: 00000400 fe001efc 9000ff00 ffffed6a 9000ff00 0000000a 80229464 00000000 00000400 fe001f1c 9000ff00 00000000 0000002c 00000000 00000000 00000000 802cf774 80229198 00000020 fe0020b8 80376eb1 803a343c 80376ea8 80229198 0000002c 00000000 00000000 80229120 fe002020 803778e0 fe002020 00000000 0000002c 00000000 00000000 80229120 00000000 c0000000 fe002020 803778e0 ... ----------------Call Trace (0xfe001e70) (0x0): Infos: 0xfe001e70 - 0 [<80229464>] release_console_sem+0x88/0x158 [<802cf774>] vscnprintf+0x14/0x30 [<80229198>] vprintk+0x6c/0x218 [<80229198>] vprintk+0x6c/0x218 [<80229120>] printk+0x1c/0x28 [<80229120>] printk+0x1c/0x28 [<8020c6e4>] show_registers+0x58/0x7c [<8020c6bc>] show_registers+0x30/0x7c [<80206708>] handle_dbe_int+0x20/0x38 [<8020c7bc>] __die+0xb4/0xcc [<8021464c>] do_page_fault+0x16c/0x360 [<80214520>] do_page_fault+0x40/0x360 [<8021688c>] nopage_tlbl+0xf0/0x104 Cpu 0 $ 0 : 00000000 9000ff00 ffffffff fe04016a $ 4 : fe04016a fffffffe 80376eb1 fe001f1c $ 8 : ffffffff 0000000a 00000003 803eb10c $12 : 00000000 00000000 fffffffe ffffffff $16 : 803eb104 fe04016a 803eb4fb 00000000 $20 : fe001f1c ffffffff 803eb0fc 00000400 $24 : 00000010 00000003 $28 : fe002000 fe001e70 00000000 802cf58c Hi : 00000240 Lo : 000001f8 epc : 802ce6d8 strnlen+0x10/0x40 Not tainted ra : 802cf58c vsnprintf+0x46c/0x640 Status: 9000ff02 KERNEL EXL Cause : 0000841c PrId : 00003430 Modules linked in: --------------070705060406000509090507-- --------------enig8D29ECD0C95DD6BD4372544E Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.5 (MingW32) Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org iD8DBQFBh68H9lPLMJjT96cRAhkkAJ0bzgDtevU/lurLPiIjAybpmRIAxACfbL9o WDVPmJmjNcX489EvYzCStYw= =9/vm -----END PGP SIGNATURE----- --------------enig8D29ECD0C95DD6BD4372544E-- From mlachwani@mvista.com Tue Nov 2 16:52:25 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2004 16:52:39 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:34545 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Tue, 2 Nov 2004 16:52:25 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 6F480185E5; Tue, 2 Nov 2004 08:52:20 -0800 (PST) Message-ID: <4187BB44.4030508@mvista.com> Date: Tue, 02 Nov 2004 08:52:20 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: Thomas Petazzoni Cc: linux-mips@linux-mips.org Subject: Re: Custom kernel crashes References: <4187AF03.5030606@enix.org> In-Reply-To: <4187AF03.5030606@enix.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6245 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 7653 Lines: 199 Hello Thomas ! This may or may not apply to your case. Is this board still the one that has the Marvell Discovery ethernet device? If yes, Marvell Discovery has its SRAM located at 0xfe000000. So, make a check in the ethernet driver or other board specific sources and see if there is any access to this SRAM location. Thanks Manish Lachwani Thomas Petazzoni wrote: > Hello, > > I've modified the Linux MIPS CVS kernel to support my board. > Modification include platform initialization, serial driver and ethernet > driver. > > When I leave the system alone for a while, it crashes with the error > seen in the attached file. It crashes with a Bus error, but I don't know > where the bus error occurs. epc and ra respectively points to do_be() > and handle_dbe_int(), but I don't get any backtrace, because stack > address 0xfe040000 is already the end of the end stack ;( > > How can I know to what process 0xfe040000 stack address correspond ? How > can I have more information on what happened ? > > I suspect it's a bug in my serial driver, because of the strange > characters displayed before "us error", but I'm not sure. I just need > advices to be able to debug this problem. > > Thanks for your help, > > Thomas > > > ------------------------------------------------------------------------ > > # QXºX±us error, epc == 8020c878, ra == 80206708 > Oops in arch/mips/kernel/traps.c::do_be, line 333[#1]: > Stack (0xfe040000) (0x0) Stack: > ----------------Call Trace (0xfe040000) (0x1): > Infos: 0xfe040000 - 1 > > Cpu 0 > $ 0 : 00000000 00000000 bb001b00 00000000 > $ 4 : fe040030 fe07fe20 00000000 ffffffff > $ 8 : 9000ff00 1000001f 9000ff00 00000000 > $12 : 00000000 00000000 00000000 00000000 > $16 : fe07fe20 fe040030 00000000 00000000 > $20 : 00000000 00000000 00000000 00000000 > $24 : 00000000 4187a897 > $28 : fe040000 fe040000 00000000 80206708 > Hi : 00000000 > Lo : 00000000 > epc : 8020c878 do_be+0x1c/0x13c Not tainted > ra : 80206708 handle_dbe_int+0x20/0x38 > Status: 9000ff02 KERNEL EXL > Cause : 0000841c > PrId : 00003430 > Modules linked in: > CPU 0 Unable to handle kernel paging request at virtual address 00000074, epc == 80214520, ra == 8021688c > Oops in arch/mips/mm/fault.c::do_page_fault, line 166[#2]: > Stack (0xfe0020d0) (0xd0) Stack: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 > 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 > 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 > 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 > 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 > ... > ----------------Call Trace (0xfe0020d0) (0x0): > Infos: 0xfe0020d0 - 0 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<8021688c>] nopage_tlbl+0xf0/0x104 > [<80214520>] do_page_fault+0x40/0x360 > > Cpu 0 > $ 0 : 00000000 9000ff00 00030001 00000000 > $ 4 : fe002198 00000000 00000074 fe03e000 > $ 8 : 9000ff00 1000001e 00000003 803eb10c > $12 : 00000000 00000000 fffffffe ffffffff > $16 : 00000000 80376ef8 fe03ff50 00000004 > $20 : 00000000 00000000 00000000 00000000 > $24 : 00000010 00000003 > $28 : fe002000 fe0020d0 00000000 8021688c > Hi : 00000240 > Lo : 000001f8 > epc : 80214520 do_page_fault+0x40/0x360 Not tainted > ra : 8021688c nopage_tlbl+0xf0/0x104 > Status: 9000ff02 KERNEL EXL > Cause : 00008408 > BadVA : 00000000 > PrId : 00003430 > Modules linked in: > Data bus error, epc == 802ce6d8, ra == 802cf58c > Oops in arch/mips/kernel/traps.c::do_be, line 333[#3]: > Stack (0xfe001e70) (0xe70) Stack: 00000400 fe001efc 9000ff00 ffffed6a 9000ff00 0000000a 80229464 00000000 > 00000400 fe001f1c 9000ff00 00000000 0000002c 00000000 00000000 00000000 > 802cf774 80229198 00000020 fe0020b8 80376eb1 803a343c 80376ea8 80229198 > 0000002c 00000000 00000000 80229120 fe002020 803778e0 fe002020 00000000 > 0000002c 00000000 00000000 80229120 00000000 c0000000 fe002020 803778e0 > ... > ----------------Call Trace (0xfe001e70) (0x0): > Infos: 0xfe001e70 - 0 > [<80229464>] release_console_sem+0x88/0x158 > [<802cf774>] vscnprintf+0x14/0x30 > [<80229198>] vprintk+0x6c/0x218 > [<80229198>] vprintk+0x6c/0x218 > [<80229120>] printk+0x1c/0x28 > [<80229120>] printk+0x1c/0x28 > [<8020c6e4>] show_registers+0x58/0x7c > [<8020c6bc>] show_registers+0x30/0x7c > [<80206708>] handle_dbe_int+0x20/0x38 > [<8020c7bc>] __die+0xb4/0xcc > [<8021464c>] do_page_fault+0x16c/0x360 > [<80214520>] do_page_fault+0x40/0x360 > [<8021688c>] nopage_tlbl+0xf0/0x104 > > Cpu 0 > $ 0 : 00000000 9000ff00 ffffffff fe04016a > $ 4 : fe04016a fffffffe 80376eb1 fe001f1c > $ 8 : ffffffff 0000000a 00000003 803eb10c > $12 : 00000000 00000000 fffffffe ffffffff > $16 : 803eb104 fe04016a 803eb4fb 00000000 > $20 : fe001f1c ffffffff 803eb0fc 00000400 > $24 : 00000010 00000003 > $28 : fe002000 fe001e70 00000000 802cf58c > Hi : 00000240 > Lo : 000001f8 > epc : 802ce6d8 strnlen+0x10/0x40 Not tainted > ra : 802cf58c vsnprintf+0x46c/0x640 > Status: 9000ff02 KERNEL EXL > Cause : 0000841c > PrId : 00003430 > Modules linked in: > From thomas.petazzoni@enix.org Tue Nov 2 17:05:48 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2004 17:05:53 +0000 (GMT) Received: from the-doors.enix.org ([IPv6:::ffff:62.210.169.120]:55477 "EHLO the-doors.enix.org") by linux-mips.org with ESMTP id ; Tue, 2 Nov 2004 17:05:48 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by the-doors.enix.org (Postfix) with ESMTP id E9DE51EFE3; Tue, 2 Nov 2004 18:05:41 +0100 (CET) Message-ID: <4187BED1.2060208@enix.org> Date: Tue, 02 Nov 2004 18:07:29 +0100 From: Thomas Petazzoni User-Agent: Mozilla Thunderbird 0.8 (Windows/20040913) X-Accept-Language: fr, en MIME-Version: 1.0 To: Manish Lachwani Cc: linux-mips@linux-mips.org Subject: Re: Custom kernel crashes References: <4187AF03.5030606@enix.org> <4187BB44.4030508@mvista.com> In-Reply-To: <4187BB44.4030508@mvista.com> X-Enigmail-Version: 0.86.1.0 X-Enigmail-Supports: pgp-inline, pgp-mime Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig7ECF95088FC6689CE7C69BB4" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6246 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@enix.org Precedence: bulk X-list: linux-mips Content-Length: 1815 Lines: 53 This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig7ECF95088FC6689CE7C69BB4 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Hello, Manish Lachwani a écrit : > This may or may not apply to your case. Is this board still the one that > has the Marvell Discovery ethernet device? If yes, Marvell Discovery has > its SRAM located at 0xfe000000. So, make a check in the ethernet driver > or other board specific sources and see if there is any access to this > SRAM location. The DMA buffers and DMA buffer descriptors used for the serial driver are all located in the SRAM of the Marvell, which is mapped using a wired uncached TLB entry. Here's the code that wires the entry : add_wired_entry(ENTRYLO(NPP_BOARD_INTERNAL_SRAM_BASE), ENTRYLO(NPP_BOARD_INTERNAL_SRAM_END), NPP_BOARD_INTERNAL_SRAM_BASE, PM_256K); I would like to use ioremap() instead of wired TLB entries, but for the moment, I'm focusing on this crash. Thanks, Thomas -- PETAZZONI Thomas - thomas.petazzoni@enix.org http://thomas.enix.org - Jabber: kos_tom@sourcecode.de KOS: http://kos.enix.org/ - Lolut: http://lolut.utbm.info Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E 1624 F653 CB30 98D3 F7A7 --------------enig7ECF95088FC6689CE7C69BB4 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.5 (MingW32) Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org iD8DBQFBh77X9lPLMJjT96cRAqoXAJ933959DI0HCYt2iA3uwjOGJUbU0gCfWDa5 C8OhunQoE9ux79awYJNCB0Q= =6XXq -----END PGP SIGNATURE----- --------------enig7ECF95088FC6689CE7C69BB4-- From mlachwani@mvista.com Tue Nov 2 17:12:27 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2004 17:12:31 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:5874 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Tue, 2 Nov 2004 17:12:27 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id C584E1845C; Tue, 2 Nov 2004 09:12:24 -0800 (PST) Message-ID: <4187BFF8.6000905@mvista.com> Date: Tue, 02 Nov 2004 09:12:24 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: Thomas Petazzoni Cc: linux-mips@linux-mips.org Subject: Re: Custom kernel crashes References: <4187AF03.5030606@enix.org> <4187BB44.4030508@mvista.com> <4187BED1.2060208@enix.org> In-Reply-To: <4187BED1.2060208@enix.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6247 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1144 Lines: 43 Hello ! What are these values: NPP_BOARD_INTERNAL_SRAM_BASE, NPP_BOARD_INTERNAL_SRAM_END and NPP_BOARD_INTERNAL_SRAM_BASE. Also, what is ENTRYLO() defined as? Thanks Manish Lachwani Thomas Petazzoni wrote: > Hello, > > Manish Lachwani a écrit : > >> This may or may not apply to your case. Is this board still the one >> that has the Marvell Discovery ethernet device? If yes, Marvell >> Discovery has its SRAM located at 0xfe000000. So, make a check in the >> ethernet driver or other board specific sources and see if there is >> any access to this SRAM location. > > > The DMA buffers and DMA buffer descriptors used for the serial driver > are all located in the SRAM of the Marvell, which is mapped using a > wired uncached TLB entry. > > Here's the code that wires the entry : > > add_wired_entry(ENTRYLO(NPP_BOARD_INTERNAL_SRAM_BASE), > ENTRYLO(NPP_BOARD_INTERNAL_SRAM_END), > NPP_BOARD_INTERNAL_SRAM_BASE, > PM_256K); > > I would like to use ioremap() instead of wired TLB entries, but for the > moment, I'm focusing on this crash. > > Thanks, > > Thomas From thomas.petazzoni@enix.org Tue Nov 2 17:21:10 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2004 17:21:14 +0000 (GMT) Received: from the-doors.enix.org ([IPv6:::ffff:62.210.169.120]:18358 "EHLO the-doors.enix.org") by linux-mips.org with ESMTP id ; Tue, 2 Nov 2004 17:21:10 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by the-doors.enix.org (Postfix) with ESMTP id D34C51EFE3; Tue, 2 Nov 2004 18:21:03 +0100 (CET) Message-ID: <4187C26E.1090402@enix.org> Date: Tue, 02 Nov 2004 18:22:54 +0100 From: Thomas Petazzoni User-Agent: Mozilla Thunderbird 0.8 (Windows/20040913) X-Accept-Language: fr, en MIME-Version: 1.0 To: Manish Lachwani Cc: linux-mips@linux-mips.org Subject: Re: Custom kernel crashes References: <4187AF03.5030606@enix.org> <4187BB44.4030508@mvista.com> <4187BED1.2060208@enix.org> <4187BFF8.6000905@mvista.com> In-Reply-To: <4187BFF8.6000905@mvista.com> X-Enigmail-Version: 0.86.1.0 X-Enigmail-Supports: pgp-inline, pgp-mime Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig2AD1789E08A6E7C679DEE325" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6248 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@enix.org Precedence: bulk X-list: linux-mips Content-Length: 1676 Lines: 54 This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig2AD1789E08A6E7C679DEE325 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Hello, Manish Lachwani a écrit : > What are these values: NPP_BOARD_INTERNAL_SRAM_BASE, > NPP_BOARD_INTERNAL_SRAM_END and NPP_BOARD_INTERNAL_SRAM_BASE. #define NPP_BOARD_INTERNAL_SRAM_BASE 0xfe000000UL #define NPP_BOARD_INTERNAL_SRAM_SIZE (256*1024) #define NPP_BOARD_INTERNAL_SRAM_END \ (NPP_BOARD_INTERNAL_SRAM_BASE + NPP_BOARD_INTERNAL_SRAM_SIZE) Do you think it's a problem related to the SRAM ? > Also, what is ENTRYLO() defined as? static inline unsigned long ENTRYLO(unsigned long paddr) { return ((paddr & PAGE_MASK) | (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)) >> 6; } This code is taken from the jaguar_atx setup.c file. Thanks, Thomas -- PETAZZONI Thomas - thomas.petazzoni@enix.org http://thomas.enix.org - Jabber: kos_tom@sourcecode.de KOS: http://kos.enix.org/ - Lolut: http://lolut.utbm.info Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E 1624 F653 CB30 98D3 F7A7 --------------enig2AD1789E08A6E7C679DEE325 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.5 (MingW32) Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org iD8DBQFBh8Jz9lPLMJjT96cRAtjSAKCA9UcrgTyv2FzL/I2TSKAhQ99tWQCdGDpS DdoS9AJx3nn6of7qXYcc1Lo= =5KAl -----END PGP SIGNATURE----- --------------enig2AD1789E08A6E7C679DEE325-- From mlachwani@mvista.com Tue Nov 2 17:36:06 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2004 17:36:10 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:38129 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Tue, 2 Nov 2004 17:36:06 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 87AA11845C; Tue, 2 Nov 2004 09:36:04 -0800 (PST) Message-ID: <4187C584.4060000@mvista.com> Date: Tue, 02 Nov 2004 09:36:04 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: Thomas Petazzoni Cc: linux-mips@linux-mips.org Subject: Re: Custom kernel crashes References: <4187AF03.5030606@enix.org> <4187BB44.4030508@mvista.com> <4187BED1.2060208@enix.org> <4187BFF8.6000905@mvista.com> <4187C26E.1090402@enix.org> In-Reply-To: <4187C26E.1090402@enix.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6249 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1104 Lines: 46 Hello Thomas, Quick suggestion since I dont know all the details: Can you increase the size of the space mapped to say 16 MB (some larget value than 256 KB) and check if the bus error repeats? #define NPP_BOARD_INTERNAL_SRAM_SIZE (16 *1024 * 1024) Thanks Manish Lachwani Thomas Petazzoni wrote: > Hello, > > Manish Lachwani a écrit : > >> What are these values: NPP_BOARD_INTERNAL_SRAM_BASE, >> NPP_BOARD_INTERNAL_SRAM_END and NPP_BOARD_INTERNAL_SRAM_BASE. > > > #define NPP_BOARD_INTERNAL_SRAM_BASE 0xfe000000UL > #define NPP_BOARD_INTERNAL_SRAM_SIZE (256*1024) > #define NPP_BOARD_INTERNAL_SRAM_END \ > (NPP_BOARD_INTERNAL_SRAM_BASE + NPP_BOARD_INTERNAL_SRAM_SIZE) > > Do you think it's a problem related to the SRAM ? > >> Also, what is ENTRYLO() defined as? > > > static inline unsigned long ENTRYLO(unsigned long paddr) > { > return ((paddr & PAGE_MASK) | > (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | > _CACHE_UNCACHED)) >> 6; > } > > This code is taken from the jaguar_atx setup.c file. > > Thanks, > > Thomas From mlachwani@prometheus.mvista.com Tue Nov 2 20:17:24 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2004 20:17:37 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:7411 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Tue, 2 Nov 2004 20:17:24 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iA2KHLdh026681 for ; Tue, 2 Nov 2004 12:17:21 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iA2KHK4v026679 for linux-mips@linux-mips.org; Tue, 2 Nov 2004 12:17:20 -0800 Date: Tue, 2 Nov 2004 12:17:20 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Subject: [PATCH] Support for PMC-Sierra Ocelot-3 in 2.6 Message-ID: <20041102201720.GB24674@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="p4qYPpj5QlsIQJ0K" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6250 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 48290 Lines: 1866 --p4qYPpj5QlsIQJ0K Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hello ! Attached patch adds support for PMC-Sierra Ocelot-3 in 2.6. This includes both 32-bit and 64-bit support. The patch for PCI will be sent next. Thanks Manish Lachwani --p4qYPpj5QlsIQJ0K Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename="common_mips_ocelot3.patch" Source: MontaVista Software, Inc. | Manish Lachwani Description: Support for PMC-Sierra Ocelot-3 in 2.6 (32-bit and 64-bit) Index: linux/arch/mips/Makefile =================================================================== --- linux.orig/arch/mips/Makefile +++ linux/arch/mips/Makefile @@ -436,6 +436,13 @@ load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 # +# Momentum Ocelot-3 +# +core-$(CONFIG_MOMENCO_OCELOT_3) += arch/mips/momentum/ocelot_3/ +cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3 +load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000 + +# # Momentum Jaguar ATX # core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/ Index: linux/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h =================================================================== --- /dev/null +++ linux/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h @@ -0,0 +1,40 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + */ +#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H + +/* + * Momentum Ocelot-3 is based on Rm7900 processor which + * is based on the E9000 core. + */ +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_subset_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 32 + +#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ Index: linux/include/asm-mips/serial.h =================================================================== --- linux.orig/include/asm-mips/serial.h +++ linux/include/asm-mips/serial.h @@ -319,6 +319,27 @@ #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS #endif +#ifdef CONFIG_MOMENCO_OCELOT_3 +#define OCELOT_3_BASE_BAUD ( 20000000 / 16 ) +#define OCELOT_3_SERIAL_IRQ 6 +#ifdef CONFIG_MIPS64 +#define OCELOT_3_SERIAL_BASE 0xfffffffffd000020 +#else +#define OCELOT_3_SERIAL_BASE 0xfd000020 +#endif + +#define _OCELOT_3_SERIAL_INIT(int, base) \ + { baud_base: OCELOT_3_BASE_BAUD, irq: int, \ + flags: STD_COM_FLAGS, \ + iomem_base: (u8 *) base, iomem_reg_shift: 2, \ + io_type: SERIAL_IO_MEM } + +#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ + _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE) +#else +#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS +#endif + #ifdef CONFIG_MOMENCO_OCELOT /* Ordinary NS16552 duart with a 20MHz crystal. */ #define OCELOT_BASE_BAUD ( 20000000 / 16 ) @@ -420,6 +441,7 @@ MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ + MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ TXX927_SERIAL_PORT_DEFNS \ AU1000_SERIAL_PORT_DEFNS Index: linux/drivers/net/Kconfig =================================================================== --- linux.orig/drivers/net/Kconfig +++ linux/drivers/net/Kconfig @@ -2170,7 +2170,7 @@ config MV643XX_ETH tristate "MV-643XX Ethernet support" - depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX + depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 help This driver supports the gigabit Ethernet on the Marvell MV643XX chipset which is used in the Momenco Ocelot C and Jaguar ATX. Index: linux/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h @@ -0,0 +1,61 @@ +/* + * Ocelot-3 Board Register Definitions + * + * (C) 2002 Momentum Computer Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + */ + +#ifndef __OCELOT_3_FPGA_H__ +#define __OCELOT_3_FPGA_H__ + +#ifdef CONFIG_MIPS64 +#define OCELOT_3_CS0_ADDR 0xfffffffffc000000 +#else +#define OCELOT_3_CS0_ADDR 0xfc000000 +#endif + +#define OCELOT_3_REG_BOARDREV 0x0 +#define OCELOT_3_REG_FPGA_REV 0x1 +#define OCELOT_3_REG_FPGA_TYPE 0x2 +#define OCELOT_3_REG_RESET_STATUS 0x3 +#define OCELOT_3_REG_BOARD_STATUS 0x4 +#define OCELOT_3_REG_CPCI_ID 0x5 +#define OCELOT_3_REG_SET 0x6 +#define OCELOT_3_REG_CLR 0x7 +#define OCELOT_3_REG_EEPROM_MODE 0x9 +#define OCELOT_3_REG_INTMASK 0xa +#define OCELOT_3_REG_INTSTAT 0xb +#define OCELOT_3_REG_UART_INTMASK 0xc +#define OCELOT_3_REG_UART_INTSTAT 0xd +#define OCELOT_3_REG_INTSET 0xe +#define OCELOT_3_REG_INTCLR 0xf + +#define OCELOT_FPGA_WRITE(x, y) writeb(x, OCELOT_3_CS0_ADDR + OCELOT_3_REG_##y) +#define OCELOT_FPGA_READ(x) readb(OCELOT_3_CS0_ADDR + OCELOT_3_REG_##x) + +#endif Index: linux/arch/mips/Kconfig =================================================================== --- linux.orig/arch/mips/Kconfig +++ linux/arch/mips/Kconfig @@ -329,6 +329,18 @@ The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer . +config MOMENCO_OCELOT_3 + bool "Support for Momentum Ocelot-3 board" + select DMA_NONCOHERENT + select IRQ_CPU + select IRQ_CPU_RM7K + select IRQ_MV64340 + select RM7000_CPU_SCACHE + select SWAP_IO_SPACE + help + The Ocelot-3 is based off Discovery III System Controller and + PMC-Sierra Rm79000 core. + config MOMENCO_JAGUAR_ATX bool "Support for Momentum Jaguar board" select DMA_NONCOHERENT @@ -1004,7 +1016,7 @@ config BOOT_ELF32 bool - depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI + depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI default y config MIPS_L1_CACHE_SHIFT Index: linux/include/asm-mips/bootinfo.h =================================================================== --- linux.orig/include/asm-mips/bootinfo.h +++ linux/include/asm-mips/bootinfo.h @@ -122,6 +122,7 @@ #define MACH_MOMENCO_OCELOT_G 1 #define MACH_MOMENCO_OCELOT_C 2 #define MACH_MOMENCO_JAGUAR_ATX 3 +#define MACH_MOMENCO_OCELOT_3 4 /* * Valid machtype for group ITE Index: linux/arch/mips/momentum/ocelot_3/reset.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/reset.c @@ -0,0 +1,64 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 1997, 2001 Ralf Baechle + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright (C) 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + */ +#include +#include +#include +#include +#include +#include +#include +#include + +void momenco_ocelot_restart(char *command) +{ + /* base address of timekeeper portion of part */ + void *nvram = (void *) +#ifdef CONFIG_MIPS64 + 0xfffffffffc807000; +#else + 0xfc807000; +#endif + + /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ + writeb(0x84, nvram + 0xff7); + + /* wait for the watchdog to go off */ + mdelay(100+(1000/16)); + + /* if the watchdog fails for some reason, let people know */ + printk(KERN_NOTICE "Watchdog reset failed\n"); +} + +void momenco_ocelot_halt(void) +{ + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void momenco_ocelot_power_off(void) +{ + momenco_ocelot_halt(); +} Index: linux/arch/mips/momentum/ocelot_3/prom.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/prom.c @@ -0,0 +1,259 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + */ +#include +#include +#include +#include + +#include +#include +#include +#include "ocelot_3_fpga.h" + +struct callvectors { + int (*open) (char*, int, int); + int (*close) (int); + int (*read) (int, void*, int); + int (*write) (int, void*, int); + off_t (*lseek) (int, off_t, int); + int (*printf) (const char*, ...); + void (*cacheflush) (void); + char* (*gets) (char*); +}; + +struct callvectors* debug_vectors; +extern unsigned long marvell_base; +extern unsigned long cpu_clock; + +#ifdef CONFIG_MV64340_ETH +extern unsigned char prom_mac_addr_base[6]; +#endif + +const char *get_system_type(void) +{ + return "Momentum Ocelot-3"; +} + +#ifdef CONFIG_MV64340_ETH +void burn_clocks(void) +{ + int i; + + /* this loop should burn at least 1us -- this should be plenty */ + for (i = 0; i < 0x10000; i++) + ; +} + +u8 exchange_bit(u8 val, u8 cs) +{ + /* place the data */ + OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE); + burn_clocks(); + + /* turn the clock on */ + OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE); + burn_clocks(); + + /* turn the clock off and read-strobe */ + OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); + + /* return the data */ + return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); +} + +void get_mac(char dest[6]) +{ + u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + int i,j; + + for (i = 0; i < 12; i++) + exchange_bit(read_opcode[i], 1); + + for (j = 0; j < 6; j++) { + dest[j] = 0; + for (i = 0; i < 8; i++) { + dest[j] <<= 1; + dest[j] |= exchange_bit(0, 1); + } + } + + /* turn off CS */ + exchange_bit(0,0); +} +#endif + + +#ifdef CONFIG_MIPS64 + +unsigned long signext(unsigned long addr) +{ + addr &= 0xffffffff; + return (unsigned long)((int)addr); +} + +void *get_arg(unsigned long args, int arc) +{ + unsigned long ul; + unsigned char *puc, uc; + + args += (arc * 4); + ul = (unsigned long)signext(args); + puc = (unsigned char *)ul; + if (puc == 0) + return (void *)0; + +#ifdef CONFIG_CPU_LITTLE_ENDIAN + uc = *puc++; + ul = (unsigned long)uc; + uc = *puc++; + ul |= (((unsigned long)uc) << 8); + uc = *puc++; + ul |= (((unsigned long)uc) << 16); + uc = *puc++; + ul |= (((unsigned long)uc) << 24); +#else /* CONFIG_CPU_LITTLE_ENDIAN */ + uc = *puc++; + ul = ((unsigned long)uc) << 24; + uc = *puc++; + ul |= (((unsigned long)uc) << 16); + uc = *puc++; + ul |= (((unsigned long)uc) << 8); + uc = *puc++; + ul |= ((unsigned long)uc); +#endif /* CONFIG_CPU_LITTLE_ENDIAN */ + ul = signext(ul); + return (void *)ul; +} + +char *arg64(unsigned long addrin, int arg_index) +{ + unsigned long args; + char *p; + + args = signext(addrin); + p = (char *)get_arg(args, arg_index); + + return p; +} +#endif /* CONFIG_MIPS64 */ + +void __init prom_init(void) +{ + int argc = fw_arg0; + char **arg = (char **) fw_arg1; + char **env = (char **) fw_arg2; + struct callvectors *cv = (struct callvectors *) fw_arg3; + int i; + +#ifdef CONFIG_MIPS64 + char *ptr; + printk("prom_init - MIPS64\n"); + + /* save the PROM vectors for debugging use */ + debug_vectors = (struct callvectors *)signext((unsigned long)cv); + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + + for (i = 1; i < argc; i++) { + ptr = (char *)arg64((unsigned long)arg, i); + if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >= + sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ptr); + strcat(arcs_cmdline, " "); + } + i = 0; + + while (1) { + ptr = (char *)arg64((unsigned long)env, i); + if (! ptr) + break; + + if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) { + marvell_base = simple_strtol(ptr + strlen("gtbase="), + NULL, 16); + + if ((marvell_base & 0xffffffff00000000) == 0) + marvell_base |= 0xffffffff00000000; + + printk("marvell_base set to 0x%016lx\n", marvell_base); + } + if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) { + cpu_clock = simple_strtol(ptr + strlen("cpuclock="), + NULL, 10); + printk("cpu_clock set to %d\n", cpu_clock); + } + i++; + } + printk("arcs_cmdline: %s\n", arcs_cmdline); + +#else /* CONFIG_MIPS64 */ + + /* save the PROM vectors for debugging use */ + debug_vectors = cv; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < argc; i++) { + if (strlen(arcs_cmdline) + strlen(arg[i] + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, arg[i]); + strcat(arcs_cmdline, " "); + } + + while (*env) { + if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { + marvell_base = simple_strtol(*env + strlen("gtbase="), + NULL, 16); + } + if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) { + cpu_clock = simple_strtol(*env + strlen("cpuclock="), + NULL, 10); + } + env++; + } +#endif /* CONFIG_MIPS64 */ + + mips_machgroup = MACH_GROUP_MOMENCO; + mips_machtype = MACH_MOMENCO_OCELOT_3; + +#ifdef CONFIG_MV64340_ETH + /* get the base MAC address for on-board ethernet ports */ + get_mac(prom_mac_addr_base); +#endif + +#ifndef CONFIG_MIPS64 + debug_vectors->printf("Booting Linux kernel...\n"); +#endif +} + +void __init prom_free_prom_memory(void) +{ +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ +} Index: linux/arch/mips/momentum/ocelot_3/Makefile =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for Momentum Computer's Ocelot-3 board. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# +obj-y += int-handler.o irq.o prom.o reset.o setup.o Index: linux/arch/mips/momentum/ocelot_3/int-handler.S =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/int-handler.S @@ -0,0 +1,138 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * First-level interrupt dispatcher for Ocelot-3 board. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include "ocelot_3_fpga.h" + +/* + * First level interrupt dispatcher for Ocelot-3 board + */ + .align 5 + NESTED(ocelot3_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 t0, CP0_CAUSE + mfc0 t2, CP0_STATUS + + and t0, t2 + + andi t1, t0, STATUSF_IP0 /* sw0 software interrupt (IRQ0) */ + bnez t1, ll_sw0_irq + + andi t1, t0, STATUSF_IP1 /* sw1 software interrupt (IRQ1) */ + bnez t1, ll_sw1_irq + + andi t1, t0, STATUSF_IP2 /* int0 hardware line (IRQ2) */ + bnez t1, ll_pci0slot1_irq + + andi t1, t0, STATUSF_IP3 /* int1 hardware line (IRQ3) */ + bnez t1, ll_pci0slot2_irq + + andi t1, t0, STATUSF_IP4 /* int2 hardware line (IRQ4) */ + bnez t1, ll_pci1slot1_irq + + andi t1, t0, STATUSF_IP5 /* int3 hardware line (IRQ5) */ + bnez t1, ll_pci1slot2_irq + + andi t1, t0, STATUSF_IP6 /* int4 hardware line (IRQ6) */ + bnez t1, ll_uart_irq + + andi t1, t0, STATUSF_IP7 /* cpu timer (IRQ7) */ + bnez t1, ll_cputimer_irq + + /* now look at extended interrupts */ + mfc0 t0, CP0_CAUSE + cfc0 t1, CP0_S1_INTCONTROL + + /* shift the mask 8 bits left to line up the bits */ + sll t2, t1, 8 + + and t0, t2 + srl t0, t0, 16 + + andi t1, t0, STATUSF_IP8 /* int6 hardware line (IRQ9) */ + bnez t1, ll_mv64340_decode_irq + + .set reorder + + /* wrong alarm or masked ... */ + j spurious_interrupt + nop + END(ocelot3_handle_int) + + .align 5 +ll_sw0_irq: + li a0, 0 /* IRQ 1 */ + move a1, sp + jal do_IRQ + j ret_from_irq +ll_sw1_irq: + li a0, 1 /* IRQ 2 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci0slot1_irq: + li a0, 2 /* IRQ 3 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci0slot2_irq: + li a0, 3 /* IRQ 4 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci1slot1_irq: + li a0, 4 /* IRQ 5 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci1slot2_irq: + li a0, 5 /* IRQ 6 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_uart_irq: + li a0, 6 /* IRQ 7 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cputimer_irq: + li a0, 7 /* IRQ 8 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_mv64340_decode_irq: + move a0, sp + jal ll_mv64340_irq + j ret_from_irq + Index: linux/arch/mips/momentum/ocelot_3/irq.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/irq.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern asmlinkage void ocelot3_handle_int(void); + +static struct irqaction cascade_mv64340 = { + no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL +}; + +void __init arch_init_irq(void) +{ + /* + * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap + */ + clear_c0_status(ST0_IM | ST0_BEV); + + /* Sets the first-level interrupt dispatcher. */ + set_except_vector(0, ocelot3_handle_int); + mips_cpu_irq_init(0); + rm7k_cpu_irq_init(8); + + /* set up the cascading interrupts */ + setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */ + mv64340_irq_init(16); + + set_c0_status(ST0_IM); /* IE in the status register */ + +} Index: linux/arch/mips/momentum/ocelot_3/setup.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/setup.c @@ -0,0 +1,312 @@ +/* + * setup.c + * + * BRIEF MODULE DESCRIPTION + * Momentum Computer Ocelot-3 board dependent boot routines + * + * Copyright (C) 1996, 1997, 2001 Ralf Baechle + * Copyright (C) 2000 RidgeRun, Inc. + * Copyright (C) 2001 Red Hat, Inc. + * Copyright (C) 2002 Momentum Computer + * + * Author: Matthew Dharm, Momentum Computer + * mdharm@momenco.com + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ocelot_3_fpga.h" + +/* Marvell Discovery Register Base */ +unsigned long marvell_base; +/* Serial */ +unsigned long uart_base; +/* CPU clock */ +unsigned long cpu_clock; +/* RTC/NVRAM */ +unsigned char* rtc_base; + +/* + * Marvell Discovery SRAM. This is one place where Ethernet + * Tx and Rx descriptors can be placed to improve performance + */ +extern unsigned long mv64340_sram_base; + + +/* These functions are used for rebooting or halting the machine*/ +extern void momenco_ocelot_restart(char *command); +extern void momenco_ocelot_halt(void); +extern void momenco_ocelot_power_off(void); + +void momenco_time_init(void); +static char reset_reason; + +void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask); + +#define ENTRYLO(x) (((x & PAGE_MASK) | (_PAGE_PRESENT | __READABLE | \ + __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)) >> 6) + +void __init bus_error_init(void) +{ + /* nothing */ +} + +/* + * setup code for a handoff from a version 2 PMON 2000 PROM + */ +void setup_wired_tlb_entries(void) +{ +#ifdef CONFIG_MIPS64 + /* marvell and extra space */ + add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), + 0xfffffffff4000000, PM_64K); + + /* fpga, rtc, and uart */ + add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), + 0xfffffffffc000000, PM_16M); + + marvell_base = 0xfffffffff4000000; + uart_base = 0xfffffffffd000000; + rtc_base = (unsigned char*)0xfffffffffc800000; +#else + write_c0_wired(0); + local_flush_tlb_all(); + + /* marvell and extra space */ + add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K); + + /* fpga, rtc, and uart */ + add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M); + + marvell_base = 0xf4000000; + uart_base = 0xfd000000; + rtc_base = (unsigned char*)0xfc800000; +#endif +} + +#define CONV_BCD_TO_BIN(val) (((val) & 0xf) + (((val) >> 4) * 10)) +#define CONV_BIN_TO_BCD(val) (((val) % 10) + (((val) / 10) << 4)) + +unsigned long m48t37y_get_time(void) +{ + unsigned int year, month, day, hour, min, sec; + + /* stop the update */ + rtc_base[0x7ff8] = 0x40; + + year = CONV_BCD_TO_BIN(rtc_base[0x7fff]); + year += CONV_BCD_TO_BIN(rtc_base[0x7ff1]) * 100; + + month = CONV_BCD_TO_BIN(rtc_base[0x7ffe]); + + day = CONV_BCD_TO_BIN(rtc_base[0x7ffd]); + + hour = CONV_BCD_TO_BIN(rtc_base[0x7ffb]); + min = CONV_BCD_TO_BIN(rtc_base[0x7ffa]); + sec = CONV_BCD_TO_BIN(rtc_base[0x7ff9]); + + /* start the update */ + rtc_base[0x7ff8] = 0x00; + + return mktime(year, month, day, hour, min, sec); +} + +int m48t37y_set_time(unsigned long sec) +{ + struct rtc_time tm; + + /* convert to a more useful format -- note months count from 0 */ + to_tm(sec, &tm); + tm.tm_mon += 1; + + /* enable writing */ + rtc_base[0x7ff8] = 0x80; + + /* year */ + rtc_base[0x7fff] = CONV_BIN_TO_BCD(tm.tm_year % 100); + rtc_base[0x7ff1] = CONV_BIN_TO_BCD(tm.tm_year / 100); + + /* month */ + rtc_base[0x7ffe] = CONV_BIN_TO_BCD(tm.tm_mon); + + /* day */ + rtc_base[0x7ffd] = CONV_BIN_TO_BCD(tm.tm_mday); + + /* hour/min/sec */ + rtc_base[0x7ffb] = CONV_BIN_TO_BCD(tm.tm_hour); + rtc_base[0x7ffa] = CONV_BIN_TO_BCD(tm.tm_min); + rtc_base[0x7ff9] = CONV_BIN_TO_BCD(tm.tm_sec); + + /* day of week -- not really used, but let's keep it up-to-date */ + rtc_base[0x7ffc] = CONV_BIN_TO_BCD(tm.tm_wday + 1); + + /* disable writing */ + rtc_base[0x7ff8] = 0x00; + + return 0; +} + +void momenco_timer_setup(struct irqaction *irq) +{ + setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */ +} + +void momenco_time_init(void) +{ + setup_wired_tlb_entries(); + + /* + * Ocelot-3 board has been built with both + * the Rm7900 and the Rm7065C + */ + mips_hpt_frequency = cpu_clock / 2; + board_timer_setup = momenco_timer_setup; + + rtc_get_time = m48t37y_get_time; + rtc_set_time = m48t37y_set_time; +} + +static int __init momenco_ocelot_3_setup(void) +{ + unsigned int tmpword; + + board_time_init = momenco_time_init; + + _machine_restart = momenco_ocelot_restart; + _machine_halt = momenco_ocelot_halt; + _machine_power_off = momenco_ocelot_power_off; + + /* Wired TLB entries */ + setup_wired_tlb_entries(); + + /* shut down ethernet ports, just to be sure our memory doesn't get + * corrupted by random ethernet traffic. + */ + MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); + MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); + do {} + while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); + do {} + while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); + do {} + while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); + do {} + while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); + MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), + MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); + MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), + MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); + + /* Turn off the Bit-Error LED */ + OCELOT_FPGA_WRITE(0x80, CLR); + + tmpword = OCELOT_FPGA_READ(BOARDREV); + if (tmpword < 26) + printk("Momenco Ocelot-3: Board Assembly Rev. %c\n", + 'A'+tmpword); + else + printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n", + tmpword); + + tmpword = OCELOT_FPGA_READ(FPGA_REV); + printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); + tmpword = OCELOT_FPGA_READ(RESET_STATUS); + printk("Reset reason: 0x%x\n", tmpword); + switch (tmpword) { + case 0x1: + printk(" - Power-up reset\n"); + break; + case 0x2: + printk(" - Push-button reset\n"); + break; + case 0x4: + printk(" - cPCI bus reset\n"); + break; + case 0x8: + printk(" - Watchdog reset\n"); + break; + case 0x10: + printk(" - Software reset\n"); + break; + default: + printk(" - Unknown reset cause\n"); + } + reset_reason = tmpword; + OCELOT_FPGA_WRITE(0xff, RESET_STATUS); + + tmpword = OCELOT_FPGA_READ(CPCI_ID); + printk("cPCI ID register: 0x%02x\n", tmpword); + printk(" - Slot number: %d\n", tmpword & 0x1f); + printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); + printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); + + tmpword = OCELOT_FPGA_READ(BOARD_STATUS); + printk("Board Status register: 0x%02x\n", tmpword); + printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); + printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); + printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1); + + /* Support for 128 MB memory */ + add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM); + + return 0; +} + +early_initcall(momenco_ocelot_3_setup); Index: linux/arch/mips/configs/ocelot_3_defconfig =================================================================== --- /dev/null +++ linux/arch/mips/configs/ocelot_3_defconfig @@ -0,0 +1,719 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.10-rc1 +# Tue Nov 2 12:08:59 2004 +# +CONFIG_MIPS=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set +CONFIG_MIPS32=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_HOTPLUG is not set +CONFIG_KOBJECT_UEVENT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +# CONFIG_TINY_SHMEM is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_MACH_JAZZ is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +CONFIG_MOMENCO_OCELOT_3=y +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_HAVE_DEC_LOCK=y +CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_IRQ_CPU=y +CONFIG_IRQ_CPU_RM7K=y +CONFIG_IRQ_MV64340=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_FB=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_RM9000=y +# CONFIG_CPU_SB1 is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_BOARD_SCACHE=y +CONFIG_RM7000_CPU_SCACHE=y +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_HIGHMEM is not set +# CONFIG_SMP is not set +# CONFIG_PREEMPT is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_MMU=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_LBD is not set +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=m +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +# CONFIG_BLK_DEV_SD is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set + +# +# SCSI low-level drivers +# +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_QLOGIC_1280_1040 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK_DEV=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_IPV6_TUNNEL is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +# CONFIG_IP_NF_CONNTRACK_MARK is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set +# CONFIG_IP_NF_COMPAT_IPFWADM is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y + +# +# Ethernet (1000 Mbit) +# +CONFIG_MV643XX_ETH=y +CONFIG_MV643XX_ETH_0=y +CONFIG_MV643XX_ETH_1=y +CONFIG_MV643XX_ETH_2=y + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +CONFIG_PPPOE=m +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_RAW is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Misc devices +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y + +# +# Logo configuration +# +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_RT is not set +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=m + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_SYSFS=y +CONFIG_DEVFS_FS=y +CONFIG_DEVFS_MOUNT=y +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +CONFIG_EFS_FS=y +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V4 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_DEBUG_KERNEL is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="ip=any root=nfs" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_CRC_CCITT=m +CONFIG_CRC32=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y --p4qYPpj5QlsIQJ0K-- From ralf@linux-mips.org Tue Nov 2 21:44:44 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2004 21:44:48 +0000 (GMT) Received: from p508B6BBF.dip.t-dialin.net ([IPv6:::ffff:80.139.107.191]:22552 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Tue, 2 Nov 2004 21:44:44 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.12.11/8.12.8) with ESMTP id iA2MiWqK030739; Tue, 2 Nov 2004 23:44:32 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.12.11/8.12.11/Submit) id iA2MiSjR030738; Tue, 2 Nov 2004 23:44:28 +0100 Date: Tue, 2 Nov 2004 23:44:28 +0100 From: Ralf Baechle To: Manish Lachwani Cc: linux-mips@linux-mips.org Subject: Re: [PATCH]MTD Support for Malta in 2.6.10 Message-ID: <20041102224428.GB28025@linux-mips.org> References: <20041101180453.GB10943@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041101180453.GB10943@prometheus.mvista.com> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6251 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 161 Lines: 7 On Mon, Nov 01, 2004 at 10:04:53AM -0800, Manish Lachwani wrote: > Attached patch gets MTD to work on the Malta board in 2.6.10. Please review ... Ok. Ralf From ralf@linux-mips.org Tue Nov 2 22:07:34 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2004 22:07:38 +0000 (GMT) Received: from p508B6BBF.dip.t-dialin.net ([IPv6:::ffff:80.139.107.191]:36120 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Tue, 2 Nov 2004 22:07:34 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.12.11/8.12.8) with ESMTP id iA2N7Xir031291; Wed, 3 Nov 2004 00:07:33 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.12.11/8.12.11/Submit) id iA2N7X2k031290; Wed, 3 Nov 2004 00:07:33 +0100 Date: Wed, 3 Nov 2004 00:07:33 +0100 From: Ralf Baechle To: Manish Lachwani Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Support for PMC-Sierra Ocelot-3 in 2.6 Message-ID: <20041102230733.GC28025@linux-mips.org> References: <20041102201720.GB24674@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041102201720.GB24674@prometheus.mvista.com> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6252 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 256 Lines: 12 On Tue, Nov 02, 2004 at 12:17:20PM -0800, Manish Lachwani wrote: > +#ifdef CONFIG_MIPS64 > + 0xfffffffffc807000; > +#else > + 0xfc807000; > +#endif Ouch. Rather ugly. I suggest you rely on the implicit sign extension of the compiler instead. Ralf From mlachwani@mvista.com Tue Nov 2 22:09:35 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Nov 2004 22:09:40 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:8692 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Tue, 2 Nov 2004 22:09:35 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 5D9AE185D1; Tue, 2 Nov 2004 14:09:33 -0800 (PST) Message-ID: <4188059D.1000601@mvista.com> Date: Tue, 02 Nov 2004 14:09:33 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: Ralf Baechle Cc: Manish Lachwani , linux-mips@linux-mips.org Subject: Re: [PATCH] Support for PMC-Sierra Ocelot-3 in 2.6 References: <20041102201720.GB24674@prometheus.mvista.com> <20041102230733.GC28025@linux-mips.org> In-Reply-To: <20041102230733.GC28025@linux-mips.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6253 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 391 Lines: 21 Ralf Baechle wrote: > On Tue, Nov 02, 2004 at 12:17:20PM -0800, Manish Lachwani wrote: > > >>+#ifdef CONFIG_MIPS64 >>+ 0xfffffffffc807000; >>+#else >>+ 0xfc807000; >>+#endif > > > Ouch. Rather ugly. I suggest you rely on the implicit sign extension > of the compiler instead. > > Ralf > Got it. Will send a patch with the changes and with PCI included Thanks Manish Lachwani From mlachwani@prometheus.mvista.com Wed Nov 3 03:10:34 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Nov 2004 03:10:47 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:46064 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Wed, 3 Nov 2004 03:10:34 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iA33AUdh017963 for ; Tue, 2 Nov 2004 19:10:31 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iA33AUfX017961 for linux-mips@linux-mips.org; Tue, 2 Nov 2004 19:10:30 -0800 Date: Tue, 2 Nov 2004 19:10:30 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Subject: [PATCH] Support for PMC-Sierra Ocelot-3 in 2.6 (32-bit and 64-bit) Message-ID: <20041103031030.GA17954@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="17pEHd4RhPHOinZp" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6254 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 47860 Lines: 1846 --17pEHd4RhPHOinZp Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hello Ralf, Attached patch after your comments. This patch does not support PCI as yet. Please apply Thanks Manish Lachwani --17pEHd4RhPHOinZp Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename="common_mips_ocelot3.patch" Source: MontaVista Software, Inc. | http://www.mvista.com | Manish Lachwani Type: Enhancement Disposition: Submitted to linux-mips@linux-mips.org Description: Support for PMC-Sierra Ocelot-3 in 2.6 (32-bit and 64-bit) Index: linux/arch/mips/Makefile =================================================================== --- linux.orig/arch/mips/Makefile +++ linux/arch/mips/Makefile @@ -436,6 +436,13 @@ load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 # +# Momentum Ocelot-3 +# +core-$(CONFIG_MOMENCO_OCELOT_3) += arch/mips/momentum/ocelot_3/ +cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3 +load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000 + +# # Momentum Jaguar ATX # core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/ Index: linux/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h =================================================================== --- /dev/null +++ linux/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h @@ -0,0 +1,40 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + */ +#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H + +/* + * Momentum Ocelot-3 is based on Rm7900 processor which + * is based on the E9000 core. + */ +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_subset_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 32 + +#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ Index: linux/include/asm-mips/serial.h =================================================================== --- linux.orig/include/asm-mips/serial.h +++ linux/include/asm-mips/serial.h @@ -319,6 +319,23 @@ #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS #endif +#ifdef CONFIG_MOMENCO_OCELOT_3 +#define OCELOT_3_BASE_BAUD ( 20000000 / 16 ) +#define OCELOT_3_SERIAL_IRQ 6 +#define OCELOT_3_SERIAL_BASE (signed)0xfd000020 + +#define _OCELOT_3_SERIAL_INIT(int, base) \ + { baud_base: OCELOT_3_BASE_BAUD, irq: int, \ + flags: STD_COM_FLAGS, \ + iomem_base: (u8 *) base, iomem_reg_shift: 2, \ + io_type: SERIAL_IO_MEM } + +#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ + _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE) +#else +#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS +#endif + #ifdef CONFIG_MOMENCO_OCELOT /* Ordinary NS16552 duart with a 20MHz crystal. */ #define OCELOT_BASE_BAUD ( 20000000 / 16 ) @@ -420,6 +437,7 @@ MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ + MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ TXX927_SERIAL_PORT_DEFNS \ AU1000_SERIAL_PORT_DEFNS Index: linux/drivers/net/Kconfig =================================================================== --- linux.orig/drivers/net/Kconfig +++ linux/drivers/net/Kconfig @@ -2170,7 +2170,7 @@ config MV643XX_ETH tristate "MV-643XX Ethernet support" - depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX + depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 help This driver supports the gigabit Ethernet on the Marvell MV643XX chipset which is used in the Momenco Ocelot C and Jaguar ATX. Index: linux/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h @@ -0,0 +1,57 @@ +/* + * Ocelot-3 Board Register Definitions + * + * (C) 2002 Momentum Computer Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + */ + +#ifndef __OCELOT_3_FPGA_H__ +#define __OCELOT_3_FPGA_H__ + +#define OCELOT_3_REG_BOARDREV 0x0 +#define OCELOT_3_REG_FPGA_REV 0x1 +#define OCELOT_3_REG_FPGA_TYPE 0x2 +#define OCELOT_3_REG_RESET_STATUS 0x3 +#define OCELOT_3_REG_BOARD_STATUS 0x4 +#define OCELOT_3_REG_CPCI_ID 0x5 +#define OCELOT_3_REG_SET 0x6 +#define OCELOT_3_REG_CLR 0x7 +#define OCELOT_3_REG_EEPROM_MODE 0x9 +#define OCELOT_3_REG_INTMASK 0xa +#define OCELOT_3_REG_INTSTAT 0xb +#define OCELOT_3_REG_UART_INTMASK 0xc +#define OCELOT_3_REG_UART_INTSTAT 0xd +#define OCELOT_3_REG_INTSET 0xe +#define OCELOT_3_REG_INTCLR 0xf + +extern unsigned long ocelot_fpga_base; + +#define OCELOT_FPGA_WRITE(x, y) writeb(x, ocelot_fpga_base + OCELOT_3_REG_##y) +#define OCELOT_FPGA_READ(x) readb(ocelot_fpga_base + OCELOT_3_REG_##x) + +#endif Index: linux/arch/mips/Kconfig =================================================================== --- linux.orig/arch/mips/Kconfig +++ linux/arch/mips/Kconfig @@ -329,6 +329,18 @@ The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer . +config MOMENCO_OCELOT_3 + bool "Support for Momentum Ocelot-3 board" + select DMA_NONCOHERENT + select IRQ_CPU + select IRQ_CPU_RM7K + select IRQ_MV64340 + select RM7000_CPU_SCACHE + select SWAP_IO_SPACE + help + The Ocelot-3 is based off Discovery III System Controller and + PMC-Sierra Rm79000 core. + config MOMENCO_JAGUAR_ATX bool "Support for Momentum Jaguar board" select DMA_NONCOHERENT @@ -1004,7 +1016,7 @@ config BOOT_ELF32 bool - depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI + depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI default y config MIPS_L1_CACHE_SHIFT Index: linux/include/asm-mips/bootinfo.h =================================================================== --- linux.orig/include/asm-mips/bootinfo.h +++ linux/include/asm-mips/bootinfo.h @@ -122,6 +122,7 @@ #define MACH_MOMENCO_OCELOT_G 1 #define MACH_MOMENCO_OCELOT_C 2 #define MACH_MOMENCO_JAGUAR_ATX 3 +#define MACH_MOMENCO_OCELOT_3 4 /* * Valid machtype for group ITE Index: linux/arch/mips/momentum/ocelot_3/reset.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/reset.c @@ -0,0 +1,60 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 1997, 2001 Ralf Baechle + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright (C) 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void momenco_ocelot_restart(char *command) +{ + /* base address of timekeeper portion of part */ + void *nvram = (void *) 0xfc807000L; + + /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ + writeb(0x84, nvram + 0xff7); + + /* wait for the watchdog to go off */ + mdelay(100+(1000/16)); + + /* if the watchdog fails for some reason, let people know */ + printk(KERN_NOTICE "Watchdog reset failed\n"); +} + +void momenco_ocelot_halt(void) +{ + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void momenco_ocelot_power_off(void) +{ + momenco_ocelot_halt(); +} Index: linux/arch/mips/momentum/ocelot_3/prom.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/prom.c @@ -0,0 +1,259 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + */ +#include +#include +#include +#include + +#include +#include +#include +#include "ocelot_3_fpga.h" + +struct callvectors { + int (*open) (char*, int, int); + int (*close) (int); + int (*read) (int, void*, int); + int (*write) (int, void*, int); + off_t (*lseek) (int, off_t, int); + int (*printf) (const char*, ...); + void (*cacheflush) (void); + char* (*gets) (char*); +}; + +struct callvectors* debug_vectors; +extern unsigned long marvell_base; +extern unsigned long cpu_clock; + +#ifdef CONFIG_MV64340_ETH +extern unsigned char prom_mac_addr_base[6]; +#endif + +const char *get_system_type(void) +{ + return "Momentum Ocelot-3"; +} + +#ifdef CONFIG_MV64340_ETH +void burn_clocks(void) +{ + int i; + + /* this loop should burn at least 1us -- this should be plenty */ + for (i = 0; i < 0x10000; i++) + ; +} + +u8 exchange_bit(u8 val, u8 cs) +{ + /* place the data */ + OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE); + burn_clocks(); + + /* turn the clock on */ + OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE); + burn_clocks(); + + /* turn the clock off and read-strobe */ + OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); + + /* return the data */ + return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); +} + +void get_mac(char dest[6]) +{ + u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + int i,j; + + for (i = 0; i < 12; i++) + exchange_bit(read_opcode[i], 1); + + for (j = 0; j < 6; j++) { + dest[j] = 0; + for (i = 0; i < 8; i++) { + dest[j] <<= 1; + dest[j] |= exchange_bit(0, 1); + } + } + + /* turn off CS */ + exchange_bit(0,0); +} +#endif + + +#ifdef CONFIG_MIPS64 + +unsigned long signext(unsigned long addr) +{ + addr &= 0xffffffff; + return (unsigned long)((int)addr); +} + +void *get_arg(unsigned long args, int arc) +{ + unsigned long ul; + unsigned char *puc, uc; + + args += (arc * 4); + ul = (unsigned long)signext(args); + puc = (unsigned char *)ul; + if (puc == 0) + return (void *)0; + +#ifdef CONFIG_CPU_LITTLE_ENDIAN + uc = *puc++; + ul = (unsigned long)uc; + uc = *puc++; + ul |= (((unsigned long)uc) << 8); + uc = *puc++; + ul |= (((unsigned long)uc) << 16); + uc = *puc++; + ul |= (((unsigned long)uc) << 24); +#else /* CONFIG_CPU_LITTLE_ENDIAN */ + uc = *puc++; + ul = ((unsigned long)uc) << 24; + uc = *puc++; + ul |= (((unsigned long)uc) << 16); + uc = *puc++; + ul |= (((unsigned long)uc) << 8); + uc = *puc++; + ul |= ((unsigned long)uc); +#endif /* CONFIG_CPU_LITTLE_ENDIAN */ + ul = signext(ul); + return (void *)ul; +} + +char *arg64(unsigned long addrin, int arg_index) +{ + unsigned long args; + char *p; + + args = signext(addrin); + p = (char *)get_arg(args, arg_index); + + return p; +} +#endif /* CONFIG_MIPS64 */ + +void __init prom_init(void) +{ + int argc = fw_arg0; + char **arg = (char **) fw_arg1; + char **env = (char **) fw_arg2; + struct callvectors *cv = (struct callvectors *) fw_arg3; + int i; + +#ifdef CONFIG_MIPS64 + char *ptr; + printk("prom_init - MIPS64\n"); + + /* save the PROM vectors for debugging use */ + debug_vectors = (struct callvectors *)signext((unsigned long)cv); + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + + for (i = 1; i < argc; i++) { + ptr = (char *)arg64((unsigned long)arg, i); + if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >= + sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ptr); + strcat(arcs_cmdline, " "); + } + i = 0; + + while (1) { + ptr = (char *)arg64((unsigned long)env, i); + if (! ptr) + break; + + if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) { + marvell_base = simple_strtol(ptr + strlen("gtbase="), + NULL, 16); + + if ((marvell_base & 0xffffffff00000000) == 0) + marvell_base |= 0xffffffff00000000; + + printk("marvell_base set to 0x%016lx\n", marvell_base); + } + if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) { + cpu_clock = simple_strtol(ptr + strlen("cpuclock="), + NULL, 10); + printk("cpu_clock set to %d\n", cpu_clock); + } + i++; + } + printk("arcs_cmdline: %s\n", arcs_cmdline); + +#else /* CONFIG_MIPS64 */ + + /* save the PROM vectors for debugging use */ + debug_vectors = cv; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < argc; i++) { + if (strlen(arcs_cmdline) + strlen(arg[i] + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, arg[i]); + strcat(arcs_cmdline, " "); + } + + while (*env) { + if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { + marvell_base = simple_strtol(*env + strlen("gtbase="), + NULL, 16); + } + if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) { + cpu_clock = simple_strtol(*env + strlen("cpuclock="), + NULL, 10); + } + env++; + } +#endif /* CONFIG_MIPS64 */ + + mips_machgroup = MACH_GROUP_MOMENCO; + mips_machtype = MACH_MOMENCO_OCELOT_3; + +#ifdef CONFIG_MV64340_ETH + /* get the base MAC address for on-board ethernet ports */ + get_mac(prom_mac_addr_base); +#endif + +#ifndef CONFIG_MIPS64 + debug_vectors->printf("Booting Linux kernel...\n"); +#endif +} + +void __init prom_free_prom_memory(void) +{ +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ +} Index: linux/arch/mips/momentum/ocelot_3/Makefile =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for Momentum Computer's Ocelot-3 board. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# +obj-y += int-handler.o irq.o prom.o reset.o setup.o Index: linux/arch/mips/momentum/ocelot_3/int-handler.S =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/int-handler.S @@ -0,0 +1,137 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * First-level interrupt dispatcher for Ocelot-3 board. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include + +/* + * First level interrupt dispatcher for Ocelot-3 board + */ + .align 5 + NESTED(ocelot3_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 t0, CP0_CAUSE + mfc0 t2, CP0_STATUS + + and t0, t2 + + andi t1, t0, STATUSF_IP0 /* sw0 software interrupt (IRQ0) */ + bnez t1, ll_sw0_irq + + andi t1, t0, STATUSF_IP1 /* sw1 software interrupt (IRQ1) */ + bnez t1, ll_sw1_irq + + andi t1, t0, STATUSF_IP2 /* int0 hardware line (IRQ2) */ + bnez t1, ll_pci0slot1_irq + + andi t1, t0, STATUSF_IP3 /* int1 hardware line (IRQ3) */ + bnez t1, ll_pci0slot2_irq + + andi t1, t0, STATUSF_IP4 /* int2 hardware line (IRQ4) */ + bnez t1, ll_pci1slot1_irq + + andi t1, t0, STATUSF_IP5 /* int3 hardware line (IRQ5) */ + bnez t1, ll_pci1slot2_irq + + andi t1, t0, STATUSF_IP6 /* int4 hardware line (IRQ6) */ + bnez t1, ll_uart_irq + + andi t1, t0, STATUSF_IP7 /* cpu timer (IRQ7) */ + bnez t1, ll_cputimer_irq + + /* now look at extended interrupts */ + mfc0 t0, CP0_CAUSE + cfc0 t1, CP0_S1_INTCONTROL + + /* shift the mask 8 bits left to line up the bits */ + sll t2, t1, 8 + + and t0, t2 + srl t0, t0, 16 + + andi t1, t0, STATUSF_IP8 /* int6 hardware line (IRQ9) */ + bnez t1, ll_mv64340_decode_irq + + .set reorder + + /* wrong alarm or masked ... */ + j spurious_interrupt + nop + END(ocelot3_handle_int) + + .align 5 +ll_sw0_irq: + li a0, 0 /* IRQ 1 */ + move a1, sp + jal do_IRQ + j ret_from_irq +ll_sw1_irq: + li a0, 1 /* IRQ 2 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci0slot1_irq: + li a0, 2 /* IRQ 3 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci0slot2_irq: + li a0, 3 /* IRQ 4 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci1slot1_irq: + li a0, 4 /* IRQ 5 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci1slot2_irq: + li a0, 5 /* IRQ 6 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_uart_irq: + li a0, 6 /* IRQ 7 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cputimer_irq: + li a0, 7 /* IRQ 8 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_mv64340_decode_irq: + move a0, sp + jal ll_mv64340_irq + j ret_from_irq + Index: linux/arch/mips/momentum/ocelot_3/irq.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/irq.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern asmlinkage void ocelot3_handle_int(void); + +static struct irqaction cascade_mv64340 = { + no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL +}; + +void __init arch_init_irq(void) +{ + /* + * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap + */ + clear_c0_status(ST0_IM | ST0_BEV); + + /* Sets the first-level interrupt dispatcher. */ + set_except_vector(0, ocelot3_handle_int); + mips_cpu_irq_init(0); + rm7k_cpu_irq_init(8); + + /* set up the cascading interrupts */ + setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */ + mv64340_irq_init(16); + + set_c0_status(ST0_IM); /* IE in the status register */ + +} Index: linux/arch/mips/momentum/ocelot_3/setup.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/setup.c @@ -0,0 +1,304 @@ +/* + * setup.c + * + * BRIEF MODULE DESCRIPTION + * Momentum Computer Ocelot-3 board dependent boot routines + * + * Copyright (C) 1996, 1997, 2001 Ralf Baechle + * Copyright (C) 2000 RidgeRun, Inc. + * Copyright (C) 2001 Red Hat, Inc. + * Copyright (C) 2002 Momentum Computer + * + * Author: Matthew Dharm, Momentum Computer + * mdharm@momenco.com + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ocelot_3_fpga.h" + +/* Marvell Discovery Register Base */ +unsigned long marvell_base = (signed)0xf4000000; + +/* CPU clock */ +unsigned long cpu_clock; + +/* RTC/NVRAM */ +unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000; + +/* FPGA Base */ +unsigned long ocelot_fpga_base = (signed)0xfc000000; + +/* Serial base */ +unsigned long uart_base = (signed)0xfd000000; + +/* + * Marvell Discovery SRAM. This is one place where Ethernet + * Tx and Rx descriptors can be placed to improve performance + */ +extern unsigned long mv64340_sram_base; + +/* These functions are used for rebooting or halting the machine*/ +extern void momenco_ocelot_restart(char *command); +extern void momenco_ocelot_halt(void); +extern void momenco_ocelot_power_off(void); + +void momenco_time_init(void); +static char reset_reason; + +void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask); + +static inline unsigned long ENTRYLO(unsigned long paddr) +{ + return ((paddr & PAGE_MASK) | + (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | + _CACHE_UNCACHED)) >> 6; +} + +void __init bus_error_init(void) +{ + /* nothing */ +} + +/* + * setup code for a handoff from a version 2 PMON 2000 PROM + */ +void setup_wired_tlb_entries(void) +{ + write_c0_wired(0); + local_flush_tlb_all(); + + /* marvell and extra space */ + add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K); + + /* fpga, rtc, and uart */ + add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M); +} + +#define CONV_BCD_TO_BIN(val) (((val) & 0xf) + (((val) >> 4) * 10)) +#define CONV_BIN_TO_BCD(val) (((val) % 10) + (((val) / 10) << 4)) + +unsigned long m48t37y_get_time(void) +{ + unsigned int year, month, day, hour, min, sec; + + /* stop the update */ + rtc_base[0x7ff8] = 0x40; + + year = CONV_BCD_TO_BIN(rtc_base[0x7fff]); + year += CONV_BCD_TO_BIN(rtc_base[0x7ff1]) * 100; + + month = CONV_BCD_TO_BIN(rtc_base[0x7ffe]); + + day = CONV_BCD_TO_BIN(rtc_base[0x7ffd]); + + hour = CONV_BCD_TO_BIN(rtc_base[0x7ffb]); + min = CONV_BCD_TO_BIN(rtc_base[0x7ffa]); + sec = CONV_BCD_TO_BIN(rtc_base[0x7ff9]); + + /* start the update */ + rtc_base[0x7ff8] = 0x00; + + return mktime(year, month, day, hour, min, sec); +} + +int m48t37y_set_time(unsigned long sec) +{ + struct rtc_time tm; + + /* convert to a more useful format -- note months count from 0 */ + to_tm(sec, &tm); + tm.tm_mon += 1; + + /* enable writing */ + rtc_base[0x7ff8] = 0x80; + + /* year */ + rtc_base[0x7fff] = CONV_BIN_TO_BCD(tm.tm_year % 100); + rtc_base[0x7ff1] = CONV_BIN_TO_BCD(tm.tm_year / 100); + + /* month */ + rtc_base[0x7ffe] = CONV_BIN_TO_BCD(tm.tm_mon); + + /* day */ + rtc_base[0x7ffd] = CONV_BIN_TO_BCD(tm.tm_mday); + + /* hour/min/sec */ + rtc_base[0x7ffb] = CONV_BIN_TO_BCD(tm.tm_hour); + rtc_base[0x7ffa] = CONV_BIN_TO_BCD(tm.tm_min); + rtc_base[0x7ff9] = CONV_BIN_TO_BCD(tm.tm_sec); + + /* day of week -- not really used, but let's keep it up-to-date */ + rtc_base[0x7ffc] = CONV_BIN_TO_BCD(tm.tm_wday + 1); + + /* disable writing */ + rtc_base[0x7ff8] = 0x00; + + return 0; +} + +void momenco_timer_setup(struct irqaction *irq) +{ + setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */ +} + +void momenco_time_init(void) +{ + setup_wired_tlb_entries(); + + /* + * Ocelot-3 board has been built with both + * the Rm7900 and the Rm7065C + */ + mips_hpt_frequency = cpu_clock / 2; + board_timer_setup = momenco_timer_setup; + + rtc_get_time = m48t37y_get_time; + rtc_set_time = m48t37y_set_time; +} + +static int __init momenco_ocelot_3_setup(void) +{ + unsigned int tmpword; + + board_time_init = momenco_time_init; + + _machine_restart = momenco_ocelot_restart; + _machine_halt = momenco_ocelot_halt; + _machine_power_off = momenco_ocelot_power_off; + + /* Wired TLB entries */ + setup_wired_tlb_entries(); + + /* shut down ethernet ports, just to be sure our memory doesn't get + * corrupted by random ethernet traffic. + */ + MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); + MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); + do {} + while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); + do {} + while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); + do {} + while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); + do {} + while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); + MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), + MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); + MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), + MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); + + /* Turn off the Bit-Error LED */ + OCELOT_FPGA_WRITE(0x80, CLR); + + tmpword = OCELOT_FPGA_READ(BOARDREV); + if (tmpword < 26) + printk("Momenco Ocelot-3: Board Assembly Rev. %c\n", + 'A'+tmpword); + else + printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n", + tmpword); + + tmpword = OCELOT_FPGA_READ(FPGA_REV); + printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); + tmpword = OCELOT_FPGA_READ(RESET_STATUS); + printk("Reset reason: 0x%x\n", tmpword); + switch (tmpword) { + case 0x1: + printk(" - Power-up reset\n"); + break; + case 0x2: + printk(" - Push-button reset\n"); + break; + case 0x4: + printk(" - cPCI bus reset\n"); + break; + case 0x8: + printk(" - Watchdog reset\n"); + break; + case 0x10: + printk(" - Software reset\n"); + break; + default: + printk(" - Unknown reset cause\n"); + } + reset_reason = tmpword; + OCELOT_FPGA_WRITE(0xff, RESET_STATUS); + + tmpword = OCELOT_FPGA_READ(CPCI_ID); + printk("cPCI ID register: 0x%02x\n", tmpword); + printk(" - Slot number: %d\n", tmpword & 0x1f); + printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); + printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); + + tmpword = OCELOT_FPGA_READ(BOARD_STATUS); + printk("Board Status register: 0x%02x\n", tmpword); + printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); + printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); + printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1); + + /* Support for 128 MB memory */ + add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM); + + return 0; +} + +early_initcall(momenco_ocelot_3_setup); Index: linux/arch/mips/configs/ocelot_3_defconfig =================================================================== --- /dev/null +++ linux/arch/mips/configs/ocelot_3_defconfig @@ -0,0 +1,719 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.10-rc1 +# Tue Nov 2 12:08:59 2004 +# +CONFIG_MIPS=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set +CONFIG_MIPS32=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_HOTPLUG is not set +CONFIG_KOBJECT_UEVENT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +# CONFIG_TINY_SHMEM is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_MACH_JAZZ is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +CONFIG_MOMENCO_OCELOT_3=y +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_HAVE_DEC_LOCK=y +CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_IRQ_CPU=y +CONFIG_IRQ_CPU_RM7K=y +CONFIG_IRQ_MV64340=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_FB=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_RM9000=y +# CONFIG_CPU_SB1 is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_BOARD_SCACHE=y +CONFIG_RM7000_CPU_SCACHE=y +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_HIGHMEM is not set +# CONFIG_SMP is not set +# CONFIG_PREEMPT is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_MMU=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_LBD is not set +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=m +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +# CONFIG_BLK_DEV_SD is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set + +# +# SCSI low-level drivers +# +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_QLOGIC_1280_1040 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK_DEV=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_IPV6_TUNNEL is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +# CONFIG_IP_NF_CONNTRACK_MARK is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set +# CONFIG_IP_NF_COMPAT_IPFWADM is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y + +# +# Ethernet (1000 Mbit) +# +CONFIG_MV643XX_ETH=y +CONFIG_MV643XX_ETH_0=y +CONFIG_MV643XX_ETH_1=y +CONFIG_MV643XX_ETH_2=y + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +CONFIG_PPPOE=m +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_RAW is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Misc devices +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y + +# +# Logo configuration +# +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_RT is not set +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=m + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_SYSFS=y +CONFIG_DEVFS_FS=y +CONFIG_DEVFS_MOUNT=y +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +CONFIG_EFS_FS=y +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V4 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_DEBUG_KERNEL is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="ip=any root=nfs" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_CRC_CCITT=m +CONFIG_CRC32=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y --17pEHd4RhPHOinZp-- From colin@realtek.com.tw Wed Nov 3 08:52:02 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Nov 2004 08:52:06 +0000 (GMT) Received: from mf2.realtek.com.tw ([IPv6:::ffff:220.128.56.22]:65292 "EHLO mf2.realtek.com.tw") by linux-mips.org with ESMTP id ; Wed, 3 Nov 2004 08:52:02 +0000 Received: from msx.realtek.com.tw (unverified [172.20.1.77]) by mf2.realtek.com.tw (Content Technologies SMTPRS 4.3.14) with ESMTP id for ; Wed, 3 Nov 2004 16:53:05 +0800 Received: from rtpdii3098 ([172.19.26.139]) by msx.realtek.com.tw (Lotus Domino Release 6.0.2CF1) with ESMTP id 2004110316530665-48494 ; Wed, 3 Nov 2004 16:53:06 +0800 Message-ID: <01e101c4c182$5d0f2780$8b1a13ac@realtek.com.tw> From: "colin" To: Subject: KGDB: I cannot stop execution by using "ctrl+c" Date: Wed, 3 Nov 2004 16:51:52 +0800 MIME-Version: 1.0 X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1437 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1441 X-MIMETrack: Itemize by SMTP Server on msx/Realtek(Release 6.0.2CF1|June 9, 2003) at 2004/11/03 =?Bog5?B?pFWkyCAwNDo1MzowNg==?=, Serialize by Router on msx/Realtek(Release 6.0.2CF1|June 9, 2003) at 2004/11/03 =?Bog5?B?pFWkyCAwNDo1MzowNw==?=, Serialize complete at 2004/11/03 =?Bog5?B?pFWkyCAwNDo1MzowNw==?= Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="big5" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6255 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: colin@realtek.com.tw Precedence: bulk X-list: linux-mips Content-Length: 469 Lines: 16 Hi all, When using gdb to debug Linux kernel, I found that it cannot be stopped temporarily by using "ctrl+c". After the first strike of "ctrl+c", nothing happen. After the second, Linux kernel will show these messages: Interrupted while waiting for the program. Give up (and stop debugging it)? (y or n) If choose yes, kernel will totally stop and it goes back to gdb shell. How can I stop kernel temporarily and then resume it? Thanks and regards, Colin From vag@paulidav.org Wed Nov 3 15:21:11 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Nov 2004 15:21:18 +0000 (GMT) Received: from pimout3-ext.prodigy.net ([IPv6:::ffff:207.115.63.102]:463 "EHLO pimout3-ext.prodigy.net") by linux-mips.org with ESMTP id ; Wed, 3 Nov 2004 15:21:11 +0000 Received: from berloga.paulidav.org (adsl-67-116-37-218.dsl.sntc01.pacbell.net [67.116.37.218]) by pimout3-ext.prodigy.net (8.12.10 milter /8.12.10) with ESMTP id iA3FL35g357976; Wed, 3 Nov 2004 10:21:06 -0500 Received: from paulidav.org (berloga.paulidav.org [67.116.37.218]) by berloga.paulidav.org (Postfix) with ESMTP id B1DECB940; Wed, 3 Nov 2004 07:21:02 -0800 (PST) Message-ID: <4188F75E.9010105@paulidav.org> Date: Wed, 03 Nov 2004 07:21:02 -0800 From: "Vladimir A. Gurevich" User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4) Gecko/20030630 X-Accept-Language: ru, en-us, en MIME-Version: 1.0 To: colin Cc: linux-mips@linux-mips.org Subject: Re: KGDB: I cannot stop execution by using "ctrl+c" References: <01e101c4c182$5d0f2780$8b1a13ac@realtek.com.tw> In-Reply-To: <01e101c4c182$5d0f2780$8b1a13ac@realtek.com.tw> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6256 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vag@paulidav.org Precedence: bulk X-list: linux-mips Content-Length: 683 Lines: 23 Hello Colin, colin wrote: >When using gdb to debug Linux kernel, I found that it cannot be stopped >temporarily by using "ctrl+c". >After the first strike of "ctrl+c", nothing happen. >After the second, Linux kernel will show these messages: > Interrupted while waiting for the program. > Give up (and stop debugging it)? (y or n) >If choose yes, kernel will totally stop and it goes back to gdb shell. >How can I stop kernel temporarily and then resume it? > You should use the following command in GDB: set remotebreak 1 After that it will start to behave as you expect it to, i.e. it will interrupt the kernel as soon as you press CTRL-C. Happy hacking, Vladimir From mlachwani@prometheus.mvista.com Thu Nov 4 00:31:40 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2004 00:31:53 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:28399 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Thu, 4 Nov 2004 00:31:40 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iA40VYdh008770; Wed, 3 Nov 2004 16:31:34 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iA40VXkT008768; Wed, 3 Nov 2004 16:31:33 -0800 Date: Wed, 3 Nov 2004 16:31:33 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] PCI support for Ocelot-3 in 2.6 Message-ID: <20041104003133.GA8761@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="y0ulUmNC+osPPQO6" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6257 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 56824 Lines: 2118 --y0ulUmNC+osPPQO6 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hello Ralf, The PCI support for Ocelot-3 has been implemented in 2.6. This includes support for both the PCI busses and the four PCI slots. As we agreed, the PCI changes have been included in the patch sent yesterday. So, this is one patch that has all the changes to 2.6 to support Ocelot-3. Please review ... Thanks Manish Lachwani --y0ulUmNC+osPPQO6 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename="common_mips_ocelot3.patch" Source: MontaVista Software, Inc. | http://www.mvista.com | Manish Lachwani Type: Enhancement Disposition: Submitted to linux-mips@linux-mips.org Description: Support for PMC-Sierra Ocelot-3 in 2.6 (32-bit and 64-bit). Includes PCI Index: linux/arch/mips/Makefile =================================================================== --- linux.orig/arch/mips/Makefile +++ linux/arch/mips/Makefile @@ -436,6 +436,13 @@ load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 # +# Momentum Ocelot-3 +# +core-$(CONFIG_MOMENCO_OCELOT_3) += arch/mips/momentum/ocelot_3/ +cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3 +load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000 + +# # Momentum Jaguar ATX # core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/ Index: linux/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h =================================================================== --- /dev/null +++ linux/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h @@ -0,0 +1,40 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + */ +#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H + +/* + * Momentum Ocelot-3 is based on Rm7900 processor which + * is based on the E9000 core. + */ +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_subset_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 32 + +#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ Index: linux/include/asm-mips/serial.h =================================================================== --- linux.orig/include/asm-mips/serial.h +++ linux/include/asm-mips/serial.h @@ -319,6 +319,23 @@ #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS #endif +#ifdef CONFIG_MOMENCO_OCELOT_3 +#define OCELOT_3_BASE_BAUD ( 20000000 / 16 ) +#define OCELOT_3_SERIAL_IRQ 6 +#define OCELOT_3_SERIAL_BASE (signed)0xfd000020 + +#define _OCELOT_3_SERIAL_INIT(int, base) \ + { baud_base: OCELOT_3_BASE_BAUD, irq: int, \ + flags: STD_COM_FLAGS, \ + iomem_base: (u8 *) base, iomem_reg_shift: 2, \ + io_type: SERIAL_IO_MEM } + +#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ + _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE) +#else +#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS +#endif + #ifdef CONFIG_MOMENCO_OCELOT /* Ordinary NS16552 duart with a 20MHz crystal. */ #define OCELOT_BASE_BAUD ( 20000000 / 16 ) @@ -420,6 +437,7 @@ MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ + MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ TXX927_SERIAL_PORT_DEFNS \ AU1000_SERIAL_PORT_DEFNS Index: linux/drivers/net/Kconfig =================================================================== --- linux.orig/drivers/net/Kconfig +++ linux/drivers/net/Kconfig @@ -2170,7 +2170,7 @@ config MV643XX_ETH tristate "MV-643XX Ethernet support" - depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX + depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 help This driver supports the gigabit Ethernet on the Marvell MV643XX chipset which is used in the Momenco Ocelot C and Jaguar ATX. Index: linux/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h @@ -0,0 +1,57 @@ +/* + * Ocelot-3 Board Register Definitions + * + * (C) 2002 Momentum Computer Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + */ + +#ifndef __OCELOT_3_FPGA_H__ +#define __OCELOT_3_FPGA_H__ + +#define OCELOT_3_REG_BOARDREV 0x0 +#define OCELOT_3_REG_FPGA_REV 0x1 +#define OCELOT_3_REG_FPGA_TYPE 0x2 +#define OCELOT_3_REG_RESET_STATUS 0x3 +#define OCELOT_3_REG_BOARD_STATUS 0x4 +#define OCELOT_3_REG_CPCI_ID 0x5 +#define OCELOT_3_REG_SET 0x6 +#define OCELOT_3_REG_CLR 0x7 +#define OCELOT_3_REG_EEPROM_MODE 0x9 +#define OCELOT_3_REG_INTMASK 0xa +#define OCELOT_3_REG_INTSTAT 0xb +#define OCELOT_3_REG_UART_INTMASK 0xc +#define OCELOT_3_REG_UART_INTSTAT 0xd +#define OCELOT_3_REG_INTSET 0xe +#define OCELOT_3_REG_INTCLR 0xf + +extern unsigned long ocelot_fpga_base; + +#define OCELOT_FPGA_WRITE(x, y) writeb(x, ocelot_fpga_base + OCELOT_3_REG_##y) +#define OCELOT_FPGA_READ(x) readb(ocelot_fpga_base + OCELOT_3_REG_##x) + +#endif Index: linux/arch/mips/Kconfig =================================================================== --- linux.orig/arch/mips/Kconfig +++ linux/arch/mips/Kconfig @@ -329,6 +329,20 @@ The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer . +config MOMENCO_OCELOT_3 + bool "Support for Momentum Ocelot-3 board" + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select IRQ_CPU_RM7K + select IRQ_MV64340 + select PCI_MARVELL + select RM7000_CPU_SCACHE + select SWAP_IO_SPACE + help + The Ocelot-3 is based off Discovery III System Controller and + PMC-Sierra Rm79000 core. + config MOMENCO_JAGUAR_ATX bool "Support for Momentum Jaguar board" select DMA_NONCOHERENT @@ -1004,7 +1018,7 @@ config BOOT_ELF32 bool - depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI + depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI default y config MIPS_L1_CACHE_SHIFT Index: linux/include/asm-mips/bootinfo.h =================================================================== --- linux.orig/include/asm-mips/bootinfo.h +++ linux/include/asm-mips/bootinfo.h @@ -122,6 +122,7 @@ #define MACH_MOMENCO_OCELOT_G 1 #define MACH_MOMENCO_OCELOT_C 2 #define MACH_MOMENCO_JAGUAR_ATX 3 +#define MACH_MOMENCO_OCELOT_3 4 /* * Valid machtype for group ITE Index: linux/arch/mips/momentum/ocelot_3/reset.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/reset.c @@ -0,0 +1,60 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 1997, 2001 Ralf Baechle + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright (C) 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void momenco_ocelot_restart(char *command) +{ + /* base address of timekeeper portion of part */ + void *nvram = (void *) 0xfc807000L; + + /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ + writeb(0x84, nvram + 0xff7); + + /* wait for the watchdog to go off */ + mdelay(100+(1000/16)); + + /* if the watchdog fails for some reason, let people know */ + printk(KERN_NOTICE "Watchdog reset failed\n"); +} + +void momenco_ocelot_halt(void) +{ + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void momenco_ocelot_power_off(void) +{ + momenco_ocelot_halt(); +} Index: linux/arch/mips/momentum/ocelot_3/prom.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/prom.c @@ -0,0 +1,259 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + */ +#include +#include +#include +#include + +#include +#include +#include +#include "ocelot_3_fpga.h" + +struct callvectors { + int (*open) (char*, int, int); + int (*close) (int); + int (*read) (int, void*, int); + int (*write) (int, void*, int); + off_t (*lseek) (int, off_t, int); + int (*printf) (const char*, ...); + void (*cacheflush) (void); + char* (*gets) (char*); +}; + +struct callvectors* debug_vectors; +extern unsigned long marvell_base; +extern unsigned long cpu_clock; + +#ifdef CONFIG_MV64340_ETH +extern unsigned char prom_mac_addr_base[6]; +#endif + +const char *get_system_type(void) +{ + return "Momentum Ocelot-3"; +} + +#ifdef CONFIG_MV64340_ETH +void burn_clocks(void) +{ + int i; + + /* this loop should burn at least 1us -- this should be plenty */ + for (i = 0; i < 0x10000; i++) + ; +} + +u8 exchange_bit(u8 val, u8 cs) +{ + /* place the data */ + OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE); + burn_clocks(); + + /* turn the clock on */ + OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE); + burn_clocks(); + + /* turn the clock off and read-strobe */ + OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); + + /* return the data */ + return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); +} + +void get_mac(char dest[6]) +{ + u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + int i,j; + + for (i = 0; i < 12; i++) + exchange_bit(read_opcode[i], 1); + + for (j = 0; j < 6; j++) { + dest[j] = 0; + for (i = 0; i < 8; i++) { + dest[j] <<= 1; + dest[j] |= exchange_bit(0, 1); + } + } + + /* turn off CS */ + exchange_bit(0,0); +} +#endif + + +#ifdef CONFIG_MIPS64 + +unsigned long signext(unsigned long addr) +{ + addr &= 0xffffffff; + return (unsigned long)((int)addr); +} + +void *get_arg(unsigned long args, int arc) +{ + unsigned long ul; + unsigned char *puc, uc; + + args += (arc * 4); + ul = (unsigned long)signext(args); + puc = (unsigned char *)ul; + if (puc == 0) + return (void *)0; + +#ifdef CONFIG_CPU_LITTLE_ENDIAN + uc = *puc++; + ul = (unsigned long)uc; + uc = *puc++; + ul |= (((unsigned long)uc) << 8); + uc = *puc++; + ul |= (((unsigned long)uc) << 16); + uc = *puc++; + ul |= (((unsigned long)uc) << 24); +#else /* CONFIG_CPU_LITTLE_ENDIAN */ + uc = *puc++; + ul = ((unsigned long)uc) << 24; + uc = *puc++; + ul |= (((unsigned long)uc) << 16); + uc = *puc++; + ul |= (((unsigned long)uc) << 8); + uc = *puc++; + ul |= ((unsigned long)uc); +#endif /* CONFIG_CPU_LITTLE_ENDIAN */ + ul = signext(ul); + return (void *)ul; +} + +char *arg64(unsigned long addrin, int arg_index) +{ + unsigned long args; + char *p; + + args = signext(addrin); + p = (char *)get_arg(args, arg_index); + + return p; +} +#endif /* CONFIG_MIPS64 */ + +void __init prom_init(void) +{ + int argc = fw_arg0; + char **arg = (char **) fw_arg1; + char **env = (char **) fw_arg2; + struct callvectors *cv = (struct callvectors *) fw_arg3; + int i; + +#ifdef CONFIG_MIPS64 + char *ptr; + printk("prom_init - MIPS64\n"); + + /* save the PROM vectors for debugging use */ + debug_vectors = (struct callvectors *)signext((unsigned long)cv); + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + + for (i = 1; i < argc; i++) { + ptr = (char *)arg64((unsigned long)arg, i); + if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >= + sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ptr); + strcat(arcs_cmdline, " "); + } + i = 0; + + while (1) { + ptr = (char *)arg64((unsigned long)env, i); + if (! ptr) + break; + + if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) { + marvell_base = simple_strtol(ptr + strlen("gtbase="), + NULL, 16); + + if ((marvell_base & 0xffffffff00000000) == 0) + marvell_base |= 0xffffffff00000000; + + printk("marvell_base set to 0x%016lx\n", marvell_base); + } + if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) { + cpu_clock = simple_strtol(ptr + strlen("cpuclock="), + NULL, 10); + printk("cpu_clock set to %d\n", cpu_clock); + } + i++; + } + printk("arcs_cmdline: %s\n", arcs_cmdline); + +#else /* CONFIG_MIPS64 */ + + /* save the PROM vectors for debugging use */ + debug_vectors = cv; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < argc; i++) { + if (strlen(arcs_cmdline) + strlen(arg[i] + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, arg[i]); + strcat(arcs_cmdline, " "); + } + + while (*env) { + if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { + marvell_base = simple_strtol(*env + strlen("gtbase="), + NULL, 16); + } + if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) { + cpu_clock = simple_strtol(*env + strlen("cpuclock="), + NULL, 10); + } + env++; + } +#endif /* CONFIG_MIPS64 */ + + mips_machgroup = MACH_GROUP_MOMENCO; + mips_machtype = MACH_MOMENCO_OCELOT_3; + +#ifdef CONFIG_MV64340_ETH + /* get the base MAC address for on-board ethernet ports */ + get_mac(prom_mac_addr_base); +#endif + +#ifndef CONFIG_MIPS64 + debug_vectors->printf("Booting Linux kernel...\n"); +#endif +} + +void __init prom_free_prom_memory(void) +{ +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ +} Index: linux/arch/mips/momentum/ocelot_3/Makefile =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for Momentum Computer's Ocelot-3 board. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# +obj-y += int-handler.o irq.o prom.o reset.o setup.o Index: linux/arch/mips/momentum/ocelot_3/int-handler.S =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/int-handler.S @@ -0,0 +1,137 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * First-level interrupt dispatcher for Ocelot-3 board. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include + +/* + * First level interrupt dispatcher for Ocelot-3 board + */ + .align 5 + NESTED(ocelot3_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 t0, CP0_CAUSE + mfc0 t2, CP0_STATUS + + and t0, t2 + + andi t1, t0, STATUSF_IP0 /* sw0 software interrupt (IRQ0) */ + bnez t1, ll_sw0_irq + + andi t1, t0, STATUSF_IP1 /* sw1 software interrupt (IRQ1) */ + bnez t1, ll_sw1_irq + + andi t1, t0, STATUSF_IP2 /* int0 hardware line (IRQ2) */ + bnez t1, ll_pci0slot1_irq + + andi t1, t0, STATUSF_IP3 /* int1 hardware line (IRQ3) */ + bnez t1, ll_pci0slot2_irq + + andi t1, t0, STATUSF_IP4 /* int2 hardware line (IRQ4) */ + bnez t1, ll_pci1slot1_irq + + andi t1, t0, STATUSF_IP5 /* int3 hardware line (IRQ5) */ + bnez t1, ll_pci1slot2_irq + + andi t1, t0, STATUSF_IP6 /* int4 hardware line (IRQ6) */ + bnez t1, ll_uart_irq + + andi t1, t0, STATUSF_IP7 /* cpu timer (IRQ7) */ + bnez t1, ll_cputimer_irq + + /* now look at extended interrupts */ + mfc0 t0, CP0_CAUSE + cfc0 t1, CP0_S1_INTCONTROL + + /* shift the mask 8 bits left to line up the bits */ + sll t2, t1, 8 + + and t0, t2 + srl t0, t0, 16 + + andi t1, t0, STATUSF_IP8 /* int6 hardware line (IRQ9) */ + bnez t1, ll_mv64340_decode_irq + + .set reorder + + /* wrong alarm or masked ... */ + j spurious_interrupt + nop + END(ocelot3_handle_int) + + .align 5 +ll_sw0_irq: + li a0, 0 /* IRQ 1 */ + move a1, sp + jal do_IRQ + j ret_from_irq +ll_sw1_irq: + li a0, 1 /* IRQ 2 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci0slot1_irq: + li a0, 2 /* IRQ 3 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci0slot2_irq: + li a0, 3 /* IRQ 4 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci1slot1_irq: + li a0, 4 /* IRQ 5 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pci1slot2_irq: + li a0, 5 /* IRQ 6 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_uart_irq: + li a0, 6 /* IRQ 7 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cputimer_irq: + li a0, 7 /* IRQ 8 */ + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_mv64340_decode_irq: + move a0, sp + jal ll_mv64340_irq + j ret_from_irq + Index: linux/arch/mips/momentum/ocelot_3/irq.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/irq.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern asmlinkage void ocelot3_handle_int(void); + +static struct irqaction cascade_mv64340 = { + no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL +}; + +void __init arch_init_irq(void) +{ + /* + * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap + */ + clear_c0_status(ST0_IM | ST0_BEV); + + /* Sets the first-level interrupt dispatcher. */ + set_except_vector(0, ocelot3_handle_int); + mips_cpu_irq_init(0); + rm7k_cpu_irq_init(8); + + /* set up the cascading interrupts */ + setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */ + mv64340_irq_init(16); + + set_c0_status(ST0_IM); /* IE in the status register */ + +} Index: linux/arch/mips/momentum/ocelot_3/setup.c =================================================================== --- /dev/null +++ linux/arch/mips/momentum/ocelot_3/setup.c @@ -0,0 +1,399 @@ +/* + * setup.c + * + * BRIEF MODULE DESCRIPTION + * Momentum Computer Ocelot-3 board dependent boot routines + * + * Copyright (C) 1996, 1997, 2001 Ralf Baechle + * Copyright (C) 2000 RidgeRun, Inc. + * Copyright (C) 2001 Red Hat, Inc. + * Copyright (C) 2002 Momentum Computer + * + * Author: Matthew Dharm, Momentum Computer + * mdharm@momenco.com + * + * Louis Hamilton, Red Hat, Inc. + * hamilton@redhat.com [MIPS64 modifications] + * + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2004 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ocelot_3_fpga.h" + +/* Marvell Discovery Register Base */ +unsigned long marvell_base = (signed)0xf4000000; + +/* CPU clock */ +unsigned long cpu_clock; + +/* RTC/NVRAM */ +unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000; + +/* FPGA Base */ +unsigned long ocelot_fpga_base = (signed)0xfc000000; + +/* Serial base */ +unsigned long uart_base = (signed)0xfd000000; + +/* + * Marvell Discovery SRAM. This is one place where Ethernet + * Tx and Rx descriptors can be placed to improve performance + */ +extern unsigned long mv64340_sram_base; + +/* These functions are used for rebooting or halting the machine*/ +extern void momenco_ocelot_restart(char *command); +extern void momenco_ocelot_halt(void); +extern void momenco_ocelot_power_off(void); + +void momenco_time_init(void); +static char reset_reason; + +void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask); + +static inline unsigned long ENTRYLO(unsigned long paddr) +{ + return ((paddr & PAGE_MASK) | + (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | + _CACHE_UNCACHED)) >> 6; +} + +void __init bus_error_init(void) +{ + /* nothing */ +} + +/* + * setup code for a handoff from a version 2 PMON 2000 PROM + */ +void setup_wired_tlb_entries(void) +{ + write_c0_wired(0); + local_flush_tlb_all(); + + /* marvell and extra space */ + add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K); + + /* fpga, rtc, and uart */ + add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M); +} + +#define CONV_BCD_TO_BIN(val) (((val) & 0xf) + (((val) >> 4) * 10)) +#define CONV_BIN_TO_BCD(val) (((val) % 10) + (((val) / 10) << 4)) + +unsigned long m48t37y_get_time(void) +{ + unsigned int year, month, day, hour, min, sec; + + /* stop the update */ + rtc_base[0x7ff8] = 0x40; + + year = CONV_BCD_TO_BIN(rtc_base[0x7fff]); + year += CONV_BCD_TO_BIN(rtc_base[0x7ff1]) * 100; + + month = CONV_BCD_TO_BIN(rtc_base[0x7ffe]); + + day = CONV_BCD_TO_BIN(rtc_base[0x7ffd]); + + hour = CONV_BCD_TO_BIN(rtc_base[0x7ffb]); + min = CONV_BCD_TO_BIN(rtc_base[0x7ffa]); + sec = CONV_BCD_TO_BIN(rtc_base[0x7ff9]); + + /* start the update */ + rtc_base[0x7ff8] = 0x00; + + return mktime(year, month, day, hour, min, sec); +} + +int m48t37y_set_time(unsigned long sec) +{ + struct rtc_time tm; + + /* convert to a more useful format -- note months count from 0 */ + to_tm(sec, &tm); + tm.tm_mon += 1; + + /* enable writing */ + rtc_base[0x7ff8] = 0x80; + + /* year */ + rtc_base[0x7fff] = CONV_BIN_TO_BCD(tm.tm_year % 100); + rtc_base[0x7ff1] = CONV_BIN_TO_BCD(tm.tm_year / 100); + + /* month */ + rtc_base[0x7ffe] = CONV_BIN_TO_BCD(tm.tm_mon); + + /* day */ + rtc_base[0x7ffd] = CONV_BIN_TO_BCD(tm.tm_mday); + + /* hour/min/sec */ + rtc_base[0x7ffb] = CONV_BIN_TO_BCD(tm.tm_hour); + rtc_base[0x7ffa] = CONV_BIN_TO_BCD(tm.tm_min); + rtc_base[0x7ff9] = CONV_BIN_TO_BCD(tm.tm_sec); + + /* day of week -- not really used, but let's keep it up-to-date */ + rtc_base[0x7ffc] = CONV_BIN_TO_BCD(tm.tm_wday + 1); + + /* disable writing */ + rtc_base[0x7ff8] = 0x00; + + return 0; +} + +void momenco_timer_setup(struct irqaction *irq) +{ + setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */ +} + +void momenco_time_init(void) +{ + setup_wired_tlb_entries(); + + /* + * Ocelot-3 board has been built with both + * the Rm7900 and the Rm7065C + */ + mips_hpt_frequency = cpu_clock / 2; + board_timer_setup = momenco_timer_setup; + + rtc_get_time = m48t37y_get_time; + rtc_set_time = m48t37y_set_time; +} + +/* + * PCI Support for Ocelot-3 + */ + +/* Bus #0 IO and MEM space */ +#define OCELOT_3_PCI_IO_0_START 0xe0000000 +#define OCELOT_3_PCI_IO_0_SIZE 0x08000000 +#define OCELOT_3_PCI_MEM_0_START 0xc0000000 +#define OCELOT_3_PCI_MEM_0_SIZE 0x10000000 + +/* Bus #1 IO and MEM space */ +#define OCELOT_3_PCI_IO_1_START 0xe8000000 +#define OCELOT_3_PCI_IO_1_SIZE 0x08000000 +#define OCELOT_3_PCI_MEM_1_START 0xd0000000 +#define OCELOT_3_PCI_MEM_1_SIZE 0x10000000 + +static struct resource mv_pci_io_mem0_resource = { + .name = "MV64340 PCI0 IO MEM", + .start = OCELOT_3_PCI_IO_0_START, + .end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE - 1, + .flags = IORESOURCE_IO, +}; + +static struct resource mv_pci_io_mem1_resource = { + .name = "MV64340 PCI1 IO MEM", + .start = OCELOT_3_PCI_IO_1_START, + .end = OCELOT_3_PCI_IO_1_START + OCELOT_3_PCI_IO_1_SIZE - 1, + .flags = IORESOURCE_IO, +}; + +static struct resource mv_pci_mem0_resource = { + .name = "MV64340 PCI0 MEM", + .start = OCELOT_3_PCI_MEM_0_START, + .end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct resource mv_pci_mem1_resource = { + .name = "MV64340 PCI1 MEM", + .start = OCELOT_3_PCI_MEM_1_START, + .end = OCELOT_3_PCI_MEM_1_START + OCELOT_3_PCI_MEM_1_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct mv_pci_controller mv_bus0_controller = { + .pcic = { + .pci_ops = &mv_pci_ops, + .mem_resource = &mv_pci_mem0_resource, + .io_resource = &mv_pci_io_mem0_resource, + }, + .config_addr = MV64340_PCI_0_CONFIG_ADDR, + .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, +}; + +static struct mv_pci_controller mv_bus1_controller = { + .pcic = { + .pci_ops = &mv_pci_ops, + .mem_resource = &mv_pci_mem1_resource, + .io_resource = &mv_pci_io_mem1_resource, + }, + .config_addr = MV64340_PCI_1_CONFIG_ADDR, + .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, +}; + +static __init int __init ja_pci_init(void) +{ + uint32_t enable; + extern int pci_probe_only; + + /* PMON will assign PCI resources */ + pci_probe_only = 1; + + enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE); + /* + * We require at least one enabled I/O or PCI memory window or we + * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3. + */ + if (enable & (0x01 << 9) || enable & (0x01 << 10)) + register_pci_controller(&mv_bus0_controller.pcic); + + if (enable & (0x01 << 14) || enable & (0x01 << 15)) + register_pci_controller(&mv_bus1_controller.pcic); + + ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE + + OCELOT_3_PCI_IO_1_SIZE - 1; + + iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE + + OCELOT_3_PCI_MEM_1_SIZE - 1; + + set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */ + + return 0; +} + +arch_initcall(ja_pci_init); + +static int __init momenco_ocelot_3_setup(void) +{ + unsigned int tmpword; + + board_time_init = momenco_time_init; + + _machine_restart = momenco_ocelot_restart; + _machine_halt = momenco_ocelot_halt; + _machine_power_off = momenco_ocelot_power_off; + + /* Wired TLB entries */ + setup_wired_tlb_entries(); + + /* shut down ethernet ports, just to be sure our memory doesn't get + * corrupted by random ethernet traffic. + */ + MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); + MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); + do {} + while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); + do {} + while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); + do {} + while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); + do {} + while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); + MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), + MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); + MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), + MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); + + /* Turn off the Bit-Error LED */ + OCELOT_FPGA_WRITE(0x80, CLR); + + tmpword = OCELOT_FPGA_READ(BOARDREV); + if (tmpword < 26) + printk("Momenco Ocelot-3: Board Assembly Rev. %c\n", + 'A'+tmpword); + else + printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n", + tmpword); + + tmpword = OCELOT_FPGA_READ(FPGA_REV); + printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); + tmpword = OCELOT_FPGA_READ(RESET_STATUS); + printk("Reset reason: 0x%x\n", tmpword); + switch (tmpword) { + case 0x1: + printk(" - Power-up reset\n"); + break; + case 0x2: + printk(" - Push-button reset\n"); + break; + case 0x4: + printk(" - cPCI bus reset\n"); + break; + case 0x8: + printk(" - Watchdog reset\n"); + break; + case 0x10: + printk(" - Software reset\n"); + break; + default: + printk(" - Unknown reset cause\n"); + } + reset_reason = tmpword; + OCELOT_FPGA_WRITE(0xff, RESET_STATUS); + + tmpword = OCELOT_FPGA_READ(CPCI_ID); + printk("cPCI ID register: 0x%02x\n", tmpword); + printk(" - Slot number: %d\n", tmpword & 0x1f); + printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); + printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); + + tmpword = OCELOT_FPGA_READ(BOARD_STATUS); + printk("Board Status register: 0x%02x\n", tmpword); + printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); + printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); + printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1); + + /* Support for 128 MB memory */ + add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM); + + return 0; +} + +early_initcall(momenco_ocelot_3_setup); Index: linux/arch/mips/configs/ocelot_3_defconfig =================================================================== --- /dev/null +++ linux/arch/mips/configs/ocelot_3_defconfig @@ -0,0 +1,838 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.10-rc1 +# Wed Nov 3 13:48:19 2004 +# +CONFIG_MIPS=y +# CONFIG_MIPS64 is not set +# CONFIG_64BIT is not set +CONFIG_MIPS32=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_HOTPLUG is not set +CONFIG_KOBJECT_UEVENT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SHMEM=y +# CONFIG_TINY_SHMEM is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_MACH_JAZZ is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +CONFIG_MOMENCO_OCELOT_3=y +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_HAVE_DEC_LOCK=y +CONFIG_DMA_NONCOHERENT=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_IRQ_CPU=y +CONFIG_IRQ_CPU_RM7K=y +CONFIG_IRQ_MV64340=y +CONFIG_PCI_MARVELL=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_FB=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_RM9000=y +# CONFIG_CPU_SB1 is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_BOARD_SCACHE=y +CONFIG_RM7000_CPU_SCACHE=y +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_HIGHMEM is not set +# CONFIG_SMP is not set +# CONFIG_PREEMPT is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_LBD is not set +# CONFIG_CDROM_PKTCDVD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=m +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +# CONFIG_BLK_DEV_SD is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set + +# +# SCSI low-level drivers +# +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_ISP is not set +# CONFIG_SCSI_QLOGIC_FC is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLOGIC_1280_1040 is not set +CONFIG_SCSI_QLA2XXX=m +# CONFIG_SCSI_QLA21XX is not set +# CONFIG_SCSI_QLA22XX is not set +# CONFIG_SCSI_QLA2300 is not set +# CONFIG_SCSI_QLA2322 is not set +# CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_QLA6322 is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK_DEV=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_IPV6_TUNNEL is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +# CONFIG_IP_NF_CONNTRACK_MARK is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set +# CONFIG_IP_NF_COMPAT_IPFWADM is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_ETHERTAP is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_E100_NAPI is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_LAN_SAA9730 is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set +CONFIG_MV643XX_ETH=y +CONFIG_MV643XX_ETH_0=y +CONFIG_MV643XX_ETH_1=y +CONFIG_MV643XX_ETH_2=y + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +CONFIG_PPPOE=m +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_RAW is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Misc devices +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON_OLD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_E1356 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y + +# +# Logo configuration +# +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_RT is not set +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=m + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_SYSFS=y +CONFIG_DEVFS_FS=y +CONFIG_DEVFS_MOUNT=y +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +CONFIG_EFS_FS=y +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V4 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_DEBUG_KERNEL is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="ip=any root=nfs" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_CRC_CCITT=m +CONFIG_CRC32=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y Index: linux/arch/mips/pci/Makefile =================================================================== --- linux.orig/arch/mips/pci/Makefile +++ linux/arch/mips/pci/Makefile @@ -36,7 +36,7 @@ obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o -obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-jaguar.o +obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o Index: linux/arch/mips/pci/fixup-ocelot3.c =================================================================== --- /dev/null +++ linux/arch/mips/pci/fixup-ocelot3.c @@ -0,0 +1,32 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004 Montavista Software Inc. + * Author: Manish Lachwani (mlachwani@mvista.com) + * + * Looking at the schematics for the Ocelot-3 board, there are + * two PCI busses and each bus has two PCI slots. + */ +#include +#include +#include +#include + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int bus = dev->bus->number; + + if (bus == 0 && slot == 1) + return 2; /* PCI-X A */ + if (bus == 0 && slot == 2) + return 3; /* PCI-X B */ + if (bus == 1 && slot == 1) + return 4; /* PCI A */ + if (bus == 1 && slot == 2) + return 5; /* PCI B */ + +return 0; + panic("Whooops in pcibios_map_irq"); +} --y0ulUmNC+osPPQO6-- From anemo@mba.ocn.ne.jp Thu Nov 4 06:39:02 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2004 06:39:08 +0000 (GMT) Received: from topsns.toshiba-tops.co.jp ([IPv6:::ffff:202.230.225.5]:50203 "HELO topsns.toshiba-tops.co.jp") by linux-mips.org with SMTP id ; Thu, 4 Nov 2004 06:39:02 +0000 Received: from newms.toshiba-tops.co.jp by topsns.toshiba-tops.co.jp via smtpd (for mail.linux-mips.org [62.254.210.162]) with SMTP; 4 Nov 2004 06:39:00 UT Received: from srd2sd.toshiba-tops.co.jp (gw-chiba7.toshiba-tops.co.jp [172.17.244.27]) by newms.toshiba-tops.co.jp (Postfix) with ESMTP id 0687B239E1A; Thu, 4 Nov 2004 15:38:57 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id iA46cudD024722; Thu, 4 Nov 2004 15:38:56 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Thu, 04 Nov 2004 15:37:44 +0900 (JST) Message-Id: <20041104.153744.122623401.nemoto@toshiba-tops.co.jp> To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: Re: gcc 3.3.4/3.4.1 and get_user From: Atsushi Nemoto In-Reply-To: <20040920171021.GA25371@linux-mips.org> References: <87656yqsmz.fsf@redhat.com> <20040920154042.GB5150@linux-mips.org> <20040920171021.GA25371@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6258 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 602 Lines: 15 >>>>> On Mon, 20 Sep 2004 19:10:21 +0200, Ralf Baechle said: ralf> And here the same for 2.4. Actually this is a straight backport ralf> of the 2.6 uaccess.h to 2.4 so with this patch ralf> include/asm-mips/uaccess.h and include/asm-mips64/uaccess.h are ralf> going to be identical. I found that asm-mips/uaccess.h and asm-mips64/uaccess.h in 2.4 are sill not identical. Is this intentional? Current asm-mips64/uaccess.h seems broken... Also, arch/mips64/lib/strxxx_user.S should be modified to use t0/t1 instead of ta0/ta1 ? (__UA_t0 is now $12, not $8) --- Atsushi Nemoto From thomas.koeller@baslerweb.com Thu Nov 4 10:31:32 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2004 10:31:37 +0000 (GMT) Received: from mail.baslerweb.com ([IPv6:::ffff:145.253.187.130]:38759 "EHLO mail.baslerweb.com") by linux-mips.org with ESMTP id ; Thu, 4 Nov 2004 10:31:32 +0000 Received: (from mail@localhost) by mail.baslerweb.com (8.12.10/8.12.10) id iA4AUjUc003659 for ; Thu, 4 Nov 2004 11:30:45 +0100 Received: from unknown by gateway id /var/KryptoWall/smtpp/kwWlIwvP; Thu Nov 04 11:30:32 2004 Received: from vclinux-1.basler.corp (localhost [172.16.13.253]) by comm1.baslerweb.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2657.72) id WHM6N9CA; Thu, 4 Nov 2004 11:31:18 +0100 From: Thomas Koeller Organization: Basler AG To: linux-mips@linux-mips.org Subject: [PATCH] The compiler's revenge Date: Thu, 4 Nov 2004 11:35:31 +0100 User-Agent: KMail/1.6.2 MIME-Version: 1.0 Message-Id: <200411041135.31503.thomas.koeller@baslerweb.com> Content-Disposition: inline Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6259 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.koeller@baslerweb.com Precedence: bulk X-list: linux-mips Content-Length: 1683 Lines: 50 ... for lying to it is to produce code that does unexpected things. In include/asm-mips/io.h, mips_io_port_base is declared to be const, but can actually be modified using set_io_port_base(). The compiler believes the const declaration and uses the uninitialized value if an in(b|w|l) or out(b|w|l) is used right after set_io_port_base(). Signed-off-by: Thomas Koeller --- linux-mips-cvs/include/asm-mips/io.h 2004-10-25 11:16:42.000000000 +0200 +++ linux-mips-basler/include/asm-mips/io.h 2004-11-04 10:40:57.796646368 +0100 @@ -67,10 +67,9 @@ * instruction, so the lower 16 bits must be zero. Should be true on * on any sane architecture; generic code does not use this assumption. */ -extern const unsigned long mips_io_port_base; +extern unsigned long mips_io_port_base; -#define set_io_port_base(base) \ - do { * (unsigned long *) &mips_io_port_base = (base); } while (0) +#define set_io_port_base(base) mips_io_port_base = (base) /* * Thanks to James van Artsdalen for a better timing-fix than --- linux-mips-cvs/arch/mips/kernel/setup.c 2004-07-14 16:21:29.000000000 +0200 +++ linux-mips-basler/arch/mips/kernel/setup.c 2004-11-04 10:39:45.359658464 +0100 @@ -78,7 +78,7 @@ * mips_io_port_base is the begin of the address space to which x86 style * I/O ports are mapped. */ -const unsigned long mips_io_port_base = -1; +unsigned long mips_io_port_base = -1; EXPORT_SYMBOL(mips_io_port_base); /* -- -------------------------------------------------- Thomas Koeller, Software Development Basler Vision Technologies thomas dot koeller at baslerweb dot com http://www.baslerweb.com ============================== From vergiss-es@gmx.de Thu Nov 4 11:20:11 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2004 11:20:16 +0000 (GMT) Received: from pop.gmx.de ([IPv6:::ffff:213.165.64.20]:7308 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Thu, 4 Nov 2004 11:20:11 +0000 Received: (qmail 15068 invoked by uid 0); 4 Nov 2004 11:20:05 -0000 Received: from 134.108.33.122 by www38.gmx.net with HTTP; Thu, 4 Nov 2004 12:20:05 +0100 (MET) Date: Thu, 4 Nov 2004 12:20:05 +0100 (MET) From: "Hannes Bischof" To: linux-mips@linux-mips.org MIME-Version: 1.0 Subject: Compile Mips-Architecture on an i386? X-Priority: 3 (Normal) X-Authenticated: #5350918 Message-ID: <20244.1099567205@www38.gmx.net> X-Mailer: WWW-Mail 1.6 (Global Message Exchange) X-Flags: 0001 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6260 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vergiss-es@gmx.de Precedence: bulk X-list: linux-mips Content-Length: 916 Lines: 30 Hello! Ok i´ll describe first my hardware. It´s a small DSL-Router with the following hardware: Its a variant of the AR7-Variante TNETD7300(A)GDW in it is a MIPS 4KEc Processor communicationsprocessor (TI DSP) for ADSL interface USB slave interface GPIO-Ports and Ethernet also a 4MB flash memory and a 32MB SDRAM module OK now the problem: on the router is a small BusyBox linux and I don´t want to change that now. But I would like to compile some files like a small webserver or an ftp programm for the router. Now my question, is it possible to compile a programm for the router by example on an normal PC(i386)??? What do I need to compile the software so that it runs under the linux system of the router?? Many questions but I hope some one could help me. Greets Maruu -- NEU +++ DSL Komplett von GMX +++ http://www.gmx.net/de/go/dsl GMX DSL-Netzanschluss + Tarif zum supergünstigen Komplett-Preis! From thomas.petazzoni@enix.org Thu Nov 4 13:17:56 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2004 13:18:01 +0000 (GMT) Received: from the-doors.enix.org ([IPv6:::ffff:62.210.169.120]:11406 "EHLO the-doors.enix.org") by linux-mips.org with ESMTP id ; Thu, 4 Nov 2004 13:17:56 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by the-doors.enix.org (Postfix) with ESMTP id 70C591EF67; Thu, 4 Nov 2004 14:17:49 +0100 (CET) Message-ID: <418A2C6F.7010508@enix.org> Date: Thu, 04 Nov 2004 14:19:43 +0100 From: Thomas Petazzoni User-Agent: Mozilla Thunderbird 0.8 (Windows/20040913) X-Accept-Language: fr, en MIME-Version: 1.0 To: Hannes Bischof Cc: linux-mips@linux-mips.org Subject: Re: Compile Mips-Architecture on an i386? References: <20244.1099567205@www38.gmx.net> In-Reply-To: <20244.1099567205@www38.gmx.net> X-Enigmail-Version: 0.86.1.0 X-Enigmail-Supports: pgp-inline, pgp-mime Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig9ABF694F6385F3598593A7E2" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6261 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@enix.org Precedence: bulk X-list: linux-mips Content-Length: 1411 Lines: 43 This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig9ABF694F6385F3598593A7E2 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Hello, Hannes Bischof a écrit : > What do I need to compile the software so that it runs under the linux > system of the router?? You need a cross-compilation toolchain (that is a gcc, binutils and libc that runs on your i386, but that generates binaries for MIPS). Different tools are available to do that : * Toolchain : http://www.uclibc.org/toolchains.html * Crosstool : http://kegel.com/crosstool/ * Debian way : http://skaya.enix.org/wiki/ToolChain Thomas -- PETAZZONI Thomas - thomas.petazzoni@enix.org http://thomas.enix.org - Jabber: kos_tom@sourcecode.de KOS: http://kos.enix.org/ - Lolut: http://lolut.utbm.info Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E 1624 F653 CB30 98D3 F7A7 --------------enig9ABF694F6385F3598593A7E2 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.5 (MingW32) Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org iD8DBQFBiixx9lPLMJjT96cRAiwSAJ9DGh5xcbLzU1k57kHllJusPMrgxgCfVbJy jfAHZuNcgr2KBEUrBZpgPMg= =OTAU -----END PGP SIGNATURE----- --------------enig9ABF694F6385F3598593A7E2-- From yuasa@hh.iij4u.or.jp Thu Nov 4 16:13:24 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2004 16:13:29 +0000 (GMT) Received: from mo01.iij4u.or.jp ([IPv6:::ffff:210.130.0.20]:35577 "EHLO mo01.iij4u.or.jp") by linux-mips.org with ESMTP id ; Thu, 4 Nov 2004 16:13:24 +0000 Received: MO(mo01)id iA4GDKWr014952; Fri, 5 Nov 2004 01:13:20 +0900 (JST) Received: MDO(mdo01) id iA4GDJuu002266; Fri, 5 Nov 2004 01:13:20 +0900 (JST) Received: 4UMRO01 id iA4GDIU1022268; Fri, 5 Nov 2004 01:13:19 +0900 (JST) from stratos (localhost [127.0.0.1]) (authenticated) Date: Fri, 5 Nov 2004 01:13:17 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@hh.iij4u.or.jp, linux-mips Subject: [PATCH] add iomap funtions Message-Id: <20041105011317.012b10ad.yuasa@hh.iij4u.or.jp> X-Mailer: Sylpheed version 0.9.99 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6262 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@hh.iij4u.or.jp Precedence: bulk X-list: linux-mips Content-Length: 5199 Lines: 174 Hi Ralf, This patch adds iomap functions to MIPS system. Please apply this patch to v2.6. Signed-off-by: Yoichi Yuasa diff -urN -X dontdiff b-orig/arch/mips/lib/Makefile b/arch/mips/lib/Makefile --- b-orig/arch/mips/lib/Makefile Mon Jan 5 17:27:29 2004 +++ b/arch/mips/lib/Makefile Fri Nov 5 00:55:23 2004 @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial_copy.o dec_and_lock.o memcpy.o promlib.o strlen_user.o \ - strncpy_user.o strnlen_user.o +lib-y += csum_partial_copy.o dec_and_lock.o iomap.o memcpy.o promlib.o \ + strlen_user.o strncpy_user.o strnlen_user.o EXTRA_AFLAGS := $(CFLAGS) diff -urN -X dontdiff b-orig/arch/mips/lib/iomap.c b/arch/mips/lib/iomap.c --- b-orig/arch/mips/lib/iomap.c Thu Jan 1 09:00:00 1970 +++ b/arch/mips/lib/iomap.c Fri Nov 5 00:55:23 2004 @@ -0,0 +1,69 @@ +/* + * iomap.c, Memory Mapped I/O routines for MIPS architecture. + * + * Copyright (C) 2004 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include + +#include + +void __iomem *ioport_map(unsigned long port, unsigned int nr) +{ + return (void __iomem *)(mips_io_port_base + port); +} + +EXPORT_SYMBOL(ioport_map); + +void ioport_unmap(void __iomem *addr) +{ +} + +EXPORT_SYMBOL(ioport_unmap); + +void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) +{ + unsigned long start, len, flags; + + start = pci_resource_start(dev, bar); + len = pci_resource_len(dev, bar); + + if (start == 0 || len == 0) + return NULL; + if (maxlen != 0 && len > maxlen) + len = maxlen; + + flags = pci_resource_flags(dev, bar); + if (flags & IORESOURCE_IO) + return ioport_map(start, len); + if (flags & IORESOURCE_MEM) { + if (flags & IORESOURCE_CACHEABLE) + return ioremap_cacheable_cow(start, len); + return ioremap_nocache(start, len); + } + + return NULL; +} + +EXPORT_SYMBOL(pci_iomap); + +void pci_iounmap(struct pci_dev *dev, void __iomem *addr) +{ + iounmap(addr); +} + +EXPORT_SYMBOL(pci_iounmap); diff -urN -X dontdiff b-orig/include/asm-mips/io.h b/include/asm-mips/io.h --- b-orig/include/asm-mips/io.h Thu Oct 21 17:34:51 2004 +++ b/include/asm-mips/io.h Fri Nov 5 00:55:23 2004 @@ -353,6 +353,77 @@ #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) /* + * Memory Mapped I/O + */ +#define ioread8(addr) readb(addr) +#define ioread16(addr) readw(addr) +#define ioread32(addr) readl(addr) + +#define iowrite8(val,addr) writeb(val,addr) +#define iowrite16(val,addr) writew(val,addr) +#define iowrite32(val,addr) writel(val,addr) + +static inline void fastcall ioread8_rep(void __iomem *addr, void *dst, unsigned long count) +{ + while (count-- > 0) { + uint8_t val = __raw_readb(addr); + *(volatile uint8_t *)dst = val; + (uint8_t *)dst++; + } +} + +static inline void fastcall ioread16_rep(void __iomem *addr, void *dst, unsigned long count) +{ + while (count-- > 0) { + uint16_t val = __raw_readw(addr); + *(volatile uint16_t *)dst = val; + (uint16_t *)dst++; + } +} + +static inline void fastcall ioread32_rep(void __iomem *addr, void *dst, unsigned long count) +{ + while (count-- > 0) { + uint32_t val = __raw_readl(addr); + *(volatile uint32_t *)dst = val; + (uint32_t *)dst++; + } +} + +static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count) +{ + while (count-- > 0) { + __raw_writeb(*(uint8_t *)src, addr); + (uint8_t *)src++; + } +} + +static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count) +{ + while (count-- > 0) { + __raw_writew(*(uint16_t *)src, addr); + (uint16_t *)src++; + } +} + +static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count) +{ + while (count-- > 0) { + __raw_writel(*(uint32_t *)src, addr); + (uint32_t *)src++; + } +} + +/* Create a virtual mapping cookie for an IO port range */ +extern void __iomem *ioport_map(unsigned long port, unsigned int nr); +extern void ioport_unmap(void __iomem *); + +/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ +struct pci_dev; +extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); +extern void pci_iounmap(struct pci_dev *dev, void __iomem *); + +/* * ISA space is 'always mapped' on currently supported MIPS systems, no need * to explicitly ioremap() it. The fact that the ISA IO space is mapped * to PAGE_OFFSET is pure coincidence - it does not mean ISA values From mlachwani@prometheus.mvista.com Thu Nov 4 18:04:12 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2004 18:04:17 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:16891 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Thu, 4 Nov 2004 18:04:12 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iA4I49dh026096; Thu, 4 Nov 2004 10:04:09 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iA4I49dC026094; Thu, 4 Nov 2004 10:04:09 -0800 Date: Thu, 4 Nov 2004 10:04:09 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Rm7000/Rm9000 cache code change for 64-bit Message-ID: <20041104180409.GA26087@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="wRRV7LY7NUeQGEoC" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6263 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1016 Lines: 40 --wRRV7LY7NUeQGEoC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ralf Attached small change fixes Rm7000/Rm9000 cache code to compile for 64-bit. This has been verified on the 2.6.10 kernel and tested on the Momentum Ocelot-3 board. Please review Thanks Manish Lachwani --wRRV7LY7NUeQGEoC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename=patch-cache-ckseg --- arch/mips/mm/sc-rm7k.c.orig 2004-11-04 09:27:09.000000000 -0800 +++ arch/mips/mm/sc-rm7k.c 2004-11-02 11:10:51.000000000 -0800 @@ -127,13 +127,13 @@ ".set mips0\n\t" ".set reorder" : - : "r" (KSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); + : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); } } static __init void rm7k_sc_enable(void) { - void (*func)(void) = (void *) KSEG1ADDR(&__rm7k_sc_enable); + void (*func)(void) = (void *) CKSEG1ADDR(&__rm7k_sc_enable); if (read_c0_config() & 0x08) /* CONF_SE */ return; --wRRV7LY7NUeQGEoC-- From wd@denx.de Thu Nov 4 21:30:43 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2004 21:30:48 +0000 (GMT) Received: from mailout06.sul.t-online.com ([IPv6:::ffff:194.25.134.19]:6800 "EHLO mailout06.sul.t-online.com") by linux-mips.org with ESMTP id ; Thu, 4 Nov 2004 21:30:43 +0000 Received: from fwd00.aul.t-online.de by mailout06.sul.t-online.com with smtp id 1CPpBd-0007VH-01; Thu, 04 Nov 2004 22:30:29 +0100 Received: from denx.de (EAryJGZAYeAvsJWot7oAZW7VX8Urf0q64TvN7GPROYq-TLRSHM0grC@[217.235.243.140]) by fmrl00.sul.t-online.com with esmtp id 1CPpBb-20RSF60; Thu, 4 Nov 2004 22:30:27 +0100 Received: from atlas.denx.de (atlas.denx.de [10.0.0.14]) by denx.de (Postfix) with ESMTP id 574D942B91; Thu, 4 Nov 2004 22:30:24 +0100 (MET) Received: by atlas.denx.de (Postfix, from userid 15) id DA9CCC1430; Thu, 4 Nov 2004 22:30:20 +0100 (MET) Received: from atlas.denx.de (localhost [127.0.0.1]) by atlas.denx.de (Postfix) with ESMTP id D7EED13D6DB; Thu, 4 Nov 2004 22:30:20 +0100 (MET) To: "Hannes Bischof" Cc: linux-mips@linux-mips.org From: Wolfgang Denk Subject: Re: Compile Mips-Architecture on an i386? Mime-version: 1.0 Content-type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: 8bit In-reply-to: Your message of "Thu, 04 Nov 2004 12:20:05 +0100." <20244.1099567205@www38.gmx.net> Date: Thu, 04 Nov 2004 22:30:15 +0100 Message-Id: <20041104213020.DA9CCC1430@atlas.denx.de> X-ID: EAryJGZAYeAvsJWot7oAZW7VX8Urf0q64TvN7GPROYq-TLRSHM0grC@t-dialin.net X-TOI-MSGID: be656206-994f-4012-bbcd-863bf7110eb7 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6264 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wd@denx.de Precedence: bulk X-list: linux-mips Content-Length: 930 Lines: 25 In message <20244.1099567205@www38.gmx.net> you wrote: > > programm for the router. Now my question, is it possible to compile a > programm for the router by example on an normal PC(i386)??? Yes, of course this is possible. This is what everybody does every day. > What do I need to compile the software so that it runs under the linux > system of the router?? You need a set of cross development tools. I'd recommend our ELDK (Embedded Linux Development Kit, see http://www.denx.de/ELDK.html) which is available for free, but I'm obviously biased. [Note: ELDK 3.1 will be released in a couple of days.] Viele Grüße, Wolfgang Denk -- See us @ Embedded/Electronica Munich, Nov 09 - 12, Hall A.6 Booth 513 Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de The biggest difference between time and space is that you can't reuse time. - Merrick Furst From bruno.randolf@4g-systems.biz Thu Nov 4 21:39:35 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Nov 2004 21:39:40 +0000 (GMT) Received: from grey.subnet.at ([IPv6:::ffff:193.170.141.20]:7428 "EHLO grey.subnet.at") by linux-mips.org with ESMTP id ; Thu, 4 Nov 2004 21:39:35 +0000 Received: from ip6-localhost ([193.170.141.4]) by grey.subnet.at ; Thu, 04 Nov 2004 22:39:29 +0100 From: Bruno Randolf To: linux-mips@linux-mips.org Subject: Re: Compile Mips-Architecture on an i386? Date: Thu, 4 Nov 2004 22:32:50 +0100 User-Agent: KMail/1.7 References: <20244.1099567205@www38.gmx.net> <418A2C6F.7010508@enix.org> In-Reply-To: <418A2C6F.7010508@enix.org> Organization: 4G Systems MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart2220995.2bMazBtAf9"; protocol="application/pgp-signature"; micalg=pgp-sha1 Content-Transfer-Encoding: 7bit Message-Id: <200411042232.55210.bruno.randolf@4g-systems.biz> X-Rcpt-To: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6265 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bruno.randolf@4g-systems.biz Precedence: bulk X-list: linux-mips Content-Length: 1194 Lines: 47 --nextPart2220995.2bMazBtAf9 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline hi! another option is to use the openembedded build system: http://openembedded.org/oe_wiki/ it includes the cross-toolchain and has lots of packages which you can=20 compile. bruno On Thursday 04 November 2004 14:19, Thomas Petazzoni wrote: > Hello, > > Hannes Bischof a =E9crit : > > What do I need to compile the software so that it runs under the linux > > system of the router?? > > You need a cross-compilation toolchain (that is a gcc, binutils and libc > that runs on your i386, but that generates binaries for MIPS). > > Different tools are available to do that : > > * Toolchain : http://www.uclibc.org/toolchains.html > * Crosstool : http://kegel.com/crosstool/ > * Debian way : http://skaya.enix.org/wiki/ToolChain > > Thomas --nextPart2220995.2bMazBtAf9 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.4 (GNU/Linux) iD8DBQBBiqAHfg2jtUL97G4RAtL7AKCKp6DFHVjb9a3CcPDN/eeGdaEf6wCfWC08 UPCKeMZNOuY/wQBiPbaQ4Y0= =0p2d -----END PGP SIGNATURE----- --nextPart2220995.2bMazBtAf9-- From joseph@omnilux.net Fri Nov 5 01:49:37 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2004 01:49:42 +0000 (GMT) Received: from foothill.iad.idealab.com ([IPv6:::ffff:64.208.8.35]:30347 "EHLO foothill.iad.idealab.com") by linux-mips.org with ESMTP id convert rfc822-to-8bit; Fri, 5 Nov 2004 01:49:37 +0000 X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Subject: RE: Compile Mips-Architecture on an i386? Date: Thu, 4 Nov 2004 17:49:27 -0800 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Compile Mips-Architecture on an i386? Thread-Index: AcTCtuG5MXT9SbvFRkiGyR5n6+BMlAAItowQ From: "Joseph Chiu" To: "Bruno Randolf" , Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6266 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joseph@omnilux.net Precedence: bulk X-list: linux-mips Content-Length: 1273 Lines: 42 If you're doing it to get stuff done, a pre-built package (commercial or opensource) is the way to go. But I also rebuilt my toolchain from scratch and learned immensely from it... > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org]On Behalf Of Bruno Randolf > Sent: Thursday, November 04, 2004 1:33 PM > To: linux-mips@linux-mips.org > Subject: Re: Compile Mips-Architecture on an i386? > > > hi! > > another option is to use the openembedded build system: > > http://openembedded.org/oe_wiki/ > > it includes the cross-toolchain and has lots of packages > which you can > compile. > > bruno > > On Thursday 04 November 2004 14:19, Thomas Petazzoni wrote: > > Hello, > > > > Hannes Bischof a écrit : > > > What do I need to compile the software so that it runs > under the linux > > > system of the router?? > > > > You need a cross-compilation toolchain (that is a gcc, > binutils and libc > > that runs on your i386, but that generates binaries for MIPS). > > > > Different tools are available to do that : > > > > * Toolchain : http://www.uclibc.org/toolchains.html > > * Crosstool : http://kegel.com/crosstool/ > > * Debian way : http://skaya.enix.org/wiki/ToolChain > > > > Thomas > From vergiss-es@gmx.de Fri Nov 5 07:07:51 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2004 07:07:55 +0000 (GMT) Received: from pop.gmx.net ([IPv6:::ffff:213.165.64.20]:20932 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Fri, 5 Nov 2004 07:07:51 +0000 Received: (qmail 16138 invoked by uid 65534); 5 Nov 2004 07:07:44 -0000 Received: from p508A10B4.dip0.t-ipconnect.de (HELO maruu) (80.138.16.180) by mail.gmx.net (mp005) with SMTP; 05 Nov 2004 08:07:44 +0100 X-Authenticated: #5350918 From: "Maruu" To: Subject: Compile Mips-Architecture on an i386? Date: Fri, 5 Nov 2004 08:08:21 +0100 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook IMO, Build 9.0.2416 (9.0.2910.0) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1441 Importance: Normal Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6267 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: vergiss-es@gmx.de Precedence: bulk X-list: linux-mips Content-Length: 295 Lines: 11 Hy! Ok now I searched for some files and found (with your help) http://www.uclibc.org/ I downloaded the toolchains and compiled gcc3.3 with Mipsel architecture. My littel "Hello wolrd" programm works fine. Now I have to taste the rest if it works. What do you think of uClibc?? Greets Maruu From thomas.petazzoni@enix.org Fri Nov 5 08:00:38 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2004 08:00:42 +0000 (GMT) Received: from the-doors.enix.org ([IPv6:::ffff:62.210.169.120]:22955 "EHLO the-doors.enix.org") by linux-mips.org with ESMTP id ; Fri, 5 Nov 2004 08:00:38 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by the-doors.enix.org (Postfix) with ESMTP id 87A931EF7C; Fri, 5 Nov 2004 09:00:27 +0100 (CET) Message-ID: <418B3390.8010403@enix.org> Date: Fri, 05 Nov 2004 09:02:24 +0100 From: Thomas Petazzoni User-Agent: Mozilla Thunderbird 0.8 (Windows/20040913) X-Accept-Language: fr, en MIME-Version: 1.0 To: Maruu , linux-mips@linux-mips.org Subject: Re: Compile Mips-Architecture on an i386? References: In-Reply-To: X-Enigmail-Version: 0.86.1.0 X-Enigmail-Supports: pgp-inline, pgp-mime Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig80B4AFABD8204F5D533F815B" Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6268 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.petazzoni@enix.org Precedence: bulk X-list: linux-mips Content-Length: 1082 Lines: 37 This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig80B4AFABD8204F5D533F815B Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Hello, Maruu a écrit : > What do you think of uClibc?? - Works well on my MIPS platform (both C and C++) - Small - Fast to compile Thomas -- PETAZZONI Thomas - thomas.petazzoni@enix.org http://thomas.enix.org - Jabber: kos_tom@sourcecode.de KOS: http://kos.enix.org/ - Lolut: http://lolut.utbm.info Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E 1624 F653 CB30 98D3 F7A7 --------------enig80B4AFABD8204F5D533F815B Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.5 (MingW32) Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org iD8DBQFBizOQ9lPLMJjT96cRAv4iAKCI8l9rV0VRhWCJz5yn8ePzbU0B8ACeKnK+ Po2khMpsXrMOPK5XmIyLsk8= =HBx7 -----END PGP SIGNATURE----- --------------enig80B4AFABD8204F5D533F815B-- From hvr@inso.tuwien.ac.at Fri Nov 5 08:19:54 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2004 08:19:59 +0000 (GMT) Received: from [IPv6:::ffff:80.122.96.210] ([IPv6:::ffff:80.122.96.210]:58073 "EHLO fwswe.inso.tuwien.ac.at") by linux-mips.org with ESMTP id ; Fri, 5 Nov 2004 08:19:54 +0000 Received: from s052.inso.tuwien.ac.at ([128.130.59.52]) by fwswe.inso.tuwien.ac.at with esmtp (Exim 3.36 #1 (Debian)) id 1CPzJs-00065t-00; Fri, 05 Nov 2004 09:19:40 +0100 Subject: ohci-au1xxx.c cleanups and fix for 2.6.10-rc1 From: Herbert Valerio Riedel To: Pete Popov Cc: linux-mips@linux-mips.org Content-Type: text/plain Date: Fri, 05 Nov 2004 09:19:34 +0100 Message-Id: <1099642775.9984.16.camel@s052.inso.tuwien.ac.at> Mime-Version: 1.0 X-Mailer: Evolution 2.0.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6269 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hvr@inso.tuwien.ac.at Precedence: bulk X-list: linux-mips Content-Length: 3142 Lines: 116 below just a patch to have usb working again for 2.6.10-rc1 and some minor cleanups... (alas usb still doesn't work on big endian...) Index: ohci-au1xxx.c =================================================================== RCS file: /home/cvs/linux/drivers/usb/host/ohci-au1xxx.c,v retrieving revision 1.1 diff -u -r1.1 ohci-au1xxx.c --- ohci-au1xxx.c 10 Oct 2004 17:56:25 -0000 1.1 +++ ohci-au1xxx.c 5 Nov 2004 08:15:05 -0000 @@ -20,6 +20,21 @@ #include +#define USBH_ENABLE_BE (1<<0) +#define USBH_ENABLE_C (1<<1) +#define USBH_ENABLE_E (1<<2) +#define USBH_ENABLE_CE (1<<3) +#define USBH_ENABLE_RD (1<<4) + +// shall we set USBH_ENABLE_C depending on !CONFIG_NONCOHERENT? +#ifdef __LITTLE_ENDIAN +# define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) +#elif __BIG_ENDIAN +# define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE) +#else +# error not byte order defined +#endif + extern int usb_disabled(void); /*-------------------------------------------------------------------------*/ @@ -30,18 +45,17 @@ ": starting Au1xxx OHCI USB Controller\n"); /* enable host controller */ - au_writel(0x00000008, USB_HOST_CONFIG); + au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); udelay(1000); - au_writel(0x0000000e, USB_HOST_CONFIG); + au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG); udelay(1000); - /* wait for reset complete */ - au_readl(USB_HOST_CONFIG); /* throw away first read */ - while (!(au_readl(USB_HOST_CONFIG) & 0x10)) - au_readl(USB_HOST_CONFIG); + /* wait for reset complete (read register twice; see to au1500 errata) */ + while (au_readl(USB_HOST_CONFIG), !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) + udelay(1000); printk(KERN_DEBUG __FILE__ - ": Clock to USB host has been enabled \n"); + ": Clock to USB host has been enabled \n"); } static void au1xxx_stop_hc(struct platform_device *dev) @@ -49,9 +63,8 @@ printk(KERN_DEBUG __FILE__ ": stopping Au1xxx OHCI USB Controller\n"); - /* Disable clock */ - au_writel(readl(USB_HOST_CONFIG) & 0xffffff7, USB_HOST_CONFIG); + au_writel(readl(USB_HOST_CONFIG) & ~(USBH_ENABLE_RD | USBH_ENABLE_CE), USB_HOST_CONFIG); } @@ -234,37 +247,15 @@ ohci_dbg (ohci, "ohci_au1xxx_start, ohci:%p", ohci); - ohci->hcca = dma_alloc_noncoherent (hcd->self.controller, - sizeof *ohci->hcca, &ohci->hcca_dma, 0); - if (!ohci->hcca) - return -ENOMEM; - - ohci_dbg (ohci, "ohci_au1xxx_start, ohci->hcca:%p", - ohci->hcca); - - memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); - - if ((ret = ohci_mem_init (ohci)) < 0) { - ohci_stop (hcd); + if ((ret = ohci_init (ohci)) < 0) return ret; - } - ohci->regs = hcd->regs; - if (hc_reset (ohci) < 0) { - ohci_stop (hcd); - return -ENODEV; - } - - if (hc_start (ohci) < 0) { + if ((ret = ohci_run (ohci)) < 0) { err ("can't start %s", ohci->hcd.self.bus_name); ohci_stop (hcd); - return -EBUSY; + return ret; } - create_debug_files (ohci); -#ifdef DEBUG - ohci_dump (ohci, 1); -#endif /*DEBUG*/ return 0; } -- Herbert Valerio Riedel From ppopov@embeddedalley.com Fri Nov 5 08:24:01 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2004 08:24:07 +0000 (GMT) Received: from web81005.mail.yahoo.com ([IPv6:::ffff:206.190.37.150]:25458 "HELO web81005.mail.yahoo.com") by linux-mips.org with SMTP id ; Fri, 5 Nov 2004 08:24:01 +0000 Message-ID: <20041105082354.36787.qmail@web81005.mail.yahoo.com> Received: from [63.194.214.47] by web81005.mail.yahoo.com via HTTP; Fri, 05 Nov 2004 00:23:54 PST X-RocketYMMF: pvpopov@pacbell.net Date: Fri, 5 Nov 2004 00:23:54 -0800 (PST) From: Pete Popov Reply-To: ppopov@embeddedalley.com Subject: Re: ohci-au1xxx.c cleanups and fix for 2.6.10-rc1 To: Herbert Valerio Riedel , Pete Popov Cc: linux-mips@linux-mips.org In-Reply-To: <1099642775.9984.16.camel@s052.inso.tuwien.ac.at> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6270 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ppopov@embeddedalley.com Precedence: bulk X-list: linux-mips Content-Length: 3522 Lines: 145 Thanks. We were just working on that too. Pete --- Herbert Valerio Riedel wrote: > > below just a patch to have usb working again for > 2.6.10-rc1 and some minor cleanups... > (alas usb still doesn't work on big endian...) > > Index: ohci-au1xxx.c > =================================================================== > RCS file: > /home/cvs/linux/drivers/usb/host/ohci-au1xxx.c,v > retrieving revision 1.1 > diff -u -r1.1 ohci-au1xxx.c > --- ohci-au1xxx.c 10 Oct 2004 17:56:25 -0000 1.1 > +++ ohci-au1xxx.c 5 Nov 2004 08:15:05 -0000 > @@ -20,6 +20,21 @@ > > #include > > +#define USBH_ENABLE_BE (1<<0) > +#define USBH_ENABLE_C (1<<1) > +#define USBH_ENABLE_E (1<<2) > +#define USBH_ENABLE_CE (1<<3) > +#define USBH_ENABLE_RD (1<<4) > + > +// shall we set USBH_ENABLE_C depending on > !CONFIG_NONCOHERENT? > +#ifdef __LITTLE_ENDIAN > +# define USBH_ENABLE_INIT (USBH_ENABLE_CE | > USBH_ENABLE_E | USBH_ENABLE_C) > +#elif __BIG_ENDIAN > +# define USBH_ENABLE_INIT (USBH_ENABLE_CE | > USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE) > +#else > +# error not byte order defined > +#endif > + > extern int usb_disabled(void); > > > /*-------------------------------------------------------------------------*/ > @@ -30,18 +45,17 @@ > ": starting Au1xxx OHCI USB Controller\n"); > > /* enable host controller */ > - au_writel(0x00000008, USB_HOST_CONFIG); > + au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); > udelay(1000); > - au_writel(0x0000000e, USB_HOST_CONFIG); > + au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG); > udelay(1000); > > - /* wait for reset complete */ > - au_readl(USB_HOST_CONFIG); /* throw away first > read */ > - while (!(au_readl(USB_HOST_CONFIG) & 0x10)) > - au_readl(USB_HOST_CONFIG); > + /* wait for reset complete (read register twice; > see to au1500 errata) */ > + while (au_readl(USB_HOST_CONFIG), > !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) > + udelay(1000); > > printk(KERN_DEBUG __FILE__ > - ": Clock to USB host has been enabled \n"); > + ": Clock to USB host has been enabled \n"); > } > > static void au1xxx_stop_hc(struct platform_device > *dev) > @@ -49,9 +63,8 @@ > printk(KERN_DEBUG __FILE__ > ": stopping Au1xxx OHCI USB Controller\n"); > > - > /* Disable clock */ > - au_writel(readl(USB_HOST_CONFIG) & 0xffffff7, > USB_HOST_CONFIG); > + au_writel(readl(USB_HOST_CONFIG) & > ~(USBH_ENABLE_RD | USBH_ENABLE_CE), > USB_HOST_CONFIG); > } > > > @@ -234,37 +247,15 @@ > > ohci_dbg (ohci, "ohci_au1xxx_start, ohci:%p", > ohci); > > - ohci->hcca = dma_alloc_noncoherent > (hcd->self.controller, > - sizeof *ohci->hcca, &ohci->hcca_dma, 0); > - if (!ohci->hcca) > - return -ENOMEM; > - > - ohci_dbg (ohci, "ohci_au1xxx_start, > ohci->hcca:%p", > - ohci->hcca); > - > - memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); > - > - if ((ret = ohci_mem_init (ohci)) < 0) { > - ohci_stop (hcd); > + if ((ret = ohci_init (ohci)) < 0) > return ret; > - } > - ohci->regs = hcd->regs; > > - if (hc_reset (ohci) < 0) { > - ohci_stop (hcd); > - return -ENODEV; > - } > - > - if (hc_start (ohci) < 0) { > + if ((ret = ohci_run (ohci)) < 0) { > err ("can't start %s", ohci->hcd.self.bus_name); > ohci_stop (hcd); > - return -EBUSY; > + return ret; > } > - create_debug_files (ohci); > > -#ifdef DEBUG > - ohci_dump (ohci, 1); > -#endif /*DEBUG*/ > return 0; > } > > > > > -- > Herbert Valerio Riedel > > > From mmporter@cox.net Fri Nov 5 14:18:41 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Nov 2004 14:18:46 +0000 (GMT) Received: from fed1rmmtao07.cox.net ([IPv6:::ffff:68.230.241.32]:13697 "EHLO fed1rmmtao07.cox.net") by linux-mips.org with ESMTP id ; Fri, 5 Nov 2004 14:18:41 +0000 Received: from liberty.homelinux.org ([68.2.41.86]) by fed1rmmtao07.cox.net (InterMail vM.6.01.04.00 201-2131-117-20041022) with ESMTP id <20041105141829.FAWP3261.fed1rmmtao07.cox.net@liberty.homelinux.org>; Fri, 5 Nov 2004 09:18:29 -0500 Received: (from mmporter@localhost) by liberty.homelinux.org (8.9.3/8.9.3/Debian 8.9.3-21) id HAA19358; Fri, 5 Nov 2004 07:18:17 -0700 Date: Fri, 5 Nov 2004 07:18:17 -0700 From: Matt Porter To: Herbert Valerio Riedel Cc: Pete Popov , linux-mips@linux-mips.org Subject: Re: ohci-au1xxx.c cleanups and fix for 2.6.10-rc1 Message-ID: <20041105071817.A19291@home.com> References: <1099642775.9984.16.camel@s052.inso.tuwien.ac.at> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5i In-Reply-To: <1099642775.9984.16.camel@s052.inso.tuwien.ac.at>; from hvr@inso.tuwien.ac.at on Fri, Nov 05, 2004 at 09:19:34AM +0100 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6271 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mporter@kernel.crashing.org Precedence: bulk X-list: linux-mips Content-Length: 448 Lines: 12 On Fri, Nov 05, 2004 at 09:19:34AM +0100, Herbert Valerio Riedel wrote: > > below just a patch to have usb working again for 2.6.10-rc1 and > some minor cleanups... > (alas usb still doesn't work on big endian...) The patches to support BE OHCI operation were posted months ago on the USB list. GregKH recently picked them up and I just saw the first of them merged to the mainline tree. You should have better luck with BE OHCI soon. :) -Matt From anemo@mba.ocn.ne.jp Sat Nov 6 12:37:31 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Nov 2004 12:37:36 +0000 (GMT) Received: from mba.ocn.ne.jp ([IPv6:::ffff:210.190.142.172]:32460 "HELO smtp.mba.ocn.ne.jp") by linux-mips.org with SMTP id ; Sat, 6 Nov 2004 12:37:31 +0000 Received: from localhost (p7216-ipad29funabasi.chiba.ocn.ne.jp [221.184.74.216]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 69B1684B6; Sat, 6 Nov 2004 21:37:23 +0900 (JST) Date: Sat, 06 Nov 2004 21:40:18 +0900 (JST) Message-Id: <20041106.214018.74755085.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: rsandifo@redhat.com, ralf@linux-mips.org Subject: Re: failed to merge string constant? (gcc 3.4.2 + binutils 2.15) From: Atsushi Nemoto In-Reply-To: <20041029.225817.76758438.nemoto@toshiba-tops.co.jp> References: <20041029.225817.76758438.nemoto@toshiba-tops.co.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 20.7 / Mule 4.0 (HANANOEN) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6272 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 463 Lines: 13 >>>>> On Fri, 29 Oct 2004 22:58:17 +0900 (JST), Atsushi Nemoto said: anemo> I have some strange kernel panic with gcc 3.4.2 + binutils anemo> 2.15. Address of some string constant seems broken. ... anemo> If I compiled kernel with -fno-merge-constants, this problem anemo> does not happen. gcc 3.3.4 + bintuils 2.15 also works fine. It has been fixed in binutils CVS. I tried with binutils 2.15.92.0.2 and it works. --- Atsushi Nemoto From likhit@cg-coreel.com Mon Nov 8 12:04:00 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2004 12:04:05 +0000 (GMT) Received: from mail4.hostek.com ([IPv6:::ffff:216.198.218.132]:53010 "EHLO mail4.hostek.com") by linux-mips.org with ESMTP id ; Mon, 8 Nov 2004 12:04:00 +0000 Received: from cgcorel-195-158-ban.cgcoreel.com [203.196.158.195] by mail4.hostek.com with SMTP; Mon, 8 Nov 2004 06:03:17 -0600 Message-ID: <156401c4c58a$f2ba7080$9b00a2c0@core> From: "likhit" To: Subject: ATI Radeon 9000 on MIPS platform Date: Mon, 8 Nov 2004 17:33:00 +0530 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_155B_01C4C5B8.FE3188D0" X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1437 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1441 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6273 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: likhit@cg-coreel.com Precedence: bulk X-list: linux-mips Content-Length: 1158 Lines: 43 This is a multi-part message in MIME format. ------=_NextPart_000_155B_01C4C5B8.FE3188D0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi, Has anybody used ATI Radeon-9000 on MIPS platform?=20 I m looking for Radeon-9000 device drivers for Linux, any idea of = availability of open source linux drivers for the same? Reagrds, Likiht ------=_NextPart_000_155B_01C4C5B8.FE3188D0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Hi,
 
Has anybody used ATI Radeon-9000 on MIPS platform?
 
I m looking for Radeon-9000 device drivers for Linux, any idea = of=20 availability of open source linux drivers for the same?
 
Reagrds,
Likiht
------=_NextPart_000_155B_01C4C5B8.FE3188D0-- From Yoni.Rabinovich@Teledata-Networks.com Mon Nov 8 14:12:46 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2004 14:12:51 +0000 (GMT) Received: from [IPv6:::ffff:194.90.152.129] ([IPv6:::ffff:194.90.152.129]:30184 "EHLO mr.teledata-networks.com") by linux-mips.org with ESMTP id ; Mon, 8 Nov 2004 14:12:46 +0000 Received: from mr.teledata-networks.com (localhost.localdomain [127.0.0.1]) by localhost.teledata-networks.com (Postfix) with ESMTP id DFD2C7C0070 for ; Mon, 8 Nov 2004 16:11:03 +0200 (IST) Received: from tndcmail.Teledata.Local (ADC-FW.ser.netvision.net.il [199.203 .98.2])by mr.teledata-networks.com (Postfix) with ESMTP id 7B99A7C006Dfor < linux-mips@linux-mips.org>; Mon, 8 Nov 2004 09:10:57 -0500 (EST) Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----_=_NextPart_001_01C4C59C.D9218731" Subject: Problems debugging multithreaded program wirh gdbserver via serial port X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Date: Mon, 8 Nov 2004 16:11:32 +0200 Message-ID: X-MS-Has-Attach: yes X-MS-TNEF-Correlator: Thread-Topic: Problems debugging multithreaded program wirh gdbserver via se rial port Thread-Index: AcTFnNkjnX55Q8ekTa6oyaL41Xlfeg== From: "Yoni Rabinovitch" To: X-imss-version: 2.0 X-imss-result: Passed X-imss-scores: Clean:27.35956 C:14 M:1 S:5 R:5 X-imss-settings: Baseline:1 C:1 M:1 S:1 R:1 (0.0000 0.0000) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6274 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Yoni.Rabinovich@Teledata-Networks.com Precedence: bulk X-list: linux-mips Content-Length: 68060 Lines: 1010 This is a multi-part message in MIME format. ------_=_NextPart_001_01C4C59C.D9218731 Content-Type: multipart/alternative; boundary="----_=_NextPart_002_01C4C59C.D9218731" ------_=_NextPart_002_01C4C59C.D9218731 Content-Type: text/plain; charset="iso-8859-8-i" Content-Transfer-Encoding: quoted-printable Hi, I am trying to debug a multithreaded program running on an embedded = MIPS 5Kc using gdb and gdbserver, connected via a serial port. My environment is as follows: MIPS kernel based on 2.4.18 gdb : 6.2.1, configured with --host=3Di686-pc-linux-gnu = --target=3Dmips-hardhat-linux --disable-sim --disable-tcl = --enable-threads --enable-shared gdbserver: 6.2.1, configured with --target=3Dmips-linux = --enable-threads --enable-shared gcc : 3.2.3, } binutils : 2.13 } Built using crosstool glibc: 2.2.5 } My problems are as follows: 1) If I try to run the program from gdbserver (i.e. gdbserver = /dev/ttyS0 wlsd), I get "readchar: Input/output error" messages, and nothing works. See attached file gdb_fail. What is going on here ? 2) If I first run the program, and then attach gdbserver to it (i.e. = gdbserver /dev/ttyS0 --attach 80), I can debug it.=20 However, debugging is amazingly slow !!=20 For example, it can take 10 minutes for the "backtrace" (bt) command to = complete !!!=20 Also, I get messages saying "Cannot access memory at address 0x2c" = whnever I try to look at the stack. See attached file gdb_trace. Why is it going so slow ? What is the cause of the "Cannot access memory at address 0x2c" = messages ? 3) If I repeat the scenario described in 2), but with "set debug remote = 1", it seems to work somewhat faster (e.g. bt takes about 1 minute to complete). I am seeing alot of "Packet instead of Ack, ignoring it" messages. See attached file gdb_trace_debug. What do these messages mean ?=20 In general, what to I need to do to get gdb <-> gdbserver debugging = working properly over a serial port?=20 Thanks in advance for any tips !!=20 -Yoni <> <> <>=20 ------_=_NextPart_002_01C4C59C.D9218731 Content-Type: text/html; charset="iso-8859-8-i" Content-Transfer-Encoding: quoted-printable Problems debugging multithreaded program wirh gdbserver via = serial port

Hi,

  I = am trying to debug a multithreaded program running on an embedded MIPS = 5Kc using gdb and gdbserver, connected via

a serial = port.

  = My environment is as follows:

  = MIPS kernel based on 2.4.18

  = gdb :  6.2.1, configured with --host=3Di686-pc-linux-gnu = --target=3Dmips-hardhat-linux --disable-sim --disable-tcl = --enable-threads --enable-shared

  = gdbserver: 6.2.1, configured with --target=3Dmips-linux --enable-threads = --enable-shared

  = gcc : 3.2.3,     }

  = binutils : 2.13  }   Built using = crosstool

  = glibc: 2.2.5      }

  = My problems are as follows:

1)  = If I try to run the program from gdbserver (i.e. gdbserver /dev/ttyS0 = wlsd), I get "readchar: Input/output error" = messages,

and = nothing works. See attached file gdb_fail.

What is = going on here ?


2) If I = first run the program, and then attach gdbserver to it (i.e. gdbserver = /dev/ttyS0 --attach 80), I can debug it.

However, = debugging is amazingly slow !!

For = example, it can take 10 minutes for the "backtrace" (bt) = command to complete !!!

Also, I = get messages saying "Cannot access memory at address 0x2c" = whnever I try to look at the stack.

See = attached file gdb_trace.

Why is = it going so slow ?

What is = the cause of the "Cannot access memory at address 0x2c"  = messages ?

3) If I = repeat the scenario described in 2), but with "set debug remote = 1", it seems to work somewhat faster

(e.g. bt = takes about 1 minute to complete).

I am = seeing alot of "Packet instead of Ack, ignoring it" = messages.

See = attached file gdb_trace_debug.

What do = these messages mean ?

  = In general, what to I need to do to get gdb <-> gdbserver = debugging working properly over a serial port?

  = Thanks in advance for any tips !!

  = -Yoni

<<gdb_fail>> <<gdb_trace_debug>> <<gdb_trace>> =

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#1 (Debian)) id 1CRAgb-0006DX-Vv; Mon, 08 Nov 2004 09:40:02 -0500 Date: Mon, 8 Nov 2004 09:40:01 -0500 From: Daniel Jacobowitz To: Yoni Rabinovitch Cc: linux-mips@linux-mips.org Subject: Re: Problems debugging multithreaded program wirh gdbserver via serial port Message-ID: <20041108144001.GA23783@nevyn.them.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.5.1+cvs20040105i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6275 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@debian.org Precedence: bulk X-list: linux-mips Content-Length: 1938 Lines: 45 On Mon, Nov 08, 2004 at 04:11:32PM +0200, Yoni Rabinovitch wrote: > Hi, > > I am trying to debug a multithreaded program running on an embedded MIPS 5Kc using gdb and gdbserver, connected via > a serial port. > > My environment is as follows: > > MIPS kernel based on 2.4.18 > gdb : 6.2.1, configured with --host=i686-pc-linux-gnu --target=mips-hardhat-linux --disable-sim --disable-tcl --enable-threads --enable-shared > gdbserver: 6.2.1, configured with --target=mips-linux --enable-threads --enable-shared > gcc : 3.2.3, } > binutils : 2.13 } Built using crosstool > glibc: 2.2.5 } > > My problems are as follows: > > 1) If I try to run the program from gdbserver (i.e. gdbserver /dev/ttyS0 wlsd), I get "readchar: Input/output error" messages, > and nothing works. See attached file gdb_fail. > What is going on here ? It sounds like your serial port is messed up. > 2) If I first run the program, and then attach gdbserver to it (i.e. gdbserver /dev/ttyS0 --attach 80), I can debug it. > However, debugging is amazingly slow !! > For example, it can take 10 minutes for the "backtrace" (bt) command to complete !!! > Also, I get messages saying "Cannot access memory at address 0x2c" whnever I try to look at the stack. > See attached file gdb_trace. > Why is it going so slow ? > What is the cause of the "Cannot access memory at address 0x2c" messages ? GDB is confused by glibc's syscall stubs. In general, don't worry about errors at the end of backtraces. > 3) If I repeat the scenario described in 2), but with "set debug remote 1", it seems to work somewhat faster > (e.g. bt takes about 1 minute to complete). > I am seeing alot of "Packet instead of Ack, ignoring it" messages. > See attached file gdb_trace_debug. > What do these messages mean ? Try "set debug serial 1" in addition - it's very verbose but maybe it will tell you what the "packet" is. -- Daniel Jacobowitz From Yoni.Rabinovich@Teledata-Networks.com Mon Nov 8 15:57:10 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2004 15:57:15 +0000 (GMT) Received: from [IPv6:::ffff:194.90.152.129] ([IPv6:::ffff:194.90.152.129]:12779 "EHLO mr.teledata-networks.com") by linux-mips.org with ESMTP id ; Mon, 8 Nov 2004 15:57:10 +0000 Received: from mr.teledata-networks.com (localhost.localdomain [127.0.0.1]) by localhost.teledata-networks.com (Postfix) with ESMTP id 941C97C0075; Mon, 8 Nov 2004 17:55:25 +0200 (IST) Received: from tndcmail.Teledata.Local (ADC-FW.ser.netvision.net.il [199.203 .98.2])by mr.teledata-networks.com (Postfix) with ESMTPid CFC867C0077; Mon, 8 Nov 2004 10:55:24 -0500 (EST) Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----_=_NextPart_001_01C4C5AB.1E0783CE" Subject: RE: Problems debugging multithreaded program wirh gdbserver via ser ial port X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Date: Mon, 8 Nov 2004 17:53:40 +0200 Message-ID: X-MS-Has-Attach: yes X-MS-TNEF-Correlator: Thread-Topic: Problems debugging multithreaded program wirh gdbserver via se rial port Thread-Index: AcTFoLZYcvhp9WyQTwe7MqGi0WP+WwABXtcg From: "Yoni Rabinovitch" To: "Daniel Jacobowitz" Cc: X-imss-version: 2.0 X-imss-result: Passed X-imss-scores: Clean:37.00037 C:20 M:1 S:5 R:5 X-imss-settings: Baseline:1 C:1 M:1 S:1 R:1 (0.0000 0.0000) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6276 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Yoni.Rabinovich@Teledata-Networks.com Precedence: bulk X-list: linux-mips Content-Length: 24887 Lines: 360 This is a multi-part message in MIME format. ------_=_NextPart_001_01C4C5AB.1E0783CE Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable >> 1) If I try to run the program from gdbserver (i.e. gdbserver = /dev/ttyS0 wlsd), I get "readchar: Input/output error" messages, >> and nothing works. See attached file gdb_fail. >> What is going on here ? >It sounds like your serial port is messed up. What exactly do you mean by "messed up" ?=20 minicom seems to work OK. What do I need to check ? >> 3) If I repeat the scenario described in 2), but with "set debug = remote 1", it seems to work somewhat faster >> (e.g. bt takes about 1 minute to complete). >> I am seeing alot of "Packet instead of Ack, ignoring it" messages. >> See attached file gdb_trace_debug. >> What do these messages mean ?=20 >Try "set debug serial 1" in addition - it's very verbose but maybe it > will tell you what the "packet" is. Running with "set debug serial 1" gives me the following: In the gdb session,I see lots of the following messages: [O][K][#][9][a][$]Packet instead of Ack, ignoring it Simultaneously, in the gdbserver session (via minicom) I see: +$OK#9a Then, in the gdb session, I see lots of the following: [2][7][9][c][3][9][0][c][#][0][4][$]Packet instead of Ack, ignoring it at which point, the gdbserver (minicom) session now proudly shows: +$OK#9a$279c390c#04 See the attached file (gdb_trace_serial). Why am I seeing stuff printed at the gdbserver (minicom) session ? Is = this an indication that something is wrong with the serial port, and if so, what ? What is the = significance of the=20 messages gdb thinks are "Packet instead of Ack", which also seem to get = printed out (once) in the gdbserver session ? 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Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 08 Nov 2004 16:36:56.0829 (UTC) FILETIME=[296FC2D0:01C4C5B1] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6277 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@avtrex.com Precedence: bulk X-list: linux-mips Content-Length: 421 Lines: 21 Yoni Rabinovitch wrote: > > > Hi, > > I am trying to debug a multithreaded program running on an embedded > MIPS 5Kc using gdb and gdbserver, connected via ... > glibc: 2.2.5 } > This could be the problem. 2.2.5 shipped with a broken sys/procfs.h that prevented multithreaded debugging. See many of these messages: http://www.google.com/search?hl=en&q=mips+procfs.h+gdb&btnG=Google+Search David Daney. From airlied@csn.ul.ie Mon Nov 8 22:01:02 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2004 22:01:07 +0000 (GMT) Received: from holly.csn.ul.ie ([IPv6:::ffff:136.201.105.4]:44977 "EHLO holly.csn.ul.ie") by linux-mips.org with ESMTP id ; Mon, 8 Nov 2004 22:01:02 +0000 Received: from skynet.csn.ul.ie (skynet [136.201.105.2]) by holly.csn.ul.ie (Postfix) with ESMTP id 4F9ACB615; Mon, 8 Nov 2004 22:00:35 +0000 (GMT) Received: by skynet.csn.ul.ie (Postfix, from userid 2139) id 307C1E598; Mon, 8 Nov 2004 22:00:35 +0000 (GMT) Received: from localhost (localhost [127.0.0.1]) by skynet.csn.ul.ie (Postfix) with ESMTP id 2215D7288; Mon, 8 Nov 2004 22:00:35 +0000 (GMT) Date: Mon, 8 Nov 2004 22:00:35 +0000 (GMT) From: Dave Airlie X-X-Sender: airlied@skynet To: likhit Cc: linux-mips@linux-mips.org Subject: Re: ATI Radeon 9000 on MIPS platform In-Reply-To: <156401c4c58a$f2ba7080$9b00a2c0@core> Message-ID: References: <156401c4c58a$f2ba7080$9b00a2c0@core> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6278 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: airlied@csn.ul.ie Precedence: bulk X-list: linux-mips Content-Length: 546 Lines: 18 > Has anybody used ATI Radeon-9000 on MIPS platform? > > I m looking for Radeon-9000 device drivers for Linux, any idea of > availability of open source linux drivers for the same? > do you want 3D or just 2D? 2D should work with Xorg or framebuffer stuff, but 3D mgiht need a bit of work, there are the DRI drivers and they should work but I've never heard of anyone testing them on mips.... Dave. -- David Airlie, Software Engineer http://www.skynet.ie/~airlied / airlied at skynet.ie pam_smb / Linux DECstation / Linux VAX / ILUG person From mlachwani@prometheus.mvista.com Mon Nov 8 23:51:52 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Nov 2004 23:51:57 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:21745 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Mon, 8 Nov 2004 23:51:52 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iA8Npndh021000 for ; Mon, 8 Nov 2004 15:51:49 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iA8NpnVH020998 for linux-mips@linux-mips.org; Mon, 8 Nov 2004 15:51:49 -0800 Date: Mon, 8 Nov 2004 15:51:48 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Subject: [PATCH] Small fix for the Sibyte Mac driver Message-ID: <20041108235148.GA20991@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="4Ckj6UjgE2iN1+kY" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6279 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 952 Lines: 38 --4Ckj6UjgE2iN1+kY Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hello ! Attached is a small patch for the Sibyte MAC Driver. This helps print the device name correctly Thanks Manish Lachwani --4Ckj6UjgE2iN1+kY Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename=patch-sb1250-mac --- drivers/net/sb1250-mac.c.orig 2004-11-08 15:36:45.000000000 -0800 +++ drivers/net/sb1250-mac.c 2004-11-08 15:44:33.000000000 -0800 @@ -2410,13 +2410,13 @@ dev->change_mtu = sb1250_change_mtu; - /* This is needed for PASS2 for Rx H/W checksum feature */ - sbmac_set_iphdr_offset(sc); - err = register_netdev(dev); if (err) goto out_uninit; + /* This is needed for PASS2 for Rx H/W checksum feature */ + sbmac_set_iphdr_offset(sc); + /* * Display Ethernet address (this is called during the config * process so we need to finish off the config message that --4Ckj6UjgE2iN1+kY-- From drow@nevyn.them.org Tue Nov 9 00:57:08 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 00:57:13 +0000 (GMT) Received: from nevyn.them.org ([IPv6:::ffff:66.93.172.17]:20672 "EHLO nevyn.them.org") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 00:57:08 +0000 Received: from drow by nevyn.them.org with local (Exim 4.34 #1 (Debian)) id 1CRKJj-0008Ad-83; Mon, 08 Nov 2004 19:57:03 -0500 Date: Mon, 8 Nov 2004 19:57:03 -0500 From: Daniel Jacobowitz To: Yoni Rabinovitch Cc: linux-mips@linux-mips.org Subject: Re: Problems debugging multithreaded program wirh gdbserver via ser ial port Message-ID: <20041109005703.GA31331@nevyn.them.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.5.1+cvs20040105i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6280 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@debian.org Precedence: bulk X-list: linux-mips Content-Length: 564 Lines: 16 On Mon, Nov 08, 2004 at 05:53:40PM +0200, Yoni Rabinovitch wrote: > Running with "set debug serial 1" gives me the following: > > In the gdb session,I see lots of the following messages: > [O][K][#][9][a][$]Packet instead of Ack, ignoring it > > Simultaneously, in the gdbserver session (via minicom) I see: > +$OK#9a Um.... you're running with a serial port open on the same port you're trying to debug on? That can't work. Use one for console and the other for gdbserver, or come to some other arrangement if your board only has one. -- Daniel Jacobowitz From thomas.koeller@baslerweb.com Tue Nov 9 12:24:32 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 12:24:39 +0000 (GMT) Received: from mail.baslerweb.com ([IPv6:::ffff:145.253.187.130]:51534 "EHLO mail.baslerweb.com") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 12:24:32 +0000 Received: (from mail@localhost) by mail.baslerweb.com (8.12.10/8.12.10) id iA9CNJAE001081 for ; Tue, 9 Nov 2004 13:23:19 +0100 Received: from unknown by gateway id /var/KryptoWall/smtpp/kwk4WLSI; Tue Nov 09 13:23:10 2004 Received: from vclinux-1.basler.corp (localhost [172.16.13.253]) by comm1.baslerweb.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2657.72) id WHM64HZP; Tue, 9 Nov 2004 13:24:22 +0100 From: Thomas Koeller Organization: Basler AG To: linux-mips@linux-mips.org Subject: [PATCH] Function / prototype mismatch Date: Tue, 9 Nov 2004 13:28:42 +0100 User-Agent: KMail/1.6.2 MIME-Version: 1.0 Message-Id: <200411091328.42360.thomas.koeller@baslerweb.com> Content-Disposition: inline Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6281 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.koeller@baslerweb.com Precedence: bulk X-list: linux-mips Content-Length: 832 Lines: 32 The definition of do_IRQ() in arch/mips/kernel/irq.c does not match the prototype in include/asm-mips/irq.h, resulting in a compile error. tk Signed-off-by: Thomas Koeller --- linux-mips-cvs/arch/mips/kernel/irq.c 2004-11-09 11:43:46.921669824 +0100 +++ linux-mips-basler/arch/mips/kernel/irq.c 2004-11-09 13:18:46.496202792 +0100 @@ -45,7 +45,7 @@ * SMP cross-CPU interrupts have their own specific * handlers). */ -asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs) +asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs) { irq_enter(); -- -------------------------------------------------- Thomas Koeller, Software Development Basler Vision Technologies thomas dot koeller at baslerweb dot com http://www.baslerweb.com ============================== From hch@lst.de Tue Nov 9 12:45:50 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 12:45:55 +0000 (GMT) Received: from verein.lst.de ([IPv6:::ffff:213.95.11.210]:64420 "EHLO mail.lst.de") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 12:45:50 +0000 Received: from verein.lst.de (localhost [127.0.0.1]) by mail.lst.de (8.12.3/8.12.3/Debian-6.6) with ESMTP id iA9Cjlla005880 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Tue, 9 Nov 2004 13:45:47 +0100 Received: (from hch@localhost) by verein.lst.de (8.12.3/8.12.3/Debian-6.6) id iA9CjlMl005878; Tue, 9 Nov 2004 13:45:47 +0100 Date: Tue, 9 Nov 2004 13:45:47 +0100 From: Christoph Hellwig To: Thomas Koeller Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Function / prototype mismatch Message-ID: <20041109124547.GA5766@lst.de> References: <200411091328.42360.thomas.koeller@baslerweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200411091328.42360.thomas.koeller@baslerweb.com> User-Agent: Mutt/1.3.28i X-Spam-Score: -4.901 () BAYES_00 X-Scanned-By: MIMEDefang 2.39 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6282 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hch@lst.de Precedence: bulk X-list: linux-mips Content-Length: 309 Lines: 9 On Tue, Nov 09, 2004 at 01:28:42PM +0100, Thomas Koeller wrote: > The definition of do_IRQ() in arch/mips/kernel/irq.c > does not match the prototype in include/asm-mips/irq.h, > resulting in a compile error. might be worse to switch mips to the generic kernel/irq/ code whicg gets this right From ralf@linux-mips.org Tue Nov 9 12:54:37 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 12:54:41 +0000 (GMT) Received: from pD95621F5.dip.t-dialin.net ([IPv6:::ffff:217.86.33.245]:10300 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 12:54:37 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.12.11/8.12.8) with ESMTP id iA9CsVc9006358; Tue, 9 Nov 2004 13:54:31 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.12.11/8.12.11/Submit) id iA9CsIFH006354; Tue, 9 Nov 2004 13:54:18 +0100 Date: Tue, 9 Nov 2004 13:54:18 +0100 From: Ralf Baechle To: Christoph Hellwig Cc: Thomas Koeller , linux-mips@linux-mips.org Subject: Re: [PATCH] Function / prototype mismatch Message-ID: <20041109125418.GC5652@linux-mips.org> References: <200411091328.42360.thomas.koeller@baslerweb.com> <20041109124547.GA5766@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041109124547.GA5766@lst.de> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6283 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 270 Lines: 12 On Tue, Nov 09, 2004 at 01:45:47PM +0100, Christoph Hellwig wrote: > > might be worse to switch mips to the generic kernel/irq/ code > whicg gets this right > This has long happened and generic irq code doesn't even cover do_IRQ. Ralf From ralf@linux-mips.org Tue Nov 9 12:56:55 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 12:56:59 +0000 (GMT) Received: from pD95621F5.dip.t-dialin.net ([IPv6:::ffff:217.86.33.245]:13116 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 12:56:55 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.12.11/8.12.8) with ESMTP id iA9Cup2G006431; Tue, 9 Nov 2004 13:56:51 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.12.11/8.12.11/Submit) id iA9CupoD006430; Tue, 9 Nov 2004 13:56:51 +0100 Date: Tue, 9 Nov 2004 13:56:51 +0100 From: Ralf Baechle To: Thomas Koeller Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Function / prototype mismatch Message-ID: <20041109125651.GD5652@linux-mips.org> References: <200411091328.42360.thomas.koeller@baslerweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200411091328.42360.thomas.koeller@baslerweb.com> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6284 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 481 Lines: 14 On Tue, Nov 09, 2004 at 01:28:42PM +0100, Thomas Koeller wrote: > The definition of do_IRQ() in arch/mips/kernel/irq.c > does not match the prototype in include/asm-mips/irq.h, > resulting in a compile error. [ralf@fluff linux]$ grep -r do_IRQ include/linux include/linux/irq.h:extern asmlinkage unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs); [ralf@fluff linux]$ Just reposting somebody else's broken fix doesn't increase chances that I take a patch ... Ralf From hch@lst.de Tue Nov 9 12:59:14 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 12:59:18 +0000 (GMT) Received: from verein.lst.de ([IPv6:::ffff:213.95.11.210]:33445 "EHLO mail.lst.de") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 12:59:14 +0000 Received: from verein.lst.de (localhost [127.0.0.1]) by mail.lst.de (8.12.3/8.12.3/Debian-6.6) with ESMTP id iA9CxCla006236 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Tue, 9 Nov 2004 13:59:12 +0100 Received: (from hch@localhost) by verein.lst.de (8.12.3/8.12.3/Debian-6.6) id iA9CxC2O006234; Tue, 9 Nov 2004 13:59:12 +0100 Date: Tue, 9 Nov 2004 13:59:12 +0100 From: Christoph Hellwig To: Ralf Baechle Cc: Christoph Hellwig , Thomas Koeller , linux-mips@linux-mips.org Subject: Re: [PATCH] Function / prototype mismatch Message-ID: <20041109125912.GA6222@lst.de> References: <200411091328.42360.thomas.koeller@baslerweb.com> <20041109124547.GA5766@lst.de> <20041109125418.GC5652@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041109125418.GC5652@linux-mips.org> User-Agent: Mutt/1.3.28i X-Spam-Score: -4.901 () BAYES_00 X-Scanned-By: MIMEDefang 2.39 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6285 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hch@lst.de Precedence: bulk X-list: linux-mips Content-Length: 368 Lines: 13 On Tue, Nov 09, 2004 at 01:54:18PM +0100, Ralf Baechle wrote: > On Tue, Nov 09, 2004 at 01:45:47PM +0100, Christoph Hellwig wrote: > > > > > might be worse to switch mips to the generic kernel/irq/ code > > whicg gets this right > > > > > This has long happened and generic irq code doesn't even cover do_IRQ. Well, 90% of it as __do_IRQ ;-) From mansoor@isofttech.com Tue Nov 9 13:01:23 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 13:01:27 +0000 (GMT) Received: from illchn-static-203.199.202.17.vsnl.net.in ([IPv6:::ffff:203.199.202.17]:50951 "EHLO pub.isofttechindia.com") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 13:01:23 +0000 Received: from mansoor ([192.168.0.140]) by pub.isofttechindia.com (8.11.0/8.11.0) with SMTP id iA9D18f31189 for ; Tue, 9 Nov 2004 18:31:08 +0530 Message-ID: <04e601c4c65c$2fdc15a0$8c00a8c0@mansoor> From: "mansoor" To: Subject: Disabling lwc0 instruction Date: Tue, 9 Nov 2004 18:31:11 +0530 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1437 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1441 X-MailScanner: Found to be clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6286 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mansoor@isofttech.com Precedence: bulk X-list: linux-mips Content-Length: 540 Lines: 26 Hi all, Iam working on lx4189. This core doesnt support "lwc0" instruction but my tool chain generates this instruction. So when I run some applications it throws "unknown instruction" exception. How can solve this issue ? I have few solutions but I dont know whether its correct. 1) Re-build the toolchain with this instruction disbaled. But how to do this ?. 2) Write an exception handler to handle this instruction. The exact replacement would be "mfc0". how to do this ? Thanx in advance Mansoor Ahamed Basheer From ralf@linux-mips.org Tue Nov 9 13:24:26 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 13:24:31 +0000 (GMT) Received: from pD95621F5.dip.t-dialin.net ([IPv6:::ffff:217.86.33.245]:35644 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 13:24:26 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.12.11/8.12.8) with ESMTP id iA9DOIdf000979; Tue, 9 Nov 2004 14:24:18 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.12.11/8.12.11/Submit) id iA9DOI4x000978; Tue, 9 Nov 2004 14:24:18 +0100 Date: Tue, 9 Nov 2004 14:24:18 +0100 From: Ralf Baechle To: mansoor Cc: linux-mips@linux-mips.org Subject: Re: Disabling lwc0 instruction Message-ID: <20041109132418.GE5652@linux-mips.org> References: <04e601c4c65c$2fdc15a0$8c00a8c0@mansoor> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <04e601c4c65c$2fdc15a0$8c00a8c0@mansoor> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6287 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1083 Lines: 31 On Tue, Nov 09, 2004 at 06:31:11PM +0530, mansoor wrote: > Iam working on lx4189. This core doesnt support > "lwc0" instruction but my tool chain generates > this instruction. > > So when I run some applications it throws > "unknown instruction" exception. > > How can solve this issue ? > > I have few solutions but I dont know > whether its correct. > > > 1) Re-build the toolchain with this instruction > disbaled. But how to do this ?. > 2) Write an exception handler to handle this > instruction. The exact replacement would be > "mfc0". how to do this ? No. lwc0 is ll, load linked. In 2.6 define cpu_has_llsc to return 0 in your system's cpu-feature-override.h. In 2.4 disable CONFIG_CPU_HAS_LLSC. The kernel actually has an emulation for ll/sc in applications which enables running of application code using ll/sc on ll/sc-less processors. You should try to find why this seems to fail for you. Maybe this Lexra kernel is simply super-ancient? If it's as old as it seems you should replace it as it has various exploitable security holes. Ralf From ralf@linux-mips.org Tue Nov 9 13:25:16 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 13:25:20 +0000 (GMT) Received: from pD95621F5.dip.t-dialin.net ([IPv6:::ffff:217.86.33.245]:37180 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 13:25:16 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.12.11/8.12.8) with ESMTP id iA9DP9Gt001029; Tue, 9 Nov 2004 14:25:09 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.12.11/8.12.11/Submit) id iA9DP9H4001028; Tue, 9 Nov 2004 14:25:09 +0100 Date: Tue, 9 Nov 2004 14:25:09 +0100 From: Ralf Baechle To: Christoph Hellwig Cc: Thomas Koeller , linux-mips@linux-mips.org Subject: Re: [PATCH] Function / prototype mismatch Message-ID: <20041109132509.GA983@linux-mips.org> References: <200411091328.42360.thomas.koeller@baslerweb.com> <20041109124547.GA5766@lst.de> <20041109125418.GC5652@linux-mips.org> <20041109125912.GA6222@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041109125912.GA6222@lst.de> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6288 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 180 Lines: 7 On Tue, Nov 09, 2004 at 01:59:12PM +0100, Christoph Hellwig wrote: > Well, 90% of it as __do_IRQ ;-) Would seem natural to have the same prototype for both, wouldn't it? Ralf From Yoni.Rabinovich@Teledata-Networks.com Tue Nov 9 16:09:57 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 16:10:02 +0000 (GMT) Received: from [IPv6:::ffff:194.90.152.129] ([IPv6:::ffff:194.90.152.129]:33432 "EHLO mr.teledata-networks.com") by linux-mips.org with ESMTP id convert rfc822-to-8bit; Tue, 9 Nov 2004 16:09:57 +0000 Received: from mr.teledata-networks.com (localhost.localdomain [127.0.0.1]) by localhost.teledata-networks.com (Postfix) with ESMTP id E4B9E7C0070; Tue, 9 Nov 2004 18:08:09 +0200 (IST) Received: from tndcmail.Teledata.Local (ADC-FW.ser.netvision.net.il [199.203 .98.2])by mr.teledata-networks.com (Postfix) with ESMTPid D97177C006B; Tue, 9 Nov 2004 11:08:09 -0500 (EST) Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Subject: RE: Problems debugging multithreaded program wirh gdbserver via ser ial port X-MimeOLE: Produced By Microsoft Exchange V6.5.7226.0 Date: Tue, 9 Nov 2004 18:08:47 +0200 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Problems debugging multithreaded program wirh gdbserver via se r ial port Thread-Index: AcTF9uhy1PNdWjCyRbSJLlefLizejgAfkIvg From: "Yoni Rabinovitch" To: "Daniel Jacobowitz" Cc: X-imss-version: 2.0 X-imss-result: Passed X-imss-scores: Clean:34.41925 C:20 M:1 S:5 R:5 X-imss-settings: Baseline:1 C:1 M:1 S:1 R:1 (0.0000 0.0000) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6289 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Yoni.Rabinovich@Teledata-Networks.com Precedence: bulk X-list: linux-mips Content-Length: 1014 Lines: 23 >> Simultaneously, in the gdbserver session (via minicom) I see: >> +$OK#9a >Um.... you're running with a serial port open on the same port you're >trying to debug on? That can't work. Use one for console and the >other for gdbserver, or come to some other arrangement if your board >only has one. OK, thanks. I now have this sorted out. It seems the only way it agrees to work is if I start gdbserver in a minicom session, and then kill -9 the minicom session, and then connect with gdb. So, now I have basic (command line) gdb <-> gdbserver working OK over the serial connection. However, I am trying to run gdb from a GUI front end, which is running gdb/mi. What I am seeing is that the GUI is invoking gdb/mi stack-info-depth, which seems to be causing a memory exception in frame_register_unwind ("Cannot access memory at address 0x2c"). Thus, even though gdb is able to decipher the stack, the error at the end of the backtrace causes the gdb/mi GUI to choke. How can I work around this ? Thanks !! From ralf@linux-mips.org Tue Nov 9 20:00:00 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 20:00:07 +0000 (GMT) Received: from pD95621F5.dip.t-dialin.net ([IPv6:::ffff:217.86.33.245]:32579 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 20:00:00 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.12.11/8.12.8) with ESMTP id iA9JxxXE025513; Tue, 9 Nov 2004 20:59:59 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.12.11/8.12.11/Submit) id iA9Jxr7p025512; Tue, 9 Nov 2004 20:59:53 +0100 Date: Tue, 9 Nov 2004 20:59:53 +0100 From: Ralf Baechle To: Manish Lachwani Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Small fix for the Sibyte Mac driver Message-ID: <20041109195953.GA25337@linux-mips.org> References: <20041108235148.GA20991@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041108235148.GA20991@prometheus.mvista.com> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6290 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 948 Lines: 25 On Mon, Nov 08, 2004 at 03:51:48PM -0800, Manish Lachwani wrote: > Attached is a small patch for the Sibyte MAC Driver. This helps > print the device name correctly > - /* This is needed for PASS2 for Rx H/W checksum feature */ > - sbmac_set_iphdr_offset(sc); > - > err = register_netdev(dev); > if (err) > goto out_uninit; > > + /* This is needed for PASS2 for Rx H/W checksum feature */ > + sbmac_set_iphdr_offset(sc); > + Your patch introduces a race condition - the NIC needs to be fully setup before register_netdev. By the time register_netdev returns the driver could possibly already be opened and traffic be flowing. What's usually done is using the PCI device's name as obtained through pci_name(). Which in this case fails, so maybe you should convert the driver to a platform_device() and print platform_device->name instead. The Titan GE driver which I think you're familiar with already use platform_device ;-) Ralf From mlachwani@mvista.com Tue Nov 9 20:50:56 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 20:51:02 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:63740 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 20:50:56 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 1F390185C2; Tue, 9 Nov 2004 12:50:53 -0800 (PST) Message-ID: <41912DAC.6070905@mvista.com> Date: Tue, 09 Nov 2004 12:50:52 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Small fix for the Sibyte Mac driver References: <20041108235148.GA20991@prometheus.mvista.com> <20041109195953.GA25337@linux-mips.org> In-Reply-To: <20041109195953.GA25337@linux-mips.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6291 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1400 Lines: 43 Ralf Baechle wrote: > On Mon, Nov 08, 2004 at 03:51:48PM -0800, Manish Lachwani wrote: > > >>Attached is a small patch for the Sibyte MAC Driver. This helps >>print the device name correctly > > >>- /* This is needed for PASS2 for Rx H/W checksum feature */ >>- sbmac_set_iphdr_offset(sc); >>- >> err = register_netdev(dev); >> if (err) >> goto out_uninit; >> >>+ /* This is needed for PASS2 for Rx H/W checksum feature */ >>+ sbmac_set_iphdr_offset(sc); >>+ > > > Your patch introduces a race condition - the NIC needs to be fully setup > before register_netdev. By the time register_netdev returns the driver > could possibly already be opened and traffic be flowing. What's usually > done is using the PCI device's name as obtained through pci_name(). > Which in this case fails, so maybe you should convert the driver to a > platform_device() and print platform_device->name instead. The Titan GE > driver which I think you're familiar with already use platform_device ;-) > > Ralf > Hi Ralf Thanks for the response. To make it really simple and avoid lot of changes to the driver code, we can continue to do sbmac_set_iphdr_offset() before the call to register_netdev() and print the "...enabling TCP rcv checksum" after register_netdev(). Since we need the driver to print the device name correctly, this change can keep things really simple :) Thanks Manish Lachwani From ralf@linux-mips.org Tue Nov 9 21:43:56 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 21:44:00 +0000 (GMT) Received: from pD95621F5.dip.t-dialin.net ([IPv6:::ffff:217.86.33.245]:35909 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 21:43:56 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.12.11/8.12.8) with ESMTP id iA9Lhlap028324; Tue, 9 Nov 2004 22:43:47 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.12.11/8.12.11/Submit) id iA9Lhhlw028323; Tue, 9 Nov 2004 22:43:43 +0100 Date: Tue, 9 Nov 2004 22:43:43 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH] add iomap funtions Message-ID: <20041109214343.GA28260@linux-mips.org> References: <20041105011317.012b10ad.yuasa@hh.iij4u.or.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041105011317.012b10ad.yuasa@hh.iij4u.or.jp> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6292 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 216 Lines: 8 On Fri, Nov 05, 2004 at 01:13:17AM +0900, Yoichi Yuasa wrote: > This patch adds iomap functions to MIPS system. > Please apply this patch to v2.6. Any reason you're not simply setting CONFIG_GENERIC_IOMAP? Ralf From yuasa@hh.iij4u.or.jp Tue Nov 9 22:43:02 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Nov 2004 22:43:07 +0000 (GMT) Received: from mo00.iij4u.or.jp ([IPv6:::ffff:210.130.0.19]:29664 "EHLO mo00.iij4u.or.jp") by linux-mips.org with ESMTP id ; Tue, 9 Nov 2004 22:43:02 +0000 Received: MO(mo00)id iA9MgxDR017839; Wed, 10 Nov 2004 07:42:59 +0900 (JST) Received: MDO(mdo01) id iA9MgxiL028871; Wed, 10 Nov 2004 07:42:59 +0900 (JST) Received: 4UMRO00 id iA9Mgwmb016785; Wed, 10 Nov 2004 07:42:58 +0900 (JST) from stratos (localhost [127.0.0.1]) (authenticated) Date: Wed, 10 Nov 2004 07:42:53 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@hh.iij4u.or.jp, linux-mips@linux-mips.org Subject: Re: [PATCH] add iomap funtions Message-Id: <20041110074253.231ffa42.yuasa@hh.iij4u.or.jp> In-Reply-To: <20041109214343.GA28260@linux-mips.org> References: <20041105011317.012b10ad.yuasa@hh.iij4u.or.jp> <20041109214343.GA28260@linux-mips.org> X-Mailer: Sylpheed version 0.9.99 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6293 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@hh.iij4u.or.jp Precedence: bulk X-list: linux-mips Content-Length: 438 Lines: 16 Hi Ralf, On Tue, 9 Nov 2004 22:43:43 +0100 Ralf Baechle wrote: > On Fri, Nov 05, 2004 at 01:13:17AM +0900, Yoichi Yuasa wrote: > > > This patch adds iomap functions to MIPS system. > > Please apply this patch to v2.6. > > Any reason you're not simply setting CONFIG_GENERIC_IOMAP? PIO and MMIO cannot be judged from an address. I thought that PIO_MASK/PIO_RESERVED/PIO_OFFSET was not suitable for MIPS. Yoichi From r.zilli@ingredium.it Wed Nov 10 09:22:44 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Nov 2004 09:22:51 +0000 (GMT) Received: from host195-84.pool217141.interbusiness.it ([IPv6:::ffff:217.141.84.195]:19211 "EHLO ingredium.it") by linux-mips.org with ESMTP id ; Wed, 10 Nov 2004 09:22:44 +0000 Received: (qmail 66376 invoked by uid 89); 10 Nov 2004 09:22:42 -0000 Message-ID: <20041110092242.66375.qmail@ingredium.it> From: "r.zilli" To: linux-mips@linux-mips.org Subject: HPT 371N kernel 2.4.26 Date: Wed, 10 Nov 2004 10:22:42 +0100 Mime-Version: 1.0 Content-Type: text/plain; format=flowed; charset="utf-8" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6294 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: r.zilli@ingredium.it Precedence: bulk X-list: linux-mips Content-Length: 359 Lines: 14 Hi guys, there is a problem on HPT371N HD controller, it's working only if i compile the kernel 2.4.26 with CONFIG_IDEPCI_SHARE_IRQ flag. It is not completely working, in the sense that during the phase of writing the machine is frozen. Meanwhile on the evaluation board Au1500 with HPT370A it's working very well. Anyone have patch this? Roberto From huangyk@gmail.com Wed Nov 10 17:16:34 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Nov 2004 17:16:40 +0000 (GMT) Received: from mproxy.gmail.com ([IPv6:::ffff:216.239.56.245]:42885 "EHLO mproxy.gmail.com") by linux-mips.org with ESMTP id ; Wed, 10 Nov 2004 17:16:34 +0000 Received: by mproxy.gmail.com with SMTP id x71so221410cwb for ; Wed, 10 Nov 2004 09:16:28 -0800 (PST) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:reply-to:to:subject:mime-version:content-type:content-transfer-encoding; b=NSZn+5RIGnm7h92SL3iqcdCHMJU3O6AWyRBFHzMDexGWyfwMy0jEMUX6Ns2DAeLPvX65L9hpUqW61wxo4KuCN6Raec5l//DDevOZ9fhM75Oc7Pips8WnOcyxx8eLPIKqAHvmJnZn7+kyOFBzeulIlesE5PdvqJE8bBJVF162TRo= Received: by 10.11.100.47 with SMTP id x47mr246778cwb; Wed, 10 Nov 2004 09:16:28 -0800 (PST) Received: by 10.11.98.17 with HTTP; Wed, 10 Nov 2004 09:16:28 -0800 (PST) Message-ID: <8498a8b00411100916544a804e@mail.gmail.com> Date: Wed, 10 Nov 2004 12:16:28 -0500 From: Kang Reply-To: Kang To: linux-mips@linux-mips.org Subject: Problem caused by changing PAGE_OFFSET from 0x80000000 to 0x91000000 Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6295 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: huangyk@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 3399 Lines: 95 Hello buddies, I am working on linux-2.4.20 support for a MIPS4Kc based reference design board. For some reason, I need to load and execute kernel at a non-standard address 0x91xxxxxx instead of 0x80xxxxxx. Regarding the memory management/paging stuff, I tried changing the PAGE_OFFSET variable to 0x91000000 in page.h, the UNCAC_BASE variable was changed to 0xb1000000 at the same time. So far the physical RAM map looks fine to me, the memory initialization works fine. The RAMDISK seems like to be loaded to correct address and the size is correct. But I got a "length error" when the kernel tried to decompress the RAMDISK, the original length seemed to be corrupted. The bytes_out value matched with the size of uncompressed RAMDISK size. Then I got a "Reserved instruction in kernel code in traps.c::do_ri, line 652:" kernel panic. I don't know whether it is the PAGE_OFFSET change caused this problem. Probably some page alignment issue. In addition to the PAGE_OFFSET value change, any other place I should change to fix this problem? Can anybody enlighten me? The log message is attched. Thanks a lot. Leo **************************************************************** Determined physical RAM map: memory: 00001000 @ 11000000 (reserved) memory: 000ef000 @ 11001000 (ROM data) memory: 00010000 @ 110f0000 (ROM data) memory: 001ac000 @ 11100000 (reserved) memory: 03d54000 @ 112ac000 (usable) Initial ramdisk at: 0x912ac000 (1002027 bytes) On node 0 totalpages: 16384 zone(0): 16384 pages. zone(1): 0 pages. zone(2): 0 pages. Kernel command line: console=ttyS0,38400 calculating r4koff... 000f422a(999978) CPU frequency 200.00 MHz Calibrating delay loop... 199.47 BogoMIPS Memory: 61108k/62800k available (1376k kernel code, 1692k reserved, 92k data, 72k init, 0k highmem) Dentry cache hash table entries: 8192 (order: 4, 65536 bytes) Inode cache hash table entries: 4096 (order: 3, 32768 bytes) Mount-cache hash table entries: 1024 (order: 1, 8192 bytes) Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes) Page-cache hash table entries: 16384 (order: 4, 65536 bytes) Checking for 'wait' instruction... available. POSIX conformance testing by UNIFIX Autoconfig PCI channel 0x91286db0 ...................................... RAMDISK: Compressed image found at block 0 orig_len: ff74a400 bytes_out: 74a400 Freeing initrd memory: 978k freed VFS: Mounted root (ext2 filesystem) readonly. Freeing prom memory: 1020kb freed Freeing unused kernel memory: 72k freed Reserved instruction in kernel code in traps.c::do_ri, line 652: $0 : 00000000 1050ff00 2ab07ff8 2ab07ff8 2ab05748 00000000 000008f8 000008f8 $8 : 00000038 2ab05fc8 2ab05708 00001000 00000005 00000080 913abb70 000008fa $16: 2ab05000 913abc70 00000080 2ab05708 913d61a0 00000001 2ab05730 2aac0000 $24: 00000000 00000080 913aa000 913abbb0 913abcd4 91156384 Hi : 00000000 Lo : 00000180 epc : 91230d34 Not tainted Status: 1050ff03 Cause : 30800028 The kernel hung just after the interrupt was first time opened, after sti(), before calibrate_delay() in init/main.c. It was weird that I didn't see any problem if I put interrupt vector to location 0x80000200 while all other exception vectors to 0x91xxxxxx. Was interrupt vector location hardcode to the address 0x80000200? Or some other place I need to change to walk around it. Any idea? Thanks a bunch for your help. Leo From macro@mips.com Wed Nov 10 17:18:24 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Nov 2004 17:18:31 +0000 (GMT) Received: from alg145.algor.co.uk ([IPv6:::ffff:62.254.210.145]:30221 "EHLO dmz.algor.co.uk") by linux-mips.org with ESMTP id ; Wed, 10 Nov 2004 17:18:24 +0000 Received: from alg158.algor.co.uk ([62.254.210.158] helo=olympia.mips.com) by dmz.algor.co.uk with esmtp (Exim 3.35 #1 (Debian)) id 1CRwF3-0002lA-00; Wed, 10 Nov 2004 17:26:45 +0000 Received: from perivale.mips.com ([192.168.192.200]) by olympia.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1CRw6c-0007E3-00; Wed, 10 Nov 2004 17:18:02 +0000 Received: from macro (helo=localhost) by perivale.mips.com with local-esmtp (Exim 3.36 #1 (Debian)) id 1CRw6c-00036t-00; Wed, 10 Nov 2004 17:18:02 +0000 Date: Wed, 10 Nov 2004 17:18:02 +0000 (GMT) From: "Maciej W. Rozycki" To: Ralf Baechle , linux-mips@linux-mips.org, libc-alpha@sources.redhat.com cc: Nigel Stephens , "Maciej W. Rozycki" Subject: [PATCH] MIPS/Linux: Kernel vs libc struct siginfo discrepancy Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-MTUK-Scanner: Found to be clean X-MTUK-SpamCheck: not spam, SpamAssassin (score=-4.803, required 4, AWL, BAYES_00) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6296 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@mips.com Precedence: bulk X-list: linux-mips Content-Length: 2568 Lines: 58 Hello, Since the following change: http://www.linux-mips.org/cvsweb/linux/include/asm-mips/siginfo.h.diff?r1=1.4&r2=1.5&only_with_tag=MAIN dated back to Aug 1999 (!), the definitions of struct siginfo in Linux and GNU libc differ to each other. While it's the kernel that is at fault by changing its ABI, at this stage it may be more acceptable to update glibc as it's not the only program interfacing to Linux (uClibc?). It doesn't seem to be a heavily used feature as otherwise someone else would have noticed the problem during these five years. As I don't really have a preference, hereby I provide two patches to choose from and ask for voting. The ChangeLog entry is for glibc, of course. 2004-11-10 Maciej W. Rozycki * sysdeps/unix/sysv/linux/mips/bits/siginfo.h [struct siginfo] (_sigchld): Update to match the kernel. Maciej glibc-2.3.3-20041018-mips-siginfo_sigchld-1.patch diff -up --recursive --new-file glibc-2.3.3-20041018.macro/sysdeps/unix/sysv/linux/bits/siginfo.h glibc-2.3.3-20041018/sysdeps/unix/sysv/linux/bits/siginfo.h --- glibc-2.3.3-20041018.macro/sysdeps/unix/sysv/linux/bits/siginfo.h Tue Apr 22 02:26:04 2003 +++ glibc-2.3.3-20041018/sysdeps/unix/sysv/linux/bits/siginfo.h Wed Nov 10 16:52:24 2004 @@ -1,5 +1,5 @@ /* siginfo_t, sigevent and constants. Linux version. - Copyright (C) 1997-2002, 2003 Free Software Foundation, Inc. + Copyright (C) 1997-2002, 2003, 2004 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or @@ -87,8 +87,8 @@ typedef struct siginfo { __pid_t si_pid; /* Which child. */ __uid_t si_uid; /* Real user ID of sending process. */ - int si_status; /* Exit value or signal. */ __clock_t si_utime; + int si_status; /* Exit value or signal. */ __clock_t si_stime; } _sigchld; patch-malta-2.6.9-rc1-20041020-mips-siginfo_sigchld-0 diff -up --recursive --new-file linux-malta-2.6.9-rc1-20041020.macro/include/asm-mips/siginfo.h linux-malta-2.6.9-rc1-20041020/include/asm-mips/siginfo.h --- linux-malta-2.6.9-rc1-20041020.macro/include/asm-mips/siginfo.h 2004-10-01 14:49:33.000000000 +0000 +++ linux-malta-2.6.9-rc1-20041020/include/asm-mips/siginfo.h 2004-11-10 16:53:42.000000000 +0000 @@ -47,8 +47,8 @@ typedef struct siginfo { struct { pid_t _pid; /* which child */ uid_t _uid; /* sender's uid */ - clock_t _utime; int _status; /* exit code */ + clock_t _utime; clock_t _stime; } _sigchld; From ica2_ts@csv.ica.uni-stuttgart.de Wed Nov 10 18:00:59 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Nov 2004 18:01:05 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:62282 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Wed, 10 Nov 2004 18:00:59 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CRwm3-0003Fk-00; Wed, 10 Nov 2004 19:00:51 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CRwm2-0006LG-00; Wed, 10 Nov 2004 19:00:50 +0100 Date: Wed, 10 Nov 2004 19:00:50 +0100 To: "Maciej W. Rozycki" Cc: Ralf Baechle , linux-mips@linux-mips.org, libc-alpha@sources.redhat.com, Nigel Stephens Subject: Re: [PATCH] MIPS/Linux: Kernel vs libc struct siginfo discrepancy Message-ID: <20041110180050.GK7235@rembrandt.csv.ica.uni-stuttgart.de> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6297 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 1547 Lines: 38 Maciej W. Rozycki wrote: > Hello, > > Since the following change: > > http://www.linux-mips.org/cvsweb/linux/include/asm-mips/siginfo.h.diff?r1=1.4&r2=1.5&only_with_tag=MAIN > > dated back to Aug 1999 (!), the definitions of struct siginfo in Linux and > GNU libc differ to each other. Only 2.4 Kernels, 2.6 uses the normal definition again. > While it's the kernel that is at fault by > changing its ABI, at this stage it may be more acceptable to update glibc > as it's not the only program interfacing to Linux (uClibc?). It doesn't > seem to be a heavily used feature as otherwise someone else would have > noticed the problem during these five years. As I don't really have a > preference, hereby I provide two patches to choose from and ask for > voting. I prefer to bring the 2.4 kernel in line with the rest of the system. > The ChangeLog entry is for glibc, of course. > > 2004-11-10 Maciej W. Rozycki > > * sysdeps/unix/sysv/linux/mips/bits/siginfo.h [struct siginfo] > (_sigchld): Update to match the kernel. > > Maciej > > glibc-2.3.3-20041018-mips-siginfo_sigchld-1.patch > diff -up --recursive --new-file glibc-2.3.3-20041018.macro/sysdeps/unix/sysv/linux/bits/siginfo.h glibc-2.3.3-20041018/sysdeps/unix/sysv/linux/bits/siginfo.h > --- glibc-2.3.3-20041018.macro/sysdeps/unix/sysv/linux/bits/siginfo.h Tue Apr 22 02:26:04 2003 > +++ glibc-2.3.3-20041018/sysdeps/unix/sysv/linux/bits/siginfo.h Wed Nov 10 16:52:24 2004 You surely meant to change the mips-specific siginfo.h here. From macro@mips.com Wed Nov 10 18:19:40 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Nov 2004 18:19:45 +0000 (GMT) Received: from alg145.algor.co.uk ([IPv6:::ffff:62.254.210.145]:16403 "EHLO dmz.algor.co.uk") by linux-mips.org with ESMTP id ; Wed, 10 Nov 2004 18:19:40 +0000 Received: from alg158.algor.co.uk ([62.254.210.158] helo=olympia.mips.com) by dmz.algor.co.uk with esmtp (Exim 3.35 #1 (Debian)) id 1CRxCG-0003r5-00; Wed, 10 Nov 2004 18:27:56 +0000 Received: from perivale.mips.com ([192.168.192.200]) by olympia.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1CRx3q-00080f-00; Wed, 10 Nov 2004 18:19:14 +0000 Received: from macro (helo=localhost) by perivale.mips.com with local-esmtp (Exim 3.36 #1 (Debian)) id 1CRx3q-00037P-00; Wed, 10 Nov 2004 18:19:14 +0000 Date: Wed, 10 Nov 2004 18:19:14 +0000 (GMT) From: "Maciej W. Rozycki" To: Thiemo Seufer cc: Ralf Baechle , linux-mips@linux-mips.org, libc-alpha@sources.redhat.com, Nigel Stephens , "Maciej W. Rozycki" Subject: Re: [PATCH] MIPS/Linux: Kernel vs libc struct siginfo discrepancy In-Reply-To: <20041110180050.GK7235@rembrandt.csv.ica.uni-stuttgart.de> Message-ID: References: <20041110180050.GK7235@rembrandt.csv.ica.uni-stuttgart.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-MTUK-Scanner: Found to be clean X-MTUK-SpamCheck: not spam, SpamAssassin (score=-4.805, required 4, AWL, BAYES_00) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6298 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@mips.com Precedence: bulk X-list: linux-mips Content-Length: 1848 Lines: 46 On Wed, 10 Nov 2004, Thiemo Seufer wrote: > > Since the following change: > > > > http://www.linux-mips.org/cvsweb/linux/include/asm-mips/siginfo.h.diff?r1=1.4&r2=1.5&only_with_tag=MAIN > > > > dated back to Aug 1999 (!), the definitions of struct siginfo in Linux and > > GNU libc differ to each other. > > Only 2.4 Kernels, 2.6 uses the normal definition again. Ah, it's been changed again for 2.6.9-rc3 without a word of a comment, grrr... > > While it's the kernel that is at fault by > > changing its ABI, at this stage it may be more acceptable to update glibc > > as it's not the only program interfacing to Linux (uClibc?). It doesn't > > seem to be a heavily used feature as otherwise someone else would have > > noticed the problem during these five years. As I don't really have a > > preference, hereby I provide two patches to choose from and ask for > > voting. > > I prefer to bring the 2.4 kernel in line with the rest of the system. OK for me. > You surely meant to change the mips-specific siginfo.h here. Thanks for spotting it. Here's an update just in case. Maciej glibc-2.3.3-20041018-mips-siginfo_sigchld-2.patch diff -up --recursive --new-file glibc-2.3.3-20041018.macro/sysdeps/unix/sysv/linux/mips/bits/siginfo.h glibc-2.3.3-20041018/sysdeps/unix/sysv/linux/mips/bits/siginfo.h --- glibc-2.3.3-20041018.macro/sysdeps/unix/sysv/linux/mips/bits/siginfo.h Fri May 23 02:26:20 2003 +++ glibc-2.3.3-20041018/sysdeps/unix/sysv/linux/mips/bits/siginfo.h Wed Nov 10 18:06:51 2004 @@ -65,8 +65,8 @@ typedef struct siginfo { __pid_t si_pid; /* Which child. */ __uid_t si_uid; /* Real user ID of sending process. */ - int si_status; /* Exit value or signal. */ __clock_t si_utime; + int si_status; /* Exit value or signal. */ __clock_t si_stime; } _sigchld; From ppopov@embeddedalley.com Wed Nov 10 18:26:47 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 10 Nov 2004 18:26:53 +0000 (GMT) Received: from web81001.mail.yahoo.com ([IPv6:::ffff:206.190.37.146]:57248 "HELO web81001.mail.yahoo.com") by linux-mips.org with SMTP id ; Wed, 10 Nov 2004 18:26:47 +0000 Message-ID: <20041110182638.80909.qmail@web81001.mail.yahoo.com> Received: from [63.194.214.47] by web81001.mail.yahoo.com via HTTP; Wed, 10 Nov 2004 10:26:37 PST X-RocketYMMF: pvpopov@pacbell.net Date: Wed, 10 Nov 2004 10:26:37 -0800 (PST) From: Pete Popov Reply-To: ppopov@embeddedalley.com Subject: Re: HPT 371N kernel 2.4.26 To: "r.zilli" , linux-mips@linux-mips.org In-Reply-To: <20041110092242.66375.qmail@ingredium.it> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6299 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ppopov@embeddedalley.com Precedence: bulk X-list: linux-mips Content-Length: 544 Lines: 28 I have a small patch in my directory: ftp.linux-mips.org:/pub/linux/mips/people/ppopov/2.4 Pete --- "r.zilli" wrote: > > Hi guys, > > there is a problem on HPT371N HD controller, it's > working only if i compile > the kernel 2.4.26 with CONFIG_IDEPCI_SHARE_IRQ flag. > It is not completely working, in the sense that > during the phase of writing > the machine is frozen. > Meanwhile on the evaluation board Au1500 with > HPT370A it's working very > well. > > Anyone have patch this? > > Roberto > > > From ralf@linux-mips.org Thu Nov 11 01:48:08 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2004 01:48:13 +0000 (GMT) Received: from pD95629F8.dip.t-dialin.net ([IPv6:::ffff:217.86.41.248]:35604 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Thu, 11 Nov 2004 01:48:08 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAB1m6JD030065; Thu, 11 Nov 2004 02:48:06 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAB1lxHF030064; Thu, 11 Nov 2004 02:47:59 +0100 Date: Thu, 11 Nov 2004 02:47:59 +0100 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@linux-mips.org, libc-alpha@sources.redhat.com, Nigel Stephens , "Maciej W. Rozycki" Subject: Re: [PATCH] MIPS/Linux: Kernel vs libc struct siginfo discrepancy Message-ID: <20041111014759.GA29699@linux-mips.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6300 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 651 Lines: 14 On Wed, Nov 10, 2004 at 05:18:02PM +0000, Maciej W. Rozycki wrote: > http://www.linux-mips.org/cvsweb/linux/include/asm-mips/siginfo.h.diff?r1=1.4&r2=1.5&only_with_tag=MAIN > > dated back to Aug 1999 (!), the definitions of struct siginfo in Linux and > GNU libc differ to each other. While it's the kernel that is at fault by > changing its ABI, at this stage it may be more acceptable to update glibc > as it's not the only program interfacing to Linux (uClibc?). It doesn't uClibc copies it's headers from glibc it seems. The change in 1999 was quite intensional because back then there was no SA_SIGINFO using libc for MIPS yet. Ralf From ralf@linux-mips.org Thu Nov 11 01:58:04 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2004 01:58:08 +0000 (GMT) Received: from pD95629F8.dip.t-dialin.net ([IPv6:::ffff:217.86.41.248]:47892 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Thu, 11 Nov 2004 01:58:04 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAB1u3MK030275; Thu, 11 Nov 2004 02:56:03 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAB1u0oT030274; Thu, 11 Nov 2004 02:56:00 +0100 Date: Thu, 11 Nov 2004 02:56:00 +0100 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: Thiemo Seufer , linux-mips@linux-mips.org, libc-alpha@sources.redhat.com, Nigel Stephens , "Maciej W. Rozycki" Subject: Re: [PATCH] MIPS/Linux: Kernel vs libc struct siginfo discrepancy Message-ID: <20041111015600.GA30150@linux-mips.org> References: <20041110180050.GK7235@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6301 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 543 Lines: 16 On Wed, Nov 10, 2004 at 06:19:14PM +0000, Maciej W. Rozycki wrote: > > > http://www.linux-mips.org/cvsweb/linux/include/asm-mips/siginfo.h.diff?r1=1.4&r2=1.5&only_with_tag=MAIN > > > > > > dated back to Aug 1999 (!), the definitions of struct siginfo in Linux and > > > GNU libc differ to each other. > > > > Only 2.4 Kernels, 2.6 uses the normal definition again. > > Ah, it's been changed again for 2.6.9-rc3 without a word of a comment, > grrr... Yoichi Yuasa sent this patch upstream without notifying anybody. GRRRR also. Ralf From macro@linux-mips.org Thu Nov 11 02:39:35 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2004 02:39:39 +0000 (GMT) Received: from pollux.ds.pg.gda.pl ([IPv6:::ffff:153.19.208.7]:41479 "EHLO pollux.ds.pg.gda.pl") by linux-mips.org with ESMTP id ; Thu, 11 Nov 2004 02:39:35 +0000 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 7E268F596F; Thu, 11 Nov 2004 03:39:27 +0100 (CET) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 10744-10; Thu, 11 Nov 2004 03:39:27 +0100 (CET) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 4E7A2E1C9A; Thu, 11 Nov 2004 03:39:27 +0100 (CET) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.1/8.13.1) with ESMTP id iAB2diMO000698; Thu, 11 Nov 2004 03:39:44 +0100 Date: Thu, 11 Nov 2004 02:39:29 +0000 (GMT) From: "Maciej W. Rozycki" To: Ralf Baechle Cc: "Maciej W. Rozycki" , linux-mips@linux-mips.org, libc-alpha@sources.redhat.com, Nigel Stephens Subject: Re: [PATCH] MIPS/Linux: Kernel vs libc struct siginfo discrepancy In-Reply-To: <20041111014759.GA29699@linux-mips.org> Message-ID: References: <20041111014759.GA29699@linux-mips.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.80/578/Mon Nov 8 15:26:49 2004 clamav-milter version 0.80j on piorun.ds.pg.gda.pl X-Virus-Status: Clean X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6302 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1073 Lines: 21 On Thu, 11 Nov 2004, Ralf Baechle wrote: > > dated back to Aug 1999 (!), the definitions of struct siginfo in Linux and > > GNU libc differ to each other. While it's the kernel that is at fault by > > changing its ABI, at this stage it may be more acceptable to update glibc > > as it's not the only program interfacing to Linux (uClibc?). It doesn't > > uClibc copies it's headers from glibc it seems. The change in 1999 was > quite intensional because back then there was no SA_SIGINFO using libc for > MIPS yet. Well, I'm afraid the glibc's header dates back to Jan 1999, so it predates the change to Linux and this is why it uses the original definition. Of course I know what the relationship between MIPS/Linux and glibc was back then and problems like this prove this wasn't the best idea ever. They are the very reason I insist on pushing changes upstream as soon as possible. Otherwise fixes get forgotten or lost as patches for old versions get discarded. This change should have made its way to glibc at the time of the change to Linux. Maciej From ho.tan@avantec.com.hk Thu Nov 11 08:10:00 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2004 08:10:05 +0000 (GMT) Received: from hmail02.netvigator.com ([IPv6:::ffff:218.102.23.141]:30652 "EHLO hmail02dat.netvigator.com") by linux-mips.org with ESMTP id ; Thu, 11 Nov 2004 08:10:00 +0000 Received: from HughTan ([220.246.1.125]) by hmail02dat.netvigator.com (InterMail vM.6.01.03.02 201-2131-111-104-20040324) with SMTP id <20041111080950.HKKD1253.hmail02dat.netvigator.com@HughTan> for ; Thu, 11 Nov 2004 16:09:50 +0800 Message-ID: <00df01c4c7c5$cffdad90$6e01a8c0@HughTan> From: "Ho Tan" To: Subject: Kernel compile error Date: Thu, 11 Nov 2004 16:09:48 +0800 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_00DC_01C4C808.DDF60D00" X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6303 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ho.tan@avantec.com.hk Precedence: bulk X-list: linux-mips Content-Length: 8833 Lines: 207 This is a multi-part message in MIME format. ------=_NextPart_000_00DC_01C4C808.DDF60D00 Content-Type: text/plain; charset="big5" Content-Transfer-Encoding: quoted-printable Dear all, I download the ELDK tools kit (2.1.0 eldk-mips-linux-x86) from = www.denx.de website and follow the instruction to install it into the = RedHat 7.3. and I successfully installed into the Redhat 7.3 without any problem. My target hardware platform is infineon INCAIP and i follow the below = instruction to compile the kernel. The kernel source is download from = www.denx.de (linux-mips) make mrproper make incaip_config make oldconfig make dep make uImage When compliation, everything go fine until the compiler compling entry.S = which locate at arch/mips/kernel. and the Error message prompt. make[1]: Entering directory = `/usr/eldk/usr/src/linux-mips/arch/mips/kernel' mips_4KC-gcc -D__ASSEMBLY__ -D__KERNEL__ = -I/usr/eldk/usr/src/linux-mips/include -D_MIPS_SZLONG=3D32 = -D_MIPS_SZPTR=3D32 -D_MIPS_SZINT=3D32 -g -G 0 -mno-abicalls -fno-pic = -pipe -c -o entry.o entry.S entry.S: Assembler messages: entry.S:225: Error: unrecognized opcode `reg_s $8,164($29)' entry.S:226: Error: unrecognized opcode `reg_s $8,164($29)' make[1]: *** [entry.o] Error 1 make[1]: Leaving directory = `/usr/eldk/usr/src/linux-mips/arch/mips/kernel' make: *** [_dir_arch/mips/kernel] Error 2 The source of the entry.S is as below: Line 225: BUILD_HANDLER(adel,ade,ade,silent) = /* #4 */ Line 226: BUILD_HANDLER(ades,ade,ade,silent) = /* #5 */ Line 227: BUILD_HANDLER(ibe,be,cli,silent) = /* #6 */ Line 228: BUILD_HANDLER(dbe,be,cli,silent) = /* #7 */ Line 229: BUILD_HANDLER(bp,bp,sti,silent) = /* #9 */ Line 230: BUILD_HANDLER(ri,ri,sti,silent) = /* #10 */ Line 231: BUILD_HANDLER(cpu,cpu,sti,silent) = /* #11 */ Line 232: BUILD_HANDLER(ov,ov,sti,silent) = /* #12 */ Line 233: BUILD_HANDLER(tr,tr,sti,silent) = /* #13 */ Line 234: BUILD_HANDLER(fpe,fpe,fpe,silent) = /* #15 */ Line 235: BUILD_HANDLER(watch,watch,sti,silent) /* = #23 */ Line 236: BUILD_HANDLER(mcheck,mcheck,cli,silent) /* #24 = */ Line 237: BUILD_HANDLER(reserved,reserved,sti,silent) /* = others */ Anyone could give any suggestion on this?? Best Regards, Hugh ------=_NextPart_000_00DC_01C4C808.DDF60D00 Content-Type: text/html; charset="big5" Content-Transfer-Encoding: quoted-printable
Dear all,
 
I download the ELDK tools kit (2.1.0=20 eldk-mips-linux-x86) from www.denx.de = website=20 and follow the instruction to install it into the RedHat = 7.3.
and I successfully installed into the = Redhat 7.3=20 without any problem.
 
My target hardware platform is infineon = INCAIP=20 and i follow the below instruction to compile the kernel. The = kernel source=20 is download from www.denx.de=20 (linux-mips)
make mrproper
make incaip_config
make oldconfig
make dep
make uImage
 
When compliation, everything go fine = until the=20 compiler compling entry.S which locate at arch/mips/kernel. and the = Error=20 message prompt.
 
make[1]: Entering directory=20 `/usr/eldk/usr/src/linux-mips/arch/mips/kernel'
mips_4KC-gcc = -D__ASSEMBLY__=20 -D__KERNEL__ -I/usr/eldk/usr/src/linux-mips/include -D_MIPS_SZLONG=3D32=20 -D_MIPS_SZPTR=3D32 -D_MIPS_SZINT=3D32  -g -G 0 -mno-abicalls = -fno-pic=20 -pipe   -c -o entry.o entry.S
entry.S: Assembler=20 messages:
entry.S:225: Error: unrecognized opcode `reg_s=20 $8,164($29)'
entry.S:226: Error: unrecognized opcode `reg_s=20 $8,164($29)'
make[1]: *** [entry.o] Error 1
make[1]: Leaving = directory=20 `/usr/eldk/usr/src/linux-mips/arch/mips/kernel'
make: ***=20 [_dir_arch/mips/kernel] Error 2
The source of the entry.S is as = below:
 
Line=20 225:           &nb= sp;   =20 BUILD_HANDLER(adel,ade,ade,silent)      &nb= sp;      =20 /* #4  */
Line=20 226:           &nb= sp;   =20 BUILD_HANDLER(ades,ade,ade,silent)      &nb= sp;     =20 /* #5  */
Line=20 227:           &nb= sp;   =20 BUILD_HANDLER(ibe,be,cli,silent)       = ;          =20  /* #6  */
Line=20 228:           &nb= sp;   =20 BUILD_HANDLER(dbe,be,cli,silent)       = ;          =20 /* #7  */
Line=20 229:           &nb= sp;   =20 BUILD_HANDLER(bp,bp,sti,silent)       =            =20 /* #9  */
Line=20 230:           &nb= sp;   =20 BUILD_HANDLER(ri,ri,sti,silent)       =          =20      /* #10 */
Line=20 231:           &nb= sp;   =20 BUILD_HANDLER(cpu,cpu,sti,silent)      &nbs= p;       =20 /* #11 */
Line=20 232:           &nb= sp;   =20 BUILD_HANDLER(ov,ov,sti,silent)       =            =20 /* #12 */
Line=20 233:           &nb= sp;   =20 BUILD_HANDLER(tr,tr,sti,silent)       =             &= nbsp;=20 /* #13 */
Line=20 234:           &nb= sp;   =20 BUILD_HANDLER(fpe,fpe,fpe,silent)      &nbs= p;        =20 /* #15 */
Line=20 235:           &nb= sp;   =20 BUILD_HANDLER(watch,watch,sti,silent)      =   /*=20 #23 */
Line=20 236:           &nb= sp;   =20 BUILD_HANDLER(mcheck,mcheck,cli,silent)  /* #24 */
Line=20 237:           &nb= sp;   =20 BUILD_HANDLER(reserved,reserved,sti,silent) /* others = */
 
Anyone could give any suggestion on=20 this??
 
Best Regards,
 
Hugh
------=_NextPart_000_00DC_01C4C808.DDF60D00-- From ralf@linux-mips.org Thu Nov 11 12:38:26 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2004 12:38:46 +0000 (GMT) Received: from p508B63AE.dip.t-dialin.net ([IPv6:::ffff:80.139.99.174]:15647 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Thu, 11 Nov 2004 12:38:26 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iABCcJMU001146; Thu, 11 Nov 2004 13:38:19 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iABCcGLk001145; Thu, 11 Nov 2004 13:38:16 +0100 Date: Thu, 11 Nov 2004 13:38:15 +0100 From: Ralf Baechle To: Ho Tan Cc: linux-mips@linux-mips.org Subject: Re: Kernel compile error Message-ID: <20041111123815.GA23713@linux-mips.org> References: <00df01c4c7c5$cffdad90$6e01a8c0@HughTan> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <00df01c4c7c5$cffdad90$6e01a8c0@HughTan> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6304 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 962 Lines: 19 On Thu, Nov 11, 2004 at 04:09:48PM +0800, Ho Tan wrote: > When compliation, everything go fine until the compiler compling entry.S which locate at arch/mips/kernel. and the Error message prompt. > > make[1]: Entering directory `/usr/eldk/usr/src/linux-mips/arch/mips/kernel' > mips_4KC-gcc -D__ASSEMBLY__ -D__KERNEL__ -I/usr/eldk/usr/src/linux-mips/include -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32 -D_MIPS_SZINT=32 -g -G 0 -mno-abicalls -fno-pic -pipe -c -o entry.o entry.S _MIPS_SZLONG etc. are defined by the compiler. If your tree has kludgery such as defining _MIPS_SZLONG etc. you shouldn't be surprised to see errors like this. It also seems to indicate that mips_4KC-gcc is not a compiler for a mips*-linux* target. > entry.S: Assembler messages: > entry.S:225: Error: unrecognized opcode `reg_s $8,164($29)' > entry.S:226: Error: unrecognized opcode `reg_s $8,164($29)' And that's what you get from it. See include/asm-mips/asm.h for REG_S. Ralf From hvr@inso.tuwien.ac.at Thu Nov 11 12:59:35 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2004 12:59:39 +0000 (GMT) Received: from [IPv6:::ffff:80.122.96.210] ([IPv6:::ffff:80.122.96.210]:64683 "EHLO fwswe.inso.tuwien.ac.at") by linux-mips.org with ESMTP id ; Thu, 11 Nov 2004 12:59:35 +0000 Received: from s052.inso.tuwien.ac.at ([128.130.59.52]) by fwswe.inso.tuwien.ac.at with esmtp (Exim 3.36 #1 (Debian)) id 1CSEXS-0002FT-00; Thu, 11 Nov 2004 13:58:58 +0100 Subject: Re: ohci-au1xxx.c cleanups and fix for 2.6.10-rc1 From: Herbert Valerio Riedel To: Matt Porter Cc: Pete Popov , linux-mips@linux-mips.org In-Reply-To: <20041105071817.A19291@home.com> References: <1099642775.9984.16.camel@s052.inso.tuwien.ac.at> <20041105071817.A19291@home.com> Content-Type: text/plain Date: Thu, 11 Nov 2004 13:58:55 +0100 Message-Id: <1100177936.17620.32.camel@s052.inso.tuwien.ac.at> Mime-Version: 1.0 X-Mailer: Evolution 2.0.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6305 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hvr@inso.tuwien.ac.at Precedence: bulk X-list: linux-mips Content-Length: 1081 Lines: 27 On Fri, 2004-11-05 at 07:18 -0700, Matt Porter wrote: > On Fri, Nov 05, 2004 at 09:19:34AM +0100, Herbert Valerio Riedel wrote: > > > > below just a patch to have usb working again for 2.6.10-rc1 and > > some minor cleanups... > > (alas usb still doesn't work on big endian...) > > The patches to support BE OHCI operation were posted months ago on > the USB list. GregKH recently picked them up and I just saw the > first of them merged to the mainline tree. You should have better > luck with BE OHCI soon. :) I've played w/ the upcoming patches for 2.6.10-rc2 contained in the bk snapshots, and was able to confirm that better luck is really in sight for me (wrt to USB/BE) :-) USB worked fine w/ mouse and some usb-storage ram module, I'd be glad to provide you w/ the required modifications (if necessary) as soon as 2.6.10-rc2 comes out and get merged into linux-mips cvs... now I just need to find how to fix that subtle pci w/ BE issue I'm having w/ pci-device subfunctions disappearing in BE mode... greetings, -- Herbert Valerio Riedel From trini@kernel.crashing.org Thu Nov 11 15:30:05 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2004 15:30:10 +0000 (GMT) Received: from fed1rmmtao09.cox.net ([IPv6:::ffff:68.230.241.30]:3477 "EHLO fed1rmmtao09.cox.net") by linux-mips.org with ESMTP id ; Thu, 11 Nov 2004 15:30:05 +0000 Received: from opus ([68.107.143.141]) by fed1rmmtao09.cox.net (InterMail vM.6.01.04.00 201-2131-117-20041022) with ESMTP id <20041111152955.VGOH14545.fed1rmmtao09.cox.net@opus> for ; Thu, 11 Nov 2004 10:29:55 -0500 Date: Thu, 11 Nov 2004 08:29:55 -0700 From: Tom Rini To: linux-mips@linux-mips.org Subject: [PATCH] Remove duplicates from drivers/mtd/maps/Makefile Message-ID: <20041111152955.GF3815@smtp.west.cox.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6+20040907i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6306 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: trini@kernel.crashing.org Precedence: bulk X-list: linux-mips Content-Length: 830 Lines: 23 There are 2 duplicate entries in drivers/mtd/maps/Makefile only found in CVS. Signed-off-by: Tom Rini --- drivers/mtd/maps/Makefile 25 Oct 2004 20:44:27 -0000 1.19 +++ drivers/mtd/maps/Makefile 11 Nov 2004 15:28:11 -0000 @@ -42,11 +42,9 @@ obj-$(CONFIG_MTD_VMAX) += vmax301.o obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx200_docflash.o obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o obj-$(CONFIG_MTD_OCELOT) += ocelot.o -obj-$(CONFIG_MTD_LASAT) += lasat.o obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o obj-$(CONFIG_MTD_PCI) += pci.o obj-$(CONFIG_MTD_LASAT) += lasat.o -obj-$(CONFIG_MTD_DB1X00) += db1x00-flash.o obj-$(CONFIG_MTD_PB1550) += pb1550-flash.o obj-$(CONFIG_MTD_DB1550) += db1550-flash.o obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o -- Tom Rini http://gate.crashing.org/~trini/ From mlachwani@prometheus.mvista.com Thu Nov 11 22:12:01 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Nov 2004 22:12:13 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:30970 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Thu, 11 Nov 2004 22:12:01 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iABMBwdh013655; Thu, 11 Nov 2004 14:11:58 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iABMBw52013653; Thu, 11 Nov 2004 14:11:58 -0800 Date: Thu, 11 Nov 2004 14:11:57 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Support for Toshiba TX4927 based board in 2.6.10 Message-ID: <20041111221157.GA13646@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="0OAP2g/MAC+5xKAE" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6307 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 33398 Lines: 1268 --0OAP2g/MAC+5xKAE Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ralf Attached patch implements support for Toshiba TX4927 based board in 2.6.10. Please review ... Thanks Manish Lachwani --0OAP2g/MAC+5xKAE Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename="common_mips_toshiba_tx4927_MR9019.patch" Source: MontaVista Software, Inc. | http://www.mvista.com | Manish lachwani Type: Defect Fix Disposition: Submitted to Linux-MIPS Description: Support TX4927 board in 2.6.10 Index: linux/arch/mips/Makefile =================================================================== --- linux.orig/arch/mips/Makefile +++ linux/arch/mips/Makefile @@ -159,6 +159,10 @@ $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \ -Wa,--trap +cflags-$(CONFIG_CPU_TX49XX) += \ + $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \ + -Wa,--trap + cflags-$(CONFIG_CPU_MIPS32) += \ $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \ -Wa,--trap Index: linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c =================================================================== --- linux.orig/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -134,10 +134,10 @@ #include #include #ifdef CONFIG_RTC_DS1742 -#include +#include #endif #ifdef CONFIG_TOSHIBA_FPCIB0 -#include +#include #endif #include @@ -681,13 +681,6 @@ } #endif -#ifdef CONFIG_PCI - { - extern void toshiba_rbtx4927_pci_irq_init(void); - toshiba_rbtx4927_pci_irq_init(); - } -#endif - wbflush(); return; Index: linux/drivers/char/serial_txx9.c =================================================================== --- linux.orig/drivers/char/serial_txx9.c +++ linux/drivers/char/serial_txx9.c @@ -10,7 +10,10 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Serial driver for TX3927/TX4927/TX4925/TX4938 internal SIO controller + * Serial driver for TX3927/TX4927/TX4925/TX4938 internal SIO controller + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com */ #include #include @@ -34,6 +37,7 @@ #ifdef CONFIG_MAGIC_SYSRQ #include #endif +#include #define DEBUG #ifdef DEBUG @@ -44,6 +48,7 @@ static char *serial_version = "0.30-mvl"; static char *serial_name = "TX39/49 Serial driver"; +static struct tty_driver *serial_driver; #define GS_INTERNAL_FLAGS (GS_TX_INTEN|GS_RX_INTEN|GS_ACTIVE) @@ -734,7 +739,7 @@ return -EIO; } - line = minor(tty->device) - tty->driver.minor_start; + line = tty->index; if ((line < 0) || (line >= NR_PORTS)) return -ENODEV; @@ -761,8 +766,6 @@ port->gs.flags |= GS_ACTIVE; if (port->gs.count == 1) { - MOD_INC_USE_COUNT; - /* * Clear the FIFO buffers and disable them * (they will be reenabled in rs_set_real_termios()) @@ -781,7 +784,6 @@ if (retval) { printk(KERN_ERR "serial_txx9: request_irq: err %d\n", retval); - MOD_DEC_USE_COUNT; port->gs.count--; return retval; } @@ -815,20 +817,15 @@ if (retval) { if (port->gs.count == 1) { free_irq(port->irq, port); - MOD_DEC_USE_COUNT; } port->gs.count--; return retval; } /* tty->low_latency = 1; */ - if ((port->gs.count == 1) && (port->gs.flags & ASYNC_SPLIT_TERMIOS)) { - if (tty->driver.subtype == SERIAL_TYPE_NORMAL) - *tty->termios = port->gs.normal_termios; - else - *tty->termios = port->gs.callout_termios; + if (port->gs.count == 1) rs_set_real_termios(port); - } + #ifdef CONFIG_SERIAL_TXX9_CONSOLE if (sercons.cflag && sercons.index == line) { tty->termios->c_cflag = sercons.cflag; @@ -836,8 +833,6 @@ rs_set_real_termios(port); } #endif - port->gs.session = current->session; - port->gs.pgrp = current->pgrp; return 0; } @@ -931,7 +926,6 @@ struct rs_port *port = ptr; free_irq(port->irq, port); #endif - MOD_DEC_USE_COUNT; } /* I haven't the foggiest why the decrement use count has to happen @@ -943,7 +937,6 @@ exit minicom. I expect an "oops". -- REW */ static void rs_hungup (void *ptr) { - MOD_DEC_USE_COUNT; } static void rs_getserial (void *ptr, struct serial_struct *sp) @@ -951,7 +944,7 @@ struct rs_port *port = ptr; struct tty_struct *tty = port->gs.tty; /* some applications (busybox, dbootstrap, etc.) look this */ - sp->line = minor(tty->device) - tty->driver.minor_start; + sp->line = tty->index; } /* @@ -1148,8 +1141,6 @@ port = rs_ports; for (i=0; i < NR_PORTS;i++) { - port->gs.callout_termios = tty_std_termios; - port->gs.normal_termios = tty_std_termios; port->gs.magic = TXX9_SERIAL_MAGIC; port->gs.close_delay = HZ/2; port->gs.closing_wait = 30 * HZ; @@ -1188,7 +1179,6 @@ rs_driver.init_termios.c_cflag = B9600 | CS8 | CREAD | HUPCL | CLOCAL; rs_driver.refcount = &rs_refcount; - rs_driver.table = rs_table; rs_driver.termios = rs_termios; rs_driver.termios_locked = rs_termios_locked; @@ -1216,24 +1206,12 @@ #else rs_callout_driver.name = TXX9_CU_NAME; #endif - rs_callout_driver.major = TXX9_TTYAUX_MAJOR; - rs_callout_driver.subtype = SERIAL_TYPE_CALLOUT; - rs_callout_driver.read_proc = 0; - rs_callout_driver.proc_entry = 0; - if ((error = tty_register_driver(&rs_driver))) { printk(KERN_ERR "Couldn't register serial driver, error = %d\n", error); return 1; } - if ((error = tty_register_driver(&rs_callout_driver))) { - tty_unregister_driver(&rs_driver); - printk(KERN_ERR - "Couldn't register callout driver, error = %d\n", - error); - return 1; - } return 0; } @@ -1532,16 +1510,17 @@ sio_out(port, TXX9_SIDICR, ier); } -static kdev_t serial_console_device(struct console *c) +static struct tty_driver *serial_console_device(struct console *c, int *index) { - return mk_kdev(TXX9_TTY_MAJOR, TXX9_TTY_MINOR_START + c->index); + *index = c->index; + return &rs_driver; } -static __init int serial_console_setup(struct console *co, char *options) +static int serial_console_setup(struct console *co, char *options) { struct rs_port *port; unsigned cval; - int baud = 9600; + int baud = 9600; int bits = 8; int parity = 'n'; int doflow = 0; @@ -1643,11 +1622,15 @@ index: -1, }; -void __init txx9_serial_console_init(void) +static int __init txx9_serial_console_init(void) { register_console(&sercons); + + return 0; } +console_initcall(txx9_serial_console_init); + #endif /******************************************************************************/ @@ -1656,9 +1639,7 @@ #ifdef CONFIG_KGDB int kgdb_init_count = 0; -#endif -#ifdef CONFIG_KGDB void txx9_sio_kgdb_hook(unsigned int port, unsigned int baud_rate) { static struct resource kgdb_resource; @@ -1676,9 +1657,6 @@ return; } -#endif /* CONFIG_KGDB */ - -#ifdef CONFIG_KGDB void txx9_sio_kdbg_init( unsigned int port_number ) { @@ -1689,9 +1667,7 @@ } return; } -#endif /* CONFIG_KGDB */ -#ifdef CONFIG_KGDB u8 txx9_sio_kdbg_rd( void ) { @@ -1715,10 +1691,7 @@ return( ch ); } -#endif /* CONFIG_KGDB */ - -#ifdef CONFIG_KGDB int txx9_sio_kdbg_wr( u8 ch ) { Index: linux/arch/mips/Kconfig =================================================================== --- linux.orig/arch/mips/Kconfig +++ linux/arch/mips/Kconfig @@ -848,9 +848,18 @@ bool "Support for Toshiba TBTX49[23]7 board" depends on MIPS32 select DMA_NONCOHERENT - select HW_HAS_PCI select ISA select SWAP_IO_SPACE + select HW_HAS_PCI + select PCI + select I8259 + help + This Toshiba board is based on the TX4927 processor. Say Y here to + support this machine type + +config TOSHIBA_FPCIB0 + bool "FPCIB0 Backplane Support" + depends on TOSHIBA_RBTX4927 config RWSEM_GENERIC_SPINLOCK bool Index: linux/include/asm-mips/tx4927/smsc_fdc37m81x.h =================================================================== --- /dev/null +++ linux/include/asm-mips/tx4927/smsc_fdc37m81x.h @@ -0,0 +1,72 @@ +/* + * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h + * + * Interface for smsc fdc48m81x Super IO chip + * + * Author: MontaVista Software, Inc. source@mvista.com + * + * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Manish Lachwani, mlachwani@mvista.com + */ + +#ifndef _SMSC_FDC37M81X_H_ +#define _SMSC_FDC37M81X_H_ + +/* Common Registers */ +#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 +#define SMSC_FDC37M81X_CONFIG_DATA 0x01 +#define SMSC_FDC37M81X_CONF 0x02 +#define SMSC_FDC37M81X_INDEX 0x03 +#define SMSC_FDC37M81X_DNUM 0x07 +#define SMSC_FDC37M81X_DID 0x20 +#define SMSC_FDC37M81X_DREV 0x21 +#define SMSC_FDC37M81X_PCNT 0x22 +#define SMSC_FDC37M81X_PMGT 0x23 +#define SMSC_FDC37M81X_OSC 0x24 +#define SMSC_FDC37M81X_CONFPA0 0x26 +#define SMSC_FDC37M81X_CONFPA1 0x27 +#define SMSC_FDC37M81X_TEST4 0x2B +#define SMSC_FDC37M81X_TEST5 0x2C +#define SMSC_FDC37M81X_TEST1 0x2D +#define SMSC_FDC37M81X_TEST2 0x2E +#define SMSC_FDC37M81X_TEST3 0x2F + +/* Logical device numbers */ +#define SMSC_FDC37M81X_FDD 0x00 +#define SMSC_FDC37M81X_PARALLEL 0x03 +#define SMSC_FDC37M81X_SERIAL1 0x04 +#define SMSC_FDC37M81X_SERIAL2 0x05 +#define SMSC_FDC37M81X_KBD 0x07 +#define SMSC_FDC37M81X_AUXIO 0x08 +#define SMSC_FDC37M81X_NONE 0xff + +/* Logical device Config Registers */ +#define SMSC_FDC37M81X_ACTIVE 0x30 +#define SMSC_FDC37M81X_BASEADDR0 0x60 +#define SMSC_FDC37M81X_BASEADDR1 0x61 +#define SMSC_FDC37M81X_INT 0x70 +#define SMSC_FDC37M81X_INT2 0x72 +#define SMSC_FDC37M81X_LDCR_F0 0xF0 + +/* Chip Config Values */ +#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 +#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa +#define SMSC_FDC37M81X_CHIP_ID 0x4d + +unsigned long __init smsc_fdc37m81x_init(unsigned long port); + +void + smsc_fdc37m81x_config_beg(void); + +void + smsc_fdc37m81x_config_end(void); + +void + smsc_fdc37m81x_config_set(u8 reg, u8 val); + +#endif Index: linux/arch/mips/pci/fixup-rbtx4927.c =================================================================== --- linux.orig/arch/mips/pci/fixup-rbtx4927.c +++ linux/arch/mips/pci/fixup-rbtx4927.c @@ -9,6 +9,9 @@ * * Copyright (C) 2000-2001 Toshiba Corporation * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani (mlachwani@mvista.com) + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -115,59 +118,28 @@ DBG("assigned irq %d\n", irq); return irq; } - - -#ifdef TX4927_SUPPORT_PCI_66 -extern int tx4927_pci66; -extern void tx4927_pci66_setup(void); -#endif -extern void tx4927_pci_setup(void); - -#ifdef TX4927_SUPPORT_PCI_66 -int tx4927_pci66_check(void) -{ - struct pci_dev *dev; - unsigned short stat; - int cap66 = 1; - - if (tx4927_pci66 < 0) - return 0; - - /* check 66MHz capability */ - pci_for_each_dev(dev) { - if (cap66) { - pci_read_config_word(dev, PCI_STATUS, &stat); - if (!(stat & PCI_STATUS_66MHZ)) { - printk(KERN_INFO - "PCI: %02x:%02x not 66MHz capable.\n", - dev->bus->number, dev->devfn); - cap66 = 0; - } - } - } - return cap66; -} -#endif - /* * This is dead, rotten code, needs to be rewritten -- Ralf */ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { + unsigned int id; unsigned char irq; -#ifdef TX4927_SUPPORT_PCI_66 /* Has no f*cking biz here */ - if (tx4927_pci66_check()) { - tx4927_pci66_setup(); - tx4927_pci_setup(); /* Reinitialize PCIC */ - } -#endif + printk("PCI Setup for pin %d \n", pin); - if (dev->vendor == PCI_VENDOR_ID_EFAR && - dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1) + pci_read_config_dword(dev, PCI_VENDOR_ID, &id); + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + + if (id == 0x91301055) { irq = 14; - else - irq = 0; + } + + if (irq == 0) { + irq = pci_get_irq(dev, pin); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); + } return irq; } Index: linux/arch/mips/tx4927/common/Makefile =================================================================== --- linux.orig/arch/mips/tx4927/common/Makefile +++ linux/arch/mips/tx4927/common/Makefile @@ -8,4 +8,5 @@ obj-y += tx4927_prom.o tx4927_setup.o tx4927_irq.o tx4927_irq_handler.o +obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o obj-$(CONFIG_KGDB) += tx4927_dbgio.o Index: linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c =================================================================== --- linux.orig/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c +++ linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c @@ -6,6 +6,9 @@ * * Copyright 2001-2002 MontaVista Software Inc. * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -86,3 +89,9 @@ { return "Toshiba RBTX4927/RBTX4937"; } + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + Index: linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c =================================================================== --- linux.orig/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -17,7 +17,10 @@ * Copyright 2002 MontaVista Software Inc. * Author: Michael Pruznick, michael_pruznick@mvista.com * - * Copyright (C) 2000-2001 Toshiba Corporation + * Copyright (C) 2000-2001 Toshiba Corporation + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -61,10 +64,10 @@ #include #include #ifdef CONFIG_RTC_DS1742 -#include +#include #endif #ifdef CONFIG_TOSHIBA_FPCIB0 -#include +#include #endif #include #ifdef CONFIG_PCI @@ -145,49 +148,15 @@ unsigned long tx4927_ce_base[8]; void tx4927_pci_setup(void); void tx4927_reset_pci_pcic(void); -#ifdef TX4927_SUPPORT_PCI_66 -void tx4927_pci66_setup(void); -extern int tx4927_pci66_check(void); -#endif int tx4927_pci66 = 0; /* 0:auto */ #endif char *toshiba_name = ""; #ifdef CONFIG_PCI -void tx4927_dump_pcic_settings(void) -{ - printk("%s pcic settings:",toshiba_name); - { - int i; - unsigned long *preg = (unsigned long *) tx4927_pcicptr; - for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4) { - if (i % 32 == 0) - printk("\n%04x:", i); - if (preg == &tx4927_pcicptr->g2pintack - || preg == &tx4927_pcicptr->g2pspc -#ifdef CONFIG_TX4927BUG_WORKAROUND - || preg == &tx4927_pcicptr->g2pcfgadrs - || preg == &tx4927_pcicptr->g2pcfgdata -#endif - ) { - printk(" XXXXXXXX"); - preg++; - continue; - } - printk(" %08lx", *preg++); - if (preg == &tx4927_pcicptr->g2pcfgadrs) - break; - } - printk("\n"); - } -} - static void tx4927_pcierr_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - extern void tx4927_dump_pcic_settings(void); - #ifdef CONFIG_BLK_DEV_IDEPCI /* ignore MasterAbort for ide probing... */ if (irq == TX4927_IRQ_IRC_PCIERR && @@ -202,6 +171,7 @@ } #endif printk("PCI error interrupt (irq 0x%x).\n", irq); + printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n", (unsigned short) (tx4927_pcicptr->pcistatus >> 16), tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus); @@ -210,23 +180,10 @@ (unsigned long) (tx4927_ccfgptr->tear >> 32), (unsigned long) tx4927_ccfgptr->tear); show_regs(regs); - //tx4927_dump_pcic_settings(); - panic("PCI error at PC:%08lx.", regs->cp0_epc); } -static struct irqaction pcic_action = { - tx4927_pcierr_interrupt, 0, 0, "PCI-C", NULL, NULL -}; - -static struct irqaction pcierr_action = { - tx4927_pcierr_interrupt, 0, 0, "PCI-ERR", NULL, NULL -}; - - void __init toshiba_rbtx4927_pci_irq_init(void) { - setup_irq(TX4927_IRQ_IRC_PCIC, &pcic_action); - setup_irq(TX4927_IRQ_IRC_PCIERR, &pcierr_action); return; } @@ -244,91 +201,26 @@ #endif /* CONFIG_PCI */ #ifdef CONFIG_PCI -#ifdef TX4927_SUPPORT_PCI_66 -void tx4927_pci66_setup(void) -{ - int pciclk, pciclkin = 1; - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI66, - "-\n"); - - if (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) - return; - - tx4927_reset_pci_pcic(); - - /* Assert M66EN */ - tx4927_ccfgptr->ccfg |= TX4927_CCFG_PCI66; - /* set PCICLK 66MHz */ - if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { - unsigned int pcidivmode = 0; - pcidivmode = - (unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK; - if (tx4927_cpu_clock >= 170000000) { - /* CPU 200MHz */ - pcidivmode = TX4927_CCFG_PCIDIVMODE_3; - pciclk = tx4927_cpu_clock / 3; - } else { - /* CPU 166MHz */ - pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5; - pciclk = tx4927_cpu_clock * 2 / 5; - } - tx4927_ccfgptr->ccfg = - (tx4927_ccfgptr->ccfg & ~TX4927_CCFG_PCIDIVMODE_MASK) - | pcidivmode; - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCI66, - ":PCICLK: ccfg:0x%08lx\n", - (unsigned long) tx4927_ccfgptr->ccfg); - } else { - int pciclk_setting = *tx4927_pci_clk_ptr; - pciclkin = 0; - pciclk = 66666666; - pciclk_setting &= ~TX4927_PCI_CLK_MASK; - pciclk_setting |= TX4927_PCI_CLK_66; - *tx4927_pci_clk_ptr = pciclk_setting; - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCI66, - "PCICLK: pci_clk:%02x\n", *tx4927_pci_clk_ptr); - } - - udelay(10000); - - /* clear PCIC reset */ - tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST; - /* clear PCI reset */ - *tx4927_pcireset_ptr = 0; - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI66, - "+\n"); - return; -} -#endif /* TX4927_SUPPORT_PCI_66 */ - void print_pci_status(void) { printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus); printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus); } +extern struct pci_controller tx4927_controller; + static struct pci_dev *fake_pci_dev(struct pci_controller *hose, int top_bus, int busnr, int devfn) { static struct pci_dev dev; static struct pci_bus bus; - dev.bus = &bus; - dev.sysdata = hose; + dev.sysdata = (void *)hose; dev.devfn = devfn; bus.number = busnr; bus.ops = hose->pci_ops; - - if (busnr != top_bus) - /* Fake a parent bus structure. */ - bus.parent = &bus; - else - bus.parent = NULL; + bus.parent = NULL; + dev.bus = &bus; return &dev; } @@ -349,15 +241,19 @@ EARLY_PCI_OP(write, word, u16) EARLY_PCI_OP(write, dword, u32) -static int __init tx4927_pcibios_init(int busno, struct pci_controller *hose) +static int __init tx4927_pcibios_init(void) { unsigned int id; u32 pci_devfn; + int devfn_start = 0; + int devfn_stop = 0xff; + int busno = 0; /* One bus on the Toshiba */ + struct pci_controller *hose = &tx4927_controller; TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, "-\n"); - for (pci_devfn = 0x0; pci_devfn < 0xff; pci_devfn++) { + for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { early_read_config_dword(hose, busno, busno, pci_devfn, PCI_VENDOR_ID, &id); @@ -580,12 +476,15 @@ } + register_pci_controller(&tx4927_controller); TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, "+\n"); - return busno; + return 0; } +arch_initcall(tx4927_pcibios_init); + extern struct resource pci_io_resource; extern struct resource pci_mem_resource; @@ -596,11 +495,6 @@ TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n"); -#ifndef TX4927_SUPPORT_PCI_66 - if (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) - printk("PCI 66 current unsupported\n"); -#endif - mips_memory_upper = tx4927_get_mem_size() << 20; mips_memory_upper += KSEG0; TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, @@ -735,19 +629,6 @@ /* PCI->GB mappings (I/O 256B) */ tx4927_pcicptr->p2giopbase = 0; /* 256B */ - -#ifdef TX4927_SUPPORT_COMMAND_IO - tx4927_pcicptr->p2giogbase = 0 | TX4927_PCIC_P2GIOGBASE_TIOEN | -#ifdef __BIG_ENDIAN - TX4927_PCIC_P2GIOGBASE_TECHG -#else - TX4927_PCIC_P2GIOGBASE_TBSDIS -#endif - ; -#else - tx4927_pcicptr->p2giogbase = 0; -#endif - /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ tx4927_pcicptr->p2gm0plbase = 0; tx4927_pcicptr->p2gm0pubase = 0; @@ -790,8 +671,6 @@ if (tx4927_pcic_trdyto >= 0) { tx4927_pcicptr->g2ptocnt &= ~0xff; tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); - //printk("%s PCIC -- TRDYTO:%02lx\n",toshiba_name, - // tx4927_pcicptr->g2ptocnt & 0xff); } /* Clear All Local Bus Status */ @@ -824,17 +703,10 @@ tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | -#ifdef TX4927_SUPPORT_COMMAND_IO - PCI_COMMAND_IO | -#endif PCI_COMMAND_PARITY | PCI_COMMAND_SERR; TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, ":pci setup complete:\n"); - //tx4927_dump_pcic_settings(); - - tx4927_pcibios_init(0, &tx4927_controller); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n"); } @@ -882,6 +754,7 @@ void __init toshiba_rbtx4927_setup(void) { vu32 cp0_config; + char *argptr; printk("CPU is %s\n", toshiba_name); @@ -922,21 +795,16 @@ TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, "+\n"); - - - mips_io_port_base = KSEG1 + TBTX4927_ISA_IO_OFFSET; + set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, ":mips_io_port_base=0x%08lx\n", mips_io_port_base); TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, ":Resource\n"); - ioport_resource.start = 0; ioport_resource.end = 0xffffffff; - iomem_resource.start = 0; iomem_resource.end = 0xffffffff; - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, ":ResetRoutines\n"); _machine_restart = toshiba_rbtx4927_restart; @@ -999,25 +867,11 @@ tx4927_sdramcptr->tr |= 0x02000000; /* RCD:3tck */ #endif -#ifdef TX4927_SUPPORT_PCI_66 - tx4927_pci66_setup(); -#endif - tx4927_pci_setup(); -#endif - - - { - u32 id = 0; - early_read_config_dword(&tx4927_controller, 0, 0, 0x90, - PCI_VENDOR_ID, &id); - if (id == 0x94601055) { - tx4927_using_backplane = 1; - printk("backplane board IS installed\n"); - } else { - printk("backplane board NOT installed\n"); - } - } + if (tx4927_using_backplane == 1) + printk("backplane board IS installed\n"); + else + printk("No Backplane \n"); /* this is on ISA bus behind PCI bus, so need PCI up first */ #ifdef CONFIG_TOSHIBA_FPCIB0 @@ -1064,11 +918,41 @@ } #endif +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } +#endif + +#ifdef CONFIG_ROOT_NFS + argptr = prom_getcmdline(); + if (strstr(argptr, "root=") == NULL) { + strcat(argptr, " root=/dev/nfs rw"); + } +#endif + + +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } +#endif + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - "+\n"); + "+\n"); } +#ifdef CONFIG_RTC_DS1742 +extern unsigned long rtc_ds1742_get_time(void); +extern int rtc_ds1742_set_time(unsigned long); +extern void rtc_ds1742_wait(void); +#endif + void __init toshiba_rbtx4927_time_init(void) { Index: linux/arch/mips/pci/ops-tx4927.c =================================================================== --- linux.orig/arch/mips/pci/ops-tx4927.c +++ linux/arch/mips/pci/ops-tx4927.c @@ -13,6 +13,9 @@ * Much of the code is derived from the original DDB5074 port by * Geert Uytterhoeven * + * Copyright 2004 MontaVista Software Inc. + * Author: Manish Lachwani (mlachwani@mvista.com) + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -44,33 +47,21 @@ /* initialize in setup */ struct resource pci_io_resource = { - "pci IO space", - (PCIBIOS_MIN_IO), - ((PCIBIOS_MIN_IO) + (TX4927_PCIIO_SIZE)) - 1, - IORESOURCE_IO + .name = "TX4927 PCI IO SPACE", + .start = 0x1000, + .end = (0x1000 + (TX4927_PCIIO_SIZE)) - 1, + .flags = IORESOURCE_IO }; /* initialize in setup */ struct resource pci_mem_resource = { - "pci memory space", - TX4927_PCIMEM, - TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1, - IORESOURCE_MEM -}; - -extern struct pci_ops tx4927_pci_ops; - -/* - * h/w only supports devices 0x00 to 0x14 - */ -struct pci_controller tx4927_controller = { - .pci_ops = &tx4927_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, + .name = "TX4927 PCI MEM SPACE", + .start = TX4927_PCIMEM, + .end = TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1, + .flags = IORESOURCE_MEM }; -static int mkaddr(unsigned char bus, unsigned char dev_fn, - unsigned char where, int *flagsp) +static int mkaddr(int bus, int dev_fn, int where, int *flagsp) { if (bus > 0) { /* Type 1 configuration */ @@ -107,107 +98,49 @@ return code; } -/* - * We can't address 8 and 16 bit words directly. Instead we have to - * read/write a 32bit word and mask/modify the data we actually want. - */ -static int tx4927_pcibios_read_config_byte(struct pci_dev *dev, - int where, unsigned char *val) +static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 * val) { - int flags, retval; - unsigned char bus, func_num; + int flags, retval, dev, busno, func; - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); + busno = bus->number; + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); - /* check if the bus is top-level */ - if (dev->bus->parent != NULL) { - bus = dev->bus->number; - db_assert(bus != 0); - } else { - bus = 0; + if (size == 2) { + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; } - func_num = PCI_FUNC(dev->devfn); - if (mkaddr(bus, dev->devfn, where, &flags)) - return -1; -#ifdef __BIG_ENDIAN - *val = - *(volatile u8 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | ((where & 3) ^ 3)); -#else - *val = - *(volatile u8 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | (where & 3)); -#endif - retval = check_abort(flags); - if (retval == PCIBIOS_DEVICE_NOT_FOUND) - *val = 0xff; - return retval; -} - -static int tx4927_pcibios_read_config_word(struct pci_dev *dev, - int where, unsigned short *val) -{ - int flags, retval; - unsigned char bus, func_num; - - if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; - - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); + if (size == 4) { + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + } /* check if the bus is top-level */ - if (dev->bus->parent != NULL) { - bus = dev->bus->number; - db_assert(bus != 0); + if (bus->parent != NULL) { + busno = bus->number; } else { - bus = 0; + busno = 0; } - func_num = PCI_FUNC(dev->devfn); - if (mkaddr(bus, dev->devfn, where, &flags)) + if (mkaddr(busno, devfn, where, &flags)) return -1; -#ifdef __BIG_ENDIAN - *val = - *(volatile u16 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | ((where & 3) ^ 2)); -#else - *val = - *(volatile u16 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | (where & 3)); -#endif - retval = check_abort(flags); - if (retval == PCIBIOS_DEVICE_NOT_FOUND) - *val = 0xffff; - return retval; -} - -static int tx4927_pcibios_read_config_dword(struct pci_dev *dev, - int where, unsigned int *val) -{ - int flags, retval; - unsigned char bus, func_num; - if (where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; - - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); - - /* check if the bus is top-level */ - if (dev->bus->parent != NULL) { - bus = dev->bus->number; - db_assert(bus != 0); - } else { - bus = 0; + switch (size) { + case 1: + *val = *(volatile u8 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | (where & 3)); + break; + case 2: + *val = *(volatile u16 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | (where & 3)); + break; + case 4: + *val = tx4927_pcicptr->g2pcfgdata; + break; } - func_num = PCI_FUNC(dev->devfn); - if (mkaddr(bus, dev->devfn, where, &flags)) - return -1; - *val = tx4927_pcicptr->g2pcfgdata; retval = check_abort(flags); if (retval == PCIBIOS_DEVICE_NOT_FOUND) *val = 0xffffffff; @@ -215,92 +148,62 @@ return retval; } -static int tx4927_pcibios_write_config_byte(struct pci_dev *dev, - int where, unsigned char val) +static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) { - int flags; - unsigned char bus, func_num; + int flags, dev, busno, func; + busno = bus->number; + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); - /* check if the bus is top-level */ - if (dev->bus->parent != NULL) { - bus = dev->bus->number; - db_assert(bus != 0); - } else { - bus = 0; + if (size == 1) { + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; } - func_num = PCI_FUNC(dev->devfn); - if (mkaddr(bus, dev->devfn, where, &flags)) - return -1; -#ifdef __BIG_ENDIAN - *(volatile u8 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | ((where & 3) ^ 3)) = val; -#else - *(volatile u8 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | (where & 3)) = val; -#endif - return check_abort(flags); -} - -static int tx4927_pcibios_write_config_word(struct pci_dev *dev, - int where, unsigned short val) -{ - int flags; - unsigned char bus, func_num; - - if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; + if (size == 4) { + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + } /* check if the bus is top-level */ - if (dev->bus->parent != NULL) { - bus = dev->bus->number; - db_assert(bus != 0); + if (bus->parent != NULL) { + busno = bus->number; } else { - bus = 0; + busno = 0; } - func_num = PCI_FUNC(dev->devfn); - if (mkaddr(bus, dev->devfn, where, &flags)) + if (mkaddr(busno, devfn, where, &flags)) return -1; -#ifdef __BIG_ENDIAN - *(volatile u16 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | ((where & 3) ^ 2)) = val; -#else - *(volatile u16 *) ((ulong) & tx4927_pcicptr-> - g2pcfgdata | (where & 3)) = val; -#endif - return check_abort(flags); -} - -static int tx4927_pcibios_write_config_dword(struct pci_dev *dev, - int where, unsigned int val) -{ - int flags; - unsigned char bus, func_num; - if (where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; + switch (size) { + case 1: + *(volatile u8 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | (where & 3)) = val; + break; - /* check if the bus is top-level */ - if (dev->bus->parent != NULL) { - bus = dev->bus->number; - db_assert(bus != 0); - } else { - bus = 0; + case 2: + *(volatile u16 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | (where & 3)) = val; + break; + case 4: + tx4927_pcicptr->g2pcfgdata = val; + break; } - func_num = PCI_FUNC(dev->devfn); - if (mkaddr(bus, dev->devfn, where, &flags)) - return -1; - tx4927_pcicptr->g2pcfgdata = val; return check_abort(flags); } struct pci_ops tx4927_pci_ops = { - tx4927_pcibios_read_config_byte, - tx4927_pcibios_read_config_word, - tx4927_pcibios_read_config_dword, - tx4927_pcibios_write_config_byte, - tx4927_pcibios_write_config_word, - tx4927_pcibios_write_config_dword + tx4927_pcibios_read_config, + tx4927_pcibios_write_config +}; + +/* + * h/w only supports devices 0x00 to 0x14 + */ +struct pci_controller tx4927_controller = { + .pci_ops = &tx4927_pci_ops, + .io_resource = &pci_io_resource, + .mem_resource = &pci_mem_resource, }; --0OAP2g/MAC+5xKAE-- From ralf@linux-mips.org Fri Nov 12 00:49:06 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2004 00:49:11 +0000 (GMT) Received: from p508B63AE.dip.t-dialin.net ([IPv6:::ffff:80.139.99.174]:16668 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Fri, 12 Nov 2004 00:49:06 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAC0mw8S010987; Fri, 12 Nov 2004 01:48:58 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAC0mww3010980; Fri, 12 Nov 2004 01:48:58 +0100 Date: Fri, 12 Nov 2004 01:48:58 +0100 From: Ralf Baechle To: Tom Rini Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Remove duplicates from drivers/mtd/maps/Makefile Message-ID: <20041112004858.GB2952@linux-mips.org> References: <20041111152955.GF3815@smtp.west.cox.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041111152955.GF3815@smtp.west.cox.net> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6308 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 167 Lines: 8 On Thu, Nov 11, 2004 at 08:29:55AM -0700, Tom Rini wrote: > There are 2 duplicate entries in drivers/mtd/maps/Makefile only found in > CVS. Thanks, applied. Ralf From mlachwani@prometheus.mvista.com Fri Nov 12 02:59:53 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2004 03:00:09 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:18429 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Fri, 12 Nov 2004 02:59:53 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iAC2xpdh015613; Thu, 11 Nov 2004 18:59:51 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iAC2xpnP015611; Thu, 11 Nov 2004 18:59:51 -0800 Date: Thu, 11 Nov 2004 18:59:51 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] ne.c driver to support TX4927 board Message-ID: <20041112025951.GA15605@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="MGYHOYXEY6WxJCY8" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6309 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1611 Lines: 61 --MGYHOYXEY6WxJCY8 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ralf Attached patch implements changes to the ne.c driver to support the TX4927 board. Please review Thanks Manish Lachwani --MGYHOYXEY6WxJCY8 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename="common_mips_toshiba_net_MR9019.patch" Source: MontaVista Software, Inc. | http://www.mvista.com | Manish Lachwani Type: Defect Fix Disposition: Submitted to Linux-MIPS Description: Support for RBTX4927 in NS8390 ethernet driver in 2.6.10 Index: linux/drivers/net/ne.c =================================================================== --- linux.orig/drivers/net/ne.c +++ linux/drivers/net/ne.c @@ -112,6 +112,7 @@ {"PCM-4823", "PCM-4823", {0x00, 0xc0, 0x6c}}, /* Broken Advantech MoBo */ {"REALTEK", "RTL8019", {0x00, 0x00, 0xe8}}, /* no-name with Realtek chip */ {"LCS-8834", "LCS-8836", {0x04, 0x04, 0x37}}, /* ShinyNet (SET) */ + {"RBHMA4X00-RTL8019", "RBHMA4X00/RTL8019", {0x00, 0x60, 0x0a}}, /* Toshiba built-in */ {NULL,} }; #endif @@ -226,6 +227,10 @@ sprintf(dev->name, "eth%d", unit); netdev_boot_setup_check(dev); +#ifdef CONFIG_TOSHIBA_RBTX4927 + dev->base_addr = 0x06020280; + dev->irq = 29; +#endif err = do_ne_probe(dev); if (err) goto out; @@ -511,6 +516,11 @@ ei_status.name = name; ei_status.tx_start_page = start_page; ei_status.stop_page = stop_page; + +#ifdef CONFIG_TOSHIBA_RBTX4927 + wordlength = 1; +#endif + #ifdef CONFIG_PLAT_OAKS32R ei_status.word16 = 0; #else --MGYHOYXEY6WxJCY8-- From toch@dfpost.ru Fri Nov 12 06:28:24 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2004 06:28:32 +0000 (GMT) Received: from dfpost.ru ([IPv6:::ffff:194.85.103.225]:41933 "EHLO mail.dfpost.ru") by linux-mips.org with ESMTP id ; Fri, 12 Nov 2004 06:28:24 +0000 Received: from toch.dfpost.ru (toch.dfpost.ru [192.168.7.60]) by mail.dfpost.ru (Postfix) with SMTP id 53E963E4AC for ; Fri, 12 Nov 2004 09:24:39 +0300 (MSK) Date: Fri, 12 Nov 2004 09:27:35 +0300 From: Dmitriy Tochansky To: linux-mips@linux-mips.org Subject: RTAI on mips Message-Id: <20041112092735.11f16b31.toch@dfpost.ru> Organization: Special Technology Center X-Mailer: Sylpheed version 0.9.12 (GTK+ 1.2.10; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6310 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: toch@dfpost.ru Precedence: bulk X-list: linux-mips Content-Length: 63 Lines: 3 Hi! It there anybody using RTAI(from rtai.org) on mips board? From colin@realtek.com.tw Fri Nov 12 07:49:23 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2004 07:49:29 +0000 (GMT) Received: from mf2.realtek.com.tw ([IPv6:::ffff:220.128.56.22]:60431 "EHLO mf2.realtek.com.tw") by linux-mips.org with ESMTP id ; Fri, 12 Nov 2004 07:49:23 +0000 Received: from msx.realtek.com.tw (unverified [172.20.1.77]) by mf2.realtek.com.tw (Content Technologies SMTPRS 4.3.14) with ESMTP id ; Fri, 12 Nov 2004 15:50:28 +0800 Received: from rtpdii3098 ([172.19.26.139]) by msx.realtek.com.tw (Lotus Domino Release 6.0.2CF1) with ESMTP id 2004111215503028-57814 ; Fri, 12 Nov 2004 15:50:30 +0800 Message-ID: <000d01c4c88c$1a82e8a0$8b1a13ac@realtek.com.tw> From: "colin" To: "Vladimir A. Gurevich" Cc: References: <01e101c4c182$5d0f2780$8b1a13ac@realtek.com.tw> <4188F75E.9010105@paulidav.org> Subject: Re: KGDB: I cannot stop execution by using "ctrl+c" Date: Fri, 12 Nov 2004 15:49:13 +0800 MIME-Version: 1.0 X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1437 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1441 X-MIMETrack: Itemize by SMTP Server on msx/Realtek(Release 6.0.2CF1|June 9, 2003) at 2004/11/12 =?Bog5?B?pFWkyCAwMzo1MDozMA==?=, Serialize by Router on msx/Realtek(Release 6.0.2CF1|June 9, 2003) at 2004/11/12 =?Bog5?B?pFWkyCAwMzo1MDozMQ==?=, Serialize complete at 2004/11/12 =?Bog5?B?pFWkyCAwMzo1MDozMQ==?= Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="iso-8859-1" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6311 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: colin@realtek.com.tw Precedence: bulk X-list: linux-mips Content-Length: 1061 Lines: 39 Hi Vladimir, It still cannot work using "set remotebreak 1". Regards, Colin ----- Original Message ----- From: "Vladimir A. Gurevich" To: "colin" Cc: Sent: Wednesday, November 03, 2004 11:21 PM Subject: Re: KGDB: I cannot stop execution by using "ctrl+c" > Hello Colin, > > colin wrote: > > >When using gdb to debug Linux kernel, I found that it cannot be stopped > >temporarily by using "ctrl+c". > >After the first strike of "ctrl+c", nothing happen. > >After the second, Linux kernel will show these messages: > > Interrupted while waiting for the program. > > Give up (and stop debugging it)? (y or n) > >If choose yes, kernel will totally stop and it goes back to gdb shell. > >How can I stop kernel temporarily and then resume it? > > > You should use the following command in GDB: > > set remotebreak 1 > > After that it will start to behave as you expect it to, i.e. it will > interrupt the kernel as soon as you press CTRL-C. > > Happy hacking, > Vladimir > From gilad@romat.com Fri Nov 12 10:08:12 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2004 10:08:21 +0000 (GMT) Received: from mail.romat.com ([IPv6:::ffff:212.143.245.3]:24587 "EHLO mail.romat.com") by linux-mips.org with ESMTP id ; Fri, 12 Nov 2004 10:08:11 +0000 Received: from localhost (localhost.lan [127.0.0.1]) by mail.romat.com (Postfix) with ESMTP id D1EA9EB2E2 for ; Fri, 12 Nov 2004 12:07:23 +0200 (IST) Received: from mail.romat.com ([127.0.0.1]) by localhost (mail.romat.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 17773-04 for ; Fri, 12 Nov 2004 12:07:18 +0200 (IST) Received: from gilad (unknown [192.168.1.167]) by mail.romat.com (Postfix) with SMTP id 8C109EB2B6 for ; Fri, 12 Nov 2004 12:07:18 +0200 (IST) Message-ID: <093401c4c89f$7e997d00$a701a8c0@lan> From: "Gilad Rom" To: Subject: [PATCH] Support for RTL8201BL PHY on Au1000 Date: Fri, 12 Nov 2004 12:06:42 +0200 Organization: Romat Telecom MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="windows-1255"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2900.2180 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-Virus-Scanned: by amavisd-new at romat.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6312 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gilad@romat.com Precedence: bulk X-list: linux-mips Content-Length: 6689 Lines: 232 Hello All, Attached is a patch to support the RTL8201BL Phyceiver on the AMD Alchemy Au1x, if anyone is interested. We use it here for our own custom design. Thank you, Gilad Rom Romat Telecom --- linux-2.4.21-mycable.orig/drivers/net/au1000_eth.c 2004-11-10 15:54:07.000000000 +0200 +++ linux-2.4.21-mycable/drivers/net/au1000_eth.c 2004-11-12 12:01:10.000000000 +0200 @@ -330,8 +330,98 @@ { return 0; } +int rtl8201_init(struct net_device *dev, int phy_addr) +{ + s16 data; + + /* Stop auto-negotiation */ + data = mdio_read(dev, phy_addr, MII_CONTROL); + mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO); + + /* Set advertisement to 10/100 and Half/Full duplex + * (full capabilities) */ + data = mdio_read(dev, phy_addr, MII_ANADV); + data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T; + mdio_write(dev, phy_addr, MII_ANADV, data); + + /* Restart auto-negotiation */ + data = mdio_read(dev, phy_addr, MII_CONTROL); + data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO; + mdio_write(dev, phy_addr, MII_CONTROL, data); + + if (au1000_debug > 4) dump_mii(dev, phy_addr); + return 0; +} + +int rtl8201_reset(struct net_device *dev, int phy_addr) +{ + s16 mii_control, timeout; + + if (au1000_debug > 4) { + printk("rtl8201_reset\n"); + dump_mii(dev, phy_addr); + } + + mii_control = mdio_read(dev, phy_addr, MII_CONTROL); + mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET); + mdelay(1); + for (timeout = 100; timeout > 0; --timeout) { + mii_control = mdio_read(dev, phy_addr, MII_CONTROL); + if ((mii_control & MII_CNTL_RESET) == 0) + break; + mdelay(1); + } + if (mii_control & MII_CNTL_RESET) { + printk(KERN_ERR "%s PHY reset timeout !\n", dev->name); + return -1; + } + return 0; +} + +int +rtl8201_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed) +{ + u16 mii_data; + struct au1000_private *aup; + + if (!dev) { + printk(KERN_ERR "rtl8201_status error: NULL dev\n"); + return -1; + } + + aup = (struct au1000_private *) dev->priv; + mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS); + + if (mii_data & MII_STAT_LINK) { + *link = 1; + mii_data = mdio_read(dev, aup->phy_addr, MII_ANLPAR); + + if (mii_data & MII_RTL_PHY_STAT_SPD) { + if (mii_data & MII_RTL_PHY_STAT_FDX) { + *speed = IF_PORT_100BASEFX; + dev->if_port = IF_PORT_100BASEFX; + } + else { + *speed = IF_PORT_100BASETX; + dev->if_port = IF_PORT_100BASETX; + } + } + else { + *speed = IF_PORT_10BASET; + dev->if_port = IF_PORT_10BASET; + } + + } + else { + *link = 0; + *speed = 0; + dev->if_port = IF_PORT_UNKNOWN; + } + return 0; +} + int am79c874_init(struct net_device *dev, int phy_addr) { s16 data; @@ -627,8 +717,14 @@ am79c874_reset, am79c874_status, }; +struct phy_ops rtl8201_ops = { + rtl8201_init, + rtl8201_reset, + rtl8201_status, +}; + struct phy_ops am79c901_ops = { am79c901_init, am79c901_reset, am79c901_status, @@ -671,8 +767,9 @@ {"Broadcom BCM5221 10/100 BaseT PHY",0x0040,0x61e4, &bcm_5201_ops,0}, {"Broadcom BCM5222 10/100 BaseT PHY",0x0040,0x6322, &bcm_5201_ops,1}, {"AMD 79C901 HomePNA PHY",0x0000,0x35c8, &am79c901_ops,0}, {"AMD 79C874 10/100 BaseT PHY",0x0022,0x561b, &am79c874_ops,0}, + {"RealTek 8201BL 10/100 BaseT Phyceiver",0x0000,0x8201, &rtl8201_ops, 0}, {"LSI 80227 10/100 BaseT PHY",0x0016,0xf840, &lsi_80227_ops,0}, {"Intel LXT971A Dual Speed PHY",0x0013,0x78e2, &lxt971a_ops,0}, {"Kendin KS8995M 10/100 BaseT PHY",0x0022,0x1450, &ks8995m_ops,0}, #ifdef CONFIG_MIPS_BOSPORUS @@ -801,11 +898,9 @@ static int mii_probe (struct net_device * dev) { struct au1000_private *aup = (struct au1000_private *) dev->priv; int phy_addr; -#ifdef CONFIG_MIPS_BOSPORUS int phy_found=0; -#endif /* search for total of 32 possible mii phy addresses */ for (phy_addr = 0; phy_addr < 32; phy_addr++) { u16 mii_status; @@ -820,9 +915,9 @@ } #endif mii_status = mdio_read(dev, phy_addr, MII_STATUS); - if (mii_status == 0xffff || mii_status == 0x0000) + if (mii_status == 0xffff || mii_status == 0x0000) /* the mii is not accessable, try next one */ continue; phy_id0 = mdio_read(dev, phy_addr, MII_PHY_ID0); @@ -836,11 +931,9 @@ printk(KERN_INFO "%s: %s at phy address %d\n", dev->name, mii_chip_table[i].name, phy_addr); -#ifdef CONFIG_MIPS_BOSPORUS phy_found = 1; -#endif mii_phy->chip_info = mii_chip_table+i; aup->phy_addr = phy_addr; aup->phy_ops = mii_chip_table[i].phy_ops; aup->phy_ops->phy_init(dev,phy_addr); @@ -932,11 +1025,15 @@ dev->name); return -1; } - printk(KERN_INFO "%s: Using %s as default\n", + if ( (!phy_found) ) { + printk(KERN_INFO "%s: No PHY information available!\n", + dev->name); + } else { + printk(KERN_INFO "%s: Using %s as default\n", dev->name, aup->mii->chip_info->name); - + } return 0; } @@ -1361,8 +1458,9 @@ } au_sync(); aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed); + control = MAC_DISABLE_RX_OWN | MAC_RX_ENABLE | MAC_TX_ENABLE; #ifndef CONFIG_CPU_LITTLE_ENDIAN control |= MAC_BIG_ENDIAN; #endif @@ -1428,9 +1526,8 @@ aup->timer.expires = RUN_AT((1*HZ)); aup->timer.data = (unsigned long)dev; aup->timer.function = &au1000_timer; /* timer handler */ add_timer(&aup->timer); - } static int au1000_open(struct net_device *dev) { --- linux-2.4.21-mycable.orig/drivers/net/au1000_eth.h 2004-11-10 15:54:07.000000000 +0200 +++ linux-2.4.21-mycable/drivers/net/au1000_eth.h 2004-11-11 17:59:21.000000000 +0200 @@ -129,8 +129,12 @@ /* amd phy status register */ #define MII_AMD_PHY_STAT_FDX 0x0800 #define MII_AMD_PHY_STAT_SPD 0x0400 +/* realtek phy status register */ +#define MII_RTL_PHY_STAT_FDX 0x0100 +#define MII_RTL_PHY_STAT_SPD 0x0080 + /* intel phy status register */ #define MII_INTEL_PHY_STAT_FDX 0x0200 #define MII_INTEL_PHY_STAT_SPD 0x4000 From gilad@romat.com Fri Nov 12 10:37:51 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2004 10:37:55 +0000 (GMT) Received: from mail.romat.com ([IPv6:::ffff:212.143.245.3]:6416 "EHLO mail.romat.com") by linux-mips.org with ESMTP id ; Fri, 12 Nov 2004 10:37:51 +0000 Received: from localhost (localhost.lan [127.0.0.1]) by mail.romat.com (Postfix) with ESMTP id 5579EEB2AB for ; Fri, 12 Nov 2004 12:37:45 +0200 (IST) Received: from mail.romat.com ([127.0.0.1]) by localhost (mail.romat.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 17773-07 for ; Fri, 12 Nov 2004 12:37:42 +0200 (IST) Received: from gilad (unknown [192.168.1.167]) by mail.romat.com (Postfix) with SMTP id 1A1B9EB2A9 for ; Fri, 12 Nov 2004 12:37:42 +0200 (IST) Message-ID: <095c01c4c8a3$bd9e0210$a701a8c0@lan> From: "Gilad Rom" To: Subject: GPIO on the Au1500 Date: Fri, 12 Nov 2004 12:38:25 +0200 Organization: Romat Telecom MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="windows-1255"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2900.2180 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-Virus-Scanned: by amavisd-new at romat.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6313 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gilad@romat.com Precedence: bulk X-list: linux-mips Content-Length: 233 Lines: 10 Hello, I am trying to use the au1000_gpio driver, but I'm a little clueless as to how it is meant to be used. Can I use the GPIO ioctl's from a userland program, or must I write a kernel module? Thank you, Gilad Rom Romat Telecom From ralf@linux-mips.org Fri Nov 12 13:44:43 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2004 13:45:57 +0000 (GMT) Received: from pD9562B74.dip.t-dialin.net ([IPv6:::ffff:217.86.43.116]:13865 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Fri, 12 Nov 2004 13:44:43 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iACDiew0007624; Fri, 12 Nov 2004 14:44:40 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iACDieJr007623; Fri, 12 Nov 2004 14:44:40 +0100 Date: Fri, 12 Nov 2004 14:44:40 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Subject: Re: gcc 3.3.4/3.4.1 and get_user Message-ID: <20041112134440.GA7588@linux-mips.org> References: <87656yqsmz.fsf@redhat.com> <20040920154042.GB5150@linux-mips.org> <20040920171021.GA25371@linux-mips.org> <20041104.153744.122623401.nemoto@toshiba-tops.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041104.153744.122623401.nemoto@toshiba-tops.co.jp> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6314 X-Approved-By: ralf@linux-mips.org X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 24588 Lines: 886 On Thu, Nov 04, 2004 at 03:37:44PM +0900, Atsushi Nemoto wrote: Slow answer - but not forgotten :-) > ralf> And here the same for 2.4. Actually this is a straight backport > ralf> of the 2.6 uaccess.h to 2.4 so with this patch > ralf> include/asm-mips/uaccess.h and include/asm-mips64/uaccess.h are > ralf> going to be identical. > > I found that asm-mips/uaccess.h and asm-mips64/uaccess.h in 2.4 are > sill not identical. Is this intentional? Current > asm-mips64/uaccess.h seems broken... They were both supposed to be identical. > Also, arch/mips64/lib/strxxx_user.S should be modified to use t0/t1 > instead of ta0/ta1 ? (__UA_t0 is now $12, not $8) Right, part of the same mistake. See the patch below which gets my test system working. The 32-bit parts are cosmetic and shouldn't change the generated code. They just make the 32-bit and 64-bit str*_user.S files almost identical. I'm surprised somebody still cares about 2.4 64-bit ;-) The 64-bit improvments in 2.6, especially in the area of the 32-bit compatibility code are so substancial that I don't think 2.4 is still a good choice. Ralf Index: arch/mips/lib/strlen_user.S =================================================================== RCS file: /home/cvs/linux/arch/mips/lib/strlen_user.S,v retrieving revision 1.6.2.1 diff -u -r1.6.2.1 strlen_user.S --- arch/mips/lib/strlen_user.S 1 Jul 2002 15:27:23 -0000 1.6.2.1 +++ arch/mips/lib/strlen_user.S 12 Nov 2004 13:32:02 -0000 @@ -23,18 +23,18 @@ * Return 0 for error */ LEAF(__strlen_user_asm) - lw v0, THREAD_CURDS($28) # pointer ok? - and v0, a0 - bltz v0, fault + LONG_L v0, THREAD_CURDS($28) # pointer ok? + and v0, a0 + bltz v0, fault FEXPORT(__strlen_user_nocheck_asm) - move v0, a0 + move v0, a0 1: EX(lb, t0, (v0), fault) - addiu v0, 1 - bnez t0, 1b - subu v0, a0 - jr ra + addiu v0, 1 + bnez t0, 1b + subu v0, a0 + jr ra END(__strlen_user_asm) -fault: move v0, zero - jr ra +fault: move v0, zero + jr ra Index: arch/mips/lib/strncpy_user.S =================================================================== RCS file: /home/cvs/linux/arch/mips/lib/strncpy_user.S,v retrieving revision 1.5 diff -u -r1.5 strncpy_user.S --- arch/mips/lib/strncpy_user.S 6 Sep 2001 13:12:02 -0000 1.5 +++ arch/mips/lib/strncpy_user.S 12 Nov 2004 13:32:02 -0000 @@ -28,31 +28,31 @@ */ LEAF(__strncpy_from_user_asm) - lw v0, THREAD_CURDS($28) # pointer ok? - and v0, a1 - bltz v0, fault + LONG_L v0, THREAD_CURDS($28) # pointer ok? + and v0, a1 + bltz v0, fault -EXPORT(__strncpy_from_user_nocheck_asm) - move v0, zero - move v1, a1 - .set noreorder -1: EX(lbu, t0, (v1), fault) - addiu v1, v1, 1 - beqz t0, 2f - sb t0, (a0) - addiu v0, 1 - bne v0, a2, 1b - addiu a0, 1 - .set reorder -2: addu t0, a1, v0 - xor t0, a1 - bltz t0, fault - jr ra # return n +FEXPORT(__strncpy_from_user_nocheck_asm) + move v0, zero + move v1, a1 + .set noreorder +1: EX(lbu, t0, (v1), fault) + PTR_ADDIU v1, 1 + beqz t0, 2f + sb t0, (a0) + PTR_ADDIU v0, 1 + bne v0, a2, 1b + PTR_ADDIU a0, 1 + .set reorder +2: PTR_ADDU t0, a1, v0 + xor t0, a1 + bltz t0, fault + jr ra # return n END(__strncpy_from_user_asm) -fault: li v0, -EFAULT - jr ra +fault: li v0, -EFAULT + jr ra - .section __ex_table,"a" - PTR 1b, fault + .section __ex_table,"a" + PTR 1b, fault .previous Index: arch/mips/lib/strnlen_user.S =================================================================== RCS file: /home/cvs/linux/arch/mips/lib/strnlen_user.S,v retrieving revision 1.3.2.1 diff -u -r1.3.2.1 strnlen_user.S --- arch/mips/lib/strnlen_user.S 1 Jul 2002 15:27:23 -0000 1.3.2.1 +++ arch/mips/lib/strnlen_user.S 12 Nov 2004 13:32:02 -0000 @@ -27,23 +27,22 @@ * bytes. There's nothing secret there ... */ LEAF(__strnlen_user_asm) - lw v0, THREAD_CURDS($28) # pointer ok? - and v0, a0 - bltz v0, fault + LONG_L v0, THREAD_CURDS($28) # pointer ok? + and v0, a0 + bltz v0, fault FEXPORT(__strnlen_user_nocheck_asm) - .type __strnlen_user_nocheck_asm,@function - move v0, a0 - addu a1, a0 # stop pointer - .set noreorder -1: beq v0, a1, 1f # limit reached? - addiu v0, 1 - .set reorder + move v0, a0 + PTR_ADDU a1, a0 # stop pointer + .set noreorder +1: beq v0, a1, 1f # limit reached? + PTR_ADDIU v0, 1 + .set reorder EX(lb, t0, -1(v0), fault) - bnez t0, 1b -1: subu v0, a0 - jr ra + bnez t0, 1b +1: PTR_SUBU v0, a0 + jr ra END(__strnlen_user_asm) -fault: move v0, zero - jr ra +fault: move v0, zero + jr ra Index: arch/mips64/lib/strlen_user.S =================================================================== RCS file: /home/cvs/linux/arch/mips64/lib/Attic/strlen_user.S,v retrieving revision 1.4.2.2 diff -u -r1.4.2.2 strlen_user.S --- arch/mips64/lib/strlen_user.S 9 Dec 2002 21:24:13 -0000 1.4.2.2 +++ arch/mips64/lib/strlen_user.S 12 Nov 2004 13:32:02 -0000 @@ -23,18 +23,18 @@ * Return 0 for error */ LEAF(__strlen_user_asm) - ld v0, THREAD_CURDS($28) # pointer ok? - and v0, a0 - bnez v0, fault + LONG_L v0, THREAD_CURDS($28) # pointer ok? + and v0, a0 + bnez v0, fault FEXPORT(__strlen_user_nocheck_asm) - move v0, a0 -1: EX(lb, ta0, (v0), fault) - daddiu v0, 1 - bnez ta0, 1b - dsubu v0, a0 - jr ra + move v0, a0 +1: EX(lb, t0, (v0), fault) + PTR_ADDIU v0, 1 + bnez t0, 1b + PTR_SUBU v0, a0 + jr ra END(__strlen_user_asm) -fault: move v0, zero - jr ra +fault: move v0, zero + jr ra Index: arch/mips64/lib/strncpy_user.S =================================================================== RCS file: /home/cvs/linux/arch/mips64/lib/Attic/strncpy_user.S,v retrieving revision 1.4.2.1 diff -u -r1.4.2.1 strncpy_user.S --- arch/mips64/lib/strncpy_user.S 9 Dec 2002 21:24:13 -0000 1.4.2.1 +++ arch/mips64/lib/strncpy_user.S 12 Nov 2004 13:32:02 -0000 @@ -28,31 +28,31 @@ */ LEAF(__strncpy_from_user_asm) - ld v0, THREAD_CURDS($28) # pointer ok? - and v0, a1 - bnez v0, fault + LONG_L v0, THREAD_CURDS($28) # pointer ok? + and v0, a1 + bnez v0, fault FEXPORT(__strncpy_from_user_nocheck_asm) - move v0, zero - move v1, a1 - .set noreorder -1: EX(lbu, ta0, (v1), fault) - daddiu v1, 1 - beqz ta0, 2f - sb ta0, (a0) - daddiu v0, 1 - bne v0, a2, 1b - daddiu a0, 1 - .set reorder -2: daddu ta0, a1, v0 - xor ta0, a1 - bltz ta0, fault - jr ra # return n + move v0, zero + move v1, a1 + .set noreorder +1: EX(lbu, t0, (v1), fault) + PTR_ADDIU v1, 1 + beqz t0, 2f + sb t0, (a0) + PTR_ADDIU v0, 1 + bne v0, a2, 1b + PTR_ADDIU a0, 1 + .set reorder +2: PTR_ADDU t0, a1, v0 + xor t0, a1 + bltz t0, fault + jr ra # return n END(__strncpy_from_user_asm) -fault: li v0, -EFAULT - jr ra +fault: li v0, -EFAULT + jr ra .section __ex_table,"a" - PTR 1b, fault + PTR 1b, fault .previous Index: arch/mips64/lib/strnlen_user.S =================================================================== RCS file: /home/cvs/linux/arch/mips64/lib/Attic/strnlen_user.S,v retrieving revision 1.2.2.3 diff -u -r1.2.2.3 strnlen_user.S --- arch/mips64/lib/strnlen_user.S 9 Dec 2002 21:24:13 -0000 1.2.2.3 +++ arch/mips64/lib/strnlen_user.S 12 Nov 2004 13:32:02 -0000 @@ -20,23 +20,29 @@ /* * Return the size of a string (including the ending 0) * - * Return 0 for error, len on string but at max a1 otherwise + * Return 0 for error, len of string but at max a1 otherwise + * + * Note: for performance reasons we deliberately accept that a user may + * make strlen_user and strnlen_user access the first few KSEG0 + * bytes. There's nothing secret there ... */ LEAF(__strnlen_user_asm) - ld v0, THREAD_CURDS($28) # pointer ok? - and v0, a0 - bnez v0, fault + LONG_L v0, THREAD_CURDS($28) # pointer ok? + and v0, a0 + bnez v0, fault FEXPORT(__strnlen_user_nocheck_asm) - move v0, a0 - daddu a1, a0 # stop pointer -1: beq v0, a1, 1f # limit reached? - EX(lb, ta0, (v0), fault) - daddiu v0, 1 - bnez ta0, 1b -1: dsubu v0, a0 - jr ra + move v0, a0 + PTR_ADDU a1, a0 # stop pointer + .set noreorder +1: beq v0, a1, 1f # limit reached? + PTR_ADDIU v0, 1 + .set reorder + EX(lb, t0, -1(v0), fault) + bnez t0, 1b +1: PTR_SUBU v0, a0 + jr ra END(__strnlen_user_asm) -fault: move v0, zero - jr ra +fault: move v0, zero + jr ra Index: include/asm-mips64/uaccess.h =================================================================== RCS file: /home/cvs/linux/include/asm-mips64/Attic/uaccess.h,v retrieving revision 1.13.2.3 diff -u -r1.13.2.3 uaccess.h --- include/asm-mips64/uaccess.h 5 Jul 2003 03:23:46 -0000 1.13.2.3 +++ include/asm-mips64/uaccess.h 12 Nov 2004 13:32:06 -0000 @@ -3,18 +3,17 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle + * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_UACCESS_H #define _ASM_UACCESS_H +#include +#include #include #include -#define STR(x) __STR(x) -#define __STR(x) #x - /* * The fs value determines whether argument validity checking should be * performed or not. If get_fs() == USER_DS, checking is performed, with @@ -22,15 +21,47 @@ * * For historical reasons, these macros are grossly misnamed. */ +#ifdef CONFIG_MIPS32 + +#define __UA_LIMIT 0x80000000UL + +#define __UA_ADDR ".word" +#define __UA_LA "la" +#define __UA_ADDU "addu" +#define __UA_t0 "$8" +#define __UA_t1 "$9" + +#endif /* CONFIG_MIPS32 */ + +#ifdef CONFIG_MIPS64 + +#define __UA_LIMIT (- TASK_SIZE) + +#define __UA_ADDR ".dword" +#define __UA_LA "dla" +#define __UA_ADDU "daddu" +#define __UA_t0 "$12" +#define __UA_t1 "$13" + +#endif /* CONFIG_MIPS64 */ + +/* + * USER_DS is a bitmask that has the bits set that may not be set in a valid + * userspace address. Note that we limit 32-bit userspace to 0x7fff8000 but + * the arithmetic we're doing only works if the limit is a power of two, so + * we use 0x80000000 here on 32-bit kernels. If a process passes an invalid + * address in this range it's the process's problem, not ours :-) + */ + #define KERNEL_DS ((mm_segment_t) { 0UL }) -#define USER_DS ((mm_segment_t) { -TASK_SIZE }) +#define USER_DS ((mm_segment_t) { __UA_LIMIT }) #define VERIFY_READ 0 #define VERIFY_WRITE 1 -#define get_fs() (current->thread.current_ds) #define get_ds() (KERNEL_DS) -#define set_fs(x) (current->thread.current_ds=(x)) +#define get_fs() (current->thread.current_ds) +#define set_fs(x) (current->thread.current_ds = (x)) #define segment_eq(a,b) ((a).seg == (b).seg) @@ -44,14 +75,12 @@ * - AND "size" doesn't have any high-bits set * - AND "addr+size" doesn't have any high-bits set * - OR we are in kernel mode. + * + * __ua_size() is a trick to avoid runtime checking of positive constant + * sizes; for those we already know at compile time that the size is ok. */ #define __ua_size(size) \ - ((__builtin_constant_p(size) && (size)) > 0 ? 0 : (size)) - -#define __access_ok(addr, size, mask) \ - (((mask) & ((addr) | ((addr) + (size)) | __ua_size(size))) == 0) - -#define __access_mask get_fs().seg + ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size)) /* * access_ok: - Checks if a user space pointer is valid @@ -72,8 +101,14 @@ * checks that the pointer is in the user space range - after calling * this function, memory access functions may still return -EFAULT. */ + +#define __access_mask get_fs().seg + +#define __access_ok(addr, size, mask) \ + (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) + #define access_ok(type, addr, size) \ - __access_ok((unsigned long)(addr), (size), __access_mask) + likely(__access_ok((unsigned long)(addr), (size),__access_mask)) /* * verify_area: - Obsolete, use access_ok() @@ -184,117 +219,177 @@ struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct *)(x)) -#define __get_user_nocheck(x,ptr,size) \ -({ \ - long __gu_err; \ - __typeof(*(ptr)) __gu_val; \ - long __gu_addr; \ - __asm__("":"=r" (__gu_val)); \ - __gu_addr = (long) (ptr); \ - __asm__("":"=r" (__gu_err)); \ - switch (size) { \ - case 1: __get_user_asm("lb"); break; \ - case 2: __get_user_asm("lh"); break; \ - case 4: __get_user_asm("lw"); break; \ - case 8: __get_user_asm("ld"); break; \ - default: __get_user_unknown(); break; \ - } x = (__typeof__(*(ptr))) __gu_val; \ - __gu_err; \ -}) - -#define __get_user_check(x,ptr,size) \ -({ \ - long __gu_err; \ - __typeof__(*(ptr)) __gu_val; \ - long __gu_addr; \ - __asm__("":"=r" (__gu_val)); \ - __gu_addr = (long) (ptr); \ - __asm__("":"=r" (__gu_err)); \ - if (__access_ok(__gu_addr,size,__access_mask)) { \ - switch (size) { \ - case 1: __get_user_asm("lb"); break; \ - case 2: __get_user_asm("lh"); break; \ - case 4: __get_user_asm("lw"); break; \ - case 8: __get_user_asm("ld"); break; \ - default: __get_user_unknown(); break; \ - } \ - } x = (__typeof__(*(ptr))) __gu_val; \ - __gu_err; \ -}) - -#define __get_user_asm(insn) \ -({ \ - __asm__ __volatile__( \ - "1:\t" insn "\t%1,%2\n\t" \ - "move\t%0,$0\n" \ - "2:\n\t" \ - ".section\t.fixup,\"ax\"\n" \ - "3:\tli\t%0,%3\n\t" \ - "move\t%1,$0\n\t" \ - "j\t2b\n\t" \ - ".previous\n\t" \ - ".section\t__ex_table,\"a\"\n\t" \ - ".dword\t1b,3b\n\t" \ - ".previous" \ - :"=r" (__gu_err), "=r" (__gu_val) \ - :"o" (__m(__gu_addr)), "i" (-EFAULT)); \ +/* + * Yuck. We need two variants, one for 64bit operation and one + * for 32 bit mode and old iron. + */ +#ifdef __mips64 +#define __GET_USER_DW(__gu_err) __get_user_asm("ld", __gu_err) +#else +#define __GET_USER_DW(__gu_err) __get_user_asm_ll32(__gu_err) +#endif + +#define __get_user_nocheck(x,ptr,size) \ +({ \ + long __gu_err = 0; \ + __typeof(*(ptr)) __gu_val = 0; \ + long __gu_addr; \ + __gu_addr = (long) (ptr); \ + switch (size) { \ + case 1: __get_user_asm("lb", __gu_err); break; \ + case 2: __get_user_asm("lh", __gu_err); break; \ + case 4: __get_user_asm("lw", __gu_err); break; \ + case 8: __GET_USER_DW(__gu_err); break; \ + default: __get_user_unknown(); break; \ + } \ + x = (__typeof__(*(ptr))) __gu_val; \ + __gu_err; \ +}) + +#define __get_user_check(x,ptr,size) \ +({ \ + __typeof__(*(ptr)) __gu_val = 0; \ + long __gu_addr = (long) (ptr); \ + long __gu_err; \ + \ + __gu_err = verify_area(VERIFY_READ, (void *) __gu_addr, size); \ + \ + if (likely(!__gu_err)) { \ + switch (size) { \ + case 1: __get_user_asm("lb", __gu_err); break; \ + case 2: __get_user_asm("lh", __gu_err); break; \ + case 4: __get_user_asm("lw", __gu_err); break; \ + case 8: __GET_USER_DW(__gu_err); break; \ + default: __get_user_unknown(); break; \ + } \ + } \ + x = (__typeof__(*(ptr))) __gu_val; \ + __gu_err; \ +}) + +#define __get_user_asm(insn,__gu_err) \ +({ \ + __asm__ __volatile__( \ + "1: " insn " %1, %3 \n" \ + "2: \n" \ + " .section .fixup,\"ax\" \n" \ + "3: li %0, %4 \n" \ + " j 2b \n" \ + " .previous \n" \ + " .section __ex_table,\"a\" \n" \ + " "__UA_ADDR "\t1b, 3b \n" \ + " .previous \n" \ + : "=r" (__gu_err), "=r" (__gu_val) \ + : "0" (__gu_err), "o" (__m(__gu_addr)), "i" (-EFAULT)); \ +}) + +/* + * Get a long long 64 using 32 bit registers. + */ +#define __get_user_asm_ll32(__gu_err) \ +({ \ + __asm__ __volatile__( \ + "1: lw %1, %3 \n" \ + "2: lw %D1, %4 \n" \ + " move %0, $0 \n" \ + "3: .section .fixup,\"ax\" \n" \ + "4: li %0, %5 \n" \ + " move %1, $0 \n" \ + " move %D1, $0 \n" \ + " j 3b \n" \ + " .previous \n" \ + " .section __ex_table,\"a\" \n" \ + " " __UA_ADDR " 1b, 4b \n" \ + " " __UA_ADDR " 2b, 4b \n" \ + " .previous \n" \ + : "=r" (__gu_err), "=&r" (__gu_val) \ + : "0" (__gu_err), "o" (__m(__gu_addr)), \ + "o" (__m(__gu_addr + 4)), "i" (-EFAULT)); \ }) extern void __get_user_unknown(void); -#define __put_user_nocheck(x,ptr,size) \ -({ \ - long __pu_err; \ - __typeof__(*(ptr)) __pu_val; \ - long __pu_addr; \ - __pu_val = (x); \ - __pu_addr = (long) (ptr); \ - __asm__("":"=r" (__pu_err)); \ - switch (size) { \ - case 1: __put_user_asm("sb"); break; \ - case 2: __put_user_asm("sh"); break; \ - case 4: __put_user_asm("sw"); break; \ - case 8: __put_user_asm("sd"); break; \ - default: __put_user_unknown(); break; \ - } \ - __pu_err; \ -}) - -#define __put_user_check(x,ptr,size) \ -({ \ - long __pu_err; \ - __typeof__(*(ptr)) __pu_val; \ - long __pu_addr; \ - __pu_val = (x); \ - __pu_addr = (long) (ptr); \ - __asm__("":"=r" (__pu_err)); \ - if (__access_ok(__pu_addr,size,__access_mask)) { \ - switch (size) { \ - case 1: __put_user_asm("sb"); break; \ - case 2: __put_user_asm("sh"); break; \ - case 4: __put_user_asm("sw"); break; \ - case 8: __put_user_asm("sd"); break; \ - default: __put_user_unknown(); break; \ - } \ - } \ - __pu_err; \ -}) - -#define __put_user_asm(insn) \ -({ \ - __asm__ __volatile__( \ - "1:\t" insn "\t%z1, %2\t\t\t# __put_user_asm\n\t" \ - "move\t%0, $0\n" \ - "2:\n\t" \ - ".section\t.fixup,\"ax\"\n" \ - "3:\tli\t%0, %3\n\t" \ - "j\t2b\n\t" \ - ".previous\n\t" \ - ".section\t__ex_table,\"a\"\n\t" \ - ".dword\t1b, 3b\n\t" \ - ".previous" \ - :"=r" (__pu_err) \ - :"Jr" (__pu_val), "o" (__m(__pu_addr)), "i" (-EFAULT)); \ +/* + * Yuck. We need two variants, one for 64bit operation and one + * for 32 bit mode and old iron. + */ +#ifdef __mips64 +#define __PUT_USER_DW(__pu_val) __put_user_asm("sd", __pu_val) +#else +#define __PUT_USER_DW(__pu_val) __put_user_asm_ll32(__pu_val) +#endif + +#define __put_user_nocheck(x,ptr,size) \ +({ \ + long __pu_err = 0; \ + __typeof__(*(ptr)) __pu_val; \ + long __pu_addr; \ + __pu_val = (x); \ + __pu_addr = (long) (ptr); \ + switch (size) { \ + case 1: __put_user_asm("sb", __pu_val); break; \ + case 2: __put_user_asm("sh", __pu_val); break; \ + case 4: __put_user_asm("sw", __pu_val); break; \ + case 8: __PUT_USER_DW(__pu_val); break; \ + default: __put_user_unknown(); break; \ + } \ + __pu_err; \ +}) + +#define __put_user_check(x,ptr,size) \ +({ \ + __typeof__(*(ptr)) __pu_val = (x); \ + long __pu_addr = (long) (ptr); \ + long __pu_err; \ + \ + __pu_err = verify_area(VERIFY_WRITE, (void *) __pu_addr, size); \ + \ + if (likely(!__pu_err)) { \ + switch (size) { \ + case 1: __put_user_asm("sb", __pu_val); break; \ + case 2: __put_user_asm("sh", __pu_val); break; \ + case 4: __put_user_asm("sw", __pu_val); break; \ + case 8: __PUT_USER_DW(__pu_val); break; \ + default: __put_user_unknown(); break; \ + } \ + } \ + __pu_err; \ +}) + +#define __put_user_asm(insn, __pu_val) \ +({ \ + __asm__ __volatile__( \ + "1: " insn " %z2, %3 # __put_user_asm\n" \ + "2: \n" \ + " .section .fixup,\"ax\" \n" \ + "3: li %0, %4 \n" \ + " j 2b \n" \ + " .previous \n" \ + " .section __ex_table,\"a\" \n" \ + " " __UA_ADDR " 1b, 3b \n" \ + " .previous \n" \ + : "=r" (__pu_err) \ + : "0" (__pu_err), "Jr" (__pu_val), "o" (__m(__pu_addr)), \ + "i" (-EFAULT)); \ +}) + +#define __put_user_asm_ll32(__pu_val) \ +({ \ + __asm__ __volatile__( \ + "1: sw %2, %3 # __put_user_asm_ll32 \n" \ + "2: sw %D2, %4 \n" \ + "3: \n" \ + " .section .fixup,\"ax\" \n" \ + "4: li %0, %5 \n" \ + " j 3b \n" \ + " .previous \n" \ + " .section __ex_table,\"a\" \n" \ + " " __UA_ADDR " 1b, 4b \n" \ + " " __UA_ADDR " 2b, 4b \n" \ + " .previous" \ + : "=r" (__pu_err) \ + : "0" (__pu_err), "r" (__pu_val), "o" (__m(__pu_addr)), \ + "o" (__m(__pu_addr + 4)), "i" (-EFAULT)); \ }) extern void __put_user_unknown(void); @@ -304,13 +399,13 @@ * jump instructions */ #ifdef MODULE -#define __MODULE_JAL(destination) \ - ".set\tnoat\n\t" \ - "dla\t$1, " #destination "\n\t" \ - "jalr\t$1\n\t" \ +#define __MODULE_JAL(destination) \ + ".set\tnoat\n\t" \ + __UA_LA "\t$1, " #destination "\n\t" \ + "jalr\t$1\n\t" \ ".set\tat\n\t" #else -#define __MODULE_JAL(destination) \ +#define __MODULE_JAL(destination) \ "jal\t" #destination "\n\t" #endif @@ -361,6 +456,9 @@ __cu_len; \ }) +#define __copy_to_user_inatomic __copy_to_user +#define __copy_from_user_inatomic __copy_from_user + /* * copy_to_user: - Copy a block of data into user space. * @to: Destination address, in user space. @@ -402,10 +500,9 @@ ".set\tnoreorder\n\t" \ __MODULE_JAL(__copy_user) \ ".set\tnoat\n\t" \ - "daddu\t$1, %1, %2\n\t" \ + __UA_ADDU "\t$1, %1, %2\n\t" \ ".set\tat\n\t" \ - ".set\treorder\n\t" \ - "move\t%0, $6" \ + ".set\treorder" \ : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ : \ : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ @@ -498,19 +595,19 @@ "move\t%0, $6" : "=r" (res) : "r" (addr), "r" (size) - : "$4", "$5", "$6", "$8", "$9", "$31"); + : "$4", "$5", "$6", __UA_t0, __UA_t1, "$31"); return res; } -#define clear_user(addr,n) \ -({ \ - void * __cl_addr = (addr); \ - unsigned long __cl_size = (n); \ - if (__cl_size && access_ok(VERIFY_WRITE, \ - ((unsigned long)(__cl_addr)), __cl_size)) \ - __cl_size = __clear_user(__cl_addr, __cl_size); \ - __cl_size; \ +#define clear_user(addr,n) \ +({ \ + void * __cl_addr = (addr); \ + unsigned long __cl_size = (n); \ + if (__cl_size && access_ok(VERIFY_WRITE, \ + ((unsigned long)(__cl_addr)), __cl_size)) \ + __cl_size = __clear_user(__cl_addr, __cl_size); \ + __cl_size; \ }) /* @@ -546,7 +643,7 @@ "move\t%0, $2" : "=r" (res) : "r" (__to), "r" (__from), "r" (__len) - : "$2", "$3", "$4", "$5", "$6", "$8", "$31", "memory"); + : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); return res; } @@ -582,7 +679,7 @@ "move\t%0, $2" : "=r" (res) : "r" (__to), "r" (__from), "r" (__len) - : "$2", "$3", "$4", "$5", "$6", "$8", "$31", "memory"); + : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); return res; } @@ -598,7 +695,7 @@ "move\t%0, $2" : "=r" (res) : "r" (s) - : "$2", "$4", "$8", "$31"); + : "$2", "$4", __UA_t0, "$31"); return res; } @@ -627,7 +724,24 @@ "move\t%0, $2" : "=r" (res) : "r" (s) - : "$2", "$4", "$8", "$31"); + : "$2", "$4", __UA_t0, "$31"); + + return res; +} + +/* Returns: 0 if bad, string length+1 (memory size) of string if ok */ +static inline long __strnlen_user(const char *s, long n) +{ + long res; + + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + __MODULE_JAL(__strnlen_user_nocheck_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s), "r" (n) + : "$2", "$4", "$5", __UA_t0, "$31"); return res; } @@ -635,13 +749,16 @@ /* * strlen_user: - Get the size of a string in user space. * @str: The string to measure. - * @n: The maximum valid length + * + * Context: User context only. This function may sleep. * * Get the size of a NUL-terminated string in user space. * * Returns the size of the string INCLUDING the terminating NUL. * On exception, returns 0. - * If the string is too long, returns a value greater than @n. + * + * If there is a limit on the length of a valid string, you may wish to + * consider using strnlen_user() instead. */ static inline long strnlen_user(const char *s, long n) { @@ -654,7 +771,7 @@ "move\t%0, $2" : "=r" (res) : "r" (s), "r" (n) - : "$2", "$4", "$5", "$8", "$31"); + : "$2", "$4", "$5", __UA_t0, "$31"); return res; } @@ -669,9 +786,9 @@ extern unsigned long search_exception_table(unsigned long addr); /* Returns the new pc */ -#define fixup_exception(map_reg, fixup_unit, pc) \ -({ \ - fixup_unit; \ +#define fixup_exception(map_reg, fixup_unit, pc) \ +({ \ + fixup_unit; \ }) #endif /* _ASM_UACCESS_H */ From ppopov@embeddedalley.com Fri Nov 12 18:13:45 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Nov 2004 18:13:52 +0000 (GMT) Received: from web81008.mail.yahoo.com ([IPv6:::ffff:206.190.37.153]:25998 "HELO web81008.mail.yahoo.com") by linux-mips.org with SMTP id ; Fri, 12 Nov 2004 18:13:45 +0000 Message-ID: <20041112181335.13362.qmail@web81008.mail.yahoo.com> Received: from [64.163.129.140] by web81008.mail.yahoo.com via HTTP; Fri, 12 Nov 2004 10:13:35 PST X-RocketYMMF: pvpopov@pacbell.net Date: Fri, 12 Nov 2004 10:13:35 -0800 (PST) From: Pete Popov Reply-To: ppopov@embeddedalley.com Subject: Re: GPIO on the Au1500 To: Gilad Rom , linux-mips@linux-mips.org In-Reply-To: <095c01c4c8a3$bd9e0210$a701a8c0@lan> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6315 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ppopov@embeddedalley.com Precedence: bulk X-list: linux-mips Content-Length: 442 Lines: 23 --- Gilad Rom wrote: > Hello, > > I am trying to use the au1000_gpio driver, but I'm a > little clueless as to how it is meant to be used. > Can I use the GPIO ioctl's from a userland > program, or must I write a kernel module? I'll see if I can dig up some docs and the example userland program this weekend. That driver hasn't been tested in a while though. Pete > Thank you, > Gilad Rom > Romat Telecom > > > From mlachwani@prometheus.mvista.com Sat Nov 13 03:18:31 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 13 Nov 2004 03:18:37 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:64754 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Sat, 13 Nov 2004 03:18:31 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iAD3ITdh029143; Fri, 12 Nov 2004 19:18:29 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iAD3ISLo029141; Fri, 12 Nov 2004 19:18:28 -0800 Date: Fri, 12 Nov 2004 19:18:28 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Support for backplane on the Toshiba 4400 board Message-ID: <20041113031828.GA29134@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="WIyZ46R2i8wDzkSu" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6316 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 6391 Lines: 226 --WIyZ46R2i8wDzkSu Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ralf Attached patch implements support for backplane on the TX4927 based board. Tested using PCI and IDE on the backplane. Please review ... Thanks Manish Lachwani --WIyZ46R2i8wDzkSu Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename="common_mips_toshiba_backplane_MR9019.patch" Source: MontaVista Software, Inc. | http://www.mvista.com | Manish Lachwani Type: Enhancement Disposition: Submitted to Linux-MIPS Description: Support for Backplane on the Toshiba 4400. Tested using PCI and IDE on the backplane Index: linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c =================================================================== --- linux.orig/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -337,7 +337,6 @@ return (sw_irq); } -//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } #define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, SA_SHIRQ, CPU_MASK_NONE, s, NULL, NULL } static struct irqaction toshiba_rbtx4927_irq_ioc_action = TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME); @@ -513,7 +512,7 @@ #ifdef CONFIG_TOSHIBA_FPCIB0 -static void __init toshiba_rbtx4927_irq_isa_init(void) +void toshiba_rbtx4927_irq_isa_init(void) { int i; @@ -675,13 +674,6 @@ tx4927_irq_init(); toshiba_rbtx4927_irq_ioc_init(); -#ifdef CONFIG_TOSHIBA_FPCIB0 - { - if (tx4927_using_backplane) { - toshiba_rbtx4927_irq_isa_init(); - } - } -#endif wbflush(); Index: linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c =================================================================== --- linux.orig/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -242,6 +242,16 @@ EARLY_PCI_OP(write, word, u16) EARLY_PCI_OP(write, dword, u32) +#ifdef CONFIG_TOSHIBA_FPCIB0 +extern void toshiba_rbtx4927_irq_isa_init(); +#endif + +/* + * tx4927_pcibios_init is now an arch_initcall and no longer + * called from pci_setup(). As a result, we can determine whether + * the board has a backplane or not only after tx4927_pcibios_init + * is done. + */ static int __init tx4927_pcibios_init(void) { unsigned int id; @@ -345,6 +355,9 @@ s); } + /* + * This is IDE on the backplane + */ if (id == 0x91301055) { u8 v08_04; u8 v08_09; @@ -481,6 +494,74 @@ TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, "+\n"); + /* Backplane */ + early_read_config_dword(hose, busno, busno, 0x90, + PCI_VENDOR_ID, &id); + + /* Check backplane */ + if (id == 0x94601055) { + tx4927_using_backplane = 1; + printk("backplane board IS installed\n"); + } + else + printk("No Backplane \n"); + +#ifdef CONFIG_TOSHIBA_FPCIB0 +{ + if (tx4927_using_backplane) { + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":fpcibo=yes\n"); + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":smsc_fdc37m81x_init()\n"); + smsc_fdc37m81x_init(0x3f0); + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":smsc_fdc37m81x_config_beg()\n"); + smsc_fdc37m81x_config_beg(); + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":smsc_fdc37m81x_config_set(KBD)\n"); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, + SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, + 1); + + smsc_fdc37m81x_config_end(); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":smsc_fdc37m81x_config_end()\n"); + } else { + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":fpcibo=not_found\n"); + } +} +#else + { + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n"); + } +#endif + +#ifdef CONFIG_TOSHIBA_FPCIB0 + if (tx4927_using_backplane) { + /* + * This function below does a critical job of allocating + * IRQ for IDE. Since at the time arch_init_irq() calls this + * the PCI is not initialized and we dont know whether + * there is backplane or not. Hence, we do this here + */ + toshiba_rbtx4927_irq_isa_init(); + } +#endif + return 0; } @@ -869,56 +950,6 @@ #endif tx4927_pci_setup(); - if (tx4927_using_backplane == 1) - printk("backplane board IS installed\n"); - else - printk("No Backplane \n"); - - /* this is on ISA bus behind PCI bus, so need PCI up first */ -#ifdef CONFIG_TOSHIBA_FPCIB0 - { - if (tx4927_using_backplane) { - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":fpcibo=yes\n"); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_init()\n"); - smsc_fdc37m81x_init(0x3f0); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_config_beg()\n"); - smsc_fdc37m81x_config_beg(); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_config_set(KBD)\n"); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, - SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, - 1); - - smsc_fdc37m81x_config_end(); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_config_end()\n"); - } else { - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":fpcibo=not_found\n"); - } - } -#else - { - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n"); - } -#endif - #endif /* CONFIG_PCI */ #ifdef CONFIG_SERIAL_TXX9_CONSOLE --WIyZ46R2i8wDzkSu-- From emblinux@macrohat.com Sat Nov 13 13:47:35 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 13 Nov 2004 13:47:39 +0000 (GMT) Received: from [IPv6:::ffff:218.30.103.173] ([IPv6:::ffff:218.30.103.173]:42756 "EHLO mxvip13.hichina.com") by linux-mips.org with ESMTP id ; Sat, 13 Nov 2004 13:47:35 +0000 Received: from 210.82.109.205 (HELO wanghonghui) (envelope-from emblinux@macrohat.com) by mxvip13.hichina.com (quarkmail-1.2.1) with ESMTP id S334183AbUKMNrD for linux-mips@linux-mips.org; Sat, 13 Nov 2004 21:47:03 +0800 Date: Sat, 13 Nov 2004 21:47:02 +0800 From: "macrohat" Reply-To: emblinux@macrohat.com To: "linux-mips" Cc: "linux-cvs" Subject: X-mailer: Foxmail 5.0 beta1 [cn] Mime-Version: 1.0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: base64 Message-Id: <20041113134735Z8224907-1751+1490@linux-mips.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6317 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: emblinux@macrohat.com Precedence: bulk X-list: linux-mips Content-Length: 585 Lines: 9 SGVsbG8gbGludXgtbWlwczoNCg0KSSBoYXZlIGEgcXVlc3Rpb24gdG8gYXNrIHlvdTogd2h5IEJD TTEyNTAgQ1BVIEJvZ29taXBzIGlzIHNvIG11Y2ggbG93ZXIgdGhhbiBDUFUgY2xvY2sgZnJlcXVl bmN5LHN1Y2ggYXM6DQpDUFUgNzAwTUh6IC0gNDY1LjMwIEJvZ29taXBzLCBDUFUgODAwTUhaIC0g NTMyLjQ4IEJvZ29NSVBTLkFuZCBpIGZpbmQgb3V0IHRoYXQgQ1BVIEJvZ29taXBzIGlzIGEgZml4 ZWQgdmFsdWUgcmVnYXJkbGVzcyBMMiBjYWNoZSBvcGVuIG9yIGNsb3NlZCwNCg0KRW5jbG9zZWQg aXMgdGhlIGxvZyBmcm9tIHRoZSBjb25zb2xlDQoNClJlZ2FyZHMhDQogCQkJCQ0KDQqhoaGhoaGh oaGhoaGhoaGhbWFjcm9oYXQNCqGhoaGhoaGhoaGhoaGhoaFlbWJsaW51eEBtYWNyb2hhdC5jb20N CqGhoaGhoaGhoaGhoaGhoaGhoaGhMjAwNC0xMS0xMw0K From emblinux@macrohat.com Sat Nov 13 14:48:30 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 13 Nov 2004 14:48:35 +0000 (GMT) Received: from [IPv6:::ffff:218.30.103.173] ([IPv6:::ffff:218.30.103.173]:1292 "EHLO mxvip13.hichina.com") by linux-mips.org with ESMTP id ; Sat, 13 Nov 2004 14:48:30 +0000 Received: from 210.82.109.205 (HELO wanghonghui) (envelope-from emblinux@macrohat.com) by mxvip13.hichina.com (quarkmail-1.2.1) with ESMTP id S334225AbUKMOr7 for fxzhang@ict.ac.cn; Sat, 13 Nov 2004 22:47:59 +0800 Date: Sat, 13 Nov 2004 22:47:58 +0800 From: "macrohat" Reply-To: emblinux@macrohat.com To: "Fuxin Zhang" Cc: "linux-mips" Subject: Re: Re: X-mailer: Foxmail 5.0 beta1 [cn] Mime-Version: 1.0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: base64 Message-Id: <20041113144830Z8225203-1751+1494@linux-mips.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6318 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: emblinux@macrohat.com Precedence: bulk X-list: linux-mips Content-Length: 1586 Lines: 22 RGVhciBsaW51eC1taXBzOg0KDQpUaGFua3MhDQoNClNvLENvdWxkIEkgdGhpbmsgdGhhdCBCQ00x MjUwIGlzIG5vdCBhIHR5cGUgb2YgaGlnaCBwZXJmb3JtYW5jZSBDUFU/IGFzIGluIEFSTSBvciBQ b3dlciBQQyBBUkNIIHN5c3RlbSxCb2dvbWlwcyBpcyBhbG1vc3QgZXF1YWwgdG8gQ1BVIGNsb2Nr IGZyZXF1ZW5jeS5JcyB0aGVyZSBhbnkgd2F5IHRvIGlucHJvdmUgaXQgd2l0aCBzb2Z0d2FyZT8N CgkNCg0KUmVnYXJkcyENCg0KPT09PT09PSAyMDA0LTExLTEzIDIyOjAxOjAwIMT61NrAtNDF1tDQ tLXAo7o9PT09PT09DQoNCj4NCj4NCj5tYWNyb2hhdCB3cm90ZToNCj4NCj4+SGVsbG8gbGludXgt bWlwczoNCj4+DQo+PkkgaGF2ZSBhIHF1ZXN0aW9uIHRvIGFzayB5b3U6IHdoeSBCQ00xMjUwIENQ VSBCb2dvbWlwcyBpcyBzbyBtdWNoIGxvd2VyIHRoYW4gQ1BVIGNsb2NrIGZyZXF1ZW5jeSxzdWNo IGFzOg0KPj5DUFUgNzAwTUh6IC0gNDY1LjMwIEJvZ29taXBzLCBDUFUgODAwTUhaIC0gNTMyLjQ4 IEJvZ29NSVBTLkFuZCBpIGZpbmQgb3V0IHRoYXQgQ1BVIEJvZ29taXBzIGlzIGEgZml4ZWQgdmFs dWUgcmVnYXJkbGVzcyBMMiBjYWNoZSBvcGVuIG9yIGNsb3NlZCwNCj4+DQo+PiAgDQo+Pg0KPlRo aXMgaW5kaWNhdGVzIHRoZSBBTFUgb3BzIG9mIHRoYXQgQ1BVIGhhdmUgbW9yZSB0aGFuIG9uZSBj eWNsZSBsYXRlbmN5Lg0KPlRvIGFjaGlldmUgaGlnaGVyIGZyZXF1ZW5jeSwNCj50aGUgcGlwZWxp bmUgaXMgYmVjb21pbmcgbG9uZ2VyLi4uDQo+DQo+Qm9nb21pcHMgY2FsY3VsYXRpb24gaXMgYSBz aG9ydCBsb29wIHdoaWNoIGZpdHMgd2VsbCBpbiBMMSBjYWNoZXMsIHNvIEwyDQo+d29uJ3QgYWZm ZWN0IHRoZSBwZXJmb3JtYW5jZS4NCj4NCj4+RW5jbG9zZWQgaXMgdGhlIGxvZyBmcm9tIHRoZSBj b25zb2xlDQo+Pg0KPj5SZWdhcmRzIQ0KPj4gCQkJCQ0KPj4NCj4+oaGhoaGhoaGhoaGhoaGhoW1h Y3JvaGF0DQo+PqGhoaGhoaGhoaGhoaGhoaFlbWJsaW51eEBtYWNyb2hhdC5jb20NCj4+oaGhoaGh oaGhoaGhoaGhoaGhoaEyMDA0LTExLTEzDQo+PiAgDQo+Pg0KDQogDQoJCQkJIA0KoaGhoaGhoaGh oaGhoaGhoW1hY3JvaGF0DQqhoaGhoaGhoaGhoaGhoaGhZW1ibGludXhAbWFjcm9oYXQuY29tDQqh oaGhoaGhoaGhoaGhoaGhoaGhoTIwMDQtMTEtMTMNCg0K From fxzhang@ict.ac.cn Sun Nov 14 01:33:59 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 01:34:05 +0000 (GMT) Received: from [IPv6:::ffff:159.226.39.7] ([IPv6:::ffff:159.226.39.7]:39908 "HELO ict.ac.cn") by linux-mips.org with SMTP id ; Sun, 14 Nov 2004 01:33:59 +0000 Received: (qmail 20350 invoked by uid 507); 14 Nov 2004 01:03:53 -0000 Received: from unknown (HELO ict.ac.cn) (fxzhang@159.226.40.187) by ict.ac.cn with SMTP; 14 Nov 2004 01:03:53 -0000 Message-ID: <4196B593.40307@ict.ac.cn> Date: Sun, 14 Nov 2004 09:32:03 +0800 From: Fuxin Zhang User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.6) Gecko/20040122 X-Accept-Language: zh-cn, en-us MIME-Version: 1.0 To: emblinux@macrohat.com CC: linux-mips Subject: Re: Content-Type: text/plain; charset=GB2312 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6319 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fxzhang@ict.ac.cn Precedence: bulk X-list: linux-mips Content-Length: 1800 Lines: 80 macrohat wrote: >Dear linux-mips: > >Thanks! > >So,Could I think that BCM1250 is not a type of high performance CPU? as in ARM or Power PC ARCH system,Bogomips is almost equal to CPU clock > Intel P4 has 2X Bogomips than the frequency:) I think we could not conclude just by this: performance of a CPU is a complex topic, its architects may think ALU latency is not important enough for them to implement full bypass,instead put their energy on other issues.Nowadays, the memory hierarchy performance often dominates. Of course you can benmark it, for general purpose CPU, SPEC CPU2000 may be a good choice(www.spec.org) and there are numerous other free benchmarks too. >frequency.Is there any way to inprove it with software? > > The compiler may help a bit by scheduling instructions around. > > >Regards! > >======= 2004-11-13 22:01:00 ÄúÔÚÀ´ÐÅÖÐдµÀ£º======= > > > >>macrohat wrote: >> >> >> >>>Hello linux-mips: >>> >>>I have a question to ask you: why BCM1250 CPU Bogomips is so much lower than CPU clock frequency,such as: >>>CPU 700MHz - 465.30 Bogomips, CPU 800MHZ - 532.48 BogoMIPS.And i find out that CPU Bogomips is a fixed value regardless L2 cache open or closed, >>> >>> >>> >>> >>> >>This indicates the ALU ops of that CPU have more than one cycle latency. >>To achieve higher frequency, >>the pipeline is becoming longer... >> >>Bogomips calculation is a short loop which fits well in L1 caches, so L2 >>won't affect the performance. >> >> >> >>>Enclosed is the log from the console >>> >>>Regards! >>> >>> >>>¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡macrohat >>>¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡emblinux@macrohat.com >>>¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2004-11-13 >>> >>> >>> >>> > > > >¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡macrohat >¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡emblinux@macrohat.com >¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2004-11-13 > > > From kumba@gentoo.org Sun Nov 14 06:40:52 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 06:40:58 +0000 (GMT) Received: from sccrmhc11.comcast.net ([IPv6:::ffff:204.127.202.55]:60563 "EHLO sccrmhc11.comcast.net") by linux-mips.org with ESMTP id ; Sun, 14 Nov 2004 06:40:52 +0000 Received: from [192.168.1.4] (pcp05077810pcs.waldrf01.md.comcast.net[68.54.246.193]) by comcast.net (sccrmhc11) with ESMTP id <20041114064044011006rd02e>; Sun, 14 Nov 2004 06:40:45 +0000 Message-ID: <4196FE7C.9040309@gentoo.org> Date: Sun, 14 Nov 2004 01:43:08 -0500 From: Kumba User-Agent: Mozilla Thunderbird 0.9 (Windows/20041103) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org CC: Ralf Baechle Subject: [PATCH]: Rewrite of arch/mips/ramdisk/ Content-Type: multipart/mixed; boundary="------------000407090604080206050501" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6320 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips Content-Length: 3020 Lines: 86 This is a multi-part message in MIME format. --------------000407090604080206050501 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Attached is a patch for 2.6 that rewrites how embedded mips ramdisks are merged into the kernel. It basically replicates the method used by 2.6's initramfs (for linking in config.gz and such into the kernel, see the files in usr/ in the source tree). The upside of this is the resulting ramdisk.o file has all the correct ELF flags, which is needed for the few o64 targets used (IP32, IP22), and it gets built to the right ABI (avoiding the binutils error about mixing 32/64bit code). Tested on Indy R5K, O2 R5K and Cobalt RaQ2. --Kumba -- "Such is oft the course of deeds that move the wheels of the world: small hands do them because they must, while the eyes of the great are elsewhere." --Elrond --------------000407090604080206050501 Content-Type: text/plain; name="mips-new-way-of-doing-ramdisks.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="mips-new-way-of-doing-ramdisks.patch" diff -Naurp linux-2.6.10-rc1.mips.orig/arch/mips/ramdisk/Makefile linux-2.6.10-rc1.mips.mod/arch/mips/ramdisk/Makefile --- linux-2.6.10-rc1.mips.orig/arch/mips/ramdisk/Makefile 2004-06-08 16:41:55.000000000 -0400 +++ linux-2.6.10-rc1.mips.mod/arch/mips/ramdisk/Makefile 2004-11-13 17:16:59.124686128 -0500 @@ -2,19 +2,12 @@ # Makefile for a ramdisk image # +# Builds from ramdisk.S using .incbin obj-y += ramdisk.o - -O_FORMAT = $(shell $(OBJDUMP) -i | head -n 2 | grep elf32) +# Set the path accordingly img := $(subst ",,$(CONFIG_EMBEDDED_RAMDISK_IMAGE)) -# add $(src) when $(img) is relative img := $(subst $(src)//,/,$(src)/$(img)) -quiet_cmd_ramdisk = LD $@ -define cmd_ramdisk - $(LD) $(LDFLAGS) -T $(src)/ld.script -b binary --oformat $(O_FORMAT) -o $@ $(img) -endef - -$(obj)/ramdisk.o: $(img) $(src)/ld.script - $(call cmd,ramdisk) - +# Pass the filename to ${AS} +EXTRA_AFLAGS="-DMIPS_EMBEDDED_RAMDISK=\"$(img)\"" diff -Naurp linux-2.6.10-rc1.mips.orig/arch/mips/ramdisk/ld.script linux-2.6.10-rc1.mips.mod/arch/mips/ramdisk/ld.script --- linux-2.6.10-rc1.mips.orig/arch/mips/ramdisk/ld.script 2001-11-13 00:35:54.000000000 -0500 +++ linux-2.6.10-rc1.mips.mod/arch/mips/ramdisk/ld.script 1969-12-31 19:00:00.000000000 -0500 @@ -1,9 +0,0 @@ -OUTPUT_ARCH(mips) -SECTIONS -{ - .initrd : - { - *(.data) - } -} - diff -Naurp linux-2.6.10-rc1.mips.orig/arch/mips/ramdisk/ramdisk.S linux-2.6.10-rc1.mips.mod/arch/mips/ramdisk/ramdisk.S --- linux-2.6.10-rc1.mips.orig/arch/mips/ramdisk/ramdisk.S 1969-12-31 19:00:00.000000000 -0500 +++ linux-2.6.10-rc1.mips.mod/arch/mips/ramdisk/ramdisk.S 2004-11-13 17:17:59.825458208 -0500 @@ -0,0 +1,9 @@ +/* + * For a detailed explanation of this file and the + * commands, see usr/initramfs_data.S in the root + * of this source tree. + */ + +.section .initrd,"a" +.incbin MIPS_EMBEDDED_RAMDISK + --------------000407090604080206050501-- From kumba@gentoo.org Sun Nov 14 06:41:21 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 06:41:31 +0000 (GMT) Received: from sccrmhc11.comcast.net ([IPv6:::ffff:204.127.202.55]:60563 "EHLO sccrmhc11.comcast.net") by linux-mips.org with ESMTP id ; Sun, 14 Nov 2004 06:40:53 +0000 Received: from [192.168.1.4] (pcp05077810pcs.waldrf01.md.comcast.net[68.54.246.193]) by comcast.net (sccrmhc11) with ESMTP id <20041114064052011006s5lme>; Sun, 14 Nov 2004 06:40:52 +0000 Message-ID: <4196FE87.5050606@gentoo.org> Date: Sun, 14 Nov 2004 01:43:19 -0500 From: Kumba User-Agent: Mozilla Thunderbird 0.9 (Windows/20041103) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org CC: Ralf Baechle Subject: [PATCH]: R52x0 -> RM52xx Content-Type: multipart/mixed; boundary="------------060204080708080103040305" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6321 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips Content-Length: 1283 Lines: 42 This is a multi-part message in MIME format. --------------060204080708080103040305 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Attached is a minor cosmetic patch for 2.6 that just changes menuconfig to show the RM52xx CPU by the name it's known by on Systems that use it (Cobalt (RM5231), O2 RM5200). It's a really minor thing, but afaict, it doesn't look to be incorrect. --Kumba -- "Such is oft the course of deeds that move the wheels of the world: small hands do them because they must, while the eyes of the great are elsewhere." --Elrond --------------060204080708080103040305 Content-Type: text/plain; name="misc-2.6-kconfig-tweak" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="misc-2.6-kconfig-tweak" --- arch/mips/Kconfig.orig 2004-11-13 19:55:05.647515448 -0500 +++ arch/mips/Kconfig 2004-11-13 19:55:50.313725152 -0500 @@ -1183,9 +1183,9 @@ config CPU_R6000 processors are extremly rare and the support for them is incomplete. config CPU_NEVADA - bool "R52xx" + bool "RM52xx" help - MIPS Technologies R52x0-series ("Nevada") processors. + MIPS Technologies RM52xx-series ("Nevada") processors. config CPU_R8000 bool "R8000" --------------060204080708080103040305-- From gilad@romat.com Sun Nov 14 08:34:42 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 08:34:47 +0000 (GMT) Received: from support.romat.com ([IPv6:::ffff:212.143.245.3]:24836 "EHLO mail.romat.com") by linux-mips.org with ESMTP id ; Sun, 14 Nov 2004 08:34:42 +0000 Received: from localhost (localhost.lan [127.0.0.1]) by mail.romat.com (Postfix) with ESMTP id 03482EB2CA; Sun, 14 Nov 2004 10:34:35 +0200 (IST) Received: from mail.romat.com ([127.0.0.1]) by localhost (mail.romat.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 36569-08; Sun, 14 Nov 2004 10:34:31 +0200 (IST) Received: from gilad (unknown [192.168.1.167]) by mail.romat.com (Postfix) with SMTP id 75FDBEB2A9; Sun, 14 Nov 2004 10:34:31 +0200 (IST) Message-ID: <09ac01c4ca24$e68a6740$a701a8c0@lan> From: "Gilad Rom" To: , References: <20041112181335.13362.qmail@web81008.mail.yahoo.com> Subject: Re: GPIO on the Au1500 Date: Sun, 14 Nov 2004 10:35:30 +0200 Organization: Romat Telecom MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2900.2180 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-Virus-Scanned: by amavisd-new at romat.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6322 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gilad@romat.com Precedence: bulk X-list: linux-mips Content-Length: 772 Lines: 36 Thanks. Can't I just mmap /dev/mem and use the GPIO offset from SYS_BASE? Gilad. ----- Original Message ----- From: "Pete Popov" To: "Gilad Rom" ; Sent: Friday, November 12, 2004 8:13 PM Subject: Re: GPIO on the Au1500 > > --- Gilad Rom wrote: > >> Hello, >> >> I am trying to use the au1000_gpio driver, but I'm a >> little clueless as to how it is meant to be used. >> Can I use the GPIO ioctl's from a userland >> program, or must I write a kernel module? > > I'll see if I can dig up some docs and the example > userland program this weekend. That driver hasn't been > tested in a while though. > > Pete > >> Thank you, >> Gilad Rom >> Romat Telecom >> >> >> > From hch@lst.de Sun Nov 14 08:52:05 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 08:52:19 +0000 (GMT) Received: from verein.lst.de ([IPv6:::ffff:213.95.11.210]:53426 "EHLO mail.lst.de") by linux-mips.org with ESMTP id ; Sun, 14 Nov 2004 08:52:05 +0000 Received: from verein.lst.de (localhost [127.0.0.1]) by mail.lst.de (8.12.3/8.12.3/Debian-6.6) with ESMTP id iAE8q2la030500 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Sun, 14 Nov 2004 09:52:02 +0100 Received: (from hch@localhost) by verein.lst.de (8.12.3/8.12.3/Debian-6.6) id iAE8q2pa030498; Sun, 14 Nov 2004 09:52:02 +0100 Date: Sun, 14 Nov 2004 09:52:02 +0100 From: Christoph Hellwig To: Kumba Cc: linux-mips@linux-mips.org, Ralf Baechle Subject: Re: [PATCH]: Rewrite of arch/mips/ramdisk/ Message-ID: <20041114085202.GA30480@lst.de> References: <4196FE7C.9040309@gentoo.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4196FE7C.9040309@gentoo.org> User-Agent: Mutt/1.3.28i X-Spam-Score: -4.901 () BAYES_00 X-Scanned-By: MIMEDefang 2.39 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6323 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hch@lst.de Precedence: bulk X-list: linux-mips Content-Length: 435 Lines: 8 On Sun, Nov 14, 2004 at 01:43:08AM -0500, Kumba wrote: > Attached is a patch for 2.6 that rewrites how embedded mips ramdisks are > merged into the kernel. It basically replicates the method used by 2.6's > initramfs (for linking in config.gz and such into the kernel, see the files > in usr/ in the source tree). So why do you keep it instead of using initramfs as you should - which is the portable method useable on all ports. From emblinux@macrohat.com Sun Nov 14 13:15:40 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 13:15:47 +0000 (GMT) Received: from [IPv6:::ffff:218.30.103.173] ([IPv6:::ffff:218.30.103.173]:11788 "EHLO mxvip13.hichina.com") by linux-mips.org with ESMTP id ; Sun, 14 Nov 2004 13:15:40 +0000 Received: from 210.82.109.205 (HELO wanghonghui) (envelope-from emblinux@macrohat.com) by mxvip13.hichina.com (quarkmail-1.2.1) with ESMTP id S334332AbUKNNPE for fxzhang@ict.ac.cn; Sun, 14 Nov 2004 21:15:04 +0800 Date: Sun, 14 Nov 2004 21:15:02 +0800 From: "macrohat" Reply-To: emblinux@macrohat.com To: "Fuxin Zhang" Cc: "linux-cvs" , "linux-mips" Subject: X-mailer: Foxmail 5.0 beta1 [cn] Mime-Version: 1.0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: base64 Message-Id: <20041114131540Z8225234-1751+1559@linux-mips.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6324 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: emblinux@macrohat.com Precedence: bulk X-list: linux-mips Content-Length: 1647 Lines: 23 RGVhciBGdXhpbiBaaGFuZzoNCg0KVGhpbmtzIGZvciB5b3VyIGhlbHAhDQoNCk5vdyBpIGhhdmUg YW5vdGhlciBxdWVzdGlvbiwgSSB1c2UgbWlwcy1saW51eC1nY2Mgd2hpY2ggaXMgcG9ydGVkIGZy b20gZ2NjLTMuMi4zIGJ5IEJyb2FkY29tIHRvIGNvbXBpbGUgbGludXgga2VybmVsLHdoZW4gSSB1 c2UgIi1PMiIgb3IgIi1PcyIgb3B0aW9uLCBpdCBjYW4gY29tcGxldGUgc3VjY2Vzc2Z1bGx5LCBi dXQgaWYgaSB1c2UgIi1PMyIgb3B0aW9uLCBpdCBjYW4gbm90IGNvbXBsZXRlLkVuY2xvc2VkIGlz IHRoZSBlcnIgbG9nIGFuZCBzb3VjZSBjb2RlLg0KQW55IGhlbHAgd291bGQgYmUgcmVhbGx5IGFw cHJlY2lhdGVkLg0KDQplcnIgbG9nOg0KDQphcmNoL21pcHM2NC9tbS9tbS5vOiBJbiBmdW5jdGlv biBgc2IxX19fZmx1c2hfY2FjaGVfYWxsJzoNCmFyY2gvbWlwczY0L21tL21tLm8oLnRleHQrMHgx OTMwKTogdW5kZWZpbmVkIHJlZmVyZW5jZSB0byBgbG9jYWxfc2IxX19fZmx1c2hfY2FjDQpoZV9h bGwnDQphcmNoL21pcHM2NC9tbS9tbS5vKC50ZXh0KzB4MTkzNCk6IHVuZGVmaW5lZCByZWZlcmVu Y2UgdG8gYGxvY2FsX3NiMV9fX2ZsdXNoX2NhYw0KaGVfYWxsJw0KbWFrZTogKioqIFt2bWxpbnV4 XSBFcnJvciAxDQoNCnNvdXJjZSBjb2RlOg0KDQpzdGF0aWMgdm9pZCBsb2NhbF9zYjFfX19mbHVz aF9jYWNoZV9hbGwodm9pZCkNCnsNCglUUkFDRV9SRUNPUkQoVFJDX0NBQ0hFT1BfQkFTRSs1LCAw LCAwLA0KCQkgICAgIHJlYWRfYzBfY291bnQoKSk7DQoNCglfX3NiMV93cml0ZWJhY2tfaW52X2Rj YWNoZV9hbGwoKTsNCglfX3NiMV9mbHVzaF9pY2FjaGVfYWxsKCk7DQp9DQoNCmV4dGVybiB2b2lk IHNiMV9fX2ZsdXNoX2NhY2hlX2FsbF9pcGkodm9pZCAqaWdub3JlZCk7DQphc20oInNiMV9fX2Zs dXNoX2NhY2hlX2FsbF9pcGkgPSBsb2NhbF9zYjFfX19mbHVzaF9jYWNoZV9hbGwiKTsNCg0Kc3Rh dGljIHZvaWQgc2IxX19fZmx1c2hfY2FjaGVfYWxsKHZvaWQpDQp7DQoJc21wX2NhbGxfZnVuY3Rp b24oc2IxX19fZmx1c2hfY2FjaGVfYWxsX2lwaSwgMCwgMSwgMSk7DQoJbG9jYWxfc2IxX19fZmx1 c2hfY2FjaGVfYWxsKCk7DQp9DQoNCgkNClJlZ2FyZHMhDQoNCqGhoaGhoaGhoaGhoaGhoaFtYWNy b2hhdA0KoaGhoaGhoaGhoaGhoaGhoWVtYmxpbnV4QG1hY3JvaGF0LmNvbQ0KoaGhoaGhoaGhoaGh oaGhoaGhoaEyMDA0LTExLTE0DQo= From gilad@romat.com Sun Nov 14 15:53:09 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 15:53:13 +0000 (GMT) Received: from mail.romat.com ([IPv6:::ffff:212.143.245.3]:47877 "EHLO mail.romat.com") by linux-mips.org with ESMTP id ; Sun, 14 Nov 2004 15:53:09 +0000 Received: from localhost (localhost.lan [127.0.0.1]) by mail.romat.com (Postfix) with ESMTP id D3E8CEB2EF for ; Sun, 14 Nov 2004 17:53:01 +0200 (IST) Received: from mail.romat.com ([127.0.0.1]) by localhost (mail.romat.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 40319-01 for ; Sun, 14 Nov 2004 17:52:54 +0200 (IST) Received: from gilad (unknown [192.168.1.167]) by mail.romat.com (Postfix) with SMTP id 6F55AEB2A9 for ; Sun, 14 Nov 2004 17:52:48 +0200 (IST) Message-ID: <0a2201c4ca62$25d37f80$a701a8c0@lan> From: "Gilad Rom" To: References: <20041112181335.13362.qmail@web81008.mail.yahoo.com> <09ac01c4ca24$e68a6740$a701a8c0@lan> Subject: Re: GPIO on the Au1500 Date: Sun, 14 Nov 2004 17:53:49 +0200 Organization: Romat Telecom MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=response Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2900.2180 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-Virus-Scanned: by amavisd-new at romat.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6325 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gilad@romat.com Precedence: bulk X-list: linux-mips Content-Length: 2307 Lines: 104 Replying to myself - I've composed a small program which mmap()'s SYS_BASE and then tries to read at the appropriate GPIO offset, as defined in the Au1500 databook. For some reason, I keep getting that magical value, 0x10000001 for EVERY address I try to read, be it SYS_BASE (0xB1900000) or every other address. (for example, I've tried reading the MAC address from the MAC0 base address of 0xB1500000, offset 0x0008, and I always get 0x10000001). Any reason I shouldn't succeed in reading the au1500 hardware addresses through /dev/mem? Attached is the code I'm using: #include #include #include #include #include #define SYS_BASE 0xB1900000 int main () { volatile unsigned long *base; unsigned char val; int f, i; f = open ("/dev/mem", O_RDWR | O_SYNC); if (f < 0) { perror ("fopen"); exit (-1); } base = (unsigned long *) mmap (NULL, getpagesize (), PROT_READ | PROT_WRITE, MAP_SHARED, f, SYS_BASE); if (base == (unsigned long *) (-1)) { perror ("mmap"); exit (-1); } printf ("data at %p: 0x%x\n", base, (unsigned long) *base); *base = 0xffffffff; printf ("data at %p: 0x%x\n", base, (unsigned long) *base); close (f); return (0); } Thanks! Gilad. ----- Original Message ----- From: "Gilad Rom" To: ; Sent: Sunday, November 14, 2004 10:35 AM Subject: Re: GPIO on the Au1500 > Thanks. > Can't I just mmap /dev/mem and use the > GPIO offset from SYS_BASE? > > Gilad. > > ----- Original Message ----- > From: "Pete Popov" > To: "Gilad Rom" ; > Sent: Friday, November 12, 2004 8:13 PM > Subject: Re: GPIO on the Au1500 > > >> >> --- Gilad Rom wrote: >> >>> Hello, >>> >>> I am trying to use the au1000_gpio driver, but I'm a >>> little clueless as to how it is meant to be used. >>> Can I use the GPIO ioctl's from a userland >>> program, or must I write a kernel module? >> >> I'll see if I can dig up some docs and the example >> userland program this weekend. That driver hasn't been >> tested in a while though. >> >> Pete >> >>> Thank you, >>> Gilad Rom >>> Romat Telecom >>> >>> >>> >> > From charles.eidsness@ieee.org Sun Nov 14 17:09:08 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 17:09:13 +0000 (GMT) Received: from smtp103.rog.mail.re2.yahoo.com ([IPv6:::ffff:206.190.36.81]:57754 "HELO smtp103.rog.mail.re2.yahoo.com") by linux-mips.org with SMTP id ; Sun, 14 Nov 2004 17:09:08 +0000 Received: from unknown (HELO ?192.168.1.100?) (charles.eidsness@rogers.com@24.157.59.167 with plain) by smtp103.rog.mail.re2.yahoo.com with SMTP; 14 Nov 2004 17:09:01 -0000 Message-ID: <41979129.1050200@ieee.org> Date: Sun, 14 Nov 2004 12:08:57 -0500 From: Charles Eidsness Reply-To: charles.eidsness@ieee.org User-Agent: Mozilla Thunderbird 0.8 (Windows/20040913) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Gilad Rom CC: linux-mips@linux-mips.org Subject: Re: GPIO on the Au1500 References: <20041112181335.13362.qmail@web81008.mail.yahoo.com> <09ac01c4ca24$e68a6740$a701a8c0@lan> In-Reply-To: <09ac01c4ca24$e68a6740$a701a8c0@lan> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6326 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: charles.eidsness@ieee.org Precedence: bulk X-list: linux-mips Content-Length: 1270 Lines: 52 Hi Gilad, A little while ago I wrote my own GPIO driver for the Au1000, mainly as a learning experience. I never bothered to release it because a driver already exists and I thought it was working. I'm not sure if it will work on the Au1550, but if you're interested you can find the source code here: http://members.rogers.com/charles.eidsness/au1000_gpio.c http://members.rogers.com/charles.eidsness/au1000_gpio.h Cheers, Charles Gilad Rom wrote: > Thanks. Can't I just mmap /dev/mem and use the > GPIO offset from SYS_BASE? > > Gilad. > > ----- Original Message ----- From: "Pete Popov" > To: "Gilad Rom" ; > Sent: Friday, November 12, 2004 8:13 PM > Subject: Re: GPIO on the Au1500 > > >> >> --- Gilad Rom wrote: >> >>> Hello, >>> >>> I am trying to use the au1000_gpio driver, but I'm a >>> little clueless as to how it is meant to be used. Can I use the GPIO >>> ioctl's from a userland program, or must I write a kernel module? >> >> >> I'll see if I can dig up some docs and the example >> userland program this weekend. That driver hasn't been >> tested in a while though. >> >> Pete >> >>> Thank you, >>> Gilad Rom >>> Romat Telecom >>> >>> >>> >> > > > From kumba@gentoo.org Sun Nov 14 17:22:57 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 17:23:02 +0000 (GMT) Received: from rwcrmhc12.comcast.net ([IPv6:::ffff:216.148.227.85]:38301 "EHLO rwcrmhc12.comcast.net") by linux-mips.org with ESMTP id ; Sun, 14 Nov 2004 17:22:57 +0000 Received: from [192.168.1.4] (pcp05077810pcs.waldrf01.md.comcast.net[68.54.246.193]) by comcast.net (rwcrmhc12) with ESMTP id <2004111417224801400pkanhe> (Authid: kumba12345); Sun, 14 Nov 2004 17:22:48 +0000 Message-ID: <419794FB.6020104@gentoo.org> Date: Sun, 14 Nov 2004 12:25:15 -0500 From: Kumba User-Agent: Mozilla Thunderbird 0.9 (Windows/20041103) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH]: Rewrite of arch/mips/ramdisk/ References: <4196FE7C.9040309@gentoo.org> <20041114085202.GA30480@lst.de> In-Reply-To: <20041114085202.GA30480@lst.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6327 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips Content-Length: 1075 Lines: 25 Christoph Hellwig wrote: > > So why do you keep it instead of using initramfs as you should - which > is the portable method useable on all ports. Not sure I'm following what you're asking/referring to. This is for an embedded filesystem initrd, like for a small busybox-based initrd, useful for netboot images and the like. From looking at the initramfs stuff in usr/, that looks to be specific for linking config.gz into the kernel, and not configurable to link in a filesystem-based initrd. I basically mimiced the method in usr/ for arch/mips/ramdisk/. If there's some more global mechanism for utilizing this and tying in an initrd, then I didn't see it. The current code in arch/mips/ramdisk/ is virtually the same as the stuff in arch/sh/ramdisk/, so it doesn't look like any kind of code sharing is going on between the various ports that have an optional embedded ramdisk. --Kumba -- "Such is oft the course of deeds that move the wheels of the world: small hands do them because they must, while the eyes of the great are elsewhere." --Elrond From ppopov@embeddedalley.com Sun Nov 14 18:45:10 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 18:45:17 +0000 (GMT) Received: from web81007.mail.yahoo.com ([IPv6:::ffff:206.190.37.152]:59520 "HELO web81007.mail.yahoo.com") by linux-mips.org with SMTP id ; Sun, 14 Nov 2004 18:45:09 +0000 Message-ID: <20041114184502.41815.qmail@web81007.mail.yahoo.com> Received: from [63.194.214.47] by web81007.mail.yahoo.com via HTTP; Sun, 14 Nov 2004 10:45:02 PST X-RocketYMMF: pvpopov@pacbell.net Date: Sun, 14 Nov 2004 10:45:02 -0800 (PST) From: Pete Popov Reply-To: ppopov@embeddedalley.com Subject: Re: GPIO on the Au1500 To: charles.eidsness@ieee.org, Gilad Rom Cc: linux-mips@linux-mips.org In-Reply-To: <41979129.1050200@ieee.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6328 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ppopov@embeddedalley.com Precedence: bulk X-list: linux-mips Content-Length: 1691 Lines: 80 --- Charles Eidsness wrote: > Hi Gilad, > > A little while ago I wrote my own GPIO driver for > the Au1000, mainly as a learning experience. I > never bothered to release it because a driver > already exists and I thought it was working. It was, a long time ago, when it was written for the Au1000. I had a user app and doc somewhere but can't find it anymore. The driver didn't support gpio2 and was, in general, stale. So perhaps your driver will help Gilad. Pete > I'm not sure if it will > work on the Au1550, but if you're interested you can > find the source > code here: > > http://members.rogers.com/charles.eidsness/au1000_gpio.c > http://members.rogers.com/charles.eidsness/au1000_gpio.h > > Cheers, > Charles > > Gilad Rom wrote: > > Thanks. Can't I just mmap /dev/mem and use the > > GPIO offset from SYS_BASE? > > > > Gilad. > > > > ----- Original Message ----- From: "Pete Popov" > > > To: "Gilad Rom" ; > > > Sent: Friday, November 12, 2004 8:13 PM > > Subject: Re: GPIO on the Au1500 > > > > > >> > >> --- Gilad Rom wrote: > >> > >>> Hello, > >>> > >>> I am trying to use the au1000_gpio driver, but > I'm a > >>> little clueless as to how it is meant to be > used. Can I use the GPIO > >>> ioctl's from a userland program, or must I write > a kernel module? > >> > >> > >> I'll see if I can dig up some docs and the > example > >> userland program this weekend. That driver hasn't > been > >> tested in a while though. > >> > >> Pete > >> > >>> Thank you, > >>> Gilad Rom > >>> Romat Telecom > >>> > >>> > >>> > >> > > > > > > > > From kumba@gentoo.org Sun Nov 14 19:28:57 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 19:29:01 +0000 (GMT) Received: from rwcrmhc12.comcast.net ([IPv6:::ffff:216.148.227.85]:43225 "EHLO rwcrmhc12.comcast.net") by linux-mips.org with ESMTP id ; Sun, 14 Nov 2004 19:28:57 +0000 Received: from [192.168.1.4] (pcp05077810pcs.waldrf01.md.comcast.net[68.54.246.193]) by comcast.net (rwcrmhc12) with ESMTP id <2004111419285001400pr59re> (Authid: kumba12345); Sun, 14 Nov 2004 19:28:50 +0000 Message-ID: <4197B286.4060503@gentoo.org> Date: Sun, 14 Nov 2004 14:31:18 -0500 From: Kumba User-Agent: Mozilla Thunderbird 0.9 (Windows/20041103) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH]: Rewrite of arch/mips/ramdisk/ References: <4196FE7C.9040309@gentoo.org> <20041114085202.GA30480@lst.de> <419794FB.6020104@gentoo.org> In-Reply-To: <419794FB.6020104@gentoo.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6329 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips Content-Length: 1536 Lines: 32 Kumba wrote: > > Not sure I'm following what you're asking/referring to. This is for an > embedded filesystem initrd, like for a small busybox-based initrd, > useful for netboot images and the like. From looking at the initramfs > stuff in usr/, that looks to be specific for linking config.gz into the > kernel, and not configurable to link in a filesystem-based initrd. > > I basically mimiced the method in usr/ for arch/mips/ramdisk/. If > there's some more global mechanism for utilizing this and tying in an > initrd, then I didn't see it. The current code in arch/mips/ramdisk/ is > virtually the same as the stuff in arch/sh/ramdisk/, so it doesn't look > like any kind of code sharing is going on between the various ports that > have an optional embedded ramdisk. Ahh, I see. Ralf pointed me at CONFIG_INITRAMFS_SOURCE in 2.6.10. My patch was based on 2.6.9, and I didn't exactly think this specific bit of the kernel would change between 2.6.9 and 2.6.10. Go figure. It looks like this option, which afaict, doesn't seem to have an entry anywhere in Kconfig, specifies a list of files for inclusion in a cpio archive that's bundled into the kernel. My question then is, can a lookback-mountable filesystem image be included in this list, and the kernel, given /dev/ram0 as root, know to mount and use the loopback image? --Kumba -- "Such is oft the course of deeds that move the wheels of the world: small hands do them because they must, while the eyes of the great are elsewhere." --Elrond From hvr@inso.tuwien.ac.at Sun Nov 14 20:15:16 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Nov 2004 20:15:23 +0000 (GMT) Received: from dhcp-1263-9.blizz.at ([IPv6:::ffff:213.143.126.4]:1767 "EHLO cervus.intra") by linux-mips.org with ESMTP id ; Sun, 14 Nov 2004 20:15:16 +0000 Received: from xterm.intra ([10.49.1.10]) by cervus.intra with esmtp (Exim 4.34) id 1CTQmF-0006zs-0P; Sun, 14 Nov 2004 21:15:11 +0100 Subject: [PATCH] fix for big-endian bug in arch/mips/pci/ops-au1000.c From: Herbert Valerio Riedel To: Pete Popov Cc: linux-mips@linux-mips.org Content-Type: text/plain Organization: Research Group for Industrial Software @ Vienna University of Technology Date: Sun, 14 Nov 2004 21:03:13 +0100 Message-Id: <1100462594.3329.5.camel@xterm.intra> Mime-Version: 1.0 X-Mailer: Evolution 2.0.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6330 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hvr@inso.tuwien.ac.at Precedence: bulk X-list: linux-mips Content-Length: 1179 Lines: 38 well, w/ the following modification, the code becomes endian-independent... :-) diff -u -r1.11 ops-au1000.c --- arch/mips/pci/ops-au1000.c 6 Jun 2004 02:12:38 -0000 1.11 +++ arch/mips/pci/ops-au1000.c 14 Nov 2004 19:59:23 -0000 @@ -288,10 +288,18 @@ int where, int size, u32 * val) { switch (size) { - case 1: - return read_config_byte(bus, devfn, where, (u8 *) val); - case 2: - return read_config_word(bus, devfn, where, (u16 *) val); + case 1: { + u8 _val; + int rc = read_config_byte(bus, devfn, where, &_val); + *val = _val; + return rc; + } + case 2: { + u16 _val; + int rc = read_config_word(bus, devfn, where, &_val); + *val = _val; + return rc; + } default: return read_config_dword(bus, devfn, where, val); } -- Herbert Valerio Riedel Research Group for Industrial Software @ Vienna University of Technology From gilad@romat.com Mon Nov 15 07:43:35 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2004 07:43:40 +0000 (GMT) Received: from support.romat.com ([IPv6:::ffff:212.143.245.3]:13072 "EHLO mail.romat.com") by linux-mips.org with ESMTP id ; Mon, 15 Nov 2004 07:43:35 +0000 Received: from localhost (localhost.lan [127.0.0.1]) by mail.romat.com (Postfix) with ESMTP id 36D69EB2EF for ; Mon, 15 Nov 2004 09:43:28 +0200 (IST) Received: from mail.romat.com ([127.0.0.1]) by localhost (mail.romat.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 44580-07 for ; Mon, 15 Nov 2004 09:43:24 +0200 (IST) Received: from gilad (unknown [192.168.1.167]) by mail.romat.com (Postfix) with SMTP id B4F6FEB2B6 for ; Mon, 15 Nov 2004 09:43:24 +0200 (IST) Message-ID: <0a9001c4cae6$f1aa3890$a701a8c0@lan> From: "Gilad Rom" To: References: <20041114184502.41815.qmail@web81007.mail.yahoo.com> Subject: Re: GPIO on the Au1500 Date: Mon, 15 Nov 2004 09:44:31 +0200 Organization: Romat Telecom MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2900.2180 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-Virus-Scanned: by amavisd-new at romat.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6331 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gilad@romat.com Precedence: bulk X-list: linux-mips Content-Length: 2329 Lines: 102 Thank you for the driver, I'm using it as a reference. Still, I am trying to acccess the GPIO ports of the Au1500 using /dev/mem, but I keep getting these odd values (see previous messages to this list) Do you think it is possible, or should I stick to using the driver? Thank you, Gilad. ----- Original Message ----- From: "Pete Popov" To: ; "Gilad Rom" Cc: Sent: Sunday, November 14, 2004 8:45 PM Subject: Re: GPIO on the Au1500 > > --- Charles Eidsness > wrote: > >> Hi Gilad, >> >> A little while ago I wrote my own GPIO driver for >> the Au1000, mainly as a learning experience. I >> never bothered to release it because a driver >> already exists and I thought it was working. > > It was, a long time ago, when it was written for the > Au1000. I had a user app and doc somewhere but can't > find it anymore. The driver didn't support gpio2 and > was, in general, stale. So perhaps your driver will > help Gilad. > > Pete > >> I'm not sure if it will >> work on the Au1550, but if you're interested you can >> find the source >> code here: >> >> > http://members.rogers.com/charles.eidsness/au1000_gpio.c >> > http://members.rogers.com/charles.eidsness/au1000_gpio.h >> >> Cheers, >> Charles >> >> Gilad Rom wrote: >> > Thanks. Can't I just mmap /dev/mem and use the >> > GPIO offset from SYS_BASE? >> > >> > Gilad. >> > >> > ----- Original Message ----- From: "Pete Popov" >> >> > To: "Gilad Rom" ; >> >> > Sent: Friday, November 12, 2004 8:13 PM >> > Subject: Re: GPIO on the Au1500 >> > >> > >> >> >> >> --- Gilad Rom wrote: >> >> >> >>> Hello, >> >>> >> >>> I am trying to use the au1000_gpio driver, but >> I'm a >> >>> little clueless as to how it is meant to be >> used. Can I use the GPIO >> >>> ioctl's from a userland program, or must I write >> a kernel module? >> >> >> >> >> >> I'll see if I can dig up some docs and the >> example >> >> userland program this weekend. That driver hasn't >> been >> >> tested in a while though. >> >> >> >> Pete >> >> >> >>> Thank you, >> >>> Gilad Rom >> >>> Romat Telecom >> >>> >> >>> >> >>> >> >> >> > >> > >> > >> >> > > From charles.eidsness@ieee.org Mon Nov 15 16:17:56 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2004 16:18:04 +0000 (GMT) Received: from smtp102.rog.mail.re2.yahoo.com ([IPv6:::ffff:206.190.36.80]:45448 "HELO smtp102.rog.mail.re2.yahoo.com") by linux-mips.org with SMTP id ; Mon, 15 Nov 2004 16:17:56 +0000 Received: from unknown (HELO ?192.168.1.100?) (charles.eidsness@rogers.com@24.157.59.167 with plain) by smtp102.rog.mail.re2.yahoo.com with SMTP; 15 Nov 2004 16:17:48 -0000 Message-ID: <4198D6AB.2060005@ieee.org> Date: Mon, 15 Nov 2004 11:17:47 -0500 From: Charles Eidsness Reply-To: charles.eidsness@ieee.org User-Agent: Mozilla Thunderbird 0.8 (Windows/20040913) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Gilad Rom CC: linux-mips@linux-mips.org Subject: Re: GPIO on the Au1500 References: <20041114184502.41815.qmail@web81007.mail.yahoo.com> <0a9001c4cae6$f1aa3890$a701a8c0@lan> In-Reply-To: <0a9001c4cae6$f1aa3890$a701a8c0@lan> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6332 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: charles.eidsness@ieee.org Precedence: bulk X-list: linux-mips Content-Length: 2898 Lines: 112 Hi Gilad, I'd be really surprised if it's possible. I think that those addresses are beyond the valid physical address range for the mem driver. Even if it did work I personally wouldn't feel comfortable doing that sort of thing. You could inadvertently cause a lot of nasty things to happen. Maybe someone else has a different (better) opinion. If you do use my driver I uploaded the wrong header file yesterday. I've now uploaded the correct one. Cheers, Charles Gilad Rom wrote: > Thank you for the driver, I'm using it as a reference. > > Still, I am trying to acccess the GPIO ports of the Au1500 > using /dev/mem, but I keep getting these odd values > (see previous messages to this list) > > Do you think it is possible, or should I stick to using the driver? > > > Thank you, > Gilad. > > ----- Original Message ----- From: "Pete Popov" > To: ; "Gilad Rom" > Cc: > Sent: Sunday, November 14, 2004 8:45 PM > Subject: Re: GPIO on the Au1500 > > >> >> --- Charles Eidsness >> wrote: >> >>> Hi Gilad, >>> >>> A little while ago I wrote my own GPIO driver for >>> the Au1000, mainly as a learning experience. I never bothered to >>> release it because a driver already exists and I thought it was working. >> >> >> It was, a long time ago, when it was written for the >> Au1000. I had a user app and doc somewhere but can't >> find it anymore. The driver didn't support gpio2 and >> was, in general, stale. So perhaps your driver will >> help Gilad. >> >> Pete >> >>> I'm not sure if it will work on the Au1550, but if you're interested >>> you can >>> find the source code here: >>> >>> >> http://members.rogers.com/charles.eidsness/au1000_gpio.c >> >>> >> http://members.rogers.com/charles.eidsness/au1000_gpio.h >> >>> >>> Cheers, >>> Charles >>> >>> Gilad Rom wrote: >>> > Thanks. Can't I just mmap /dev/mem and use the >>> > GPIO offset from SYS_BASE? >>> > > Gilad. >>> > > ----- Original Message ----- From: "Pete Popov" >>> >>> > To: "Gilad Rom" ; >>> >>> > Sent: Friday, November 12, 2004 8:13 PM >>> > Subject: Re: GPIO on the Au1500 >>> > > >> >>> >> --- Gilad Rom wrote: >>> >> >>> >>> Hello, >>> >>> >>> >>> I am trying to use the au1000_gpio driver, but >>> I'm a >>> >>> little clueless as to how it is meant to be >>> used. Can I use the GPIO >>> ioctl's from a userland program, or must >>> I write >>> a kernel module? >>> >> >>> >> >>> >> I'll see if I can dig up some docs and the >>> example >>> >> userland program this weekend. That driver hasn't >>> been >>> >> tested in a while though. >>> >> >>> >> Pete >>> >> >>> >>> Thank you, >>> >>> Gilad Rom >>> >>> Romat Telecom >>> >>> >>> >>> >>> >>> >>> >> >>> > > > >>> >> >> > > > From gilad@romat.com Mon Nov 15 16:38:49 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2004 16:38:57 +0000 (GMT) Received: from mail.romat.com ([IPv6:::ffff:212.143.245.3]:18692 "EHLO mail.romat.com") by linux-mips.org with ESMTP id ; Mon, 15 Nov 2004 16:38:49 +0000 Received: from localhost (localhost.lan [127.0.0.1]) by mail.romat.com (Postfix) with ESMTP id D2344EB2A9; Mon, 15 Nov 2004 18:38:41 +0200 (IST) Received: from mail.romat.com ([127.0.0.1]) by localhost (mail.romat.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 48957-06; Mon, 15 Nov 2004 18:38:38 +0200 (IST) Received: from gilad (unknown [192.168.1.167]) by mail.romat.com (Postfix) with SMTP id 0EA02EB2EE; Mon, 15 Nov 2004 18:38:38 +0200 (IST) Message-ID: <0b2001c4cb31$94b0b060$a701a8c0@lan> From: "Gilad Rom" To: Cc: References: <20041114184502.41815.qmail@web81007.mail.yahoo.com> <0a9001c4cae6$f1aa3890$a701a8c0@lan> <4198D6AB.2060005@ieee.org> Subject: Re: GPIO on the Au1500 Date: Mon, 15 Nov 2004 18:38:43 +0200 Organization: Romat Telecom MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=response Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2900.2180 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-Virus-Scanned: by amavisd-new at romat.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6333 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gilad@romat.com Precedence: bulk X-list: linux-mips Content-Length: 3488 Lines: 132 Thanks Charles. First of all, I managed to get it working today, (mmapping /dev/mem) so it is possible ;) Secondly, I am using the GPIO ports for our own custom design, so I am not exposing /dev/mem to all kinds of nasty userland apps. Gilad. ----- Original Message ----- From: "Charles Eidsness" To: "Gilad Rom" Cc: Sent: Monday, November 15, 2004 6:17 PM Subject: Re: GPIO on the Au1500 > Hi Gilad, > > I'd be really surprised if it's possible. I think that those addresses are > beyond the valid physical address range for the mem driver. Even if it did > work I personally wouldn't feel comfortable doing that sort of thing. You > could inadvertently cause a lot of nasty things to happen. Maybe someone > else has a different (better) opinion. > > If you do use my driver I uploaded the wrong header file yesterday. I've > now uploaded the correct one. > > Cheers, > Charles > > Gilad Rom wrote: >> Thank you for the driver, I'm using it as a reference. >> >> Still, I am trying to acccess the GPIO ports of the Au1500 >> using /dev/mem, but I keep getting these odd values >> (see previous messages to this list) >> >> Do you think it is possible, or should I stick to using the driver? >> >> >> Thank you, >> Gilad. >> >> ----- Original Message ----- From: "Pete Popov" >> >> To: ; "Gilad Rom" >> Cc: >> Sent: Sunday, November 14, 2004 8:45 PM >> Subject: Re: GPIO on the Au1500 >> >> >>> >>> --- Charles Eidsness >>> wrote: >>> >>>> Hi Gilad, >>>> >>>> A little while ago I wrote my own GPIO driver for >>>> the Au1000, mainly as a learning experience. I never bothered to >>>> release it because a driver already exists and I thought it was >>>> working. >>> >>> >>> It was, a long time ago, when it was written for the >>> Au1000. I had a user app and doc somewhere but can't >>> find it anymore. The driver didn't support gpio2 and >>> was, in general, stale. So perhaps your driver will >>> help Gilad. >>> >>> Pete >>> >>>> I'm not sure if it will work on the Au1550, but if you're interested >>>> you can >>>> find the source code here: >>>> >>>> >>> http://members.rogers.com/charles.eidsness/au1000_gpio.c >>> >>>> >>> http://members.rogers.com/charles.eidsness/au1000_gpio.h >>> >>>> >>>> Cheers, >>>> Charles >>>> >>>> Gilad Rom wrote: >>>> > Thanks. Can't I just mmap /dev/mem and use the >>>> > GPIO offset from SYS_BASE? >>>> > > Gilad. >>>> > > ----- Original Message ----- From: "Pete Popov" >>>> >>>> > To: "Gilad Rom" ; >>>> >>>> > Sent: Friday, November 12, 2004 8:13 PM >>>> > Subject: Re: GPIO on the Au1500 >>>> > > >> >>>> >> --- Gilad Rom wrote: >>>> >> >>>> >>> Hello, >>>> >>> >>>> >>> I am trying to use the au1000_gpio driver, but >>>> I'm a >>>> >>> little clueless as to how it is meant to be >>>> used. Can I use the GPIO >>> ioctl's from a userland program, or must I >>>> write >>>> a kernel module? >>>> >> >>>> >> >>>> >> I'll see if I can dig up some docs and the >>>> example >>>> >> userland program this weekend. That driver hasn't >>>> been >>>> >> tested in a while though. >>>> >> >>>> >> Pete >>>> >> >>>> >>> Thank you, >>>> >>> Gilad Rom >>>> >>> Romat Telecom >>>> >>> >>>> >>> >>>> >>> >>>> >> >>>> > > > >>>> >>> >>> >> >> From macro@mips.com Mon Nov 15 17:51:07 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2004 17:51:13 +0000 (GMT) Received: from alg145.algor.co.uk ([IPv6:::ffff:62.254.210.145]:43792 "EHLO dmz.algor.co.uk") by linux-mips.org with ESMTP id ; Mon, 15 Nov 2004 17:51:07 +0000 Received: from alg158.algor.co.uk ([62.254.210.158] helo=olympia.mips.com) by dmz.algor.co.uk with esmtp (Exim 3.35 #1 (Debian)) id 1CTl8C-0000no-00; Mon, 15 Nov 2004 17:59:12 +0000 Received: from perivale.mips.com ([192.168.192.200]) by olympia.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1CTkzo-00083t-00; Mon, 15 Nov 2004 17:50:32 +0000 Received: from macro (helo=localhost) by perivale.mips.com with local-esmtp (Exim 3.36 #1 (Debian)) id 1CTkzo-00027G-00; Mon, 15 Nov 2004 17:50:32 +0000 Date: Mon, 15 Nov 2004 17:50:32 +0000 (GMT) From: "Maciej W. Rozycki" To: libc-alpha@sources.redhat.com, Thiemo Seufer cc: Ralf Baechle , linux-mips@linux-mips.org, Nigel Stephens Subject: Re: [PATCH] MIPS/Linux: Kernel vs libc struct siginfo discrepancy In-Reply-To: <20041110180050.GK7235@rembrandt.csv.ica.uni-stuttgart.de> Message-ID: References: <20041110180050.GK7235@rembrandt.csv.ica.uni-stuttgart.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-MTUK-Scanner: Found to be clean X-MTUK-SpamCheck: not spam, SpamAssassin (score=-4.81, required 4, AWL, BAYES_00) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6334 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@mips.com Precedence: bulk X-list: linux-mips Content-Length: 3331 Lines: 90 On Wed, 10 Nov 2004, Thiemo Seufer wrote: > I prefer to bring the 2.4 kernel in line with the rest of the system. This is what is now in effect (Ralf, thanks for looking into it) and all that is left to be done is to fix padding done in glibc as this is incorrect for 64-bit MIPS. Here is a patch based on the current Linux header and sysdeps/unix/sysv/linux/bits/siginfo.h. It seems to work for me for the mips-linux host. 2004-11-15 Maciej W. Rozycki * sysdeps/unix/sysv/linux/mips/bits/siginfo.h (__SI_MAX_SIZE): Define appropriately based on __WORDSIZE. [struct siginfo] (__pad0): Add for explicit padding. * sysdeps/unix/sysv/linux/mips/bits/siginfo.h: Formatting fixes throughout. Please apply. Maciej glibc-2.3.3-20041018-mips-siginfo-pad-3.patch diff -up --recursive --new-file glibc-2.3.3-20041018.macro/sysdeps/unix/sysv/linux/mips/bits/siginfo.h glibc-2.3.3-20041018/sysdeps/unix/sysv/linux/mips/bits/siginfo.h --- glibc-2.3.3-20041018.macro/sysdeps/unix/sysv/linux/mips/bits/siginfo.h Fri May 23 02:26:20 2003 +++ glibc-2.3.3-20041018/sysdeps/unix/sysv/linux/mips/bits/siginfo.h Mon Nov 15 15:44:49 2004 @@ -1,5 +1,6 @@ /* siginfo_t, sigevent and constants. Linux/MIPS version. - Copyright (C) 1997, 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + Copyright (C) 1997, 1998, 2000, 2001, 2002, 2003, 2004 + Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or @@ -22,6 +23,8 @@ # error "Never include this file directly. Use instead" #endif +#include + #if (!defined __have_sigval_t \ && (defined _SIGNAL_H || defined __need_siginfo_t \ || defined __need_sigevent_t)) @@ -39,8 +42,13 @@ typedef union sigval && (defined _SIGNAL_H || defined __need_siginfo_t)) # define __have_siginfo_t 1 -# define __SI_MAX_SIZE 128 -# define __SI_PAD_SIZE ((__SI_MAX_SIZE / sizeof (int)) - 3) +# define __SI_MAX_SIZE 128 +# if __WORDSIZE == 64 +# define __SI_PAD_SIZE ((__SI_MAX_SIZE / sizeof (int)) - 4) +# else +# define __SI_PAD_SIZE ((__SI_MAX_SIZE / sizeof (int)) - 3) +# endif + typedef struct siginfo { @@ -48,6 +56,8 @@ typedef struct siginfo int si_code; /* Signal code. */ int si_errno; /* If non-zero, an errno value associated with this signal, as defined in . */ + int __pad0[__SI_MAX_SIZE / sizeof (int) - __SI_PAD_SIZE - 3]; + /* Explicit padding. */ union { @@ -121,9 +131,9 @@ enum { SI_ASYNCNL = -60, /* Sent by asynch name lookup completion. */ # define SI_ASYNCNL SI_ASYNCNL - SI_TKILL = -6, /* Sent by tkill. */ + SI_TKILL = -6, /* Sent by tkill. */ # define SI_TKILL SI_TKILL - SI_SIGIO, /* Sent by queued SIGIO. */ + SI_SIGIO, /* Sent by queued SIGIO. */ # define SI_SIGIO SI_SIGIO SI_MESGQ, /* Sent by real time mesq state change. */ # define SI_MESGQ SI_MESGQ @@ -149,7 +159,7 @@ enum # define ILL_ILLOPN ILL_ILLOPN ILL_ILLADR, /* Illegal addressing mode. */ # define ILL_ILLADR ILL_ILLADR - ILL_ILLTRP, /* Illegal trap. */ + ILL_ILLTRP, /* Illegal trap. */ # define ILL_ILLTRP ILL_ILLTRP ILL_PRVOPC, /* Privileged opcode. */ # define ILL_PRVOPC ILL_PRVOPC From ralf@linux-mips.org Mon Nov 15 17:55:18 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2004 17:55:22 +0000 (GMT) Received: from pD9562417.dip.t-dialin.net ([IPv6:::ffff:217.86.36.23]:31016 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Mon, 15 Nov 2004 17:55:17 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAFHtFed007924; Mon, 15 Nov 2004 18:55:15 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAFHtEYO007923; Mon, 15 Nov 2004 18:55:14 +0100 Date: Mon, 15 Nov 2004 18:55:14 +0100 From: Ralf Baechle To: Kumba Cc: linux-mips@linux-mips.org Subject: Re: [PATCH]: Rewrite of arch/mips/ramdisk/ Message-ID: <20041115175514.GA6069@linux-mips.org> References: <4196FE7C.9040309@gentoo.org> <20041114085202.GA30480@lst.de> <419794FB.6020104@gentoo.org> <4197B286.4060503@gentoo.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4197B286.4060503@gentoo.org> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6335 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 901 Lines: 18 On Sun, Nov 14, 2004 at 02:31:18PM -0500, Kumba wrote: > Ahh, I see. Ralf pointed me at CONFIG_INITRAMFS_SOURCE in 2.6.10. My > patch was based on 2.6.9, and I didn't exactly think this specific bit of > the kernel would change between 2.6.9 and 2.6.10. Go figure. > > It looks like this option, which afaict, doesn't seem to have an entry > anywhere in Kconfig, specifies a list of files for inclusion in a cpio > archive that's bundled into the kernel. My question then is, can a > lookback-mountable filesystem image be included in this list, and the > kernel, given /dev/ram0 as root, know to mount and use the loopback image? I guess you and many others don't realize the speed of the Linux evolution these days. Between 2.6.10-rc1 and 2.6.10-rc2 there's about 9MB of patches. Even if much of the code is not changing - the halftime for patches has reduced quite a bit ... Ralf From hch@lst.de Mon Nov 15 18:05:09 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2004 18:05:14 +0000 (GMT) Received: from verein.lst.de ([IPv6:::ffff:213.95.11.210]:45455 "EHLO mail.lst.de") by linux-mips.org with ESMTP id ; Mon, 15 Nov 2004 18:05:09 +0000 Received: from verein.lst.de (localhost [127.0.0.1]) by mail.lst.de (8.12.3/8.12.3/Debian-6.6) with ESMTP id iAFI57la024012 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=NO); Mon, 15 Nov 2004 19:05:07 +0100 Received: (from hch@localhost) by verein.lst.de (8.12.3/8.12.3/Debian-6.6) id iAFI57nE024010; Mon, 15 Nov 2004 19:05:07 +0100 Date: Mon, 15 Nov 2004 19:05:07 +0100 From: Christoph Hellwig To: Kumba Cc: linux-mips@linux-mips.org Subject: Re: [PATCH]: Rewrite of arch/mips/ramdisk/ Message-ID: <20041115180507.GA23952@lst.de> References: <4196FE7C.9040309@gentoo.org> <20041114085202.GA30480@lst.de> <419794FB.6020104@gentoo.org> <4197B286.4060503@gentoo.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4197B286.4060503@gentoo.org> User-Agent: Mutt/1.3.28i X-Spam-Score: -4.901 () BAYES_00 X-Scanned-By: MIMEDefang 2.39 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6336 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hch@lst.de Precedence: bulk X-list: linux-mips Content-Length: 628 Lines: 11 > It looks like this option, which afaict, doesn't seem to have an entry > anywhere in Kconfig, specifies a list of files for inclusion in a cpio > archive that's bundled into the kernel. My question then is, can a > lookback-mountable filesystem image be included in this list, and the > kernel, given /dev/ram0 as root, know to mount and use the loopback image? You could include a loop-back mountable filesystem image. But that's not even nessecary. The kernel will call /init of the files in the initramfs, and you could just store everything you'd store in the loopback filesystem directly in the initramfs image. From pf@net.alphadv.de Mon Nov 15 22:47:00 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Nov 2004 22:47:05 +0000 (GMT) Received: from mail.alphastar.de ([IPv6:::ffff:194.59.236.179]:2058 "EHLO mail.alphastar.de") by linux-mips.org with ESMTP id convert rfc822-to-8bit; Mon, 15 Nov 2004 22:47:00 +0000 Received: from SNaIlmail.Peter (217.249.200.252) by mail.alphastar.de with MERCUR Mailserver (v4.02.28 MTIxLTIxODAtNjY2OA==) for ; Mon, 15 Nov 2004 23:45:17 +0100 Received: from Opal.Peter (pf@Opal.Peter [192.168.1.1]) by SNaIlmail.Peter (8.12.6/8.12.6/Sendmail/Linux 2.0.32) with ESMTP id iAFMiEbr000547; Mon, 15 Nov 2004 23:44:15 +0100 Received: from localhost (pf@localhost) by Opal.Peter (8.9.3/8.9.3/Sendmail/Linux 2.2.5-15) with ESMTP id XAA01128; Mon, 15 Nov 2004 23:43:40 +0100 Date: Mon, 15 Nov 2004 23:43:40 +0100 (CET) From: peter fuerst To: macrohat cc: linux-mips Subject: On Sat, 13 Nov 2004, macrohat wrote... In-Reply-To: <20041113134735Z8224907-1751+1490@linux-mips.org> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Reply-To: pf@net.alphadv.de Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6337 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pf@net.alphadv.de Precedence: bulk X-list: linux-mips Content-Length: 2116 Lines: 74 Hello ! BogoMips is most useful as a benchmark, if the main purpose of your machine is to calculate BogoMips' ... (see BogoMips Mini-HOWTO :)) However - since there seems to be such a strong desire to see large BogoMips values - here is some help: Your BogoMips factor of 0.66, instead of the usual 0.99..., indicates that the delay loop is misaligned, i.e. there's a instruction-cache-block boundary inmidst the loop. (Recently i managed somehow to achieve this on a R10000 :) A ".align 3\n\t" at the begin of __delay() will keep the branch and its delay-slot together. You should even be able to double the BogoMips value (factor 1.99...) by unrolling the delay loop (at least on R10k): static __inline__ void __delay(unsigned long loops) { loops |= 1; __asm__ __volatile__ ( ".align 4\n\t" /* only the paranoid survive. */ ".set\tnoreorder\n" "1:\n\t" "dsubu\t%0,1\n\t" "bnez\t%0,1b\n\t" "dsubu\t%0,1\n\t" ".set\treorder" :"=r" (loops) :"0" (loops)); } Nevertheless, despite all this trickery, your machine will run exactly as fast (slow), as it did before. with kind regards pf "I have been a happy man ever since January 1, 1990, when I no longer had an email address. ..." Donald E. Knuth (http://www-cs-faculty.stanford.edu/~knuth/email.html) On Sat, 13 Nov 2004, macrohat wrote: > Date: Sat, 13 Nov 2004 21:47:02 +0800 > From: macrohat > To: linux-mips > Cc: linux-cvs > > Hello linux-mips: > > I have a question to ask you: why BCM1250 CPU Bogomips is so much lower than CPU clock frequency,such as: > CPU 700MHz - 465.30 Bogomips, CPU 800MHZ - 532.48 BogoMIPS.And i find out that CPU Bogomips is a fixed value regardless L2 cache open or closed, > > Enclosed is the log from the console > > Regards! > > > ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡macrohat > ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡emblinux@macrohat.com > ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2004-11-13 > From dan@embeddededge.com Tue Nov 16 00:22:30 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2004 00:22:36 +0000 (GMT) Received: from embeddededge.com ([IPv6:::ffff:209.113.146.155]:35085 "EHLO penguin.netx4.com") by linux-mips.org with ESMTP id ; Tue, 16 Nov 2004 00:22:30 +0000 Received: from [192.168.2.27] (x1000-57.tellink.net [63.161.110.249]) by penguin.netx4.com (8.12.8/8.12.9) with ESMTP id iAG0BjB4004633; Mon, 15 Nov 2004 19:11:46 -0500 In-Reply-To: <0a2201c4ca62$25d37f80$a701a8c0@lan> References: <20041112181335.13362.qmail@web81008.mail.yahoo.com> <09ac01c4ca24$e68a6740$a701a8c0@lan> <0a2201c4ca62$25d37f80$a701a8c0@lan> Mime-Version: 1.0 (Apple Message framework v619) Content-Type: text/plain; charset=US-ASCII; format=flowed Message-Id: Content-Transfer-Encoding: 7bit Cc: From: Dan Malek Subject: Re: GPIO on the Au1500 Date: Mon, 15 Nov 2004 19:25:10 -0500 To: "Gilad Rom" X-Mailer: Apple Mail (2.619) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6338 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@embeddededge.com Precedence: bulk X-list: linux-mips Content-Length: 715 Lines: 19 On Nov 14, 2004, at 10:53 AM, Gilad Rom wrote: > For some reason, I keep getting that magical value, 0x10000001 for > EVERY address I try to read, be it SYS_BASE (0xB1900000) or every > other address. It's not working because that is not the address of the device(s). The 0xB1900000 is the Kernel Virtual address of these devices, the real physical address, and the one you have to use with mmap() is the system control block address 0x11900000. Just be very, very careful with user space access of any IO using this method. The kernel can ensure atomic updates using various methods, but user applications can't and may cause system failures. This is why a GPIO driver is a much better approach. -- Dan From kumba@gentoo.org Tue Nov 16 01:19:20 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2004 01:19:25 +0000 (GMT) Received: from rwcrmhc11.comcast.net ([IPv6:::ffff:204.127.198.35]:47031 "EHLO rwcrmhc11.comcast.net") by linux-mips.org with ESMTP id ; Tue, 16 Nov 2004 01:19:20 +0000 Received: from [192.168.1.4] (pcp05077810pcs.waldrf01.md.comcast.net[68.54.246.193]) by comcast.net (rwcrmhc11) with ESMTP id <2004111601191201300cuogpe>; Tue, 16 Nov 2004 01:19:13 +0000 Message-ID: <4199561E.9040500@gentoo.org> Date: Mon, 15 Nov 2004 20:21:34 -0500 From: Kumba User-Agent: Mozilla Thunderbird 0.9 (Windows/20041103) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH]: Rewrite of arch/mips/ramdisk/ References: <4196FE7C.9040309@gentoo.org> <20041114085202.GA30480@lst.de> <419794FB.6020104@gentoo.org> <4197B286.4060503@gentoo.org> <20041115175514.GA6069@linux-mips.org> In-Reply-To: <20041115175514.GA6069@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6339 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kumba@gentoo.org Precedence: bulk X-list: linux-mips Content-Length: 1039 Lines: 24 Ralf Baechle wrote: > > I guess you and many others don't realize the speed of the Linux evolution > these days. Between 2.6.10-rc1 and 2.6.10-rc2 there's about 9MB of > patches. Even if much of the code is not changing - the halftime for > patches has reduced quite a bit ... I'm aware of the speed at which the kernel changes. What I didn't expect was that I picked the one time to try and fix mips embedded ramdisks with a more permanent fix at the same time someone else did -- just the someone else had a much better idea that applied more globally. Call it bad timing with a little bit of coincidence mixed in. I'll have to figure out how this CONFIG_INITRAMFS_SOURCE works now (it doesn't look like the Kconfig bits are in yet, a quick grep only shows mentions in defconfigs), and then see how it can replace the older embedded ramdisk idea. --Kumba -- "Such is oft the course of deeds that move the wheels of the world: small hands do them because they must, while the eyes of the great are elsewhere." --Elrond From anemo@mba.ocn.ne.jp Tue Nov 16 03:16:41 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2004 03:16:47 +0000 (GMT) Received: from topsns.toshiba-tops.co.jp ([IPv6:::ffff:202.230.225.5]:41243 "HELO topsns.toshiba-tops.co.jp") by linux-mips.org with SMTP id ; Tue, 16 Nov 2004 03:16:41 +0000 Received: from newms.toshiba-tops.co.jp by topsns.toshiba-tops.co.jp via smtpd (for mail.linux-mips.org [62.254.210.162]) with SMTP; 16 Nov 2004 03:16:40 UT Received: from srd2sd.toshiba-tops.co.jp (gw-chiba7.toshiba-tops.co.jp [172.17.244.27]) by newms.toshiba-tops.co.jp (Postfix) with ESMTP id E3E5B239E1A; Tue, 16 Nov 2004 12:16:35 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id iAG3GZdD075948; Tue, 16 Nov 2004 12:16:35 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Tue, 16 Nov 2004 12:15:20 +0900 (JST) Message-Id: <20041116.121520.27957567.nemoto@toshiba-tops.co.jp> To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: Re: gcc 3.3.4/3.4.1 and get_user From: Atsushi Nemoto In-Reply-To: <20041112134440.GA7588@linux-mips.org> References: <20040920171021.GA25371@linux-mips.org> <20041104.153744.122623401.nemoto@toshiba-tops.co.jp> <20041112134440.GA7588@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 3.3 on Emacs 21.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6340 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 764 Lines: 18 >>>>> On Fri, 12 Nov 2004 14:44:40 +0100, Ralf Baechle said: ralf> Right, part of the same mistake. See the patch below which gets ralf> my test system working. The 32-bit parts are cosmetic and ralf> shouldn't change the generated code. They just make the 32-bit ralf> and 64-bit str*_user.S files almost identical. Thank you. They work fine. ralf> I'm surprised somebody still cares about 2.4 64-bit ;-) The ralf> 64-bit improvments in 2.6, especially in the area of the 32-bit ralf> compatibility code are so substancial that I don't think 2.4 is ralf> still a good choice. Yes, I agree that 2.6 is better. I just want to run 2.4 64-bit for comparison from time to time. (only when something failed on 2.6 :-)) --- Atsushi Nemoto From emblinux@macrohat.com Tue Nov 16 05:51:40 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2004 05:51:45 +0000 (GMT) Received: from [IPv6:::ffff:218.30.103.173] ([IPv6:::ffff:218.30.103.173]:62219 "EHLO mxvip13.hichina.com") by linux-mips.org with ESMTP id ; Tue, 16 Nov 2004 05:51:39 +0000 Received: from 210.82.109.205 (HELO wanghonghui) (envelope-from emblinux@macrohat.com) by mxvip13.hichina.com (quarkmail-1.2.1) with ESMTP id S334312AbUKPFvH for linux-mips@linux-mips.org; Tue, 16 Nov 2004 13:51:07 +0800 Date: Tue, 16 Nov 2004 13:51:05 +0800 From: "macrohat" Reply-To: emblinux@macrohat.com To: "linux-mips" Cc: "Fuxin Zhang" Subject: X-mailer: Foxmail 5.0 beta1 [cn] Mime-Version: 1.0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: base64 Message-Id: <20041116055140Z8224771-1751+1666@linux-mips.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6341 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: emblinux@macrohat.com Precedence: bulk X-list: linux-mips Content-Length: 318 Lines: 6 SGkgTGludXgtbWlwczoNCg0KSG93IHRvIGFkZCBwcmVmZXRjaCBpbnN0cnVjdGlvbiBmb3IgU0Ix MjUwIHRvIG1lbWNweS5TIGFuZCBtZW1zZXQuUyAgdG8gaW1wcm92ZSBwZXJmb3JtYW5jZT8gDQoN Cg0KUmVnYXJkcyEgCQ0KDQoNCg0KoaGhoaGhoaGhoaGhoaGhoW1hY3JvaGF0DQqhoaGhoaGhoaGh oaGhoaGhZW1ibGludXhAbWFjcm9oYXQuY29tDQqhoaGhoaGhoaGhoaGhoaGhoaGhoTIwMDQtMTEt MTYNCg== From fxzhang@ict.ac.cn Tue Nov 16 06:11:50 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2004 06:11:56 +0000 (GMT) Received: from webmail.ict.ac.cn ([IPv6:::ffff:159.226.39.7]:47529 "HELO ict.ac.cn") by linux-mips.org with SMTP id ; Tue, 16 Nov 2004 06:11:50 +0000 Received: (qmail 7493 invoked by uid 507); 16 Nov 2004 05:41:22 -0000 Received: from unknown (HELO ict.ac.cn) (fxzhang@159.226.40.187) by ict.ac.cn with SMTP; 16 Nov 2004 05:41:22 -0000 Message-ID: <419999B5.3070901@ict.ac.cn> Date: Tue, 16 Nov 2004 14:09:57 +0800 From: Fuxin Zhang User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.6) Gecko/20040122 X-Accept-Language: zh-cn, en-us MIME-Version: 1.0 To: emblinux@macrohat.com CC: linux-cvs , linux-mips Subject: Re: Content-Type: text/plain; charset=GB2312 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6342 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fxzhang@ict.ac.cn Precedence: bulk X-list: linux-mips Content-Length: 1649 Lines: 57 Probably because -O3 automatically make short functions inline so local_sb1___flush_cache_all disappears asm("sb1___flush_cache_all_ipi = local_sb1___flush_cache_all"); ^^^^^^^^^I don't know whether this trick is safe for auto-inlining. as for the problem of adding prefetch to memcpy, I am not famliar with SB1250, but as of version 2.4.22, arch/mips/lib/memcpy.S already support using MIPS IV prefetch macrohat wrote: >Dear Fuxin Zhang: > >Thinks for your help! > >Now i have another question, I use mips-linux-gcc which is ported from gcc-3.2.3 by Broadcom to compile linux kernel,when I use "-O2" or "-Os" option, it can complete successfully, but if i use "-O3" option, it can not complete.Enclosed is the err log and souce code. >Any help would be really appreciated. > >err log: > >arch/mips64/mm/mm.o: In function `sb1___flush_cache_all': >arch/mips64/mm/mm.o(.text+0x1930): undefined reference to `local_sb1___flush_cac >he_all' >arch/mips64/mm/mm.o(.text+0x1934): undefined reference to `local_sb1___flush_cac >he_all' >make: *** [vmlinux] Error 1 > >source code: > >static void local_sb1___flush_cache_all(void) >{ > TRACE_RECORD(TRC_CACHEOP_BASE+5, 0, 0, > read_c0_count()); > > __sb1_writeback_inv_dcache_all(); > __sb1_flush_icache_all(); >} > >extern void sb1___flush_cache_all_ipi(void *ignored); >asm("sb1___flush_cache_all_ipi = local_sb1___flush_cache_all"); > >static void sb1___flush_cache_all(void) >{ > smp_call_function(sb1___flush_cache_all_ipi, 0, 1, 1); > local_sb1___flush_cache_all(); >} > > >Regards! > >¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡macrohat >¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡emblinux@macrohat.com >¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2004-11-14 > > From gilad@romat.com Tue Nov 16 14:34:21 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2004 14:34:26 +0000 (GMT) Received: from mail.romat.com ([IPv6:::ffff:212.143.245.3]:54289 "EHLO mail.romat.com") by linux-mips.org with ESMTP id ; Tue, 16 Nov 2004 14:34:21 +0000 Received: from localhost (localhost.lan [127.0.0.1]) by mail.romat.com (Postfix) with ESMTP id 66E09EB2B8 for ; Tue, 16 Nov 2004 16:34:14 +0200 (IST) Received: from mail.romat.com ([127.0.0.1]) by localhost (mail.romat.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 56329-02 for ; Tue, 16 Nov 2004 16:34:11 +0200 (IST) Received: from gilad (unknown [192.168.1.167]) by mail.romat.com (Postfix) with SMTP id 4F739EB2B6 for ; Tue, 16 Nov 2004 16:34:11 +0200 (IST) Message-ID: <0bbe01c4cbe9$60fa9570$a701a8c0@lan> From: "Gilad Rom" To: Subject: zboot on 2.6 Date: Tue, 16 Nov 2004 16:34:28 +0200 Organization: Romat Telecom MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="windows-1255"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2900.2180 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-Virus-Scanned: by amavisd-new at romat.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6343 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gilad@romat.com Precedence: bulk X-list: linux-mips Content-Length: 127 Lines: 9 Hello list, Is zboot supported on the linux-mips cvs 2.6 kernel tree, like it is on 2.4? Thank you, Gilad Rom Romat Telecom From ppopov@embeddedalley.com Tue Nov 16 16:46:18 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Nov 2004 16:46:26 +0000 (GMT) Received: from web81001.mail.yahoo.com ([IPv6:::ffff:206.190.37.146]:60066 "HELO web81001.mail.yahoo.com") by linux-mips.org with SMTP id ; Tue, 16 Nov 2004 16:46:18 +0000 Message-ID: <20041116164606.73956.qmail@web81001.mail.yahoo.com> Received: from [63.194.214.47] by web81001.mail.yahoo.com via HTTP; Tue, 16 Nov 2004 08:46:06 PST X-RocketYMMF: pvpopov@pacbell.net Date: Tue, 16 Nov 2004 08:46:06 -0800 (PST) From: Pete Popov Reply-To: ppopov@embeddedalley.com Subject: Re: zboot on 2.6 To: Gilad Rom , linux-mips@linux-mips.org In-Reply-To: <0bbe01c4cbe9$60fa9570$a701a8c0@lan> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6344 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ppopov@embeddedalley.com Precedence: bulk X-list: linux-mips Content-Length: 363 Lines: 17 --- Gilad Rom wrote: > Hello list, > > Is zboot supported on the linux-mips cvs 2.6 kernel > tree, > like it is on 2.4? It's not in the kernel source tree yet. Grab ftp.linux-mips.org:/pub/linux/mips/people/ppopov/2.6/zImage_2_6_10-rc1.patch There's no more zboot directory. The compressed kernel is under arch/mips/boot/compressed. Pete From ralf@linux-mips.org Wed Nov 17 13:17:54 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Nov 2004 13:17:59 +0000 (GMT) Received: from pD956202C.dip.t-dialin.net ([IPv6:::ffff:217.86.32.44]:51493 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Wed, 17 Nov 2004 13:17:54 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAHDHolk023723; Wed, 17 Nov 2004 14:17:50 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAHDHfPr023722; Wed, 17 Nov 2004 14:17:41 +0100 Date: Wed, 17 Nov 2004 14:17:41 +0100 From: Ralf Baechle To: Christoph Hellwig Cc: Kumba , linux-mips@linux-mips.org Subject: Re: [PATCH]: Rewrite of arch/mips/ramdisk/ Message-ID: <20041117131741.GA23041@linux-mips.org> References: <4196FE7C.9040309@gentoo.org> <20041114085202.GA30480@lst.de> <419794FB.6020104@gentoo.org> <4197B286.4060503@gentoo.org> <20041115180507.GA23952@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041115180507.GA23952@lst.de> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6345 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 530 Lines: 12 On Mon, Nov 15, 2004 at 07:05:07PM +0100, Christoph Hellwig wrote: > You could include a loop-back mountable filesystem image. But that's > not even nessecary. The kernel will call /init of the files in the > initramfs, and you could just store everything you'd store in the > loopback filesystem directly in the initramfs image. Right. So this means CONFIG_EMBEDDED_RAMDISK and CONFIG_EMBEDDED_RAMDISK_IMAGE have become obsolete. So unless somebody delivers a convincing argument I'm going to remove these options. Ralf From ralf@linux-mips.org Wed Nov 17 13:29:40 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Nov 2004 13:29:44 +0000 (GMT) Received: from pD956202C.dip.t-dialin.net ([IPv6:::ffff:217.86.32.44]:63013 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Wed, 17 Nov 2004 13:29:40 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAHDTccs003896; Wed, 17 Nov 2004 14:29:38 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAHDTcl7003895; Wed, 17 Nov 2004 14:29:38 +0100 Date: Wed, 17 Nov 2004 14:29:38 +0100 From: Ralf Baechle To: Kumba Cc: linux-mips@linux-mips.org Subject: Re: [PATCH]: R52x0 -> RM52xx Message-ID: <20041117132937.GA23812@linux-mips.org> References: <4196FE87.5050606@gentoo.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4196FE87.5050606@gentoo.org> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6346 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 554 Lines: 15 On Sun, Nov 14, 2004 at 01:43:19AM -0500, Kumba wrote: > > Attached is a minor cosmetic patch for 2.6 that just changes menuconfig to > show the RM52xx CPU by the name it's known by on Systems that use it > (Cobalt (RM5231), O2 RM5200). > > It's a really minor thing, but afaict, it doesn't look to be incorrect. The CPU core is originally a QED (today PMC-Sierra) core but there are licenses are selling it too such as IDT. I'm not sure if all of them are using the RM prefix or not but I usually stick to whatever the original name was. Ralf From yuasa@hh.iij4u.or.jp Wed Nov 17 15:15:05 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Nov 2004 15:15:11 +0000 (GMT) Received: from mo01.iij4u.or.jp ([IPv6:::ffff:210.130.0.20]:33762 "EHLO mo01.iij4u.or.jp") by linux-mips.org with ESMTP id ; Wed, 17 Nov 2004 15:15:05 +0000 Received: MO(mo01)id iAHFF10F027114; Thu, 18 Nov 2004 00:15:01 +0900 (JST) Received: MDO(mdo01) id iAHFF1EH002743; Thu, 18 Nov 2004 00:15:01 +0900 (JST) Received: 4UMRO01 id iAHFF0Ta023773; Thu, 18 Nov 2004 00:15:00 +0900 (JST) from stratos (localhost [127.0.0.1]) (authenticated) Date: Thu, 18 Nov 2004 00:14:58 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@hh.iij4u.or.jp, linux-mips Subject: [PATCH] Add cpu_wait() for NEC VR41xx Message-Id: <20041118001458.25f845ce.yuasa@hh.iij4u.or.jp> X-Mailer: Sylpheed version 0.9.99 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6347 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@hh.iij4u.or.jp Precedence: bulk X-list: linux-mips Content-Length: 2441 Lines: 105 Hi Ralf, This patch had added cpu_wait() for NEC VR41xx. Please apply this patch to v2.6 CVS tree. Yoichi Signed-off-by: Yoichi Yuasa diff -urN -X dontdiff b-orig/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c --- b-orig/arch/mips/kernel/cpu-probe.c Sun Oct 31 21:49:07 2004 +++ b/arch/mips/kernel/cpu-probe.c Wed Nov 17 22:51:36 2004 @@ -85,11 +85,9 @@ case CPU_R3081: case CPU_R3081E: cpu_wait = r3081_wait; - printk(" available.\n"); break; case CPU_TX3927: cpu_wait = r39xx_wait; - printk(" available.\n"); break; case CPU_R4200: /* case CPU_R4300: */ @@ -110,7 +108,6 @@ case CPU_24K: case CPU_25KF: cpu_wait = r4k_wait; - printk(" available.\n"); break; #ifdef CONFIG_PM case CPU_AU1000: @@ -118,17 +115,19 @@ case CPU_AU1500: if (au1k_wait_ptr != NULL) { cpu_wait = au1k_wait_ptr; - printk(" available.\n"); } else { - printk(" unavailable.\n"); } break; #endif default: - printk(" unavailable.\n"); break; } + + if (cpu_wait) + printk(" available.\n"); + else + printk(" unavailable.\n"); } void __init check_bugs32(void) diff -urN -X dontdiff b-orig/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c --- b-orig/arch/mips/vr41xx/common/pmu.c Thu May 27 02:11:11 2004 +++ b/arch/mips/vr41xx/common/pmu.c Wed Nov 17 22:58:09 2004 @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -29,6 +30,17 @@ #define PMUCNT2REG KSEG1ADDR(0x0f0000c6) #define SOFTRST 0x0010 +static void vr41xx_cpu_wait(void) +{ + __asm__ __volatile__( + ".set\tmips3\n\t" + "standby\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + ".set\tmips0"); +} + static inline void software_reset(void) { uint16_t val; @@ -70,6 +82,8 @@ static int __init vr41xx_pmu_init(void) { + cpu_wait = vr41xx_cpu_wait; + _machine_restart = vr41xx_restart; _machine_halt = vr41xx_halt; _machine_power_off = vr41xx_power_off; diff -urN -X dontdiff b-orig/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h --- b-orig/include/asm-mips/cpu-features.h Tue Aug 17 21:07:18 2004 +++ b/include/asm-mips/cpu-features.h Wed Nov 17 22:57:04 2004 @@ -124,4 +124,6 @@ #define cpu_scache_line_size() current_cpu_data.scache.linesz #endif +extern void (*cpu_wait)(void); + #endif /* __ASM_CPU_FEATURES_H */ From dom@mips.com Wed Nov 17 15:20:12 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Nov 2004 15:20:17 +0000 (GMT) Received: from alg145.algor.co.uk ([IPv6:::ffff:62.254.210.145]:12037 "EHLO dmz.algor.co.uk") by linux-mips.org with ESMTP id ; Wed, 17 Nov 2004 15:20:12 +0000 Received: from alg158.algor.co.uk ([62.254.210.158] helo=olympia.mips.com) by dmz.algor.co.uk with esmtp (Exim 3.35 #1 (Debian)) id 1CURjG-0005jI-00; Wed, 17 Nov 2004 15:28:18 +0000 Received: from arsenal.mips.com ([192.168.192.197]) by olympia.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1CURbD-0006p7-00; Wed, 17 Nov 2004 15:19:59 +0000 Received: from dom by arsenal.mips.com with local (Exim 3.35 #1 (Debian)) id 1CURbD-0002zy-00; Wed, 17 Nov 2004 15:19:59 +0000 From: Dominic Sweetman MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <16795.27678.928274.955392@arsenal.mips.com> Date: Wed, 17 Nov 2004 15:19:58 +0000 To: Ralf Baechle Cc: Kumba , linux-mips@linux-mips.org Subject: Re: [PATCH]: R52x0 -> RM52xx In-Reply-To: <20041117132937.GA23812@linux-mips.org> References: <4196FE87.5050606@gentoo.org> <20041117132937.GA23812@linux-mips.org> X-Mailer: VM 7.03 under 21.4 (patch 6) "Common Lisp" XEmacs Lucid X-MTUK-Scanner: Found to be clean X-MTUK-SpamCheck: not spam, SpamAssassin (score=-4.843, required 4, AWL, BAYES_00) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6348 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dom@mips.com Precedence: bulk X-list: linux-mips Content-Length: 851 Lines: 20 Ralf Baechle (ralf@linux-mips.org) writes: > > Attached is a minor cosmetic patch for 2.6 that just changes menuconfig to > > show the RM52xx CPU by the name it's known by on Systems that use it > > (Cobalt (RM5231), O2 RM5200). > > > > It's a really minor thing, but afaict, it doesn't look to be incorrect. > > The CPU core is originally a QED (today PMC-Sierra) core but there are > licenses are selling it too such as IDT. I'm not sure if all of them > are using the RM prefix or not but I usually stick to whatever the > original name was. FWIW (not much) there was an RM5230, RM5260, RM5231 and RM5261 - pretty much the same from a software point of view (the '3' and '6' stand for the external bus width 32- vs 64-bit). There was an RM5270, too, to which you could bolt an external L2 cache. So RM52xx is really quite a good name... From kevink@mips.com Wed Nov 17 15:23:26 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Nov 2004 15:23:30 +0000 (GMT) Received: from 209-232-97-206.ded.pacbell.net ([IPv6:::ffff:209.232.97.206]:7858 "EHLO dns0.mips.com") by linux-mips.org with ESMTP id ; Wed, 17 Nov 2004 15:23:26 +0000 Received: from mercury.mips.com (sbcns-dmz [209.232.97.193]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id iAHFNHpf001574 for ; Wed, 17 Nov 2004 07:23:17 -0800 (PST) Received: from grendel (grendel [192.168.236.16]) by mercury.mips.com (8.12.11/8.12.11) with SMTP id iAHFNHdh015831 for ; Wed, 17 Nov 2004 07:23:17 -0800 (PST) Message-ID: <006d01c4ccba$36a43110$10eca8c0@grendel> From: "Kevin D. Kissell" To: "Linux-MIPS Mailing List" Subject: Dubious MIPS kernel SMP Structures Date: Wed, 17 Nov 2004 16:29:21 +0100 Organization: MIPS Technologies Inc. MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1437 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1441 X-Scanned-By: MIMEDefang 2.39 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6349 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@mips.com Precedence: bulk X-list: linux-mips Content-Length: 647 Lines: 12 In arch/mips/kerenl/smp.c, there are two tables defined, __cpu_number_map[] and __cpu_logical_map[], which would appear to provide forward and backward mapping between a set of unique but arbitrary CPU numbers and a monotonically increasing number 0..n of indices into per-CPU data. As near as I can tell, the only use of this is in the sb1250 code for setting up interrupt hardware. Is there a reason why it's defined at the mips/kernel level, and not down in the SiByte platform subtree? Is there a generic, architectural definition of how these mappings should and should not be set up and used? Regards, Kevin K. From ralf@linux-mips.org Wed Nov 17 16:46:31 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Nov 2004 16:46:38 +0000 (GMT) Received: from pD956202C.dip.t-dialin.net ([IPv6:::ffff:217.86.32.44]:55592 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Wed, 17 Nov 2004 16:46:31 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAHGkT1w025609; Wed, 17 Nov 2004 17:46:29 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAHGkT8b025608; Wed, 17 Nov 2004 17:46:29 +0100 Date: Wed, 17 Nov 2004 17:46:29 +0100 From: Ralf Baechle To: "Kevin D. Kissell" Cc: Linux-MIPS Mailing List Subject: Re: Dubious MIPS kernel SMP Structures Message-ID: <20041117164629.GA10920@linux-mips.org> References: <006d01c4ccba$36a43110$10eca8c0@grendel> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <006d01c4ccba$36a43110$10eca8c0@grendel> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6350 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 2723 Lines: 60 On Wed, Nov 17, 2004 at 04:29:21PM +0100, Kevin D. Kissell wrote: > In arch/mips/kerenl/smp.c, there are two tables defined, __cpu_number_map[] > and __cpu_logical_map[], which would appear to provide forward and backward > mapping between a set of unique but arbitrary CPU numbers and a monotonically > increasing number 0..n of indices into per-CPU data. As near as I can tell, the > only use of this is in the sb1250 code for setting up interrupt hardware. Is there > a reason why it's defined at the mips/kernel level, and not down in the SiByte > platform subtree? Is there a generic, architectural definition of how these mappings > should and should not be set up and used? The Linux kernel is living in the assumption of having a dense CPU number space and being started by cpu 0 - something that isn't necessarily reflected by the underlying hardware. The system for which this concept was introduced into Linux is SGI's IP27. IP27 permits dividing of large systems into multiple independant partitions. Assume a two module Origin 2000; let's assume it's fully configured with 16 processors. Parititioning results in two domains. The first consists of processors 0 - 7; the second 8 - 15. Just for the kicks let's assume physical processors 11 and 13 are broken and therfor were disabled. From point of view of the generic Linux kernel this leaves a 6 processor system. So when we boot the kernel it will initialize these two mappings to the following mapping: logical physical CPU # -> CPU # 0 8 1 9 2 10 3 12 4 14 5 15 physical logical CPU # -> CPU # 8 0 9 1 10 2 11 # broken CPU, we're skipping this CPU number 12 3 13 # broken CPU, we're skipping this CPU number 14 4 15 5 As you found the IP27 code doesn't properly setup these mappings anymore; partly because it's SMP initialization code is twisted to the point where nobody understands it anymore. Partly also because the systems we used as SGI were too large to leave CPU numbers unused :) Honestly no idea why the Sibyte code is using that mapping stuff. The Sibyte firmware is always launching the kernel on CPU 0 anyway so we have the case of either only CPU 0 or both CPU 0 and CPU 1 which means the mapping would always be a 1:1 mapping. For most simple SMP or ccNUMA configurations assuming a 1:1 mapping is reasonable. For some uniprocessor configurations where a uniprocessor kernel is running on a single processor other than processor number 0 on a multiprocessor platform this also may be useful. Ralf From kevink@mips.com Wed Nov 17 17:01:43 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Nov 2004 17:01:47 +0000 (GMT) Received: from 209-232-97-206.ded.pacbell.net ([IPv6:::ffff:209.232.97.206]:5043 "EHLO dns0.mips.com") by linux-mips.org with ESMTP id ; Wed, 17 Nov 2004 17:01:43 +0000 Received: from mercury.mips.com (sbcns-dmz [209.232.97.193]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id iAHH1YjQ002030; Wed, 17 Nov 2004 09:01:35 -0800 (PST) Received: from [192.168.236.16] (grendel [192.168.236.16]) by mercury.mips.com (8.12.11/8.12.11) with ESMTP id iAHH1Ytw019987; Wed, 17 Nov 2004 09:01:35 -0800 (PST) Message-ID: <419B855B.1050304@mips.com> Date: Wed, 17 Nov 2004 18:07:39 +0100 From: "Kevin D. Kissell" User-Agent: Mozilla Thunderbird 0.9 (X11/20041103) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Ralf Baechle CC: Linux-MIPS Mailing List Subject: Re: Dubious MIPS kernel SMP Structures References: <006d01c4ccba$36a43110$10eca8c0@grendel> <20041117164629.GA10920@linux-mips.org> In-Reply-To: <20041117164629.GA10920@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.39 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6351 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@mips.com Precedence: bulk X-list: linux-mips Content-Length: 1611 Lines: 33 Ralf Baechle wrote: [snip of lots of cool historical explanations] > As you found the IP27 code doesn't properly setup these mappings anymore; > partly because it's SMP initialization code is twisted to the point > where nobody understands it anymore. Partly also because the systems > we used as SGI were too large to leave CPU numbers unused :) > > Honestly no idea why the Sibyte code is using that mapping stuff. The > Sibyte firmware is always launching the kernel on CPU 0 anyway so we have > the case of either only CPU 0 or both CPU 0 and CPU 1 which means the > mapping would always be a 1:1 mapping. > > For most simple SMP or ccNUMA configurations assuming a 1:1 mapping is > reasonable. For some uniprocessor configurations where a uniprocessor > kernel is running on a single processor other than processor number 0 on > a multiprocessor platform this also may be useful. But my question is really one of why it is that the platform-independent MIPS kernel code needs/needed to know anything about physical CPU numbers? Naively, I would have thought that any such mapping would be burried in the platform code, and that the architectural kernel code would simply invoke (possibly null) platform-level functions that do whatever mapping of logical 0...N CPU numbers to bizarre mesh node numbers might be necessary. As it stands, people who have no need to do mapping (SiByte, PMC-Sierra, and stuff we're doing at MIPS around MIPS MT) are mindlessly replicating code to set up 1:1 mappings that will never (in the PMC-Sierra and MIPS cases) be referenced. Regards, Kevin K. From ralf@linux-mips.org Thu Nov 18 09:37:31 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 09:37:35 +0000 (GMT) Received: from p508B71E5.dip.t-dialin.net ([IPv6:::ffff:80.139.113.229]:3901 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Thu, 18 Nov 2004 09:37:31 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAI9bUhn029416 for ; Thu, 18 Nov 2004 10:37:30 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAI9bTLM029415 for linux-mips@linux-mips.org; Thu, 18 Nov 2004 10:37:29 +0100 Date: Thu, 18 Nov 2004 10:37:29 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: Wiki Message-ID: <20041118093729.GA28447@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6352 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 539 Lines: 12 Some of you may have already noticed; I replaced the old homepage of linux-mips.org which was generated from the same sources as the Linux/MIPS Howto by a wiki at http://www.linux-mips.org. The wiki's currently 82 pages including a somewhat updated version of Jun Sun's Porting Linux document and inspite of the young age of the wiki it should already have bypassed the old documents in quantity, readability, up-to-dateness. Check it out, post what you think about the wiki. Most importantatly write many nice new articles :-) Ralf From mlachwani@prometheus.mvista.com Thu Nov 18 18:41:12 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 18:41:19 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:59126 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Thu, 18 Nov 2004 18:41:12 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iAIIf9dh003237; Thu, 18 Nov 2004 10:41:09 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iAIIf8sQ003235; Thu, 18 Nov 2004 10:41:08 -0800 Date: Thu, 18 Nov 2004 10:41:08 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Fix for the pcnet32 ethernet driver Message-ID: <20041118184108.GA3228@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="7AUc2qLy4jB3hD7Z" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6353 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1153 Lines: 43 --7AUc2qLy4jB3hD7Z Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ralf, This patch fixes the pcnet32 ethernet driver to clear any other interrupt when setting interrupt enable in the pcnet32 interrupt handler. This has been tested on the NEC CMB-VR4133 board. Please review Thanks Manish Lachwani --7AUc2qLy4jB3hD7Z Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename="common_mips_NEC_eth_MR9056.patch" Source: MontaVista Software, Inc. | http;//www.mvista.com | Manish Lachwani Type: Defect Fix Disposition: Submitted to Linux-MIPS Description: Fix the Interrupt Enable for the PcNet32 driver. Ack any remaining interrupts. Tested on the NEC CMB-VR4133 Index: linux/drivers/net/pcnet32.c =================================================================== --- linux.orig/drivers/net/pcnet32.c +++ linux/drivers/net/pcnet32.c @@ -1897,7 +1897,7 @@ } /* Set interrupt enable. */ - lp->a.write_csr (ioaddr, 0, 0x0040); + lp->a.write_csr (ioaddr, 0, 0x7940); lp->a.write_rap (ioaddr,rap); if (netif_msg_intr(lp)) --7AUc2qLy4jB3hD7Z-- From mlachwani@prometheus.mvista.com Thu Nov 18 18:49:52 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 18:49:57 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:63726 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Thu, 18 Nov 2004 18:49:52 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iAIInodh003490; Thu, 18 Nov 2004 10:49:50 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iAIIno2K003488; Thu, 18 Nov 2004 10:49:50 -0800 Date: Thu, 18 Nov 2004 10:49:50 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Compile in the serial driver for TX4927 Message-ID: <20041118184950.GA3482@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="AqsLC8rIMeq19msA" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6354 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 907 Lines: 29 --AqsLC8rIMeq19msA Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ralf Attached small patch compiles in the serial driver (serial_txx9.c) for Toshiba TX4927. Thanks for Ralf Roesch for pointing this out Thanks Manish Lachwani --AqsLC8rIMeq19msA Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename=patch-tx4927-serial --- drivers/char/Makefile.orig 2004-11-18 10:44:22.000000000 -0800 +++ drivers/char/Makefile 2004-11-18 10:45:27.000000000 -0800 @@ -21,6 +21,7 @@ obj-$(CONFIG_MVME162_SCC) += generic_serial.o vme_scc.o obj-$(CONFIG_BVME6000_SCC) += generic_serial.o vme_scc.o obj-$(CONFIG_SERIAL_TX3912) += generic_serial.o serial_tx3912.o +obj-$(CONFIG_SERIAL_TXX9) += generic_serial.o serial_txx9.o obj-$(CONFIG_ROCKETPORT) += rocket.o obj-$(CONFIG_SERIAL167) += serial167.o obj-$(CONFIG_CYCLADES) += cyclades.o --AqsLC8rIMeq19msA-- From macro@linux-mips.org Thu Nov 18 19:16:44 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 19:16:50 +0000 (GMT) Received: from pollux.ds.pg.gda.pl ([IPv6:::ffff:153.19.208.7]:34566 "EHLO pollux.ds.pg.gda.pl") by linux-mips.org with ESMTP id ; Thu, 18 Nov 2004 19:16:44 +0000 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 3786EF59AF; Thu, 18 Nov 2004 20:16:37 +0100 (CET) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 30969-02; Thu, 18 Nov 2004 20:16:37 +0100 (CET) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 73468E1CB6; Thu, 18 Nov 2004 20:16:34 +0100 (CET) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.1/8.13.1) with ESMTP id iAIJGhoP028423; Thu, 18 Nov 2004 20:16:43 +0100 Date: Thu, 18 Nov 2004 19:16:38 +0000 (GMT) From: "Maciej W. Rozycki" To: Manish Lachwani Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] Compile in the serial driver for TX4927 In-Reply-To: <20041118184950.GA3482@prometheus.mvista.com> Message-ID: References: <20041118184950.GA3482@prometheus.mvista.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.80/590/Wed Nov 17 22:03:52 2004 clamav-milter version 0.80j on piorun.ds.pg.gda.pl X-Virus-Status: Clean X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6355 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 223 Lines: 9 On Thu, 18 Nov 2004, Manish Lachwani wrote: > Attached small patch compiles in the serial driver (serial_txx9.c) for > Toshiba TX4927. > Thanks for Ralf Roesch for pointing this out Applied as obvious, thanks. Maciej From mlachwani@prometheus.mvista.com Thu Nov 18 19:32:03 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 19:32:08 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:56046 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Thu, 18 Nov 2004 19:32:03 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iAIJW1dh004278; Thu, 18 Nov 2004 11:32:01 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iAIJW1Fa004276; Thu, 18 Nov 2004 11:32:01 -0800 Date: Thu, 18 Nov 2004 11:32:01 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Fix to the Broadcom sb1250-mac driver Message-ID: <20041118193201.GA4269@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="wac7ysb48OaltWcw" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6356 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1117 Lines: 42 --wac7ysb48OaltWcw Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ralf Attached is a small patch for the sb1250-mac driver to print the ethernet device name correctly. This is based on a previous discussion. Please review Thanks Manish Lachwani --wac7ysb48OaltWcw Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename=patch-sb1250-mac --- drivers/net/sb1250-mac.c.orig 2004-11-18 11:24:12.000000000 -0800 +++ drivers/net/sb1250-mac.c 2004-11-18 11:27:49.000000000 -0800 @@ -1811,8 +1811,6 @@ /* read system identification to determine revision */ if (periph_rev >= 2) { - printk(KERN_INFO "%s: enabling TCP rcv checksum\n", - sc->sbm_dev->name); sc->rx_hw_checksum = ENABLE; } else { sc->rx_hw_checksum = DISABLE; @@ -2417,6 +2415,11 @@ if (err) goto out_uninit; + if (periph_rev >= 2) { + printk(KERN_INFO "%s: enabling TCP rcv checksum\n", + sc->sbm_dev->name); + } + /* * Display Ethernet address (this is called during the config * process so we need to finish off the config message that --wac7ysb48OaltWcw-- From mlachwani@prometheus.mvista.com Thu Nov 18 19:52:22 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 19:52:34 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:58353 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Thu, 18 Nov 2004 19:52:22 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iAIJqJdh004346; Thu, 18 Nov 2004 11:52:19 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iAIJqJ9Y004344; Thu, 18 Nov 2004 11:52:19 -0800 Date: Thu, 18 Nov 2004 11:52:19 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Support for NEC VR4133 in 2.6 Message-ID: <20041118195219.GA4337@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="0F1p//8PRICkK4MW" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6357 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 38316 Lines: 1272 --0F1p//8PRICkK4MW Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ralf Attached patch implements support for NEC VR4133 and NEC Rockhopper in 2.6. Currently there is no ethernet driver for the ports on the CMB-VR4133. The board has been booted with the Onboard PcNet32 network interface and with an Intel EEPRO100 PCI NIC card. Please review ... Thanks Manish Lachwani --0F1p//8PRICkK4MW Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename="common_mips_NEC_vr4133_MR9056.patch" Source: MontaVista Software, Inc. | http://www.mvista.com | Manish Lachwani Type: Enhancement Disposition: Submitted to Linux-MIPS Description: Support for NEC VR4133 and NEC CMB-VR4133 in 2.6.10 kernel Index: linux/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c @@ -0,0 +1,256 @@ +/* + * arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c + * + * Initialize for ALi M1535+(included M5229 and M5237). + * + * Author: Yoichi Yuasa and + * Alex Sapkov + * + * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for NEC-CMBVR4133 in 2.6 + * Author: Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include + +#include +#include +#include + +#define CONFIG_PORT(port) ((port) ? 0x3f0 : 0x370) +#define DATA_PORT(port) ((port) ? 0x3f1 : 0x371) +#define INDEX_PORT(port) CONFIG_PORT(port) + +#define ENTER_CONFIG_MODE(port) \ + do { \ + outb_p(0x51, CONFIG_PORT(port)); \ + outb_p(0x23, CONFIG_PORT(port)); \ + } while(0) + +#define SELECT_LOGICAL_DEVICE(port, dev_no) \ + do { \ + outb_p(0x07, INDEX_PORT(port)); \ + outb_p((dev_no), DATA_PORT(port)); \ + } while(0) + +#define WRITE_CONFIG_DATA(port,index,data) \ + do { \ + outb_p((index), INDEX_PORT(port)); \ + outb_p((data), DATA_PORT(port)); \ + } while(0) + +#define EXIT_CONFIG_MODE(port) outb(0xbb, CONFIG_PORT(port)) + +#define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18) +#define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14) + +#ifdef CONFIG_BLK_DEV_FD + +void __devinit ali_m1535plus_fdc_init(int port) +{ + ENTER_CONFIG_MODE(port); + SELECT_LOGICAL_DEVICE(port, 0); /* FDC */ + WRITE_CONFIG_DATA(port, 0x30, 0x01); /* FDC: enable */ + WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x3f0 */ + WRITE_CONFIG_DATA(port, 0x61, 0xf0); + WRITE_CONFIG_DATA(port, 0x70, 0x06); /* IRQ: 6 */ + WRITE_CONFIG_DATA(port, 0x74, 0x02); /* DMA: channel 2 */ + WRITE_CONFIG_DATA(port, 0xf0, 0x08); + WRITE_CONFIG_DATA(port, 0xf1, 0x00); + WRITE_CONFIG_DATA(port, 0xf2, 0xff); + WRITE_CONFIG_DATA(port, 0xf4, 0x00); + EXIT_CONFIG_MODE(port); +} + +#endif + +void __devinit ali_m1535plus_parport_init(int port) +{ + ENTER_CONFIG_MODE(port); + SELECT_LOGICAL_DEVICE(port, 3); /* Parallel Port */ + WRITE_CONFIG_DATA(port, 0x30, 0x01); + WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x378 */ + WRITE_CONFIG_DATA(port, 0x61, 0x78); + WRITE_CONFIG_DATA(port, 0x70, 0x07); /* IRQ: 7 */ + WRITE_CONFIG_DATA(port, 0x74, 0x04); /* DMA: None */ + WRITE_CONFIG_DATA(port, 0xf0, 0x8c); /* IRQ polarity: Active Low */ + WRITE_CONFIG_DATA(port, 0xf1, 0xc5); + EXIT_CONFIG_MODE(port); +} + +#ifdef CONFIG_PC_KEYB + +void __devinit ali_m1535plus_keyboard_init(int port) +{ + ENTER_CONFIG_MODE(port); + SELECT_LOGICAL_DEVICE(port, 7); /* KEYBOARD */ + WRITE_CONFIG_DATA(port, 0x30, 0x01); /* KEYBOARD: eable */ + WRITE_CONFIG_DATA(port, 0x70, 0x01); /* IRQ: 1 */ + WRITE_CONFIG_DATA(port, 0x72, 0x0c); /* PS/2 Mouse IRQ: 12 */ + WRITE_CONFIG_DATA(port, 0xf0, 0x00); + EXIT_CONFIG_MODE(port); +} + +#endif + +void __devinit ali_m1535plus_hotkey_init(int port) +{ + ENTER_CONFIG_MODE(port); + SELECT_LOGICAL_DEVICE(port, 0xc); /* HOTKEY */ + WRITE_CONFIG_DATA(port, 0x30, 0x00); + WRITE_CONFIG_DATA(port, 0xf0, 0x35); + WRITE_CONFIG_DATA(port, 0xf1, 0x14); + WRITE_CONFIG_DATA(port, 0xf2, 0x11); + WRITE_CONFIG_DATA(port, 0xf3, 0x71); + WRITE_CONFIG_DATA(port, 0xf5, 0x05); + EXIT_CONFIG_MODE(port); +} + +void ali_m1535plus_init(struct pci_dev *dev) +{ + pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */ + pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */ + pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */ + pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */ + pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */ + pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */ + pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */ + + /* IRQ routing */ + pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */ + pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */ + pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */ + pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */ + + pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */ + pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */ + pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */ + pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */ + + pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */ + pci_write_config_byte(dev, 0x5a, 0x00); + pci_write_config_byte(dev, 0x5b, 0x00); + pci_write_config_word(dev, 0x5c, 0x0000); + pci_write_config_byte(dev, 0x5e, 0x00); + pci_write_config_byte(dev, 0x5f, 0x00); + pci_write_config_word(dev, 0x60, 0x0000); + + pci_write_config_byte(dev, 0x6c, 0x00); + pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */ + pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */ + + pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */ + pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */ + pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */ + pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */ + + /* + * IRQ setup ALi M5237 USB Host Controller + * IRQ: 9 + */ + pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */ + + pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15 */ + pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */ + pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */ + pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */ + pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */ + pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */ + pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */ + pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */ + +#ifdef CONFIG_BLK_DEV_FD + ali_m1535plus_fdc_init(1); +#endif + +#ifdef CONFIG_PC_KEYB + ali_m1535plus_keyboard_init(1); + ali_m1535plus_hotkey_init(1); +#endif +} + +static inline void ali_config_writeb(u8 reg, u8 val, int devfn) +{ + u32 data; + int shift; + + writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); + data = readl(PCI_CONFIG_DATA); + + shift = (reg & 3) << 3; + data &= ~(0xff << shift); + data |= (((u32)val) << shift); + + writel(data, PCI_CONFIG_DATA); +} + +static inline u8 ali_config_readb(u8 reg, int devfn) +{ + u32 data; + + writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); + data = readl(PCI_CONFIG_DATA); + + return (u8)(data >> ((reg & 3) << 3)); +} + +static inline u16 ali_config_readw(u8 reg, int devfn) +{ + u32 data; + + writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); + data = readl(PCI_CONFIG_DATA); + + return (u16)(data >> ((reg & 2) << 3)); +} + +int vr4133_rockhopper = 0; +void __init ali_m5229_preinit(void) +{ + if (ali_config_readw(PCI_VENDOR_ID,16) == PCI_VENDOR_ID_AL && + ali_config_readw(PCI_DEVICE_ID,16) == PCI_DEVICE_ID_AL_M1533) { + printk(KERN_INFO "Found an NEC Rockhopper \n"); + vr4133_rockhopper = 1; + /* + * Enable ALi M5229 IDE Controller (both channels) + * IDSEL: A27 + */ + ali_config_writeb(0x58, 0x4c, 16); + } +} + +void __init ali_m5229_init(struct pci_dev *dev) +{ + /* + * Enable Primary/Secondary Channel Cable Detect 40-Pin + */ + pci_write_config_word(dev, 0x4a, 0xc023); + + /* + * Set only the 3rd byteis for the master IDE's cycle and + * enable Internal IDE Function + */ + pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */ + + pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */ + pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */ + pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */ + pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */ + pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */ + pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */ + pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */ + pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */ + pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */ + pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */ + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); + pci_write_config_word(dev, PCI_COMMAND, + PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | + PCI_COMMAND_IO); +} + Index: linux/arch/mips/vr41xx/nec-cmbvr4133/init.c =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/nec-cmbvr4133/init.c @@ -0,0 +1,81 @@ +/* + * arch/mips/vr41xx/nec-cmbvr4133/init.c + * + * PROM library initialisation code for NEC CMB-VR4133 board. + * + * Author: Yoichi Yuasa and + * Jun Sun and + * Alex Sapkov + * + * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for NEC-CMBVR4133 in 2.6 + * Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include + +#include + +#ifdef CONFIG_ROCKHOPPER +#include +#include + +#define PCICONFDREG 0xaf000c14 +#define PCICONFAREG 0xaf000c18 +#endif + +const char *get_system_type(void) +{ + return "NEC CMB-VR4133"; +} + +void __init bus_error_init(void) +{ + /* Do Nothing */ +} + +#ifdef CONFIG_ROCKHOPPER +void disable_pcnet(void) +{ + u32 data; + + /* Workaround for the bug in PMON on VR4133. PMON leaves + AMD PCNet controller (on Rockhopper) initialized and running in + bus master mode. We have do disable it before doing any + further initialization. Or we get problems with PCI bus 2 + and random lockups and crashes.*/ + + writel((2 << 16) | + (PCI_DEVFN(1,0) << 8) | + (0 & 0xfc) | + 1UL, + PCICONFAREG); + + data = readl(PCICONFDREG); + + writel((2 << 16) | + (PCI_DEVFN(1,0) << 8) | + (4 & 0xfc) | + 1UL, + PCICONFAREG); + + data = readl(PCICONFDREG); + + writel((2 << 16) | + (PCI_DEVFN(1,0) << 8) | + (4 & 0xfc) | + 1UL, + PCICONFAREG); + + data &= ~4; + + writel(data, PCICONFDREG); +} +#endif + Index: linux/arch/mips/vr41xx/nec-cmbvr4133/setup.c =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/nec-cmbvr4133/setup.c @@ -0,0 +1,127 @@ +/* + * arch/mips/vr41xx/nec-cmbvr4133/setup.c + * + * Setup for the NEC CMB-VR4133. + * + * Author: Yoichi Yuasa and + * Alex Sapkov + * + * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for CMBVR4133 board in 2.6 + * Author: Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_MTD +#include +#include +#include +#include + +static struct mtd_partition cmbvr4133_mtd_parts[] = { + { + .name = "User FS", + .size = 0x1be0000, + .offset = 0, + .mask_flags = 0, + }, + { + .name = "PMON", + .size = 0x140000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "User FS2", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0, + } +}; + +#define number_partitions (sizeof(cmbvr4133_mtd_parts)/sizeof(struct mtd_partition)) +#endif + +void vr41xx_restart(char *command) +{ + change_c0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL)); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); +} + +void vr41xx_halt(void) +{ + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); + while (1); +} + +void vr41xx_power_off(void) +{ + vr41xx_halt(); +} + +extern void (*late_time_init)(void); + +static void __init vr4133_serial_init(void) +{ + vr41xx_select_siu_interface(SIU_RS232C, IRDA_NONE); + vr41xx_siu_init(); + vr41xx_dsiu_init(); +} + +static int __init nec_cmbvr4133_setup(void) +{ +#ifdef CONFIG_ROCKHOPPER + extern void disable_pcnet(void); + + disable_pcnet(); +#endif + set_io_port_base(IO_PORT_BASE); + + mips_machgroup = MACH_GROUP_NEC_VR41XX; + mips_machtype = MACH_NEC_CMBVR4133; + + _machine_restart = vr41xx_restart; + _machine_halt = vr41xx_halt; + _machine_power_off = vr41xx_power_off; + + late_time_init = vr4133_serial_init; + +#ifdef CONFIG_PCI +#ifdef CONFIG_ROCKHOPPER + ali_m5229_preinit(); +#endif +#endif + +#ifdef CONFIG_ROCKHOPPER + rockhopper_init_irq(); +#endif + +#ifdef CONFIG_MTD + /* we use generic physmap mapping driver and we use partitions */ + physmap_configure(0x1C000000, 0x02000000, 4, NULL); + physmap_set_partitions(cmbvr4133_mtd_parts, number_partitions); +#endif + + /* 128 MB memory support */ + add_memory_region(0, 0x08000000, BOOT_MEM_RAM); + + return 0; +} + +early_initcall(nec_cmbvr4133_setup); Index: linux/arch/mips/vr41xx/nec-cmbvr4133/irq.c =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/nec-cmbvr4133/irq.c @@ -0,0 +1,114 @@ +/* + * arch/mips/vr41xx/nec-cmbvr4133/irq.c + * + * Interrupt routines for the NEC CMB-VR4133 board. + * + * Author: Yoichi Yuasa and + * Alex Sapkov + * + * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for NEC-CMBVR4133 in 2.6 + * Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +#include +#include + +extern void enable_8259A_irq(unsigned int irq); +extern void disable_8259A_irq(unsigned int irq); +extern void mask_and_ack_8259A(unsigned int irq); +extern void init_8259A(int hoge); + +extern int vr4133_rockhopper; + +static unsigned int startup_i8259_irq(unsigned int irq) +{ + enable_8259A_irq(irq - I8259_IRQ_BASE); + return 0; +} + +static void shutdown_i8259_irq(unsigned int irq) +{ + disable_8259A_irq(irq - I8259_IRQ_BASE); +} + +static void enable_i8259_irq(unsigned int irq) +{ + enable_8259A_irq(irq - I8259_IRQ_BASE); +} + +static void disable_i8259_irq(unsigned int irq) +{ + disable_8259A_irq(irq - I8259_IRQ_BASE); +} + +static void ack_i8259_irq(unsigned int irq) +{ + mask_and_ack_8259A(irq - I8259_IRQ_BASE); +} + +static void end_i8259_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_8259A_irq(irq - I8259_IRQ_BASE); +} + +static struct hw_interrupt_type i8259_irq_type = { + .typename = "XT-PIC", + .startup = startup_i8259_irq, + .shutdown = shutdown_i8259_irq, + .enable = enable_i8259_irq, + .disable = disable_i8259_irq, + .ack = ack_i8259_irq, + .end = end_i8259_irq, +}; + +static int i8259_get_irq_number(int irq) +{ + unsigned long isr; + + isr = inb(0x20); + irq = ffz(~isr); + if (irq == 2) { + isr = inb(0xa0); + irq = 8 + ffz(~isr); + } + + if (irq < 0 || irq > 15) + return -EINVAL; + + return I8259_IRQ_BASE + irq; +} + +static struct irqaction i8259_slave_cascade = { + .handler = &no_action, + .name = "cascade", +}; + +void __init rockhopper_init_irq(void) +{ + int i; + + if(!vr4133_rockhopper) { + printk(KERN_ERR "Not a Rockhopper Board \n"); + return; + } + + for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) + irq_desc[i].handler = &i8259_irq_type; + + setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); + + vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH); + vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH); + vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number); +} Index: linux/arch/mips/vr41xx/nec-cmbvr4133/Makefile =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/nec-cmbvr4133/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the NEC-CMBVR4133 +# + +obj-y := init.o setup.o + +obj-$(CONFIG_PCI) += m1535plus.o +obj-$(CONFIG_ROCKHOPPER) += irq.o Index: linux/arch/mips/Makefile =================================================================== --- linux.orig/arch/mips/Makefile +++ linux/arch/mips/Makefile @@ -486,6 +486,12 @@ cflags-$(CONFIG_MACH_VR41XX) += -Iinclude/asm-mips/mach-vr41xx # +# NEC VR4133 +# +core-$(CONFIG_NEC_CMBVR4133) += arch/mips/vr41xx/nec-cmbvr4133/ +load-$(CONFIG_NEC_CMBVR4133) += 0xffffffff80100000 + +# # ZAO Networks Capcella (VR4131) # core-$(CONFIG_ZAO_CAPCELLA) += arch/mips/vr41xx/zao-capcella/ Index: linux/include/asm-mips/vr41xx/cmbvr4133.h =================================================================== --- /dev/null +++ linux/include/asm-mips/vr41xx/cmbvr4133.h @@ -0,0 +1,93 @@ +/* + * include/asm-mips/vr41xx/cmbvr4133.h + * + * Include file for NEC CMB-VR4133. + * + * Author: Yoichi Yuasa and + * Jun Sun and + * Alex Sapkov + * + * 2002-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __NEC_CMBVR4133_H +#define __NEC_CMBVR4133_H + +#include + +#include +#include +#include + +/* + * Board specific address mapping + */ +#define VR41XX_PCI_MEM1_BASE 0x10000000 +#define VR41XX_PCI_MEM1_SIZE 0x04000000 +#define VR41XX_PCI_MEM1_MASK 0x7c000000 + +#define VR41XX_PCI_MEM2_BASE 0x14000000 +#define VR41XX_PCI_MEM2_SIZE 0x02000000 +#define VR41XX_PCI_MEM2_MASK 0x7e000000 + +#define VR41XX_PCI_IO_BASE 0x16000000 +#define VR41XX_PCI_IO_SIZE 0x02000000 +#define VR41XX_PCI_IO_MASK 0x7e000000 + +#define VR41XX_PCI_IO_START 0x01000000 +#define VR41XX_PCI_IO_END 0x01ffffff + +#define VR41XX_PCI_MEM_START 0x12000000 +#define VR41XX_PCI_MEM_END 0x15ffffff + +#define IO_PORT_BASE KSEG1ADDR(VR41XX_PCI_IO_BASE) +#define IO_PORT_RESOURCE_START 0 +#define IO_PORT_RESOURCE_END VR41XX_PCI_IO_SIZE +#define IO_MEM1_RESOURCE_START VR41XX_PCI_MEM1_BASE +#define IO_MEM1_RESOURCE_END (VR41XX_PCI_MEM1_BASE + VR41XX_PCI_MEM1_SIZE) +#define IO_MEM2_RESOURCE_START VR41XX_PCI_MEM2_BASE +#define IO_MEM2_RESOURCE_END (VR41XX_PCI_MEM2_BASE + VR41XX_PCI_MEM2_SIZE) + +/* + * General-Purpose I/O Pin Number + */ +#define CMBVR41XX_INTA_PIN 1 +#define CMBVR41XX_INTB_PIN 1 +#define CMBVR41XX_INTC_PIN 3 +#define CMBVR41XX_INTD_PIN 1 +#define CMBVR41XX_INTE_PIN 1 + +/* + * Interrupt Number + */ +#define CMBVR41XX_INTA_IRQ GIU_IRQ(CMBVR41XX_INTA_PIN) +#define CMBVR41XX_INTB_IRQ GIU_IRQ(CMBVR41XX_INTB_PIN) +#define CMBVR41XX_INTC_IRQ GIU_IRQ(CMBVR41XX_INTC_PIN) +#define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN) +#define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN) + +#define I8259_IRQ_BASE 72 +#define I8259_IRQ(x) (I8259_IRQ_BASE + (x)) +#define TIMER_IRQ I8259_IRQ(0) +#define KEYBOARD_IRQ I8259_IRQ(1) +#define I8259_SLAVE_IRQ I8259_IRQ(2) +#define UART3_IRQ I8259_IRQ(3) +#define UART1_IRQ I8259_IRQ(4) +#define UART2_IRQ I8259_IRQ(5) +#define FDC_IRQ I8259_IRQ(6) +#define PARPORT_IRQ I8259_IRQ(7) +#define RTC_IRQ I8259_IRQ(8) +#define USB_IRQ I8259_IRQ(9) +#define I8259_INTA_IRQ I8259_IRQ(10) +#define AUDIO_IRQ I8259_IRQ(11) +#define AUX_IRQ I8259_IRQ(12) +#define IDE_PRIMARY_IRQ I8259_IRQ(14) +#define IDE_SECONDARY_IRQ I8259_IRQ(15) +#define I8259_IRQ_LAST IDE_SECONDARY_IRQ + +#define RTC_PORT(x) (0xaf000100 + (x)) +#define RTC_IO_EXTENT 0x140 + +#endif /* __NEC_CMBVR4133_H */ Index: linux/arch/mips/vr41xx/common/vr4133.c =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/common/vr4133.c @@ -0,0 +1,75 @@ +/* + * arch/mips/vr41xx/common/vr4133.c + * + * NEC VR4133 specific routines. + * + * Author: Alex Sapkov or + * + * 2001-2004 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include + +#include +#include + +#define VR4133_CMUCLKMSK2 KSEG1ADDR(0x0f000064) + +#define VR4133_CMU_CEU 0x0001 +#define VR4133_CMU_MSKMAC0 0x0002 +#define VR4133_CMU_MSKMAC1 0x0004 + +/* Clock Mask Unit primitives */ + +void vr4133_clock_ceu_supply(void) +{ + u16 cmuclkmsk2; + + cmuclkmsk2 = readw(VR4133_CMUCLKMSK2) | VR4133_CMU_CEU; + writew(cmuclkmsk2, VR4133_CMUCLKMSK2); +} + +void vr4133_clock_ceu_mask(void) +{ + u16 cmuclkmsk2; + + cmuclkmsk2 = readw(VR4133_CMUCLKMSK2) & ~VR4133_CMU_CEU; + writew(cmuclkmsk2, VR4133_CMUCLKMSK2); +} + +void vr4133_clock_ether0_supply(void) +{ + u16 cmuclkmsk2; + + cmuclkmsk2 = readw(VR4133_CMUCLKMSK2) | VR4133_CMU_MSKMAC0; + writew(cmuclkmsk2, VR4133_CMUCLKMSK2); +} + +void vr4133_clock_ether0_mask(void) +{ + u16 cmuclkmsk2; + + cmuclkmsk2 = readw(VR4133_CMUCLKMSK2) & ~VR4133_CMU_MSKMAC0; + writew(cmuclkmsk2, VR4133_CMUCLKMSK2); +} + +void vr4133_clock_ether1_supply(void) +{ + u16 cmuclkmsk2; + + cmuclkmsk2 = readw(VR4133_CMUCLKMSK2) | VR4133_CMU_MSKMAC1; + writew(cmuclkmsk2, VR4133_CMUCLKMSK2); +} + +void vr4133_clock_ether1_mask(void) +{ + u16 cmuclkmsk2; + + cmuclkmsk2 = readw(VR4133_CMUCLKMSK2) & ~VR4133_CMU_MSKMAC1; + writew(cmuclkmsk2, VR4133_CMUCLKMSK2); +} + + Index: linux/include/asm-mips/vr41xx/vr4133.h =================================================================== --- /dev/null +++ linux/include/asm-mips/vr41xx/vr4133.h @@ -0,0 +1,25 @@ +/* + * include/asm-mips/vr41xx/vr4133.h + * + * Include file for NEC VR4133. + * + * Author: Alex Sapkov or + * + * 2004 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __NEC_VR4133_H +#define __NEC_VR4133_H +/* + * Clock Mask Unit + */ +extern void vr4133_clock_ether0_supply(void); +extern void vr4133_clock_ether1_supply(void); +extern void vr4133_clock_ceu_supply(void); +extern void vr4133_clock_ether0_mask(void); +extern void vr4133_clock_ether1_mask(void); +extern void vr4133_clock_ceu_mask(void); + +#endif /* __NEC_VR4133_H */ Index: linux/arch/mips/Kconfig =================================================================== --- linux.orig/arch/mips/Kconfig +++ linux/arch/mips/Kconfig @@ -69,6 +69,21 @@ config MACH_VR41XX bool "Support for NEC VR41XX-based machines" +config NEC_CMBVR4133 + bool "Support for NEC CMB-VR4133" + depends on MACH_VR41XX + select CPU_VR41XX + select DMA_NONCOHERENT + select IRQ_CPU + select HW_HAS_PCI + select PCI_VR41XX + +config ROCKHOPPER + bool "Support for Rockhopper baseboard" + depends on NEC_CMBVR4133 + select I8259 + select HAVE_STD_PC_SERIAL_PORT + config CASIO_E55 bool "Support for CASIO CASSIOPEIA E-10/15/55/65" depends on MACH_VR41XX Index: linux/include/asm-mips/bootinfo.h =================================================================== --- linux.orig/include/asm-mips/bootinfo.h +++ linux/include/asm-mips/bootinfo.h @@ -195,6 +195,7 @@ #define MACH_CASIO_E55 5 /* CASIO CASSIOPEIA E-10/15/55/65 */ #define MACH_TANBAC_TB0226 6 /* TANBAC TB0226 (Mbase) */ #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */ +#define MACH_NEC_CMBVR4133 8 /* CMB VR4133 Board */ #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */ #define MACH_HP_LASERJET 1 Index: linux/arch/mips/pci/Makefile =================================================================== --- linux.orig/arch/mips/pci/Makefile +++ linux/arch/mips/pci/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_MIPS_TX3927) += ops-jmr3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o +obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o # # These are still pretty much in the old state, watch, go blind. Index: linux/arch/mips/vr41xx/common/Makefile =================================================================== --- linux.orig/arch/mips/vr41xx/common/Makefile +++ linux/arch/mips/vr41xx/common/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_SERIAL_8250) += serial.o obj-$(CONFIG_VRC4171) += vrc4171.o obj-$(CONFIG_VRC4173) += vrc4173.o +obj-$(NEC_CMBVR4133) += vr4133.o EXTRA_AFLAGS := $(CFLAGS) Index: linux/arch/mips/pci/fixup-vr4133.c =================================================================== --- /dev/null +++ linux/arch/mips/pci/fixup-vr4133.c @@ -0,0 +1,214 @@ +/* + * arch/mips/vr41xx/nec-cmbvr4133/pci_fixup.c + * + * The NEC CMB-VR4133 Board specific PCI fixups. + * + * Author: Yoichi Yuasa and + * Alex Sapkov + * + * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Modified for support in 2.6 + * Author: Manish Lachwani (mlachwani@mvista.com) + * + */ +#include +#include +#include + +#include +#include + +extern int vr4133_rockhopper; +extern void ali_m1535plus_init(struct pci_dev *dev); +extern void ali_m5229_init(struct pci_dev *dev); + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + if (dev->vendor == PCI_VENDOR_ID_AL) { + switch (dev->device) { + case PCI_DEVICE_ID_AL_M1533: + ali_m1535plus_init(dev); + break; + case PCI_DEVICE_ID_AL_M5229: + ali_m5229_init(dev); + break; + case PCI_DEVICE_ID_AL_M5237: + break; + } + } + + /* + * We have to reset AMD PCnet adapter on Rockhopper since + * PMON leaves it enabled and generating interrupts. This leads + * to a lock if some PCI device driver later enables the IRQ line + * shared with PCnet and there is no AMD PCnet driver to catch its + * interrupts. + */ +#ifdef CONFIG_ROCKHOPPER + if (dev->vendor == PCI_VENDOR_ID_AMD && + dev->device == PCI_DEVICE_ID_AMD_LANCE) { + inl(pci_resource_start(dev, 0) + 0x18); + } +#endif + + /* + * we have to open the bridges' windows down to 0 because otherwise + * we cannot access ISA south bridge I/O registers that get mapped from + * 0. for example, 8259 PIC would be unaccessible without that + */ + if(dev->vendor == 0x8086 && dev->device == 0xb152) { + pci_write_config_byte(dev, PCI_IO_BASE, 0); + if(dev->bus->number == 0) { + pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0); + } else { + pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 1); + } + } + + return 0; +} + +/* + * M1535 IRQ mapping + * Feel free to change this, although it shouldn't be needed + */ +#define M1535_IRQ_INTA 7 +#define M1535_IRQ_INTB 9 +#define M1535_IRQ_INTC 10 +#define M1535_IRQ_INTD 11 + +#define M1535_IRQ_USB 9 +#define M1535_IRQ_IDE 14 +#define M1535_IRQ_IDE2 15 +#define M1535_IRQ_PS2 12 +#define M1535_IRQ_RTC 8 +#define M1535_IRQ_FDC 6 +#define M1535_IRQ_AUDIO 5 +#define M1535_IRQ_COM1 4 +#define M1535_IRQ_COM2 4 +#define M1535_IRQ_IRDA 3 +#define M1535_IRQ_KBD 1 +#define M1535_IRQ_TMR 0 + +/* Rockhopper "slots" assignment; this is hard-coded ... */ +#define ROCKHOPPER_M5451_SLOT 1 +#define ROCKHOPPER_M1535_SLOT 2 +#define ROCKHOPPER_M5229_SLOT 11 +#define ROCKHOPPER_M5237_SLOT 15 +#define ROCKHOPPER_PMU_SLOT 12 +/* ... and hard-wired. */ +#define ROCKHOPPER_PCI1_SLOT 3 +#define ROCKHOPPER_PCI2_SLOT 4 +#define ROCKHOPPER_PCI3_SLOT 5 +#define ROCKHOPPER_PCI4_SLOT 6 +#define ROCKHOPPER_PCNET_SLOT 1 + +#define M1535_IRQ_MASK(n) (1 << (n)) + +#define M1535_IRQ_EDGE (M1535_IRQ_MASK(M1535_IRQ_TMR) | \ + M1535_IRQ_MASK(M1535_IRQ_KBD) | \ + M1535_IRQ_MASK(M1535_IRQ_COM1) | \ + M1535_IRQ_MASK(M1535_IRQ_COM2) | \ + M1535_IRQ_MASK(M1535_IRQ_IRDA) | \ + M1535_IRQ_MASK(M1535_IRQ_RTC) | \ + M1535_IRQ_MASK(M1535_IRQ_FDC) | \ + M1535_IRQ_MASK(M1535_IRQ_PS2)) + +#define M1535_IRQ_LEVEL (M1535_IRQ_MASK(M1535_IRQ_IDE) | \ + M1535_IRQ_MASK(M1535_IRQ_USB) | \ + M1535_IRQ_MASK(M1535_IRQ_INTA) | \ + M1535_IRQ_MASK(M1535_IRQ_INTB) | \ + M1535_IRQ_MASK(M1535_IRQ_INTC) | \ + M1535_IRQ_MASK(M1535_IRQ_INTD)) + +struct irq_map_entry { + u16 bus; + u8 slot; + u8 irq; +}; +static struct irq_map_entry int_map[] = { + {1, ROCKHOPPER_M5451_SLOT, M1535_IRQ_AUDIO}, /* Audio controller */ + {1, ROCKHOPPER_PCI1_SLOT, M1535_IRQ_INTD}, /* PCI slot #1 */ + {1, ROCKHOPPER_PCI2_SLOT, M1535_IRQ_INTC}, /* PCI slot #2 */ + {1, ROCKHOPPER_M5237_SLOT, M1535_IRQ_USB}, /* USB host controller */ + {1, ROCKHOPPER_M5229_SLOT, IDE_PRIMARY_IRQ}, /* IDE controller */ + {2, ROCKHOPPER_PCNET_SLOT, M1535_IRQ_INTD}, /* AMD Am79c973 on-board + ethernet */ + {2, ROCKHOPPER_PCI3_SLOT, M1535_IRQ_INTB}, /* PCI slot #3 */ + {2, ROCKHOPPER_PCI4_SLOT, M1535_IRQ_INTC} /* PCI slot #4 */ +}; + +static int pci_intlines[] = + { M1535_IRQ_INTA, M1535_IRQ_INTB, M1535_IRQ_INTC, M1535_IRQ_INTD }; + +/* Determine the Rockhopper IRQ line number for the PCI device */ +int rockhopper_get_irq(struct pci_dev *dev, u8 pin, u8 slot) +{ + struct pci_bus *bus; + int i; + + bus = dev->bus; + if (bus == NULL) + return -1; + + for (i = 0; i < sizeof (int_map) / sizeof (int_map[0]); i++) { + if (int_map[i].bus == bus->number && int_map[i].slot == slot) { + int line; + for (line = 0; line < 4; line++) + if (pci_intlines[line] == int_map[i].irq) + break; + if (line < 4) + return pci_intlines[(line + (pin - 1)) % 4]; + else + return int_map[i].irq; + } + } + return -1; +} + +#ifdef CONFIG_ROCKHOPPER +static void i8259_init(void) +{ + outb(0x11, 0x20); /* Master ICW1 */ + outb(I8259_IRQ_BASE, 0x21); /* Master ICW2 */ + outb(0x04, 0x21); /* Master ICW3 */ + outb(0x01, 0x21); /* Master ICW4 */ + outb(0xff, 0x21); /* Master IMW */ + + outb(0x11, 0xa0); /* Slave ICW1 */ + outb(I8259_IRQ_BASE + 8, 0xa1); /* Slave ICW2 */ + outb(0x02, 0xa1); /* Slave ICW3 */ + outb(0x01, 0xa1); /* Slave ICW4 */ + outb(0xff, 0xa1); /* Slave IMW */ + + outb(0x00, 0x4d0); + outb(0x02, 0x4d1); /* USB IRQ9 is level */ +} +#endif + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + extern int pci_probe_only; + pci_probe_only = 1; + +#ifdef CONFIG_ROCKHOPPER + i8259_init(); + if( dev->bus->number == 1 && vr4133_rockhopper ) { + if(slot == ROCKHOPPER_PCI1_SLOT || slot == ROCKHOPPER_PCI2_SLOT) + dev->irq = CMBVR41XX_INTA_IRQ; + else + dev->irq = rockhopper_get_irq(dev, pin, slot); + } else + dev->irq = CMBVR41XX_INTA_IRQ; +#else + dev->irq = CMBVR41XX_INTA_IRQ; +#endif + + return dev->irq; +} + Index: linux/arch/mips/pci/pci-vr41xx.h =================================================================== --- linux.orig/arch/mips/pci/pci-vr41xx.h +++ linux/arch/mips/pci/pci-vr41xx.h @@ -18,6 +18,8 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Support for NEC VR4133 in 2.6 - Manish Lachwani (mlachwani@mvista.com) */ #ifndef __PCI_VR41XX_H #define __PCI_VR41XX_H @@ -127,6 +129,10 @@ #define PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U +#define PCI_MASTER_MEM2_BUS_BASE_ADDRESS 0x14000000U +#define PCI_MASTER_MEM2_ADDRESS_MASK 0x7e000000U +#define PCI_MASTER_MEM2_PCI_BASE_ADDRESS 0x14000000U + #define PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U Index: linux/arch/mips/pci/pci-vr41xx.c =================================================================== --- linux.orig/arch/mips/pci/pci-vr41xx.c +++ linux/arch/mips/pci/pci-vr41xx.c @@ -19,6 +19,8 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Support for NEC VR4133 in 2.6 - Manish Lachwani (mlachwani@mvista.com) */ /* * Changes: @@ -43,6 +45,12 @@ .pci_base_address = PCI_MASTER_MEM1_PCI_BASE_ADDRESS, }; +static struct pci_master_address_conversion pci_master_memory2 = { + .bus_base_address = PCI_MASTER_MEM2_BUS_BASE_ADDRESS, + .address_mask = PCI_MASTER_MEM2_ADDRESS_MASK, + .pci_base_address = PCI_MASTER_MEM2_PCI_BASE_ADDRESS, +}; + static struct pci_target_address_conversion pci_target_memory1 = { .address_mask = PCI_TARGET_MEM1_ADDRESS_MASK, .bus_base_address = PCI_TARGET_MEM1_BUS_BASE_ADDRESS, @@ -76,6 +84,22 @@ .flags = IORESOURCE_IO, }; +#ifdef CONFIG_ROCKHOPPER +static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = { + .master_memory1 = &pci_master_memory1, + .master_memory2 = &pci_master_memory2, + .target_memory1 = &pci_target_memory1, + .master_io = &pci_master_io, + .exclusive_access = CANNOT_LOCK_FROM_DEVICE, + .wait_time_limit_from_irdy_to_trdy = 0, + .mailbox = &pci_mailbox, + .target_window1 = &pci_target_window1, + .master_latency_timer = 0x80, + .retry_limit = 0, + .arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR, + .take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE, +}; +#else static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = { .master_memory1 = &pci_master_memory1, .target_memory1 = &pci_target_memory1, @@ -89,6 +113,7 @@ .arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR, .take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE, }; +#endif static struct pci_controller vr41xx_pci_controller = { .pci_ops = &vr41xx_pci_ops, Index: linux/arch/mips/vr41xx/common/serial.c =================================================================== --- linux.orig/arch/mips/vr41xx/common/serial.c +++ linux/arch/mips/vr41xx/common/serial.c @@ -52,17 +52,17 @@ #define TMICTX 0x10 #define TMICMODE 0x20 -#define SIU_BASE_TYPE1 0x0c000000UL /* VR4111 and VR4121 */ -#define SIU_BASE_TYPE2 0x0f000800UL /* VR4122, VR4131 and VR4133 */ +#define SIU_BASE_TYPE1 KSEG1ADDR(0x0c000000) /* VR4111 and VR4121 */ +#define SIU_BASE_TYPE2 KSEG1ADDR(0x0f000800) /* VR4122, VR4131 and VR4133 */ #define SIU_SIZE 0x8UL -#define SIU_BASE_BAUD 1152000 +#define SIU_BASE_BAUD 115200 /* VR4122, VR4131 and VR4133 DSIU Registers */ -#define DSIU_BASE 0x0f000820UL +#define DSIU_BASE KSEG1ADDR(0x0f000820) #define DSIU_SIZE 0x8UL -#define DSIU_BASE_BAUD 1152000 +#define DSIU_BASE_BAUD 115200 int vr41xx_serial_ports = 0; @@ -132,7 +132,7 @@ } port.regshift = 0; port.iotype = UPIO_MEM; - port.membase = ioremap(port.mapbase, SIU_SIZE); + port.membase = (unsigned char *)port.mapbase; if (port.membase != NULL) { if (early_serial_setup(&port) == 0) { vr41xx_supply_clock(SIU_CLOCK); @@ -164,7 +164,7 @@ port.mapbase = DSIU_BASE; port.regshift = 0; port.iotype = UPIO_MEM; - port.membase = ioremap(port.mapbase, DSIU_SIZE); + port.membase = (unsigned char *)port.mapbase; if (port.membase != NULL) { if (early_serial_setup(&port) == 0) { vr41xx_supply_clock(DSIU_CLOCK); --0F1p//8PRICkK4MW-- From TheNop@gmx.net Thu Nov 18 20:13:47 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 20:13:51 +0000 (GMT) Received: from pop.gmx.de ([IPv6:::ffff:213.165.64.20]:1668 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Thu, 18 Nov 2004 20:13:47 +0000 Received: (qmail 12381 invoked by uid 65534); 18 Nov 2004 20:13:40 -0000 Received: from c210132.adsl.hansenet.de (EHLO [192.168.0.1]) (213.39.210.132) by mail.gmx.net (mp013) with SMTP; 18 Nov 2004 21:13:40 +0100 X-Authenticated: #947741 Message-ID: <419D03DE.8090403@gmx.net> Date: Thu, 18 Nov 2004 21:19:42 +0100 From: TheNop User-Agent: Mozilla Thunderbird 0.7.3 (Windows/20040803) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Titan ethernet driver broken Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6358 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: TheNop@gmx.net Precedence: bulk X-list: linux-mips Content-Length: 254 Lines: 12 Hello, using DHCP support on the yosemite target with the current sources did not work anymore. The DHCP request timed out. Using the sources from cvs lable linux_2_6_8_1 for the titan ethernet driver works around this problem. Best regards TheNop From mlachwani@mvista.com Thu Nov 18 20:23:08 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 20:23:12 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:47098 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Thu, 18 Nov 2004 20:23:08 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 6214E18492; Thu, 18 Nov 2004 12:23:06 -0800 (PST) Message-ID: <419D04AA.50508@mvista.com> Date: Thu, 18 Nov 2004 12:23:06 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: TheNop Cc: linux-mips@linux-mips.org Subject: Re: Titan ethernet driver broken References: <419D03DE.8090403@gmx.net> In-Reply-To: <419D03DE.8090403@gmx.net> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6359 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 459 Lines: 22 TheNop wrote: > Hello, > > using DHCP support on the yosemite target with the current sources did > not work anymore. > The DHCP request timed out. > Using the sources from cvs lable linux_2_6_8_1 for the titan ethernet > driver works around this problem. > > Best regards > TheNop > > > Hello ! Can you send the diff between the titan_ge (both .c and .h files) driver version in linux_2_6_8_1 and the latest driver sources? Thanks Manish Lachwani From TheNop@gmx.net Thu Nov 18 21:35:54 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 21:36:02 +0000 (GMT) Received: from mail.gmx.net ([IPv6:::ffff:213.165.64.20]:44676 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Thu, 18 Nov 2004 21:35:54 +0000 Received: (qmail 16280 invoked by uid 65534); 18 Nov 2004 21:35:47 -0000 Received: from c210132.adsl.hansenet.de (EHLO [192.168.0.1]) (213.39.210.132) by mail.gmx.net (mp014) with SMTP; 18 Nov 2004 22:35:47 +0100 X-Authenticated: #947741 Message-ID: <419D171E.5040507@gmx.net> Date: Thu, 18 Nov 2004 22:41:50 +0100 From: TheNop User-Agent: Mozilla Thunderbird 0.7.3 (Windows/20040803) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: Titan ethernet driver broken References: <419D03DE.8090403@gmx.net> <419D04AA.50508@mvista.com> In-Reply-To: <419D04AA.50508@mvista.com> Content-Type: multipart/mixed; boundary="------------070608030705010706000200" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6360 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: TheNop@gmx.net Precedence: bulk X-list: linux-mips Content-Length: 17324 Lines: 704 This is a multi-part message in MIME format. --------------070608030705010706000200 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Manish Lachwani wrote: > TheNop wrote: > >> Hello, >> >> using DHCP support on the yosemite target with the current sources >> did not work anymore. >> The DHCP request timed out. >> Using the sources from cvs lable linux_2_6_8_1 for the titan ethernet >> driver works around this problem. >> >> Best regards >> TheNop >> >> >> > Hello ! > > Can you send the diff between the titan_ge (both .c and .h files) > driver version in linux_2_6_8_1 and the latest driver sources? > > Thanks > Manish Lachwani > > > Hi Manish, here are the diffs. You also need moduls.h from linux_2_6_8_1. Best regards TheNop --------------070608030705010706000200 Content-Type: text/plain; name="module.h.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="module.h.diff" 47,60d46 < struct module; < < struct module_attribute { < struct attribute attr; < ssize_t (*show)(struct module *, char *); < ssize_t (*store)(struct module *, const char *, size_t count); < }; < < struct module_kobject < { < struct kobject kobj; < struct module *mod; < }; < 76,77d61 < extern struct subsystem module_subsys; < 160c144,145 < local headers in "srcversion". --- > local headers to the end. Use MODULE_VERSION("") if you want just > this. Macro includes room for this. 162c147,148 < #define MODULE_VERSION(_version) MODULE_INFO(version, _version) --- > #define MODULE_VERSION(_version) \ > MODULE_INFO(version, _version "\0xxxxxxxxxxxxxxxxxxxxxxxx") 224a211,227 > /* sysfs stuff */ > struct module_attribute > { > struct attribute attr; > struct kernel_param *param; > }; > > struct module_kobject > { > /* Everyone should have one of these. */ > struct kobject kobj; > > /* We always have refcnt, we may have others from module_param(). */ > unsigned int num_attributes; > struct module_attribute attr[0]; > }; > 240d242 < struct param_kobject; 254d255 < struct param_kobject *params_kobject; 305a307,309 > > /* Fake kernel param for refcnt. */ > struct kernel_param refcnt_param; 444,448d447 < < struct device_driver; < void module_add_driver(struct module *, struct device_driver *); < void module_remove_driver(struct device_driver *); < 538,549d536 < < struct device_driver; < struct module; < < static inline void module_add_driver(struct module *module, struct device_driver *driver) < { < } < < static inline void module_remove_driver(struct device_driver *driver) < { < } < 561,562d547 < < static inline void __deprecated MODULE_PARM_(void) { } 567c552,572 < { __stringify(var), type, &MODULE_PARM_ }; --- > { __stringify(var), type }; > > static inline void __deprecated MOD_INC_USE_COUNT(struct module *module) > { > __unsafe(module); > > #if defined(CONFIG_MODULE_UNLOAD) && defined(MODULE) > local_inc(&module->ref[get_cpu()].count); > put_cpu(); > #else > (void)try_module_get(module); > #endif > } > > static inline void __deprecated MOD_DEC_USE_COUNT(struct module *module) > { > module_put(module); > } > > #define MOD_INC_USE_COUNT MOD_INC_USE_COUNT(THIS_MODULE) > #define MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT(THIS_MODULE) 569c574,576 < #define MODULE_PARM(var,type) static void __attribute__((__unused__)) *__parm_##var = &MODULE_PARM_; --- > #define MODULE_PARM(var,type) > #define MOD_INC_USE_COUNT do { } while (0) > #define MOD_DEC_USE_COUNT do { } while (0) 576,582c583,587 < extern void __deprecated inter_module_register(const char *, < struct module *, const void *); < extern void __deprecated inter_module_unregister(const char *); < extern const void * __deprecated inter_module_get(const char *); < extern const void * __deprecated inter_module_get_request(const char *, < const char *); < extern void __deprecated inter_module_put(const char *); --- > extern void inter_module_register(const char *, struct module *, const void *); > extern void inter_module_unregister(const char *); > extern const void *inter_module_get(const char *); > extern const void *inter_module_get_request(const char *, const char *); > extern void inter_module_put(const char *); --------------070608030705010706000200 Content-Type: text/plain; name="titan_ge.c.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="titan_ge.c.diff" 50c50 < #include --- > #include 52a53 > #include 53a55,56 > #include > #include 61a65 > #include 97a102 > static int titan_ge_set_mac_address(struct net_device *, void *); 105a111 > static int titan_ge_init(int); 119a126 > #ifdef TITAN_RX_NAPI 120a128 > #endif 124,125d131 < static struct platform_device *titan_ge_device[3]; < 132,133d137 < static char titan_string[] = "titan"; < 450a455 > #ifdef TITAN_RX_NAPI 468,470d472 < if (port_num == 2) < ack &= ~(0x30000); < 476a479,481 > #else > titan_ge_free_tx_queue(titan_ge_eth); > titan_ge_receive_queue(netdev, 0); 477a483 > #endif 612,613d617 < struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev; < volatile titan_ge_rx_desc *rx_desc; 614a619 > volatile titan_ge_rx_desc *rx_desc; 621,622c626,627 < dma_map_single(device, skb->data, TITAN_GE_JUMBO_BUFSIZE - 2, < DMA_FROM_DEVICE); --- > pci_map_single(0, skb->data, TITAN_GE_JUMBO_BUFSIZE - 2, > PCI_DMA_FROMDEVICE); 625,626c630,631 < dma_map_single(device, skb->data, TITAN_GE_STD_BUFSIZE - 2, < DMA_FROM_DEVICE); --- > pci_map_single(0, skb->data, TITAN_GE_STD_BUFSIZE - 2, > PCI_DMA_FROMDEVICE); 723d727 < unsigned long reg_data_1; 737c741 < --- > #ifdef TITAN_RX_NAPI 739c743,745 < --- > #else > TITAN_GE_WRITE(0x000c, 0x00000100); /* No WCIMODE */ > #endif 748a755 > #ifdef TITAN_RX_NAPI 750a758 > #endif 905,950d912 < /* < * Titan 1.2 revision does support port #2 < */ < if (port_num == 2) { < /* < * Put the descriptors in the SRAM < */ < reg_data = TITAN_GE_READ(0x48a0); < < reg_data |= 0x100000; < reg_data |= (0xff << 10) | (2*(0xff + 1)); < < TITAN_GE_WRITE(0x48a0, reg_data); < /* < * BAV2,BAV and DAV settings for the Rx FIFO < */ < reg_data1 = TITAN_GE_READ(0x48a4); < reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); < TITAN_GE_WRITE(0x48a4, reg_data1); < < reg_data &= ~(0x00100000); < reg_data |= 0x200000; < < TITAN_GE_WRITE(0x48a0, reg_data); < < reg_data = TITAN_GE_READ(0x4958); < reg_data |= 0x100000; < < TITAN_GE_WRITE(0x4958, reg_data); < reg_data |= (0xff << 10) | (2*(0xff + 1)); < TITAN_GE_WRITE(0x4958, reg_data); < < /* < * BAV2, BAV and DAV settings for the Tx FIFO < */ < reg_data1 = TITAN_GE_READ(0x495c); < reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); < < TITAN_GE_WRITE(0x495c, reg_data1); < < reg_data &= ~(0x00100000); < reg_data |= 0x200000; < < TITAN_GE_WRITE(0x4958, reg_data); < } < 995,1016d956 < < /* < * This is the 1.2 revision of the chip. It has fix for the < * IP header alignment. Now, the IP header begins at an < * aligned address and this wont need an extra copy in the < * driver. This performance drawback existed in the previous < * versions of the silicon < */ < reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12)); < reg_data_1 |= 0x40000000; < TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); < < reg_data_1 |= 0x04000000; < TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); < < mdelay(5); < < reg_data_1 &= ~(0x04000000); < TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); < < mdelay(5); < 1074,1076d1013 < if (port_num == 2) < reg_data1 |= 0x30000; < 1107,1108d1043 < struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev; < unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q; 1110a1046,1047 > unsigned int curr_desc = > titan_ge_eth->tx_curr_desc_q; 1114,1115c1051,1052 < dma_map_single(device, skb->data, skb_headlen(skb), < DMA_TO_DEVICE); --- > pci_map_single(0, skb->data, skb_headlen(skb), > PCI_DMA_TODEVICE); 1133a1071,1083 > #ifndef TITAN_RX_NAPI > /* > * Coalescing for the Rx path > */ > static unsigned long titan_ge_rx_coal(unsigned long delay, int port) > { > TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay); > TITAN_GE_WRITE(0x5038, delay); > > return delay; > } > #endif > 1141d1090 < struct device *device = &titan_ge_device[port_num]->dev; 1190,1196d1138 < if (port_num == 2) { < titan_ge_eth->tx_desc_area = < (titan_ge_tx_desc *) (titan_ge_sram + 0x200); < < titan_ge_eth->tx_dma = TITAN_SRAM_BASE + 0x200; < } < 1231,1236d1172 < if (port_num == 2) { < titan_ge_eth->rx_desc_area = < (titan_ge_rx_desc *)(titan_ge_sram + 0x1200); < titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1200; < } < 1246c1182 < dma_free_coherent(device, titan_ge_eth->tx_desc_area_size, --- > pci_free_consistent(0, titan_ge_eth->tx_desc_area_size, 1278a1215,1225 > #ifndef TITAN_RX_NAPI > /* > * If NAPI is turned on, we disable Rx interrupts > * completely. So, we dont need coalescing then. Tx side > * coalescing set to very high value. Maybe, disable > * Tx side interrupts completely > */ > if (TITAN_GE_RX_COAL) { > titan_ge_eth->rx_int_coal = > titan_ge_rx_coal(TITAN_GE_RX_COAL, port_num); > } 1279a1227 > #endif 1408a1357,1395 > * Do the slowpath route. This route is kicked off > * when the IP header is misaligned. Grrr .. > */ > static int titan_ge_slowpath(struct sk_buff *skb, > titan_ge_packet *packet, > struct net_device *netdev) > { > struct sk_buff *copy_skb; > > copy_skb = dev_alloc_skb(packet->len + 2); > > if (!copy_skb) { > dev_kfree_skb_any(packet->skb); > return -1; > } > > copy_skb->dev = netdev; > skb_reserve(copy_skb, 2); > skb_put(copy_skb, packet->len); > > memcpy(copy_skb->data, skb->data, packet->len); > > /* Titan supports Rx checksum offload */ > copy_skb->ip_summed = CHECKSUM_HW; > copy_skb->csum = packet->checksum; > > copy_skb->protocol = eth_type_trans(copy_skb, netdev); > > dev_kfree_skb_any(packet->skb); > #ifdef TITAN_RX_NAPI > netif_receive_skb(copy_skb); > #else > netif_rx(copy_skb); > #endif > > return 0; > } > > /* 1436a1424 > #ifdef TITAN_RX_NAPI 1440c1428 < --- > #endif 1458a1447 > skb_put(skb, packet.len); 1460,1468c1449,1450 < skb_put(skb, packet.len - 2); < < /* < * Increment data pointer by two since thats where < * the MAC starts < */ < skb_reserve(skb, 2); < skb->protocol = eth_type_trans(skb, netdev); < netif_receive_skb(skb); --- > if (titan_ge_slowpath(skb, &packet, netdev) < 0) > goto out_next; 1469a1452 > #ifdef TITAN_RX_NAPI 1475a1459,1462 > #else > ack = titan_ge_rx_task(netdev, titan_ge_eth); > TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack); > #endif 1476a1464,1466 > out_next: > > #ifdef TITAN_RX_NAPI 1482a1473 > #endif 1488a1480,1481 > #ifdef TITAN_RX_NAPI > 1589a1583 > #endif 1600a1595 > MOD_DEC_USE_COUNT; 1646,1647c1641 < dma_free_coherent(&titan_ge_device[port_num]->dev, < titan_ge_eth->tx_desc_area_size, --- > pci_free_consistent(0, titan_ge_eth->tx_desc_area_size, 1693,1694c1687 < dma_free_coherent(&titan_ge_device[port_num]->dev, < titan_ge_eth->rx_desc_area_size, --- > pci_free_consistent(0, titan_ge_eth->rx_desc_area_size, 1754a1748,1749 > > return; 1760c1755 < static int titan_ge_set_mac_address(struct net_device *dev, void *addr) --- > int titan_ge_set_mac_address(struct net_device *netdev, void *addr) 1762,1765c1757 < titan_ge_port_info *tp = netdev_priv(dev); < struct sockaddr *sa = addr; < < memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); --- > int i; 1767,1769c1759,1760 < spin_lock_irq(&tp->lock); < titan_ge_update_mac_address(dev); < spin_unlock_irq(&tp->lock); --- > for (i = 0; i < 6; i++) > netdev->dev_addr[i] = ((unsigned char *) addr)[i + 2]; 1770a1762 > titan_ge_update_mac_address(netdev); 1784a1777,1835 > * Register the Titan GE with the kernel > */ > static int __init titan_ge_init_module(void) > { > unsigned int version, device; > > printk(KERN_NOTICE > "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n"); > > titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE); > if (!titan_ge_base) { > printk("Mapping Titan GE failed\n"); > goto out; > } > > device = TITAN_GE_READ(TITAN_GE_DEVICE_ID); > version = (device & 0x000f0000) >> 16; > device &= 0x0000ffff; > > printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version); > > #ifdef TITAN_RX_RING_IN_SRAM > titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE, > TITAN_SRAM_SIZE); > if (!titan_ge_sram) { > printk("Mapping Titan SRAM failed\n"); > goto out_unmap_ge; > } > #endif > > /* Register only one port */ > if (titan_ge_init(0)) > printk(KERN_ERR > "Error registering the TITAN Ethernet driver" > "for port 0 \n"); > > if (titan_ge_init(1)) > printk(KERN_ERR "Error registering the TITAN Ethernet" > "driver for port 1\n"); > > return 0; > > out_unmap_ge: > iounmap((void *)titan_ge_base); > > out: > return -ENOMEM; > } > > /* > * Unregister the Titan GE from the kernel > */ > static void __init titan_ge_cleanup_module(void) > { > iounmap((void *)titan_ge_sram); > iounmap((void *)titan_ge_base); > } > > /* 1878c1929 < static int __init titan_ge_probe(struct device *device) --- > static int titan_ge_init(int port) 1882d1932 < int port = to_platform_device(device)->id; 1901a1952 > #ifdef TITAN_RX_NAPI 1905c1956 < --- > #endif 1938a1990 > #ifdef TITAN_RX_NAPI 1939a1992,1994 > #else > printk(KERN_NOTICE "Rx and Tx Coalescing ON \n"); > #endif 2016,2131d2070 < static struct device_driver titan_soc_driver = { < .name = titan_string, < .bus = &platform_bus_type, < .probe = titan_ge_probe, < .remove = __devexit_p(titan_device_remove), < }; < < static void titan_platform_release (struct device *device) < { < struct platform_device *pldev; < < /* free device */ < pldev = to_platform_device (device); < kfree (pldev); < } < < /* < * Register the Titan GE with the kernel < */ < static int __init titan_ge_init_module(void) < { < struct platform_device *pldev; < unsigned int version, device; < int i; < < printk(KERN_NOTICE < "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n"); < < titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE); < if (!titan_ge_base) { < printk("Mapping Titan GE failed\n"); < goto out; < } < < device = TITAN_GE_READ(TITAN_GE_DEVICE_ID); < version = (device & 0x000f0000) >> 16; < device &= 0x0000ffff; < < printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version); < < #ifdef TITAN_RX_RING_IN_SRAM < titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE, < TITAN_SRAM_SIZE); < if (!titan_ge_sram) { < printk("Mapping Titan SRAM failed\n"); < goto out_unmap_ge; < } < #endif < < if (driver_register(&titan_soc_driver)) { < printk(KERN_ERR "Driver registration failed\n"); < goto out_unmap_sram; < } < < for (i = 0; i < 3; i++) { < titan_ge_device[i] = NULL; < < if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL))) < continue; < < memset (pldev, 0, sizeof (*pldev)); < pldev->name = titan_string; < pldev->id = i; < pldev->dev.release = titan_platform_release; < titan_ge_device[i] = pldev; < < if (platform_device_register (pldev)) { < kfree (pldev); < titan_ge_device[i] = NULL; < continue; < } < < if (!pldev->dev.driver) { < /* < * The driver was not bound to this device, there was < * no hardware at this address. Unregister it, as the < * release fuction will take care of freeing the < * allocated structure < */ < titan_ge_device[i] = NULL; < platform_device_unregister (pldev); < } < } < < return 0; < < out_unmap_sram: < iounmap((void *)titan_ge_sram); < < out_unmap_ge: < iounmap((void *)titan_ge_base); < < out: < return -ENOMEM; < } < < /* < * Unregister the Titan GE from the kernel < */ < static void __exit titan_ge_cleanup_module(void) < { < int i; < < driver_unregister(&titan_soc_driver); < < for (i = 0; i < 3; i++) { < if (titan_ge_device[i]) { < platform_device_unregister (titan_ge_device[i]); < titan_ge_device[i] = NULL; < } < } < < iounmap((void *)titan_ge_sram); < iounmap((void *)titan_ge_base); < } < --------------070608030705010706000200 Content-Type: text/plain; name="titan_ge.h.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="titan_ge.h.diff" 103a104,106 > /* Support for Rx side NAPI */ > #define TITAN_RX_NAPI > --------------070608030705010706000200-- From mlachwani@mvista.com Thu Nov 18 21:42:26 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 21:42:30 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:57839 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Thu, 18 Nov 2004 21:42:26 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 9001F185C2; Thu, 18 Nov 2004 13:42:22 -0800 (PST) Message-ID: <419D173E.6050602@mvista.com> Date: Thu, 18 Nov 2004 13:42:22 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: TheNop Cc: linux-mips@linux-mips.org Subject: Re: Titan ethernet driver broken References: <419D03DE.8090403@gmx.net> <419D04AA.50508@mvista.com> <419D171E.5040507@gmx.net> In-Reply-To: <419D171E.5040507@gmx.net> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6361 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 114 Lines: 8 Hello ! Can you please send the diffs using "diff -u" ? It would make the reading easy Thanks Manish Lachwani From TheNop@gmx.net Thu Nov 18 21:48:57 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 21:49:03 +0000 (GMT) Received: from pop.gmx.net ([IPv6:::ffff:213.165.64.20]:60623 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Thu, 18 Nov 2004 21:48:57 +0000 Received: (qmail 12052 invoked by uid 65534); 18 Nov 2004 21:48:51 -0000 Received: from c210132.adsl.hansenet.de (EHLO [192.168.0.1]) (213.39.210.132) by mail.gmx.net (mp008) with SMTP; 18 Nov 2004 22:48:51 +0100 X-Authenticated: #947741 Message-ID: <419D1A2D.5000009@gmx.net> Date: Thu, 18 Nov 2004 22:54:53 +0100 From: TheNop User-Agent: Mozilla Thunderbird 0.7.3 (Windows/20040803) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: Titan ethernet driver broken References: <419D03DE.8090403@gmx.net> <419D04AA.50508@mvista.com> <419D171E.5040507@gmx.net> <419D173E.6050602@mvista.com> In-Reply-To: <419D173E.6050602@mvista.com> Content-Type: multipart/mixed; boundary="------------020102030605070102020905" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6362 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: TheNop@gmx.net Precedence: bulk X-list: linux-mips Content-Length: 16901 Lines: 686 This is a multi-part message in MIME format. --------------020102030605070102020905 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Manish Lachwani wrote: > Hello ! > > Can you please send the diffs using "diff -u" ? It would make the > reading easy > > Thanks > Manish Lachwani > > > For sure. Best regards TheNop --------------020102030605070102020905 Content-Type: text/plain; name="module.h.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="module.h.diff" 47,60d46 < struct module; < < struct module_attribute { < struct attribute attr; < ssize_t (*show)(struct module *, char *); < ssize_t (*store)(struct module *, const char *, size_t count); < }; < < struct module_kobject < { < struct kobject kobj; < struct module *mod; < }; < 76,77d61 < extern struct subsystem module_subsys; < 160c144,145 < local headers in "srcversion". --- > local headers to the end. Use MODULE_VERSION("") if you want just > this. Macro includes room for this. 162c147,148 < #define MODULE_VERSION(_version) MODULE_INFO(version, _version) --- > #define MODULE_VERSION(_version) \ > MODULE_INFO(version, _version "\0xxxxxxxxxxxxxxxxxxxxxxxx") 224a211,227 > /* sysfs stuff */ > struct module_attribute > { > struct attribute attr; > struct kernel_param *param; > }; > > struct module_kobject > { > /* Everyone should have one of these. */ > struct kobject kobj; > > /* We always have refcnt, we may have others from module_param(). */ > unsigned int num_attributes; > struct module_attribute attr[0]; > }; > 240d242 < struct param_kobject; 254d255 < struct param_kobject *params_kobject; 305a307,309 > > /* Fake kernel param for refcnt. */ > struct kernel_param refcnt_param; 444,448d447 < < struct device_driver; < void module_add_driver(struct module *, struct device_driver *); < void module_remove_driver(struct device_driver *); < 538,549d536 < < struct device_driver; < struct module; < < static inline void module_add_driver(struct module *module, struct device_driver *driver) < { < } < < static inline void module_remove_driver(struct device_driver *driver) < { < } < 561,562d547 < < static inline void __deprecated MODULE_PARM_(void) { } 567c552,572 < { __stringify(var), type, &MODULE_PARM_ }; --- > { __stringify(var), type }; > > static inline void __deprecated MOD_INC_USE_COUNT(struct module *module) > { > __unsafe(module); > > #if defined(CONFIG_MODULE_UNLOAD) && defined(MODULE) > local_inc(&module->ref[get_cpu()].count); > put_cpu(); > #else > (void)try_module_get(module); > #endif > } > > static inline void __deprecated MOD_DEC_USE_COUNT(struct module *module) > { > module_put(module); > } > > #define MOD_INC_USE_COUNT MOD_INC_USE_COUNT(THIS_MODULE) > #define MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT(THIS_MODULE) 569c574,576 < #define MODULE_PARM(var,type) static void __attribute__((__unused__)) *__parm_##var = &MODULE_PARM_; --- > #define MODULE_PARM(var,type) > #define MOD_INC_USE_COUNT do { } while (0) > #define MOD_DEC_USE_COUNT do { } while (0) 576,582c583,587 < extern void __deprecated inter_module_register(const char *, < struct module *, const void *); < extern void __deprecated inter_module_unregister(const char *); < extern const void * __deprecated inter_module_get(const char *); < extern const void * __deprecated inter_module_get_request(const char *, < const char *); < extern void __deprecated inter_module_put(const char *); --- > extern void inter_module_register(const char *, struct module *, const void *); > extern void inter_module_unregister(const char *); > extern const void *inter_module_get(const char *); > extern const void *inter_module_get_request(const char *, const char *); > extern void inter_module_put(const char *); --------------020102030605070102020905 Content-Type: text/plain; name="titan_ge.c.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="titan_ge.c.diff" 50c50 < #include --- > #include 52a53 > #include 53a55,56 > #include > #include 61a65 > #include 97a102 > static int titan_ge_set_mac_address(struct net_device *, void *); 105a111 > static int titan_ge_init(int); 119a126 > #ifdef TITAN_RX_NAPI 120a128 > #endif 124,125d131 < static struct platform_device *titan_ge_device[3]; < 132,133d137 < static char titan_string[] = "titan"; < 450a455 > #ifdef TITAN_RX_NAPI 468,470d472 < if (port_num == 2) < ack &= ~(0x30000); < 476a479,481 > #else > titan_ge_free_tx_queue(titan_ge_eth); > titan_ge_receive_queue(netdev, 0); 477a483 > #endif 612,613d617 < struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev; < volatile titan_ge_rx_desc *rx_desc; 614a619 > volatile titan_ge_rx_desc *rx_desc; 621,622c626,627 < dma_map_single(device, skb->data, TITAN_GE_JUMBO_BUFSIZE - 2, < DMA_FROM_DEVICE); --- > pci_map_single(0, skb->data, TITAN_GE_JUMBO_BUFSIZE - 2, > PCI_DMA_FROMDEVICE); 625,626c630,631 < dma_map_single(device, skb->data, TITAN_GE_STD_BUFSIZE - 2, < DMA_FROM_DEVICE); --- > pci_map_single(0, skb->data, TITAN_GE_STD_BUFSIZE - 2, > PCI_DMA_FROMDEVICE); 723d727 < unsigned long reg_data_1; 737c741 < --- > #ifdef TITAN_RX_NAPI 739c743,745 < --- > #else > TITAN_GE_WRITE(0x000c, 0x00000100); /* No WCIMODE */ > #endif 748a755 > #ifdef TITAN_RX_NAPI 750a758 > #endif 905,950d912 < /* < * Titan 1.2 revision does support port #2 < */ < if (port_num == 2) { < /* < * Put the descriptors in the SRAM < */ < reg_data = TITAN_GE_READ(0x48a0); < < reg_data |= 0x100000; < reg_data |= (0xff << 10) | (2*(0xff + 1)); < < TITAN_GE_WRITE(0x48a0, reg_data); < /* < * BAV2,BAV and DAV settings for the Rx FIFO < */ < reg_data1 = TITAN_GE_READ(0x48a4); < reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); < TITAN_GE_WRITE(0x48a4, reg_data1); < < reg_data &= ~(0x00100000); < reg_data |= 0x200000; < < TITAN_GE_WRITE(0x48a0, reg_data); < < reg_data = TITAN_GE_READ(0x4958); < reg_data |= 0x100000; < < TITAN_GE_WRITE(0x4958, reg_data); < reg_data |= (0xff << 10) | (2*(0xff + 1)); < TITAN_GE_WRITE(0x4958, reg_data); < < /* < * BAV2, BAV and DAV settings for the Tx FIFO < */ < reg_data1 = TITAN_GE_READ(0x495c); < reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); < < TITAN_GE_WRITE(0x495c, reg_data1); < < reg_data &= ~(0x00100000); < reg_data |= 0x200000; < < TITAN_GE_WRITE(0x4958, reg_data); < } < 995,1016d956 < < /* < * This is the 1.2 revision of the chip. It has fix for the < * IP header alignment. Now, the IP header begins at an < * aligned address and this wont need an extra copy in the < * driver. This performance drawback existed in the previous < * versions of the silicon < */ < reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12)); < reg_data_1 |= 0x40000000; < TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); < < reg_data_1 |= 0x04000000; < TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); < < mdelay(5); < < reg_data_1 &= ~(0x04000000); < TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); < < mdelay(5); < 1074,1076d1013 < if (port_num == 2) < reg_data1 |= 0x30000; < 1107,1108d1043 < struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev; < unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q; 1110a1046,1047 > unsigned int curr_desc = > titan_ge_eth->tx_curr_desc_q; 1114,1115c1051,1052 < dma_map_single(device, skb->data, skb_headlen(skb), < DMA_TO_DEVICE); --- > pci_map_single(0, skb->data, skb_headlen(skb), > PCI_DMA_TODEVICE); 1133a1071,1083 > #ifndef TITAN_RX_NAPI > /* > * Coalescing for the Rx path > */ > static unsigned long titan_ge_rx_coal(unsigned long delay, int port) > { > TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay); > TITAN_GE_WRITE(0x5038, delay); > > return delay; > } > #endif > 1141d1090 < struct device *device = &titan_ge_device[port_num]->dev; 1190,1196d1138 < if (port_num == 2) { < titan_ge_eth->tx_desc_area = < (titan_ge_tx_desc *) (titan_ge_sram + 0x200); < < titan_ge_eth->tx_dma = TITAN_SRAM_BASE + 0x200; < } < 1231,1236d1172 < if (port_num == 2) { < titan_ge_eth->rx_desc_area = < (titan_ge_rx_desc *)(titan_ge_sram + 0x1200); < titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1200; < } < 1246c1182 < dma_free_coherent(device, titan_ge_eth->tx_desc_area_size, --- > pci_free_consistent(0, titan_ge_eth->tx_desc_area_size, 1278a1215,1225 > #ifndef TITAN_RX_NAPI > /* > * If NAPI is turned on, we disable Rx interrupts > * completely. So, we dont need coalescing then. Tx side > * coalescing set to very high value. Maybe, disable > * Tx side interrupts completely > */ > if (TITAN_GE_RX_COAL) { > titan_ge_eth->rx_int_coal = > titan_ge_rx_coal(TITAN_GE_RX_COAL, port_num); > } 1279a1227 > #endif 1408a1357,1395 > * Do the slowpath route. This route is kicked off > * when the IP header is misaligned. Grrr .. > */ > static int titan_ge_slowpath(struct sk_buff *skb, > titan_ge_packet *packet, > struct net_device *netdev) > { > struct sk_buff *copy_skb; > > copy_skb = dev_alloc_skb(packet->len + 2); > > if (!copy_skb) { > dev_kfree_skb_any(packet->skb); > return -1; > } > > copy_skb->dev = netdev; > skb_reserve(copy_skb, 2); > skb_put(copy_skb, packet->len); > > memcpy(copy_skb->data, skb->data, packet->len); > > /* Titan supports Rx checksum offload */ > copy_skb->ip_summed = CHECKSUM_HW; > copy_skb->csum = packet->checksum; > > copy_skb->protocol = eth_type_trans(copy_skb, netdev); > > dev_kfree_skb_any(packet->skb); > #ifdef TITAN_RX_NAPI > netif_receive_skb(copy_skb); > #else > netif_rx(copy_skb); > #endif > > return 0; > } > > /* 1436a1424 > #ifdef TITAN_RX_NAPI 1440c1428 < --- > #endif 1458a1447 > skb_put(skb, packet.len); 1460,1468c1449,1450 < skb_put(skb, packet.len - 2); < < /* < * Increment data pointer by two since thats where < * the MAC starts < */ < skb_reserve(skb, 2); < skb->protocol = eth_type_trans(skb, netdev); < netif_receive_skb(skb); --- > if (titan_ge_slowpath(skb, &packet, netdev) < 0) > goto out_next; 1469a1452 > #ifdef TITAN_RX_NAPI 1475a1459,1462 > #else > ack = titan_ge_rx_task(netdev, titan_ge_eth); > TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack); > #endif 1476a1464,1466 > out_next: > > #ifdef TITAN_RX_NAPI 1482a1473 > #endif 1488a1480,1481 > #ifdef TITAN_RX_NAPI > 1589a1583 > #endif 1600a1595 > MOD_DEC_USE_COUNT; 1646,1647c1641 < dma_free_coherent(&titan_ge_device[port_num]->dev, < titan_ge_eth->tx_desc_area_size, --- > pci_free_consistent(0, titan_ge_eth->tx_desc_area_size, 1693,1694c1687 < dma_free_coherent(&titan_ge_device[port_num]->dev, < titan_ge_eth->rx_desc_area_size, --- > pci_free_consistent(0, titan_ge_eth->rx_desc_area_size, 1754a1748,1749 > > return; 1760c1755 < static int titan_ge_set_mac_address(struct net_device *dev, void *addr) --- > int titan_ge_set_mac_address(struct net_device *netdev, void *addr) 1762,1765c1757 < titan_ge_port_info *tp = netdev_priv(dev); < struct sockaddr *sa = addr; < < memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); --- > int i; 1767,1769c1759,1760 < spin_lock_irq(&tp->lock); < titan_ge_update_mac_address(dev); < spin_unlock_irq(&tp->lock); --- > for (i = 0; i < 6; i++) > netdev->dev_addr[i] = ((unsigned char *) addr)[i + 2]; 1770a1762 > titan_ge_update_mac_address(netdev); 1784a1777,1835 > * Register the Titan GE with the kernel > */ > static int __init titan_ge_init_module(void) > { > unsigned int version, device; > > printk(KERN_NOTICE > "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n"); > > titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE); > if (!titan_ge_base) { > printk("Mapping Titan GE failed\n"); > goto out; > } > > device = TITAN_GE_READ(TITAN_GE_DEVICE_ID); > version = (device & 0x000f0000) >> 16; > device &= 0x0000ffff; > > printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version); > > #ifdef TITAN_RX_RING_IN_SRAM > titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE, > TITAN_SRAM_SIZE); > if (!titan_ge_sram) { > printk("Mapping Titan SRAM failed\n"); > goto out_unmap_ge; > } > #endif > > /* Register only one port */ > if (titan_ge_init(0)) > printk(KERN_ERR > "Error registering the TITAN Ethernet driver" > "for port 0 \n"); > > if (titan_ge_init(1)) > printk(KERN_ERR "Error registering the TITAN Ethernet" > "driver for port 1\n"); > > return 0; > > out_unmap_ge: > iounmap((void *)titan_ge_base); > > out: > return -ENOMEM; > } > > /* > * Unregister the Titan GE from the kernel > */ > static void __init titan_ge_cleanup_module(void) > { > iounmap((void *)titan_ge_sram); > iounmap((void *)titan_ge_base); > } > > /* 1878c1929 < static int __init titan_ge_probe(struct device *device) --- > static int titan_ge_init(int port) 1882d1932 < int port = to_platform_device(device)->id; 1901a1952 > #ifdef TITAN_RX_NAPI 1905c1956 < --- > #endif 1938a1990 > #ifdef TITAN_RX_NAPI 1939a1992,1994 > #else > printk(KERN_NOTICE "Rx and Tx Coalescing ON \n"); > #endif 2016,2131d2070 < static struct device_driver titan_soc_driver = { < .name = titan_string, < .bus = &platform_bus_type, < .probe = titan_ge_probe, < .remove = __devexit_p(titan_device_remove), < }; < < static void titan_platform_release (struct device *device) < { < struct platform_device *pldev; < < /* free device */ < pldev = to_platform_device (device); < kfree (pldev); < } < < /* < * Register the Titan GE with the kernel < */ < static int __init titan_ge_init_module(void) < { < struct platform_device *pldev; < unsigned int version, device; < int i; < < printk(KERN_NOTICE < "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n"); < < titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE); < if (!titan_ge_base) { < printk("Mapping Titan GE failed\n"); < goto out; < } < < device = TITAN_GE_READ(TITAN_GE_DEVICE_ID); < version = (device & 0x000f0000) >> 16; < device &= 0x0000ffff; < < printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version); < < #ifdef TITAN_RX_RING_IN_SRAM < titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE, < TITAN_SRAM_SIZE); < if (!titan_ge_sram) { < printk("Mapping Titan SRAM failed\n"); < goto out_unmap_ge; < } < #endif < < if (driver_register(&titan_soc_driver)) { < printk(KERN_ERR "Driver registration failed\n"); < goto out_unmap_sram; < } < < for (i = 0; i < 3; i++) { < titan_ge_device[i] = NULL; < < if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL))) < continue; < < memset (pldev, 0, sizeof (*pldev)); < pldev->name = titan_string; < pldev->id = i; < pldev->dev.release = titan_platform_release; < titan_ge_device[i] = pldev; < < if (platform_device_register (pldev)) { < kfree (pldev); < titan_ge_device[i] = NULL; < continue; < } < < if (!pldev->dev.driver) { < /* < * The driver was not bound to this device, there was < * no hardware at this address. Unregister it, as the < * release fuction will take care of freeing the < * allocated structure < */ < titan_ge_device[i] = NULL; < platform_device_unregister (pldev); < } < } < < return 0; < < out_unmap_sram: < iounmap((void *)titan_ge_sram); < < out_unmap_ge: < iounmap((void *)titan_ge_base); < < out: < return -ENOMEM; < } < < /* < * Unregister the Titan GE from the kernel < */ < static void __exit titan_ge_cleanup_module(void) < { < int i; < < driver_unregister(&titan_soc_driver); < < for (i = 0; i < 3; i++) { < if (titan_ge_device[i]) { < platform_device_unregister (titan_ge_device[i]); < titan_ge_device[i] = NULL; < } < } < < iounmap((void *)titan_ge_sram); < iounmap((void *)titan_ge_base); < } < --------------020102030605070102020905 Content-Type: text/plain; name="titan_ge.h.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="titan_ge.h.diff" 103a104,106 > /* Support for Rx side NAPI */ > #define TITAN_RX_NAPI > --------------020102030605070102020905-- From TheNop@gmx.net Thu Nov 18 22:11:36 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 22:11:45 +0000 (GMT) Received: from mail.gmx.net ([IPv6:::ffff:213.165.64.20]:6574 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Thu, 18 Nov 2004 22:11:36 +0000 Received: (qmail 17960 invoked by uid 65534); 18 Nov 2004 22:11:29 -0000 Received: from c210132.adsl.hansenet.de (EHLO [192.168.0.1]) (213.39.210.132) by mail.gmx.net (mp006) with SMTP; 18 Nov 2004 23:11:29 +0100 X-Authenticated: #947741 Message-ID: <419D1F76.6010603@gmx.net> Date: Thu, 18 Nov 2004 23:17:26 +0100 From: TheNop User-Agent: Mozilla Thunderbird 0.7.3 (Windows/20040803) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: Titan ethernet driver broken References: <419D03DE.8090403@gmx.net> <419D04AA.50508@mvista.com> <419D171E.5040507@gmx.net> <419D173E.6050602@mvista.com> <419D1A2D.5000009@gmx.net> In-Reply-To: <419D1A2D.5000009@gmx.net> Content-Type: multipart/mixed; boundary="------------010709030108050202000102" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6363 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: TheNop@gmx.net Precedence: bulk X-list: linux-mips Content-Length: 25775 Lines: 1002 This is a multi-part message in MIME format. --------------010709030108050202000102 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit TheNop wrote: > Manish Lachwani wrote: > >> Hello ! >> >> Can you please send the diffs using "diff -u" ? It would make the >> reading easy >> >> Thanks >> Manish Lachwani >> >> >> > For sure. > > Best regards > TheNop > Ups, something went wrong. Next try. CU --------------010709030108050202000102 Content-Type: text/plain; name="module.h.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="module.h.diff" --- linux/include/linux/module.h 2004-11-15 12:49:39.000000000 +0100 +++ linux_2_6_8_1/include/linux/module.h 2004-06-28 23:04:16.000000000 +0200 @@ -44,20 +44,6 @@ char name[MODULE_NAME_LEN]; }; -struct module; - -struct module_attribute { - struct attribute attr; - ssize_t (*show)(struct module *, char *); - ssize_t (*store)(struct module *, const char *, size_t count); -}; - -struct module_kobject -{ - struct kobject kobj; - struct module *mod; -}; - /* These are either module local, or the kernel's dummy ones. */ extern int init_module(void); extern void cleanup_module(void); @@ -73,8 +59,6 @@ struct exception_table_entry *finish); void sort_main_extable(void); -extern struct subsystem module_subsys; - #ifdef MODULE #define ___module_cat(a,b) __mod_ ## a ## b #define __module_cat(a,b) ___module_cat(a,b) @@ -157,9 +141,11 @@ customizations, eg "rh3" or "rusty1". Using this automatically adds a checksum of the .c files and the - local headers in "srcversion". + local headers to the end. Use MODULE_VERSION("") if you want just + this. Macro includes room for this. */ -#define MODULE_VERSION(_version) MODULE_INFO(version, _version) +#define MODULE_VERSION(_version) \ + MODULE_INFO(version, _version "\0xxxxxxxxxxxxxxxxxxxxxxxx") /* Given an address, look for it in the exception tables */ const struct exception_table_entry *search_exception_tables(unsigned long add); @@ -222,6 +208,23 @@ MODULE_STATE_GOING, }; +/* sysfs stuff */ +struct module_attribute +{ + struct attribute attr; + struct kernel_param *param; +}; + +struct module_kobject +{ + /* Everyone should have one of these. */ + struct kobject kobj; + + /* We always have refcnt, we may have others from module_param(). */ + unsigned int num_attributes; + struct module_attribute attr[0]; +}; + /* Similar stuff for section attributes. */ #define MODULE_SECT_NAME_LEN 32 struct module_sect_attr @@ -237,7 +240,6 @@ struct module_sect_attr attrs[0]; }; -struct param_kobject; struct module { @@ -251,7 +253,6 @@ /* Sysfs stuff. */ struct module_kobject *mkobj; - struct param_kobject *params_kobject; /* Exported symbols */ const struct kernel_symbol *syms; @@ -303,6 +304,9 @@ /* Destruction function. */ void (*exit)(void); + + /* Fake kernel param for refcnt. */ + struct kernel_param refcnt_param; #endif #ifdef CONFIG_KALLSYMS @@ -441,11 +445,6 @@ int unregister_module_notifier(struct notifier_block * nb); extern void print_modules(void); - -struct device_driver; -void module_add_driver(struct module *, struct device_driver *); -void module_remove_driver(struct device_driver *); - #else /* !CONFIG_MODULES... */ #define EXPORT_SYMBOL(sym) #define EXPORT_SYMBOL_GPL(sym) @@ -535,18 +534,6 @@ static inline void print_modules(void) { } - -struct device_driver; -struct module; - -static inline void module_add_driver(struct module *module, struct device_driver *driver) -{ -} - -static inline void module_remove_driver(struct device_driver *driver) -{ -} - #endif /* CONFIG_MODULES */ #define symbol_request(x) try_then_request_module(symbol_get(x), "symbol:" #x) @@ -558,27 +545,45 @@ char type[64-sizeof(void *)]; void *addr; }; - -static inline void __deprecated MODULE_PARM_(void) { } #ifdef MODULE /* DEPRECATED: Do not use. */ #define MODULE_PARM(var,type) \ struct obsolete_modparm __parm_##var __attribute__((section("__obsparm"))) = \ -{ __stringify(var), type, &MODULE_PARM_ }; +{ __stringify(var), type }; + +static inline void __deprecated MOD_INC_USE_COUNT(struct module *module) +{ + __unsafe(module); + +#if defined(CONFIG_MODULE_UNLOAD) && defined(MODULE) + local_inc(&module->ref[get_cpu()].count); + put_cpu(); +#else + (void)try_module_get(module); +#endif +} + +static inline void __deprecated MOD_DEC_USE_COUNT(struct module *module) +{ + module_put(module); +} + +#define MOD_INC_USE_COUNT MOD_INC_USE_COUNT(THIS_MODULE) +#define MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT(THIS_MODULE) #else -#define MODULE_PARM(var,type) static void __attribute__((__unused__)) *__parm_##var = &MODULE_PARM_; +#define MODULE_PARM(var,type) +#define MOD_INC_USE_COUNT do { } while (0) +#define MOD_DEC_USE_COUNT do { } while (0) #endif #define __MODULE_STRING(x) __stringify(x) /* Use symbol_get and symbol_put instead. You'll thank me. */ #define HAVE_INTER_MODULE -extern void __deprecated inter_module_register(const char *, - struct module *, const void *); -extern void __deprecated inter_module_unregister(const char *); -extern const void * __deprecated inter_module_get(const char *); -extern const void * __deprecated inter_module_get_request(const char *, - const char *); -extern void __deprecated inter_module_put(const char *); +extern void inter_module_register(const char *, struct module *, const void *); +extern void inter_module_unregister(const char *); +extern const void *inter_module_get(const char *); +extern const void *inter_module_get_request(const char *, const char *); +extern void inter_module_put(const char *); #endif /* _LINUX_MODULE_H */ --------------010709030108050202000102 Content-Type: text/plain; name="titan_ge.c.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="titan_ge.c.diff" --- linux/drivers/net/titan_ge.c 2004-11-17 04:08:25.000000000 +0100 +++ linux_2_6_8_1/drivers/net/titan_ge.c 2004-08-19 22:31:47.000000000 +0200 @@ -47,10 +47,13 @@ */ #include -#include +#include #include #include +#include #include +#include +#include #include #include #include @@ -59,6 +62,7 @@ #include #include #include +#include #include #include @@ -95,6 +99,7 @@ static int titan_ge_open(struct net_device *); static int titan_ge_start_xmit(struct sk_buff *, struct net_device *); static int titan_ge_stop(struct net_device *); +static int titan_ge_set_mac_address(struct net_device *, void *); static unsigned long titan_ge_tx_coal(unsigned long, int); @@ -103,6 +108,7 @@ static int titan_ge_rx_task(struct net_device *, titan_ge_port_info *); static int titan_ge_port_start(struct net_device *, titan_ge_port_info *); +static int titan_ge_init(int); static int titan_ge_return_tx_desc(titan_ge_port_info *, int); /* @@ -117,20 +123,18 @@ */ static unsigned int oom_flag; +#ifdef TITAN_RX_NAPI static int titan_ge_poll(struct net_device *netdev, int *budget); +#endif static int titan_ge_receive_queue(struct net_device *, unsigned int); -static struct platform_device *titan_ge_device[3]; - /* MAC Address */ extern unsigned char titan_ge_mac_addr_base[6]; unsigned long titan_ge_base; static unsigned long titan_ge_sram; -static char titan_string[] = "titan"; - /* * The Titan GE has two alignment requirements: * -> skb->data to be cacheline aligned (32 byte) @@ -448,6 +452,7 @@ #endif titan_ge_free_tx_queue(titan_ge_eth); +#ifdef TITAN_RX_NAPI /* Handle the Rx next */ #ifdef CONFIG_SMP if ( (eth_int_cause1 & 0x10101) || @@ -465,16 +470,17 @@ if (port_num == 1) ack &= ~(0x300); - if (port_num == 2) - ack &= ~(0x30000); - /* Interrupts have been disabled */ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack); __netif_rx_schedule(netdev); } } +#else + titan_ge_free_tx_queue(titan_ge_eth); + titan_ge_receive_queue(netdev, 0); +#endif /* Handle error interrupts */ if (eth_int_cause_error && (eth_int_cause_error != 0x2)) { printk(KERN_ERR @@ -609,21 +615,20 @@ static int titan_ge_rx_return_buff(titan_ge_port_info * titan_ge_port, struct sk_buff *skb) { - struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev; - volatile titan_ge_rx_desc *rx_desc; int rx_used_desc; + volatile titan_ge_rx_desc *rx_desc; rx_used_desc = titan_ge_port->rx_used_desc_q; rx_desc = &(titan_ge_port->rx_desc_area[rx_used_desc]); #ifdef TITAN_GE_JUMBO_FRAMES rx_desc->buffer_addr = - dma_map_single(device, skb->data, TITAN_GE_JUMBO_BUFSIZE - 2, - DMA_FROM_DEVICE); + pci_map_single(0, skb->data, TITAN_GE_JUMBO_BUFSIZE - 2, + PCI_DMA_FROMDEVICE); #else rx_desc->buffer_addr = - dma_map_single(device, skb->data, TITAN_GE_STD_BUFSIZE - 2, - DMA_FROM_DEVICE); + pci_map_single(0, skb->data, TITAN_GE_STD_BUFSIZE - 2, + PCI_DMA_FROMDEVICE); #endif titan_ge_port->rx_skb[rx_used_desc] = skb; @@ -720,7 +725,6 @@ volatile unsigned long reg_data, reg_data1; int port_num = titan_port->port_num; int count = 0; - unsigned long reg_data_1; if (config_done == 0) { reg_data = TITAN_GE_READ(0x0004); @@ -734,9 +738,11 @@ reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1); reg_data |= 0x00000700; reg_data &= ~(0x00800000); /* Fencing */ - +#ifdef TITAN_RX_NAPI TITAN_GE_WRITE(0x000c, 0x00001100); - +#else + TITAN_GE_WRITE(0x000c, 0x00000100); /* No WCIMODE */ +#endif TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data); /* Set the CPU Resource Limit register */ @@ -746,8 +752,10 @@ TITAN_GE_WRITE(0x0068, 0x4); } +#ifdef TITAN_RX_NAPI titan_port->tx_threshold = 0; titan_port->rx_threshold = 0; +#endif /* We need to write the descriptors for Tx and Rx */ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)), @@ -902,52 +910,6 @@ TITAN_GE_WRITE(0x494c, reg_data); } - /* - * Titan 1.2 revision does support port #2 - */ - if (port_num == 2) { - /* - * Put the descriptors in the SRAM - */ - reg_data = TITAN_GE_READ(0x48a0); - - reg_data |= 0x100000; - reg_data |= (0xff << 10) | (2*(0xff + 1)); - - TITAN_GE_WRITE(0x48a0, reg_data); - /* - * BAV2,BAV and DAV settings for the Rx FIFO - */ - reg_data1 = TITAN_GE_READ(0x48a4); - reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); - TITAN_GE_WRITE(0x48a4, reg_data1); - - reg_data &= ~(0x00100000); - reg_data |= 0x200000; - - TITAN_GE_WRITE(0x48a0, reg_data); - - reg_data = TITAN_GE_READ(0x4958); - reg_data |= 0x100000; - - TITAN_GE_WRITE(0x4958, reg_data); - reg_data |= (0xff << 10) | (2*(0xff + 1)); - TITAN_GE_WRITE(0x4958, reg_data); - - /* - * BAV2, BAV and DAV settings for the Tx FIFO - */ - reg_data1 = TITAN_GE_READ(0x495c); - reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); - - TITAN_GE_WRITE(0x495c, reg_data1); - - reg_data &= ~(0x00100000); - reg_data |= 0x200000; - - TITAN_GE_WRITE(0x4958, reg_data); - } - if (port_num == 2) { reg_data = TITAN_GE_READ(0x48a0); @@ -992,28 +954,6 @@ * Step 3: TRTG block enable */ reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12)); - - /* - * This is the 1.2 revision of the chip. It has fix for the - * IP header alignment. Now, the IP header begins at an - * aligned address and this wont need an extra copy in the - * driver. This performance drawback existed in the previous - * versions of the silicon - */ - reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12)); - reg_data_1 |= 0x40000000; - TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); - - reg_data_1 |= 0x04000000; - TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); - - mdelay(5); - - reg_data_1 &= ~(0x04000000); - TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); - - mdelay(5); - reg_data |= 0x0001; TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data); @@ -1071,9 +1011,6 @@ reg_data1 |= 0x300; } - if (port_num == 2) - reg_data1 |= 0x30000; - TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1); TITAN_GE_WRITE(0x003c, 0x300); @@ -1104,15 +1041,15 @@ static void titan_ge_tx_queue(titan_ge_port_info * titan_ge_eth, struct sk_buff * skb) { - struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev; - unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q; volatile titan_ge_tx_desc *tx_curr; int port_num = titan_ge_eth->port_num; + unsigned int curr_desc = + titan_ge_eth->tx_curr_desc_q; tx_curr = &(titan_ge_eth->tx_desc_area[curr_desc]); tx_curr->buffer_addr = - dma_map_single(device, skb->data, skb_headlen(skb), - DMA_TO_DEVICE); + pci_map_single(0, skb->data, skb_headlen(skb), + PCI_DMA_TODEVICE); titan_ge_eth->tx_skb[curr_desc] = (struct sk_buff *) skb; tx_curr->buffer_len = skb_headlen(skb); @@ -1131,6 +1068,19 @@ &titan_ge_eth->tx_desc_area[titan_ge_eth->tx_curr_desc_q]); } +#ifndef TITAN_RX_NAPI +/* + * Coalescing for the Rx path + */ +static unsigned long titan_ge_rx_coal(unsigned long delay, int port) +{ + TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay); + TITAN_GE_WRITE(0x5038, delay); + + return delay; +} +#endif + /* * Actually does the open of the Ethernet device */ @@ -1138,7 +1088,6 @@ { titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); unsigned int port_num = titan_ge_eth->port_num; - struct device *device = &titan_ge_device[port_num]->dev; unsigned int size, phy_reg; unsigned long reg_data; int err = 0; @@ -1187,13 +1136,6 @@ titan_ge_eth->tx_dma = TITAN_SRAM_BASE + 0x100; } - if (port_num == 2) { - titan_ge_eth->tx_desc_area = - (titan_ge_tx_desc *) (titan_ge_sram + 0x200); - - titan_ge_eth->tx_dma = TITAN_SRAM_BASE + 0x200; - } - if (!titan_ge_eth->tx_desc_area) { printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes) for port %d\n", @@ -1228,12 +1170,6 @@ titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1100; } - if (port_num == 2) { - titan_ge_eth->rx_desc_area = - (titan_ge_rx_desc *)(titan_ge_sram + 0x1200); - titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1200; - } - if (!titan_ge_eth->rx_desc_area) { printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n", @@ -1243,7 +1179,7 @@ "%s: Freeing previously allocated TX queues...", netdev->name); - dma_free_coherent(device, titan_ge_eth->tx_desc_area_size, + pci_free_consistent(0, titan_ge_eth->tx_desc_area_size, (void *) titan_ge_eth->tx_desc_area, titan_ge_eth->tx_dma); @@ -1276,7 +1212,19 @@ * (8 x 64 nanoseconds) to determine when an interrupt should * be sent to the CPU. */ +#ifndef TITAN_RX_NAPI + /* + * If NAPI is turned on, we disable Rx interrupts + * completely. So, we dont need coalescing then. Tx side + * coalescing set to very high value. Maybe, disable + * Tx side interrupts completely + */ + if (TITAN_GE_RX_COAL) { + titan_ge_eth->rx_int_coal = + titan_ge_rx_coal(TITAN_GE_RX_COAL, port_num); + } +#endif if (TITAN_GE_TX_COAL) { titan_ge_eth->tx_int_coal = titan_ge_tx_coal(TITAN_GE_TX_COAL, port_num); @@ -1406,6 +1354,45 @@ } /* + * Do the slowpath route. This route is kicked off + * when the IP header is misaligned. Grrr .. + */ +static int titan_ge_slowpath(struct sk_buff *skb, + titan_ge_packet *packet, + struct net_device *netdev) +{ + struct sk_buff *copy_skb; + + copy_skb = dev_alloc_skb(packet->len + 2); + + if (!copy_skb) { + dev_kfree_skb_any(packet->skb); + return -1; + } + + copy_skb->dev = netdev; + skb_reserve(copy_skb, 2); + skb_put(copy_skb, packet->len); + + memcpy(copy_skb->data, skb->data, packet->len); + + /* Titan supports Rx checksum offload */ + copy_skb->ip_summed = CHECKSUM_HW; + copy_skb->csum = packet->checksum; + + copy_skb->protocol = eth_type_trans(copy_skb, netdev); + + dev_kfree_skb_any(packet->skb); +#ifdef TITAN_RX_NAPI + netif_receive_skb(copy_skb); +#else + netif_rx(copy_skb); +#endif + + return 0; +} + +/* * Threshold beyond which we do the cleaning of * Tx queue and new allocation for the Rx * queue @@ -1434,10 +1421,11 @@ titan_ge_eth->rx_ring_skbs--; +#ifdef TITAN_RX_NAPI if (--titan_ge_eth->rx_work_limit < 0) break; received_packets++; - +#endif stats->rx_packets++; stats->rx_bytes += packet.len; @@ -1456,36 +1444,41 @@ * idea is to cut down the number of checks and improve * the fastpath. */ + skb_put(skb, packet.len); - skb_put(skb, packet.len - 2); - - /* - * Increment data pointer by two since thats where - * the MAC starts - */ - skb_reserve(skb, 2); - skb->protocol = eth_type_trans(skb, netdev); - netif_receive_skb(skb); + if (titan_ge_slowpath(skb, &packet, netdev) < 0) + goto out_next; +#ifdef TITAN_RX_NAPI if (titan_ge_eth->rx_threshold > RX_THRESHOLD) { ack = titan_ge_rx_task(netdev, titan_ge_eth); TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack); titan_ge_eth->rx_threshold = 0; } else titan_ge_eth->rx_threshold++; +#else + ack = titan_ge_rx_task(netdev, titan_ge_eth); + TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack); +#endif +out_next: + +#ifdef TITAN_RX_NAPI if (titan_ge_eth->tx_threshold > TX_THRESHOLD) { titan_ge_eth->tx_threshold = 0; titan_ge_free_tx_queue(titan_ge_eth); } else titan_ge_eth->tx_threshold++; +#endif } return received_packets; } +#ifdef TITAN_RX_NAPI + /* * Enable the Rx side interrupts */ @@ -1587,6 +1580,7 @@ return 0; } +#endif /* * Close the network device @@ -1598,6 +1592,7 @@ spin_lock_irq(&(titan_ge_eth->lock)); titan_ge_eth_stop(netdev); free_irq(netdev->irq, netdev); + MOD_DEC_USE_COUNT; spin_unlock_irq(&titan_ge_eth->lock); return TITAN_OK; @@ -1643,8 +1638,7 @@ titan_ge_eth->tx_ring_skbs); #ifndef TITAN_RX_RING_IN_SRAM - dma_free_coherent(&titan_ge_device[port_num]->dev, - titan_ge_eth->tx_desc_area_size, + pci_free_consistent(0, titan_ge_eth->tx_desc_area_size, (void *) titan_ge_eth->tx_desc_area, titan_ge_eth->tx_dma); #endif @@ -1690,8 +1684,7 @@ titan_ge_eth->rx_ring_skbs); #ifndef TITAN_RX_RING_IN_SRAM - dma_free_coherent(&titan_ge_device[port_num]->dev, - titan_ge_eth->rx_desc_area_size, + pci_free_consistent(0, titan_ge_eth->rx_desc_area_size, (void *) titan_ge_eth->rx_desc_area, titan_ge_eth->rx_dma); #endif @@ -1752,22 +1745,21 @@ ((p_addr[3] << 8) | p_addr[2])); TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)), ((p_addr[1] << 8) | p_addr[0])); + + return; } /* * Set the MAC address of the Ethernet device */ -static int titan_ge_set_mac_address(struct net_device *dev, void *addr) +int titan_ge_set_mac_address(struct net_device *netdev, void *addr) { - titan_ge_port_info *tp = netdev_priv(dev); - struct sockaddr *sa = addr; - - memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); + int i; - spin_lock_irq(&tp->lock); - titan_ge_update_mac_address(dev); - spin_unlock_irq(&tp->lock); + for (i = 0; i < 6; i++) + netdev->dev_addr[i] = ((unsigned char *) addr)[i + 2]; + titan_ge_update_mac_address(netdev); return 0; } @@ -1782,6 +1774,65 @@ } /* + * Register the Titan GE with the kernel + */ +static int __init titan_ge_init_module(void) +{ + unsigned int version, device; + + printk(KERN_NOTICE + "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n"); + + titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE); + if (!titan_ge_base) { + printk("Mapping Titan GE failed\n"); + goto out; + } + + device = TITAN_GE_READ(TITAN_GE_DEVICE_ID); + version = (device & 0x000f0000) >> 16; + device &= 0x0000ffff; + + printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version); + +#ifdef TITAN_RX_RING_IN_SRAM + titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE, + TITAN_SRAM_SIZE); + if (!titan_ge_sram) { + printk("Mapping Titan SRAM failed\n"); + goto out_unmap_ge; + } +#endif + + /* Register only one port */ + if (titan_ge_init(0)) + printk(KERN_ERR + "Error registering the TITAN Ethernet driver" + "for port 0 \n"); + + if (titan_ge_init(1)) + printk(KERN_ERR "Error registering the TITAN Ethernet" + "driver for port 1\n"); + + return 0; + +out_unmap_ge: + iounmap((void *)titan_ge_base); + +out: + return -ENOMEM; +} + +/* + * Unregister the Titan GE from the kernel + */ +static void __init titan_ge_cleanup_module(void) +{ + iounmap((void *)titan_ge_sram); + iounmap((void *)titan_ge_base); +} + +/* * Initialize the Rx descriptor ring for the Titan Ge */ static int titan_ge_init_rx_desc_ring(titan_ge_port_info * titan_eth_port, @@ -1875,11 +1926,10 @@ /* * Initialize the device as an Ethernet device */ -static int __init titan_ge_probe(struct device *device) +static int titan_ge_init(int port) { titan_ge_port_info *titan_ge_eth; struct net_device *netdev; - int port = to_platform_device(device)->id; int err; netdev = alloc_etherdev(sizeof(titan_ge_port_info)); @@ -1899,10 +1949,11 @@ netdev->tx_timeout = titan_ge_tx_timeout; netdev->watchdog_timeo = 2 * HZ; +#ifdef TITAN_RX_NAPI /* Set these to very high values */ netdev->poll = titan_ge_poll; netdev->weight = 64; - +#endif netdev->tx_queue_len = TITAN_GE_TX_QUEUE; netif_carrier_off(netdev); netdev->base_addr = 0; @@ -1936,7 +1987,11 @@ netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]); +#ifdef TITAN_RX_NAPI printk(KERN_NOTICE "Rx NAPI supported, Tx Coalescing ON \n"); +#else + printk(KERN_NOTICE "Rx and Tx Coalescing ON \n"); +#endif return 0; @@ -2013,122 +2068,6 @@ return delay; } -static struct device_driver titan_soc_driver = { - .name = titan_string, - .bus = &platform_bus_type, - .probe = titan_ge_probe, - .remove = __devexit_p(titan_device_remove), -}; - -static void titan_platform_release (struct device *device) -{ - struct platform_device *pldev; - - /* free device */ - pldev = to_platform_device (device); - kfree (pldev); -} - -/* - * Register the Titan GE with the kernel - */ -static int __init titan_ge_init_module(void) -{ - struct platform_device *pldev; - unsigned int version, device; - int i; - - printk(KERN_NOTICE - "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n"); - - titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE); - if (!titan_ge_base) { - printk("Mapping Titan GE failed\n"); - goto out; - } - - device = TITAN_GE_READ(TITAN_GE_DEVICE_ID); - version = (device & 0x000f0000) >> 16; - device &= 0x0000ffff; - - printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version); - -#ifdef TITAN_RX_RING_IN_SRAM - titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE, - TITAN_SRAM_SIZE); - if (!titan_ge_sram) { - printk("Mapping Titan SRAM failed\n"); - goto out_unmap_ge; - } -#endif - - if (driver_register(&titan_soc_driver)) { - printk(KERN_ERR "Driver registration failed\n"); - goto out_unmap_sram; - } - - for (i = 0; i < 3; i++) { - titan_ge_device[i] = NULL; - - if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL))) - continue; - - memset (pldev, 0, sizeof (*pldev)); - pldev->name = titan_string; - pldev->id = i; - pldev->dev.release = titan_platform_release; - titan_ge_device[i] = pldev; - - if (platform_device_register (pldev)) { - kfree (pldev); - titan_ge_device[i] = NULL; - continue; - } - - if (!pldev->dev.driver) { - /* - * The driver was not bound to this device, there was - * no hardware at this address. Unregister it, as the - * release fuction will take care of freeing the - * allocated structure - */ - titan_ge_device[i] = NULL; - platform_device_unregister (pldev); - } - } - - return 0; - -out_unmap_sram: - iounmap((void *)titan_ge_sram); - -out_unmap_ge: - iounmap((void *)titan_ge_base); - -out: - return -ENOMEM; -} - -/* - * Unregister the Titan GE from the kernel - */ -static void __exit titan_ge_cleanup_module(void) -{ - int i; - - driver_unregister(&titan_soc_driver); - - for (i = 0; i < 3; i++) { - if (titan_ge_device[i]) { - platform_device_unregister (titan_ge_device[i]); - titan_ge_device[i] = NULL; - } - } - - iounmap((void *)titan_ge_sram); - iounmap((void *)titan_ge_base); -} - MODULE_AUTHOR("Manish Lachwani "); MODULE_DESCRIPTION("Titan GE Ethernet driver"); MODULE_LICENSE("GPL"); --------------010709030108050202000102 Content-Type: text/plain; name="titan_ge.h.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="titan_ge.h.diff" --- linux/drivers/net/titan_ge.h 2004-10-26 03:46:16.000000000 +0200 +++ linux_2_6_8_1/drivers/net/titan_ge.h 2004-08-19 22:31:47.000000000 +0200 @@ -101,6 +101,9 @@ /* Debugging info only */ #undef TITAN_DEBUG +/* Support for Rx side NAPI */ +#define TITAN_RX_NAPI + /* Keep the rings in the Titan's SSRAM */ #define TITAN_RX_RING_IN_SRAM --------------010709030108050202000102-- From mlachwani@mvista.com Thu Nov 18 22:23:07 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 22:23:12 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:37104 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Thu, 18 Nov 2004 22:23:07 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 11154184F5; Thu, 18 Nov 2004 14:23:06 -0800 (PST) Message-ID: <419D20C9.10909@mvista.com> Date: Thu, 18 Nov 2004 14:23:05 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: TheNop Cc: linux-mips@linux-mips.org Subject: Re: Titan ethernet driver broken References: <419D03DE.8090403@gmx.net> <419D04AA.50508@mvista.com> <419D171E.5040507@gmx.net> <419D173E.6050602@mvista.com> <419D1A2D.5000009@gmx.net> <419D1F76.6010603@gmx.net> In-Reply-To: <419D1F76.6010603@gmx.net> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6364 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 484 Lines: 14 Hello ! Thanks for sending this. I have one question regarding the Yosemite board that you have. What is the version of the Titan chip on the board? Is it 1.0, 1.1 or 1.2? This is because 1.0 and 1.1 have a problem where the IP header is not aligned on the Rx side. As a result, there was an extra copy involved in the driver, i.e. titan_ge_slowpath. The latest version of the driver only support Titan chip revision 1.2 in which this problem is fixed Thanks Manish Lachwani From TheNop@gmx.net Thu Nov 18 22:37:55 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 22:38:00 +0000 (GMT) Received: from imap.gmx.net ([IPv6:::ffff:213.165.64.20]:63193 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Thu, 18 Nov 2004 22:37:55 +0000 Received: (qmail 15737 invoked by uid 65534); 18 Nov 2004 22:37:49 -0000 Received: from c210132.adsl.hansenet.de (EHLO [192.168.0.1]) (213.39.210.132) by mail.gmx.net (mp025) with SMTP; 18 Nov 2004 23:37:49 +0100 X-Authenticated: #947741 Message-ID: <419D25A7.2090506@gmx.net> Date: Thu, 18 Nov 2004 23:43:51 +0100 From: TheNop User-Agent: Mozilla Thunderbird 0.7.3 (Windows/20040803) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: Titan ethernet driver broken References: <419D03DE.8090403@gmx.net> <419D04AA.50508@mvista.com> <419D171E.5040507@gmx.net> <419D173E.6050602@mvista.com> <419D1A2D.5000009@gmx.net> <419D1F76.6010603@gmx.net> <419D20C9.10909@mvista.com> In-Reply-To: <419D20C9.10909@mvista.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6365 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: TheNop@gmx.net Precedence: bulk X-list: linux-mips Content-Length: 808 Lines: 27 Manish Lachwani wrote: > Hello ! > > Thanks for sending this. I have one question regarding the Yosemite > board that you have. What is the version of the Titan chip on the > board? Is it 1.0, 1.1 or 1.2? > > This is because 1.0 and 1.1 have a problem where the IP header is not > aligned on the Rx side. As a result, there was an extra copy involved > in the driver, i.e. titan_ge_slowpath. The latest version of the > driver only support Titan chip revision 1.2 in which this problem is > fixed > > Thanks > Manish Lachwani > > > I use the chip version 1.1. Now I have the problem, that I can not use the newest code, until 1.2 version of the chip is available. Is it possible to make the code usable for all chip version by choosing the version at the kernel configuration? Best regards TheNop From mlachwani@mvista.com Thu Nov 18 23:43:42 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Nov 2004 23:43:47 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:65006 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Thu, 18 Nov 2004 23:43:42 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 9695118608; Thu, 18 Nov 2004 15:43:40 -0800 (PST) Message-ID: <419D33AC.8090307@mvista.com> Date: Thu, 18 Nov 2004 15:43:40 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: TheNop , Linux/MIPS Development Subject: Re: Titan ethernet driver broken References: <419D03DE.8090403@gmx.net> <419D04AA.50508@mvista.com> <419D171E.5040507@gmx.net> <419D173E.6050602@mvista.com> <419D1A2D.5000009@gmx.net> <419D1F76.6010603@gmx.net> <419D20C9.10909@mvista.com> <419D25A7.2090506@gmx.net> In-Reply-To: <419D25A7.2090506@gmx.net> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6366 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1188 Lines: 41 Well, you dont need to configure kernel based on the chip revision. You can determine the chip revision (on bootup) by reading the processor id (PRID) and the CPU Mask register. Then, check the version number in the driver and do the copy (for IP header alignment) if the version is 1.0 or 1.1 Thanks Manish Lachwani TheNop wrote: > Manish Lachwani wrote: > >> Hello ! >> >> Thanks for sending this. I have one question regarding the Yosemite >> board that you have. What is the version of the Titan chip on the >> board? Is it 1.0, 1.1 or 1.2? >> >> This is because 1.0 and 1.1 have a problem where the IP header is not >> aligned on the Rx side. As a result, there was an extra copy involved >> in the driver, i.e. titan_ge_slowpath. The latest version of the >> driver only support Titan chip revision 1.2 in which this problem is >> fixed >> >> Thanks >> Manish Lachwani >> >> >> > I use the chip version 1.1. > Now I have the problem, that I can not use the newest code, until 1.2 > version of the chip is available. > Is it possible to make the code usable for all chip version by choosing > the version at the kernel configuration? > > Best regards > TheNop > From yuasa@hh.iij4u.or.jp Fri Nov 19 02:07:19 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2004 02:07:28 +0000 (GMT) Received: from mo01.iij4u.or.jp ([IPv6:::ffff:210.130.0.20]:63463 "EHLO mo01.iij4u.or.jp") by linux-mips.org with ESMTP id ; Fri, 19 Nov 2004 02:07:19 +0000 Received: MO(mo01)id iAJ27EUU004378; Fri, 19 Nov 2004 11:07:14 +0900 (JST) Received: MDO(mdo00) id iAJ27DkH029159; Fri, 19 Nov 2004 11:07:13 +0900 (JST) Received: 4UMRO00 id iAJ27DLc024943; Fri, 19 Nov 2004 11:07:13 +0900 (JST) from rally (localhost [127.0.0.1]) (authenticated) Date: Fri, 19 Nov 2004 11:07:33 +0900 From: Yoichi Yuasa To: Manish Lachwani Cc: yuasa@hh.iij4u.or.jp, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] Support for NEC VR4133 in 2.6 Message-Id: <20041119110733.5ddf14ea.yuasa@hh.iij4u.or.jp> In-Reply-To: <20041118195219.GA4337@prometheus.mvista.com> References: <20041118195219.GA4337@prometheus.mvista.com> X-Mailer: Sylpheed version 0.9.99 (GTK+ 1.2.10; i386-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6367 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@hh.iij4u.or.jp Precedence: bulk X-list: linux-mips Content-Length: 10347 Lines: 330 Hi Manish, I have a few comment ;p On Thu, 18 Nov 2004 11:52:19 -0800 Manish Lachwani wrote: > Hi Ralf > > Attached patch implements support for NEC VR4133 and NEC Rockhopper in > 2.6. Currently there is no ethernet driver for the ports on the CMB-VR4133. > > The board has been booted with the Onboard PcNet32 network interface and with > an Intel EEPRO100 PCI NIC card. > > Please review ... > > Thanks > Manish Lachwani > > Index: linux/arch/mips/vr41xx/nec-cmbvr4133/init.c > =================================================================== > --- /dev/null > +++ linux/arch/mips/vr41xx/nec-cmbvr4133/init.c > @@ -0,0 +1,81 @@ > +/* > + * arch/mips/vr41xx/nec-cmbvr4133/init.c > + * > + * PROM library initialisation code for NEC CMB-VR4133 board. > + * > + * Author: Yoichi Yuasa and > + * Jun Sun and > + * Alex Sapkov > + * > + * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under > + * the terms of the GNU General Public License version 2. This program > + * is licensed "as is" without any warranty of any kind, whether express > + * or implied. > + * > + * Support for NEC-CMBVR4133 in 2.6 > + * Manish Lachwani (mlachwani@mvista.com) > + */ > +#include > +#include > +#include > +#include > + > +#include > + > +#ifdef CONFIG_ROCKHOPPER > +#include > +#include > + > +#define PCICONFDREG 0xaf000c14 > +#define PCICONFAREG 0xaf000c18 > +#endif > + > +const char *get_system_type(void) > +{ > + return "NEC CMB-VR4133"; > +} > + > +void __init bus_error_init(void) > +{ > + /* Do Nothing */ > +} > + > +#ifdef CONFIG_ROCKHOPPER > +void disable_pcnet(void) > +{ We don't need bus_error_init(). I think that we should move get_system_type() and disable_pcnet() to setup.c. > Index: linux/arch/mips/vr41xx/nec-cmbvr4133/setup.c > =================================================================== > --- /dev/null > +++ linux/arch/mips/vr41xx/nec-cmbvr4133/setup.c > +void vr41xx_restart(char *command) > +{ > + change_c0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL)); > + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); > + flush_cache_all(); > + write_c0_wired(0); > + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); > +} > + > +void vr41xx_halt(void) > +{ > + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); > + while (1); > +} > + > +void vr41xx_power_off(void) > +{ > + vr41xx_halt(); > +} We don't need these functions. We already have these in common part. > +static int __init nec_cmbvr4133_setup(void) > +{ > +#ifdef CONFIG_ROCKHOPPER > + extern void disable_pcnet(void); > + > + disable_pcnet(); > +#endif > + set_io_port_base(IO_PORT_BASE); We don't need set_io_port_base(). It already set in common part. > + _machine_restart = vr41xx_restart; > + _machine_halt = vr41xx_halt; > + _machine_power_off = vr41xx_power_off; We don't need these. > + late_time_init = vr4133_serial_init; This should just only do vr4133_serial_init(). This function don't need to late_time_init. > Index: linux/include/asm-mips/vr41xx/cmbvr4133.h > =================================================================== > --- /dev/null > +++ linux/include/asm-mips/vr41xx/cmbvr4133.h > @@ -0,0 +1,93 @@ > +/* > + * include/asm-mips/vr41xx/cmbvr4133.h > +/* > + * Board specific address mapping > + */ > +#define VR41XX_PCI_MEM1_BASE 0x10000000 > +#define VR41XX_PCI_MEM1_SIZE 0x04000000 > +#define VR41XX_PCI_MEM1_MASK 0x7c000000 > + > +#define VR41XX_PCI_MEM2_BASE 0x14000000 > +#define VR41XX_PCI_MEM2_SIZE 0x02000000 > +#define VR41XX_PCI_MEM2_MASK 0x7e000000 > + > +#define VR41XX_PCI_IO_BASE 0x16000000 > +#define VR41XX_PCI_IO_SIZE 0x02000000 > +#define VR41XX_PCI_IO_MASK 0x7e000000 > + > +#define VR41XX_PCI_IO_START 0x01000000 > +#define VR41XX_PCI_IO_END 0x01ffffff > + > +#define VR41XX_PCI_MEM_START 0x12000000 > +#define VR41XX_PCI_MEM_END 0x15ffffff > + > +#define IO_PORT_BASE KSEG1ADDR(VR41XX_PCI_IO_BASE) > +#define IO_PORT_RESOURCE_START 0 > +#define IO_PORT_RESOURCE_END VR41XX_PCI_IO_SIZE > +#define IO_MEM1_RESOURCE_START VR41XX_PCI_MEM1_BASE > +#define IO_MEM1_RESOURCE_END (VR41XX_PCI_MEM1_BASE + VR41XX_PCI_MEM1_SIZE) > +#define IO_MEM2_RESOURCE_START VR41XX_PCI_MEM2_BASE > +#define IO_MEM2_RESOURCE_END (VR41XX_PCI_MEM2_BASE + VR41XX_PCI_MEM2_SIZE) > + We don't need these definitions. These definitions are not used. > Index: linux/arch/mips/vr41xx/common/vr4133.c > =================================================================== > --- /dev/null > +++ linux/arch/mips/vr41xx/common/vr4133.c > @@ -0,0 +1,75 @@ We don't need these functions. We already have these in common part. > Index: linux/include/asm-mips/vr41xx/vr4133.h > =================================================================== > --- /dev/null > +++ linux/include/asm-mips/vr41xx/vr4133.h > @@ -0,0 +1,25 @@ Same, we don't need it. > Index: linux/arch/mips/pci/pci-vr41xx.h > =================================================================== > --- linux.orig/arch/mips/pci/pci-vr41xx.h > +++ linux/arch/mips/pci/pci-vr41xx.h > @@ -18,6 +18,8 @@ > * You should have received a copy of the GNU General Public License > * along with this program; if not, write to the Free Software > * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > + * > + * Support for NEC VR4133 in 2.6 - Manish Lachwani (mlachwani@mvista.com) > */ > #ifndef __PCI_VR41XX_H > #define __PCI_VR41XX_H > @@ -127,6 +129,10 @@ > #define PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U > #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U > > +#define PCI_MASTER_MEM2_BUS_BASE_ADDRESS 0x14000000U > +#define PCI_MASTER_MEM2_ADDRESS_MASK 0x7e000000U > +#define PCI_MASTER_MEM2_PCI_BASE_ADDRESS 0x14000000U > + > #define PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U > #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U > > Index: linux/arch/mips/pci/pci-vr41xx.c > =================================================================== > --- linux.orig/arch/mips/pci/pci-vr41xx.c > +++ linux/arch/mips/pci/pci-vr41xx.c > @@ -19,6 +19,8 @@ > * You should have received a copy of the GNU General Public License > * along with this program; if not, write to the Free Software > * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > + * > + * Support for NEC VR4133 in 2.6 - Manish Lachwani (mlachwani@mvista.com) > */ > /* > * Changes: > @@ -43,6 +45,12 @@ > .pci_base_address = PCI_MASTER_MEM1_PCI_BASE_ADDRESS, > }; > > +static struct pci_master_address_conversion pci_master_memory2 = { > + .bus_base_address = PCI_MASTER_MEM2_BUS_BASE_ADDRESS, > + .address_mask = PCI_MASTER_MEM2_ADDRESS_MASK, > + .pci_base_address = PCI_MASTER_MEM2_PCI_BASE_ADDRESS, > +}; > + > static struct pci_target_address_conversion pci_target_memory1 = { > .address_mask = PCI_TARGET_MEM1_ADDRESS_MASK, > .bus_base_address = PCI_TARGET_MEM1_BUS_BASE_ADDRESS, > @@ -76,6 +84,22 @@ > .flags = IORESOURCE_IO, > }; > > +#ifdef CONFIG_ROCKHOPPER > +static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = { > + .master_memory1 = &pci_master_memory1, > + .master_memory2 = &pci_master_memory2, > + .target_memory1 = &pci_target_memory1, > + .master_io = &pci_master_io, > + .exclusive_access = CANNOT_LOCK_FROM_DEVICE, > + .wait_time_limit_from_irdy_to_trdy = 0, > + .mailbox = &pci_mailbox, > + .target_window1 = &pci_target_window1, > + .master_latency_timer = 0x80, > + .retry_limit = 0, > + .arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR, > + .take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE, > +}; > +#else > static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = { > .master_memory1 = &pci_master_memory1, > .target_memory1 = &pci_target_memory1, > @@ -89,6 +113,7 @@ > .arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR, > .take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE, > }; > +#endif > > static struct pci_controller vr41xx_pci_controller = { > .pci_ops = &vr41xx_pci_ops, Since pci_master_memory2 was the area which is not used, it was deleted. If you need this area, please let me know a reason. > Index: linux/arch/mips/vr41xx/common/serial.c > =================================================================== > --- linux.orig/arch/mips/vr41xx/common/serial.c > +++ linux/arch/mips/vr41xx/common/serial.c > @@ -52,17 +52,17 @@ > #define TMICTX 0x10 > #define TMICMODE 0x20 > > -#define SIU_BASE_TYPE1 0x0c000000UL /* VR4111 and VR4121 */ > -#define SIU_BASE_TYPE2 0x0f000800UL /* VR4122, VR4131 and VR4133 */ > +#define SIU_BASE_TYPE1 KSEG1ADDR(0x0c000000) /* VR4111 and VR4121 */ > +#define SIU_BASE_TYPE2 KSEG1ADDR(0x0f000800) /* VR4122, VR4131 and VR4133 */ > #define SIU_SIZE 0x8UL > > -#define SIU_BASE_BAUD 1152000 > +#define SIU_BASE_BAUD 115200 SIU base baud is 1152000. This change is wrong. > /* VR4122, VR4131 and VR4133 DSIU Registers */ > -#define DSIU_BASE 0x0f000820UL > +#define DSIU_BASE KSEG1ADDR(0x0f000820) > #define DSIU_SIZE 0x8UL > > -#define DSIU_BASE_BAUD 1152000 > +#define DSIU_BASE_BAUD 115200 DSIU base baud is 1152000. This change is wrong. > int vr41xx_serial_ports = 0; > > @@ -132,7 +132,7 @@ > } > port.regshift = 0; > port.iotype = UPIO_MEM; > - port.membase = ioremap(port.mapbase, SIU_SIZE); > + port.membase = (unsigned char *)port.mapbase; > if (port.membase != NULL) { > if (early_serial_setup(&port) == 0) { > vr41xx_supply_clock(SIU_CLOCK); > @@ -164,7 +164,7 @@ > port.mapbase = DSIU_BASE; > port.regshift = 0; > port.iotype = UPIO_MEM; > - port.membase = ioremap(port.mapbase, DSIU_SIZE); > + port.membase = (unsigned char *)port.mapbase; > if (port.membase != NULL) { > if (early_serial_setup(&port) == 0) { > vr41xx_supply_clock(DSIU_CLOCK); > These changes are same meaning. We don't need these. Yoichi From mlachwani@mvista.com Fri Nov 19 02:18:32 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2004 02:18:38 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:61172 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Fri, 19 Nov 2004 02:18:32 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 0822918514; Thu, 18 Nov 2004 18:18:30 -0800 (PST) Message-ID: <419D57F5.5000808@mvista.com> Date: Thu, 18 Nov 2004 18:18:29 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: Yoichi Yuasa Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] Support for NEC VR4133 in 2.6 References: <20041118195219.GA4337@prometheus.mvista.com> <20041119110733.5ddf14ea.yuasa@hh.iij4u.or.jp> In-Reply-To: <20041119110733.5ddf14ea.yuasa@hh.iij4u.or.jp> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6368 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 11017 Lines: 382 Hi Yoichi, Thanks for the comments. My comments below: Yoichi Yuasa wrote: > Hi Manish, > > I have a few comment ;p > > On Thu, 18 Nov 2004 11:52:19 -0800 > Manish Lachwani wrote: > > >>Hi Ralf >> >>Attached patch implements support for NEC VR4133 and NEC Rockhopper in >>2.6. Currently there is no ethernet driver for the ports on the CMB-VR4133. >> >>The board has been booted with the Onboard PcNet32 network interface and with >>an Intel EEPRO100 PCI NIC card. >> >>Please review ... >> >>Thanks >>Manish Lachwani >> >>Index: linux/arch/mips/vr41xx/nec-cmbvr4133/init.c >>=================================================================== >>--- /dev/null >>+++ linux/arch/mips/vr41xx/nec-cmbvr4133/init.c >>@@ -0,0 +1,81 @@ >>+/* >>+ * arch/mips/vr41xx/nec-cmbvr4133/init.c >>+ * >>+ * PROM library initialisation code for NEC CMB-VR4133 board. >>+ * >>+ * Author: Yoichi Yuasa and >>+ * Jun Sun and >>+ * Alex Sapkov >>+ * >>+ * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under >>+ * the terms of the GNU General Public License version 2. This program >>+ * is licensed "as is" without any warranty of any kind, whether express >>+ * or implied. >>+ * >>+ * Support for NEC-CMBVR4133 in 2.6 >>+ * Manish Lachwani (mlachwani@mvista.com) >>+ */ >>+#include >>+#include >>+#include >>+#include >>+ >>+#include >>+ >>+#ifdef CONFIG_ROCKHOPPER >>+#include >>+#include >>+ >>+#define PCICONFDREG 0xaf000c14 >>+#define PCICONFAREG 0xaf000c18 >>+#endif >>+ >>+const char *get_system_type(void) >>+{ >>+ return "NEC CMB-VR4133"; >>+} >>+ >>+void __init bus_error_init(void) >>+{ >>+ /* Do Nothing */ >>+} >>+ >>+#ifdef CONFIG_ROCKHOPPER >>+void disable_pcnet(void) >>+{ > > > We don't need bus_error_init(). > I think that we should move get_system_type() and disable_pcnet() to setup.c. > > >>Index: linux/arch/mips/vr41xx/nec-cmbvr4133/setup.c >>=================================================================== >>--- /dev/null >>+++ linux/arch/mips/vr41xx/nec-cmbvr4133/setup.c > > > > >>+void vr41xx_restart(char *command) >>+{ >>+ change_c0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL)); >>+ change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); >>+ flush_cache_all(); >>+ write_c0_wired(0); >>+ __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); >>+} >>+ >>+void vr41xx_halt(void) >>+{ >>+ printk(KERN_NOTICE "\n** You can safely turn off the power\n"); >>+ while (1); >>+} >>+ >>+void vr41xx_power_off(void) >>+{ >>+ vr41xx_halt(); >>+} > > > We don't need these functions. We already have these in common part. > > > >>+static int __init nec_cmbvr4133_setup(void) >>+{ >>+#ifdef CONFIG_ROCKHOPPER >>+ extern void disable_pcnet(void); >>+ >>+ disable_pcnet(); >>+#endif >>+ set_io_port_base(IO_PORT_BASE); > > > We don't need set_io_port_base(). > It already set in common part. We need to do set_io_port_base() here else it will cause a TLB exception and fall back into the PROM. > > > >>+ _machine_restart = vr41xx_restart; >>+ _machine_halt = vr41xx_halt; >>+ _machine_power_off = vr41xx_power_off; > > > We don't need these. > > >>+ late_time_init = vr4133_serial_init; > > > This should just only do vr4133_serial_init(). > This function don't need to late_time_init. We need to call vr4133_serial_init() after console_init(). Hence, this change. The idea is that late_time_init() will be called after console_init() in init/main.c > > >>Index: linux/include/asm-mips/vr41xx/cmbvr4133.h >>=================================================================== >>--- /dev/null >>+++ linux/include/asm-mips/vr41xx/cmbvr4133.h >>@@ -0,0 +1,93 @@ >>+/* >>+ * include/asm-mips/vr41xx/cmbvr4133.h > > > > >>+/* >>+ * Board specific address mapping >>+ */ >>+#define VR41XX_PCI_MEM1_BASE 0x10000000 >>+#define VR41XX_PCI_MEM1_SIZE 0x04000000 >>+#define VR41XX_PCI_MEM1_MASK 0x7c000000 >>+ >>+#define VR41XX_PCI_MEM2_BASE 0x14000000 >>+#define VR41XX_PCI_MEM2_SIZE 0x02000000 >>+#define VR41XX_PCI_MEM2_MASK 0x7e000000 >>+ >>+#define VR41XX_PCI_IO_BASE 0x16000000 >>+#define VR41XX_PCI_IO_SIZE 0x02000000 >>+#define VR41XX_PCI_IO_MASK 0x7e000000 >>+ >>+#define VR41XX_PCI_IO_START 0x01000000 >>+#define VR41XX_PCI_IO_END 0x01ffffff >>+ >>+#define VR41XX_PCI_MEM_START 0x12000000 >>+#define VR41XX_PCI_MEM_END 0x15ffffff >>+ >>+#define IO_PORT_BASE KSEG1ADDR(VR41XX_PCI_IO_BASE) >>+#define IO_PORT_RESOURCE_START 0 >>+#define IO_PORT_RESOURCE_END VR41XX_PCI_IO_SIZE >>+#define IO_MEM1_RESOURCE_START VR41XX_PCI_MEM1_BASE >>+#define IO_MEM1_RESOURCE_END (VR41XX_PCI_MEM1_BASE + VR41XX_PCI_MEM1_SIZE) >>+#define IO_MEM2_RESOURCE_START VR41XX_PCI_MEM2_BASE >>+#define IO_MEM2_RESOURCE_END (VR41XX_PCI_MEM2_BASE + VR41XX_PCI_MEM2_SIZE) >>+ > > > We don't need these definitions. > These definitions are not used. > > >>Index: linux/arch/mips/vr41xx/common/vr4133.c >>=================================================================== >>--- /dev/null >>+++ linux/arch/mips/vr41xx/common/vr4133.c >>@@ -0,0 +1,75 @@ > > > We don't need these functions. We already have these in common part. > > >>Index: linux/include/asm-mips/vr41xx/vr4133.h >>=================================================================== >>--- /dev/null >>+++ linux/include/asm-mips/vr41xx/vr4133.h >>@@ -0,0 +1,25 @@ > > > Same, we don't need it. > > >>Index: linux/arch/mips/pci/pci-vr41xx.h >>=================================================================== >>--- linux.orig/arch/mips/pci/pci-vr41xx.h >>+++ linux/arch/mips/pci/pci-vr41xx.h >>@@ -18,6 +18,8 @@ >> * You should have received a copy of the GNU General Public License >> * along with this program; if not, write to the Free Software >> * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA >>+ * >>+ * Support for NEC VR4133 in 2.6 - Manish Lachwani (mlachwani@mvista.com) >> */ >> #ifndef __PCI_VR41XX_H >> #define __PCI_VR41XX_H >>@@ -127,6 +129,10 @@ >> #define PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U >> #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U >> >>+#define PCI_MASTER_MEM2_BUS_BASE_ADDRESS 0x14000000U >>+#define PCI_MASTER_MEM2_ADDRESS_MASK 0x7e000000U >>+#define PCI_MASTER_MEM2_PCI_BASE_ADDRESS 0x14000000U >>+ >> #define PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U >> #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U >> >>Index: linux/arch/mips/pci/pci-vr41xx.c >>=================================================================== >>--- linux.orig/arch/mips/pci/pci-vr41xx.c >>+++ linux/arch/mips/pci/pci-vr41xx.c >>@@ -19,6 +19,8 @@ >> * You should have received a copy of the GNU General Public License >> * along with this program; if not, write to the Free Software >> * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA >>+ * >>+ * Support for NEC VR4133 in 2.6 - Manish Lachwani (mlachwani@mvista.com) >> */ >> /* >> * Changes: >>@@ -43,6 +45,12 @@ >> .pci_base_address = PCI_MASTER_MEM1_PCI_BASE_ADDRESS, >> }; >> >>+static struct pci_master_address_conversion pci_master_memory2 = { >>+ .bus_base_address = PCI_MASTER_MEM2_BUS_BASE_ADDRESS, >>+ .address_mask = PCI_MASTER_MEM2_ADDRESS_MASK, >>+ .pci_base_address = PCI_MASTER_MEM2_PCI_BASE_ADDRESS, >>+}; >>+ >> static struct pci_target_address_conversion pci_target_memory1 = { >> .address_mask = PCI_TARGET_MEM1_ADDRESS_MASK, >> .bus_base_address = PCI_TARGET_MEM1_BUS_BASE_ADDRESS, >>@@ -76,6 +84,22 @@ >> .flags = IORESOURCE_IO, >> }; >> >>+#ifdef CONFIG_ROCKHOPPER >>+static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = { >>+ .master_memory1 = &pci_master_memory1, >>+ .master_memory2 = &pci_master_memory2, >>+ .target_memory1 = &pci_target_memory1, >>+ .master_io = &pci_master_io, >>+ .exclusive_access = CANNOT_LOCK_FROM_DEVICE, >>+ .wait_time_limit_from_irdy_to_trdy = 0, >>+ .mailbox = &pci_mailbox, >>+ .target_window1 = &pci_target_window1, >>+ .master_latency_timer = 0x80, >>+ .retry_limit = 0, >>+ .arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR, >>+ .take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE, >>+}; >>+#else >> static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = { >> .master_memory1 = &pci_master_memory1, >> .target_memory1 = &pci_target_memory1, >>@@ -89,6 +113,7 @@ >> .arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR, >> .take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE, >> }; >>+#endif >> >> static struct pci_controller vr41xx_pci_controller = { >> .pci_ops = &vr41xx_pci_ops, > > > Since pci_master_memory2 was the area which is not used, it was deleted. > If you need this area, please let me know a reason. > > >>Index: linux/arch/mips/vr41xx/common/serial.c >>=================================================================== >>--- linux.orig/arch/mips/vr41xx/common/serial.c >>+++ linux/arch/mips/vr41xx/common/serial.c >>@@ -52,17 +52,17 @@ >> #define TMICTX 0x10 >> #define TMICMODE 0x20 >> >>-#define SIU_BASE_TYPE1 0x0c000000UL /* VR4111 and VR4121 */ >>-#define SIU_BASE_TYPE2 0x0f000800UL /* VR4122, VR4131 and VR4133 */ >>+#define SIU_BASE_TYPE1 KSEG1ADDR(0x0c000000) /* VR4111 and VR4121 */ >>+#define SIU_BASE_TYPE2 KSEG1ADDR(0x0f000800) /* VR4122, VR4131 and VR4133 */ >> #define SIU_SIZE 0x8UL >> >>-#define SIU_BASE_BAUD 1152000 >>+#define SIU_BASE_BAUD 115200 > > > SIU base baud is 1152000. This change is wrong. > > >> /* VR4122, VR4131 and VR4133 DSIU Registers */ >>-#define DSIU_BASE 0x0f000820UL >>+#define DSIU_BASE KSEG1ADDR(0x0f000820) >> #define DSIU_SIZE 0x8UL >> >>-#define DSIU_BASE_BAUD 1152000 >>+#define DSIU_BASE_BAUD 115200 > > > DSIU base baud is 1152000. This change is wrong. My bad > > >> int vr41xx_serial_ports = 0; >> >>@@ -132,7 +132,7 @@ >> } >> port.regshift = 0; >> port.iotype = UPIO_MEM; >>- port.membase = ioremap(port.mapbase, SIU_SIZE); >>+ port.membase = (unsigned char *)port.mapbase; >> if (port.membase != NULL) { >> if (early_serial_setup(&port) == 0) { >> vr41xx_supply_clock(SIU_CLOCK); >>@@ -164,7 +164,7 @@ >> port.mapbase = DSIU_BASE; >> port.regshift = 0; >> port.iotype = UPIO_MEM; >>- port.membase = ioremap(port.mapbase, DSIU_SIZE); >>+ port.membase = (unsigned char *)port.mapbase; >> if (port.membase != NULL) { >> if (early_serial_setup(&port) == 0) { >> vr41xx_supply_clock(DSIU_CLOCK); >> > > > These changes are same meaning. > We don't need these. I will look at the remaining changes which are unnecessary and generate a new patch Thanks Manish Lachwani > > > Yoichi > From maillist@jg555.com Fri Nov 19 17:20:04 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2004 17:20:09 +0000 (GMT) Received: from dsl-64-30-195-78.lcinet.net ([IPv6:::ffff:64.30.195.78]:1229 "EHLO jg555.com") by linux-mips.org with ESMTP id ; Fri, 19 Nov 2004 17:20:04 +0000 Received: from [172.16.0.150] (w2rz8l4s02.jg555.com [::ffff:172.16.0.150]) (AUTH: PLAIN jim, SSL: TLSv1/SSLv3,256bits,AES256-SHA) by jg555.com with esmtp; Fri, 19 Nov 2004 09:17:34 -0800 id 0000C642.419E2AAF.0000520F Message-ID: <419E2B1E.2050602@jg555.com> Date: Fri, 19 Nov 2004 09:19:26 -0800 From: Jim Gifford User-Agent: Mozilla Thunderbird 0.9 (Windows/20041103) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Glibc - Current CVS Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6369 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maillist@jg555.com Precedence: bulk X-list: linux-mips Content-Length: 2527 Lines: 49 Hi everyone, I'm one of the editors for Linux From Scratch, and we have had a lot of requests to make LFS compatible with other platforms. So I have been tasked to get a mips version up and running. The biggest issue I have faced has been the current glibc snapshot. I have fixed most of the issues based on the information located here on this list. But there is one error I have seen mentioned, but no word on how to fix it. Any help will be appreciated. Here is the error message. : /mnt/lfs/build/glibc-build/rt/librt_pic.a gcc -B/tools/bin/ -mabi=32 -shared -static-libgcc -Wl,-O1 -Wl,-z,defs -Wl,-dynamic-linker=/tools/lib/ld.so.1 -B/mnt/lfs/build/glibc-build/csu/ -Wl,--version-script=/mnt/lfs/build/glibc-build/librt.map -Wl,-soname=librt.so.1 -Wl,--enable-new-dtags,-z,nodelete -L/mnt/lfs/build/glibc-build -L/mnt/lfs/build/glibc-build/math -L/mnt/lfs/build/glibc-build/elf -L/mnt/lfs/build/glibc-build/dlfcn -L/mnt/lfs/build/glibc-build/nss -L/mnt/lfs/build/glibc-build/nis -L/mnt/lfs/build/glibc-build/rt -L/mnt/lfs/build/glibc-build/resolv -L/mnt/lfs/build/glibc-build/crypt -L/mnt/lfs/build/glibc-build/linuxthreads -Wl,-rpath-link=/mnt/lfs/build/glibc-build:/mnt/lfs/build/glibc-build/math:/mnt/lfs/build/glibc-build/elf:/mnt/lfs/build/glibc-build/dlfcn:/mnt/lfs/build/glibc-build/nss:/mnt/lfs/build/glibc-build/nis:/mnt/lfs/build/glibc-build/rt:/mnt/lfs/build/glibc-build/resolv:/mnt/lfs/build/glibc-build/crypt:/mnt/lfs/build/glibc-build/linuxthreads -o /mnt/lfs/build/glibc-build/rt/librt.so -T /mnt/lfs/build/glibc-build/shlib.lds /mnt/lfs/build/glibc-build/csu/abi-note.o -Wl,--whole-archive /mnt/lfs/build/glibc-build/rt/librt_pic.a -Wl,--no-whole-archive /mnt/lfs/build/glibc-build/elf/interp.os /mnt/lfs/build/glibc-build/libc.so /mnt/lfs/build/glibc-build/libc_nonshared.a /mnt/lfs/build/glibc-build/linuxthreads/libpthread_nonshared.a /mnt/lfs/build/glibc-build/linuxthreads/libpthread.so /mnt/lfs/build/glibc-build/elf/ld.so /mnt/lfs/build/glibc-build/rt/librt_pic.a(mq_setattr.os)(.text+0x0): undefined reference to `__syscall_error' /mnt/lfs/build/glibc-build/rt/librt_pic.a(mq_timedsend.os)(.text+0x0): undefined reference to `__syscall_error' /mnt/lfs/build/glibc-build/rt/librt_pic.a(mq_timedreceive.os)(.text+0x0): undefined reference to `__syscall_error' collect2: ld returned 1 exit status make[2]: *** [/mnt/lfs/build/glibc-build/rt/librt.so] Error 1 make[2]: Leaving directory `/mnt/lfs/build/glibc-20041115/rt' -- ---- Jim Gifford maillist@jg555.com From mlachwani@mvista.com Fri Nov 19 17:32:03 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2004 17:32:08 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:24564 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Fri, 19 Nov 2004 17:32:03 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id 3627C183E0; Fri, 19 Nov 2004 09:32:01 -0800 (PST) Message-ID: <419E2E10.5020304@mvista.com> Date: Fri, 19 Nov 2004 09:32:00 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: TheNop Cc: linux-mips@linux-mips.org Subject: Re: Titan ethernet driver broken References: <419D03DE.8090403@gmx.net> <419D04AA.50508@mvista.com> <419D171E.5040507@gmx.net> <419D173E.6050602@mvista.com> <419D1A2D.5000009@gmx.net> <419D1F76.6010603@gmx.net> In-Reply-To: <419D1F76.6010603@gmx.net> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6370 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 2693 Lines: 115 Hello ! If you are interested in creating a patch for supporting Titan GE in older Titan versions (1.0 and 1.1), then I have indicated the part of the diffs below that you will need to apply to the current driver > > /* > + * Do the slowpath route. This route is kicked off > + * when the IP header is misaligned. Grrr .. > + */ > +static int titan_ge_slowpath(struct sk_buff *skb, > + titan_ge_packet *packet, > + struct net_device *netdev) > +{ > + struct sk_buff *copy_skb; > + > + copy_skb = dev_alloc_skb(packet->len + 2); > + > + if (!copy_skb) { > + dev_kfree_skb_any(packet->skb); > + return -1; > + } > + > + copy_skb->dev = netdev; > + skb_reserve(copy_skb, 2); > + skb_put(copy_skb, packet->len); > + > + memcpy(copy_skb->data, skb->data, packet->len); > + > + /* Titan supports Rx checksum offload */ > + copy_skb->ip_summed = CHECKSUM_HW; > + copy_skb->csum = packet->checksum; > + > + copy_skb->protocol = eth_type_trans(copy_skb, netdev); > + > + dev_kfree_skb_any(packet->skb); > +#ifdef TITAN_RX_NAPI > + netif_receive_skb(copy_skb); > +#else > + netif_rx(copy_skb); > +#endif > + > + return 0; > +} > + > +/* > * Threshold beyond which we do the cleaning of > * Tx queue and new allocation for the Rx > * queue > @@ -1434,10 +1421,11 @@ > > titan_ge_eth->rx_ring_skbs--; > > +#ifdef TITAN_RX_NAPI > if (--titan_ge_eth->rx_work_limit < 0) > break; > received_packets++; > - > +#endif > stats->rx_packets++; > stats->rx_bytes += packet.len; > > @@ -1456,36 +1444,41 @@ > * idea is to cut down the number of checks and improve > * the fastpath. > */ > + skb_put(skb, packet.len); > > - skb_put(skb, packet.len - 2); > - > - /* > - * Increment data pointer by two since thats where > - * the MAC starts > - */ > - skb_reserve(skb, 2); > - skb->protocol = eth_type_trans(skb, netdev); > - netif_receive_skb(skb); > + if (titan_ge_slowpath(skb, &packet, netdev) < 0) > + goto out_next; > > +#ifdef TITAN_RX_NAPI > if (titan_ge_eth->rx_threshold > RX_THRESHOLD) { > ack = titan_ge_rx_task(netdev, titan_ge_eth); > TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack); > titan_ge_eth->rx_threshold = 0; > } else > titan_ge_eth->rx_threshold++; > +#else > + ack = titan_ge_rx_task(netdev, titan_ge_eth); > + TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack); > +#endif > > +out_next: > + > +#ifdef TITAN_RX_NAPI > if (titan_ge_eth->tx_threshold > TX_THRESHOLD) { > titan_ge_eth->tx_threshold = 0; > titan_ge_free_tx_queue(titan_ge_eth); > } > else > titan_ge_eth->tx_threshold++; > +#endif > > } > return received_packets; > } > Thanks Manish Lachwani From mlachwani@prometheus.mvista.com Fri Nov 19 20:02:21 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Nov 2004 20:02:32 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:32754 "EHLO prometheus.mvista.com") by linux-mips.org with ESMTP id ; Fri, 19 Nov 2004 20:02:21 +0000 Received: from prometheus.mvista.com (localhost.localdomain [127.0.0.1]) by prometheus.mvista.com (8.12.8/8.12.8) with ESMTP id iAJK2Fdh025328; Fri, 19 Nov 2004 12:02:15 -0800 Received: (from mlachwani@localhost) by prometheus.mvista.com (8.12.8/8.12.8/Submit) id iAJK2EGq025326; Fri, 19 Nov 2004 12:02:15 -0800 Date: Fri, 19 Nov 2004 12:02:14 -0800 From: Manish Lachwani To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, yuasa@hh.iij4u.or.jp Subject: [PATCH] Support for NEC VR4133 and NEC CMBVR4133 in 2.6 Message-ID: <20041119200214.GB25310@prometheus.mvista.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="hQiwHBbRI9kgIhsi" Content-Disposition: inline User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6371 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@prometheus.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 28728 Lines: 965 --hQiwHBbRI9kgIhsi Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ralf Resending the patch to add support for NEC VR4133 and NEC CMBVR4133 in 2.6. This is after Yoichi's comments. Removed all the unnecessary code that was already in the common part. Please review ... Thanks Manish Lachwani --hQiwHBbRI9kgIhsi Content-Type: text/plain; charset=us-ascii Content-Disposition: inline; filename="common_mips_NEC_vr4133_MR9056.patch" Source: MontaVista Software, Inc. | http://www.mvista.com | Manish Lachwani Type: Enhancement Disposition: Submitted to Linux-MIPS Description: Support for NEC VR4133 and NEC CMB-VR4133 in 2.6.10 kernel Index: linux/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c @@ -0,0 +1,256 @@ +/* + * arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c + * + * Initialize for ALi M1535+(included M5229 and M5237). + * + * Author: Yoichi Yuasa and + * Alex Sapkov + * + * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for NEC-CMBVR4133 in 2.6 + * Author: Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include + +#include +#include +#include + +#define CONFIG_PORT(port) ((port) ? 0x3f0 : 0x370) +#define DATA_PORT(port) ((port) ? 0x3f1 : 0x371) +#define INDEX_PORT(port) CONFIG_PORT(port) + +#define ENTER_CONFIG_MODE(port) \ + do { \ + outb_p(0x51, CONFIG_PORT(port)); \ + outb_p(0x23, CONFIG_PORT(port)); \ + } while(0) + +#define SELECT_LOGICAL_DEVICE(port, dev_no) \ + do { \ + outb_p(0x07, INDEX_PORT(port)); \ + outb_p((dev_no), DATA_PORT(port)); \ + } while(0) + +#define WRITE_CONFIG_DATA(port,index,data) \ + do { \ + outb_p((index), INDEX_PORT(port)); \ + outb_p((data), DATA_PORT(port)); \ + } while(0) + +#define EXIT_CONFIG_MODE(port) outb(0xbb, CONFIG_PORT(port)) + +#define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18) +#define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14) + +#ifdef CONFIG_BLK_DEV_FD + +void __devinit ali_m1535plus_fdc_init(int port) +{ + ENTER_CONFIG_MODE(port); + SELECT_LOGICAL_DEVICE(port, 0); /* FDC */ + WRITE_CONFIG_DATA(port, 0x30, 0x01); /* FDC: enable */ + WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x3f0 */ + WRITE_CONFIG_DATA(port, 0x61, 0xf0); + WRITE_CONFIG_DATA(port, 0x70, 0x06); /* IRQ: 6 */ + WRITE_CONFIG_DATA(port, 0x74, 0x02); /* DMA: channel 2 */ + WRITE_CONFIG_DATA(port, 0xf0, 0x08); + WRITE_CONFIG_DATA(port, 0xf1, 0x00); + WRITE_CONFIG_DATA(port, 0xf2, 0xff); + WRITE_CONFIG_DATA(port, 0xf4, 0x00); + EXIT_CONFIG_MODE(port); +} + +#endif + +void __devinit ali_m1535plus_parport_init(int port) +{ + ENTER_CONFIG_MODE(port); + SELECT_LOGICAL_DEVICE(port, 3); /* Parallel Port */ + WRITE_CONFIG_DATA(port, 0x30, 0x01); + WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x378 */ + WRITE_CONFIG_DATA(port, 0x61, 0x78); + WRITE_CONFIG_DATA(port, 0x70, 0x07); /* IRQ: 7 */ + WRITE_CONFIG_DATA(port, 0x74, 0x04); /* DMA: None */ + WRITE_CONFIG_DATA(port, 0xf0, 0x8c); /* IRQ polarity: Active Low */ + WRITE_CONFIG_DATA(port, 0xf1, 0xc5); + EXIT_CONFIG_MODE(port); +} + +#ifdef CONFIG_PC_KEYB + +void __devinit ali_m1535plus_keyboard_init(int port) +{ + ENTER_CONFIG_MODE(port); + SELECT_LOGICAL_DEVICE(port, 7); /* KEYBOARD */ + WRITE_CONFIG_DATA(port, 0x30, 0x01); /* KEYBOARD: eable */ + WRITE_CONFIG_DATA(port, 0x70, 0x01); /* IRQ: 1 */ + WRITE_CONFIG_DATA(port, 0x72, 0x0c); /* PS/2 Mouse IRQ: 12 */ + WRITE_CONFIG_DATA(port, 0xf0, 0x00); + EXIT_CONFIG_MODE(port); +} + +#endif + +void __devinit ali_m1535plus_hotkey_init(int port) +{ + ENTER_CONFIG_MODE(port); + SELECT_LOGICAL_DEVICE(port, 0xc); /* HOTKEY */ + WRITE_CONFIG_DATA(port, 0x30, 0x00); + WRITE_CONFIG_DATA(port, 0xf0, 0x35); + WRITE_CONFIG_DATA(port, 0xf1, 0x14); + WRITE_CONFIG_DATA(port, 0xf2, 0x11); + WRITE_CONFIG_DATA(port, 0xf3, 0x71); + WRITE_CONFIG_DATA(port, 0xf5, 0x05); + EXIT_CONFIG_MODE(port); +} + +void ali_m1535plus_init(struct pci_dev *dev) +{ + pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */ + pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */ + pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */ + pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */ + pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */ + pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */ + pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */ + + /* IRQ routing */ + pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */ + pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */ + pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */ + pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */ + + pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */ + pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */ + pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */ + pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */ + + pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */ + pci_write_config_byte(dev, 0x5a, 0x00); + pci_write_config_byte(dev, 0x5b, 0x00); + pci_write_config_word(dev, 0x5c, 0x0000); + pci_write_config_byte(dev, 0x5e, 0x00); + pci_write_config_byte(dev, 0x5f, 0x00); + pci_write_config_word(dev, 0x60, 0x0000); + + pci_write_config_byte(dev, 0x6c, 0x00); + pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */ + pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */ + + pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */ + pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */ + pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */ + pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */ + + /* + * IRQ setup ALi M5237 USB Host Controller + * IRQ: 9 + */ + pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */ + + pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15 */ + pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */ + pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */ + pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */ + pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */ + pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */ + pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */ + pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */ + +#ifdef CONFIG_BLK_DEV_FD + ali_m1535plus_fdc_init(1); +#endif + +#ifdef CONFIG_PC_KEYB + ali_m1535plus_keyboard_init(1); + ali_m1535plus_hotkey_init(1); +#endif +} + +static inline void ali_config_writeb(u8 reg, u8 val, int devfn) +{ + u32 data; + int shift; + + writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); + data = readl(PCI_CONFIG_DATA); + + shift = (reg & 3) << 3; + data &= ~(0xff << shift); + data |= (((u32)val) << shift); + + writel(data, PCI_CONFIG_DATA); +} + +static inline u8 ali_config_readb(u8 reg, int devfn) +{ + u32 data; + + writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); + data = readl(PCI_CONFIG_DATA); + + return (u8)(data >> ((reg & 3) << 3)); +} + +static inline u16 ali_config_readw(u8 reg, int devfn) +{ + u32 data; + + writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); + data = readl(PCI_CONFIG_DATA); + + return (u16)(data >> ((reg & 2) << 3)); +} + +int vr4133_rockhopper = 0; +void __init ali_m5229_preinit(void) +{ + if (ali_config_readw(PCI_VENDOR_ID,16) == PCI_VENDOR_ID_AL && + ali_config_readw(PCI_DEVICE_ID,16) == PCI_DEVICE_ID_AL_M1533) { + printk(KERN_INFO "Found an NEC Rockhopper \n"); + vr4133_rockhopper = 1; + /* + * Enable ALi M5229 IDE Controller (both channels) + * IDSEL: A27 + */ + ali_config_writeb(0x58, 0x4c, 16); + } +} + +void __init ali_m5229_init(struct pci_dev *dev) +{ + /* + * Enable Primary/Secondary Channel Cable Detect 40-Pin + */ + pci_write_config_word(dev, 0x4a, 0xc023); + + /* + * Set only the 3rd byteis for the master IDE's cycle and + * enable Internal IDE Function + */ + pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */ + + pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */ + pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */ + pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */ + pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */ + pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */ + pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */ + pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */ + pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */ + pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */ + pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */ + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); + pci_write_config_word(dev, PCI_COMMAND, + PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | + PCI_COMMAND_IO); +} + Index: linux/arch/mips/vr41xx/nec-cmbvr4133/init.c =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/nec-cmbvr4133/init.c @@ -0,0 +1,78 @@ +/* + * arch/mips/vr41xx/nec-cmbvr4133/init.c + * + * PROM library initialisation code for NEC CMB-VR4133 board. + * + * Author: Yoichi Yuasa and + * Jun Sun and + * Alex Sapkov + * + * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for NEC-CMBVR4133 in 2.6 + * Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include + +#include + +#ifdef CONFIG_ROCKHOPPER +#include +#include + +#define PCICONFDREG 0xaf000c14 +#define PCICONFAREG 0xaf000c18 +#endif + +const char *get_system_type(void) +{ + return "NEC CMB-VR4133"; +} + +#ifdef CONFIG_ROCKHOPPER +void disable_pcnet(void) +{ + u32 data; + + /* + * Workaround for the bug in PMON on VR4133. PMON leaves + * AMD PCNet controller (on Rockhopper) initialized and running in + * bus master mode. We have do disable it before doing any + * further initialization. Or we get problems with PCI bus 2 + * and random lockups and crashes. + */ + + writel((2 << 16) | + (PCI_DEVFN(1,0) << 8) | + (0 & 0xfc) | + 1UL, + PCICONFAREG); + + data = readl(PCICONFDREG); + + writel((2 << 16) | + (PCI_DEVFN(1,0) << 8) | + (4 & 0xfc) | + 1UL, + PCICONFAREG); + + data = readl(PCICONFDREG); + + writel((2 << 16) | + (PCI_DEVFN(1,0) << 8) | + (4 & 0xfc) | + 1UL, + PCICONFAREG); + + data &= ~4; + + writel(data, PCICONFDREG); +} +#endif + Index: linux/arch/mips/vr41xx/nec-cmbvr4133/setup.c =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/nec-cmbvr4133/setup.c @@ -0,0 +1,103 @@ +/* + * arch/mips/vr41xx/nec-cmbvr4133/setup.c + * + * Setup for the NEC CMB-VR4133. + * + * Author: Yoichi Yuasa and + * Alex Sapkov + * + * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for CMBVR4133 board in 2.6 + * Author: Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_MTD +#include +#include +#include +#include + +static struct mtd_partition cmbvr4133_mtd_parts[] = { + { + .name = "User FS", + .size = 0x1be0000, + .offset = 0, + .mask_flags = 0, + }, + { + .name = "PMON", + .size = 0x140000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "User FS2", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0, + } +}; + +#define number_partitions (sizeof(cmbvr4133_mtd_parts)/sizeof(struct mtd_partition)) +#endif + +extern void (*late_time_init)(void); + +static void __init vr4133_serial_init(void) +{ + vr41xx_select_siu_interface(SIU_RS232C, IRDA_NONE); + vr41xx_siu_init(); + vr41xx_dsiu_init(); +} + +static int __init nec_cmbvr4133_setup(void) +{ +#ifdef CONFIG_ROCKHOPPER + extern void disable_pcnet(void); + + disable_pcnet(); +#endif + set_io_port_base(KSEG1ADDR(0x16000000)); + + mips_machgroup = MACH_GROUP_NEC_VR41XX; + mips_machtype = MACH_NEC_CMBVR4133; + + late_time_init = vr4133_serial_init; + +#ifdef CONFIG_PCI +#ifdef CONFIG_ROCKHOPPER + ali_m5229_preinit(); +#endif +#endif + +#ifdef CONFIG_ROCKHOPPER + rockhopper_init_irq(); +#endif + +#ifdef CONFIG_MTD + /* we use generic physmap mapping driver and we use partitions */ + physmap_configure(0x1C000000, 0x02000000, 4, NULL); + physmap_set_partitions(cmbvr4133_mtd_parts, number_partitions); +#endif + + /* 128 MB memory support */ + add_memory_region(0, 0x08000000, BOOT_MEM_RAM); + + return 0; +} + +early_initcall(nec_cmbvr4133_setup); Index: linux/arch/mips/vr41xx/nec-cmbvr4133/irq.c =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/nec-cmbvr4133/irq.c @@ -0,0 +1,114 @@ +/* + * arch/mips/vr41xx/nec-cmbvr4133/irq.c + * + * Interrupt routines for the NEC CMB-VR4133 board. + * + * Author: Yoichi Yuasa and + * Alex Sapkov + * + * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for NEC-CMBVR4133 in 2.6 + * Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +#include +#include + +extern void enable_8259A_irq(unsigned int irq); +extern void disable_8259A_irq(unsigned int irq); +extern void mask_and_ack_8259A(unsigned int irq); +extern void init_8259A(int hoge); + +extern int vr4133_rockhopper; + +static unsigned int startup_i8259_irq(unsigned int irq) +{ + enable_8259A_irq(irq - I8259_IRQ_BASE); + return 0; +} + +static void shutdown_i8259_irq(unsigned int irq) +{ + disable_8259A_irq(irq - I8259_IRQ_BASE); +} + +static void enable_i8259_irq(unsigned int irq) +{ + enable_8259A_irq(irq - I8259_IRQ_BASE); +} + +static void disable_i8259_irq(unsigned int irq) +{ + disable_8259A_irq(irq - I8259_IRQ_BASE); +} + +static void ack_i8259_irq(unsigned int irq) +{ + mask_and_ack_8259A(irq - I8259_IRQ_BASE); +} + +static void end_i8259_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_8259A_irq(irq - I8259_IRQ_BASE); +} + +static struct hw_interrupt_type i8259_irq_type = { + .typename = "XT-PIC", + .startup = startup_i8259_irq, + .shutdown = shutdown_i8259_irq, + .enable = enable_i8259_irq, + .disable = disable_i8259_irq, + .ack = ack_i8259_irq, + .end = end_i8259_irq, +}; + +static int i8259_get_irq_number(int irq) +{ + unsigned long isr; + + isr = inb(0x20); + irq = ffz(~isr); + if (irq == 2) { + isr = inb(0xa0); + irq = 8 + ffz(~isr); + } + + if (irq < 0 || irq > 15) + return -EINVAL; + + return I8259_IRQ_BASE + irq; +} + +static struct irqaction i8259_slave_cascade = { + .handler = &no_action, + .name = "cascade", +}; + +void __init rockhopper_init_irq(void) +{ + int i; + + if(!vr4133_rockhopper) { + printk(KERN_ERR "Not a Rockhopper Board \n"); + return; + } + + for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) + irq_desc[i].handler = &i8259_irq_type; + + setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); + + vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH); + vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH); + vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number); +} Index: linux/arch/mips/vr41xx/nec-cmbvr4133/Makefile =================================================================== --- /dev/null +++ linux/arch/mips/vr41xx/nec-cmbvr4133/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the NEC-CMBVR4133 +# + +obj-y := init.o setup.o + +obj-$(CONFIG_PCI) += m1535plus.o +obj-$(CONFIG_ROCKHOPPER) += irq.o Index: linux/arch/mips/Makefile =================================================================== --- linux.orig/arch/mips/Makefile +++ linux/arch/mips/Makefile @@ -486,6 +486,12 @@ cflags-$(CONFIG_MACH_VR41XX) += -Iinclude/asm-mips/mach-vr41xx # +# NEC VR4133 +# +core-$(CONFIG_NEC_CMBVR4133) += arch/mips/vr41xx/nec-cmbvr4133/ +load-$(CONFIG_NEC_CMBVR4133) += 0xffffffff80100000 + +# # ZAO Networks Capcella (VR4131) # core-$(CONFIG_ZAO_CAPCELLA) += arch/mips/vr41xx/zao-capcella/ Index: linux/arch/mips/Kconfig =================================================================== --- linux.orig/arch/mips/Kconfig +++ linux/arch/mips/Kconfig @@ -69,6 +69,21 @@ config MACH_VR41XX bool "Support for NEC VR41XX-based machines" +config NEC_CMBVR4133 + bool "Support for NEC CMB-VR4133" + depends on MACH_VR41XX + select CPU_VR41XX + select DMA_NONCOHERENT + select IRQ_CPU + select HW_HAS_PCI + select PCI_VR41XX + +config ROCKHOPPER + bool "Support for Rockhopper baseboard" + depends on NEC_CMBVR4133 + select I8259 + select HAVE_STD_PC_SERIAL_PORT + config CASIO_E55 bool "Support for CASIO CASSIOPEIA E-10/15/55/65" depends on MACH_VR41XX Index: linux/include/asm-mips/bootinfo.h =================================================================== --- linux.orig/include/asm-mips/bootinfo.h +++ linux/include/asm-mips/bootinfo.h @@ -195,6 +195,7 @@ #define MACH_CASIO_E55 5 /* CASIO CASSIOPEIA E-10/15/55/65 */ #define MACH_TANBAC_TB0226 6 /* TANBAC TB0226 (Mbase) */ #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */ +#define MACH_NEC_CMBVR4133 8 /* CMB VR4133 Board */ #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */ #define MACH_HP_LASERJET 1 Index: linux/arch/mips/pci/Makefile =================================================================== --- linux.orig/arch/mips/pci/Makefile +++ linux/arch/mips/pci/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_MIPS_TX3927) += ops-jmr3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o +obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o # # These are still pretty much in the old state, watch, go blind. Index: linux/arch/mips/pci/fixup-vr4133.c =================================================================== --- /dev/null +++ linux/arch/mips/pci/fixup-vr4133.c @@ -0,0 +1,214 @@ +/* + * arch/mips/vr41xx/nec-cmbvr4133/pci_fixup.c + * + * The NEC CMB-VR4133 Board specific PCI fixups. + * + * Author: Yoichi Yuasa and + * Alex Sapkov + * + * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Modified for support in 2.6 + * Author: Manish Lachwani (mlachwani@mvista.com) + * + */ +#include +#include +#include + +#include +#include + +extern int vr4133_rockhopper; +extern void ali_m1535plus_init(struct pci_dev *dev); +extern void ali_m5229_init(struct pci_dev *dev); + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + if (dev->vendor == PCI_VENDOR_ID_AL) { + switch (dev->device) { + case PCI_DEVICE_ID_AL_M1533: + ali_m1535plus_init(dev); + break; + case PCI_DEVICE_ID_AL_M5229: + ali_m5229_init(dev); + break; + case PCI_DEVICE_ID_AL_M5237: + break; + } + } + + /* + * We have to reset AMD PCnet adapter on Rockhopper since + * PMON leaves it enabled and generating interrupts. This leads + * to a lock if some PCI device driver later enables the IRQ line + * shared with PCnet and there is no AMD PCnet driver to catch its + * interrupts. + */ +#ifdef CONFIG_ROCKHOPPER + if (dev->vendor == PCI_VENDOR_ID_AMD && + dev->device == PCI_DEVICE_ID_AMD_LANCE) { + inl(pci_resource_start(dev, 0) + 0x18); + } +#endif + + /* + * we have to open the bridges' windows down to 0 because otherwise + * we cannot access ISA south bridge I/O registers that get mapped from + * 0. for example, 8259 PIC would be unaccessible without that + */ + if(dev->vendor == 0x8086 && dev->device == 0xb152) { + pci_write_config_byte(dev, PCI_IO_BASE, 0); + if(dev->bus->number == 0) { + pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0); + } else { + pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 1); + } + } + + return 0; +} + +/* + * M1535 IRQ mapping + * Feel free to change this, although it shouldn't be needed + */ +#define M1535_IRQ_INTA 7 +#define M1535_IRQ_INTB 9 +#define M1535_IRQ_INTC 10 +#define M1535_IRQ_INTD 11 + +#define M1535_IRQ_USB 9 +#define M1535_IRQ_IDE 14 +#define M1535_IRQ_IDE2 15 +#define M1535_IRQ_PS2 12 +#define M1535_IRQ_RTC 8 +#define M1535_IRQ_FDC 6 +#define M1535_IRQ_AUDIO 5 +#define M1535_IRQ_COM1 4 +#define M1535_IRQ_COM2 4 +#define M1535_IRQ_IRDA 3 +#define M1535_IRQ_KBD 1 +#define M1535_IRQ_TMR 0 + +/* Rockhopper "slots" assignment; this is hard-coded ... */ +#define ROCKHOPPER_M5451_SLOT 1 +#define ROCKHOPPER_M1535_SLOT 2 +#define ROCKHOPPER_M5229_SLOT 11 +#define ROCKHOPPER_M5237_SLOT 15 +#define ROCKHOPPER_PMU_SLOT 12 +/* ... and hard-wired. */ +#define ROCKHOPPER_PCI1_SLOT 3 +#define ROCKHOPPER_PCI2_SLOT 4 +#define ROCKHOPPER_PCI3_SLOT 5 +#define ROCKHOPPER_PCI4_SLOT 6 +#define ROCKHOPPER_PCNET_SLOT 1 + +#define M1535_IRQ_MASK(n) (1 << (n)) + +#define M1535_IRQ_EDGE (M1535_IRQ_MASK(M1535_IRQ_TMR) | \ + M1535_IRQ_MASK(M1535_IRQ_KBD) | \ + M1535_IRQ_MASK(M1535_IRQ_COM1) | \ + M1535_IRQ_MASK(M1535_IRQ_COM2) | \ + M1535_IRQ_MASK(M1535_IRQ_IRDA) | \ + M1535_IRQ_MASK(M1535_IRQ_RTC) | \ + M1535_IRQ_MASK(M1535_IRQ_FDC) | \ + M1535_IRQ_MASK(M1535_IRQ_PS2)) + +#define M1535_IRQ_LEVEL (M1535_IRQ_MASK(M1535_IRQ_IDE) | \ + M1535_IRQ_MASK(M1535_IRQ_USB) | \ + M1535_IRQ_MASK(M1535_IRQ_INTA) | \ + M1535_IRQ_MASK(M1535_IRQ_INTB) | \ + M1535_IRQ_MASK(M1535_IRQ_INTC) | \ + M1535_IRQ_MASK(M1535_IRQ_INTD)) + +struct irq_map_entry { + u16 bus; + u8 slot; + u8 irq; +}; +static struct irq_map_entry int_map[] = { + {1, ROCKHOPPER_M5451_SLOT, M1535_IRQ_AUDIO}, /* Audio controller */ + {1, ROCKHOPPER_PCI1_SLOT, M1535_IRQ_INTD}, /* PCI slot #1 */ + {1, ROCKHOPPER_PCI2_SLOT, M1535_IRQ_INTC}, /* PCI slot #2 */ + {1, ROCKHOPPER_M5237_SLOT, M1535_IRQ_USB}, /* USB host controller */ + {1, ROCKHOPPER_M5229_SLOT, IDE_PRIMARY_IRQ}, /* IDE controller */ + {2, ROCKHOPPER_PCNET_SLOT, M1535_IRQ_INTD}, /* AMD Am79c973 on-board + ethernet */ + {2, ROCKHOPPER_PCI3_SLOT, M1535_IRQ_INTB}, /* PCI slot #3 */ + {2, ROCKHOPPER_PCI4_SLOT, M1535_IRQ_INTC} /* PCI slot #4 */ +}; + +static int pci_intlines[] = + { M1535_IRQ_INTA, M1535_IRQ_INTB, M1535_IRQ_INTC, M1535_IRQ_INTD }; + +/* Determine the Rockhopper IRQ line number for the PCI device */ +int rockhopper_get_irq(struct pci_dev *dev, u8 pin, u8 slot) +{ + struct pci_bus *bus; + int i; + + bus = dev->bus; + if (bus == NULL) + return -1; + + for (i = 0; i < sizeof (int_map) / sizeof (int_map[0]); i++) { + if (int_map[i].bus == bus->number && int_map[i].slot == slot) { + int line; + for (line = 0; line < 4; line++) + if (pci_intlines[line] == int_map[i].irq) + break; + if (line < 4) + return pci_intlines[(line + (pin - 1)) % 4]; + else + return int_map[i].irq; + } + } + return -1; +} + +#ifdef CONFIG_ROCKHOPPER +static void i8259_init(void) +{ + outb(0x11, 0x20); /* Master ICW1 */ + outb(I8259_IRQ_BASE, 0x21); /* Master ICW2 */ + outb(0x04, 0x21); /* Master ICW3 */ + outb(0x01, 0x21); /* Master ICW4 */ + outb(0xff, 0x21); /* Master IMW */ + + outb(0x11, 0xa0); /* Slave ICW1 */ + outb(I8259_IRQ_BASE + 8, 0xa1); /* Slave ICW2 */ + outb(0x02, 0xa1); /* Slave ICW3 */ + outb(0x01, 0xa1); /* Slave ICW4 */ + outb(0xff, 0xa1); /* Slave IMW */ + + outb(0x00, 0x4d0); + outb(0x02, 0x4d1); /* USB IRQ9 is level */ +} +#endif + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + extern int pci_probe_only; + pci_probe_only = 1; + +#ifdef CONFIG_ROCKHOPPER + i8259_init(); + if( dev->bus->number == 1 && vr4133_rockhopper ) { + if(slot == ROCKHOPPER_PCI1_SLOT || slot == ROCKHOPPER_PCI2_SLOT) + dev->irq = CMBVR41XX_INTA_IRQ; + else + dev->irq = rockhopper_get_irq(dev, pin, slot); + } else + dev->irq = CMBVR41XX_INTA_IRQ; +#else + dev->irq = CMBVR41XX_INTA_IRQ; +#endif + + return dev->irq; +} + Index: linux/include/asm-mips/vr41xx/cmbvr4133.h =================================================================== --- /dev/null +++ linux/include/asm-mips/vr41xx/cmbvr4133.h @@ -0,0 +1,63 @@ +/* + * include/asm-mips/vr41xx/cmbvr4133.h + * + * Include file for NEC CMB-VR4133. + * + * Author: Yoichi Yuasa and + * Jun Sun and + * Alex Sapkov + * + * 2002-2004 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __NEC_CMBVR4133_H +#define __NEC_CMBVR4133_H + +#include + +#include +#include + +/* + * General-Purpose I/O Pin Number + */ +#define CMBVR41XX_INTA_PIN 1 +#define CMBVR41XX_INTB_PIN 1 +#define CMBVR41XX_INTC_PIN 3 +#define CMBVR41XX_INTD_PIN 1 +#define CMBVR41XX_INTE_PIN 1 + +/* + * Interrupt Number + */ +#define CMBVR41XX_INTA_IRQ GIU_IRQ(CMBVR41XX_INTA_PIN) +#define CMBVR41XX_INTB_IRQ GIU_IRQ(CMBVR41XX_INTB_PIN) +#define CMBVR41XX_INTC_IRQ GIU_IRQ(CMBVR41XX_INTC_PIN) +#define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN) +#define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN) + +#define I8259_IRQ_BASE 72 +#define I8259_IRQ(x) (I8259_IRQ_BASE + (x)) +#define TIMER_IRQ I8259_IRQ(0) +#define KEYBOARD_IRQ I8259_IRQ(1) +#define I8259_SLAVE_IRQ I8259_IRQ(2) +#define UART3_IRQ I8259_IRQ(3) +#define UART1_IRQ I8259_IRQ(4) +#define UART2_IRQ I8259_IRQ(5) +#define FDC_IRQ I8259_IRQ(6) +#define PARPORT_IRQ I8259_IRQ(7) +#define RTC_IRQ I8259_IRQ(8) +#define USB_IRQ I8259_IRQ(9) +#define I8259_INTA_IRQ I8259_IRQ(10) +#define AUDIO_IRQ I8259_IRQ(11) +#define AUX_IRQ I8259_IRQ(12) +#define IDE_PRIMARY_IRQ I8259_IRQ(14) +#define IDE_SECONDARY_IRQ I8259_IRQ(15) +#define I8259_IRQ_LAST IDE_SECONDARY_IRQ + +#define RTC_PORT(x) (0xaf000100 + (x)) +#define RTC_IO_EXTENT 0x140 + +#endif /* __NEC_CMBVR4133_H */ --hQiwHBbRI9kgIhsi-- From ralf.roesch@rw-gmbh.de Sat Nov 20 09:40:14 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Nov 2004 09:40:18 +0000 (GMT) Received: from fw01.bwg.de ([IPv6:::ffff:213.69.156.2]:12708 "EHLO fw01.bwg.de") by linux-mips.org with ESMTP id ; Sat, 20 Nov 2004 09:40:14 +0000 Received: from fw01.bwg.de (localhost [127.0.0.1]) by fw01.bwg.de (8.11.6p2G/8.11.6) with ESMTP id iAK9eCR15962 for ; Sat, 20 Nov 2004 10:40:12 +0100 (CET) Received: (from localhost) by fw01.bwg.de (MSCAN) id 3/fw01.bwg.de/smtp-gw/mscan; Sat Nov 20 10:40:12 2004 From: =?iso-8859-1?Q?Ralf_R=F6sch?= To: Subject: [PATCH] Fix for Toshiba tx4297.h Date: Sat, 20 Nov 2004 10:40:20 +0100 Message-ID: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0023_01C4CEED.5579E780" X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook IMO, Build 9.0.6604 (9.0.2911.0) X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 Importance: Normal Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6372 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf.roesch@rw-gmbh.de Precedence: bulk X-list: linux-mips Content-Length: 5329 Lines: 105 This is a multi-part message in MIME format. ------=_NextPart_000_0023_01C4CEED.5579E780 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit This patch fixes wrong address registers for the TX4927. I have checked against the TMPR4927A data sheet and tested with some of the registers. The patch included is against 2.6. Could anyone review and apply please? Thanks and regards Ralf Roesch ------=_NextPart_000_0023_01C4CEED.5579E780 Content-Type: application/octet-stream; name="tx4927.h-2004-11-18-rnw.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="tx4927.h-2004-11-18-rnw.patch" Index: include/asm-mips/tx4927/tx4927.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /home/cvs/linux/include/asm-mips/tx4927/tx4927.h,v=0A= retrieving revision 1.2=0A= diff -u -r1.2 tx4927.h=0A= --- include/asm-mips/tx4927/tx4927.h 11 Apr 2003 17:28:35 -0000 1.2=0A= +++ include/asm-mips/tx4927/tx4927.h 18 Nov 2004 22:19:20 -0000=0A= @@ -88,8 +88,8 @@=0A= =0A= =0A= /* TX4927 Configuration registers (64-bit registers) */=0A= -#define TX4927_CONFIG_BASE 0xe300=0A= -#define TX4927_CONFIG_CCFG 0xe300=0A= +#define TX4927_CONFIG_BASE 0xe000=0A= +#define TX4927_CONFIG_CCFG 0xe000=0A= #define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42=0A= #define TX4927_CONFIG_CCFG_WDRST BM_41_41=0A= #define TX4927_CONFIG_CCFG_WDREXEN BM_40_40=0A= @@ -124,14 +124,14 @@=0A= #define TX4927_CONFIG_CCFG_ENDIAN BM_02_02=0A= #define TX4927_CONFIG_CCFG_ARMODE BM_01_01=0A= #define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00=0A= -#define TX4927_CONFIG_REVID 0xe308 =0A= +#define TX4927_CONFIG_REVID 0xe008 =0A= #define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63=0A= #define TX4927_CONFIG_REVID_PCODE BM_16_31=0A= #define TX4927_CONFIG_REVID_MJERREV BM_12_15=0A= #define TX4927_CONFIG_REVID_MINEREV BM_08_11=0A= #define TX4927_CONFIG_REVID_MJREV BM_04_07=0A= #define TX4927_CONFIG_REVID_MINREV BM_00_03=0A= -#define TX4927_CONFIG_PCFG 0xe310 =0A= +#define TX4927_CONFIG_PCFG 0xe010 =0A= #define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63=0A= #define TX4927_CONFIG_PCFG_DRVDATA BM_56_56=0A= #define TX4927_CONFIG_PCFG_DRVCB BM_55_55=0A= @@ -197,10 +197,10 @@=0A= #define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00=0A= #define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01=0A= #define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01=0A= -#define TX4927_CONFIG_TOEA 0xe318 =0A= +#define TX4927_CONFIG_TOEA 0xe018 =0A= #define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63=0A= #define TX4927_CONFIG_TOEA_TOEA BM_00_35=0A= -#define TX4927_CONFIG_CLKCTR 0xe320 =0A= +#define TX4927_CONFIG_CLKCTR 0xe020 =0A= #define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63=0A= #define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25=0A= #define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24=0A= @@ -223,7 +223,7 @@=0A= #define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02=0A= #define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01=0A= #define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00=0A= -#define TX4927_CONFIG_GARBC 0xe330 =0A= +#define TX4927_CONFIG_GARBC 0xe030 =0A= #define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63=0A= #define TX4927_CONFIG_GARBC_SET_09 BM_09_09=0A= #define TX4927_CONFIG_GARBC_ARBMD BM_08_08=0A= @@ -243,7 +243,7 @@=0A= #define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00=0A= #define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01=0A= #define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01=0A= -#define TX4927_CONFIG_RAMP 0xe348 =0A= +#define TX4927_CONFIG_RAMP 0xe048 =0A= #define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63=0A= #define TX4927_CONFIG_RAMP_RAMP BM_00_19=0A= #define TX4927_CONFIG_LIMIT 0xefff=0A= @@ -456,7 +456,7 @@=0A= #define TX4927_ACLC_ACINTSTS 0xf710=0A= #define TX4927_ACLC_ACINTMSTS 0xf714=0A= #define TX4927_ACLC_ACINTEN 0xf718=0A= -#define TX4927_ACLC_ACINTDIS 0xfR71c=0A= +#define TX4927_ACLC_ACINTDIS 0xf71c=0A= #define TX4927_ACLC_ACSEMAPH 0xf720=0A= #define TX4927_ACLC_ACGPIDAT 0xf740=0A= #define TX4927_ACLC_ACGPODAT 0xf744=0A= ------=_NextPart_000_0023_01C4CEED.5579E780-- From ralf@linux-mips.org Sat Nov 20 09:56:20 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Nov 2004 09:56:25 +0000 (GMT) Received: from p508B6B58.dip.t-dialin.net ([IPv6:::ffff:80.139.107.88]:50546 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Sat, 20 Nov 2004 09:56:20 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAK9tB0E025878; Sat, 20 Nov 2004 10:55:11 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAK9skr4025850; Sat, 20 Nov 2004 10:54:46 +0100 Date: Sat, 20 Nov 2004 10:54:46 +0100 From: Ralf Baechle To: TheNop Cc: linux-mips@linux-mips.org Subject: Re: Titan ethernet driver broken Message-ID: <20041120095445.GA12870@linux-mips.org> References: <419D03DE.8090403@gmx.net> <419D04AA.50508@mvista.com> <419D171E.5040507@gmx.net> <419D173E.6050602@mvista.com> <419D1A2D.5000009@gmx.net> <419D1F76.6010603@gmx.net> <419D20C9.10909@mvista.com> <419D25A7.2090506@gmx.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <419D25A7.2090506@gmx.net> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6373 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1008 Lines: 24 On Thu, Nov 18, 2004 at 11:43:51PM +0100, TheNop wrote: > I use the chip version 1.1. > Now I have the problem, that I can not use the newest code, until 1.2 > version of the chip is available. > Is it possible to make the code usable for all chip version by choosing > the version at the kernel configuration? Titan 1.2 is available since quite a while - the dust on my board is proof ;-) Since Titan 1.0 and 1.0 were shipped in very low numbers to early customers only and will never be available in volume production the support for them was removed. As I recall there were at least these problems with Titan 1.0 and 1.1 in Linux: - Linux uses the prefetch prepare for store operation. - Coherency mode 5 which is mandatory for good performance and any kind of sanity on SMP is now being used. - The problem with the third ethernet port which Manish just had described. You can dig through XCVS, WebCVS or the linux-cvs archive to find where I broke backward compatibility. Ralf From ica2_ts@csv.ica.uni-stuttgart.de Sun Nov 21 02:40:23 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 02:40:28 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:22535 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 02:40:23 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CVheI-0004cU-00; Sun, 21 Nov 2004 03:40:22 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CVheG-0004ia-00; Sun, 21 Nov 2004 03:40:20 +0100 Date: Sun, 21 Nov 2004 03:40:20 +0100 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Fix ip22 console init Message-ID: <20041121024020.GJ20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6374 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 1615 Lines: 59 Hello All, this patch fixes the serial console init for ip22. Currently the console gets registered twice, with the funny effect of an endless which continuosly prints the first line of the printk buffer. Thiemo Index: drivers/serial/ip22zilog.c =================================================================== RCS file: /home/cvs/linux/drivers/serial/ip22zilog.c,v retrieving revision 1.15 diff -u -p -r1.15 ip22zilog.c --- drivers/serial/ip22zilog.c 28 Sep 2004 19:22:07 -0000 1.15 +++ drivers/serial/ip22zilog.c 20 Nov 2004 16:46:58 -0000 @@ -1100,28 +1100,19 @@ static struct console ip22zilog_console .index = -1, .data = &ip22zilog_reg, }; -#define IP22ZILOG_CONSOLE (&ip22zilog_console) - -static int __init ip22zilog_console_init(void) -{ - register_console(&ip22zilog_console); - return 0; -} -#else /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */ -#define IP22ZILOG_CONSOLE (NULL) -#define ip22zilog_console_init() do { } while (0) -#endif +#endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */ static struct uart_driver ip22zilog_reg = { .owner = THIS_MODULE, .driver_name = "serial", - .devfs_name = "tty/", + .devfs_name = "tts/", .dev_name = "ttyS", .major = TTY_MAJOR, .minor = 64, .nr = NUM_CHANNELS, - .cons = IP22ZILOG_CONSOLE, - +#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE + .cons = &ip22zilog_console, +#endif }; static void __init ip22zilog_prepare(void) @@ -1254,7 +1245,6 @@ static int __init ip22zilog_init(void) /* IP22 Zilog setup is hard coded, no probing to do. */ ip22zilog_alloc_tables(); ip22zilog_ports_init(); - ip22zilog_console_init(); return 0; } From ica2_ts@csv.ica.uni-stuttgart.de Sun Nov 21 02:41:45 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 02:41:50 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:24327 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 02:41:45 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CVhfc-0004dS-00; Sun, 21 Nov 2004 03:41:44 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CVhfc-0004iz-00; Sun, 21 Nov 2004 03:41:44 +0100 Date: Sun, 21 Nov 2004 03:41:44 +0100 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] ip32 build fix Message-ID: <20041121024144.GK20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6375 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 628 Lines: 24 Hello All, a simple build fix for the ip32 framebuffer. Thiemo Index: drivers/video/gbefb.c =================================================================== RCS file: /home/cvs/linux/drivers/video/gbefb.c,v retrieving revision 1.11 diff -u -p -r1.11 gbefb.c --- drivers/video/gbefb.c 16 Nov 2004 16:20:39 -0000 1.11 +++ drivers/video/gbefb.c 20 Nov 2004 16:46:58 -0000 @@ -1122,7 +1122,7 @@ static int __init gbefb_probe(struct dev if (fb_get_options("gbefb", &option)) return -ENODEV; - gbefb_setup(options); + gbefb_setup(option); #endif if (!request_mem_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) { From ica2_ts@csv.ica.uni-stuttgart.de Sun Nov 21 03:06:16 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 03:06:23 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:44551 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 03:06:16 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CVi3L-0004p2-00; Sun, 21 Nov 2004 04:06:15 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CVi3K-0004rZ-00; Sun, 21 Nov 2004 04:06:14 +0100 Date: Sun, 21 Nov 2004 04:06:14 +0100 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Improve ramdisk support Message-ID: <20041121030614.GL20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6376 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 6165 Lines: 192 Hello All, there are currently two methods to use an initial ramdisk in the kernel, either by compiling it in via CONFIG_EMBEDDED_RAMDISK or by tacking the ramdisk on the kernel image via addinitrd. A third method currently under development is a compiled in cpio archive handled via initramfs. There is, however, no way to add an initial ramdisk after the kernel was built. The appended patch introduces "rd_start" and "rd_size" command line parameters which allow a bootloader to preload the ramdisk and make its location known to the kernel by feeding appropriate rd_start/rd_size values. Debian used an earlier version of this patch for several years now. Thiemo Index: arch/mips/kernel/setup.c =================================================================== RCS file: /home/cvs/linux/arch/mips/kernel/setup.c,v retrieving revision 1.171 diff -u -p -r1.171 setup.c --- arch/mips/kernel/setup.c 28 Jun 2004 21:04:12 -0000 1.171 +++ arch/mips/kernel/setup.c 20 Nov 2004 16:46:39 -0000 @@ -194,6 +194,68 @@ static inline void parse_cmdline_early(v } } +static inline int parse_rd_cmdline(unsigned long* rd_start, unsigned long* rd_end) +{ + /* + * "rd_start=0xNNNNNNNN" defines the memory address of an initrd + * "rd_size=0xNN" it's size + */ + unsigned long start = 0; + unsigned long size = 0; + unsigned long end; + char cmd_line[CL_SIZE]; + char *start_str; + char *size_str; + char *tmp; + + strcpy(cmd_line, command_line); + *command_line = 0; + tmp = cmd_line; + /* Ignore "rd_start=" strings in other parameters. */ + start_str = strstr(cmd_line, "rd_start="); + if (start_str && start_str != cmd_line && *(start_str - 1) != ' ') + start_str = strstr(start_str, " rd_start="); + while (start_str) { + if (start_str != cmd_line) + strncat(command_line, tmp, start_str - tmp); + start = memparse(start_str + 9, &start_str); + tmp = start_str + 1; + start_str = strstr(start_str, " rd_start="); + } + if (*tmp) + strcat(command_line, tmp); + + strcpy(cmd_line, command_line); + *command_line = 0; + tmp = cmd_line; + /* Ignore "rd_size" strings in other parameters. */ + size_str = strstr(cmd_line, "rd_size="); + if (size_str && size_str != cmd_line && *(size_str - 1) != ' ') + size_str = strstr(size_str, " rd_size="); + while (size_str) { + if (size_str != cmd_line) + strncat(command_line, tmp, size_str - tmp); + size = memparse(size_str + 8, &size_str); + tmp = size_str + 1; + size_str = strstr(size_str, " rd_size="); + } + if (*tmp) + strcat(command_line, tmp); + +#ifdef CONFIG_MIPS64 + /* HACK: Guess if the sign extension was forgotten */ + if (start > 0x0000000080000000 && start < 0x00000000ffffffff) + start |= 0xffffffff00000000; +#endif + + end = start + size; + if (start && end) { + *rd_start = start; + *rd_end = end; + return 1; + } + return 0; +} #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) #define PFN_DOWN(x) ((x) >> PAGE_SHIFT) @@ -205,30 +267,45 @@ static inline void parse_cmdline_early(v static inline void bootmem_init(void) { unsigned long start_pfn; + unsigned long reserved_end = (unsigned long)&_end; #ifndef CONFIG_SGI_IP27 - unsigned long bootmap_size, max_low_pfn, first_usable_pfn; + unsigned long first_usable_pfn; + unsigned long bootmap_size; int i; #endif #ifdef CONFIG_BLK_DEV_INITRD - unsigned long tmp; - unsigned long *initrd_header; + int initrd_reserve_bootmem = 0; - tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8; - if (tmp < (unsigned long)&_end) - tmp += PAGE_SIZE; - initrd_header = (unsigned long *)tmp; - if (initrd_header[0] == 0x494E5244) { - initrd_start = (unsigned long)&initrd_header[2]; - initrd_end = initrd_start + initrd_header[1]; + /* Board specific code should have set up initrd_start and initrd_end */ + ROOT_DEV = Root_RAM0; + if (&__rd_start != &__rd_end) { + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; + } else if (parse_rd_cmdline(&initrd_start, &initrd_end)) { + reserved_end = max(reserved_end, initrd_end); + initrd_reserve_bootmem = 1; + } else { + unsigned long tmp; + unsigned long *initrd_header; + + tmp = ((reserved_end + PAGE_SIZE-1) & PAGE_MASK) - 8; + if (tmp < reserved_end) + tmp += PAGE_SIZE; + initrd_header = (unsigned long *)tmp; + if (initrd_header[0] == 0x494E5244) { + initrd_start = (unsigned long)&initrd_header[2]; + initrd_end = initrd_start + initrd_header[1]; + reserved_end = max(reserved_end, initrd_end); + initrd_reserve_bootmem = 1; + } } - start_pfn = PFN_UP(CPHYSADDR((&_end)+(initrd_end - initrd_start) + PAGE_SIZE)); -#else +#endif /* CONFIG_BLK_DEV_INITRD */ + /* * Partially used pages are not usable - thus * we are rounding upwards. */ - start_pfn = PFN_UP(CPHYSADDR(&_end)); -#endif /* CONFIG_BLK_DEV_INITRD */ + start_pfn = PFN_UP(CPHYSADDR(reserved_end)); #ifndef CONFIG_SGI_IP27 /* Find the highest page frame number we have available. */ @@ -341,21 +418,14 @@ static inline void bootmem_init(void) /* Reserve the bootmap memory. */ reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size); -#endif +#endif /* CONFIG_SGI_IP27 */ #ifdef CONFIG_BLK_DEV_INITRD - /* Board specific code should have set up initrd_start and initrd_end */ - ROOT_DEV = Root_RAM0; - if (&__rd_start != &__rd_end) { - initrd_start = (unsigned long)&__rd_start; - initrd_end = (unsigned long)&__rd_end; - } initrd_below_start_ok = 1; if (initrd_start) { unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start); printk("Initial ramdisk at: 0x%p (%lu bytes)\n", - (void *)initrd_start, - initrd_size); + (void *)initrd_start, initrd_size); if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { printk("initrd extends beyond end of memory " @@ -363,7 +433,11 @@ static inline void bootmem_init(void) sizeof(long) * 2, CPHYSADDR(initrd_end), sizeof(long) * 2, PFN_PHYS(max_low_pfn)); initrd_start = initrd_end = 0; + initrd_reserve_bootmem = 0; } + + if (initrd_reserve_bootmem) + reserve_bootmem(CPHYSADDR(initrd_start), initrd_size); } #endif /* CONFIG_BLK_DEV_INITRD */ } From ica2_ts@csv.ica.uni-stuttgart.de Sun Nov 21 03:17:15 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 03:17:22 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:48135 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 03:17:15 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CViDy-0004tf-00; Sun, 21 Nov 2004 04:17:14 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CViDy-0004sA-00; Sun, 21 Nov 2004 04:17:14 +0100 Date: Sun, 21 Nov 2004 04:17:14 +0100 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] signal handling code improvements Message-ID: <20041121031714.GM20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6377 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 13924 Lines: 452 Hello All, this patch - moves inline functions common to N32 and N64 ABI to a separate include file - remove the asmlinkage attribute from functions whic aren't actually called from asm code - makes do_signal static. - Lets sys_sigreturn, sys_rt_sigreturn, sys32_sigreturn, sys32_rt_sigreturn, sysn32_rt_sigreturn save the static registers, because the exit path tries to restore them. Thiemo Index: arch/mips/kernel/signal.c =================================================================== RCS file: /home/cvs/linux/arch/mips/kernel/signal.c,v retrieving revision 1.77 diff -u -p -r1.77 signal.c --- arch/mips/kernel/signal.c 25 Oct 2004 20:44:17 -0000 1.77 +++ arch/mips/kernel/signal.c 20 Nov 2004 16:46:39 -0000 @@ -30,11 +30,13 @@ #include #include +#include "signal64.h" + #define DEBUG_SIG 0 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) -extern asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs); +static int do_signal(sigset_t *oldset, struct pt_regs *regs); /* * Atomically swap in the new signal mask, and wait for a signal. @@ -152,51 +154,6 @@ asmlinkage int sys_sigaltstack(nabi_no_r return do_sigaltstack(uss, uoss, usp); } -asmlinkage int restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) -{ - int err = 0; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - err |= __get_user(regs->cp0_epc, &sc->sc_pc); - err |= __get_user(regs->hi, &sc->sc_mdhi); - err |= __get_user(regs->lo, &sc->sc_mdlo); - -#define restore_gp_reg(i) do { \ - err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \ -} while(0) - restore_gp_reg( 1); restore_gp_reg( 2); restore_gp_reg( 3); - restore_gp_reg( 4); restore_gp_reg( 5); restore_gp_reg( 6); - restore_gp_reg( 7); restore_gp_reg( 8); restore_gp_reg( 9); - restore_gp_reg(10); restore_gp_reg(11); restore_gp_reg(12); - restore_gp_reg(13); restore_gp_reg(14); restore_gp_reg(15); - restore_gp_reg(16); restore_gp_reg(17); restore_gp_reg(18); - restore_gp_reg(19); restore_gp_reg(20); restore_gp_reg(21); - restore_gp_reg(22); restore_gp_reg(23); restore_gp_reg(24); - restore_gp_reg(25); restore_gp_reg(26); restore_gp_reg(27); - restore_gp_reg(28); restore_gp_reg(29); restore_gp_reg(30); - restore_gp_reg(31); -#undef restore_gp_reg - - err |= __get_user(current->used_math, &sc->sc_used_math); - - preempt_disable(); - - if (current->used_math) { - /* restore fpu context if we have used it before */ - own_fpu(); - err |= restore_fp_context(sc); - } else { - /* signal handler may have used FPU. Give it up. */ - lose_fpu(); - } - - preempt_enable(); - - return err; -} - #ifdef CONFIG_TRAD_SIGNALS struct sigframe { u32 sf_ass[4]; /* argument save space for o32 */ @@ -214,7 +171,9 @@ struct rt_sigframe { }; #ifdef CONFIG_TRAD_SIGNALS -asmlinkage void sys_sigreturn(struct pt_regs regs) +save_static_function(sys_sigreturn); +__attribute_used__ noinline static void +_sys_sigreturn(nabi_no_regargs struct pt_regs regs) { struct sigframe *frame; sigset_t blocked; @@ -251,7 +210,9 @@ badframe: } #endif -asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs) +save_static_function(sys_rt_sigreturn); +__attribute_used__ noinline static void +_sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs) { struct rt_sigframe *frame; sigset_t set; @@ -292,80 +253,6 @@ badframe: force_sig(SIGSEGV, current); } -inline int setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) -{ - int err = 0; - - err |= __put_user(regs->cp0_epc, &sc->sc_pc); - err |= __put_user(regs->cp0_status, &sc->sc_status); - -#define save_gp_reg(i) do { \ - err |= __put_user(regs->regs[i], &sc->sc_regs[i]); \ -} while(0) - __put_user(0, &sc->sc_regs[0]); save_gp_reg(1); save_gp_reg(2); - save_gp_reg(3); save_gp_reg(4); save_gp_reg(5); save_gp_reg(6); - save_gp_reg(7); save_gp_reg(8); save_gp_reg(9); save_gp_reg(10); - save_gp_reg(11); save_gp_reg(12); save_gp_reg(13); save_gp_reg(14); - save_gp_reg(15); save_gp_reg(16); save_gp_reg(17); save_gp_reg(18); - save_gp_reg(19); save_gp_reg(20); save_gp_reg(21); save_gp_reg(22); - save_gp_reg(23); save_gp_reg(24); save_gp_reg(25); save_gp_reg(26); - save_gp_reg(27); save_gp_reg(28); save_gp_reg(29); save_gp_reg(30); - save_gp_reg(31); -#undef save_gp_reg - - err |= __put_user(regs->hi, &sc->sc_mdhi); - err |= __put_user(regs->lo, &sc->sc_mdlo); - err |= __put_user(regs->cp0_cause, &sc->sc_cause); - err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); - - err |= __put_user(current->used_math, &sc->sc_used_math); - - if (!current->used_math) - goto out; - - /* - * Save FPU state to signal context. Signal handler will "inherit" - * current FPU state. - */ - preempt_disable(); - - if (!is_fpu_owner()) { - own_fpu(); - restore_fp(current); - } - err |= save_fp_context(sc); - - preempt_enable(); - -out: - return err; -} - -/* - * Determine which stack to use.. - */ -static inline void *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, - size_t frame_size) -{ - unsigned long sp; - - /* Default to using normal stack */ - sp = regs->regs[29]; - - /* - * FPU emulator may have it's own trampoline active just - * above the user stack, 16-bytes before the next lowest - * 16 byte boundary. Try to avoid trashing it. - */ - sp -= 32; - - /* This is the X/Open sanctioned signal stack switching. */ - if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0)) - sp = current->sas_ss_sp + current->sas_ss_size; - - return (void *)((sp - frame_size) & ALMASK); -} - #ifdef CONFIG_TRAD_SIGNALS static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set) @@ -540,7 +427,7 @@ static inline void handle_signal(unsigne extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); extern int do_irix_signal(sigset_t *oldset, struct pt_regs *regs); -asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs) +static int do_signal(sigset_t *oldset, struct pt_regs *regs) { struct k_sigaction ka; siginfo_t info; Index: arch/mips/kernel/signal32.c =================================================================== RCS file: /home/cvs/linux/arch/mips/kernel/signal32.c,v retrieving revision 1.18 diff -u -p -r1.18 signal32.c --- arch/mips/kernel/signal32.c 11 Nov 2004 14:09:09 -0000 1.18 +++ arch/mips/kernel/signal32.c 20 Nov 2004 16:46:39 -0000 @@ -106,7 +106,7 @@ typedef struct siginfo32 { #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) -extern asmlinkage int do_signal32(sigset_t *oldset, struct pt_regs *regs); +extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); /* 32-bit compatibility types */ @@ -192,6 +192,7 @@ static inline int get_sigset(sigset_t *k /* * Atomically swap in the new signal mask, and wait for a signal. */ + save_static_function(sys32_sigsuspend); __attribute_used__ noinline static int _sys32_sigsuspend(nabi_no_regargs struct pt_regs regs) @@ -333,8 +334,7 @@ asmlinkage int sys32_sigaltstack(nabi_no return ret; } -static asmlinkage int restore_sigcontext32(struct pt_regs *regs, - struct sigcontext32 *sc) +static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc) { int err = 0; @@ -440,7 +440,9 @@ static int copy_siginfo_to_user32(siginf return err; } -asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs) +save_static_function(sys32_sigreturn); +__attribute_used__ noinline static void +_sys32_sigreturn(nabi_no_regargs struct pt_regs regs) { struct sigframe *frame; sigset_t blocked; @@ -476,7 +478,9 @@ badframe: force_sig(SIGSEGV, current); } -asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) +save_static_function(sys32_rt_sigreturn); +__attribute_used__ noinline static void +_sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) { struct rt_sigframe32 *frame; sigset_t set; @@ -759,7 +763,7 @@ static inline void handle_signal(unsigne } } -asmlinkage int do_signal32(sigset_t *oldset, struct pt_regs *regs) +int do_signal32(sigset_t *oldset, struct pt_regs *regs) { struct k_sigaction ka; siginfo_t info; Index: arch/mips/kernel/signal_n32.c =================================================================== RCS file: /home/cvs/linux/arch/mips/kernel/signal_n32.c,v retrieving revision 1.8 diff -u -p -r1.8 signal_n32.c --- arch/mips/kernel/signal_n32.c 25 Oct 2004 20:44:17 -0000 1.8 +++ arch/mips/kernel/signal_n32.c 20 Nov 2004 16:46:39 -0000 @@ -36,6 +36,8 @@ #include #include +#include "signal64.h" + /* * Including regs[29]; - - /* - * FPU emulator may have it's own trampoline active just - * above the user stack, 16-bytes before the next lowest - * 16 byte boundary. Try to avoid trashing it. - */ - sp -= 32; - - /* This is the X/Open sanctioned signal stack switching. */ - if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0)) - sp = current->sas_ss_sp + current->sas_ss_size; - - return (void *)((sp - frame_size) & ALMASK); -} - void setup_rt_frame_n32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { --- /dev/null 2004-08-24 19:23:08.000000000 +0200 +++ arch/mips/kernel/signal64.h 2004-10-27 02:12:47.000000000 +0200 @@ -0,0 +1,120 @@ +extern inline int +setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) +{ + int err = 0; + + err |= __put_user(regs->cp0_epc, &sc->sc_pc); + err |= __put_user(regs->cp0_status, &sc->sc_status); + +#define save_gp_reg(i) do { \ + err |= __put_user(regs->regs[i], &sc->sc_regs[i]); \ +} while(0) + __put_user(0, &sc->sc_regs[0]); save_gp_reg(1); save_gp_reg(2); + save_gp_reg(3); save_gp_reg(4); save_gp_reg(5); save_gp_reg(6); + save_gp_reg(7); save_gp_reg(8); save_gp_reg(9); save_gp_reg(10); + save_gp_reg(11); save_gp_reg(12); save_gp_reg(13); save_gp_reg(14); + save_gp_reg(15); save_gp_reg(16); save_gp_reg(17); save_gp_reg(18); + save_gp_reg(19); save_gp_reg(20); save_gp_reg(21); save_gp_reg(22); + save_gp_reg(23); save_gp_reg(24); save_gp_reg(25); save_gp_reg(26); + save_gp_reg(27); save_gp_reg(28); save_gp_reg(29); save_gp_reg(30); + save_gp_reg(31); +#undef save_gp_reg + + err |= __put_user(regs->hi, &sc->sc_mdhi); + err |= __put_user(regs->lo, &sc->sc_mdlo); + err |= __put_user(regs->cp0_cause, &sc->sc_cause); + err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); + + err |= __put_user(current->used_math, &sc->sc_used_math); + + if (!current->used_math) + goto out; + + /* + * Save FPU state to signal context. Signal handler will "inherit" + * current FPU state. + */ + preempt_disable(); + + if (!is_fpu_owner()) { + own_fpu(); + restore_fp(current); + } + err |= save_fp_context(sc); + + preempt_enable(); + +out: + return err; +} + +extern inline int +restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) +{ + int err = 0; + + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + + err |= __get_user(regs->cp0_epc, &sc->sc_pc); + err |= __get_user(regs->hi, &sc->sc_mdhi); + err |= __get_user(regs->lo, &sc->sc_mdlo); + +#define restore_gp_reg(i) do { \ + err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \ +} while(0) + restore_gp_reg( 1); restore_gp_reg( 2); restore_gp_reg( 3); + restore_gp_reg( 4); restore_gp_reg( 5); restore_gp_reg( 6); + restore_gp_reg( 7); restore_gp_reg( 8); restore_gp_reg( 9); + restore_gp_reg(10); restore_gp_reg(11); restore_gp_reg(12); + restore_gp_reg(13); restore_gp_reg(14); restore_gp_reg(15); + restore_gp_reg(16); restore_gp_reg(17); restore_gp_reg(18); + restore_gp_reg(19); restore_gp_reg(20); restore_gp_reg(21); + restore_gp_reg(22); restore_gp_reg(23); restore_gp_reg(24); + restore_gp_reg(25); restore_gp_reg(26); restore_gp_reg(27); + restore_gp_reg(28); restore_gp_reg(29); restore_gp_reg(30); + restore_gp_reg(31); +#undef restore_gp_reg + + err |= __get_user(current->used_math, &sc->sc_used_math); + + preempt_disable(); + + if (current->used_math) { + /* restore fpu context if we have used it before */ + own_fpu(); + err |= restore_fp_context(sc); + } else { + /* signal handler may have used FPU. Give it up. */ + lose_fpu(); + } + + preempt_enable(); + + return err; +} + +/* + * Determine which stack to use.. + */ +extern inline void * +get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) +{ + unsigned long sp; + + /* Default to using normal stack */ + sp = regs->regs[29]; + + /* + * FPU emulator may have it's own trampoline active just + * above the user stack, 16-bytes before the next lowest + * 16 byte boundary. Try to avoid trashing it. + */ + sp -= 32; + + /* This is the X/Open sanctioned signal stack switching. */ + if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0)) + sp = current->sas_ss_sp + current->sas_ss_size; + + return (void *)((sp - frame_size) & ALMASK); +} From ica2_ts@csv.ica.uni-stuttgart.de Sun Nov 21 03:20:51 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 03:20:55 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:49927 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 03:20:51 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CViHS-0004vW-00; Sun, 21 Nov 2004 04:20:50 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CViHS-0004tD-00; Sun, 21 Nov 2004 04:20:50 +0100 Date: Sun, 21 Nov 2004 04:20:50 +0100 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Canonicalize mmap addresses to unsigned long Message-ID: <20041121032050.GN20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6378 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 2015 Lines: 62 Hello All, this patch canonicalizes address arguments and returns from a mixture of "unsigned long", "long" and "size_t" to "unsigned long". Thiemo Index: arch/mips/kernel/syscall.c =================================================================== RCS file: /home/cvs/linux/arch/mips/kernel/syscall.c,v retrieving revision 1.46 diff -u -p -r1.46 syscall.c --- arch/mips/kernel/syscall.c 19 Sep 2004 12:30:04 -0000 1.46 +++ arch/mips/kernel/syscall.c 20 Nov 2004 16:46:39 -0000 @@ -116,7 +116,7 @@ unsigned long arch_get_unmapped_area(str } /* common code for old and new mmaps */ -static inline long +static inline unsigned long do_mmap2(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, unsigned long fd, unsigned long pgoff) { @@ -140,8 +140,9 @@ out: return error; } -asmlinkage unsigned long old_mmap(unsigned long addr, size_t len, int prot, - int flags, int fd, off_t offset) +asmlinkage unsigned long +old_mmap(unsigned long addr, unsigned long len, int prot, + int flags, int fd, off_t offset) { unsigned long result; @@ -155,7 +156,7 @@ out: return result; } -asmlinkage long +asmlinkage unsigned long sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, unsigned long fd, unsigned long pgoff) { Index: arch/mips/kernel/linux32.c =================================================================== RCS file: /home/cvs/linux/arch/mips/kernel/linux32.c,v retrieving revision 1.21 diff -u -p -r1.21 linux32.c --- arch/mips/kernel/linux32.c 13 Aug 2004 07:18:52 -0000 1.21 +++ arch/mips/kernel/linux32.c 20 Nov 2004 16:46:38 -0000 @@ -99,7 +99,7 @@ int cp_compat_stat(struct kstat *stat, s } asmlinkage unsigned long -sys32_mmap2(unsigned long addr, size_t len, unsigned long prot, +sys32_mmap2(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, unsigned long fd, unsigned long pgoff) { struct file * file = NULL; From ralf@linux-mips.org Sun Nov 21 06:58:33 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 06:58:38 +0000 (GMT) Received: from p508B7F2C.dip.t-dialin.net ([IPv6:::ffff:80.139.127.44]:15383 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 06:58:33 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAL6uWL7007596; Sun, 21 Nov 2004 07:56:32 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAL6uUY9007595; Sun, 21 Nov 2004 07:56:30 +0100 Date: Sun, 21 Nov 2004 07:56:30 +0100 From: Ralf Baechle To: Thiemo Seufer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] ip32 build fix Message-ID: <20041121065630.GA6701@linux-mips.org> References: <20041121024144.GK20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041121024144.GK20986@rembrandt.csv.ica.uni-stuttgart.de> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6379 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 137 Lines: 7 On Sun, Nov 21, 2004 at 03:41:44AM +0100, Thiemo Seufer wrote: > a simple build fix for the ip32 framebuffer. Thanks, applied. Ralf From mlachwani@mvista.com Sun Nov 21 07:26:06 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 07:26:12 +0000 (GMT) Received: from gateway-1237.mvista.com ([IPv6:::ffff:12.44.186.158]:53230 "EHLO hermes.mvista.com") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 07:26:06 +0000 Received: from mvista.com (prometheus.mvista.com [10.0.0.139]) by hermes.mvista.com (Postfix) with ESMTP id AA3AA185CB; Sat, 20 Nov 2004 23:26:03 -0800 (PST) Message-ID: <41A0430B.6080201@mvista.com> Date: Sat, 20 Nov 2004 23:26:03 -0800 From: Manish Lachwani User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 X-Accept-Language: en-us, en MIME-Version: 1.0 To: Ralf Baechle Cc: TheNop , linux-mips@linux-mips.org Subject: Re: Titan ethernet driver broken References: <419D03DE.8090403@gmx.net> <419D04AA.50508@mvista.com> <419D171E.5040507@gmx.net> <419D173E.6050602@mvista.com> <419D1A2D.5000009@gmx.net> <419D1F76.6010603@gmx.net> <419D20C9.10909@mvista.com> <419D25A7.2090506@gmx.net> <20041120095445.GA12870@linux-mips.org> In-Reply-To: <20041120095445.GA12870@linux-mips.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6380 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlachwani@mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1858 Lines: 51 Ralf Baechle wrote: > On Thu, Nov 18, 2004 at 11:43:51PM +0100, TheNop wrote: > > >>I use the chip version 1.1. >>Now I have the problem, that I can not use the newest code, until 1.2 >>version of the chip is available. >>Is it possible to make the code usable for all chip version by choosing >>the version at the kernel configuration? > > > Titan 1.2 is available since quite a while - the dust on my board is > proof ;-) Since Titan 1.0 and 1.0 were shipped in very low numbers to > early customers only and will never be available in volume production the > support for them was removed. As I recall there were at least these > problems with Titan 1.0 and 1.1 in Linux: > > - Linux uses the prefetch prepare for store operation. > - Coherency mode 5 which is mandatory for good performance and any kind > of sanity on SMP is now being used. > - The problem with the third ethernet port which Manish just had > described. > > You can dig through XCVS, WebCVS or the linux-cvs archive to find where > I broke backward compatibility. > > Ralf > Hello ! Ralf, thanks for the good description. Anyways, just to make it a little more clear. Port #2 (third ethernet port) was not working on Titan 1.0 and 1.1. This is because there is no interrupt line on which interrupts for port #2 could be routed. And Titan MACs cannot share interrupts. One other problem with 1.0 and 1.1 was that for incoming packets, the IP header is not aligned. As a result, an extra copy was implemented in the driver to align this IP header. This problem exists on all ports (0 and 1). With Titan 1.2, there is no need for the extra copy and port #2 can be enabled since there is an interrupt line which it can use. And of course, 1.0 and 1.1 did not support the five state MOESI protocol. They supported MEI only. Thanks Manish Lachwani From geert@linux-m68k.org Sun Nov 21 09:18:30 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 09:18:35 +0000 (GMT) Received: from witte.sonytel.be ([IPv6:::ffff:80.88.33.193]:43491 "EHLO witte.sonytel.be") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 09:18:29 +0000 Received: from waterleaf.sonytel.be (mail.sonytel.be [43.221.60.197]) by witte.sonytel.be (8.12.10/8.12.10) with ESMTP id iAL9IQGU013647; Sun, 21 Nov 2004 10:18:27 +0100 (MET) Date: Sun, 21 Nov 2004 10:18:26 +0100 (MET) From: Geert Uytterhoeven To: Ralf Baechle cc: Thiemo Seufer , Linux/MIPS Development Subject: Re: [PATCH] ip32 build fix In-Reply-To: <20041121065630.GA6701@linux-mips.org> Message-ID: References: <20041121024144.GK20986@rembrandt.csv.ica.uni-stuttgart.de> <20041121065630.GA6701@linux-mips.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6381 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Content-Length: 1695 Lines: 56 On Sun, 21 Nov 2004, Ralf Baechle wrote: > On Sun, Nov 21, 2004 at 03:41:44AM +0100, Thiemo Seufer wrote: > > a simple build fix for the ip32 framebuffer. > > Thanks, applied. FYI, this has been fixed differently in mainline: On Fri, 19 Nov 2004, Linux Kernel Mailing List wrote: | ChangeSet 1.2183, 2004/11/19 14:54:09-08:00, giuseppe@eppesuigoccas.homedns.org | | [PATCH] gbefb.c build fix | | The current gbefb.c source cannot be compiled as module because of a small | typo where "option" was written instead of "options" in two places. | | Signed-off-by: Andrew Morton | Signed-off-by: Linus Torvalds | | | | gbefb.c | 4 ++-- | 1 files changed, 2 insertions(+), 2 deletions(-) | | | diff -Nru a/drivers/video/gbefb.c b/drivers/video/gbefb.c | --- a/drivers/video/gbefb.c 2004-11-19 16:11:11 -08:00 | +++ b/drivers/video/gbefb.c 2004-11-19 16:11:11 -08:00 | @@ -1084,9 +1084,9 @@ | int i, ret = 0; | | #ifndef MODULE | - char *option = NULL; | + char *options = NULL; | | - if (fb_get_options("gbefb", &option)) | + if (fb_get_options("gbefb", &options)) | return -ENODEV; | gbefb_setup(options); | #endif | - | To unsubscribe from this list: send the line "unsubscribe bk-commits-head" in | the body of a message to majordomo@vger.kernel.org | More majordomo info at http://vger.kernel.org/majordomo-info.html | Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From ica2_ts@csv.ica.uni-stuttgart.de Sun Nov 21 16:20:59 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 16:21:05 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:51982 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 16:20:59 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CVuSQ-0002Lv-00; Sun, 21 Nov 2004 17:20:58 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CVuSM-0006mY-00; Sun, 21 Nov 2004 17:20:54 +0100 Date: Sun, 21 Nov 2004 17:20:54 +0100 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Re: [PATCH] Improve ramdisk support Message-ID: <20041121162054.GO20986@rembrandt.csv.ica.uni-stuttgart.de> References: <20041121030614.GL20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041121030614.GL20986@rembrandt.csv.ica.uni-stuttgart.de> User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6382 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 11216 Lines: 343 Thiemo Seufer wrote: > Hello All, > > there are currently two methods to use an initial ramdisk in the > kernel, either by compiling it in via CONFIG_EMBEDDED_RAMDISK or by > tacking the ramdisk on the kernel image via addinitrd. A third method > currently under development is a compiled in cpio archive handled via > initramfs. > > There is, however, no way to add an initial ramdisk after the kernel > was built. The appended patch introduces "rd_start" and "rd_size" > command line parameters which allow a bootloader to preload the > ramdisk and make its location known to the kernel by feeding > appropriate rd_start/rd_size values. > > Debian used an earlier version of this patch for several years now. CONFIG_EMBEDDED_RAMDISK is gone now. The updated patch below removes some leftovers. Thiemo Index: arch/mips/au1000/common/setup.c =================================================================== RCS file: /home/cvs/linux/arch/mips/au1000/common/setup.c,v retrieving revision 1.20 diff -u -p -r1.20 setup.c --- arch/mips/au1000/common/setup.c 11 Oct 2004 20:01:14 -0000 1.20 +++ arch/mips/au1000/common/setup.c 21 Nov 2004 16:14:03 -0000 @@ -42,11 +42,6 @@ #include #include -#ifdef CONFIG_BLK_DEV_INITRD -extern unsigned long initrd_start, initrd_end; -extern void * __rd_start, * __rd_end; -#endif - extern char * __init prom_getcmdline(void); extern void __init board_setup(void); extern void au1000_restart(char *); @@ -153,12 +148,6 @@ static int __init au1x00_setup(void) iomem_resource.start = IOMEM_RESOURCE_START; iomem_resource.end = IOMEM_RESOURCE_END; -#ifdef CONFIG_BLK_DEV_INITRD - ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); - initrd_start = (unsigned long)&__rd_start; - initrd_end = (unsigned long)&__rd_end; -#endif - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); au_sync(); Index: arch/mips/dec/setup.c =================================================================== RCS file: /home/cvs/linux/arch/mips/dec/setup.c,v retrieving revision 1.41 diff -u -p -r1.41 setup.c --- arch/mips/dec/setup.c 20 Aug 2004 09:19:01 -0000 1.41 +++ arch/mips/dec/setup.c 21 Nov 2004 16:14:03 -0000 @@ -48,11 +48,6 @@ extern irqreturn_t dec_intr_halt(int irq extern asmlinkage void decstation_handle_int(void); -#ifdef CONFIG_BLK_DEV_INITRD -extern unsigned long initrd_start, initrd_end; -extern void * __rd_start, * __rd_end; -#endif - spinlock_t ioasic_ssr_lock; volatile u32 *ioasic_base; @@ -136,11 +131,6 @@ extern void dec_timer_setup(struct irqac static void __init decstation_setup(void) { -#ifdef CONFIG_BLK_DEV_INITRD - ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); - initrd_start = (unsigned long)&__rd_start; - initrd_end = (unsigned long)&__rd_end; -#endif board_be_init = dec_be_init; board_time_init = dec_time_init; board_timer_setup = dec_timer_setup; Index: arch/mips/dec/boot/decstation.c =================================================================== RCS file: /home/cvs/linux/arch/mips/dec/boot/decstation.c,v retrieving revision 1.2 diff -u -p -r1.2 decstation.c --- arch/mips/dec/boot/decstation.c 4 Jun 2003 18:14:26 -0000 1.2 +++ arch/mips/dec/boot/decstation.c 21 Nov 2004 16:14:03 -0000 @@ -26,7 +26,6 @@ #define INITRD_SIZE (*(unsigned long *) (PARAM+0x21c)) extern int _ftext, _end; /* begin and end of kernel image */ -extern void *__rd_start, *__rd_end; /* begin and end of ramdisk image */ extern void kernel_entry(int, char **, unsigned long, int *); void * memcpy(void * dest, const void *src, unsigned int count) @@ -81,11 +80,5 @@ void dec_entry(int argc, char **argv, rex_clear_cache(); } -#ifdef CONFIG_BLK_DEV_INITRD - LOADER_TYPE = 1; - INITRD_START = (long)&__rd_start; - INITRD_SIZE = (long)&__rd_end - (long)&__rd_start; -#endif - kernel_entry(argc, argv, magic, prom_vec); } Index: arch/mips/jmr3927/rbhma3100/setup.c =================================================================== RCS file: /home/cvs/linux/arch/mips/jmr3927/rbhma3100/setup.c,v retrieving revision 1.14 diff -u -p -r1.14 setup.c --- arch/mips/jmr3927/rbhma3100/setup.c 20 Aug 2004 11:29:06 -0000 1.14 +++ arch/mips/jmr3927/rbhma3100/setup.c 21 Nov 2004 16:14:03 -0000 @@ -184,10 +184,6 @@ unsigned long jmr3927_do_gettimeoffset(v } -#if defined(CONFIG_BLK_DEV_INITRD) -extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end; -#endif - //#undef DO_WRITE_THROUGH #define DO_WRITE_THROUGH #define DO_ENABLE_CACHE Index: arch/mips/kernel/setup.c =================================================================== RCS file: /home/cvs/linux/arch/mips/kernel/setup.c,v retrieving revision 1.171 diff -u -p -r1.171 setup.c --- arch/mips/kernel/setup.c 28 Jun 2004 21:04:12 -0000 1.171 +++ arch/mips/kernel/setup.c 21 Nov 2004 16:14:03 -0000 @@ -56,8 +56,6 @@ unsigned int PCI_DMA_BUS_IS_PHYS; EXPORT_SYMBOL(PCI_DMA_BUS_IS_PHYS); -extern void * __rd_start, * __rd_end; - /* * Setup information * @@ -194,6 +192,68 @@ static inline void parse_cmdline_early(v } } +static inline int parse_rd_cmdline(unsigned long* rd_start, unsigned long* rd_end) +{ + /* + * "rd_start=0xNNNNNNNN" defines the memory address of an initrd + * "rd_size=0xNN" it's size + */ + unsigned long start = 0; + unsigned long size = 0; + unsigned long end; + char cmd_line[CL_SIZE]; + char *start_str; + char *size_str; + char *tmp; + + strcpy(cmd_line, command_line); + *command_line = 0; + tmp = cmd_line; + /* Ignore "rd_start=" strings in other parameters. */ + start_str = strstr(cmd_line, "rd_start="); + if (start_str && start_str != cmd_line && *(start_str - 1) != ' ') + start_str = strstr(start_str, " rd_start="); + while (start_str) { + if (start_str != cmd_line) + strncat(command_line, tmp, start_str - tmp); + start = memparse(start_str + 9, &start_str); + tmp = start_str + 1; + start_str = strstr(start_str, " rd_start="); + } + if (*tmp) + strcat(command_line, tmp); + + strcpy(cmd_line, command_line); + *command_line = 0; + tmp = cmd_line; + /* Ignore "rd_size" strings in other parameters. */ + size_str = strstr(cmd_line, "rd_size="); + if (size_str && size_str != cmd_line && *(size_str - 1) != ' ') + size_str = strstr(size_str, " rd_size="); + while (size_str) { + if (size_str != cmd_line) + strncat(command_line, tmp, size_str - tmp); + size = memparse(size_str + 8, &size_str); + tmp = size_str + 1; + size_str = strstr(size_str, " rd_size="); + } + if (*tmp) + strcat(command_line, tmp); + +#ifdef CONFIG_MIPS64 + /* HACK: Guess if the sign extension was forgotten */ + if (start > 0x0000000080000000 && start < 0x00000000ffffffff) + start |= 0xffffffff00000000; +#endif + + end = start + size; + if (start && end) { + *rd_start = start; + *rd_end = end; + return 1; + } + return 0; +} #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) #define PFN_DOWN(x) ((x) >> PAGE_SHIFT) @@ -205,30 +265,42 @@ static inline void parse_cmdline_early(v static inline void bootmem_init(void) { unsigned long start_pfn; + unsigned long reserved_end = (unsigned long)&_end; #ifndef CONFIG_SGI_IP27 - unsigned long bootmap_size, max_low_pfn, first_usable_pfn; + unsigned long first_usable_pfn; + unsigned long bootmap_size; int i; #endif #ifdef CONFIG_BLK_DEV_INITRD - unsigned long tmp; - unsigned long *initrd_header; + int initrd_reserve_bootmem = 0; - tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8; - if (tmp < (unsigned long)&_end) - tmp += PAGE_SIZE; - initrd_header = (unsigned long *)tmp; - if (initrd_header[0] == 0x494E5244) { - initrd_start = (unsigned long)&initrd_header[2]; - initrd_end = initrd_start + initrd_header[1]; + /* Board specific code should have set up initrd_start and initrd_end */ + ROOT_DEV = Root_RAM0; + if (parse_rd_cmdline(&initrd_start, &initrd_end)) { + reserved_end = max(reserved_end, initrd_end); + initrd_reserve_bootmem = 1; + } else { + unsigned long tmp; + unsigned long *initrd_header; + + tmp = ((reserved_end + PAGE_SIZE-1) & PAGE_MASK) - 8; + if (tmp < reserved_end) + tmp += PAGE_SIZE; + initrd_header = (unsigned long *)tmp; + if (initrd_header[0] == 0x494E5244) { + initrd_start = (unsigned long)&initrd_header[2]; + initrd_end = initrd_start + initrd_header[1]; + reserved_end = max(reserved_end, initrd_end); + initrd_reserve_bootmem = 1; + } } - start_pfn = PFN_UP(CPHYSADDR((&_end)+(initrd_end - initrd_start) + PAGE_SIZE)); -#else +#endif /* CONFIG_BLK_DEV_INITRD */ + /* * Partially used pages are not usable - thus * we are rounding upwards. */ - start_pfn = PFN_UP(CPHYSADDR(&_end)); -#endif /* CONFIG_BLK_DEV_INITRD */ + start_pfn = PFN_UP(CPHYSADDR(reserved_end)); #ifndef CONFIG_SGI_IP27 /* Find the highest page frame number we have available. */ @@ -341,21 +413,14 @@ static inline void bootmem_init(void) /* Reserve the bootmap memory. */ reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size); -#endif +#endif /* CONFIG_SGI_IP27 */ #ifdef CONFIG_BLK_DEV_INITRD - /* Board specific code should have set up initrd_start and initrd_end */ - ROOT_DEV = Root_RAM0; - if (&__rd_start != &__rd_end) { - initrd_start = (unsigned long)&__rd_start; - initrd_end = (unsigned long)&__rd_end; - } initrd_below_start_ok = 1; if (initrd_start) { unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start); printk("Initial ramdisk at: 0x%p (%lu bytes)\n", - (void *)initrd_start, - initrd_size); + (void *)initrd_start, initrd_size); if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { printk("initrd extends beyond end of memory " @@ -363,7 +428,11 @@ static inline void bootmem_init(void) sizeof(long) * 2, CPHYSADDR(initrd_end), sizeof(long) * 2, PFN_PHYS(max_low_pfn)); initrd_start = initrd_end = 0; + initrd_reserve_bootmem = 0; } + + if (initrd_reserve_bootmem) + reserve_bootmem(CPHYSADDR(initrd_start), initrd_size); } #endif /* CONFIG_BLK_DEV_INITRD */ } Index: arch/mips/sibyte/cfe/setup.c =================================================================== RCS file: /home/cvs/linux/arch/mips/sibyte/cfe/setup.c,v retrieving revision 1.19 diff -u -p -r1.19 setup.c --- arch/mips/sibyte/cfe/setup.c 21 Nov 2004 13:50:35 -0000 1.19 +++ arch/mips/sibyte/cfe/setup.c 21 Nov 2004 16:14:04 -0000 @@ -56,7 +56,6 @@ int cfe_cons_handle; #ifdef CONFIG_BLK_DEV_INITRD extern unsigned long initrd_start, initrd_end; -extern void * __rd_start, * __rd_end; #endif #ifdef CONFIG_KGDB Index: arch/mips/sibyte/swarm/setup.c =================================================================== RCS file: /home/cvs/linux/arch/mips/sibyte/swarm/setup.c,v retrieving revision 1.32 diff -u -p -r1.32 setup.c --- arch/mips/sibyte/swarm/setup.c 14 Sep 2004 21:23:33 -0000 1.32 +++ arch/mips/sibyte/swarm/setup.c 21 Nov 2004 16:14:04 -0000 @@ -52,10 +52,6 @@ extern int m41t81_probe(void); extern int m41t81_set_time(unsigned long); extern unsigned long m41t81_get_time(void); -#ifdef CONFIG_BLK_DEV_INITRD -extern void * __rd_start, * __rd_end; -#endif - const char *get_system_type(void) { return "SiByte " SIBYTE_BOARD_NAME; From ica2_ts@csv.ica.uni-stuttgart.de Sun Nov 21 16:24:59 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 16:25:03 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:55822 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 16:24:59 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CVuWI-0002OO-00; Sun, 21 Nov 2004 17:24:58 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CVuWI-0006nE-00; Sun, 21 Nov 2004 17:24:58 +0100 Date: Sun, 21 Nov 2004 17:24:58 +0100 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Add comment about oversized r4000 interrupt vector Message-ID: <20041121162458.GP20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6383 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 783 Lines: 24 Hello All, to prevent it to get lost again, this adds an explanatory comment to the r4000 exception vector init. Thiemo Index: arch/mips/kernel/traps.c =================================================================== RCS file: /home/cvs/linux/arch/mips/kernel/traps.c,v retrieving revision 1.201 diff -u -p -r1.201 traps.c --- arch/mips/kernel/traps.c 11 Nov 2004 03:06:01 -0000 1.201 +++ arch/mips/kernel/traps.c 20 Nov 2004 16:46:40 -0000 @@ -1026,6 +1027,7 @@ void __init trap_init(void) set_except_vector(24, handle_mcheck); if (cpu_has_vce) + /* Special exception: R4[04]00 uses also the divec space. */ memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); else if (cpu_has_4kex) memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); From ica2_ts@csv.ica.uni-stuttgart.de Sun Nov 21 16:45:58 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 16:46:05 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:3087 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 16:45:58 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CVuqb-0002ZF-00; Sun, 21 Nov 2004 17:45:57 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CVuqb-0006oC-00; Sun, 21 Nov 2004 17:45:57 +0100 Date: Sun, 21 Nov 2004 17:45:57 +0100 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Improve o32 syscall handling Message-ID: <20041121164557.GQ20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6384 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 12197 Lines: 469 Hello All, this is a major cleanup for the o32 syscall handling. For the 32bit kernel, it - uses a more efficient syscall table layout, and reduces its size - handles stack arguments also more efficiently, and allows for up to 8 arguments. This gives an indirect fadvise64_64 syscall a chance to work. - Fixes several flaws in the indirect syscall path, like duplicated user stack handling, and incomplete argument handling. For the 64bit Kernel, it - checks for unaligned user stack - also allows now up to 8 arguments - removes unused stackhandling cruft from the indirect syscall path and does complete argument handling there. Thiemo Index: arch/mips/kernel/scall32-o32.S =================================================================== RCS file: /home/cvs/linux/arch/mips/kernel/scall32-o32.S,v retrieving revision 1.15 diff -u -p -r1.15 scall32-o32.S --- arch/mips/kernel/scall32-o32.S 15 Nov 2004 11:49:19 -0000 1.15 +++ arch/mips/kernel/scall32-o32.S 20 Nov 2004 16:46:39 -0000 @@ -5,6 +5,7 @@ * * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02 by Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2004 Thiemo Seufer */ #include #include @@ -32,26 +33,30 @@ NESTED(handle_sys, PT_SIZE, sp) lw t1, PT_EPC(sp) # skip syscall on return +#if defined(CONFIG_BINFMT_IRIX) sltiu t0, v0, MAX_SYSCALL_NO + 1 # check syscall number +#else + subu v0, v0, __NR_O32_Linux # check syscall number + sltiu t0, v0, __NR_O32_Linux_syscalls + 1 +#endif addiu t1, 4 # skip to next instruction sw t1, PT_EPC(sp) beqz t0, illegal_syscall - /* XXX Put both in one cacheline, should save a bit. */ - sll t0, v0, 2 - lw t2, sys_call_table(t0) # syscall routine - lbu t3, sys_narg_table(v0) # number of arguments - beqz t2, illegal_syscall; + sll t0, v0, 3 + la t1, sys_call_table + addu t1, t0 + lw t2, (t1) # syscall routine + lw t3, 4(t1) # >= 0 if we need stack arguments + beqz t2, illegal_syscall - subu t0, t3, 5 # 5 or more arguments? sw a3, PT_R26(sp) # save a3 for syscall restarting - bgez t0, stackargs + bgez t3, stackargs stack_done: - sw a3, PT_R26(sp) # save for syscall restart - LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? + lw t0, TI_FLAGS($28) # syscall tracing enabled? li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT - and t0, t1, t0 + and t0, t1 bnez t0, syscall_trace_entry # -> yes jalr t2 # Do The Real Thing (TM) @@ -70,9 +75,9 @@ o32_syscall_exit: local_irq_disable # make sure need_resched and # signals dont change between # sampling and return - LONG_L a2, TI_FLAGS($28) # current->work + lw a2, TI_FLAGS($28) # current->work li t0, _TIF_ALLWORK_MASK - and t0, a2, t0 + and t0, a2 bnez t0, o32_syscall_exit_work j restore_partial @@ -117,49 +122,50 @@ syscall_trace_entry: */ stackargs: lw t0, PT_R29(sp) # get old user stack pointer - subu t3, 4 - sll t1, t3, 2 # stack valid? - - addu t1, t0 # end address - or t0, t1 - bltz t0, bad_stack # -> sp is bad - - lw t0, PT_R29(sp) # get old user stack pointer - PTR_LA t1, 4f # copy 1 to 3 arguments - sll t3, t3, 4 - subu t1, t3 - jr t1 - /* Ok, copy the args from the luser stack to the kernel stack */ /* - * I know Ralf doesn't like nops but this avoids code - * duplication for R3000 targets (and this is the - * only place where ".set reorder" doesn't help). - * Harald. + * We intentionally keep the kernel stack a little below the top of + * userspace so we don't have to do a slower byte accurate check here. */ + andi t1, t0, 7 + lw t5, TI_ADDR_LIMIT($28) + bnez t1, bad_stack + addu t4, t0, 32 + and t5, t4 + bltz t5, bad_stack # -> sp is bad + + /* Ok, copy the args from the luser stack to the kernel stack. + * t3 is the precomputed number of instruction bytes needed to + * load or store arguments 6-8. + */ + + la t1, 5f # load up to 3 arguments + subu t1, t3 +1: lw t5, 16(t0) # argument #5 from usp .set push .set noreorder .set nomacro -1: lw t1, 24(t0) # argument #7 from usp - nop - sw t1, 24(sp) - nop -2: lw t1, 20(t0) # argument #5 from usp - nop - sw t1, 20(sp) - nop -3: lw t1, 16(t0) # argument #5 from usp - nop - sw t1, 16(sp) - nop -4: .set pop + jr t1 + addiu t1, 6f - 5f - j stack_done # go back +2: lw t8, 28(t0) # argument #8 from usp +3: lw t7, 24(t0) # argument #7 from usp +4: lw t6, 20(t0) # argument #6 from usp +5: jr t1 + sw t5, 16(sp) # argument #5 to ksp + + sw t8, 28(sp) # argument #8 to ksp + sw t7, 24(sp) # argument #7 to ksp + sw t6, 20(sp) # argument #6 to ksp +6: j stack_done # go back + nop + .set pop .section __ex_table,"a" PTR 1b,bad_stack PTR 2b,bad_stack PTR 3b,bad_stack + PTR 4b,bad_stack .previous /* @@ -239,12 +245,12 @@ illegal_syscall: sw v0, PT_R2(sp) # result /* Success, so skip usual error handling garbage. */ - LONG_L a2, TI_FLAGS($28) # syscall tracing enabled? + lw a2, TI_FLAGS($28) # syscall tracing enabled? li t0, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT and t0, a2, t0 bnez t0, 1f - b o32_syscall_exit + j o32_syscall_exit 1: SAVE_STATIC move a0, sp @@ -270,67 +276,47 @@ bad_alignment: END(sys_sysmips) LEAF(sys_syscall) - lw t0, PT_R29(sp) # user sp - - sltu v0, a0, __NR_O32_Linux + __NR_O32_Linux_syscalls + 1 +#if defined(CONFIG_BINFMT_IRIX) + sltiu v0, a0, MAX_SYSCALL_NO + 1 # check syscall number +#else + subu v0, a0, __NR_O32_Linux # check syscall number + sltiu v0, v0, __NR_O32_Linux_syscalls + 1 +#endif beqz v0, enosys - sll v0, a0, 2 - la v1, sys_syscall - lw t2, sys_call_table(v0) # function pointer - lbu t4, sys_narg_table(a0) # number of arguments - - li v0, -EINVAL - beq t2, v1, out # do not recurse + sll t0, v0, 3 + lw t2, sys_call_table(t0) # syscall routine + li v1, 4000 # nr of sys_syscall beqz t2, enosys # null function pointer? - andi v0, t0, 0x3 # unaligned stack pointer? - bnez v0, sigsegv + li v0, -EINVAL + beq a0, v1, out # do not recurse - addu v0, t0, 16 # v0 = usp + 16 - addu t1, v0, 12 # 3 32-bit arguments - lw v1, TI_ADDR_LIMIT($28) - or v0, v0, t1 - and v1, v1, v0 - bltz v1, efault + /* Some syscalls like execve get their arguments from struct pt_regs + and claim zero arguments in the syscall table. Thus we have to + assume the worst case and shuffle around all potential arguments. + If you want performance, don't use indirect syscalls. */ move a0, a1 # shift argument registers move a1, a2 move a2, a3 - -1: lw a3, 16(t0) -2: lw t3, 20(t0) -3: lw t4, 24(t0) - - .section __ex_table, "a" - .word 1b, efault - .word 2b, efault - .word 3b, efault - .previous - - sw t3, 16(sp) # put into new stackframe - sw t4, 20(sp) - - bnez t4, 1f # zero arguments? - addu a0, sp, 32 # then pass sp in a0 -1: - - sw t3, 16(sp) - sw v1, 20(sp) + lw a3, 16(sp) + lw t4, 20(sp) + lw t5, 24(sp) + lw t6, 28(sp) + sw t4, 16(sp) + sw t5, 20(sp) + sw t6, 24(sp) + sw a0, PT_R4(sp) # .. and push back a0 - a3, some + sw a1, PT_R5(sp) # syscalls expect them there + sw a2, PT_R6(sp) + sw a3, PT_R7(sp) + sw a3, PT_R26(sp) # update a3 for syscall restarting jr t2 /* Unreached */ enosys: li v0, -ENOSYS - b out - -sigsegv: - li a0, _SIGSEGV - move a1, $28 - jal force_sig - /* Fall through */ - -efault: li v0, -EFAULT out: jr ra END(sys_syscall) @@ -350,12 +336,14 @@ out: jr ra .endm .macro syscalltable +#if defined(CONFIG_BINFMT_IRIX) mille sys_ni_syscall 0 /* 0 - 999 SVR4 flavour */ - #include "irix5sys.h" /* 1000 - 1999 32-bit IRIX */ +# include "irix5sys.h" /* 1000 - 1999 32-bit IRIX */ mille sys_ni_syscall 0 /* 2000 - 2999 BSD43 flavour */ mille sys_ni_syscall 0 /* 3000 - 3999 POSIX flavour */ +#endif - sys sys_syscall 0 /* 4000 */ + sys sys_syscall 8 /* 4000 */ sys sys_exit 1 sys sys_fork 0 sys sys_read 3 @@ -641,19 +629,16 @@ out: jr ra .endm + /* We pre-compute the number of _instruction_ bytes needed to + load or store the arguments 6-8. Negative values are ignored. */ + .macro sys function, nargs PTR \function + LONG (\nargs << 2) - (5 << 2) .endm .align 3 + .type sys_call_table,@object sys_call_table: syscalltable .size sys_call_table, . - sys_call_table - - .macro sys function, nargs - .byte \nargs - .endm - -sys_narg_table: - syscalltable - .size sys_narg_table, . - sys_narg_table Index: arch/mips/kernel/scall64-o32.S =================================================================== RCS file: /home/cvs/linux/arch/mips/kernel/scall64-o32.S,v retrieving revision 1.22 diff -u -p -r1.22 scall64-o32.S --- arch/mips/kernel/scall64-o32.S 15 Nov 2004 11:49:19 -0000 1.22 +++ arch/mips/kernel/scall64-o32.S 20 Nov 2004 16:46:39 -0000 @@ -6,6 +6,7 @@ * Copyright (C) 1995 - 2000, 2001 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2004 Thiemo Seufer * * Hairy, the userspace application uses a different argument passing * convention than the kernel, so we have to translate things from o32 @@ -43,6 +44,8 @@ NESTED(handle_sys, PT_SIZE, sp) RESTORE_ALL #endif + /* We don't want to stumble over broken sign extensions from + userland. O32 does never use the upper half. */ sll a0, a0, 0 sll a1, a1, 0 sll a2, a2, 0 @@ -62,17 +65,21 @@ NESTED(handle_sys, PT_SIZE, sp) * userspace so we don't have to do a slower byte accurate check here. */ ld t0, PT_R29(sp) # get old user stack pointer + andi t3, t0, 7 + bnez t3, bad_stack daddu t1, t0, 32 bltz t1, bad_stack 1: lw a4, 16(t0) # argument #5 from usp 2: lw a5, 20(t0) # argument #6 from usp 3: lw a6, 24(t0) # argument #7 from usp +4: lw a7, 28(t0) # argument #8 from usp (for indirect syscalls) .section __ex_table,"a" PTR 1b, bad_stack PTR 2b, bad_stack PTR 3b, bad_stack + PTR 4b, bad_stack .previous li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT @@ -91,7 +98,7 @@ NESTED(handle_sys, PT_SIZE, sp) sd v0, PT_R0(sp) # flag for syscall restarting 1: sd v0, PT_R2(sp) # result -FEXPORT(o32_syscall_exit) +o32_syscall_exit: local_irq_disable # make need_resched and # signals dont change between # sampling and return @@ -109,12 +116,11 @@ o32_syscall_exit_work: trace_a_syscall: SAVE_STATIC - sd a4, PT_R8(sp) + sd t2, PT_R1(sp) + sd a4, PT_R8(sp) # Save argument registers sd a5, PT_R9(sp) sd a6, PT_R10(sp) - sd a7, PT_R11(sp) - - sd t2,PT_R1(sp) + sd a7, PT_R11(sp) # For indirect syscalls move a0, sp li a1, 0 jal do_syscall_trace @@ -126,7 +132,8 @@ trace_a_syscall: ld a3, PT_R7(sp) ld a4, PT_R8(sp) ld a5, PT_R9(sp) - ld a6, PT_R10(sp) # For indirect syscalls + ld a6, PT_R10(sp) + ld a7, PT_R11(sp) # For indirect syscalls jalr t2 li t0, -EMAXERRNO - 1 # error? @@ -174,55 +181,40 @@ illegal_syscall: END(handle_sys) LEAF(sys32_syscall) - ld t0, PT_R29(sp) # user sp - sltu v0, a0, __NR_O32_Linux + __NR_O32_Linux_syscalls + 1 beqz v0, enosys dsll v0, a0, 3 - dla v1, sys32_syscall ld t2, (sys_call_table - (__NR_O32_Linux * 8))(v0) + li v1, 4000 # indirect syscall number li v0, -EINVAL - beq t2, v1, out # do not recurse + beq a0, v1, out # do not recurse beqz t2, enosys # null function pointer? - andi v0, t0, 0x3 # unaligned stack pointer? - bnez v0, sigsegv - - daddiu v0, t0, 16 # v0 = usp + 16 - daddu t1, v0, 12 # 3 32-bit arguments - ld v1, TI_ADDR_LIMIT($28) - or v0, v0, t1 - and v1, v1, v0 - bnez v1, efault - move a0, a1 # shift argument registers move a1, a2 move a2, a3 move a3, a4 move a4, a5 move a5, a6 + move a6, a7 + sd a0, PT_R4(sp) # ... and push back a0 - a3, some + sd a1, PT_R5(sp) # syscalls expect them there + sd a2, PT_R6(sp) + sd a3, PT_R7(sp) + sd a3, PT_R26(sp) # update a3 for syscall restarting jr t2 /* Unreached */ enosys: li v0, -ENOSYS - b out - -sigsegv: - li a0, _SIGSEGV - move a1, $28 - jal force_sig - /* Fall through */ - -efault: li v0, -EFAULT out: jr ra END(sys32_syscall) .align 3 - .type sys_call_table,@object; + .type sys_call_table,@object sys_call_table: PTR sys32_syscall /* 4000 */ PTR sys_exit From ica2_ts@csv.ica.uni-stuttgart.de Sun Nov 21 17:02:43 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 17:02:53 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:22287 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 17:02:43 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CVv6o-0002gc-00; Sun, 21 Nov 2004 18:02:42 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CVv6o-0006wf-00; Sun, 21 Nov 2004 18:02:42 +0100 Date: Sun, 21 Nov 2004 18:02:42 +0100 To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Synthesize TLB refill handler at runtime Message-ID: <20041121170242.GR20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6385 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 49495 Lines: 1860 Hello All, currently we have a large number of TLB refill handlers written in hand-optimized assembly which are mostly indentical. The appended patch removes them all, and adds a micro-assembler instead which synthesizes the proper variant for the CPU at runtime. Tested for - ip22 32bit - ip22 64bit - ip27 SMP 64bit - ip32 64bit with excellent results. The synthesized handler is in most cases shorter and more performant than the hand-written version. Please test on your machine as well. Thiemo Index: arch/mips/mm/Makefile =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/Makefile,v retrieving revision 1.68 diff -u -p -r1.68 Makefile --- arch/mips/mm/Makefile 20 Jun 2004 23:52:17 -0000 1.68 +++ arch/mips/mm/Makefile 20 Nov 2004 16:46:40 -0000 @@ -2,7 +2,8 @@ # Makefile for the Linux/MIPS-specific parts of the memory manager. # -obj-y += cache.o extable.o fault.o init.o pgtable.o +obj-y += cache.o extable.o fault.o init.o pgtable.o \ + tlbex.o obj-$(CONFIG_MIPS32) += ioremap.o pgtable-32.o obj-$(CONFIG_MIPS64) += pgtable-64.o @@ -47,16 +48,16 @@ obj-$(CONFIG_CPU_SB1) += tlbex32-r4k.o obj-$(CONFIG_CPU_TX39XX) += tlbex32-r3k.o endif ifdef CONFIG_MIPS64 -obj-$(CONFIG_CPU_R4300) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_R4X00) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_R5000) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_NEVADA) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_R5432) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_RM7000) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_RM9000) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_R10000) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_SB1) += tlb64-glue-sb1.o tlbex64-r4k.o -obj-$(CONFIG_CPU_MIPS64) += tlb64-glue-r4k.o tlbex64-r4k.o +obj-$(CONFIG_CPU_R4300) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_R4X00) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_R5000) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_NEVADA) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_R5432) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_RM7000) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_RM9000) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_R10000) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_SB1) += tlb64-glue-sb1.o +obj-$(CONFIG_CPU_MIPS64) += tlb64-glue-r4k.o endif Index: arch/mips/mm/tlb-andes.c =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlb-andes.c,v retrieving revision 1.8 diff -u -p -r1.8 tlb-andes.c --- arch/mips/mm/tlb-andes.c 19 Oct 2004 02:21:16 -0000 1.8 +++ arch/mips/mm/tlb-andes.c 20 Nov 2004 16:46:46 -0000 @@ -17,10 +17,7 @@ #include #include -extern void except_vec0_generic(void); -extern void except_vec0_r4000(void); -extern void except_vec1_generic(void); -extern void except_vec1_r4k(void); +extern void build_tlb_refill_handler(void); #define NTLB_ENTRIES 64 #define NTLB_ENTRIES_HALF 32 @@ -257,14 +254,5 @@ void __init tlb_init(void) /* Did I tell you that ARC SUCKS? */ -#ifdef CONFIG_MIPS32 - memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); - memcpy((void *)(KSEG0 + 0x080), &except_vec1_generic, 0x80); - flush_icache_range(KSEG0, KSEG0 + 0x100); -#endif -#ifdef CONFIG_MIPS64 - memcpy((void *)(CKSEG0 + 0x000), &except_vec0_generic, 0x80); - memcpy((void *)(CKSEG0 + 0x080), except_vec1_r4k, 0x80); - flush_icache_range(CKSEG0 + 0x80, CKSEG0 + 0x100); -#endif + build_tlb_refill_handler(); } Index: arch/mips/mm/tlb-r3k.c =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlb-r3k.c,v retrieving revision 1.26 diff -u -p -r1.26 tlb-r3k.c --- arch/mips/mm/tlb-r3k.c 11 Dec 2003 16:27:01 -0000 1.26 +++ arch/mips/mm/tlb-r3k.c 20 Nov 2004 16:46:46 -0000 @@ -26,7 +26,7 @@ #undef DEBUG_TLB -extern char except_vec0_r2300; +extern void build_tlb_refill_handler(void); /* CP0 hazard avoidance. */ #define BARRIER \ @@ -284,6 +284,6 @@ void __init add_wired_entry(unsigned lon void __init tlb_init(void) { local_flush_tlb_all(); - memcpy((void *)KSEG0, &except_vec0_r2300, 0x80); - flush_icache_range(KSEG0, KSEG0 + 0x80); + + build_tlb_refill_handler(); } Index: arch/mips/mm/tlb-r4k.c =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlb-r4k.c,v retrieving revision 1.38 diff -u -p -r1.38 tlb-r4k.c --- arch/mips/mm/tlb-r4k.c 19 Mar 2004 04:07:59 -0000 1.38 +++ arch/mips/mm/tlb-r4k.c 20 Nov 2004 16:46:46 -0000 @@ -19,12 +19,7 @@ #include #include -extern void except_vec0_generic(void); -extern void except_vec0_nevada(void); -extern void except_vec0_r4000(void); -extern void except_vec0_r4600(void); -extern void except_vec1_generic(void); -extern void except_vec1_r4k(void); +extern void build_tlb_refill_handler(void); /* CP0 hazard avoidance. */ #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ @@ -414,19 +409,5 @@ void __init tlb_init(void) temp_tlb_entry = current_cpu_data.tlbsize - 1; local_flush_tlb_all(); -#ifdef CONFIG_MIPS32 - if (current_cpu_data.cputype == CPU_NEVADA) - memcpy((void *)KSEG0, &except_vec0_nevada, 0x80); - else if (current_cpu_data.cputype == CPU_R4600) - memcpy((void *)KSEG0, &except_vec0_r4600, 0x80); - else - memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); - memcpy((void *)(KSEG0 + 0x080), &except_vec1_generic, 0x80); - flush_icache_range(KSEG0, KSEG0 + 0x100); -#endif -#ifdef CONFIG_MIPS64 - memcpy((void *)(CKSEG0 + 0x00), &except_vec0_generic, 0x80); - memcpy((void *)(CKSEG0 + 0x80), except_vec1_r4k, 0x80); - flush_icache_range(CKSEG0 + 0x80, CKSEG0 + 0x100); -#endif + build_tlb_refill_handler(); } Index: arch/mips/mm/tlb-r8k.c =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlb-r8k.c,v retrieving revision 1.1 diff -u -p -r1.1 tlb-r8k.c --- arch/mips/mm/tlb-r8k.c 20 Jun 2004 23:01:07 -0000 1.1 +++ arch/mips/mm/tlb-r8k.c 20 Nov 2004 16:46:46 -0000 @@ -19,8 +19,7 @@ #include #include -extern void except_vec0_generic(void); -extern void except_vec1_r8k(void); +extern void build_tlb_refill_handler(void); #define TFP_TLB_SIZE 384 #define TFP_TLB_SET_SHIFT 7 @@ -247,7 +246,5 @@ void __init tlb_init(void) local_flush_tlb_all(); - memcpy((void *)(CKSEG0 + 0x00), &except_vec0_generic, 0x80); - memcpy((void *)(CKSEG0 + 0x80), except_vec1_r8k, 0x80); - flush_icache_range(CKSEG0 + 0x80, CKSEG0 + 0x100); + build_tlb_refill_handler(); } Index: arch/mips/mm/tlb-sb1.c =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlb-sb1.c,v retrieving revision 1.45 diff -u -p -r1.45 tlb-sb1.c --- arch/mips/mm/tlb-sb1.c 23 Oct 2004 01:18:17 -0000 1.45 +++ arch/mips/mm/tlb-sb1.c 20 Nov 2004 16:46:46 -0000 @@ -23,14 +23,7 @@ #include #include -#ifdef CONFIG_MIPS32 -extern void except_vec0_sb1(void); -extern void except_vec1_generic(void); -#endif -#ifdef CONFIG_MIPS64 -extern void except_vec0_generic(void); -extern void except_vec1_sb1(void); -#endif +extern void build_tlb_refill_handler(void); #define UNIQUE_ENTRYHI(idx) (KSEG0 + ((idx) << (PAGE_SHIFT + 1))) @@ -380,14 +373,5 @@ void tlb_init(void) */ sb1_sanitize_tlb(); -#ifdef CONFIG_MIPS32 - memcpy((void *)KSEG0, &except_vec0_sb1, 0x80); - memcpy((void *)(KSEG0 + 0x080), &except_vec1_generic, 0x80); - flush_icache_range(KSEG0, KSEG0 + 0x100); -#endif -#ifdef CONFIG_MIPS64 - memcpy((void *)CKSEG0, &except_vec0_generic, 0x80); - memcpy((void *)(CKSEG0 + 0x80), &except_vec1_sb1, 0x80); - flush_icache_range(CKSEG0, CKSEG0 + 0x100); -#endif + build_tlb_refill_handler(); } Index: arch/mips/mm/tlbex32-r3k.S =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlbex32-r3k.S,v retrieving revision 1.1 diff -u -p -r1.1 tlbex32-r3k.S --- arch/mips/mm/tlbex32-r3k.S 20 Jun 2004 23:52:17 -0000 1.1 +++ arch/mips/mm/tlbex32-r3k.S 20 Nov 2004 16:46:46 -0000 @@ -24,36 +24,6 @@ #define TLB_OPTIMIZE /* If you are paranoid, disable this. */ - .text - .set mips1 - .set noreorder - - __INIT - - /* TLB refill, R[23]00 version */ - LEAF(except_vec0_r2300) - .set noat - .set mips1 - mfc0 k0, CP0_BADVADDR - lw k1, pgd_current # get pgd pointer - srl k0, k0, 22 - sll k0, k0, 2 - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) - and k0, k0, 0xffc - addu k1, k1, k0 - lw k0, (k1) - nop - mtc0 k0, CP0_ENTRYLO0 - mfc0 k1, CP0_EPC - tlbwr - jr k1 - rfe - END(except_vec0_r2300) - - __FINIT - /* ABUSE of CPP macros 101. */ /* After this macro runs, the pte faulted on is Index: arch/mips/mm/tlbex32-r4k.S =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlbex32-r4k.S,v retrieving revision 1.2 diff -u -p -r1.2 tlbex32-r4k.S --- arch/mips/mm/tlbex32-r4k.S 3 Oct 2004 01:16:24 -0000 1.2 +++ arch/mips/mm/tlbex32-r4k.S 20 Nov 2004 16:46:46 -0000 @@ -139,272 +139,6 @@ _PAGE_VALID | _PAGE_DIRTY); \ PTE_S pte, (ptr); - __INIT - -#ifdef CONFIG_64BIT_PHYS_ADDR -#define GET_PTE_OFF(reg) -#elif CONFIG_CPU_VR41XX -#define GET_PTE_OFF(reg) srl reg, reg, 3 -#else -#define GET_PTE_OFF(reg) srl reg, reg, 1 -#endif - -/* - * These handlers much be written in a relocatable manner - * because based upon the cpu type an arbitrary one of the - * following pieces of code will be copied to the KSEG0 - * vector location. - */ - /* TLB refill, EXL == 0, R4xx0, non-R4600 version */ - .set noreorder - .set noat - LEAF(except_vec0_r4000) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR # Get faulting address - srl k0, k0, _PGDIR_SHIFT # get pgd only bits - - sll k0, k0, 2 - addu k1, k1, k0 # add in pgd offset - mfc0 k0, CP0_CONTEXT # get context reg - lw k1, (k1) - GET_PTE_OFF(k0) # get pte offset - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 # add in offset - PTE_L k0, 0(k1) # get even pte - PTE_L k1, PTE_SIZE(k1) # get odd pte - PTE_SRL k0, k0, 6 # convert to entrylo0 - P_MTC0 k0, CP0_ENTRYLO0 # load it - PTE_SRL k1, k1, 6 # convert to entrylo1 - P_MTC0 k1, CP0_ENTRYLO1 # load it - mtc0_tlbw_hazard - tlbwr # write random tlb entry - nop - tlbw_eret_hazard - eret # return from trap - END(except_vec0_r4000) - - /* TLB refill, EXL == 0, R4600 version */ - LEAF(except_vec0_r4600) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR - srl k0, k0, _PGDIR_SHIFT - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) - GET_PTE_OFF(k0) # get pte offset - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 - PTE_L k0, 0(k1) - PTE_L k1, PTE_SIZE(k1) - PTE_SRL k0, k0, 6 - P_MTC0 k0, CP0_ENTRYLO0 - PTE_SRL k1, k1, 6 - P_MTC0 k1, CP0_ENTRYLO1 - nop - tlbwr - nop - eret - END(except_vec0_r4600) - - /* TLB refill, EXL == 0, R52x0 "Nevada" version */ - /* - * This version has a bug workaround for the Nevada. It seems - * as if under certain circumstances the move from cp0_context - * might produce a bogus result when the mfc0 instruction and - * it's consumer are in a different cacheline or a load instruction, - * probably any memory reference, is between them. This is - * potencially slower than the R4000 version, so we use this - * special version. - */ - .set noreorder - .set noat - LEAF(except_vec0_nevada) - .set mips3 - mfc0 k0, CP0_BADVADDR # Get faulting address - srl k0, k0, _PGDIR_SHIFT # get pgd only bits - lw k1, pgd_current # get pgd pointer - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 # add in pgd offset - lw k1, (k1) - mfc0 k0, CP0_CONTEXT # get context reg - GET_PTE_OFF(k0) # get pte offset - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 # add in offset - PTE_L k0, 0(k1) # get even pte - PTE_L k1, PTE_SIZE(k1) # get odd pte - PTE_SRL k0, k0, 6 # convert to entrylo0 - P_MTC0 k0, CP0_ENTRYLO0 # load it - PTE_SRL k1, k1, 6 # convert to entrylo1 - P_MTC0 k1, CP0_ENTRYLO1 # load it - nop # QED specified nops - nop - tlbwr # write random tlb entry - nop # traditional nop - eret # return from trap - END(except_vec0_nevada) - - /* TLB refill, EXL == 0, SB1 with M3 errata handling version */ - LEAF(except_vec0_sb1) -#if BCM1250_M3_WAR - mfc0 k0, CP0_BADVADDR - mfc0 k1, CP0_ENTRYHI - xor k0, k1 - srl k0, k0, PAGE_SHIFT+1 - bnez k0, 1f -#endif - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR # Get faulting address - srl k0, k0, _PGDIR_SHIFT # get pgd only bits - sll k0, k0, 2 - addu k1, k1, k0 # add in pgd offset - mfc0 k0, CP0_CONTEXT # get context reg - lw k1, (k1) - GET_PTE_OFF(k0) # get pte offset - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 # add in offset - PTE_L k0, 0(k1) # get even pte - PTE_L k1, PTE_SIZE(k1) # get odd pte - PTE_SRL k0, k0, 6 # convert to entrylo0 - P_MTC0 k0, CP0_ENTRYLO0 # load it - PTE_SRL k1, k1, 6 # convert to entrylo1 - P_MTC0 k1, CP0_ENTRYLO1 # load it - tlbwr # write random tlb entry -1: eret # return from trap - END(except_vec0_sb1) - - /* TLB refill, EXL == 0, R4[40]00/R5000 badvaddr hwbug version */ - LEAF(except_vec0_r45k_bvahwbug) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR - srl k0, k0, _PGDIR_SHIFT - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) -#ifndef CONFIG_64BIT_PHYS_ADDR - srl k0, k0, 1 -#endif - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 - PTE_L k0, 0(k1) - PTE_L k1, PTE_SIZE(k1) - nop /* XXX */ - tlbp - PTE_SRL k0, k0, 6 - P_MTC0 k0, CP0_ENTRYLO0 - PTE_SRL k1, k1, 6 - mfc0 k0, CP0_INDEX - P_MTC0 k1, CP0_ENTRYLO1 - bltzl k0, 1f - tlbwr -1: - nop - eret - END(except_vec0_r45k_bvahwbug) - -#ifdef CONFIG_SMP - /* TLB refill, EXL == 0, R4000 MP badvaddr hwbug version */ - LEAF(except_vec0_r4k_mphwbug) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR - srl k0, k0, _PGDIR_SHIFT - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) -#ifndef CONFIG_64BIT_PHYS_ADDR - srl k0, k0, 1 -#endif - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 - PTE_L k0, 0(k1) - PTE_L k1, PTE_SIZE(k1) - nop /* XXX */ - tlbp - PTE_SRL k0, k0, 6 - P_MTC0 k0, CP0_ENTRYLO0 - PTE_SRL k1, k1, 6 - mfc0 k0, CP0_INDEX - P_MTC0 k1, CP0_ENTRYLO1 - bltzl k0, 1f - tlbwr -1: - nop - eret - END(except_vec0_r4k_mphwbug) -#endif - - /* TLB refill, EXL == 0, R4000 UP 250MHZ entrylo[01] hwbug version */ - LEAF(except_vec0_r4k_250MHZhwbug) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR - srl k0, k0, _PGDIR_SHIFT - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) -#ifndef CONFIG_64BIT_PHYS_ADDR - srl k0, k0, 1 -#endif - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 - PTE_L k0, 0(k1) - PTE_L k1, PTE_SIZE(k1) - PTE_SRL k0, k0, 6 - P_MTC0 zero, CP0_ENTRYLO0 - P_MTC0 k0, CP0_ENTRYLO0 - PTE_SRL k1, k1, 6 - P_MTC0 zero, CP0_ENTRYLO1 - P_MTC0 k1, CP0_ENTRYLO1 - b 1f - tlbwr -1: - nop - eret - END(except_vec0_r4k_250MHZhwbug) - -#ifdef CONFIG_SMP - /* TLB refill, EXL == 0, R4000 MP 250MHZ entrylo[01]+badvaddr bug version */ - LEAF(except_vec0_r4k_MP250MHZhwbug) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR - srl k0, k0, _PGDIR_SHIFT - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) -#ifndef CONFIG_64BIT_PHYS_ADDR - srl k0, k0, 1 -#endif - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 - PTE_L k0, 0(k1) - PTE_L k1, PTE_SIZE(k1) - nop /* XXX */ - tlbp - PTE_SRL k0, k0, 6 - P_MTC0 zero, CP0_ENTRYLO0 - P_MTC0 k0, CP0_ENTRYLO0 - mfc0 k0, CP0_INDEX - PTE_SRL k1, k1, 6 - P_MTC0 zero, CP0_ENTRYLO1 - P_MTC0 k1, CP0_ENTRYLO1 - bltzl k0, 1f - tlbwr -1: - nop - eret - END(except_vec0_r4k_MP250MHZhwbug) -#endif - - __FINIT .set noreorder --- /dev/null 2004-08-24 19:23:08.000000000 +0200 +++ arch/mips/mm/tlbex.c 2004-11-20 17:41:35.000000000 +0100 @@ -0,0 +1,1162 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Systhesize TLB refill handlers at runtime. + * + * Copyright (C) 2004 by Thiemo Seufer + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* #define DEBUG_TLB */ + +static __init int r45k_bvahwbug(void) +{ + /* XXX: We should probe for the presence of this bug, but we don't. */ + return 0; +} + +static __init int r4k_250MHZhwbug(void) +{ + /* XXX: We should probe for the presence of this bug, but we don't. */ + return 0; +} + +static __init int bcm1250_m3_war(void) +{ + return BCM1250_M3_WAR; +} + +/* + * A little micro-assembler, intended for TLB refill handler + * synthesizing. It is intentionally kept simple, does only support + * a subset of instructions, and does not try to hide pipeline effects + * like branch delay slots. + */ + +enum fields +{ + RS = 0x001, + RT = 0x002, + RD = 0x004, + RE = 0x008, + SIMM = 0x010, + UIMM = 0x020, + BIMM = 0x040, + JIMM = 0x080, + FUNC = 0x100, +}; + +#define OP_MASK 0x2f +#define OP_SH 26 +#define RS_MASK 0x1f +#define RS_SH 21 +#define RT_MASK 0x1f +#define RT_SH 16 +#define RD_MASK 0x1f +#define RD_SH 11 +#define RE_MASK 0x1f +#define RE_SH 6 +#define IMM_MASK 0xffff +#define IMM_SH 0 +#define JIMM_MASK 0x3ffffff +#define JIMM_SH 0 +#define FUNC_MASK 0x2f +#define FUNC_SH 0 + +enum opcode { + insn_invalid, + insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, + insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, insn_bne, + insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, + insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, + insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, + insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_ori, insn_rfe, + insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, + insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori +}; + +struct insn { + enum opcode opcode; + u32 match; + enum fields fields; +}; + +/* This macro sets the non-variable bits of an instruction. */ +#define M(a, b, c, d, e, f) \ + ((a) << OP_SH \ + | (b) << RS_SH \ + | (c) << RT_SH \ + | (d) << RD_SH \ + | (e) << RE_SH \ + | (f) << FUNC_SH) + +static __initdata struct insn insn_table[] = { + { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, + { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, + { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, + { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, + { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, + { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, + { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, + { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, + { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, + { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, + { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD }, + { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD }, + { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, + { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, + { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, + { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, + { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE }, + { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, + { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, + { insn_j, M(j_op,0,0,0,0,0), JIMM }, + { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, + { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, + { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, + { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD }, + { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD }, + { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, + { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, + { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, + { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, + { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, + { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, + { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, + { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, + { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, + { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, + { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, + { insn_invalid, 0, 0 } +}; + +#undef M + +static __init u32 build_rs(u32 arg) +{ + if (arg & ~RS_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return (arg & RS_MASK) << RS_SH; +} + +static __init u32 build_rt(u32 arg) +{ + if (arg & ~RT_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return (arg & RT_MASK) << RT_SH; +} + +static __init u32 build_rd(u32 arg) +{ + if (arg & ~RD_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return (arg & RD_MASK) << RD_SH; +} + +static __init u32 build_re(u32 arg) +{ + if (arg & ~RE_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return (arg & RE_MASK) << RE_SH; +} + +static __init u32 build_simm(s32 arg) +{ + if (arg > 0x7fff || arg < -0x8000) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return arg & 0xffff; +} + +static __init u32 build_uimm(u32 arg) +{ + if (arg & ~IMM_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return arg & IMM_MASK; +} + +static __init u32 build_bimm(s32 arg) +{ + if (arg > 0x1ffff || arg < -0x20000) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + if (arg & 0x3) + printk(KERN_WARNING "Invalid TLB synthesizer branch target\n"); + + return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); +} + +static __init u32 build_jimm(u32 arg) +{ + if (arg & ~((JIMM_MASK) << 2)) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return (arg >> 2) & JIMM_MASK; +} + +static __init u32 build_func(u32 arg) +{ + if (arg & ~FUNC_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return arg & FUNC_MASK; +} + +/* + * The order of opcode arguments is implicitly left to right, + * starting with RS and ending with FUNC or IMM. + */ +static void __init build_insn(u32 **buf, enum opcode opc, ...) +{ + struct insn *ip = NULL; + unsigned int i; + va_list ap; + u32 op; + + for (i = 0; insn_table[i].opcode != insn_invalid; i++) + if (insn_table[i].opcode == opc) { + ip = &insn_table[i]; + break; + } + + if (!ip) + panic("Unsupported TLB synthesizer instruction %d", opc); + + op = ip->match; + va_start(ap, opc); + if (ip->fields & RS) op |= build_rs(va_arg(ap, u32)); + if (ip->fields & RT) op |= build_rt(va_arg(ap, u32)); + if (ip->fields & RD) op |= build_rd(va_arg(ap, u32)); + if (ip->fields & RE) op |= build_re(va_arg(ap, u32)); + if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32)); + if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32)); + if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32)); + if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32)); + if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32)); + va_end(ap); + + **buf = op; + (*buf)++; +} + +#define I_u1u2u3(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b, unsigned int c) \ + { \ + build_insn(buf, insn##op, a, b, c); \ + } + +#define I_u2u1u3(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b, unsigned int c) \ + { \ + build_insn(buf, insn##op, b, a, c); \ + } + +#define I_u3u1u2(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b, unsigned int c) \ + { \ + build_insn(buf, insn##op, b, c, a); \ + } + +#define I_u1u2s3(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b, signed int c) \ + { \ + build_insn(buf, insn##op, a, b, c); \ + } + +#define I_u2s3u1(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + signed int b, unsigned int c) \ + { \ + build_insn(buf, insn##op, c, a, b); \ + } + +#define I_u2u1s3(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b, signed int c) \ + { \ + build_insn(buf, insn##op, b, a, c); \ + } + +#define I_u1u2(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b) \ + { \ + build_insn(buf, insn##op, a, b); \ + } + +#define I_u1s2(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + signed int b) \ + { \ + build_insn(buf, insn##op, a, b); \ + } + +#define I_u1(op) \ + static inline void i##op(u32 **buf, unsigned int a) \ + { \ + build_insn(buf, insn##op, a); \ + } + +#define I_0(op) \ + static inline void i##op(u32 **buf) \ + { \ + build_insn(buf, insn##op); \ + } + +I_u2u1s3(_addiu); +I_u3u1u2(_addu); +I_u2u1u3(_andi); +I_u3u1u2(_and); +I_u1u2s3(_beq); +I_u1s2(_bgez); +I_u1s2(_bgezl); +I_u1s2(_bltz); +I_u1s2(_bltzl); +I_u1u2s3(_bne); +I_u1u2(_dmfc0); +I_u1u2(_dmtc0); +I_u2u1s3(_daddiu); +I_u3u1u2(_daddu); +I_u2u1u3(_dsll); +I_u2u1u3(_dsll32); +I_u2u1u3(_dsra); +I_u2u1u3(_dsrl); +I_u2u1u3(_dsrl32); +I_u3u1u2(_dsubu); +I_0(_eret); +I_u1(_j); +I_u1(_jal); +I_u1(_jr); +I_u2s3u1(_ld); +I_u1s2(_lui); +I_u2s3u1(_lw); +I_u1u2(_mfc0); +I_u1u2(_mtc0); +I_u2u1u3(_ori); +I_0(_rfe); +I_u2s3u1(_sd); +I_u2u1u3(_sll); +I_u2u1u3(_sra); +I_u2u1u3(_srl); +I_u3u1u2(_subu); +I_u2s3u1(_sw); +I_0(_tlbp); +I_0(_tlbwi); +I_0(_tlbwr); +I_u3u1u2(_xor) +I_u2u1u3(_xori); + +/* + * handling labels + */ + +enum label_id { + label_invalid, + label_second_part, + label_leave, + label_vmalloc, + label_vmalloc_done, + label_tlbwr_hazard, + label_split +}; + +struct label { + u32 *addr; + enum label_id lab; +}; + +static __init void build_label(struct label **lab, u32 *addr, + enum label_id l) +{ + (*lab)->addr = addr; + (*lab)->lab = l; + (*lab)++; +} + +#define L_LA(lb) \ + static inline void l##lb(struct label **lab, u32 *addr) \ + { \ + build_label(lab, addr, label##lb); \ + } + +L_LA(_second_part) +L_LA(_leave) +L_LA(_vmalloc) +L_LA(_vmalloc_done) +L_LA(_tlbwr_hazard) +L_LA(_split) + +/* convenience macros for instructions */ +#ifdef CONFIG_MIPS64 +# define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) +# define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) +# define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) +# define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh) +# define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh) +# define i_MFC0(buf, rt, rd) i_dmfc0(buf, rt, rd) +# define i_MTC0(buf, rt, rd) i_dmtc0(buf, rt, rd) +# define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val) +# define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd) +# define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd) +#else +# define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off) +# define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off) +# define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh) +# define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh) +# define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh) +# define i_MFC0(buf, rt, rd) i_mfc0(buf, rt, rd) +# define i_MTC0(buf, rt, rd) i_mtc0(buf, rt, rd) +# define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val) +# define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd) +# define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd) +#endif + +#define i_b(buf, off) i_beq(buf, 0, 0, off) +#define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off) +#define i_move(buf, a, b) i_ADDU(buf, a, 0, b) +#define i_nop(buf) i_sll(buf, 0, 0, 0) +#define i_ssnop(buf) i_sll(buf, 0, 2, 1) + +#if CONFIG_MIPS64 +static __init int in_compat_space_p(long addr) +{ + /* Is this address in 32bit compat space? */ + return (((addr) & 0xffffffff00000000) == 0xffffffff00000000); +} + +static __init int rel_highest(long val) +{ + return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; +} + +static __init int rel_higher(long val) +{ + return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; +} +#endif + +static __init int rel_hi(long val) +{ + return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; +} + +static __init int rel_lo(long val) +{ + return ((val & 0xffff) ^ 0x8000) - 0x8000; +} + +static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) +{ +#if CONFIG_MIPS64 + if (!in_compat_space_p(addr)) { + i_lui(buf, rs, rel_highest(addr)); + if (rel_higher(addr)) + i_daddiu(buf, rs, rs, rel_higher(addr)); + if (rel_hi(addr)) { + i_dsll(buf, rs, rs, 16); + i_daddiu(buf, rs, rs, rel_hi(addr)); + i_dsll(buf, rs, rs, 16); + } else + i_dsll32(buf, rs, rs, 0); + } else +#endif + i_lui(buf, rs, rel_hi(addr)); +} + +static __init void i_LA(u32 **buf, unsigned int rs, long addr) +{ + i_LA_mostly(buf, rs, addr); + if (rel_lo(addr)) + i_ADDIU(buf, rs, rs, rel_lo(addr)); +} + +/* + * handle relocations + */ + +struct reloc { + u32 *addr; + unsigned int type; + enum label_id lab; +}; + +static __init void r_mips_pc16(struct reloc **rel, u32 *addr, + enum label_id l) +{ + (*rel)->addr = addr; + (*rel)->type = R_MIPS_PC16; + (*rel)->lab = l; + (*rel)++; +} + +static inline void __resolve_relocs(struct reloc *rel, struct label *lab) +{ + long laddr = (long)lab->addr; + long raddr = (long)rel->addr; + + switch (rel->type) { + case R_MIPS_PC16: + *rel->addr |= build_bimm(laddr - (raddr + 4)); + break; + + default: + panic("Unsupported TLB systhesizer relocation %d", + rel->type); + } +} + +static __init void resolve_relocs(struct reloc *rel, struct label *lab) +{ + struct label *l; + + for (; rel->lab != label_invalid; rel++) + for (l = lab; l->lab != label_invalid; l++) + if (rel->lab == l->lab) + __resolve_relocs(rel, l); +} + +static __init void copy_handler(struct reloc *rel, struct label *lab, + u32 *first, u32 *end, u32* target) +{ + long off = (long)(target - first); + + memcpy(target, first, (end - first) * sizeof(u32)); + + for (; rel->lab != label_invalid; rel++) + if (rel->addr >= first && rel->addr < end) + rel->addr += off; + + for (; lab->lab != label_invalid; lab++) + if (lab->addr >= first && lab->addr < end) + lab->addr += off; +} + +static __init int insn_has_bdelay(struct reloc *rel, u32 *addr) +{ + for (; rel->lab != label_invalid; rel++) { + if (rel->addr == addr + && (rel->type == R_MIPS_PC16 + || rel->type == R_MIPS_26)) + return 1; + } + + return 0; +} + +/* convenience functions for labeled branches */ +static void il_bltz(u32 **p, struct reloc **r, unsigned int reg, + enum label_id l) +{ + r_mips_pc16(r, *p, l); + i_bltz(p, reg, 0); +} + +static void il_b(u32 **p, struct reloc **r, enum label_id l) +{ + r_mips_pc16(r, *p, l); + i_b(p, 0); +} + +static void il_bnez(u32 **p, struct reloc **r, unsigned int reg, + enum label_id l) +{ + r_mips_pc16(r, *p, l); + i_bnez(p, reg, 0); +} + +static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg, + enum label_id l) +{ + r_mips_pc16(r, *p, l); + i_bgezl(p, reg, 0); +} + +/* The only registers allowed in TLB handlers. */ +#define K0 26 +#define K1 27 + +/* Some CP0 registers */ +#define C0_INDEX 0 +#define C0_ENTRYLO0 2 +#define C0_ENTRYLO1 3 +#define C0_CONTEXT 4 +#define C0_BADVADDR 8 +#define C0_ENTRYHI 10 +#define C0_EPC 14 +#define C0_XCONTEXT 20 + +#ifdef CONFIG_MIPS64 +# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) +#else +# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) +#endif + +/* The worst case length of the handler is around 18 instructions for + * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. + * Maximum space available is 32 instructions for R3000 and 64 + * instructions for R4000. + * + * We deliberately chose a buffer size of 128, so we won't scribble + * over anything important on overflow before we panic. + */ +static __initdata u32 tlb_handler[128]; + +/* simply assume worst case size for labels and relocs */ +static __initdata struct label labels[128]; +static __initdata struct reloc relocs[128]; + +#ifdef CONFIG_MIPS32 +/* + * The R3000 TLB handler is simple. + */ +static void __init build_r3000_tlb_refill_handler(void) +{ + long pgdc = (long)pgd_current; + u32 *p; + + memset(tlb_handler, 0, sizeof(tlb_handler)); + p = tlb_handler; + + i_mfc0(&p, K0, C0_BADVADDR); + i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */ + i_lw(&p, K1, rel_lo(pgdc), K1); + i_srl(&p, K0, K0, 22); /* load delay */ + i_sll(&p, K0, K0, 2); + i_addu(&p, K1, K1, K0); + i_mfc0(&p, K0, C0_CONTEXT); + i_lw(&p, K1, 0, K1); + i_andi(&p, K0, K0, 0xffc); /* load delay */ + i_addu(&p, K1, K1, K0); + i_lw(&p, K0, 0, K1); + i_nop(&p); /* load delay */ + i_mtc0(&p, K0, C0_ENTRYLO0); + i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ + i_tlbwr(&p); /* cp0 delay */ + i_jr(&p, K1); /* cp0 delay */ + i_rfe(&p); /* branch delay */ + + if (p > tlb_handler + 32) + panic("TLB refill handler space exceeded"); + + printk("Synthesized TLB handler (%u instructions).\n", + p - tlb_handler); +#ifdef DEBUG_TLB + { + int i; + for (i = 0; i < (p - tlb_handler); i++) + printk("%08x\n", tlb_handler[i]); + } +#endif + + memcpy((void *)CAC_BASE, tlb_handler, 0x80); + flush_icache_range(CAC_BASE, CAC_BASE + 0x80); +} +#endif /* CONFIG_MIPS32 */ + +/* + * The R4000 TLB handler is much more complicated. We have two + * consecutive handler areas with 32 instructions space each. + * Since they aren't used at the same time, we can overflow in the + * other one.To keep things simple, we first assume linear space, + * then we relocate it to the final handler layout as needed. + */ +static __initdata u32 final_handler[64]; + +/* + * Hazards + * + * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: + * 2. A timing hazard exists for the TLBP instruction. + * + * stalling_instruction + * TLBP + * + * The JTLB is being read for the TLBP throughout the stall generated by the + * previous instruction. This is not really correct as the stalling instruction + * can modify the address used to access the JTLB. The failure symptom is that + * the TLBP instruction will use an address created for the stalling instruction + * and not the address held in C0_ENHI and thus report the wrong results. + * + * The software work-around is to not allow the instruction preceding the TLBP + * to stall - make it an NOP or some other instruction guaranteed not to stall. + * + * Errata 2 will not be fixed. This errata is also on the R5000. + * + * As if we MIPS hackers wouldn't know how to nop pipelines happy ... + */ +static __init void build_tlbp_hazard(u32 **p) +{ + switch (current_cpu_data.cputype) { + case CPU_R5000: + case CPU_R5000A: + case CPU_NEVADA: + i_nop(p); + break; + + default: + break; + } +} + +/* + * Write random TLB entry, and care about the hazards from the + * preceeding mtc0 and for the following eret. + */ +static __init void build_tlb_write_random_entry(u32 **p, struct label **l, + struct reloc **r) +{ + switch (current_cpu_data.cputype) { + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + /* + * This branch uses up a mtc0 hazard nop slot and saves + * two nops after the tlbwr. + */ + il_bgezl(p, r, 0, label_tlbwr_hazard); + i_tlbwr(p); + l_tlbwr_hazard(l, *p); + i_nop(p); + break; + + case CPU_R4600: + case CPU_R4700: + i_nop(p); + i_tlbwr(p); + break; + + case CPU_NEVADA: + i_nop(p); /* QED specifies 2 nops hazard */ + /* + * This branch uses up a mtc0 hazard nop slot and saves + * a nop after the tlbwr. + */ + il_bgezl(p, r, 0, label_tlbwr_hazard); + i_tlbwr(p); + l_tlbwr_hazard(l, *p); + break; + + case CPU_RM9000: + /* + * When the JTLB is updated by tlbwi or tlbwr, a subsequent + * use of the JTLB for instructions should not occur for 4 + * cpu cycles and use for data translations should not occur + * for 3 cpu cycles. + */ + i_ssnop(p); + i_ssnop(p); + i_ssnop(p); + i_ssnop(p); + i_tlbwr(p); + i_ssnop(p); + i_ssnop(p); + i_ssnop(p); + i_ssnop(p); + break; + + case CPU_R10000: + case CPU_R12000: + case CPU_SB1: + i_tlbwr(p); + break; + + default: + /* + * Others are assumed to have one cycle mtc0 hazard, + * and one cycle tlbwr hazard. + * XXX: This might be overly general. + */ + i_nop(p); + i_tlbwr(p); + i_nop(p); + break; + } +} + +#if CONFIG_MIPS64 +/* + * TMP and PTR are scratch. + * TMP will be clobbered, PTR will hold the pmd entry. + */ +static __init void +build_get_pmde64(u32 **p, struct label **l, struct reloc **r, + unsigned int tmp, unsigned int ptr) +{ + long pgdc = (long)pgd_current; + + /* + * The vmalloc handling is not in the hotpath. + */ + i_dmfc0(p, tmp, C0_BADVADDR); + il_bltz(p, r, tmp, label_vmalloc); + /* No i_nop needed here, since the next insn doesn't touch TMP. */ + +# ifdef CONFIG_SMP + /* + * 64 bit SMP has the lower part of &pgd_current[smp_processor_id()] + * stored in CONTEXT. + */ + if (in_compat_space_p(pgdc)) { + i_dmfc0(p, ptr, C0_CONTEXT); + i_dsra(p, ptr, ptr, 23); + } else { + i_dmfc0(p, ptr, C0_CONTEXT); + i_lui(p, tmp, rel_highest(pgdc)); + i_dsll(p, ptr, ptr, 9); + i_daddiu(p, tmp, tmp, rel_higher(pgdc)); + i_dsrl32(p, ptr, ptr, 0); + i_and(p, ptr, ptr, tmp); + i_dmfc0(p, tmp, C0_BADVADDR); + } + i_ld(p, ptr, 0, ptr); +# else + i_LA_mostly(p, ptr, pgdc); + i_ld(p, ptr, rel_lo(pgdc), ptr); +# endif + + l_vmalloc_done(l, *p); + i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */ + i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); + i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ + i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + i_ld(p, ptr, 0, ptr); /* get pmd pointer */ + i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ + i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); + i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ +} + +/* + * BVADDR is the faulting address, PTR is scratch. + * PTR will hold the pgd for vmalloc. + */ +static __init void +build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, + unsigned int bvaddr, unsigned int ptr) +{ + long swpd = (long)swapper_pg_dir; + + l_vmalloc(l, *p); + i_LA(p, ptr, VMALLOC_START); + i_dsubu(p, bvaddr, bvaddr, ptr); + + if (in_compat_space_p(swpd) && !rel_lo(swpd)) { + il_b(p, r, label_vmalloc_done); + i_lui(p, ptr, rel_hi(swpd)); + } else { + i_LA_mostly(p, ptr, swpd); + il_b(p, r, label_vmalloc_done); + i_daddiu(p, ptr, ptr, rel_lo(swpd)); + } +} + +#else /* CONFIG_MIPS32 */ + +/* + * TMP and PTR are scratch. + * TMP will be clobbered, PTR will hold the pgd entry. + */ +static __init void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) +{ + long pgdc = (long)pgd_current; + + /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ +#ifdef CONFIG_SMP + i_mfc0(p, ptr, C0_CONTEXT); + i_LA_mostly(p, tmp, pgdc); + i_srl(p, ptr, ptr, 23); + i_sll(p, ptr, ptr, 2); + i_addu(p, ptr, tmp, ptr); +#else + i_LA_mostly(p, ptr, pgdc); +#endif + i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + i_lw(p, ptr, rel_lo(pgdc), ptr); + i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ + i_sll(p, tmp, tmp, PGD_T_LOG2); + i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ +} +#endif /* CONFIG_MIPS32 */ + +static __init void build_adjust_context(u32 **p, unsigned int ctx) +{ + unsigned int shift = 0; + unsigned int mask = 0xff0; + +#if !defined(CONFIG_MIPS64) && !defined(CONFIG_64BIT_PHYS_ADDR) + shift++; + mask |= 0x008; +#endif + + switch (current_cpu_data.cputype) { + case CPU_VR41XX: + case CPU_VR4111: + case CPU_VR4121: + case CPU_VR4122: + case CPU_VR4131: + case CPU_VR4181: + case CPU_VR4181A: + case CPU_VR4133: + shift += 2; + break; + + default: + break; + } + + if (shift) + i_SRL(p, ctx, ctx, shift); + i_andi(p, ctx, ctx, mask); +} + +static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) +{ + /* + * Bug workaround for the Nevada. It seems as if under certain + * circumstances the move from cp0_context might produce a + * bogus result when the mfc0 instruction and its consumer are + * in a different cacheline or a load instruction, probably any + * memory reference, is between them. + */ + switch (current_cpu_data.cputype) { + case CPU_NEVADA: + i_LW(p, ptr, 0, ptr); + GET_CONTEXT(p, tmp); /* get context reg */ + break; + + default: + GET_CONTEXT(p, tmp); /* get context reg */ + i_LW(p, ptr, 0, ptr); + break; + } + + build_adjust_context(p, tmp); + i_ADDU(p, ptr, ptr, tmp); /* add in offset */ +} + +static __init void build_update_entries(u32 **p, unsigned int tmp, + unsigned int ptep) +{ + /* + * 64bit address support (36bit on a 32bit CPU) in a 32bit + * Kernel is a special case. Only a few CPUs use it. + */ +#ifdef CONFIG_64BIT_PHYS_ADDR + if (cpu_has_64bit_registers) { + i_ld(p, tmp, 0, ptep); /* get even pte */ + i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ + i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ + i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ + i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ + } else { + int pte_off_even = sizeof(pte_t) / 2; + int pte_off_odd = pte_off_even + sizeof(pte_t); + + /* The pte entries are pre-shifted */ + i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ + i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ + i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ + } +#else + i_LW(p, tmp, 0, ptep); /* get even pte */ + i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ + if (r45k_bvahwbug()) { + build_tlbp_hazard(p); + i_tlbp(p); + } + i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ + if (r4k_250MHZhwbug()) + i_mtc0(p, 0, C0_ENTRYLO0); + i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ + if (r45k_bvahwbug()) + i_mfc0(p, tmp, C0_INDEX); + if (r4k_250MHZhwbug()) + i_mtc0(p, 0, C0_ENTRYLO1); + i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ +#endif +} + +static void __init build_r4000_tlb_refill_handler(void) +{ + u32 *p = tlb_handler; + struct label *l = labels; + struct reloc *r = relocs; + u32 *f; + unsigned int final_len; + + memset(tlb_handler, 0, sizeof(tlb_handler)); + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + memset(final_handler, 0, sizeof(final_handler)); + + /* + * create the plain linear handler + */ + if (bcm1250_m3_war) { + i_MFC0(&p, K0, C0_BADVADDR); + i_MFC0(&p, K1, C0_ENTRYHI); + i_xor(&p, K0, K0, K1); + i_SRL(&p, K0, K0, PAGE_SHIFT+1); + il_bnez(&p, &r, K0, label_leave); + /* No need for i_nop */ + } + +#ifdef CONFIG_MIPS64 + build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd ptr in K1 */ +#else + build_get_pgde32(&p, K0, K1); /* get pgd ptr in K1 */ +#endif + + build_get_ptep(&p, K0, K1); + build_update_entries(&p, K0, K1); + build_tlb_write_random_entry(&p, &l, &r); + l_leave(&l, p); + i_eret(&p); /* return from trap */ + +#ifdef CONFIG_MIPS64 + build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); +#endif + + /* + * Overflow check: For the 64bit handler, we need at least one + * free instruction slot for the wrap-around branch. In worst + * case, if the intended insertion point is a delay slot, we + * need three, with the the second nop'ed and the third being + * unused. + */ +#ifdef CONFIG_MIPS32 + if ((p - tlb_handler) > 64) + panic("TLB refill handler space exceeded"); +#else + if (((p - tlb_handler) > 63) + || (((p - tlb_handler) > 61) + && insn_has_bdelay(relocs, tlb_handler + 29))) + panic("TLB refill handler space exceeded"); +#endif + + /* + * Now fold the handler in the TLB refill handler space. + */ +#ifdef CONFIG_MIPS32 + f = final_handler; + /* Simplest case, just copy the handler. */ + copy_handler(relocs, labels, tlb_handler, p, f); + final_len = p - tlb_handler; +#else /* CONFIG_MIPS64 */ + f = final_handler + 32; + if ((p - tlb_handler) <= 32) { + /* Just copy the handler. */ + copy_handler(relocs, labels, tlb_handler, p, f); + final_len = p - tlb_handler; + } else { + u32 *split = tlb_handler + 30; + + /* + * Find the split point. + */ + if (insn_has_bdelay(relocs, split - 1)) + split--; + + /* Copy first part of the handler. */ + copy_handler(relocs, labels, tlb_handler, split, f); + f += split - tlb_handler; + + /* Insert branch. */ + l_split(&l, final_handler); + il_b(&f, &r, label_split); + if (insn_has_bdelay(relocs, split)) + i_nop(&f); + else { + copy_handler(relocs, labels, split, split + 1, f); + f++; + split++; + } + + /* Copy the rest of the handler. */ + copy_handler(relocs, labels, split, p, final_handler); + final_len = (f - (final_handler + 32)) + (p - split); + } +#endif /* CONFIG_MIPS64 */ + + resolve_relocs(relocs, labels); + printk("Synthesized TLB handler (%u instructions).\n", final_len); + +#ifdef DEBUG_TLB + { + int i; + + for (i = 0; i < 64; i++) + printk("%08x\n", final_handler[i]); + } +#endif + + memcpy((void *)CAC_BASE, final_handler, 0x100); + flush_icache_range(CAC_BASE, CAC_BASE + 0x100); +} + +void __init build_tlb_refill_handler(void) +{ + switch (current_cpu_data.cputype) { +#ifdef CONFIG_MIPS32 + case CPU_R2000: + case CPU_R3000: + case CPU_R3000A: + case CPU_R3081E: + case CPU_TX3912: + case CPU_TX3922: + case CPU_TX3927: + build_r3000_tlb_refill_handler(); + break; + + case CPU_R6000: + case CPU_R6000A: + panic("No R6000 TLB refill handler yet"); + break; +#endif + + case CPU_R8000: + panic("No R8000 TLB refill handler yet"); + break; + + default: + build_r4000_tlb_refill_handler(); + } +} --- arch/mips/mm/tlbex64-r4k.S 2004-11-21 03:05:35.000000000 +0100 +++ /dev/null 2004-08-24 19:23:08.000000000 +0200 @@ -1,136 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Written by Ulf Carlsson (ulfc@engr.sgi.com) - * Copyright (C) 2002 Maciej W. Rozycki - */ -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define _VMALLOC_START 0xc000000000000000 - - .macro GET_PGD, ptr -#ifdef CONFIG_SMP - /* - * Fixme - this is b0rked for pgd_current outside of CKSEG0 - */ - dmfc0 \ptr, CP0_CONTEXT - dsra \ptr, 23 # get pgd_current[cpu] - ld \ptr, (\ptr) -#else - ld \ptr, pgd_current -#endif - .endm - - /* - * After this macro runs we have a pointer to the pte of the address - * that caused the fault in PTR. Expects register containing the - * the pagetable root pointer as the ptr argument and c0_badvaddr - * passed as tmp argument. - */ - .macro LOAD_PTE2, ptr, tmp - dsrl \tmp, (_PGDIR_SHIFT-3) # get pgd offset in bytes - andi \tmp, ((_PTRS_PER_PGD - 1)<<3) - daddu \ptr, \tmp # add in pgd offset - dmfc0 \tmp, CP0_BADVADDR - ld \ptr, (\ptr) # get pmd pointer - dsrl \tmp, (_PMD_SHIFT-3) # get pmd offset in bytes - andi \tmp, ((_PTRS_PER_PMD - 1)<<3) - daddu \ptr, \tmp # add in pmd offset - dmfc0 \tmp, CP0_XCONTEXT - ld \ptr, (\ptr) # get pte pointer - andi \tmp, 0xff0 # get pte offset - daddu \ptr, \tmp - .endm - - /* - * This places the even/odd pte pair in the page table at the pte - * entry pointed to by PTE into ENTRYLO0 and ENTRYLO1. - */ - .macro PTE_RELOAD, pte0, pte1 - dsrl \pte0, 6 # convert to entrylo0 - dmtc0 \pte0, CP0_ENTRYLO0 # load it - dsrl \pte1, 6 # convert to entrylo1 - dmtc0 \pte1, CP0_ENTRYLO1 # load it - .endm - - - .text - .set noreorder - .set mips3 - - __INIT - - /* - * TLB refill handlers for the R4000 and SB1. - * Attention: We may only use 32 instructions / 128 bytes. - */ - .align 5 -LEAF(except_vec1_r4k) - .set noat - dla k0, handle_vec1_r4k - jr k0 - nop -END(except_vec1_r4k) - -LEAF(except_vec1_sb1) -#if BCM1250_M3_WAR - dmfc0 k0, CP0_BADVADDR - dmfc0 k1, CP0_ENTRYHI - xor k0, k1 - dsrl k0, k0, _PAGE_SHIFT+1 - bnez k0, 1f -#endif - .set noat - dla k0, handle_vec1_r4k - jr k0 - nop - -1: eret - nop -END(except_vec1_sb1) - - __FINIT - - .align 5 -LEAF(handle_vec1_r4k) - .set noat - dmfc0 k0, CP0_BADVADDR - bltz k0, 9f - - GET_PGD k1 # pointer to root of pgd - LOAD_PTE2 k1 k0 - ld k0, 0(k1) # get even pte - ld k1, 8(k1) # get odd pte - PTE_RELOAD k0 k1 - mtc0_tlbw_hazard - tlbwr - nop - tlbw_eret_hazard - eret - -9: # handle the vmalloc range - dli k1, _VMALLOC_START - dsubu k0, k1 - dla k1, swapper_pg_dir # pointer to root of pgd - LOAD_PTE2 k1 k0 - ld k0, 0(k1) # get even pte - ld k1, 8(k1) # get odd pte - PTE_RELOAD k0 k1 - mtc0_tlbw_hazard - tlbwr - nop - tlbw_eret_hazard - eret -END(handle_vec1_r4k) From ralf@linux-mips.org Sun Nov 21 17:16:38 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 17:16:42 +0000 (GMT) Received: from p508B7F2C.dip.t-dialin.net ([IPv6:::ffff:80.139.127.44]:48925 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 17:16:38 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iALHESlA009204; Sun, 21 Nov 2004 18:14:28 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iALHENOr009203; Sun, 21 Nov 2004 18:14:23 +0100 Date: Sun, 21 Nov 2004 18:14:23 +0100 From: Ralf Baechle To: Geert Uytterhoeven Cc: Thiemo Seufer , Linux/MIPS Development Subject: Re: [PATCH] ip32 build fix Message-ID: <20041121171423.GA9177@linux-mips.org> References: <20041121024144.GK20986@rembrandt.csv.ica.uni-stuttgart.de> <20041121065630.GA6701@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6386 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 215 Lines: 8 On Sun, Nov 21, 2004 at 10:18:26AM +0100, Geert Uytterhoeven wrote: > FYI, this has been fixed differently in mainline: Argh, I hat that. Defining variables in the middle of a block is also unhealthy ... Ralf From ralf@linux-mips.org Sun Nov 21 17:24:05 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 17:24:09 +0000 (GMT) Received: from p508B7F2C.dip.t-dialin.net ([IPv6:::ffff:80.139.127.44]:54813 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 17:24:05 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iALHLv2D009348; Sun, 21 Nov 2004 18:21:57 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iALHLvHc009347; Sun, 21 Nov 2004 18:21:57 +0100 Date: Sun, 21 Nov 2004 18:21:57 +0100 From: Ralf Baechle To: Thiemo Seufer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Add comment about oversized r4000 interrupt vector Message-ID: <20041121172157.GB9177@linux-mips.org> References: <20041121162458.GP20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041121162458.GP20986@rembrandt.csv.ica.uni-stuttgart.de> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6387 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 175 Lines: 6 On Sun, Nov 21, 2004 at 05:24:58PM +0100, Thiemo Seufer wrote: > to prevent it to get lost again, this adds an explanatory comment > to the r4000 exception vector init. Ok. From ralf@linux-mips.org Sun Nov 21 19:34:55 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 19:34:59 +0000 (GMT) Received: from p508B7F2C.dip.t-dialin.net ([IPv6:::ffff:80.139.127.44]:1055 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 19:34:55 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iALJWlWF011604; Sun, 21 Nov 2004 20:32:47 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iALJWkWU011603; Sun, 21 Nov 2004 20:32:46 +0100 Date: Sun, 21 Nov 2004 20:32:46 +0100 From: Ralf Baechle To: Thiemo Seufer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Improve ramdisk support Message-ID: <20041121193246.GA10561@linux-mips.org> References: <20041121030614.GL20986@rembrandt.csv.ica.uni-stuttgart.de> <20041121162054.GO20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041121162054.GO20986@rembrandt.csv.ica.uni-stuttgart.de> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6388 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 205 Lines: 8 On Sun, Nov 21, 2004 at 05:20:54PM +0100, Thiemo Seufer wrote: > CONFIG_EMBEDDED_RAMDISK is gone now. The updated patch below removes > some leftovers. Thanks for updating your patch so quickly. Ralf From geert@linux-m68k.org Sun Nov 21 19:50:32 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 19:50:37 +0000 (GMT) Received: from witte.sonytel.be ([IPv6:::ffff:80.88.33.193]:54983 "EHLO witte.sonytel.be") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 19:50:32 +0000 Received: from waterleaf.sonytel.be (mail.sonytel.be [43.221.60.197]) by witte.sonytel.be (8.12.10/8.12.10) with ESMTP id iALJoUGU015081; Sun, 21 Nov 2004 20:50:30 +0100 (MET) Date: Sun, 21 Nov 2004 20:50:30 +0100 (MET) From: Geert Uytterhoeven To: Thiemo Seufer cc: Linux/MIPS Development , Ralf Baechle Subject: Re: [PATCH] Synthesize TLB refill handler at runtime In-Reply-To: <20041121170242.GR20986@rembrandt.csv.ica.uni-stuttgart.de> Message-ID: References: <20041121170242.GR20986@rembrandt.csv.ica.uni-stuttgart.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6389 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Content-Length: 745 Lines: 23 On Sun, 21 Nov 2004, Thiemo Seufer wrote: > currently we have a large number of TLB refill handlers written in > hand-optimized assembly which are mostly indentical. The appended > patch removes them all, and adds a micro-assembler instead which > synthesizes the proper variant for the CPU at runtime. Woow..... I found a few typos (in the comments, didn't verify the code ;-) s/Systhesize/Synthesize/ s/systhesizer/synthesizer/ Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From ica2_ts@csv.ica.uni-stuttgart.de Sun Nov 21 20:37:59 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 20:38:12 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:17169 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 20:37:59 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CVyT8-0004Kt-00; Sun, 21 Nov 2004 21:37:58 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CVyT7-0007SJ-00; Sun, 21 Nov 2004 21:37:57 +0100 Date: Sun, 21 Nov 2004 21:37:57 +0100 To: Geert Uytterhoeven Cc: Linux/MIPS Development , Ralf Baechle Subject: Re: [PATCH] Synthesize TLB refill handler at runtime Message-ID: <20041121203757.GS20986@rembrandt.csv.ica.uni-stuttgart.de> References: <20041121170242.GR20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6390 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 49542 Lines: 1860 Geert Uytterhoeven wrote: > On Sun, 21 Nov 2004, Thiemo Seufer wrote: > > currently we have a large number of TLB refill handlers written in > > hand-optimized assembly which are mostly indentical. The appended > > patch removes them all, and adds a micro-assembler instead which > > synthesizes the proper variant for the CPU at runtime. > > Woow..... > > I found a few typos (in the comments, didn't verify the code ;-) > > s/Systhesize/Synthesize/ > s/systhesizer/synthesizer/ Aww, fatal error in the spelling module. :-) Updated. Thiemo Index: arch/mips/mm/Makefile =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/Makefile,v retrieving revision 1.68 diff -u -p -r1.68 Makefile --- arch/mips/mm/Makefile 20 Jun 2004 23:52:17 -0000 1.68 +++ arch/mips/mm/Makefile 20 Nov 2004 16:46:40 -0000 @@ -2,7 +2,8 @@ # Makefile for the Linux/MIPS-specific parts of the memory manager. # -obj-y += cache.o extable.o fault.o init.o pgtable.o +obj-y += cache.o extable.o fault.o init.o pgtable.o \ + tlbex.o obj-$(CONFIG_MIPS32) += ioremap.o pgtable-32.o obj-$(CONFIG_MIPS64) += pgtable-64.o @@ -47,16 +48,16 @@ obj-$(CONFIG_CPU_SB1) += tlbex32-r4k.o obj-$(CONFIG_CPU_TX39XX) += tlbex32-r3k.o endif ifdef CONFIG_MIPS64 -obj-$(CONFIG_CPU_R4300) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_R4X00) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_R5000) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_NEVADA) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_R5432) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_RM7000) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_RM9000) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_R10000) += tlb64-glue-r4k.o tlbex64-r4k.o -obj-$(CONFIG_CPU_SB1) += tlb64-glue-sb1.o tlbex64-r4k.o -obj-$(CONFIG_CPU_MIPS64) += tlb64-glue-r4k.o tlbex64-r4k.o +obj-$(CONFIG_CPU_R4300) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_R4X00) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_R5000) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_NEVADA) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_R5432) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_RM7000) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_RM9000) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_R10000) += tlb64-glue-r4k.o +obj-$(CONFIG_CPU_SB1) += tlb64-glue-sb1.o +obj-$(CONFIG_CPU_MIPS64) += tlb64-glue-r4k.o endif Index: arch/mips/mm/tlb-andes.c =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlb-andes.c,v retrieving revision 1.8 diff -u -p -r1.8 tlb-andes.c --- arch/mips/mm/tlb-andes.c 19 Oct 2004 02:21:16 -0000 1.8 +++ arch/mips/mm/tlb-andes.c 20 Nov 2004 16:46:46 -0000 @@ -17,10 +17,7 @@ #include #include -extern void except_vec0_generic(void); -extern void except_vec0_r4000(void); -extern void except_vec1_generic(void); -extern void except_vec1_r4k(void); +extern void build_tlb_refill_handler(void); #define NTLB_ENTRIES 64 #define NTLB_ENTRIES_HALF 32 @@ -257,14 +254,5 @@ void __init tlb_init(void) /* Did I tell you that ARC SUCKS? */ -#ifdef CONFIG_MIPS32 - memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); - memcpy((void *)(KSEG0 + 0x080), &except_vec1_generic, 0x80); - flush_icache_range(KSEG0, KSEG0 + 0x100); -#endif -#ifdef CONFIG_MIPS64 - memcpy((void *)(CKSEG0 + 0x000), &except_vec0_generic, 0x80); - memcpy((void *)(CKSEG0 + 0x080), except_vec1_r4k, 0x80); - flush_icache_range(CKSEG0 + 0x80, CKSEG0 + 0x100); -#endif + build_tlb_refill_handler(); } Index: arch/mips/mm/tlb-r3k.c =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlb-r3k.c,v retrieving revision 1.26 diff -u -p -r1.26 tlb-r3k.c --- arch/mips/mm/tlb-r3k.c 11 Dec 2003 16:27:01 -0000 1.26 +++ arch/mips/mm/tlb-r3k.c 20 Nov 2004 16:46:46 -0000 @@ -26,7 +26,7 @@ #undef DEBUG_TLB -extern char except_vec0_r2300; +extern void build_tlb_refill_handler(void); /* CP0 hazard avoidance. */ #define BARRIER \ @@ -284,6 +284,6 @@ void __init add_wired_entry(unsigned lon void __init tlb_init(void) { local_flush_tlb_all(); - memcpy((void *)KSEG0, &except_vec0_r2300, 0x80); - flush_icache_range(KSEG0, KSEG0 + 0x80); + + build_tlb_refill_handler(); } Index: arch/mips/mm/tlb-r4k.c =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlb-r4k.c,v retrieving revision 1.38 diff -u -p -r1.38 tlb-r4k.c --- arch/mips/mm/tlb-r4k.c 19 Mar 2004 04:07:59 -0000 1.38 +++ arch/mips/mm/tlb-r4k.c 20 Nov 2004 16:46:46 -0000 @@ -19,12 +19,7 @@ #include #include -extern void except_vec0_generic(void); -extern void except_vec0_nevada(void); -extern void except_vec0_r4000(void); -extern void except_vec0_r4600(void); -extern void except_vec1_generic(void); -extern void except_vec1_r4k(void); +extern void build_tlb_refill_handler(void); /* CP0 hazard avoidance. */ #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ @@ -414,19 +409,5 @@ void __init tlb_init(void) temp_tlb_entry = current_cpu_data.tlbsize - 1; local_flush_tlb_all(); -#ifdef CONFIG_MIPS32 - if (current_cpu_data.cputype == CPU_NEVADA) - memcpy((void *)KSEG0, &except_vec0_nevada, 0x80); - else if (current_cpu_data.cputype == CPU_R4600) - memcpy((void *)KSEG0, &except_vec0_r4600, 0x80); - else - memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); - memcpy((void *)(KSEG0 + 0x080), &except_vec1_generic, 0x80); - flush_icache_range(KSEG0, KSEG0 + 0x100); -#endif -#ifdef CONFIG_MIPS64 - memcpy((void *)(CKSEG0 + 0x00), &except_vec0_generic, 0x80); - memcpy((void *)(CKSEG0 + 0x80), except_vec1_r4k, 0x80); - flush_icache_range(CKSEG0 + 0x80, CKSEG0 + 0x100); -#endif + build_tlb_refill_handler(); } Index: arch/mips/mm/tlb-r8k.c =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlb-r8k.c,v retrieving revision 1.1 diff -u -p -r1.1 tlb-r8k.c --- arch/mips/mm/tlb-r8k.c 20 Jun 2004 23:01:07 -0000 1.1 +++ arch/mips/mm/tlb-r8k.c 20 Nov 2004 16:46:46 -0000 @@ -19,8 +19,7 @@ #include #include -extern void except_vec0_generic(void); -extern void except_vec1_r8k(void); +extern void build_tlb_refill_handler(void); #define TFP_TLB_SIZE 384 #define TFP_TLB_SET_SHIFT 7 @@ -247,7 +246,5 @@ void __init tlb_init(void) local_flush_tlb_all(); - memcpy((void *)(CKSEG0 + 0x00), &except_vec0_generic, 0x80); - memcpy((void *)(CKSEG0 + 0x80), except_vec1_r8k, 0x80); - flush_icache_range(CKSEG0 + 0x80, CKSEG0 + 0x100); + build_tlb_refill_handler(); } Index: arch/mips/mm/tlb-sb1.c =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlb-sb1.c,v retrieving revision 1.45 diff -u -p -r1.45 tlb-sb1.c --- arch/mips/mm/tlb-sb1.c 23 Oct 2004 01:18:17 -0000 1.45 +++ arch/mips/mm/tlb-sb1.c 20 Nov 2004 16:46:46 -0000 @@ -23,14 +23,7 @@ #include #include -#ifdef CONFIG_MIPS32 -extern void except_vec0_sb1(void); -extern void except_vec1_generic(void); -#endif -#ifdef CONFIG_MIPS64 -extern void except_vec0_generic(void); -extern void except_vec1_sb1(void); -#endif +extern void build_tlb_refill_handler(void); #define UNIQUE_ENTRYHI(idx) (KSEG0 + ((idx) << (PAGE_SHIFT + 1))) @@ -380,14 +373,5 @@ void tlb_init(void) */ sb1_sanitize_tlb(); -#ifdef CONFIG_MIPS32 - memcpy((void *)KSEG0, &except_vec0_sb1, 0x80); - memcpy((void *)(KSEG0 + 0x080), &except_vec1_generic, 0x80); - flush_icache_range(KSEG0, KSEG0 + 0x100); -#endif -#ifdef CONFIG_MIPS64 - memcpy((void *)CKSEG0, &except_vec0_generic, 0x80); - memcpy((void *)(CKSEG0 + 0x80), &except_vec1_sb1, 0x80); - flush_icache_range(CKSEG0, CKSEG0 + 0x100); -#endif + build_tlb_refill_handler(); } Index: arch/mips/mm/tlbex32-r3k.S =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlbex32-r3k.S,v retrieving revision 1.1 diff -u -p -r1.1 tlbex32-r3k.S --- arch/mips/mm/tlbex32-r3k.S 20 Jun 2004 23:52:17 -0000 1.1 +++ arch/mips/mm/tlbex32-r3k.S 20 Nov 2004 16:46:46 -0000 @@ -24,36 +24,6 @@ #define TLB_OPTIMIZE /* If you are paranoid, disable this. */ - .text - .set mips1 - .set noreorder - - __INIT - - /* TLB refill, R[23]00 version */ - LEAF(except_vec0_r2300) - .set noat - .set mips1 - mfc0 k0, CP0_BADVADDR - lw k1, pgd_current # get pgd pointer - srl k0, k0, 22 - sll k0, k0, 2 - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) - and k0, k0, 0xffc - addu k1, k1, k0 - lw k0, (k1) - nop - mtc0 k0, CP0_ENTRYLO0 - mfc0 k1, CP0_EPC - tlbwr - jr k1 - rfe - END(except_vec0_r2300) - - __FINIT - /* ABUSE of CPP macros 101. */ /* After this macro runs, the pte faulted on is Index: arch/mips/mm/tlbex32-r4k.S =================================================================== RCS file: /home/cvs/linux/arch/mips/mm/tlbex32-r4k.S,v retrieving revision 1.2 diff -u -p -r1.2 tlbex32-r4k.S --- arch/mips/mm/tlbex32-r4k.S 3 Oct 2004 01:16:24 -0000 1.2 +++ arch/mips/mm/tlbex32-r4k.S 20 Nov 2004 16:46:46 -0000 @@ -139,272 +139,6 @@ _PAGE_VALID | _PAGE_DIRTY); \ PTE_S pte, (ptr); - __INIT - -#ifdef CONFIG_64BIT_PHYS_ADDR -#define GET_PTE_OFF(reg) -#elif CONFIG_CPU_VR41XX -#define GET_PTE_OFF(reg) srl reg, reg, 3 -#else -#define GET_PTE_OFF(reg) srl reg, reg, 1 -#endif - -/* - * These handlers much be written in a relocatable manner - * because based upon the cpu type an arbitrary one of the - * following pieces of code will be copied to the KSEG0 - * vector location. - */ - /* TLB refill, EXL == 0, R4xx0, non-R4600 version */ - .set noreorder - .set noat - LEAF(except_vec0_r4000) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR # Get faulting address - srl k0, k0, _PGDIR_SHIFT # get pgd only bits - - sll k0, k0, 2 - addu k1, k1, k0 # add in pgd offset - mfc0 k0, CP0_CONTEXT # get context reg - lw k1, (k1) - GET_PTE_OFF(k0) # get pte offset - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 # add in offset - PTE_L k0, 0(k1) # get even pte - PTE_L k1, PTE_SIZE(k1) # get odd pte - PTE_SRL k0, k0, 6 # convert to entrylo0 - P_MTC0 k0, CP0_ENTRYLO0 # load it - PTE_SRL k1, k1, 6 # convert to entrylo1 - P_MTC0 k1, CP0_ENTRYLO1 # load it - mtc0_tlbw_hazard - tlbwr # write random tlb entry - nop - tlbw_eret_hazard - eret # return from trap - END(except_vec0_r4000) - - /* TLB refill, EXL == 0, R4600 version */ - LEAF(except_vec0_r4600) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR - srl k0, k0, _PGDIR_SHIFT - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) - GET_PTE_OFF(k0) # get pte offset - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 - PTE_L k0, 0(k1) - PTE_L k1, PTE_SIZE(k1) - PTE_SRL k0, k0, 6 - P_MTC0 k0, CP0_ENTRYLO0 - PTE_SRL k1, k1, 6 - P_MTC0 k1, CP0_ENTRYLO1 - nop - tlbwr - nop - eret - END(except_vec0_r4600) - - /* TLB refill, EXL == 0, R52x0 "Nevada" version */ - /* - * This version has a bug workaround for the Nevada. It seems - * as if under certain circumstances the move from cp0_context - * might produce a bogus result when the mfc0 instruction and - * it's consumer are in a different cacheline or a load instruction, - * probably any memory reference, is between them. This is - * potencially slower than the R4000 version, so we use this - * special version. - */ - .set noreorder - .set noat - LEAF(except_vec0_nevada) - .set mips3 - mfc0 k0, CP0_BADVADDR # Get faulting address - srl k0, k0, _PGDIR_SHIFT # get pgd only bits - lw k1, pgd_current # get pgd pointer - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 # add in pgd offset - lw k1, (k1) - mfc0 k0, CP0_CONTEXT # get context reg - GET_PTE_OFF(k0) # get pte offset - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 # add in offset - PTE_L k0, 0(k1) # get even pte - PTE_L k1, PTE_SIZE(k1) # get odd pte - PTE_SRL k0, k0, 6 # convert to entrylo0 - P_MTC0 k0, CP0_ENTRYLO0 # load it - PTE_SRL k1, k1, 6 # convert to entrylo1 - P_MTC0 k1, CP0_ENTRYLO1 # load it - nop # QED specified nops - nop - tlbwr # write random tlb entry - nop # traditional nop - eret # return from trap - END(except_vec0_nevada) - - /* TLB refill, EXL == 0, SB1 with M3 errata handling version */ - LEAF(except_vec0_sb1) -#if BCM1250_M3_WAR - mfc0 k0, CP0_BADVADDR - mfc0 k1, CP0_ENTRYHI - xor k0, k1 - srl k0, k0, PAGE_SHIFT+1 - bnez k0, 1f -#endif - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR # Get faulting address - srl k0, k0, _PGDIR_SHIFT # get pgd only bits - sll k0, k0, 2 - addu k1, k1, k0 # add in pgd offset - mfc0 k0, CP0_CONTEXT # get context reg - lw k1, (k1) - GET_PTE_OFF(k0) # get pte offset - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 # add in offset - PTE_L k0, 0(k1) # get even pte - PTE_L k1, PTE_SIZE(k1) # get odd pte - PTE_SRL k0, k0, 6 # convert to entrylo0 - P_MTC0 k0, CP0_ENTRYLO0 # load it - PTE_SRL k1, k1, 6 # convert to entrylo1 - P_MTC0 k1, CP0_ENTRYLO1 # load it - tlbwr # write random tlb entry -1: eret # return from trap - END(except_vec0_sb1) - - /* TLB refill, EXL == 0, R4[40]00/R5000 badvaddr hwbug version */ - LEAF(except_vec0_r45k_bvahwbug) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR - srl k0, k0, _PGDIR_SHIFT - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) -#ifndef CONFIG_64BIT_PHYS_ADDR - srl k0, k0, 1 -#endif - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 - PTE_L k0, 0(k1) - PTE_L k1, PTE_SIZE(k1) - nop /* XXX */ - tlbp - PTE_SRL k0, k0, 6 - P_MTC0 k0, CP0_ENTRYLO0 - PTE_SRL k1, k1, 6 - mfc0 k0, CP0_INDEX - P_MTC0 k1, CP0_ENTRYLO1 - bltzl k0, 1f - tlbwr -1: - nop - eret - END(except_vec0_r45k_bvahwbug) - -#ifdef CONFIG_SMP - /* TLB refill, EXL == 0, R4000 MP badvaddr hwbug version */ - LEAF(except_vec0_r4k_mphwbug) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR - srl k0, k0, _PGDIR_SHIFT - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) -#ifndef CONFIG_64BIT_PHYS_ADDR - srl k0, k0, 1 -#endif - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 - PTE_L k0, 0(k1) - PTE_L k1, PTE_SIZE(k1) - nop /* XXX */ - tlbp - PTE_SRL k0, k0, 6 - P_MTC0 k0, CP0_ENTRYLO0 - PTE_SRL k1, k1, 6 - mfc0 k0, CP0_INDEX - P_MTC0 k1, CP0_ENTRYLO1 - bltzl k0, 1f - tlbwr -1: - nop - eret - END(except_vec0_r4k_mphwbug) -#endif - - /* TLB refill, EXL == 0, R4000 UP 250MHZ entrylo[01] hwbug version */ - LEAF(except_vec0_r4k_250MHZhwbug) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR - srl k0, k0, _PGDIR_SHIFT - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) -#ifndef CONFIG_64BIT_PHYS_ADDR - srl k0, k0, 1 -#endif - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 - PTE_L k0, 0(k1) - PTE_L k1, PTE_SIZE(k1) - PTE_SRL k0, k0, 6 - P_MTC0 zero, CP0_ENTRYLO0 - P_MTC0 k0, CP0_ENTRYLO0 - PTE_SRL k1, k1, 6 - P_MTC0 zero, CP0_ENTRYLO1 - P_MTC0 k1, CP0_ENTRYLO1 - b 1f - tlbwr -1: - nop - eret - END(except_vec0_r4k_250MHZhwbug) - -#ifdef CONFIG_SMP - /* TLB refill, EXL == 0, R4000 MP 250MHZ entrylo[01]+badvaddr bug version */ - LEAF(except_vec0_r4k_MP250MHZhwbug) - .set mips3 - GET_PGD(k0, k1) # get pgd pointer - mfc0 k0, CP0_BADVADDR - srl k0, k0, _PGDIR_SHIFT - sll k0, k0, 2 # log2(sizeof(pgd_t) - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) -#ifndef CONFIG_64BIT_PHYS_ADDR - srl k0, k0, 1 -#endif - and k0, k0, PTEP_INDX_MSK - addu k1, k1, k0 - PTE_L k0, 0(k1) - PTE_L k1, PTE_SIZE(k1) - nop /* XXX */ - tlbp - PTE_SRL k0, k0, 6 - P_MTC0 zero, CP0_ENTRYLO0 - P_MTC0 k0, CP0_ENTRYLO0 - mfc0 k0, CP0_INDEX - PTE_SRL k1, k1, 6 - P_MTC0 zero, CP0_ENTRYLO1 - P_MTC0 k1, CP0_ENTRYLO1 - bltzl k0, 1f - tlbwr -1: - nop - eret - END(except_vec0_r4k_MP250MHZhwbug) -#endif - - __FINIT .set noreorder --- /dev/null 2004-08-24 19:23:08.000000000 +0200 +++ arch/mips/mm/tlbex.c 2004-11-20 17:41:35.000000000 +0100 @@ -0,0 +1,1162 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Synthesize TLB refill handlers at runtime. + * + * Copyright (C) 2004 by Thiemo Seufer + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* #define DEBUG_TLB */ + +static __init int r45k_bvahwbug(void) +{ + /* XXX: We should probe for the presence of this bug, but we don't. */ + return 0; +} + +static __init int r4k_250MHZhwbug(void) +{ + /* XXX: We should probe for the presence of this bug, but we don't. */ + return 0; +} + +static __init int bcm1250_m3_war(void) +{ + return BCM1250_M3_WAR; +} + +/* + * A little micro-assembler, intended for TLB refill handler + * synthesizing. It is intentionally kept simple, does only support + * a subset of instructions, and does not try to hide pipeline effects + * like branch delay slots. + */ + +enum fields +{ + RS = 0x001, + RT = 0x002, + RD = 0x004, + RE = 0x008, + SIMM = 0x010, + UIMM = 0x020, + BIMM = 0x040, + JIMM = 0x080, + FUNC = 0x100, +}; + +#define OP_MASK 0x2f +#define OP_SH 26 +#define RS_MASK 0x1f +#define RS_SH 21 +#define RT_MASK 0x1f +#define RT_SH 16 +#define RD_MASK 0x1f +#define RD_SH 11 +#define RE_MASK 0x1f +#define RE_SH 6 +#define IMM_MASK 0xffff +#define IMM_SH 0 +#define JIMM_MASK 0x3ffffff +#define JIMM_SH 0 +#define FUNC_MASK 0x2f +#define FUNC_SH 0 + +enum opcode { + insn_invalid, + insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, + insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, insn_bne, + insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, + insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, + insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, + insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_ori, insn_rfe, + insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, + insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori +}; + +struct insn { + enum opcode opcode; + u32 match; + enum fields fields; +}; + +/* This macro sets the non-variable bits of an instruction. */ +#define M(a, b, c, d, e, f) \ + ((a) << OP_SH \ + | (b) << RS_SH \ + | (c) << RT_SH \ + | (d) << RD_SH \ + | (e) << RE_SH \ + | (f) << FUNC_SH) + +static __initdata struct insn insn_table[] = { + { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, + { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, + { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, + { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, + { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, + { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, + { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, + { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, + { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, + { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, + { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD }, + { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD }, + { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, + { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, + { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, + { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, + { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE }, + { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, + { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, + { insn_j, M(j_op,0,0,0,0,0), JIMM }, + { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, + { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, + { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, + { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD }, + { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD }, + { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, + { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, + { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, + { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, + { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, + { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, + { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, + { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, + { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, + { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, + { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, + { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, + { insn_invalid, 0, 0 } +}; + +#undef M + +static __init u32 build_rs(u32 arg) +{ + if (arg & ~RS_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return (arg & RS_MASK) << RS_SH; +} + +static __init u32 build_rt(u32 arg) +{ + if (arg & ~RT_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return (arg & RT_MASK) << RT_SH; +} + +static __init u32 build_rd(u32 arg) +{ + if (arg & ~RD_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return (arg & RD_MASK) << RD_SH; +} + +static __init u32 build_re(u32 arg) +{ + if (arg & ~RE_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return (arg & RE_MASK) << RE_SH; +} + +static __init u32 build_simm(s32 arg) +{ + if (arg > 0x7fff || arg < -0x8000) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return arg & 0xffff; +} + +static __init u32 build_uimm(u32 arg) +{ + if (arg & ~IMM_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return arg & IMM_MASK; +} + +static __init u32 build_bimm(s32 arg) +{ + if (arg > 0x1ffff || arg < -0x20000) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + if (arg & 0x3) + printk(KERN_WARNING "Invalid TLB synthesizer branch target\n"); + + return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); +} + +static __init u32 build_jimm(u32 arg) +{ + if (arg & ~((JIMM_MASK) << 2)) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return (arg >> 2) & JIMM_MASK; +} + +static __init u32 build_func(u32 arg) +{ + if (arg & ~FUNC_MASK) + printk(KERN_WARNING "TLB synthesizer field overflow\n"); + + return arg & FUNC_MASK; +} + +/* + * The order of opcode arguments is implicitly left to right, + * starting with RS and ending with FUNC or IMM. + */ +static void __init build_insn(u32 **buf, enum opcode opc, ...) +{ + struct insn *ip = NULL; + unsigned int i; + va_list ap; + u32 op; + + for (i = 0; insn_table[i].opcode != insn_invalid; i++) + if (insn_table[i].opcode == opc) { + ip = &insn_table[i]; + break; + } + + if (!ip) + panic("Unsupported TLB synthesizer instruction %d", opc); + + op = ip->match; + va_start(ap, opc); + if (ip->fields & RS) op |= build_rs(va_arg(ap, u32)); + if (ip->fields & RT) op |= build_rt(va_arg(ap, u32)); + if (ip->fields & RD) op |= build_rd(va_arg(ap, u32)); + if (ip->fields & RE) op |= build_re(va_arg(ap, u32)); + if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32)); + if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32)); + if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32)); + if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32)); + if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32)); + va_end(ap); + + **buf = op; + (*buf)++; +} + +#define I_u1u2u3(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b, unsigned int c) \ + { \ + build_insn(buf, insn##op, a, b, c); \ + } + +#define I_u2u1u3(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b, unsigned int c) \ + { \ + build_insn(buf, insn##op, b, a, c); \ + } + +#define I_u3u1u2(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b, unsigned int c) \ + { \ + build_insn(buf, insn##op, b, c, a); \ + } + +#define I_u1u2s3(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b, signed int c) \ + { \ + build_insn(buf, insn##op, a, b, c); \ + } + +#define I_u2s3u1(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + signed int b, unsigned int c) \ + { \ + build_insn(buf, insn##op, c, a, b); \ + } + +#define I_u2u1s3(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b, signed int c) \ + { \ + build_insn(buf, insn##op, b, a, c); \ + } + +#define I_u1u2(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + unsigned int b) \ + { \ + build_insn(buf, insn##op, a, b); \ + } + +#define I_u1s2(op) \ + static inline void i##op(u32 **buf, unsigned int a, \ + signed int b) \ + { \ + build_insn(buf, insn##op, a, b); \ + } + +#define I_u1(op) \ + static inline void i##op(u32 **buf, unsigned int a) \ + { \ + build_insn(buf, insn##op, a); \ + } + +#define I_0(op) \ + static inline void i##op(u32 **buf) \ + { \ + build_insn(buf, insn##op); \ + } + +I_u2u1s3(_addiu); +I_u3u1u2(_addu); +I_u2u1u3(_andi); +I_u3u1u2(_and); +I_u1u2s3(_beq); +I_u1s2(_bgez); +I_u1s2(_bgezl); +I_u1s2(_bltz); +I_u1s2(_bltzl); +I_u1u2s3(_bne); +I_u1u2(_dmfc0); +I_u1u2(_dmtc0); +I_u2u1s3(_daddiu); +I_u3u1u2(_daddu); +I_u2u1u3(_dsll); +I_u2u1u3(_dsll32); +I_u2u1u3(_dsra); +I_u2u1u3(_dsrl); +I_u2u1u3(_dsrl32); +I_u3u1u2(_dsubu); +I_0(_eret); +I_u1(_j); +I_u1(_jal); +I_u1(_jr); +I_u2s3u1(_ld); +I_u1s2(_lui); +I_u2s3u1(_lw); +I_u1u2(_mfc0); +I_u1u2(_mtc0); +I_u2u1u3(_ori); +I_0(_rfe); +I_u2s3u1(_sd); +I_u2u1u3(_sll); +I_u2u1u3(_sra); +I_u2u1u3(_srl); +I_u3u1u2(_subu); +I_u2s3u1(_sw); +I_0(_tlbp); +I_0(_tlbwi); +I_0(_tlbwr); +I_u3u1u2(_xor) +I_u2u1u3(_xori); + +/* + * handling labels + */ + +enum label_id { + label_invalid, + label_second_part, + label_leave, + label_vmalloc, + label_vmalloc_done, + label_tlbwr_hazard, + label_split +}; + +struct label { + u32 *addr; + enum label_id lab; +}; + +static __init void build_label(struct label **lab, u32 *addr, + enum label_id l) +{ + (*lab)->addr = addr; + (*lab)->lab = l; + (*lab)++; +} + +#define L_LA(lb) \ + static inline void l##lb(struct label **lab, u32 *addr) \ + { \ + build_label(lab, addr, label##lb); \ + } + +L_LA(_second_part) +L_LA(_leave) +L_LA(_vmalloc) +L_LA(_vmalloc_done) +L_LA(_tlbwr_hazard) +L_LA(_split) + +/* convenience macros for instructions */ +#ifdef CONFIG_MIPS64 +# define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) +# define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) +# define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) +# define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh) +# define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh) +# define i_MFC0(buf, rt, rd) i_dmfc0(buf, rt, rd) +# define i_MTC0(buf, rt, rd) i_dmtc0(buf, rt, rd) +# define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val) +# define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd) +# define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd) +#else +# define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off) +# define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off) +# define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh) +# define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh) +# define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh) +# define i_MFC0(buf, rt, rd) i_mfc0(buf, rt, rd) +# define i_MTC0(buf, rt, rd) i_mtc0(buf, rt, rd) +# define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val) +# define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd) +# define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd) +#endif + +#define i_b(buf, off) i_beq(buf, 0, 0, off) +#define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off) +#define i_move(buf, a, b) i_ADDU(buf, a, 0, b) +#define i_nop(buf) i_sll(buf, 0, 0, 0) +#define i_ssnop(buf) i_sll(buf, 0, 2, 1) + +#if CONFIG_MIPS64 +static __init int in_compat_space_p(long addr) +{ + /* Is this address in 32bit compat space? */ + return (((addr) & 0xffffffff00000000) == 0xffffffff00000000); +} + +static __init int rel_highest(long val) +{ + return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; +} + +static __init int rel_higher(long val) +{ + return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; +} +#endif + +static __init int rel_hi(long val) +{ + return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; +} + +static __init int rel_lo(long val) +{ + return ((val & 0xffff) ^ 0x8000) - 0x8000; +} + +static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) +{ +#if CONFIG_MIPS64 + if (!in_compat_space_p(addr)) { + i_lui(buf, rs, rel_highest(addr)); + if (rel_higher(addr)) + i_daddiu(buf, rs, rs, rel_higher(addr)); + if (rel_hi(addr)) { + i_dsll(buf, rs, rs, 16); + i_daddiu(buf, rs, rs, rel_hi(addr)); + i_dsll(buf, rs, rs, 16); + } else + i_dsll32(buf, rs, rs, 0); + } else +#endif + i_lui(buf, rs, rel_hi(addr)); +} + +static __init void i_LA(u32 **buf, unsigned int rs, long addr) +{ + i_LA_mostly(buf, rs, addr); + if (rel_lo(addr)) + i_ADDIU(buf, rs, rs, rel_lo(addr)); +} + +/* + * handle relocations + */ + +struct reloc { + u32 *addr; + unsigned int type; + enum label_id lab; +}; + +static __init void r_mips_pc16(struct reloc **rel, u32 *addr, + enum label_id l) +{ + (*rel)->addr = addr; + (*rel)->type = R_MIPS_PC16; + (*rel)->lab = l; + (*rel)++; +} + +static inline void __resolve_relocs(struct reloc *rel, struct label *lab) +{ + long laddr = (long)lab->addr; + long raddr = (long)rel->addr; + + switch (rel->type) { + case R_MIPS_PC16: + *rel->addr |= build_bimm(laddr - (raddr + 4)); + break; + + default: + panic("Unsupported TLB synthesizer relocation %d", + rel->type); + } +} + +static __init void resolve_relocs(struct reloc *rel, struct label *lab) +{ + struct label *l; + + for (; rel->lab != label_invalid; rel++) + for (l = lab; l->lab != label_invalid; l++) + if (rel->lab == l->lab) + __resolve_relocs(rel, l); +} + +static __init void copy_handler(struct reloc *rel, struct label *lab, + u32 *first, u32 *end, u32* target) +{ + long off = (long)(target - first); + + memcpy(target, first, (end - first) * sizeof(u32)); + + for (; rel->lab != label_invalid; rel++) + if (rel->addr >= first && rel->addr < end) + rel->addr += off; + + for (; lab->lab != label_invalid; lab++) + if (lab->addr >= first && lab->addr < end) + lab->addr += off; +} + +static __init int insn_has_bdelay(struct reloc *rel, u32 *addr) +{ + for (; rel->lab != label_invalid; rel++) { + if (rel->addr == addr + && (rel->type == R_MIPS_PC16 + || rel->type == R_MIPS_26)) + return 1; + } + + return 0; +} + +/* convenience functions for labeled branches */ +static void il_bltz(u32 **p, struct reloc **r, unsigned int reg, + enum label_id l) +{ + r_mips_pc16(r, *p, l); + i_bltz(p, reg, 0); +} + +static void il_b(u32 **p, struct reloc **r, enum label_id l) +{ + r_mips_pc16(r, *p, l); + i_b(p, 0); +} + +static void il_bnez(u32 **p, struct reloc **r, unsigned int reg, + enum label_id l) +{ + r_mips_pc16(r, *p, l); + i_bnez(p, reg, 0); +} + +static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg, + enum label_id l) +{ + r_mips_pc16(r, *p, l); + i_bgezl(p, reg, 0); +} + +/* The only registers allowed in TLB handlers. */ +#define K0 26 +#define K1 27 + +/* Some CP0 registers */ +#define C0_INDEX 0 +#define C0_ENTRYLO0 2 +#define C0_ENTRYLO1 3 +#define C0_CONTEXT 4 +#define C0_BADVADDR 8 +#define C0_ENTRYHI 10 +#define C0_EPC 14 +#define C0_XCONTEXT 20 + +#ifdef CONFIG_MIPS64 +# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) +#else +# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) +#endif + +/* The worst case length of the handler is around 18 instructions for + * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. + * Maximum space available is 32 instructions for R3000 and 64 + * instructions for R4000. + * + * We deliberately chose a buffer size of 128, so we won't scribble + * over anything important on overflow before we panic. + */ +static __initdata u32 tlb_handler[128]; + +/* simply assume worst case size for labels and relocs */ +static __initdata struct label labels[128]; +static __initdata struct reloc relocs[128]; + +#ifdef CONFIG_MIPS32 +/* + * The R3000 TLB handler is simple. + */ +static void __init build_r3000_tlb_refill_handler(void) +{ + long pgdc = (long)pgd_current; + u32 *p; + + memset(tlb_handler, 0, sizeof(tlb_handler)); + p = tlb_handler; + + i_mfc0(&p, K0, C0_BADVADDR); + i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */ + i_lw(&p, K1, rel_lo(pgdc), K1); + i_srl(&p, K0, K0, 22); /* load delay */ + i_sll(&p, K0, K0, 2); + i_addu(&p, K1, K1, K0); + i_mfc0(&p, K0, C0_CONTEXT); + i_lw(&p, K1, 0, K1); + i_andi(&p, K0, K0, 0xffc); /* load delay */ + i_addu(&p, K1, K1, K0); + i_lw(&p, K0, 0, K1); + i_nop(&p); /* load delay */ + i_mtc0(&p, K0, C0_ENTRYLO0); + i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ + i_tlbwr(&p); /* cp0 delay */ + i_jr(&p, K1); /* cp0 delay */ + i_rfe(&p); /* branch delay */ + + if (p > tlb_handler + 32) + panic("TLB refill handler space exceeded"); + + printk("Synthesized TLB handler (%u instructions).\n", + p - tlb_handler); +#ifdef DEBUG_TLB + { + int i; + for (i = 0; i < (p - tlb_handler); i++) + printk("%08x\n", tlb_handler[i]); + } +#endif + + memcpy((void *)CAC_BASE, tlb_handler, 0x80); + flush_icache_range(CAC_BASE, CAC_BASE + 0x80); +} +#endif /* CONFIG_MIPS32 */ + +/* + * The R4000 TLB handler is much more complicated. We have two + * consecutive handler areas with 32 instructions space each. + * Since they aren't used at the same time, we can overflow in the + * other one.To keep things simple, we first assume linear space, + * then we relocate it to the final handler layout as needed. + */ +static __initdata u32 final_handler[64]; + +/* + * Hazards + * + * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: + * 2. A timing hazard exists for the TLBP instruction. + * + * stalling_instruction + * TLBP + * + * The JTLB is being read for the TLBP throughout the stall generated by the + * previous instruction. This is not really correct as the stalling instruction + * can modify the address used to access the JTLB. The failure symptom is that + * the TLBP instruction will use an address created for the stalling instruction + * and not the address held in C0_ENHI and thus report the wrong results. + * + * The software work-around is to not allow the instruction preceding the TLBP + * to stall - make it an NOP or some other instruction guaranteed not to stall. + * + * Errata 2 will not be fixed. This errata is also on the R5000. + * + * As if we MIPS hackers wouldn't know how to nop pipelines happy ... + */ +static __init void build_tlbp_hazard(u32 **p) +{ + switch (current_cpu_data.cputype) { + case CPU_R5000: + case CPU_R5000A: + case CPU_NEVADA: + i_nop(p); + break; + + default: + break; + } +} + +/* + * Write random TLB entry, and care about the hazards from the + * preceeding mtc0 and for the following eret. + */ +static __init void build_tlb_write_random_entry(u32 **p, struct label **l, + struct reloc **r) +{ + switch (current_cpu_data.cputype) { + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + /* + * This branch uses up a mtc0 hazard nop slot and saves + * two nops after the tlbwr. + */ + il_bgezl(p, r, 0, label_tlbwr_hazard); + i_tlbwr(p); + l_tlbwr_hazard(l, *p); + i_nop(p); + break; + + case CPU_R4600: + case CPU_R4700: + i_nop(p); + i_tlbwr(p); + break; + + case CPU_NEVADA: + i_nop(p); /* QED specifies 2 nops hazard */ + /* + * This branch uses up a mtc0 hazard nop slot and saves + * a nop after the tlbwr. + */ + il_bgezl(p, r, 0, label_tlbwr_hazard); + i_tlbwr(p); + l_tlbwr_hazard(l, *p); + break; + + case CPU_RM9000: + /* + * When the JTLB is updated by tlbwi or tlbwr, a subsequent + * use of the JTLB for instructions should not occur for 4 + * cpu cycles and use for data translations should not occur + * for 3 cpu cycles. + */ + i_ssnop(p); + i_ssnop(p); + i_ssnop(p); + i_ssnop(p); + i_tlbwr(p); + i_ssnop(p); + i_ssnop(p); + i_ssnop(p); + i_ssnop(p); + break; + + case CPU_R10000: + case CPU_R12000: + case CPU_SB1: + i_tlbwr(p); + break; + + default: + /* + * Others are assumed to have one cycle mtc0 hazard, + * and one cycle tlbwr hazard. + * XXX: This might be overly general. + */ + i_nop(p); + i_tlbwr(p); + i_nop(p); + break; + } +} + +#if CONFIG_MIPS64 +/* + * TMP and PTR are scratch. + * TMP will be clobbered, PTR will hold the pmd entry. + */ +static __init void +build_get_pmde64(u32 **p, struct label **l, struct reloc **r, + unsigned int tmp, unsigned int ptr) +{ + long pgdc = (long)pgd_current; + + /* + * The vmalloc handling is not in the hotpath. + */ + i_dmfc0(p, tmp, C0_BADVADDR); + il_bltz(p, r, tmp, label_vmalloc); + /* No i_nop needed here, since the next insn doesn't touch TMP. */ + +# ifdef CONFIG_SMP + /* + * 64 bit SMP has the lower part of &pgd_current[smp_processor_id()] + * stored in CONTEXT. + */ + if (in_compat_space_p(pgdc)) { + i_dmfc0(p, ptr, C0_CONTEXT); + i_dsra(p, ptr, ptr, 23); + } else { + i_dmfc0(p, ptr, C0_CONTEXT); + i_lui(p, tmp, rel_highest(pgdc)); + i_dsll(p, ptr, ptr, 9); + i_daddiu(p, tmp, tmp, rel_higher(pgdc)); + i_dsrl32(p, ptr, ptr, 0); + i_and(p, ptr, ptr, tmp); + i_dmfc0(p, tmp, C0_BADVADDR); + } + i_ld(p, ptr, 0, ptr); +# else + i_LA_mostly(p, ptr, pgdc); + i_ld(p, ptr, rel_lo(pgdc), ptr); +# endif + + l_vmalloc_done(l, *p); + i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */ + i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); + i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ + i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + i_ld(p, ptr, 0, ptr); /* get pmd pointer */ + i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ + i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); + i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ +} + +/* + * BVADDR is the faulting address, PTR is scratch. + * PTR will hold the pgd for vmalloc. + */ +static __init void +build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, + unsigned int bvaddr, unsigned int ptr) +{ + long swpd = (long)swapper_pg_dir; + + l_vmalloc(l, *p); + i_LA(p, ptr, VMALLOC_START); + i_dsubu(p, bvaddr, bvaddr, ptr); + + if (in_compat_space_p(swpd) && !rel_lo(swpd)) { + il_b(p, r, label_vmalloc_done); + i_lui(p, ptr, rel_hi(swpd)); + } else { + i_LA_mostly(p, ptr, swpd); + il_b(p, r, label_vmalloc_done); + i_daddiu(p, ptr, ptr, rel_lo(swpd)); + } +} + +#else /* CONFIG_MIPS32 */ + +/* + * TMP and PTR are scratch. + * TMP will be clobbered, PTR will hold the pgd entry. + */ +static __init void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) +{ + long pgdc = (long)pgd_current; + + /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ +#ifdef CONFIG_SMP + i_mfc0(p, ptr, C0_CONTEXT); + i_LA_mostly(p, tmp, pgdc); + i_srl(p, ptr, ptr, 23); + i_sll(p, ptr, ptr, 2); + i_addu(p, ptr, tmp, ptr); +#else + i_LA_mostly(p, ptr, pgdc); +#endif + i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + i_lw(p, ptr, rel_lo(pgdc), ptr); + i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ + i_sll(p, tmp, tmp, PGD_T_LOG2); + i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ +} +#endif /* CONFIG_MIPS32 */ + +static __init void build_adjust_context(u32 **p, unsigned int ctx) +{ + unsigned int shift = 0; + unsigned int mask = 0xff0; + +#if !defined(CONFIG_MIPS64) && !defined(CONFIG_64BIT_PHYS_ADDR) + shift++; + mask |= 0x008; +#endif + + switch (current_cpu_data.cputype) { + case CPU_VR41XX: + case CPU_VR4111: + case CPU_VR4121: + case CPU_VR4122: + case CPU_VR4131: + case CPU_VR4181: + case CPU_VR4181A: + case CPU_VR4133: + shift += 2; + break; + + default: + break; + } + + if (shift) + i_SRL(p, ctx, ctx, shift); + i_andi(p, ctx, ctx, mask); +} + +static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) +{ + /* + * Bug workaround for the Nevada. It seems as if under certain + * circumstances the move from cp0_context might produce a + * bogus result when the mfc0 instruction and its consumer are + * in a different cacheline or a load instruction, probably any + * memory reference, is between them. + */ + switch (current_cpu_data.cputype) { + case CPU_NEVADA: + i_LW(p, ptr, 0, ptr); + GET_CONTEXT(p, tmp); /* get context reg */ + break; + + default: + GET_CONTEXT(p, tmp); /* get context reg */ + i_LW(p, ptr, 0, ptr); + break; + } + + build_adjust_context(p, tmp); + i_ADDU(p, ptr, ptr, tmp); /* add in offset */ +} + +static __init void build_update_entries(u32 **p, unsigned int tmp, + unsigned int ptep) +{ + /* + * 64bit address support (36bit on a 32bit CPU) in a 32bit + * Kernel is a special case. Only a few CPUs use it. + */ +#ifdef CONFIG_64BIT_PHYS_ADDR + if (cpu_has_64bit_registers) { + i_ld(p, tmp, 0, ptep); /* get even pte */ + i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ + i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ + i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ + i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ + } else { + int pte_off_even = sizeof(pte_t) / 2; + int pte_off_odd = pte_off_even + sizeof(pte_t); + + /* The pte entries are pre-shifted */ + i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ + i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ + i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ + } +#else + i_LW(p, tmp, 0, ptep); /* get even pte */ + i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ + if (r45k_bvahwbug()) { + build_tlbp_hazard(p); + i_tlbp(p); + } + i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ + if (r4k_250MHZhwbug()) + i_mtc0(p, 0, C0_ENTRYLO0); + i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ + if (r45k_bvahwbug()) + i_mfc0(p, tmp, C0_INDEX); + if (r4k_250MHZhwbug()) + i_mtc0(p, 0, C0_ENTRYLO1); + i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ +#endif +} + +static void __init build_r4000_tlb_refill_handler(void) +{ + u32 *p = tlb_handler; + struct label *l = labels; + struct reloc *r = relocs; + u32 *f; + unsigned int final_len; + + memset(tlb_handler, 0, sizeof(tlb_handler)); + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + memset(final_handler, 0, sizeof(final_handler)); + + /* + * create the plain linear handler + */ + if (bcm1250_m3_war) { + i_MFC0(&p, K0, C0_BADVADDR); + i_MFC0(&p, K1, C0_ENTRYHI); + i_xor(&p, K0, K0, K1); + i_SRL(&p, K0, K0, PAGE_SHIFT+1); + il_bnez(&p, &r, K0, label_leave); + /* No need for i_nop */ + } + +#ifdef CONFIG_MIPS64 + build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd ptr in K1 */ +#else + build_get_pgde32(&p, K0, K1); /* get pgd ptr in K1 */ +#endif + + build_get_ptep(&p, K0, K1); + build_update_entries(&p, K0, K1); + build_tlb_write_random_entry(&p, &l, &r); + l_leave(&l, p); + i_eret(&p); /* return from trap */ + +#ifdef CONFIG_MIPS64 + build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); +#endif + + /* + * Overflow check: For the 64bit handler, we need at least one + * free instruction slot for the wrap-around branch. In worst + * case, if the intended insertion point is a delay slot, we + * need three, with the the second nop'ed and the third being + * unused. + */ +#ifdef CONFIG_MIPS32 + if ((p - tlb_handler) > 64) + panic("TLB refill handler space exceeded"); +#else + if (((p - tlb_handler) > 63) + || (((p - tlb_handler) > 61) + && insn_has_bdelay(relocs, tlb_handler + 29))) + panic("TLB refill handler space exceeded"); +#endif + + /* + * Now fold the handler in the TLB refill handler space. + */ +#ifdef CONFIG_MIPS32 + f = final_handler; + /* Simplest case, just copy the handler. */ + copy_handler(relocs, labels, tlb_handler, p, f); + final_len = p - tlb_handler; +#else /* CONFIG_MIPS64 */ + f = final_handler + 32; + if ((p - tlb_handler) <= 32) { + /* Just copy the handler. */ + copy_handler(relocs, labels, tlb_handler, p, f); + final_len = p - tlb_handler; + } else { + u32 *split = tlb_handler + 30; + + /* + * Find the split point. + */ + if (insn_has_bdelay(relocs, split - 1)) + split--; + + /* Copy first part of the handler. */ + copy_handler(relocs, labels, tlb_handler, split, f); + f += split - tlb_handler; + + /* Insert branch. */ + l_split(&l, final_handler); + il_b(&f, &r, label_split); + if (insn_has_bdelay(relocs, split)) + i_nop(&f); + else { + copy_handler(relocs, labels, split, split + 1, f); + f++; + split++; + } + + /* Copy the rest of the handler. */ + copy_handler(relocs, labels, split, p, final_handler); + final_len = (f - (final_handler + 32)) + (p - split); + } +#endif /* CONFIG_MIPS64 */ + + resolve_relocs(relocs, labels); + printk("Synthesized TLB handler (%u instructions).\n", final_len); + +#ifdef DEBUG_TLB + { + int i; + + for (i = 0; i < 64; i++) + printk("%08x\n", final_handler[i]); + } +#endif + + memcpy((void *)CAC_BASE, final_handler, 0x100); + flush_icache_range(CAC_BASE, CAC_BASE + 0x100); +} + +void __init build_tlb_refill_handler(void) +{ + switch (current_cpu_data.cputype) { +#ifdef CONFIG_MIPS32 + case CPU_R2000: + case CPU_R3000: + case CPU_R3000A: + case CPU_R3081E: + case CPU_TX3912: + case CPU_TX3922: + case CPU_TX3927: + build_r3000_tlb_refill_handler(); + break; + + case CPU_R6000: + case CPU_R6000A: + panic("No R6000 TLB refill handler yet"); + break; +#endif + + case CPU_R8000: + panic("No R8000 TLB refill handler yet"); + break; + + default: + build_r4000_tlb_refill_handler(); + } +} --- arch/mips/mm/tlbex64-r4k.S 2004-11-21 03:05:35.000000000 +0100 +++ /dev/null 2004-08-24 19:23:08.000000000 +0200 @@ -1,136 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Written by Ulf Carlsson (ulfc@engr.sgi.com) - * Copyright (C) 2002 Maciej W. Rozycki - */ -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define _VMALLOC_START 0xc000000000000000 - - .macro GET_PGD, ptr -#ifdef CONFIG_SMP - /* - * Fixme - this is b0rked for pgd_current outside of CKSEG0 - */ - dmfc0 \ptr, CP0_CONTEXT - dsra \ptr, 23 # get pgd_current[cpu] - ld \ptr, (\ptr) -#else - ld \ptr, pgd_current -#endif - .endm - - /* - * After this macro runs we have a pointer to the pte of the address - * that caused the fault in PTR. Expects register containing the - * the pagetable root pointer as the ptr argument and c0_badvaddr - * passed as tmp argument. - */ - .macro LOAD_PTE2, ptr, tmp - dsrl \tmp, (_PGDIR_SHIFT-3) # get pgd offset in bytes - andi \tmp, ((_PTRS_PER_PGD - 1)<<3) - daddu \ptr, \tmp # add in pgd offset - dmfc0 \tmp, CP0_BADVADDR - ld \ptr, (\ptr) # get pmd pointer - dsrl \tmp, (_PMD_SHIFT-3) # get pmd offset in bytes - andi \tmp, ((_PTRS_PER_PMD - 1)<<3) - daddu \ptr, \tmp # add in pmd offset - dmfc0 \tmp, CP0_XCONTEXT - ld \ptr, (\ptr) # get pte pointer - andi \tmp, 0xff0 # get pte offset - daddu \ptr, \tmp - .endm - - /* - * This places the even/odd pte pair in the page table at the pte - * entry pointed to by PTE into ENTRYLO0 and ENTRYLO1. - */ - .macro PTE_RELOAD, pte0, pte1 - dsrl \pte0, 6 # convert to entrylo0 - dmtc0 \pte0, CP0_ENTRYLO0 # load it - dsrl \pte1, 6 # convert to entrylo1 - dmtc0 \pte1, CP0_ENTRYLO1 # load it - .endm - - - .text - .set noreorder - .set mips3 - - __INIT - - /* - * TLB refill handlers for the R4000 and SB1. - * Attention: We may only use 32 instructions / 128 bytes. - */ - .align 5 -LEAF(except_vec1_r4k) - .set noat - dla k0, handle_vec1_r4k - jr k0 - nop -END(except_vec1_r4k) - -LEAF(except_vec1_sb1) -#if BCM1250_M3_WAR - dmfc0 k0, CP0_BADVADDR - dmfc0 k1, CP0_ENTRYHI - xor k0, k1 - dsrl k0, k0, _PAGE_SHIFT+1 - bnez k0, 1f -#endif - .set noat - dla k0, handle_vec1_r4k - jr k0 - nop - -1: eret - nop -END(except_vec1_sb1) - - __FINIT - - .align 5 -LEAF(handle_vec1_r4k) - .set noat - dmfc0 k0, CP0_BADVADDR - bltz k0, 9f - - GET_PGD k1 # pointer to root of pgd - LOAD_PTE2 k1 k0 - ld k0, 0(k1) # get even pte - ld k1, 8(k1) # get odd pte - PTE_RELOAD k0 k1 - mtc0_tlbw_hazard - tlbwr - nop - tlbw_eret_hazard - eret - -9: # handle the vmalloc range - dli k1, _VMALLOC_START - dsubu k0, k1 - dla k1, swapper_pg_dir # pointer to root of pgd - LOAD_PTE2 k1 k0 - ld k0, 0(k1) # get even pte - ld k1, 8(k1) # get odd pte - PTE_RELOAD k0 k1 - mtc0_tlbw_hazard - tlbwr - nop - tlbw_eret_hazard - eret -END(handle_vec1_r4k) From ralf@linux-mips.org Sun Nov 21 20:45:11 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Nov 2004 20:45:15 +0000 (GMT) Received: from p508B7F2C.dip.t-dialin.net ([IPv6:::ffff:80.139.127.44]:62495 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Sun, 21 Nov 2004 20:45:11 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iALKh0Rn012865; Sun, 21 Nov 2004 21:43:00 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iALKh0Gx012864; Sun, 21 Nov 2004 21:43:00 +0100 Date: Sun, 21 Nov 2004 21:43:00 +0100 From: Ralf Baechle To: Geert Uytterhoeven Cc: Thiemo Seufer , Linux/MIPS Development Subject: Re: [PATCH] Synthesize TLB refill handler at runtime Message-ID: <20041121204300.GA12664@linux-mips.org> References: <20041121170242.GR20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6391 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 835 Lines: 19 On Sun, Nov 21, 2004 at 08:50:30PM +0100, Geert Uytterhoeven wrote: > On Sun, 21 Nov 2004, Thiemo Seufer wrote: > > currently we have a large number of TLB refill handlers written in > > hand-optimized assembly which are mostly indentical. The appended > > patch removes them all, and adds a micro-assembler instead which > > synthesizes the proper variant for the CPU at runtime. > > Woow..... This has been the plan for quite a while already. Nowhere else than in the TLB exception handler more details about exception handling, pipeline structure, SMP etc. become visible and benchmarkable in that few instructions. Copy_page / clear_page have basically been a test how well it'd work out - it did. So from that point it was just a question of who was going to bite the bullet and do the work and Thiemo did. Thanks! Ralf From madprops@gmx.net Mon Nov 22 01:25:12 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2004 01:25:25 +0000 (GMT) Received: from pop.gmx.net ([IPv6:::ffff:213.165.64.20]:58537 "HELO mail.gmx.net") by linux-mips.org with SMTP id ; Mon, 22 Nov 2004 01:25:12 +0000 Received: (qmail 8825 invoked by uid 0); 22 Nov 2004 01:25:06 -0000 Received: from 69.193.111.169 by www8.gmx.net with HTTP; Mon, 22 Nov 2004 02:25:06 +0100 (MET) Date: Mon, 22 Nov 2004 02:25:06 +0100 (MET) From: "Mad Props" To: linux-mips@linux-mips.org MIME-Version: 1.0 Subject: beginners question X-Priority: 3 (Normal) X-Authenticated: #24801140 Message-ID: <8709.1101086706@www8.gmx.net> X-Mailer: WWW-Mail 1.6 (Global Message Exchange) X-Flags: 0001 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6392 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: madprops@gmx.net Precedence: bulk X-list: linux-mips Content-Length: 572 Lines: 18 Hi, i wrote a little MIPS startup code that uses the serial port to print some output. Further I enabled timer interrupts. So far, I'm using kseg1 since nothing else is intialized. I have a static variable in my C exception hander. The problem with it: it's apparently not within kseg1 but in the user segment and causes the exception handler to get invoked recursively. How can I change this so that all variables / code use kseg1 ? thx Thomas -- Geschenkt: 3 Monate GMX ProMail + 3 Top-Spielfilme auf DVD ++ Jetzt kostenlos testen http://www.gmx.net/de/go/mail ++ From Thomas.Koeller@baslerweb.com Mon Nov 22 06:16:24 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2004 06:16:29 +0000 (GMT) Received: from mail.baslerweb.com ([IPv6:::ffff:145.253.187.130]:41675 "EHLO mail.baslerweb.com") by linux-mips.org with ESMTP id ; Mon, 22 Nov 2004 06:16:24 +0000 Received: (from mail@localhost) by mail.baslerweb.com (8.12.10/8.12.10) id iAM6E4HN012332 for ; Mon, 22 Nov 2004 07:14:04 +0100 Received: from unknown by gateway id /var/KryptoWall/smtpp/kwL0JuON; Mon Nov 22 07:13:05 2004 From: Thomas Koeller Organization: Basler AG To: Manish Lachwani Subject: titan code question Date: Fri, 19 Nov 2004 16:23:14 +0100 User-Agent: KMail/1.6.2 Cc: linux-mips@linux-mips.org MIME-Version: 1.0 X-KMail-Identity: 87982748 Message-Id: <200411191623.14760.thomas.koeller@baslerweb.com> X-KMail-EncryptionState: N X-KMail-SignatureState: N X-KMail-MDN-Sent: Content-Disposition: inline Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6393 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: thomas.koeller@baslerweb.com Precedence: bulk X-list: linux-mips Status: RO Content-Length: 1277 Lines: 48 Hi Manish & Ralf, the code below is from tian_ge.c: /* * This is the 1.2 revision of the chip. It has fix for the * IP header alignment. Now, the IP header begins at an * aligned address and this wont need an extra copy in the * driver. This performance drawback existed in the previous * versions of the silicon */ reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12)); reg_data_1 |= 0x40000000; TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); reg_data_1 |= 0x04000000; TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); mdelay(5); reg_data_1 &= ~(0x04000000); TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); mdelay(5); According to the RM9000 user manual, register 0x103c (and 0x203c and 0x303c), named TTPRI0, contains eight four-bit fields, each of which is a packet priority value. This would be used to find the priority for incoming packets. Given the register description in the cpu manual, I cannot make any sense of the code above. Whoever did that, would you care to explain? thanks, Thomas -- -------------------------------------------------- Thomas Koeller, Software Development Basler Vision Technologies thomas dot koeller at baslerweb dot com http://www.baslerweb.com ============================== From ralf@linux-mips.org Mon Nov 22 06:20:55 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2004 06:21:02 +0000 (GMT) Received: from p508B767E.dip.t-dialin.net ([IPv6:::ffff:80.139.118.126]:1577 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Mon, 22 Nov 2004 06:20:55 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAM6Isbu025583; Mon, 22 Nov 2004 07:18:54 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAM6IsF4025582; Mon, 22 Nov 2004 07:18:54 +0100 Date: Mon, 22 Nov 2004 07:18:54 +0100 From: Ralf Baechle To: Thiemo Seufer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Improve o32 syscall handling Message-ID: <20041122061854.GA25433@linux-mips.org> References: <20041121164557.GQ20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041121164557.GQ20986@rembrandt.csv.ica.uni-stuttgart.de> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6394 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 510 Lines: 18 On Sun, Nov 21, 2004 at 05:45:57PM +0100, Thiemo Seufer wrote: > For the 64bit Kernel, it > - checks for unaligned user stack Why bother, the unaligned exception handler should take care of this. > - also allows now up to 8 arguments Quite frankly I'd prefer to see this being handle in userspace. For o32 it's too late to go for that but for N32 / N64 we still may have a chance. > - LONG_L a2, TI_FLAGS($28) # current->work > + lw a2, TI_FLAGS($28) # current->work Flags is a long variable. Ralf From ica2_ts@csv.ica.uni-stuttgart.de Mon Nov 22 07:00:08 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2004 07:00:17 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:49432 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Mon, 22 Nov 2004 07:00:08 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CW8BD-00011a-00; Mon, 22 Nov 2004 08:00:07 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CW8BB-0001Mo-00; Mon, 22 Nov 2004 08:00:05 +0100 Date: Mon, 22 Nov 2004 08:00:04 +0100 To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Improve o32 syscall handling Message-ID: <20041122070003.GA902@rembrandt.csv.ica.uni-stuttgart.de> References: <20041121164557.GQ20986@rembrandt.csv.ica.uni-stuttgart.de> <20041122061854.GA25433@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041122061854.GA25433@linux-mips.org> User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6395 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 1088 Lines: 32 Ralf Baechle wrote: > On Sun, Nov 21, 2004 at 05:45:57PM +0100, Thiemo Seufer wrote: > > > For the 64bit Kernel, it > > - checks for unaligned user stack > > Why bother, the unaligned exception handler should take care of this. It really does so for unaligned accesses from kernel space? > > - also allows now up to 8 arguments > > Quite frankly I'd prefer to see this being handle in userspace. For o32 > it's too late to go for that but for N32 / N64 we still may have a chance. My changes are for O32 only. N32/N64 doesn't need more than 6 arguments. > > - LONG_L a2, TI_FLAGS($28) # current->work > > + lw a2, TI_FLAGS($28) # current->work > > Flags is a long variable. "long" isn't a quantity the assembler knows about. :-) The whole assembler file for O32 support in 32bit Kernels makes only sense when it is compiled as 32bit code. In that case, the C "long" has 4 bytes and is loaded with lw. Using a macro which abstracts for 32/64bit compilation hides this needlessly, and can even lead to the erraneous impression the code would be useful for 64bit, too. Thiemo From ralf@linux-mips.org Mon Nov 22 07:03:20 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2004 07:03:24 +0000 (GMT) Received: from p508B767E.dip.t-dialin.net ([IPv6:::ffff:80.139.118.126]:42793 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Mon, 22 Nov 2004 07:03:20 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAM71HJj026579; Mon, 22 Nov 2004 08:01:17 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAM71H0H026578; Mon, 22 Nov 2004 08:01:17 +0100 Date: Mon, 22 Nov 2004 08:01:17 +0100 From: Ralf Baechle To: Thiemo Seufer Cc: Geert Uytterhoeven , Linux/MIPS Development Subject: Re: [PATCH] Synthesize TLB refill handler at runtime Message-ID: <20041122070117.GB25433@linux-mips.org> References: <20041121170242.GR20986@rembrandt.csv.ica.uni-stuttgart.de> <20041121203757.GS20986@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041121203757.GS20986@rembrandt.csv.ica.uni-stuttgart.de> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6396 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 249 Lines: 11 On Sun, Nov 21, 2004 at 09:37:57PM +0100, Thiemo Seufer wrote: > Aww, fatal error in the spelling module. :-) > Updated. The patch was looking good, so I gave it a shot on one of my machines also and it was working fine, applied. Thanks! Ralf From ralf@linux-mips.org Mon Nov 22 07:15:14 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2004 07:15:19 +0000 (GMT) Received: from p508B767E.dip.t-dialin.net ([IPv6:::ffff:80.139.118.126]:53033 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Mon, 22 Nov 2004 07:15:14 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAM7DDl6026842; Mon, 22 Nov 2004 08:13:13 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAM7DDsa026841; Mon, 22 Nov 2004 08:13:13 +0100 Date: Mon, 22 Nov 2004 08:13:13 +0100 From: Ralf Baechle To: Thiemo Seufer Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Improve o32 syscall handling Message-ID: <20041122071313.GC25433@linux-mips.org> References: <20041121164557.GQ20986@rembrandt.csv.ica.uni-stuttgart.de> <20041122061854.GA25433@linux-mips.org> <20041122070003.GA902@rembrandt.csv.ica.uni-stuttgart.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041122070003.GA902@rembrandt.csv.ica.uni-stuttgart.de> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6397 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1106 Lines: 25 On Mon, Nov 22, 2004 at 08:00:04AM +0100, Thiemo Seufer wrote: > > Why bother, the unaligned exception handler should take care of this. > > It really does so for unaligned accesses from kernel space? Yes. In fact it's crucially important for this very case. TCP for example may result in missalignment. And not everybody is using get_unaligned / put_unaligned as they were intended. Relying on the unaligned handler is preferable where we expect pointers to be properly aligned almost always. The MIPS ABI mandates at least 8 byte stack alignment and funny things happen if that assumption is violated. So there is no motivation at all to care about the performance of missalignment. Aside of me defining this to be verboten by punishment of signal 9 ;-) > has 4 bytes and is loaded with lw. Using a macro which abstracts for > 32/64bit compilation hides this needlessly, and can even lead to the > erraneous impression the code would be useful for 64bit, too. I'm more following the religion of using such abstractions everywhere because code tends to be copied around mindlessly ... Ralf From ica2_ts@csv.ica.uni-stuttgart.de Mon Nov 22 09:37:15 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2004 09:37:19 +0000 (GMT) Received: from iris1.csv.ica.uni-stuttgart.de ([IPv6:::ffff:129.69.118.2]:5147 "EHLO iris1.csv.ica.uni-stuttgart.de") by linux-mips.org with ESMTP id ; Mon, 22 Nov 2004 09:37:15 +0000 Received: from rembrandt.csv.ica.uni-stuttgart.de ([129.69.118.42]) by iris1.csv.ica.uni-stuttgart.de with esmtp id 1CWAdG-0002Qj-00; Mon, 22 Nov 2004 10:37:14 +0100 Received: from ica2_ts by rembrandt.csv.ica.uni-stuttgart.de with local (Exim 3.35 #1 (Debian)) id 1CWAdG-0001rz-00; Mon, 22 Nov 2004 10:37:14 +0100 Date: Mon, 22 Nov 2004 10:37:14 +0100 To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Improve o32 syscall handling Message-ID: <20041122093714.GC902@rembrandt.csv.ica.uni-stuttgart.de> References: <20041121164557.GQ20986@rembrandt.csv.ica.uni-stuttgart.de> <20041122061854.GA25433@linux-mips.org> <20041122070003.GA902@rembrandt.csv.ica.uni-stuttgart.de> <20041122071313.GC25433@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20041122071313.GC25433@linux-mips.org> User-Agent: Mutt/1.5.6i From: Thiemo Seufer Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6398 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ica2_ts@csv.ica.uni-stuttgart.de Precedence: bulk X-list: linux-mips Content-Length: 978 Lines: 27 Ralf Baechle wrote: > On Mon, Nov 22, 2004 at 08:00:04AM +0100, Thiemo Seufer wrote: > > > > Why bother, the unaligned exception handler should take care of this. > > > > It really does so for unaligned accesses from kernel space? > > Yes. In fact it's crucially important for this very case. Ok, I'll update the patch accordingly when I'm back to better connectivity than I have now. [snip] > > has 4 bytes and is loaded with lw. Using a macro which abstracts for > > 32/64bit compilation hides this needlessly, and can even lead to the > > erraneous impression the code would be useful for 64bit, too. > > I'm more following the religion of using such abstractions everywhere > because code tends to be copied around mindlessly ... I would agree if there was a roughly similiar 64bit version of the code. But due to the differences between 32bit and 64bit kernel there will never be one, so it's IMHO best to make them as distinct as reasonable in this case. Thiemo From macro@linux-mips.org Mon Nov 22 14:37:43 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2004 14:37:47 +0000 (GMT) Received: from pollux.ds.pg.gda.pl ([IPv6:::ffff:153.19.208.7]:45575 "EHLO pollux.ds.pg.gda.pl") by linux-mips.org with ESMTP id ; Mon, 22 Nov 2004 14:37:43 +0000 Received: from localhost (localhost [127.0.0.1]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id E59B0F596A; Mon, 22 Nov 2004 15:37:36 +0100 (CET) Received: from pollux.ds.pg.gda.pl ([127.0.0.1]) by localhost (pollux [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 30888-10; Mon, 22 Nov 2004 15:37:36 +0100 (CET) Received: from piorun.ds.pg.gda.pl (piorun.ds.pg.gda.pl [153.19.208.8]) by pollux.ds.pg.gda.pl (Postfix) with ESMTP id 6491FE1C79; Mon, 22 Nov 2004 15:37:36 +0100 (CET) Received: from blysk.ds.pg.gda.pl (macro@blysk.ds.pg.gda.pl [153.19.208.6]) by piorun.ds.pg.gda.pl (8.13.1/8.13.1) with ESMTP id iAMEbkdl004476; Mon, 22 Nov 2004 15:37:46 +0100 Date: Mon, 22 Nov 2004 14:37:38 +0000 (GMT) From: "Maciej W. Rozycki" To: Thiemo Seufer Cc: Geert Uytterhoeven , Linux/MIPS Development , Ralf Baechle Subject: Re: [PATCH] Synthesize TLB refill handler at runtime In-Reply-To: <20041121203757.GS20986@rembrandt.csv.ica.uni-stuttgart.de> Message-ID: References: <20041121170242.GR20986@rembrandt.csv.ica.uni-stuttgart.de> <20041121203757.GS20986@rembrandt.csv.ica.uni-stuttgart.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: ClamAV 0.80/590/Wed Nov 17 22:03:52 2004 clamav-milter version 0.80j on piorun.ds.pg.gda.pl X-Virus-Status: Clean X-Virus-Scanned: by amavisd-new at pollux.ds.pg.gda.pl Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 6399 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 616 Lines: 17 On Sun, 21 Nov 2004, Thiemo Seufer wrote: > Aww, fatal error in the spelling module. :-) > Updated. Great stuff! Thanks a lot. I gave it some testing on hardware available to me and it works just fine. I've got a couple of warnings upon building, though: arch/mips/mm/tlbex.c:500: warning: 'i_LA' defined but not used arch/mips/mm/tlbex.c:568: warning: 'insn_has_bdelay' defined but not used arch/mips/mm/tlbex.c:582: warning: 'il_bltz' defined but not used arch/mips/mm/tlbex.c:588: warning: 'il_b' defined but not used How about marking them "attribute((unused))"? I can do that if you agree. Maciej From ralf@linux-mips.org Mon Nov 22 15:01:29 2004 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Nov 2004 15:01:34 +0000 (GMT) Received: from p508B767E.dip.t-dialin.net ([IPv6:::ffff:80.139.118.126]:48177 "EHLO mail.linux-mips.net") by linux-mips.org with ESMTP id ; Mon, 22 Nov 2004 15:01:29 +0000 Received: from fluff.linux-mips.net (localhost [127.0.0.1]) by mail.linux-mips.net (8.13.1/8.13.1) with ESMTP id iAMF180c004658; Mon, 22 Nov 2004 16:01:08 +0100 Received: (from ralf@localhost) by fluff.linux-mips.net (8.13.1/8.13.1/Submit) id iAMF18ro004657; Mon, 22 Nov 2004 16:01:08 +0100 Date: Mon, 22 Nov 2004 16:01:08 +0100 From: Ralf Baechle To: Mad Props Cc: linux-mips@linux-mips.org Subject: Re: beginners question Message-ID: <20041122150108.GA4241@linux-mips.org> References: <8709.1101086706@www8.gmx.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8709.1101086706@www8.gmx.net> User-Agent: Mutt/1.4.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips">