From Geert.Uytterhoeven@sonycom.com Mon Dec  2 10:38:41 2002
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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Ralf Baechle <ralf@linux-mips.org>
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Subject: [PATCH] Eagle compile fix
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The compilation of arch/mips/vr41xx/common/serial.c depends on CONFIG_SERIAL.

--- linux-mips-2.4.x/arch/mips/vr41xx/nec-eagle/setup.c.orig	Mon Jul 15 02:02:56 2002
+++ linux-mips-2.4.x/arch/mips/vr41xx/nec-eagle/setup.c	Mon Dec  2 10:38:16 2002
@@ -143,8 +143,10 @@
 
 	vr41xx_cmu_init(0);
 
+#ifdef CONFIG_SERIAL
 	vr41xx_dsiu_init();
 	vr41xx_siu_init(SIU_RS232C, 0);
+#endif
 
 #ifdef CONFIG_PCI
 	vr41xx_pciu_init(&pci_address_map);

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


From Geert.Uytterhoeven@sonycom.com Mon Dec  2 12:13:40 2002
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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Linux/MIPS Development <linux-mips@linux-mips.org>
Subject: atlas_serial_{in,out}
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	Hi,

The MIPS 2.4.x drivers/char/serial.c differs from the upstream version by the
addition of hooks for the Atlas serial ports. However, I cannot find where
those hooks (atlas_serial_{in,out}) are actualy defined.

Did I overlook something, or is this a leftover from obsolete code?

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


From carstenl@mips.com Mon Dec  2 13:08:39 2002
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They should have been in arch/mips/mips-boards/generic/printf.c, but they have
been removed, apparently.
Ralf, do you have any comment on why this code has been removed.

/Carsten



Geert Uytterhoeven wrote:

>         Hi,
>
> The MIPS 2.4.x drivers/char/serial.c differs from the upstream version by the
> addition of hooks for the Atlas serial ports. However, I cannot find where
> those hooks (atlas_serial_{in,out}) are actualy defined.
>
> Did I overlook something, or is this a leftover from obsolete code?
>
> Gr{oetje,eeting}s,
>
>                                                 Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                                             -- Linus Torvalds

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From jsun@orion.mvista.com Mon Dec  2 20:20:29 2002
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I have vr4131 board running just fine here for quite a while now.

A couple of basic things you may to check with:

. Make sure you have CONFIG_CPU_VR41XX set (obviously).
. Use your own init program that poke some devices other
  than console.  Just to make sure it is *not* the SIU
  console driver problem.

Other things you want to check is the CPU revision.  Make sure
it is 0x0c82, which is v2.2.  Otherwise there are some nasty
cache problems you need to work around.

What is your kernel base?  The latest linux-mips.org CVS tree?

Jun

On Thu, Nov 28, 2002 at 02:42:22AM +0000, henaldohzh@hotmail.com wrote:
>  I carefully check the codes of TLB, but no any problem found.
>  And I debug my kernel, I found that before init task jump into 
> application, it means after do_execve, sp is 0. it is for 
> __strnlen_user_asm function return invalid result. And I done a little 
> change(only for test), the system stop after ret_from_syscall. In normal, 
> it should jump to user space to execute user task.
> before ret_from_syscall, the start_thread arguments 
> is:"elf_entry:0x2aaa8a00,user_sp is:0x7fff7f40,cp0_status is:0x200cc13".I 
> determine that the arguments are correct. But why my application cann't run 
> at all?
> > >   these days, I am busy with porting mips kernel to a board with vr4131
> > > core. This board has only SIU serial port, and some hw have been 
> modified.
> > > Now, I have ported the kernel to it, and modified hw run well. But so
> > > puzzling me, the execution file cann't run at all. If some one can help 
> me
> > > or give some advices. I have been crazy for the problem. Off hat for 
> your
> > > help. Thanks a lot.
> > >  btw, I use the ramdisk with busybox.
> >
> >In general this kind of problem means the tlb or cache code for a 
> particular
> >platform is faulty or the kernel not configured properly.
> >
> >   Ralf
> 
> 
> _________________________________________________________________
> 与联机的朋友进行交流，请使用 MSN Messenger: http://messenger.msn.com/cn 
> 
> 

From Manoj_Ekbote@pmc-sierra.com Mon Dec  2 22:12:46 2002
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> Hi,
> 
> I am looking for GNU's fortran compiler for mips. I have gcc ver. 2.95.3. Luckily, I found  g77-2.95_2.95.4-7_mips.deb <ftp://debian.org/debian/pool/main/g/gcc-2.95/g77-2.95_2.95.4-7_mips.deb> .
> 
> I tried to convert this file into an rpm using the alien program, but I am running into trouble.
> Is there any other place where I can find g77 for mips?
> 
> Thanks,
> Manoj
> 
> 
> 
> 
> 
> 

From hjl@lucon.org Mon Dec  2 22:17:29 2002
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On Mon, Dec 02, 2002 at 01:10:46PM -0800, Manoj Ekbote wrote:
> > Hi,
> > 
> > I am looking for GNU's fortran compiler for mips. I have gcc ver. 2.95.3. Luckily, I found  g77-2.95_2.95.4-7_mips.deb <ftp://debian.org/debian/pool/main/g/gcc-2.95/g77-2.95_2.95.4-7_mips.deb> .
> > 
> > I tried to convert this file into an rpm using the alien program, but I am running into trouble.
> > Is there any other place where I can find g77 for mips?
> > 

It is the part of my RedHat 7.3 mips port.


H.J.

From ralf@linux-mips.org Tue Dec  3 02:40:40 2002
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On Mon, Dec 02, 2002 at 01:10:08PM +0100, Carsten Langgaard wrote:

> They should have been in arch/mips/mips-boards/generic/printf.c, but they have
> been removed, apparently.
> Ralf, do you have any comment on why this code has been removed.

Simply a glitch when cleaning in arch/mips/mips-boards/generic/printf.c.

Btw, that file seem to follow the motto "generic due to ifdef" ;-)

  Ralf

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Ralf Baechle wrote:

> On Mon, Dec 02, 2002 at 01:10:08PM +0100, Carsten Langgaard wrote:
>
> > They should have been in arch/mips/mips-boards/generic/printf.c, but they have
> > been removed, apparently.
> > Ralf, do you have any comment on why this code has been removed.
>
> Simply a glitch when cleaning in arch/mips/mips-boards/generic/printf.c.
>
> Btw, that file seem to follow the motto "generic due to ifdef" ;-)
>

Isn't the ifdef wonderful ;-)
A guess it's always a matter of compromise, tring to avoid the ifdef and sharing as
much code as possible.


>
>   Ralf

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From erlend-a@ux.his.no Tue Dec  3 15:32:00 2002
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From: Erlend Aasland <erlend-a@ux.his.no>
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Cc: LKML <linux-kernel@vger.kernel.org>, Ralf Baechle <ralf@gnu.org>,
	linux-mips@linux-mips.org
Subject: [TRIVIAL PATCH 2.5] get rid of CONFIG_UDF_RW (mips)
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Remove CONFIG_UDF_RW from mips{,64} defconfigs, (it's not used anymore)

Regards,
	Erlend Aasland

diff -urN linux-2.5.50/arch/mips/defconfig linux-2.5.50-eaa/arch/mips/defconfig
--- linux-2.5.50/arch/mips/defconfig	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig	Tue Dec  3 00:48:05 2002
@@ -456,7 +456,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips/defconfig-atlas linux-2.5.50-eaa/arch/mips/defconfig-atlas
--- linux-2.5.50/arch/mips/defconfig-atlas	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-atlas	Tue Dec  3 00:48:05 2002
@@ -446,7 +446,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips/defconfig-ddb5476 linux-2.5.50-eaa/arch/mips/defconfig-ddb5476
--- linux-2.5.50/arch/mips/defconfig-ddb5476	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-ddb5476	Tue Dec  3 00:48:05 2002
@@ -480,7 +480,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips/defconfig-ddb5477 linux-2.5.50-eaa/arch/mips/defconfig-ddb5477
--- linux-2.5.50/arch/mips/defconfig-ddb5477	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-ddb5477	Tue Dec  3 00:48:05 2002
@@ -407,7 +407,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips/defconfig-decstation linux-2.5.50-eaa/arch/mips/defconfig-decstation
--- linux-2.5.50/arch/mips/defconfig-decstation	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-decstation	Tue Dec  3 00:48:05 2002
@@ -443,7 +443,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips/defconfig-ip22 linux-2.5.50-eaa/arch/mips/defconfig-ip22
--- linux-2.5.50/arch/mips/defconfig-ip22	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-ip22	Tue Dec  3 00:48:05 2002
@@ -456,7 +456,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips/defconfig-it8172 linux-2.5.50-eaa/arch/mips/defconfig-it8172
--- linux-2.5.50/arch/mips/defconfig-it8172	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-it8172	Tue Dec  3 00:48:05 2002
@@ -559,7 +559,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips/defconfig-malta linux-2.5.50-eaa/arch/mips/defconfig-malta
--- linux-2.5.50/arch/mips/defconfig-malta	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-malta	Tue Dec  3 00:48:05 2002
@@ -472,7 +472,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips/defconfig-nino linux-2.5.50-eaa/arch/mips/defconfig-nino
--- linux-2.5.50/arch/mips/defconfig-nino	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-nino	Tue Dec  3 00:48:05 2002
@@ -283,7 +283,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 # CONFIG_NCPFS_NLS is not set
diff -urN linux-2.5.50/arch/mips/defconfig-ocelot linux-2.5.50-eaa/arch/mips/defconfig-ocelot
--- linux-2.5.50/arch/mips/defconfig-ocelot	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-ocelot	Tue Dec  3 00:48:05 2002
@@ -408,7 +408,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips/defconfig-pb1000 linux-2.5.50-eaa/arch/mips/defconfig-pb1000
--- linux-2.5.50/arch/mips/defconfig-pb1000	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-pb1000	Tue Dec  3 00:48:05 2002
@@ -395,7 +395,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips/defconfig-rm200 linux-2.5.50-eaa/arch/mips/defconfig-rm200
--- linux-2.5.50/arch/mips/defconfig-rm200	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips/defconfig-rm200	Tue Dec  3 00:48:05 2002
@@ -326,7 +326,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set

diff -urN linux-2.5.50/arch/mips64/defconfig linux-2.5.50-eaa/arch/mips64/defconfig
--- linux-2.5.50/arch/mips64/defconfig	Sun Oct 13 19:24:14 2002
+++ linux-2.5.50-eaa/arch/mips64/defconfig	Tue Dec  3 00:48:05 2002
@@ -414,7 +414,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips64/defconfig-ip22 linux-2.5.50-eaa/arch/mips64/defconfig-ip22
--- linux-2.5.50/arch/mips64/defconfig-ip22	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips64/defconfig-ip22	Tue Dec  3 00:48:05 2002
@@ -418,7 +418,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips64/defconfig-ip27 linux-2.5.50-eaa/arch/mips64/defconfig-ip27
--- linux-2.5.50/arch/mips64/defconfig-ip27	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips64/defconfig-ip27	Tue Dec  3 00:48:05 2002
@@ -413,7 +413,6 @@
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 
diff -urN linux-2.5.50/arch/mips64/defconfig-ip32 linux-2.5.50-eaa/arch/mips64/defconfig-ip32
--- linux-2.5.50/arch/mips64/defconfig-ip32	Mon Sep  2 15:57:00 2002
+++ linux-2.5.50-eaa/arch/mips64/defconfig-ip32	Tue Dec  3 00:48:05 2002
@@ -444,7 +444,6 @@
 # CONFIG_SYSV_FS is not set
 # CONFIG_SYSV_FS_WRITE is not set
 # CONFIG_UDF_FS is not set
-# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
 # CONFIG_UFS_FS_WRITE is not set
 

From hjl@lucon.org Tue Dec  3 18:42:14 2002
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I updated the following rpms in my RedHat 7.3 mips port:

toolchain-20021126-1.src.rpm
autofs-4.0.0pre10-0.6.src.rpm
automake-1.4p5-4.1.src.rpm
binutils-2.13.90.0.16-1.src.rpm
gcc-2.96-113.2.src.rpm
gdb-5.2.90-0.2.src.rpm
glibc-2.2.5-42.1.src.rpm
glibc-kernheaders-2.4.20pre6-1.src.rpm
hwdata-0.14.1-1.2.src.rpm
kudzu-0.99.52-1.4.src.rpm
libcap-1.10-12.1.src.rpm
libpng-1.0.14-0.7x.3.1.src.rpm
lvm-1.0.3-4.src.rpm
modutils-2.4.18-3.7x.1.src.rpm
nfs-utils-1.0.2-0.4.src.rpm
ntp-4.1.1-1.2.src.rpm
openssh-3.1p1-6.2.src.rpm
pam-0.75-32.2.src.rpm
parted-1.4.24-3.2.src.rpm
strace-4.4-8.1.src.rpm
tar-1.13.25-4.7.1.src.rpm
tcltk-8.3.3-67.2.src.rpm
tftp-0.30-0.1.src.rpm
XFree86-4.2.0-72.2.src.rpm
ypserv-2.5-2.7x.1.src.rpm
zsh-4.0.4-5.3.src.rpm


H.J.
----
My mini-port of RedHat 7.3 is at

ftp://ftp.linux-mips.org/pub/linux/mips/redhat/7.3/

It has both mips (big endian) and mipsel (little endian) binary rpms.
You should be able to put a small RedHat 7.3 on the mips/mipsel box and
compile the rest of RedHat 7.3 yourselves.

Here are something you should know:

1. The cross compiler hosted on RedHat 7.3/x86 is provided as the
toolchain rpm. The binary rpms for the mips and mipsel cross compilers
are included. This toolchain is a combination of gcc, binutils and
glibc. It is packaged for the cross compiling. It allows you to cross
compile to RedHat 7.3/mips/mipsel from a RedHat 7.3/x86 host.
2. You have to find a way to put those rpms on your machine. I use
network boot and NFS root to do it.
3. baseline.tar.bz2 contains the cross build tree. You may need to
install i386 rpm binary included here to rebuild mips/mipsel rpms on
an x86 host. The "installer" directory has a simple installer, which
can be used to prepare NFS root and install RedHat 7.3/mips/mipsel on
a hard drive.
4. Since everything is cross compiled from x86, which is little endian,
many data files for mips, which is big endian, are either missing or
wrong. To get those data files for mips, you have to rebuild/install
the folowing rpms:

cracklib
glibc

natively on Linux/mips.

Thanks.


H.J.

From drow@false.org Tue Dec  3 19:17:13 2002
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From: Daniel Jacobowitz <dan@debian.org>
To: "Aric, Wang" <aricwang@svanetworks.com>
Cc: linux-mips@linux-mips.org
Subject: Re: can't checkout linux source code
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On Tue, Dec 03, 2002 at 07:57:14PM +0800, Aric, Wang wrote:
> I can't check out the linux directory by execute the following commands:
>  
> cvs -d :pserver:cvs@ftp.linux-mips.org:/home/cvs login
> password: cvs
> 
> cvs -d :pserver:cvs@ftp.linux-mips.org:/home/cvs co linux
> 
> This was work some days before. How about it now? How can give me some thread?

Use cvs.linux-mips.org, as was announced on the list a couple days ago.

-- 
Daniel Jacobowitz
MontaVista Software                         Debian GNU/Linux Developer

From ralf@linux-mips.org Tue Dec  3 22:58:26 2002
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On Tue, Dec 03, 2002 at 01:17:27PM -0500, Daniel Jacobowitz wrote:

> > cvs -d :pserver:cvs@ftp.linux-mips.org:/home/cvs co linux
> > 
> > This was work some days before. How about it now? How can give me some thread?
> 
> Use cvs.linux-mips.org, as was announced on the list a couple days ago.

For a few days ftp.linux-mips.org and cvs.linux-mips.org were two different
machines.  Now they're the same machine again.  Anyway, use the cvs.*
hostname to avoid surprises in the future.  Near future ...

  Ralf

From drow@false.org Wed Dec  4 01:15:37 2002
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From: Daniel Jacobowitz <dan@debian.org>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
	Ralf Baechle <ralf@linux-mips.org>
Cc: atul srivastava <atulsrivastava9@rediffmail.com>,
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On Mon, Nov 25, 2002 at 04:30:13PM +0100, Maciej W. Rozycki wrote:
> On Mon, 25 Nov 2002, Daniel Jacobowitz wrote:
> 
> > >  I think the best use of the watch exception would be making it available
> > > to userland via PTRACE_PEEKUSR and PTRACE_POKEUSR for hardware watchpoint
> > > support (e.g. for gdb).  Hardware support is absolutely necessary for
> > > watching read accesses and much beneficial for write ones (otherwise gdb
> > > single-steps code which sucks performace-wise).
> > 
> > (Although that isn't necessary; page-protection watchpoints are on my
> > TODO for next year.  They aren't quite as efficient as hardware
> > watchpoints but they don't require hardware support either, just an
> > MMU.)
> 
>  As a fallback the approach is just fine, but doesn't is suck
> performance-wise for watchpoints at the stack?  It certainly sucks for
> instruction fetches.  While gdb doesn't seem to use hardware breakpoints
> as they are only really necessary for ROMs, other software may want to
> (well, gdb too, one day). 

Page-protection watchpoints on the stack do bite for performance, yes. 
Most watched variables are not on the stack, though.  People tend to
watch globals.


On Mon, Nov 25, 2002 at 04:08:00PM +0100, Ralf Baechle wrote:
> I assume you got and R4000 manual and the MIPS64 spec.   R4000 implements
> matching a physical address with a granularity of 8 bytes for load and
> store operations.

Not handy.

> MIPS64 extends that to also support instruction address matches; the
> granularity can be set anywhere from 8 bytes to 4kB; in addition ASID
> matching and a global bit can be used for matching.  A MIPS64 CPU can
> support anywhere from 0 to 4 such watch registers.
> 
> The global bit stuff would only be useful for in-kernel use, I think.  The
> ASID thing could be used to implement watchpoints for an entire process, not
> just per thread though I doubt there is much use for something like that.
> 
> So how would a prefered ptrace(2) API for hardware watchpoints look like?

Well, it would be nice to have at least:
  - query total number
  - query the granularity, or at least query whether or not the
    granularity is settable
  - Set and remove watchpoints.

Off the top of my head:
PTRACE_MIPS_WATCHPOINT_INFO
struct mips_watchpoint_info {
  u32 num_avail;
  u32 max_size;
};

PTRACE_MIPS_WATCHPOINT_SET
struct mips_watchpoint_set {
  u32 index;
  u32 size;
  s64 address;
};

-- 
Daniel Jacobowitz
MontaVista Software                         Debian GNU/Linux Developer

From ralf@linux-mips.org Wed Dec  4 01:37:38 2002
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On Mon, Nov 25, 2002 at 04:47:33PM +0100, Maciej W. Rozycki wrote:

> > MIPS64 extends that to also support instruction address matches; the
> > granularity can be set anywhere from 8 bytes to 4kB; in addition ASID
> > matching and a global bit can be used for matching.  A MIPS64 CPU can
> > support anywhere from 0 to 4 such watch registers.
> 
>  Actually up to eight -- for all dmfc0/dmtc0 3-bit "sel" values, if I read
> it correctly.

Correct but I don't know of any CPU that actually uses more than 4 of the
possible 8 sets atm.  So we're both right :)

> > The global bit stuff would only be useful for in-kernel use, I think.  The
> > ASID thing could be used to implement watchpoints for an entire process, not
> > just per thread though I doubt there is much use for something like that.
> 
>  Well, there are two options only -- either use global matching or ASID
> matching.  What else would you expect?  Do you mean lazy vs immediate
> switching? 

Basically there would be two possibilities, associate the debugging state
of a process with it's thread_struct or with it's mm_struct.  The latter
would have a little less impact on the context switching performance,
the first be a bit more flexible.

  Ralf

From drow@false.org Wed Dec  4 01:58:00 2002
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On Wed, Dec 04, 2002 at 01:37:13AM +0100, Ralf Baechle wrote:
> On Mon, Nov 25, 2002 at 04:47:33PM +0100, Maciej W. Rozycki wrote:
> 
> > > MIPS64 extends that to also support instruction address matches; the
> > > granularity can be set anywhere from 8 bytes to 4kB; in addition ASID
> > > matching and a global bit can be used for matching.  A MIPS64 CPU can
> > > support anywhere from 0 to 4 such watch registers.
> > 
> >  Actually up to eight -- for all dmfc0/dmtc0 3-bit "sel" values, if I read
> > it correctly.
> 
> Correct but I don't know of any CPU that actually uses more than 4 of the
> possible 8 sets atm.  So we're both right :)
> 
> > > The global bit stuff would only be useful for in-kernel use, I think.  The
> > > ASID thing could be used to implement watchpoints for an entire process, not
> > > just per thread though I doubt there is much use for something like that.
> > 
> >  Well, there are two options only -- either use global matching or ASID
> > matching.  What else would you expect?  Do you mean lazy vs immediate
> > switching? 
> 
> Basically there would be two possibilities, associate the debugging state
> of a process with it's thread_struct or with it's mm_struct.  The latter
> would have a little less impact on the context switching performance,
> the first be a bit more flexible.

Thread_struct, please.  Just because two processes have the same
mm_struct doesn't mean that we want watchpoints to trigger in both of
them, unless specifically requested.

-- 
Daniel Jacobowitz
MontaVista Software                         Debian GNU/Linux Developer

From jsun@orion.mvista.com Wed Dec  4 07:45:12 2002
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From: Jun Sun <jsun@mvista.com>
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Subject: possible Malta 4Kc cache problem ...
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I attached the test case.  Untar it.  Type 'make' and run 'a.out'.

If the test fails you will see a print-out.  Otherwise you see nothing.

It does not always fail.  But if it fails, it is usually pretty consistent.
Try a few times.  Moving source tree to a different directory may cause
the symptom appear or disappear.

I spent quite some time to trace this problem, and came to suspect
there might be a hardware problem.

The problem involves emulating a "lw" instruction in cp1 branch delay
slot, which needs to  set up trampoline in user stack.  The net effect
looks as if the icache line or dcache line is not flushed properly.

Using gdb/kgdb, printf or printk in any useful places would hide the bug.

I did find a smaller part of the problem.  flush_cache_sigtramp for
MIPS32 (4Kc) calls protected_writeback_dcache_line in mips32_cache.h.
It uses Hit_Writeback_D, and the 4Kc mannual says it is not implemented
and executed as no-op (*ick*).

Even after fixing this, I still see the problem happening.

If you replace flush_cache_sigtramp() with flush_cache_all(), symptom
would disppear.

Several of my tests seem to suggest it is the icache that did not
get flushed (or updated) properly.

Not re-producible on other MIPS boards.  At least so far.

Does anybody with more knowledge about 4Kc have any clues here?

Thanks.

Jun

--tThc/1wpZn/ma/RB
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--tThc/1wpZn/ma/RB--

From carstenl@mips.com Wed Dec  4 09:34:23 2002
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Date: Wed, 04 Dec 2002 09:34:04 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Latest sources from CVS.
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I just checked the latest sources out of cvs.

It look like you are only able to compile the kernel, if you got a
MIPS32/MIPS64 compliant compiler.
The mips32 and mips64 assembler directives are set in
include/asm-mips/mipsregs.h

I guess this will make some people out there, which doesn't use a MIPS32
compliant compiler, a little bit unhappy.
But then again, we would like to force everybody to use the SDE
compiler.

/Carsten


--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From kevink@mips.com Wed Dec  4 10:06:08 2002
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	"Ralf Baechle" <ralf@linux-mips.org>, <linux-mips@linux-mips.org>
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> I just checked the latest sources out of cvs.
> 
> It look like you are only able to compile the kernel, if you got a
> MIPS32/MIPS64 compliant compiler.
> The mips32 and mips64 assembler directives are set in
> include/asm-mips/mipsregs.h
> 
> I guess this will make some people out there, which doesn't use a MIPS32
> compliant compiler, a little bit unhappy.
> But then again, we would like to force everybody to use the SDE
> compiler.

For those on the list who don't understand Carsten's sense
of humour, I think that was missing a smiley!  ;-)
I mean, sure, we'd like to move more people toward SDE, 
but "force" is putting it a bit strongly!  And if those directives
are really being used unconditionally, I worry that the code
being generated is likewise emitting MIPS32 instructions
that won't work on the "ghost fleet" of abandoned workstations
now running Linux on R4K/R5K CPUs.

            Kevin K.

From kevink@mips.com Wed Dec  4 10:34:47 2002
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> I attached the test case.  Untar it.  Type 'make' and run 'a.out'.
> 
> If the test fails you will see a print-out.  Otherwise you see nothing.
> 
> It does not always fail.  But if it fails, it is usually pretty consistent.
> Try a few times.  Moving source tree to a different directory may cause
> the symptom appear or disappear.
> 
> I spent quite some time to trace this problem, and came to suspect
> there might be a hardware problem.
> 
> The problem involves emulating a "lw" instruction in cp1 branch delay
> slot, which needs to  set up trampoline in user stack.  The net effect
> looks as if the icache line or dcache line is not flushed properly.
> 
> Using gdb/kgdb, printf or printk in any useful places would hide the bug.
> 
> I did find a smaller part of the problem.  flush_cache_sigtramp for
> MIPS32 (4Kc) calls protected_writeback_dcache_line in mips32_cache.h.
> It uses Hit_Writeback_D, and the 4Kc mannual says it is not implemented
> and executed as no-op (*ick*).

Which version of the 4Kc manual are you looking at?  I'm looking
at a very recent version of the 4Kc Software User's Manual
(version 1.17, dated September 25, 2002), and it only shows
Hit_Writeback_D to be invalid for *secondary and teritary*
caches, which makes sense, since the 4KSc doesn't have any.

> Even after fixing this, I still see the problem happening.

That's not too surprising.  The 4Kc D-cache is write-through,
so if you're really seeing a problem with trampolimes, it is almost
certain to be a problem with the Icache invalidation, not the
Dcache flush.
 
> If you replace flush_cache_sigtramp() with flush_cache_all(), symptom
> would disppear.

Which again would make sense if there's a problem on
the icache side of the flush.  Oddly enough, we've seen
some glitches on other CPUs with other kernels that 
might have been explicable by failures of protected_flush_icache_line(),
but we never found a problem with it, and a higher-level
memory management patch made the problem go away.
Makes me wonder if we shouldn't look at it again, more
closely.  Is there any possibility that the logic for restarting
a protected kernel access following a page fault will somehow
screw up on CACHE instructions, as opposed to the loads
and stores for which the code was originally written?

> Several of my tests seem to suggest it is the icache that did not
> get flushed (or updated) properly.
> 
> Not re-producible on other MIPS boards.  At least so far.
> 
> Does anybody with more knowledge about 4Kc have any clues here?
> 
> Thanks.
> 
> Jun

From kevink@mips.com Wed Dec  4 10:42:31 2002
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Subject: Re: possible Malta 4Kc cache problem ...
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> Which version of the 4Kc manual are you looking at?  I'm looking
> at a very recent version of the 4Kc Software User's Manual
> (version 1.17, dated September 25, 2002), and it only shows
> Hit_Writeback_D to be invalid for *secondary and teritary*
> caches, which makes sense, since the 4KSc doesn't have any.

Note for the pendantic - that "S" was a typo, though of
course the lack of secondary and tertiary caches applies
to the whole 4K family, c, Ec, Sc, and Sd.

From carstenl@mips.com Wed Dec  4 11:08:30 2002
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I have just tried your test on a 4Kc and I see no problems.
However I'm running on our internal kernel sources, and as Kevin mention we have
changed a fixed a few things in this area.
As Kevin also mention it sure look more like a I-cache invalidation problem,
rather than a D-cache flush problem, as the 4Kc has a write-through cache.
One think you could try, is our latest kernel release. You can find it here:
ftp://ftp.mips.com/pub/linux/mips/kernel/2.4/images/


/Carsten


"Kevin D. Kissell" wrote:

> > I attached the test case.  Untar it.  Type 'make' and run 'a.out'.
> >
> > If the test fails you will see a print-out.  Otherwise you see nothing.
> >
> > It does not always fail.  But if it fails, it is usually pretty consistent.
> > Try a few times.  Moving source tree to a different directory may cause
> > the symptom appear or disappear.
> >
> > I spent quite some time to trace this problem, and came to suspect
> > there might be a hardware problem.
> >
> > The problem involves emulating a "lw" instruction in cp1 branch delay
> > slot, which needs to  set up trampoline in user stack.  The net effect
> > looks as if the icache line or dcache line is not flushed properly.
> >
> > Using gdb/kgdb, printf or printk in any useful places would hide the bug.
> >
> > I did find a smaller part of the problem.  flush_cache_sigtramp for
> > MIPS32 (4Kc) calls protected_writeback_dcache_line in mips32_cache.h.
> > It uses Hit_Writeback_D, and the 4Kc mannual says it is not implemented
> > and executed as no-op (*ick*).
>
> Which version of the 4Kc manual are you looking at?  I'm looking
> at a very recent version of the 4Kc Software User's Manual
> (version 1.17, dated September 25, 2002), and it only shows
> Hit_Writeback_D to be invalid for *secondary and teritary*
> caches, which makes sense, since the 4KSc doesn't have any.
>
> > Even after fixing this, I still see the problem happening.
>
> That's not too surprising.  The 4Kc D-cache is write-through,
> so if you're really seeing a problem with trampolimes, it is almost
> certain to be a problem with the Icache invalidation, not the
> Dcache flush.
>
> > If you replace flush_cache_sigtramp() with flush_cache_all(), symptom
> > would disppear.
>
> Which again would make sense if there's a problem on
> the icache side of the flush.  Oddly enough, we've seen
> some glitches on other CPUs with other kernels that
> might have been explicable by failures of protected_flush_icache_line(),
> but we never found a problem with it, and a higher-level
> memory management patch made the problem go away.
> Makes me wonder if we shouldn't look at it again, more
> closely.  Is there any possibility that the logic for restarting
> a protected kernel access following a page fault will somehow
> screw up on CACHE instructions, as opposed to the loads
> and stores for which the code was originally written?
>
> > Several of my tests seem to suggest it is the icache that did not
> > get flushed (or updated) properly.
> >
> > Not re-producible on other MIPS boards.  At least so far.
> >
> > Does anybody with more knowledge about 4Kc have any clues here?
> >
> > Thanks.
> >
> > Jun

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From atulsrivastava9@rediffmail.com Wed Dec  4 11:18:54 2002
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Subject: hazards during DO_FAULT macro..
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My problem is that during return of sys_execve i get a page fault 
on userspace address (0x004000b0) but the pt_regs address in 
do_page_fault I get is 0x8013a61c which is actually envp_init 
arguement passed in execve("/bin/sh",argv_init,envp_init);

I was trying to debug where my pt_regs pointer got thrased during 
do_page_fault()

I found following stuff very strange.

macro Do_FAULt(write) expands like..

#define DO_FAULT(write) \
         .set    noreorder; \
         .set    noat; \
         SAVE_ALL; \
         STI; \
         nop; \
         .set    at; \
         move a0, sp; \
         jal     do_page_fault; \
         li     a1, write; \
         nop; \
         j       ret_from_sys_call; \
         nop; \
        .set    noat;

this macro is called by handle_tlbx() routines.
when I tracked this problem and i observed my pt_regs address
looked o.k. and apparently right till after STI; \ and just before 
instruction     mfc0    a2, CP0_BADVADDR;
this i found by putting following instructions,

move  a0,sp; \
jal show_regs; \
nop; \

later it jumps to do_page_fault() ,and pt_regs address there 
equals unexpectedly to envp_init and from thereon everythings goes 
wrong..

I also tried with negating STI; \ , but same result.

problamatic assembly code for DO_FAULT macro is following.

.set noat; \
SAVE_ALL; \
8001e694:  03a02021 	move	$a0,$sp               ----{
8001e698:  0c03bba8 	jal	800eeea0 <show_regs>  my debug code of          
                      show_regs() ...here pt_regs address is 
o.k..
8001e69c:	00000000 	nop                   ---}

8001e6a0:	40086000 	mfc0	$t0,$12     -----{
8001e6a4:	3c091000 	lui	$t1,0x1000
8001e6a8:	3529001f 	ori	$t1,$t1,0x1f
8001e6ac:	01094025 	or	$t0,$t0,$t1     STI macro code , though i 
tried without STI for testing purpose, as well
8001e6b0:	3908001e 	xori	$t0,$t0,0x1e
8001e6b4:	40886000 	mtc0	$t0,$12
8001e6b8:	40064000 	mfc0	$a2,$8      -----}
...
8001e6c4:	03a02021 	move	$a0,$sp
8001e6c8:	0c007e34 	jal	8001f8d0 <do_page_fault>
                                                    -----{now in         
          do_page_fault() pt_regs address is erronousely
         different in my case it is equal to envp_init.  }
8001e6cc:	24050000 	li	$a1,0
8001e6d0:	00000000 	nop
8001e6d4:	08006a9a 	j	8001aa68 <ret_from_irq>

what kind of hazard happening..?

Best Regards,
Atul




From atulsrivastava9@rediffmail.com Wed Dec  4 11:20:05 2002
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My problem is that during return of sys_execve i get a page fault 
on userspace address (0x004000b0) but the pt_regs address in 
do_page_fault I get is 0x8013a61c which is actually envp_init 
arguement passed in execve("/bin/sh",argv_init,envp_init);

I was trying to debug where my pt_regs pointer got thrased during 
do_page_fault()

I found following stuff very strange.

macro Do_FAULt(write) expands like..

#define DO_FAULT(write) \
         .set    noreorder; \
         .set    noat; \
         SAVE_ALL; \
         STI; \
         nop; \
         .set    at; \
         move a0, sp; \
         jal     do_page_fault; \
         li     a1, write; \
         nop; \
         j       ret_from_sys_call; \
         nop; \
        .set    noat;

this macro is called by handle_tlbx() routines.
when I tracked this problem and i observed my pt_regs address
looked o.k. and apparently right till after STI; \ and just before 
instruction     mfc0    a2, CP0_BADVADDR;
this i found by putting following instructions,

move  a0,sp; \
jal show_regs; \
nop; \

later it jumps to do_page_fault() ,and pt_regs address there 
equals unexpectedly to envp_init and from thereon everythings goes 
wrong..

I also tried with negating STI; \ , but same result.

problamatic assembly code for DO_FAULT macro is following.

.set noat; \
SAVE_ALL; \
8001e694:  03a02021 	move	$a0,$sp               ----{
8001e698:  0c03bba8 	jal	800eeea0 <show_regs>  my debug code of          
                      show_regs() ...here pt_regs address is 
o.k..
8001e69c:	00000000 	nop                   ---}

8001e6a0:	40086000 	mfc0	$t0,$12     -----{
8001e6a4:	3c091000 	lui	$t1,0x1000
8001e6a8:	3529001f 	ori	$t1,$t1,0x1f
8001e6ac:	01094025 	or	$t0,$t0,$t1     STI macro code , though i 
tried without STI for testing purpose, as well
8001e6b0:	3908001e 	xori	$t0,$t0,0x1e
8001e6b4:	40886000 	mtc0	$t0,$12
8001e6b8:	40064000 	mfc0	$a2,$8      -----}
...
8001e6c4:	03a02021 	move	$a0,$sp
8001e6c8:	0c007e34 	jal	8001f8d0 <do_page_fault>
                                                    -----{now in         
          do_page_fault() pt_regs address is erronousely
         different in my case it is equal to envp_init.  }
8001e6cc:	24050000 	li	$a1,0
8001e6d0:	00000000 	nop
8001e6d4:	08006a9a 	j	8001aa68 <ret_from_irq>

what kind of hazard happening..?

Best Regards,
Atul




From carstenl@mips.com Wed Dec  4 12:21:44 2002
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I just noticed that the patch I send (I don't know how long ago), hasn't made it
into the CVS tree.
So there is a potentially hole in the indexed flushes, which might only flush one
of the cache ways.

Please try the mips32_cache.h, I have attached.

/Carsten



Carsten Langgaard wrote:

> I have just tried your test on a 4Kc and I see no problems.
> However I'm running on our internal kernel sources, and as Kevin mention we have
> changed a fixed a few things in this area.
> As Kevin also mention it sure look more like a I-cache invalidation problem,
> rather than a D-cache flush problem, as the 4Kc has a write-through cache.
> One think you could try, is our latest kernel release. You can find it here:
> ftp://ftp.mips.com/pub/linux/mips/kernel/2.4/images/
>
> /Carsten
>
> "Kevin D. Kissell" wrote:
>
> > > I attached the test case.  Untar it.  Type 'make' and run 'a.out'.
> > >
> > > If the test fails you will see a print-out.  Otherwise you see nothing.
> > >
> > > It does not always fail.  But if it fails, it is usually pretty consistent.
> > > Try a few times.  Moving source tree to a different directory may cause
> > > the symptom appear or disappear.
> > >
> > > I spent quite some time to trace this problem, and came to suspect
> > > there might be a hardware problem.
> > >
> > > The problem involves emulating a "lw" instruction in cp1 branch delay
> > > slot, which needs to  set up trampoline in user stack.  The net effect
> > > looks as if the icache line or dcache line is not flushed properly.
> > >
> > > Using gdb/kgdb, printf or printk in any useful places would hide the bug.
> > >
> > > I did find a smaller part of the problem.  flush_cache_sigtramp for
> > > MIPS32 (4Kc) calls protected_writeback_dcache_line in mips32_cache.h.
> > > It uses Hit_Writeback_D, and the 4Kc mannual says it is not implemented
> > > and executed as no-op (*ick*).
> >
> > Which version of the 4Kc manual are you looking at?  I'm looking
> > at a very recent version of the 4Kc Software User's Manual
> > (version 1.17, dated September 25, 2002), and it only shows
> > Hit_Writeback_D to be invalid for *secondary and teritary*
> > caches, which makes sense, since the 4KSc doesn't have any.
> >
> > > Even after fixing this, I still see the problem happening.
> >
> > That's not too surprising.  The 4Kc D-cache is write-through,
> > so if you're really seeing a problem with trampolimes, it is almost
> > certain to be a problem with the Icache invalidation, not the
> > Dcache flush.
> >
> > > If you replace flush_cache_sigtramp() with flush_cache_all(), symptom
> > > would disppear.
> >
> > Which again would make sense if there's a problem on
> > the icache side of the flush.  Oddly enough, we've seen
> > some glitches on other CPUs with other kernels that
> > might have been explicable by failures of protected_flush_icache_line(),
> > but we never found a problem with it, and a higher-level
> > memory management patch made the problem go away.
> > Makes me wonder if we shouldn't look at it again, more
> > closely.  Is there any possibility that the logic for restarting
> > a protected kernel access following a page fault will somehow
> > screw up on CACHE instructions, as opposed to the loads
> > and stores for which the code was originally written?
> >
> > > Several of my tests seem to suggest it is the icache that did not
> > > get flushed (or updated) properly.
> > >
> > > Not re-producible on other MIPS boards.  At least so far.
> > >
> > > Does anybody with more knowledge about 4Kc have any clues here?
> > >
> > > Thanks.
> > >
> > > Jun
>
> --
> _    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark            http://www.mips.com

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



--------------63CEFDDE1EAEF4F9A52D6AA8
Content-Type: text/plain; charset=iso-8859-15;
 name="mips32_cache.h"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="mips32_cache.h"

/*
 * mips32_cache.h
 *
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 *
 * Inline assembly cache operations.
 * 
 * This file is the original r4cache.c file with modification that makes the
 * cache handling more generic.
 *
 * FIXME: Handle split L2 caches.
 *
 */
#ifndef _MIPS_R4KCACHE_H
#define _MIPS_R4KCACHE_H

#include <asm/asm.h>
#include <asm/cacheops.h>

static inline void flush_icache_line_indexed(unsigned long addr)
{
	unsigned long waystep = icache_size/mips_cpu.icache.ways;
	unsigned int way;

	for (way = 0; way < mips_cpu.icache.ways; way++)
	{
		__asm__ __volatile__(
			".set noreorder\n\t"
			".set mips3\n\t"
			"cache %1, (%0)\n\t"
			".set mips0\n\t"
			".set reorder"
			:
			: "r" (addr),
			"i" (Index_Invalidate_I));
		
		addr += waystep;
	}
}

static inline void flush_dcache_line_indexed(unsigned long addr)
{
	unsigned long waystep = dcache_size/mips_cpu.dcache.ways;
	unsigned int way;

	for (way = 0; way < mips_cpu.dcache.ways; way++)
	{
		__asm__ __volatile__(
			".set noreorder\n\t"
			".set mips3\n\t"
			"cache %1, (%0)\n\t"
			".set mips0\n\t"
			".set reorder"
			:
			: "r" (addr),
			"i" (Index_Writeback_Inv_D));

		addr += waystep;
	}
}

static inline void flush_scache_line_indexed(unsigned long addr)
{
	unsigned long waystep = scache_size/mips_cpu.scache.ways;
	unsigned int way;

	for (way = 0; way < mips_cpu.scache.ways; way++)
	{
		__asm__ __volatile__(
			".set noreorder\n\t"
			".set mips3\n\t"
			"cache %1, (%0)\n\t"
			".set mips0\n\t"
			".set reorder"
			:
			: "r" (addr),
			"i" (Index_Writeback_Inv_SD));

		addr += waystep;
	}
}

static inline void flush_icache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		".set mips3\n\t"
		"cache %1, (%0)\n\t"
		".set mips0\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Hit_Invalidate_I));
}

static inline void flush_dcache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		".set mips3\n\t"
		"cache %1, (%0)\n\t"
		".set mips0\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Hit_Writeback_Inv_D));
}

static inline void invalidate_dcache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		".set mips3\n\t"
		"cache %1, (%0)\n\t"
		".set mips0\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Hit_Invalidate_D));
}

static inline void invalidate_scache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		".set mips3\n\t"
		"cache %1, (%0)\n\t"
		".set mips0\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Hit_Invalidate_SD));
}

static inline void flush_scache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		".set mips3\n\t"
		"cache %1, (%0)\n\t"
		".set mips0\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Hit_Writeback_Inv_SD));
}

/*
 * The next two are for badland addresses like signal trampolines.
 */
static inline void protected_flush_icache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		".set mips3\n"
		"1:\tcache %1,(%0)\n"
		"2:\t.set mips0\n\t"
		".set reorder\n\t"
		".section\t__ex_table,\"a\"\n\t"
		STR(PTR)"\t1b,2b\n\t"
		".previous"
		:
		: "r" (addr),
		  "i" (Hit_Invalidate_I));
}

static inline void protected_writeback_dcache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		".set mips3\n"
		"1:\tcache %1,(%0)\n"
		"2:\t.set mips0\n\t"
		".set reorder\n\t"
		".section\t__ex_table,\"a\"\n\t"
		STR(PTR)"\t1b,2b\n\t"
		".previous"
		:
		: "r" (addr),
		  "i" (Hit_Writeback_D));
}

#define cache_unroll(base,op)	        	\
	__asm__ __volatile__("	         	\
		.set noreorder;		        \
		.set mips3;		        \
                cache %1, (%0);	                \
		.set mips0;			\
		.set reorder"			\
		:				\
		: "r" (base),			\
		  "i" (op));


static inline void blast_dcache(void)
{
	unsigned long start = KSEG0;
	unsigned long end = (start + dcache_size);

	while(start < end) {
		cache_unroll(start,Index_Writeback_Inv_D);
		start += dc_lsize;
	}
}

static inline void blast_dcache_page(unsigned long page)
{
	unsigned long start = page;
	unsigned long end = (start + PAGE_SIZE);

	while(start < end) {
		cache_unroll(start,Hit_Writeback_Inv_D);
		start += dc_lsize;
	}
}

static inline void blast_dcache_page_indexed(unsigned long page)
{
	unsigned long start;
	unsigned long end = (page + PAGE_SIZE);
	unsigned long waystep = dcache_size/mips_cpu.dcache.ways;
	unsigned int way;

	for (way = 0; way < mips_cpu.dcache.ways; way++) {
		start = page + way*waystep;
		while(start < end) {
			cache_unroll(start,Index_Writeback_Inv_D);
			start += dc_lsize;
		}
	}
}

static inline void blast_icache(void)
{
	unsigned long start = KSEG0;
	unsigned long end = (start + icache_size);

	while(start < end) {
		cache_unroll(start,Index_Invalidate_I);
		start += ic_lsize;
	}
}

static inline void blast_icache_page(unsigned long page)
{
	unsigned long start = page;
	unsigned long end = (start + PAGE_SIZE);

	while(start < end) {
		cache_unroll(start,Hit_Invalidate_I);
		start += ic_lsize;
	}
}

static inline void blast_icache_page_indexed(unsigned long page)
{
	unsigned long start;
	unsigned long end = (page + PAGE_SIZE);
	unsigned long waystep = icache_size/mips_cpu.icache.ways;
	unsigned int way;

	for (way = 0; way < mips_cpu.icache.ways; way++) {
		start = page + way*waystep;
		while(start < end) {
			cache_unroll(start,Index_Invalidate_I);
			start += ic_lsize;
		}
	}
}

static inline void blast_scache(void)
{
	unsigned long start = KSEG0;
	unsigned long end = KSEG0 + scache_size;

	while(start < end) {
		cache_unroll(start,Index_Writeback_Inv_SD);
		start += sc_lsize;
	}
}

static inline void blast_scache_page(unsigned long page)
{
	unsigned long start = page;
	unsigned long end = page + PAGE_SIZE;

	while(start < end) {
		cache_unroll(start,Hit_Writeback_Inv_SD);
		start += sc_lsize;
	}
}

static inline void blast_scache_page_indexed(unsigned long page)
{
	unsigned long start;
	unsigned long end = (page + PAGE_SIZE);
	unsigned long waystep = scache_size/mips_cpu.scache.ways;
	unsigned int way;

	for (way = 0; way < mips_cpu.scache.ways; way++) {
		start = page + way*waystep;
		while(start < end) {
			cache_unroll(start,Index_Writeback_Inv_SD);
			start += sc_lsize;
		}
	}
}

#endif /* !(_MIPS_R4KCACHE_H) */

--------------63CEFDDE1EAEF4F9A52D6AA8--


From carstenl@mips.com Wed Dec  4 13:53:55 2002
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Date: Wed, 04 Dec 2002 13:53:29 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: MIPS16 patch in unaligned.c
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--------------73DC21F3D4A65EF8B07A6456
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The attached patch make sure we don't try to emulate load and stores,
when running in MIPS16 mode on CPUs, which support MIPS16.
Without this patch the kernel crashes, if running something nasty like
crashme on a CPU, which support MIPS16.

/Carsten


--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



--------------73DC21F3D4A65EF8B07A6456
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Index: arch/mips/kernel/unaligned.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/kernel/unaligned.c,v
retrieving revision 1.15.2.7
diff -u -r1.15.2.7 unaligned.c
--- arch/mips/kernel/unaligned.c	7 Nov 2002 23:50:11 -0000	1.15.2.7
+++ arch/mips/kernel/unaligned.c	4 Dec 2002 12:37:38 -0000
@@ -494,10 +494,10 @@
 
 	/*
 	 * Did we catch a fault trying to load an instruction?
-	 * This also catches attempts to activate MIPS16 code on
-	 * CPUs which don't support it.
+	 * Or are we running in MIPS16 mode?
 	 */
-	if (regs->cp0_badvaddr == regs->cp0_epc)
+	if ((regs->cp0_badvaddr == regs->cp0_epc) ||
+	    (regs->cp0_epc & 0x1))
 		goto sigbus;
 
 	pc = regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) ? 4 : 0);
Index: arch/mips64/kernel/unaligned.c
===================================================================
RCS file: /home/cvs/linux/arch/mips64/kernel/unaligned.c,v
retrieving revision 1.6.2.6
diff -u -r1.6.2.6 unaligned.c
--- arch/mips64/kernel/unaligned.c	7 Nov 2002 23:50:11 -0000	1.6.2.6
+++ arch/mips64/kernel/unaligned.c	4 Dec 2002 12:37:40 -0000
@@ -494,10 +494,10 @@
 
 	/*
 	 * Did we catch a fault trying to load an instruction?
-	 * This also catches attempts to activate MIPS16 code on
-	 * CPUs which don't support it.
+	 * Or are we running in MIPS16 mode?
 	 */
-	if (regs->cp0_badvaddr == regs->cp0_epc)
+	if ((regs->cp0_badvaddr == regs->cp0_epc) ||
+	    (regs->cp0_epc & 0x1))
 		goto sigbus;
 
 	pc = regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) ? 4 : 0);

--------------73DC21F3D4A65EF8B07A6456--


From kevink@mips.com Wed Dec  4 14:02:40 2002
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From: "Kevin D. Kissell" <kevink@mips.com>
To: "Carsten Langgaard" <carstenl@mips.com>,
	<linux-mips@linux-mips.org>, "Jun Sun" <jsun@mvista.com>
References: <20021203224504.B13437@mvista.com> <007501c29b78$f34680e0$10eca8c0@grendel> <3DEDD414.3854664F@mips.com> <3DEDE537.CD58AD8F@mips.com>
Subject: Re: possible Malta 4Kc cache problem ...
Date: Wed, 4 Dec 2002 14:06:23 +0100
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I think that Carsten's patch (or equivalent) should certainly be
applied to the main tree, but I wonder how relevant it is here.
The flushes associated with trampolines don't do indexed
flush operations, do they?  I don't have a 4Kc platform at
hand, but I think that Jun Sun *may* have found a better
way to get at the other problem I was referring to, which
we rarely saw on non-superscalar issue CPUs, and which
seems to be masked by an otherwise superfluous flush of 
the Icache that was added to the latest versions of break_cow().
If Carsten's patch solves the problem without applying that
other update, I'd want to know that.  If it *doesn't*, I'd be
really interested to know if, by any chance, there is a
corelation between failures of Jun Sun's test and the incidence
of page faults on the CACHE op in protected_icache_invalidate_line().

            Kevin K.

----- Original Message ----- 
From: "Carsten Langgaard" <carstenl@mips.com>
To: "Kevin D. Kissell" <kevink@mips.com>; <linux-mips@linux-mips.org>; "Jun Sun" <jsun@mvista.com>
Sent: Wednesday, December 04, 2002 12:21 PM
Subject: Re: possible Malta 4Kc cache problem ...


> I just noticed that the patch I send (I don't know how long ago), hasn't made it
> into the CVS tree.
> So there is a potentially hole in the indexed flushes, which might only flush one
> of the cache ways.
> 
> Please try the mips32_cache.h, I have attached.
> 
> /Carsten
> 
> 
> 
> Carsten Langgaard wrote:
> 
> > I have just tried your test on a 4Kc and I see no problems.
> > However I'm running on our internal kernel sources, and as Kevin mention we have
> > changed a fixed a few things in this area.
> > As Kevin also mention it sure look more like a I-cache invalidation problem,
> > rather than a D-cache flush problem, as the 4Kc has a write-through cache.
> > One think you could try, is our latest kernel release. You can find it here:
> > ftp://ftp.mips.com/pub/linux/mips/kernel/2.4/images/
> >
> > /Carsten
> >
> > "Kevin D. Kissell" wrote:
> >
> > > > I attached the test case.  Untar it.  Type 'make' and run 'a.out'.
> > > >
> > > > If the test fails you will see a print-out.  Otherwise you see nothing.
> > > >
> > > > It does not always fail.  But if it fails, it is usually pretty consistent.
> > > > Try a few times.  Moving source tree to a different directory may cause
> > > > the symptom appear or disappear.
> > > >
> > > > I spent quite some time to trace this problem, and came to suspect
> > > > there might be a hardware problem.
> > > >
> > > > The problem involves emulating a "lw" instruction in cp1 branch delay
> > > > slot, which needs to  set up trampoline in user stack.  The net effect
> > > > looks as if the icache line or dcache line is not flushed properly.
> > > >
> > > > Using gdb/kgdb, printf or printk in any useful places would hide the bug.
> > > >
> > > > I did find a smaller part of the problem.  flush_cache_sigtramp for
> > > > MIPS32 (4Kc) calls protected_writeback_dcache_line in mips32_cache.h.
> > > > It uses Hit_Writeback_D, and the 4Kc mannual says it is not implemented
> > > > and executed as no-op (*ick*).
> > >
> > > Which version of the 4Kc manual are you looking at?  I'm looking
> > > at a very recent version of the 4Kc Software User's Manual
> > > (version 1.17, dated September 25, 2002), and it only shows
> > > Hit_Writeback_D to be invalid for *secondary and teritary*
> > > caches, which makes sense, since the 4KSc doesn't have any.
> > >
> > > > Even after fixing this, I still see the problem happening.
> > >
> > > That's not too surprising.  The 4Kc D-cache is write-through,
> > > so if you're really seeing a problem with trampolimes, it is almost
> > > certain to be a problem with the Icache invalidation, not the
> > > Dcache flush.
> > >
> > > > If you replace flush_cache_sigtramp() with flush_cache_all(), symptom
> > > > would disppear.
> > >
> > > Which again would make sense if there's a problem on
> > > the icache side of the flush.  Oddly enough, we've seen
> > > some glitches on other CPUs with other kernels that
> > > might have been explicable by failures of protected_flush_icache_line(),
> > > but we never found a problem with it, and a higher-level
> > > memory management patch made the problem go away.
> > > Makes me wonder if we shouldn't look at it again, more
> > > closely.  Is there any possibility that the logic for restarting
> > > a protected kernel access following a page fault will somehow
> > > screw up on CACHE instructions, as opposed to the loads
> > > and stores for which the code was originally written?
> > >
> > > > Several of my tests seem to suggest it is the icache that did not
> > > > get flushed (or updated) properly.
> > > >
> > > > Not re-producible on other MIPS boards.  At least so far.
> > > >
> > > > Does anybody with more knowledge about 4Kc have any clues here?
> > > >
> > > > Thanks.
> > > >
> > > > Jun
> >
> > --
> > _    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
> > |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> > | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> >   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> >                    Denmark            http://www.mips.com
> 
> --
> _    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark             http://www.mips.com
> 
> 
> 


--------------------------------------------------------------------------------


> /*
>  * mips32_cache.h
>  *
>  * Carsten Langgaard, carstenl@mips.com
>  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
>  *
>  * ########################################################################
>  *
>  *  This program is free software; you can distribute it and/or modify it
>  *  under the terms of the GNU General Public License (Version 2) as
>  *  published by the Free Software Foundation.
>  *
>  *  This program is distributed in the hope it will be useful, but WITHOUT
>  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
>  *  for more details.
>  *
>  *  You should have received a copy of the GNU General Public License along
>  *  with this program; if not, write to the Free Software Foundation, Inc.,
>  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
>  *
>  * ########################################################################
>  *
>  * Inline assembly cache operations.
>  * 
>  * This file is the original r4cache.c file with modification that makes the
>  * cache handling more generic.
>  *
>  * FIXME: Handle split L2 caches.
>  *
>  */
> #ifndef _MIPS_R4KCACHE_H
> #define _MIPS_R4KCACHE_H
> 
> #include <asm/asm.h>
> #include <asm/cacheops.h>
> 
> static inline void flush_icache_line_indexed(unsigned long addr)
> {
> unsigned long waystep = icache_size/mips_cpu.icache.ways;
> unsigned int way;
> 
> for (way = 0; way < mips_cpu.icache.ways; way++)
> {
> __asm__ __volatile__(
> ".set noreorder\n\t"
> ".set mips3\n\t"
> "cache %1, (%0)\n\t"
> ".set mips0\n\t"
> ".set reorder"
> :
> : "r" (addr),
> "i" (Index_Invalidate_I));
> 
> addr += waystep;
> }
> }
> 
> static inline void flush_dcache_line_indexed(unsigned long addr)
> {
> unsigned long waystep = dcache_size/mips_cpu.dcache.ways;
> unsigned int way;
> 
> for (way = 0; way < mips_cpu.dcache.ways; way++)
> {
> __asm__ __volatile__(
> ".set noreorder\n\t"
> ".set mips3\n\t"
> "cache %1, (%0)\n\t"
> ".set mips0\n\t"
> ".set reorder"
> :
> : "r" (addr),
> "i" (Index_Writeback_Inv_D));
> 
> addr += waystep;
> }
> }
> 
> static inline void flush_scache_line_indexed(unsigned long addr)
> {
> unsigned long waystep = scache_size/mips_cpu.scache.ways;
> unsigned int way;
> 
> for (way = 0; way < mips_cpu.scache.ways; way++)
> {
> __asm__ __volatile__(
> ".set noreorder\n\t"
> ".set mips3\n\t"
> "cache %1, (%0)\n\t"
> ".set mips0\n\t"
> ".set reorder"
> :
> : "r" (addr),
> "i" (Index_Writeback_Inv_SD));
> 
> addr += waystep;
> }
> }
> 
> static inline void flush_icache_line(unsigned long addr)
> {
> __asm__ __volatile__(
> ".set noreorder\n\t"
> ".set mips3\n\t"
> "cache %1, (%0)\n\t"
> ".set mips0\n\t"
> ".set reorder"
> :
> : "r" (addr),
>   "i" (Hit_Invalidate_I));
> }
> 
> static inline void flush_dcache_line(unsigned long addr)
> {
> __asm__ __volatile__(
> ".set noreorder\n\t"
> ".set mips3\n\t"
> "cache %1, (%0)\n\t"
> ".set mips0\n\t"
> ".set reorder"
> :
> : "r" (addr),
>   "i" (Hit_Writeback_Inv_D));
> }
> 
> static inline void invalidate_dcache_line(unsigned long addr)
> {
> __asm__ __volatile__(
> ".set noreorder\n\t"
> ".set mips3\n\t"
> "cache %1, (%0)\n\t"
> ".set mips0\n\t"
> ".set reorder"
> :
> : "r" (addr),
>   "i" (Hit_Invalidate_D));
> }
> 
> static inline void invalidate_scache_line(unsigned long addr)
> {
> __asm__ __volatile__(
> ".set noreorder\n\t"
> ".set mips3\n\t"
> "cache %1, (%0)\n\t"
> ".set mips0\n\t"
> ".set reorder"
> :
> : "r" (addr),
>   "i" (Hit_Invalidate_SD));
> }
> 
> static inline void flush_scache_line(unsigned long addr)
> {
> __asm__ __volatile__(
> ".set noreorder\n\t"
> ".set mips3\n\t"
> "cache %1, (%0)\n\t"
> ".set mips0\n\t"
> ".set reorder"
> :
> : "r" (addr),
>   "i" (Hit_Writeback_Inv_SD));
> }
> 
> /*
>  * The next two are for badland addresses like signal trampolines.
>  */
> static inline void protected_flush_icache_line(unsigned long addr)
> {
> __asm__ __volatile__(
> ".set noreorder\n\t"
> ".set mips3\n"
> "1:\tcache %1,(%0)\n"
> "2:\t.set mips0\n\t"
> ".set reorder\n\t"
> ".section\t__ex_table,\"a\"\n\t"
> STR(PTR)"\t1b,2b\n\t"
> ".previous"
> :
> : "r" (addr),
>   "i" (Hit_Invalidate_I));
> }
> 
> static inline void protected_writeback_dcache_line(unsigned long addr)
> {
> __asm__ __volatile__(
> ".set noreorder\n\t"
> ".set mips3\n"
> "1:\tcache %1,(%0)\n"
> "2:\t.set mips0\n\t"
> ".set reorder\n\t"
> ".section\t__ex_table,\"a\"\n\t"
> STR(PTR)"\t1b,2b\n\t"
> ".previous"
> :
> : "r" (addr),
>   "i" (Hit_Writeback_D));
> }
> 
> #define cache_unroll(base,op)         \
> __asm__ __volatile__("          \
> .set noreorder;         \
> .set mips3;         \
>                 cache %1, (%0);                 \
> .set mips0; \
> .set reorder" \
> : \
> : "r" (base), \
>   "i" (op));
> 
> 
> static inline void blast_dcache(void)
> {
> unsigned long start = KSEG0;
> unsigned long end = (start + dcache_size);
> 
> while(start < end) {
> cache_unroll(start,Index_Writeback_Inv_D);
> start += dc_lsize;
> }
> }
> 
> static inline void blast_dcache_page(unsigned long page)
> {
> unsigned long start = page;
> unsigned long end = (start + PAGE_SIZE);
> 
> while(start < end) {
> cache_unroll(start,Hit_Writeback_Inv_D);
> start += dc_lsize;
> }
> }
> 
> static inline void blast_dcache_page_indexed(unsigned long page)
> {
> unsigned long start;
> unsigned long end = (page + PAGE_SIZE);
> unsigned long waystep = dcache_size/mips_cpu.dcache.ways;
> unsigned int way;
> 
> for (way = 0; way < mips_cpu.dcache.ways; way++) {
> start = page + way*waystep;
> while(start < end) {
> cache_unroll(start,Index_Writeback_Inv_D);
> start += dc_lsize;
> }
> }
> }
> 
> static inline void blast_icache(void)
> {
> unsigned long start = KSEG0;
> unsigned long end = (start + icache_size);
> 
> while(start < end) {
> cache_unroll(start,Index_Invalidate_I);
> start += ic_lsize;
> }
> }
> 
> static inline void blast_icache_page(unsigned long page)
> {
> unsigned long start = page;
> unsigned long end = (start + PAGE_SIZE);
> 
> while(start < end) {
> cache_unroll(start,Hit_Invalidate_I);
> start += ic_lsize;
> }
> }
> 
> static inline void blast_icache_page_indexed(unsigned long page)
> {
> unsigned long start;
> unsigned long end = (page + PAGE_SIZE);
> unsigned long waystep = icache_size/mips_cpu.icache.ways;
> unsigned int way;
> 
> for (way = 0; way < mips_cpu.icache.ways; way++) {
> start = page + way*waystep;
> while(start < end) {
> cache_unroll(start,Index_Invalidate_I);
> start += ic_lsize;
> }
> }
> }
> 
> static inline void blast_scache(void)
> {
> unsigned long start = KSEG0;
> unsigned long end = KSEG0 + scache_size;
> 
> while(start < end) {
> cache_unroll(start,Index_Writeback_Inv_SD);
> start += sc_lsize;
> }
> }
> 
> static inline void blast_scache_page(unsigned long page)
> {
> unsigned long start = page;
> unsigned long end = page + PAGE_SIZE;
> 
> while(start < end) {
> cache_unroll(start,Hit_Writeback_Inv_SD);
> start += sc_lsize;
> }
> }
> 
> static inline void blast_scache_page_indexed(unsigned long page)
> {
> unsigned long start;
> unsigned long end = (page + PAGE_SIZE);
> unsigned long waystep = scache_size/mips_cpu.scache.ways;
> unsigned int way;
> 
> for (way = 0; way < mips_cpu.scache.ways; way++) {
> start = page + way*waystep;
> while(start < end) {
> cache_unroll(start,Index_Writeback_Inv_SD);
> start += sc_lsize;
> }
> }
> }
> 
> #endif /* !(_MIPS_R4KCACHE_H) */
> 

From ralf@linux-mips.org Wed Dec  4 14:05:07 2002
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From: Ralf Baechle <ralf@linux-mips.org>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: Carsten Langgaard <carstenl@mips.com>, linux-mips@linux-mips.org
Subject: Re: Latest sources from CVS.
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On Wed, Dec 04, 2002 at 10:09:54AM +0100, Kevin D. Kissell wrote:

> > It look like you are only able to compile the kernel, if you got a
> > MIPS32/MIPS64 compliant compiler.

Assembler.  I'm building with egcs 1.1.2 + binutils 1.13 btw.

> I mean, sure, we'd like to move more people toward SDE, 
> but "force" is putting it a bit strongly!  And if those directives
> are really being used unconditionally, I worry that the code
> being generated is likewise emitting MIPS32 instructions
> that won't work on the "ghost fleet" of abandoned workstations
> now running Linux on R4K/R5K CPUs.

It isn't.  We've been dragging around .word stuff in our code for years
and it was time to clean tht mess.  Further we had stuff like:

  read_32bit_cp0_register(CP0_STATUS)

which is a ridiculous long macro name for something that just expands
into a single machine instruction; the macro also didn't provide for
access to another cop0 register set than set 0.  For a few TLB-related
functions we already had functions with shorter names, so two names for
doing the one and same thing.  Another problem was that the name did
already hardcode the size of the access intothe code, so the user of
those macros had to know if it was 32-bit or 64-bit.  In short it was
time to clean the mess and as it seemed that pretty much everybody was
already having a MIPS32 / MIPS64 assembler, simply always emitting a
.set mips32 / .set mips64 seemed the right thing.  That's necessary even
for accessing cop0 set 0 because gas rejects something like

  mfc0 $2, $12, 0

unless running in MIPS32 or MIPS64 mode - even though the generated opcode
is perfectly valid for MIPS I.  The 64-bit kernel was another reason for
me to go with the assumption of rather current binutils - and I'd like
to make the same assumptions on tools versions for both 32-bit and 64-bit
versions.

Anyway, it seems that my assumptions about tools versions were a bit too
agressive, so I'm going to kludge things a bit for pre-MIPS32/MIPS64
assemblers.

Deprecating support for MIPS I - IV legacy CPUs is definately not something
I'd support.  Not before x86 has died out that is ;-)

  Ralf

From carstenl@mips.com Wed Dec  4 14:14:45 2002
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From: Carsten Langgaard <carstenl@mips.com>
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Subject: Re: possible Malta 4Kc cache problem ...
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"Kevin D. Kissell" wrote:

> I think that Carsten's patch (or equivalent) should certainly be
> applied to the main tree, but I wonder how relevant it is here.
> The flushes associated with trampolines don't do indexed
> flush operations, do they?

True, but are we sure that it's the trampoline that's the problem here.


>  I don't have a 4Kc platform at
> hand, but I think that Jun Sun *may* have found a better
> way to get at the other problem I was referring to, which
> we rarely saw on non-superscalar issue CPUs, and which
> seems to be masked by an otherwise superfluous flush of
> the Icache that was added to the latest versions of break_cow().
> If Carsten's patch solves the problem without applying that
> other update, I'd want to know that.  If it *doesn't*, I'd be
> really interested to know if, by any chance, there is a
> corelation between failures of Jun Sun's test and the incidence
> of page faults on the CACHE op in protected_icache_invalidate_line().
>
>             Kevin K.
>
> ----- Original Message -----
> From: "Carsten Langgaard" <carstenl@mips.com>
> To: "Kevin D. Kissell" <kevink@mips.com>; <linux-mips@linux-mips.org>; "Jun Sun" <jsun@mvista.com>
> Sent: Wednesday, December 04, 2002 12:21 PM
> Subject: Re: possible Malta 4Kc cache problem ...
>
> > I just noticed that the patch I send (I don't know how long ago), hasn't made it
> > into the CVS tree.
> > So there is a potentially hole in the indexed flushes, which might only flush one
> > of the cache ways.
> >
> > Please try the mips32_cache.h, I have attached.
> >
> > /Carsten
> >
> >
> >
> > Carsten Langgaard wrote:
> >
> > > I have just tried your test on a 4Kc and I see no problems.
> > > However I'm running on our internal kernel sources, and as Kevin mention we have
> > > changed a fixed a few things in this area.
> > > As Kevin also mention it sure look more like a I-cache invalidation problem,
> > > rather than a D-cache flush problem, as the 4Kc has a write-through cache.
> > > One think you could try, is our latest kernel release. You can find it here:
> > > ftp://ftp.mips.com/pub/linux/mips/kernel/2.4/images/
> > >
> > > /Carsten
> > >
> > > "Kevin D. Kissell" wrote:
> > >
> > > > > I attached the test case.  Untar it.  Type 'make' and run 'a.out'.
> > > > >
> > > > > If the test fails you will see a print-out.  Otherwise you see nothing.
> > > > >
> > > > > It does not always fail.  But if it fails, it is usually pretty consistent.
> > > > > Try a few times.  Moving source tree to a different directory may cause
> > > > > the symptom appear or disappear.
> > > > >
> > > > > I spent quite some time to trace this problem, and came to suspect
> > > > > there might be a hardware problem.
> > > > >
> > > > > The problem involves emulating a "lw" instruction in cp1 branch delay
> > > > > slot, which needs to  set up trampoline in user stack.  The net effect
> > > > > looks as if the icache line or dcache line is not flushed properly.
> > > > >
> > > > > Using gdb/kgdb, printf or printk in any useful places would hide the bug.
> > > > >
> > > > > I did find a smaller part of the problem.  flush_cache_sigtramp for
> > > > > MIPS32 (4Kc) calls protected_writeback_dcache_line in mips32_cache.h.
> > > > > It uses Hit_Writeback_D, and the 4Kc mannual says it is not implemented
> > > > > and executed as no-op (*ick*).
> > > >
> > > > Which version of the 4Kc manual are you looking at?  I'm looking
> > > > at a very recent version of the 4Kc Software User's Manual
> > > > (version 1.17, dated September 25, 2002), and it only shows
> > > > Hit_Writeback_D to be invalid for *secondary and teritary*
> > > > caches, which makes sense, since the 4KSc doesn't have any.
> > > >
> > > > > Even after fixing this, I still see the problem happening.
> > > >
> > > > That's not too surprising.  The 4Kc D-cache is write-through,
> > > > so if you're really seeing a problem with trampolimes, it is almost
> > > > certain to be a problem with the Icache invalidation, not the
> > > > Dcache flush.
> > > >
> > > > > If you replace flush_cache_sigtramp() with flush_cache_all(), symptom
> > > > > would disppear.
> > > >
> > > > Which again would make sense if there's a problem on
> > > > the icache side of the flush.  Oddly enough, we've seen
> > > > some glitches on other CPUs with other kernels that
> > > > might have been explicable by failures of protected_flush_icache_line(),
> > > > but we never found a problem with it, and a higher-level
> > > > memory management patch made the problem go away.
> > > > Makes me wonder if we shouldn't look at it again, more
> > > > closely.  Is there any possibility that the logic for restarting
> > > > a protected kernel access following a page fault will somehow
> > > > screw up on CACHE instructions, as opposed to the loads
> > > > and stores for which the code was originally written?
> > > >
> > > > > Several of my tests seem to suggest it is the icache that did not
> > > > > get flushed (or updated) properly.
> > > > >
> > > > > Not re-producible on other MIPS boards.  At least so far.
> > > > >
> > > > > Does anybody with more knowledge about 4Kc have any clues here?
> > > > >
> > > > > Thanks.
> > > > >
> > > > > Jun
> > >
> > > --
> > > _    _ ____  ___   Carsten Langgaard Mailto:carstenl@mips.com
> > > |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> > > | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> > >   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> > >                    Denmark           http://www.mips.com
> >
> > --
> > _    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
> > |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> > | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> >   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> >                    Denmark            http://www.mips.com
> >
> >
> >
>
> --------------------------------------------------------------------------------
>
> > /*
> >  * mips32_cache.h
> >  *
> >  * Carsten Langgaard, carstenl@mips.com
> >  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
> >  *
> >  * ########################################################################
> >  *
> >  *  This program is free software; you can distribute it and/or modify it
> >  *  under the terms of the GNU General Public License (Version 2) as
> >  *  published by the Free Software Foundation.
> >  *
> >  *  This program is distributed in the hope it will be useful, but WITHOUT
> >  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> >  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> >  *  for more details.
> >  *
> >  *  You should have received a copy of the GNU General Public License along
> >  *  with this program; if not, write to the Free Software Foundation, Inc.,
> >  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
> >  *
> >  * ########################################################################
> >  *
> >  * Inline assembly cache operations.
> >  *
> >  * This file is the original r4cache.c file with modification that makes the
> >  * cache handling more generic.
> >  *
> >  * FIXME: Handle split L2 caches.
> >  *
> >  */
> > #ifndef _MIPS_R4KCACHE_H
> > #define _MIPS_R4KCACHE_H
> >
> > #include <asm/asm.h>
> > #include <asm/cacheops.h>
> >
> > static inline void flush_icache_line_indexed(unsigned long addr)
> > {
> > unsigned long waystep = icache_size/mips_cpu.icache.ways;
> > unsigned int way;
> >
> > for (way = 0; way < mips_cpu.icache.ways; way++)
> > {
> > __asm__ __volatile__(
> > ".set noreorder\n\t"
> > ".set mips3\n\t"
> > "cache %1, (%0)\n\t"
> > ".set mips0\n\t"
> > ".set reorder"
> > :
> > : "r" (addr),
> > "i" (Index_Invalidate_I));
> >
> > addr += waystep;
> > }
> > }
> >
> > static inline void flush_dcache_line_indexed(unsigned long addr)
> > {
> > unsigned long waystep = dcache_size/mips_cpu.dcache.ways;
> > unsigned int way;
> >
> > for (way = 0; way < mips_cpu.dcache.ways; way++)
> > {
> > __asm__ __volatile__(
> > ".set noreorder\n\t"
> > ".set mips3\n\t"
> > "cache %1, (%0)\n\t"
> > ".set mips0\n\t"
> > ".set reorder"
> > :
> > : "r" (addr),
> > "i" (Index_Writeback_Inv_D));
> >
> > addr += waystep;
> > }
> > }
> >
> > static inline void flush_scache_line_indexed(unsigned long addr)
> > {
> > unsigned long waystep = scache_size/mips_cpu.scache.ways;
> > unsigned int way;
> >
> > for (way = 0; way < mips_cpu.scache.ways; way++)
> > {
> > __asm__ __volatile__(
> > ".set noreorder\n\t"
> > ".set mips3\n\t"
> > "cache %1, (%0)\n\t"
> > ".set mips0\n\t"
> > ".set reorder"
> > :
> > : "r" (addr),
> > "i" (Index_Writeback_Inv_SD));
> >
> > addr += waystep;
> > }
> > }
> >
> > static inline void flush_icache_line(unsigned long addr)
> > {
> > __asm__ __volatile__(
> > ".set noreorder\n\t"
> > ".set mips3\n\t"
> > "cache %1, (%0)\n\t"
> > ".set mips0\n\t"
> > ".set reorder"
> > :
> > : "r" (addr),
> >   "i" (Hit_Invalidate_I));
> > }
> >
> > static inline void flush_dcache_line(unsigned long addr)
> > {
> > __asm__ __volatile__(
> > ".set noreorder\n\t"
> > ".set mips3\n\t"
> > "cache %1, (%0)\n\t"
> > ".set mips0\n\t"
> > ".set reorder"
> > :
> > : "r" (addr),
> >   "i" (Hit_Writeback_Inv_D));
> > }
> >
> > static inline void invalidate_dcache_line(unsigned long addr)
> > {
> > __asm__ __volatile__(
> > ".set noreorder\n\t"
> > ".set mips3\n\t"
> > "cache %1, (%0)\n\t"
> > ".set mips0\n\t"
> > ".set reorder"
> > :
> > : "r" (addr),
> >   "i" (Hit_Invalidate_D));
> > }
> >
> > static inline void invalidate_scache_line(unsigned long addr)
> > {
> > __asm__ __volatile__(
> > ".set noreorder\n\t"
> > ".set mips3\n\t"
> > "cache %1, (%0)\n\t"
> > ".set mips0\n\t"
> > ".set reorder"
> > :
> > : "r" (addr),
> >   "i" (Hit_Invalidate_SD));
> > }
> >
> > static inline void flush_scache_line(unsigned long addr)
> > {
> > __asm__ __volatile__(
> > ".set noreorder\n\t"
> > ".set mips3\n\t"
> > "cache %1, (%0)\n\t"
> > ".set mips0\n\t"
> > ".set reorder"
> > :
> > : "r" (addr),
> >   "i" (Hit_Writeback_Inv_SD));
> > }
> >
> > /*
> >  * The next two are for badland addresses like signal trampolines.
> >  */
> > static inline void protected_flush_icache_line(unsigned long addr)
> > {
> > __asm__ __volatile__(
> > ".set noreorder\n\t"
> > ".set mips3\n"
> > "1:\tcache %1,(%0)\n"
> > "2:\t.set mips0\n\t"
> > ".set reorder\n\t"
> > ".section\t__ex_table,\"a\"\n\t"
> > STR(PTR)"\t1b,2b\n\t"
> > ".previous"
> > :
> > : "r" (addr),
> >   "i" (Hit_Invalidate_I));
> > }
> >
> > static inline void protected_writeback_dcache_line(unsigned long addr)
> > {
> > __asm__ __volatile__(
> > ".set noreorder\n\t"
> > ".set mips3\n"
> > "1:\tcache %1,(%0)\n"
> > "2:\t.set mips0\n\t"
> > ".set reorder\n\t"
> > ".section\t__ex_table,\"a\"\n\t"
> > STR(PTR)"\t1b,2b\n\t"
> > ".previous"
> > :
> > : "r" (addr),
> >   "i" (Hit_Writeback_D));
> > }
> >
> > #define cache_unroll(base,op)         \
> > __asm__ __volatile__("          \
> > .set noreorder;         \
> > .set mips3;         \
> >                 cache %1, (%0);                 \
> > .set mips0; \
> > .set reorder" \
> > : \
> > : "r" (base), \
> >   "i" (op));
> >
> >
> > static inline void blast_dcache(void)
> > {
> > unsigned long start = KSEG0;
> > unsigned long end = (start + dcache_size);
> >
> > while(start < end) {
> > cache_unroll(start,Index_Writeback_Inv_D);
> > start += dc_lsize;
> > }
> > }
> >
> > static inline void blast_dcache_page(unsigned long page)
> > {
> > unsigned long start = page;
> > unsigned long end = (start + PAGE_SIZE);
> >
> > while(start < end) {
> > cache_unroll(start,Hit_Writeback_Inv_D);
> > start += dc_lsize;
> > }
> > }
> >
> > static inline void blast_dcache_page_indexed(unsigned long page)
> > {
> > unsigned long start;
> > unsigned long end = (page + PAGE_SIZE);
> > unsigned long waystep = dcache_size/mips_cpu.dcache.ways;
> > unsigned int way;
> >
> > for (way = 0; way < mips_cpu.dcache.ways; way++) {
> > start = page + way*waystep;
> > while(start < end) {
> > cache_unroll(start,Index_Writeback_Inv_D);
> > start += dc_lsize;
> > }
> > }
> > }
> >
> > static inline void blast_icache(void)
> > {
> > unsigned long start = KSEG0;
> > unsigned long end = (start + icache_size);
> >
> > while(start < end) {
> > cache_unroll(start,Index_Invalidate_I);
> > start += ic_lsize;
> > }
> > }
> >
> > static inline void blast_icache_page(unsigned long page)
> > {
> > unsigned long start = page;
> > unsigned long end = (start + PAGE_SIZE);
> >
> > while(start < end) {
> > cache_unroll(start,Hit_Invalidate_I);
> > start += ic_lsize;
> > }
> > }
> >
> > static inline void blast_icache_page_indexed(unsigned long page)
> > {
> > unsigned long start;
> > unsigned long end = (page + PAGE_SIZE);
> > unsigned long waystep = icache_size/mips_cpu.icache.ways;
> > unsigned int way;
> >
> > for (way = 0; way < mips_cpu.icache.ways; way++) {
> > start = page + way*waystep;
> > while(start < end) {
> > cache_unroll(start,Index_Invalidate_I);
> > start += ic_lsize;
> > }
> > }
> > }
> >
> > static inline void blast_scache(void)
> > {
> > unsigned long start = KSEG0;
> > unsigned long end = KSEG0 + scache_size;
> >
> > while(start < end) {
> > cache_unroll(start,Index_Writeback_Inv_SD);
> > start += sc_lsize;
> > }
> > }
> >
> > static inline void blast_scache_page(unsigned long page)
> > {
> > unsigned long start = page;
> > unsigned long end = page + PAGE_SIZE;
> >
> > while(start < end) {
> > cache_unroll(start,Hit_Writeback_Inv_SD);
> > start += sc_lsize;
> > }
> > }
> >
> > static inline void blast_scache_page_indexed(unsigned long page)
> > {
> > unsigned long start;
> > unsigned long end = (page + PAGE_SIZE);
> > unsigned long waystep = scache_size/mips_cpu.scache.ways;
> > unsigned int way;
> >
> > for (way = 0; way < mips_cpu.scache.ways; way++) {
> > start = page + way*waystep;
> > while(start < end) {
> > cache_unroll(start,Index_Writeback_Inv_SD);
> > start += sc_lsize;
> > }
> > }
> > }
> >
> > #endif /* !(_MIPS_R4KCACHE_H) */
> >

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From carstenl@mips.com Wed Dec  4 14:29:04 2002
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Date: Wed, 04 Dec 2002 14:28:54 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: "Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org,
	Jun Sun <jsun@mvista.com>
Subject: Re: possible Malta 4Kc cache problem ...
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Carsten Langgaard wrote:

> "Kevin D. Kissell" wrote:
>
> > I think that Carsten's patch (or equivalent) should certainly be
> > applied to the main tree, but I wonder how relevant it is here.
> > The flushes associated with trampolines don't do indexed
> > flush operations, do they?
>

Sorry, my answer was probably not very clear.
The trampoline flushes do not do indexed flush, but it use hit-writeback-invalidate for the D-cache and
hit-invalidate for the I-cache.


>
> True, but are we sure that it's the trampoline that's the problem here.
>
> >  I don't have a 4Kc platform at
> > hand, but I think that Jun Sun *may* have found a better
> > way to get at the other problem I was referring to, which
> > we rarely saw on non-superscalar issue CPUs, and which
> > seems to be masked by an otherwise superfluous flush of
> > the Icache that was added to the latest versions of break_cow().
> > If Carsten's patch solves the problem without applying that
> > other update, I'd want to know that.  If it *doesn't*, I'd be
> > really interested to know if, by any chance, there is a
> > corelation between failures of Jun Sun's test and the incidence
> > of page faults on the CACHE op in protected_icache_invalidate_line().
> >
> >             Kevin K.
> >
> > ----- Original Message -----
> > From: "Carsten Langgaard" <carstenl@mips.com>
> > To: "Kevin D. Kissell" <kevink@mips.com>; <linux-mips@linux-mips.org>; "Jun Sun" <jsun@mvista.com>
> > Sent: Wednesday, December 04, 2002 12:21 PM
> > Subject: Re: possible Malta 4Kc cache problem ...
> >
> > > I just noticed that the patch I send (I don't know how long ago), hasn't made it
> > > into the CVS tree.
> > > So there is a potentially hole in the indexed flushes, which might only flush one
> > > of the cache ways.
> > >
> > > Please try the mips32_cache.h, I have attached.
> > >
> > > /Carsten
> > >
> > >
> > >
> > > Carsten Langgaard wrote:
> > >
> > > > I have just tried your test on a 4Kc and I see no problems.
> > > > However I'm running on our internal kernel sources, and as Kevin mention we have
> > > > changed a fixed a few things in this area.
> > > > As Kevin also mention it sure look more like a I-cache invalidation problem,
> > > > rather than a D-cache flush problem, as the 4Kc has a write-through cache.
> > > > One think you could try, is our latest kernel release. You can find it here:
> > > > ftp://ftp.mips.com/pub/linux/mips/kernel/2.4/images/
> > > >
> > > > /Carsten
> > > >
> > > > "Kevin D. Kissell" wrote:
> > > >
> > > > > > I attached the test case.  Untar it.  Type 'make' and run 'a.out'.
> > > > > >
> > > > > > If the test fails you will see a print-out.  Otherwise you see nothing.
> > > > > >
> > > > > > It does not always fail.  But if it fails, it is usually pretty consistent.
> > > > > > Try a few times.  Moving source tree to a different directory may cause
> > > > > > the symptom appear or disappear.
> > > > > >
> > > > > > I spent quite some time to trace this problem, and came to suspect
> > > > > > there might be a hardware problem.
> > > > > >
> > > > > > The problem involves emulating a "lw" instruction in cp1 branch delay
> > > > > > slot, which needs to  set up trampoline in user stack.  The net effect
> > > > > > looks as if the icache line or dcache line is not flushed properly.
> > > > > >
> > > > > > Using gdb/kgdb, printf or printk in any useful places would hide the bug.
> > > > > >
> > > > > > I did find a smaller part of the problem.  flush_cache_sigtramp for
> > > > > > MIPS32 (4Kc) calls protected_writeback_dcache_line in mips32_cache.h.
> > > > > > It uses Hit_Writeback_D, and the 4Kc mannual says it is not implemented
> > > > > > and executed as no-op (*ick*).
> > > > >
> > > > > Which version of the 4Kc manual are you looking at?  I'm looking
> > > > > at a very recent version of the 4Kc Software User's Manual
> > > > > (version 1.17, dated September 25, 2002), and it only shows
> > > > > Hit_Writeback_D to be invalid for *secondary and teritary*
> > > > > caches, which makes sense, since the 4KSc doesn't have any.
> > > > >
> > > > > > Even after fixing this, I still see the problem happening.
> > > > >
> > > > > That's not too surprising.  The 4Kc D-cache is write-through,
> > > > > so if you're really seeing a problem with trampolimes, it is almost
> > > > > certain to be a problem with the Icache invalidation, not the
> > > > > Dcache flush.
> > > > >
> > > > > > If you replace flush_cache_sigtramp() with flush_cache_all(), symptom
> > > > > > would disppear.
> > > > >
> > > > > Which again would make sense if there's a problem on
> > > > > the icache side of the flush.  Oddly enough, we've seen
> > > > > some glitches on other CPUs with other kernels that
> > > > > might have been explicable by failures of protected_flush_icache_line(),
> > > > > but we never found a problem with it, and a higher-level
> > > > > memory management patch made the problem go away.
> > > > > Makes me wonder if we shouldn't look at it again, more
> > > > > closely.  Is there any possibility that the logic for restarting
> > > > > a protected kernel access following a page fault will somehow
> > > > > screw up on CACHE instructions, as opposed to the loads
> > > > > and stores for which the code was originally written?
> > > > >
> > > > > > Several of my tests seem to suggest it is the icache that did not
> > > > > > get flushed (or updated) properly.
> > > > > >
> > > > > > Not re-producible on other MIPS boards.  At least so far.
> > > > > >
> > > > > > Does anybody with more knowledge about 4Kc have any clues here?
> > > > > >
> > > > > > Thanks.
> > > > > >
> > > > > > Jun
> > > >
> > > > --
> > > > _    _ ____  ___   Carsten Langgaard Mailto:carstenl@mips.com
> > > > |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> > > > | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> > > >   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> > > >                    Denmark           http://www.mips.com
> > >
> > > --
> > > _    _ ____  ___   Carsten Langgaard Mailto:carstenl@mips.com
> > > |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> > > | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> > >   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> > >                    Denmark           http://www.mips.com
> > >
> > >
> > >
> >
> > --------------------------------------------------------------------------------
> >
> > > /*
> > >  * mips32_cache.h
> > >  *
> > >  * Carsten Langgaard, carstenl@mips.com
> > >  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
> > >  *
> > >  * ########################################################################
> > >  *
> > >  *  This program is free software; you can distribute it and/or modify it
> > >  *  under the terms of the GNU General Public License (Version 2) as
> > >  *  published by the Free Software Foundation.
> > >  *
> > >  *  This program is distributed in the hope it will be useful, but WITHOUT
> > >  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > >  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> > >  *  for more details.
> > >  *
> > >  *  You should have received a copy of the GNU General Public License along
> > >  *  with this program; if not, write to the Free Software Foundation, Inc.,
> > >  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
> > >  *
> > >  * ########################################################################
> > >  *
> > >  * Inline assembly cache operations.
> > >  *
> > >  * This file is the original r4cache.c file with modification that makes the
> > >  * cache handling more generic.
> > >  *
> > >  * FIXME: Handle split L2 caches.
> > >  *
> > >  */
> > > #ifndef _MIPS_R4KCACHE_H
> > > #define _MIPS_R4KCACHE_H
> > >
> > > #include <asm/asm.h>
> > > #include <asm/cacheops.h>
> > >
> > > static inline void flush_icache_line_indexed(unsigned long addr)
> > > {
> > > unsigned long waystep = icache_size/mips_cpu.icache.ways;
> > > unsigned int way;
> > >
> > > for (way = 0; way < mips_cpu.icache.ways; way++)
> > > {
> > > __asm__ __volatile__(
> > > ".set noreorder\n\t"
> > > ".set mips3\n\t"
> > > "cache %1, (%0)\n\t"
> > > ".set mips0\n\t"
> > > ".set reorder"
> > > :
> > > : "r" (addr),
> > > "i" (Index_Invalidate_I));
> > >
> > > addr += waystep;
> > > }
> > > }
> > >
> > > static inline void flush_dcache_line_indexed(unsigned long addr)
> > > {
> > > unsigned long waystep = dcache_size/mips_cpu.dcache.ways;
> > > unsigned int way;
> > >
> > > for (way = 0; way < mips_cpu.dcache.ways; way++)
> > > {
> > > __asm__ __volatile__(
> > > ".set noreorder\n\t"
> > > ".set mips3\n\t"
> > > "cache %1, (%0)\n\t"
> > > ".set mips0\n\t"
> > > ".set reorder"
> > > :
> > > : "r" (addr),
> > > "i" (Index_Writeback_Inv_D));
> > >
> > > addr += waystep;
> > > }
> > > }
> > >
> > > static inline void flush_scache_line_indexed(unsigned long addr)
> > > {
> > > unsigned long waystep = scache_size/mips_cpu.scache.ways;
> > > unsigned int way;
> > >
> > > for (way = 0; way < mips_cpu.scache.ways; way++)
> > > {
> > > __asm__ __volatile__(
> > > ".set noreorder\n\t"
> > > ".set mips3\n\t"
> > > "cache %1, (%0)\n\t"
> > > ".set mips0\n\t"
> > > ".set reorder"
> > > :
> > > : "r" (addr),
> > > "i" (Index_Writeback_Inv_SD));
> > >
> > > addr += waystep;
> > > }
> > > }
> > >
> > > static inline void flush_icache_line(unsigned long addr)
> > > {
> > > __asm__ __volatile__(
> > > ".set noreorder\n\t"
> > > ".set mips3\n\t"
> > > "cache %1, (%0)\n\t"
> > > ".set mips0\n\t"
> > > ".set reorder"
> > > :
> > > : "r" (addr),
> > >   "i" (Hit_Invalidate_I));
> > > }
> > >
> > > static inline void flush_dcache_line(unsigned long addr)
> > > {
> > > __asm__ __volatile__(
> > > ".set noreorder\n\t"
> > > ".set mips3\n\t"
> > > "cache %1, (%0)\n\t"
> > > ".set mips0\n\t"
> > > ".set reorder"
> > > :
> > > : "r" (addr),
> > >   "i" (Hit_Writeback_Inv_D));
> > > }
> > >
> > > static inline void invalidate_dcache_line(unsigned long addr)
> > > {
> > > __asm__ __volatile__(
> > > ".set noreorder\n\t"
> > > ".set mips3\n\t"
> > > "cache %1, (%0)\n\t"
> > > ".set mips0\n\t"
> > > ".set reorder"
> > > :
> > > : "r" (addr),
> > >   "i" (Hit_Invalidate_D));
> > > }
> > >
> > > static inline void invalidate_scache_line(unsigned long addr)
> > > {
> > > __asm__ __volatile__(
> > > ".set noreorder\n\t"
> > > ".set mips3\n\t"
> > > "cache %1, (%0)\n\t"
> > > ".set mips0\n\t"
> > > ".set reorder"
> > > :
> > > : "r" (addr),
> > >   "i" (Hit_Invalidate_SD));
> > > }
> > >
> > > static inline void flush_scache_line(unsigned long addr)
> > > {
> > > __asm__ __volatile__(
> > > ".set noreorder\n\t"
> > > ".set mips3\n\t"
> > > "cache %1, (%0)\n\t"
> > > ".set mips0\n\t"
> > > ".set reorder"
> > > :
> > > : "r" (addr),
> > >   "i" (Hit_Writeback_Inv_SD));
> > > }
> > >
> > > /*
> > >  * The next two are for badland addresses like signal trampolines.
> > >  */
> > > static inline void protected_flush_icache_line(unsigned long addr)
> > > {
> > > __asm__ __volatile__(
> > > ".set noreorder\n\t"
> > > ".set mips3\n"
> > > "1:\tcache %1,(%0)\n"
> > > "2:\t.set mips0\n\t"
> > > ".set reorder\n\t"
> > > ".section\t__ex_table,\"a\"\n\t"
> > > STR(PTR)"\t1b,2b\n\t"
> > > ".previous"
> > > :
> > > : "r" (addr),
> > >   "i" (Hit_Invalidate_I));
> > > }
> > >
> > > static inline void protected_writeback_dcache_line(unsigned long addr)
> > > {
> > > __asm__ __volatile__(
> > > ".set noreorder\n\t"
> > > ".set mips3\n"
> > > "1:\tcache %1,(%0)\n"
> > > "2:\t.set mips0\n\t"
> > > ".set reorder\n\t"
> > > ".section\t__ex_table,\"a\"\n\t"
> > > STR(PTR)"\t1b,2b\n\t"
> > > ".previous"
> > > :
> > > : "r" (addr),
> > >   "i" (Hit_Writeback_D));
> > > }
> > >
> > > #define cache_unroll(base,op)         \
> > > __asm__ __volatile__("          \
> > > .set noreorder;         \
> > > .set mips3;         \
> > >                 cache %1, (%0);                 \
> > > .set mips0; \
> > > .set reorder" \
> > > : \
> > > : "r" (base), \
> > >   "i" (op));
> > >
> > >
> > > static inline void blast_dcache(void)
> > > {
> > > unsigned long start = KSEG0;
> > > unsigned long end = (start + dcache_size);
> > >
> > > while(start < end) {
> > > cache_unroll(start,Index_Writeback_Inv_D);
> > > start += dc_lsize;
> > > }
> > > }
> > >
> > > static inline void blast_dcache_page(unsigned long page)
> > > {
> > > unsigned long start = page;
> > > unsigned long end = (start + PAGE_SIZE);
> > >
> > > while(start < end) {
> > > cache_unroll(start,Hit_Writeback_Inv_D);
> > > start += dc_lsize;
> > > }
> > > }
> > >
> > > static inline void blast_dcache_page_indexed(unsigned long page)
> > > {
> > > unsigned long start;
> > > unsigned long end = (page + PAGE_SIZE);
> > > unsigned long waystep = dcache_size/mips_cpu.dcache.ways;
> > > unsigned int way;
> > >
> > > for (way = 0; way < mips_cpu.dcache.ways; way++) {
> > > start = page + way*waystep;
> > > while(start < end) {
> > > cache_unroll(start,Index_Writeback_Inv_D);
> > > start += dc_lsize;
> > > }
> > > }
> > > }
> > >
> > > static inline void blast_icache(void)
> > > {
> > > unsigned long start = KSEG0;
> > > unsigned long end = (start + icache_size);
> > >
> > > while(start < end) {
> > > cache_unroll(start,Index_Invalidate_I);
> > > start += ic_lsize;
> > > }
> > > }
> > >
> > > static inline void blast_icache_page(unsigned long page)
> > > {
> > > unsigned long start = page;
> > > unsigned long end = (start + PAGE_SIZE);
> > >
> > > while(start < end) {
> > > cache_unroll(start,Hit_Invalidate_I);
> > > start += ic_lsize;
> > > }
> > > }
> > >
> > > static inline void blast_icache_page_indexed(unsigned long page)
> > > {
> > > unsigned long start;
> > > unsigned long end = (page + PAGE_SIZE);
> > > unsigned long waystep = icache_size/mips_cpu.icache.ways;
> > > unsigned int way;
> > >
> > > for (way = 0; way < mips_cpu.icache.ways; way++) {
> > > start = page + way*waystep;
> > > while(start < end) {
> > > cache_unroll(start,Index_Invalidate_I);
> > > start += ic_lsize;
> > > }
> > > }
> > > }
> > >
> > > static inline void blast_scache(void)
> > > {
> > > unsigned long start = KSEG0;
> > > unsigned long end = KSEG0 + scache_size;
> > >
> > > while(start < end) {
> > > cache_unroll(start,Index_Writeback_Inv_SD);
> > > start += sc_lsize;
> > > }
> > > }
> > >
> > > static inline void blast_scache_page(unsigned long page)
> > > {
> > > unsigned long start = page;
> > > unsigned long end = page + PAGE_SIZE;
> > >
> > > while(start < end) {
> > > cache_unroll(start,Hit_Writeback_Inv_SD);
> > > start += sc_lsize;
> > > }
> > > }
> > >
> > > static inline void blast_scache_page_indexed(unsigned long page)
> > > {
> > > unsigned long start;
> > > unsigned long end = (page + PAGE_SIZE);
> > > unsigned long waystep = scache_size/mips_cpu.scache.ways;
> > > unsigned int way;
> > >
> > > for (way = 0; way < mips_cpu.scache.ways; way++) {
> > > start = page + way*waystep;
> > > while(start < end) {
> > > cache_unroll(start,Index_Writeback_Inv_SD);
> > > start += sc_lsize;
> > > }
> > > }
> > > }
> > >
> > > #endif /* !(_MIPS_R4KCACHE_H) */
> > >
>
> --
> _    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark            http://www.mips.com

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From ralf@linux-mips.org Wed Dec  4 15:14:30 2002
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From: Ralf Baechle <ralf@linux-mips.org>
To: atul srivastava <atulsrivastava9@rediffmail.com>
Cc: linux-mips@linux-mips.org
Subject: Re: hazards during DO_FAULT macro..
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On Wed, Dec 04, 2002 at 10:17:41AM -0000, atul srivastava wrote:

> macro Do_FAULt(write) expands like..
> 
> #define DO_FAULT(write) \
>          .set    noreorder; \
>          .set    noat; \
>          SAVE_ALL; \
>          STI; \
>          nop; \

Unnecessary nop.

>          .set    at; \
>          move a0, sp; \
>          jal     do_page_fault; \
>          li     a1, write; \
>          nop; \

Unnecessary nop.

>          j       ret_from_sys_call; \

This is ret_from_exception since about 14 months.

>          nop; \
>         .set    noat;
> 
> this macro is called by handle_tlbx() routines.
> when I tracked this problem and i observed my pt_regs address
> looked o.k. and apparently right till after STI; \ and just before 
> instruction     mfc0    a2, CP0_BADVADDR;
> this i found by putting following instructions,
> 
> move  a0,sp; \
> jal show_regs; \
> nop; \
> 
> later it jumps to do_page_fault() ,and pt_regs address there 
> equals unexpectedly to envp_init and from thereon everythings goes 
> wrong..

This would means something like your user process was running with
c0_status.cu0 = 1 which is forbidden.  If that happens the kernel wouldn't
load a new stack pointer on kerne entry.

> I also tried with negating STI; \ , but same result.

This would means something like your user process was running with
c0_status.cu0 = 1 which is forbidden.  If that happens the kernel wouldn't
load a new stack pointer on kerne entry.

> 8001e6ac:	01094025 	or	$t0,$t0,$t1     STI macro code , though i 

The function there has doesn't have STI but KMODE since almost half a
year.  Time to upgrade.

And our code never had the mfc0 from the badvaddr register after the STI /
KMODE, so it seems you kernel tree is a) antique b) seems hacked beyond
recognition.

Moving the mfc0 behind the sti would be valid as long as we know there's
always a hazard of at least one cycle before interrupts get activated.  That
was true for the initially supported processors like R4000 (3 cycles) or
R4600 (1 cycle) but no longer for modern processors.

  Ralf

From carstenl@mips.com Wed Dec  4 16:06:44 2002
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From: Carsten Langgaard <carstenl@mips.com>
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Subject: Re: Prefetches in memcpy
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I would like to open this thread again, since nothing has been done about it.
I think we should get rid of the prefetches until someone comes up with a
version that doesn't prefetch beyond the copy destination/source area.

/Carsten


Ralf Baechle wrote:

> On Tue, Nov 05, 2002 at 02:45:47PM +0100, Carsten Langgaard wrote:
>
> > The problem is the prefetches in the memcpy function in the kernel.
> > There is spread a number of PREF instructions in the memcpy function,
> > but there is no check if we are prefetching out-side the areas we are
> > copying to/from. This is extremely dangerous because we might prefetch
> > out-side the physical memory area, causing e.g. a bus error or something
> > even more nasty.
> >
> > I recently found something even nastier, it could also hit a DMA buffer
> > region, and thereby break the PCI DMA flushing scheme.
> > For example if the kernel is doing a memcpy from an area that's next to
> > a DMA buffer area, we could end up in a situation where, we are
> > prefetching
> > data into the cache from a memory location that is used for DMA transfer
> > and owned by the device, but the DMA transfer has not yet completed.
> > We then end up in a situation, where the memory and cache is out of sync
> > and the cache is containing some old data.
> >
> > So we definitely need to do something about the prefetches in the memcpy
> > function.  We can either get rid of all the prefetches or make sure we
> > don't prefetch out side the "memcpy" area.
>
> We could fix the prefetch into DMA buffer problem with an extra flush but
> that's going to be expensive, I rather think we should avoid prefetches.
> As Kevin explained KSEG1 is a loophole in the spec so we can't really say
> what the behaviour of memcpy will be in KSEG1.
>
> So I think the fix will have to be:
>
>  - Avoid prefetching beyond the end of the copy area in memcpy and memmove.
>  - Introduce a second variant of memcpy that never does prefetching.  This
>    one will be safe to use in KSEG1 / uncached XKPHYS also and will be used
>    for memcpy_fromio, memcpy_toio and friends.
>
>   Ralf

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From macro@ds2.pg.gda.pl Wed Dec  4 16:45:27 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Reply-To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Daniel Jacobowitz <dan@debian.org>
cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: watch exception only for kseg0 addresses..?
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On Tue, 3 Dec 2002, Daniel Jacobowitz wrote:

> >  As a fallback the approach is just fine, but doesn't is suck
> > performance-wise for watchpoints at the stack?  It certainly sucks for
> > instruction fetches.  While gdb doesn't seem to use hardware breakpoints
> > as they are only really necessary for ROMs, other software may want to
> > (well, gdb too, one day). 
> 
> Page-protection watchpoints on the stack do bite for performance, yes. 
> Most watched variables are not on the stack, though.  People tend to
> watch globals.

 Well, so far I've almost exclusively watched the stack, sometimes
malloc()ed areas, to track down out of bound corruption.  It's really
useful when a program crashes with a SIGSEGV when returning from a
function call or when calling free() with a legal pointer.  Watching
globals has not been really useful for me so far -- they are rarely used
in the first place and you know where they can get modified, so you can
set ordinary breakpoints in contexts of interest. 

> On Mon, Nov 25, 2002 at 04:08:00PM +0100, Ralf Baechle wrote:
> > I assume you got and R4000 manual and the MIPS64 spec.   R4000 implements
> > matching a physical address with a granularity of 8 bytes for load and
> > store operations.
> 
> Not handy.

 Still better than nothing.  Userland doesn't need to care of the
underlying implementation anyway.  You simply have a single watchpoint
available.  The kernel needs to take care when entering and exiting
userland.

> > So how would a prefered ptrace(2) API for hardware watchpoints look like?
> 
> Well, it would be nice to have at least:
>   - query total number
>   - query the granularity, or at least query whether or not the
>     granularity is settable
>   - Set and remove watchpoints.
> 
> Off the top of my head:
> PTRACE_MIPS_WATCHPOINT_INFO
> struct mips_watchpoint_info {
>   u32 num_avail;
>   u32 max_size;
> };

 The information may be provided when reading the registers.

> PTRACE_MIPS_WATCHPOINT_SET
> struct mips_watchpoint_set {
>   u32 index;
>   u32 size;
>   s64 address;
> };

 How about a KISS approach:

typedef struct {
	s64 address;
	u64 mask;
	u64 access;
} mips_watchpoint;

typedef struct {
	s32 api_version;
	s32 nr_watchpoints;
	mips_watchpoint watchpoints[0];
} mips_watchpoint_set;

Then PTRACE_MIPS_WATCHPOINT_GET is used to retrieve current settings,
PTRACE_MIPS_WATCHPOINT_SET is used to alter them.  More details:

PTRACE_MIPS_WATCHPOINT_SET:

Input:

- api_version has to match the version implemented, currently 0,

- nr_watchpoints specifies the number of watchpoint descriptions
  following, >= 0,

- for each watchpoints entry i, (i = 0; i < nr_watchpoints; i++):

  - address specifies the virtual address covered -- properly
    sign-extended for the 32-bit kernel),

  - mask specifies the mask to use against the address -- don't care bits
    set to one,

  - access specifies the access type; currently read, write and exec are
    specified -- we may follow the MIPS32/64 ISA definition.

Output:

- error code: a failure if a protection violation happens when reading
  mips_watchpoint_set, otherwise success.

PTRACE_MIPS_WATCHPOINT_GET:

Input:

- api_version set to the version expected, currently 0, = api_version_i,

- nr_watchpoints specifies the maximum number of watchpoint descriptions
  expected, >= 0, = nr_watchpoints_i

Output:

- error code: a failure if a protection violation happens when writing
  mips_watchpoint_set, otherwise success,

- api_version set to the version supported, currently 0, = api_version_o,

- if (api_version_i == api_version_o):

  - nr_watchpoints set to the number of watchpoints supported, >= 0, =
    nr_watchpoints_o,

  - for each watchpoints entry i, (i = 0; i < min(nr_watchpoints_i,
    nr_watchpoints_o; i++):

    - address set to the value preset for the watchpoint, as obtained
      from hardware,

    - mask set to the value preset for the watchpoint, as obtained from
      hardware,

    - access set to the value preset for the watchpoint, as obtained from
      hardware.

 I think such an interface covers all the functionality we care of now,
including implementation variations (R4000 vs R4650 vs MIPS32/64), and
provides for cheap future expansion.  Additionally thread-global
watchpoints may be handled by adding a bit to the access member if needed. 

 What do you think?

  Maciej

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From macro@ds2.pg.gda.pl Wed Dec  4 16:47:49 2002
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On Wed, 4 Dec 2002, Ralf Baechle wrote:

> Correct but I don't know of any CPU that actually uses more than 4 of the
> possible 8 sets atm.  So we're both right :)

 Well, software needs to be prepared to handle eight ones.  Actually it's
easy to handle any number. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From drow@false.org Wed Dec  4 16:51:13 2002
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From: Daniel Jacobowitz <dan@debian.org>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: watch exception only for kseg0 addresses..?
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On Wed, Dec 04, 2002 at 04:45:38PM +0100, Maciej W. Rozycki wrote:
> On Tue, 3 Dec 2002, Daniel Jacobowitz wrote:
> 
> > >  As a fallback the approach is just fine, but doesn't is suck
> > > performance-wise for watchpoints at the stack?  It certainly sucks for
> > > instruction fetches.  While gdb doesn't seem to use hardware breakpoints
> > > as they are only really necessary for ROMs, other software may want to
> > > (well, gdb too, one day). 
> > 
> > Page-protection watchpoints on the stack do bite for performance, yes. 
> > Most watched variables are not on the stack, though.  People tend to
> > watch globals.
> 
>  Well, so far I've almost exclusively watched the stack, sometimes
> malloc()ed areas, to track down out of bound corruption.  It's really
> useful when a program crashes with a SIGSEGV when returning from a
> function call or when calling free() with a legal pointer.  Watching
> globals has not been really useful for me so far -- they are rarely used
> in the first place and you know where they can get modified, so you can
> set ordinary breakpoints in contexts of interest. 

Whereas I'm usually tracking global or heap variables whose value is
getting set to something peculiar.  Interesting.

> 
> > On Mon, Nov 25, 2002 at 04:08:00PM +0100, Ralf Baechle wrote:
> > > I assume you got and R4000 manual and the MIPS64 spec.   R4000 implements
> > > matching a physical address with a granularity of 8 bytes for load and
> > > store operations.
> > 
> > Not handy.
> 
>  Still better than nothing.

Sorry, by "not handy" I meant I didn't have the manuals available :)

>  Userland doesn't need to care of the
> underlying implementation anyway.  You simply have a single watchpoint
> available.  The kernel needs to take care when entering and exiting
> userland.
> 
> > > So how would a prefered ptrace(2) API for hardware watchpoints look like?
> > 
> > Well, it would be nice to have at least:
> >   - query total number
> >   - query the granularity, or at least query whether or not the
> >     granularity is settable
> >   - Set and remove watchpoints.
> > 
> > Off the top of my head:
> > PTRACE_MIPS_WATCHPOINT_INFO
> > struct mips_watchpoint_info {
> >   u32 num_avail;
> >   u32 max_size;
> > };
> 
>  The information may be provided when reading the registers.
> 
> > PTRACE_MIPS_WATCHPOINT_SET
> > struct mips_watchpoint_set {
> >   u32 index;
> >   u32 size;
> >   s64 address;
> > };
> 
>  How about a KISS approach:
> 
> typedef struct {
> 	s64 address;
> 	u64 mask;
> 	u64 access;
> } mips_watchpoint;
> 
> typedef struct {
> 	s32 api_version;
> 	s32 nr_watchpoints;
> 	mips_watchpoint watchpoints[0];
> } mips_watchpoint_set;
> 
> Then PTRACE_MIPS_WATCHPOINT_GET is used to retrieve current settings,
> PTRACE_MIPS_WATCHPOINT_SET is used to alter them.  More details:

>  What do you think?

You don't reveal to userland what size watchpoints are available - i.e.
how large a watchpoint can be.  Does the mask match the hardware
implementation, and what are the restrictions on it?

-- 
Daniel Jacobowitz
MontaVista Software                         Debian GNU/Linux Developer

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To: "Carsten Langgaard" <carstenl@mips.com>
Cc: <linux-mips@linux-mips.org>, "Jun Sun" <jsun@mvista.com>
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Subject: Re: possible Malta 4Kc cache problem ...
Date: Wed, 4 Dec 2002 18:08:22 +0100
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> > I think that Carsten's patch (or equivalent) should certainly be
> > applied to the main tree, but I wonder how relevant it is here.
> > The flushes associated with trampolines don't do indexed
> > flush operations, do they?
> 
> True, but are we sure that it's the trampoline that's the problem here?

Jun Sun seemed to think it was. To quote his original message

"The problem involves emulating a "lw" instruction in cp1 branch delay
 slot, which needs to  set up trampoline in user stack.  The net effect
 looks as if the icache line or dcache line is not flushed properly."

I don't know what his actual observations were that lead to that
conclusion, but the resemblence to what was reported under LTP
with the pre-break_cow()-patch kernel intrigues me.

So, I repeat... 
> > ...I don't have a 4Kc platform at
> > hand, but I think that Jun Sun *may* have found a better
> > way to get at the other problem I was referring to, which
> > we rarely saw on non-superscalar issue CPUs, and which
> > seems to be masked by an otherwise superfluous flush of
> > the Icache that was added to the latest versions of break_cow().
> > If Carsten's patch solves the problem without applying that
> > other update, I'd want to know that.  If it *doesn't*, I'd be
> > really interested to know if, by any chance, there is a
> > corelation between failures of Jun Sun's test and the incidence
> > of page faults on the CACHE op in protected_icache_invalidate_line().
> >
> >             Kevin K.


From drow@false.org Wed Dec  4 18:32:51 2002
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Date: Wed, 4 Dec 2002 12:32:48 -0500
From: Daniel Jacobowitz <dan@debian.org>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: Carsten Langgaard <carstenl@mips.com>, linux-mips@linux-mips.org,
	Jun Sun <jsun@mvista.com>
Subject: Re: possible Malta 4Kc cache problem ...
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On Wed, Dec 04, 2002 at 06:08:22PM +0100, Kevin D. Kissell wrote:
> > > I think that Carsten's patch (or equivalent) should certainly be
> > > applied to the main tree, but I wonder how relevant it is here.
> > > The flushes associated with trampolines don't do indexed
> > > flush operations, do they?
> > 
> > True, but are we sure that it's the trampoline that's the problem here?
> 
> Jun Sun seemed to think it was. To quote his original message
> 
> "The problem involves emulating a "lw" instruction in cp1 branch delay
>  slot, which needs to  set up trampoline in user stack.  The net effect
>  looks as if the icache line or dcache line is not flushed properly."
> 
> I don't know what his actual observations were that lead to that
> conclusion, but the resemblence to what was reported under LTP
> with the pre-break_cow()-patch kernel intrigues me.

Here's some of the actual observations: if you single-step over the
bc1t instruction, then it comes out as you'd expect; the load in the
delay slot was executed.  Even if you breakpoint in the general
vicinity and then continue.

But if you breakpoint _after_ the instruction, it is evident that the
load did not occur as expected.

> So, I repeat... 
> > > ...I don't have a 4Kc platform at
> > > hand, but I think that Jun Sun *may* have found a better
> > > way to get at the other problem I was referring to, which
> > > we rarely saw on non-superscalar issue CPUs, and which
> > > seems to be masked by an otherwise superfluous flush of
> > > the Icache that was added to the latest versions of break_cow().
> > > If Carsten's patch solves the problem without applying that
> > > other update, I'd want to know that.  If it *doesn't*, I'd be
> > > really interested to know if, by any chance, there is a
> > > corelation between failures of Jun Sun's test and the incidence
> > > of page faults on the CACHE op in protected_icache_invalidate_line().
> > >
> > >             Kevin K.
> 
> 
> 

-- 
Daniel Jacobowitz
MontaVista Software                         Debian GNU/Linux Developer

From macro@ds2.pg.gda.pl Wed Dec  4 18:53:53 2002
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cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: watch exception only for kseg0 addresses..?
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On Wed, 4 Dec 2002, Daniel Jacobowitz wrote:

> Sorry, by "not handy" I meant I didn't have the manuals available :)

 'http://www.mips.com/Documentation/R4400_Uman_book_Ed2.pdf' or see under
"Publications"/"R4000...".  There are other sources of the book available,
e.g. somewhere within SGI web pages.  R10k implements a single watchpoint
this way, too. 

> >  What do you think?
> 
> You don't reveal to userland what size watchpoints are available - i.e.
> how large a watchpoint can be.  Does the mask match the hardware
> implementation, and what are the restrictions on it?

 For that you set up a disabled watchpoint with a mask set to all ones (or
the range you are interested in).  Then when you retrieve it, you may see
which bits stayed at ones.  Similarly you may check for hardwired
don't-cares by using a mask with all zeroes.  The mask may differ for each
watchpoint, e.g. for R4650 it's different for IWatch and DWatch, so you
really want to have a per-watchpoint setting.  Also the MIPS32/64 ISA
specification implies a mask need not be contiguous. 

 Similarly you may check for access types permitted, by enabling all of
them (or ones you are interested in) and seeing which ones remained
enabled.  Per-watchpoint, again. 

 I'd prefer not to overdesign the API leaving as much information as
possible passed as is.  This way userland gets more control over what's
available.

  Maciej

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From carstenl@mips.com Wed Dec  4 21:29:51 2002
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CC: "Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org,
	Jun Sun <jsun@mvista.com>
Subject: Re: possible Malta 4Kc cache problem ...
References: <20021203224504.B13437@mvista.com> <007501c29b78$f34680e0$10eca8c0@grendel> <3DEDD414.3854664F@mips.com> <3DEDE537.CD58AD8F@mips.com> <013d01c29b95$fb487f60$10eca8c0@grendel> <3DEDFFB9.3312BA1A@mips.com> <021401c29bb7$cd02abe0$10eca8c0@grendel> <20021204173248.GA23213@nevyn.them.org>
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Could you please tell us, which 4Kc you are running on ?
What are the cache configuration (size, number of ways) ?
Are you running on the latest kernel sources from the CVS tree ?
Have you tried the mips32_cache.h file I send and/or have you tried the kernel
from the ftp.mips.com FTP server ?

Many question at the same time ;-)
/Carsten


Daniel Jacobowitz wrote:

> On Wed, Dec 04, 2002 at 06:08:22PM +0100, Kevin D. Kissell wrote:
> > > > I think that Carsten's patch (or equivalent) should certainly be
> > > > applied to the main tree, but I wonder how relevant it is here.
> > > > The flushes associated with trampolines don't do indexed
> > > > flush operations, do they?
> > >
> > > True, but are we sure that it's the trampoline that's the problem here?
> >
> > Jun Sun seemed to think it was. To quote his original message
> >
> > "The problem involves emulating a "lw" instruction in cp1 branch delay
> >  slot, which needs to  set up trampoline in user stack.  The net effect
> >  looks as if the icache line or dcache line is not flushed properly."
> >
> > I don't know what his actual observations were that lead to that
> > conclusion, but the resemblence to what was reported under LTP
> > with the pre-break_cow()-patch kernel intrigues me.
>
> Here's some of the actual observations: if you single-step over the
> bc1t instruction, then it comes out as you'd expect; the load in the
> delay slot was executed.  Even if you breakpoint in the general
> vicinity and then continue.
>
> But if you breakpoint _after_ the instruction, it is evident that the
> load did not occur as expected.
>
> > So, I repeat...
> > > > ...I don't have a 4Kc platform at
> > > > hand, but I think that Jun Sun *may* have found a better
> > > > way to get at the other problem I was referring to, which
> > > > we rarely saw on non-superscalar issue CPUs, and which
> > > > seems to be masked by an otherwise superfluous flush of
> > > > the Icache that was added to the latest versions of break_cow().
> > > > If Carsten's patch solves the problem without applying that
> > > > other update, I'd want to know that.  If it *doesn't*, I'd be
> > > > really interested to know if, by any chance, there is a
> > > > corelation between failures of Jun Sun's test and the incidence
> > > > of page faults on the CACHE op in protected_icache_invalidate_line().
> > > >
> > > >             Kevin K.
> >
> >
> >
>
> --
> Daniel Jacobowitz
> MontaVista Software                         Debian GNU/Linux Developer


From jsun@orion.mvista.com Wed Dec  4 23:00:03 2002
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From: Jun Sun <jsun@mvista.com>
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Subject: Re: possible Malta 4Kc cache problem ...
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On Wed, Dec 04, 2002 at 10:38:36AM +0100, Kevin D. Kissell wrote:
> 
> Which version of the 4Kc manual are you looking at?  I'm looking
> at a very recent version of the 4Kc Software User's Manual
> (version 1.17, dated September 25, 2002), and it only shows
> Hit_Writeback_D to be invalid for *secondary and teritary*
> caches, which makes sense, since the 4KSc doesn't have any.
>

I was looking at rev 1.12, Jan 3, 2001.

Good to know that 4K family does have Hit_WRiteback_D.  However,
since it is "recommanded" instead of "required".  Shouldn't we
still use "Hit_Writeback_Inv_D" just to be on the safe side?

Jun

From jsun@orion.mvista.com Wed Dec  4 23:19:07 2002
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Date: Wed, 4 Dec 2002 14:19:00 -0800
From: Jun Sun <jsun@mvista.com>
To: Carsten Langgaard <carstenl@mips.com>
Cc: "Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org,
	jsun@mvista.com
Subject: Re: possible Malta 4Kc cache problem ...
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On Wed, Dec 04, 2002 at 11:08:20AM +0100, Carsten Langgaard wrote:
> I have just tried your test on a 4Kc and I see no problems.
> However I'm running on our internal kernel sources, and as Kevin mention we have
> changed a fixed a few things in this area.
> As Kevin also mention it sure look more like a I-cache invalidation problem,
> rather than a D-cache flush problem, as the 4Kc has a write-through cache.
> One think you could try, is our latest kernel release. You can find it here:
> ftp://ftp.mips.com/pub/linux/mips/kernel/2.4/images/
>

Yes, the problem still exists with this kernel.

Try to move the source tree to /root/, rename top dir to "try18", 
re-make the binary, and try again.

This problem is tricky to reproduce.  The location of the tree
definitely matters.  I am testing 32bit LE version.  Have not
tried BE.

I think I have pinned down the problem.  See my other follow-up posting.

Jun

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OK, I am fully convinced that this is some kind of hardware
problem.  Basically, it appears CPU is running from a stale 
icache line even though it has invalid flags!

In order to see how I draw this conclusion, you will need to 
be a little patient.

Here is the relavent user code segment:

  400f3c:       45010009        bc1t    400f64 <C_x_co_DIDI_J+0x84>
  400f40:       8c510008        lw      $s1,8($v0)
  ....
  400f94:       4501000a        bc1t    400fc0 <C_x_co_DIDI_J+0xe0>
  400f98:       8fa20050        lw      $v0,80($sp)

In both cases, branch are taken.  The faulting symptom is that
"lw" in the second delay slot does not load correct value to $v0.

I wrote some sizable instrumentation code to capture what has happened
before and after "lw" emulation.  A rough patch of my change is included for 
the diehard hackers.

Here is the output from my captured data for the faulting "lw" case:

----------
dsemul_insns = 7fff78f0, epc=00400f98, cpc=00400fc0, ir=8fa20050
v0 = 10000028, s1=00000004
ret_epc = 7fff78f4, ret_ir=8fa20050, ret_sp=7fff7900, ret_sp_80val=00000004
ret_v0 = 10000028, ret_s1=00000004, bad_addr=00000000
cache tags before: 0018a8f2, 03b878f0, 000308f2, 03b888f2
cache tags after : 0018a8f2, 03b87800, 000308f2, 03b888f2
mem @ a3b878f0 : 8fa20050, 8c000001, 0000bd36, 00400fc0
----------

Several notes and observations:

. 7fff78f0 is in fact 83b878f0 (or a3b878f0) in kernel space

. ret_v0 is the v0 value after we return from trampoline execution.  Wowla,
  it has the same value as before, meaning "lw $v0,80($sp)" did not happen.  
  To further confirm that, I actually printed out the value at 80($sp) which is
  "ret_sp_80val=00000004" (That is the right value $v0 should have, BTW).

. apparently the trampoline is executed, because we did come back from it
  through unaligned access exception.

. In order to figure out what the first instruction is, I modified $s1 value
  to 0x55 right before we start to execute trampoline code.  Guess what, after 
  it comes back, $s1 is changed to "ret_s1=00000004", which suggests an stale instruction
  "lw $s1,8($v0)" was executed.  This instruction was put into icache during the previous
  bc1t emulation.

. "cache tags before/after" dumps cache tags of all four ways in the same set as the
   trampoline.  It is clear that after flush_cache_sigtramp() the valid bits are correctly
   cleared.

. The last line shows memory indeed has the right values.  It is the icache
  to blame.

. No page fault has happened during flush_cache_sigtramp() because bad_addr would
  otherwise contains the faulting address.

It seems safe to conclude CPU executed from a stale icache line.  I have no clue why 
icache exhibits such a problem.

I modified flush_cache_sigtramp() to flush the whole icache, and things appear
to be working.  However, not knowing the root cause I am not 100% sure
if this is a valid workaround.

Here are some info related to the CPU:

CPU revision is: 00018001
Primary instruction cache 16kb, linesize 16 bytes (4 ways)
Primary data cache 16kb, linesize 16 bytes (4 ways)

Jun


On Tue, Dec 03, 2002 at 10:45:04PM -0800, Jun Sun wrote:
> 
> I attached the test case.  Untar it.  Type 'make' and run 'a.out'.
> 
> If the test fails you will see a print-out.  Otherwise you see nothing.
> 
> It does not always fail.  But if it fails, it is usually pretty consistent.
> Try a few times.  Moving source tree to a different directory may cause
> the symptom appear or disappear.
> 
> I spent quite some time to trace this problem, and came to suspect
> there might be a hardware problem.
> 
> The problem involves emulating a "lw" instruction in cp1 branch delay
> slot, which needs to  set up trampoline in user stack.  The net effect
> looks as if the icache line or dcache line is not flushed properly.
> 
> Using gdb/kgdb, printf or printk in any useful places would hide the bug.
> 
> I did find a smaller part of the problem.  flush_cache_sigtramp for
> MIPS32 (4Kc) calls protected_writeback_dcache_line in mips32_cache.h.
> It uses Hit_Writeback_D, and the 4Kc mannual says it is not implemented
> and executed as no-op (*ick*).
> 
> Even after fixing this, I still see the problem happening.
> 
> If you replace flush_cache_sigtramp() with flush_cache_all(), symptom
> would disppear.
> 
> Several of my tests seem to suggest it is the icache that did not
> get flushed (or updated) properly.
> 
> Not re-producible on other MIPS boards.  At least so far.
> 
> Does anybody with more knowledge about 4Kc have any clues here?
> 
> Thanks.
> 
> Jun



--/04w6evG8XlLl3ft
Content-Type: text/plain; charset=us-ascii
Content-Disposition: attachment; filename="trace.patch"

diff -Nru ./arch/mips/math-emu/cp1emu.c.orig ./arch/mips/math-emu/cp1emu.c
--- ./arch/mips/math-emu/cp1emu.c.orig	Tue Oct 22 18:36:50 2002
+++ ./arch/mips/math-emu/cp1emu.c	Wed Dec  4 13:44:55 2002
@@ -772,6 +772,47 @@
 /* Instruction inserted following the AdELOAD to further tag the sequence */
 #define BD_COOKIE 0x0000bd36 /* tne $0,$0 with baggage */
 
+int jsun_flag=0;
+unsigned long jsun_addr;
+struct {
+	unsigned dsemul_insns, epc, cpc, ir;
+	unsigned v0, s1;
+	unsigned ret_epc, ret_ir, ret_sp, ret_sp_80val;
+	unsigned ret_v0, ret_s1;
+	unsigned long bad_addr;
+	unsigned cache_tag[4], ret_cache_tag[4];
+	unsigned long kaddr;
+	unsigned kaddr_data[4];
+} jsun_array[200];
+int jsun_index;
+
+extern unsigned long user_to_kernel(unsigned long addr);
+extern int dcache_way_offset, icache_way_offset;
+
+#include <asm/cacheops.h>
+static inline unsigned load_icache_line_indexed(unsigned long addr)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                ".set mips3\n\t"
+                "cache %1, (%0)\n\t"
+                ".set mips0\n\t"
+                ".set reorder"
+                :
+                : "r" (addr),
+                  "i" (Index_Load_Tag_I));
+
+	return read_32bit_cp0_register(CP0_TAGLO);
+}
+
+void read_cache_tag(unsigned long addr, unsigned *tag)
+{
+	tag[0] = load_icache_line_indexed(addr);
+	tag[1] = load_icache_line_indexed(addr+icache_way_offset);
+	tag[2] = load_icache_line_indexed(addr+icache_way_offset*2);
+	tag[3] = load_icache_line_indexed(addr+icache_way_offset*3);
+}
+
 int do_dsemulret(struct pt_regs *xcp)
 {
 	unsigned long *pinst;
@@ -786,7 +827,7 @@
 	 * If we can't even access the area, something is very wrong, but we'll
 	 * leave that to the default handling
 	 */
-	if (verify_area(VERIFY_READ, pinst, sizeof(unsigned long) * 3))
+	if (verify_area(VERIFY_READ, pinst-1, sizeof(unsigned long) * 4))
 		return 0;
 
 	/* Is the instruction pointed to by the EPC an AdELOAD? */
@@ -826,16 +867,77 @@
 	/* Set EPC to return to post-branch instruction */
 	xcp->cp0_epc = stackitem;
 
+	jsun_array[jsun_index].ret_epc = (unsigned long)pinst;
+	jsun_array[jsun_index].ret_ir = mips_get_word(xcp, pinst-1, &err);
+	jsun_array[jsun_index].ret_sp = xcp->regs[29];
+	jsun_array[jsun_index].ret_v0 = xcp->regs[2];
+	jsun_array[jsun_index].ret_s1 = xcp->regs[17];
+	jsun_array[jsun_index].ret_sp_80val = mips_get_word(xcp, xcp->regs[29]+80, &err);
+	if (jsun_array[jsun_index].ret_ir == 0x8fa20050) {
+		xcp->regs[17] = jsun_array[jsun_index].s1;
+	}
+
+	jsun_index ++;
+
 	return 1;
 }
 
 
 #define AdELOAD 0x8c000001	/* lw $0,1($0) */
 
+void jsun_dump_struct(void)
+{
+	int i;
+	printk("dump jsun_struct:\n");
+	for (i=0; i< jsun_index; i++) {
+		printk("------\n");
+		printk("dsemul_insns = %08x, epc=%08x, cpc=%08x, ir=%08x\n", 
+				jsun_array[i].dsemul_insns, 
+				jsun_array[i].epc,
+				jsun_array[i].cpc,
+				jsun_array[i].ir);
+		printk("v0 = %08x, s1=%08x\n",
+				jsun_array[i].v0,
+				jsun_array[i].s1);
+		printk("ret_epc = %08x, ret_ir=%08x, ret_sp=%08x, ret_sp_80val=%08x\n", 
+				jsun_array[i].ret_epc,
+				jsun_array[i].ret_ir,
+				jsun_array[i].ret_sp,
+				jsun_array[i].ret_sp_80val);
+		printk("ret_v0 = %08x, ret_s1=%08x, bad_addr=%08lx\n",
+				jsun_array[i].ret_v0,
+				jsun_array[i].ret_s1,
+				jsun_array[i].bad_addr
+				);
+		printk("cache tags before: %08x, %08x, %08x, %08x\n",
+				jsun_array[i].cache_tag[0],
+				jsun_array[i].cache_tag[1],
+				jsun_array[i].cache_tag[2],
+				jsun_array[i].cache_tag[3]
+		      );
+		printk("cache tags after : %08x, %08x, %08x, %08x\n",
+				jsun_array[i].ret_cache_tag[0],
+				jsun_array[i].ret_cache_tag[1],
+				jsun_array[i].ret_cache_tag[2],
+				jsun_array[i].ret_cache_tag[3]
+		      );
+		printk("mem @ %08x : %08x, %08x, %08x, %08x\n",
+				jsun_array[i].kaddr + 0x20000000,
+				jsun_array[i].kaddr_data[0],
+				jsun_array[i].kaddr_data[1],
+				jsun_array[i].kaddr_data[2],
+				jsun_array[i].kaddr_data[3]);
+				
+	}
+	jsun_index = 0;
+}
+
 static int mips_dsemul(struct pt_regs *regs, mips_instruction ir, vaddr_t cpc)
 {
 	mips_instruction *dsemul_insns;
 	extern asmlinkage void handle_dsemulret(void);
+	mips_instruction new_ir;
+	unsigned long temp;
 
 	if (ir == 0) {		/* a nop is easy */
 		regs->cp0_epc = VA_TO_REG(cpc);
@@ -864,11 +966,17 @@
 	dsemul_insns = (mips_instruction *) (regs->regs[29] & ~0xf);
 	dsemul_insns -= 4;	/* Retain 16-byte alignment */
 
+	temp=user_to_kernel((unsigned long)dsemul_insns);
+
 	/* Verify that the stack pointer is not competely insane */
 	if (verify_area
 	    (VERIFY_WRITE, dsemul_insns, sizeof(mips_instruction) * 4))
 		return SIGBUS;
 
+	if (ir == 0x8fa20050) {
+		// ir = 0x24020004;	// li v0, 9
+		// regs->regs[2]=0;
+	}
 	if (mips_put_word(regs, &dsemul_insns[0], ir)) {
 		fpuemuprivate.stats.errors++;
 		return (SIGBUS);
@@ -890,9 +998,50 @@
 		return (SIGBUS);
 	}
 
+
+	jsun_array[jsun_index].dsemul_insns = (unsigned long)dsemul_insns;
+	jsun_array[jsun_index].epc = (unsigned long)regs->cp0_epc;
+	jsun_array[jsun_index].cpc = cpc;
+	jsun_array[jsun_index].v0 = regs->regs[2];
+	jsun_array[jsun_index].s1 = regs->regs[17];
+	jsun_array[jsun_index].ir = *(unsigned long *)&ir;
+	jsun_array[jsun_index].kaddr = temp;
+
+	// jsun_index ++;
+
+	if (ir == 0x8fa20050) {
+		regs->regs[17] = 0x55;
+	}
+
 	regs->cp0_epc = VA_TO_REG & dsemul_insns[0];
 
+	read_cache_tag(temp, jsun_array[jsun_index].cache_tag);
+	jsun_addr=0;
 	flush_cache_sigtramp((unsigned long)dsemul_insns);
+	jsun_array[jsun_index].bad_addr = jsun_addr;
+	read_cache_tag(temp, jsun_array[jsun_index].ret_cache_tag);
+
+	jsun_array[jsun_index].kaddr_data[0] = *(unsigned*)(temp + 0x20000000);
+	jsun_array[jsun_index].kaddr_data[1] = *(unsigned*)(temp + 0x20000004);
+	jsun_array[jsun_index].kaddr_data[2] = *(unsigned*)(temp + 0x20000008);
+	jsun_array[jsun_index].kaddr_data[3] = *(unsigned*)(temp + 0x2000000c);
+
+	// my_flush_cache_sigtramp((unsigned long)dsemul_insns);
+	// flush_cache_all();
+
+#if 0
+	jsun_addr=user_to_kernel((unsigned long)dsemul_insns);
+	if (jsun_addr) 
+		printk("mem @ %08x : %08x, %08x, %08x, %08x\n",
+				jsun_addr,
+				*(unsigned long*)jsun_addr,
+				*(unsigned long*)(jsun_addr+4),
+				*(unsigned long*)(jsun_addr+8),
+				*(unsigned long*)(jsun_addr+12));
+	else 
+		printk("convertion failed\n");
+#endif
+
 	return SIGILL;		/* force out of emulation loop */
 }
 
diff -Nru ./arch/mips/mm/c-mips32.c.orig ./arch/mips/mm/c-mips32.c
--- ./arch/mips/mm/c-mips32.c.orig	Tue Dec  3 18:54:52 2002
+++ ./arch/mips/mm/c-mips32.c	Wed Dec  4 13:04:29 2002
@@ -39,6 +39,7 @@
 /* Primary cache parameters. */
 int icache_size, dcache_size; 			/* Size in bytes */
 int ic_lsize, dc_lsize;				/* LineSize in bytes */
+int icache_way_offset, dcache_way_offset;	/* offset between ways w. same set */
 
 /* Secondary cache (if present) parameters. */
 unsigned int scache_size, sc_lsize;		/* Again, in bytes */
@@ -407,6 +408,55 @@
  * very much about what happens in that case.  Usually a segmentation
  * fault will dump the process later on anyway ...
  */
+static void indexed_writeback_dcache_line(unsigned long addr)
+{
+	int i;
+	int set_size = dcache_size / mips_cpu.dcache.ways;
+	for (i=0; i<mips_cpu.dcache.ways; i++) {
+	       flush_dcache_line_indexed(addr);
+	       addr += set_size;
+	}
+}
+
+void my_flush_cache_sigtramp(unsigned long addr)
+{
+	indexed_writeback_dcache_line(addr & ~(dc_lsize - 1));
+	protected_flush_icache_line(addr & ~(ic_lsize - 1));
+}
+
+unsigned long user_to_kernel(unsigned long addr)
+{
+	unsigned offset;
+	pgd_t *pgd;
+	pmd_t *pmd;
+	pte_t *pte;
+	mem_map_t *pg;
+	struct mm_struct *mm;
+
+	offset = addr & ~PAGE_MASK;
+	addr &= PAGE_MASK;
+	if (!current->mm  ||
+		!current->mm->context ||
+		!current->active_mm ||
+		!current->active_mm->context ||
+		current->mm != current->active_mm) {
+		printk("user_to_kernel condition failed\n");
+		return 0;
+	}
+
+	mm= current->mm;
+	pgd = pgd_offset(mm, addr);
+	pmd = pmd_offset(pgd, addr);
+	pte = pte_offset(pmd, addr);
+	if(!(pte_val(*pte) & _PAGE_VALID)) {
+		printk("user_to_kernel : pte not valid\n");
+		return 0;
+	}
+
+	pg= pte_page(*pte);
+	return (unsigned long)pg->virtual + offset;
+}
+
 static void mips32_flush_cache_sigtramp(unsigned long addr)
 {
 	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
@@ -451,6 +501,7 @@
 	}
 	printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n",
 	       icache_size >> 10, ic_lsize, mips_cpu.icache.ways);
+	icache_way_offset = icache_size / mips_cpu.icache.ways;
 }
 
 static void __init probe_dcache(unsigned long config)
@@ -490,6 +541,7 @@
 	}
 	printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n",
 	       dcache_size >> 10, dc_lsize, mips_cpu.dcache.ways);
+	dcache_way_offset = dcache_size / mips_cpu.dcache.ways;
 }
 
 
diff -Nru ./arch/mips/mm/fault.c.orig ./arch/mips/mm/fault.c
--- ./arch/mips/mm/fault.c.orig	Tue Oct 22 18:36:51 2002
+++ ./arch/mips/mm/fault.c	Wed Dec  4 10:35:26 2002
@@ -74,6 +74,7 @@
  * and the problem, and then passes it off to one of the appropriate
  * routines.
  */
+extern unsigned long jsun_addr;
 asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
 			      unsigned long address)
 {
@@ -193,6 +194,7 @@
 		long new_epc;
 
 		tsk->thread.cp0_baduaddr = address;
+		jsun_addr = address;
 		new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc);
 		if (development_version)
 			printk(KERN_DEBUG "%s: Exception at [<%lx>] (%lx)\n",
diff -Nru ./include/asm-mips/mips32_cache.h.orig ./include/asm-mips/mips32_cache.h
--- ./include/asm-mips/mips32_cache.h.orig	Tue Oct 22 18:37:03 2002
+++ ./include/asm-mips/mips32_cache.h	Tue Dec  3 18:24:25 2002
@@ -171,7 +171,7 @@
 		".previous"
 		:
 		: "r" (addr),
-		  "i" (Hit_Writeback_D));
+		  "i" (Hit_Writeback_Inv_D));
 }
 
 #define cache_unroll(base,op)	        	\
diff -Nru ./net/ipv4/icmp.c.orig ./net/ipv4/icmp.c
--- ./net/ipv4/icmp.c.orig	Mon Feb 25 11:38:14 2002
+++ ./net/ipv4/icmp.c	Tue Dec  3 12:08:01 2002
@@ -733,6 +733,7 @@
 
 static void icmp_echo(struct sk_buff *skb)
 {
+	jsun_dump_struct();
 	if (!sysctl_icmp_echo_ignore_all) {
 		struct icmp_bxm icmp_param;
 

--/04w6evG8XlLl3ft--

From jsun@orion.mvista.com Wed Dec  4 23:58:31 2002
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Date: Wed, 4 Dec 2002 14:58:23 -0800
From: Jun Sun <jsun@mvista.com>
To: Carsten Langgaard <carstenl@mips.com>
Cc: Daniel Jacobowitz <dan@debian.org>,
	"Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org,
	jsun@mvista.com
Subject: Re: possible Malta 4Kc cache problem ...
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References: <20021203224504.B13437@mvista.com> <007501c29b78$f34680e0$10eca8c0@grendel> <3DEDD414.3854664F@mips.com> <3DEDE537.CD58AD8F@mips.com> <013d01c29b95$fb487f60$10eca8c0@grendel> <3DEDFFB9.3312BA1A@mips.com> <021401c29bb7$cd02abe0$10eca8c0@grendel> <20021204173248.GA23213@nevyn.them.org> <3DEE6572.5331C5CD@mips.com>
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I guess I still did not answer some of your questions:

On Wed, Dec 04, 2002 at 09:28:34PM +0100, Carsten Langgaard wrote:
> Could you please tell us, which 4Kc you are running on ?

Is the PRID telling enough?  I posted it in the other email.

> What are the cache configuration (size, number of ways) ?
> Are you running on the latest kernel sources from the CVS tree ?

Debugging work is done with my kernel, but confirmed that latest
CVS tree shows the same problem.

> Have you tried the mips32_cache.h file I send and

No, because I don't think it is related to indexed cache operations.

> /or have you tried the kernel
> from the ftp.mips.com FTP server ?
>

Jun

From kevink@mips.com Thu Dec  5 00:10:34 2002
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From: "Kevin D. Kissell" <kevink@mips.com>
To: "Jun Sun" <jsun@mvista.com>
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References: <20021203224504.B13437@mvista.com> <007501c29b78$f34680e0$10eca8c0@grendel> <20021204135950.T4363@mvista.com>
Subject: Re: possible Malta 4Kc cache problem ...
Date: Thu, 5 Dec 2002 00:14:18 +0100
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> On Wed, Dec 04, 2002 at 10:38:36AM +0100, Kevin D. Kissell wrote:
> > 
> > Which version of the 4Kc manual are you looking at?  I'm looking
> > at a very recent version of the 4Kc Software User's Manual
> > (version 1.17, dated September 25, 2002), and it only shows
> > Hit_Writeback_D to be invalid for *secondary and teritary*
> > caches, which makes sense, since the 4KSc doesn't have any.
> >
> 
> I was looking at rev 1.12, Jan 3, 2001.
> 
> Good to know that 4K family does have Hit_WRiteback_D.  However,
> since it is "recommanded" instead of "required".  Shouldn't we
> still use "Hit_Writeback_Inv_D" just to be on the safe side?

Pardon me, but I thought that you were talking about 
hit-writeback-invalidates to begin with.  Indeed, I had
thought that we had organized things so that Linux always
did writeback-invalidates and never simple writebacks,
just to be on the safe side, as you say, but tampoline code 
is a special case where I can see no possible multiprocessor 
coherence issues with failing to invalidate the local Dcache 
copy. In any case, it would  be100% correct for a pure 
"hit writeback" to be a no-op on a write-through cache, 
since there is never anything dirty to write back.

            Kevin K.

From dennisn@pe.net Thu Dec  5 02:27:21 2002
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Date: Wed, 4 Dec 2002 17:27:11 -0800 (PST)
From: Dennis Newbold <dennisn@pe.net>
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Subject: Looking For Profiling Tools
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Dear Linux-Mips Mailing List Members,

     We have an application running under Linux on a Mips processor.
We are currently interested in doing some performance tuning and
bottleneck analysis on this application.  Searching the web turns
up alot of profiling tools of various kinds, but they are almost
universally oriented toward a PC / IA32 architecture.  The more useful
ones generally are tightly coupled to the PC hardware, and specifically
the timer chip.

     I wondered if any of you are aware of any porfiling tools which
can be used on a Linux/Mips OS/Platform, or perhaps someone has written
something for there own use that you'd be willing to share?

Some specific info about our environment:

   1. its a little endian processor using the MIPS IV architecture / IS

   2. the application is written in C, and compiled with the gcc 2.95.2
      C compiler

   3. the Linux kernel is 2.0,xx, mostly because we lack the resources
      to upgrade / port to 2.2 or 2.4.  Someday, hopefully (:

Any suggestions, help you can offer would be appreciated.  Thanks.

Dennis

P.S.  Please respond to my personal email address, as I'm not subscribed
      to the mailing list.

---------------------------------------------
|                                           |
|     The way to be happy is to be good     |
|                                           |
---------------------------------------------


From ralf@linux-mips.org Thu Dec  5 04:35:03 2002
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From: Ralf Baechle <ralf@linux-mips.org>
To: "Kevin D. Kissell" <kevink@mips.com>
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On Wed, Dec 04, 2002 at 10:09:54AM +0100, Kevin D. Kissell wrote:

> For those on the list who don't understand Carsten's sense
> of humour, I think that was missing a smiley!  ;-)
> I mean, sure, we'd like to move more people toward SDE, 
> but "force" is putting it a bit strongly!  And if those directives
> are really being used unconditionally, I worry that the code
> being generated is likewise emitting MIPS32 instructions
> that won't work on the "ghost fleet" of abandoned workstations
> now running Linux on R4K/R5K CPUs.

A fix is now in CVS.  With this fix only compiling a kernel for MIPS32
and MIPS64 CPUs will require a the new tools.

Everybody satisfied?

I was quite amazed how much email in just like 2 days this change was
producing, even people binutils 2.8 started yelling ...

  Ralf

From kevink@mips.com Thu Dec  5 10:23:25 2002
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Subject: Re: possible Malta 4Kc cache problem ...
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> On Wed, Dec 04, 2002 at 11:08:20AM +0100, Carsten Langgaard wrote:
> > I have just tried your test on a 4Kc and I see no problems.
> > However I'm running on our internal kernel sources, and as Kevin mention we have
> > changed a fixed a few things in this area.
> > As Kevin also mention it sure look more like a I-cache invalidation problem,
> > rather than a D-cache flush problem, as the 4Kc has a write-through cache.
> > One think you could try, is our latest kernel release. You can find it here:
> > ftp://ftp.mips.com/pub/linux/mips/kernel/2.4/images/
> >
> 
> Yes, the problem still exists with this kernel.
> 
> Try to move the source tree to /root/, rename top dir to "try18", 
> re-make the binary, and try again.
> 
> This problem is tricky to reproduce.  The location of the tree
> definitely matters.  I am testing 32bit LE version.  Have not
> tried BE.
> 
> I think I have pinned down the problem.  See my other follow-up posting.

Your results are certainly interesting and suspicious.
Before I take it up with the designers as a possible
hardware bug, I would really like to know if there
is more than one chip which exhibits this behavior.
In principle, it *could* be a manufacturing defect.
And while I acknowledge that your trace info
would seem to argue on the face of it that the
hardware didn't do what it should have done,
there is a remarkable similarity between what
you report and something that Carsten saw on
a couple of completely different CPUs a week
or two ago, which makes me wonder if there isn't
still some subtle software failure behind all this.
Thank you very, very, much for digging into
this as deeply as you have.

            Kevin K.

From dom@algor.co.uk Thu Dec  5 10:32:39 2002
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Carsten,

> I think we should get rid of the prefetches until someone comes up with a
> version that doesn't prefetch beyond the copy destination/source area.

I agree.

--
Dominic

From carstenl@mips.com Thu Dec  5 10:39:37 2002
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Subject: Re: possible Malta 4Kc cache problem ...
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I think I know what the problem is, the PRID is telling me everything.
Jun Sun, you have just found an ancient 4Kc bug, sorry if you spend a
lot of time debugging this.
We have a newer TMSC 4Kc board, which doesn't have this problem
You fix flushing the whole cache works, but the problem with this kind
of bug, is that there are other potential problems.

There is what the errata sheet says:

E16. Fill buffers not flushed on CACHE instructions
Problem: The fill buffers in the cache controllers were not flushed by
CACHE instructions. Under certain circumstances, the fill buffer could
service future loads even though the cache was invalidated with the
intent of causing a refill from memory. The ICache fill buffer is left
valid for all cache refills (and all cacheable read requests) until the
following cache miss. In this case, memory was being updated and the
ICache was being cleared. The line being cleared was the last one to be
filled and there was not another cache miss before that line was
re-accessed. The second fetch can get the stale data from the fill
buffer. A similar problem exists in the DCache, but the DFB is
invalidated when the cache is written. Thus, the only time this would be
seen is if all ways of the DCache were locked and the fill buffer was
being treated as an  extra way of the cache.

Implication: This could show up in any place where self modifying code
exists and the ICache is selectively flushed. (If the entire cache is
flushed, there will be an intervening cache miss or uncached reference
to flush the FB). The problem with the DCache would primarily show up
when accessing the same memory with different physical addresses or
cache coherency attributes. If an invalidate is used to flush an entry
from the DCache with the intent of forcing a refill, the refill may not
occur.

Workarounds: Flush the entire ICache when using self-modifying code.
Force a cache miss, cache refill, or uncached access to clear fill
buffers near the invalidation. For the instruction cache, this could be
done by using a CACHE Fill instruction to pre-load the invalidation
routine into the cache. This will force a refill which will flush the
fill buffer.

Status: Fixed.


/Carsten


Jun Sun wrote:

> I guess I still did not answer some of your questions:
>
> On Wed, Dec 04, 2002 at 09:28:34PM +0100, Carsten Langgaard wrote:
> > Could you please tell us, which 4Kc you are running on ?
>
> Is the PRID telling enough?  I posted it in the other email.
>
> > What are the cache configuration (size, number of ways) ?
> > Are you running on the latest kernel sources from the CVS tree ?
>
> Debugging work is done with my kernel, but confirmed that latest
> CVS tree shows the same problem.
>
> > Have you tried the mips32_cache.h file I send and
>
> No, because I don't think it is related to indexed cache operations.
>
> > /or have you tried the kernel
> > from the ftp.mips.com FTP server ?
> >
>
> Jun

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
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                   Denmark             http://www.mips.com




From carstenl@mips.com Thu Dec  5 11:47:35 2002
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Date: Thu, 05 Dec 2002 11:47:26 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Compiler problems with zero-length array in the middle of a struct
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Some compiler reject a zero-length array in the middle of a structure,
and report it as an error.
So could we please redo the change, that has recently been done to
include/linux/raid/md_p.h (see patch below).

/Carsten



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Index: include/linux/raid/md_p.h
===================================================================
RCS file: /home/cvs/linux/include/linux/raid/md_p.h,v
retrieving revision 1.3
diff -u -r1.3 md_p.h
--- include/linux/raid/md_p.h	28 Nov 2000 03:59:04 -0000	1.3
+++ include/linux/raid/md_p.h	5 Dec 2002 10:40:55 -0000
@@ -151,10 +151,12 @@
 	 */
 	mdp_disk_t disks[MD_SB_DISKS];
 
+#if MD_SB_RESERVED_WORDS
 	/*
 	 * Reserved
 	 */
 	__u32 reserved[MD_SB_RESERVED_WORDS];
+#endif
 
 	/*
 	 * Active descriptor

--------------263E4BD1E717834E31EFD8E6--


From Geert.Uytterhoeven@sonycom.com Thu Dec  5 12:08:02 2002
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Date: Thu, 5 Dec 2002 12:07:48 +0100 (MET)
From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Ralf Baechle <ralf@linux-mips.org>
cc: Linux/MIPS Development <linux-mips@linux-mips.org>
Subject: Old SGI penguin logo
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In 2.4.6, the penguin logos were updated in Linus' tree for all architectures
(cfr.  http://home.tvd.be/cr26864/Linux/fbdev/logo.html).

However, the MIPS merge in 2.4.10 reverted that change in include/asm-mips/,
and introduced a new logo for DECstations. The logo in include/asm-mips64/ was
not affected by this merge.

This patch updates the logo for non-DEC machines, and brings the other parts of
the MIPS-specific logo code in sync with the other architectures. It applies to
both 2.4.x and 2.5.x.

--- linux-mips-2.4.x/include/asm-mips/linux_logo.h	Mon Aug 26 11:33:33 2002
+++ geert-mips-2.4.x/include/asm-mips/linux_logo.h	Thu Dec  5 11:33:51 2002
@@ -28,16 +28,5 @@
 #	include <asm/linux_logo_dec.h>
 #endif
 
-#ifndef INCLUDE_LINUX_LOGO_DATA
-/* prototypes only */
-extern unsigned char linux_logo_red[];
-extern unsigned char linux_logo_green[];
-extern unsigned char linux_logo_blue[];
-extern unsigned char linux_logo[];
-extern unsigned char linux_logo_bw[];
-extern unsigned char linux_logo16_red[];
-extern unsigned char linux_logo16_green[];
-extern unsigned char linux_logo16_blue[];
-extern unsigned char linux_logo16[];
+#include <linux/linux_logo.h>
 
-#endif
--- linux-mips-2.4.x/include/asm-mips/linux_logo_dec.h	Mon Aug 26 11:33:33 2002
+++ geert-mips-2.4.x/include/asm-mips/linux_logo_dec.h	Thu Dec  5 11:33:51 2002
@@ -13,11 +13,13 @@
 #include <linux/version.h>
 
 #define linux_logo_banner "Linux/MIPSel version " UTS_RELEASE
-#define LINUX_LOGO_COLORS 183
 
 #define __HAVE_ARCH_LINUX_LOGO
 
+#define LINUX_LOGO_COLORS 183
+
 #ifdef INCLUDE_LINUX_LOGO_DATA
+
 unsigned char linux_logo_red[] __initdata = {
     0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
     0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
@@ -899,8 +901,5 @@
     0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
 };
 
-#define INCLUDE_LINUX_LOGOBW
-#define INCLUDE_LINUX_LOGO16
-#include <linux/linux_logo.h>
+#endif /* INCLUDE_LINUX_LOGO_DATA */
 
-#endif
--- linux-mips-2.4.x/include/asm-mips/linux_logo_sgi.h	Tue Jul  2 14:19:16 2002
+++ geert-mips-2.4.x/include/asm-mips/linux_logo_sgi.h	Thu Dec  5 11:33:51 2002
@@ -12,906 +12,895 @@
 #include <linux/version.h>
 
 #define linux_logo_banner "Linux/MIPS version " UTS_RELEASE
-#define LINUX_LOGO_COLORS 212
 
 #define __HAVE_ARCH_LINUX_LOGO
 
+#define LINUX_LOGO_COLORS 212
+
 #ifdef INCLUDE_LINUX_LOGO_DATA
+
 unsigned char linux_logo_red[] __initdata = {
-  0x03, 0x82, 0xE9, 0xBF, 0x42, 0xC9, 0x7E, 0xC0,
-  0xE9, 0xE3, 0xC2, 0x24, 0xA4, 0x65, 0xEC, 0xC4,
-  0x82, 0x9F, 0xF3, 0x12, 0x5F, 0xA0, 0xC2, 0xED,
-  0x3E, 0xD5, 0xDB, 0xA0, 0x1C, 0xF4, 0xEB, 0xA4,
-  0xCD, 0x0A, 0x9A, 0x51, 0xCC, 0xBE, 0xC0, 0xBA,
-  0x74, 0xDC, 0xAA, 0xF6, 0xD3, 0xC5, 0xE6, 0x26,
-  0xC2, 0x83, 0x38, 0xEA, 0x49, 0xB0, 0xED, 0xE5,
-  0xF4, 0x96, 0x96, 0x1B, 0xFA, 0xCC, 0xF2, 0x0F,
-  0xCD, 0xE5, 0xF4, 0xD3, 0x50, 0x7A, 0xB5, 0xDE,
-  0xD5, 0xB6, 0x60, 0x0A, 0x6A, 0xEA, 0xD4, 0xEB,
-  0xC1, 0xCA, 0xEA, 0xEC, 0x2A, 0x96, 0x95, 0xDC,
-  0xE4, 0xCE, 0xEC, 0x1E, 0xDC, 0x8A, 0xD1, 0xF6,
-  0x3C, 0x5E, 0xC6, 0xB4, 0xB2, 0xAC, 0xBA, 0x9E,
-  0x0F, 0x59, 0xBA, 0xFA, 0xCC, 0xBF, 0x82, 0xCE,
-  0xE6, 0x4F, 0xAA, 0x4C, 0xCA, 0x8E, 0x8E, 0xDF,
-  0x2C, 0xB6, 0x3B, 0xDE, 0xCE, 0xEE, 0x46, 0x4A,
-  0x6F, 0x7A, 0x82, 0xE4, 0xAA, 0x88, 0xE2, 0xCE,
-  0xAE, 0xB6, 0x70, 0xC2, 0x9A, 0xDA, 0x35, 0x9E,
-  0x95, 0xC0, 0x7E, 0x8C, 0xC2, 0xB6, 0xCE, 0xB9,
-  0xD5, 0xAA, 0xC1, 0xF4, 0xC7, 0xB6, 0xB6, 0xA3,
-  0xF2, 0x68, 0xDB, 0x76, 0xDC, 0x57, 0xD3, 0xA8,
-  0xC0, 0xEF, 0x46, 0xF4, 0x2F, 0xD7, 0x53, 0x36,
-  0xE6, 0xA7, 0xCA, 0xCB, 0x7E, 0xE4, 0x86, 0x9A,
-  0xCE, 0x94, 0xB4, 0x1D, 0xDA, 0xCE, 0x6C, 0xE6,
-  0x9E, 0xC6, 0xDA, 0x16, 0xFA, 0xAA, 0x56, 0xB6,
-  0xFE, 0x6E, 0xEA, 0xCE, 0xE5, 0xCC, 0xDB, 0xD3,
-  0xED, 0xDC, 0xF4, 0x72
+    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
+    0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
+    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x02, 0x65,
+    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
+    0xc3, 0x65, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
+    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
+    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x76, 0x79,
+    0x62, 0x36, 0x9a, 0xe2, 0xec, 0xe1, 0xb8, 0xd7,
+    0xaf, 0x25, 0xbc, 0xc0, 0xef, 0xea, 0xe8, 0xe8,
+    0xf5, 0xf1, 0xda, 0xd3, 0x79, 0xdb, 0xf4, 0xf6,
+    0xf6, 0xf6, 0xe2, 0x3d, 0xb4, 0xce, 0xe6, 0xee,
+    0xf6, 0x68, 0xd8, 0xec, 0xf5, 0xc6, 0xc8, 0x9c,
+    0x89, 0xd2, 0xee, 0xcb, 0xb9, 0xd2, 0x66, 0x5e,
+    0x8b, 0xbe, 0xa8, 0xd5, 0xca, 0xb6, 0xae, 0x9c,
+    0xc5, 0xbe, 0xbe, 0xca, 0x90, 0xb2, 0x9a, 0xa8,
+    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
+    0x12, 0x4a, 0x8e, 0xf2, 0xf6, 0xee, 0xb5, 0xe4,
+    0xf1, 0x26, 0x9a, 0xea, 0xf6, 0xe0, 0xd2, 0x16,
+    0x9a, 0x2e, 0x70, 0xd6, 0x46, 0x7c, 0xb4, 0x62,
+    0xd6, 0xa3, 0x74, 0xa7, 0xa2, 0xca, 0xe0, 0xae,
+    0xbe, 0xce, 0xa3, 0x8e, 0x6d, 0x8e, 0x32, 0xaf,
+    0x50, 0x9e, 0x5b, 0x8a, 0x98, 0x82, 0x7a, 0x82,
+    0x56, 0x7c, 0x8a, 0x56, 0x5e, 0x86, 0x6a, 0x52,
+    0x59, 0x64, 0x5e,
 };
 
 unsigned char linux_logo_green[] __initdata = {
-  0x03, 0x82, 0xC4, 0x83, 0x42, 0xA2, 0x4A, 0xA4,
-  0xE5, 0xA6, 0xC2, 0x24, 0xA4, 0x65, 0xB4, 0x94,
-  0x66, 0x87, 0xB6, 0x12, 0x44, 0x6C, 0x96, 0xD4,
-  0x36, 0x95, 0xB2, 0x92, 0x0E, 0xF4, 0xBC, 0x77,
-  0xA5, 0x0A, 0x92, 0x52, 0xB4, 0x9A, 0x8C, 0xB2,
-  0x74, 0xC2, 0x8E, 0xBD, 0xA2, 0xCA, 0xD2, 0x12,
-  0xB6, 0x61, 0x24, 0xDA, 0x33, 0x79, 0xCB, 0xAC,
-  0xDA, 0x84, 0x7A, 0x1B, 0xFA, 0x8D, 0xBE, 0x06,
-  0x93, 0xBB, 0xBC, 0xAB, 0x44, 0x62, 0x83, 0xDA,
-  0x9B, 0xA2, 0x4C, 0x04, 0x6A, 0xB6, 0xC8, 0xBD,
-  0x8D, 0xB6, 0xAD, 0xEC, 0x2A, 0x68, 0x62, 0x9D,
-  0xC4, 0xC4, 0xB4, 0x13, 0xA3, 0x8A, 0xD2, 0xD6,
-  0x3C, 0x5D, 0x8C, 0x7E, 0x82, 0xAC, 0x96, 0x7E,
-  0x0D, 0x5A, 0xBA, 0xBB, 0xCC, 0xBE, 0x76, 0xB6,
-  0xDE, 0x4E, 0x9A, 0x3C, 0xBE, 0x8E, 0x6E, 0xCB,
-  0x1C, 0xAA, 0x2E, 0xBE, 0xAA, 0xDE, 0x3E, 0x4B,
-  0x4D, 0x7A, 0x54, 0xE4, 0x8E, 0x6E, 0xCA, 0x9B,
-  0x70, 0x9E, 0x5A, 0xAA, 0x9A, 0xBE, 0x34, 0x9E,
-  0x71, 0x9E, 0x7E, 0x5F, 0xAA, 0x8A, 0xBE, 0x91,
-  0xCE, 0x88, 0x92, 0xDB, 0xC6, 0xAB, 0x8A, 0x72,
-  0xE2, 0x44, 0xC3, 0x54, 0xAA, 0x45, 0xBB, 0x92,
-  0xBA, 0xC4, 0x46, 0xCA, 0x2D, 0xD6, 0x3B, 0x1A,
-  0xC2, 0x7E, 0xA6, 0xCB, 0x7A, 0xDC, 0x86, 0x72,
-  0xB6, 0x94, 0xB4, 0x1C, 0xBC, 0xAE, 0x4C, 0xD6,
-  0x62, 0x86, 0xD3, 0x16, 0xF6, 0x7A, 0x55, 0x79,
-  0xFE, 0x6E, 0xC6, 0xC6, 0xAA, 0x93, 0xDC, 0x9D,
-  0xAE, 0xA4, 0xD4, 0x56
+    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
+    0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
+    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x02, 0x65,
+    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
+    0xc3, 0x62, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
+    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
+    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x62, 0x5c,
+    0x4e, 0x26, 0x72, 0xaa, 0xba, 0xaf, 0x90, 0xae,
+    0x92, 0x1a, 0xa4, 0x85, 0xb6, 0xbe, 0xc3, 0xc8,
+    0xcf, 0xd0, 0xc2, 0xce, 0x57, 0xa2, 0xd6, 0xda,
+    0xda, 0xd7, 0xb8, 0x2a, 0x7b, 0x91, 0xae, 0xca,
+    0xda, 0x45, 0x9e, 0xb2, 0xd7, 0x9b, 0x90, 0x76,
+    0x5c, 0xa2, 0xbe, 0xa6, 0x85, 0x96, 0x4e, 0x46,
+    0x66, 0x92, 0x7a, 0x9a, 0x96, 0x9d, 0x9a, 0x6b,
+    0x8a, 0x8e, 0xb2, 0xca, 0x90, 0xa6, 0x79, 0x7c,
+    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
+    0x0e, 0x36, 0x86, 0xba, 0xbe, 0xcc, 0x8e, 0xb8,
+    0xc4, 0x1e, 0x8e, 0xae, 0xba, 0xb2, 0xa6, 0x12,
+    0x7a, 0x20, 0x64, 0xaa, 0x2f, 0x70, 0x85, 0x46,
+    0xa6, 0x6e, 0x51, 0x72, 0x92, 0xa2, 0xa6, 0x87,
+    0x96, 0xa2, 0x85, 0x7a, 0x6a, 0x6e, 0x22, 0x76,
+    0x36, 0x76, 0x3c, 0x6e, 0x63, 0x53, 0x66, 0x62,
+    0x42, 0x50, 0x56, 0x42, 0x56, 0x56, 0x56, 0x3e,
+    0x51, 0x52, 0x56,
 };
 
 unsigned char linux_logo_blue[] __initdata = {
-  0x04, 0x84, 0x10, 0x0C, 0x41, 0x14, 0x04, 0x78,
-  0xC7, 0x0E, 0xC4, 0x24, 0xA4, 0x64, 0x0C, 0x0D,
-  0x17, 0x24, 0x0D, 0x13, 0x11, 0x07, 0x40, 0x22,
-  0x0C, 0x0C, 0x11, 0x78, 0x06, 0xF4, 0x0B, 0x0A,
-  0x47, 0x0B, 0x7C, 0x54, 0x6C, 0x0C, 0x0D, 0x9C,
-  0x73, 0x54, 0x14, 0x0C, 0x0F, 0xC7, 0x94, 0x04,
-  0x94, 0x17, 0x0A, 0x6C, 0x08, 0x0F, 0x14, 0x0B,
-  0x12, 0x68, 0x28, 0x11, 0xFA, 0x0A, 0x34, 0x09,
-  0x0A, 0x2F, 0x15, 0x19, 0x14, 0x3C, 0x06, 0xC4,
-  0x0B, 0x84, 0x24, 0x08, 0x69, 0x38, 0xBC, 0x15,
-  0x1F, 0xA0, 0x0A, 0xEC, 0x2A, 0x0C, 0x0C, 0x0C,
-  0x2C, 0xA0, 0x15, 0x07, 0x0B, 0x8C, 0xD3, 0x10,
-  0x3B, 0x5C, 0x0C, 0x04, 0x3C, 0xAC, 0x54, 0x1C,
-  0x0B, 0x5B, 0xBB, 0x0A, 0xC1, 0xBB, 0x5C, 0x3C,
-  0xBC, 0x4D, 0x74, 0x10, 0x8C, 0x8C, 0x14, 0x91,
-  0x0C, 0x74, 0x17, 0x0C, 0x48, 0x9C, 0x3C, 0x4C,
-  0x09, 0x7C, 0x05, 0xE4, 0x34, 0x38, 0x6C, 0x11,
-  0x08, 0x7C, 0x18, 0x2C, 0x9C, 0x4C, 0x34, 0x9C,
-  0x29, 0x54, 0x7C, 0x0C, 0x78, 0x18, 0x9C, 0x14,
-  0xBA, 0x30, 0x27, 0x31, 0xC2, 0x97, 0x24, 0x09,
-  0xB4, 0x04, 0x87, 0x0C, 0x14, 0x1F, 0x7C, 0x64,
-  0xB0, 0x0F, 0x45, 0x10, 0x2C, 0xD4, 0x0A, 0x04,
-  0x44, 0x1F, 0x2C, 0xCC, 0x7C, 0xD8, 0x84, 0x0C,
-  0x8C, 0x94, 0xB4, 0x1D, 0x20, 0x5C, 0x18, 0xB4,
-  0x04, 0x09, 0xBC, 0x14, 0xF4, 0x08, 0x54, 0x07,
-  0xFC, 0x6C, 0x24, 0xB4, 0x15, 0x18, 0xDB, 0x17,
-  0x17, 0x18, 0x21, 0x24
+    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
+    0x12, 0x01, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
+    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x06, 0x65,
+    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
+    0xc3, 0x59, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
+    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
+    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x2e, 0x08,
+    0x0a, 0x06, 0x0a, 0x0b, 0x0b, 0x0f, 0x0c, 0x0f,
+    0x3d, 0x09, 0x73, 0x09, 0x0d, 0x0a, 0x10, 0x1e,
+    0x2d, 0x13, 0x86, 0xba, 0x19, 0x0a, 0x36, 0x3c,
+    0x26, 0x14, 0x0d, 0x06, 0x07, 0x0a, 0x0b, 0x0f,
+    0x4a, 0x06, 0x0a, 0x0c, 0x2b, 0x0a, 0x0b, 0x0a,
+    0x06, 0x0a, 0x0a, 0x11, 0x0b, 0x0a, 0x0a, 0x1e,
+    0x0f, 0x0d, 0x0a, 0x0b, 0x22, 0x6a, 0x72, 0x0b,
+    0x0b, 0x22, 0x90, 0xca, 0x90, 0x92, 0x3c, 0x2c,
+    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
+    0x06, 0x0e, 0x6a, 0x0e, 0x0e, 0x5b, 0x2c, 0x3e,
+    0x0e, 0x0a, 0x5a, 0x0d, 0x0e, 0x3e, 0x0a, 0x06,
+    0x2e, 0x06, 0x4e, 0x36, 0x06, 0x58, 0x24, 0x06,
+    0x3a, 0x08, 0x08, 0x07, 0x5e, 0x45, 0x0a, 0x32,
+    0x2e, 0x2a, 0x43, 0x48, 0x5f, 0x2e, 0x06, 0x06,
+    0x07, 0x24, 0x06, 0x32, 0x06, 0x06, 0x46, 0x2e,
+    0x22, 0x06, 0x06, 0x1e, 0x4c, 0x06, 0x3a, 0x22,
+    0x42, 0x34, 0x42,
 };
 
 unsigned char linux_logo[] __initdata = {
-  0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF,
-  0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA, 0xDA, 0x2C,
-  0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A, 0x8A, 0xDA,
-  0x85, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0xD9, 0xD9,
-  0xAF, 0x85, 0x85, 0x85, 0x8D, 0xBC, 0x2A, 0x2A,
-  0xBC, 0x8C, 0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85,
-  0x2C, 0x2C, 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
-  0x2C, 0xAF, 0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA,
-  0xDA, 0x2C, 0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A,
-  0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D,
-  0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
-  0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA, 0x85, 0x2C,
-  0x2C, 0xAC, 0xD9, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C,
-  0x2C, 0x85, 0x2C, 0x2C, 0x85, 0xDA, 0xDA, 0xDA,
-  0xDA, 0xDA, 0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C,
-  0x2C, 0xAC, 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
-  0xD9, 0x7D, 0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA,
-  0x85, 0x2C, 0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA,
-  0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF,
-  0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0x7D,
-  0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
-  0xAF, 0x2C, 0x2C, 0xDA, 0x85, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xD9, 0xAF, 0xDA, 0x85, 0x2C, 0x2C,
-  0x85, 0xDA, 0xDA, 0x85, 0x85, 0xDA, 0x85, 0x85,
-  0x85, 0xAF, 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85,
-  0x2C, 0xAF, 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9,
-  0xD9, 0x7D, 0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA,
-  0x85, 0x2C, 0xAF, 0x2C, 0x2C, 0xDA, 0xDA, 0x85,
-  0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAF,
-  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0x95,
-  0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
-  0xAC, 0xAC, 0x2C, 0x2C, 0x85, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xD9, 0x2C, 0x91, 0x41, 0x20, 0x6B, 0x20,
-  0x6B, 0x20, 0x6B, 0xAE, 0x2C, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA,
-  0x85, 0xAF, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
-  0x95, 0x95, 0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA,
-  0x85, 0x2C, 0xAC, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
-  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0xD9,
-  0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xAF, 0xAC,
-  0x2C, 0xB2, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x6B, 0x80, 0x85, 0x2C,
-  0xD9, 0xD6, 0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA,
-  0x85, 0x2C, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
-  0xD9, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85,
-  0x2C, 0xD9, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF,
-  0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA, 0x2C, 0xAC,
-  0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0xAF, 0x2C,
-  0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xAC, 0xD9,
-  0xD9, 0xD9, 0xAF, 0xAF, 0x2C, 0x2C, 0xAF, 0xDA,
-  0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xE3, 0x20, 0x6B, 0x48,
-  0xAC, 0x95, 0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA,
-  0x2C, 0xAC, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
-  0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0xAF,
-  0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
-  0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
-  0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0xAF, 0xAC,
-  0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x89,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x74, 0x43, 0x80, 0x41, 0x20,
-  0x9F, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85,
-  0x2C, 0xD9, 0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C,
-  0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF,
-  0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xD9,
-  0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
-  0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC,
-  0xAF, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x41,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xAE, 0x48, 0x89, 0x74, 0x41,
-  0x6B, 0xD6, 0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85,
-  0x2C, 0xD9, 0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C,
-  0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF,
-  0xAF, 0xAC, 0xAF, 0xAC, 0xAC, 0x2C, 0xAF, 0xAC,
-  0x2C, 0x7D, 0xD9, 0x2C, 0xDA, 0x85, 0x2C, 0x7D,
-  0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0x85,
-  0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0xD9,
-  0x95, 0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x48, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x6B, 0xAE, 0xE6, 0x80, 0x2B, 0x88,
-  0x20, 0x33, 0xDA, 0x95, 0xD9, 0x2C, 0xDA, 0x85,
-  0x2C, 0x7D, 0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85,
-  0x85, 0x85, 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC,
-  0xAC, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9,
-  0x85, 0xD9, 0x2C, 0x85, 0xDA, 0xDA, 0xD9, 0x21,
-  0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, 0x85, 0xAF,
-  0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, 0x7D, 0xD6,
-  0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0x85, 0xDB, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xDB, 0xE3, 0x6B, 0x20, 0x20,
-  0x20, 0x20, 0xE9, 0xD9, 0x2C, 0x85, 0xDA, 0xDA,
-  0xD9, 0x21, 0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA,
-  0x85, 0xAF, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9,
-  0x7D, 0xD6, 0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
-  0xDA, 0x2C, 0x85, 0xDA, 0xDA, 0x85, 0x95, 0x21,
-  0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xD9,
-  0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xAC, 0xAC, 0x2C, 0xAF, 0x2C, 0x85, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x88, 0xDA, 0x85, 0xDA, 0xDA, 0x85,
-  0x95, 0x21, 0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C,
-  0x2C, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xD9, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xDA, 0x2C, 0x85, 0x85, 0x2C, 0xD9, 0xD6, 0xB2,
-  0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC, 0x95, 0x95,
-  0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0x2C, 0x85,
-  0x85, 0x85, 0x85, 0x85, 0x85, 0xAC, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xAC, 0x85, 0x85, 0x2C, 0xD9,
-  0xD6, 0xB2, 0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC,
-  0x95, 0x95, 0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
-  0x85, 0x2C, 0x2C, 0x2C, 0xAC, 0x95, 0xD6, 0x7D,
-  0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D, 0x7D, 0x95,
-  0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9, 0x2C, 0x85,
-  0xDA, 0xDA, 0xDA, 0x85, 0x85, 0x21, 0x20, 0x20,
-  0x6B, 0x41, 0xDB, 0x6B, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xDB, 0xDB, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xE6, 0x2C, 0x2C, 0xAC, 0x95,
-  0xD6, 0x7D, 0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D,
-  0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9,
-  0x2C, 0x85, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
-  0x2C, 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD9,
-  0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6, 0xD9, 0xAF,
-  0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9, 0x2C, 0x85,
-  0xDA, 0xDA, 0x2C, 0xAF, 0xAF, 0x21, 0x20, 0x20,
-  0x88, 0x2B, 0x88, 0x74, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0xAE, 0x2D, 0x2D, 0x74, 0x74, 0x88, 0x20,
-  0x20, 0x20, 0x20, 0x80, 0xAC, 0xD9, 0x95, 0xD6,
-  0xD6, 0xD9, 0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6,
-  0xD9, 0xAF, 0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9,
-  0x2C, 0xDA, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
-  0x2C, 0xAF, 0xD9, 0x95, 0xD6, 0xD6, 0x95, 0xAF,
-  0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95, 0xAF, 0x2C,
-  0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C, 0x85, 0x85,
-  0x85, 0xAF, 0xD9, 0x95, 0xD9, 0x7D, 0x20, 0x33,
-  0x7D, 0x8A, 0x7D, 0x5B, 0x6B, 0x20, 0x20, 0x6B,
-  0xE6, 0xD9, 0x85, 0x2A, 0xDA, 0x2B, 0x41, 0x20,
-  0x20, 0x20, 0x6B, 0x74, 0xD9, 0x95, 0xD6, 0xD6,
-  0x95, 0xAF, 0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95,
-  0xAF, 0x2C, 0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C,
-  0x85, 0x85, 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x85, 0xD9, 0x7D, 0x21, 0x21, 0x7D, 0xAC, 0x2C,
-  0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF, 0x2C, 0x85,
-  0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA, 0x8A, 0xDA,
-  0x85, 0xAF, 0xD9, 0x7D, 0xD9, 0x95, 0x20, 0x91,
-  0xBC, 0x73, 0xEE, 0x7D, 0x20, 0x20, 0x20, 0x80,
-  0x4D, 0x3D, 0x73, 0x73, 0xA3, 0xD6, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x2B, 0x7D, 0x21, 0x21, 0x7D,
-  0xAC, 0x2C, 0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF,
-  0x2C, 0x85, 0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA,
-  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0x7D, 0xD9, 0xAC,
-  0x2C, 0xD9, 0xD6, 0xB2, 0xB2, 0x7D, 0xAF, 0x85,
-  0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C, 0x2C, 0x2C,
-  0xD9, 0xD9, 0xAC, 0x85, 0x8D, 0x2A, 0x2A, 0xDA,
-  0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAC, 0x20, 0xAF,
-  0x2C, 0xE6, 0x8D, 0x73, 0xE3, 0x20, 0x20, 0x48,
-  0x5C, 0xDA, 0x5B, 0x43, 0xBC, 0x73, 0x2B, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0xB2, 0x7D,
-  0xAF, 0x85, 0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C,
-  0x2C, 0x2C, 0xD9, 0xD9, 0xAC, 0x85, 0x8A, 0x2A,
-  0x8D, 0xDA, 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
-  0xAC, 0xD9, 0xD6, 0xB2, 0x21, 0xD9, 0x2C, 0x85,
-  0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C, 0x2C, 0xAC,
-  0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0xBC, 0xDA, 0xD9,
-  0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xAC, 0x20, 0x2A,
-  0xCC, 0xAE, 0x9F, 0xE4, 0xAE, 0x5B, 0x74, 0xA1,
-  0xE4, 0xAE, 0x20, 0x9F, 0x89, 0xE8, 0xE6, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0x21, 0xD9,
-  0x2C, 0x85, 0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C,
-  0x2C, 0xAC, 0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0x2A,
-  0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9,
-  0xD9, 0x95, 0x21, 0xA1, 0x21, 0xAC, 0x85, 0x85,
-  0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0xAF, 0xAC,
-  0xAF, 0x85, 0x8A, 0x2A, 0x2A, 0xDA, 0xD9, 0xA1,
-  0x48, 0xE9, 0x48, 0x21, 0x95, 0xAC, 0x20, 0x2A,
-  0xDB, 0x41, 0x74, 0xBC, 0x2B, 0x7B, 0x7B, 0x80,
-  0x73, 0x41, 0x20, 0x6B, 0x2B, 0xE8, 0x2D, 0x20,
-  0x20, 0x20, 0x20, 0x33, 0x21, 0xA1, 0x21, 0xAC,
-  0x85, 0x85, 0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C,
-  0xAF, 0xAC, 0xAF, 0x85, 0x8A, 0xBC, 0x2A, 0xDA,
-  0xD9, 0xA1, 0x48, 0xE9, 0x48, 0x21, 0xD9, 0xD9,
-  0xA1, 0xB2, 0xB2, 0x48, 0xD6, 0xAC, 0x2C, 0x2C,
-  0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
-  0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95, 0xA1, 0x6C,
-  0x6C, 0x48, 0xD6, 0xD9, 0x2C, 0x85, 0x20, 0x2C,
-  0x89, 0x20, 0x3C, 0xB9, 0xA7, 0x63, 0xD2, 0xB9,
-  0xC6, 0x9A, 0x20, 0x20, 0x43, 0x5C, 0xE6, 0x20,
-  0x20, 0x20, 0x20, 0x33, 0xB2, 0x48, 0xD6, 0xAC,
-  0x2C, 0x2C, 0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C,
-  0x2C, 0x2C, 0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95,
-  0xA1, 0x6C, 0x6C, 0x48, 0xD6, 0xD9, 0xAF, 0xAC,
-  0xA1, 0xD6, 0x7D, 0xB2, 0xD6, 0xAF, 0x85, 0x85,
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+    0xa4, 0x64, 0x76, 0x7a, 0x91, 0xb5, 0x31, 0x30,
+    0x28, 0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x24,
+    0x39, 0x97, 0x75, 0xbe, 0x7b, 0x64, 0xa3, 0xa3,
+    0xac, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0x7b, 0x7a, 0xc7,
+    0xc8, 0x36, 0x21, 0x26, 0x2b, 0x39, 0x33, 0x30,
+    0x23, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x21, 0xc8, 0xbb, 0x8b, 0x7b, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa3, 0x64, 0x64,
+    0x76, 0x85, 0xbf, 0xb5, 0x34, 0x2b, 0x27, 0x28,
+    0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x28,
+    0x33, 0xc9, 0x63, 0x7e, 0x7a, 0x6d, 0xbe, 0x5b,
+    0x76, 0x7b, 0x64, 0x64, 0xa3, 0xac, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xac, 0x76, 0x85, 0xb9,
+    0x79, 0x22, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x21, 0xca, 0xbb, 0x75, 0x76, 0xa3, 0xa4,
+    0xa4, 0xa4, 0xac, 0xa3, 0x64, 0x76, 0xbe, 0x8b,
+    0xb6, 0xb5, 0x2f, 0x35, 0x30, 0x24, 0x22, 0x21,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x23,
+    0x27, 0x31, 0xcb, 0xc9, 0xbb, 0x74, 0x63, 0x90,
+    0x7e, 0x75, 0x8b, 0x6d, 0xbe, 0x76, 0x64, 0xa3,
+    0xac, 0xac, 0xac, 0xac, 0x64, 0x7a, 0x84, 0xcc,
+    0x79, 0xa0, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x21, 0xc8, 0xcc, 0x63, 0x6d, 0x7b, 0x64,
+    0xac, 0xa3, 0x64, 0x7b, 0xbe, 0x75, 0x63, 0x96,
+    0x38, 0x39, 0x2a, 0x24, 0x23, 0x21, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21,
+    0x28, 0x27, 0x35, 0x2d, 0x41, 0xb5, 0xc5, 0x8f,
+    0xb9, 0xbb, 0xc7, 0x74, 0x84, 0x90, 0x85, 0x6d,
+    0x5b, 0x7b, 0x7b, 0xab, 0x6d, 0x90, 0xb9, 0xcd,
+    0xca, 0x22, 0x36, 0x36, 0x28, 0x30, 0x30, 0x30,
+    0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x25, 0x36,
+    0x36, 0x21, 0xb4, 0x80, 0xc7, 0x7e, 0x6d, 0x76,
+    0xab, 0x76, 0x6d, 0x85, 0x63, 0xb9, 0xb5, 0x34,
+    0x33, 0x26, 0x23, 0x21, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x21, 0x23, 0x24, 0x27, 0x2a, 0x35, 0x2e, 0x2f,
+    0x41, 0xce, 0xcf, 0x6c, 0x80, 0xcc, 0xb9, 0x74,
+    0x84, 0x90, 0x75, 0x7e, 0x74, 0x8f, 0xcd, 0x79,
+    0xc6, 0x2b, 0x9d, 0x41, 0x2f, 0x34, 0x2d, 0x2d,
+    0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x34, 0x2f, 0x38,
+    0x4d, 0x37, 0xd0, 0xd1, 0x8f, 0x74, 0x63, 0x7e,
+    0x75, 0x7e, 0x63, 0xc7, 0x88, 0xc4, 0x31, 0x2a,
+    0x24, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x21, 0x22, 0x23, 0x24, 0x26, 0x30,
+    0x33, 0x39, 0x2e, 0x51, 0x41, 0xb2, 0x6c, 0xd1,
+    0x80, 0xcc, 0xcc, 0xcc, 0xd2, 0xd1, 0xb7, 0xd3,
+    0x41, 0x34, 0x35, 0x32, 0x30, 0x27, 0x27, 0x27,
+    0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x30, 0x2a,
+    0x2b, 0x34, 0xd4, 0xca, 0xd5, 0x8f, 0xbb, 0xc7,
+    0xc7, 0xbb, 0xcc, 0x6c, 0x41, 0x39, 0x27, 0x28,
+    0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22,
+    0x28, 0x24, 0x26, 0x2a, 0x33, 0x2c, 0x2f, 0x41,
+    0xd6, 0xb7, 0x79, 0x79, 0x79, 0xca, 0xd7, 0x51,
+    0x39, 0x30, 0x24, 0x23, 0x22, 0x22, 0x22, 0x22,
+    0x22, 0x22, 0x21, 0x22, 0x22, 0x22, 0x22, 0x23,
+    0x24, 0x2a, 0x31, 0xd8, 0xc8, 0x79, 0xd1, 0x80,
+    0xd5, 0xba, 0xd9, 0x2f, 0x35, 0x26, 0x23, 0x21,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x21, 0x22, 0x23, 0x28, 0x25, 0x30, 0x2b,
+    0x31, 0x2f, 0xd4, 0xd8, 0xd8, 0x2f, 0x2e, 0x33,
+    0x26, 0x23, 0x21, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x21, 0x28, 0x27, 0x35, 0x34, 0xd8, 0xd8, 0xd8,
+    0xda, 0xd4, 0x2e, 0x33, 0x25, 0x23, 0x21, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x23, 0x28,
+    0x26, 0x30, 0x32, 0x2b, 0x33, 0x2a, 0x26, 0x28,
+    0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x21, 0x23, 0x25, 0x30, 0x33, 0x35, 0x35,
+    0x2b, 0x2a, 0x26, 0x28, 0x22, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21,
+    0x21, 0x22, 0x23, 0x28, 0x28, 0x23, 0x22, 0x21,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x21, 0x23, 0x28, 0x24, 0x24,
+    0x28, 0x23, 0x22, 0x21, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
 };
-
-#define INCLUDE_LINUX_LOGOBW
-#define INCLUDE_LINUX_LOGO16
-#include <linux/linux_logo.h>
 
 #endif /* INCLUDE_LINUX_LOGO_DATA */

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


From carstenl@mips.com Thu Dec  5 12:14:53 2002
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From: Carsten Langgaard <carstenl@mips.com>
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CC: "Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org
Subject: Re: Latest sources from CVS.
References: <3DEDBDFC.D87C1B84@mips.com> <005701c29b74$f1f76870$10eca8c0@grendel> <20021205043444.B29939@linux-mips.org>
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Ralf Baechle wrote:

> On Wed, Dec 04, 2002 at 10:09:54AM +0100, Kevin D. Kissell wrote:
>
> > For those on the list who don't understand Carsten's sense
> > of humour, I think that was missing a smiley!  ;-)
> > I mean, sure, we'd like to move more people toward SDE,
> > but "force" is putting it a bit strongly!  And if those directives
> > are really being used unconditionally, I worry that the code
> > being generated is likewise emitting MIPS32 instructions
> > that won't work on the "ghost fleet" of abandoned workstations
> > now running Linux on R4K/R5K CPUs.
>
> A fix is now in CVS.  With this fix only compiling a kernel for MIPS32
> and MIPS64 CPUs will require a the new tools.
>
> Everybody satisfied?

Not quite, I afraid.
I would like to be able to compile a 64-bit kernel, using the
MIPS32/MIPS64 config1 register, but I don't have a MIPS64 compliant n64
compiler (assembler). So I need the hardcoded ".word" opcode version, we
previously had.

Something like this:

/*
 * This should be changed when we get a compiler that support the MIPS32
ISA.
 */
#define read_mips32_cp0_config1()                               \
({ int __res;                                                   \
        __asm__ __volatile__(                                   \
 ".set\tnoreorder\n\t"                                   \
 ".set\tnoat\n\t"                                        \
 "#.set\tmips64\n\t"     \
 "#mfc0\t$1, $16, 1\n\t"     \
 "#.set\tmips0\n\t"     \
      ".word\t0x40018001\n\t"                                 \
 "move\t%0,$1\n\t"                                       \
 ".set\tat\n\t"                                          \
 ".set\treorder"                                         \
 :"=r" (__res));                                         \
        __res;})


>
> I was quite amazed how much email in just like 2 days this change was
> producing, even people binutils 2.8 started yelling ...
>
>   Ralf

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From kevink@mips.com Thu Dec  5 12:17:50 2002
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From: "Kevin D. Kissell" <kevink@mips.com>
To: "Geert Uytterhoeven" <geert@linux-m68k.org>,
	"Ralf Baechle" <ralf@linux-mips.org>
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References: <Pine.GSO.4.21.0212051203140.7346-100000@vervain.sonytel.be>
Subject: Re: Old SGI penguin logo
Date: Thu, 5 Dec 2002 12:21:25 +0100
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I'm not that good at visualizing things based on the ASCII
source, but how does that compare with the attached GIF,
which I generated ages ago, and which is used on at least
a couple MIPS/Linux web sites?

            Kevin K.

----- Original Message ----- 
From: "Geert Uytterhoeven" <geert@linux-m68k.org>
To: "Ralf Baechle" <ralf@linux-mips.org>
Cc: "Linux/MIPS Development" <linux-mips@linux-mips.org>
Sent: Thursday, December 05, 2002 12:07 PM
Subject: Old SGI penguin logo


> 
> In 2.4.6, the penguin logos were updated in Linus' tree for all architectures
> (cfr.  http://home.tvd.be/cr26864/Linux/fbdev/logo.html).
> 
> However, the MIPS merge in 2.4.10 reverted that change in include/asm-mips/,
> and introduced a new logo for DECstations. The logo in include/asm-mips64/ was
> not affected by this merge.
> 
> This patch updates the logo for non-DEC machines, and brings the other parts of
> the MIPS-specific logo code in sync with the other architectures. It applies to
> both 2.4.x and 2.5.x.
> 
> --- linux-mips-2.4.x/include/asm-mips/linux_logo.h Mon Aug 26 11:33:33 2002
> +++ geert-mips-2.4.x/include/asm-mips/linux_logo.h Thu Dec  5 11:33:51 2002
> @@ -28,16 +28,5 @@
>  # include <asm/linux_logo_dec.h>
>  #endif
>  
> -#ifndef INCLUDE_LINUX_LOGO_DATA
> -/* prototypes only */
> -extern unsigned char linux_logo_red[];
> -extern unsigned char linux_logo_green[];
> -extern unsigned char linux_logo_blue[];
> -extern unsigned char linux_logo[];
> -extern unsigned char linux_logo_bw[];
> -extern unsigned char linux_logo16_red[];
> -extern unsigned char linux_logo16_green[];
> -extern unsigned char linux_logo16_blue[];
> -extern unsigned char linux_logo16[];
> +#include <linux/linux_logo.h>
>  
> -#endif
> --- linux-mips-2.4.x/include/asm-mips/linux_logo_dec.h Mon Aug 26 11:33:33 2002
> +++ geert-mips-2.4.x/include/asm-mips/linux_logo_dec.h Thu Dec  5 11:33:51 2002
> @@ -13,11 +13,13 @@
>  #include <linux/version.h>
>  
>  #define linux_logo_banner "Linux/MIPSel version " UTS_RELEASE
> -#define LINUX_LOGO_COLORS 183
>  
>  #define __HAVE_ARCH_LINUX_LOGO
>  
> +#define LINUX_LOGO_COLORS 183
> +
>  #ifdef INCLUDE_LINUX_LOGO_DATA
> +
>  unsigned char linux_logo_red[] __initdata = {
>      0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
>      0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
> @@ -899,8 +901,5 @@
>      0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
>  };
>  
> -#define INCLUDE_LINUX_LOGOBW
> -#define INCLUDE_LINUX_LOGO16
> -#include <linux/linux_logo.h>
> +#endif /* INCLUDE_LINUX_LOGO_DATA */
>  
> -#endif
> --- linux-mips-2.4.x/include/asm-mips/linux_logo_sgi.h Tue Jul  2 14:19:16 2002
> +++ geert-mips-2.4.x/include/asm-mips/linux_logo_sgi.h Thu Dec  5 11:33:51 2002
> @@ -12,906 +12,895 @@
>  #include <linux/version.h>
>  
>  #define linux_logo_banner "Linux/MIPS version " UTS_RELEASE
> -#define LINUX_LOGO_COLORS 212
>  
>  #define __HAVE_ARCH_LINUX_LOGO
>  
> +#define LINUX_LOGO_COLORS 212
> +
>  #ifdef INCLUDE_LINUX_LOGO_DATA
> +
>  unsigned char linux_logo_red[] __initdata = {
> -  0x03, 0x82, 0xE9, 0xBF, 0x42, 0xC9, 0x7E, 0xC0,
> -  0xE9, 0xE3, 0xC2, 0x24, 0xA4, 0x65, 0xEC, 0xC4,
> -  0x82, 0x9F, 0xF3, 0x12, 0x5F, 0xA0, 0xC2, 0xED,
> -  0x3E, 0xD5, 0xDB, 0xA0, 0x1C, 0xF4, 0xEB, 0xA4,
> -  0xCD, 0x0A, 0x9A, 0x51, 0xCC, 0xBE, 0xC0, 0xBA,
> -  0x74, 0xDC, 0xAA, 0xF6, 0xD3, 0xC5, 0xE6, 0x26,
> -  0xC2, 0x83, 0x38, 0xEA, 0x49, 0xB0, 0xED, 0xE5,
> -  0xF4, 0x96, 0x96, 0x1B, 0xFA, 0xCC, 0xF2, 0x0F,
> -  0xCD, 0xE5, 0xF4, 0xD3, 0x50, 0x7A, 0xB5, 0xDE,
> -  0xD5, 0xB6, 0x60, 0x0A, 0x6A, 0xEA, 0xD4, 0xEB,
> -  0xC1, 0xCA, 0xEA, 0xEC, 0x2A, 0x96, 0x95, 0xDC,
> -  0xE4, 0xCE, 0xEC, 0x1E, 0xDC, 0x8A, 0xD1, 0xF6,
> -  0x3C, 0x5E, 0xC6, 0xB4, 0xB2, 0xAC, 0xBA, 0x9E,
> -  0x0F, 0x59, 0xBA, 0xFA, 0xCC, 0xBF, 0x82, 0xCE,
> -  0xE6, 0x4F, 0xAA, 0x4C, 0xCA, 0x8E, 0x8E, 0xDF,
> -  0x2C, 0xB6, 0x3B, 0xDE, 0xCE, 0xEE, 0x46, 0x4A,
> -  0x6F, 0x7A, 0x82, 0xE4, 0xAA, 0x88, 0xE2, 0xCE,
> -  0xAE, 0xB6, 0x70, 0xC2, 0x9A, 0xDA, 0x35, 0x9E,
> -  0x95, 0xC0, 0x7E, 0x8C, 0xC2, 0xB6, 0xCE, 0xB9,
> -  0xD5, 0xAA, 0xC1, 0xF4, 0xC7, 0xB6, 0xB6, 0xA3,
> -  0xF2, 0x68, 0xDB, 0x76, 0xDC, 0x57, 0xD3, 0xA8,
> -  0xC0, 0xEF, 0x46, 0xF4, 0x2F, 0xD7, 0x53, 0x36,
> -  0xE6, 0xA7, 0xCA, 0xCB, 0x7E, 0xE4, 0x86, 0x9A,
> -  0xCE, 0x94, 0xB4, 0x1D, 0xDA, 0xCE, 0x6C, 0xE6,
> -  0x9E, 0xC6, 0xDA, 0x16, 0xFA, 0xAA, 0x56, 0xB6,
> -  0xFE, 0x6E, 0xEA, 0xCE, 0xE5, 0xCC, 0xDB, 0xD3,
> -  0xED, 0xDC, 0xF4, 0x72
> +    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
> +    0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
> +    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x02, 0x65,
> +    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
> +    0xc3, 0x65, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
> +    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
> +    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x76, 0x79,
> +    0x62, 0x36, 0x9a, 0xe2, 0xec, 0xe1, 0xb8, 0xd7,
> +    0xaf, 0x25, 0xbc, 0xc0, 0xef, 0xea, 0xe8, 0xe8,
> +    0xf5, 0xf1, 0xda, 0xd3, 0x79, 0xdb, 0xf4, 0xf6,
> +    0xf6, 0xf6, 0xe2, 0x3d, 0xb4, 0xce, 0xe6, 0xee,
> +    0xf6, 0x68, 0xd8, 0xec, 0xf5, 0xc6, 0xc8, 0x9c,
> +    0x89, 0xd2, 0xee, 0xcb, 0xb9, 0xd2, 0x66, 0x5e,
> +    0x8b, 0xbe, 0xa8, 0xd5, 0xca, 0xb6, 0xae, 0x9c,
> +    0xc5, 0xbe, 0xbe, 0xca, 0x90, 0xb2, 0x9a, 0xa8,
> +    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
> +    0x12, 0x4a, 0x8e, 0xf2, 0xf6, 0xee, 0xb5, 0xe4,
> +    0xf1, 0x26, 0x9a, 0xea, 0xf6, 0xe0, 0xd2, 0x16,
> +    0x9a, 0x2e, 0x70, 0xd6, 0x46, 0x7c, 0xb4, 0x62,
> +    0xd6, 0xa3, 0x74, 0xa7, 0xa2, 0xca, 0xe0, 0xae,
> +    0xbe, 0xce, 0xa3, 0x8e, 0x6d, 0x8e, 0x32, 0xaf,
> +    0x50, 0x9e, 0x5b, 0x8a, 0x98, 0x82, 0x7a, 0x82,
> +    0x56, 0x7c, 0x8a, 0x56, 0x5e, 0x86, 0x6a, 0x52,
> +    0x59, 0x64, 0x5e,
>  };
>  
>  unsigned char linux_logo_green[] __initdata = {
> -  0x03, 0x82, 0xC4, 0x83, 0x42, 0xA2, 0x4A, 0xA4,
> -  0xE5, 0xA6, 0xC2, 0x24, 0xA4, 0x65, 0xB4, 0x94,
> -  0x66, 0x87, 0xB6, 0x12, 0x44, 0x6C, 0x96, 0xD4,
> -  0x36, 0x95, 0xB2, 0x92, 0x0E, 0xF4, 0xBC, 0x77,
> -  0xA5, 0x0A, 0x92, 0x52, 0xB4, 0x9A, 0x8C, 0xB2,
> -  0x74, 0xC2, 0x8E, 0xBD, 0xA2, 0xCA, 0xD2, 0x12,
> -  0xB6, 0x61, 0x24, 0xDA, 0x33, 0x79, 0xCB, 0xAC,
> -  0xDA, 0x84, 0x7A, 0x1B, 0xFA, 0x8D, 0xBE, 0x06,
> -  0x93, 0xBB, 0xBC, 0xAB, 0x44, 0x62, 0x83, 0xDA,
> -  0x9B, 0xA2, 0x4C, 0x04, 0x6A, 0xB6, 0xC8, 0xBD,
> -  0x8D, 0xB6, 0xAD, 0xEC, 0x2A, 0x68, 0x62, 0x9D,
> -  0xC4, 0xC4, 0xB4, 0x13, 0xA3, 0x8A, 0xD2, 0xD6,
> -  0x3C, 0x5D, 0x8C, 0x7E, 0x82, 0xAC, 0x96, 0x7E,
> -  0x0D, 0x5A, 0xBA, 0xBB, 0xCC, 0xBE, 0x76, 0xB6,
> -  0xDE, 0x4E, 0x9A, 0x3C, 0xBE, 0x8E, 0x6E, 0xCB,
> -  0x1C, 0xAA, 0x2E, 0xBE, 0xAA, 0xDE, 0x3E, 0x4B,
> -  0x4D, 0x7A, 0x54, 0xE4, 0x8E, 0x6E, 0xCA, 0x9B,
> -  0x70, 0x9E, 0x5A, 0xAA, 0x9A, 0xBE, 0x34, 0x9E,
> -  0x71, 0x9E, 0x7E, 0x5F, 0xAA, 0x8A, 0xBE, 0x91,
> -  0xCE, 0x88, 0x92, 0xDB, 0xC6, 0xAB, 0x8A, 0x72,
> -  0xE2, 0x44, 0xC3, 0x54, 0xAA, 0x45, 0xBB, 0x92,
> -  0xBA, 0xC4, 0x46, 0xCA, 0x2D, 0xD6, 0x3B, 0x1A,
> -  0xC2, 0x7E, 0xA6, 0xCB, 0x7A, 0xDC, 0x86, 0x72,
> -  0xB6, 0x94, 0xB4, 0x1C, 0xBC, 0xAE, 0x4C, 0xD6,
> -  0x62, 0x86, 0xD3, 0x16, 0xF6, 0x7A, 0x55, 0x79,
> -  0xFE, 0x6E, 0xC6, 0xC6, 0xAA, 0x93, 0xDC, 0x9D,
> -  0xAE, 0xA4, 0xD4, 0x56
> +    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
> +    0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
> +    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x02, 0x65,
> +    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
> +    0xc3, 0x62, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
> +    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
> +    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x62, 0x5c,
> +    0x4e, 0x26, 0x72, 0xaa, 0xba, 0xaf, 0x90, 0xae,
> +    0x92, 0x1a, 0xa4, 0x85, 0xb6, 0xbe, 0xc3, 0xc8,
> +    0xcf, 0xd0, 0xc2, 0xce, 0x57, 0xa2, 0xd6, 0xda,
> +    0xda, 0xd7, 0xb8, 0x2a, 0x7b, 0x91, 0xae, 0xca,
> +    0xda, 0x45, 0x9e, 0xb2, 0xd7, 0x9b, 0x90, 0x76,
> +    0x5c, 0xa2, 0xbe, 0xa6, 0x85, 0x96, 0x4e, 0x46,
> +    0x66, 0x92, 0x7a, 0x9a, 0x96, 0x9d, 0x9a, 0x6b,
> +    0x8a, 0x8e, 0xb2, 0xca, 0x90, 0xa6, 0x79, 0x7c,
> +    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
> +    0x0e, 0x36, 0x86, 0xba, 0xbe, 0xcc, 0x8e, 0xb8,
> +    0xc4, 0x1e, 0x8e, 0xae, 0xba, 0xb2, 0xa6, 0x12,
> +    0x7a, 0x20, 0x64, 0xaa, 0x2f, 0x70, 0x85, 0x46,
> +    0xa6, 0x6e, 0x51, 0x72, 0x92, 0xa2, 0xa6, 0x87,
> +    0x96, 0xa2, 0x85, 0x7a, 0x6a, 0x6e, 0x22, 0x76,
> +    0x36, 0x76, 0x3c, 0x6e, 0x63, 0x53, 0x66, 0x62,
> +    0x42, 0x50, 0x56, 0x42, 0x56, 0x56, 0x56, 0x3e,
> +    0x51, 0x52, 0x56,
>  };
>  
>  unsigned char linux_logo_blue[] __initdata = {
> -  0x04, 0x84, 0x10, 0x0C, 0x41, 0x14, 0x04, 0x78,
> -  0xC7, 0x0E, 0xC4, 0x24, 0xA4, 0x64, 0x0C, 0x0D,
> -  0x17, 0x24, 0x0D, 0x13, 0x11, 0x07, 0x40, 0x22,
> -  0x0C, 0x0C, 0x11, 0x78, 0x06, 0xF4, 0x0B, 0x0A,
> -  0x47, 0x0B, 0x7C, 0x54, 0x6C, 0x0C, 0x0D, 0x9C,
> -  0x73, 0x54, 0x14, 0x0C, 0x0F, 0xC7, 0x94, 0x04,
> -  0x94, 0x17, 0x0A, 0x6C, 0x08, 0x0F, 0x14, 0x0B,
> -  0x12, 0x68, 0x28, 0x11, 0xFA, 0x0A, 0x34, 0x09,
> -  0x0A, 0x2F, 0x15, 0x19, 0x14, 0x3C, 0x06, 0xC4,
> -  0x0B, 0x84, 0x24, 0x08, 0x69, 0x38, 0xBC, 0x15,
> -  0x1F, 0xA0, 0x0A, 0xEC, 0x2A, 0x0C, 0x0C, 0x0C,
> -  0x2C, 0xA0, 0x15, 0x07, 0x0B, 0x8C, 0xD3, 0x10,
> -  0x3B, 0x5C, 0x0C, 0x04, 0x3C, 0xAC, 0x54, 0x1C,
> -  0x0B, 0x5B, 0xBB, 0x0A, 0xC1, 0xBB, 0x5C, 0x3C,
> -  0xBC, 0x4D, 0x74, 0x10, 0x8C, 0x8C, 0x14, 0x91,
> -  0x0C, 0x74, 0x17, 0x0C, 0x48, 0x9C, 0x3C, 0x4C,
> -  0x09, 0x7C, 0x05, 0xE4, 0x34, 0x38, 0x6C, 0x11,
> -  0x08, 0x7C, 0x18, 0x2C, 0x9C, 0x4C, 0x34, 0x9C,
> -  0x29, 0x54, 0x7C, 0x0C, 0x78, 0x18, 0x9C, 0x14,
> -  0xBA, 0x30, 0x27, 0x31, 0xC2, 0x97, 0x24, 0x09,
> -  0xB4, 0x04, 0x87, 0x0C, 0x14, 0x1F, 0x7C, 0x64,
> -  0xB0, 0x0F, 0x45, 0x10, 0x2C, 0xD4, 0x0A, 0x04,
> -  0x44, 0x1F, 0x2C, 0xCC, 0x7C, 0xD8, 0x84, 0x0C,
> -  0x8C, 0x94, 0xB4, 0x1D, 0x20, 0x5C, 0x18, 0xB4,
> -  0x04, 0x09, 0xBC, 0x14, 0xF4, 0x08, 0x54, 0x07,
> -  0xFC, 0x6C, 0x24, 0xB4, 0x15, 0x18, 0xDB, 0x17,
> -  0x17, 0x18, 0x21, 0x24
> +    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
> +    0x12, 0x01, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
> +    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x06, 0x65,
> +    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
> +    0xc3, 0x59, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
> +    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
> +    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x2e, 0x08,
> +    0x0a, 0x06, 0x0a, 0x0b, 0x0b, 0x0f, 0x0c, 0x0f,
> +    0x3d, 0x09, 0x73, 0x09, 0x0d, 0x0a, 0x10, 0x1e,
> +    0x2d, 0x13, 0x86, 0xba, 0x19, 0x0a, 0x36, 0x3c,
> +    0x26, 0x14, 0x0d, 0x06, 0x07, 0x0a, 0x0b, 0x0f,
> +    0x4a, 0x06, 0x0a, 0x0c, 0x2b, 0x0a, 0x0b, 0x0a,
> +    0x06, 0x0a, 0x0a, 0x11, 0x0b, 0x0a, 0x0a, 0x1e,
> +    0x0f, 0x0d, 0x0a, 0x0b, 0x22, 0x6a, 0x72, 0x0b,
> +    0x0b, 0x22, 0x90, 0xca, 0x90, 0x92, 0x3c, 0x2c,
> +    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
> +    0x06, 0x0e, 0x6a, 0x0e, 0x0e, 0x5b, 0x2c, 0x3e,
> +    0x0e, 0x0a, 0x5a, 0x0d, 0x0e, 0x3e, 0x0a, 0x06,
> +    0x2e, 0x06, 0x4e, 0x36, 0x06, 0x58, 0x24, 0x06,
> +    0x3a, 0x08, 0x08, 0x07, 0x5e, 0x45, 0x0a, 0x32,
> +    0x2e, 0x2a, 0x43, 0x48, 0x5f, 0x2e, 0x06, 0x06,
> +    0x07, 0x24, 0x06, 0x32, 0x06, 0x06, 0x46, 0x2e,
> +    0x22, 0x06, 0x06, 0x1e, 0x4c, 0x06, 0x3a, 0x22,
> +    0x42, 0x34, 0x42,
>  };
>  
>  unsigned char linux_logo[] __initdata = {
> -  0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C,
> -  0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF,
> -  0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA, 0xDA, 0x2C,
> -  0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A, 0x8A, 0xDA,
> -  0x85, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0xD9, 0xD9,
> -  0xAF, 0x85, 0x85, 0x85, 0x8D, 0xBC, 0x2A, 0x2A,
> -  0xBC, 0x8C, 0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85,
> -  0x2C, 0x2C, 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
> -  0x2C, 0xAF, 0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA,
> -  0xDA, 0x2C, 0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A,
> -  0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C, 0x2C, 0xAC,
> -  0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D,
> -  0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
> -  0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA, 0x85, 0x2C,
> -  0x2C, 0xAC, 0xD9, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C,
> -  0x2C, 0x85, 0x2C, 0x2C, 0x85, 0xDA, 0xDA, 0xDA,
> -  0xDA, 0xDA, 0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C,
> -  0x2C, 0xAC, 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
> -  0xD9, 0x7D, 0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA,
> -  0x85, 0x2C, 0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA,
> -  0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF,
> -  0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0x7D,
> -  0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
> -  0xAF, 0x2C, 0x2C, 0xDA, 0x85, 0x85, 0x2C, 0x2C,
> -  0xAC, 0xD9, 0xD9, 0xAF, 0xDA, 0x85, 0x2C, 0x2C,
> -  0x85, 0xDA, 0xDA, 0x85, 0x85, 0xDA, 0x85, 0x85,
> -  0x85, 0xAF, 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85,
> -  0x2C, 0xAF, 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9,
> -  0xD9, 0x7D, 0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA,
> -  0x85, 0x2C, 0xAF, 0x2C, 0x2C, 0xDA, 0xDA, 0x85,
> -  0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAF,
> -  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0x95,
> -  0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
> -  0xAC, 0xAC, 0x2C, 0x2C, 0x85, 0x2C, 0x2C, 0xAC,
> -  0xD9, 0xD9, 0x2C, 0x91, 0x41, 0x20, 0x6B, 0x20,
> -  0x6B, 0x20, 0x6B, 0xAE, 0x2C, 0x85, 0x2C, 0x2C,
> -  0xAC, 0xD9, 0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA,
> -  0x85, 0xAF, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
> -  0x95, 0x95, 0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA,
> -  0x85, 0x2C, 0xAC, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C,
> -  0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
> -  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0xD9,
> -  0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xAF, 0xAC,
> -  0x2C, 0xB2, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x6B, 0x80, 0x85, 0x2C,
> -  0xD9, 0xD6, 0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA,
> -  0x85, 0x2C, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
> -  0xD9, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85,
> -  0x2C, 0xD9, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF,
> -  0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA, 0x2C, 0xAC,
> -  0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0xAF, 0x2C,
> -  0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xAC, 0xD9,
> -  0xD9, 0xD9, 0xAF, 0xAF, 0x2C, 0x2C, 0xAF, 0xDA,
> -  0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x41, 0xE3, 0x20, 0x6B, 0x48,
> -  0xAC, 0x95, 0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA,
> -  0x2C, 0xAC, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
> -  0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C,
> -  0xAC, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0xAF,
> -  0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
> -  0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
> -  0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0xAF, 0xAC,
> -  0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x89,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x74, 0x43, 0x80, 0x41, 0x20,
> -  0x9F, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85,
> -  0x2C, 0xD9, 0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C,
> -  0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF,
> -  0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
> -  0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xD9,
> -  0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
> -  0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC,
> -  0xAF, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x41,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0xAE, 0x48, 0x89, 0x74, 0x41,
> -  0x6B, 0xD6, 0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85,
> -  0x2C, 0xD9, 0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C,
> -  0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF,
> -  0xAF, 0xAC, 0xAF, 0xAC, 0xAC, 0x2C, 0xAF, 0xAC,
> -  0x2C, 0x7D, 0xD9, 0x2C, 0xDA, 0x85, 0x2C, 0x7D,
> -  0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0x85,
> -  0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0xD9,
> -  0x95, 0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x48, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x6B, 0xAE, 0xE6, 0x80, 0x2B, 0x88,
> -  0x20, 0x33, 0xDA, 0x95, 0xD9, 0x2C, 0xDA, 0x85,
> -  0x2C, 0x7D, 0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85,
> -  0x85, 0x85, 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC,
> -  0xAC, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9,
> -  0x85, 0xD9, 0x2C, 0x85, 0xDA, 0xDA, 0xD9, 0x21,
> -  0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, 0x85, 0xAF,
> -  0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, 0x7D, 0xD6,
> -  0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0x85, 0xDB, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0xDB, 0xE3, 0x6B, 0x20, 0x20,
> -  0x20, 0x20, 0xE9, 0xD9, 0x2C, 0x85, 0xDA, 0xDA,
> -  0xD9, 0x21, 0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA,
> -  0x85, 0xAF, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9,
> -  0x7D, 0xD6, 0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
> -  0xDA, 0x2C, 0x85, 0xDA, 0xDA, 0x85, 0x95, 0x21,
> -  0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xD9,
> -  0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0xAC, 0xAC, 0x2C, 0xAF, 0x2C, 0x85, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x88, 0xDA, 0x85, 0xDA, 0xDA, 0x85,
> -  0x95, 0x21, 0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C,
> -  0x2C, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0xD9, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
> -  0xDA, 0x2C, 0x85, 0x85, 0x2C, 0xD9, 0xD6, 0xB2,
> -  0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC, 0x95, 0x95,
> -  0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0x2C, 0x85,
> -  0x85, 0x85, 0x85, 0x85, 0x85, 0xAC, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0xAC, 0x85, 0x85, 0x2C, 0xD9,
> -  0xD6, 0xB2, 0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC,
> -  0x95, 0x95, 0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
> -  0x85, 0x2C, 0x2C, 0x2C, 0xAC, 0x95, 0xD6, 0x7D,
> -  0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D, 0x7D, 0x95,
> -  0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9, 0x2C, 0x85,
> -  0xDA, 0xDA, 0xDA, 0x85, 0x85, 0x21, 0x20, 0x20,
> -  0x6B, 0x41, 0xDB, 0x6B, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x41, 0xDB, 0xDB, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0xE6, 0x2C, 0x2C, 0xAC, 0x95,
> -  0xD6, 0x7D, 0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D,
> -  0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9,
> -  0x2C, 0x85, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
> -  0x2C, 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD9,
> -  0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6, 0xD9, 0xAF,
> -  0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9, 0x2C, 0x85,
> -  0xDA, 0xDA, 0x2C, 0xAF, 0xAF, 0x21, 0x20, 0x20,
> -  0x88, 0x2B, 0x88, 0x74, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0xAE, 0x2D, 0x2D, 0x74, 0x74, 0x88, 0x20,
> -  0x20, 0x20, 0x20, 0x80, 0xAC, 0xD9, 0x95, 0xD6,
> -  0xD6, 0xD9, 0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6,
> -  0xD9, 0xAF, 0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9,
> -  0x2C, 0xDA, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
> -  0x2C, 0xAF, 0xD9, 0x95, 0xD6, 0xD6, 0x95, 0xAF,
> -  0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95, 0xAF, 0x2C,
> -  0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C, 0x85, 0x85,
> -  0x85, 0xAF, 0xD9, 0x95, 0xD9, 0x7D, 0x20, 0x33,
> -  0x7D, 0x8A, 0x7D, 0x5B, 0x6B, 0x20, 0x20, 0x6B,
> -  0xE6, 0xD9, 0x85, 0x2A, 0xDA, 0x2B, 0x41, 0x20,
> -  0x20, 0x20, 0x6B, 0x74, 0xD9, 0x95, 0xD6, 0xD6,
> -  0x95, 0xAF, 0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95,
> -  0xAF, 0x2C, 0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C,
> -  0x85, 0x85, 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0x85, 0xD9, 0x7D, 0x21, 0x21, 0x7D, 0xAC, 0x2C,
> -  0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF, 0x2C, 0x85,
> -  0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA, 0x8A, 0xDA,
> -  0x85, 0xAF, 0xD9, 0x7D, 0xD9, 0x95, 0x20, 0x91,
> -  0xBC, 0x73, 0xEE, 0x7D, 0x20, 0x20, 0x20, 0x80,
> -  0x4D, 0x3D, 0x73, 0x73, 0xA3, 0xD6, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x2B, 0x7D, 0x21, 0x21, 0x7D,
> -  0xAC, 0x2C, 0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF,
> -  0x2C, 0x85, 0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA,
> -  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0x7D, 0xD9, 0xAC,
> -  0x2C, 0xD9, 0xD6, 0xB2, 0xB2, 0x7D, 0xAF, 0x85,
> -  0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C, 0x2C, 0x2C,
> -  0xD9, 0xD9, 0xAC, 0x85, 0x8D, 0x2A, 0x2A, 0xDA,
> -  0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAC, 0x20, 0xAF,
> -  0x2C, 0xE6, 0x8D, 0x73, 0xE3, 0x20, 0x20, 0x48,
> -  0x5C, 0xDA, 0x5B, 0x43, 0xBC, 0x73, 0x2B, 0x20,
> -  0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0xB2, 0x7D,
> -  0xAF, 0x85, 0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C,
> -  0x2C, 0x2C, 0xD9, 0xD9, 0xAC, 0x85, 0x8A, 0x2A,
> -  0x8D, 0xDA, 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
> -  0xAC, 0xD9, 0xD6, 0xB2, 0x21, 0xD9, 0x2C, 0x85,
> -  0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C, 0x2C, 0xAC,
> -  0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0xBC, 0xDA, 0xD9,
> -  0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xAC, 0x20, 0x2A,
> -  0xCC, 0xAE, 0x9F, 0xE4, 0xAE, 0x5B, 0x74, 0xA1,
> -  0xE4, 0xAE, 0x20, 0x9F, 0x89, 0xE8, 0xE6, 0x20,
> -  0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0x21, 0xD9,
> -  0x2C, 0x85, 0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C,
> -  0x2C, 0xAC, 0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0x2A,
> -  0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9,
> -  0xD9, 0x95, 0x21, 0xA1, 0x21, 0xAC, 0x85, 0x85,
> -  0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0xAF, 0xAC,
> -  0xAF, 0x85, 0x8A, 0x2A, 0x2A, 0xDA, 0xD9, 0xA1,
> -  0x48, 0xE9, 0x48, 0x21, 0x95, 0xAC, 0x20, 0x2A,
> -  0xDB, 0x41, 0x74, 0xBC, 0x2B, 0x7B, 0x7B, 0x80,
> -  0x73, 0x41, 0x20, 0x6B, 0x2B, 0xE8, 0x2D, 0x20,
> -  0x20, 0x20, 0x20, 0x33, 0x21, 0xA1, 0x21, 0xAC,
> -  0x85, 0x85, 0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C,
> -  0xAF, 0xAC, 0xAF, 0x85, 0x8A, 0xBC, 0x2A, 0xDA,
> -  0xD9, 0xA1, 0x48, 0xE9, 0x48, 0x21, 0xD9, 0xD9,
> -  0xA1, 0xB2, 0xB2, 0x48, 0xD6, 0xAC, 0x2C, 0x2C,
> -  0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
> -  0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95, 0xA1, 0x6C,
> -  0x6C, 0x48, 0xD6, 0xD9, 0x2C, 0x85, 0x20, 0x2C,
> -  0x89, 0x20, 0x3C, 0xB9, 0xA7, 0x63, 0xD2, 0xB9,
> -  0xC6, 0x9A, 0x20, 0x20, 0x43, 0x5C, 0xE6, 0x20,
> -  0x20, 0x20, 0x20, 0x33, 0xB2, 0x48, 0xD6, 0xAC,
> -  0x2C, 0x2C, 0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C,
> -  0x2C, 0x2C, 0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95,
> -  0xA1, 0x6C, 0x6C, 0x48, 0xD6, 0xD9, 0xAF, 0xAC,
> -  0xA1, 0xD6, 0x7D, 0xB2, 0xD6, 0xAF, 0x85, 0x85,
> -  0xD9, 0x95, 0x2C, 0x85, 0xDA, 0x85, 0x85, 0x2C,
> -  0x85, 0x8A, 0x8D, 0xDA, 0xD9, 0x48, 0x81, 0x2D,
> -  0x48, 0xD6, 0xD9, 0xAC, 0x2C, 0x85, 0x20, 0x2D,
> -  0xEE, 0x93, 0xD1, 0xA7, 0x3E, 0x3E, 0x3A, 0x25,
> -  0x56, 0xAB, 0xAA, 0xC5, 0xEE, 0xEE, 0x33, 0x20,
> -  0x20, 0x20, 0x20, 0x41, 0xD9, 0xB2, 0xD6, 0xAF,
> -  0x85, 0x85, 0xD9, 0x95, 0x2C, 0x85, 0xDA, 0x85,
> -  0x85, 0x2C, 0x85, 0x8A, 0x8D, 0xDA, 0xD9, 0x48,
> -  0x81, 0x2D, 0x48, 0xD6, 0xD9, 0xAF, 0x2C, 0x2C,
> -  0xAC, 0xAF, 0xD9, 0x7D, 0xD6, 0x2C, 0x85, 0x2C,
> -  0xD9, 0xD9, 0x2C, 0xDA, 0xDA, 0xDA, 0x2C, 0x2C,
> -  0x85, 0x8D, 0x8D, 0x2C, 0x21, 0x2D, 0x2D, 0xE9,
> -  0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, 0x20, 0xE3,
> -  0xB4, 0xBE, 0xF1, 0x3E, 0x9B, 0x22, 0x56, 0xF2,
> -  0xBB, 0x7F, 0x56, 0xDC, 0x8F, 0x5A, 0x5F, 0x20,
> -  0x20, 0x20, 0x20, 0x6B, 0x2C, 0x7D, 0xD6, 0x2C,
> -  0x85, 0x2C, 0xD9, 0xD9, 0x2C, 0xDA, 0xDA, 0xDA,
> -  0x2C, 0x2C, 0x85, 0x8D, 0x8A, 0x85, 0x21, 0x2D,
> -  0x2D, 0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
> -  0x2A, 0x85, 0xAC, 0x95, 0x95, 0x2C, 0x85, 0x85,
> -  0xAC, 0xAF, 0x85, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
> -  0xDA, 0x8A, 0x8A, 0xAF, 0xA1, 0x2D, 0xE9, 0xD6,
> -  0xD9, 0xAC, 0x85, 0x85, 0x85, 0xDA, 0x20, 0x52,
> -  0x55, 0xED, 0x57, 0x3E, 0x22, 0x56, 0x37, 0xBB,
> -  0xBB, 0x58, 0x7F, 0x7F, 0x56, 0x5E, 0xC5, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x2C, 0x95, 0x95, 0x2C,
> -  0x85, 0x85, 0xAC, 0xAF, 0x85, 0xDA, 0xDA, 0x85,
> -  0x2C, 0x2C, 0xDA, 0x8D, 0xDA, 0xAF, 0xA1, 0x2D,
> -  0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, 0x85,
> -  0xCD, 0xAF, 0xD9, 0x95, 0xD9, 0x2C, 0xDA, 0x85,
> -  0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x2C, 0xAC, 0xAF,
> -  0x85, 0x8A, 0x85, 0xD9, 0x48, 0x48, 0xB2, 0x95,
> -  0x95, 0xAC, 0x2C, 0x85, 0xDA, 0xDA, 0x6B, 0xB3,
> -  0x46, 0x7C, 0x2E, 0x9B, 0x22, 0x56, 0xBB, 0x37,
> -  0x58, 0x58, 0xF2, 0x3A, 0x46, 0x63, 0x64, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x2D, 0x95, 0xD9, 0x2C,
> -  0xDA, 0x85, 0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x2C,
> -  0xAC, 0xAF, 0x85, 0xDA, 0x85, 0xD9, 0x48, 0x48,
> -  0xB2, 0x95, 0x95, 0xD9, 0x85, 0xDA, 0x85, 0x85,
> -  0xBC, 0xB2, 0xB2, 0x7D, 0xD9, 0x2C, 0xDA, 0x85,
> -  0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x85, 0xAF, 0x2C,
> -  0x85, 0xDA, 0x2C, 0x7D, 0xA1, 0x48, 0xB2, 0x21,
> -  0xD6, 0xD9, 0x85, 0xDA, 0x85, 0xDA, 0x41, 0x51,
> -  0xB7, 0xEC, 0x2E, 0x22, 0x56, 0x37, 0xBB, 0xF2,
> -  0x37, 0xEA, 0x2F, 0x2F, 0x77, 0xA7, 0x38, 0x20,
> -  0x20, 0x6B, 0x20, 0x20, 0x5B, 0x2C, 0xD9, 0x2C,
> -  0xDA, 0x85, 0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x85,
> -  0xAF, 0x2C, 0xDA, 0xDA, 0x2C, 0x7D, 0xA1, 0x48,
> -  0xB2, 0x21, 0xD6, 0xD9, 0x2C, 0xDA, 0x85, 0xAF,
> -  0x2C, 0x2D, 0x48, 0x7D, 0xAF, 0x2C, 0x85, 0x2C,
> -  0xD9, 0xAC, 0xAF, 0x85, 0x85, 0x2C, 0x2C, 0x2C,
> -  0x85, 0x2C, 0xD9, 0xD6, 0xA1, 0xA1, 0x48, 0xA1,
> -  0x21, 0x2C, 0xDA, 0xDA, 0x2C, 0x85, 0x41, 0x98,
> -  0xA2, 0xA7, 0x6F, 0xC9, 0x37, 0xF2, 0xF2, 0x9B,
> -  0xB7, 0x66, 0x60, 0x4C, 0xED, 0x84, 0x3C, 0x20,
> -  0x5B, 0x2D, 0x2B, 0x6B, 0x20, 0xAF, 0xAF, 0x2C,
> -  0x85, 0x2C, 0xD9, 0xAC, 0xAF, 0x85, 0x85, 0x2C,
> -  0x2C, 0x2C, 0x2C, 0x85, 0xD9, 0xD6, 0xA1, 0xA1,
> -  0x48, 0xA1, 0xD6, 0xAF, 0xDA, 0x8A, 0x2C, 0xD9,
> -  0xB2, 0x2D, 0x48, 0x95, 0x2C, 0x2C, 0x2C, 0x85,
> -  0xAC, 0xAC, 0xAF, 0x85, 0xDA, 0x85, 0xAF, 0xAC,
> -  0xAF, 0x2C, 0xD9, 0xD6, 0xD6, 0xD6, 0x21, 0xD6,
> -  0xD9, 0xDA, 0x8D, 0xDA, 0xAF, 0x2C, 0x20, 0x88,
> -  0x42, 0x51, 0x3F, 0x2F, 0x45, 0xB7, 0x66, 0x55,
> -  0x46, 0x60, 0x5D, 0x36, 0xD8, 0x71, 0x43, 0x20,
> -  0x20, 0x2D, 0xB2, 0x80, 0x20, 0x2D, 0x2C, 0x2C,
> -  0x2C, 0x85, 0xAC, 0xAC, 0xAF, 0x85, 0xDA, 0x85,
> -  0xAF, 0xAC, 0xAC, 0xAF, 0xD9, 0xD6, 0xD6, 0xD6,
> -  0x21, 0xD6, 0xD9, 0xDA, 0x8D, 0x8A, 0x2C, 0xD9,
> -  0xB2, 0x48, 0xD6, 0xAC, 0xAF, 0x2C, 0x2C, 0x85,
> -  0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85, 0xAF, 0xD9,
> -  0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC,
> -  0x85, 0x8D, 0xBC, 0xDA, 0xD9, 0xDA, 0x20, 0xE3,
> -  0xDA, 0x69, 0x96, 0xB5, 0xF1, 0x68, 0x5D, 0x82,
> -  0xE1, 0xBE, 0x27, 0x8D, 0x4D, 0xD3, 0x7D, 0x20,
> -  0x20, 0xDB, 0xA1, 0xCA, 0x20, 0x88, 0x85, 0x2C,
> -  0x2C, 0x85, 0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85,
> -  0xAF, 0xD9, 0xAC, 0xAF, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0xD9, 0xAC, 0xDA, 0x8D, 0xBC, 0xDA, 0xD9, 0x95,
> -  0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C, 0x85,
> -  0x85, 0xAF, 0xAF, 0x85, 0x85, 0x2C, 0x2C, 0xAC,
> -  0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x85,
> -  0x8D, 0x2A, 0x2A, 0x85, 0xD9, 0x95, 0x20, 0xDB,
> -  0x8D, 0x8D, 0x99, 0xB0, 0x35, 0xE5, 0x3F, 0x35,
> -  0xB9, 0x50, 0x8A, 0x4D, 0x73, 0xE8, 0xA3, 0xCC,
> -  0x20, 0x20, 0x33, 0x6B, 0x20, 0x20, 0xCC, 0x85,
> -  0x2C, 0x85, 0x85, 0xAF, 0xAF, 0x85, 0x85, 0x85,
> -  0x2C, 0xD9, 0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C,
> -  0x2C, 0x85, 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0xD9,
> -  0xAF, 0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x85,
> -  0x2C, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C, 0xAC,
> -  0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x85, 0xDA, 0xDA,
> -  0x8A, 0x8A, 0x85, 0xD9, 0x2C, 0x2B, 0x20, 0xAE,
> -  0xA3, 0xBC, 0x8D, 0xC8, 0xA9, 0xC7, 0x92, 0x47,
> -  0x8D, 0x8D, 0x7E, 0xE4, 0xE8, 0xE8, 0x5C, 0x2C,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x6B, 0xAF,
> -  0x2C, 0x85, 0x2C, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C,
> -  0x2C, 0xAF, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85,
> -  0x85, 0xDA, 0x8D, 0x8A, 0x85, 0xAC, 0x95, 0xD9,
> -  0xAC, 0xAC, 0xAC, 0xAC, 0x2C, 0xAF, 0xAF, 0x2C,
> -  0x2C, 0xAF, 0xAF, 0xAC, 0x2C, 0xAF, 0x2C, 0xAF,
> -  0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85, 0x85, 0x85,
> -  0x85, 0x2C, 0xD9, 0xD9, 0x2D, 0x6B, 0x41, 0x2A,
> -  0xE8, 0xA3, 0xC8, 0x8D, 0x8A, 0x8A, 0x8A, 0x8D,
> -  0x4D, 0xA3, 0x3D, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C,
> -  0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0xDB,
> -  0xDA, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAF,
> -  0x2C, 0xAC, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85,
> -  0x85, 0x85, 0x85, 0x2C, 0xD9, 0x95, 0x7D, 0xD9,
> -  0x7D, 0x7D, 0xD9, 0xAC, 0xAC, 0xAF, 0xAF, 0xAF,
> -  0x2C, 0x2C, 0xAC, 0xAC, 0xD9, 0xAC, 0xAC, 0xD9,
> -  0x95, 0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xAF, 0xAC,
> -  0xD9, 0x7D, 0x7D, 0x7D, 0x33, 0x41, 0x2D, 0xE8,
> -  0xE8, 0x5C, 0xD3, 0x8D, 0x8D, 0x8D, 0x8D, 0x7E,
> -  0x3D, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0xDA, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x81, 0x2C, 0x2C, 0x2C, 0xAC, 0xAC, 0xAC, 0xAC,
> -  0xAC, 0xD9, 0x95, 0x95, 0xAC, 0xAF, 0xAF, 0xAF,
> -  0xAF, 0xAC, 0xD9, 0x95, 0x7D, 0xD6, 0xD6, 0x7D,
> -  0x21, 0xD6, 0x95, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF,
> -  0x2C, 0xAF, 0xAC, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0x21, 0x21, 0x7D, 0x95, 0x95, 0x7D, 0xD6, 0x21,
> -  0xB2, 0xA1, 0x2C, 0x88, 0x20, 0xE3, 0xA3, 0xE8,
> -  0xE8, 0xE8, 0xE4, 0xEE, 0xD3, 0x7E, 0x73, 0x5C,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0x5C, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x2C, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9,
> -  0xD9, 0xD9, 0xD6, 0x21, 0x7D, 0x95, 0x95, 0x7D,
> -  0xD6, 0xB2, 0xA1, 0xA1, 0xB2, 0xD6, 0x21, 0x21,
> -  0x21, 0xD9, 0xD9, 0xD9, 0xAC, 0xAF, 0xAC, 0xAF,
> -  0x2C, 0x2C, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0x95,
> -  0x7D, 0xB2, 0xD6, 0x95, 0xD9, 0x95, 0xD6, 0xA1,
> -  0xA1, 0xAF, 0x5B, 0x20, 0x20, 0xD6, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0x5C, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0x48, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0xE3, 0x8A, 0x2C, 0xAC, 0xAC, 0xD9, 0xD9,
> -  0xD9, 0x95, 0xD6, 0xB2, 0xD6, 0x95, 0xD9, 0x95,
> -  0x21, 0xB2, 0xA1, 0xB2, 0xD6, 0xD6, 0xD6, 0xA1,
> -  0xD9, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAF,
> -  0x2C, 0x2C, 0xAF, 0xAC, 0xD9, 0xAC, 0xD9, 0xD9,
> -  0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0xAC, 0x95, 0x7D,
> -  0xD9, 0x91, 0x20, 0x20, 0xE3, 0xA3, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0x85, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x2B, 0x8A, 0xAF, 0xAC, 0xD9, 0xAC,
> -  0xD9, 0xD9, 0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0xAC,
> -  0x95, 0x7D, 0x95, 0x95, 0xD9, 0x95, 0x7D, 0x21,
> -  0x2C, 0xDA, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
> -  0xAF, 0xAF, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAC,
> -  0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xAF, 0xD9, 0xAF,
> -  0x48, 0x20, 0x20, 0x20, 0xE6, 0xA3, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C,
> -  0xE4, 0x73, 0x41, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x2B, 0xDA, 0xAF, 0xAF, 0xAC,
> -  0xAC, 0xAF, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xAF,
> -  0xD9, 0xD9, 0xAC, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9,
> -  0x85, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, 0xAC, 0xAF,
> -  0xAF, 0xAF, 0xAF, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC,
> -  0xAF, 0x2C, 0x2C, 0x2C, 0xAC, 0x95, 0x95, 0xA1,
> -  0x20, 0x20, 0x20, 0x20, 0xE9, 0x8C, 0x5C, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0x3D, 0x73, 0x73, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xE4, 0x73, 0x73, 0x73, 0xCD,
> -  0x7E, 0xA3, 0x74, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x24, 0x85, 0xAF, 0xAF,
> -  0xAC, 0xAC, 0xAC, 0xAF, 0x85, 0x2C, 0xAC, 0x95,
> -  0x95, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, 0xAC, 0xAF,
> -  0x8A, 0x8A, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, 0x2C,
> -  0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAF, 0xAC,
> -  0xAC, 0xAF, 0xAF, 0xD9, 0xD6, 0xD6, 0x2C, 0x88,
> -  0x20, 0x20, 0x20, 0x88, 0xB2, 0xDA, 0x7E, 0x73,
> -  0xE8, 0xE8, 0xE8, 0x3D, 0x73, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xA3, 0xCD, 0xD3, 0x2A, 0x2A,
> -  0x2A, 0x8C, 0x8D, 0x88, 0x20, 0xE3, 0x6B, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x41, 0x85, 0xAF, 0xAC,
> -  0xAC, 0xAC, 0xAC, 0xAF, 0xAC, 0xD9, 0x7D, 0xD6,
> -  0x7D, 0x7D, 0xD9, 0x95, 0xD9, 0xAC, 0xAC, 0xAF,
> -  0xD3, 0x8D, 0xDA, 0xDA, 0x85, 0x85, 0x2C, 0x2C,
> -  0x2C, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0xAF, 0xAF, 0xAC, 0xD9, 0x95, 0x7D, 0xAC, 0x20,
> -  0x20, 0x20, 0x20, 0xDB, 0x2C, 0xA3, 0x5C, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0x5C, 0x3D, 0x3D, 0xE8, 0xE8,
> -  0xE8, 0xE4, 0xE8, 0xE8, 0xE8, 0xE4, 0x73, 0xEE,
> -  0xD3, 0x2A, 0xEE, 0xAC, 0x20, 0x33, 0x2B, 0xE3,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x9F, 0xAF, 0xD9,
> -  0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xD9, 0x95, 0x7D,
> -  0xD9, 0x95, 0x95, 0x95, 0x95, 0xD9, 0xAF, 0xAF,
> -  0x7E, 0x85, 0x85, 0x2C, 0x85, 0x85, 0x85, 0x2C,
> -  0x2C, 0x2C, 0xAF, 0xD9, 0xD9, 0x95, 0xD9, 0xAC,
> -  0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0xAC, 0x91, 0x20,
> -  0x33, 0xE3, 0x41, 0x48, 0x73, 0x5C, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xA3, 0xD6, 0x6C, 0x85, 0xE8,
> -  0xDA, 0xAE, 0xB2, 0xA3, 0x5C, 0xE8, 0xE8, 0xE8,
> -  0x3D, 0xEE, 0x4D, 0xA3, 0x24, 0x20, 0x6B, 0xDB,
> -  0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x85, 0x95,
> -  0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xD9, 0xAC,
> -  0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC, 0xD9, 0xAC,
> -  0x8A, 0xD9, 0xAC, 0xD9, 0xAC, 0xAC, 0x2C, 0x2C,
> -  0xAF, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0xAF, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x33, 0x20,
> -  0xCC, 0x20, 0xE3, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0xA3, 0xD9, 0x81, 0xAC, 0xDA, 0x2D, 0x5C,
> -  0x48, 0x41, 0x88, 0x74, 0x21, 0xA3, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0x73, 0x8C, 0x8A, 0x20, 0x20, 0x20,
> -  0xDB, 0x33, 0x20, 0x20, 0x20, 0x20, 0xE6, 0xD9,
> -  0xD9, 0xAC, 0xAC, 0xAF, 0xAC, 0xAF, 0xAC, 0xAF,
> -  0xAF, 0xAC, 0xD9, 0xAF, 0xD9, 0xAC, 0xAC, 0xAF,
> -  0x85, 0xD9, 0x95, 0xD9, 0x95, 0xD9, 0xD9, 0xAC,
> -  0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0xAF, 0x2C, 0x2C,
> -  0xAF, 0xAF, 0xAF, 0xAC, 0xAC, 0x2C, 0x20, 0x5B,
> -  0x33, 0x20, 0xD6, 0xE8, 0xE8, 0xE8, 0xE8, 0x73,
> -  0xAF, 0x2D, 0xD9, 0xDA, 0xB2, 0x81, 0x81, 0xE4,
> -  0xA1, 0x91, 0x2B, 0x88, 0x33, 0x80, 0xAF, 0x73,
> -  0xE8, 0xE8, 0xE8, 0x5C, 0xA3, 0x80, 0x41, 0xCC,
> -  0x2B, 0xCC, 0x20, 0x20, 0x20, 0x20, 0x88, 0xDA,
> -  0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAF,
> -  0xAF, 0xAF, 0xAF, 0xAC, 0xAF, 0xAF, 0xAF, 0x2C,
> -  0x85, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xD9,
> -  0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C, 0x85, 0x85,
> -  0x85, 0x2C, 0x2C, 0xAF, 0x2C, 0x91, 0x20, 0xAE,
> -  0x20, 0xDB, 0x3D, 0xE8, 0xE8, 0x5C, 0xB2, 0x80,
> -  0xB2, 0xAF, 0x48, 0xB2, 0x48, 0x89, 0x89, 0x3D,
> -  0x21, 0x48, 0x6C, 0x2D, 0x2B, 0x41, 0xE3, 0xAE,
> -  0xD9, 0x5C, 0xE8, 0xE8, 0xE8, 0x95, 0x33, 0x80,
> -  0xAE, 0x33, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x95,
> -  0x85, 0x2C, 0x85, 0x2C, 0x2C, 0xAF, 0x2C, 0x2C,
> -  0x2C, 0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C,
> -  0xDA, 0xAF, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C,
> -  0xAC, 0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x2C, 0x85,
> -  0x85, 0x2C, 0x2C, 0x2C, 0x8A, 0x41, 0xDB, 0x33,
> -  0x20, 0x95, 0xE8, 0xE8, 0xE8, 0xA3, 0xDB, 0x88,
> -  0xDB, 0x80, 0xD6, 0x7E, 0x85, 0x2D, 0xE6, 0x5C,
> -  0x21, 0x48, 0xD9, 0x7E, 0xD6, 0x2B, 0xCC, 0xAC,
> -  0x85, 0xBC, 0xE8, 0xE8, 0xE8, 0xCD, 0x88, 0x5B,
> -  0x41, 0x20, 0xAE, 0x20, 0x20, 0x20, 0x20, 0x74,
> -  0xDA, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x2C,
> -  0xAF, 0xAC, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9,
> -  0x8A, 0xAF, 0xAC, 0xAC, 0x2C, 0x85, 0x2C, 0xAF,
> -  0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0x2C, 0xAF, 0x2C,
> -  0x2C, 0x2C, 0x2C, 0xAF, 0x95, 0x20, 0x74, 0x20,
> -  0x33, 0xA3, 0xE8, 0xE8, 0xE8, 0xE4, 0x7D, 0xCC,
> -  0x6B, 0x33, 0xAE, 0x2C, 0x85, 0x2D, 0x9F, 0x73,
> -  0xA1, 0x2D, 0x2C, 0xDA, 0x89, 0x48, 0xD3, 0xD9,
> -  0x21, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8, 0xE3, 0x20,
> -  0x20, 0x20, 0xDB, 0x41, 0x20, 0x20, 0x20, 0x20,
> -  0xDA, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAC, 0xAC,
> -  0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0x95, 0x95, 0xD9,
> -  0x2C, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0xAF,
> -  0xAF, 0xAF, 0xAC, 0xAC, 0xD9, 0xAC, 0xAF, 0xAC,
> -  0xAC, 0x95, 0xD6, 0x7D, 0xAE, 0x88, 0x2B, 0x20,
> -  0x6C, 0xE8, 0xE8, 0xE8, 0x73, 0xEE, 0x73, 0x2C,
> -  0x89, 0x2B, 0x41, 0x33, 0xCC, 0xCC, 0x80, 0x3D,
> -  0x2D, 0x74, 0x80, 0x48, 0x8D, 0x95, 0x48, 0x95,
> -  0xEE, 0x5C, 0x5C, 0xE8, 0xE8, 0xE8, 0x24, 0x20,
> -  0x20, 0x20, 0x5B, 0xDB, 0x20, 0x20, 0x20, 0x20,
> -  0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD6, 0x7D,
> -  0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xD9, 0xAC,
> -  0xAC, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C, 0xAF,
> -  0xAC, 0xAC, 0xAC, 0xAC, 0xD9, 0xAC, 0xAC, 0xD9,
> -  0xD6, 0x48, 0xE9, 0x95, 0x20, 0x2B, 0x41, 0x6B,
> -  0x8D, 0xE8, 0xE8, 0xCD, 0x2B, 0x2B, 0x2C, 0x73,
> -  0xCD, 0x48, 0xCA, 0x5B, 0x41, 0x5B, 0x74, 0xDA,
> -  0x80, 0xE6, 0xC8, 0x85, 0xA1, 0x7D, 0x8D, 0x3D,
> -  0x7E, 0xE9, 0x7D, 0xEE, 0xE8, 0xE8, 0x81, 0x20,
> -  0x20, 0x20, 0xE3, 0xE3, 0x20, 0x20, 0x20, 0x20,
> -  0x2D, 0xD9, 0xD6, 0x48, 0x6C, 0xE9, 0xA1, 0xD6,
> -  0xD9, 0xD9, 0xAC, 0xD9, 0xD9, 0x95, 0xAC, 0x2C,
> -  0x2C, 0x2C, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C,
> -  0xAF, 0x2C, 0xAF, 0xD9, 0xAC, 0xAF, 0xAF, 0x95,
> -  0xB2, 0xE9, 0x21, 0x2B, 0x41, 0x2B, 0x20, 0x5B,
> -  0x3D, 0xE8, 0xE8, 0x8D, 0x2B, 0x88, 0x5B, 0xE6,
> -  0xBC, 0x73, 0x85, 0x89, 0x80, 0x5B, 0xE3, 0xAE,
> -  0x2C, 0x8A, 0xD6, 0xB2, 0x2C, 0xA3, 0xA3, 0xD9,
> -  0xA1, 0x2C, 0x85, 0x8D, 0xE8, 0xE8, 0x48, 0x20,
> -  0x20, 0x20, 0xE3, 0x88, 0x20, 0x20, 0x20, 0x20,
> -  0xAE, 0xD9, 0xB2, 0xE9, 0x6C, 0x48, 0xD6, 0xD9,
> -  0x2C, 0x85, 0x2C, 0xD9, 0x7D, 0xD9, 0x2C, 0x85,
> -  0x8D, 0x85, 0x2C, 0xAC, 0xAF, 0x2C, 0x2C, 0x85,
> -  0x2C, 0x2C, 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xD9,
> -  0xB2, 0x48, 0xB2, 0x20, 0x20, 0xCC, 0x20, 0x9F,
> -  0xE8, 0xE8, 0xE8, 0xCD, 0x48, 0x89, 0xDB, 0x88,
> -  0x2B, 0xE9, 0xCD, 0x2A, 0x48, 0x80, 0xAE, 0xAE,
> -  0x7D, 0x48, 0x21, 0xEE, 0x3D, 0x2C, 0x48, 0x85,
> -  0x2C, 0x95, 0x7D, 0x8C, 0xE8, 0xE8, 0xB2, 0x20,
> -  0x20, 0x20, 0xDB, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0xDB, 0x2C, 0xB2, 0x48, 0x48, 0x7D, 0xD9, 0xAF,
> -  0x85, 0x8A, 0x85, 0x7D, 0xB2, 0x95, 0x85, 0xDA,
> -  0xD3, 0x85, 0xAF, 0xAC, 0x2C, 0x85, 0x85, 0x2C,
> -  0xAC, 0xAC, 0xAC, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C,
> -  0xD9, 0xAC, 0x5B, 0x20, 0x20, 0xAE, 0x20, 0x2D,
> -  0xE8, 0xE8, 0xE8, 0x7E, 0xD6, 0x48, 0xE9, 0xAE,
> -  0x88, 0x5B, 0x80, 0x6C, 0xAE, 0xCA, 0x91, 0xE9,
> -  0x43, 0x9F, 0xE6, 0x2C, 0x48, 0x21, 0xBC, 0x95,
> -  0x95, 0xD6, 0x21, 0x7E, 0xE8, 0xE8, 0x7D, 0x20,
> -  0x20, 0x20, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x6B, 0xDA, 0xD9, 0x48, 0xB2, 0xD9, 0x2C, 0x85,
> -  0xDA, 0xDA, 0x2C, 0xA1, 0x48, 0xAC, 0xDA, 0x8D,
> -  0x2A, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C,
> -  0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF,
> -  0x7D, 0xD6, 0x20, 0x20, 0x88, 0x9F, 0x20, 0xA1,
> -  0xE8, 0xE8, 0xE8, 0xA3, 0xD6, 0x6C, 0xB2, 0x2C,
> -  0x89, 0xE3, 0x88, 0xDB, 0xCC, 0x24, 0x7D, 0xEE,
> -  0xB2, 0xCC, 0xAE, 0x2D, 0xDA, 0x2C, 0xD6, 0x2C,
> -  0xB2, 0x2D, 0xD6, 0xEE, 0xE8, 0xE8, 0x95, 0x20,
> -  0x20, 0x20, 0xDB, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x6B, 0xDA, 0x95, 0xA1, 0xB2, 0xAC, 0x85, 0x85,
> -  0xDA, 0x2C, 0x95, 0xA1, 0x21, 0x2C, 0x8A, 0x2A,
> -  0xAF, 0xA1, 0x48, 0xD6, 0xAF, 0x2C, 0x2C, 0xAC,
> -  0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D,
> -  0x48, 0xE6, 0x20, 0x20, 0x33, 0x89, 0x6B, 0x95,
> -  0xE8, 0xE8, 0xE8, 0xA3, 0x21, 0x48, 0xAF, 0xAF,
> -  0x9F, 0xE9, 0x43, 0x33, 0x33, 0x2D, 0xDA, 0xCD,
> -  0xD6, 0xAE, 0x85, 0x2C, 0x7D, 0xD6, 0x91, 0xB8,
> -  0xD4, 0x48, 0x7D, 0xA3, 0xE8, 0xE8, 0x95, 0x20,
> -  0x20, 0x33, 0xE3, 0x20, 0x20, 0x20, 0x20, 0x20,
> -  0x20, 0x2C, 0x48, 0x6C, 0xB2, 0xAF, 0xDA, 0xDA,
> -  0x85, 0xAF, 0xD9, 0x95, 0xAC, 0xDA, 0x8A, 0xDA,
> -  0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF,
> -  0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0x95, 0xD6,
> -  0x21, 0x24, 0x20, 0x20, 0x20, 0x5B, 0xDB, 0xAC,
> -  0xE8, 0xE8, 0xE8, 0x3D, 0x7D, 0x48, 0xE6, 0x2D,
> -  0x85, 0x81, 0x81, 0x48, 0xAE, 0xCA, 0x89, 0xCC,
> -  0xAE, 0xDB, 0x2D, 0x95, 0x21, 0xCC, 0xDB, 0xAE,
> -  0x91, 0xE9, 0x7D, 0x73, 0xE8, 0xE8, 0x48, 0x20,
> -  0x6B, 0x74, 0x41, 0x88, 0x6B, 0x20, 0x20, 0x20,
> -  0x6B, 0x95, 0xB2, 0xD6, 0xD9, 0x85, 0xDA, 0xDA,
> -  0xDA, 0x2C, 0xAF, 0xAF, 0x2C, 0xDA, 0xDA, 0x85,
> -  0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAC,
> -  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0x95,
> -  0x95, 0x6C, 0x41, 0x93, 0x93, 0x41, 0xDB, 0x95,
> -  0xE8, 0xE8, 0xE8, 0x3D, 0x95, 0xD4, 0x6C, 0x21,
> -  0x2D, 0x95, 0xCD, 0x2C, 0xD6, 0xD9, 0x6C, 0x91,
> -  0x89, 0x7D, 0xAC, 0x2A, 0x8D, 0xE6, 0xCC, 0x88,
> -  0x74, 0x48, 0xD9, 0xE4, 0xE8, 0xE8, 0xE6, 0x88,
> -  0x2B, 0x88, 0x20, 0x33, 0xDB, 0x2B, 0xDB, 0x20,
> -  0x91, 0x7D, 0xD9, 0xD9, 0x85, 0x85, 0xDA, 0xDA,
> -  0x85, 0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
> -  0xA1, 0xA1, 0xD6, 0xAF, 0x85, 0xDA, 0x85, 0x2C,
> -  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xAC,
> -  0x2C, 0x47, 0x87, 0x3E, 0x3E, 0xA4, 0x7B, 0x80,
> -  0xA3, 0xE8, 0xE8, 0x5C, 0x7D, 0x48, 0xE6, 0xD9,
> -  0xBC, 0xEE, 0x7D, 0x43, 0xD6, 0x21, 0x43, 0x6C,
> -  0x43, 0x7D, 0x7D, 0xB2, 0x8A, 0xEE, 0x2C, 0xCA,
> -  0xAE, 0x48, 0x2C, 0xE4, 0xE8, 0x5C, 0xCC, 0x88,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x41, 0x91, 0xE3,
> -  0x21, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85,
> -  0x2C, 0xAC, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAF,
> -  0xD6, 0x7D, 0xD9, 0x2C, 0xDA, 0xDA, 0x85, 0xAC,
> -  0xD9, 0x7D, 0x7D, 0xD9, 0xD9, 0xD9, 0x2C, 0x2C,
> -  0xB8, 0x9C, 0xEC, 0x62, 0x6F, 0x62, 0x70, 0x3C,
> -  0xAE, 0xCD, 0xE8, 0xE8, 0x8C, 0x7D, 0xC8, 0x3D,
> -  0x8A, 0xE9, 0x2D, 0x9E, 0xA1, 0xD6, 0x48, 0x73,
> -  0x81, 0xD6, 0xD6, 0xAE, 0x5B, 0x2D, 0xA3, 0xA3,
> -  0x21, 0x21, 0xCD, 0xE8, 0xC0, 0x56, 0x31, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x33, 0xCC, 0xDB,
> -  0x42, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C,
> -  0xAC, 0xD9, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAF,
> -  0xD9, 0x95, 0xAC, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
> -  0x7D, 0xD6, 0xD6, 0xD9, 0xAC, 0xAF, 0x8A, 0xBC,
> -  0xC2, 0x68, 0x2E, 0x4B, 0xC9, 0x8B, 0x62, 0x87,
> -  0x3C, 0x74, 0xBC, 0xE8, 0xE8, 0xE4, 0xEE, 0xA1,
> -  0xE9, 0x21, 0xE6, 0x89, 0x48, 0x7D, 0xB2, 0x5C,
> -  0x6C, 0x7D, 0x21, 0x80, 0xE3, 0x33, 0xCC, 0x2C,
> -  0x3D, 0x3D, 0xE8, 0xE8, 0xEC, 0xCB, 0x5A, 0x6B,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x88, 0x41, 0x51,
> -  0x49, 0x28, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF,
> -  0xAC, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
> -  0xD9, 0x95, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
> -  0xB2, 0xB2, 0x2C, 0x2A, 0x79, 0x79, 0x97, 0x44,
> -  0xED, 0x29, 0x32, 0x62, 0x4B, 0x62, 0x6F, 0x22,
> -  0xF3, 0x6B, 0x33, 0x85, 0x73, 0xE4, 0x2D, 0x2B,
> -  0xCC, 0x9F, 0xDA, 0xBC, 0x48, 0xD6, 0xA1, 0xE4,
> -  0xE9, 0xD6, 0xD9, 0x2A, 0xB2, 0x2B, 0x2B, 0xA1,
> -  0xB8, 0xE8, 0xE8, 0xE8, 0xEC, 0x3E, 0x30, 0x20,
> -  0x20, 0x20, 0x20, 0x20, 0x20, 0x6B, 0x54, 0xDC,
> -  0xC9, 0x53, 0xBC, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF,
> -  0xAF, 0xAC, 0xAF, 0xAC, 0xAC, 0x2C, 0xAF, 0xAC,
> -  0x2C, 0x7D, 0xD9, 0x2C, 0x85, 0xDA, 0xAF, 0x7D,
> -  0xB2, 0xAC, 0xC6, 0xBA, 0x4C, 0xEF, 0xA7, 0xEF,
> -  0xEC, 0x7A, 0x62, 0x4B, 0x62, 0x4B, 0x8B, 0x4B,
> -  0x3A, 0x52, 0x20, 0x6B, 0x21, 0x73, 0xAC, 0x2B,
> -  0x41, 0x33, 0x48, 0x67, 0xA1, 0xD6, 0xD6, 0x5C,
> -  0xE9, 0xD6, 0x2C, 0xEE, 0xB2, 0x9F, 0x8A, 0x95,
> -  0x4D, 0xE8, 0xE8, 0x3D, 0x7A, 0x57, 0xD1, 0x7B,
> -  0x20, 0x20, 0x20, 0x20, 0x6B, 0xCF, 0xBA, 0x3E,
> -  0x3E, 0xD0, 0xBC, 0xAC, 0xAC, 0x2C, 0x2C, 0xAC,
> -  0xD9, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9,
> -  0x85, 0xD9, 0xAF, 0xDA, 0xDA, 0x85, 0xAC, 0x21,
> -  0xB2, 0x2A, 0xBA, 0x57, 0x2E, 0x2E, 0x2E, 0x7A,
> -  0x32, 0x62, 0x8B, 0x4B, 0x8B, 0x4B, 0x4B, 0x4B,
> -  0xC9, 0x4A, 0x5F, 0x20, 0x20, 0x2D, 0xA3, 0xD9,
> -  0xCA, 0x88, 0xDB, 0x24, 0x48, 0x7D, 0xB2, 0xE4,
> -  0x2D, 0x7D, 0x7D, 0x81, 0xA1, 0xDA, 0x21, 0xDA,
> -  0xE4, 0xE8, 0xEE, 0xF1, 0x2E, 0x57, 0x82, 0x76,
> -  0x52, 0x4F, 0x4F, 0x98, 0xDE, 0xB5, 0xEC, 0x2E,
> -  0x3E, 0x6D, 0x85, 0x2C, 0xAC, 0xAC, 0xD9, 0xD9,
> -  0x95, 0xD6, 0x7D, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
> -  0xDA, 0x2C, 0x85, 0xDA, 0xDA, 0x2C, 0x95, 0xB2,
> -  0x21, 0xB8, 0xED, 0x2E, 0x3E, 0x4B, 0xC9, 0x4B,
> -  0x8B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
> -  0x22, 0x6F, 0xCE, 0x20, 0x20, 0x20, 0x80, 0xCD,
> -  0xDA, 0x2D, 0x2B, 0xDB, 0xE9, 0xD6, 0x95, 0x5C,
> -  0x2D, 0x7D, 0x7D, 0xAF, 0xAF, 0xAC, 0xEE, 0x5C,
> -  0xE8, 0xE8, 0xEB, 0x25, 0x7A, 0x57, 0x39, 0xE1,
> -  0x83, 0xA8, 0x55, 0x83, 0x82, 0x57, 0x32, 0x8B,
> -  0x62, 0x6D, 0xEB, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0xD9, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
> -  0xDA, 0x2C, 0x85, 0x85, 0x85, 0xAC, 0xD6, 0x21,
> -  0x95, 0x6E, 0xED, 0x57, 0x62, 0x4B, 0x8B, 0x4B,
> -  0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x62,
> -  0x62, 0x62, 0x25, 0x3C, 0x20, 0x20, 0x20, 0xE3,
> -  0x2A, 0xBC, 0x7D, 0xCA, 0x6C, 0xD6, 0x95, 0x3D,
> -  0x81, 0x7D, 0xD6, 0xD6, 0xDA, 0x73, 0xE8, 0xE8,
> -  0xE8, 0x4D, 0x94, 0xED, 0x72, 0x3A, 0xF1, 0xA7,
> -  0x39, 0xED, 0x39, 0xEF, 0x57, 0x32, 0x8B, 0x4B,
> -  0x62, 0x62, 0xA6, 0x2A, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0x2C, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
> -  0x85, 0x2C, 0x2C, 0xAF, 0xAC, 0x95, 0x21, 0x7D,
> -  0xAC, 0x8C, 0x46, 0xC4, 0x62, 0x8B, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
> -  0x4B, 0x62, 0xC9, 0x30, 0x7B, 0x20, 0x20, 0x20,
> -  0x41, 0x4D, 0x3D, 0x85, 0x48, 0x21, 0xDA, 0x3D,
> -  0xE9, 0xD6, 0xD9, 0xCD, 0x5C, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0x4D, 0x71, 0x46, 0xEC, 0x2E, 0x72, 0xEC,
> -  0x29, 0x29, 0x7C, 0x29, 0x2E, 0x4B, 0x4B, 0x62,
> -  0x62, 0x4B, 0x3A, 0xAD, 0xE2, 0xAF, 0xD9, 0xD9,
> -  0x2C, 0xDA, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
> -  0x2C, 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD9,
> -  0x2C, 0x8C, 0xBA, 0x7C, 0x2E, 0x4B, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
> -  0x4B, 0x62, 0xC9, 0xDC, 0x34, 0x20, 0x20, 0x20,
> -  0x20, 0xAC, 0xE8, 0x5C, 0x8C, 0xBC, 0xE4, 0xE8,
> -  0xEE, 0x2A, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0xE4, 0x7E, 0x65, 0x46, 0x29, 0x62, 0x62, 0x2E,
> -  0x2E, 0x72, 0x2E, 0x2E, 0x32, 0x4B, 0x4B, 0x62,
> -  0x4B, 0x4B, 0x4B, 0x32, 0x61, 0x9D, 0x2C, 0xD9,
> -  0x2C, 0x85, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
> -  0x2C, 0xAC, 0xD9, 0x95, 0xD6, 0x7D, 0x95, 0xAC,
> -  0x2C, 0xDA, 0x40, 0x7C, 0x2E, 0x4B, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
> -  0x4B, 0x62, 0x62, 0x22, 0xB7, 0xCE, 0x20, 0x20,
> -  0x20, 0x95, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C,
> -  0x3D, 0xE9, 0x9A, 0x46, 0x7C, 0x32, 0x8B, 0x62,
> -  0x4B, 0x8B, 0x8B, 0x4B, 0x4B, 0x4B, 0x4B, 0x62,
> -  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x61, 0x4E, 0xDA,
> -  0x85, 0x85, 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0xD9,
> -  0x85, 0xD9, 0x7D, 0x21, 0x21, 0xD6, 0xAC, 0x2C,
> -  0x2C, 0xDA, 0xDD, 0x77, 0x8B, 0x62, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
> -  0x3E, 0x8B, 0x32, 0xC9, 0x22, 0x68, 0x88, 0x33,
> -  0xA1, 0x73, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0x5C, 0x5C, 0x5C, 0x5C, 0x3D,
> -  0x89, 0x20, 0x54, 0x23, 0x29, 0x2E, 0x4B, 0x62,
> -  0x4B, 0x3E, 0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x8B,
> -  0x8B, 0xC9, 0x6F, 0x4B, 0x8B, 0x4B, 0x78, 0xE2,
> -  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0x7D, 0xD9, 0xAC,
> -  0x2C, 0xD9, 0xD6, 0xB2, 0x21, 0x7D, 0xAF, 0x85,
> -  0x2C, 0xDA, 0x40, 0xEF, 0x62, 0x62, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x8B, 0x4B, 0xC9, 0x63, 0xB4, 0x5C,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0x5C, 0x5C, 0xCD, 0xAE,
> -  0x20, 0x20, 0xCE, 0xE1, 0x57, 0x32, 0x4B, 0x4B,
> -  0x8B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
> -  0x8B, 0x4B, 0x62, 0x4B, 0x62, 0x2E, 0x61, 0x28,
> -  0x8D, 0xDA, 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
> -  0xAF, 0xD9, 0xD6, 0xB2, 0x21, 0xD9, 0x2C, 0x85,
> -  0xAF, 0xEB, 0xE1, 0x57, 0x2E, 0x62, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x4B, 0x4B, 0x3E, 0x9B, 0x31, 0x6E,
> -  0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
> -  0x5C, 0xE8, 0xE8, 0xE8, 0x3D, 0x7D, 0x33, 0x6B,
> -  0x20, 0x20, 0x34, 0x23, 0x29, 0x3E, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
> -  0x4B, 0x3E, 0x62, 0x62, 0x2E, 0xC4, 0x49, 0xD5,
> -  0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9,
> -  0xD9, 0x95, 0x21, 0x48, 0xD6, 0xAC, 0x85, 0x85,
> -  0xAF, 0xB6, 0x5D, 0x2E, 0x32, 0x4B, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B,
> -  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x2E, 0x45, 0xDE,
> -  0xDA, 0x5C, 0xE8, 0x5C, 0xE8, 0xE8, 0x5C, 0xE8,
> -  0x5C, 0x5C, 0xA3, 0xAC, 0x2B, 0x20, 0x20, 0x20,
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> -  0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x4B, 0x4B, 0x4B,
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> +    0x33, 0x26, 0x23, 0x21, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x21, 0x23, 0x24, 0x27, 0x2a, 0x35, 0x2e, 0x2f,
> +    0x41, 0xce, 0xcf, 0x6c, 0x80, 0xcc, 0xb9, 0x74,
> +    0x84, 0x90, 0x75, 0x7e, 0x74, 0x8f, 0xcd, 0x79,
> +    0xc6, 0x2b, 0x9d, 0x41, 0x2f, 0x34, 0x2d, 0x2d,
> +    0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x34, 0x2f, 0x38,
> +    0x4d, 0x37, 0xd0, 0xd1, 0x8f, 0x74, 0x63, 0x7e,
> +    0x75, 0x7e, 0x63, 0xc7, 0x88, 0xc4, 0x31, 0x2a,
> +    0x24, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x21, 0x22, 0x23, 0x24, 0x26, 0x30,
> +    0x33, 0x39, 0x2e, 0x51, 0x41, 0xb2, 0x6c, 0xd1,
> +    0x80, 0xcc, 0xcc, 0xcc, 0xd2, 0xd1, 0xb7, 0xd3,
> +    0x41, 0x34, 0x35, 0x32, 0x30, 0x27, 0x27, 0x27,
> +    0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x30, 0x2a,
> +    0x2b, 0x34, 0xd4, 0xca, 0xd5, 0x8f, 0xbb, 0xc7,
> +    0xc7, 0xbb, 0xcc, 0x6c, 0x41, 0x39, 0x27, 0x28,
> +    0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22,
> +    0x28, 0x24, 0x26, 0x2a, 0x33, 0x2c, 0x2f, 0x41,
> +    0xd6, 0xb7, 0x79, 0x79, 0x79, 0xca, 0xd7, 0x51,
> +    0x39, 0x30, 0x24, 0x23, 0x22, 0x22, 0x22, 0x22,
> +    0x22, 0x22, 0x21, 0x22, 0x22, 0x22, 0x22, 0x23,
> +    0x24, 0x2a, 0x31, 0xd8, 0xc8, 0x79, 0xd1, 0x80,
> +    0xd5, 0xba, 0xd9, 0x2f, 0x35, 0x26, 0x23, 0x21,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x21, 0x22, 0x23, 0x28, 0x25, 0x30, 0x2b,
> +    0x31, 0x2f, 0xd4, 0xd8, 0xd8, 0x2f, 0x2e, 0x33,
> +    0x26, 0x23, 0x21, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x21, 0x28, 0x27, 0x35, 0x34, 0xd8, 0xd8, 0xd8,
> +    0xda, 0xd4, 0x2e, 0x33, 0x25, 0x23, 0x21, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x23, 0x28,
> +    0x26, 0x30, 0x32, 0x2b, 0x33, 0x2a, 0x26, 0x28,
> +    0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x21, 0x23, 0x25, 0x30, 0x33, 0x35, 0x35,
> +    0x2b, 0x2a, 0x26, 0x28, 0x22, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21,
> +    0x21, 0x22, 0x23, 0x28, 0x28, 0x23, 0x22, 0x21,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x21, 0x23, 0x28, 0x24, 0x24,
> +    0x28, 0x23, 0x22, 0x21, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
> +    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
>  };
> -
> -#define INCLUDE_LINUX_LOGOBW
> -#define INCLUDE_LINUX_LOGO16
> -#include <linux/linux_logo.h>
>  
>  #endif /* INCLUDE_LINUX_LOGO_DATA */
> 
> Gr{oetje,eeting}s,
> 
> Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>     -- Linus Torvalds
> 
> 
> 
------=_NextPart_000_00FE_01C29C58.D4534FC0
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------=_NextPart_000_00FE_01C29C58.D4534FC0--


From Geert.Uytterhoeven@sonycom.com Thu Dec  5 12:20:41 2002
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Date: Thu, 5 Dec 2002 12:20:21 +0100 (MET)
From: Geert Uytterhoeven <geert@linux-m68k.org>
To: "Kevin D. Kissell" <kevink@mips.com>
cc: Ralf Baechle <ralf@linux-mips.org>,
	Linux/MIPS Development <linux-mips@linux-mips.org>
Subject: Re: Old SGI penguin logo
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On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> I'm not that good at visualizing things based on the ASCII
> source, but how does that compare with the attached GIF,

Then visit the website :-)

> which I generated ages ago, and which is used on at least
> a couple MIPS/Linux web sites?

That one has a MIPS logo instead of a SGI logo.

> ----- Original Message ----- 
> From: "Geert Uytterhoeven" <geert@linux-m68k.org>
> To: "Ralf Baechle" <ralf@linux-mips.org>
> Cc: "Linux/MIPS Development" <linux-mips@linux-mips.org>
> Sent: Thursday, December 05, 2002 12:07 PM
> Subject: Old SGI penguin logo
> 
> 
> > 
> > In 2.4.6, the penguin logos were updated in Linus' tree for all architectures
> > (cfr.  http://home.tvd.be/cr26864/Linux/fbdev/logo.html).

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


From kevink@mips.com Thu Dec  5 12:26:58 2002
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Subject: Re: Old SGI penguin logo
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> On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > I'm not that good at visualizing things based on the ASCII
> > source, but how does that compare with the attached GIF,
> 
> Then visit the website :-)
> 
> > which I generated ages ago, and which is used on at least
> > a couple MIPS/Linux web sites?
> 
> That one has a MIPS logo instead of a SGI logo.

Given that we're working on a port to MIPS, not 
SGI, wouldn't it be more appropriate?

From kevin@gv.com.tw Thu Dec  5 12:49:56 2002
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From: "??" <kevin@gv.com.tw>
To: <linux-mips@linux-mips.org>, "Ralf Baechle" <ralf@linux-mips.org>
Subject: sgi linux version 2.4.18 cvs 
Date: Thu, 5 Dec 2002 19:50:16 +0800
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dear all,

how to check out sgi linux source version 2.4.18 from cvs?

best regards,


From Geert.Uytterhoeven@sonycom.com Thu Dec  5 13:10:20 2002
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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: "Kevin D. Kissell" <kevink@mips.com>
cc: Ralf Baechle <ralf@linux-mips.org>,
	Linux/MIPS Development <linux-mips@linux-mips.org>
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On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > > I'm not that good at visualizing things based on the ASCII
> > > source, but how does that compare with the attached GIF,
> > 
> > Then visit the website :-)
> > 
> > > which I generated ages ago, and which is used on at least
> > > a couple MIPS/Linux web sites?
> > 
> > That one has a MIPS logo instead of a SGI logo.
> 
> Given that we're working on a port to MIPS, not 
> SGI, wouldn't it be more appropriate?

Yes, if some talented person can create a nice penguin/mips logo, that would be
nice.

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds



From ralf@linux-mips.org Thu Dec  5 13:24:18 2002
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From: Ralf Baechle <ralf@linux-mips.org>
To: ?? <kevin@gv.com.tw>
Cc: linux-mips@linux-mips.org
Subject: Re: sgi linux version 2.4.18 cvs
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On Thu, Dec 05, 2002 at 07:50:16PM +0800, ?? wrote:

Hello doublequestionmark,

> how to check out sgi linux source version 2.4.18 from cvs?

Use -rlinux_2_4_18 for checkout.

  Ralf

From carstenl@mips.com Thu Dec  5 13:30:25 2002
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--------------E3A736EA6106AFECAE9E9AE8
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Try this (attached).

/Carsten



Geert Uytterhoeven wrote:

> On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > > On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > > > I'm not that good at visualizing things based on the ASCII
> > > > source, but how does that compare with the attached GIF,
> > >
> > > Then visit the website :-)
> > >
> > > > which I generated ages ago, and which is used on at least
> > > > a couple MIPS/Linux web sites?
> > >
> > > That one has a MIPS logo instead of a SGI logo.
> >
> > Given that we're working on a port to MIPS, not
> > SGI, wouldn't it be more appropriate?
>
> Yes, if some talented person can create a nice penguin/mips logo, that would be
> nice.
>
> Gr{oetje,eeting}s,
>
>                                                 Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                                             -- Linus Torvalds

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



--------------E3A736EA6106AFECAE9E9AE8
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 name="linux_logo.h"
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/* $Id: linux_logo.h,v 1.2 2002/02/11 15:56:48 kjelde Exp $
 *
 * include/asm-mips/linux_logo.h: This is a linux logo
 *                                to be displayed on boot.
 *
 * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 *
 * You can put anything here, but:
 * LINUX_LOGO_COLORS has to be less than 224
 * image size has to be 80x80
 * values have to start from 0x20
 * (i.e. RGB(linux_logo_red[0],
 *	     linux_logo_green[0],
 *	     linux_logo_blue[0]) is color 0x20)
 * BW image has to be 80x80 as well, with MS bit
 * on the left
 * Serial_console ascii image can be any size,
 * but should contain %s to display the version
 */
 
#include <linux/init.h>
#include <linux/version.h>

#define linux_logo_banner "Linux/MIPS version " UTS_RELEASE

#define LINUX_LOGO_COLORS 187

#ifdef INCLUDE_LINUX_LOGO_DATA

unsigned char linux_logo_red[] __initdata = {
  0x00, 0x48, 0x80, 0xE0, 0x80, 0xE8, 0x70, 0x40,
  0xE8, 0xE0, 0xE0, 0x60, 0xE0, 0x40, 0xD8, 0xE0,
  0xC0, 0x48, 0xC0, 0xB8, 0xB8, 0xE8, 0xA0, 0x20,
  0xA0, 0xF4, 0xF0, 0x90, 0x08, 0xE8, 0xD8, 0x88,
  0xE8, 0xF0, 0xE8, 0xF0, 0xE8, 0xE8, 0x68, 0xE8,
  0x68, 0xD0, 0xE0, 0x60, 0xE0, 0x28, 0xA4, 0xF8,
  0x40, 0xC0, 0xB4, 0xC0, 0xA8, 0xF0, 0xB8, 0xA8,
  0x28, 0xF8, 0xE8, 0x94, 0x98, 0xE0, 0x98, 0xF0,
  0xE8, 0x90, 0xF0, 0xD8, 0xF0, 0xF8, 0xF0, 0x88,
  0x80, 0xE4, 0xD0, 0xF0, 0xF0, 0x70, 0xC8, 0xD8,
  0x68, 0xC0, 0xD0, 0xD0, 0x70, 0xB8, 0x48, 0x38,
  0xC8, 0xC8, 0xB0, 0x40, 0xC0, 0xB0, 0x60, 0xA8,
  0xB0, 0xF8, 0xA8, 0x8C, 0xA0, 0xEC, 0x00, 0xA0,
  0xA0, 0xA0, 0x98, 0x98, 0xF0, 0x88, 0xF0, 0xF8,
  0x48, 0x90, 0xF8, 0xF8, 0x74, 0x88, 0x78, 0xF8,
  0xC0, 0x80, 0x70, 0xD8, 0xD8, 0x78, 0xD8, 0x50,
  0xD0, 0x50, 0xD0, 0x70, 0x48, 0xC8, 0xC8, 0x24,
  0x38, 0xA8, 0x38, 0xA4, 0x60, 0xA8, 0xA0, 0xA8,
  0xA8, 0x58, 0xF0, 0xF8, 0x10, 0xA0, 0xF0, 0x50,
  0xF8, 0x90, 0x10, 0x90, 0x48, 0x80, 0x80, 0x40,
  0xE0, 0x38, 0xD8, 0xD8, 0x54, 0x30, 0xD8, 0x50,
  0x28, 0x50, 0xD0, 0x40, 0xC0, 0x20, 0xB0, 0x18,
  0xF0, 0x58, 0xA8, 0x10, 0xF0, 0x18, 0xD8, 0x08,
  0xE4, 0x88, 0x88
};

unsigned char linux_logo_green[] __initdata = {
  0x00, 0x48, 0x58, 0xC8, 0x50, 0xB0, 0x50, 0x40,
  0xA8, 0xB0, 0xA8, 0x40, 0xA0, 0x38, 0xA0, 0xD0,
  0x88, 0x28, 0x80, 0x80, 0x78, 0xE8, 0x80, 0x18,
  0x78, 0xD0, 0xD8, 0x60, 0x08, 0xD0, 0xAC, 0x58,
  0xC8, 0xB8, 0xC0, 0xB0, 0xB8, 0xB0, 0x48, 0xA8,
  0x40, 0xB4, 0xA8, 0x40, 0xA0, 0x28, 0x80, 0xF8,
  0x28, 0x88, 0x84, 0x80, 0xA8, 0xF0, 0x80, 0x80,
  0x18, 0xC8, 0xE8, 0x74, 0x68, 0xE0, 0x60, 0xD8,
  0xCC, 0x60, 0xD0, 0xD8, 0xC8, 0xB8, 0xC0, 0x88,
  0x80, 0xBC, 0xD0, 0xB8, 0xB0, 0x48, 0xC8, 0xB4,
  0x40, 0xC0, 0x98, 0x90, 0x70, 0xB8, 0x30, 0x24,
  0x90, 0x88, 0xB0, 0x28, 0x88, 0x88, 0x60, 0xA8,
  0x80, 0xD8, 0x70, 0x60, 0xA0, 0xCC, 0x00, 0x70,
  0x68, 0x60, 0x98, 0x68, 0xD0, 0x68, 0xC8, 0xCC,
  0x48, 0x90, 0xC0, 0xB8, 0x58, 0x88, 0x50, 0xB0,
  0xC0, 0x80, 0x48, 0xA4, 0x98, 0x78, 0x90, 0x38,
  0x98, 0x30, 0x90, 0x70, 0x30, 0x90, 0x88, 0x24,
  0x28, 0x7C, 0x20, 0x88, 0x60, 0xA8, 0xA0, 0x78,
  0x70, 0x58, 0xD8, 0xD8, 0x10, 0x68, 0xCC, 0x50,
  0xCC, 0x68, 0x04, 0x58, 0x48, 0x58, 0x50, 0x40,
  0xA4, 0x38, 0xA8, 0xA0, 0x44, 0x30, 0x98, 0x38,
  0x28, 0x30, 0x90, 0x30, 0x90, 0x20, 0x78, 0x18,
  0xE8, 0x58, 0x70, 0x10, 0xE8, 0x14, 0xD8, 0x08,
  0xCC, 0x60, 0x58
};

unsigned char linux_logo_blue[] __initdata = {
  0x00, 0x40, 0x00, 0x08, 0x00, 0x10, 0x04, 0x38,
  0x10, 0x08, 0x08, 0x08, 0x08, 0x24, 0x00, 0x8C,
  0x10, 0x04, 0x10, 0x08, 0x08, 0xF0, 0x04, 0x04,
  0x04, 0x28, 0x10, 0x08, 0x00, 0x08, 0x34, 0x00,
  0x08, 0x10, 0x08, 0x10, 0x08, 0x08, 0x08, 0x08,
  0x08, 0x04, 0x00, 0x00, 0x00, 0x40, 0x3C, 0xF8,
  0x08, 0x08, 0x10, 0x08, 0xB0, 0xF0, 0x00, 0x04,
  0x04, 0x38, 0xE8, 0x04, 0x08, 0xE0, 0x08, 0x08,
  0x14, 0x00, 0x08, 0xD8, 0x08, 0x10, 0x08, 0x90,
  0x9C, 0x10, 0xD0, 0x08, 0x08, 0x08, 0xC8, 0x04,
  0x00, 0xC0, 0x10, 0x10, 0x78, 0xB8, 0x08, 0x20,
  0x08, 0x08, 0xB0, 0x00, 0x00, 0x04, 0x68, 0xA8,
  0x04, 0x30, 0x10, 0x30, 0xA0, 0x38, 0xF8, 0x08,
  0x08, 0x08, 0x98, 0x00, 0x14, 0x04, 0x14, 0x08,
  0x50, 0x90, 0x08, 0x08, 0x04, 0x88, 0x08, 0x08,
  0xE0, 0x80, 0x00, 0x10, 0x10, 0x78, 0x10, 0x08,
  0x08, 0x08, 0x08, 0x70, 0x00, 0x00, 0x00, 0x18,
  0x04, 0x1C, 0x04, 0x04, 0x60, 0xA0, 0xAC, 0x08,
  0x08, 0x58, 0x20, 0x14, 0x04, 0x00, 0x20, 0x50,
  0x14, 0x04, 0x04, 0x04, 0x48, 0x08, 0x08, 0x40,
  0x10, 0x38, 0x08, 0x08, 0x04, 0x30, 0x08, 0x00,
  0x28, 0x00, 0x00, 0x04, 0x04, 0x20, 0x08, 0x18,
  0xEC, 0x64, 0x00, 0x10, 0xD8, 0x04, 0xE8, 0x08,
  0x20, 0x08, 0x08
};

unsigned char linux_logo[] __initdata = {
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0x20, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x20,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0x20, 0xCD, 0x27, 0xC1, 0x20, 0x20,
  0x20, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
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  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x9C,
  0x25, 0x92, 0x92, 0x8E, 0x92, 0x92, 0x65, 0x8E,
  0x65, 0x65, 0x8E, 0x8E, 0x2C, 0x92, 0x65, 0x2C,
  0x2C, 0x92, 0x65, 0x25, 0x69, 0xC3, 0x96, 0x4F,
  0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F,
  0x4F, 0x4F, 0x4F, 0x4F, 0x75, 0x20, 0x20, 0x20,
  0x20, 0x20, 0xD5, 0x22, 0x78, 0x4A, 0x6C, 0x65,
  0x2C, 0x92, 0x92, 0x2C, 0x8E, 0x8E, 0xB6, 0x8E,
  0x8E, 0x2C, 0x92, 0x92, 0x65, 0x92, 0x8E, 0x9C,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x73, 0xC6,
  0x28, 0x41, 0x65, 0x8E, 0x65, 0x92, 0xB8, 0x8E,
  0xB6, 0xB6, 0x8E, 0x8E, 0x92, 0x8E, 0x2C, 0x92,
  0x92, 0x92, 0x41, 0x45, 0xC2, 0x72, 0x87, 0xCB,
  0x55, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F,
  0x4F, 0x4F, 0x8A, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0x58, 0x22, 0x78, 0x2A, 0x6B, 0x65,
  0x8E, 0xB6, 0x2C, 0x2C, 0x8E, 0xB6, 0x92, 0x65,
  0xB6, 0x8E, 0x92, 0x65, 0x8E, 0x2C, 0x9C, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x9C, 0x9C,
  0x2C, 0x47, 0x45, 0x45, 0x25, 0x41, 0x65, 0xB8,
  0xB6, 0x65, 0x92, 0x8E, 0x92, 0x8E, 0x92, 0x92,
  0xB6, 0x39, 0x8E, 0x65, 0x2A, 0x72, 0x33, 0x7B,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0xA4, 0x61, 0xA5, 0x4A, 0x65, 0x8E,
  0x92, 0x8E, 0x2C, 0xB6, 0x2C, 0x8E, 0xB6, 0xB6,
  0x2C, 0x65, 0x59, 0x9C, 0x9C, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x73, 0x73,
  0xA2, 0xA0, 0x72, 0x72, 0xC3, 0x2A, 0x2A, 0x2A,
  0x45, 0x43, 0x41, 0x65, 0xB6, 0x92, 0x8E, 0x8E,
  0x92, 0x65, 0x92, 0x43, 0xC3, 0x78, 0xB0, 0x48,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0xC7, 0x61, 0x79, 0xC3, 0x6C, 0x92,
  0xB6, 0x65, 0x92, 0x2C, 0x65, 0x65, 0x43, 0x25,
  0x9B, 0x9E, 0xA9, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0xD9,
  0x88, 0x34, 0x33, 0x51, 0x79, 0x78, 0xA2, 0xA2,
  0xA0, 0xC6, 0xC3, 0x2A, 0x45, 0x92, 0x92, 0x92,
  0x92, 0x65, 0x41, 0x2A, 0x78, 0x34, 0x88, 0x6D,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0xA4, 0x24, 0x33, 0x78, 0xC3, 0x45,
  0x45, 0x41, 0x45, 0x45, 0x2A, 0x2C, 0x9C, 0x9C,
  0x34, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x3B, 0x5C, 0xAF, 0xCE, 0x34, 0x33,
  0x53, 0x53, 0xCC, 0xA2, 0xA0, 0x47, 0x25, 0x43,
  0x41, 0x47, 0xC3, 0xA0, 0x33, 0xB0, 0x3F, 0xC7,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
  0x20, 0x20, 0x50, 0x6D, 0xCE, 0x53, 0xCA, 0x2E,
  0x4C, 0x2A, 0x2C, 0xC3, 0xA0, 0x78, 0x33, 0x3B,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x2B, 0xBD,
  0x5E, 0x5C, 0xB0, 0xAF, 0xCE, 0x33, 0x79, 0xA0,
  0x78, 0x79, 0x33, 0xCE, 0x88, 0xBB, 0x9A, 0x7B,
  0x20, 0x20, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x7B, 0x70, 0x89, 0xCE, 0x33, 0x79,
  0x78, 0xCA, 0xA5, 0x51, 0x56, 0xB0, 0x76, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0xA8, 0x2B, 0xBD, 0x5C, 0xB0, 0xAF,
  0xAF, 0xB0, 0x88, 0x3B, 0xBE, 0x9A, 0xC9, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x50, 0xA1, 0x24, 0x88, 0xB0, 0xCE,
  0xCE, 0x80, 0xCE, 0xB5, 0x3B, 0x2D, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x76, 0x46, 0xBE,
  0xBD, 0xDA, 0xBE, 0x6D, 0x4B, 0xCB, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x50, 0xA4, 0x6D, 0x3B, 0x5C,
  0x5C, 0x8B, 0xDA, 0x48, 0xA1, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0xCB, 0x7B, 0xCB, 0xCB, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0xCB, 0x7B, 0x31,
  0x76, 0x76, 0x77, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
  0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71
};

#define INCLUDE_LINUX_LOGOBW
#define INCLUDE_LINUX_LOGO16
#include <linux/linux_logo.h>

#else

/* prototypes only */
extern unsigned char linux_logo_red[];
extern unsigned char linux_logo_green[];
extern unsigned char linux_logo_blue[];
extern unsigned char linux_logo[];
extern unsigned char linux_logo_bw[];
extern unsigned char linux_logo16_red[];
extern unsigned char linux_logo16_green[];
extern unsigned char linux_logo16_blue[];
extern unsigned char linux_logo16[];

#endif

--------------E3A736EA6106AFECAE9E9AE8--


From Geert.Uytterhoeven@sonycom.com Thu Dec  5 13:45:59 2002
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Date: Thu, 5 Dec 2002 13:45:40 +0100 (MET)
From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Carsten Langgaard <carstenl@mips.com>
cc: "Kevin D. Kissell" <kevink@mips.com>,
	Ralf Baechle <ralf@linux-mips.org>,
	Linux/MIPS Development <linux-mips@linux-mips.org>
Subject: Re: Old SGI penguin logo
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On Thu, 5 Dec 2002, Carsten Langgaard wrote:
> Try this (attached).

Unfortunately it doen't have the nice glowing look of the other logos.

> Geert Uytterhoeven wrote:
> > On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > > > On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > > > > I'm not that good at visualizing things based on the ASCII
> > > > > source, but how does that compare with the attached GIF,
> > > >
> > > > Then visit the website :-)
> > > >
> > > > > which I generated ages ago, and which is used on at least
> > > > > a couple MIPS/Linux web sites?
> > > >
> > > > That one has a MIPS logo instead of a SGI logo.
> > >
> > > Given that we're working on a port to MIPS, not
> > > SGI, wouldn't it be more appropriate?
> >
> > Yes, if some talented person can create a nice penguin/mips logo, that would be
> > nice.

Gr{oetje,eeting}s,

						Geert

P.S. Yes, logo threads easily grow beyond the average thread size :-)
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


From carstenl@mips.com Thu Dec  5 13:49:07 2002
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Geert Uytterhoeven wrote:

> On Thu, 5 Dec 2002, Carsten Langgaard wrote:
> > Try this (attached).
>
> Unfortunately it doen't have the nice glowing look of the other logos.
>

Sorry, it's the best I got.


>
> > Geert Uytterhoeven wrote:
> > > On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > > > > On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > > > > > I'm not that good at visualizing things based on the ASCII
> > > > > > source, but how does that compare with the attached GIF,
> > > > >
> > > > > Then visit the website :-)
> > > > >
> > > > > > which I generated ages ago, and which is used on at least
> > > > > > a couple MIPS/Linux web sites?
> > > > >
> > > > > That one has a MIPS logo instead of a SGI logo.
> > > >
> > > > Given that we're working on a port to MIPS, not
> > > > SGI, wouldn't it be more appropriate?
> > >
> > > Yes, if some talented person can create a nice penguin/mips logo, that would be
> > > nice.
>
> Gr{oetje,eeting}s,
>
>                                                 Geert
>
> P.S. Yes, logo threads easily grow beyond the average thread size :-)
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                                             -- Linus Torvalds

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From agx@sigxcpu.org Thu Dec  5 13:49:41 2002
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From: Guido Guenther <agx@sigxcpu.org>
To: linux-mips@linux-mips.org
Subject: Re: Old SGI penguin logo
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On Thu, Dec 05, 2002 at 01:10:09PM +0100, Geert Uytterhoeven wrote:
> On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
[..snip..] 
> > Given that we're working on a port to MIPS, not 
> > SGI, wouldn't it be more appropriate?
> 
> Yes, if some talented person can create a nice penguin/mips logo, that would be
> nice.
Can we keep the SGI logo for the SGI IP22, IP27 & IP32 subarchitectures?
 -- Guido

From ralf@linux-mips.org Thu Dec  5 14:10:28 2002
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From: Ralf Baechle <ralf@linux-mips.org>
To: Carsten Langgaard <carstenl@mips.com>
Cc: linux-mips@linux-mips.org
Subject: Re: Compiler problems with zero-length array in the middle of a struct
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On Thu, Dec 05, 2002 at 11:47:26AM +0100, Carsten Langgaard wrote:

> Some compiler reject a zero-length array in the middle of a structure,
> and report it as an error.
> So could we please redo the change, that has recently been done to
> include/linux/raid/md_p.h (see patch below).

Hmm...  What compiler version is that?  The gcc documentation explicitly
permits empty arrays.

  Ralf

From carstenl@mips.com Thu Dec  5 14:35:12 2002
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Date: Thu, 05 Dec 2002 14:35:03 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@linux-mips.org>
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References: <3DEF2EBE.F273B44A@mips.com> <20021205141018.A6106@linux-mips.org>
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It should be a problem in gcc-3.0, also the SDE compiler has a problem with
that, but it's going to be fixed.

/Carsten


Ralf Baechle wrote:

> On Thu, Dec 05, 2002 at 11:47:26AM +0100, Carsten Langgaard wrote:
>
> > Some compiler reject a zero-length array in the middle of a structure,
> > and report it as an error.
> > So could we please redo the change, that has recently been done to
> > include/linux/raid/md_p.h (see patch below).
>
> Hmm...  What compiler version is that?  The gcc documentation explicitly
> permits empty arrays.
>
>   Ralf

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To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: EJTAG and NMI handler broken
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The EJTAG and NMI handler are broken in the 32-bit kernel, because they
are laying in the __INIT section, which is removed after boot.
The handlers are missing in the 64-bit kernel.
The attached patch will fix that.

/Carsten



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Index: arch/mips/kernel/head.S
===================================================================
RCS file: /home/cvs/linux/arch/mips/kernel/head.S,v
retrieving revision 1.29.2.14
diff -u -r1.29.2.14 head.S
--- arch/mips/kernel/head.S	5 Aug 2002 23:53:33 -0000	1.29.2.14
+++ arch/mips/kernel/head.S	5 Dec 2002 13:32:24 -0000
@@ -92,34 +92,6 @@
 		END(except_vec_ejtag_debug)
 
 		/*
-		 * EJTAG debug exception handler.
-		 */
-		NESTED(ejtag_debug_handler, PT_SIZE, sp)
-		.set	noat
-		.set	noreorder
-		mtc0	k0, CP0_DESAVE
-		mfc0	k0, CP0_DEBUG
-
-		sll	k0, k0, 30	# Check for SDBBP.
-		bgez	k0, ejtag_return
-
-		la	k0, ejtag_debug_buffer
-		sw	k1, 0(k0)
-		SAVE_ALL
-		jal	ejtag_exception_handler
-		 move	a0, sp
-		RESTORE_ALL
-		la	k0, ejtag_debug_buffer
-		lw	k1, 0(k0)
-
-ejtag_return:
-		mfc0	k0, CP0_DESAVE
-		.word	0x4200001f     # DERET, return from EJTAG debug exception.
-		 nop
-		.set	at
-		END(ejtag_debug_handler)
-
-		/*
 		* NMI debug exception handler for MIPS reference boards.
 		* The NMI debug exception entry point is 0xbfc00000, which
 		* normally is in the boot PROM, so the boot PROM must do a
@@ -130,19 +102,6 @@
 		 nop
 		END(except_vec_nmi)
 
-		NESTED(nmi_handler, PT_SIZE, sp)
-		.set    noat
-		.set    noreorder
-		.set    mips3
-		SAVE_ALL
-		jal     nmi_exception_handler
-		 move   a0, sp
-		RESTORE_ALL
-		eret
-		.set    at
-		.set    mips0
-		END(nmi_handler)
-
 		/*
 		 * Kernel entry point
 		 */
@@ -199,10 +158,52 @@
 		__FINIT
 
 		/*
+		 * EJTAG debug exception handler.
+		 */
+		NESTED(ejtag_debug_handler, PT_SIZE, sp)
+		.set	noat
+		.set	noreorder
+		mtc0	k0, CP0_DESAVE
+		mfc0	k0, CP0_DEBUG
+
+		sll	k0, k0, 30	# Check for SDBBP.
+		bgez	k0, ejtag_return
+
+		la	k0, ejtag_debug_buffer
+		sw	k1, 0(k0)
+		SAVE_ALL
+		jal	ejtag_exception_handler
+		 move	a0, sp
+		RESTORE_ALL
+		la	k0, ejtag_debug_buffer
+		lw	k1, 0(k0)
+
+ejtag_return:
+		mfc0	k0, CP0_DESAVE
+		.word	0x4200001f     # DERET, return from EJTAG debug exception.
+		 nop
+		.set	at
+		END(ejtag_debug_handler)
+
+		NESTED(nmi_handler, PT_SIZE, sp)
+		.set    noat
+		.set    noreorder
+		.set    mips3
+		SAVE_ALL
+		jal     nmi_exception_handler
+		 move   a0, sp
+		RESTORE_ALL
+		eret
+		.set    at
+		.set    mips0
+		END(nmi_handler)
+		
+		/*
 		 * This buffer is reserved for the use of the EJTAG debug
 		 * handler.
 		 */
 		.data
+		.align 2
 		EXPORT(ejtag_debug_buffer)
 		.fill	4
 
Index: arch/mips64/kernel/r4k_genex.S
===================================================================
RCS file: /home/cvs/linux/arch/mips64/kernel/r4k_genex.S,v
retrieving revision 1.7.2.8
diff -u -r1.7.2.8 r4k_genex.S
--- arch/mips64/kernel/r4k_genex.S	2 Oct 2002 14:45:46 -0000	1.7.2.8
+++ arch/mips64/kernel/r4k_genex.S	5 Dec 2002 13:32:25 -0000
@@ -121,4 +121,72 @@
 1:	j	1b			/* Dummy, will be replaced */
 END(except_vec4)
 
+/*
+ * EJTAG debug exception handler.
+ * The EJTAG debug exception entry point is 0xbfc00480, which
+ * normally is in the boot PROM, so the boot PROM must do a
+ * unconditional jump to this vector.
+ */	
+NESTED(except_vec_ejtag_debug, 0, sp)
+	j	ejtag_debug_handler
+	 nop
+END(except_vec_ejtag_debug)
+
+/*
+ * NMI debug exception handler for MIPS reference boards.
+ * The NMI debug exception entry point is 0xbfc00000, which
+ * normally is in the boot PROM, so the boot PROM must do a
+ * unconditional jump to this vector.
+ */
+NESTED(except_vec_nmi, 0, sp)
+	j       nmi_handler
+	 nop
+END(except_vec_nmi)
+	
 	__FINIT
+
+/*
+ * EJTAG debug exception handler.
+ */
+NESTED(ejtag_debug_handler, PT_SIZE, sp)
+	.set	noat
+	.set	noreorder
+	dmtc0	k0, CP0_DESAVE
+	mfc0	k0, CP0_DEBUG	
+
+	sll	k0, k0, 30	# Check for SDBBP.
+	bgez	k0, ejtag_return
+
+	dla	k0, ejtag_debug_buffer
+	sd	k1, 0(k0)
+	SAVE_ALL
+	jal	ejtag_exception_handler
+	 move	a0, sp
+	RESTORE_ALL
+	dla	k0, ejtag_debug_buffer
+	ld	k1, 0(k0)	
+
+ejtag_return:
+	mfc0	k0, CP0_DESAVE	
+	.word	0x4200001f     # DERET, return from EJTAG debug exception.
+	 nop
+	.set	at
+END(ejtag_debug_handler)
+	
+NESTED(nmi_handler, PT_SIZE, sp)
+	.set    noat
+	.set    noreorder
+	SAVE_ALL
+	jal     nmi_exception_handler
+	 move   a0, sp
+	.set    at
+END(nmi_handler)		
+		
+/*
+ * This buffer is reserved for the use of the EJTAG debug 
+ * handler.
+ */
+	.data
+	.align 3
+	EXPORT(ejtag_debug_buffer)
+	.fill	8
\ No newline at end of file
Index: arch/mips64/kernel/traps.c
===================================================================
RCS file: /home/cvs/linux/arch/mips64/kernel/traps.c,v
retrieving revision 1.30.2.37
diff -u -r1.30.2.37 traps.c
--- arch/mips64/kernel/traps.c	2 Dec 2002 00:24:52 -0000	1.30.2.37
+++ arch/mips64/kernel/traps.c	5 Dec 2002 13:32:25 -0000
@@ -638,6 +638,46 @@
 	}
 }
 
+/*
+ * SDBBP EJTAG debug exception handler.
+ * We skip the instruction and return to the next instruction.
+ */
+void ejtag_exception_handler(struct pt_regs *regs)
+{
+        unsigned long depc, old_epc;
+	unsigned int debug;
+
+        printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
+	depc = read_c0_depc();
+        debug = read_c0_debug();
+        printk("DEPC = %p, DEBUG = %08x\n", depc, debug); 
+        if (debug & 0x80000000) {
+                /* 
+                 * In branch delay slot.
+                 * We cheat a little bit here and use EPC to calculate the
+                 * debug return address (DEPC). EPC is restored after the
+                 * calculation.
+                 */
+                old_epc = regs->cp0_epc;
+                regs->cp0_epc = depc;
+                __compute_return_epc(regs);
+                depc = regs->cp0_epc;
+                regs->cp0_epc = old_epc;
+        } else
+                depc += 4;
+	write_c0_depc(depc);
+}
+
+/*
+ * NMI exception handler.
+ */
+void nmi_exception_handler(struct pt_regs *regs)
+{
+	printk("NMI taken: ERROREPC = %p\n", read_c0_errorepc());
+        die("NMI", regs);
+        while(1) ;  /* We die here. */
+}
+
 unsigned long exception_handlers[32];
 
 /*
@@ -702,6 +742,8 @@
 	extern char except_vec0_generic, except_vec2_generic;
 	extern char except_vec3_generic, except_vec3_r4000;
 	extern char except_vec4;
+	extern char except_vec_ejtag_debug;
+	extern char except_vec_nmi;
 	unsigned long i;
 
 	per_cpu_trap_init();
@@ -716,6 +758,19 @@
 	 */
 	for (i = 0; i <= 31; i++)
 		set_except_vector(i, handle_reserved);
+
+	/* 
+	 * Copy the EJTAG debug exception vector handler code to it's final 
+	 * destination.
+	 */
+	if (mips_cpu.options & MIPS_CPU_EJTAG)
+		memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80);
+
+	/* 
+         * Copy the NMI exception vector handler code to it's final 
+         * destination.
+         */
+        memcpy((void *)(KSEG0 + 0x380), &except_vec_nmi, 0x80);
 
 	/*
 	 * Only some CPUs have the watch exceptions or a dedicated

--------------E0EED89142D881527C0D666A--


From macro@ds2.pg.gda.pl Thu Dec  5 14:47:49 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Reply-To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Carsten Langgaard <carstenl@mips.com>
cc: Ralf Baechle <ralf@linux-mips.org>,
	"Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org
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On Thu, 5 Dec 2002, Carsten Langgaard wrote:

> > Everybody satisfied?
> 
> Not quite, I afraid.
> I would like to be able to compile a 64-bit kernel, using the
> MIPS32/MIPS64 config1 register, but I don't have a MIPS64 compliant n64
> compiler (assembler). So I need the hardcoded ".word" opcode version, we
> previously had.

 Please upgrade/patch your tools.  If you can't, then this qualifies for a
privately maintained patch perfectly. 

 Support for MIPS32/MIPS64 was added to binutils two years ago.  Version
2.11 suffices. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From carstenl@mips.com Thu Dec  5 15:12:47 2002
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"Maciej W. Rozycki" wrote:

> On Thu, 5 Dec 2002, Carsten Langgaard wrote:
>
> > > Everybody satisfied?
> >
> > Not quite, I afraid.
> > I would like to be able to compile a 64-bit kernel, using the
> > MIPS32/MIPS64 config1 register, but I don't have a MIPS64 compliant n64
> > compiler (assembler). So I need the hardcoded ".word" opcode version, we
> > previously had.
>
>  Please upgrade/patch your tools.  If you can't, then this qualifies for a
> privately maintained patch perfectly.

I can live with that, already done.


>
>  Support for MIPS32/MIPS64 was added to binutils two years ago.  Version
> 2.11 suffices.
>

I just checked the FTP server for a new version
(ftp://ftp.linux-mips.org/pub/linux/mips/crossdev/i386-linux/), and someone
actually provided a
new set of binutils. It's less than a month ago (Nov 12), it was put there.
But if that works you won't hear more about it from my side ;-)

Thanks.
/Carsten



>
> --
> +  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
> +--------------------------------------------------------------+
> +        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

--
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|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
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From ralf@linux-mips.org Thu Dec  5 15:27:34 2002
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On Thu, Dec 05, 2002 at 03:12:00PM +0100, Carsten Langgaard wrote:

> >  Support for MIPS32/MIPS64 was added to binutils two years ago.  Version
> > 2.11 suffices.
> >
> 
> I just checked the FTP server for a new version
> (ftp://ftp.linux-mips.org/pub/linux/mips/crossdev/i386-linux/), and someone
> actually provided a
> new set of binutils. It's less than a month ago (Nov 12), it was put there.
> But if that works you won't hear more about it from my side ;-)

Excellent :-)

  Ralf

From carstenl@mips.com Thu Dec  5 16:14:45 2002
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Date: Thu, 05 Dec 2002 16:14:21 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: Dominic Sweetman <dom@algor.co.uk>
CC: Ralf Baechle <ralf@uni-koblenz.de>, linux-mips@linux-mips.org,
	dom@mips.com, chris@mips.com, kevink@mips.com
Subject: Re: Prefetches in memcpy
References: <3DC7CB8B.E2C1D4E5@mips.com>
		<20021105163806.A24996@bacchus.dhis.org>
		<3DEE19EC.DD007304@mips.com> <15855.7458.19248.593085@arsenal.algor.co.uk>
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Here's what I think we should do for now (attached patch).

/Carsten


Dominic Sweetman wrote:

> Carsten,
>
> > I think we should get rid of the prefetches until someone comes up with a
> > version that doesn't prefetch beyond the copy destination/source area.
>
> I agree.
>
> --
> Dominic

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
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--------------534F69F3F58268A8B4810BE7
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 name="memcpy.patch"
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 filename="memcpy.patch"

Index: arch/mips/lib/memcpy.S
===================================================================
RCS file: /home/cvs/linux/arch/mips/lib/memcpy.S,v
retrieving revision 1.6.2.4
diff -u -r1.6.2.4 memcpy.S
--- arch/mips/lib/memcpy.S	19 Sep 2002 14:01:24 -0000	1.6.2.4
+++ arch/mips/lib/memcpy.S	5 Dec 2002 15:06:58 -0000
@@ -21,6 +21,17 @@
 #define src a1
 #define len a2
 
+/* 
+ * There is spread a number of PREF instructions in the memcpy function, but 
+ * there is no check if we are prefetching out-side the "memcpy" areas. 
+ * This is extremely dangerous because we might prefetch out-side the physical
+ * memory area causing e.g. a bus error or something even more nasty. 
+ * It could also hit a DMA buffer region, and there by break the PCI DMA 
+ * flushing scheme.
+ * So for now, we simply get rid of the PREFs here.
+ */
+#define PREF(hint,addr)
+	
 /*
  * Spec
  *
Index: arch/mips64/lib/memcpy.S
===================================================================
RCS file: /home/cvs/linux/arch/mips64/lib/memcpy.S,v
retrieving revision 1.9.2.3
diff -u -r1.9.2.3 memcpy.S
--- arch/mips64/lib/memcpy.S	19 Sep 2002 14:01:24 -0000	1.9.2.3
+++ arch/mips64/lib/memcpy.S	5 Dec 2002 15:06:59 -0000
@@ -21,6 +21,17 @@
 #define src a1
 #define len a2
 
+/* 
+ * There is spread a number of PREF instructions in the memcpy function, but 
+ * there is no check if we are prefetching out-side the "memcpy" areas. 
+ * This is extremely dangerous because we might prefetch out-side the physical
+ * memory area causing e.g. a bus error or something even more nasty. 
+ * It could also hit a DMA buffer region, and there by break the PCI DMA 
+ * flushing scheme.
+ * So for now, we simply get rid of the PREFs here.
+ */
+#define PREF(hint,addr)
+	
 /*
  * Spec
  *

--------------534F69F3F58268A8B4810BE7--


From carstenl@mips.com Thu Dec  5 16:28:24 2002
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Date: Thu, 05 Dec 2002 16:28:07 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@linux-mips.org>,
	Dominic Sweetman <dom@algor.co.uk>, chris@mips.com,
	kevink@mips.com, linux-mips@linux-mips.org
Subject: The 64-bit version of __access_ok is broken.
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I have addressed this issue before, and I do it again, because we have a
potential kernel crash situation, if this isn't fixed.

The __access_ok macro in include/asm-mips64/uaccess.h and the check_axs
macro in arch/mips64/kernel/unaligned.c need to be changed in order to
work correctly, it's a copy from the 32-bit kernel. It's not good enough
to simply check for the "sign bit" of the address.
The area between USEG (XUSEG) and KSEG0 will in 64-bit addressing mode
generate an address error, if accessed.
The size of the area depend on the number of virtual addressing bits
implemented in the CPU.

Please take a look at the patch below.
I think Ralf had some objection the last time I send it, about the fix,
not being efficient enough (performance vice), but I think we need to
consider stability and functionality over performance. So until someone
comes up with a better solution, I think we need this fix.

/Carsten




--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



--------------ED3149EB9F1B0424A5270285
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 filename="access_ok.patch"

Index: arch/mips64/kernel/unaligned.c
===================================================================
RCS file: /home/cvs/linux/arch/mips64/kernel/unaligned.c,v
retrieving revision 1.6.2.7
diff -u -r1.6.2.7 unaligned.c
--- arch/mips64/kernel/unaligned.c	5 Dec 2002 03:09:58 -0000	1.6.2.7
+++ arch/mips64/kernel/unaligned.c	5 Dec 2002 15:06:59 -0000
@@ -89,11 +89,14 @@
 #define __STR(x)  #x
 
 /*
- * User code may only access USEG; kernel code may access the
- * entire address space.
+ * User code may only access USEG; 
+ * Kernel code may access the entire address space, except the area between
+ * USEG (XUSEG) and KSEG0.
  */
-#define check_axs(pc,a,s)				\
-	if ((long)(~(pc) & ((a) | ((a)+(s)))) < 0)	\
+#define check_axs(pc,a,s)						\
+        if (((pc < KUSIZE) && (((a) | ((a)+(s))) >= KUSIZE)) ||		\
+	    ((((a) | ((a)+(s))) < K0BASE) &&				\
+	     (((a) | ((a)+(s))) >= KUSIZE)))				\
 		goto sigbus;
 
 static inline int emulate_load_store_insn(struct pt_regs *regs,
Index: include/asm-mips64/uaccess.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips64/uaccess.h,v
retrieving revision 1.13.2.1
diff -u -r1.13.2.1 uaccess.h
--- include/asm-mips64/uaccess.h	1 Jul 2002 15:27:31 -0000	1.13.2.1
+++ include/asm-mips64/uaccess.h	5 Dec 2002 15:07:11 -0000
@@ -40,16 +40,23 @@
  * than tests.
  *
  * Address valid if:
- *  - "addr" doesn't have any high-bits set
- *  - AND "size" doesn't have any high-bits set
- *  - AND "addr+size" doesn't have any high-bits set
- *  - OR we are in kernel mode.
+ *  - In user mode and "addr" and "addr+size" in USEG (or XUSEG).
+ *  - OR we are in kernel mode and "addr" and "addr+size" isn't in the 
+ *    area between USEG (XUSEG) and KSEG0.
  */
 #define __ua_size(size)							\
 	(__builtin_constant_p(size) && (signed long) (size) > 0 ? 0 : (size))
 
-#define __access_ok(addr,size,mask)					\
-	(((signed long)((mask)&(addr | (addr + size) | __ua_size(size)))) >= 0)
+static inline int 
+__access_ok(unsigned long addr, unsigned long size, long mask)
+{
+	if (((mask) && ((addr | (addr+size)) >= KUSIZE)) ||     
+	    (((addr | (addr+size)) < K0BASE) &&
+	     ((addr | (addr+size)) >= KUSIZE)))
+		return 0;
+	else
+		return 1;
+}
 
 #define __access_mask ((long)(get_fs().seg))

--------------ED3149EB9F1B0424A5270285--


From kevink@mips.com Thu Dec  5 16:36:01 2002
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To: "Guido Guenther" <agx@sigxcpu.org>, <linux-mips@linux-mips.org>
References: <011001c29c51$c76d5370$10eca8c0@grendel> <Pine.GSO.4.21.0212051307590.7346-100000@vervain.sonytel.be> <20021205124548.GK18549@bogon.ms20.nix>
Subject: Re: Old SGI penguin logo
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> On Thu, Dec 05, 2002 at 01:10:09PM +0100, Geert Uytterhoeven wrote:
> > On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> [..snip..] 
> > > Given that we're working on a port to MIPS, not 
> > > SGI, wouldn't it be more appropriate?
> > 
> > Yes, if some talented person can create a nice penguin/mips logo, that would be
> > nice.
> Can we keep the SGI logo for the SGI IP22, IP27 & IP32 subarchitectures?
>  -- Guido

I would hope so - and I'd hope that the DECstation guys can keep
their DEC logos if they like - but I've found it irksome for a long time
that whenever I boot my Malta with a graphics head, I get an SGI
logo...

            Kevin K.

From Geert.Uytterhoeven@sonycom.com Thu Dec  5 16:43:55 2002
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From: Geert Uytterhoeven <geert@linux-m68k.org>
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	Linux/MIPS Development <linux-mips@linux-mips.org>
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On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > On Thu, Dec 05, 2002 at 01:10:09PM +0100, Geert Uytterhoeven wrote:
> > > On Thu, 5 Dec 2002, Kevin D. Kissell wrote:
> > [..snip..] 
> > > > Given that we're working on a port to MIPS, not 
> > > > SGI, wouldn't it be more appropriate?
> > > 
> > > Yes, if some talented person can create a nice penguin/mips logo, that would be
> > > nice.
> > Can we keep the SGI logo for the SGI IP22, IP27 & IP32 subarchitectures?
> >  -- Guido
> 
> I would hope so - and I'd hope that the DECstation guys can keep
> their DEC logos if they like - but I've found it irksome for a long time

Sure you can! All my patch did was replace the old SGI logo by the new logo,
which is also used on mips64.

> that whenever I boot my Malta with a graphics head, I get an SGI
> logo...

All it needs is someone with the GIMP, artistic talents, and my pnmtologo
program.

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


From macro@ds2.pg.gda.pl Thu Dec  5 16:47:32 2002
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To: Carsten Langgaard <carstenl@mips.com>
cc: Dominic Sweetman <dom@algor.co.uk>,
	Ralf Baechle <ralf@uni-koblenz.de>, linux-mips@linux-mips.org,
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Subject: Re: Prefetches in memcpy
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On Thu, 5 Dec 2002, Carsten Langgaard wrote:

> Here's what I think we should do for now (attached patch).

 Obviously you want to #undef them first...

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From Geert.Uytterhoeven@sonycom.com Thu Dec  5 16:47:51 2002
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To: Ralf Baechle <ralf@linux-mips.org>
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Subject: [PATCH] Embedded ramdisks
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The embedded ramdisk support allows to embed an arbitrary file in the image,
but the dependency in the Makefile still contains the hardcoded name
`ramdisk.gz'. This patch changes the dependency so it matches the selected file
name during kernel configuration.

The sed magic is needed because the kernel configuration embeds the filename in
double quotes.

--- linux-mips-2.4.x/arch/mips/ramdisk/Makefile	Fri Oct 25 13:37:30 2002
+++ geert-mips-2.4.x/arch/mips/ramdisk/Makefile	Thu Dec  5 11:53:14 2002
@@ -8,7 +8,7 @@
 
 O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
 img = $(CONFIG_EMBEDDED_RAMDISK_IMAGE)
-ramdisk.o: ramdisk.gz ld.script
+ramdisk.o: $(shell echo $(img) | sed -e 's/"//g') ld.script
 	echo "O_FORMAT:  " $(O_FORMAT)
 	$(LD) -T ld.script -b binary --oformat $(O_FORMAT) -o $@ $(img)
 

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


From macro@ds2.pg.gda.pl Thu Dec  5 16:54:10 2002
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Date: Thu, 5 Dec 2002 16:51:42 +0100 (MET)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Geert Uytterhoeven <geert@linux-m68k.org>
cc: "Kevin D. Kissell" <kevink@mips.com>,
	Guido Guenther <agx@sigxcpu.org>,
	Linux/MIPS Development <linux-mips@linux-mips.org>
Subject: Re: Old SGI penguin logo
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On Thu, 5 Dec 2002, Geert Uytterhoeven wrote:

> > I would hope so - and I'd hope that the DECstation guys can keep
> > their DEC logos if they like - but I've found it irksome for a long time
> 
> Sure you can! All my patch did was replace the old SGI logo by the new logo,
> which is also used on mips64.
> 
> > that whenever I boot my Malta with a graphics head, I get an SGI
> > logo...
> 
> All it needs is someone with the GIMP, artistic talents, and my pnmtologo
> program.

 And until then the generic logo can actually be used. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From Geert.Uytterhoeven@sonycom.com Thu Dec  5 17:44:18 2002
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Date: Thu, 5 Dec 2002 17:42:01 +0100 (MET)
From: Geert Uytterhoeven <geert@linux-m68k.org>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
cc: "Kevin D. Kissell" <kevink@mips.com>,
	Guido Guenther <agx@sigxcpu.org>,
	Linux/MIPS Development <linux-mips@linux-mips.org>
Subject: Re: Old SGI penguin logo
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On Thu, 5 Dec 2002, Maciej W. Rozycki wrote:
> On Thu, 5 Dec 2002, Geert Uytterhoeven wrote:
> > > I would hope so - and I'd hope that the DECstation guys can keep
> > > their DEC logos if they like - but I've found it irksome for a long time
> > 
> > Sure you can! All my patch did was replace the old SGI logo by the new logo,
> > which is also used on mips64.
> > 
> > > that whenever I boot my Malta with a graphics head, I get an SGI
> > > logo...
> > 
> > All it needs is someone with the GIMP, artistic talents, and my pnmtologo
> > program.
> 
>  And until then the generic logo can actually be used. 

OK, here's a new (this time untested) patch:
  - Kill the old SGI logo on mips
  - Use the SGI logo for SGI machines only, both on mips and mips64
    (I moved the SGI logo on mips64 to linux_logo_sgi.h, cfr. on mips)
  - Use the DEC logo for DECstations
  - Use the generic logo for other machines

A MIPS-specific logo can be added later.

--- linux-mips/include/asm-mips/linux_logo.h	5 Aug 2002 23:53:37 -0000	1.6.2.1
+++ linux-mips/include/asm-mips/linux_logo.h	5 Dec 2002 16:21:28 -0000
@@ -22,22 +22,13 @@
 #include <linux/version.h>
 #include <linux/config.h>
 
-#ifndef CONFIG_DECSTATION
-#	include <asm/linux_logo_sgi.h>
+#if defined(CONFIG_DECSTATION)
+#include <asm/linux_logo_dec.h>
+#elif defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP32)
+#include <asm/linux_logo_sgi.h>
 #else
-#	include <asm/linux_logo_dec.h>
+#define linux_logo_banner "Linux/MIPS version " UTS_RELEASE
 #endif
 
-#ifndef INCLUDE_LINUX_LOGO_DATA
-/* prototypes only */
-extern unsigned char linux_logo_red[];
-extern unsigned char linux_logo_green[];
-extern unsigned char linux_logo_blue[];
-extern unsigned char linux_logo[];
-extern unsigned char linux_logo_bw[];
-extern unsigned char linux_logo16_red[];
-extern unsigned char linux_logo16_green[];
-extern unsigned char linux_logo16_blue[];
-extern unsigned char linux_logo16[];
+#include <linux/linux_logo.h>
 
-#endif
--- linux-mips/include/asm-mips/linux_logo_dec.h	5 Aug 2002 23:53:37 -0000	1.2.2.2
+++ linux-mips/include/asm-mips/linux_logo_dec.h	5 Dec 2002 16:21:29 -0000
@@ -9,15 +9,14 @@
  *
  */
 
-#include <linux/init.h>
-#include <linux/version.h>
-
 #define linux_logo_banner "Linux/MIPSel version " UTS_RELEASE
-#define LINUX_LOGO_COLORS 183
 
 #define __HAVE_ARCH_LINUX_LOGO
 
+#define LINUX_LOGO_COLORS 183
+
 #ifdef INCLUDE_LINUX_LOGO_DATA
+
 unsigned char linux_logo_red[] __initdata = {
     0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
     0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
@@ -899,8 +898,5 @@
     0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
 };
 
-#define INCLUDE_LINUX_LOGOBW
-#define INCLUDE_LINUX_LOGO16
-#include <linux/linux_logo.h>
+#endif /* INCLUDE_LINUX_LOGO_DATA */
 
-#endif
--- linux-mips/include/asm-mips/linux_logo_sgi.h	29 May 2002 03:03:18 -0000	1.2.2.1
+++ linux-mips/include/asm-mips/linux_logo_sgi.h	5 Dec 2002 16:21:30 -0000
@@ -8,910 +8,897 @@
  * Copyright (C) 2001 Jan-Benedict Glaw <jbglaw@lug-owl.de>
  *
  */
-#include <linux/init.h>
-#include <linux/version.h>
 
 #define linux_logo_banner "Linux/MIPS version " UTS_RELEASE
-#define LINUX_LOGO_COLORS 212
 
 #define __HAVE_ARCH_LINUX_LOGO
 
+#define LINUX_LOGO_COLORS	187
+
 #ifdef INCLUDE_LINUX_LOGO_DATA
+
 unsigned char linux_logo_red[] __initdata = {
-  0x03, 0x82, 0xE9, 0xBF, 0x42, 0xC9, 0x7E, 0xC0,
-  0xE9, 0xE3, 0xC2, 0x24, 0xA4, 0x65, 0xEC, 0xC4,
-  0x82, 0x9F, 0xF3, 0x12, 0x5F, 0xA0, 0xC2, 0xED,
-  0x3E, 0xD5, 0xDB, 0xA0, 0x1C, 0xF4, 0xEB, 0xA4,
-  0xCD, 0x0A, 0x9A, 0x51, 0xCC, 0xBE, 0xC0, 0xBA,
-  0x74, 0xDC, 0xAA, 0xF6, 0xD3, 0xC5, 0xE6, 0x26,
-  0xC2, 0x83, 0x38, 0xEA, 0x49, 0xB0, 0xED, 0xE5,
-  0xF4, 0x96, 0x96, 0x1B, 0xFA, 0xCC, 0xF2, 0x0F,
-  0xCD, 0xE5, 0xF4, 0xD3, 0x50, 0x7A, 0xB5, 0xDE,
-  0xD5, 0xB6, 0x60, 0x0A, 0x6A, 0xEA, 0xD4, 0xEB,
-  0xC1, 0xCA, 0xEA, 0xEC, 0x2A, 0x96, 0x95, 0xDC,
-  0xE4, 0xCE, 0xEC, 0x1E, 0xDC, 0x8A, 0xD1, 0xF6,
-  0x3C, 0x5E, 0xC6, 0xB4, 0xB2, 0xAC, 0xBA, 0x9E,
-  0x0F, 0x59, 0xBA, 0xFA, 0xCC, 0xBF, 0x82, 0xCE,
-  0xE6, 0x4F, 0xAA, 0x4C, 0xCA, 0x8E, 0x8E, 0xDF,
-  0x2C, 0xB6, 0x3B, 0xDE, 0xCE, 0xEE, 0x46, 0x4A,
-  0x6F, 0x7A, 0x82, 0xE4, 0xAA, 0x88, 0xE2, 0xCE,
-  0xAE, 0xB6, 0x70, 0xC2, 0x9A, 0xDA, 0x35, 0x9E,
-  0x95, 0xC0, 0x7E, 0x8C, 0xC2, 0xB6, 0xCE, 0xB9,
-  0xD5, 0xAA, 0xC1, 0xF4, 0xC7, 0xB6, 0xB6, 0xA3,
-  0xF2, 0x68, 0xDB, 0x76, 0xDC, 0x57, 0xD3, 0xA8,
-  0xC0, 0xEF, 0x46, 0xF4, 0x2F, 0xD7, 0x53, 0x36,
-  0xE6, 0xA7, 0xCA, 0xCB, 0x7E, 0xE4, 0x86, 0x9A,
-  0xCE, 0x94, 0xB4, 0x1D, 0xDA, 0xCE, 0x6C, 0xE6,
-  0x9E, 0xC6, 0xDA, 0x16, 0xFA, 0xAA, 0x56, 0xB6,
-  0xFE, 0x6E, 0xEA, 0xCE, 0xE5, 0xCC, 0xDB, 0xD3,
-  0xED, 0xDC, 0xF4, 0x72
+    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
+    0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
+    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x02, 0x65,
+    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
+    0xc3, 0x65, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
+    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
+    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x76, 0x79,
+    0x62, 0x36, 0x9a, 0xe2, 0xec, 0xe1, 0xb8, 0xd7,
+    0xaf, 0x25, 0xbc, 0xc0, 0xef, 0xea, 0xe8, 0xe8,
+    0xf5, 0xf1, 0xda, 0xd3, 0x79, 0xdb, 0xf4, 0xf6,
+    0xf6, 0xf6, 0xe2, 0x3d, 0xb4, 0xce, 0xe6, 0xee,
+    0xf6, 0x68, 0xd8, 0xec, 0xf5, 0xc6, 0xc8, 0x9c,
+    0x89, 0xd2, 0xee, 0xcb, 0xb9, 0xd2, 0x66, 0x5e,
+    0x8b, 0xbe, 0xa8, 0xd5, 0xca, 0xb6, 0xae, 0x9c,
+    0xc5, 0xbe, 0xbe, 0xca, 0x90, 0xb2, 0x9a, 0xa8,
+    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
+    0x12, 0x4a, 0x8e, 0xf2, 0xf6, 0xee, 0xb5, 0xe4,
+    0xf1, 0x26, 0x9a, 0xea, 0xf6, 0xe0, 0xd2, 0x16,
+    0x9a, 0x2e, 0x70, 0xd6, 0x46, 0x7c, 0xb4, 0x62,
+    0xd6, 0xa3, 0x74, 0xa7, 0xa2, 0xca, 0xe0, 0xae,
+    0xbe, 0xce, 0xa3, 0x8e, 0x6d, 0x8e, 0x32, 0xaf,
+    0x50, 0x9e, 0x5b, 0x8a, 0x98, 0x82, 0x7a, 0x82,
+    0x56, 0x7c, 0x8a, 0x56, 0x5e, 0x86, 0x6a, 0x52,
+    0x59, 0x64, 0x5e,
 };
 
 unsigned char linux_logo_green[] __initdata = {
-  0x03, 0x82, 0xC4, 0x83, 0x42, 0xA2, 0x4A, 0xA4,
-  0xE5, 0xA6, 0xC2, 0x24, 0xA4, 0x65, 0xB4, 0x94,
-  0x66, 0x87, 0xB6, 0x12, 0x44, 0x6C, 0x96, 0xD4,
-  0x36, 0x95, 0xB2, 0x92, 0x0E, 0xF4, 0xBC, 0x77,
-  0xA5, 0x0A, 0x92, 0x52, 0xB4, 0x9A, 0x8C, 0xB2,
-  0x74, 0xC2, 0x8E, 0xBD, 0xA2, 0xCA, 0xD2, 0x12,
-  0xB6, 0x61, 0x24, 0xDA, 0x33, 0x79, 0xCB, 0xAC,
-  0xDA, 0x84, 0x7A, 0x1B, 0xFA, 0x8D, 0xBE, 0x06,
-  0x93, 0xBB, 0xBC, 0xAB, 0x44, 0x62, 0x83, 0xDA,
-  0x9B, 0xA2, 0x4C, 0x04, 0x6A, 0xB6, 0xC8, 0xBD,
-  0x8D, 0xB6, 0xAD, 0xEC, 0x2A, 0x68, 0x62, 0x9D,
-  0xC4, 0xC4, 0xB4, 0x13, 0xA3, 0x8A, 0xD2, 0xD6,
-  0x3C, 0x5D, 0x8C, 0x7E, 0x82, 0xAC, 0x96, 0x7E,
-  0x0D, 0x5A, 0xBA, 0xBB, 0xCC, 0xBE, 0x76, 0xB6,
-  0xDE, 0x4E, 0x9A, 0x3C, 0xBE, 0x8E, 0x6E, 0xCB,
-  0x1C, 0xAA, 0x2E, 0xBE, 0xAA, 0xDE, 0x3E, 0x4B,
-  0x4D, 0x7A, 0x54, 0xE4, 0x8E, 0x6E, 0xCA, 0x9B,
-  0x70, 0x9E, 0x5A, 0xAA, 0x9A, 0xBE, 0x34, 0x9E,
-  0x71, 0x9E, 0x7E, 0x5F, 0xAA, 0x8A, 0xBE, 0x91,
-  0xCE, 0x88, 0x92, 0xDB, 0xC6, 0xAB, 0x8A, 0x72,
-  0xE2, 0x44, 0xC3, 0x54, 0xAA, 0x45, 0xBB, 0x92,
-  0xBA, 0xC4, 0x46, 0xCA, 0x2D, 0xD6, 0x3B, 0x1A,
-  0xC2, 0x7E, 0xA6, 0xCB, 0x7A, 0xDC, 0x86, 0x72,
-  0xB6, 0x94, 0xB4, 0x1C, 0xBC, 0xAE, 0x4C, 0xD6,
-  0x62, 0x86, 0xD3, 0x16, 0xF6, 0x7A, 0x55, 0x79,
-  0xFE, 0x6E, 0xC6, 0xC6, 0xAA, 0x93, 0xDC, 0x9D,
-  0xAE, 0xA4, 0xD4, 0x56
+    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
+    0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
+    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x02, 0x65,
+    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
+    0xc3, 0x62, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
+    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
+    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x62, 0x5c,
+    0x4e, 0x26, 0x72, 0xaa, 0xba, 0xaf, 0x90, 0xae,
+    0x92, 0x1a, 0xa4, 0x85, 0xb6, 0xbe, 0xc3, 0xc8,
+    0xcf, 0xd0, 0xc2, 0xce, 0x57, 0xa2, 0xd6, 0xda,
+    0xda, 0xd7, 0xb8, 0x2a, 0x7b, 0x91, 0xae, 0xca,
+    0xda, 0x45, 0x9e, 0xb2, 0xd7, 0x9b, 0x90, 0x76,
+    0x5c, 0xa2, 0xbe, 0xa6, 0x85, 0x96, 0x4e, 0x46,
+    0x66, 0x92, 0x7a, 0x9a, 0x96, 0x9d, 0x9a, 0x6b,
+    0x8a, 0x8e, 0xb2, 0xca, 0x90, 0xa6, 0x79, 0x7c,
+    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
+    0x0e, 0x36, 0x86, 0xba, 0xbe, 0xcc, 0x8e, 0xb8,
+    0xc4, 0x1e, 0x8e, 0xae, 0xba, 0xb2, 0xa6, 0x12,
+    0x7a, 0x20, 0x64, 0xaa, 0x2f, 0x70, 0x85, 0x46,
+    0xa6, 0x6e, 0x51, 0x72, 0x92, 0xa2, 0xa6, 0x87,
+    0x96, 0xa2, 0x85, 0x7a, 0x6a, 0x6e, 0x22, 0x76,
+    0x36, 0x76, 0x3c, 0x6e, 0x63, 0x53, 0x66, 0x62,
+    0x42, 0x50, 0x56, 0x42, 0x56, 0x56, 0x56, 0x3e,
+    0x51, 0x52, 0x56,
 };
 
 unsigned char linux_logo_blue[] __initdata = {
-  0x04, 0x84, 0x10, 0x0C, 0x41, 0x14, 0x04, 0x78,
-  0xC7, 0x0E, 0xC4, 0x24, 0xA4, 0x64, 0x0C, 0x0D,
-  0x17, 0x24, 0x0D, 0x13, 0x11, 0x07, 0x40, 0x22,
-  0x0C, 0x0C, 0x11, 0x78, 0x06, 0xF4, 0x0B, 0x0A,
-  0x47, 0x0B, 0x7C, 0x54, 0x6C, 0x0C, 0x0D, 0x9C,
-  0x73, 0x54, 0x14, 0x0C, 0x0F, 0xC7, 0x94, 0x04,
-  0x94, 0x17, 0x0A, 0x6C, 0x08, 0x0F, 0x14, 0x0B,
-  0x12, 0x68, 0x28, 0x11, 0xFA, 0x0A, 0x34, 0x09,
-  0x0A, 0x2F, 0x15, 0x19, 0x14, 0x3C, 0x06, 0xC4,
-  0x0B, 0x84, 0x24, 0x08, 0x69, 0x38, 0xBC, 0x15,
-  0x1F, 0xA0, 0x0A, 0xEC, 0x2A, 0x0C, 0x0C, 0x0C,
-  0x2C, 0xA0, 0x15, 0x07, 0x0B, 0x8C, 0xD3, 0x10,
-  0x3B, 0x5C, 0x0C, 0x04, 0x3C, 0xAC, 0x54, 0x1C,
-  0x0B, 0x5B, 0xBB, 0x0A, 0xC1, 0xBB, 0x5C, 0x3C,
-  0xBC, 0x4D, 0x74, 0x10, 0x8C, 0x8C, 0x14, 0x91,
-  0x0C, 0x74, 0x17, 0x0C, 0x48, 0x9C, 0x3C, 0x4C,
-  0x09, 0x7C, 0x05, 0xE4, 0x34, 0x38, 0x6C, 0x11,
-  0x08, 0x7C, 0x18, 0x2C, 0x9C, 0x4C, 0x34, 0x9C,
-  0x29, 0x54, 0x7C, 0x0C, 0x78, 0x18, 0x9C, 0x14,
-  0xBA, 0x30, 0x27, 0x31, 0xC2, 0x97, 0x24, 0x09,
-  0xB4, 0x04, 0x87, 0x0C, 0x14, 0x1F, 0x7C, 0x64,
-  0xB0, 0x0F, 0x45, 0x10, 0x2C, 0xD4, 0x0A, 0x04,
-  0x44, 0x1F, 0x2C, 0xCC, 0x7C, 0xD8, 0x84, 0x0C,
-  0x8C, 0x94, 0xB4, 0x1D, 0x20, 0x5C, 0x18, 0xB4,
-  0x04, 0x09, 0xBC, 0x14, 0xF4, 0x08, 0x54, 0x07,
-  0xFC, 0x6C, 0x24, 0xB4, 0x15, 0x18, 0xDB, 0x17,
-  0x17, 0x18, 0x21, 0x24
+    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
+    0x12, 0x01, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
+    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x06, 0x65,
+    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
+    0xc3, 0x59, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
+    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
+    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x2e, 0x08,
+    0x0a, 0x06, 0x0a, 0x0b, 0x0b, 0x0f, 0x0c, 0x0f,
+    0x3d, 0x09, 0x73, 0x09, 0x0d, 0x0a, 0x10, 0x1e,
+    0x2d, 0x13, 0x86, 0xba, 0x19, 0x0a, 0x36, 0x3c,
+    0x26, 0x14, 0x0d, 0x06, 0x07, 0x0a, 0x0b, 0x0f,
+    0x4a, 0x06, 0x0a, 0x0c, 0x2b, 0x0a, 0x0b, 0x0a,
+    0x06, 0x0a, 0x0a, 0x11, 0x0b, 0x0a, 0x0a, 0x1e,
+    0x0f, 0x0d, 0x0a, 0x0b, 0x22, 0x6a, 0x72, 0x0b,
+    0x0b, 0x22, 0x90, 0xca, 0x90, 0x92, 0x3c, 0x2c,
+    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
+    0x06, 0x0e, 0x6a, 0x0e, 0x0e, 0x5b, 0x2c, 0x3e,
+    0x0e, 0x0a, 0x5a, 0x0d, 0x0e, 0x3e, 0x0a, 0x06,
+    0x2e, 0x06, 0x4e, 0x36, 0x06, 0x58, 0x24, 0x06,
+    0x3a, 0x08, 0x08, 0x07, 0x5e, 0x45, 0x0a, 0x32,
+    0x2e, 0x2a, 0x43, 0x48, 0x5f, 0x2e, 0x06, 0x06,
+    0x07, 0x24, 0x06, 0x32, 0x06, 0x06, 0x46, 0x2e,
+    0x22, 0x06, 0x06, 0x1e, 0x4c, 0x06, 0x3a, 0x22,
+    0x42, 0x34, 0x42,
 };
 
 unsigned char linux_logo[] __initdata = {
-  0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF,
-  0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA, 0xDA, 0x2C,
-  0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A, 0x8A, 0xDA,
-  0x85, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0xD9, 0xD9,
-  0xAF, 0x85, 0x85, 0x85, 0x8D, 0xBC, 0x2A, 0x2A,
-  0xBC, 0x8C, 0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85,
-  0x2C, 0x2C, 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
-  0x2C, 0xAF, 0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA,
-  0xDA, 0x2C, 0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A,
-  0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D,
-  0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
-  0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA, 0x85, 0x2C,
-  0x2C, 0xAC, 0xD9, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C,
-  0x2C, 0x85, 0x2C, 0x2C, 0x85, 0xDA, 0xDA, 0xDA,
-  0xDA, 0xDA, 0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C,
-  0x2C, 0xAC, 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC,
-  0xD9, 0x7D, 0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA,
-  0x85, 0x2C, 0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA,
-  0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF,
-  0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0x7D,
-  0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
-  0xAF, 0x2C, 0x2C, 0xDA, 0x85, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xD9, 0xAF, 0xDA, 0x85, 0x2C, 0x2C,
-  0x85, 0xDA, 0xDA, 0x85, 0x85, 0xDA, 0x85, 0x85,
-  0x85, 0xAF, 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85,
-  0x2C, 0xAF, 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9,
-  0xD9, 0x7D, 0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA,
-  0x85, 0x2C, 0xAF, 0x2C, 0x2C, 0xDA, 0xDA, 0x85,
-  0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAF,
-  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0x95,
-  0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA, 0x85, 0x2C,
-  0xAC, 0xAC, 0x2C, 0x2C, 0x85, 0x2C, 0x2C, 0xAC,
-  0xD9, 0xD9, 0x2C, 0x91, 0x41, 0x20, 0x6B, 0x20,
-  0x6B, 0x20, 0x6B, 0xAE, 0x2C, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA,
-  0x85, 0xAF, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
-  0x95, 0x95, 0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA,
-  0x85, 0x2C, 0xAC, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA, 0x85, 0x2C,
-  0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0xD9,
-  0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xAF, 0xAC,
-  0x2C, 0xB2, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x6B, 0x80, 0x85, 0x2C,
-  0xD9, 0xD6, 0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA,
-  0x85, 0x2C, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9,
-  0xD9, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85,
-  0x2C, 0xD9, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF,
-  0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA, 0x2C, 0xAC,
-  0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0xAF, 0x2C,
-  0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xAC, 0xD9,
-  0xD9, 0xD9, 0xAF, 0xAF, 0x2C, 0x2C, 0xAF, 0xDA,
-  0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xE3, 0x20, 0x6B, 0x48,
-  0xAC, 0x95, 0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA,
-  0x2C, 0xAC, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
-  0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C,
-  0xAC, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0xAF,
-  0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9,
-  0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
-  0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0xAF, 0xAC,
-  0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x89,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x74, 0x43, 0x80, 0x41, 0x20,
-  0x9F, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85,
-  0x2C, 0xD9, 0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C,
-  0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF,
-  0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xD9,
-  0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C, 0x85, 0x85,
-  0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC,
-  0xAF, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x41,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xAE, 0x48, 0x89, 0x74, 0x41,
-  0x6B, 0xD6, 0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85,
-  0x2C, 0xD9, 0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C,
-  0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF,
-  0xAF, 0xAC, 0xAF, 0xAC, 0xAC, 0x2C, 0xAF, 0xAC,
-  0x2C, 0x7D, 0xD9, 0x2C, 0xDA, 0x85, 0x2C, 0x7D,
-  0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0x85,
-  0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0xD9,
-  0x95, 0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x48, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x6B, 0xAE, 0xE6, 0x80, 0x2B, 0x88,
-  0x20, 0x33, 0xDA, 0x95, 0xD9, 0x2C, 0xDA, 0x85,
-  0x2C, 0x7D, 0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85,
-  0x85, 0x85, 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC,
-  0xAC, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9,
-  0x85, 0xD9, 0x2C, 0x85, 0xDA, 0xDA, 0xD9, 0x21,
-  0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, 0x85, 0xAF,
-  0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, 0x7D, 0xD6,
-  0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0x85, 0xDB, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xDB, 0xE3, 0x6B, 0x20, 0x20,
-  0x20, 0x20, 0xE9, 0xD9, 0x2C, 0x85, 0xDA, 0xDA,
-  0xD9, 0x21, 0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA,
-  0x85, 0xAF, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9,
-  0x7D, 0xD6, 0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0xD9,
-  0xDA, 0x2C, 0x85, 0xDA, 0xDA, 0x85, 0x95, 0x21,
-  0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xD9,
-  0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xAC, 0xAC, 0x2C, 0xAF, 0x2C, 0x85, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x88, 0xDA, 0x85, 0xDA, 0xDA, 0x85,
-  0x95, 0x21, 0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C,
-  0x2C, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9,
-  0xD9, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C,
-  0xDA, 0x2C, 0x85, 0x85, 0x2C, 0xD9, 0xD6, 0xB2,
-  0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC, 0x95, 0x95,
-  0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0x2C, 0x85,
-  0x85, 0x85, 0x85, 0x85, 0x85, 0xAC, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xAC, 0x85, 0x85, 0x2C, 0xD9,
-  0xD6, 0xB2, 0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC,
-  0x95, 0x95, 0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
-  0x85, 0x2C, 0x2C, 0x2C, 0xAC, 0x95, 0xD6, 0x7D,
-  0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D, 0x7D, 0x95,
-  0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9, 0x2C, 0x85,
-  0xDA, 0xDA, 0xDA, 0x85, 0x85, 0x21, 0x20, 0x20,
-  0x6B, 0x41, 0xDB, 0x6B, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xDB, 0xDB, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0xE6, 0x2C, 0x2C, 0xAC, 0x95,
-  0xD6, 0x7D, 0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D,
-  0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9,
-  0x2C, 0x85, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0x2C,
-  0x2C, 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD9,
-  0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6, 0xD9, 0xAF,
-  0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9, 0x2C, 0x85,
-  0xDA, 0xDA, 0x2C, 0xAF, 0xAF, 0x21, 0x20, 0x20,
-  0x88, 0x2B, 0x88, 0x74, 0x20, 0x20, 0x20, 0x20,
-  0x20, 0xAE, 0x2D, 0x2D, 0x74, 0x74, 0x88, 0x20,
-  0x20, 0x20, 0x20, 0x80, 0xAC, 0xD9, 0x95, 0xD6,
-  0xD6, 0xD9, 0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6,
-  0xD9, 0xAF, 0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9,
-  0x2C, 0xDA, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF,
-  0x2C, 0xAF, 0xD9, 0x95, 0xD6, 0xD6, 0x95, 0xAF,
-  0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95, 0xAF, 0x2C,
-  0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C, 0x85, 0x85,
-  0x85, 0xAF, 0xD9, 0x95, 0xD9, 0x7D, 0x20, 0x33,
-  0x7D, 0x8A, 0x7D, 0x5B, 0x6B, 0x20, 0x20, 0x6B,
-  0xE6, 0xD9, 0x85, 0x2A, 0xDA, 0x2B, 0x41, 0x20,
-  0x20, 0x20, 0x6B, 0x74, 0xD9, 0x95, 0xD6, 0xD6,
-  0x95, 0xAF, 0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95,
-  0xAF, 0x2C, 0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C,
-  0x85, 0x85, 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0xD9,
-  0x85, 0xD9, 0x7D, 0x21, 0x21, 0x7D, 0xAC, 0x2C,
-  0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF, 0x2C, 0x85,
-  0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA, 0x8A, 0xDA,
-  0x85, 0xAF, 0xD9, 0x7D, 0xD9, 0x95, 0x20, 0x91,
-  0xBC, 0x73, 0xEE, 0x7D, 0x20, 0x20, 0x20, 0x80,
-  0x4D, 0x3D, 0x73, 0x73, 0xA3, 0xD6, 0x20, 0x20,
-  0x20, 0x20, 0x20, 0x2B, 0x7D, 0x21, 0x21, 0x7D,
-  0xAC, 0x2C, 0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF,
-  0x2C, 0x85, 0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA,
-  0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0x7D, 0xD9, 0xAC,
-  0x2C, 0xD9, 0xD6, 0xB2, 0xB2, 0x7D, 0xAF, 0x85,
-  0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C, 0x2C, 0x2C,
-  0xD9, 0xD9, 0xAC, 0x85, 0x8D, 0x2A, 0x2A, 0xDA,
-  0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAC, 0x20, 0xAF,
-  0x2C, 0xE6, 0x8D, 0x73, 0xE3, 0x20, 0x20, 0x48,
-  0x5C, 0xDA, 0x5B, 0x43, 0xBC, 0x73, 0x2B, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0xB2, 0x7D,
-  0xAF, 0x85, 0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C,
-  0x2C, 0x2C, 0xD9, 0xD9, 0xAC, 0x85, 0x8A, 0x2A,
-  0x8D, 0xDA, 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAF,
-  0xAC, 0xD9, 0xD6, 0xB2, 0x21, 0xD9, 0x2C, 0x85,
-  0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C, 0x2C, 0xAC,
-  0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0xBC, 0xDA, 0xD9,
-  0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xAC, 0x20, 0x2A,
-  0xCC, 0xAE, 0x9F, 0xE4, 0xAE, 0x5B, 0x74, 0xA1,
-  0xE4, 0xAE, 0x20, 0x9F, 0x89, 0xE8, 0xE6, 0x20,
-  0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0x21, 0xD9,
-  0x2C, 0x85, 0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C,
-  0x2C, 0xAC, 0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0x2A,
-  0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9,
-  0xD9, 0x95, 0x21, 0xA1, 0x21, 0xAC, 0x85, 0x85,
-  0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0xAF, 0xAC,
-  0xAF, 0x85, 0x8A, 0x2A, 0x2A, 0xDA, 0xD9, 0xA1,
-  0x48, 0xE9, 0x48, 0x21, 0x95, 0xAC, 0x20, 0x2A,
-  0xDB, 0x41, 0x74, 0xBC, 0x2B, 0x7B, 0x7B, 0x80,
-  0x73, 0x41, 0x20, 0x6B, 0x2B, 0xE8, 0x2D, 0x20,
-  0x20, 0x20, 0x20, 0x33, 0x21, 0xA1, 0x21, 0xAC,
-  0x85, 0x85, 0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C,
-  0xAF, 0xAC, 0xAF, 0x85, 0x8A, 0xBC, 0x2A, 0xDA,
-  0xD9, 0xA1, 0x48, 0xE9, 0x48, 0x21, 0xD9, 0xD9,
-  0xA1, 0xB2, 0xB2, 0x48, 0xD6, 0xAC, 0x2C, 0x2C,
-  0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
-  0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95, 0xA1, 0x6C,
-  0x6C, 0x48, 0xD6, 0xD9, 0x2C, 0x85, 0x20, 0x2C,
-  0x89, 0x20, 0x3C, 0xB9, 0xA7, 0x63, 0xD2, 0xB9,
-  0xC6, 0x9A, 0x20, 0x20, 0x43, 0x5C, 0xE6, 0x20,
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+    0xa4, 0xa4, 0xa4, 0xa4, 0xac, 0x7b, 0x81, 0xb9,
+    0x73, 0x3b, 0x44, 0x9b, 0x48, 0x48, 0x48, 0x9b,
+    0x99, 0x43, 0x94, 0x2c, 0x21, 0x36, 0x36, 0x36,
+    0x36, 0x36, 0x73, 0xb9, 0x7a, 0x7b, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
+    0xa4, 0x64, 0x76, 0x7a, 0x91, 0xb5, 0x31, 0x30,
+    0x28, 0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x24,
+    0x39, 0x97, 0x75, 0xbe, 0x7b, 0x64, 0xa3, 0xa3,
+    0xac, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0x7b, 0x7a, 0xc7,
+    0xc8, 0x36, 0x21, 0x26, 0x2b, 0x39, 0x33, 0x30,
+    0x23, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x21, 0xc8, 0xbb, 0x8b, 0x7b, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa3, 0x64, 0x64,
+    0x76, 0x85, 0xbf, 0xb5, 0x34, 0x2b, 0x27, 0x28,
+    0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x28,
+    0x33, 0xc9, 0x63, 0x7e, 0x7a, 0x6d, 0xbe, 0x5b,
+    0x76, 0x7b, 0x64, 0x64, 0xa3, 0xac, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xac, 0x76, 0x85, 0xb9,
+    0x79, 0x22, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x21, 0xca, 0xbb, 0x75, 0x76, 0xa3, 0xa4,
+    0xa4, 0xa4, 0xac, 0xa3, 0x64, 0x76, 0xbe, 0x8b,
+    0xb6, 0xb5, 0x2f, 0x35, 0x30, 0x24, 0x22, 0x21,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x23,
+    0x27, 0x31, 0xcb, 0xc9, 0xbb, 0x74, 0x63, 0x90,
+    0x7e, 0x75, 0x8b, 0x6d, 0xbe, 0x76, 0x64, 0xa3,
+    0xac, 0xac, 0xac, 0xac, 0x64, 0x7a, 0x84, 0xcc,
+    0x79, 0xa0, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x21, 0xc8, 0xcc, 0x63, 0x6d, 0x7b, 0x64,
+    0xac, 0xa3, 0x64, 0x7b, 0xbe, 0x75, 0x63, 0x96,
+    0x38, 0x39, 0x2a, 0x24, 0x23, 0x21, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21,
+    0x28, 0x27, 0x35, 0x2d, 0x41, 0xb5, 0xc5, 0x8f,
+    0xb9, 0xbb, 0xc7, 0x74, 0x84, 0x90, 0x85, 0x6d,
+    0x5b, 0x7b, 0x7b, 0xab, 0x6d, 0x90, 0xb9, 0xcd,
+    0xca, 0x22, 0x36, 0x36, 0x28, 0x30, 0x30, 0x30,
+    0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x25, 0x36,
+    0x36, 0x21, 0xb4, 0x80, 0xc7, 0x7e, 0x6d, 0x76,
+    0xab, 0x76, 0x6d, 0x85, 0x63, 0xb9, 0xb5, 0x34,
+    0x33, 0x26, 0x23, 0x21, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x21, 0x23, 0x24, 0x27, 0x2a, 0x35, 0x2e, 0x2f,
+    0x41, 0xce, 0xcf, 0x6c, 0x80, 0xcc, 0xb9, 0x74,
+    0x84, 0x90, 0x75, 0x7e, 0x74, 0x8f, 0xcd, 0x79,
+    0xc6, 0x2b, 0x9d, 0x41, 0x2f, 0x34, 0x2d, 0x2d,
+    0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x34, 0x2f, 0x38,
+    0x4d, 0x37, 0xd0, 0xd1, 0x8f, 0x74, 0x63, 0x7e,
+    0x75, 0x7e, 0x63, 0xc7, 0x88, 0xc4, 0x31, 0x2a,
+    0x24, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x21, 0x22, 0x23, 0x24, 0x26, 0x30,
+    0x33, 0x39, 0x2e, 0x51, 0x41, 0xb2, 0x6c, 0xd1,
+    0x80, 0xcc, 0xcc, 0xcc, 0xd2, 0xd1, 0xb7, 0xd3,
+    0x41, 0x34, 0x35, 0x32, 0x30, 0x27, 0x27, 0x27,
+    0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x30, 0x2a,
+    0x2b, 0x34, 0xd4, 0xca, 0xd5, 0x8f, 0xbb, 0xc7,
+    0xc7, 0xbb, 0xcc, 0x6c, 0x41, 0x39, 0x27, 0x28,
+    0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22,
+    0x28, 0x24, 0x26, 0x2a, 0x33, 0x2c, 0x2f, 0x41,
+    0xd6, 0xb7, 0x79, 0x79, 0x79, 0xca, 0xd7, 0x51,
+    0x39, 0x30, 0x24, 0x23, 0x22, 0x22, 0x22, 0x22,
+    0x22, 0x22, 0x21, 0x22, 0x22, 0x22, 0x22, 0x23,
+    0x24, 0x2a, 0x31, 0xd8, 0xc8, 0x79, 0xd1, 0x80,
+    0xd5, 0xba, 0xd9, 0x2f, 0x35, 0x26, 0x23, 0x21,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x21, 0x22, 0x23, 0x28, 0x25, 0x30, 0x2b,
+    0x31, 0x2f, 0xd4, 0xd8, 0xd8, 0x2f, 0x2e, 0x33,
+    0x26, 0x23, 0x21, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x21, 0x28, 0x27, 0x35, 0x34, 0xd8, 0xd8, 0xd8,
+    0xda, 0xd4, 0x2e, 0x33, 0x25, 0x23, 0x21, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x23, 0x28,
+    0x26, 0x30, 0x32, 0x2b, 0x33, 0x2a, 0x26, 0x28,
+    0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x21, 0x23, 0x25, 0x30, 0x33, 0x35, 0x35,
+    0x2b, 0x2a, 0x26, 0x28, 0x22, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21,
+    0x21, 0x22, 0x23, 0x28, 0x28, 0x23, 0x22, 0x21,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x21, 0x23, 0x28, 0x24, 0x24,
+    0x28, 0x23, 0x22, 0x21, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
 };
-
-#define INCLUDE_LINUX_LOGOBW
-#define INCLUDE_LINUX_LOGO16
-#include <linux/linux_logo.h>
 
 #endif /* INCLUDE_LINUX_LOGO_DATA */
--- linux-mips/include/asm-mips64/linux_logo.h	5 Aug 2002 23:53:39 -0000	1.3.2.1
+++ linux-mips/include/asm-mips64/linux_logo.h	5 Dec 2002 16:21:30 -0000
@@ -20,900 +20,14 @@
 
 #include <linux/init.h>
 #include <linux/version.h>
+#include <linux/config.h>
 
 #define linux_logo_banner "Linux/MIPS64 version " UTS_RELEASE
 
-#define __HAVE_ARCH_LINUX_LOGO
-
-#define LINUX_LOGO_COLORS	187
-
-#ifdef INCLUDE_LINUX_LOGO_DATA
-
-unsigned char linux_logo_red[] __initdata = {
-    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
-    0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
-    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x02, 0x65,
-    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
-    0xc3, 0x65, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
-    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
-    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x76, 0x79,
-    0x62, 0x36, 0x9a, 0xe2, 0xec, 0xe1, 0xb8, 0xd7,
-    0xaf, 0x25, 0xbc, 0xc0, 0xef, 0xea, 0xe8, 0xe8,
-    0xf5, 0xf1, 0xda, 0xd3, 0x79, 0xdb, 0xf4, 0xf6,
-    0xf6, 0xf6, 0xe2, 0x3d, 0xb4, 0xce, 0xe6, 0xee,
-    0xf6, 0x68, 0xd8, 0xec, 0xf5, 0xc6, 0xc8, 0x9c,
-    0x89, 0xd2, 0xee, 0xcb, 0xb9, 0xd2, 0x66, 0x5e,
-    0x8b, 0xbe, 0xa8, 0xd5, 0xca, 0xb6, 0xae, 0x9c,
-    0xc5, 0xbe, 0xbe, 0xca, 0x90, 0xb2, 0x9a, 0xa8,
-    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
-    0x12, 0x4a, 0x8e, 0xf2, 0xf6, 0xee, 0xb5, 0xe4,
-    0xf1, 0x26, 0x9a, 0xea, 0xf6, 0xe0, 0xd2, 0x16,
-    0x9a, 0x2e, 0x70, 0xd6, 0x46, 0x7c, 0xb4, 0x62,
-    0xd6, 0xa3, 0x74, 0xa7, 0xa2, 0xca, 0xe0, 0xae,
-    0xbe, 0xce, 0xa3, 0x8e, 0x6d, 0x8e, 0x32, 0xaf,
-    0x50, 0x9e, 0x5b, 0x8a, 0x98, 0x82, 0x7a, 0x82,
-    0x56, 0x7c, 0x8a, 0x56, 0x5e, 0x86, 0x6a, 0x52,
-    0x59, 0x64, 0x5e,
-};
-
-unsigned char linux_logo_green[] __initdata = {
-    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
-    0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
-    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x02, 0x65,
-    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
-    0xc3, 0x62, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
-    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
-    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x62, 0x5c,
-    0x4e, 0x26, 0x72, 0xaa, 0xba, 0xaf, 0x90, 0xae,
-    0x92, 0x1a, 0xa4, 0x85, 0xb6, 0xbe, 0xc3, 0xc8,
-    0xcf, 0xd0, 0xc2, 0xce, 0x57, 0xa2, 0xd6, 0xda,
-    0xda, 0xd7, 0xb8, 0x2a, 0x7b, 0x91, 0xae, 0xca,
-    0xda, 0x45, 0x9e, 0xb2, 0xd7, 0x9b, 0x90, 0x76,
-    0x5c, 0xa2, 0xbe, 0xa6, 0x85, 0x96, 0x4e, 0x46,
-    0x66, 0x92, 0x7a, 0x9a, 0x96, 0x9d, 0x9a, 0x6b,
-    0x8a, 0x8e, 0xb2, 0xca, 0x90, 0xa6, 0x79, 0x7c,
-    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
-    0x0e, 0x36, 0x86, 0xba, 0xbe, 0xcc, 0x8e, 0xb8,
-    0xc4, 0x1e, 0x8e, 0xae, 0xba, 0xb2, 0xa6, 0x12,
-    0x7a, 0x20, 0x64, 0xaa, 0x2f, 0x70, 0x85, 0x46,
-    0xa6, 0x6e, 0x51, 0x72, 0x92, 0xa2, 0xa6, 0x87,
-    0x96, 0xa2, 0x85, 0x7a, 0x6a, 0x6e, 0x22, 0x76,
-    0x36, 0x76, 0x3c, 0x6e, 0x63, 0x53, 0x66, 0x62,
-    0x42, 0x50, 0x56, 0x42, 0x56, 0x56, 0x56, 0x3e,
-    0x51, 0x52, 0x56,
-};
-
-unsigned char linux_logo_blue[] __initdata = {
-    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
-    0x12, 0x01, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
-    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x06, 0x65,
-    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
-    0xc3, 0x59, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
-    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
-    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x2e, 0x08,
-    0x0a, 0x06, 0x0a, 0x0b, 0x0b, 0x0f, 0x0c, 0x0f,
-    0x3d, 0x09, 0x73, 0x09, 0x0d, 0x0a, 0x10, 0x1e,
-    0x2d, 0x13, 0x86, 0xba, 0x19, 0x0a, 0x36, 0x3c,
-    0x26, 0x14, 0x0d, 0x06, 0x07, 0x0a, 0x0b, 0x0f,
-    0x4a, 0x06, 0x0a, 0x0c, 0x2b, 0x0a, 0x0b, 0x0a,
-    0x06, 0x0a, 0x0a, 0x11, 0x0b, 0x0a, 0x0a, 0x1e,
-    0x0f, 0x0d, 0x0a, 0x0b, 0x22, 0x6a, 0x72, 0x0b,
-    0x0b, 0x22, 0x90, 0xca, 0x90, 0x92, 0x3c, 0x2c,
-    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
-    0x06, 0x0e, 0x6a, 0x0e, 0x0e, 0x5b, 0x2c, 0x3e,
-    0x0e, 0x0a, 0x5a, 0x0d, 0x0e, 0x3e, 0x0a, 0x06,
-    0x2e, 0x06, 0x4e, 0x36, 0x06, 0x58, 0x24, 0x06,
-    0x3a, 0x08, 0x08, 0x07, 0x5e, 0x45, 0x0a, 0x32,
-    0x2e, 0x2a, 0x43, 0x48, 0x5f, 0x2e, 0x06, 0x06,
-    0x07, 0x24, 0x06, 0x32, 0x06, 0x06, 0x46, 0x2e,
-    0x22, 0x06, 0x06, 0x1e, 0x4c, 0x06, 0x3a, 0x22,
-    0x42, 0x34, 0x42,
-};
-
-unsigned char linux_logo[] __initdata = {
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22, 0x22,
-    0x22, 0x21, 0x21, 0x21, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
-    0x26, 0x26, 0x25, 0x28, 0x23, 0x22, 0x21, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x29, 0x29, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x21, 0x23, 0x25, 0x2a, 0x2b, 0x2c, 0x2d, 0x2d,
-    0x2d, 0x2e, 0x2c, 0x2b, 0x2a, 0x25, 0x28, 0x22,
-    0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
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-    0x26, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x24,
-    0x35, 0x96, 0x75, 0xab, 0xa3, 0xac, 0xa4, 0xa4,
-    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
-    0xa4, 0xa4, 0xa4, 0xa4, 0xac, 0x7b, 0x81, 0xb9,
-    0x73, 0x3b, 0x44, 0x9b, 0x48, 0x48, 0x48, 0x9b,
-    0x99, 0x43, 0x94, 0x2c, 0x21, 0x36, 0x36, 0x36,
-    0x36, 0x36, 0x73, 0xb9, 0x7a, 0x7b, 0xa4, 0xa4,
-    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
-    0xa4, 0x64, 0x76, 0x7a, 0x91, 0xb5, 0x31, 0x30,
-    0x28, 0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x24,
-    0x39, 0x97, 0x75, 0xbe, 0x7b, 0x64, 0xa3, 0xa3,
-    0xac, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
-    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0x7b, 0x7a, 0xc7,
-    0xc8, 0x36, 0x21, 0x26, 0x2b, 0x39, 0x33, 0x30,
-    0x23, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
-    0x36, 0x21, 0xc8, 0xbb, 0x8b, 0x7b, 0xa4, 0xa4,
-    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa3, 0x64, 0x64,
-    0x76, 0x85, 0xbf, 0xb5, 0x34, 0x2b, 0x27, 0x28,
-    0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x28,
-    0x33, 0xc9, 0x63, 0x7e, 0x7a, 0x6d, 0xbe, 0x5b,
-    0x76, 0x7b, 0x64, 0x64, 0xa3, 0xac, 0xa4, 0xa4,
-    0xa4, 0xa4, 0xa4, 0xa4, 0xac, 0x76, 0x85, 0xb9,
-    0x79, 0x22, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
-    0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
-    0x36, 0x21, 0xca, 0xbb, 0x75, 0x76, 0xa3, 0xa4,
-    0xa4, 0xa4, 0xac, 0xa3, 0x64, 0x76, 0xbe, 0x8b,
-    0xb6, 0xb5, 0x2f, 0x35, 0x30, 0x24, 0x22, 0x21,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x23,
-    0x27, 0x31, 0xcb, 0xc9, 0xbb, 0x74, 0x63, 0x90,
-    0x7e, 0x75, 0x8b, 0x6d, 0xbe, 0x76, 0x64, 0xa3,
-    0xac, 0xac, 0xac, 0xac, 0x64, 0x7a, 0x84, 0xcc,
-    0x79, 0xa0, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
-    0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
-    0x36, 0x21, 0xc8, 0xcc, 0x63, 0x6d, 0x7b, 0x64,
-    0xac, 0xa3, 0x64, 0x7b, 0xbe, 0x75, 0x63, 0x96,
-    0x38, 0x39, 0x2a, 0x24, 0x23, 0x21, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21,
-    0x28, 0x27, 0x35, 0x2d, 0x41, 0xb5, 0xc5, 0x8f,
-    0xb9, 0xbb, 0xc7, 0x74, 0x84, 0x90, 0x85, 0x6d,
-    0x5b, 0x7b, 0x7b, 0xab, 0x6d, 0x90, 0xb9, 0xcd,
-    0xca, 0x22, 0x36, 0x36, 0x28, 0x30, 0x30, 0x30,
-    0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x25, 0x36,
-    0x36, 0x21, 0xb4, 0x80, 0xc7, 0x7e, 0x6d, 0x76,
-    0xab, 0x76, 0x6d, 0x85, 0x63, 0xb9, 0xb5, 0x34,
-    0x33, 0x26, 0x23, 0x21, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x21, 0x23, 0x24, 0x27, 0x2a, 0x35, 0x2e, 0x2f,
-    0x41, 0xce, 0xcf, 0x6c, 0x80, 0xcc, 0xb9, 0x74,
-    0x84, 0x90, 0x75, 0x7e, 0x74, 0x8f, 0xcd, 0x79,
-    0xc6, 0x2b, 0x9d, 0x41, 0x2f, 0x34, 0x2d, 0x2d,
-    0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x34, 0x2f, 0x38,
-    0x4d, 0x37, 0xd0, 0xd1, 0x8f, 0x74, 0x63, 0x7e,
-    0x75, 0x7e, 0x63, 0xc7, 0x88, 0xc4, 0x31, 0x2a,
-    0x24, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x21, 0x22, 0x23, 0x24, 0x26, 0x30,
-    0x33, 0x39, 0x2e, 0x51, 0x41, 0xb2, 0x6c, 0xd1,
-    0x80, 0xcc, 0xcc, 0xcc, 0xd2, 0xd1, 0xb7, 0xd3,
-    0x41, 0x34, 0x35, 0x32, 0x30, 0x27, 0x27, 0x27,
-    0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x30, 0x2a,
-    0x2b, 0x34, 0xd4, 0xca, 0xd5, 0x8f, 0xbb, 0xc7,
-    0xc7, 0xbb, 0xcc, 0x6c, 0x41, 0x39, 0x27, 0x28,
-    0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22,
-    0x28, 0x24, 0x26, 0x2a, 0x33, 0x2c, 0x2f, 0x41,
-    0xd6, 0xb7, 0x79, 0x79, 0x79, 0xca, 0xd7, 0x51,
-    0x39, 0x30, 0x24, 0x23, 0x22, 0x22, 0x22, 0x22,
-    0x22, 0x22, 0x21, 0x22, 0x22, 0x22, 0x22, 0x23,
-    0x24, 0x2a, 0x31, 0xd8, 0xc8, 0x79, 0xd1, 0x80,
-    0xd5, 0xba, 0xd9, 0x2f, 0x35, 0x26, 0x23, 0x21,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x21, 0x22, 0x23, 0x28, 0x25, 0x30, 0x2b,
-    0x31, 0x2f, 0xd4, 0xd8, 0xd8, 0x2f, 0x2e, 0x33,
-    0x26, 0x23, 0x21, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x21, 0x28, 0x27, 0x35, 0x34, 0xd8, 0xd8, 0xd8,
-    0xda, 0xd4, 0x2e, 0x33, 0x25, 0x23, 0x21, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x23, 0x28,
-    0x26, 0x30, 0x32, 0x2b, 0x33, 0x2a, 0x26, 0x28,
-    0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x21, 0x23, 0x25, 0x30, 0x33, 0x35, 0x35,
-    0x2b, 0x2a, 0x26, 0x28, 0x22, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21,
-    0x21, 0x22, 0x23, 0x28, 0x28, 0x23, 0x22, 0x21,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x21, 0x23, 0x28, 0x24, 0x24,
-    0x28, 0x23, 0x22, 0x21, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
-};
-
-#endif /* INCLUDE_LINUX_LOGO_DATA */
+#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP27) || \
+    defined(CONFIG_SGI_IP32)
+#include <asm/linux_logo_sgi.h>
+#endif
 
 #include <linux/linux_logo.h>
 
--- /dev/null	Mon Mar 18 12:17:27 2002
+++ linux-mips/include/asm-mips64/linux_logo_sgi.h	Thu Dec  5 17:14:36 2002
@@ -0,0 +1,902 @@
+/*
+ * include/asm-mips/linux_logo_sgi.h: This is a linux logo
+ *                                for SGI based machines
+ *                                to be displayed on boot.
+ *
+ * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
+ * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ * Copyright (C) 2001 Jan-Benedict Glaw <jbglaw@lug-owl.de>
+ *
+ */
+
+#define __HAVE_ARCH_LINUX_LOGO
+
+#define LINUX_LOGO_COLORS	187
+
+#ifdef INCLUDE_LINUX_LOGO_DATA
+
+unsigned char linux_logo_red[] __initdata = {
+    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
+    0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
+    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x02, 0x65,
+    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
+    0xc3, 0x65, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
+    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
+    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x76, 0x79,
+    0x62, 0x36, 0x9a, 0xe2, 0xec, 0xe1, 0xb8, 0xd7,
+    0xaf, 0x25, 0xbc, 0xc0, 0xef, 0xea, 0xe8, 0xe8,
+    0xf5, 0xf1, 0xda, 0xd3, 0x79, 0xdb, 0xf4, 0xf6,
+    0xf6, 0xf6, 0xe2, 0x3d, 0xb4, 0xce, 0xe6, 0xee,
+    0xf6, 0x68, 0xd8, 0xec, 0xf5, 0xc6, 0xc8, 0x9c,
+    0x89, 0xd2, 0xee, 0xcb, 0xb9, 0xd2, 0x66, 0x5e,
+    0x8b, 0xbe, 0xa8, 0xd5, 0xca, 0xb6, 0xae, 0x9c,
+    0xc5, 0xbe, 0xbe, 0xca, 0x90, 0xb2, 0x9a, 0xa8,
+    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
+    0x12, 0x4a, 0x8e, 0xf2, 0xf6, 0xee, 0xb5, 0xe4,
+    0xf1, 0x26, 0x9a, 0xea, 0xf6, 0xe0, 0xd2, 0x16,
+    0x9a, 0x2e, 0x70, 0xd6, 0x46, 0x7c, 0xb4, 0x62,
+    0xd6, 0xa3, 0x74, 0xa7, 0xa2, 0xca, 0xe0, 0xae,
+    0xbe, 0xce, 0xa3, 0x8e, 0x6d, 0x8e, 0x32, 0xaf,
+    0x50, 0x9e, 0x5b, 0x8a, 0x98, 0x82, 0x7a, 0x82,
+    0x56, 0x7c, 0x8a, 0x56, 0x5e, 0x86, 0x6a, 0x52,
+    0x59, 0x64, 0x5e,
+};
+
+unsigned char linux_logo_green[] __initdata = {
+    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
+    0x12, 0x00, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
+    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x02, 0x65,
+    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
+    0xc3, 0x62, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
+    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
+    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x62, 0x5c,
+    0x4e, 0x26, 0x72, 0xaa, 0xba, 0xaf, 0x90, 0xae,
+    0x92, 0x1a, 0xa4, 0x85, 0xb6, 0xbe, 0xc3, 0xc8,
+    0xcf, 0xd0, 0xc2, 0xce, 0x57, 0xa2, 0xd6, 0xda,
+    0xda, 0xd7, 0xb8, 0x2a, 0x7b, 0x91, 0xae, 0xca,
+    0xda, 0x45, 0x9e, 0xb2, 0xd7, 0x9b, 0x90, 0x76,
+    0x5c, 0xa2, 0xbe, 0xa6, 0x85, 0x96, 0x4e, 0x46,
+    0x66, 0x92, 0x7a, 0x9a, 0x96, 0x9d, 0x9a, 0x6b,
+    0x8a, 0x8e, 0xb2, 0xca, 0x90, 0xa6, 0x79, 0x7c,
+    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
+    0x0e, 0x36, 0x86, 0xba, 0xbe, 0xcc, 0x8e, 0xb8,
+    0xc4, 0x1e, 0x8e, 0xae, 0xba, 0xb2, 0xa6, 0x12,
+    0x7a, 0x20, 0x64, 0xaa, 0x2f, 0x70, 0x85, 0x46,
+    0xa6, 0x6e, 0x51, 0x72, 0x92, 0xa2, 0xa6, 0x87,
+    0x96, 0xa2, 0x85, 0x7a, 0x6a, 0x6e, 0x22, 0x76,
+    0x36, 0x76, 0x3c, 0x6e, 0x63, 0x53, 0x66, 0x62,
+    0x42, 0x50, 0x56, 0x42, 0x56, 0x56, 0x56, 0x3e,
+    0x51, 0x52, 0x56,
+};
+
+unsigned char linux_logo_blue[] __initdata = {
+    0x00, 0x06, 0x0a, 0x0e, 0x16, 0x1a, 0x1e, 0x22,
+    0x12, 0x01, 0x2a, 0x36, 0x42, 0x4e, 0x4a, 0x56,
+    0x26, 0x46, 0x2e, 0x32, 0x52, 0x3a, 0x06, 0x65,
+    0x5e, 0x3e, 0x74, 0x8a, 0xa2, 0x9a, 0x86, 0xc6,
+    0xc3, 0x59, 0xbb, 0xd2, 0xda, 0xd6, 0xe2, 0xf6,
+    0xfd, 0xae, 0x7b, 0xdd, 0xea, 0x6a, 0xaa, 0xe7,
+    0xbe, 0x5a, 0xee, 0x9e, 0x95, 0x80, 0x2e, 0x08,
+    0x0a, 0x06, 0x0a, 0x0b, 0x0b, 0x0f, 0x0c, 0x0f,
+    0x3d, 0x09, 0x73, 0x09, 0x0d, 0x0a, 0x10, 0x1e,
+    0x2d, 0x13, 0x86, 0xba, 0x19, 0x0a, 0x36, 0x3c,
+    0x26, 0x14, 0x0d, 0x06, 0x07, 0x0a, 0x0b, 0x0f,
+    0x4a, 0x06, 0x0a, 0x0c, 0x2b, 0x0a, 0x0b, 0x0a,
+    0x06, 0x0a, 0x0a, 0x11, 0x0b, 0x0a, 0x0a, 0x1e,
+    0x0f, 0x0d, 0x0a, 0x0b, 0x22, 0x6a, 0x72, 0x0b,
+    0x0b, 0x22, 0x90, 0xca, 0x90, 0x92, 0x3c, 0x2c,
+    0xb6, 0xf2, 0xce, 0xfa, 0xb2, 0x6e, 0xa6, 0x8d,
+    0x06, 0x0e, 0x6a, 0x0e, 0x0e, 0x5b, 0x2c, 0x3e,
+    0x0e, 0x0a, 0x5a, 0x0d, 0x0e, 0x3e, 0x0a, 0x06,
+    0x2e, 0x06, 0x4e, 0x36, 0x06, 0x58, 0x24, 0x06,
+    0x3a, 0x08, 0x08, 0x07, 0x5e, 0x45, 0x0a, 0x32,
+    0x2e, 0x2a, 0x43, 0x48, 0x5f, 0x2e, 0x06, 0x06,
+    0x07, 0x24, 0x06, 0x32, 0x06, 0x06, 0x46, 0x2e,
+    0x22, 0x06, 0x06, 0x1e, 0x4c, 0x06, 0x3a, 0x22,
+    0x42, 0x34, 0x42,
+};
+
+unsigned char linux_logo[] __initdata = {
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22, 0x22,
+    0x22, 0x21, 0x21, 0x21, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
+    0x26, 0x26, 0x25, 0x28, 0x23, 0x22, 0x21, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x29, 0x29, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
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+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa3, 0x72, 0x81, 0xc5,
+    0x46, 0x48, 0x48, 0x48, 0x48, 0x48, 0x48, 0x48,
+    0x48, 0x48, 0x48, 0x48, 0x3f, 0x2c, 0x36, 0x36,
+    0x36, 0x36, 0xc6, 0x8f, 0x6d, 0x64, 0xac, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa3, 0xab, 0x8b, 0xb0, 0x2c,
+    0x26, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x24,
+    0x35, 0x96, 0x75, 0xab, 0xa3, 0xac, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xac, 0x7b, 0x81, 0xb9,
+    0x73, 0x3b, 0x44, 0x9b, 0x48, 0x48, 0x48, 0x9b,
+    0x99, 0x43, 0x94, 0x2c, 0x21, 0x36, 0x36, 0x36,
+    0x36, 0x36, 0x73, 0xb9, 0x7a, 0x7b, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
+    0xa4, 0x64, 0x76, 0x7a, 0x91, 0xb5, 0x31, 0x30,
+    0x28, 0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x24,
+    0x39, 0x97, 0x75, 0xbe, 0x7b, 0x64, 0xa3, 0xa3,
+    0xac, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0x7b, 0x7a, 0xc7,
+    0xc8, 0x36, 0x21, 0x26, 0x2b, 0x39, 0x33, 0x30,
+    0x23, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x21, 0xc8, 0xbb, 0x8b, 0x7b, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa3, 0x64, 0x64,
+    0x76, 0x85, 0xbf, 0xb5, 0x34, 0x2b, 0x27, 0x28,
+    0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x28,
+    0x33, 0xc9, 0x63, 0x7e, 0x7a, 0x6d, 0xbe, 0x5b,
+    0x76, 0x7b, 0x64, 0x64, 0xa3, 0xac, 0xa4, 0xa4,
+    0xa4, 0xa4, 0xa4, 0xa4, 0xac, 0x76, 0x85, 0xb9,
+    0x79, 0x22, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x21, 0xca, 0xbb, 0x75, 0x76, 0xa3, 0xa4,
+    0xa4, 0xa4, 0xac, 0xa3, 0x64, 0x76, 0xbe, 0x8b,
+    0xb6, 0xb5, 0x2f, 0x35, 0x30, 0x24, 0x22, 0x21,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x23,
+    0x27, 0x31, 0xcb, 0xc9, 0xbb, 0x74, 0x63, 0x90,
+    0x7e, 0x75, 0x8b, 0x6d, 0xbe, 0x76, 0x64, 0xa3,
+    0xac, 0xac, 0xac, 0xac, 0x64, 0x7a, 0x84, 0xcc,
+    0x79, 0xa0, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+    0x36, 0x21, 0xc8, 0xcc, 0x63, 0x6d, 0x7b, 0x64,
+    0xac, 0xa3, 0x64, 0x7b, 0xbe, 0x75, 0x63, 0x96,
+    0x38, 0x39, 0x2a, 0x24, 0x23, 0x21, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21,
+    0x28, 0x27, 0x35, 0x2d, 0x41, 0xb5, 0xc5, 0x8f,
+    0xb9, 0xbb, 0xc7, 0x74, 0x84, 0x90, 0x85, 0x6d,
+    0x5b, 0x7b, 0x7b, 0xab, 0x6d, 0x90, 0xb9, 0xcd,
+    0xca, 0x22, 0x36, 0x36, 0x28, 0x30, 0x30, 0x30,
+    0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x25, 0x36,
+    0x36, 0x21, 0xb4, 0x80, 0xc7, 0x7e, 0x6d, 0x76,
+    0xab, 0x76, 0x6d, 0x85, 0x63, 0xb9, 0xb5, 0x34,
+    0x33, 0x26, 0x23, 0x21, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x21, 0x23, 0x24, 0x27, 0x2a, 0x35, 0x2e, 0x2f,
+    0x41, 0xce, 0xcf, 0x6c, 0x80, 0xcc, 0xb9, 0x74,
+    0x84, 0x90, 0x75, 0x7e, 0x74, 0x8f, 0xcd, 0x79,
+    0xc6, 0x2b, 0x9d, 0x41, 0x2f, 0x34, 0x2d, 0x2d,
+    0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x34, 0x2f, 0x38,
+    0x4d, 0x37, 0xd0, 0xd1, 0x8f, 0x74, 0x63, 0x7e,
+    0x75, 0x7e, 0x63, 0xc7, 0x88, 0xc4, 0x31, 0x2a,
+    0x24, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x21, 0x22, 0x23, 0x24, 0x26, 0x30,
+    0x33, 0x39, 0x2e, 0x51, 0x41, 0xb2, 0x6c, 0xd1,
+    0x80, 0xcc, 0xcc, 0xcc, 0xd2, 0xd1, 0xb7, 0xd3,
+    0x41, 0x34, 0x35, 0x32, 0x30, 0x27, 0x27, 0x27,
+    0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x30, 0x2a,
+    0x2b, 0x34, 0xd4, 0xca, 0xd5, 0x8f, 0xbb, 0xc7,
+    0xc7, 0xbb, 0xcc, 0x6c, 0x41, 0x39, 0x27, 0x28,
+    0x21, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22,
+    0x28, 0x24, 0x26, 0x2a, 0x33, 0x2c, 0x2f, 0x41,
+    0xd6, 0xb7, 0x79, 0x79, 0x79, 0xca, 0xd7, 0x51,
+    0x39, 0x30, 0x24, 0x23, 0x22, 0x22, 0x22, 0x22,
+    0x22, 0x22, 0x21, 0x22, 0x22, 0x22, 0x22, 0x23,
+    0x24, 0x2a, 0x31, 0xd8, 0xc8, 0x79, 0xd1, 0x80,
+    0xd5, 0xba, 0xd9, 0x2f, 0x35, 0x26, 0x23, 0x21,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x21, 0x22, 0x23, 0x28, 0x25, 0x30, 0x2b,
+    0x31, 0x2f, 0xd4, 0xd8, 0xd8, 0x2f, 0x2e, 0x33,
+    0x26, 0x23, 0x21, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x21, 0x28, 0x27, 0x35, 0x34, 0xd8, 0xd8, 0xd8,
+    0xda, 0xd4, 0x2e, 0x33, 0x25, 0x23, 0x21, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x23, 0x28,
+    0x26, 0x30, 0x32, 0x2b, 0x33, 0x2a, 0x26, 0x28,
+    0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x21, 0x23, 0x25, 0x30, 0x33, 0x35, 0x35,
+    0x2b, 0x2a, 0x26, 0x28, 0x22, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x21,
+    0x21, 0x22, 0x23, 0x28, 0x28, 0x23, 0x22, 0x21,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x21, 0x23, 0x28, 0x24, 0x24,
+    0x28, 0x23, 0x22, 0x21, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+};
+
+#endif /* INCLUDE_LINUX_LOGO_DATA */

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


From alan@lxorguk.ukuu.org.uk Thu Dec  5 17:52:20 2002
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Subject: Re: Old SGI penguin logo
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "Kevin D. Kissell" <kevink@mips.com>,
	Ralf Baechle <ralf@linux-mips.org>,
	Linux/MIPS Development <linux-mips@linux-mips.org>
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On Thu, 2002-12-05 at 12:10, Geert Uytterhoeven wrote:
> Yes, if some talented person can create a nice penguin/mips logo, that would be
> nice.

Make sure mips trademark vultures are ok with it too. We've had some
minor (friendly) runins with other chip vendors over penguins with their
logo on.


From alan@lxorguk.ukuu.org.uk Thu Dec  5 17:54:44 2002
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From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Carsten Langgaard <carstenl@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
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On Thu, 2002-12-05 at 13:35, Carsten Langgaard wrote:
> > Hmm...  What compiler version is that?  The gcc documentation explicitly
> > permits empty arrays.

There was some discussion about this and what to do with zero sized
objects. In the C++ universe it seems to be horribly complicated with
rules about two objects not having the same address.



From atulsrivastava9@rediffmail.com Fri Dec  6 13:14:11 2002
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Hello ,

Excuse me for putting a tentative question.

I have a obscure problem of pagefault at unlikely address
that is pinned down to ret_from_sys_call called from
nopage_tlbl -> DO_FAULT -> ret_from_sys_call(nowdays ret_from 
excep-
tion) during execing userspace programmes.

also due to sone resons out of my control my working source tree
appears to be hacked too much.

I have one entry.S in linux 2.4.17 having top line like

/* $Id: entry.S,v 1.19 1999/12/08 22:05:10 harald Exp

with ret_from_sys_call like

EXPORT(ret_from_sys_call)
         MEASURED_CLI

         /* Check to see if the current task
          * needs to be resscheduled
          */
         lw      t2, TASK_NEED_RESCHED($28)
         nop
         bnez    t2, reschedule
         nop

and one entry.S in some earlier version of entry.S with top line
   /* $Id: entry.S,v 1.1.1.2 2001/04/30 10:53:58 carstenl Exp $

here the ret_from_sys_call is just Blank like this

EXPORT(ret_from_sys_call)

EXPORT(ret_from_irq)
                 .type   ret_from_irq,@function
                 ......
                 ......

i am curently using this later one .
but i amn't able to follow the changes for ret_from_sys_call 
between these two versions.

Best Regards,
Atul

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Carsten Langgaard wrote:

> "Maciej W. Rozycki" wrote:
>
> > On Thu, 5 Dec 2002, Carsten Langgaard wrote:
> >
> > > > Everybody satisfied?
> > >
> > > Not quite, I afraid.
> > > I would like to be able to compile a 64-bit kernel, using the
> > > MIPS32/MIPS64 config1 register, but I don't have a MIPS64 compliant n64
> > > compiler (assembler). So I need the hardcoded ".word" opcode version, we
> > > previously had.
> >
> >  Please upgrade/patch your tools.  If you can't, then this qualifies for a
> > privately maintained patch perfectly.
>
> I can live with that, already done.
>
> >
> >  Support for MIPS32/MIPS64 was added to binutils two years ago.  Version
> > 2.11 suffices.
> >
>
> I just checked the FTP server for a new version
> (ftp://ftp.linux-mips.org/pub/linux/mips/crossdev/i386-linux/), and someone
> actually provided a
> new set of binutils. It's less than a month ago (Nov 12), it was put there.
> But if that works you won't hear more about it from my side ;-)
>

I'm afraid I have to speak up again :-(
Although the new binutils (binutils-mips64el-linux-2.13.1-1.i386.rpm) work on
the latest sources from linux-mips.org, I have a problem with my local sources.

I get the following error from the assembler:


mips64el-linux-gcc -D__KERNEL__
-I/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include -Wall
-Wstrict-prototypes -Wno-trigraphs -O2 -fomit-frame-pointer
-fno-strict-aliasing -fno-common -I
/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include/asm/gcc
-D__KERNEL__
-I/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include -Wall
-Wstrict-prototypes -Wno-trigraphs -O2 -fomit-frame-pointer
-fno-strict-aliasing -fno-common -mabi=64 -G 0 -mno-abicalls -fno-pic
-Wa,--trap -pipe -mcpu=r8000 -mips4 -Wa,-32   -DKBUILD_BASENAME=sched
-fno-omit-frame-pointer -c -o sched.o sched.c
{standard input}: Assembler messages:
{standard input}:329: Warning: dla used to load 32-bit register
{standard input}:382: Error: Number (0xffffffff) larger than 32 bits
{standard input}:408: Warning: dla used to load 32-bit register
{standard input}:431: Warning: dla used to load 32-bit register
{standard input}:541: Warning: dla used to load 32-bit register
{standard input}:542: Warning: dla used to load 32-bit register
{standard input}:554: Warning: dla used to load 32-bit register
{standard input}:557: Warning: dla used to load 32-bit register
{standard input}:558: Warning: dla used to load 32-bit register
{standard input}:567: Warning: dla used to load 32-bit register
{standard input}:569: Warning: dla used to load 32-bit register
{standard input}:570: Warning: dla used to load 32-bit register
{standard input}:581: Warning: dla used to load 32-bit register
{standard input}:824: Warning: dla used to load 32-bit register
{standard input}:847: Warning: dla used to load 32-bit register
{standard input}:848: Warning: dla used to load 32-bit register
{standard input}:884: Warning: dla used to load 32-bit register
{standard input}:885: Warning: dla used to load 32-bit register
{standard input}:898: Warning: dla used to load 32-bit register
{standard input}:1107: Warning: dla used to load 32-bit register
{standard input}:1251: Warning: dla used to load 32-bit register
{standard input}:1407: Warning: dla used to load 32-bit register
{standard input}:2017: Error: Number (0xffffffff) larger than 32 bits
{standard input}:2029: Error: Number (0x0) larger than 32 bits
{standard input}:2031: Error: Number (0xffffffff) larger than 32 bits
{standard input}:2082: Warning: dla used to load 32-bit register
{standard input}:2262: Warning: dla used to load 32-bit register
{standard input}:2393: Warning: dla used to load 32-bit register
{standard input}:2478: Warning: dla used to load 32-bit register
{standard input}:2517: Error: Number (0xffffffff) larger than 32 bits
{standard input}:2529: Error: Number (0x0) larger than 32 bits
{standard input}:2531: Error: Number (0xffffffff) larger than 32 bits
{standard input}:2635: Warning: dla used to load 32-bit register
{standard input}:2797: Warning: dla used to load 32-bit register
{standard input}:2885: Error: Number (0xffffffff) larger than 32 bits
{standard input}:2897: Error: Number (0x0) larger than 32 bits
{standard input}:2899: Error: Number (0xffffffff) larger than 32 bits
{standard input}:3030: Warning: dla used to load 32-bit register
{standard input}:3102: Warning: dla used to load 32-bit register
{standard input}:3113: Warning: dla used to load 32-bit register
{standard input}:3123: Warning: dla used to load 32-bit register
{standard input}:3134: Warning: dla used to load 32-bit register
{standard input}:3140: Warning: dla used to load 32-bit register
{standard input}:3164: Warning: dla used to load 32-bit register
{standard input}:3178: Warning: dla used to load 32-bit register
{standard input}:3194: Warning: dla used to load 32-bit register
{standard input}:3199: Warning: dla used to load 32-bit register
{standard input}:3215: Warning: dla used to load 32-bit register
{standard input}:3220: Warning: dla used to load 32-bit register
{standard input}:3236: Warning: dla used to load 32-bit register
{standard input}:3241: Warning: dla used to load 32-bit register
{standard input}:3244: Warning: dla used to load 32-bit register
{standard input}:3398: Warning: dla used to load 32-bit register
{standard input}:3408: Warning: dla used to load 32-bit register
{standard input}:3410: Warning: dla used to load 32-bit register
{standard input}:3412: Warning: dla used to load 32-bit register
{standard input}:3502: Warning: dla used to load 32-bit register
{standard input}:3532: Error: Number (0xffffffff) larger than 32 bits
{standard input}:3534: Warning: dla used to load 32-bit register
{standard input}:3596: Warning: dla used to load 32-bit register
{standard input}:3657: Warning: dla used to load 32-bit register
{standard input}:3658: Warning: dla used to load 32-bit register
{standard input}:3677: Warning: dla used to load 32-bit register
{standard input}:3708: Warning: dla used to load 32-bit register
{standard input}:3755: Warning: dla used to load 32-bit register
{standard input}:3757: Warning: dla used to load 32-bit register
{standard input}:3773: Warning: dla used to load 32-bit register
{standard input}:3781: Warning: dla used to load 32-bit register
{standard input}:3789: Warning: dla used to load 32-bit register
{standard input}:3849: Warning: dla used to load 32-bit register
make[2]: *** [sched.o] Error 1
make[2]: Leaving directory
`/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/kernel'
make[1]: *** [first_rule] Error 2
make[1]: Leaving directory
`/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/kernel'
make: *** [_dir_kernel] Error 2


The old binutils (binutils-mips64el-linux-2.9.5-3.i386.rpm) worked fine.



>
> Thanks.
> /Carsten
>
> >
> > --
> > +  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
> > +--------------------------------------------------------------+
> > +        e-mail: macro@ds2.pg.gda.pl, PGP key available        +
>
> --
> _    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark            http://www.mips.com

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From ralf@linux-mips.org Fri Dec  6 14:14:16 2002
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On Fri, Dec 06, 2002 at 01:52:57PM +0100, Carsten Langgaard wrote:

> I'm afraid I have to speak up again :-(
> Although the new binutils (binutils-mips64el-linux-2.13.1-1.i386.rpm) work on
> the latest sources from linux-mips.org, I have a problem with my local sources.
> 
> I get the following error from the assembler:
> 
> 
> {standard input}: Assembler messages:
> {standard input}:329: Warning: dla used to load 32-bit register
> {standard input}:382: Error: Number (0xffffffff) larger than 32 bits
> {standard input}:408: Warning: dla used to load 32-bit register

These are caused by an !%$@#$!$ incompatible change in gas.  In essence
the code model we're using now requires to pass the additional option
-mgp64.  arch/mips64/Makefile probes for gas accepting this new option.

So standard advice, update your sources.

  Ralf

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	Ralf Baechle <ralf@linux-mips.org>,
	"Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org
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Carsten Langgaard wrote:
[snip]
> I'm afraid I have to speak up again :-(
> Although the new binutils (binutils-mips64el-linux-2.13.1-1.i386.rpm) work on
> the latest sources from linux-mips.org, I have a problem with my local sources.
>
> I get the following error from the assembler:
> 
> 
> mips64el-linux-gcc -D__KERNEL__
> -I/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include -Wall
> -Wstrict-prototypes -Wno-trigraphs -O2 -fomit-frame-pointer
> -fno-strict-aliasing -fno-common -I
> /home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include/asm/gcc
> -D__KERNEL__
> -I/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include -Wall
> -Wstrict-prototypes -Wno-trigraphs -O2 -fomit-frame-pointer
> -fno-strict-aliasing -fno-common -mabi=64 -G 0 -mno-abicalls -fno-pic
> -Wa,--trap -pipe -mcpu=r8000 -mips4 -Wa,-32   -DKBUILD_BASENAME=sched
> -fno-omit-frame-pointer -c -o sched.o sched.c
> {standard input}: Assembler messages:
> {standard input}:329: Warning: dla used to load 32-bit register
> {standard input}:382: Error: Number (0xffffffff) larger than 32 bits

The new assembler does better checks for invalid opcodes.
Looks like your code misses some e.g.

	set .mips3

but wants to handle 64 bit quantities nevertheless.


Thiemo

From carstenl@mips.com Fri Dec  6 14:28:26 2002
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Ralf Baechle wrote:

> On Fri, Dec 06, 2002 at 01:52:57PM +0100, Carsten Langgaard wrote:
>
> > I'm afraid I have to speak up again :-(
> > Although the new binutils (binutils-mips64el-linux-2.13.1-1.i386.rpm) work on
> > the latest sources from linux-mips.org, I have a problem with my local sources.
> >
> > I get the following error from the assembler:
> >
> >
> > {standard input}: Assembler messages:
> > {standard input}:329: Warning: dla used to load 32-bit register
> > {standard input}:382: Error: Number (0xffffffff) larger than 32 bits
> > {standard input}:408: Warning: dla used to load 32-bit register
>
> These are caused by an !%$@#$!$ incompatible change in gas.  In essence
> the code model we're using now requires to pass the additional option
> -mgp64.  arch/mips64/Makefile probes for gas accepting this new option.
>

Thanks a lot.


>
> So standard advice, update your sources.

In order to have a stable kernel at all time (for core validation), we need to stay
away from the bleeding edge.
So our local sources will always be a little bit behind the main stream.
I have started to send my last patches to you, in order to get ready for a merge
with your latest 2.4.20 sources.


>
>   Ralf

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From ica2_ts@csv.ica.uni-stuttgart.de Fri Dec  6 14:34:56 2002
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Thiemo Seufer wrote:
> Carsten Langgaard wrote:
> [snip]
> > I'm afraid I have to speak up again :-(
> > Although the new binutils (binutils-mips64el-linux-2.13.1-1.i386.rpm) work on
> > the latest sources from linux-mips.org, I have a problem with my local sources.
> >
> > I get the following error from the assembler:
> > 
> > 
> > mips64el-linux-gcc -D__KERNEL__
> > -I/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include -Wall
> > -Wstrict-prototypes -Wno-trigraphs -O2 -fomit-frame-pointer
> > -fno-strict-aliasing -fno-common -I
> > /home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include/asm/gcc
> > -D__KERNEL__
> > -I/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include -Wall
> > -Wstrict-prototypes -Wno-trigraphs -O2 -fomit-frame-pointer
> > -fno-strict-aliasing -fno-common -mabi=64 -G 0 -mno-abicalls -fno-pic
                                     ^^^^^^^^
> > -Wa,--trap -pipe -mcpu=r8000 -mips4 -Wa,-32   -DKBUILD_BASENAME=sched
                                        ^^^^^^^
Then again, I missed you are building for a 64 bit kernel. The
commandline given advises the compiler to create N64 code, but
the assembler is forced to regard it as O32.

I guess the reason for this is the hack to pack 64 bit code in
O32 binaries.


Thiemo

From carstenl@mips.com Fri Dec  6 14:42:19 2002
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From: Carsten Langgaard <carstenl@mips.com>
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To: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
CC: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
	Ralf Baechle <ralf@linux-mips.org>,
	"Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org
Subject: Re: Latest sources from CVS.
References: <Pine.GSO.3.96.1021205143717.29101C-100000@delta.ds2.pg.gda.pl> <3DEF5EB0.A1A18E17@mips.com> <3DF09DA9.B3D108@mips.com> <20021206132412.GB23743@rembrandt.csv.ica.uni-stuttgart.de> <20021206133448.GC23743@rembrandt.csv.ica.uni-stuttgart.de>
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Thiemo Seufer wrote:

> Thiemo Seufer wrote:
> > Carsten Langgaard wrote:
> > [snip]
> > > I'm afraid I have to speak up again :-(
> > > Although the new binutils (binutils-mips64el-linux-2.13.1-1.i386.rpm) work on
> > > the latest sources from linux-mips.org, I have a problem with my local sources.
> > >
> > > I get the following error from the assembler:
> > >
> > >
> > > mips64el-linux-gcc -D__KERNEL__
> > > -I/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include -Wall
> > > -Wstrict-prototypes -Wno-trigraphs -O2 -fomit-frame-pointer
> > > -fno-strict-aliasing -fno-common -I
> > > /home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include/asm/gcc
> > > -D__KERNEL__
> > > -I/home/soc/proj/work/carstenl/linux-2.4.18/sw/linux-2.4.18/include -Wall
> > > -Wstrict-prototypes -Wno-trigraphs -O2 -fomit-frame-pointer
> > > -fno-strict-aliasing -fno-common -mabi=64 -G 0 -mno-abicalls -fno-pic
>                                      ^^^^^^^^
> > > -Wa,--trap -pipe -mcpu=r8000 -mips4 -Wa,-32   -DKBUILD_BASENAME=sched
>                                         ^^^^^^^
> Then again, I missed you are building for a 64 bit kernel. The
> commandline given advises the compiler to create N64 code, but
> the assembler is forced to regard it as O32.
>
> I guess the reason for this is the hack to pack 64 bit code in
> O32 binaries.
>

Exactly.
Note, Ralf has already identified the problem, please see his answer.
After hacking the Makefile (gas option), everything work fine.


>
> Thiemo

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From ica2_ts@csv.ica.uni-stuttgart.de Fri Dec  6 15:15:27 2002
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To: Carsten Langgaard <carstenl@mips.com>
Cc: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
	Ralf Baechle <ralf@linux-mips.org>,
	"Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org
Subject: Re: Latest sources from CVS.
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References: <Pine.GSO.3.96.1021205143717.29101C-100000@delta.ds2.pg.gda.pl> <3DEF5EB0.A1A18E17@mips.com> <3DF09DA9.B3D108@mips.com> <20021206132412.GB23743@rembrandt.csv.ica.uni-stuttgart.de> <20021206133448.GC23743@rembrandt.csv.ica.uni-stuttgart.de> <3DF0A8ED.D9B80781@mips.com>
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Carsten Langgaard wrote:
[snip]
> > > > -fno-strict-aliasing -fno-common -mabi=64 -G 0 -mno-abicalls -fno-pic
> >                                      ^^^^^^^^
> > > > -Wa,--trap -pipe -mcpu=r8000 -mips4 -Wa,-32   -DKBUILD_BASENAME=sched
> >                                         ^^^^^^^
> > Then again, I missed you are building for a 64 bit kernel. The
> > commandline given advises the compiler to create N64 code, but
> > the assembler is forced to regard it as O32.
> >
> > I guess the reason for this is the hack to pack 64 bit code in
> > O32 binaries.
> >
> 
> Exactly.
> Note, Ralf has already identified the problem, please see his answer.
> After hacking the Makefile (gas option), everything work fine.

Er, well, for some values of 'fine'. In principle, 64 bit code shouldn't
be disguised in O32 objects. OTOH i must admit it's a bit early to use
binutils N32 for this purpose.


Thiemo

From macro@ds2.pg.gda.pl Fri Dec  6 17:36:29 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
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On Fri, 6 Dec 2002, Thiemo Seufer wrote:

> Er, well, for some values of 'fine'. In principle, 64 bit code shouldn't
> be disguised in O32 objects. OTOH i must admit it's a bit early to use
> binutils N32 for this purpose.

 Which wouldn't work either as it implies 32-bit pointers, while gcc still
emits 64-bit assembly.  If we want to preserve the setup cleanly, we
probably need yet another ABI model in gcc (especially in the face of the
coming changes to get rid of assembly macros), with sign-extended 32-bit
pointers for accessing program segments and 64-bit ones for the remaining
addresses.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From macro@ds2.pg.gda.pl Fri Dec  6 17:46:20 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Carsten Langgaard <carstenl@mips.com>
cc: "Kevin D. Kissell" <kevink@mips.com>, linux-mips@linux-mips.org
Subject: Re: possible Malta 4Kc cache problem ...
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On Thu, 5 Dec 2002, Carsten Langgaard wrote:

> There is what the errata sheet says:

 Is the errata doc available from anywhere?  Actually are such docs
available for any of your current (recent) processor products? 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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Maciej W. Rozycki wrote:
> On Fri, 6 Dec 2002, Thiemo Seufer wrote:
> 
> > Er, well, for some values of 'fine'. In principle, 64 bit code shouldn't
> > be disguised in O32 objects. OTOH i must admit it's a bit early to use
> > binutils N32 for this purpose.
> 
>  Which wouldn't work either as it implies 32-bit pointers, while gcc still
> emits 64-bit assembly.

Which should be enough for smaller address spaces.

> If we want to preserve the setup cleanly, we
> probably need yet another ABI model in gcc (especially in the face of the
> coming changes to get rid of assembly macros), with sign-extended 32-bit
> pointers for accessing program segments and 64-bit ones for the remaining
> addresses.

Do you think this is worth the hassle? N64 offers better flexibility in
the large memory case at some performance cost, and it's conceptionally
cleaner.


Thiemo

From ralf@linux-mips.org Fri Dec  6 18:04:52 2002
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On Fri, Dec 06, 2002 at 05:45:58PM +0100, Thiemo Seufer wrote:

> > If we want to preserve the setup cleanly, we
> > probably need yet another ABI model in gcc (especially in the face of the
> > coming changes to get rid of assembly macros), with sign-extended 32-bit
> > pointers for accessing program segments and 64-bit ones for the remaining
> > addresses.
> 
> Do you think this is worth the hassle? N64 offers better flexibility in
> the large memory case at some performance cost, and it's conceptionally
> cleaner.

Absolutely:

[ralf@dea linux-sgi-2.4]$ mips64-linux-size vmlinux
   text    data     bss     dec     hex filename
1978296  317344  156224 2451864  256998 vmlinux
[ralf@dea linux-sgi-2.4]$ mips64-linux-size vmlinux
   text    data     bss     dec     hex filename
1761168  317344  156224 2234736  221970 vmlinux

The first kernel was built as 64-bit ELF using 64-bit pointer and everything
64-bit.  The second kernel was built using the -Wa,-32 trick.  That's over
12% of bloat for full 64-bitiness which brings zero gain.

  Ralf

From macro@ds2.pg.gda.pl Fri Dec  6 18:05:37 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
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On Fri, 6 Dec 2002, Thiemo Seufer wrote:

> >  Which wouldn't work either as it implies 32-bit pointers, while gcc still
> > emits 64-bit assembly.
> 
> Which should be enough for smaller address spaces.

 But gas will complain of the same address truncation as for o32. 

> > If we want to preserve the setup cleanly, we
> > probably need yet another ABI model in gcc (especially in the face of the
> > coming changes to get rid of assembly macros), with sign-extended 32-bit
> > pointers for accessing program segments and 64-bit ones for the remaining
> > addresses.
> 
> Do you think this is worth the hassle? N64 offers better flexibility in
> the large memory case at some performance cost, and it's conceptionally
> cleaner.

 Remember we are writing of the kernel -- we don't know what userland is
going to bring us -- a user pointer need not fit in 32 bits.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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Subject: Re: Latest sources from CVS.
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From: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
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Ralf Baechle wrote:
> On Fri, Dec 06, 2002 at 05:45:58PM +0100, Thiemo Seufer wrote:
> 
> > > If we want to preserve the setup cleanly, we
> > > probably need yet another ABI model in gcc (especially in the face of the
> > > coming changes to get rid of assembly macros), with sign-extended 32-bit
> > > pointers for accessing program segments and 64-bit ones for the remaining
> > > addresses.
> > 
> > Do you think this is worth the hassle? N64 offers better flexibility in
> > the large memory case at some performance cost, and it's conceptionally
> > cleaner.
> 
> Absolutely:
> 
> [ralf@dea linux-sgi-2.4]$ mips64-linux-size vmlinux
>    text    data     bss     dec     hex filename
> 1978296  317344  156224 2451864  256998 vmlinux
> [ralf@dea linux-sgi-2.4]$ mips64-linux-size vmlinux
>    text    data     bss     dec     hex filename
> 1761168  317344  156224 2234736  221970 vmlinux
> 
> The first kernel was built as 64-bit ELF using 64-bit pointer and everything
> 64-bit.  The second kernel was built using the -Wa,-32 trick.  That's over
> 12% of bloat for full 64-bitiness which brings zero gain.

I found that in the first case the text segment of my linux kernels
has trailing garbage in it, which can explain most of the difference.

I haven't looked into it yet, it seems to be harmless besides of
increasing file and memory size.

Could you have a look at the disassembly, I guess your kernels suffer
the same effect.


Thiemo

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Subject: Re: Latest sources from CVS.
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Maciej W. Rozycki wrote:
> On Fri, 6 Dec 2002, Thiemo Seufer wrote:
> 
> > >  Which wouldn't work either as it implies 32-bit pointers, while gcc still
> > > emits 64-bit assembly.
> > 
> > Which should be enough for smaller address spaces.
> 
>  But gas will complain of the same address truncation as for o32. 

Maybe I wasn't clear about it, I meant kernels with 32 bit address
space but 64 bit register width, allowing for userland N32 ABI.

E.g. the old DECstations with R4k CPU and limited memory would fit
in this scheme. :-)

> > > If we want to preserve the setup cleanly, we
> > > probably need yet another ABI model in gcc (especially in the face of the
> > > coming changes to get rid of assembly macros), with sign-extended 32-bit
> > > pointers for accessing program segments and 64-bit ones for the remaining
> > > addresses.
> > 
> > Do you think this is worth the hassle? N64 offers better flexibility in
> > the large memory case at some performance cost, and it's conceptionally
> > cleaner.
> 
>  Remember we are writing of the kernel -- we don't know what userland is
> going to bring us

I don't understand this. The kernel _defines_ what the userland is allowed
to do.

> -- a user pointer need not fit in 32 bits.

It needs to, if the kernel doesn't want to support 64 bit address space. :-)


Thiemo

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Subject: Re: Latest sources from CVS.
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On Fri, Dec 06, 2002 at 06:02:41PM +0100, Ralf Baechle wrote:

> The first kernel was built as 64-bit ELF using 64-bit pointer and everything
> 64-bit.  The second kernel was built using the -Wa,-32 trick.  That's over
> 12% of bloat for full 64-bitiness which brings zero gain.

Yes, but that 12% overhead will be reduced when gcc stops using those
crappy macros for everything, and finds some common subexpressions.

-- greg



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On Fri, Dec 06, 2002 at 06:24:38PM +0100, Thiemo Seufer wrote:

> Maybe I wasn't clear about it, I meant kernels with 32 bit address
> space but 64 bit register width, allowing for userland N32 ABI.
> 
> E.g. the old DECstations with R4k CPU and limited memory would fit
> in this scheme. :-)

I'm considering kernels with just 2-level page tables as a step into that
direction.  With 16kB pages that permits for 64GB of virtual address
space, with 4kB pages; with a bit of tweaking we should be able to
maintain the ability to map 2GB in the userspace.

  Ralf

From dom@algor.co.uk Fri Dec  6 19:20:25 2002
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Ralf Baechle (ralf@linux-mips.org) writes:

> Absolutely:
> 
> [ralf@dea linux-sgi-2.4]$ mips64-linux-size vmlinux
>    text    data     bss     dec     hex filename
> 1978296  317344  156224 2451864  256998 vmlinux
> [ralf@dea linux-sgi-2.4]$ mips64-linux-size vmlinux
>    text    data     bss     dec     hex filename
> 1761168  317344  156224 2234736  221970 vmlinux
> 
> The first kernel was built as 64-bit ELF using 64-bit pointer and everything
> 64-bit.  The second kernel was built using the -Wa,-32 trick.  That's over
> 12% of bloat for full 64-bitiness which brings zero gain.

Percentages are dangerous things.  This is 220Kbytes of memory, which
currently represents an investment of about $0.05.  There may be
embedded linux applications which care about 5c cost, but they
probably won't use any variety of 64 bits...


From macro@ds2.pg.gda.pl Fri Dec  6 19:33:20 2002
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On Fri, 6 Dec 2002, Thiemo Seufer wrote:

> Maybe I wasn't clear about it, I meant kernels with 32 bit address
> space but 64 bit register width, allowing for userland N32 ABI.
> 
> E.g. the old DECstations with R4k CPU and limited memory would fit
> in this scheme. :-)

 I'm only going to support n64 on the DECstation.  You are welcomed to do
n32 stuff yourself if you want to. 

> >  Remember we are writing of the kernel -- we don't know what userland is
> > going to bring us
> 
> I don't understand this. The kernel _defines_ what the userland is allowed
> to do.

 I haven't considered you may mean crippling the available user address
space.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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On Fri, Dec 06, 2002 at 06:18:22PM +0000, Dominic Sweetman wrote:

> Percentages are dangerous things.  This is 220Kbytes of memory, which
> currently represents an investment of about $0.05.  There may be
> embedded linux applications which care about 5c cost, but they
> probably won't use any variety of 64 bits...

It's not the 5 cents, it's the slowdown of executing extra code.

-- greg


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Maciej W. Rozycki wrote:
> On Fri, 6 Dec 2002, Thiemo Seufer wrote:
> 
> > Maybe I wasn't clear about it, I meant kernels with 32 bit address
> > space but 64 bit register width, allowing for userland N32 ABI.
> > 
> > E.g. the old DECstations with R4k CPU and limited memory would fit
> > in this scheme. :-)
> 
>  I'm only going to support n64 on the DECstation.  You are welcomed to do
> n32 stuff yourself if you want to. 

What does N64 on the DECstation better than N32 could do? N32 has
more compact code, better cache usage and less memory consumption.

> > >  Remember we are writing of the kernel -- we don't know what userland is
> > > going to bring us
> > 
> > I don't understand this. The kernel _defines_ what the userland is allowed
> > to do.
> 
>  I haven't considered you may mean crippling the available user address
> space.

IIRC is the maximum of RAM 448 MB on some machines. Actually utilizing
an user address space larger than 2 GB would mean a RAM/Swap ratio of
about 1:4, IOW, it likely gets unusable slow.

Is there any point besides of hack value to use N64 on these machines?


Thiemo

From macro@ds2.pg.gda.pl Fri Dec  6 20:01:33 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
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On Fri, 6 Dec 2002, Thiemo Seufer wrote:

> >  I'm only going to support n64 on the DECstation.  You are welcomed to do
> > n32 stuff yourself if you want to. 
> 
> What does N64 on the DECstation better than N32 could do? N32 has
> more compact code, better cache usage and less memory consumption.

 Well, as you probably noticed, the DECstation is not a performance
screamer anymore.  If I needed a fast system, I'd use something else.  I
need a reference platform, though, even if it costs performance.

> >  I haven't considered you may mean crippling the available user address
> > space.
> 
> IIRC is the maximum of RAM 448 MB on some machines. Actually utilizing

 For the record, it's 480MB, actually (15 * 32MB). 

> an user address space larger than 2 GB would mean a RAM/Swap ratio of
> about 1:4, IOW, it likely gets unusable slow.

 That depends on the utility of swap -- it's usually slow, although not
always. 

> Is there any point besides of hack value to use N64 on these machines?

 Probably not.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From hartvige@mips.com Fri Dec  6 23:30:14 2002
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Subject: Re: possible Malta 4Kc cache problem ...
To: macro@ds2.pg.gda.pl (Maciej W. Rozycki)
Date: Fri, 6 Dec 2002 23:24:32 +0100 (CET)
Cc: carstenl@mips.com (Carsten Langgaard),
	kevink@mips.com (Kevin D. Kissell), linux-mips@linux-mips.org
In-Reply-To: <Pine.GSO.3.96.1021206174020.26674P-100000@delta.ds2.pg.gda.pl> from "Maciej W. Rozycki" at Dec 06, 2002 05:42:41 
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The documents are provided to all core customers, and our marketing dept
has decided that nobody else needs them :-)

As we now have a case which clearly proves otherwise, maybe somebody
should reopen this discussion internally in MIPS? Dominic, do you want
to volunteer?

/Hartvig

Maciej W. Rozycki writes:
> 
> On Thu, 5 Dec 2002, Carsten Langgaard wrote:
> 
> > There is what the errata sheet says:
> 
>  Is the errata doc available from anywhere?  Actually are such docs
> available for any of your current (recent) processor products? 
> 
> -- 
> +  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
> +--------------------------------------------------------------+
> +        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

From ralf@linux-mips.org Sat Dec  7 00:19:21 2002
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From: Ralf Baechle <ralf@linux-mips.org>
To: Dominic Sweetman <dom@algor.co.uk>
Cc: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>,
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References: <20021206135110.GD23743@rembrandt.csv.ica.uni-stuttgart.de> <Pine.GSO.3.96.1021206165118.26674N-100000@delta.ds2.pg.gda.pl> <20021206164558.GH23743@rembrandt.csv.ica.uni-stuttgart.de> <20021206180241.A7492@linux-mips.org> <15856.59886.661994.493446@gladsmuir.algor.co.uk>
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On Fri, Dec 06, 2002 at 06:18:22PM +0000, Dominic Sweetman wrote:

> > The first kernel was built as 64-bit ELF using 64-bit pointer and everything
> > 64-bit.  The second kernel was built using the -Wa,-32 trick.  That's over
> > 12% of bloat for full 64-bitiness which brings zero gain.
> 
> Percentages are dangerous things.  This is 220Kbytes of memory, which
> currently represents an investment of about $0.05.  There may be
> embedded linux applications which care about 5c cost, but they
> probably won't use any variety of 64 bits...

I'd worry less if that was just 220kB of unused memory wasted.  But it's
actually inflated code, it's wasted i-cache and cycles.  220kB translates
to alost 7 times the size of today's typical 32kB i-cache.

Even if Thiemo was right this trick is probably the biggest micro-
optimization of the decade ...

  Ralf

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Ralf Baechle wrote:
> On Fri, Dec 06, 2002 at 06:18:22PM +0000, Dominic Sweetman wrote:
> 
> > > The first kernel was built as 64-bit ELF using 64-bit pointer and everything
> > > 64-bit.  The second kernel was built using the -Wa,-32 trick.  That's over
> > > 12% of bloat for full 64-bitiness which brings zero gain.
> > 
> > Percentages are dangerous things.  This is 220Kbytes of memory, which
> > currently represents an investment of about $0.05.  There may be
> > embedded linux applications which care about 5c cost, but they
> > probably won't use any variety of 64 bits...
> 
> I'd worry less if that was just 220kB of unused memory wasted.  But it's
> actually inflated code, it's wasted i-cache and cycles.  220kB translates
> to alost 7 times the size of today's typical 32kB i-cache.
> 
> Even if Thiemo was right this trick is probably the biggest micro-
> optimization of the decade ...

Even if it was such a big win it would IMHO be better to use N64 and
teach the assembler some optimization for such register loads.
-Wa,--sign-extend-immediates shouldn't be that complicated to implement.


Thiemo

From ralf@linux-mips.org Sat Dec  7 01:00:40 2002
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On Sat, Dec 07, 2002 at 12:33:37AM +0100, Thiemo Seufer wrote:

> > I'd worry less if that was just 220kB of unused memory wasted.  But it's
> > actually inflated code, it's wasted i-cache and cycles.  220kB translates
> > to alost 7 times the size of today's typical 32kB i-cache.
> > 
> > Even if Thiemo was right this trick is probably the biggest micro-
> > optimization of the decade ...
> 
> Even if it was such a big win it would IMHO be better to use N64 and
> teach the assembler some optimization for such register loads.
> -Wa,--sign-extend-immediates shouldn't be that complicated to implement.

The entire situation will change anyway once gcc no longer emits macro
instructions such as la or dla.

  Ralf

From brian@murphy.dk Sat Dec  7 20:42:31 2002
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Ralf Baechle wrote:

 >On Tue, Dec 03, 2002 at 01:17:27PM -0500, Daniel Jacobowitz wrote:
 >
 >
 >
 >>>cvs -d :pserver:cvs@ftp.linux-mips.org:/home/cvs co linux
 >>>
 >>>This was work some days before. How about it now? How can give me 
some thread?
 >>>
 >>>
 >>Use cvs.linux-mips.org, as was announced on the list a couple days ago.
 >>
 >>
 >
 >For a few days ftp.linux-mips.org and cvs.linux-mips.org were two 
different
 >machines.  Now they're the same machine again.  Anyway, use the cvs.*
 >hostname to avoid surprises in the future.  Near future ...
 >
 >  Ralf
 >
 >
 >
 >
It seems like the rsync server disappeared during the move. Can you make
it come
back?

/Brian



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On Sat, Dec 07, 2002 at 08:37:00PM +0100, Brian Murphy wrote:

> It seems like the rsync server disappeared during the move. Can you make
> it come
> back?

When the actual server is unwrapped again, it's now actually shipping to
the UK ...

  Ralf

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As someone rather new to this list, and to mips-linux in general,
can someone explain the problem, as well as how one can avoid 
it or limit it's effects to a minimum ?

TIA


From kevink@mips.com Sun Dec  8 11:01:21 2002
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Subject: Re: Prefetches in memcpy
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> As someone rather new to this list, and to mips-linux in general,
> can someone explain the problem, as well as how one can avoid 
> it or limit it's effects to a minimum ?

The problem is that memcpy() uses prefetch to pre-load the
cache from the copy source, but does so very naively, such
that it continues prefetching beyond the end of the block to
be copied.  This is a Bad Idea for a couple of reasons.
The first to be commented upon was the fact that it can
result in bus hangs/bus errors if the kernel is trying to copy
from the last few hundred bytes of physical memory, but 
the really nasty one is that it screws up cache coherence
for DMA I/O.

The no-brainer solution which has been proposed as a
stopgap is simply to stop doing prefetch in memcpy()
altogether.  The "correct" solution would be to have a
slightly more complex memcpy() loop which only does
prefetch up to the end of the source block, which is
what is now done in the x86 port.

From ralf@linux-mips.org Mon Dec  9 05:20:13 2002
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From: Ralf Baechle <ralf@linux-mips.org>
To: Carsten Langgaard <carstenl@mips.com>
Cc: Dominic Sweetman <dom@algor.co.uk>, chris@mips.com,
	kevink@mips.com, linux-mips@linux-mips.org
Subject: Re: The 64-bit version of __access_ok is broken.
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On Thu, Dec 05, 2002 at 04:28:07PM +0100, Carsten Langgaard wrote:

> I have addressed this issue before, and I do it again, because we have a
> potential kernel crash situation, if this isn't fixed.
> 
> The __access_ok macro in include/asm-mips64/uaccess.h and the check_axs
> macro in arch/mips64/kernel/unaligned.c need to be changed in order to
> work correctly, it's a copy from the 32-bit kernel. It's not good enough
> to simply check for the "sign bit" of the address.
> The area between USEG (XUSEG) and KSEG0 will in 64-bit addressing mode
> generate an address error, if accessed.
> The size of the area depend on the number of virtual addressing bits
> implemented in the CPU.
> 
> Please take a look at the patch below.
> I think Ralf had some objection the last time I send it, about the fix,
> not being efficient enough (performance vice), but I think we need to
> consider stability and functionality over performance. So until someone
> comes up with a better solution, I think we need this fix.

Standard Linux approach - a bad solution is worse than no solution.

Just to show the impact of your patch:

   text    data     bss     dec     hex filename
1817824 1079664  173664 3071152  2edcb0 vmlinux-cvs
1870752 1079664  173664 3124080  2fab70 vmlinux-carsten

So that's 52928 bytes of bloat.  __access_ok is one of those kernel
functions that are inlined so often that each extra instruction needs a
_very_ good justification.

The patch below adds 32 bytes.  It's still not the right thing though.  It's
not fixing all stuff in the assembler code.  I have a better patch but it
results in odd userspace behaviour.  Smells like a compiler problem ...

  Ralf

Index: arch/mips64/kernel/process.c
===================================================================
RCS file: /home/cvs/linux/arch/mips64/kernel/process.c,v
retrieving revision 1.18.2.9
diff -u -r1.18.2.9 process.c
--- arch/mips64/kernel/process.c	2 Dec 2002 00:24:52 -0000	1.18.2.9
+++ arch/mips64/kernel/process.c	7 Dec 2002 02:13:40 -0000
@@ -52,17 +52,19 @@
 void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
 {
 	unsigned long status;
+	int compat32 = current->thread.mflags & MF_32BIT;
 
 	/* New thread looses kernel privileges. */
 	status = regs->cp0_status & ~(ST0_CU0|ST0_FR|ST0_KSU);
 	status |= KSU_USER;
-	status |= (current->thread.mflags & MF_32BIT) ? 0 : ST0_FR;
+	status |= compat32 ? 0 : ST0_FR;
 	regs->cp0_status = status;
 	current->used_math = 0;
 	loose_fpu();
 	regs->cp0_epc = pc;
 	regs->regs[29] = sp;
 	current->thread.current_ds = USER_DS;
+	current->thread.user_ds.seg = - (compat32 ? 0x80000000UL : TASK_SIZE);
 }
 
 void exit_thread(void)
Index: include/asm-mips64/processor.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips64/processor.h,v
retrieving revision 1.32.2.9
diff -u -r1.32.2.9 processor.h
--- include/asm-mips64/processor.h	4 Nov 2002 19:39:56 -0000	1.32.2.9
+++ include/asm-mips64/processor.h	7 Dec 2002 02:14:10 -0000
@@ -180,7 +180,7 @@
 #define MF_LOGADE 2			/* Log address errors to syslog */
 #define MF_32BIT  4			/* Process is in 32-bit compat mode */
 	unsigned long mflags;
-	mm_segment_t current_ds;
+	mm_segment_t current_ds, user_ds;
 	unsigned long irix_trampoline;  /* Wheee... */
 	unsigned long irix_oldctx;
 };
@@ -208,7 +208,7 @@
 	/* \
 	 * For now the default is to fix address errors \
 	 */ \
-	MF_FIXADE, { 0 }, 0, 0 \
+	MF_FIXADE, KERNEL_DS, { -TASK_SIZE }, 0, 0 \
 }
 
 #ifdef __KERNEL__
Index: include/asm-mips64/uaccess.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips64/uaccess.h,v
retrieving revision 1.13.2.1
diff -u -r1.13.2.1 uaccess.h
--- include/asm-mips64/uaccess.h	1 Jul 2002 15:27:31 -0000	1.13.2.1
+++ include/asm-mips64/uaccess.h	7 Dec 2002 02:14:10 -0000
@@ -23,7 +23,7 @@
  * For historical reasons, these macros are grossly misnamed.
  */
 #define KERNEL_DS	((mm_segment_t) { (unsigned long) 0L })
-#define USER_DS		((mm_segment_t) { (unsigned long) -1L })
+#define USER_DS		(current->thread.user_ds)
 
 #define VERIFY_READ    0
 #define VERIFY_WRITE   1
@@ -49,7 +49,7 @@
 	(__builtin_constant_p(size) && (signed long) (size) > 0 ? 0 : (size))
 
 #define __access_ok(addr,size,mask)					\
-	(((signed long)((mask)&(addr | (addr + size) | __ua_size(size)))) >= 0)
+	(((mask) & (addr | (addr + size) | __ua_size(size))) == 0)
 
 #define __access_mask ((long)(get_fs().seg))
 

From carstenl@mips.com Mon Dec  9 10:34:08 2002
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Ralf Baechle wrote:

> On Thu, Dec 05, 2002 at 04:28:07PM +0100, Carsten Langgaard wrote:
>
> > I have addressed this issue before, and I do it again, because we have a
> > potential kernel crash situation, if this isn't fixed.
> >
> > The __access_ok macro in include/asm-mips64/uaccess.h and the check_axs
> > macro in arch/mips64/kernel/unaligned.c need to be changed in order to
> > work correctly, it's a copy from the 32-bit kernel. It's not good enough
> > to simply check for the "sign bit" of the address.
> > The area between USEG (XUSEG) and KSEG0 will in 64-bit addressing mode
> > generate an address error, if accessed.
> > The size of the area depend on the number of virtual addressing bits
> > implemented in the CPU.
> >
> > Please take a look at the patch below.
> > I think Ralf had some objection the last time I send it, about the fix,
> > not being efficient enough (performance vice), but I think we need to
> > consider stability and functionality over performance. So until someone
> > comes up with a better solution, I think we need this fix.
>
> Standard Linux approach - a bad solution is worse than no solution.
>
> Just to show the impact of your patch:

>    text    data     bss     dec     hex filename
> 1817824 1079664  173664 3071152  2edcb0 vmlinux-cvs
> 1870752 1079664  173664 3124080  2fab70 vmlinux-carsten
>
> So that's 52928 bytes of bloat.

>  __access_ok is one of those kernel
> functions that are inlined so often that each extra instruction needs a
> _very_ good justification.

I really disagree.
My solution may impact the size of the kernel (the increase is less than 2
percent), but it prevent kernel crashes.
Sure we may be able to find a better solution, but it has been almost 1/2 year ago,
the last time I addressed this problem.
I know at least one other on the list was hit by this problem.


>
> The patch below adds 32 bytes.  It's still not the right thing though.  It's
> not fixing all stuff in the assembler code.  I have a better patch but it
> results in odd userspace behaviour.  Smells like a compiler problem ...

I tried you patch below, but then nothing seems to work.


>
>   Ralf
>
> Index: arch/mips64/kernel/process.c
> ===================================================================
> RCS file: /home/cvs/linux/arch/mips64/kernel/process.c,v
> retrieving revision 1.18.2.9
> diff -u -r1.18.2.9 process.c
> --- arch/mips64/kernel/process.c        2 Dec 2002 00:24:52 -0000       1.18.2.9
> +++ arch/mips64/kernel/process.c        7 Dec 2002 02:13:40 -0000
> @@ -52,17 +52,19 @@
>  void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
>  {
>         unsigned long status;
> +       int compat32 = current->thread.mflags & MF_32BIT;
>
>         /* New thread looses kernel privileges. */
>         status = regs->cp0_status & ~(ST0_CU0|ST0_FR|ST0_KSU);
>         status |= KSU_USER;
> -       status |= (current->thread.mflags & MF_32BIT) ? 0 : ST0_FR;
> +       status |= compat32 ? 0 : ST0_FR;
>         regs->cp0_status = status;
>         current->used_math = 0;
>         loose_fpu();
>         regs->cp0_epc = pc;
>         regs->regs[29] = sp;
>         current->thread.current_ds = USER_DS;
> +       current->thread.user_ds.seg = - (compat32 ? 0x80000000UL : TASK_SIZE);
>  }
>
>  void exit_thread(void)
> Index: include/asm-mips64/processor.h
> ===================================================================
> RCS file: /home/cvs/linux/include/asm-mips64/processor.h,v
> retrieving revision 1.32.2.9
> diff -u -r1.32.2.9 processor.h
> --- include/asm-mips64/processor.h      4 Nov 2002 19:39:56 -0000       1.32.2.9
> +++ include/asm-mips64/processor.h      7 Dec 2002 02:14:10 -0000
> @@ -180,7 +180,7 @@
>  #define MF_LOGADE 2                    /* Log address errors to syslog */
>  #define MF_32BIT  4                    /* Process is in 32-bit compat mode */
>         unsigned long mflags;
> -       mm_segment_t current_ds;
> +       mm_segment_t current_ds, user_ds;
>         unsigned long irix_trampoline;  /* Wheee... */
>         unsigned long irix_oldctx;
>  };
> @@ -208,7 +208,7 @@
>         /* \
>          * For now the default is to fix address errors \
>          */ \
> -       MF_FIXADE, { 0 }, 0, 0 \
> +       MF_FIXADE, KERNEL_DS, { -TASK_SIZE }, 0, 0 \
>  }
>
>  #ifdef __KERNEL__
> Index: include/asm-mips64/uaccess.h
> ===================================================================
> RCS file: /home/cvs/linux/include/asm-mips64/uaccess.h,v
> retrieving revision 1.13.2.1
> diff -u -r1.13.2.1 uaccess.h
> --- include/asm-mips64/uaccess.h        1 Jul 2002 15:27:31 -0000       1.13.2.1
> +++ include/asm-mips64/uaccess.h        7 Dec 2002 02:14:10 -0000
> @@ -23,7 +23,7 @@
>   * For historical reasons, these macros are grossly misnamed.
>   */
>  #define KERNEL_DS      ((mm_segment_t) { (unsigned long) 0L })
> -#define USER_DS                ((mm_segment_t) { (unsigned long) -1L })
> +#define USER_DS                (current->thread.user_ds)
>
>  #define VERIFY_READ    0
>  #define VERIFY_WRITE   1
> @@ -49,7 +49,7 @@
>         (__builtin_constant_p(size) && (signed long) (size) > 0 ? 0 : (size))
>
>  #define __access_ok(addr,size,mask)                                    \
> -       (((signed long)((mask)&(addr | (addr + size) | __ua_size(size)))) >= 0)
> +       (((mask) & (addr | (addr + size) | __ua_size(size))) == 0)
>
>  #define __access_mask ((long)(get_fs().seg))
>

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From dom@algor.co.uk Mon Dec  9 11:53:07 2002
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	carstenl@mips.com (Carsten Langgaard),
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Subject: Re: possible Malta 4Kc cache problem ...
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Hartvig,

> As we now have a case which clearly proves otherwise, maybe somebody
> should reopen this discussion internally in MIPS? Dominic, do you want
> to volunteer?

I am stirring...

--
Dominic


From dom@algor.co.uk Mon Dec  9 12:55:41 2002
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> > > The __access_ok macro in include/asm-mips64/uaccess.h and the
> > > check_axs macro in arch/mips64/kernel/unaligned.c ... is a copy
> > > from the 32-bit kernel...
> > >
> > > The area between USEG (XUSEG) and KSEG0 will in 64-bit
> > > addressing mode generate an address error, if accessed.

I'd like to be clear about the consequences of this.  Presumably the
'access_ok()' macro is used to check addresses which were (originally)
provided by a user program's system call.

Carsten, are you saying that if such an address is set to say 2**41 in
a CPU supporting 40-bit user virtual addresses, that the kernel will
crash?

If so, that seems to require a fix, even if we don't know a very
efficient one.  But perhaps any problem is a bit more subtle than
that?

-- 
Dominic Sweetman
MIPS Technologies
The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND
phone +44 1223 706205/fax +44 1223 706250/swbrd +44 1223 706200
http://www.algor.co.uk



From carstenl@mips.com Mon Dec  9 13:31:50 2002
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From: Carsten Langgaard <carstenl@mips.com>
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Subject: Re: The 64-bit version of __access_ok is broken.
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		<20021209051845.A31939@linux-mips.org>
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Dominic Sweetman wrote:

> > > > The __access_ok macro in include/asm-mips64/uaccess.h and the
> > > > check_axs macro in arch/mips64/kernel/unaligned.c ... is a copy
> > > > from the 32-bit kernel...
> > > >
> > > > The area between USEG (XUSEG) and KSEG0 will in 64-bit
> > > > addressing mode generate an address error, if accessed.
>
> I'd like to be clear about the consequences of this.  Presumably the
> 'access_ok()' macro is used to check addresses which were (originally)
> provided by a user program's system call.
>
> Carsten, are you saying that if such an address is set to say 2**41 in
> a CPU supporting 40-bit user virtual addresses, that the kernel will
> crash?

Yes, that's the case.
It's been a while since I fixed it locally, but if I ran something like
crashme, I could end up, in a situation where the kernel tries (on the
behalf of the user) to access an address like 2**41 in a CPU supporting
40-bit user virtual addresses, which generate an address error and
because we are in kernel mode we die.


>
> If so, that seems to require a fix, even if we don't know a very
> efficient one.  But perhaps any problem is a bit more subtle than
> that?
>
> --
> Dominic Sweetman
> MIPS Technologies
> The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND
> phone +44 1223 706205/fax +44 1223 706250/swbrd +44 1223 706200
> http://www.algor.co.uk

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From ralf@linux-mips.org Mon Dec  9 17:36:40 2002
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From: Ralf Baechle <ralf@linux-mips.org>
To: Carsten Langgaard <carstenl@mips.com>
Cc: Dominic Sweetman <dom@algor.co.uk>, chris@mips.com,
	kevink@mips.com, linux-mips@linux-mips.org
Subject: Re: The 64-bit version of __access_ok is broken.
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On Mon, Dec 09, 2002 at 10:30:03AM +0100, Carsten Langgaard wrote:

> > The patch below adds 32 bytes.  It's still not the right thing though.  It's
> > not fixing all stuff in the assembler code.  I have a better patch but it
> > results in odd userspace behaviour.  Smells like a compiler problem ...
> 
> I tried you patch below, but then nothing seems to work.

The reason for this problem (and a few others is the broken call to
__access_ok() in clear_user().  That should actually be access_ok().
Basically the kernel was only working so far because addresses were just
right ...

Below my working version.  I still needs to make TASK_SIZE variable but
with the clear_user thing fixed that should be easy.

  Ralf

Index: arch/mips64/kernel/scall_o32.S
===================================================================
RCS file: /home/cvs/linux/arch/mips64/kernel/scall_o32.S,v
retrieving revision 1.48.2.21
diff -u -r1.48.2.21 scall_o32.S
--- arch/mips64/kernel/scall_o32.S	3 Dec 2002 14:23:05 -0000	1.48.2.21
+++ arch/mips64/kernel/scall_o32.S	8 Dec 2002 06:08:55 -0000
@@ -209,7 +209,7 @@
 	daddiu	a0, a1, 4
 	or	a0, a0, a1
 	and	a0, a0, v1
-	bltz	a0, bad_address
+	bnez	a0, bad_address
 
 	/* Ok, this is the ll/sc case.  World is sane :-)  */
 1:	ll	v0, (a1)
@@ -273,7 +273,7 @@
 	ld	v1, THREAD_CURDS($28)
 	or	v0, v0, t1
 	and	v1, v1, v0
-	bltz	v1, efault
+	bnez	v1, efault
 
 	move	a0, a1			# shift argument registers
 	move	a1, a2
Index: arch/mips64/lib/strlen_user.S
===================================================================
RCS file: /home/cvs/linux/arch/mips64/lib/strlen_user.S,v
retrieving revision 1.4.2.1
diff -u -r1.4.2.1 strlen_user.S
--- arch/mips64/lib/strlen_user.S	1 Jul 2002 15:27:29 -0000	1.4.2.1
+++ arch/mips64/lib/strlen_user.S	8 Dec 2002 06:08:55 -0000
@@ -25,7 +25,7 @@
 LEAF(__strlen_user_asm)
 	ld	v0, THREAD_CURDS($28)			# pointer ok?
 	and	v0, a0
-	bltz	v0, fault
+	bnez	v0, fault
 
 FEXPORT(__strlen_user_nocheck_asm)
 	move	v0, a0
Index: arch/mips64/lib/strncpy_user.S
===================================================================
RCS file: /home/cvs/linux/arch/mips64/lib/strncpy_user.S,v
retrieving revision 1.4
diff -u -r1.4 strncpy_user.S
--- arch/mips64/lib/strncpy_user.S	9 Jul 2001 00:25:37 -0000	1.4
+++ arch/mips64/lib/strncpy_user.S	8 Dec 2002 06:08:55 -0000
@@ -30,7 +30,7 @@
 LEAF(__strncpy_from_user_asm)
 	ld	v0, THREAD_CURDS($28)		# pointer ok?
 	and	v0, a1
-	bltz	v0, fault
+	bnez	v0, fault
 
 FEXPORT(__strncpy_from_user_nocheck_asm)
 	move	v0, zero
Index: arch/mips64/lib/strnlen_user.S
===================================================================
RCS file: /home/cvs/linux/arch/mips64/lib/strnlen_user.S,v
retrieving revision 1.2.2.2
diff -u -r1.2.2.2 strnlen_user.S
--- arch/mips64/lib/strnlen_user.S	1 Jul 2002 15:27:29 -0000	1.2.2.2
+++ arch/mips64/lib/strnlen_user.S	8 Dec 2002 06:08:55 -0000
@@ -25,7 +25,7 @@
 LEAF(__strnlen_user_asm)
 	ld	v0, THREAD_CURDS($28)	# pointer ok?
 	and	v0, a0
-	bltz	v0, fault
+	bnez	v0, fault
 
 FEXPORT(__strnlen_user_nocheck_asm)
 	move	v0, a0
Index: include/asm-mips64/processor.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips64/processor.h,v
retrieving revision 1.32.2.9
diff -u -r1.32.2.9 processor.h
--- include/asm-mips64/processor.h	4 Nov 2002 19:39:56 -0000	1.32.2.9
+++ include/asm-mips64/processor.h	8 Dec 2002 06:09:38 -0000
@@ -208,7 +208,7 @@
 	/* \
 	 * For now the default is to fix address errors \
 	 */ \
-	MF_FIXADE, { 0 }, 0, 0 \
+	MF_FIXADE, KERNEL_DS, 0, 0 \
 }
 
 #ifdef __KERNEL__
Index: include/asm-mips64/uaccess.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips64/uaccess.h,v
retrieving revision 1.13.2.1
diff -u -r1.13.2.1 uaccess.h
--- include/asm-mips64/uaccess.h	1 Jul 2002 15:27:31 -0000	1.13.2.1
+++ include/asm-mips64/uaccess.h	8 Dec 2002 06:09:39 -0000
@@ -22,8 +22,8 @@
  *
  * For historical reasons, these macros are grossly misnamed.
  */
-#define KERNEL_DS	((mm_segment_t) { (unsigned long) 0L })
-#define USER_DS		((mm_segment_t) { (unsigned long) -1L })
+#define KERNEL_DS	((mm_segment_t) { 0UL })
+#define USER_DS		((mm_segment_t) { -TASK_SIZE })
 
 #define VERIFY_READ    0
 #define VERIFY_WRITE   1
@@ -46,19 +46,19 @@
  *  - OR we are in kernel mode.
  */
 #define __ua_size(size)							\
-	(__builtin_constant_p(size) && (signed long) (size) > 0 ? 0 : (size))
+	((__builtin_constant_p(size) && (size)) > 0 ? 0 : (size))
 
-#define __access_ok(addr,size,mask)					\
-	(((signed long)((mask)&(addr | (addr + size) | __ua_size(size)))) >= 0)
+#define __access_ok(addr, size, mask)					\
+	(((mask) & ((addr) | ((addr) + (size)) | __ua_size(size))) == 0)
 
-#define __access_mask ((long)(get_fs().seg))
+#define __access_mask get_fs().seg
 
-#define access_ok(type,addr,size) \
-	__access_ok(((unsigned long)(addr)),(size),__access_mask)
+#define access_ok(type, addr, size)					\
+	__access_ok((unsigned long)(addr), (size), __access_mask)
 
 static inline int verify_area(int type, const void * addr, unsigned long size)
 {
-	return access_ok(type,addr,size) ? 0 : -EFAULT;
+	return access_ok(type, addr, size) ? 0 : -EFAULT;
 }
 
 /*
@@ -340,8 +340,8 @@
 ({								\
 	void * __cl_addr = (addr);				\
 	unsigned long __cl_size = (n);				\
-	if (__cl_size && __access_ok(VERIFY_WRITE,		\
-	       ((unsigned long)(__cl_addr)), __cl_size))	\
+	if (__cl_size && access_ok(VERIFY_WRITE,		\
+		((unsigned long)(__cl_addr)), __cl_size))	\
 		__cl_size = __clear_user(__cl_addr, __cl_size);	\
 	__cl_size;						\
 })

From jsun@orion.mvista.com Tue Dec 10 12:58:42 2002
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From: Jun Sun <jsun@mvista.com>
To: linux-mips@linux-mips.org
Cc: jsun@mvista.com
Subject: IDE module problem
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If you configure IDE support as a module (CONFIG_IDE), you
will soon find that ide-std.o and ide-no.o are missing.
This is because arch/mips/lib/Makefile says:

obj-$(CONFIG_IDE)               += ide-std.o ide-no.o


Here are the possible fixes.  I'd like to hear your feedbacks.

1) change config-shared.in file so that CONFIG_IDE only
has a binary state (y or n)

2) change Makefile so that ide-std.o and ide-no.o are always
included.  Waste about 1K for systems don't use them at all.

3) use some smart trick in Makefile so that we include those
two files only if CONFIG_IDE is 'y' or 'm'.  (How?)

Jun

From carstenl@mips.com Tue Dec 10 12:59:02 2002
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	kevink@mips.com, linux-mips@linux-mips.org
Subject: Re: The 64-bit version of __access_ok is broken.
References: <3DEF7087.B6DEA7EC@mips.com> <20021209051845.A31939@linux-mips.org> <3DF4629B.F377F711@mips.com> <15860.33900.117478.251574@gladsmuir.algor.co.uk> <20021209193808.B27999@linux-mips.org>
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Ralf Baechle wrote:

> On Mon, Dec 09, 2002 at 11:54:20AM +0000, Dominic Sweetman wrote:
>
> > I'd like to be clear about the consequences of this.  Presumably the
> > 'access_ok()' macro is used to check addresses which were (originally)
> > provided by a user program's system call.
> >
> > Carsten, are you saying that if such an address is set to say 2**41 in
> > a CPU supporting 40-bit user virtual addresses, that the kernel will
> > crash?
>
> That's correct.  The problem which Carsten diagnosed correctly was the
> assumption which has been inherited from the 32-bit kernel that the sign-
> bit makes the difference between valid userspace and kernelspace
> addresses.
>
> Linux doesn't use the supervisor mode so basically that assumption is still
> true with the except of the area 2^PHYSBITS ... 2^63-1.
>
> > If so, that seems to require a fix, even if we don't know a very
> > efficient one.  But perhaps any problem is a bit more subtle than
> > that?
>
> Access_ok is a macro which depending on kernel configuration is expanded
> hundreds, if not thousands of times throughout the kernel.  So every single
> machine instruction in access_ok will make a size difference of several
> kB.  Carsten's patch was performing pretty badly in that cathegory.  If
> access_ok wasn't used that often the issue certainly wasn't worth the fuzz.
>
> Access_ok is of course only usable in C code.  We also have a few piece of
> assembler code that access userspace and need to perform the same kind of
> address validation tests.  Carsten's patch was missing these completly.  As
> such it did only reduce the window of this bug from huge to "just" big.
>

At least I haven't hit those holes, the would have been fixed otherwise, too
;-)


>
> An efficient solution only requires fairly minor changes as you can see in
> the patch I just posted.  It doesn't even require thinking, it can be
> obtained by cut'n'paste from the Alpha code.  Alternatively the problem
> could also have been solved by forwarding address errors for the address
> range in question to the page fault handler which would have served the
> same purpose, maybe even a tad more efficient but ofuscated ...
>

I absolutely agree that we should go for an optimized solution, but we discuss
this issue 1/2 year ago, none of us, had the time to come up with a better fix
than the one I send. I'm going through my to-do list and came across this
issue again, and I just wanted to reopen the case again.
This time it annoyed you enough, so you came up with a better solution and
I achieved what I came for, so that's great ;-)
Thanks a lot. I will try you patch right away.


>
>   Ralf

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




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From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@linux-mips.org>
CC: Dominic Sweetman <dom@algor.co.uk>, chris@mips.com,
	kevink@mips.com, linux-mips@linux-mips.org
Subject: Re: The 64-bit version of __access_ok is broken.
References: <3DEF7087.B6DEA7EC@mips.com> <20021209051845.A31939@linux-mips.org> <3DF4629B.F377F711@mips.com> <20021209173626.A27999@linux-mips.org>
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Your patch seems to do the job, thanks a lot.

/Carsten


Ralf Baechle wrote:

> On Mon, Dec 09, 2002 at 10:30:03AM +0100, Carsten Langgaard wrote:
>
> > > The patch below adds 32 bytes.  It's still not the right thing though.  It's
> > > not fixing all stuff in the assembler code.  I have a better patch but it
> > > results in odd userspace behaviour.  Smells like a compiler problem ...
> >
> > I tried you patch below, but then nothing seems to work.
>
> The reason for this problem (and a few others is the broken call to
> __access_ok() in clear_user().  That should actually be access_ok().
> Basically the kernel was only working so far because addresses were just
> right ...
>
> Below my working version.  I still needs to make TASK_SIZE variable but
> with the clear_user thing fixed that should be easy.
>
>   Ralf
>
> Index: arch/mips64/kernel/scall_o32.S
> ===================================================================
> RCS file: /home/cvs/linux/arch/mips64/kernel/scall_o32.S,v
> retrieving revision 1.48.2.21
> diff -u -r1.48.2.21 scall_o32.S
> --- arch/mips64/kernel/scall_o32.S      3 Dec 2002 14:23:05 -0000       1.48.2.21
> +++ arch/mips64/kernel/scall_o32.S      8 Dec 2002 06:08:55 -0000
> @@ -209,7 +209,7 @@
>         daddiu  a0, a1, 4
>         or      a0, a0, a1
>         and     a0, a0, v1
> -       bltz    a0, bad_address
> +       bnez    a0, bad_address
>
>         /* Ok, this is the ll/sc case.  World is sane :-)  */
>  1:     ll      v0, (a1)
> @@ -273,7 +273,7 @@
>         ld      v1, THREAD_CURDS($28)
>         or      v0, v0, t1
>         and     v1, v1, v0
> -       bltz    v1, efault
> +       bnez    v1, efault
>
>         move    a0, a1                  # shift argument registers
>         move    a1, a2
> Index: arch/mips64/lib/strlen_user.S
> ===================================================================
> RCS file: /home/cvs/linux/arch/mips64/lib/strlen_user.S,v
> retrieving revision 1.4.2.1
> diff -u -r1.4.2.1 strlen_user.S
> --- arch/mips64/lib/strlen_user.S       1 Jul 2002 15:27:29 -0000       1.4.2.1
> +++ arch/mips64/lib/strlen_user.S       8 Dec 2002 06:08:55 -0000
> @@ -25,7 +25,7 @@
>  LEAF(__strlen_user_asm)
>         ld      v0, THREAD_CURDS($28)                   # pointer ok?
>         and     v0, a0
> -       bltz    v0, fault
> +       bnez    v0, fault
>
>  FEXPORT(__strlen_user_nocheck_asm)
>         move    v0, a0
> Index: arch/mips64/lib/strncpy_user.S
> ===================================================================
> RCS file: /home/cvs/linux/arch/mips64/lib/strncpy_user.S,v
> retrieving revision 1.4
> diff -u -r1.4 strncpy_user.S
> --- arch/mips64/lib/strncpy_user.S      9 Jul 2001 00:25:37 -0000       1.4
> +++ arch/mips64/lib/strncpy_user.S      8 Dec 2002 06:08:55 -0000
> @@ -30,7 +30,7 @@
>  LEAF(__strncpy_from_user_asm)
>         ld      v0, THREAD_CURDS($28)           # pointer ok?
>         and     v0, a1
> -       bltz    v0, fault
> +       bnez    v0, fault
>
>  FEXPORT(__strncpy_from_user_nocheck_asm)
>         move    v0, zero
> Index: arch/mips64/lib/strnlen_user.S
> ===================================================================
> RCS file: /home/cvs/linux/arch/mips64/lib/strnlen_user.S,v
> retrieving revision 1.2.2.2
> diff -u -r1.2.2.2 strnlen_user.S
> --- arch/mips64/lib/strnlen_user.S      1 Jul 2002 15:27:29 -0000       1.2.2.2
> +++ arch/mips64/lib/strnlen_user.S      8 Dec 2002 06:08:55 -0000
> @@ -25,7 +25,7 @@
>  LEAF(__strnlen_user_asm)
>         ld      v0, THREAD_CURDS($28)   # pointer ok?
>         and     v0, a0
> -       bltz    v0, fault
> +       bnez    v0, fault
>
>  FEXPORT(__strnlen_user_nocheck_asm)
>         move    v0, a0
> Index: include/asm-mips64/processor.h
> ===================================================================
> RCS file: /home/cvs/linux/include/asm-mips64/processor.h,v
> retrieving revision 1.32.2.9
> diff -u -r1.32.2.9 processor.h
> --- include/asm-mips64/processor.h      4 Nov 2002 19:39:56 -0000       1.32.2.9
> +++ include/asm-mips64/processor.h      8 Dec 2002 06:09:38 -0000
> @@ -208,7 +208,7 @@
>         /* \
>          * For now the default is to fix address errors \
>          */ \
> -       MF_FIXADE, { 0 }, 0, 0 \
> +       MF_FIXADE, KERNEL_DS, 0, 0 \
>  }
>
>  #ifdef __KERNEL__
> Index: include/asm-mips64/uaccess.h
> ===================================================================
> RCS file: /home/cvs/linux/include/asm-mips64/uaccess.h,v
> retrieving revision 1.13.2.1
> diff -u -r1.13.2.1 uaccess.h
> --- include/asm-mips64/uaccess.h        1 Jul 2002 15:27:31 -0000       1.13.2.1
> +++ include/asm-mips64/uaccess.h        8 Dec 2002 06:09:39 -0000
> @@ -22,8 +22,8 @@
>   *
>   * For historical reasons, these macros are grossly misnamed.
>   */
> -#define KERNEL_DS      ((mm_segment_t) { (unsigned long) 0L })
> -#define USER_DS                ((mm_segment_t) { (unsigned long) -1L })
> +#define KERNEL_DS      ((mm_segment_t) { 0UL })
> +#define USER_DS                ((mm_segment_t) { -TASK_SIZE })
>
>  #define VERIFY_READ    0
>  #define VERIFY_WRITE   1
> @@ -46,19 +46,19 @@
>   *  - OR we are in kernel mode.
>   */
>  #define __ua_size(size)                                                        \
> -       (__builtin_constant_p(size) && (signed long) (size) > 0 ? 0 : (size))
> +       ((__builtin_constant_p(size) && (size)) > 0 ? 0 : (size))
>
> -#define __access_ok(addr,size,mask)                                    \
> -       (((signed long)((mask)&(addr | (addr + size) | __ua_size(size)))) >= 0)
> +#define __access_ok(addr, size, mask)                                  \
> +       (((mask) & ((addr) | ((addr) + (size)) | __ua_size(size))) == 0)
>
> -#define __access_mask ((long)(get_fs().seg))
> +#define __access_mask get_fs().seg
>
> -#define access_ok(type,addr,size) \
> -       __access_ok(((unsigned long)(addr)),(size),__access_mask)
> +#define access_ok(type, addr, size)                                    \
> +       __access_ok((unsigned long)(addr), (size), __access_mask)
>
>  static inline int verify_area(int type, const void * addr, unsigned long size)
>  {
> -       return access_ok(type,addr,size) ? 0 : -EFAULT;
> +       return access_ok(type, addr, size) ? 0 : -EFAULT;
>  }
>
>  /*
> @@ -340,8 +340,8 @@
>  ({                                                             \
>         void * __cl_addr = (addr);                              \
>         unsigned long __cl_size = (n);                          \
> -       if (__cl_size && __access_ok(VERIFY_WRITE,              \
> -              ((unsigned long)(__cl_addr)), __cl_size))        \
> +       if (__cl_size && access_ok(VERIFY_WRITE,                \
> +               ((unsigned long)(__cl_addr)), __cl_size))       \
>                 __cl_size = __clear_user(__cl_addr, __cl_size); \
>         __cl_size;                                              \
>  })

--
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|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
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From carstenl@mips.com Tue Dec 10 13:07:46 2002
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Date: Tue, 10 Dec 2002 13:07:31 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: GDB patch
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--------------99A547E7E03B6EF4458E567E
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I've attached a patch for gdb-stub.c to make it work better with the
sde-gdb.
These changes should be backwards compatible with a standard gdb, so it
shouldn't break anything.
Ralf, could you please apply it.

/Carsten

--
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Index: arch/mips/kernel/gdb-stub.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/kernel/gdb-stub.c,v
retrieving revision 1.15.2.3
diff -u -r1.15.2.3 gdb-stub.c
--- arch/mips/kernel/gdb-stub.c	7 Nov 2002 01:47:45 -0000	1.15.2.3
+++ arch/mips/kernel/gdb-stub.c	10 Dec 2002 11:50:35 -0000
@@ -166,7 +166,7 @@
  * BUFMAX defines the maximum number of characters in inbound/outbound buffers
  * at least NUMREGBYTES*2 are needed for register packets
  */
-#define BUFMAX 2048
+#define BUFMAX 8192
 
 static char input_buffer[BUFMAX];
 static char output_buffer[BUFMAX];
@@ -218,7 +218,7 @@
 		 * now, read until a # or end of buffer is found
 		 */
 		while (count < BUFMAX) {
-			ch = getDebugChar() & 0x7f;
+			ch = getDebugChar();
 			if (ch == '#')
 				break;
 			checksum = checksum + ch;
@@ -324,19 +324,33 @@
  * may_fault is non-zero if we are reading from arbitrary memory, but is currently
  * not used.
  */
-static char *hex2mem(char *buf, char *mem, int count, int may_fault)
+static char *hex2mem(char *buf, char *mem, int count, int binary, int may_fault)
 {
 	int i;
 	unsigned char ch;
+	char *startadr = mem;
 
 	for (i=0; i<count; i++)
 	{
-		ch = hex(*buf++) << 4;
-		ch |= hex(*buf++);
+		if (binary) {
+			ch = *buf++;
+			if (ch == 0x7d)
+				ch = 0x20 ^ *buf++;
+		}
+		else {
+			ch = hex(*buf++) << 4;
+			ch |= hex(*buf++);
+		}
 		if (kgdb_write_byte(ch, mem++) != 0)
 			return 0;
 	}
 
+	/* 
+	 * Since we may have written to instruction space via 
+	 * the data path, the icache needs to be flushed here.
+	 */
+	flush_icache_range(startadr, count);
+
 	return mem;
 }
 
@@ -594,6 +608,7 @@
 	int length;
 	char *ptr;
 	unsigned long *stack;
+	int bflag;
 
 #if 0
 	printk("in handle_exception()\n");
@@ -695,6 +710,7 @@
 	 * Wait for input from remote GDB
 	 */
 	while (1) {
+		bflag = 0;
 		output_buffer[0] = 0;
 		getpacket(input_buffer);
 
@@ -767,6 +783,13 @@
 			break;
 
 		/*
+		 * XAA..AA,LLLL: Write LLLL escaped binary bytes at address AA.AA
+		 */
+		case 'X':
+			bflag = 1;
+			/* fall through */
+
+		/*
 		 * MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK
 		 */
 		case 'M':
@@ -776,7 +799,7 @@
 				&& *ptr++ == ','
 				&& hexToInt(&ptr, &length)
 				&& *ptr++ == ':') {
-				if (hex2mem(ptr, (char *)addr, length, 1))
+				if (hex2mem(ptr, (char *)addr, length, bflag, 1))
 					strcpy(output_buffer, "OK");
 				else
 					strcpy(output_buffer, "E03");
@@ -816,13 +839,64 @@
 		case 'k' :
 			break;		/* do nothing */
 
+		case 'R':
+			/* RNN[:SS],	Set the value of CPU register NN (size SS) */
+			/* FALL THROUGH */
+
+		case 'P':
+			/* PNN[:SS]=	Set the value of CPU register NN (size SS) */
+		{
+			int regno, regsize = 4, regval;
+			ptr = &input_buffer[1];
+
+			if (!hexToInt (&ptr, &regno))
+				goto error;
+
+			ptr++;
+			if (!hexToInt (&ptr, &regsize))
+				goto error;
+
+			if (regsize != 4)
+				goto error;
+			if (*ptr != ((input_buffer[0] == 'P') ? '=' : ','))
+				goto error;
+			ptr++;
+			if (!hex2mem (ptr, (char *)&regval, 4, 0, 0))
+				goto error;
+
+			memcpy ((char *)&regs->reg0+regno*4, &regval, 4);
+			strcpy (output_buffer, "OK");
+		}
+		break;
 
-		/*
-		 * Reset the whole machine (FIXME: system dependent)
-		 */
 		case 'r':
-			break;
+			/* rNN[:SS]	Return the value of CPU register NN (size SS) */
+		{
+			int regno, regsize = 4;
+			ptr = &input_buffer[1];
+			if (hexToInt (&ptr, &regno)) {
+				if (*ptr == ':') {
+					ptr++;
+					if (!hexToInt (&ptr, &regsize))
+						goto error;
+				}
+
+				if (regsize != 4)
+					goto error;
+				(void) mem2hex((char *)&regs->reg0+regno*4, 
+					       output_buffer, 4, 0);
+			}
+			else {
+			error:
+				strcpy(output_buffer,"E22 invalid arguments");
+			}
+		}
+		break;
 
+		case 'D':
+			putpacket("OK");
+			return;
+			/* NOTREACHED */
 
 		/*
 		 * Step to next instruction

--------------99A547E7E03B6EF4458E567E--


From kevin@gv.com.tw Tue Dec 10 13:24:34 2002
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Subject: enlarge KERNEL_STACK_SIZE
Date: Tue, 10 Dec 2002 20:25:03 +0800
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dear all,

 how to enlarge KERNEL_STACK_SIZE?

 is it enough if i only change 
 the definition of KERNEL_STACK_SIZE in include/asm-mips/processor.h ?

 best regards,


From ralf@linux-mips.org Tue Dec 10 13:35:50 2002
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Date: Tue, 10 Dec 2002 13:35:36 +0100
From: Ralf Baechle <ralf@linux-mips.org>
To: ?? <kevin@gv.com.tw>
Cc: linux-mips@linux-mips.org
Subject: Re: enlarge KERNEL_STACK_SIZE
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On Tue, Dec 10, 2002 at 08:25:03PM +0800, ?? wrote:

>  how to enlarge KERNEL_STACK_SIZE?
> 
>  is it enough if i only change 
>  the definition of KERNEL_STACK_SIZE in include/asm-mips/processor.h ?

No, other changes would be needed also.  HOWEVER:  It's a very bad idea.
Stacks larger than 8kB require allocation of order 2 or even bigger
pages which will make the kernel unreliable.  I really recommend to stick
with the current 8kB stacks.

  Ralf

From ralf@linux-mips.org Tue Dec 10 13:40:45 2002
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From: Ralf Baechle <ralf@linux-mips.org>
To: Carsten Langgaard <carstenl@mips.com>
Cc: Dominic Sweetman <dom@algor.co.uk>,
	Dominic Sweetman <dom@mips.com>, chris@mips.com,
	kevink@mips.com, linux-mips@linux-mips.org
Subject: Re: The 64-bit version of __access_ok is broken.
Message-ID: <20021210134030.B17306@linux-mips.org>
References: <3DEF7087.B6DEA7EC@mips.com> <20021209051845.A31939@linux-mips.org> <3DF4629B.F377F711@mips.com> <15860.33900.117478.251574@gladsmuir.algor.co.uk> <20021209193808.B27999@linux-mips.org> <3DF59CDF.DC160221@mips.com>
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In-Reply-To: <3DF59CDF.DC160221@mips.com>; from carstenl@mips.com on Tue, Dec 10, 2002 at 08:50:55AM +0100
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On Tue, Dec 10, 2002 at 08:50:55AM +0100, Carsten Langgaard wrote:

> I absolutely agree that we should go for an optimized solution, but we discuss
> this issue 1/2 year ago, none of us, had the time to come up with a better fix
> than the one I send. I'm going through my to-do list and came across this
> issue again, and I just wanted to reopen the case again.
> This time it annoyed you enough, so you came up with a better solution and
> I achieved what I came for, so that's great ;-)
> Thanks a lot. I will try you patch right away.

It's already in CVS.

Btw, a missconfigured firewall turned linux-mips.org into a heating for the
server room last night.  This should be fixed now.  The machine is now
hosted at MIPS UK, formerly Algorithmics.  There should be no user visible
changes.

  Ralf

From carstenl@mips.com Tue Dec 10 14:44:23 2002
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Date: Tue, 10 Dec 2002 14:44:10 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: EJTAG and NMI handler broken
References: <3DEF57C5.172E8E66@mips.com>
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Ralf, did you ever take a look on my previous mail (patch).
I have added few extra things, used by MIPS32/MIPS64 compliant CPUs.
Please take a look at the attached patch.

/Carsten



Carsten Langgaard wrote:

> The EJTAG and NMI handler are broken in the 32-bit kernel, because they
> are laying in the __INIT section, which is removed after boot.
> The handlers are missing in the 64-bit kernel.
> The attached patch will fix that.
>
> /Carsten
>
> --
> _    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark            http://www.mips.com
>
>   ------------------------------------------------------------------------
> Index: arch/mips/kernel/head.S
> ===================================================================
> RCS file: /home/cvs/linux/arch/mips/kernel/head.S,v
> retrieving revision 1.29.2.14
> diff -u -r1.29.2.14 head.S
> --- arch/mips/kernel/head.S     5 Aug 2002 23:53:33 -0000       1.29.2.14
> +++ arch/mips/kernel/head.S     5 Dec 2002 13:32:24 -0000
> @@ -92,34 +92,6 @@
>                 END(except_vec_ejtag_debug)
>
>                 /*
> -                * EJTAG debug exception handler.
> -                */
> -               NESTED(ejtag_debug_handler, PT_SIZE, sp)
> -               .set    noat
> -               .set    noreorder
> -               mtc0    k0, CP0_DESAVE
> -               mfc0    k0, CP0_DEBUG
> -
> -               sll     k0, k0, 30      # Check for SDBBP.
> -               bgez    k0, ejtag_return
> -
> -               la      k0, ejtag_debug_buffer
> -               sw      k1, 0(k0)
> -               SAVE_ALL
> -               jal     ejtag_exception_handler
> -                move   a0, sp
> -               RESTORE_ALL
> -               la      k0, ejtag_debug_buffer
> -               lw      k1, 0(k0)
> -
> -ejtag_return:
> -               mfc0    k0, CP0_DESAVE
> -               .word   0x4200001f     # DERET, return from EJTAG debug exception.
> -                nop
> -               .set    at
> -               END(ejtag_debug_handler)
> -
> -               /*
>                 * NMI debug exception handler for MIPS reference boards.
>                 * The NMI debug exception entry point is 0xbfc00000, which
>                 * normally is in the boot PROM, so the boot PROM must do a
> @@ -130,19 +102,6 @@
>                  nop
>                 END(except_vec_nmi)
>
> -               NESTED(nmi_handler, PT_SIZE, sp)
> -               .set    noat
> -               .set    noreorder
> -               .set    mips3
> -               SAVE_ALL
> -               jal     nmi_exception_handler
> -                move   a0, sp
> -               RESTORE_ALL
> -               eret
> -               .set    at
> -               .set    mips0
> -               END(nmi_handler)
> -
>                 /*
>                  * Kernel entry point
>                  */
> @@ -199,10 +158,52 @@
>                 __FINIT
>
>                 /*
> +                * EJTAG debug exception handler.
> +                */
> +               NESTED(ejtag_debug_handler, PT_SIZE, sp)
> +               .set    noat
> +               .set    noreorder
> +               mtc0    k0, CP0_DESAVE
> +               mfc0    k0, CP0_DEBUG
> +
> +               sll     k0, k0, 30      # Check for SDBBP.
> +               bgez    k0, ejtag_return
> +
> +               la      k0, ejtag_debug_buffer
> +               sw      k1, 0(k0)
> +               SAVE_ALL
> +               jal     ejtag_exception_handler
> +                move   a0, sp
> +               RESTORE_ALL
> +               la      k0, ejtag_debug_buffer
> +               lw      k1, 0(k0)
> +
> +ejtag_return:
> +               mfc0    k0, CP0_DESAVE
> +               .word   0x4200001f     # DERET, return from EJTAG debug exception.
> +                nop
> +               .set    at
> +               END(ejtag_debug_handler)
> +
> +               NESTED(nmi_handler, PT_SIZE, sp)
> +               .set    noat
> +               .set    noreorder
> +               .set    mips3
> +               SAVE_ALL
> +               jal     nmi_exception_handler
> +                move   a0, sp
> +               RESTORE_ALL
> +               eret
> +               .set    at
> +               .set    mips0
> +               END(nmi_handler)
> +
> +               /*
>                  * This buffer is reserved for the use of the EJTAG debug
>                  * handler.
>                  */
>                 .data
> +               .align 2
>                 EXPORT(ejtag_debug_buffer)
>                 .fill   4
>
> Index: arch/mips64/kernel/r4k_genex.S
> ===================================================================
> RCS file: /home/cvs/linux/arch/mips64/kernel/r4k_genex.S,v
> retrieving revision 1.7.2.8
> diff -u -r1.7.2.8 r4k_genex.S
> --- arch/mips64/kernel/r4k_genex.S      2 Oct 2002 14:45:46 -0000       1.7.2.8
> +++ arch/mips64/kernel/r4k_genex.S      5 Dec 2002 13:32:25 -0000
> @@ -121,4 +121,72 @@
>  1:     j       1b                      /* Dummy, will be replaced */
>  END(except_vec4)
>
> +/*
> + * EJTAG debug exception handler.
> + * The EJTAG debug exception entry point is 0xbfc00480, which
> + * normally is in the boot PROM, so the boot PROM must do a
> + * unconditional jump to this vector.
> + */
> +NESTED(except_vec_ejtag_debug, 0, sp)
> +       j       ejtag_debug_handler
> +        nop
> +END(except_vec_ejtag_debug)
> +
> +/*
> + * NMI debug exception handler for MIPS reference boards.
> + * The NMI debug exception entry point is 0xbfc00000, which
> + * normally is in the boot PROM, so the boot PROM must do a
> + * unconditional jump to this vector.
> + */
> +NESTED(except_vec_nmi, 0, sp)
> +       j       nmi_handler
> +        nop
> +END(except_vec_nmi)
> +
>         __FINIT
> +
> +/*
> + * EJTAG debug exception handler.
> + */
> +NESTED(ejtag_debug_handler, PT_SIZE, sp)
> +       .set    noat
> +       .set    noreorder
> +       dmtc0   k0, CP0_DESAVE
> +       mfc0    k0, CP0_DEBUG
> +
> +       sll     k0, k0, 30      # Check for SDBBP.
> +       bgez    k0, ejtag_return
> +
> +       dla     k0, ejtag_debug_buffer
> +       sd      k1, 0(k0)
> +       SAVE_ALL
> +       jal     ejtag_exception_handler
> +        move   a0, sp
> +       RESTORE_ALL
> +       dla     k0, ejtag_debug_buffer
> +       ld      k1, 0(k0)
> +
> +ejtag_return:
> +       mfc0    k0, CP0_DESAVE
> +       .word   0x4200001f     # DERET, return from EJTAG debug exception.
> +        nop
> +       .set    at
> +END(ejtag_debug_handler)
> +
> +NESTED(nmi_handler, PT_SIZE, sp)
> +       .set    noat
> +       .set    noreorder
> +       SAVE_ALL
> +       jal     nmi_exception_handler
> +        move   a0, sp
> +       .set    at
> +END(nmi_handler)
> +
> +/*
> + * This buffer is reserved for the use of the EJTAG debug
> + * handler.
> + */
> +       .data
> +       .align 3
> +       EXPORT(ejtag_debug_buffer)
> +       .fill   8
> \ No newline at end of file
> Index: arch/mips64/kernel/traps.c
> ===================================================================
> RCS file: /home/cvs/linux/arch/mips64/kernel/traps.c,v
> retrieving revision 1.30.2.37
> diff -u -r1.30.2.37 traps.c
> --- arch/mips64/kernel/traps.c  2 Dec 2002 00:24:52 -0000       1.30.2.37
> +++ arch/mips64/kernel/traps.c  5 Dec 2002 13:32:25 -0000
> @@ -638,6 +638,46 @@
>         }
>  }
>
> +/*
> + * SDBBP EJTAG debug exception handler.
> + * We skip the instruction and return to the next instruction.
> + */
> +void ejtag_exception_handler(struct pt_regs *regs)
> +{
> +        unsigned long depc, old_epc;
> +       unsigned int debug;
> +
> +        printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
> +       depc = read_c0_depc();
> +        debug = read_c0_debug();
> +        printk("DEPC = %p, DEBUG = %08x\n", depc, debug);
> +        if (debug & 0x80000000) {
> +                /*
> +                 * In branch delay slot.
> +                 * We cheat a little bit here and use EPC to calculate the
> +                 * debug return address (DEPC). EPC is restored after the
> +                 * calculation.
> +                 */
> +                old_epc = regs->cp0_epc;
> +                regs->cp0_epc = depc;
> +                __compute_return_epc(regs);
> +                depc = regs->cp0_epc;
> +                regs->cp0_epc = old_epc;
> +        } else
> +                depc += 4;
> +       write_c0_depc(depc);
> +}
> +
> +/*
> + * NMI exception handler.
> + */
> +void nmi_exception_handler(struct pt_regs *regs)
> +{
> +       printk("NMI taken: ERROREPC = %p\n", read_c0_errorepc());
> +        die("NMI", regs);
> +        while(1) ;  /* We die here. */
> +}
> +
>  unsigned long exception_handlers[32];
>
>  /*
> @@ -702,6 +742,8 @@
>         extern char except_vec0_generic, except_vec2_generic;
>         extern char except_vec3_generic, except_vec3_r4000;
>         extern char except_vec4;
> +       extern char except_vec_ejtag_debug;
> +       extern char except_vec_nmi;
>         unsigned long i;
>
>         per_cpu_trap_init();
> @@ -716,6 +758,19 @@
>          */
>         for (i = 0; i <= 31; i++)
>                 set_except_vector(i, handle_reserved);
> +
> +       /*
> +        * Copy the EJTAG debug exception vector handler code to it's final
> +        * destination.
> +        */
> +       if (mips_cpu.options & MIPS_CPU_EJTAG)
> +               memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80);
> +
> +       /*
> +         * Copy the NMI exception vector handler code to it's final
> +         * destination.
> +         */
> +        memcpy((void *)(KSEG0 + 0x380), &except_vec_nmi, 0x80);
>
>         /*
>          * Only some CPUs have the watch exceptions or a dedicated

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



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Index: arch/mips/kernel/head.S
===================================================================
RCS file: /home/cvs/linux/arch/mips/kernel/head.S,v
retrieving revision 1.29.2.14
diff -u -r1.29.2.14 head.S
--- arch/mips/kernel/head.S	5 Aug 2002 23:53:33 -0000	1.29.2.14
+++ arch/mips/kernel/head.S	10 Dec 2002 13:29:55 -0000
@@ -92,34 +92,6 @@
 		END(except_vec_ejtag_debug)
 
 		/*
-		 * EJTAG debug exception handler.
-		 */
-		NESTED(ejtag_debug_handler, PT_SIZE, sp)
-		.set	noat
-		.set	noreorder
-		mtc0	k0, CP0_DESAVE
-		mfc0	k0, CP0_DEBUG
-
-		sll	k0, k0, 30	# Check for SDBBP.
-		bgez	k0, ejtag_return
-
-		la	k0, ejtag_debug_buffer
-		sw	k1, 0(k0)
-		SAVE_ALL
-		jal	ejtag_exception_handler
-		 move	a0, sp
-		RESTORE_ALL
-		la	k0, ejtag_debug_buffer
-		lw	k1, 0(k0)
-
-ejtag_return:
-		mfc0	k0, CP0_DESAVE
-		.word	0x4200001f     # DERET, return from EJTAG debug exception.
-		 nop
-		.set	at
-		END(ejtag_debug_handler)
-
-		/*
 		* NMI debug exception handler for MIPS reference boards.
 		* The NMI debug exception entry point is 0xbfc00000, which
 		* normally is in the boot PROM, so the boot PROM must do a
@@ -130,19 +102,6 @@
 		 nop
 		END(except_vec_nmi)
 
-		NESTED(nmi_handler, PT_SIZE, sp)
-		.set    noat
-		.set    noreorder
-		.set    mips3
-		SAVE_ALL
-		jal     nmi_exception_handler
-		 move   a0, sp
-		RESTORE_ALL
-		eret
-		.set    at
-		.set    mips0
-		END(nmi_handler)
-
 		/*
 		 * Kernel entry point
 		 */
@@ -199,10 +158,52 @@
 		__FINIT
 
 		/*
+		 * EJTAG debug exception handler.
+		 */
+		NESTED(ejtag_debug_handler, PT_SIZE, sp)
+		.set	noat
+		.set	noreorder
+		mtc0	k0, CP0_DESAVE
+		mfc0	k0, CP0_DEBUG
+
+		sll	k0, k0, 30	# Check for SDBBP.
+		bgez	k0, ejtag_return
+
+		la	k0, ejtag_debug_buffer
+		sw	k1, 0(k0)
+		SAVE_ALL
+		jal	ejtag_exception_handler
+		 move	a0, sp
+		RESTORE_ALL
+		la	k0, ejtag_debug_buffer
+		lw	k1, 0(k0)
+
+ejtag_return:
+		mfc0	k0, CP0_DESAVE
+		.word	0x4200001f     # DERET, return from EJTAG debug exception.
+		 nop
+		.set	at
+		END(ejtag_debug_handler)
+
+		NESTED(nmi_handler, PT_SIZE, sp)
+		.set    noat
+		.set    noreorder
+		.set    mips3
+		SAVE_ALL
+		jal     nmi_exception_handler
+		 move   a0, sp
+		RESTORE_ALL
+		eret
+		.set    at
+		.set    mips0
+		END(nmi_handler)
+		
+		/*
 		 * This buffer is reserved for the use of the EJTAG debug
 		 * handler.
 		 */
 		.data
+		.align 2
 		EXPORT(ejtag_debug_buffer)
 		.fill	4
 
Index: arch/mips/kernel/traps.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.99.2.35
diff -u -r1.99.2.35 traps.c
--- arch/mips/kernel/traps.c	4 Dec 2002 23:50:23 -0000	1.99.2.35
+++ arch/mips/kernel/traps.c	10 Dec 2002 13:29:55 -0000
@@ -733,6 +733,16 @@
 
 asmlinkage void do_mcheck(struct pt_regs *regs)
 {
+	switch(mips_cpu.cputype) {
+	case CPU_4KC:
+	case CPU_4KEC:
+	case CPU_4KSC:
+	case CPU_5KC:
+	case CPU_20KC:
+		/* Clear the TS bit in the status register. */
+		clear_c0_status(0x00200000);
+		break;
+	}
 	show_regs(regs);
 	dump_tlb_all();
 	/*
@@ -777,6 +787,12 @@
 		       "MIPS 5KC CPUs.\n");
 		write_c0_ecc(read_c0_ecc() | 0x80000000);
 		break;
+	case CPU_20KC:
+		/* Clear the DE bit (bit 16) in the CP0_STATUS register. */
+		printk(KERN_INFO "Enable the cache parity detection for "
+		       "MIPS 20KC/25KF CPUs.\n");
+		clear_c0_status(0x0001000);
+		break;
 	default:
 		break;
 	}
@@ -857,7 +873,7 @@
  */
 void nmi_exception_handler(struct pt_regs *regs)
 {
-        printk("NMI taken!!!!\n");
+        printk("NMI taken: ERROREPC = %08x\n", read_c0_errorepc());
         die("NMI", regs);
         while(1) ;  /* We die here. */
 }
@@ -945,6 +961,12 @@
 	 */
 	if (mips_cpu.options & MIPS_CPU_EJTAG)
 		memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80);
+
+	/* 
+         * Copy the NMI exception vector handler code to it's final 
+         * destination.
+         */
+        memcpy((void *)(KSEG0 + 0x380), &except_vec_nmi, 0x80);
 
 	/*
 	 * Only some CPUs have the watch exceptions or a dedicated
Index: arch/mips64/kernel/r4k_genex.S
===================================================================
RCS file: /home/cvs/linux/arch/mips64/kernel/r4k_genex.S,v
retrieving revision 1.7.2.8
diff -u -r1.7.2.8 r4k_genex.S
--- arch/mips64/kernel/r4k_genex.S	2 Oct 2002 14:45:46 -0000	1.7.2.8
+++ arch/mips64/kernel/r4k_genex.S	10 Dec 2002 13:29:57 -0000
@@ -121,4 +121,72 @@
 1:	j	1b			/* Dummy, will be replaced */
 END(except_vec4)
 
+/*
+ * EJTAG debug exception handler.
+ * The EJTAG debug exception entry point is 0xbfc00480, which
+ * normally is in the boot PROM, so the boot PROM must do a
+ * unconditional jump to this vector.
+ */	
+NESTED(except_vec_ejtag_debug, 0, sp)
+	j	ejtag_debug_handler
+	 nop
+END(except_vec_ejtag_debug)
+
+/*
+ * NMI debug exception handler for MIPS reference boards.
+ * The NMI debug exception entry point is 0xbfc00000, which
+ * normally is in the boot PROM, so the boot PROM must do a
+ * unconditional jump to this vector.
+ */
+NESTED(except_vec_nmi, 0, sp)
+	j       nmi_handler
+	 nop
+END(except_vec_nmi)
+	
 	__FINIT
+
+/*
+ * EJTAG debug exception handler.
+ */
+NESTED(ejtag_debug_handler, PT_SIZE, sp)
+	.set	noat
+	.set	noreorder
+	dmtc0	k0, CP0_DESAVE
+	mfc0	k0, CP0_DEBUG	
+
+	sll	k0, k0, 30	# Check for SDBBP.
+	bgez	k0, ejtag_return
+
+	dla	k0, ejtag_debug_buffer
+	sd	k1, 0(k0)
+	SAVE_ALL
+	jal	ejtag_exception_handler
+	 move	a0, sp
+	RESTORE_ALL
+	dla	k0, ejtag_debug_buffer
+	ld	k1, 0(k0)	
+
+ejtag_return:
+	mfc0	k0, CP0_DESAVE	
+	.word	0x4200001f     # DERET, return from EJTAG debug exception.
+	 nop
+	.set	at
+END(ejtag_debug_handler)
+	
+NESTED(nmi_handler, PT_SIZE, sp)
+	.set    noat
+	.set    noreorder
+	SAVE_ALL
+	jal     nmi_exception_handler
+	 move   a0, sp
+	.set    at
+END(nmi_handler)		
+		
+/*
+ * This buffer is reserved for the use of the EJTAG debug 
+ * handler.
+ */
+	.data
+	.align 3
+	EXPORT(ejtag_debug_buffer)
+	.fill	8
\ No newline at end of file
Index: arch/mips64/kernel/traps.c
===================================================================
RCS file: /home/cvs/linux/arch/mips64/kernel/traps.c,v
retrieving revision 1.30.2.38
diff -u -r1.30.2.38 traps.c
--- arch/mips64/kernel/traps.c	5 Dec 2002 15:01:17 -0000	1.30.2.38
+++ arch/mips64/kernel/traps.c	10 Dec 2002 13:29:59 -0000
@@ -608,6 +608,13 @@
 
 asmlinkage void do_mcheck(struct pt_regs *regs)
 {
+	switch(mips_cpu.cputype) {
+	case CPU_5KC:
+	case CPU_20KC:
+		/* Clear the TS bit in the status register. */
+		clear_c0_status(0x00200000);
+		break;
+	}
 	show_regs(regs);
 	dump_tlb_all();
 	/*
@@ -638,6 +645,46 @@
 	}
 }
 
+/*
+ * SDBBP EJTAG debug exception handler.
+ * We skip the instruction and return to the next instruction.
+ */
+void ejtag_exception_handler(struct pt_regs *regs)
+{
+        unsigned long depc, old_epc;
+	unsigned int debug;
+
+        printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
+	depc = read_c0_depc();
+        debug = read_c0_debug();
+        printk("DEPC = %p, DEBUG = %08x\n", depc, debug); 
+        if (debug & 0x80000000) {
+                /* 
+                 * In branch delay slot.
+                 * We cheat a little bit here and use EPC to calculate the
+                 * debug return address (DEPC). EPC is restored after the
+                 * calculation.
+                 */
+                old_epc = regs->cp0_epc;
+                regs->cp0_epc = depc;
+                __compute_return_epc(regs);
+                depc = regs->cp0_epc;
+                regs->cp0_epc = old_epc;
+        } else
+                depc += 4;
+	write_c0_depc(depc);
+}
+
+/*
+ * NMI exception handler.
+ */
+void nmi_exception_handler(struct pt_regs *regs)
+{
+	printk("NMI taken: ERROREPC = %p\n", read_c0_errorepc());
+        die("NMI", regs);
+        while(1) ;  /* We die here. */
+}
+
 unsigned long exception_handlers[32];
 
 /*
@@ -702,6 +749,8 @@
 	extern char except_vec0_generic, except_vec2_generic;
 	extern char except_vec3_generic, except_vec3_r4000;
 	extern char except_vec4;
+	extern char except_vec_ejtag_debug;
+	extern char except_vec_nmi;
 	unsigned long i;
 
 	per_cpu_trap_init();
@@ -716,6 +765,19 @@
 	 */
 	for (i = 0; i <= 31; i++)
 		set_except_vector(i, handle_reserved);
+
+	/* 
+	 * Copy the EJTAG debug exception vector handler code to it's final 
+	 * destination.
+	 */
+	if (mips_cpu.options & MIPS_CPU_EJTAG)
+		memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80);
+
+	/* 
+         * Copy the NMI exception vector handler code to it's final 
+         * destination.
+         */
+        memcpy((void *)(KSEG0 + 0x380), &except_vec_nmi, 0x80);
 
 	/*
 	 * Only some CPUs have the watch exceptions or a dedicated

--------------D6449356168C4402DCE212F6--


From yaelgilad@myrealbox.com Tue Dec 10 17:09:35 2002
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From: "yaelgilad" <yaelgilad@myrealbox.com>
To: <linux-mips@linux-mips.org>
Subject: R_MIPS_26 etc.
Date: Tue, 10 Dec 2002 18:11:14 +0200
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Looking in the assembly code of my driver, I see the following
pattern repeating with every function call.
    4ce4: 0c000000  jal 0
      4ce4: R_MIPS_26 rx_wait_packet
(R_MIPS_26 is sometimes replaces by a similar command)
What is R_MIPS_26 ? What are the rest of them ?
I am guessing it has to do with relocatable addresses, but this specific
function is in the same C file. Marking it as "static" does change the code
and get rid of this command.

TIA
Gilad

P.S. I am building assembler files in two different methods:
- gmake <path-to-file>.lst
- mips-linux-odjdump -x -S <path-to-C-file>  > <path-to-file.lst>
The outputs are similar but not identical.
What's the more "correct" way ?
TIA-2





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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dwindows-1255">
<META content=3D"MSHTML 6.00.2722.900" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT face=3DArial size=3D2><SPAN =
class=3D328594915-10122002>Looking in the=20
assembly code of my driver, I see the following </SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN =
class=3D328594915-10122002>pattern repeating=20
with every function call.</SPAN></FONT></DIV>
<DIV><FONT><SPAN class=3D328594915-10122002>
<DIV><FONT face=3DArial size=3D2>&nbsp;&nbsp;&nbsp; 4ce4: 0c000000&nbsp; =
jal=20
0&nbsp;</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 4ce4: =
R_MIPS_26=20
rx_wait_packet</FONT></DIV>
<DIV><FONT><SPAN class=3D328594915-10122002></SPAN><FONT face=3DArial =
size=3D2>(<SPAN=20
class=3D328594915-10122002>R_MIPS_26 is sometimes replaces by a similar=20
command)</SPAN><BR>What is R_MIPS_26 ? What are the rest of them=20
?</FONT></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D328594915-10122002>I am =
guessing it has=20
to do with relocatable addresses, but this specific</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN =
class=3D328594915-10122002>function is in the=20
same C file. Marking it as "static" does change the code =
</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D328594915-10122002>and =
get rid of this=20
command.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D328594915-10122002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D328594915-10122002>TIA</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D328594915-10122002>Gilad</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D328594915-10122002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D328594915-10122002>P.S. I =
am building=20
assembler files in two different methods:</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D328594915-10122002>- =
gmake=20
&lt;path-to-file&gt;.lst</SPAN></FONT></SPAN></FONT></DIV></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D328594915-10122002>- =
mips-linux-odjdump=20
-x -S &lt;path-to-C-file&gt;&nbsp; &gt;=20
&lt;path-to-file.lst&gt;</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN =
class=3D328594915-10122002>The&nbsp;outputs are=20
similar but not identical.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D328594915-10122002>What's =
the more=20
"correct" way ?</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D328594915-10122002>TIA-2</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D328594915-10122002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D328594915-10122002></SPAN></FONT>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV></BODY></HTML>

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From lindahl@keyresearch.com Tue Dec 10 17:20:33 2002
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From: Greg Lindahl <lindahl@keyresearch.com>
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Subject: Re: R_MIPS_26 etc.
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On Tue, Dec 10, 2002 at 06:11:14PM +0200, yaelgilad wrote:

> Looking in the assembly code of my driver, I see the following
> pattern repeating with every function call.
>     4ce4: 0c000000  jal 0
>       4ce4: R_MIPS_26 rx_wait_packet
> (R_MIPS_26 is sometimes replaces by a similar command)
> What is R_MIPS_26 ? What are the rest of them ?

R_MIPS_26 is a relocation. The jal command has 26 bits available for
the address. BTW, you should mention when you are showing objdump
output instead of the .s emitted by the compiler...

g

From drow@false.org Tue Dec 10 17:51:08 2002
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Date: Tue, 10 Dec 2002 11:51:33 -0500
From: Daniel Jacobowitz <dan@debian.org>
To: Carsten Langgaard <carstenl@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: GDB patch
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On Tue, Dec 10, 2002 at 01:07:31PM +0100, Carsten Langgaard wrote:
> I've attached a patch for gdb-stub.c to make it work better with the
> sde-gdb.
> These changes should be backwards compatible with a standard gdb, so it
> shouldn't break anything.
> Ralf, could you please apply it.

Strongly object.  While I didn't check the implementation, it's nice to
see 'X' implemented.  And P.  But what the heck is this?

> @@ -816,13 +839,64 @@
>  		case 'k' :
>  			break;		/* do nothing */
>  
> +		case 'R':
> +			/* RNN[:SS],	Set the value of CPU register NN (size SS) */
> +			/* FALL THROUGH */

> -		/*
> -		 * Reset the whole machine (FIXME: system dependent)
> -		 */
>  		case 'r':
> -			break;
> +			/* rNN[:SS]	Return the value of CPU register NN (size SS) */


We're not making up a protocol here, we're implementing one.  R and r
don't have anything to do with setting registers.

> +		case 'D':
> +			putpacket("OK");
> +			return;
> +			/* NOTREACHED */
>  
>  		/*
>  		 * Step to next instruction

'D' should generally resume the machine, by the way.

-- 
Daniel Jacobowitz
MontaVista Software                         Debian GNU/Linux Developer

From ilya@gateway.total-knowledge.com Tue Dec 10 20:11:28 2002
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From: ilya@theIlya.com
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
Subject: O2 VICE support
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Attached is patch set to add support to kernel for O2 video compression engine
(VICE). It should apply cleanly to latest CVS.

	Ilya.


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Index: arch/mips64/kernel/ioctl32.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /home/cvs/linux/arch/mips64/kernel/ioctl32.c,v
retrieving revision 1.26
diff -u -r1.26 ioctl32.c
--- arch/mips64/kernel/ioctl32.c	12 Nov 2002 15:26:11 -0000	1.26
+++ arch/mips64/kernel/ioctl32.c	10 Dec 2002 17:02:29 -0000
@@ -55,6 +57,10 @@
=20
 #include <linux/rtc.h>
=20
+#ifdef CONFIG_O2_VICE
+#include <linux/vice.h>
+#endif
+
 long sys_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg);
=20
 static int w_long(unsigned int fd, unsigned int cmd, unsigned long arg)
@@ -827,6 +968,12 @@
 COMPATIBLE_IOCTL(TIOCGSERIAL)
 COMPATIBLE_IOCTL(TIOCSSERIAL)
 COMPATIBLE_IOCTL(TIOCSERGETLSR)
+#ifdef CONFIG_O2_VICE
+COMPATIBLE_IOCTL(VICE_IOCTL_MAP_DMA)
+COMPATIBLE_IOCTL(VICE_IOCTL_MSP_RUN)
+COMPATIBLE_IOCTL(VICE_IOCTL_BSP_RUN)
+COMPATIBLE_IOCTL(VICE_IOCTL_DO_DMA)
+#endif
=20
 COMPATIBLE_IOCTL(FIOCLEX)
 COMPATIBLE_IOCTL(FIONCLEX)
Index: drivers/char/Kconfig
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /home/cvs/linux/drivers/char/Kconfig,v
retrieving revision 1.1
diff -u -r1.1 Kconfig
--- drivers/char/Kconfig	2 Nov 2002 20:01:57 -0000	1.1
+++ drivers/char/Kconfig	10 Dec 2002 17:02:31 -0000
@@ -1281,6 +1281,8 @@
=20
 source "drivers/char/pcmcia/Kconfig"
=20
+source drivers/char/o2vice/Kconfig
+
 config MWAVE
 	tristate "ACP Modem (Mwave) support"
 	depends on X86
Index: drivers/char/Makefile
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /home/cvs/linux/drivers/char/Makefile,v
retrieving revision 1.100
diff -u -r1.100 Makefile
--- drivers/char/Makefile	12 Nov 2002 15:03:11 -0000	1.100
+++ drivers/char/Makefile	10 Dec 2002 17:02:31 -0000
@@ -111,6 +111,7 @@
 obj-$(CONFIG_AGP) +=3D agp/
 obj-$(CONFIG_DRM) +=3D drm/
 obj-$(CONFIG_PCMCIA) +=3D pcmcia/
+obj-$(CONFIG_O2_VICE) +=3D o2vice/
=20
 # Files generated that shall be removed upon make clean
 clean-files :=3D consolemap_deftbl.c defkeymap.c qtronixmap.c
--- /dev/null	Sun Jul 17 16:46:18 1994
+++ drivers/char/o2vice/Kconfig	Sat Nov  2 14:10:16 2002
@@ -0,0 +1,32 @@
+#
+# O2 VICE Engine confiuration
+#
+
+config O2_VICE
+    tristate "O2 VICE Engine Support"
+    depends on SGI_IP32
+    ---help---
+      This option enables O2 VICE Engine support.
+      VICE stands for Video Image Compression Engine. This is very powerfu=
ll
+      piece of silicon, that can greatly speed up lots of graphics, vide, =
or
+      sound related tasks. To be able to use it, you will also need special
+      library, that can be found at <insert URL here>
+
+config O2_VICE_DBGG
+    bool "VICE Debugger Support. READ HELP!"
+    depends on O2_VICE
+    ---help---
+      This option enables features of VICE driver needed to debug VICE lib=
rary.
+      This is probably serious security risk. You don't need it. If you th=
ink
+      you do, you are wrong. Say NO.
+
+config O2_VICE_DBG
+    bool "You seem to insist... did you read help? Yes? No? READ HELP!"
+    depends on O2_VICE_DBGG
+    ---help---
+      You are still here? Didn't I just tell you that it is not needed?
+      Or do you want to say you *legally* obtained information needed for
+      programming VICE? That you got all the tools needed? As a matter of
+      fact, these tools don't even exist yet!
+
+      Sigh... You've been warned...
--- /dev/null	Sun Jul 17 16:46:18 1994
+++ drivers/char/o2vice/Makefile	Thu Sep 12 00:12:16 2002
@@ -0,0 +1,21 @@
+#
+# drivers/char/o2vice/Makefile
+#
+# Makefile for the O2 VICE Engine driver.
+#
+
+SUB_DIRS     :=3D=20
+MOD_SUB_DIRS :=3D $(SUB_DIRS)
+ALL_SUB_DIRS :=3D $(SUB_DIRS)
+
+#O_TARGET :=3D vice.o
+
+obj-y		:=3D
+obj-m		:=3D
+obj-n		:=3D
+obj-		:=3D
+
+obj-$(CONFIG_O2_VICE)	+=3D main.o msp.o bsp.o dma.o
+#obj-$(CONFIG_O2_VICE_DBG) +=3D vicedebug.o
+
+include $(TOPDIR)/Rules.make
--- /dev/null	Sun Jul 17 16:46:18 1994
+++ include/linux/vice.h	Tue Dec 10 09:51:46 2002
@@ -0,0 +1,462 @@
+/*
+ * vice.h -- definitions for the SGI O2 VICE
+ *
+ * The code used as a template for 'vice' driver
+ * came from the book "Linux Device Drivers" by
+ * Alessandro Rubini and Jonathan Corbet,
+ * published by O'Reilly & Associates
+ *
+ * Copyright (C) 2002 Ilya Volynets
+ *      Development was sponsored by Total Knowledge
+ *      http://www.total-knowledge.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+ * 09.16.2002 - iluxa
+ *     - MSP and DMA units mostly work.
+ *     - Simple ioctl interface to managing I/O buffers (just 2 4M buffers)
+ */
+
+#ifndef _VICE_H_
+#define _VICE_H_
+
+#include <linux/ioctl.h> /* needed for the _IOW etc stuff used later */
+#ifdef __KERNEL__
+#include <asm/pci.h>
+#endif
+#include <linux/types.h>	/* size_t */
+
+#ifndef __KERNEL__
+typedef __u64 u64;
+typedef __u32 u32;
+typedef __u16 u16;
+#endif /* __KERNEL */
+
+/*
+ * Macros to help debugging
+ */
+
+#ifdef __KERNEL__
+
+#define VICE_DEBUG 1
+
+#undef DPRINTK             /* undef it, just in case */
+#ifdef VICE_DEBUG
+# define DPRINTK(fmt, args...) printk( KERN_DEBUG "vice: " fmt, ## args)
+#else
+# define DPRINTK(fmt, args...) /* not debugging: nothing */
+#endif
+
+#define PDEBUG DPRINTK
+
+#ifndef VICE_MAJOR
+#define VICE_MAJOR 240   /* dynamic major by default */
+#endif
+
+#define VICE_VICE 0 /* main vice device, debug, stream data through, etc. =
*/
+
+#define VICE_MAX_TYPE 1 /* always define it to be max possible minor nr fo=
r this driver */
+
+
+#include <linux/devfs_fs_kernel.h>
+
+#include <asm/ip32/crime.h>
+
+extern devfs_handle_t vice_devfs_dir;
+/*
+ * Prototypes for shared functions
+ */
+ssize_t vice_read (struct file *filp, char *buf, size_t count,
+                    loff_t *f_pos);
+ssize_t vice_write (struct file *filp, const char *buf, size_t count,
+                     loff_t *f_pos);
+loff_t  vice_llseek (struct file *filp, loff_t off, int whence);
+int     vice_ioctl (struct inode *inode, struct file *filp,
+                     unsigned int cmd, unsigned long arg);
+#endif /* __KERNEL__ */
+
+#define VICE_MAX_DMA_BUFFERS	1024		/* Max number of VICE_PAGE_SIZE pages t=
hat can be MMAPed by userland */
+						/* Affects size of page table */
+
+#define VICE_BASE	0x17000000 		/*Physical address...*/
+#define VICE_REG(reg)	(VICE_BASE|(reg))	/*access vice register*/
+#define VICE_IO_MAX_OFFSET	0xEFFF		/* Max offset mapped to registers (TLB =
is *not* accessible to userspace) */
+#define VICE_MIN_OFFSET	0x10000			/* Min offset mapped to RAM */
+#define VICE_MAX_OFFSET	VICE_MIN_OFFSET+0x800000/* Max offset mapped to RA=
M */
+
+#ifndef BIT
+#define BIT(x)	(0x1<<x)
+#endif /* !defined BIT */
+/*
+ * VICE Register definitions
+ */
+
+#define VICE_ID		0x0008 /* VICE revision id		size 8  ro */
+#define VICE_CFG	0xE000 /* VICE config register		size 16 rw */
+#define VICE_INT_RESET	0xE008 /* VICE reset interrupt		size 9  wo */
+#define VICE_INT_EN	0xE010 /* VICE interrupt enable		size 9  rw */
+#define HST_BSP_IN_BOX	0x0028 /* Host copy of BSP/MSP inbox	size 16 ro */
+#define HST_BSP_OUT_BOX	0x0030 /* Host copy of BSP/MSP outbox	size 16 ro */
+#define MSP_CTL_STAT	0x0040 /* MSP Control/Status register	size 32 rw */
+#define MSP_EXPT_FLAG	0x0048 /* MSP Exception flag		size 32 rw */
+#define MSP_PC		0x0050 /* MSP Program Counter		size 32 rw */
+#define MSP_BAD_ADDR	0x0058 /* MSP Bad Address		size 32 ro */
+#define MSP_WATCH_POINT	0x0060 /* MSP Watch Point address	size 32 rw */
+#define MSP_EPC		0x0068 /* MSP Exception PC		size 32 ro */
+#define MSP_CAUSE	0x0070 /* MSP Exception Cause		size 32 ro */
+#define BSP_RPAGE	0x0078 /* BSP R Page			size 16 rw */
+#define BSP_SW_INT	0x0080 /* BSP Software Interrupt	size 0  wo */
+#define MSP_D_RAM	0x0100 /* MSP Data RAM Arbitration register size 32 rw */
+#define VICEMSP_COUNT	0x0108 /* MSP Free Running Counter	size 32 ro */
+#define BSP_CTL_STAT	0x0110 /* BSP Control/Status register	size 16 rw */
+#define BSP_WATCH_POINT	0x0118 /* BSP Watch Point		size 16 rw */
+#define BSP_IN_COUNT	0x0120 /* BSP Decoded Bits counter	size 24 ro */
+#define BSP_OUT_COUNT	0x0128 /* BSP Encoded Bits counter	size 24 ro */
+#define BSP_PC		0x0140 /* BSP Program Counter		size 16 rw */
+#define BSP_EPC		0x0148 /* BSP Exception PC		size 16 rw */
+#define BSP_HALT_RESET	0x0150 /* BSP Halt/Reset Register	size 2  ro */
+#define BSP_CAUSE	0x0158 /* BSP Exception Cause		size 16 ro */
+#define VICE_INT	0x0160 /* Interruot and Status		size 9  ro */
+#define BSP_FIFO_CTL_STAT 0x0168 /* BSP FIFO Control/Status	size 6  rw */
+/* 0x170, 0x178 -?? */
+#define DMA_CH1_CTL	0x0180 /* DMA Chennel 1 Control		size 16 rw */
+#define DMA_CH1_STAT	0x0188 /* DMA Channel 1 Status		size 16 ro */
+#define DMA_CH1_DATA	0x0190 /* DMA Channel 1 Fill Pattern	size 16 rw */
+#define DMA_CH1_MEM_PTR	0x0198 /* DMA Channel 1 Sys Mem Ptr	size 32 ro */
+#define DMA_CH1_VICE_PTR 0x01A0 /* DMA Channel 1 VICE Mem Ptr	size 16 ro */
+#define DMA_CH1_COUNT	0x01A8 /* DMA Channel 1 remaining count	size 16 ro */
+/*0x01B0 -- unused */
+#define MSP_SW_INT	0x01B8 /* MSP Software Interrupt	size 0  wo */
+#define DMA_CH2_CTL	0x01C0 /* DMA Chennel 2 Control		size 16 rw */
+#define DMA_CH2_STAT	0x01C8 /* DMA Channel 2 Status		size 16 ro */
+#define DMA_CH2_DATA	0x01D0 /* DMA Channel 2 Fill Pattern	size 16 rw */
+#define DMA_CH2_MEM_PTR	0x01D8 /* DMA Channel 2 Sys Mem Ptr	size 32 ro */
+#define DMA_CH2_VICE_PTR 0x01E0 /* DMA Channel 2 VICE Mem Ptr	size 16 ro */
+#define DMA_CH2_COUNT	0x01E8 /* DMA Channel 2 remaining count	size 16 ro */
+#define BSP_INBOX	0x01F0 /* BSP inbox			size 16 ro */
+#define BSP_OUTBOX	0x01F8 /* BSP outbox			size 16 rw */
+
+/* VICE RAM's */
+#define MSP_IRAM	0x2000 /* MSP instruction RAM base, length 4K */
+#define BSP_IRAM	0x4000 /* BSP instruction RAM base, length 4K */
+#define BSP_TABLE	0x5000 /* BSP Tables, length 8K */
+#define BSP_IO_IN	0x7800 /* BSP Input buffers, length 2K */
+#define BSP_IO_OUT	0x7000 /* BSP Output buffers, length 2K */
+#define VICE_DRAM_A	0x8000 /* Data RAM Bank A, , length 2K */
+#define VICE_DRAM_B	0x8800 /* Data RAM Bank B, , length 2K */
+#define VICE_DRAM_C	0x9000 /* Data RAM Bank C, , length 2K */
+
+/* VICE Interrupt status bits */
+#define VICE_INT_DMA_CH1_DONE	BIT(0)
+#define VICE_INT_DMA_CH1_ERR	BIT(1)
+#define VICE_INT_MSP_SW		BIT(2)	/* MSP wants to interrupt host (Program is=
 finished?) */
+#define VICE_INT_MSP_ERR	BIT(3)	/* MSP exception */
+#define VICE_INT_BSP_SW		BIT(4)	/* BSP wants to interrupt host (Program is=
 finished?) */
+#define VICE_INT_BSP_ERR	BIT(5)	/* BSP exception */
+#define VICE_INT_BUSERR		BIT(6)	/* ?? Erroneous data received through SysA=
D interface */
+#define VICE_INT_DMA_CH2_DONE	BIT(7)
+#define VICE_INT_DMA_CH2_ERR	BIT(8)
+
+/*
+ * VICE DMA Describtor related definitions
+ */
+
+/* Flags */
+#define VICE_DMA_HALT BIT(15)
+#define VICE_DMA_SKIP BIT(14)
+#define VICE_DMA_TOVICE  BIT(13)	/* 1=3Dtransaction is System->VICE, 0=3DV=
ICE->System */
+#define VICE_DMA_FILL BIT(12)	/* 1=3DPattern fill VICE memory from VICEDMA=
_DATA register \
+				   0=3Dnormal VICE<->System transaction */
+/* flags (11:10) */
+#define VICE_DMA_YC_NONE    (0x0<<10) /* Just plain pump it through */
+#define VICE_DMA_YC_422_420 (0x1<<10) /* Y/C 4:2:2 to Y/C 4:2:0 split */
+#define VICE_DMA_YC_422_422 (0x2<<10) /* Y/C 4:2:2 to Y/C 4:2:2 split */
+#define VICE_DMA_YC_422_Y   (0x3<<10) /* Y/C 4:2:2 to Y split -- DMA read =
only */
+
+/* flags(9:8) */
+#define VICE_DMA_HP_FF	(0x0<<8) /* Full Pel Vert	Full Pel Horz */
+#define VICE_DMA_HP_FH	(0x1<<8) /* Full Pel Vert	Half Pel Horz */
+#define VICE_DMA_HP_HF	(0x2<<8) /* Half Pel Vert	Full Pel Horz */
+#define VICE_DMA_HP_HH	(0x3<<8) /* Half Pel Vert	Half Pel Horz */
+
+#define VICE_DMA_ILV BIT(7) /* 0=3DProcess describtor individually, \
+			       1=3DPcocess describtors as pairs and \
+			         interleave them into VICE memory */
+/* Source/Destination location within VICE FLAGS(6:4)*/
+#define VICE_DMA_LOC_DRAMA   (0x0<<4) /* Data RAM A          */
+#define VICE_DMA_LOC_DRAMB   (0x1<<4) /* Data RAM B          */
+#define VICE_DMA_LOC_DRAMC   (0x2<<4) /* Data RAM C          */
+#define VICE_DMA_LOC_MSPI    (0x3<<4) /* MSP Instruction RAM */
+#define VICE_DMA_LOC_BSPI    (0x4<<4) /* BSP Instruction RAM */
+#define VICE_DMA_LOC_BSPTBL  (0x5<<4) /* BSP Table RAM       */
+#define VICE_DMA_LOC_BSPFIFO (0x6<<4) /* BSP Decode FIFO     */
+#define VICE_DMA_LOC_TLB     (0x7<<4) /* DMA TLB RAM         */
+
+#define VICE_DMA_HPEN BIT(3) /* 0=3DHalf Pel mode disabled -- ignore 8:9 */
+
+typedef struct vice_dma_desc
+{
+    u64 flags;		/* See above for definitions of various bits */
+    u64 sys_addr_hi;	/* High word of system memory address */
+    u64 sys_addr_lo;	/* Low word of system memory address */
+    u64 span;		/* Length of one line */
+    u64 stride;		/* Number of bytes to skip between lines */
+    u64 line_count;	/* Number of lines */
+    u64 vice_addr_Y;	/* VICE memory address */
+    u64 vice_addr_C;	/* VICE mem address for Y/C translated mode transfers=
 */
+} vice_dma_desc;
+
+#define DMA_DESCRIBTORS_BASE	0x1000
+#define VICE_DMA_DESC(x)	(DMA_DESCRIBTORS_BASE+((x)*sizeof(vice_dma_desc)))
+
+/*
+ * VICE DMA has eight descriptors -- 4 for each channel
+ */
+#define VICE_DMA_CH1_D1		VICE_DMA_DESC(0)
+#define VICE_DMA_CH1_D2		VICE_DMA_DESC(1)
+#define VICE_DMA_CH1_D3		VICE_DMA_DESC(2)
+#define VICE_DMA_CH1_D4		VICE_DMA_DESC(3)
+#define VICE_DMA_CH2_D1		VICE_DMA_DESC(4)
+#define VICE_DMA_CH2_D2		VICE_DMA_DESC(5)
+#define VICE_DMA_CH2_D3		VICE_DMA_DESC(6)
+#define VICE_DMA_CH2_D4		VICE_DMA_DESC(7)
+
+/* VICE DMA control register bits */
+#define VICE_DMA_CTL_GO		BIT(0) /* Write 1 to kick off DMA */
+#define VICE_DMA_CTL_IE		BIT(1) /* 1=3DInterrupt on DMA completion, 0=3DNo=
 interrupt */
+#define VICE_DMA_CTL_STOP	BIT(2) /* Write 1 to stop DMA */
+#define VICE_DMA_CTL_RESET	BIT(3) /* 1=3DReset DMA engine, write 0 to allo=
w it to run again */
+#define VICE_DMA_CTL_DESC1	BIT(4) /* Start DMA with descriptor 1 */
+#define VICE_DMA_CTL_DESC2	BIT(5) /* Start DMA with descriptor 2 */
+#define VICE_DMA_CTL_DESC3	BIT(6) /* Start DMA with descriptor 3 */
+#define VICE_DMA_CTL_DESC4	BIT(7) /* Start DMA with descriptor 4 */
+#define VICE_DMA_CTL_TLB_BYPASS	BIT(8) /* Bypass TLB for this transaction =
*/
+#define VICE_DMA_CTL_FLUSH_BUF	BIT(9) /* What the hell does this do? */
+
+/*
+ * DMA TLB definitions
+ */
+
+#define VICE_PAGE_SHIFT 16
+#define VICE_PAGE_ORDER 4
+#define VICE_PAGE_SIZE (1<<VICE_PAGE_SHIFT)
+#define VICE_PAGE_MASK 0xFFFF0000	/* VICE DMA TLB works with 64K pages ali=
gned on 64K boundary */
+#define VICE_TLB_OFFSET 0xF000		/* Vice TLB starts here. Range is F000-FFF=
C */
+#define VICE_TLB_ENTRIES 64		/* Number of TLB entried in VICE */
+
+#define VICE_DMA_LINEAR	0x00800000	/* Linear access to system memory */
+#define VICE_DMA_TILED	0x10800000	/* Tiled access to system memory */
+
+/*
+ * TLB Entry format
+ */
+#define VICE_TLB_VALID		BIT(0)
+#define VICE_TLB_WRITABLE	BIT(1)
+
+/*
+ * MSP definitions
+ */
+
+#define MSP_GO	BIT(0)	/* writing MSP_GO to MSP_CTL_STAT register starts MS=
P */
+#define MSP_OPERATIONAL BIT(1) /* Actually you have to write 1 to take it =
out of reset... Ugh */
+
+/*
+ * BSP definitions
+ */
+#define BSP_OPERATIONAL     BIT(0) /* write 1 to take BSP out of reset */
+#define BSP_HALT            BIT(1) /* write 0 to start BSP, write 1 to hal=
t it */
+#define BSP_HALT_ACK        BIT(2) /* reads as 1, when BSP recognised HALT=
 request */
+
+#define BSP_FIFO_CTL_RESET  BIT(2)
+
+#define MAX_BSP_HALT_WAIT              10 /*max time to vait for BSP halt =
before reset */
+
+/*
+ * VICE IOCTL related definitions
+ */
+#define VICE_RES_STATUS_FREE		0
+#define VICE_RES_STATUS_INPROGRESS	1
+#define VICE_RES_STATUS_DONE		2
+#define VICE_RES_STATUS_ERR		3
+
+
+typedef struct dma_run
+{
+    u32 channel;
+    u32 desc;
+    u32 status;
+} dma_run;
+
+typedef struct msp_run
+{
+    u32 pc; /* PC, where MSP have finished running (either took exception,=
 or did SW int) */
+    u32 reason; /* MSP_EXPT_CAUSE */
+    u32 status; /* Whether MSP took exception or did SW int */
+} msp_run;
+
+typedef struct bsp_run
+{
+    u32 pc;
+    u32 reason;
+    u32 status;
+} bsp_run;
+
+/* Must be written all at once. Should I make a union of it with u32? */
+typedef struct vice_tlb_entry
+{
+    u16 page_num; /* Physical 64K page number */
+    u16 flags; /* Bit 0 - valid, bit 1 writable, rest undefined */
+} vice_tlb_entry;
+
+
+#ifdef __KERNEL__
+struct vice_dev;
+
+typedef struct vice_dev {
+    char is_open;
+    struct semaphore sem;     /* mutual exclusion semaphore     */
+    devfs_handle_t handle;    /* only used if devfs is there */
+    vice_dma_desc* ch1;       /* current DMA decriptor for channel 1 */
+    vice_dma_desc* ch2;       /* current DMA decriptor for channel 2 */
+
+    u32 ch1_dma_stat;         /* Various flags related to DMA in progress =
*/
+    u32 ch2_dma_stat;         /* Various flags related to DMA in progress =
*/
+
+    spinlock_t dma_lock[2];   /* spinlocks for accessing dma status for 2 =
VICE DMA channels */
+    u32 dma_status[2];        /* status of dma channels */
+
+    dma_addr_t dma_mem[VICE_TLB_ENTRIES*2]; /* 2 sets 64*64K pages, used f=
or DMA to/from VICE */
+    void* dma_kmem[VICE_TLB_ENTRIES*2]; /* 2 sets 64*64K pages, used for D=
MA to/from VICE */
+
+    /*
+    vice_page *page_table;
+    unsigned int page_cnt;
+    */
+    /* MSP stuff */
+    u32 msp_pc;			/* PC where MSP stopped (EPC) */
+    u32 msp_int_reason;		/* Reason MSP stopped */
+    u32 msp_status;		/* Free/Working/Done/Error */
+    spinlock_t msp_lock;	/* spinlock for accessing MSP status */
+
+    /* BSP stuff */
+    u32 bsp_pc;			/* PC where BSP stopped (EPC) */
+    u32 bsp_int_reason;		/* Reason BSP stopped */
+    u32 bsp_status;		/* Free/Working/Done/Error */
+    spinlock_t bsp_lock;	/* spinlock for accessing BSP status */
+} vice_dev;
+
+#endif /* __KERNEL__ */
+
+#define VICE_DMA_STAT_DATA	BIT(0)
+#define VICE_DMA_STAT_MSP_CODE	BIT(1)
+#define VICE_DMA_STAT_BSP_CODE	BIT(2)
+#define VICE_DMA_STAT_BSP_TBL	BIT(3)
+#define VICE_DMA_STAT_DIR	BIT(4)	/* 0 - to VICE, 1 to system */
+
+/*
+ * VICE ioctl commands
+ */
+#ifdef __KERNEL__
+#define VICE_IOCTL_MAGIC	0x96
+#define VICE_IOCTL_MAP_DMA	_IOR(VICE_IOCTL_MAGIC,1,unsigned long)
+#define VICE_IOCTL_MSP_RUN	_IOR(VICE_IOCTL_MAGIC,2,msp_run)
+#define VICE_IOCTL_BSP_RUN	_IOR(VICE_IOCTL_MAGIC,3,bsp_run)
+#define VICE_IOCTL_DO_DMA	_IOWR(VICE_IOCTL_MAGIC,4,dma_run)
+#else
+#define VICE_IOCTL_MAP_DMA	0x40089601
+#define VICE_IOCTL_MSP_RUN	0x400c9602
+#define VICE_IOCTL_BSP_RUN	0x400c9603
+#define VICE_IOCTL_DO_DMA	0xc00c9604
+#endif
+
+#ifdef __KERNEL__
+/* Vice wait queue */
+//Each unit has it's own wait_queue, as they might all sleep separately
+//extern wait_queue_head_t dma_wq;
+
+static inline void vice_write_reg(u32 reg,u64 value)
+{
+    *(volatile u64*)(KSEG1ADDR(VICE_REG(reg)))=3Dvalue;
+}
+static inline u64 vice_read_reg(u32 reg)
+{
+    return *(volatile u64*)(KSEG1ADDR(VICE_REG(reg)));
+}
+
+static inline void vice_write_32(u32 addr,u32 value)
+{
+    *(volatile u32*)(KSEG1ADDR(VICE_REG(addr)))=3Dvalue;
+}
+static inline u32 vice_read_32(u32 addr)
+{
+    return *(volatile u32*)(KSEG1ADDR(VICE_REG(addr)));
+}
+
+int vice_dma_map_set(vice_dev *vice,unsigned long set);
+
+/*
+ * Some DMA-related inline functions
+ */
+
+static inline int vice_dma_mem_init(vice_dev *vice)
+{
+    int i;
+    for (i=3D0; i<64*2;i++){
+	if(!(vice->dma_kmem[i]=3Dpci_alloc_consistent(0,VICE_PAGE_SIZE,&(vice->dm=
a_mem[i])))) {
+	    DPRINTK("failed at page# %i\n",i);
+    	    return -ENOMEM;
+	}
+    }
+    return 0;
+}
+static inline void vice_dma_mem_free(vice_dev *vice)
+{
+    int i;
+    for (i=3D0; i<64*2;i++){
+	if(vice->dma_kmem[i]) {
+	    pci_free_consistent(0,VICE_PAGE_ORDER,vice->dma_kmem[i],vice->dma_mem=
[i]);
+	    vice->dma_kmem[i]=3D0;
+	    vice->dma_mem[i]=3D0;
+	}
+    }
+}
+
+int vice_msp_init(vice_dev* vice);
+int vice_bsp_init(vice_dev* vice);
+int vice_dma_init(vice_dev* vice);
+
+void vice_msp_reset(vice_dev* vice);
+void vice_bsp_reset(vice_dev* vice);
+void vice_dma_reset(vice_dev* vice);
+
+void vice_msp_cleanup(vice_dev* vice);
+void vice_bsp_cleanup(vice_dev* vice);
+void vice_dma_cleanup(vice_dev* vice);
+
+void vice_dma_done(vice_dev* vice, int channel);
+void vice_dma_err(vice_dev* vice, int channel);
+void vice_handle_msp_int(vice_dev* vice);
+void vice_handle_msp_err(vice_dev* vice);
+void vice_handle_bsp_int(vice_dev* vice);
+void vice_handle_bsp_err(vice_dev* vice);
+void vice_handle_bus_err(vice_dev* vice);
+
+int vice_dma_run(vice_dev* vice,dma_run* run);
+int vice_msp_run(vice_dev* vice,msp_run* run);
+int vice_bsp_run(vice_dev* vice,bsp_run* run);
+#endif /* __KERNEL__ */
+
+#endif /* _VICE_H_ */
--- /dev/null	Sun Jul 17 16:46:18 1994
+++ drivers/char/o2vice/bsp.c	Tue Dec 10 09:54:48 2002
@@ -0,0 +1,161 @@
+/*
+ *
+ * Copyright (C) 2002 Ilya Volynets
+ *	Sponsored by Total Knowledge
+ *	http://www.total-knowledge.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+ * 09.16.2002	iluxa
+ *	- skeleton only (I don't have instruction set for BSP, so there
+ *	  is no way I can test it).
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+
+#include <linux/kernel.h>   /* printk() */
+#include <asm/page.h>
+#include <linux/vmalloc.h>   /* kmalloc() */
+#include <linux/fs.h>       /* everything... */
+#include <linux/errno.h>    /* error codes */
+#include <linux/types.h>    /* size_t */
+#include <linux/proc_fs.h>
+#include <linux/fcntl.h>    /* O_ACCMODE */
+
+#include <asm/system.h>     /* cli(), *_flags */
+#include <asm/pci.h>
+#include <asm/uaccess.h>    /* put_user & friends */
+#include <asm/delay.h>
+
+/*
+ * The file operations for the bsp device
+ * (some are overlayed with primary vice)
+ */
+
+#include <linux/vice.h>
+
+
+/* wait queue to wait on while BSP runs */
+static DECLARE_WAIT_QUEUE_HEAD(wq);
+
+void vice_bsp_reset(vice_dev* vice);
+
+/*
+ * Loads BSP PC with value form vice->bsp_pc, takes bsp out of reset
+ * state (just in case?) and kicks off execution.
+ */
+static inline void bsp_go(vice_dev* vice)
+{
+	vice_write_reg(BSP_HALT_RESET,BSP_OPERATIONAL); /* BSP_HALT=3D0 to start =
*/
+}
+
+static inline void vice_bsp_stop()
+{
+    int i=3D0;
+    u64 ctl=3Dvice_read_reg(BSP_HALT_RESET)|BSP_HALT;
+    vice_write_reg(BSP_HALT_RESET,ctl);
+    while(!vice_read_reg(BSP_HALT_RESET)&BSP_HALT_ACK) {
+	    if (++i>MAX_BSP_HALT_WAIT) {
+		    printk(KERN_WARNING "o2vice: timeout stopping bsp, bsp reset\n");
+		    vice_bsp_reset(0);/*FIXME: pass vice* arrond*/
+	    }
+	    udelay(16);
+    }
+}
+
+int vice_bsp_init(struct vice_dev* vice)
+{
+    spin_lock_init(&vice->dma_lock[1]);
+    return 0;
+}
+
+void vice_bsp_reset(vice_dev* vice)
+{
+    vice_write_reg(BSP_HALT_RESET,0);
+    vice_write_reg(BSP_FIFO_CTL_STAT, BSP_FIFO_CTL_RESET);
+    udelay(1);
+    vice_write_reg(BSP_HALT_RESET, BSP_OPERATIONAL|BSP_HALT);
+    vice_write_reg(BSP_FIFO_CTL_STAT,0);
+}
+void vice_bsp_cleanup(vice_dev* vice)
+{
+	vice_bsp_stop();
+}
+
+void vice_handle_bsp_int(vice_dev* vice)
+{
+    DPRINTK("Ah! We are done with BSP!\n");
+    if(vice->bsp_status!=3DVICE_RES_STATUS_INPROGRESS) {
+	DPRINTK("Ugh... BSP interrupt while BSP isn't started from driver!\n");
+	return;
+    }
+    vice->bsp_status=3DVICE_RES_STATUS_DONE;
+    vice->bsp_pc=3D-1; /* No exception, no EPC, and PC is probably
+			not one which executed Exception instruction */
+    vice->bsp_int_reason=3Dvice_read_reg(BSP_CAUSE);
+    wake_up_interruptible(&wq);
+}
+void vice_handle_bsp_err(vice_dev* vice)
+{
+    DPRINTK("Ouch! BSP Exception!\n");
+    if(vice->bsp_status!=3DVICE_RES_STATUS_INPROGRESS) {
+	DPRINTK("Ugh... BSP exception while BSP isn't started from driver!\n");
+	return;
+    }
+    vice->bsp_status=3DVICE_RES_STATUS_ERR;
+    vice->bsp_pc=3D(u32)vice_read_reg(BSP_EPC);
+    vice->bsp_int_reason=3Dvice_read_reg(BSP_CAUSE);
+    wake_up_interruptible(&wq);
+}
+
+int vice_bsp_run(vice_dev* vice, bsp_run* result)
+{
+    bsp_run r;
+    if(!access_ok(VERIFY_WRITE,result,sizeof(bsp_run)))
+	return -EFAULT;
+    DPRINTK("Checking for BSP status\n");
+    spin_lock_irq(vice->bsp_lock);
+    if(vice->bsp_status!=3DVICE_RES_STATUS_FREE) {
+	spin_unlock_irq(vice->bsp_lock);
+	return -EBUSY;
+    }
+    DPRINTK("BSP is free\n");
+    vice->bsp_status=3DVICE_RES_STATUS_INPROGRESS;
+    spin_unlock_irq(vice->bsp_lock);
+    DPRINTK("Kicking BSP off\n");
+    bsp_go(vice);
+    /*
+     * Sleep, untill BSP interrupts us...
+     *
+     * No spinlock is needed...
+     */
+    DPRINTK("Falling asleep\n");
+    while(vice->bsp_status=3D=3DVICE_RES_STATUS_INPROGRESS) {
+        interruptible_sleep_on(&wq);
+	DPRINTK("Huh? Where am I?\n");
+	if(signal_pending(current))break;
+    }
+    DPRINTK("*yawn* obviously waking up....\n");
+    copy_from_user(&r,result,sizeof(r));
+    DPRINTK("r.reason=3D%x, r.pc=3D%x, r.status=3D%x\n",r.reason,r.pc,r.st=
atus);
+    r.status=3Dvice->bsp_status;
+    vice->bsp_status=3DVICE_RES_STATUS_FREE;
+    r.pc=3Dvice->bsp_pc;
+    r.reason=3Dvice->bsp_int_reason;
+    DPRINTK("r.reason=3D%x, r.pc=3D%x, r.status=3D%x\n",r.reason,r.pc,r.st=
atus);
+    return copy_to_user(result,&r,sizeof(r));
+}
--- /dev/null	Sun Jul 17 16:46:18 1994
+++ drivers/char/o2vice/msp.c	Tue Dec 10 09:55:35 2002
@@ -0,0 +1,157 @@
+/*
+ *
+ * Copyright (C) 2002 Ilya Volynets
+ *	Sponsored by Total Knowledge
+ *	http://www.total-knowledge.com
+ *
+ * Development of this code was made possible by generous contribution
+ * from Total Knowledge (http://www.total-knowledge.com/)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * 09.16.2002	iluxa
+ *	- first rough cut. basic MSP operations supported
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+
+#include <linux/kernel.h>   /* printk() */
+#include <asm/page.h>
+#include <linux/vmalloc.h>   /* kmalloc() */
+#include <linux/fs.h>       /* everything... */
+#include <linux/errno.h>    /* error codes */
+#include <linux/types.h>    /* size_t */
+#include <linux/proc_fs.h>
+#include <linux/fcntl.h>    /* O_ACCMODE */
+
+#include <asm/system.h>     /* cli(), *_flags */
+#include <asm/pci.h>
+#include <asm/uaccess.h>    /* put_user & friends */
+#include <asm/delay.h>
+
+/*
+ * The file operations for the msp device
+ * (some are overlayed with primary vice)
+ */
+
+#include <linux/vice.h>
+
+/* Statically allocate wait queue */
+static DECLARE_WAIT_QUEUE_HEAD(wq);
+
+/*
+ * Loads MSP PC with value form msp->pc, takes msp out of reset
+ * state (just in case?) and kicks off execution.
+ */
+static inline void msp_go(vice_dev* vice)
+{
+    vice_write_reg(MSP_CTL_STAT,MSP_GO|MSP_OPERATIONAL);
+}
+
+static inline void vice_msp_stop(void)
+{
+    u64 ctl=3Dvice_read_reg(MSP_CTL_STAT)&(~MSP_GO);
+    vice_write_reg(MSP_CTL_STAT,ctl);
+}
+
+int vice_msp_run(vice_dev *vice, msp_run* result)
+{
+    msp_run r;
+    if(!access_ok(VERIFY_WRITE,result,sizeof(msp_run)))
+	return -EFAULT;
+    DPRINTK("Checking for MSP status\n");
+    spin_lock_irq(vice->msp_lock);
+    if(vice->msp_status!=3DVICE_RES_STATUS_FREE) {
+	spin_unlock_irq(vice->msp_lock);
+	return -EBUSY;
+    }
+    DPRINTK("MSP is free\n");
+    vice->msp_status=3DVICE_RES_STATUS_INPROGRESS;
+    spin_unlock_irq(vice->msp_lock);
+    DPRINTK("Kicking MSP off\n");
+    msp_go(vice);
+    /*
+     * Sleep, untill MSP interrupts us...
+     *
+     * No spinlock is needed...
+     */
+    DPRINTK("Falling asleep\n");
+    while(vice->msp_status=3D=3DVICE_RES_STATUS_INPROGRESS) {
+        interruptible_sleep_on(&wq);
+	DPRINTK("Huh? Where am I?\n");
+	if(signal_pending(current))break;
+    }
+    DPRINTK("*yawn* obviously waking up....\n");
+    copy_from_user(&r,result,sizeof(r));
+    DPRINTK("r.reason=3D%x, r.pc=3D%x, r.status=3D%x\n",r.reason,r.pc,r.st=
atus);
+    r.status=3Dvice->msp_status;
+    vice->msp_status=3DVICE_RES_STATUS_FREE;
+    r.pc=3Dvice->msp_pc;
+    r.reason=3Dvice->msp_int_reason;
+    DPRINTK("r.reason=3D%x, r.pc=3D%x, r.status=3D%x\n",r.reason,r.pc,r.st=
atus);
+    return copy_to_user(result,&r,sizeof(r));
+}
+
+void vice_handle_msp_int(vice_dev* vice)
+{
+    DPRINTK("Ah! We are done with MSP!\n");
+    if(vice->msp_status!=3DVICE_RES_STATUS_INPROGRESS) {
+	DPRINTK("Ugh... MSP interrupt while MSP isn't started from driver!\n");
+	return;
+    }
+    vice->msp_status=3DVICE_RES_STATUS_DONE;
+    vice->msp_pc=3D-1; /* No exception, no EPC, and PC is probably
+			not one which executed Exception instruction */
+    vice->msp_int_reason=3Dvice_read_reg(MSP_EXPT_FLAG);
+    wake_up_interruptible(&wq);
+}
+void vice_handle_msp_err(vice_dev* vice)
+{
+    DPRINTK("Ouch! MSP Exception!\n");
+    if(vice->msp_status!=3DVICE_RES_STATUS_INPROGRESS) {
+	DPRINTK("Ugh... MSP exception while MSP isn't started from driver!\n");
+	return;
+    }
+    vice->msp_status=3DVICE_RES_STATUS_ERR;
+    vice->msp_pc=3D(u32)vice_read_reg(MSP_EPC);
+    vice->msp_int_reason=3Dvice_read_reg(MSP_EXPT_FLAG);
+    /* clear any exception bits */
+    vice_write_reg(MSP_EXPT_FLAG,0x00);
+    wake_up_interruptible(&wq);
+}
+
+int vice_msp_init(struct vice_dev* vice)
+{
+    spin_lock_init(&vice->dma_lock[0]);
+    return 0;
+}
+
+void vice_msp_reset(vice_dev *vice)
+{
+    /* start reset */
+    vice_write_reg(MSP_CTL_STAT,0);
+    /* wait for reset to complete */
+    udelay(1);
+    /* take out of reset, and prepare to go */
+    vice_write_reg(MSP_CTL_STAT,MSP_OPERATIONAL);
+    /* let MSP access all VICE internal RAM */
+    vice_write_reg(MSP_D_RAM,0x7);
+}
+
+void vice_msp_cleanup(vice_dev* vice)
+{
+    vice_msp_stop();
+}
--- /dev/null	Sun Jul 17 16:46:18 1994
+++ drivers/char/o2vice/Kconfig	Sat Nov  2 14:10:16 2002
@@ -0,0 +1,32 @@
+#
+# O2 VICE Engine confiuration
+#
+
+config O2_VICE
+    tristate "O2 VICE Engine Support"
+    depends on SGI_IP32
+    ---help---
+      This option enables O2 VICE Engine support.
+      VICE stands for Video Image Compression Engine. This is very powerfu=
ll
+      piece of silicon, that can greatly speed up lots of graphics, vide, =
or
+      sound related tasks. To be able to use it, you will also need special
+      library, that can be found at <insert URL here>
+
+config O2_VICE_DBGG
+    bool "VICE Debugger Support. READ HELP!"
+    depends on O2_VICE
+    ---help---
+      This option enables features of VICE driver needed to debug VICE lib=
rary.
+      This is probably serious security risk. You don't need it. If you th=
ink
+      you do, you are wrong. Say NO.
+
+config O2_VICE_DBG
+    bool "You seem to insist... did you read help? Yes? No? READ HELP!"
+    depends on O2_VICE_DBGG
+    ---help---
+      You are still here? Didn't I just tell you that it is not needed?
+      Or do you want to say you *legally* obtained information needed for
+      programming VICE? That you got all the tools needed? As a matter of
+      fact, these tools don't even exist yet!
+
+      Sigh... You've been warned...
--- /dev/null	Sun Jul 17 16:46:18 1994
+++ drivers/char/o2vice/Makefile	Thu Sep 12 00:12:16 2002
@@ -0,0 +1,21 @@
+#
+# drivers/char/o2vice/Makefile
+#
+# Makefile for the O2 VICE Engine driver.
+#
+
+SUB_DIRS     :=3D=20
+MOD_SUB_DIRS :=3D $(SUB_DIRS)
+ALL_SUB_DIRS :=3D $(SUB_DIRS)
+
+#O_TARGET :=3D vice.o
+
+obj-y		:=3D
+obj-m		:=3D
+obj-n		:=3D
+obj-		:=3D
+
+obj-$(CONFIG_O2_VICE)	+=3D main.o msp.o bsp.o dma.o
+#obj-$(CONFIG_O2_VICE_DBG) +=3D vicedebug.o
+
+include $(TOPDIR)/Rules.make
--- /dev/null	Sun Jul 17 16:46:18 1994
+++ drivers/char/o2vice/main.c	Tue Dec 10 09:55:59 2002
@@ -0,0 +1,438 @@
+/*
+ * main.c -- SGI O2 VICE driver
+ *
+ * The code skeleton came from the book "Linux Device
+ * Drivers" by Alessandro Rubini and Jonathan Corbet, published
+ * by O'Reilly & Associates.   No warranty is attached;
+ * we cannot take responsibility for errors or fitness for use.
+ *
+ * Copyright (C) 2002 Ilya Volynets.
+ *	Sponsored by Total Knowledge
+ *	http://www.total-knowledge.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+ * 09.16.2002	iluxa
+ *	- first rough cut is ready.
+ */
+
+/*
+ * When debugging support is turned off, there will be no access to most of
+ * VICE I/O space. No PIO access to ram and buffers for sure, as acceessing
+ * some of "unimplemented" regions seems to halt system completely. (Is CPU
+ * just stalling, waiting for data to be returned, instead of getting erro=
r?)
+ * Safe registers are first 4K (control registers?) and next 4K with DMA
+ * describtors.
+ * Well, I could give access to correct pages through "nopage" method...
+ * Then accessing "reserved" regions would give SIG_BUS...
+ * Data ram would be problem: there are 3 2K regions, which either makes
+ * only 2 banks accessible to userspace, or none at all (giving non-root u=
ser
+ * an option to randomly hang system is not an option :)
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>		/* module_(init|exit) */
+
+#include <linux/kernel.h>	/* printk() */
+#include <asm/page.h>
+#include <linux/vmalloc.h>	/* kmalloc() */
+#include <linux/fs.h>		/* everything... */
+#include <linux/errno.h>	/* error codes */
+#include <linux/types.h>	/* size_t */
+#include <linux/proc_fs.h>
+#include <linux/fcntl.h>	/* O_ACCMODE */
+
+#include <asm/system.h>		/* cli(), *_flags */
+
+#include <linux/mm.h>
+
+#include <linux/vice.h>		/* local definitions */
+
+#include <asm/ip32/ip32_ints.h>
+
+int vice_major =3D VICE_MAJOR;
+
+MODULE_PARM(vice_major, "i");
+MODULE_AUTHOR("Ilya Volynets");
+
+const char *vice_str=3D"vice";
+
+/*
+ * Different minors behave differently, so let's use multiple fops
+ */
+
+
+void *vice_device;	/* holds pointer to vice state (allocated in module_ini=
t) */
+
+/*
+ * vice_reset -- restes VICE engine
+ */
+int vice_reset(vice_dev * dev)
+{
+    vice_bsp_reset(dev);
+    vice_msp_reset(dev);
+    vice_dma_reset(dev);
+    return 0;
+}
+
+void vice_handle_buserr(vice_dev* vice)
+{
+    printk(KERN_WARNING "vice: received \"Erroneous data\" interrupt.\n");
+    printk(KERN_WARNING "\tUnfortunately I (Ilya Volynets) Have no idea wh=
at is it, so I'm simply ignoring it.\n");
+}
+
+static void vice_interrupt(int irq, void *dev_id, struct pt_regs *pregs)
+{
+    struct vice_dev *vice =3D (struct vice_dev *) dev_id;
+    u64 status;
+    DPRINTK("irq!\n");
+    status=3Dvice_read_reg(VICE_INT);
+
+    if (!vice /*paranoid */ ) {
+	DPRINTK ("Paranoja ouch!\n");
+	return;
+    }
+
+    DPRINTK("Interrupt, status %016lx...\n", status);
+    if (status & VICE_INT_DMA_CH1_DONE)
+	vice_dma_done(vice,0);
+    if (status & VICE_INT_DMA_CH1_ERR)
+	vice_dma_err(vice,0);
+    if (status & VICE_INT_DMA_CH2_DONE)
+	vice_dma_done(vice,1);
+    if (status & VICE_INT_DMA_CH2_ERR)
+	vice_dma_err(vice,1);
+    if (status & VICE_INT_MSP_SW)
+	vice_handle_msp_int(vice);
+    if (status & VICE_INT_MSP_ERR)
+	vice_handle_msp_err(vice);
+    if (status & VICE_INT_BSP_SW)
+	vice_handle_bsp_int(vice);
+    if (status & VICE_INT_BSP_ERR)
+	vice_handle_bsp_err(vice);
+    if (status & VICE_INT_BUSERR)
+	vice_handle_buserr(vice);
+
+    vice_write_reg(VICE_INT_RESET,0x1FF);	/* clear handled interrupts */
+}
+
+/*
+ * Open and close
+ */
+
+/* In vice_open, the fop_array is used according to TYPE(dev) */
+int vice_open(struct inode *inode, struct file *filp)
+{
+    vice_dev *vice=3Dvice_device;		/* device information */
+    int res;
+
+    MOD_INC_USE_COUNT;		/* Before we maybe sleep */
+
+    if(vice->is_open)
+	return -EBUSY;
+
+    if (!filp->private_data) {
+	filp->private_data =3D vice_device;
+    }
+
+    vice_reset(vice);
+
+    if ((res=3Drequest_irq(CRIME_VICE_IRQ, vice_interrupt, SA_SHIRQ, vice_=
str, vice))) {
+	printk(KERN_ERR "vice: Can't get irq %x: res=3D%i\n", (unsigned int)CRIME=
_VICE_INT, res);
+	return res;
+    }
+
+    /*Actual device init goes in here */
+
+    {
+	int ret;
+	if((ret=3Dvice_dma_mem_init(vice))!=3D0) {
+	    DPRINTK("Failure allocating VICE I/O buffers...\n");
+	    vice_dma_mem_free(vice);
+	    DPRINTK("Freed already-allocated memory...\n");
+	    return ret;
+	}
+	/* enable interrupts in VICE */
+        vice_write_reg(VICE_INT_RESET,0x1FF); /* clear pending interrupts =
*/
+	vice_write_reg(VICE_INT_EN,0x1FF);
+    }
+    vice->is_open=3D1;
+    return 0;			/* success */
+}
+
+int vice_release(struct inode *inode, struct file *filp)
+{
+    vice_dev *vice=3D(vice_dev*)filp->private_data;
+
+    DPRINTK("closing down\n");
+    if(!vice->is_open) {
+	DPRINTK("Uuoouuuuch! Closing unopen file!!!!\n");
+	return -EINVAL; /*? Should I return something else? -ENOTOPEN? */
+    }
+    /* disable interrupts in VICE */
+    vice_write_reg(VICE_INT_EN,0x000);
+    free_irq(CRIME_VICE_IRQ, vice);
+    vice_dma_mem_free(vice);
+    vice_reset(vice);
+    vice->is_open=3D0;
+    MOD_DEC_USE_COUNT;
+    return 0;
+}
+
+/*
+ * Data management: read and write
+ */
+
+ssize_t vice_read(struct file * filp, char *buf, size_t count, loff_t * f_=
pos)
+{
+    printk(KERN_WARNING
+	   "Processing bit streams through reading/writing is not supported yet\n=
");
+    return -ENOSYS;
+}
+
+ssize_t vice_write(struct file * filp, const char *buf, size_t count,
+	   loff_t * f_pos)
+{
+    printk(KERN_WARNING
+	   "Processing bit streams through reading/writing is not supported (yet)=
\n");
+    return -ENOSYS;
+}
+
+/*
+ * The ioctl() implementation
+ */
+
+int vice_ioctl(struct inode *inode, struct file *filp,
+	   unsigned int cmd, unsigned long arg)
+{
+    vice_dev *vice=3D(vice_dev*)filp->private_data;
+
+    switch(cmd) {
+    case VICE_IOCTL_MAP_DMA:
+	return vice_dma_map_set(vice,arg);
+    case VICE_IOCTL_MSP_RUN:
+	return vice_msp_run(vice,(msp_run*)arg);
+    case VICE_IOCTL_BSP_RUN:
+	return vice_bsp_run(vice,(bsp_run*)arg);
+    case VICE_IOCTL_DO_DMA:
+	return vice_dma_run(vice,(dma_run*)arg);
+    default:
+	return -ENOTTY;
+    }
+    return 0;
+}
+
+/*
+ * Common VMA ops.
+ */
+
+static void vice_vma_open(struct vm_area_struct *vma)
+{ MOD_INC_USE_COUNT; }
+
+static void vice_vma_close(struct vm_area_struct *vma)
+{ MOD_DEC_USE_COUNT; }
+/*
+ * All it does is find 4K page in one of 64K pages from vice->dev_mem
+ * There is no need to worry about I/O addresses here, since they are rema=
p_page_ranged
+ * on initial mmap....
+ */
+struct page* vice_vma_nopage(struct vm_area_struct *vma,unsigned long addr=
ess, int write)
+{
+    vice_dev *vice=3D(vice_dev*)vma->vm_private_data;
+    unsigned long fkpn=3D((address-vma->vm_start)>>PAGE_SHIFT)+
+	    (vma->vm_pgoff-(VICE_MIN_OFFSET>>PAGE_SHIFT));
+    unsigned long v_pn=3Dfkpn>>VICE_PAGE_ORDER;
+    unsigned long kaddr;
+    struct page *pgptr;
+    if(v_pn>=3Dsizeof(vice->dma_mem)/sizeof(vice->dma_mem[0]))
+	return NOPAGE_SIGBUS;
+    kaddr=3D(unsigned long)KSEG0ADDR(vice->dma_kmem[v_pn])+((fkpn-(v_pn<<V=
ICE_PAGE_ORDER))<<PAGE_SHIFT);
+    pgptr=3Dvirt_to_page(vice->dma_kmem[v_pn]);
+    get_page(pgptr);
+    return virt_to_page(kaddr);
+}
+
+static struct vm_operations_struct vice_vm_ops =3D {
+    open:  vice_vma_open,
+    close: vice_vma_close,
+    nopage: vice_vma_nopage,
+};
+
+/*
+ * mmap I/O registers of VICE. Called when region is in 0-VICE_IO_MAX rang=
e.
+ */
+static inline int vice_io_mmap( struct vm_area_struct *vma)
+{
+    unsigned long offset=3Dvma->vm_pgoff<<PAGE_SHIFT;
+    if(offset+vma->vm_end-vma->vm_start>VICE_IO_MAX_OFFSET+1) {
+	DPRINTK("invalid offset: %lu,length=3D%lx\n",offset,vma->vm_end-vma->vm_s=
tart);
+	return -EINVAL;
+    }
+    vma->vm_page_prot =3D pgprot_noncached(vma->vm_page_prot);
+    vma->vm_flags |=3D VM_IO|VM_RESERVED;
+    flush_cache_all();
+    return remap_page_range(vma,vma->vm_start,VICE_BASE+offset,vma->vm_end=
-vma->vm_start,vma->vm_page_prot);
+}
+/*
+ * mmap I/O buffers. Called when region is above VICE_IO_MAX.
+ */
+
+static inline int vice_buffer_mmap( struct file* filep, struct vm_area_str=
uct *vma)
+{
+    vice_dev *vice=3D(vice_dev*)filep->private_data;
+    unsigned long offset=3Dvma->vm_pgoff<<PAGE_SHIFT;
+
+    /* must be VICE_PAGE aligned (64K) and size must be ... by 64K */
+    if (offset&0xFFFF||(vma->vm_end-vma->vm_start)&0xFFFF)
+	return -ENXIO; /* alignment error? */
+
+    vma->vm_page_prot =3D pgprot_noncached(vma->vm_page_prot);
+    vma->vm_flags |=3D VM_IO|VM_RESERVED;
+
+    vma->vm_private_data=3Dvice;
+    vma->vm_file =3D filep;
+    return 0;
+}
+
+static int vice_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+    unsigned long offset=3Dvma->vm_pgoff<<PAGE_SHIFT;
+    vma->vm_ops =3D &vice_vm_ops;
+    if(offset<=3DVICE_IO_MAX_OFFSET)
+	return vice_io_mmap(vma);
+    else if(offset>=3DVICE_MIN_OFFSET&&offset+vma->vm_end-vma->vm_start<=
=3DVICE_MAX_OFFSET)
+	return vice_buffer_mmap(filp,vma);
+    else
+	return -EINVAL;
+    vice_vma_open(vma);
+}
+
+struct file_operations vice_fops =3D {
+    read:vice_read,
+    write:vice_write,
+    ioctl:vice_ioctl,
+    open:vice_open,
+    release:vice_release,
+    mmap:vice_mmap,
+};
+
+/*
+ * Finally, the module stuff
+ */
+
+#ifdef CONFIG_DEVFS_FS
+devfs_handle_t vice_devfs_dir;
+static char devname[4];
+#endif
+
+/*
+ * The cleanup function is used to handle initialization failures as well.
+ * Thefore, it must be careful to work correctly even if some of the items
+ * have not been initialized
+ */
+void vice_cleanup_module(void)
+{
+#ifndef CONFIG_DEVFS_FS
+    /* cleanup_module is never called if registering failed */
+    unregister_chrdev(vice_major, "vice");
+#endif
+
+    /* Cleanup MSP/BSP/DMA */
+    /* This really should be done in close.. */
+    vice_msp_cleanup(vice_device);
+    vice_bsp_cleanup(vice_device);
+    vice_dma_cleanup(vice_device);
+
+    /* Clean up DMA and other HW */
+
+    if (vice_device) {
+	kfree(vice_device);
+    }
+#ifdef CONFIG_DEVFS_FS
+    /* once again, only for devfs */
+    devfs_unregister(vice_devfs_dir);
+#endif
+}
+
+
+int vice_init_module(void)
+{
+    int result;
+    vice_dev *vice;
+
+    SET_MODULE_OWNER(&vice_fops);
+#ifdef CONFIG_DEVFS_FS
+    /* If we have devfs, create /dev/vice to put files in there */
+    vice_devfs_dir =3D devfs_mk_dir(NULL, "vice", NULL);
+    if (!vice_devfs_dir)
+	return -EBUSY;		/* problem */
+
+#else				/* no devfs, do it the "classic" way  */
+
+    /*
+     * Register your major, and accept a dynamic number. This is the
+     * first thing to do, in order to avoid releasing other module's
+     * fops in vice_cleanup_module()
+     */
+    result =3D register_chrdev(vice_major, "vice", &vice_fops);
+    if (result < 0) {
+	printk(KERN_WARNING "vice: can't get major %d\n", vice_major);
+	return result;
+    }
+    if (vice_major =3D=3D 0)
+	vice_major =3D result;	/* dynamic */
+
+#endif				/* CONFIG_DEVFS_FS */
+    /*=20
+     * allocate the devices -- we could have them static, but... I dunno...
+     */
+    vice =3D kmalloc(sizeof(vice_dev), GFP_KERNEL);
+    if (!vice) {
+	result =3D -ENOMEM;
+	goto fail;
+    }
+    vice_device =3D vice;
+    memset(vice, 0, sizeof(vice_dev));
+#ifdef CONFIG_DEVFS_FS
+    devfs_register(vice_devfs_dir, "vice",
+		   DEVFS_FL_AUTO_DEVNUM,
+		   0, 0, S_IFCHR | S_IRUGO | S_IWUGO, &vice_fops, vice);
+#endif
+    if ((result =3D vice_dma_init(vice)))
+	goto fail;
+    /* Initialize MSP & BSP */
+    if ((result =3D vice_msp_init(vice)))
+	goto fail;
+    if ((result =3D vice_bsp_init(vice)))
+	goto fail;
+
+#ifndef VICE_DEBUG
+    EXPORT_NO_SYMBOLS;		/* otherwise, leave global symbols visible */
+#endif
+
+    vice_write_reg(VICE_ID,0xfffff);
+#define ID_BITS 0xF
+    printk("SGI O2 VICE rev. %ld\n", vice_read_reg(VICE_ID)&ID_BITS);
+    return 0;			/* succeed */
+
+  fail:
+    vice_cleanup_module();
+    return result;
+}
+
+module_init(vice_init_module);
+module_exit(vice_cleanup_module);
--- /dev/null	Sun Jul 17 16:46:18 1994
+++ drivers/char/o2vice/dma.c	Sat Nov  2 16:36:05 2002
@@ -0,0 +1,183 @@
+/*
+ *
+ * Copyright (C) 2002 Ilya Volynets
+ *	Sponsored by Total Knowledge
+ *	http://www.total-knowledge.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+
+#include <linux/kernel.h>   /* printk() */
+#include <asm/page.h>
+#include <linux/vmalloc.h>  /* kmalloc() */
+#include <linux/fs.h>       /* everything... */
+#include <linux/errno.h>    /* error codes */
+#include <linux/types.h>    /* size_t */
+#include <linux/proc_fs.h>
+#include <linux/fcntl.h>    /* O_ACCMODE */
+#include <linux/sched.h>
+
+#include <asm/system.h>     /* cli(), *_flags */
+#include <asm/pci.h>
+#include <asm/uaccess.h>    /* put_user & friends */
+#include <asm/delay.h>
+
+#include <asm/errno.h>
+#include <asm/addrspace.h>
+
+/*
+ * VICE DMA support
+ */
+
+#include <linux/vice.h>
+
+/* wait queue to sleep on, while waiting for DMA */
+static DECLARE_WAIT_QUEUE_HEAD(wq);
+
+
+/*
+ * Maps one of 4M sets into VICE TLB.
+ * Currently set# can be either 0 or 1
+ */
+int vice_dma_map_set(vice_dev *vice,unsigned long set)
+{
+    unsigned long *page_set;
+    int i;
+    /* either map in 0th or 1st set (for now....) */
+    if(set>=3D2)
+	return -EINVAL;
+    page_set=3D&(vice->dma_mem[VICE_TLB_ENTRIES*set]);
+    for(i=3D0; i<VICE_TLB_ENTRIES; i++) {
+	vice_write_reg(VICE_TLB_OFFSET+(i<<3), page_set[i]|VICE_TLB_VALID|VICE_TL=
B_WRITABLE);
+    }
+    for(i=3D0; i<VICE_TLB_ENTRIES; i++) {
+	printk("%016lx ",vice_read_reg(VICE_TLB_OFFSET+(i<<3)));
+    }
+    printk("\n");
+    return 0;
+}
+
+/*
+ * Unmaps all pages from VICE TLB
+ */
+int vice_dma_clear_tlb(vice_dev *vice)
+{
+    int i;
+    for(i=3D0; i<VICE_TLB_ENTRIES; i++) {
+	vice_write_32(VICE_TLB_OFFSET+(i<<2), 0);
+    }
+    return 0;
+}
+
+int vice_dma_init(vice_dev* vice)
+{
+    int ret=3D0;
+    spin_lock_init(&vice->dma_lock[0]);
+    spin_lock_init(&vice->dma_lock[1]);
+    return ret;
+}
+
+int vice_dma_run(vice_dev* vice,dma_run* run)
+{
+    dma_run r;
+    if(copy_from_user(&r,run,sizeof(r)))
+	return -EINVAL;
+    if(r.channel>=3D2)
+	return -EINVAL;
+
+    /*
+     * Only reason I need this spinlock is if two threads are trying to
+     * _start_ DMA at the same time. All other accesses to dma_status need=
 not
+     * be interlocked.
+     */
+    DPRINTK("Checking for channel status\n");
+    spin_lock_irq(vice->dma_lock[r.channel]);
+    if(vice->dma_status[r.channel]!=3DVICE_RES_STATUS_FREE) {
+	spin_unlock_irq(vice->dma_lock[r.channel]);
+	return -EBUSY;
+    }
+    DPRINTK("Channel OK\n");
+    vice->dma_status[r.channel]=3DVICE_RES_STATUS_INPROGRESS;
+    spin_unlock_irq(vice->dma_lock[r.channel]);
+    DPRINTK("Kicking DMA off\n");
+    if(r.channel=3D=3D0)
+        vice_write_reg(DMA_CH1_CTL,r.desc|VICE_DMA_CTL_GO|VICE_DMA_CTL_IE);
+    else
+	vice_write_reg(DMA_CH2_CTL,r.desc|VICE_DMA_CTL_GO|VICE_DMA_CTL_IE);
+    /*
+     * Sleep, untill this channel sends DMA_DONE or DMA_ERR interrupt...
+     *
+     * No spinlock is needed...
+     */
+    DPRINTK("Falling asleep\n");
+    while(vice->dma_status[r.channel]=3D=3DVICE_RES_STATUS_INPROGRESS) {
+        interruptible_sleep_on(&wq);
+	DPRINTK("Huh? Where am I?\n");
+	if(signal_pending(current))break;
+    }
+    DPRINTK("*yawn* obviously waking up....\n");
+    r.status=3Dvice->dma_status[r.channel];
+    vice->dma_status[r.channel]=3DVICE_RES_STATUS_FREE;
+    __copy_to_user(&r,run,sizeof(r));
+    DPRINTK("Done\n");
+    return 0;
+}
+
+void vice_dma_done(vice_dev *vice, int channel)
+{
+    DPRINTK("DMA done\n");
+
+    if(vice->dma_status[channel]!=3DVICE_RES_STATUS_INPROGRESS) {
+	DPRINTK("Ugh... DMA interrupt on channel %d, while DMA on that channel is=
n't initiated from CPU!\n",channel);
+	return;
+    }
+    vice->dma_status[channel]=3DVICE_RES_STATUS_DONE;
+    wake_up_interruptible(&wq);
+}
+
+void vice_dma_err(vice_dev *vice, int channel)
+{
+    DPRINTK("DMA error\n");
+    spin_lock_irq(vice->dma_lock[channel]);
+    vice->dma_status[channel]=3DVICE_RES_STATUS_ERR;
+    spin_unlock_irq(vice->dma_lock[channel]);
+    wake_up_interruptible(&wq);
+}
+
+/*
+ * Need to stop all DMA transfers
+ */
+
+void vice_dma_cleanup(vice_dev* vice)
+{
+}
+
+void vice_dma_reset(vice_dev* vice)
+{
+    /*
+     * Is DMA engine resettable?
+     * ... Yes, which register?
+     */
+    vice_write_reg(DMA_CH1_CTL,VICE_DMA_CTL_RESET);
+    vice_write_reg(DMA_CH2_CTL,VICE_DMA_CTL_RESET);
+    udelay(16); /* sleep for at least 16 VICE clocks */
+    vice_write_reg(DMA_CH1_CTL,VICE_DMA_CTL_IE|VICE_DMA_CTL_DESC1);
+    vice_write_reg(DMA_CH2_CTL,VICE_DMA_CTL_IE|VICE_DMA_CTL_DESC1);
+    vice_dma_clear_tlb(vice);
+}

--2qXFWqzzG3v1+95a--

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From ilya@gateway.total-knowledge.com Tue Dec 10 20:18:04 2002
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To: linux-mips@linux-mips.org
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Subject: update_mmu_cache bug
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Following small patch is needed to prevent kernel from going into infinite loop
on page_fault. Probably similar patches are needed for other CPUs as well,
but since I don;t have any, I'll let those who do take care of that :)

	Ilya.

Index: arch/mips64/mm/tlb-r4k.c
===================================================================
RCS file: /home/cvs/linux/arch/mips64/mm/tlb-r4k.c,v
retrieving revision 1.9
diff -u -r1.9 tlb-r4k.c
--- arch/mips64/mm/tlb-r4k.c    2 Dec 2002 00:27:49 -0000       1.9
+++ arch/mips64/mm/tlb-r4k.c    10 Dec 2002 17:02:30 -0000
@@ -260,8 +260,9 @@
        tlb_probe();
        BARRIER;
        pmdp = pmd_offset(pgdp, address);
+
        idx = read_c0_index();
-       ptep = pte_offset(pmdp, address);
+       ptep = pte_offset_map(pmdp, address);
        BARRIER;
        write_c0_entrylo0(pte_val(*ptep++) >> 6);
        write_c0_entrylo1(pte_val(*ptep) >> 6);


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cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: GDB patch
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> On Tue, Dec 10, 2002 at 01:07:31PM +0100, Carsten Langgaard wrote:
> 
> > I've attached a patch for gdb-stub.c to make it work better with the
> > sde-gdb.
> > These changes should be backwards compatible with a standard gdb, so it
> > shouldn't break anything.
> > Ralf, could you please apply it.
> 
> 
> Strongly object.  While I didn't check the implementation, it's nice to
> see 'X' implemented.  And P.  But what the heck is this?
> 
> 
> > @@ -816,13 +839,64 @@
> >  		case 'k' :
> >  			break;		/* do nothing */
> >  
> > +		case 'R':
> > +			/* RNN[:SS],	Set the value of CPU register NN (size SS) */
> > +			/* FALL THROUGH */
> 
> 
> > -		/*
> > -		 * Reset the whole machine (FIXME: system dependent)
> > -		 */
> >  		case 'r':
> > -			break;
> > +			/* rNN[:SS]	Return the value of CPU register NN (size SS) */
> 
> 
> 
> We're not making up a protocol here, we're implementing one.  R and r
> don't have anything to do with setting registers.

Hi Dan

Actually Carsten *is* trying to implement a protocol, it's just that
it's an extension to the gdb remote debug protocol, as used in our
SDE-MIPS toolchain (viz sde-gdb).  Algorithmics (now MIPS Technologies
UK), always extended the gdb remote debug protocol to support reading
and writing of single registers, and to support variable register
sizes (to allow a 64-bit debug stub to inter-work with gdb debugging a
32-bit application).

When we first implemented these extensions we used the 'R' command to
write a single register, and 'r' to read one (they weren't then used
by gdb). Since then the remote protocol has gained the 'P' command to
write a single register, so we no longer use 'R' - and it would be
dangerous to do so since it can restart the target (so you can get rid
of the special 'R' case, Carsten).

But the standard gdb remote protocol still doesn't have the ability to
read a single register, so I believe that 'r' (or something like it)
is a useful addition, which speeds up the remote protocol
significantly when running over a serial line. And it won't break the
kernel to add support for this extension.

Regards

Nigel
-- 
                         Nigel Stephens         Mailto:nigel@mips.com
    _    _ ____  ___     MIPS Technologies (UK) Phone.: +44 1223 706200
    |\  /|||___)(___     The Fruit Farm         Direct: +44 1223 706207
    | \/ |||    ____)    Ely Road, Chittering   Fax...: +44 1223 706250
    TECHNOLOGIES (UK)    Cambridge CB5 9PH      Cell..: +44 7976 686470
 [formerly Algorithmics] England                http://www.algor.co.uk

From drow@false.org Tue Dec 10 20:32:08 2002
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Date: Tue, 10 Dec 2002 14:32:41 -0500
From: Daniel Jacobowitz <dan@debian.org>
To: nigel@mips.com
Cc: Carsten Langgaard <carstenl@mips.com>,
	Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
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On Tue, Dec 10, 2002 at 07:19:16PM +0000, Nigel Stephens wrote:
> > On Tue, Dec 10, 2002 at 01:07:31PM +0100, Carsten Langgaard wrote:
> > 
> > > I've attached a patch for gdb-stub.c to make it work better with the
> > > sde-gdb.
> > > These changes should be backwards compatible with a standard gdb, so it
> > > shouldn't break anything.
> > > Ralf, could you please apply it.
> > 
> > 
> > Strongly object.  While I didn't check the implementation, it's nice to
> > see 'X' implemented.  And P.  But what the heck is this?
> > 
> > 
> > > @@ -816,13 +839,64 @@
> > >  		case 'k' :
> > >  			break;		/* do nothing */
> > >  
> > > +		case 'R':
> > > +			/* RNN[:SS],	Set the value of CPU register NN (size SS) */
> > > +			/* FALL THROUGH */
> > 
> > 
> > > -		/*
> > > -		 * Reset the whole machine (FIXME: system dependent)
> > > -		 */
> > >  		case 'r':
> > > -			break;
> > > +			/* rNN[:SS]	Return the value of CPU register NN (size SS) */
> > 
> > 
> > 
> > We're not making up a protocol here, we're implementing one.  R and r
> > don't have anything to do with setting registers.
> 
> Hi Dan
> 
> Actually Carsten *is* trying to implement a protocol, it's just that
> it's an extension to the gdb remote debug protocol, as used in our
> SDE-MIPS toolchain (viz sde-gdb).  Algorithmics (now MIPS Technologies
> UK), always extended the gdb remote debug protocol to support reading
> and writing of single registers, and to support variable register
> sizes (to allow a 64-bit debug stub to inter-work with gdb debugging a
> 32-bit application).

My point is that we implement the GDB protocol, for use with GDB -
implementing random extensions to it is not a good idea.  I would
strongly prefer these extensions be discussed on the GDB list before
you try adding them to the CVS tree.  Also, I bet Andrew has a
different idea of how the 64/32 thing ought to work than you do.  He's
the remote protocol maintainer.

These things should be planned on the GDB side before making yet more
stubs use them.

> When we first implemented these extensions we used the 'R' command to
> write a single register, and 'r' to read one (they weren't then used
> by gdb). Since then the remote protocol has gained the 'P' command to

'R' was added in 1995 according to my records.  Really?

> write a single register, so we no longer use 'R' - and it would be
> dangerous to do so since it can restart the target (so you can get rid
> of the special 'R' case, Carsten).
> 
> But the standard gdb remote protocol still doesn't have the ability to
> read a single register, so I believe that 'r' (or something like it)
> is a useful addition, which speeds up the remote protocol
> significantly when running over a serial line. And it won't break the
> kernel to add support for this extension.

The protocol does, actually.  GDB doesn't _implement_ it, but the
extension is documented in the manual ('p') and I wouldn't be surprised
if Red Hat actually had an implementation somewhere.  I recommend the
documentation of the protocol, on the GDB web site.

Also note that `R' is extended restart process; the manual lists `r' as
"restart entire target system".  I don't know when that was used but
it's reason enough to stay away from using that letter to read a
register.

-- 
Daniel Jacobowitz
MontaVista Software                         Debian GNU/Linux Developer

From nigel@mips.com Tue Dec 10 21:40:55 2002
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Daniel Jacobowitz wrote:

>>Actually Carsten *is* trying to implement a protocol, it's just that
>>it's an extension to the gdb remote debug protocol, as used in our
>>SDE-MIPS toolchain (viz sde-gdb).  Algorithmics (now MIPS Technologies
>>UK), always extended the gdb remote debug protocol to support reading
>>and writing of single registers, and to support variable register
>>sizes (to allow a 64-bit debug stub to inter-work with gdb debugging a
>>32-bit application).
>>    
>>
>
>My point is that we implement the GDB protocol, for use with GDB -
>implementing random extensions to it is not a good idea.  I would
>strongly prefer these extensions be discussed on the GDB list before
>you try adding them to the CVS tree.  Also, I bet Andrew has a
>different idea of how the 64/32 thing ought to work than you do.  He's
>the remote protocol maintainer.
>

>These things should be planned on the GDB side before making yet more
>stubs use them.
>  
>

I thought the Linux community prided itself on inventing new and 
"non-standard" extensions to the toolchain  ;-). But yes, we should try 
to avoid incompatible changes. As part of MIPS we will hopefully have 
the resources to interface with the rest of the GNU community, and argue 
for the inclusion of our patches in the CVS trees.

>>When we first implemented these extensions we used the 'R' command to
>>write a single register, and 'r' to read one (they weren't then used
>>by gdb). Since then the remote protocol has gained the 'P' command to
>>    
>>
>
>'R' was added in 1995 according to my records.  Really?
>  
>

Yup. SDE-MIPS 1.1 shipped in 1992. :-)

>The protocol does, actually.  GDB doesn't _implement_ it, but the
>extension is documented in the manual ('p') and I wouldn't be surprised
>if Red Hat actually had an implementation somewhere.  I recommend the
>documentation of the protocol, on the GDB web site.
>
>Also note that `R' is extended restart process; the manual lists `r' as
>"restart entire target system".  I don't know when that was used but
>it's reason enough to stay away from using that letter to read a
>register.
>  
>
Yeah, that's why we dropped 'R' in our more recent gdb ports, but I 
wasn't aware of the new use of 'r' - I'll check out that page. 
 Certainly 'p' is the logical inverse of 'P', so we'll change our gdb 
remote stub to use that. So how about accepting Carsten's change, with 
the 'R' case removed, and 'r' changed to 'p'?

Nigel

-- 
                         Nigel Stephens         Mailto:nigel@mips.com
    _    _ ____  ___     MIPS Technologies (UK) Phone.: +44 1223 706200
    |\  /|||___)(___     The Fruit Farm         Direct: +44 1223 706207
    | \/ |||    ____)    Ely Road, Chittering   Fax...: +44 1223 706250
    TECHNOLOGIES (UK)    Cambridge CB5 9PH      Cell..: +44 7976 686470
 [formerly Algorithmics] England                http://www.algor.co.uk




From brian@murphy.dk Tue Dec 10 22:00:54 2002
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ilya@theIlya.com wrote:

>Following small patch is needed to prevent kernel from going into infinite loop
>on page_fault. Probably similar patches are needed for other CPUs as well,
>but since I don;t have any, I'll let those who do take care of that :)
>
>	Ilya.
>
>  
>
It also seems not to work for the 32 bit kernel. The macro for

pte_offset_map

is very different in pgtable.h in the 32 bit directory than the 64 bit.

(Is there a good reason for this Ralf?)

/Brian


From jsun@orion.mvista.com Wed Dec 11 03:20:55 2002
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From: Jun Sun <jsun@mvista.com>
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I am chasing a problem which might be a cache aliasing problem
when a disk file is opened with O_DIRECT flag.

I attached the source code of two programs.  One generates a binary file
and the other opens the file with O_DIRECT and reads it.  It checks
the content of the file while reading it.

I tested this on a MIPS board with NEC vr5432 CPU, which has a
virtually indexed, two-way set associative d-cache, and can easily 
re-produce the data corruption problem.

I attached a patch which apparently solves the problem.

I am not an expert in fs and mm, but my guess is:

1) user process allocates a big buffer
2) the user buffer is mapped into kernel virtual space for doing direct IO 
   through map_user_kiobuf()
3) since the virtual address for buffer area is different in user space
   from that in kernel virtual, kernel should do a flush cache for those
   pages after doing the IO.  That is why my attached patch makes it work.

Does this make sense?

However, I still have some puzzles.  For it to work completely, another
cache flushing needs to be done for the address range of the buffer in user
space.  I thought this should be done some where inside map_user_kiobuf()
but could not find it anywhere.  Did I miss it?  Or it just happens to work
even without it?

Another puzzling part is that I also tested the program on another couple
of MIPS boards which *should* suffer from this problem, but failed to 
re-produce it.

Any thoughts?

Jun

From jsun@orion.mvista.com Wed Dec 11 03:32:57 2002
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--Yylu36WmvOXNoKYn
Content-Type: text/plain; charset=us-ascii
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... forgot the attachment, possibly due to the same memory 
corruption problem. :-)

Also, the problem is discovered in 2.4.18.  I checked with 2.4.19
and it appears it should be there as well.

Jun

On Tue, Dec 10, 2002 at 06:20:51PM -0800, Jun Sun wrote:
> 
> I am chasing a problem which might be a cache aliasing problem
> when a disk file is opened with O_DIRECT flag.
> 
> I attached the source code of two programs.  One generates a binary file
> and the other opens the file with O_DIRECT and reads it.  It checks
> the content of the file while reading it.
> 
> I tested this on a MIPS board with NEC vr5432 CPU, which has a
> virtually indexed, two-way set associative d-cache, and can easily 
> re-produce the data corruption problem.
> 
> I attached a patch which apparently solves the problem.
> 
> I am not an expert in fs and mm, but my guess is:
> 
> 1) user process allocates a big buffer
> 2) the user buffer is mapped into kernel virtual space for doing direct IO 
>    through map_user_kiobuf()
> 3) since the virtual address for buffer area is different in user space
>    from that in kernel virtual, kernel should do a flush cache for those
>    pages after doing the IO.  That is why my attached patch makes it work.
> 
> Does this make sense?
> 
> However, I still have some puzzles.  For it to work completely, another
> cache flushing needs to be done for the address range of the buffer in user
> space.  I thought this should be done some where inside map_user_kiobuf()
> but could not find it anywhere.  Did I miss it?  Or it just happens to work
> even without it?
> 
> Another puzzling part is that I also tested the program on another couple
> of MIPS boards which *should* suffer from this problem, but failed to 
> re-produce it.
> 
> Any thoughts?
> 
> Jun
> 

--Yylu36WmvOXNoKYn
Content-Type: text/plain; charset=us-ascii
Content-Disposition: attachment; filename="gen-file.c"


/*
 * generate a binary file with 33554432/4 32-bit integers.  The
 * integers range from 0 to 33554432/4-1.
 *
 * This file is used by my-diotest.c.
 */

#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>

#define		TOTAL_SIZE		33554432

main()
{
	int intsize=TOTAL_SIZE/4;
	int f;
	int i;
	int ret;
	assert(sizeof(i) == 4);
	f=open("srcdata-ordered", O_RDWR | O_CREAT);
	assert(f > 0);
	for (i=0; i< intsize; i++) {
		ret=write(f, &i, sizeof(i));
		assert(ret == sizeof(i));
	}
	close(f);
}

--Yylu36WmvOXNoKYn
Content-Type: text/plain; charset=us-ascii
Content-Disposition: attachment; filename="my-diotest.c"


/*
 * test program to demonstrate possible cache aliasing problem with O_DRECT
 * option on IDE files.
 *
 * Problem exists on NEC rochopper boards with vr5432/vr5500 CPUs.  However
 * it did not show up with vr4131 cpu and toshiba CPUs, which is unexpected.
 */

#define _GNU_SOURCE
#include <stdio.h>
#include <unistd.h>
#include <sys/mman.h>

#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>

#define IOSIZE  32768

void *aligned_alloc(int size, int align)
{
	void *p = malloc(size + align);
	return (void*) (((unsigned)p + align-1) / align * align);
}

void check_buffer(char *p, int round)
{
	int *q= (int*)p;
	int intsize = IOSIZE / 4;
	int i;
	int base=round*intsize;
	for (i=0; i< intsize; i++, q++)	
		if (*q != base+i) 
			printf("error at (%d, %d): got %d, expect %d\n",
				round, i, *q, base+i);
}

void dcp(int sfd)
{
	int zfd;
	int r, w;
	char *p;
	int round=0;

#if 0
	zfd = open("/dev/zero", O_RDWR);
	p = mmap(NULL, IOSIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE, zfd, 0);
	close(zfd);
#endif
	p = aligned_alloc(IOSIZE, 4096);
	printf("buffer alloced/mapped to memory area: %x\n", p);

	while (1) {
		memset(p, 0, IOSIZE);
		r = read(sfd, p, IOSIZE);
		if (r <= 0) break;
		check_buffer(p, round);
		round++;
	}
}

int
main(int argc, char *argv[])
{
	int sfd;
	int ret;

	sfd = open(argv[1], O_RDONLY | O_DIRECT);
	printf ("sfd ret = %d\n", sfd);
	dcp(sfd);
	return 0;
}

--Yylu36WmvOXNoKYn
Content-Type: text/plain; charset=us-ascii
Content-Disposition: attachment; filename="o_direct-cache-flush.patch"

diff -Nru mm/filemap.c.orig mm/filemap.c
--- mm/filemap.c.orig	Mon Dec  9 18:27:41 2002
+++ mm/filemap.c	Tue Dec 10 17:13:41 2002
@@ -1550,9 +1550,13 @@
 
 		retval = mapping->a_ops->direct_IO(rw, inode, iobuf, (offset+progress) >> blocksize_bits, blocksize);
 
-		if (rw == READ && retval > 0)
+		if (rw == READ && retval > 0) {
+			int i;
+			for (i=0; i< iobuf->nr_pages; i++)
+				flush_page_to_ram(iobuf->maplist[i]);
 			mark_dirty_kiobuf(iobuf, retval);
-		
+		}
+
 		if (retval >= 0) {
 			count -= retval;
 			buf += retval;

--Yylu36WmvOXNoKYn--

From carstenl@mips.com Wed Dec 11 09:34:38 2002
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Date: Wed, 11 Dec 2002 09:20:28 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Malta board patch
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I have attached a patch, with some minor changes for the Malta board.

/Carsten

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



--------------93A4B8413635DC7FA812BDF8
Content-Type: text/plain; charset=iso-8859-15;
 name="malta.patch"
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 filename="malta.patch"

Index: arch/mips/mips-boards/generic/memory.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mips-boards/generic/memory.c,v
retrieving revision 1.6.2.1
diff -u -r1.6.2.1 memory.c
--- arch/mips/mips-boards/generic/memory.c	5 Aug 2002 23:53:34 -0000	1.6.2.1
+++ arch/mips/mips-boards/generic/memory.c	11 Dec 2002 08:11:56 -0000
@@ -168,7 +168,7 @@
 			      + boot_mem_map.map[i].size) {
 			ClearPageReserved(virt_to_page(__va(addr)));
 			set_page_count(virt_to_page(__va(addr)), 1);
-			free_page(__va(addr));
+			free_page((unsigned long)__va(addr));
 			addr += PAGE_SIZE;
 			freed += PAGE_SIZE;
 		}
Index: arch/mips/mips-boards/generic/pci.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mips-boards/generic/pci.c,v
retrieving revision 1.5.2.4
diff -u -r1.5.2.4 pci.c
--- arch/mips/mips-boards/generic/pci.c	28 Sep 2002 18:28:44 -0000	1.5.2.4
+++ arch/mips/mips-boards/generic/pci.c	11 Dec 2002 08:11:56 -0000
@@ -405,6 +405,12 @@
 			".set\treorder");
 
 		irq = *(volatile u32 *)(KSEG1ADDR(BONITO_PCICFG_BASE));
+		__asm__ __volatile__(
+			".set\tnoreorder\n\t"
+			".set\tnoat\n\t"
+			"sync\n\t"
+			".set\tat\n\t"
+			".set\treorder");
 		irq &= 0xff;
 		BONITO_PCIMAP_CFG = 0;
 		break;
Index: arch/mips/mips-boards/malta/malta_int.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mips-boards/malta/malta_int.c,v
retrieving revision 1.8.2.6
diff -u -r1.8.2.6 malta_int.c
--- arch/mips/mips-boards/malta/malta_int.c	5 Aug 2002 23:53:34 -0000	1.8.2.6
+++ arch/mips/mips-boards/malta/malta_int.c	11 Dec 2002 08:11:57 -0000
@@ -91,6 +91,9 @@
 {
         unsigned int data,datahi;
 
+	/* Mask out corehi interrupt. */
+	clear_c0_status(IE_IRQ3);
+
         printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
         printk("epc   : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
 , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
@@ -125,7 +128,6 @@
 
         /* We die here*/
         die("CoreHi interrupt", regs);
-        while (1) ;
 }
 
 void __init init_IRQ(void)
Index: include/asm-mips/mips-boards/malta.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/mips-boards/malta.h,v
retrieving revision 1.1.4.2
diff -u -r1.1.4.2 malta.h
--- include/asm-mips/mips-boards/malta.h	5 Aug 2002 23:53:38 -0000	1.1.4.2
+++ include/asm-mips/mips-boards/malta.h	11 Dec 2002 08:12:17 -0000
@@ -32,9 +32,23 @@
  * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
  * Bonito system controllers.
  */
-#define MALTA_GT_PORT_BASE      (KSEG1ADDR(0x18000000))
+#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
 #define MALTA_BONITO_PORT_BASE  (KSEG1ADDR(0x1fd00000))
-#define MALTA_MSC_PORT_BASE     (KSEG1ADDR(0x18000000))
+#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
+
+static inline unsigned long get_gt_port_base(unsigned long reg)
+{
+	unsigned long addr;
+	GT_READ(reg, addr);
+	return KSEG1ADDR((addr & 0xffff) << 21);
+}
+
+static inline unsigned long get_msc_port_base(unsigned long reg)
+{
+	unsigned long addr;
+	MSC_READ(reg, addr);
+	return KSEG1ADDR(addr);
+}
 
 /*
  * Malta RTC-device indirect register access.
@@ -58,5 +72,7 @@
 #define SMSC_CONFIG_ACTIVATE_ENABLE   1
 
 #define SMSC_WRITE(x,a)     outb(x,a)
+
+#define MALTA_JMPRS_REG		(KSEG1ADDR(0x1f000210))
 
 #endif /* !(_MIPS_MALTA_H) */
Index: include/asm-mips64/mips-boards/malta.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips64/mips-boards/malta.h,v
retrieving revision 1.1.2.2
diff -u -r1.1.2.2 malta.h
--- include/asm-mips64/mips-boards/malta.h	5 Aug 2002 23:53:39 -0000	1.1.2.2
+++ include/asm-mips64/mips-boards/malta.h	11 Dec 2002 08:12:18 -0000
@@ -32,9 +32,23 @@
  * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
  * Bonito system controllers.
  */
-#define MALTA_GT_PORT_BASE      (KSEG1ADDR(0x18000000))
+#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
 #define MALTA_BONITO_PORT_BASE  (KSEG1ADDR(0x1fd00000))
-#define MALTA_MSC_PORT_BASE     (KSEG1ADDR(0x18000000))
+#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
+
+static inline unsigned long get_gt_port_base(unsigned long reg)
+{
+	unsigned long addr;
+	GT_READ(reg, addr);
+	return KSEG1ADDR((addr & 0xffff) << 21);
+}
+
+static inline unsigned long get_msc_port_base(unsigned long reg)
+{
+	unsigned long addr;
+	MSC_READ(reg, addr);
+	return KSEG1ADDR(addr);
+}
 
 /*
  * Malta RTC-device indirect register access.
@@ -58,5 +72,7 @@
 #define SMSC_CONFIG_ACTIVATE_ENABLE   1
 
 #define SMSC_WRITE(x,a)     outb(x,a)
+
+#define MALTA_JMPRS_REG		(KSEG1ADDR(0x1f000210))
 
 #endif /* !(_MIPS_MALTA_H) */

--------------93A4B8413635DC7FA812BDF8--


From carstenl@mips.com Wed Dec 11 11:56:27 2002
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Date: Wed, 11 Dec 2002 11:56:17 +0100
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Cache routine patch
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--------------6668E66FC3689DF3A63C9826
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I have attached a patch, containing some fixes for some of the cache
routines.
Most of it is related to the MIPS32/MIPS64 specific routines, but it
also contain a fix, which appear to be needed in all of the dma flushing
routines. The problem is that we sometimes flush a cache line too much.
Ralf, could you please take a look at it ?

/Carsten



--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



--------------6668E66FC3689DF3A63C9826
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 filename="cache.patch"

Index: arch/mips/mm/c-mips32.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/c-mips32.c,v
retrieving revision 1.3.2.7
diff -u -r1.3.2.7 c-mips32.c
--- arch/mips/mm/c-mips32.c	2 Dec 2002 00:24:49 -0000	1.3.2.7
+++ arch/mips/mm/c-mips32.c	11 Dec 2002 10:00:18 -0000
@@ -298,13 +298,18 @@
 static void
 mips32_flush_icache_page(struct vm_area_struct *vma, struct page *page)
 {
-	int address;
-
+	/*
+	 * If there's no context yet, or the page isn't executable, no icache 
+	 * flush is needed.
+	 */
 	if (!(vma->vm_flags & VM_EXEC))
 		return;
 
-	address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & (dcache_size - 1));
-	blast_icache_page_indexed(address);
+	/*
+	 * We're not sure of the virtual address(es) involved here, so
+	 * conservatively flush the entire caches.
+	 */
+	flush_cache_all();
 }
 
 /*
@@ -317,11 +322,11 @@
 	unsigned int flags;
 
 	if (size >= dcache_size) {
-		flush_cache_all();
+		blast_dcache();
 	} else {
 	        __save_and_cli(flags);
 		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
+		end = (addr + size - 1) & ~(dc_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
@@ -338,12 +343,12 @@
 	unsigned long end, a;
 
 	if (size >= scache_size) {
-		flush_cache_all();
+		blast_scache();
 		return;
 	}
 
 	a = addr & ~(sc_lsize - 1);
-	end = (addr + size) & ~(sc_lsize - 1);
+	end = (addr + size - 1) & ~(sc_lsize - 1);
 	while (1) {
 		flush_scache_line(a);	/* Hit_Writeback_Inv_SD */
 		if (a == end) break;
@@ -358,13 +363,13 @@
 	unsigned int flags;
 
 	if (size >= dcache_size) {
-		flush_cache_all();
+		blast_dcache();
 	} else {
 	        __save_and_cli(flags);
 		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
+		end = (addr + size - 1) & ~(dc_lsize - 1);
 		while (1) {
-			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
+			invalidate_dcache_line(a); /* Hit_Inv_D */
 			if (a == end) break;
 			a += dc_lsize;
 		}
@@ -380,14 +385,14 @@
 	unsigned long end, a;
 
 	if (size >= scache_size) {
-		flush_cache_all();
+		blast_scache();
 		return;
 	}
 
 	a = addr & ~(sc_lsize - 1);
-	end = (addr + size) & ~(sc_lsize - 1);
+	end = (addr + size - 1) & ~(sc_lsize - 1);
 	while (1) {
-		flush_scache_line(a); /* Hit_Writeback_Inv_SD */
+		invalidate_scache_line(a); /* Hit_Inv_SD */
 		if (a == end) break;
 		a += sc_lsize;
 	}
@@ -412,7 +417,7 @@
 
 static void mips32_flush_icache_all(void)
 {
-	if (mips_cpu.cputype == CPU_20KC) {
+	if (mips_cpu.icache.flags | MIPS_CACHE_VTAG_CACHE) {
 		blast_icache();
 	}
 }
@@ -423,6 +428,7 @@
         unsigned long config1;
 	unsigned int lsize;
 
+	mips_cpu.icache.flags = 0;
         if (!(config & (1 << 31))) {
 	        /*
 		 * Not a MIPS32 complainant CPU.
@@ -452,6 +458,16 @@
 	       ic_lsize = mips_cpu.icache.linesz;
 	       icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways *
 		             ic_lsize;
+
+	       if ((config & 0x8) || (mips_cpu.cputype == CPU_20KC)) {
+		       /* 
+			* The CPU has a virtually tagged I-cache.
+			* Some older 20Kc chips doesn't have the 'VI' bit in
+			* the config register, so we also check for 20Kc.
+			*/
+		       mips_cpu.icache.flags = MIPS_CACHE_VTAG_CACHE;
+		       printk("Virtually tagged I-cache detected\n");
+	       }
 	}
 	printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n",
 	       icache_size >> 10, ic_lsize, mips_cpu.icache.ways);
@@ -462,6 +478,7 @@
         unsigned long config1;
 	unsigned int lsize;
 
+	mips_cpu.dcache.flags = 0;
         if (!(config & (1 << 31))) {
 	        /*
 		 * Not a MIPS32 complainant CPU.
Index: arch/mips/mm/c-r4k.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/c-r4k.c,v
retrieving revision 1.3.2.12
diff -u -r1.3.2.12 c-r4k.c
--- arch/mips/mm/c-r4k.c	6 Dec 2002 18:46:47 -0000	1.3.2.12
+++ arch/mips/mm/c-r4k.c	11 Dec 2002 10:00:18 -0000
@@ -970,7 +970,7 @@
 #endif
 
 		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
+		end = (addr + size - 1) & ~(dc_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
@@ -993,7 +993,7 @@
 	}
 
 	a = addr & ~(sc_lsize - 1);
-	end = (addr + size) & ~(sc_lsize - 1);
+	end = (addr + size - 1) & ~(sc_lsize - 1);
 	while (1) {
 		flush_scache_line(a);	/* Hit_Writeback_Inv_SD */
 		if (a == end) break;
@@ -1016,7 +1016,7 @@
 #endif
 
 		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
+		end = (addr + size - 1) & ~(dc_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
@@ -1040,7 +1040,7 @@
 	}
 
 	a = addr & ~(sc_lsize - 1);
-	end = (addr + size) & ~(sc_lsize - 1);
+	end = (addr + size - 1) & ~(sc_lsize - 1);
 	while (1) {
 		flush_scache_line(a); /* Hit_Writeback_Inv_SD */
 		if (a == end) break;
Index: arch/mips/mm/c-r5432.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/c-r5432.c,v
retrieving revision 1.4.2.3
diff -u -r1.4.2.3 c-r5432.c
--- arch/mips/mm/c-r5432.c	2 Dec 2002 00:24:49 -0000	1.4.2.3
+++ arch/mips/mm/c-r5432.c	11 Dec 2002 10:00:18 -0000
@@ -384,7 +384,7 @@
 		flush_cache_all();
 	} else {
 		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
+		end = (addr + size - 1) & ~(dc_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
@@ -403,7 +403,7 @@
 		flush_cache_all();
 	} else {
 		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
+		end = (addr + size - 1) & ~(dc_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
Index: arch/mips/mm/c-rm7k.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/c-rm7k.c,v
retrieving revision 1.4.2.5
diff -u -r1.4.2.5 c-rm7k.c
--- arch/mips/mm/c-rm7k.c	2 Dec 2002 00:24:49 -0000	1.4.2.5
+++ arch/mips/mm/c-rm7k.c	11 Dec 2002 10:00:18 -0000
@@ -131,7 +131,7 @@
 	unsigned long end, a;
 
 	a = addr & ~(sc_lsize - 1);
-	end = (addr + size) & ~(sc_lsize - 1);
+	end = (addr + size - 1) & ~(sc_lsize - 1);
 	while (1) {
 		flush_dcache_line(a);	/* Hit_Writeback_Inv_D */
 		flush_scache_line(a);	/* Hit_Writeback_Inv_SD */
@@ -143,7 +143,7 @@
 		return;
 
 	a = addr & ~(tc_pagesize - 1);
-	end = (addr + size) & ~(tc_pagesize - 1);
+	end = (addr + size - 1) & ~(tc_pagesize - 1);
 	while(1) {
 		invalidate_tcache_page(a);	/* Page_Invalidate_T */
 		if (a == end) break;
@@ -157,7 +157,7 @@
 	unsigned long end, a;
 
 	a = addr & ~(sc_lsize - 1);
-	end = (addr + size) & ~(sc_lsize - 1);
+	end = (addr + size - 1) & ~(sc_lsize - 1);
 	while (1) {
 		invalidate_dcache_line(a);	/* Hit_Invalidate_D */
 		invalidate_scache_line(a);	/* Hit_Invalidate_SD */
@@ -169,7 +169,7 @@
 		return;
 
 	a = addr & ~(tc_pagesize - 1);
-	end = (addr + size) & ~(tc_pagesize - 1);
+	end = (addr + size - 1) & ~(tc_pagesize - 1);
 	while(1) {
 		invalidate_tcache_page(a);	/* Page_Invalidate_T */
 		if (a == end) break;
Index: arch/mips/mm/c-tx39.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/c-tx39.c,v
retrieving revision 1.4.2.3
diff -u -r1.4.2.3 c-tx39.c
--- arch/mips/mm/c-tx39.c	2 Dec 2002 00:24:50 -0000	1.4.2.3
+++ arch/mips/mm/c-tx39.c	11 Dec 2002 10:00:18 -0000
@@ -65,7 +65,7 @@
 
 	iob();
 	a = addr & ~(dcache_lsize - 1);
-	end = (addr + size) & ~(dcache_lsize - 1);
+	end = (addr + size - 1) & ~(dcache_lsize - 1);
 	while (1) {
 		invalidate_dcache_line(a); /* Hit_Invalidate_D */
 		if (a == end) break;
@@ -198,7 +198,7 @@
 		flush_cache_all();
 	} else {
 		a = addr & ~(dcache_lsize - 1);
-		end = (addr + size) & ~(dcache_lsize - 1);
+		end = (addr + size - 1) & ~(dcache_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
@@ -215,7 +215,7 @@
 		flush_cache_all();
 	} else {
 		a = addr & ~(dcache_lsize - 1);
-		end = (addr + size) & ~(dcache_lsize - 1);
+		end = (addr + size - 1) & ~(dcache_lsize - 1);
 		while (1) {
 			invalidate_dcache_line(a); /* Hit_Invalidate_D */
 			if (a == end) break;
Index: arch/mips/mm/c-tx49.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/c-tx49.c,v
retrieving revision 1.3.2.3
diff -u -r1.3.2.3 c-tx49.c
--- arch/mips/mm/c-tx49.c	2 Dec 2002 00:24:50 -0000	1.3.2.3
+++ arch/mips/mm/c-tx49.c	11 Dec 2002 10:00:18 -0000
@@ -311,7 +311,7 @@
 		__save_and_cli(flags);
 
 		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
+		end = (addr + size - 1) & ~(dc_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
@@ -333,7 +333,7 @@
 		__save_and_cli(flags);
 
 		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
+		end = (addr + size - 1) & ~(dc_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
Index: arch/mips64/mm/c-mips64.c
===================================================================
RCS file: /home/cvs/linux/arch/mips64/mm/c-mips64.c,v
retrieving revision 1.1.2.4
diff -u -r1.1.2.4 c-mips64.c
--- arch/mips64/mm/c-mips64.c	2 Dec 2002 00:24:52 -0000	1.1.2.4
+++ arch/mips64/mm/c-mips64.c	11 Dec 2002 10:00:18 -0000
@@ -301,13 +301,18 @@
 static void
 mips64_flush_icache_page(struct vm_area_struct *vma, struct page *page)
 {
-	unsigned long address;
-
+	/*
+	 * If there's no context yet, or the page isn't executable, no icache 
+	 * flush is needed.
+	 */
 	if (!(vma->vm_flags & VM_EXEC))
 		return;
 
-	address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & ((unsigned long)icache_size - 1));
-	blast_icache_page_indexed(address);
+	/*
+	 * We're not sure of the virtual address(es) involved here, so
+	 * conservatively flush the entire caches.
+	 */
+	flush_cache_all();
 }
 
 /*
@@ -324,7 +329,7 @@
 	} else {
 	        __save_and_cli(flags);
 		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~((unsigned long)dc_lsize - 1);
+		end = (addr + size - 1) & ~((unsigned long)dc_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
@@ -346,7 +351,7 @@
 	}
 
 	a = addr & ~(sc_lsize - 1);
-	end = (addr + size) & ~(sc_lsize - 1);
+	end = (addr + size - 1) & ~(sc_lsize - 1);
 	while (1) {
 		flush_scache_line(a);	/* Hit_Writeback_Inv_SD */
 		if (a == end) break;
@@ -365,7 +370,7 @@
 	} else {
 	        __save_and_cli(flags);
 		a = addr & ~((unsigned long)dc_lsize - 1);
-		end = (addr + size) & ~((unsigned long)dc_lsize - 1);
+		end = (addr + size - 1) & ~((unsigned long)dc_lsize - 1);
 		while (1) {
 			invalidate_dcache_line(a); /* Hit_Inv_D */
 			if (a == end) break;
@@ -388,7 +393,7 @@
 	}
 
 	a = addr & ~(sc_lsize - 1);
-	end = (addr + size) & ~(sc_lsize - 1);
+	end = (addr + size - 1) & ~(sc_lsize - 1);
 	while (1) {
 		invalidate_scache_line(a); /* Hit_Writeback_Inv_SD */
 		if (a == end) break;
@@ -416,7 +421,7 @@
 static void
 mips64_flush_icache_all(void)
 {
-	if (mips_cpu.cputype == CPU_20KC) {
+	if (mips_cpu.icache.flags | MIPS_CACHE_VTAG_CACHE) {
 		blast_icache();
 	}
 }
@@ -428,6 +433,7 @@
         unsigned long config1;
 	unsigned int lsize;
 
+	mips_cpu.icache.flags = 0;
         if (!(config & (1 << 31))) {
 	        /*
 		 * Not a MIPS64 complainant CPU.
@@ -457,6 +463,16 @@
 	       ic_lsize = mips_cpu.icache.linesz;
 	       icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways *
 		             ic_lsize;
+
+	       if ((config & 0x8) || (mips_cpu.cputype == CPU_20KC)) {
+		       /* 
+			* The CPU has a virtually tagged I-cache.
+			* Some older 20Kc chips doesn't have the 'VI' bit in
+			* the config register, so we also check for 20Kc.
+			*/
+		       mips_cpu.icache.flags = MIPS_CACHE_VTAG_CACHE;
+		       printk("Virtually tagged I-cache detected\n");
+	       }
 	}
 	printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n",
 	       icache_size >> 10, ic_lsize, mips_cpu.icache.ways);
@@ -467,6 +483,7 @@
         unsigned long config1;
 	unsigned int lsize;
 
+	mips_cpu.dcache.flags = 0;
         if (!(config & (1 << 31))) {
 	        /*
 		 * Not a MIPS64 complainant CPU.
Index: include/asm-mips/cache.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/cache.h,v
retrieving revision 1.10.2.1
diff -u -r1.10.2.1 cache.h
--- include/asm-mips/cache.h	27 Jun 2002 14:21:23 -0000	1.10.2.1
+++ include/asm-mips/cache.h	11 Dec 2002 10:00:22 -0000
@@ -27,6 +27,7 @@
  * Flag definitions
  */
 #define MIPS_CACHE_NOT_PRESENT 0x00000001
+#define MIPS_CACHE_VTAG_CACHE  0x00000002 /* Virtually tagged cache. */
 
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R6000) || defined(CONFIG_CPU_TX39XX)
 #define L1_CACHE_BYTES		16
Index: include/asm-mips/mips32_cache.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/mips32_cache.h,v
retrieving revision 1.2.2.1
diff -u -r1.2.2.1 mips32_cache.h
--- include/asm-mips/mips32_cache.h	5 Aug 2002 23:53:37 -0000	1.2.2.1
+++ include/asm-mips/mips32_cache.h	11 Dec 2002 10:00:22 -0000
@@ -37,45 +37,70 @@
 
 static inline void flush_icache_line_indexed(unsigned long addr)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		".set mips3\n\t"
-		"cache %1, (%0)\n\t"
-		".set mips0\n\t"
-		".set reorder"
-		:
-		: "r" (addr),
-		  "i" (Index_Invalidate_I));
+	unsigned long waystep = icache_size/mips_cpu.icache.ways;
+	unsigned int way;
+
+	for (way = 0; way < mips_cpu.icache.ways; way++)
+	{
+		__asm__ __volatile__(
+			".set noreorder\n\t"
+			".set mips3\n\t"
+			"cache %1, (%0)\n\t"
+			".set mips0\n\t"
+			".set reorder"
+			:
+			: "r" (addr),
+			"i" (Index_Invalidate_I));
+		
+		addr += waystep;
+	}
 }
 
 static inline void flush_dcache_line_indexed(unsigned long addr)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		".set mips3\n\t"
-		"cache %1, (%0)\n\t"
-		".set mips0\n\t"
-		".set reorder"
-		:
-		: "r" (addr),
-		  "i" (Index_Writeback_Inv_D));
+	unsigned long waystep = dcache_size/mips_cpu.dcache.ways;
+	unsigned int way;
+
+	for (way = 0; way < mips_cpu.dcache.ways; way++)
+	{
+		__asm__ __volatile__(
+			".set noreorder\n\t"
+			".set mips3\n\t"
+			"cache %1, (%0)\n\t"
+			".set mips0\n\t"
+			".set reorder"
+			:
+			: "r" (addr),
+			"i" (Index_Writeback_Inv_D));
+
+		addr += waystep;
+	}
 }
 
 static inline void flush_scache_line_indexed(unsigned long addr)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		".set mips3\n\t"
-		"cache %1, (%0)\n\t"
-		".set mips0\n\t"
-		".set reorder"
-		:
-		: "r" (addr),
-		  "i" (Index_Writeback_Inv_SD));
+	unsigned long waystep = scache_size/mips_cpu.scache.ways;
+	unsigned int way;
+
+	for (way = 0; way < mips_cpu.scache.ways; way++)
+	{
+		__asm__ __volatile__(
+			".set noreorder\n\t"
+			".set mips3\n\t"
+			"cache %1, (%0)\n\t"
+			".set mips0\n\t"
+			".set reorder"
+			:
+			: "r" (addr),
+			"i" (Index_Writeback_Inv_SD));
+
+		addr += waystep;
+	}
 }
 
 static inline void flush_icache_line(unsigned long addr)
 {
+
 	__asm__ __volatile__(
 		".set noreorder\n\t"
 		".set mips3\n\t"
@@ -210,12 +235,17 @@
 
 static inline void blast_dcache_page_indexed(unsigned long page)
 {
-	unsigned long start = page;
-	unsigned long end = (start + PAGE_SIZE);
-
-	while(start < end) {
-		cache_unroll(start,Index_Writeback_Inv_D);
-		start += dc_lsize;
+	unsigned long start;
+	unsigned long end = (page + PAGE_SIZE);
+	unsigned long waystep = dcache_size/mips_cpu.dcache.ways;
+	unsi