From owner-linux-mips@oss.sgi.com Sat Jun  1 11:41:49 2002
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Date: Fri, 31 May 2002 23:20:21 +0200
From: Florian Lohoff <flo@rfc822.org>
To: James Simmons <jsimmons@transvirtual.com>
Cc: linux-mips <linux-mips@oss.sgi.com>
Subject: Re: New platforms
Message-ID: <20020531212021.GA19878@paradigm.rfc822.org>
References: <Pine.LNX.4.44.0205301532510.9702-100000@ns2.total-knowledge.com> <Pine.LNX.4.44.0205311216320.3190-100000@www.transvirtual.com>
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On Fri, May 31, 2002 at 12:17:41PM -0700, James Simmons wrote:
>=20
> No. I'm talking about having a BK tree to use to sync up to Linus with.
> This way the OSS and SF tree and push into the BK tree and have no issues.
>=20

I dont know how others feel which would need to work more with this but
i don't like BK's license (and its advocat Larry 'need to earn money' McVoy=
).

Forcing people into creating seperate trees due to licensing issues of
the SCCS is not really something we need now.

Flo
--=20
Florian Lohoff                  flo@rfc822.org             +49-5201-669912
                        Heisenberg may have been here.

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From owner-linux-mips@oss.sgi.com Sat Jun  1 11:41:39 2002
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Date: Fri, 31 May 2002 21:06:24 +0200
From: Brian Murphy <brian@murphy.dk>
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To: linux-mips <linux-mips@oss.sgi.com>
Subject: Patch for support of Lasat 100 and 200 machines (~60k)
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Hi,
    this is the reference source for the lasat platforms.
I have cleaned up the original code to give a patch which
applies against todays tree and produces a running kernel
on both platforms.

The patch adds (v)r5000 cache support, the general stuff
required to add a new platform and some small patches
in various places to fix bugs and add, for example, mtd
support for the flash in these machines.

The files not patched (not existing in the oss CVS) are
in lasat.tar.gz. This includes arch/mips/lasat and
include/asm-mips/lasat - one file to support r5000 cache
support and one for the memory mapped flash modules
to give mtd support. In addition there are two drivers for
the rtc and display in the two machines which have
interface include files in include/linux.

I know I was encouraged to split up this stuff but I could
spend weeks or months doing that and not have something
which would satisfy the authorities - This is my first attempt.
Perhaps, Florian, you can look at it and give me some advice
as to how I should structure any splitting-up to get this
accepted.

If anyone has a masquerade (or safepipe) box then you will
also need the information on http://debian.murphy.dk to get
this stuff uploaded on your box. Any problems, send me a
mail.

regards
/Brian

--------------040102050900040803070107
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? arch/mips/defconfig-lasat100
? arch/mips/defconfig-lasat200
? arch/mips/lasat
? arch/mips/patch
? arch/mips/mm/c-r5000.c
? drivers/mtd/maps/lasat.c
? include/asm-mips/lasat
? include/linux/ds1603.h
? include/linux/picvue.h
Index: arch/mips/Makefile
===================================================================
RCS file: /cvs/linux/arch/mips/Makefile,v
retrieving revision 1.78.2.2
diff -u -r1.78.2.2 Makefile
--- arch/mips/Makefile	2002/02/15 21:05:47	1.78.2.2
+++ arch/mips/Makefile	2002/05/30 10:33:14
@@ -77,6 +77,9 @@
 ifdef CONFIG_CPU_R5000
 GCCFLAGS	+= -mcpu=r5000 -mips2 -Wa,--trap
 endif
+ifdef CONFIG_CPU_VR5000
+GCCFLAGS	+= -mcpu=vr5000 -mips2 -Wa,--trap
+endif
 ifdef CONFIG_CPU_R5432
 GCCFLAGS        += -mcpu=r5000 -mips2 -Wa,--trap
 endif
@@ -288,7 +291,14 @@
 LOADADDR      += 0x80100000
 endif
 
+ifdef CONFIG_LASAT
+LIBS          += arch/mips/lasat/lasatkern.o
+SUBDIRS       += arch/mips/lasat
+LOADADDR      += 0x80000000
+endif
+
 #
+#
 # Au1000 eval board
 #
 ifdef CONFIG_MIPS_PB1000
@@ -379,6 +389,11 @@
 endif
 
 MAKEBOOT = $(MAKE) -C arch/$(ARCH)/boot
+
+ifdef CONFIG_LASAT
+rom.bin: vmlinux
+		$(MAKE) -C arch/$(ARCH)/lasat/image $@
+endif
 
 vmlinux.ecoff: vmlinux
 	@$(MAKEBOOT) $@
Index: arch/mips/config.in
===================================================================
RCS file: /cvs/linux/arch/mips/config.in,v
retrieving revision 1.154.2.19
diff -u -r1.154.2.19 config.in
--- arch/mips/config.in	2002/05/29 14:30:49	1.154.2.19
+++ arch/mips/config.in	2002/05/30 10:33:14
@@ -43,6 +43,22 @@
 fi
 dep_bool 'Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)' CONFIG_MIPS_EV96100 $CONFIG_EXPERIMENTAL
 bool 'Support for Globespan IVR board' CONFIG_MIPS_IVR
+bool 'Support for LASAT Networks platforms' CONFIG_LASAT
+if [ "$CONFIG_LASAT" = "y" ]; then
+   bool '  Support for LASAT Networks 100 series' CONFIG_LASAT_100
+   bool '  Support for LASAT Networks 200 series' CONFIG_LASAT_200
+   tristate '  DS1603 rtc support' CONFIG_DS1603
+   tristate '  PICVUE LCD display driver' CONFIG_PICVUE
+   dep_tristate '   PICVUE LCD display driver /proc interface' CONFIG_PICVUE_PROC $CONFIG_PICVUE
+   if [ "$CONFIG_LASAT_100" = "y" ]; then
+      define_bool CONFIG_PCI y
+      define_bool CONFIG_NONCOHERENT_IO y
+   fi
+   if [ "$CONFIG_LASAT_200" = "y" ]; then
+      define_bool CONFIG_PCI y
+      define_bool CONFIG_NONCOHERENT_IO y
+   fi
+fi
 bool 'Support for Hewlett Packard LaserJet board' CONFIG_HP_LASERJET
 bool 'Support for ITE 8172G board' CONFIG_MIPS_ITE8172
 if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
@@ -324,6 +340,7 @@
 	 R4x00	CONFIG_CPU_R4X00 \
 	 R49XX	CONFIG_CPU_TX49XX \
 	 R5000	CONFIG_CPU_R5000 \
+	 VR5000	CONFIG_CPU_VR5000 \
 	 R5432	CONFIG_CPU_R5432 \
 	 RM7000	CONFIG_CPU_RM7000 \
 	 R52xx	CONFIG_CPU_NEVADA \
@@ -355,6 +372,7 @@
 
 if [ "$CONFIG_CPU_R4X00"  = "y" -o \
      "$CONFIG_CPU_R5000" = "y" -o \
+     "$CONFIG_CPU_VR5000" = "y" -o \
      "$CONFIG_CPU_RM7000" = "y" -o \
      "$CONFIG_CPU_R10000" = "y" -o \
      "$CONFIG_CPU_SB1" = "y" -o \
Index: arch/mips/kernel/Makefile
===================================================================
RCS file: /cvs/linux/arch/mips/kernel/Makefile,v
retrieving revision 1.51.2.1
diff -u -r1.51.2.1 Makefile
--- arch/mips/kernel/Makefile	2002/01/24 23:14:24	1.51.2.1
+++ arch/mips/kernel/Makefile	2002/05/30 10:33:15
@@ -32,6 +32,7 @@
 obj-$(CONFIG_CPU_R4300)		+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R4X00)		+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R5000)		+= r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_VR5000)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R5432)		+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_RM7000)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_NEVADA)	+= r4k_fpu.o r4k_switch.o
Index: arch/mips/kernel/setup.c
===================================================================
RCS file: /cvs/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.96.2.17
diff -u -r1.96.2.17 setup.c
--- arch/mips/kernel/setup.c	2002/05/28 05:38:37	1.96.2.17
+++ arch/mips/kernel/setup.c	2002/05/30 10:33:16
@@ -137,7 +137,7 @@
 		printk(" available.\n");
 		break;
 	case CPU_R4200: 
-/*	case CPU_R4300: */
+	case CPU_R4300: 
 	case CPU_R4600: 
 	case CPU_R4640: 
 	case CPU_R4650: 
@@ -762,6 +762,11 @@
 	case MACH_GROUP_PHILIPS:
 		nino_setup();
 		break;
+#endif
+#ifdef CONFIG_LASAT
+        case MACH_GROUP_LASAT:
+                platform_setup();
+                break;
 #endif
 #ifdef CONFIG_MIPS_PB1000
 	case MACH_GROUP_ALCHEMY:
Index: arch/mips/mm/Makefile
===================================================================
RCS file: /cvs/linux/arch/mips/mm/Makefile,v
retrieving revision 1.27
diff -u -r1.27 Makefile
--- arch/mips/mm/Makefile	2001/11/26 13:38:14	1.27
+++ arch/mips/mm/Makefile	2002/05/30 10:33:16
@@ -24,6 +24,7 @@
 obj-$(CONFIG_CPU_R4X00)		+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_VR41XX)	+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_R5000)		+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
+obj-$(CONFIG_CPU_VR5000)	+= pg-r4k.o c-r5000.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_NEVADA)	+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_R5432)		+= pg-r5432.o c-r5432.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_RM7000)	+= pg-rm7k.o c-rm7k.o tlb-r4k.o tlbex-r4k.o
Index: arch/mips/mm/loadmmu.c
===================================================================
RCS file: /cvs/linux/arch/mips/mm/loadmmu.c,v
retrieving revision 1.45
diff -u -r1.45 loadmmu.c
--- arch/mips/mm/loadmmu.c	2001/11/29 04:47:24	1.45
+++ arch/mips/mm/loadmmu.c	2002/05/30 10:33:17
@@ -52,6 +52,7 @@
 
 extern void ld_mmu_r23000(void);
 extern void ld_mmu_r4xx0(void);
+extern void ld_mmu_r5000(void);
 extern void ld_mmu_tx39(void);
 extern void ld_mmu_tx49(void);
 extern void ld_mmu_r5432(void);
@@ -72,6 +73,10 @@
     defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
     defined(CONFIG_CPU_NEVADA)
 		ld_mmu_r4xx0();
+		r4k_tlb_init();
+#endif
+#if defined(CONFIG_CPU_VR5000)
+		ld_mmu_r5000();
 		r4k_tlb_init();
 #endif
 #if defined(CONFIG_CPU_RM7000)
Index: drivers/mtd/maps/Config.in
===================================================================
RCS file: /cvs/linux/drivers/mtd/maps/Config.in,v
retrieving revision 1.3.2.2
diff -u -r1.3.2.2 Config.in
--- drivers/mtd/maps/Config.in	2002/02/15 21:05:48	1.3.2.2
+++ drivers/mtd/maps/Config.in	2002/05/30 10:33:21
@@ -50,6 +50,7 @@
       int '    Bus width in octets' CONFIG_MTD_CSTM_MIPS_IXX_BUSWIDTH 2
    fi
    dep_tristate '  Momenco Ocelot boot flash device' CONFIG_MTD_OCELOT $CONFIG_MOMENCO_OCELOT
+   dep_tristate '  LASAT flash device' CONFIG_MTD_LASAT $CONFIG_MTD_CFI $CONFIG_LASAT
 fi
 
 if [ "$CONFIG_SH" = "y" ]; then
Index: drivers/mtd/maps/Makefile
===================================================================
RCS file: /cvs/linux/drivers/mtd/maps/Makefile,v
retrieving revision 1.2.2.2
diff -u -r1.2.2.2 Makefile
--- drivers/mtd/maps/Makefile	2002/02/15 21:05:48	1.2.2.2
+++ drivers/mtd/maps/Makefile	2002/05/30 10:33:21
@@ -31,5 +31,6 @@
 obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
 obj-$(CONFIG_MTD_PB1000)        += pb1xxx-flash.o
 obj-$(CONFIG_MTD_PB1500)        += pb1xxx-flash.o
+obj-$(CONFIG_MTD_LASAT)     	+= lasat.o
 
 include $(TOPDIR)/Rules.make
Index: drivers/net/pcnet32.c
===================================================================
RCS file: /cvs/linux/drivers/net/pcnet32.c,v
retrieving revision 1.33.2.1
diff -u -r1.33.2.1 pcnet32.c
--- drivers/net/pcnet32.c	2002/02/26 05:59:35	1.33.2.1
+++ drivers/net/pcnet32.c	2002/05/30 10:33:23
@@ -656,7 +656,7 @@
 #if defined(__i386__)
 	    printk(KERN_WARNING "%s: Probably a Compaq, using the PROM address of", dev->name);
 	    memcpy(dev->dev_addr, promaddr, 6);
-#elif defined(__powerpc__)
+#else
 	    if (!is_valid_ether_addr(dev->dev_addr)
 		&& is_valid_ether_addr(promaddr)) {
 		    printk("\n" KERN_WARNING "%s: using PROM address:",
@@ -765,8 +765,12 @@
     if (irq_line) {
 	dev->irq = irq_line;
     }
-    
+
+#ifdef CONFIG_LASAT
+    if (dev->irq >= 0)
+#else
     if (dev->irq >= 2)
+#endif
 	printk(" assigned IRQ %d.\n", dev->irq);
     else {
 	unsigned long irq_mask = probe_irq_on();
@@ -821,7 +825,10 @@
     u16 val;
     int i;
 
-    if (dev->irq == 0 ||
+    if (
+#ifndef CONFIG_LASAT
+	dev->irq == 0 ||
+#endif
 	request_irq(dev->irq, &pcnet32_interrupt,
 		    lp->shared_irq ? SA_SHIRQ : 0, lp->name, (void *)dev)) {
 	return -EAGAIN;
@@ -1343,6 +1350,10 @@
 		if (!rx_in_place) {
 		    skb_reserve(skb,2); /* 16 byte align */
 		    skb_put(skb,pkt_len);	/* Make room */
+                    pci_dma_sync_single(lp->pci_dev, 
+				    lp->rx_skbuff[entry]->tail, 
+				    pkt_len,
+				    PCI_DMA_FROMDEVICE);
 		    eth_copy_and_sum(skb,
 				     (unsigned char *)(lp->rx_skbuff[entry]->tail),
 				     pkt_len,0);
@@ -1664,7 +1675,7 @@
     }
     return -EOPNOTSUPP;
 }
-					    
+
 static struct pci_driver pcnet32_driver = {
 	name:		DRV_NAME,
 	probe:		pcnet32_probe_pci,
Index: drivers/pci/pci.c
===================================================================
RCS file: /cvs/linux/drivers/pci/pci.c,v
retrieving revision 1.48
diff -u -r1.48 pci.c
--- drivers/pci/pci.c	2001/12/02 11:34:45	1.48
+++ drivers/pci/pci.c	2002/05/30 10:33:25
@@ -38,6 +38,8 @@
 LIST_HEAD(pci_root_buses);
 LIST_HEAD(pci_devices);
 
+static int pci_reverse = 0;
+
 /**
  * pci_find_slot - locate PCI device from a given PCI slot
  * @bus: number of PCI bus on which desired PCI device resides
@@ -1327,8 +1329,13 @@
 		 * Link the device to both the global PCI device chain and
 		 * the per-bus list of devices.
 		 */
-		list_add_tail(&dev->global_list, &pci_devices);
-		list_add_tail(&dev->bus_list, &bus->devices);
+		if (!pci_reverse) {
+			list_add_tail(&dev->global_list, &pci_devices);
+			list_add_tail(&dev->bus_list, &bus->devices);
+		} else {
+			list_add(&dev->global_list, &pci_devices);
+			list_add(&dev->bus_list, &bus->devices);
+		}
 
 		/* Fix up broken headers */
 		pci_fixup_device(PCI_FIXUP_HEADER, dev);
@@ -1952,7 +1959,10 @@
 			*k++ = 0;
 		if (*str && (str = pcibios_setup(str)) && *str) {
 			/* PCI layer options should be handled here */
-			printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
+			if (!strcmp(str, "reverse"))
+				pci_reverse = 1;
+			else
+				printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
 		}
 		str = k;
 	}
Index: include/asm-mips/bootinfo.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/bootinfo.h,v
retrieving revision 1.43.2.8
diff -u -r1.43.2.8 bootinfo.h
--- include/asm-mips/bootinfo.h	2002/02/15 21:05:49	1.43.2.8
+++ include/asm-mips/bootinfo.h	2002/05/30 10:33:31
@@ -35,6 +35,7 @@
 #define MACH_GROUP_ALCHEMY     18 /* Alchemy Semi Eval Boards*/
 #define MACH_GROUP_NEC_VR41XX  19 /* NEC Vr41xx based boards/gadgets          */
 #define MACH_GROUP_HP_LJ	20 /* Hewlett Packard LaserJet */
+#define MACH_GROUP_LASAT       21
 
 /*
  * Valid machtype values for group unknown (low order halfword of mips_machtype)
@@ -151,6 +152,12 @@
 #define MACH_TOPAS		1
 #define MACH_JMR		2
 #define MACH_TOSHIBA_JMR3927    3      /* JMR-TX3927 CPU/IO board */
+
+/*
+ * Valid machtype for group LASAT
+ */
+#define MACH_LASAT_100		0	/* Masquerade II/SP100/SP50/SP25 */
+#define MACH_LASAT_200		1	/* Masquerade PRO/SP200 */
 
 /*
  * Valid machtype for group Alchemy
Index: include/asm-mips/cacheops.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/cacheops.h,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 cacheops.h
--- include/asm-mips/cacheops.h	1997/06/01 03:17:12	1.1.1.1
+++ include/asm-mips/cacheops.h	2002/05/30 10:33:31
@@ -35,6 +35,7 @@
 #define Hit_Writeback_Inv_D	0x15
 					/* 0x16 is unused */
 #define Hit_Writeback_Inv_SD	0x17
+#define Page_Invalidate		0x17
 #define Hit_Writeback_I		0x18
 #define Hit_Writeback_D		0x19
 					/* 0x1a is unused */
Index: include/asm-mips/cpu.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/cpu.h,v
retrieving revision 1.24.2.6
diff -u -r1.24.2.6 cpu.h
--- include/asm-mips/cpu.h	2002/05/13 18:54:25	1.24.2.6
+++ include/asm-mips/cpu.h	2002/05/30 10:33:32
@@ -53,6 +53,7 @@
 #define PRID_IMP_R4640		0x2200
 #define PRID_IMP_R4650		0x2200		/* Same as R4640 */
 #define PRID_IMP_R5000		0x2300
+#define PRID_IMP_VR5000		0x2300
 #define PRID_IMP_TX49		0x2d00
 #define PRID_IMP_SONIC		0x2400
 #define PRID_IMP_MAGIC		0x2500
@@ -127,7 +128,7 @@
 	CPU_R5000A, CPU_R4640, CPU_NEVADA, CPU_RM7000, CPU_R5432, CPU_4KC,
 	CPU_5KC, CPU_R4310, CPU_SB1, CPU_TX3912, CPU_TX3922, CPU_TX3927,
 	CPU_AU1000, CPU_4KEC, CPU_4KSC, CPU_VR41XX, CPU_R5500, CPU_TX49XX,
-	CPU_TX39XX, CPU_AU1500, CPU_20KC, CPU_LAST
+	CPU_TX39XX, CPU_AU1500, CPU_20KC, CPU_VR5000, CPU_LAST
 };
 
 #endif
Index: include/asm-mips/r4kcache.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/r4kcache.h,v
retrieving revision 1.8
diff -u -r1.8 r4kcache.h
--- include/asm-mips/r4kcache.h	2001/10/31 02:31:23	1.8
+++ include/asm-mips/r4kcache.h	2002/05/30 10:33:35
@@ -76,6 +76,19 @@
 		  "i" (Hit_Writeback_Inv_D));
 }
 
+extern inline void flush_dcache_line_wb(unsigned long addr)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		".set mips3\n\t"
+		"cache %1, (%0)\n\t"
+		".set mips0\n\t"
+		".set reorder"
+		:
+		: "r" (addr),
+		  "i" (Hit_Writeback_D));
+}
+
 static inline void invalidate_dcache_line(unsigned long addr)
 {
 	__asm__ __volatile__(
@@ -606,6 +619,40 @@
 static inline void blast_scache128_page_indexed(unsigned long page)
 {
 	cache128_unroll32(page,Index_Writeback_Inv_SD);
+}
+
+
+#define cache_unroll(base,op)	        	\
+	__asm__ __volatile__("	         	\
+		.set noreorder;		        \
+		.set mips3;		        \
+                cache %1, (%0);	                \
+		.set mips0;			\
+		.set reorder"			\
+		:				\
+		: "r" (base),			\
+		  "i" (op));
+
+extern inline void blast_r5000_scache(void)
+{
+	unsigned long start = KSEG0;
+	unsigned long end = KSEG0 + scache_size;
+
+	while(start < end) {
+		cache_unroll(start,Page_Invalidate);
+		start += 128*sc_lsize;
+	}
+}
+
+extern inline void blast_r5000_scache_page_indexed(unsigned long page)
+{
+	unsigned long start = page;
+	unsigned long end = page + PAGE_SIZE;
+
+	while(start < end) {
+		cache_unroll(start,Page_Invalidate);
+		start += 128*sc_lsize;
+	}
 }
 
 #endif /* !(_MIPS_R4KCACHE_H) */
Index: include/asm-mips/serial.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/serial.h,v
retrieving revision 1.23.2.2
diff -u -r1.23.2.2 serial.h
--- include/asm-mips/serial.h	2002/01/07 03:33:54	1.23.2.2
+++ include/asm-mips/serial.h	2002/05/30 10:33:35
@@ -144,6 +144,18 @@
 #define IVR_SERIAL_PORT_DEFNS
 #endif
 
+#ifdef CONFIG_LASAT
+#include <asm/lasat/lasatint.h>
+#define LASAT_SERIAL_PORT_DEFNS						\
+	{ baud_base: LASAT_BASE_BAUD, irq: LASATINT_UART,		\
+	  flags: STD_COM_FLAGS,						\
+	  port: LASAT_UART_REGS_BASE, /* Only for display */		\
+	  iomem_base: (u8 *)KSEG1ADDR(LASAT_UART_REGS_BASE),		\
+	  iomem_reg_shift: LASAT_UART_REGS_SHIFT, io_type: SERIAL_IO_MEM }
+#else
+#define LASAT_SERIAL_PORT_DEFNS
+#endif
+
 #ifdef CONFIG_AU1000_UART
 #include <asm/au1000.h>
 #define AU1000_SERIAL_PORT_DEFNS                              \
@@ -286,6 +298,7 @@
 	COBALT_SERIAL_PORT_DEFNS	\
 	EV96100_SERIAL_PORT_DEFNS	\
 	JAZZ_SERIAL_PORT_DEFNS		\
+	LASAT_SERIAL_PORT_DEFNS		\
 	STD_SERIAL_PORT_DEFNS		\
 	EXTRA_SERIAL_PORT_DEFNS		\
 	HUB6_SERIAL_PORT_DFNS		\

--------------040102050900040803070107
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From owner-linux-mips@oss.sgi.com Sat Jun  1 12:42:48 2002
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Date: Sat, 01 Jun 2002 14:43:23 -0500
From: "Steven J. Hill" <sjhill@realitydiluted.com>
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To: James Simmons <jsimmons@transvirtual.com>
CC: linux-mips-kernel@lists.sourceforge.net,
   linux-mips
 <linux-mips@oss.sgi.com>
Subject: Re: TX 3912 framebuffer device
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James Simmons wrote:
> Can the video mode of this device be switched at run time or is it a
> static mode. I'm porting it to the new fbdev api and I want to get it
> right.
> 
 From my work on the 3912, my answer would be yes.

-Steve


From owner-linux-mips@oss.sgi.com Sun Jun  2 03:59:44 2002
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Date: Sun, 2 Jun 2002 12:57:54 +0200 (MEST)
From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Brian Murphy <brian@murphy.dk>
cc: linux-mips <linux-mips@oss.sgi.com>
Subject: Re: Patch for support of Lasat 100 and 200 machines (~60k)
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On Fri, 31 May 2002, Brian Murphy wrote:
> The files not patched (not existing in the oss CVS) are
> in lasat.tar.gz. This includes arch/mips/lasat and
> include/asm-mips/lasat - one file to support r5000 cache

About <asm/lasat/vrc5074.h>: Vrc-5074 definitions already exist in
<asm/nile4.h>.

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


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From: Ralf Baechle <ralf@oss.sgi.com>
To: Raymond Lo <lo@broadon.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: virtual coherency issues with 4Kc ?
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On Fri, May 31, 2002 at 03:22:41PM -0700, Raymond Lo wrote:

> I'm evaluting the MIPS 4Kc core.   One thing I'm trying to find out is 
> how does linux deal with virtual aliasing in the cache for 4Kc.  
> 
> The cache of 4Kc is virtually-indexed and it has no hardware support to 
> suppress virtual aliasing.   The cachetlb.txt under linux/Documentation 
> indicates that two things need to be done in software to handle virtual 
> aliasing in D-cache.
> 
> The first is to handle virtual aliasing in user address spaces.  Shared 
> pages are mmaped at virtual addresses that are multiples of the cache 
> size.   That has already been taked care of in  include/asm-mips/shmparam.h.
> 
> The second is to handle virtual aliasing between kernel virtual address 
> space and user virtual address space by providing a number of functions 
> to flush the cache at various points in the kernel.   The old interface 
> is flush_page_to_ram.   The new ones are
>   copy_user_page,
>   clear_user_page,
>   flush_dcache_page.
> 
> I'm surprised to find out that flush_dcache_page is a macro defined to 
> be  do {} while (0) in linux/asm-mips/pgtable.h.  The source code I 
> looked is the web CVS on oss.sgi.com and 2.4.18.

We simply haven't converted to use the new interfaces yet.

> Apparently the necessary flushing hasn't been done from the mm and fs 
> code for any MIPS port.  I know this is not necessary for R4000 with 
> virtual coherency execptions.

It's still a good idea to not rely on the virtual coherency exception
mechanism which can result in a very significant overhead.

> P.S.   The link http://oss.sgi.com/mips/archive/ is stale.  

  Ralf

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Hello,

At Fri, 31 May 2002 11:28:47 +0900 (JST),
Atsushi Nemoto wrote:
> takeshi_aihana> Is there any inconsistents on those conditions?
> 
> AFAIK, Yes.  For example, look struct ipc_perm in bits/ipc.h and
> struct ipc64_perm in asm-mips/ipcbuf.h (not struct ipc_perm in
> linux/ipc.h which is obsolete).

I did to check both bits/shm.h (glibc-2.2.3), bits/shm.h (glibc-2.2.4) and asm-mips/shmbuf.h
for calling shmctl();
There are any differences 'struct shmid_ds' between glibc-2.2.3 and 2.2.4 that I saw.
However, I do not think those diffs are caused this problem.
Because the 'shm_segsz` which a member of this will be allocated on same location even if the follows members
behind 'shm_segsz' are changed; i.e. it will have same value as 'shm_segsz' on both different structure.
Is this right?

> If you can.  Please do not forget rebuilding all applications which
> including these headers.  If you want to stay in 2.2.3, you will have
> to modify your kernel headers according to the libc headers.

I understood. It might to solve this problem as the most simple way.

Thank you for your advice.
Regards.

---
(TAKESHI - MontaVista Software)

From owner-linux-mips@oss.sgi.com Mon Jun  3 05:48:24 2002
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Date: Mon, 03 Jun 2002 21:49:57 +0900 (JST)
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To: takeshi_aihana@montavista.co.jp
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Subject: Re: (Re-Send) shmctl() returns corrupt value on pb1000.
From: Atsushi Nemoto <nemoto@toshiba-tops.co.jp>
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>>>>> On Mon, 03 Jun 2002 19:09:18 +0900, Takeshi AIHANA <takeshi_aihana@montavista.co.jp> said:
takeshi_aihana> There are any differences 'struct shmid_ds' between
takeshi_aihana> glibc-2.2.3 and 2.2.4 that I saw.  However, I do not
takeshi_aihana> think those diffs are caused this problem.  Because
takeshi_aihana> the 'shm_segsz` which a member of this will be
takeshi_aihana> allocated on same location even if the follows members
takeshi_aihana> behind 'shm_segsz' are changed; i.e. it will have same
takeshi_aihana> value as 'shm_segsz' on both different structure.  Is
takeshi_aihana> this right?

Did you check the contents of 'shm_perm'?  The type of shm_perm is
'struct ipc64_perm' in kernel and 'struct ipc_perm' in libc.  I
suppose these definitions are differ.

---
Atsushi Nemoto

From owner-linux-mips@oss.sgi.com Mon Jun  3 09:44:36 2002
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	Mon, 3 Jun 2002 18:45:51 +0200 (MET DST)
Date: Mon, 3 Jun 2002 18:45:49 +0200 (MET DST)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Ralf Baechle <ralf@uni-koblenz.de>
cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com
Subject: [patch] linux: mb() and friends again
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Hello,

 There was a discussion some time ago upon my proposal of a clean-up of
mb() and related macros.  The conclusion was a rewrite is desireable, but
the patch wasn't accepted and no alternative was proposed.

 The need for the update is more and more crucial for me as I have more
and more code to apply to the tree that needs the macros be set somehow. 
If there is a design flaw, I'd like to know of it, if there is an
implementation problem, I'm willing to fix it.  I'm aware about peripheral
bus-specific coherency problems -- the patch is orthogonal to them and
only addresses the host bus.

 Here is an updated version I'm using currently.  It's fixed to apply
against the current tree and adds <asm-mips64/wbflush.h> for source code
compatibility.

  Maciej

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

patch-mips-2.4.18-20020530-mb-wb-8
diff -up --recursive --new-file linux-mips-2.4.18-20020530.macro/arch/mips/config.in linux-mips-2.4.18-20020530/arch/mips/config.in
--- linux-mips-2.4.18-20020530.macro/arch/mips/config.in	2002-05-30 02:57:35.000000000 +0000
+++ linux-mips-2.4.18-20020530/arch/mips/config.in	2002-06-02 15:51:03.000000000 +0000
@@ -393,6 +393,11 @@ else
       fi
    fi
 fi
+if [ "$CONFIG_CPU_R3000" = "y" ]; then
+   define_bool CONFIG_CPU_HAS_SYNC n
+else
+   define_bool CONFIG_CPU_HAS_SYNC y
+fi
 endmenu
 
 mainmenu_option next_comment
diff -up --recursive --new-file linux-mips-2.4.18-20020530.macro/include/asm-mips/system.h linux-mips-2.4.18-20020530/include/asm-mips/system.h
--- linux-mips-2.4.18-20020530.macro/include/asm-mips/system.h	2002-05-28 10:13:21.000000000 +0000
+++ linux-mips-2.4.18-20020530/include/asm-mips/system.h	2002-06-02 15:51:03.000000000 +0000
@@ -18,9 +18,12 @@
 
 #include <linux/config.h>
 #include <asm/sgidefs.h>
-#include <asm/ptrace.h>
+
 #include <linux/kernel.h>
 
+#include <asm/addrspace.h>
+#include <asm/ptrace.h>
+
 __asm__ (
 	".macro\t__sti\n\t"
 	".set\tpush\n\t"
@@ -166,32 +169,58 @@ extern void __global_restore_flags(unsig
 #define local_irq_disable()	__cli()
 #define local_irq_enable()	__sti()
 
-/*
- * These are probably defined overly paranoid ...
- */
+#ifdef CONFIG_CPU_HAS_SYNC
+#define __sync()				\
+	__asm__ __volatile__(			\
+		".set	push\n\t"		\
+		".set	noreorder\n\t"		\
+		".set	mips2\n\t"		\
+		"sync\n\t"			\
+		".set	pop"			\
+		: /* no output */		\
+		: /* no input */		\
+		: "memory")
+#else
+#define __sync()	do { } while(0)
+#endif
+
+#define __fast_iob()				\
+	__asm__ __volatile__(			\
+		".set	push\n\t"		\
+		".set	noreorder\n\t"		\
+		"lw	$0,%0\n\t"		\
+		"nop\n\t"			\
+		".set	pop"			\
+		: /* no output */		\
+		: "m" (*(int *)KSEG1)		\
+		: "memory")
+
+#define fast_wmb()	__sync()
+#define fast_rmb()	__sync()
+#define fast_mb()	__sync()
+#define fast_iob()				\
+	do {					\
+		__sync();			\
+		__fast_iob();			\
+	} while (0)
+
 #ifdef CONFIG_CPU_HAS_WB
 
 #include <asm/wbflush.h>
-#define rmb()	do { } while(0)
-#define wmb()	wbflush()
-#define mb()	wbflush()
-
-#else /* CONFIG_CPU_HAS_WB  */
-
-#define mb()						\
-__asm__ __volatile__(					\
-	"# prevent instructions being moved around\n\t"	\
-	".set\tnoreorder\n\t"				\
-	"# 8 nops to fool the R4400 pipeline\n\t"	\
-	"nop;nop;nop;nop;nop;nop;nop;nop\n\t"		\
-	".set\treorder"					\
-	: /* no output */				\
-	: /* no input */				\
-	: "memory")
-#define rmb() mb()
-#define wmb() mb()
 
-#endif /* CONFIG_CPU_HAS_WB  */
+#define wmb()		fast_wmb()
+#define rmb()		fast_rmb()
+#define mb()		wbflush();
+#define iob()		wbflush();
+
+#else /* !CONFIG_CPU_HAS_WB */
+
+#define wmb()		fast_wmb()
+#define rmb()		fast_rmb()
+#define mb()		fast_mb()
+#define iob()		fast_iob()
+
+#endif /* !CONFIG_CPU_HAS_WB */
 
 #ifdef CONFIG_SMP
 #define smp_mb()	mb()
diff -up --recursive --new-file linux-mips-2.4.18-20020530.macro/include/asm-mips/wbflush.h linux-mips-2.4.18-20020530/include/asm-mips/wbflush.h
--- linux-mips-2.4.18-20020530.macro/include/asm-mips/wbflush.h	2001-09-07 04:26:33.000000000 +0000
+++ linux-mips-2.4.18-20020530/include/asm-mips/wbflush.h	2002-02-04 02:52:11.000000000 +0000
@@ -6,29 +6,30 @@
  * for more details.
  *
  * Copyright (c) 1998 Harald Koerfgen
+ * Copyright (C) 2002 Maciej W. Rozycki
  */
 #ifndef __ASM_MIPS_WBFLUSH_H
 #define __ASM_MIPS_WBFLUSH_H
 
 #include <linux/config.h>
 
-#if defined(CONFIG_CPU_HAS_WB)
-/*
- * R2000 or R3000
- */
-extern void (*__wbflush) (void);
+#ifdef CONFIG_CPU_HAS_WB
 
-#define wbflush() __wbflush()
+extern void (*__wbflush)(void);
+extern void wbflush_setup(void);
 
-#else
-/*
- * we don't need no stinkin' wbflush
- */
+#define wbflush()			\
+	do {				\
+		__sync();		\
+		__wbflush();		\
+	} while (0)
 
-#define wbflush()  do { } while(0)
+#else /* !CONFIG_CPU_HAS_WB */
 
-#endif
+#define wbflush_setup() do { } while (0)
 
-extern void wbflush_setup(void);
+#define wbflush() fast_iob()
+
+#endif /* !CONFIG_CPU_HAS_WB */
 
 #endif /* __ASM_MIPS_WBFLUSH_H */
diff -up --recursive --new-file linux-mips-2.4.18-20020530.macro/include/asm-mips64/system.h linux-mips-2.4.18-20020530/include/asm-mips64/system.h
--- linux-mips-2.4.18-20020530.macro/include/asm-mips64/system.h	2002-05-28 10:13:22.000000000 +0000
+++ linux-mips-2.4.18-20020530/include/asm-mips64/system.h	2002-06-02 15:55:32.000000000 +0000
@@ -12,9 +12,12 @@
 
 #include <linux/config.h>
 #include <asm/sgidefs.h>
-#include <asm/ptrace.h>
+
 #include <linux/kernel.h>
 
+#include <asm/addrspace.h>
+#include <asm/ptrace.h>
+
 __asm__ (
 	".macro\t__sti\n\t"
 	".set\tpush\n\t"
@@ -161,20 +164,37 @@ extern void __global_restore_flags(unsig
 #define local_irq_disable()	__cli()
 #define local_irq_enable()	__sti()
 
-/*
- * These are probably defined overly paranoid ...
- */
-#define mb()						\
-__asm__ __volatile__(					\
-	"# prevent instructions being moved around\n\t"	\
-	".set\tnoreorder\n\t"				\
-	"sync\n\t"					\
-	".set\treorder"					\
-	: /* no output */				\
-	: /* no input */				\
-	: "memory")
-#define rmb() mb()
-#define wmb() mb()
+#define __sync()				\
+	__asm__ __volatile__(			\
+		".set	push\n\t"		\
+		".set	noreorder\n\t"		\
+		"sync\n\t"			\
+		".set	pop"			\
+		: /* no output */		\
+		: /* no input */		\
+		: "memory")
+
+#define fast_wmb()	__sync()
+#define fast_rmb()	__sync()
+#define fast_mb()	__sync()
+#define fast_iob()				\
+	do {					\
+		__sync();			\
+		__asm__ __volatile__(		\
+			".set	push\n\t"	\
+			".set	noreorder\n\t"	\
+			"lw	$0,%0\n\t"	\
+			"nop\n\t"		\
+			".set	pop"		\
+			: /* no output */	\
+			: "m" (*(int *)KSEG1)	\
+			: "memory");		\
+	} while (0)
+
+#define wmb()		fast_wmb()
+#define rmb()		fast_rmb()
+#define mb()		fast_mb()
+#define iob()		fast_iob()
 
 #ifdef CONFIG_SMP
 #define smp_mb()	mb()
diff -up --recursive --new-file linux-mips-2.4.18-20020530.macro/include/asm-mips64/wbflush.h linux-mips-2.4.18-20020530/include/asm-mips64/wbflush.h
--- linux-mips-2.4.18-20020530.macro/include/asm-mips64/wbflush.h	1970-01-01 00:00:00.000000000 +0000
+++ linux-mips-2.4.18-20020530/include/asm-mips64/wbflush.h	2002-05-31 11:43:50.000000000 +0000
@@ -0,0 +1,18 @@
+/*
+ * Header file for using the wbflush routine
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ * Copyright (C) 2002 Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS64_WBFLUSH_H
+#define __ASM_MIPS64_WBFLUSH_H
+
+#define wbflush_setup() do { } while (0)
+
+#define wbflush() fast_iob()
+
+#endif /* __ASM_MIPS64_WBFLUSH_H */


From owner-linux-mips@oss.sgi.com Mon Jun  3 10:21:51 2002
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Date: Mon, 3 Jun 2002 19:23:55 +0200 (MET DST)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Justin Carlson <justinca@cs.cmu.edu>
cc: linux-mips@oss.sgi.com, ralf@oss.sgi.com
Subject: Re: __flush_cache_all() miscellany
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On 29 May 2002, Justin Carlson wrote:

> This is true;  I hadn't thought about the cases of userland touching
> hardware directly.  Of course, I think these cases should be hunted down
> and eliminated (go framebuffer device!), but alas, if that ever really
> happens, it's not going to be soon.

 Userland drivers are justified in many cases, so they'd better not go
away.  Besides, not all display adapters are framebuffers -- do you want
an X server in the kernel???

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Mon Jun  3 11:06:12 2002
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Date: Mon, 3 Jun 2002 01:55:36 -0700
From: Ralf Baechle <ralf@oss.sgi.com>
To: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Cc: Jun Sun <jsun@mvista.com>, Alexandr Andreev <andreev@niisi.msk.ru>,
   linux-mips@oss.sgi.com
Subject: Re: 3 questions about linux-2.4.18 and R3000
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On Fri, May 31, 2002 at 01:43:19PM +0400, Gleb O. Raiko wrote:

> > >> We have been using gcc 2.9.5 and binutils 2.10.x for R3000 CPUs for
> > >> quite a  while with no problems.  It seems newer gcc and binutiles are
> > >> fine too.

Some gcc 3.0 versions definately misscompiles the kernel; anyway 3.0 enjoys
a bad reputation for bugginess and being slow at generating slow code
beyond just the MIPS port, so why both with 3.0.  2.95.4 seems quite
reliable.

> > > I understand, but is there any __official__ recommended versions of these
> > > utils? http://oss.sgi.com/mips/mips-howto.html is out-of-date :(

Send patches.

> > 
> > Who are the "officiers" to decide on __official__ versions? :-)  If you are
> > really uncomfortable with non-official stuff, you might want to consider
> > paying some vendor and I am sure you will be given an "official" version.
> 
> "Official" means "if I report a bug w/o a patch in this list, I don't
> get a message which requests to change the tools". 

> I think, Ralf is the "officier" who decides what the right toolchain is.
> Now, last toolchain Ralf announced was 

Nah, I don't consider myself an officer :-)

> Date:            Fri, 1 Dec 2000 03:06:19 +0100

[embarrasingly old email deleted ...]

The issues with newer toolchains have been discussed at various times on
the list; at this time I don't have a tested toolchain that is usable for
all configurations of the kernel.  Also note that my recommendation of
binutils 2.9.5 is only for the kernel.

Anyway, binutils 2.12 is looking promising so far ...

  Ralf

From owner-linux-mips@oss.sgi.com Mon Jun  3 11:28:05 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Ralf Baechle <ralf@oss.sgi.com>
cc: "Gleb O. Raiko" <raiko@niisi.msk.ru>, Jun Sun <jsun@mvista.com>,
   Alexandr Andreev <andreev@niisi.msk.ru>, linux-mips@oss.sgi.com
Subject: Re: 3 questions about linux-2.4.18 and R3000
In-Reply-To: <20020603015536.B2832@dea.linux-mips.net>
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On Mon, 3 Jun 2002, Ralf Baechle wrote:

> Some gcc 3.0 versions definately misscompiles the kernel; anyway 3.0 enjoys
> a bad reputation for bugginess and being slow at generating slow code
> beyond just the MIPS port, so why both with 3.0.  2.95.4 seems quite
> reliable.

 As gcc 3.1 is out, it may be worth checking.  I actually plan to do that
in not so distant future.

> The issues with newer toolchains have been discussed at various times on
> the list; at this time I don't have a tested toolchain that is usable for
> all configurations of the kernel.  Also note that my recommendation of
> binutils 2.9.5 is only for the kernel.
> 
> Anyway, binutils 2.12 is looking promising so far ...

 Well, 2.12.1 seem rock solid for me.  The package I made available at my
site only contains two patches that affect code (the rest is autoconf and
similar stuff) and then only MIPS64.  They can be safely discarded for
pure MIPS work.

 For MIPS64 they definitely do not work, OTOH, including the N32 ABI.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Mon Jun  3 15:39:40 2002
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From: Ralf Baechle <ralf@oss.sgi.com>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Cc: "Gleb O. Raiko" <raiko@niisi.msk.ru>, Jun Sun <jsun@mvista.com>,
   Alexandr Andreev <andreev@niisi.msk.ru>, linux-mips@oss.sgi.com
Subject: Re: 3 questions about linux-2.4.18 and R3000
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On Mon, Jun 03, 2002 at 08:30:09PM +0200, Maciej W. Rozycki wrote:

>  Well, 2.12.1 seem rock solid for me.  The package I made available at my
> site only contains two patches that affect code (the rest is autoconf and
> similar stuff) and then only MIPS64.  They can be safely discarded for
> pure MIPS work.
> 
>  For MIPS64 they definitely do not work, OTOH, including the N32 ABI.

Are they good enough to build 64-bit kernels?

  Ralf

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Date: Tue, 4 Jun 2002 01:01:07 +0200
To: Ralf Baechle <ralf@oss.sgi.com>
Cc: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
   "Gleb O. Raiko" <raiko@niisi.msk.ru>, Jun Sun <jsun@mvista.com>,
   Alexandr Andreev <andreev@niisi.msk.ru>, linux-mips@oss.sgi.com
Subject: Re: 3 questions about linux-2.4.18 and R3000
Message-ID: <20020603230107.GH23411@rembrandt.csv.ica.uni-stuttgart.de>
References: <20020603015536.B2832@dea.linux-mips.net> <Pine.GSO.3.96.1020603202021.14451K-100000@delta.ds2.pg.gda.pl> <20020603154011.A11393@dea.linux-mips.net>
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Ralf Baechle wrote:
> On Mon, Jun 03, 2002 at 08:30:09PM +0200, Maciej W. Rozycki wrote:
> 
> >  Well, 2.12.1 seem rock solid for me.  The package I made available at my
> > site only contains two patches that affect code (the rest is autoconf and
> > similar stuff) and then only MIPS64.  They can be safely discarded for
> > pure MIPS work.
> > 
> >  For MIPS64 they definitely do not work, OTOH, including the N32 ABI.
> 
> Are they good enough to build 64-bit kernels?

One simple patch [1] is missing from the release. R_MIPS_HIGHEST relocs
are zeroed out in a few cases where the assembler resolves them itself.
The rest works for me quite nice.


Thiemo


[1] http://sources.redhat.com/ml/binutils/2002-05/msg00188.html

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From: Ralf Baechle <ralf@oss.sgi.com>
To: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
Cc: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
   "Gleb O. Raiko" <raiko@niisi.msk.ru>, Jun Sun <jsun@mvista.com>,
   Alexandr Andreev <andreev@niisi.msk.ru>, linux-mips@oss.sgi.com
Subject: Re: 3 questions about linux-2.4.18 and R3000
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On Tue, Jun 04, 2002 at 01:01:07AM +0200, Thiemo Seufer wrote:

> > >  For MIPS64 they definitely do not work, OTOH, including the N32 ABI.
> > 
> > Are they good enough to build 64-bit kernels?
> 
> One simple patch [1] is missing from the release. R_MIPS_HIGHEST relocs
> are zeroed out in a few cases where the assembler resolves them itself.
> The rest works for me quite nice.

Wonderful.  Due to the hackish way we're using to build 64-bit kernels
for the currently supported targets we don't run into this problems,
there are no R_MIPS_HIGHEST relocs ever.

  Ralf

From owner-linux-mips@oss.sgi.com Mon Jun  3 16:09:42 2002
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Date: Tue, 4 Jun 2002 01:11:18 +0200
To: Ralf Baechle <ralf@oss.sgi.com>
Cc: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>,
   "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
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Subject: Re: 3 questions about linux-2.4.18 and R3000
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Ralf Baechle wrote:
> On Tue, Jun 04, 2002 at 01:01:07AM +0200, Thiemo Seufer wrote:
> 
> > > >  For MIPS64 they definitely do not work, OTOH, including the N32 ABI.
> > > 
> > > Are they good enough to build 64-bit kernels?
> > 
> > One simple patch [1] is missing from the release. R_MIPS_HIGHEST relocs
> > are zeroed out in a few cases where the assembler resolves them itself.
> > The rest works for me quite nice.
> 
> Wonderful.  Due to the hackish way we're using to build 64-bit kernels
> for the currently supported targets we don't run into this problems,
> there are no R_MIPS_HIGHEST relocs ever.

Well, for my I2 Impact I do. :-) I hope to get it running again with
the current kernel (plus my patches) in the next days.


Thiemo

From owner-linux-mips@oss.sgi.com Mon Jun  3 16:14:14 2002
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From: Ralf Baechle <ralf@oss.sgi.com>
To: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
Cc: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
   "Gleb O. Raiko" <raiko@niisi.msk.ru>, Jun Sun <jsun@mvista.com>,
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Subject: Re: 3 questions about linux-2.4.18 and R3000
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On Tue, Jun 04, 2002 at 01:11:18AM +0200, Thiemo Seufer wrote:

> > Wonderful.  Due to the hackish way we're using to build 64-bit kernels
> > for the currently supported targets we don't run into this problems,
> > there are no R_MIPS_HIGHEST relocs ever.
> 
> Well, for my I2 Impact I do. :-) I hope to get it running again with
> the current kernel (plus my patches) in the next days.

Interesting.  So you don't place the kernel into any of the 32-bit
compatibility address spaces on that machine?

  Ralf

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Ralf Baechle wrote:
> On Tue, Jun 04, 2002 at 01:11:18AM +0200, Thiemo Seufer wrote:
> 
> > > Wonderful.  Due to the hackish way we're using to build 64-bit kernels
> > > for the currently supported targets we don't run into this problems,
> > > there are no R_MIPS_HIGHEST relocs ever.
> > 
> > Well, for my I2 Impact I do. :-) I hope to get it running again with
> > the current kernel (plus my patches) in the next days.
> 
> Interesting.  So you don't place the kernel into any of the 32-bit
> compatibility address spaces on that machine?

Load address is 0xa800000020002000 (and my diff against CVS > 300k). :-)
I'm busy because of Linuxtag now, I think I have time to provide some
parts of this in about two weeks.


Thiemo

From owner-linux-mips@oss.sgi.com Mon Jun  3 18:09:07 2002
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Date: Mon, 03 Jun 2002 21:09:16 -0400
From: Dan Malek <dan@embeddededge.com>
Organization: Embedded Edge, LLC.
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To: James Simmons <jsimmons@transvirtual.com>
CC: "Kevin D. Kissell" <kevink@mips.com>, Jun Sun <jsun@mvista.com>,
   Geert
 Uytterhoeven <geert@linux-m68k.org>,
   "Steven J. Hill"
 <sjhill@realitydiluted.com>,
   Linux/MIPS Development
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Subject: Re: PCI Graphics/Video Card for Malta Board?
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James Simmons wrote:

>>>Dan Malek also wrote a driver for MQ200.

> I have docs on this chipset. I forgot where I got them. I plan to work on
> a driver for that chipset since I have a board with it on it.

I wouldn't spend much time on it since the part is obsolete.  You and
I probably have the only boards with that part :-)  I thought the driver
was public, but if you can't find it I'll send you what I have.


	-- Dan




From owner-linux-mips@oss.sgi.com Mon Jun  3 20:14:12 2002
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At Mon, 03 Jun 2002 21:49:57 +0900 (JST),
Atsushi Nemoto wrote:
---

> Did you check the contents of 'shm_perm'?  The type of shm_perm is
> 'struct ipc64_perm' in kernel and 'struct ipc_perm' in libc.  I
> suppose these definitions are differ.

Oops, I lost that member before 'shm_segs' in.
Yes, you're right.
So I agree that it should be updated glibc to 2.2.4 and then try to do.

Thanks for your help.
Regards.
---
(TAKESHI - MontaVista Software)

From owner-linux-mips@oss.sgi.com Tue Jun  4 04:31:13 2002
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Ralf Baechle wrote:
> > > > I understand, but is there any __official__ recommended versions of these
> > > > utils? http://oss.sgi.com/mips/mips-howto.html is out-of-date :(
> 
> Send patches.

Does anybody have ideas what the patch shall contain? In the other
words, what versions of binutils and gcc will be considered stable.


> Nah, I don't consider myself an officer :-)

Sure. :-)

Regards,
Gleb.

From owner-linux-mips@oss.sgi.com Tue Jun  4 04:41:12 2002
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Maciej,

In previous version of your patch there was the change in mm/c-r3k.c:

static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long
size)
{
-       wbflush();
+       iob();
        r3k_flush_dcache_range(start, start + size);
}

Why did you drop it? It's definetely required.

While you patch operates in unusual terms from hw point of view, it does
right thins by stating that external wbs do differ from internal wb.

Regards,
Gleb.

Ah. The patch shall be applied, certainly.

From owner-linux-mips@oss.sgi.com Tue Jun  4 07:31:57 2002
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To: Ralf Baechle <ralf@oss.sgi.com>
cc: "Gleb O. Raiko" <raiko@niisi.msk.ru>, Jun Sun <jsun@mvista.com>,
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Subject: Re: 3 questions about linux-2.4.18 and R3000
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On Mon, 3 Jun 2002, Ralf Baechle wrote:

> >  For MIPS64 they definitely do not work, OTOH, including the N32 ABI.
> 
> Are they good enough to build 64-bit kernels?

 Not yet.  For N32 gas complains about 64-bit immediates and fails.  For
64 there are a few problems I'm currently resolving, but the kernel links.
As N32 is low priority for me, I'll get 64 fixed first, at least to the
point non-PIC static executables such as Linux work.  PIC and dynamic
linking are next on my to-do list. 

 I'm working on 2.12.90, though, as the MIPS/ELF backend was positively
but extensively restructured, so the ultimate target is 2.13.  For plain
MIPS 2.12.90 seem OK. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Tue Jun  4 07:34:59 2002
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To: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
cc: Ralf Baechle <ralf@oss.sgi.com>, "Gleb O. Raiko" <raiko@niisi.msk.ru>,
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Subject: Re: 3 questions about linux-2.4.18 and R3000
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On Tue, 4 Jun 2002, Thiemo Seufer wrote:

> One simple patch [1] is missing from the release. R_MIPS_HIGHEST relocs
> are zeroed out in a few cases where the assembler resolves them itself.
> The rest works for me quite nice.

 How about R_MIPS_26 relocs?  I discovered they are broken for the 64 ABI
(likely a RELA problem) and I am currently working on a fix.  As a result
of the bug a kernel executable is useless. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Tue Jun  4 07:36:53 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Ralf Baechle <ralf@oss.sgi.com>
cc: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>,
   "Gleb O. Raiko" <raiko@niisi.msk.ru>, Jun Sun <jsun@mvista.com>,
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Subject: Re: 3 questions about linux-2.4.18 and R3000
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On Mon, 3 Jun 2002, Ralf Baechle wrote:

> Wonderful.  Due to the hackish way we're using to build 64-bit kernels
> for the currently supported targets we don't run into this problems,
> there are no R_MIPS_HIGHEST relocs ever.

 I've already cleaned up the crap in my tree and I'll make the changes
available as soon as I have a version of binutils that actually works. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Tue Jun  4 07:50:48 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: "Gleb O. Raiko" <raiko@niisi.msk.ru>
cc: Ralf Baechle <ralf@uni-koblenz.de>, linux-mips@fnet.fr,
   linux-mips@oss.sgi.com
Subject: Re: [patch] linux: mb() and friends again
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On Tue, 4 Jun 2002, Gleb O. Raiko wrote:

> In previous version of your patch there was the change in mm/c-r3k.c:
> 
> static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long
> size)
> {
> -       wbflush();
> +       iob();
>         r3k_flush_dcache_range(start, start + size);
> }
> 
> Why did you drop it? It's definetely required.

 Nope, it wasn't dropped.  It's included in a different patch, namely
"patch-mips-2.4.18-20020412-wbflush-5".  The patch depends on the
"patch-mips-2.4.18-20020530-mb-wb-8" one, so I am not going to resubmit
the former one for discussion here until (unless) we decide on the latter
one.

> While you patch operates in unusual terms from hw point of view, it does
> right thins by stating that external wbs do differ from internal wb.

 What do you mean by "unusual terms"?  The names of the macros?  Well,
they are based on what's used for other platforms and if treated as
abstract names (as they should be) they actually reflect reality. 

  Maciej

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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"Maciej W. Rozycki" wrote:
> > Why did you drop it? It's definetely required.
> 
>  Nope, it wasn't dropped.  It's included in a different patch, namely
> "patch-mips-2.4.18-20020412-wbflush-5".  The patch depends on the
> "patch-mips-2.4.18-20020530-mb-wb-8" one, so I am not going to resubmit
> the former one for discussion here until (unless) we decide on the latter
> one.

Don't forget the latter one. :-)

> 
> > While you patch operates in unusual terms from hw point of view, it does
> > right thins by stating that external wbs do differ from internal wb.
> 
>  What do you mean by "unusual terms"?  The names of the macros?  Well,
> they are based on what's used for other platforms and if treated as
> abstract names (as they should be) they actually reflect reality.
> 

Basically, the patch logically allows combination of a CPU with internal
write-buffer and an external wb chip. It's impossible if hw designers
don't smoke hard. :-)

In fact, CONFIG_CPU_HAS_WB means !CONFIG_CPU_HAS_WB, i.e. CPU don't have
built-in write-buffer logic and there is an external write-buffer chip
somewhere in the box.
("Somewhere" means a place on the path from the local bus to a memory
controller.)

Then, __fast_iob just flushes internal wb while wbflush flushes an
external wb.

That's why I call it "unusual terms from hw POV". 

But, don't reimplement the patch, please. It's OK. Just from software
point of view.

Regards,
Gleb.

From owner-linux-mips@oss.sgi.com Tue Jun  4 10:42:07 2002
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To: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
cc: Ralf Baechle <ralf@oss.sgi.com>, "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
   "Gleb O. Raiko" <raiko@niisi.msk.ru>, Jun Sun <jsun@mvista.com>,
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Subject: Re: 3 questions about linux-2.4.18 and R3000
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Do you have gfx working on i2 impact?  Is it also an R10k system, or are
you useing an r4k system?
	Thanks
		Nick

On Tue, 4 Jun 2002, Thiemo Seufer wrote:

> Ralf Baechle wrote:
> > On Tue, Jun 04, 2002 at 01:11:18AM +0200, Thiemo Seufer wrote:
> > 
> > > > Wonderful.  Due to the hackish way we're using to build 64-bit kernels
> > > > for the currently supported targets we don't run into this problems,
> > > > there are no R_MIPS_HIGHEST relocs ever.
> > > 
> > > Well, for my I2 Impact I do. :-) I hope to get it running again with
> > > the current kernel (plus my patches) in the next days.
> > 
> > Interesting.  So you don't place the kernel into any of the 32-bit
> > compatibility address spaces on that machine?
> 
> Load address is 0xa800000020002000 (and my diff against CVS > 300k). :-)
> I'm busy because of Linuxtag now, I think I have time to provide some
> parts of this in about two weeks.
> 
> 
> Thiemo
> 


From owner-linux-mips@oss.sgi.com Tue Jun  4 11:05:59 2002
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Date: Tue, 04 Jun 2002 22:08:17 +0400
From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Organization: NIISI RAN
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There is bug in __copy_user (arch/mips*/lib/memcpy.S). Tested for 2.4.18
kernels, but versions 2.2, 2.4, and  2.5 for both mips and mips64 seems
to have similar bug.

For kernel 2.4.18 and mips
__copy_user returns wrong value if len = 4...7 and dst isn't accessible.

Other versions behave almost the same, just borders differ.

For example,
read(0,NULL,len), len=4...7 
getsockopt/ioctl(fd, *GET*, NULL, sizeof(int))

returns success. Fortunately, they don't write to at address 0.

The following patch seems to be OK for 2.4.18:

less_than_4units:
        /*
         * rem = len % NBYTES
         */
        beq     rem, len, copy_bytes
         nop
1:
EXC(    LOAD     t0, 0(src),            l_exc)
        ADD     src, src, NBYTES
        SUB     len, len, NBYTES
-EXC(    STORE   t0, 0(dst),             s_exc)
+EXC(    STORE   t0, 0(dst),             s_exc_p1u)
        bne     rem, len, 1b
         ADD    dst, dst, NBYTES

Any comments?

Regards,
Gleb.

From owner-linux-mips@oss.sgi.com Tue Jun  4 11:53:24 2002
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	Tue, 4 Jun 2002 20:55:20 +0200 (MET DST)
Date: Tue, 4 Jun 2002 20:55:20 +0200 (MET DST)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: "Gleb O. Raiko" <raiko@niisi.msk.ru>
cc: Ralf Baechle <ralf@uni-koblenz.de>, linux-mips@fnet.fr,
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Subject: Re: [patch] linux: mb() and friends again
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On Tue, 4 Jun 2002, Gleb O. Raiko wrote:

> Basically, the patch logically allows combination of a CPU with internal
> write-buffer and an external wb chip. It's impossible if hw designers
> don't smoke hard. :-)

 Well, I believe it might be useful -- if a CPU uses a higher clock for
its pipeline and a lower one for its external bus, it might be useful to
buffer a few words internally to avoid stalls at two consecutive writes.
Then you may have an additional buffer externally to lower the number of
stalls on memory or I/O (generally the rest of a system) accesses.
Essentially a buffer every time you cross a frequency domains' border,
leaving the faster one.  You need at least a single-word buffer at each
such border anyway if you don't want to stall the whole system for any
cycle accessing slower domains. 

 Consider it a complement of a hierarchical cache organization -- I've
seen (and actually used) systems with up to three levels of caches. 

> In fact, CONFIG_CPU_HAS_WB means !CONFIG_CPU_HAS_WB, i.e. CPU don't have
> built-in write-buffer logic and there is an external write-buffer chip
> somewhere in the box.
> ("Somewhere" means a place on the path from the local bus to a memory
> controller.)

 That's a bit awkward possibly, but "has" has a wide meaning and does not
necessarily state "contains".  It might mean "owns" as well.  For R[23]k
CPUs the option originally corresponded to external R2020 and R3220 chips
(just like floating point units may be external but still be considered a
part of a CPU) that were treated as a part of coprocessor 0 (with "bc0f"
or "bc0t" instructions testing their state). 

 Besides, who says discrete CPUs are forbidden? ;-)

> Then, __fast_iob just flushes internal wb while wbflush flushes an
> external wb.

 Well, that's used by __wbflush internally if it knows there is no
external buffer that needs explicit handling (for the DECstation, at least
-- other systems might make use of it as well).  That's unused in this
patch but is needed in the other one -- well, I had to split these patches
logically somehow and this one only contains system-independent code.

> That's why I call it "unusual terms from hw POV". 

 Hopefully, I clarified the terms a bit.

  Maciej

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Tue Jun  4 13:03:43 2002
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Date: Tue, 4 Jun 2002 13:05:27 -0700 (PDT)
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Hi!

   This patch includes the latest in the fbdev BK repository. I have
modified several fbdev drivers (maxinefb, tx3912fb, pmag drivers) to the
new api. Please test these changes out before I submit them to linus.
Thank you. It is against the latest BK tree and 2.5.20.

diff:

   http://www.transvirtual.com/~jsimmons/fbdev.diff.gz

BK:

   http://fbdev.bkbits.net:8080/fbdev-2.5

   . ---
   |o_o |
   |:_/ |   Give Micro$oft the Bird!!!!
  //   \ \  Use Linux!!!!
 (|     | )
 /'\_   _/`\
 \___)=(___/




From owner-linux-mips@oss.sgi.com Tue Jun  4 22:23:02 2002
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From: Andre.Messerschmidt@infineon.com
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Subject: kmalloc question
Date: Wed, 5 Jun 2002 07:25:02 +0200 
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Hi.

I always thought that it is save to use kmalloc in an interrupt handler as
long as you use GFP_ATOMIC. 
Now someone told me that it is not allowed to use these functions in any way
in an interrupt.

Can please someone clarify me here? 

regards
--
Andre Messerschmidt

Application Engineer
Infineon Technologies AG


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--MwF7gxnaJe
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Joe Buck (Joe.Buck@synopsys.com) writes:

> Dominic wrote:
> > > We do publish our sources on our web server.  Not only are they
> > > GPL but we have a copyright assignment to the FSF in place
> > > (which I know was sent to Jim Wilson of Cygnus, albeit in
> > > 1993...)
> 
> Eric Christopher wrote:
> > It's great that your changes do get out in one form or
> > another. I'm personally uncertain as to the nature of copyright
> > and how it would affect if I looked at your code and put it into
> > the mainline sources - so I haven't :)
> 
> Whose name and what company name would be on the copyright assignment?
> We can check with the FSF list to see if it's on file.  Meanwhile it
> should not go in.

I signed the assignment/waiver.  The companies involved are
Algorithmics Ltd and DFS3 Ltd.  It was faxed to Jim Wilson (then at
Cygnus) in October 1993 in the form recommended at that time.  Here's
a PDF.  Note the 'company stationery' has changed since 1993...


--MwF7gxnaJe
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--MwF7gxnaJe
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Content-Description: message body text
Content-Transfer-Encoding: 7bit


Let me know if you need a contemporary form.

--
Dominic Sweetman
Algorithmics Ltd
The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND
phone +44 1223 706200/fax +44 1223 706250/direct +44 1223 706205
http://www.algor.co.uk

--MwF7gxnaJe--


From owner-linux-mips@oss.sgi.com Wed Jun  5 08:38:15 2002
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From: Dominic Sweetman <dom@algor.co.uk>
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Message-ID: <15614.12481.424601.806779@gladsmuir.algor.co.uk>
Date: Wed, 5 Jun 2002 16:39:45 +0100
To: Eric Christopher <echristo@redhat.com>
Cc: Dominic Sweetman <dom@algor.co.uk>,
   Johannes Stezenbach <js@convergence.de>, gcc@gcc.gnu.org,
   linux-mips@oss.sgi.com, sde@algor.co.uk
Subject: Re: [Fwd: Current state of MIPS16 support?]
In-Reply-To: <1022870431.3668.19.camel@ghostwheel.cygnus.com>
References: <3CBFEAA9.9070707@algor.co.uk>
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Eric,

> The backend has changed a bit in the time, however, it hasn't
> changed so much that the patches would be that difficult for you to
> bring forward.
>
> I encourage you to reconsider contributing them. 

I fear it's "when time permits" at the moment.  The number of changes
is sufficiently large that it will take concentrated effort for 2-4
weeks, and this is very difficult to find.

> > We're working (with funding from MIPS Technologies) on building a
> > toolchain which:
> > 
> > o Can build Linux kernel, libraries and applications alike;
> > 
> > o Is substantially more efficient than other GCC versions when
> >   producing MIPS application ("MIPS/ABI", PIC) code;
> > 
> > o Will produce ugly-but-correct PIC code for MIPS16 functions, so
> >   MIPS16 can be tested in a standard Linux environment;
> > 
> > o Operates to a known and documented ABI (even the forgotten details,
> >   like gprof...)
> > 
> > (The modesty of those ambitions should be measured against the reality
> > of today's Linux/MIPS...)
> 
> I'm not certain what you are actually fixing here as I've not seen any
> descriptions of problems here...

Hmm.  Linux/MIPS suffers from widespread and diffuse toolchain
problems: I thought that much was pretty clear to all involved.  I
agree it seems a pity that the scheme of work laid out above should be
necessary...

> I'd love to fix any problems that you've had reported in the
> mainline sources so that everyone can get the benefit of the work
> you are doing.

Rather than snow you with a hundred compiler patches, I wonder whether
it might be better to share our regression test changes?  The tests
are likely to be a whole lot more portable than compiler patches.  If
you run them on a recent GCC 3.x compiler, you'll be in a much better
position to know to what extent our 2.96+ work is still relevant.

If this seems a good idea please mailto:sde@algor.co.uk and we'll ftp
the test sources to the place of your choice, or point you at them on
our web server.

> I'm putting in a lot of effort to cleaning up the MIPS port and am
> committed to the architecture. 

It sounds like you're in the role of maintainer of GCC for MIPS
targets.  You may not be free to answer this: but does that mean that
Red Hat have guaranteed you'll have the time to fulfill that
responsibility even during periods when Red Hat don't happen to win
relevant contracts from MIPS vendors?

If so that would be excellent...

> > It's a pity that the different priorities of various funders and
> > developers mean that there is no baseline toolkit for Linux/MIPS, so
> > that such resources as are available are frequently used to re-invent
> > the wheel.
> > 
> > Anyone got any ideas how to make it better?
>
> The problem as I see it is that no one wants/cares to contribute their
> changes back that they make, or at least file bug reports against the
> problems that they have.

During most of the last few years (as I understand it) it has been
difficult to establish a baseline to patch against, or find someone
who had the time to attend to bug reports.

As you'll know it's much harder to test the compiler as used for
'embedded' targets, because the diversity of OS' used makes it
hard to re-use tests.  Something better should be possible now
Linux/MIPS is less flaky.

> Almost 90% of the bug reports I see are against IRIX.

That does suggest you're missing some pretty large chunks of the
community!

> People have to "re-invent the wheel" because the changes never make
> it back into the official sources - everyone has their own one offs.
> If we fix this then the work that all of the disparate groups are
> doing will at least go toward a common goal. 

We believe that a large number of man hours will be required to
identify and merge all major valuable features and then chase out
the bugs, before there can be a release which everyone has reason to
adopt.

We certainly can't afford to put in those hours unless we win
contracts; I suspect Red Hat can't, either.

-- 
Dominic Sweetman
Algorithmics Ltd
The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND
phone +44 1223 706200/fax +44 1223 706250/direct +44 1223 706205
http://www.algor.co.uk


From owner-linux-mips@oss.sgi.com Wed Jun  5 09:00:07 2002
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To: Dominic Sweetman <dom@algor.co.uk>
cc: Joe Buck <Joe.Buck@synopsys.com>, echristo@redhat.com (Eric Christopher),
   js@convergence.de (Johannes Stezenbach), gcc@gcc.gnu.org,
   linux-mips@oss.sgi.com, sde@algor.co.uk
Subject: Re: [Fwd: Current state of MIPS16 support?] 
Reply-To: law@redhat.com
From: law@redhat.com
In-reply-to: Your message of Wed, 05 Jun 2002 16:13:28 BST.
             <15614.10904.705392.925058@gladsmuir.algor.co.uk> 
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In message <15614.10904.705392.925058@gladsmuir.algor.co.uk>, Dominic Sweetman 
writes:
 > 
 > --MwF7gxnaJe
 > Content-Type: text/plain; charset=us-ascii
 > Content-Description: message body text
 > Content-Transfer-Encoding: 7bit
 > 
 > 
 > Joe Buck (Joe.Buck@synopsys.com) writes:
 > 
 > > Dominic wrote:
 > > > > We do publish our sources on our web server.  Not only are they
 > > > > GPL but we have a copyright assignment to the FSF in place
 > > > > (which I know was sent to Jim Wilson of Cygnus, albeit in
 > > > > 1993...)
 > > 
 > > Eric Christopher wrote:
 > > > It's great that your changes do get out in one form or
 > > > another. I'm personally uncertain as to the nature of copyright
 > > > and how it would affect if I looked at your code and put it into
 > > > the mainline sources - so I haven't :)
 > > 
 > > Whose name and what company name would be on the copyright assignment?
 > > We can check with the FSF list to see if it's on file.  Meanwhile it
 > > should not go in.
 > 
 > I signed the assignment/waiver.  The companies involved are
 > Algorithmics Ltd and DFS3 Ltd.  It was faxed to Jim Wilson (then at
 > Cygnus) in October 1993 in the form recommended at that time.  Here's
 > a PDF.  Note the 'company stationery' has changed since 1993...
What's important here is the assignment that is on file with the FSF.  That's
what needs to be checked.  

jeff


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Subject: Re: kmalloc question
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Andre.Messerschmidt@infineon.com
Cc: linux-mips@oss.sgi.com
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On Wed, 2002-06-05 at 06:25, Andre.Messerschmidt@infineon.com wrote:
> Hi.
> 
> I always thought that it is save to use kmalloc in an interrupt handler as
> long as you use GFP_ATOMIC. 
> Now someone told me that it is not allowed to use these functions in any way
> in an interrupt.
> 
> Can please someone clarify me here? 

GFP_ATOMIC is safe in an interrupt handler. You might get NULL back and
that it is your problem, but the kmalloc is safe


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Date: Wed, 5 Jun 2002 13:53:18 -0400
From: Daniel Jacobowitz <dan@debian.org>
To: Dominic Sweetman <dom@algor.co.uk>
Cc: Eric Christopher <echristo@redhat.com>,
   Johannes Stezenbach <js@convergence.de>, gcc@gcc.gnu.org,
   linux-mips@oss.sgi.com, sde@algor.co.uk
Subject: Re: [Fwd: Current state of MIPS16 support?]
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On Wed, Jun 05, 2002 at 04:39:45PM +0100, Dominic Sweetman wrote:
> > I'm not certain what you are actually fixing here as I've not seen any
> > descriptions of problems here...
> 
> Hmm.  Linux/MIPS suffers from widespread and diffuse toolchain
> problems: I thought that much was pretty clear to all involved.  I
> agree it seems a pity that the scheme of work laid out above should be
> necessary...

...

> > Almost 90% of the bug reports I see are against IRIX.
> 
> That does suggest you're missing some pretty large chunks of the
> community!

No, that's not what it suggests at all.  It suggests to me that the
dubious state of Linux/MIPS toolchains is due to one of two things:
  - A pre-existing acceptance of this rather than any real problems
  - A reluctance to file bug reports

We've been using GCC for MIPS for several years now and seen relatively
few significant problems, so I suspect the former.  There's definitely
some of the latter as well, since we've hit more roadblocks on MIPS
than on, say, x86 or PowerPC; it's not our worst problem architecture,
though.  And we've been able to fix them all relatively easily.

I'm sure GCC would benefit from access to your regression tests, though :)

-- 
Daniel Jacobowitz                           Carnegie Mellon University
MontaVista Software                         Debian GNU/Linux Developer

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Date: Wed, 5 Jun 2002 13:12:31 -0700
From: William Jhun <wjhun@ayrnetworks.com>
To: "linux-kernel@vger.kernel.org"@ayrnetworks.com
Cc: "linux-mips@oss.sgi.com"@ayrnetworks.com, davem@redhat.com
Subject: Deprecate pci_dma_sync_{single,sg}()?
Message-ID: <20020605131231.B10773@ayrnetworks.com>
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While introducing the pci_dma_prep_{single,sg}() interface, it occured
to me that there are some subtle problems with the old interface and its
implementation on non-cache-coherent systems. For example, a PCI driver
might do the following on a buffer:

pci_map_single(..., FROM_DEVICE)
<perform DMA into buffer>
pci_dma_sync_single(..., FROM_DEVICE)
<read out of buffer>
<put buffer back on queue and give bus address back to device -
 no explicit call to "return" the buffer to the device>
<perform DMA again>
pci_unmap_single(..., FROM_DEVICE)

This happens in certain network drivers (tulip, pcnet32...) when
determining whether the packet is small enough to make a copy (and leave
the buffer on the RX ring).

In the current linux-mips implementation, this has some subtle problems:
pci_unmap_{single,sg}() is essentially a no-op. Thus, in the above
example, a driver would break (stale cachelines from a previous
pci_dma_sync_*/read would not be invalidated). One might argue that a
cache invalidate should happen in the pci_unmap_single(). But then the
other case (where a driver does a pci_map, DMAs, does a pci_unmap, and
sends it up the stack) would require an additional cache
flush/invalidate that is not needed at all. In fact, when using
pci_dma_sync_{single,sg}() on a non-cache-coherent system, a cache
flush/invalidate happens needlessly as the buffer had already been
flushed in pci_map_{single,sg}(). These extra flushes do have
significant performance hits, even if not noticeable through typical
light use.

As such, it seems that it makes sense to do cache flushes only in
pci_map_{single,sg}() and pci_dma_prep_{single,sg}() (see Message-ID:
<20020526000933.A8719@ayrnetworks.com>, [PATCH] DMA-mapping.txt) and
mandate that pci_dma_prep_{single,sg}() be called when returning a
"touched" buffer to the device for another DMA (between pci_map_* and
pci_unmap_*). The cache flush in pci_dma_sync_{single,sg}() would be
removed.

The problem with this is that it will break some existing drivers that
don't yet call pci_dma_prep_*() (e.g., tulip). Would it be possible to
keep (but deprecate) pci_dma_sync_*() and make a similar call
"pci_dma_release_{single,sg}()" which does the same thing as
pci_dma_sync_*() while omitting the cache flushes? Thus, the above
example would become:

pci_map_single(..., FROM_DEVICE)                   [cache invalidate]
<perform DMA into buffer>
pci_dma_release_single(..., FROM_DEVICE)           [no cache invalidate,
						    but might perform PCI
						    controller-specific
						    operations to allow
						    the CPU to view
						    DMAed data]
<read out of buffer>                               
pci_dma_prep_single(..., FROM_DEVICE)              [cache invalidate]
<put buffer back on queue and give bus address back to device>
<perform DMA again>
pci_unmap_single(..., FROM_DEVICE)                 [no need for cache
						    invalidate]

This interface allows for:

1) A clean abstraction of what (the device or the driver) "owns" the
   buffer and can touch it. pci_map_* and pci_dma_prep_* "give" the
   buffer to the device, pci_unmap_* and pci_dma_release_* "take"
   the buffer from the device. Adds an entry point into
   platform-specific code for each of these transitions.

2) More optimal behavior in non-cache-coherent I/O situations; a buffer
   is never needlessly flushed/invalidated in the cache when the buffer
   is "owned" by the device.

3) Ability to re-use a buffer for PCI_DMA_TODEVICE operations without
   having to unmap/map between DMA transfers. The usage of the calls are
   the same, regardless of DMA direction.

4) The old interface (using pci_dma_sync_*()) will still remain for the
   time being, allowing for gradual migration to the new interface.

Changes to Documentation/DMA-mapping.txt in vger are attached.

Thanks,
William

---
Index: Documentation/DMA-mapping.txt
===================================================================
RCS file: /vger/linux/Documentation/DMA-mapping.txt,v
retrieving revision 1.17.2.2
diff -u -r1.17.2.2 DMA-mapping.txt
--- Documentation/DMA-mapping.txt	5 Mar 2002 12:40:36 -0000	1.17.2.2
+++ Documentation/DMA-mapping.txt	5 Jun 2002 20:07:43 -0000
@@ -239,9 +239,9 @@
 
              in order to get correct behavior on all platforms.
 
-- Streaming DMA mappings which are usually mapped for one DMA transfer,
-  unmapped right after it (unless you use pci_dma_sync below) and for which
-  hardware can optimize for sequential accesses.
+- Streaming DMA mappings which are usually mapped for one DMA
+  transfer, unmapped right after it (unless you use pci_dma_release
+  below) and for which hardware can optimize for sequential accesses.
 
   This of "streaming" as "asynchronous" or "outside the coherency
   domain".
@@ -508,21 +508,46 @@
 the data in between the DMA transfers, just map it with
 pci_map_{single,sg}, and after each DMA transfer call either:
 
-	pci_dma_sync_single(dev, dma_handle, size, direction);
+	pci_dma_release_single(dev, dma_handle, size, direction);
 
 or:
 
-	pci_dma_sync_sg(dev, sglist, nents, direction);
+	pci_dma_release_sg(dev, sglist, nents, direction);
 
 as appropriate.
 
+Once you have touched the region (after having called pci_dma_release_*()),
+and need to give it back to the device for another DMA transfer, call:
+
+	pci_dma_prep_single(dev, dma_handle, size, direction);
+
+or:
+
+	pci_dma_prep_sg(dev, sglist, nents, direction);
+
+This will prepare the buffer for another DMA transfer and synchronize any
+CPU writes to it with the device's view if direction is set to
+PCI_DMA_TODEVICE or PCI_DMA_BIDIRECTIONAL.
+
+Note: Prior to the introduction of pci_dma_prep_*, drivers accessing a
+DMAed region after a pci_dma_sync_* (now obsolete) implicitly returned
+"ownership" of the region to the device without having to expressly call a
+routine to do so.  In these cases, data is only read from the buffer, and
+the CPU "view" of the region is synchronized again on the next call to
+pci_dma_sync_*. For repeated DMA transfers to a device, pci_dma_prep_*() is
+used to synchronize any changes in the region (made by the driver) with the
+device. New drivers should use pci_dma_release_* in place of pci_dma_sync_*
+and use pci_dma_prep_* when returning the buffer back to the device,
+regardless of the DMA direction. Eventually, all calls to pci_dma_sync_*
+will be eliminated.
+
 After the last DMA transfer call one of the DMA unmap routines
 pci_unmap_{single,sg}. If you don't touch the data from the first pci_map_*
-call till pci_unmap_*, then you don't have to call the pci_dma_sync_*
-routines at all.
+call till pci_unmap_*, then you don't have to call the pci_dma_release_* or
+pci_dma_prep_* routines at all.
 
 Here is pseudo code which shows a situation in which you would need
-to use the pci_dma_sync_*() interfaces.
+to use the pci_dma_release_*() and pci_dma_prep_*() interfaces.
 
 	my_card_setup_receive_buffer(struct my_card *cp, char *buffer, int len)
 	{
@@ -552,7 +577,7 @@
 			 * the DMA transfer with the CPU first
 			 * so that we see updated contents.
 			 */
-			pci_dma_sync_single(cp->pdev, cp->rx_dma, cp->rx_len,
+			pci_dma_release_single(cp->pdev, cp->rx_dma, cp->rx_len,
 					    PCI_DMA_FROMDEVICE);
 
 			/* Now it is safe to examine the buffer. */
@@ -563,7 +588,11 @@
 				pass_to_upper_layers(cp->rx_buf);
 				make_and_setup_new_rx_buf(cp);
 			} else {
-				/* Just give the buffer back to the card. */
+				/* Prepare the buffer for another DMA transfer,
+				 * then give the buffer back to the card.
+				 */
+				pci_dma_prep_single(cp->pdev, cp->rx_dma,
+				                    cp->rx_len, PCI_DMA_FROMDEVICE);
 				give_rx_buf_to_card(cp);
 			}
 		}
@@ -671,12 +700,20 @@
 
 When the DMA transfer is complete, invoke:
 
-	void pci_dac_dma_sync_single(struct pci_dev *pdev,
+	void pci_dac_dma_release_single(struct pci_dev *pdev,
 				     dma64_addr_t dma_addr,
 				     size_t len, int direction);
 
 This must be done before the CPU looks at the buffer again.
-This interface behaves identically to pci_dma_sync_{single,sg}().
+
+After calling pci_dac_dma_release_{single,sg}, and before returning the
+buffer to the device for another DMA operation, invoke:
+
+	void pci_dac_dma_prep_single(struct pci_dev *pdev, dma64_addr_t
+	                             dma_addr, size_t len, int direction);
+
+These two interfaces behave identically to pci_dma_release_{single,sg}()
+and pci_dma_prep_{single,sg}(), respectively.
 
 If you need to get back to the PAGE/OFFSET tuple from a dma64_addr_t
 the following interfaces are provided:

From owner-linux-mips@oss.sgi.com Wed Jun  5 15:35:52 2002
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Date: Thu, 6 Jun 2002 00:37:36 +0200
To: nick@snowman.net
Cc: linux-mips@oss.sgi.com
Subject: Re: 3 questions about linux-2.4.18 and R3000
Message-ID: <20020605223736.GN23411@rembrandt.csv.ica.uni-stuttgart.de>
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nick@snowman.net wrote:
> Do you have gfx working on i2 impact?

Nothing more than the firmware will do.

> Is it also an R10k system, or are
> you useing an r4k system?

IT's r10k. AFAIH the r4k systems have still ARCS32 and should be
able to boot a 32 bit kernel.


Thiemo

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Date: Thu, 6 Jun 2002 00:38:59 +0200
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Cc: Ralf Baechle <ralf@oss.sgi.com>, "Gleb O. Raiko" <raiko@niisi.msk.ru>,
   Jun Sun <jsun@mvista.com>, Alexandr Andreev <andreev@niisi.msk.ru>,
   linux-mips@oss.sgi.com
Subject: Re: 3 questions about linux-2.4.18 and R3000
Message-ID: <20020605223859.GO23411@rembrandt.csv.ica.uni-stuttgart.de>
References: <20020603230107.GH23411@rembrandt.csv.ica.uni-stuttgart.de> <Pine.GSO.3.96.1020604163438.17556C-100000@delta.ds2.pg.gda.pl>
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Maciej W. Rozycki wrote:
> On Tue, 4 Jun 2002, Thiemo Seufer wrote:
> 
> > One simple patch [1] is missing from the release. R_MIPS_HIGHEST relocs
> > are zeroed out in a few cases where the assembler resolves them itself.
> > The rest works for me quite nice.
> 
>  How about R_MIPS_26 relocs?  I discovered they are broken for the 64 ABI
> (likely a RELA problem) and I am currently working on a fix.  As a result
> of the bug a kernel executable is useless.

I forgot about this one, sorry. I have a patch for it, I think it will
go in for 2.13.


Thiemo

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To: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>, nick@snowman.net
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Hash: SHA1

On Wednesday 05 June 2002 03:37 pm, Thiemo Seufer wrote:
> nick@snowman.net wrote:
> > Do you have gfx working on i2 impact?
>
> Nothing more than the firmware will do.
>
> > Is it also an R10k system, or are
> > you useing an r4k system?
>
> IT's r10k. AFAIH the r4k systems have still ARCS32 and should be
> able to boot a 32 bit kernel.
And how are you dealing with R10K speculative execution
in non-cache-coherent systems problem?

> Thiemo
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From owner-linux-mips@oss.sgi.com Wed Jun  5 23:29:40 2002
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Subject: Re: [Fwd: Current state of MIPS16 support?]
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In-Reply-To: dom@algor.co.uk's message of
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At Wed, 5 Jun 2002 15:40:14 +0000 (UTC), "Dominic Sweetman" wrote:
> I fear it's "when time permits" at the moment.  The number of changes
> is sufficiently large that it will take concentrated effort for 2-4
> weeks, and this is very difficult to find.

For what it's worth, if you expend the effort while you go, it saves
much time in the long run, both in terms of maintaining the changes,
and merging them.


> During most of the last few years (as I understand it) it has been
> difficult to establish a baseline to patch against, or find someone
> who had the time to attend to bug reports.

As someone who's been maintaining a MIPS toolchain (based on gcc,
binutils, etc.) for a couple of years, I dunno that that makes sense.

There seems to have been some confusion in the community about which
versions to use, etc.  But, for most purposes, i've found that the
latest releases have worked "pretty well" -- certainly well enough to
use for development with a small number of patches -- for linux mips
and other mips targets.  We've been using gcc 3.0.x now for a while;
last i looked the linux mips pages recommended against that, and I
really don't understand why...  Soon we'll be switching to 3.1.


> > Almost 90% of the bug reports I see are against IRIX.
> 
> That does suggest you're missing some pretty large chunks of the
> community!


> > People have to "re-invent the wheel" because the changes never make
> > it back into the official sources - everyone has their own one offs.
> > If we fix this then the work that all of the disparate groups are
> > doing will at least go toward a common goal. 
> 
> We believe that a large number of man hours will be required to
> identify and merge all major valuable features and then chase out
> the bugs, before there can be a release which everyone has reason to
> adopt.
> 
> We certainly can't afford to put in those hours unless we win
> contracts; I suspect Red Hat can't, either.

This puts you into an interesting position:

Presumably your customers desire both features of new GCC/binutils,
but also want support for your improvements.

The way it looks to me, by not getting your changes put back into the
public sources as you go, you've managed both to make a large chunk of
work for yourself if you want to catch up and to put yourself at a
competitive disadvantage in the eyes of customers who place high value
in current GCC features.


FWIW, it's not that hard to get changes back in if you try.  Over the
past couple of years, basically starting as an "outsider," i've
managed to get ... about a hundred fifty patches -- ranging from tiny
or trivial bug fixes to fairly huge changes -- pushed back into the
public sources, and have even managed to be appointed the mips gdb
'sim' maintainer...  The result is, many of the tool problems we found
have now been fixed, and since we put in test case entries where
possible should stay fixed, and now our source merges are much easier
and go much more quickly.



cgd


From owner-linux-mips@oss.sgi.com Thu Jun  6 00:08:47 2002
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From: Andre.Messerschmidt@infineon.com
To: alan@lxorguk.ukuu.org.uk
Cc: linux-mips@oss.sgi.com
Subject: AW: kmalloc question
Date: Thu, 6 Jun 2002 09:10:45 +0200 
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> GFP_ATOMIC is safe in an interrupt handler. You might get NULL back and
> that it is your problem, but the kmalloc is safe
> 
Thanks. 
NULL is something I can handle.

regards
Andre


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Subject: Re: [Fwd: Current state of MIPS16 support?] 
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Jeff,

>  > I signed the assignment/waiver.  The companies involved are
>  > Algorithmics Ltd and DFS3 Ltd.  It was faxed to Jim Wilson (then at
>  > Cygnus) in October 1993 in the form recommended at that time.  Here's
>  > a PDF.  Note the 'company stationery' has changed since 1993...
> 
> What's important here is the assignment that is on file with the FSF.  That's
> what needs to be checked.  

Are you in a position to do that?  If not, who is?

-- 
Dominic Sweetman, 
Algorithmics Ltd
phone: +44 1223 706200 / fax: +44 1223 706250 / direct: +44 1223 706205
http://www.algor.co.uk

From owner-linux-mips@oss.sgi.com Thu Jun  6 02:13:11 2002
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Subject: Re: [Fwd: Current state of MIPS16 support?]
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I wholeheatedly agree that it would be a really good thing if we were
all working around a common, recent, source tree...

I'm finding this discussion useful because it's identifying people who
are working in the area, and I'm wondering whether we can come
together in the short term on building a better regression test
suite...

> There seems to have been some confusion in the community about which
> versions to use, etc.  But, for most purposes, i've found that the
> latest releases have worked "pretty well" -- certainly well enough to
> use for development with a small number of patches...

Difference in perception here.

Algorithmics have been maintaining GNU C for about ten years for our
'embedded' customers, some of whom have very large and demanding code
bases.  

Up to and including the 2.96+ release we currently work with, no GCC
version we've taken on has been fit for use by our MIPS customers
without a large number of fixes, including significant changes to
nominally non-machine-dependent code.

If you experienced a big improvement in quality on moving to some more
recent version, I'd love to know and that's worth telling everyone.

But if you're saying "it's always been more or less all right" then we
are bound to suspect you're not looking hard enough...

> Presumably your customers desire both features of new GCC/binutils,
> but also want support for your improvements.

They want high reliability (which requires fairly lengthy
development schedules) and the latest version... I'm sure yours do
too, but the requirements compete somewhat.

> FWIW, it's not that hard to get changes back in if you try.

Thanks for the encouragement.

Dominic Sweetman, 
Algorithmics Ltd

From owner-linux-mips@oss.sgi.com Thu Jun  6 02:57:52 2002
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Date: Thu, 6 Jun 2002 05:59:18 -0400
From: Phil Edwards <phil@jaj.com>
To: Dominic Sweetman <dom@algor.co.uk>
Cc: law@redhat.com, Joe Buck <Joe.Buck@synopsys.com>,
   Eric Christopher <echristo@redhat.com>,
   Johannes Stezenbach <js@convergence.de>, gcc@gcc.gnu.org,
   linux-mips@oss.sgi.com, sde@algor.co.uk
Subject: Re: [Fwd: Current state of MIPS16 support?]
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> >  > I signed the assignment/waiver.  The companies involved are
> >  > Algorithmics Ltd and DFS3 Ltd.  It was faxed to Jim Wilson (then at
> >  > Cygnus) in October 1993 in the form recommended at that time.  Here's
> >  > a PDF.  Note the 'company stationery' has changed since 1993...
> > 
> > What's important here is the assignment that is on file with the FSF.  That's
> > what needs to be checked.  
> 
> Are you in a position to do that?  If not, who is?
> 
> -- 
> Dominic Sweetman, 
> Algorithmics Ltd

Here's what's on file:

    BINUTILS    Algorithmics Ltd.   1997-08-20
    Assigns changes.

    GCC Algorithmics Ltd.   1997-08-20
    Assigns changes.

    GDB Algorithmics Ltd.   1997-08-20
    Assigns changes.

There's also a disclaimer for changes to Emacs, if that matters here.  :-)


Phil

-- 
If ye love wealth greater than liberty, the tranquility of servitude greater
than the animating contest for freedom, go home and leave us in peace.  We seek
not your counsel, nor your arms.  Crouch down and lick the hand that feeds you;
and may posterity forget that ye were our countrymen.            - Samuel Adams

From owner-linux-mips@oss.sgi.com Thu Jun  6 08:04:17 2002
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Date: Thu, 6 Jun 2002 17:06:05 +0200 (MEST)
From: Kjeld Borch Egevang <kjelde@mips.com>
To: linux-mips mailing list <linux-mips@oss.sgi.com>
Subject: Float crash. Fix in exit_thread()
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I'm running on a system with no FPU. Now, I've got a program do_float 
which seems to work fine. But if I enter:

/bin/echo hello; ./do_float

it terminates with a bus error or FP error. The bug is in exit_thread(). 
Can anyone explain to me, what good the "cfc1 $0,$31" does?


Here is the patch:

RCS file: /cvs/linux/arch/mips/kernel/process.c,v
retrieving revision 1.36
diff -u -r1.36 process.c
--- process.c   2002/05/29 18:36:28     1.36
+++ process.c   2002/06/06 14:51:32
@@ -54,9 +54,11 @@
 void exit_thread(void)
 {
        /* Forget lazy fpu state */
-       if (last_task_used_math == current && mips_cpu.options & MIPS_CPU_FPU) {
-               __enable_fpu();
-               __asm__ __volatile__("cfc1\t$0,$31");
+       if (last_task_used_math == current) {
+               if (mips_cpu.options & MIPS_CPU_FPU) {
+                       __enable_fpu();
+                       __asm__ __volatile__("cfc1\t$0,$31");
+               }
                last_task_used_math = NULL;
        }
 }
@@ -64,9 +66,11 @@
 void flush_thread(void)
 {
        /* Forget lazy fpu state */
-       if (last_task_used_math == current && mips_cpu.options & MIPS_CPU_FPU) {
-               __enable_fpu();
-               __asm__ __volatile__("cfc1\t$0,$31");
+       if (last_task_used_math == current) {
+               if (mips_cpu.options & MIPS_CPU_FPU) {
+                       __enable_fpu();
+                       __asm__ __volatile__("cfc1\t$0,$31");
+               }
                last_task_used_math = NULL;
        }
 }



/Kjeld


-- 
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|\  /|||___)(___    MIPS Denmark       Direct: +45 44 86 55 85
| \/ |||    ____)   Lautrupvang 4 B    Switch: +45 44 86 55 55
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To: "Dominic Sweetman" <dom@algor.co.uk>
cc: "Eric Christopher" <echristo@redhat.com>,
   "Johannes Stezenbach" <js@convergence.de>, gcc@gcc.gnu.org,
   linux-mips@oss.sgi.com, sde@algor.co.uk
Subject: Re: [Fwd: Current state of MIPS16 support?]
References: <3CBFEAA9.9070707@algor.co.uk>
 <15566.28397.770794.272735@gladsmuir.algor.co.uk>
 <1022870431.3668.19.camel@ghostwheel.cygnus.com>
 <15614.12481.424601.806779@gladsmuir.algor.co.uk>
 <mailpost.1023291613.28112@news-sj1-1> <yov5n0u8c401.fsf@broadcom.com>
 <200206060914.KAA03263@mudchute.algor.co.uk>
From: cgd@broadcom.com
Date: 06 Jun 2002 08:13:14 -0700
In-Reply-To: "Dominic Sweetman"'s message of
 "Thu, 6 Jun 2002 10:14:33 +0100 (BST)"
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At Thu, 6 Jun 2002 10:14:33 +0100 (BST), Dominic Sweetman wrote:
> Difference in perception here.

Noted.


> Up to and including the 2.96+ release we currently work with, no GCC
> version we've taken on has been fit for use by our MIPS customers
> without a large number of fixes, including significant changes to
> nominally non-machine-dependent code.
>
> If you experienced a big improvement in quality on moving to some more
> recent version, I'd love to know and that's worth telling everyone.
> 
> But if you're saying "it's always been more or less all right" then we
> are bound to suspect you're not looking hard enough...

"I don't know."  I didn't really spend a _lot_ of time staring at the
gnu toolchain until about 2 or 3 years ago (mips tools, 2 or so years
8-).  Before that, i relied on tools that others had massaged ... and
invariably, yes, they did have at least a few "important" bug fixes
(often pulled in from later development versions of the tools).  I
think even going back 2 and change years, we had some problems with
the versions of gcc at that time, and, for some sets of compile flags
(for us, -membedded-pic) a _lot_ of problems with binutils.

As of gcc 3.0.4 and w/ binutils 2.12.1 (with patches to each, but
generally not bug-fixes .... though we undoubtedly still have a few),
at least for us, they seem to work well for linux and for some amount
of stand-alone embedded development work.

I wouldn't disagree, BTW, that the current tools for mips seem to have
some shortcomings.  I also wouldn't claim that we've comprehensively
tested the tools.  8-)


I think the goal of improving test suites to show additional bugs is a
very good one.  Personally, I've been trying to make sure regression
tests get added for bugs we find & fix, but there will always be more
bugs to find.



chris


From owner-linux-mips@oss.sgi.com Thu Jun  6 08:31:15 2002
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To: Phil Edwards <phil@jaj.com>
cc: Dominic Sweetman <dom@algor.co.uk>, Joe Buck <Joe.Buck@synopsys.com>,
   Eric Christopher <echristo@redhat.com>,
   Johannes Stezenbach <js@convergence.de>, gcc@gcc.gnu.org,
   linux-mips@oss.sgi.com, sde@algor.co.uk
Subject: Re: [Fwd: Current state of MIPS16 support?] 
Reply-To: law@redhat.com
From: law@redhat.com
In-reply-to: Your message of Thu, 06 Jun 2002 05:59:18 EDT.
             <20020606055918.A13788@disaster.basement.lan> 
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In message <20020606055918.A13788@disaster.basement.lan>, Phil Edwards writes:
 > > >  > I signed the assignment/waiver.  The companies involved are
 > > >  > Algorithmics Ltd and DFS3 Ltd.  It was faxed to Jim Wilson (then at
 > > >  > Cygnus) in October 1993 in the form recommended at that time.  Here's
 > > >  > a PDF.  Note the 'company stationery' has changed since 1993...
 > > > 
 > > > What's important here is the assignment that is on file with the FSF.  T
 > hat's
 > > > what needs to be checked.  
 > > 
 > > Are you in a position to do that?  If not, who is?
 > > 
 > > -- 
 > > Dominic Sweetman, 
 > > Algorithmics Ltd
 > 
 > Here's what's on file:
 > 
 >     BINUTILS    Algorithmics Ltd.   1997-08-20
 >     Assigns changes.
 > 
 >     GCC Algorithmics Ltd.   1997-08-20
 >     Assigns changes.
 > 
 >     GDB Algorithmics Ltd.   1997-08-20
 >     Assigns changes.
 > 
 > There's also a disclaimer for changes to Emacs, if that matters here.  :-)
Thanks.  This likely means that we're better off getting a new assignment --
this kind of language "Assigns changes" typically means an assignment for a
specific set of changes.  If the scope of the changes increased over time,
then the new changes would not be covered by the old assignment.

I'd be much more comfortable if Algorithmics would sign a past & future 
assignment for binutils, gcc & gdb.

jeff



From owner-linux-mips@oss.sgi.com Thu Jun  6 10:41:09 2002
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Date: Thu, 6 Jun 2002 10:40:37 -0700
From: William Jhun <wjhun@ayrnetworks.com>
To: "David S. Miller" <davem@redhat.com>
Cc: "linux-kernel@vger.kernel.org"@ayrnetworks.com,
   "linux-mips@oss.sgi.com"@ayrnetworks.com
Subject: Re: Deprecate pci_dma_sync_{single,sg}()?
Message-ID: <20020606104036.A11943@ayrnetworks.com>
References: <20020605131231.B10773@ayrnetworks.com> <20020605.154747.58455261.davem@redhat.com>
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On Wed, Jun 05, 2002 at 03:47:47PM -0700, David S. Miller wrote:
>    From: William Jhun <wjhun@ayrnetworks.com>
>    Date: Wed, 5 Jun 2002 13:12:31 -0700
>    
>    In the current linux-mips implementation, this has some subtle problems:
>    pci_unmap_{single,sg}() is essentially a no-op.
> 
> Right, I see the problem.  I'll think about this some more.
> 
> As it stands now, I think the correct solution is to require
> pci_dma_prep_single() before giving the buffer back to the
> device after the read.

Right, that's what I was thinking. Is it asking a lot to demand that all
existing drivers that use this interface add pci_dma_prep_single()? How
will backward compatiblility with older drivers work? That's why I
suggested leaving pci_dma_sync_single() and adding
pci_dma_release_single() which can leave the cache flush to
pci_dma_prep_single(). It seems like elsewhere, like the D-cache
flushing interface (for virtual aliasing), both old and new interfaces
co-exist. Does this seem to work out O.K. in your experience?

Will

From owner-linux-mips@oss.sgi.com Thu Jun  6 11:13:01 2002
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Message-ID: <007501c20d86$f339b7a0$10eca8c0@grendel>
From: "Kevin D. Kissell" <kevink@mips.com>
To: "Kjeld Borch Egevang" <kjelde@mips.com>,
   "linux-mips mailing list" <linux-mips@oss.sgi.com>
References: <Pine.LNX.4.44.0206061657510.25647-100000@coplin19.mips.com>
Subject: Re: Float crash. Fix in exit_thread()
Date: Thu, 6 Jun 2002 20:21:15 +0200
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It's been a while since I worked on the code,
but I'm not sure why last_task_used_math
needs to be cleared if there is no FPU.
The way the FPU emulator was integrated,
the FPU register storage *is* the thread
context, so if there is no FPU, there was no 
FPU context switching, lazy or otherwise.  
Sounds like someone broke this.

Beyond that, the CFC1 instruction is presumably
there because in the R4000 (at least) it is specified
as the means to force the FP pipeline to drain
before the context switch.  I would suppose this
would be done in Linux to avoid mis-attribution
of FP exceptions. (See chapter 6 of the R4000 
User's manual, page 160 in the Second Edition).

            Kevin K.

----- Original Message ----- 
From: "Kjeld Borch Egevang" <kjelde@mips.com>
To: "linux-mips mailing list" <linux-mips@oss.sgi.com>
Sent: Thursday, June 06, 2002 5:06 PM
Subject: Float crash. Fix in exit_thread()


> I'm running on a system with no FPU. Now, I've got a program do_float 
> which seems to work fine. But if I enter:
> 
> /bin/echo hello; ./do_float
> 
> it terminates with a bus error or FP error. The bug is in exit_thread(). 
> Can anyone explain to me, what good the "cfc1 $0,$31" does?
> 
> 
> Here is the patch:
> 
> RCS file: /cvs/linux/arch/mips/kernel/process.c,v
> retrieving revision 1.36
> diff -u -r1.36 process.c
> --- process.c   2002/05/29 18:36:28     1.36
> +++ process.c   2002/06/06 14:51:32
> @@ -54,9 +54,11 @@
>  void exit_thread(void)
>  {
>         /* Forget lazy fpu state */
> -       if (last_task_used_math == current && mips_cpu.options & MIPS_CPU_FPU) {
> -               __enable_fpu();
> -               __asm__ __volatile__("cfc1\t$0,$31");
> +       if (last_task_used_math == current) {
> +               if (mips_cpu.options & MIPS_CPU_FPU) {
> +                       __enable_fpu();
> +                       __asm__ __volatile__("cfc1\t$0,$31");
> +               }
>                 last_task_used_math = NULL;
>         }
>  }
> @@ -64,9 +66,11 @@
>  void flush_thread(void)
>  {
>         /* Forget lazy fpu state */
> -       if (last_task_used_math == current && mips_cpu.options & MIPS_CPU_FPU) {
> -               __enable_fpu();
> -               __asm__ __volatile__("cfc1\t$0,$31");
> +       if (last_task_used_math == current) {
> +               if (mips_cpu.options & MIPS_CPU_FPU) {
> +                       __enable_fpu();
> +                       __asm__ __volatile__("cfc1\t$0,$31");
> +               }
>                 last_task_used_math = NULL;
>         }
>  }
> 
> 
> 
> /Kjeld
> 
> 
> -- 
> _    _ ____  ___                       Mailto:kjelde@mips.com
> |\  /|||___)(___    MIPS Denmark       Direct: +45 44 86 55 85
> | \/ |||    ____)   Lautrupvang 4 B    Switch: +45 44 86 55 55
>   TECHNOLOGIES      DK-2750 Ballerup   Fax...: +45 44 86 55 56
>                     Denmark            http://www.mips.com/
> 
> 


From owner-linux-mips@oss.sgi.com Thu Jun  6 13:58:17 2002
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Date: Thu, 6 Jun 2002 23:00:04 +0200 (CEST)
From: Kjeld Borch Egevang <kjelde@mips.com>
To: "Kevin D. Kissell" <kevink@mips.com>
cc: linux-mips mailing list <linux-mips@oss.sgi.com>
Subject: Re: Float crash. Fix in exit_thread()
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On Thu, 6 Jun 2002, Kevin D. Kissell wrote:

> It's been a while since I worked on the code,
> but I'm not sure why last_task_used_math
> needs to be cleared if there is no FPU.
> The way the FPU emulator was integrated,
> the FPU register storage *is* the thread
> context, so if there is no FPU, there was no 
> FPU context switching, lazy or otherwise.  
> Sounds like someone broke this.

If you check do_cpu in traps.c you'll find:

fp_emul:
        if (last_task_used_math != current) {
                if (!current->used_math) {
                        fpu_emulator_init_fpu();
                        current->used_math = 1;
                }
        }
        sig = fpu_emulator_cop1Handler(0, regs, &current->thread.fpu.soft);
        last_task_used_math = current;
        if (sig)


fpu_emulator_init_fpu() is not called, when two processes are created like 
I described. Alternatively the test "if (last_task_used_math != current)" 
could be removed.

> Beyond that, the CFC1 instruction is presumably
> there because in the R4000 (at least) it is specified
> as the means to force the FP pipeline to drain
> before the context switch.  I would suppose this
> would be done in Linux to avoid mis-attribution
> of FP exceptions. (See chapter 6 of the R4000 
> User's manual, page 160 in the Second Edition).

Great. It was exactly something like that I was looking for. Perhaps a 
comment would be nice in the code here ;-)

/Kjeld

-- 
_    _ ____  ___                       Mailto:kjelde@mips.com
|\  /|||___)(___    MIPS Denmark       Direct: +45 44 86 55 85
| \/ |||    ____)   Lautrupvang 4 B    Switch: +45 44 86 55 55
  TECHNOLOGIES      DK-2750 Ballerup   Fax...: +45 44 86 55 56
                    Denmark            http://www.mips.com/


From owner-linux-mips@oss.sgi.com Thu Jun  6 15:06:26 2002
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	Thu, 6 Jun 2002 23:12:52 +0200
Date: Thu, 6 Jun 2002 23:12:52 +0200
From: Pavel Machek <pavel@ucw.cz>
To: James Simmons <jsimmons@transvirtual.com>
Cc: Linux Fbdev development list <linux-fbdev-devel@lists.sourceforge.net>,
   Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
   linux-mips@oss.sgi.com, linux-mips-kernel@lists.sourceforge.net
Subject: tx3912 Re: [PATCH] fbdev updates.
Message-ID: <20020606211252.GA1112@elf.ucw.cz>
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Hi!

>    This patch includes the latest in the fbdev BK repository. I have
> modified several fbdev drivers (maxinefb, tx3912fb, pmag drivers) to the
> new api. Please test these changes out before I submit them to linus.
> Thank you. It is against the latest BK tree and 2.5.20.

Does the code even boot on any machine having tx3912fb?
									Pavel
-- 
(about SSSCA) "I don't say this lightly.  However, I really think that the U.S.
no longer is classifiable as a democracy, but rather as a plutocracy." --hpa

From owner-linux-mips@oss.sgi.com Thu Jun  6 17:03:18 2002
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Date: Fri, 7 Jun 2002 01:54:54 +0200
To: Ilya Volynets <ilya@theIlya.com>
Cc: nick@snowman.net, linux-mips@oss.sgi.com
Subject: Re: 3 questions about linux-2.4.18 and R3000
Message-ID: <20020606235453.GA5079@rembrandt.csv.ica.uni-stuttgart.de>
References: <20020603235311.GJ23411@rembrandt.csv.ica.uni-stuttgart.de> <Pine.LNX.4.21.0206041341130.31816-100000@ns> <20020605223736.GN23411@rembrandt.csv.ica.uni-stuttgart.de> <20020605235041.7895.qmail@gateway.total-knowledge.com>
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From: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
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Ilya Volynets wrote:
[snip]
> > > Is it also an R10k system, or are
> > > you useing an r4k system?
> >
> > IT's r10k. AFAIH the r4k systems have still ARCS32 and should be
> > able to boot a 32 bit kernel.
> And how are you dealing with R10K speculative execution
> in non-cache-coherent systems problem?

Not yet. I plan to modify the assembler for it.


Thiemo

From owner-linux-mips@oss.sgi.com Fri Jun  7 08:09:48 2002
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Subject: LTP RPM maintainers wanted
To: linux-mips@oss.sgi.com
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Hi all,

  The Linux Test Project is looking for a volunteer to maintain a MIPS
binary RPM.  All this person would have to do is build the binary RPM, from
the source RPM and spec file supplied each month, and send this back to me.
I would take care of the rest.  The releases are once a month, and that's
it.  The maintainer would not be responsible for any problems that arise
from installing the RPM.  We basically just want to be able to provide the
option of installing a pre-compiled testsuite...if problems arise, the
source is installed as well, so users can always re-compile.

- Robbie

Robert V. Williamson <robbiew@us.ibm.com>
Linux Test Project
IBM Linux Technology Center
Phone: (512) 838-9295   T/L: 638-9295
http://ltp.sourceforge.net



From owner-linux-mips@oss.sgi.com Fri Jun  7 15:14:32 2002
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Date: Sat, 8 Jun 2002 00:15:14 +0200 (CEST)
From: Vivien Chappelier <vivien.chappelier@enst-bretagne.fr>
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To: linux-mips@oss.sgi.com
Subject: R10K speculative store on non-coherent systems workaround proposal
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Hi,

	Here is a proposal for a software workaround to speculative
execution on a non-coherent system such as the i2 R10k and the o2 R10k.

1. Problem:
===========

	The R10000 processor can (and will) execute intructions ahead.
These instructions will be cancelled if they're not supposed to execute,
e.g. if a jump happened. If a load or store instruction is executed
speculatively, and the accessed memory is not in the cache, the cache
line will be fetched in main memory and, on a store, be marked dirty.
These speculative loads and stores can happen anywhere, since there might
be old values in registers used in a speculative load/store
instruction that would be cancelled afterwards.

The problem is:
	- on a speculative load, the fetched cache line will remain in the
cache even if the speculative load is cancelled
	- on a speculative store, the *dirty* cache line will remain in
the cache even if the speculative store is cancelled

	On non-coherent systems we need to flush the cache lines to main
memory before doing DMA to device, so that the device can see them. We
also need to invalidate lines before reading from a DMA'd buffer to make
sure the CPU will read main memory and not the cache.
	However, if a speculative load or store happens during DMA
transfer, the cache line will be fetched from memory and, on a store, 
be marked dirty. That means this cache line could be evicted when the
line is needed, thus being written back in memory if it was dirty,
thus overwritting the data a device could have put in the DMA
buffer. Something we really don't want to happen ;)

2. Proposed solution
====================

	Speculative execution will not happen in the following conditions:
		- access to memory is uncached
		- the speculated instruction causes an exception: that
also means a speculative load/store will not happen in a mapped memory
region which doesn't have a TLB line for it.

	This second point means that any mapped space can be made safe by
removing the DMA'd buffer address translations from the TLB or by marking
them 'uncached' during DMA transfer.
	The remaining unmapped adress spaces are:
		- kseg1, which is safe since uncached
		- kseg0, which can turned uncached with the K0 bits
from the CPO Config register
		- xkphys which will cause adress error if the KX bit is
not set, the aborting the speculative load/store before it can do harm ;)

	Since we need to turn KX off, xkseg will not be accessible
either.. and since we need to have KSEG0 uncached, we need to remap the
kernel elsewhere if we want performance ;). We could use the xsseg
segment, available in Supervisor mode, which is mapped (safe) and moreover
allows to access all memory (on o2 it can be up to 2G I think, whereas in
32bit mode, only 512Mb would be accessible). So the proposed workaround is
to permanently map the lower 16MB of memory in xsseg in using a wired TLB
entry and a page size of 16MB. This memory would not be usable for
DMA. Everything else would, so we could for example reserve the upper 16Mb
for DMA (and give them to the DMA zoned memory allocator). On exception or
error, the handler (in KSEG0) would set CU0 to allow access to CPO, then
switch to Supervisor mode and jump to the equivalent xsseg location and
continue execution in Supervisor mode. The code for returning to userland
would need to clear the CU0 bit, to prevent user access to CP0.
	Before DMA transfer, the DMA'd buffer cache lines would be
flushed, and then it would be remapped 'uncached', thus preventing that
any speculative load or store to this memory happens during
transfer. After the DMA transfer, the cache would be invalidated to make
sure main memory is read, and the DMA buffer would be remapped 'cacheable
non-coherent'.
	A diagram is attached to illustrate the workaround. Comments,
suggestions (and even flames) are welcome before anyone starts coding
the workaround ;)

regards,
Vivien Chappelier.


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--279724308-1017530808-1023488114=:2120--

From owner-linux-mips@oss.sgi.com Sat Jun  8 00:16:00 2002
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Date: Sat, 8 Jun 2002 15:17:55 +0800 (CST)
From: =?gb2312?q?Qingbo=20Wu?= <wu_qingbo2000@yahoo.com.cn>
Subject: can linux work well on sgi-ip27 system
To: linux-mips@oss.sgi.com
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Hi, all,

I read the code under arch/mips64, and find
some code about sgi-ip27. I do not know if
linux can work well on sgi-ip27 system.
If someone knows, please give me a reply.
Thanks in advance!

Best Regards,

Barry

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From owner-linux-mips@oss.sgi.com Sat Jun  8 06:42:59 2002
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From: "Kevin D. Kissell" <kevink@mips.com>
To: "Kjeld Borch Egevang" <kjelde@mips.com>,
   "Brad Parker" <brad@parker.boston.ma.us>
Cc: "linux-mips mailing list" <linux-mips@oss.sgi.com>
References: <200206081240.g58Cewe10560@p2.parker.boston.ma.us>
Subject: Re: float crash
Date: Sat, 8 Jun 2002 15:51:27 +0200
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The FP sr value does of course get initialized by default,
but the bug which Kjeld identified could prevent it.
The proper initialization of the emulated FPU state is
done only if last_task_used_math != current, under
the assumption that if the current task is the last task
to have used the "FPU", the current emulation cannot
be its first.  But in exit_thread()/flush_thread(), we
set last_task_used_math to NULL only if we have
an FPU.  Kjeld's patch breaks down the code so
that the *hardware* shutdown is done only if there
is an FPU, but the clearing of last_task_used_math
must be done whenever the current process has done FP.
Sorry about my offhand remark about no understanding
its relevance in my earlier response about the usefulness
of cfc1 $0,$31.

Without Kjeld's patch, a process inheriting a thread
context slot from a process which had done FP
emulation would have inherited the FP register 
state, including SR, of that previous process.
If you're seeing the problem only *with* Kjeld's
patch, there must have been a typo inserted in
the chain somewhere...

            Kevin K.

----- Original Message ----- 
From: "Brad Parker" <brad@parker.boston.ma.us>
To: "Kjeld Borch Egevang" <kjelde@mips.com>; "Kevin D. Kissell" <kevink@mips.com>
Cc: "linux-mips mailing list" <linux-mips@oss.sgi.com>
Sent: Saturday, June 08, 2002 2:40 PM
Subject: re: float crash


> 
> Quick question -
> 
> I'm running a 2.4.17 kernel on an Au1000 (MIPS32).  Trying to run
> Kaffe I get SIGFPE's in odd places (like dividing 11 by 44).  I tracked
> it down to the fpe emulator setting the cx bit which is setting
> the "inexact" bit in the fp status reg.  
> 
> I think the real problem is that the fp sr is not being initialized.
> It doesn't happen in a trivial program but in Kaffe it happens a lot.
> it's somewhat random, however, as if something is not initialized.
> 
> I wonder if the fix you two where talking about is the problem; i.e.
> in traps.c "if (last_task_used_math != current) {"
> 
> Is there a recommended fix?  Just comment out the test?
> 
> thanks!
> 
> -brad
> 
> ps: I tried to subscribe to the linux-mips list but the sendmail on
> oss.sgi.com is rejecting my email with "access denied".  I don't have
> any open relays and I'm not a spammer :-)  I can't even send email
> to the postmaster...
> 
> 


From owner-linux-mips@oss.sgi.com Sat Jun  8 17:13:48 2002
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Date: Fri, 07 Jun 2002 15:00:15 +0200
From: Carsten Langgaard <carstenl@mips.com>
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There has been some interest for the 64-bit kernel, so I have pull
together a patch against the latest sources, which contains our local
fixes and changes.
Could some please apply these fixes.

Added file are
arch/mips64/mm/c-mips64.c
arch/mips64/mm/pg-mips64.c
arch/mips64/mm/tlb-r4k.c
include/asm-mips64/mips64_cache.h

/Carsten


--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



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Index: arch/mips64/Makefile
===================================================================
RCS file: /cvs/linux/arch/mips64/Makefile,v
retrieving revision 1.22.2.3
diff -u -r1.22.2.3 Makefile
--- arch/mips64/Makefile	2002/02/26 23:59:53	1.22.2.3
+++ arch/mips64/Makefile	2002/06/07 12:26:00
@@ -66,6 +66,9 @@
 ifdef CONFIG_CPU_SB1
 CFLAGS		+= -mcpu=r8000 -mips4
 endif
+ifdef CONFIG_CPU_MIPS64
+CFLAGS		+= -mcpu=r8000 -mips4
+endif
 
 #
 # We unconditionally build the math emulator
Index: arch/mips64/config.in
===================================================================
RCS file: /cvs/linux/arch/mips64/config.in,v
retrieving revision 1.50.2.9
diff -u -r1.50.2.9 config.in
--- arch/mips64/config.in	2002/05/29 14:30:57	1.50.2.9
+++ arch/mips64/config.in	2002/06/07 12:26:00
@@ -70,10 +70,14 @@
 if [ "$CONFIG_MIPS_MALTA" = "y" ]; then
    define_bool CONFIG_BOOT_ELF32 y
    define_bool CONFIG_I8259 y
+   define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_NEW_TIME_C y
    define_int CONFIG_L1_CACHE_SHIFT 5
    define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_PCI y
    define_bool CONFIG_SWAP_IO_SPACE y
+   define_bool CONFIG_PC_KEYB y
 fi
 if [ "$CONFIG_SGI_IP22" = "y" ]; then
    define_bool CONFIG_ARC32 y
@@ -118,20 +122,25 @@
 mainmenu_option next_comment
 comment 'CPU selection'
 
-choice 'CPU type' \
-	"R4300	CONFIG_CPU_R4300 \
-	 R4x00	CONFIG_CPU_R4X00 \
-	 R5000	CONFIG_CPU_R5000 \
-	 R52x0	CONFIG_CPU_NEVADA \
-	 R8000	CONFIG_CPU_R8000 \
-	 R10000	CONFIG_CPU_R10000 \
-	 SB1	CONFIG_CPU_SB1" R4x00
+choice 'CPU type'				\
+	"R4300 CONFIG_CPU_R4300			\
+	 R4x00 CONFIG_CPU_R4X00			\
+	 R5000 CONFIG_CPU_R5000			\
+	 R52x0 CONFIG_CPU_NEVADA		\
+	 R8000 CONFIG_CPU_R8000			\
+	 R10000 CONFIG_CPU_R10000		\
+	 SB1   CONFIG_CPU_SB1			\
+	 MIPS64 CONFIG_CPU_MIPS64" R4x00
 endmenu
 
 if [ "$CONFIG_CPU_SB1" = "y" ]; then
    bool '  Workarounds for pass 1 sb1 bugs' CONFIG_SB1_PASS_1_WORKAROUNDS
    bool '  Support for SB1 Cache Error handler' CONFIG_SB1_CACHE_ERROR
    define_bool CONFIG_VTAG_ICACHE y
+fi
+
+if [ "$CONFIG_CPU_MIPS64" = "y" ]; then
+   bool '  Support for Virtual Tagged I-cache' CONFIG_VTAG_ICACHE
 fi
 
 define_bool CONFIG_CPU_HAS_LLSC y
Index: arch/mips64/kernel/Makefile
===================================================================
RCS file: /cvs/linux/arch/mips64/kernel/Makefile,v
retrieving revision 1.11.2.5
diff -u -r1.11.2.5 Makefile
--- arch/mips64/kernel/Makefile	2002/06/03 15:16:49	1.11.2.5
+++ arch/mips64/kernel/Makefile	2002/06/07 12:26:00
@@ -15,12 +15,15 @@
 
 export-objs = irq.o mips64_ksyms.o pci-dma.o setup.o smp.o
 
-obj-y	:= branch.o entry.o irq.o proc.o process.o ptrace.o r4k_cache.o \
-	   r4k_fpu.o r4k_genex.o r4k_switch.o reset.o scall_64.o semaphore.o \
-	   setup.o signal.o syscall.o time.o traps.o unaligned.o
+obj-y	:= branch.o entry.o proc.o process.o ptrace.o r4k_cache.o \
+	   r4k_fpu.o r4k_genex.o r4k_switch.o reset.o scall_64.o \
+	   semaphore.o setup.o signal.o syscall.o traps.o unaligned.o
 
+obj-$(CONFIG_NEW_IRQ)           += irq.o
 obj-$(CONFIG_I8259)		+= i8259.o
 obj-$(CONFIG_IRQ_CPU)		+= irq_cpu.o
+
+obj-$(CONFIG_NEW_TIME_C)	+= time.o
 
 obj-$(CONFIG_MODULES)		+= mips64_ksyms.o
 obj-$(CONFIG_MIPS32_COMPAT)	+= linux32.o scall_o32.o signal32.o ioctl32.o
Index: arch/mips64/kernel/entry.S
===================================================================
RCS file: /cvs/linux/arch/mips64/kernel/entry.S,v
retrieving revision 1.11.2.4
diff -u -r1.11.2.4 entry.S
--- arch/mips64/kernel/entry.S	2002/05/29 03:03:17	1.11.2.4
+++ arch/mips64/kernel/entry.S	2002/06/07 12:26:00
@@ -24,7 +24,7 @@
 FEXPORT(ret_from_fork)
 		move	a0, v0			# prev
 		jal	schedule_tail
-		lw	t0, TASK_PTRACE($28)	# syscall tracing enabled?
+		ld	t0, TASK_PTRACE($28)	# syscall tracing enabled?
 		andi	t0, PT_TRACESYS
 		bnez	t0, tracesys_exit
 		j	ret_from_sys_call
Index: arch/mips64/kernel/head.S
===================================================================
RCS file: /cvs/linux/arch/mips64/kernel/head.S,v
retrieving revision 1.34.2.4
diff -u -r1.34.2.4 head.S
--- arch/mips64/kernel/head.S	2002/02/26 05:59:03	1.34.2.4
+++ arch/mips64/kernel/head.S	2002/06/07 12:26:00
@@ -92,7 +92,7 @@
 	__INIT
 
 NESTED(kernel_entry, 16, sp)			# kernel entry point
-
+	.set	noreorder
 	ori	sp, 0xf				# align stack on 16 byte.
 	xori	sp, 0xf
 
@@ -111,8 +111,22 @@
 	set_saved_sp	sp, t0
 
 	dsubu	sp, 4*SZREG			# init stack pointer
+	
+	/* The firmware/bootloader passes argc/argp/envp
+	 * to us as arguments.  But clear bss first because
+	 * the romvec and other important info is stored there
+	 * by prom_init().
+	 */
+        la      t0, _edata
+        sd      zero, (t0)
+        la      t1, (_end - 8)
+1:
+        daddiu  t0, 8
+        bne     t0, t1, 1b
+         sd     zero, (t0)
 
 	j	init_arch
+	 nop
 	END(kernel_entry)
 
 #ifdef CONFIG_SMP
Index: arch/mips64/kernel/ioctl32.c
===================================================================
RCS file: /cvs/linux/arch/mips64/kernel/ioctl32.c,v
retrieving revision 1.10.2.1
diff -u -r1.10.2.1 ioctl32.c
--- arch/mips64/kernel/ioctl32.c	2001/12/03 07:26:20	1.10.2.1
+++ arch/mips64/kernel/ioctl32.c	2002/06/07 12:26:00
@@ -27,6 +27,7 @@
 #include <linux/auto_fs.h>
 #include <linux/ext2_fs.h>
 #include <linux/raid/md_u.h>
+#include <linux/rtc.h>
 #include <scsi/scsi.h>
 #undef __KERNEL__		/* This file was born to be ugly ...  */
 #include <scsi/scsi_ioctl.h>
@@ -834,7 +835,25 @@
 	IOCTL32_DEFAULT(AUTOFS_IOC_CATATONIC),
 	IOCTL32_DEFAULT(AUTOFS_IOC_PROTOVER),
 	IOCTL32_HANDLER(AUTOFS_IOC_SETTIMEOUT32, ioc_settimeout),
-	IOCTL32_DEFAULT(AUTOFS_IOC_EXPIRE)
+	IOCTL32_DEFAULT(AUTOFS_IOC_EXPIRE),
+
+	/* Little p (/dev/rtc, /dev/envctrl, etc.) */
+	IOCTL32_DEFAULT(_IOR('p', 20, int[7])), /* RTCGET */
+	IOCTL32_DEFAULT(_IOW('p', 21, int[7])), /* RTCSET */
+	IOCTL32_DEFAULT(RTC_AIE_ON),
+	IOCTL32_DEFAULT(RTC_AIE_OFF),
+	IOCTL32_DEFAULT(RTC_UIE_ON),
+	IOCTL32_DEFAULT(RTC_UIE_OFF),
+	IOCTL32_DEFAULT(RTC_PIE_ON),
+	IOCTL32_DEFAULT(RTC_PIE_OFF),
+	IOCTL32_DEFAULT(RTC_WIE_ON),
+	IOCTL32_DEFAULT(RTC_WIE_OFF),
+	IOCTL32_DEFAULT(RTC_ALM_SET),
+	IOCTL32_DEFAULT(RTC_ALM_READ),
+	IOCTL32_DEFAULT(RTC_RD_TIME),
+	IOCTL32_DEFAULT(RTC_SET_TIME),
+	IOCTL32_DEFAULT(RTC_WKALM_SET),
+	IOCTL32_DEFAULT(RTC_WKALM_RD)
 };
 
 #define NR_IOCTL32_HANDLERS	(sizeof(ioctl32_handler_table) /	\
Index: arch/mips64/kernel/pci-dma.c
===================================================================
RCS file: /cvs/linux/arch/mips64/kernel/Attic/pci-dma.c,v
retrieving revision 1.1.2.2
diff -u -r1.1.2.2 pci-dma.c
--- arch/mips64/kernel/pci-dma.c	2002/05/29 03:03:17	1.1.2.2
+++ arch/mips64/kernel/pci-dma.c	2002/06/07 12:26:00
@@ -10,6 +10,7 @@
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/mm.h>
+#include <linux/module.h>
 #include <linux/string.h>
 #include <linux/pci.h>
 
@@ -22,24 +23,31 @@
 	void *ret;
 	int gfp = GFP_ATOMIC;
 
-	if (hwdev != NULL && hwdev->dma_mask != 0xffffffff)
+	if (hwdev == NULL || hwdev->dma_mask != 0xffffffff)
 		gfp |= GFP_DMA;
 	ret = (void *) __get_free_pages(gfp, get_order(size));
-
 	if (ret != NULL) {
 		memset(ret, 0, size);
+		*dma_handle = __pa(ret);
 #ifdef CONFIG_NONCOHERENT_IO
 		dma_cache_wback_inv((unsigned long) ret, size);
 		ret = KSEG1ADDR(ret);
 #endif
-		*dma_handle = __pa(ret);
-		return ret;
 	}
-	return NULL;
+
+	return ret;
 }
 
 void pci_free_consistent(struct pci_dev *hwdev, size_t size,
 			 void *vaddr, dma_addr_t dma_handle)
 {
-	free_pages((unsigned long) KSEG0ADDR(vaddr), get_order(size));
+	unsigned long addr = (unsigned long) vaddr;
+
+#ifdef CONFIG_NONCOHERENT_IO
+	addr = KSEG0ADDR(addr);
+#endif
+	free_pages(addr, get_order(size));
 }
+
+EXPORT_SYMBOL(pci_alloc_consistent);
+EXPORT_SYMBOL(pci_free_consistent);
Index: arch/mips64/kernel/r4k_fpu.S
===================================================================
RCS file: /cvs/linux/arch/mips64/kernel/r4k_fpu.S,v
retrieving revision 1.3
diff -u -r1.3 r4k_fpu.S
--- arch/mips64/kernel/r4k_fpu.S	2001/05/25 20:07:50	1.3
+++ arch/mips64/kernel/r4k_fpu.S	2002/06/07 12:26:00
@@ -31,7 +31,7 @@
 
 	.set	noreorder
 	/* Save floating point context */
-LEAF(save_fp_context)
+LEAF(_save_fp_context)
 	mfc0	t1, CP0_STATUS
 	sll	t2, t1,5
 
@@ -79,7 +79,7 @@
 
 	jr	ra
 	 li	v0, 0					# success
-	END(save_fp_context)
+	END(_save_fp_context)
 
 /*
  * Restore FPU state:
@@ -90,7 +90,7 @@
  * frame on the current content of c0_status, not on the content of the
  * stack frame which might have been changed by the user.
  */
-LEAF(restore_fp_context)
+LEAF(_restore_fp_context)
 	mfc0	t1, CP0_STATUS
 	sll	t0, t1,5
 	bgez	t0, 1f
@@ -139,7 +139,7 @@
 	ctc1	t0, fcr31
 	jr	ra
 	 li	v0, 0					# success
-	END(restore_fp_context)
+	END(_restore_fp_context)
 
 	.type	fault@function
 	.ent	fault
Index: arch/mips64/kernel/setup.c
===================================================================
RCS file: /cvs/linux/arch/mips64/kernel/setup.c,v
retrieving revision 1.31.2.6
diff -u -r1.31.2.6 setup.c
--- arch/mips64/kernel/setup.c	2002/06/03 15:16:49	1.31.2.6
+++ arch/mips64/kernel/setup.c	2002/06/07 12:26:00
@@ -141,9 +141,6 @@
 	case CPU_NEVADA:
 	case CPU_RM7000:
 	case CPU_TX49XX:
-	case CPU_4KC:
-	case CPU_4KEC:
-	case CPU_4KSC:
 	case CPU_5KC:
 /*	case CPU_20KC:*/
 		cpu_wait = r4k_wait;
@@ -182,6 +179,20 @@
 #endif
 }
 
+/*
+ * Get the FPU Implementation/Revision.
+ */
+static inline unsigned long cpu_get_fpu_id(void)
+{
+	unsigned long tmp, fpu_id;
+
+	tmp = read_32bit_cp0_register(CP0_STATUS);
+	__enable_fpu();
+	fpu_id = read_32bit_cp1_register(CP1_REVISION);
+	write_32bit_cp0_register(CP0_STATUS, tmp);
+	return fpu_id;
+}
+
 /* declaration of the global struct */
 struct mips_cpu mips_cpu = {
     processor_id:	PRID_IMP_UNKNOWN,
@@ -194,15 +205,16 @@
 
 static inline void cpu_probe(void)
 {
-#ifdef CONFIG_CPU_MIPS32
-	unsigned long config0 = read_32bit_cp0_register(CP0_CONFIG);
-	unsigned long config1;
+#ifdef CONFIG_CPU_MIPS64
+	unsigned int config0 = read_32bit_cp0_register(CP0_CONFIG);
+	unsigned int config1;
 
         if (config0 & (1 << 31)) {
-		/* MIPS32 compliant CPU. Read Config 1 register. */
-		mips_cpu.isa_level = MIPS_CPU_ISA_M32;
+		/* MIPS64 compliant CPU. Read Config 1 register. */
+		mips_cpu.isa_level = MIPS_CPU_ISA_M64;
 		mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 
-			MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC;
+			MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
+			MIPS_CPU_32FPR;
 		config1 = read_mips32_cp0_config1();
 		if (config1 & (1 << 3))
 			mips_cpu.options |= MIPS_CPU_WATCH;
@@ -399,25 +411,15 @@
 			break;
 		}
 		break;
-#ifdef CONFIG_CPU_MIPS32
+#ifdef CONFIG_CPU_MIPS64
 	case PRID_COMP_MIPS:
 		switch (mips_cpu.processor_id & 0xff00) {
-		case PRID_IMP_4KC:
-			mips_cpu.cputype = CPU_4KC;
-			break;
-		case PRID_IMP_4KEC:
-			mips_cpu.cputype = CPU_4KEC;
-			break;
-		case PRID_IMP_4KSC:
-			mips_cpu.cputype = CPU_4KSC;
-			break;
 		case PRID_IMP_5KC:
 			mips_cpu.cputype = CPU_5KC;
-			mips_cpu.isa_level = MIPS_CPU_ISA_M64;
 			break;
 		case PRID_IMP_20KC:
 			mips_cpu.cputype = CPU_20KC;
-			mips_cpu.isa_level = MIPS_CPU_ISA_M64;
+			break;
 		default:
 			mips_cpu.cputype = CPU_UNKNOWN;
 			break;
@@ -459,6 +461,8 @@
 	default:
 		mips_cpu.cputype = CPU_UNKNOWN;
 	}
+	if (mips_cpu.options & MIPS_CPU_FPU)
+		mips_cpu.fpu_id = cpu_get_fpu_id();
 }
 
 static inline void cpu_report(void)
@@ -721,10 +725,11 @@
 #endif
 #ifdef CONFIG_SIBYTE_SWARM
 	swarm_setup();
-	bootmem_init();		/* XXX */
 #endif
-
-#ifdef CONFIG_ARC_MEMORY
+#ifdef CONFIG_MIPS_MALTA
+        malta_setup();
+#endif
+#if defined(CONFIG_ARC_MEMORY) || defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_MIPS_MALTA)
 	bootmem_init();
 #endif
 
Index: arch/mips64/kernel/traps.c
===================================================================
RCS file: /cvs/linux/arch/mips64/kernel/traps.c,v
retrieving revision 1.30.2.13
diff -u -r1.30.2.13 traps.c
--- arch/mips64/kernel/traps.c	2002/05/28 06:33:13	1.30.2.13
+++ arch/mips64/kernel/traps.c	2002/06/07 12:26:00
@@ -607,6 +607,15 @@
 	}
 }
 
+asmlinkage int (*save_fp_context)(struct sigcontext *sc);
+asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
+extern asmlinkage int _save_fp_context(struct sigcontext *sc);
+extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
+
+extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
+extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
+
+
 void __init per_cpu_trap_init(void)
 {
 	unsigned int cpu = smp_processor_id();
@@ -630,6 +639,7 @@
 void __init trap_init(void)
 {
 	extern char except_vec0;
+/*	extern char except_vec1_r4k;*/
 	extern char except_vec1_r10k;
 	extern char except_vec2_generic, except_vec2_sb1;
 	extern char except_vec3_generic, except_vec3_r4000;
@@ -692,14 +702,18 @@
 	case CPU_R4600:
 	case CPU_R5000:
 	case CPU_NEVADA:
-		/* Cache error vector  */
-		memcpy((void *)(KSEG0 + 0x100), (void *) KSEG0, 0x80);
-
+        case CPU_5KC:
+        case CPU_20KC:
+        case CPU_RM7000:
 nocache:
 		/* Debug TLB refill handler.  */
 		memcpy((void *)KSEG0, &except_vec0, 0x80);
-		memcpy((void *)KSEG0 + 0x080, &except_vec1_r10k, 0x80);
-
+/*		if ((mips_cpu.options & MIPS_CPU_4KEX)
+                    && (mips_cpu.options & MIPS_CPU_4KTLB)) {
+                        memcpy((void *)KSEG0 + 0x080, &except_vec1_r4k, 0x80);
+			} else { */
+			memcpy((void *)KSEG0 + 0x080, &except_vec1_r10k, 0x80);
+/*		}*/
 		if (mips_cpu.options & MIPS_CPU_VCE) {
 			memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000,
 			       0x80);
@@ -746,6 +760,15 @@
 	default:
 		panic("Unknown CPU type");
 	}
+
+	if (mips_cpu.options & MIPS_CPU_FPU) {
+                save_fp_context = _save_fp_context;
+                restore_fp_context = _restore_fp_context;
+        } else {
+                save_fp_context = fpu_emulator_save_context;
+                restore_fp_context = fpu_emulator_restore_context;
+        }
+
 	flush_icache_range(KSEG0, KSEG0 + 0x200);
 
 	if (mips_cpu.isa_level == MIPS_CPU_ISA_IV)
Index: arch/mips64/mm/Makefile
===================================================================
RCS file: /cvs/linux/arch/mips64/mm/Makefile,v
retrieving revision 1.8.2.2
diff -u -r1.8.2.2 Makefile
--- arch/mips64/mm/Makefile	2002/02/21 04:38:01	1.8.2.2
+++ arch/mips64/mm/Makefile	2002/06/07 12:26:00
@@ -17,6 +17,8 @@
 obj-$(CONFIG_CPU_R10000)	+= andes.o tlbex-r4k.o tlb-glue-r4k.o
 obj-$(CONFIG_CPU_SB1)		+= pg-sb1.o c-sb1.o tlb-sb1.o tlbex-r4k.o \
 				   tlb-glue-r4k.o
+obj-$(CONFIG_CPU_MIPS64)	+= pg-mips64.o c-mips64.o tlb-r4k.o \
+				   tlbex-r4k.o tlb-glue-r4k.o
 
 #
 # Debug TLB exception handler, currently unused
Index: arch/mips64/mm/loadmmu.c
===================================================================
RCS file: /cvs/linux/arch/mips64/mm/loadmmu.c,v
retrieving revision 1.14.2.3
diff -u -r1.14.2.3 loadmmu.c
--- arch/mips64/mm/loadmmu.c	2002/02/18 01:14:46	1.14.2.3
+++ arch/mips64/mm/loadmmu.c	2002/06/07 12:26:01
@@ -54,33 +54,27 @@
 extern void ld_mmu_andes(void);
 extern void ld_mmu_sb1(void);
 extern void sb1_tlb_init(void);
+extern void ld_mmu_mips64(void);
+extern void r4k_tlb_init(void);
 
+
 void __init load_mmu(void)
 {
-	switch(mips_cpu.cputype) {
+	if (mips_cpu.options & MIPS_CPU_4KTLB) {
 #if defined (CONFIG_CPU_R4300)						\
     || defined (CONFIG_CPU_R4X00)					\
     || defined (CONFIG_CPU_R5000)					\
     || defined (CONFIG_CPU_NEVADA)
-	case CPU_R4000PC:
-	case CPU_R4000SC:
-	case CPU_R4000MC:
-	case CPU_R4200:
-	case CPU_R4300:
-	case CPU_R4400PC:
-	case CPU_R4400SC:
-	case CPU_R4400MC:
-	case CPU_R4600:
-	case CPU_R4640:
-	case CPU_R4650:
-	case CPU_R4700:
-	case CPU_R5000:
-	case CPU_R5000A:
-	case CPU_NEVADA:
 		printk("Loading R4000 MMU routines.\n");
 		ld_mmu_r4xx0();
-		break;
 #endif
+#if defined(CONFIG_CPU_MIPS64)
+		printk("Loading MIPS64 MMU routines.\n");
+		ld_mmu_mips64();
+		r4k_tlb_init();
+#endif
+
+	} else switch(mips_cpu.cputype) {
 #ifdef CONFIG_CPU_R10000
 	case CPU_R10000:
 		printk("Loading R10000 MMU routines.\n");
@@ -94,8 +88,7 @@
 		sb1_tlb_init();
 		break;
 #endif
-
 	default:
 		/* XXX We need an generic routine in the MIPS port
 		 * XXX to jabber stuff onto the screen on all machines
Index: include/asm-mips64/addrspace.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/addrspace.h,v
retrieving revision 1.10
diff -u -r1.10 addrspace.h
--- include/asm-mips64/addrspace.h	2001/07/09 00:25:37	1.10
+++ include/asm-mips64/addrspace.h	2002/06/07 12:26:15
@@ -29,15 +29,15 @@
  * Returns the physical address of a KSEG0/KSEG1 address
  */
 #define CPHYSADDR(a)		(((unsigned long)(a)) & 0x000000001fffffffUL)
-#define PHYSADDR(a)		(((unsigned long)(a)) & 0x000000ffffffffffUL)
+#define PHYSADDR(a)		(((unsigned long)(a)) & 0x000000001fffffffUL)
 
 /*
  * Map an address to a certain kernel segment
  */
-#define KSEG0ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x000000ffffffffffUL) | KSEG0))
-#define KSEG1ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x000000ffffffffffUL) | KSEG1))
-#define KSEG2ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x000000ffffffffffUL) | KSEG2))
-#define KSEG3ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x000000ffffffffffUL) | KSEG3))
+#define KSEG0ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x000000001fffffffUL) | KSEG0))
+#define KSEG1ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x000000001fffffffUL) | KSEG1))
+#define KSEG2ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x000000001fffffffUL) | KSEG2))
+#define KSEG3ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x000000001fffffffUL) | KSEG3))
 
 /*
  * Memory segments (64bit kernel mode addresses)
Index: include/asm-mips64/cache.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/cache.h,v
retrieving revision 1.7.2.1
diff -u -r1.7.2.1 cache.h
--- include/asm-mips64/cache.h	2002/05/29 03:03:18	1.7.2.1
+++ include/asm-mips64/cache.h	2002/06/07 12:26:15
@@ -23,6 +23,11 @@
 };
 #endif
 
+/*
+ * Flag definitions
+ */
+#define MIPS_CACHE_NOT_PRESENT 0x00000001
+
 /* bytes per L1 cache line */
 #define L1_CACHE_BYTES		(1 << CONFIG_L1_CACHE_SHIFT)
 
Index: include/asm-mips64/checksum.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/checksum.h,v
retrieving revision 1.12
diff -u -r1.12 checksum.h
--- include/asm-mips64/checksum.h	2001/10/31 02:31:23	1.12
+++ include/asm-mips64/checksum.h	2002/06/07 12:26:15
@@ -161,9 +161,9 @@
 	: "=r" (sum)
 	: "0" (daddr), "r"(saddr),
 #ifdef __MIPSEL__
-	  "r" ((ntohs(len)<<16)+proto*256),
+	  "r" (((unsigned long)ntohs(len)<<16)+proto*256),
 #else
-	  "r" (((proto)<<16)+len),
+	  "r" ((((unsigned long)proto)<<16)+len),
 #endif
 	  "r" (sum));
 
Index: include/asm-mips64/ide.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/ide.h,v
retrieving revision 1.6
diff -u -r1.6 ide.h
--- include/asm-mips64/ide.h	2001/08/22 03:25:05	1.6
+++ include/asm-mips64/ide.h	2002/06/07 12:26:15
@@ -18,6 +18,7 @@
 #ifdef __KERNEL__
 
 #include <linux/config.h>
+#include <asm/io.h>
 
 #ifndef MAX_HWIFS
 # ifdef CONFIG_BLK_DEV_IDEPCI
@@ -79,11 +80,19 @@
 typedef union {
 	unsigned all			: 8;	/* all of the bits together */
 	struct {
+#ifdef __MIPSEB__
+		unsigned bit7           : 1;    /* always 1 */
+		unsigned lba            : 1;    /* using LBA instead of CHS */
+		unsigned bit5           : 1;    /* always 1 */
+		unsigned unit           : 1;    /* drive select number, 0 or 1 */
+		unsigned head           : 4;    /* always zeros here */
+#else
 		unsigned head		: 4;	/* always zeros here */
 		unsigned unit		: 1;	/* drive select number, 0 or 1 */
 		unsigned bit5		: 1;	/* always 1 */
 		unsigned lba		: 1;	/* using LBA instead of CHS */
 		unsigned bit7		: 1;	/* always 1 */
+#endif
 	} b;
 	} select_t;
 
@@ -118,54 +127,141 @@
 
 #if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
 
-#ifdef insl
-#undef insl
-#endif
-#ifdef outsl
-#undef outsl
-#endif
+/* get rid of defs from io.h - ide has its private and conflicting versions */
 #ifdef insw
 #undef insw
 #endif
 #ifdef outsw
 #undef outsw
 #endif
+#ifdef insl
+#undef insl
+#endif
+#ifdef outsl
+#undef outsl
+#endif
+
+#define insw(port, addr, count) ide_insw(port, addr, count)
+#define insl(port, addr, count) ide_insl(port, addr, count)
+#define outsw(port, addr, count) ide_outsw(port, addr, count)
+#define outsl(port, addr, count) ide_outsl(port, addr, count)
+
+static inline void ide_insw(unsigned long port, void *addr, unsigned int count)
+{
+	while (count--) {
+		*(u16 *)addr = *(volatile u16 *)(mips_io_port_base + port);
+		addr += 2;
+	}
+}
+
+static inline void ide_outsw(unsigned long port, void *addr, unsigned int count)
+{
+	while (count--) {
+		*(volatile u16 *)(mips_io_port_base + (port)) = *(u16 *)addr;
+		addr += 2;
+	}
+}
+
+static inline void ide_insl(unsigned long port, void *addr, unsigned int count)
+{
+	while (count--) {
+		*(u32 *)addr = *(volatile u32 *)(mips_io_port_base + port);
+		addr += 4;
+	}
+}
+
+static inline void ide_outsl(unsigned long port, void *addr, unsigned int count)
+{
+	while (count--) {
+		*(volatile u32 *)(mips_io_port_base + (port)) = *(u32 *)addr;
+		addr += 4;
+	}
+}
+
+#define T_CHAR          (0x0000)        /* char:  don't touch  */
+#define T_SHORT         (0x4000)        /* short: 12 -> 21     */
+#define T_INT           (0x8000)        /* int:   1234 -> 4321 */
+#define T_TEXT          (0xc000)        /* text:  12 -> 21     */
+
+#define T_MASK_TYPE     (0xc000)
+#define T_MASK_COUNT    (0x3fff)
+
+#define D_CHAR(cnt)     (T_CHAR  | (cnt))
+#define D_SHORT(cnt)    (T_SHORT | (cnt))
+#define D_INT(cnt)      (T_INT   | (cnt))
+#define D_TEXT(cnt)     (T_TEXT  | (cnt))
+
+static u_short driveid_types[] = {
+	D_SHORT(10),    /* config - vendor2 */
+	D_TEXT(20),     /* serial_no */
+	D_SHORT(3),     /* buf_type - ecc_bytes */
+	D_TEXT(48),     /* fw_rev - model */
+	D_CHAR(2),      /* max_multsect - vendor3 */
+	D_SHORT(1),     /* dword_io */
+	D_CHAR(2),      /* vendor4 - capability */
+	D_SHORT(1),     /* reserved50 */
+	D_CHAR(4),      /* vendor5 - tDMA */
+	D_SHORT(4),     /* field_valid - cur_sectors */
+	D_INT(1),       /* cur_capacity */
+	D_CHAR(2),      /* multsect - multsect_valid */
+	D_INT(1),       /* lba_capacity */
+	D_SHORT(194)    /* dma_1word - reservedyy */
+};
 
-#define insw(p,a,c)							\
-do {									\
-	unsigned short *ptr = (unsigned short *)(a);			\
-	unsigned int i = (c);						\
-	while (i--)							\
-		*ptr++ = inw(p);					\
-} while (0)
-#define insl(p,a,c)							\
-do {									\
-	unsigned long *ptr = (unsigned long *)(a);			\
-	unsigned int i = (c);						\
-	while (i--)							\
-		*ptr++ = inl(p);					\
-} while (0)
-#define outsw(p,a,c)							\
-do {									\
-	unsigned short *ptr = (unsigned short *)(a);			\
-	unsigned int i = (c);						\
-	while (i--)							\
-		outw(*ptr++, (p));					\
-} while (0)
-#define outsl(p,a,c) {							\
-	unsigned long *ptr = (unsigned long *)(a);			\
-	unsigned int i = (c);						\
-	while (i--)							\
-		outl(*ptr++, (p));					\
-} while (0)
+#define num_driveid_types       (sizeof(driveid_types)/sizeof(*driveid_types))
 
-#endif /* defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)  */
+static __inline__ void ide_fix_driveid(struct hd_driveid *id)
+{
+	u_char *p = (u_char *)id;
+	int i, j, cnt;
+	u_char t;
+
+	for (i = 0; i < num_driveid_types; i++) {
+		cnt = driveid_types[i] & T_MASK_COUNT;
+		switch (driveid_types[i] & T_MASK_TYPE) {
+		case T_CHAR:
+			p += cnt;
+			break;
+		case T_SHORT:
+			for (j = 0; j < cnt; j++) {
+				t = p[0];
+				p[0] = p[1];
+				p[1] = t;
+				p += 2;
+			}
+			break;
+		case T_INT:
+			for (j = 0; j < cnt; j++) {
+				t = p[0];
+				p[0] = p[3];
+				p[3] = t;
+				t = p[1];
+				p[1] = p[2];
+				p[2] = t;
+				p += 4;
+			}
+			break;
+		case T_TEXT:
+			for (j = 0; j < cnt; j += 2) {
+				t = p[0];
+				p[0] = p[1];
+				p[1] = t;
+				p += 2;
+			}
+			break;
+		};
+	}
+}
+#else /* defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)  */
+
+#define ide_fix_driveid(id)             do {} while (0)
+
+#endif
 
 /*
  * The following are not needed for the non-m68k ports
  */
 #define ide_ack_intr(hwif)		(1)
-#define ide_fix_driveid(id)		do {} while (0)
 #define ide_release_lock(lock)		do {} while (0)
 #define ide_get_lock(lock, hdlr, data)	do {} while (0)
 
Index: include/asm-mips64/io.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/io.h,v
retrieving revision 1.25.2.5
diff -u -r1.25.2.5 io.h
--- include/asm-mips64/io.h	2002/02/07 02:39:41	1.25.2.5
+++ include/asm-mips64/io.h	2002/06/07 12:26:15
@@ -13,6 +13,7 @@
 #include <linux/config.h>
 #include <asm/addrspace.h>
 #include <asm/page.h>
+#include <asm/byteorder.h>
 
 #ifdef CONFIG_MIPS_ATLAS
 #include <asm/mips-boards/io.h>
@@ -98,23 +99,23 @@
 /*
  * This assumes sane hardware.  The Origin is.
  */
-#define readb(addr)		(*(volatile unsigned char *) (addr))
-#define readw(addr)		(*(volatile unsigned short *) (addr))
-#define readl(addr)		(*(volatile unsigned int *) (addr))
+#define readb(addr)		(*(volatile unsigned char *)(addr))
+#define readw(addr)		__ioswab16((*(volatile unsigned short *)(addr)))
+#define readl(addr)		__ioswab32((*(volatile unsigned int *)(addr)))
 
 #define __raw_readb(addr)	(*(volatile unsigned char *)(addr))
 #define __raw_readw(addr)	(*(volatile unsigned short *)(addr))
 #define __raw_readl(addr)	(*(volatile unsigned int *)(addr))
 
-#define writeb(b,addr)		(*(volatile unsigned char *) (addr) = (b))
-#define writew(w,addr)		(*(volatile unsigned short *) (addr) = (w))
-#define writel(l,addr)		(*(volatile unsigned int *) (addr) = (l))
+#define writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (__ioswab8(b)))
+#define writew(b,addr) ((*(volatile unsigned short *)(addr)) = (__ioswab16(b)))
+#define writel(b,addr) ((*(volatile unsigned int *)(addr)) = (__ioswab32(b)))
 
 #define __raw_writeb(b,addr)	((*(volatile unsigned char *)(addr)) = (b))
 #define __raw_writew(w,addr)	((*(volatile unsigned short *)(addr)) = (w))
 #define __raw_writel(l,addr)	((*(volatile unsigned int *)(addr)) = (l))
 
-#define memset_io(a,b,c)	memset((void *) a,(b),(c))
+#define memset_io(a,b,c)	memset((void *)(a),(b),(c))
 #define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
 #define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
 
@@ -154,12 +155,12 @@
  */
 static inline unsigned long virt_to_phys(volatile void * address)
 {
-	return (unsigned long)address - PAGE_OFFSET;
+	return (unsigned long)address & ~PAGE_OFFSET;
 }
 
 static inline void * phys_to_virt(unsigned long address)
 {
-	return (void *)(address + PAGE_OFFSET);
+	return (void *)(address | PAGE_OFFSET);
 }
 
 /*
@@ -167,12 +168,12 @@
  */
 static inline unsigned long virt_to_bus(volatile void * address)
 {
-	return (unsigned long)address - PAGE_OFFSET;
+	return (unsigned long)address & ~PAGE_OFFSET;
 }
 
 static inline void * bus_to_virt(unsigned long address)
 {
-	return (void *)(address + PAGE_OFFSET);
+	return (void *)(address | PAGE_OFFSET);
 }
 
 
@@ -229,202 +230,131 @@
 	return retval;
 }
 
-/*
- * Talk about misusing macros..
- */
 
-#define __OUT1(s) \
-static inline void __out##s(unsigned int value, unsigned long port) {
+#define outb(val,port)							\
+do {									\
+	*(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val);	\
+} while(0)
+
+#define outw(val,port)							\
+do {									\
+	*(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\
+} while(0)
+
+#define outl(val,port)							\
+do {									\
+	*(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
+} while(0)
+
+#define outb_p(val,port)						\
+do {									\
+	*(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val);	\
+	SLOW_DOWN_IO;							\
+} while(0)
+
+#define outw_p(val,port)						\
+do {									\
+	*(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\
+	SLOW_DOWN_IO;							\
+} while(0)
+
+#define outl_p(val,port)						\
+do {									\
+	*(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
+	SLOW_DOWN_IO;							\
+} while(0)
 
-#define __OUT2(m) \
-__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
+static inline unsigned char inb(unsigned long port)
+{
+	return __ioswab8(*(volatile u8 *)(mips_io_port_base + port));
+}
 
-#define __OUT(m,s) \
-__OUT1(s) __OUT2(m) : : "r" (value), "i" (0), "r" (mips_io_port_base+port)); } \
-__OUT1(s##c) __OUT2(m) : : "r" (value), "ir" (port), "r" (mips_io_port_base)); } \
-__OUT1(s##_p) __OUT2(m) : : "r" (value), "i" (0), "r" (mips_io_port_base+port)); \
-	SLOW_DOWN_IO; } \
-__OUT1(s##c_p) __OUT2(m) : : "r" (value), "ir" (port), "r" (mips_io_port_base)); \
-	SLOW_DOWN_IO; }
-
-#define __IN1(t,s) \
-static inline t __in##s(unsigned long port) { t _v;
-
-/*
- * Required nops will be inserted by the assembler
- */
-#define __IN2(m) \
-__asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
-
-#define __IN(t,m,s) \
-__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return _v; } \
-__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return _v; } \
-__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return _v; } \
-__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return _v; }
-
-#define __INS1(s) \
-static inline void __ins##s(unsigned long port, void * addr, unsigned long count) {
-
-#define __INS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
-	".set\tnoreorder\n\t" \
-	".set\tnoat\n" \
-	"1:\tl" #m "\t$1, %4(%5)\n\t" \
-	"dsubu\t%1, 1\n\t" \
-	"s" #m "\t$1,(%0)\n\t" \
-	"bnez\t%1, 1b\n\t" \
-	"daddiu\t%0, %6\n\t" \
-	".set\tat\n\t" \
-	".set\treorder"
-
-#define __INS(m,s,i) \
-__INS1(s) __INS2(m) \
-	: "=r" (addr), "=r" (count) \
-	: "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), \
-	  "I" (i));} \
-__INS1(s##c) __INS2(m) \
-	: "=r" (addr), "=r" (count) \
-	: "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), \
-	  "I" (i));}
-
-#define __OUTS1(s) \
-static inline void __outs##s(unsigned long port, const void * addr, unsigned long count) {
-
-#define __OUTS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
-	".set\tnoreorder\n\t" \
-	".set\tnoat\n" \
-	"1:\tl" #m "\t$1, (%0)\n\t" \
-	"dsubu\t%1, 1\n\t" \
-	"s" #m "\t$1, %4(%5)\n\t" \
-	"bnez\t%1, 1b\n\t" \
-	"daddiu\t%0, %6\n\t" \
-	".set\tat\n\t" \
-	".set\treorder"
-
-#define __OUTS(m,s,i) \
-__OUTS1(s) __OUTS2(m) \
-	: "=r" (addr), "=r" (count) \
-	: "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), \
-	  "I" (i));} \
-__OUTS1(s##c) __OUTS2(m) \
-	: "=r" (addr), "=r" (count) \
-	: "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), \
-	  "I" (i));}
-
-__IN(unsigned char,b,b)
-__IN(unsigned short,h,w)
-__IN(unsigned int,w,l)
-
-__OUT(b,b)
-__OUT(h,w)
-__OUT(w,l)
-
-__INS(b,b,1)
-__INS(h,w,2)
-__INS(w,l,4)
-
-__OUTS(b,b,1)
-__OUTS(h,w,2)
-__OUTS(w,l,4)
-
-/*
- * Note that due to the way __builtin_constant_p() works, you
- *  - can't use it inside an inline function (it will never be true)
- *  - you don't have to worry about side effects within the __builtin..
- */
-#define outb(val,port) \
-((__builtin_constant_p((port)^(3)) && ((port)^(3)) < 32768) ? \
-	__outbc((val),(port)^(3)) : \
-	__outb((val),(port)^(3)))
-
-#define inb(port) \
-((__builtin_constant_p((port)^(3)) && ((port)^(3)) < 32768) ? \
-	__inbc((port)^(3)) : \
-	__inb((port)^(3)))
-
-#define outb_p(val,port) \
-((__builtin_constant_p((port)^(3)) && ((port)^(3)) < 32768) ? \
-	__outbc_p((val),(port)^(3)) : \
-	__outb_p((val),(port)^(3)))
-
-#define inb_p(port) \
-((__builtin_constant_p((port)^(3)) && ((port)^(3)) < 32768) ? \
-	__inbc_p((port)^(3)) : \
-	__inb_p((port)^(3)))
-
-#define outw(val,port) \
-((__builtin_constant_p(((port)^(2))) && ((port)^(2)) < 32768) ? \
-	__outwc((val),((port)^(2))) : \
-	__outw((val),((port)^(2))))
-
-#define inw(port) \
-((__builtin_constant_p(((port)^(2))) && ((port)^(2)) < 32768) ? \
-	__inwc((port)^(2)) : \
-	__inw((port)^(2)))
-
-#define outw_p(val,port) \
-((__builtin_constant_p((port)^(2)) && ((port)^(2)) < 32768) ? \
-	__outwc_p((val),(port)^(2)) : \
-	__outw_p((val),(port)^(2)))
-
-#define inw_p(port) \
-((__builtin_constant_p((port)^(2)) && ((port)^(2)) < 32768) ? \
-	__inwc_p((port)^(2)) : \
-	__inw_p((port)^(2)))
-
-#define outl(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outlc((val),(port)) : \
-	__outl((val),(port)))
-
-#define inl(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inlc(port) : \
-	__inl(port))
-
-#define outl_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outlc_p((val),(port)) : \
-	__outl_p((val),(port)))
-
-#define inl_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inlc_p(port) : \
-	__inl_p(port))
-
-
-#define outsb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outsbc((port),(addr),(count)) : \
-	__outsb ((port),(addr),(count)))
-
-#define insb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__insbc((port),(addr),(count)) : \
-	__insb((port),(addr),(count)))
-
-#define outsw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outswc((port),(addr),(count)) : \
-	__outsw ((port),(addr),(count)))
-
-#define insw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inswc((port),(addr),(count)) : \
-	__insw((port),(addr),(count)))
-
-#define outsl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outslc((port),(addr),(count)) : \
-	__outsl ((port),(addr),(count)))
-
-#define insl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inslc((port),(addr),(count)) : \
-	__insl((port),(addr),(count)))
+static inline unsigned short inw(unsigned long port)
+{
+	return __ioswab16(*(volatile u16 *)(mips_io_port_base + port));
+}
+
+static inline unsigned int inl(unsigned long port)
+{
+	return __ioswab32(*(volatile u32 *)(mips_io_port_base + port));
+}
+
+static inline unsigned char inb_p(unsigned long port)
+{
+	u8 __val;
+
+	__val = *(volatile u8 *)(mips_io_port_base + port);
+	SLOW_DOWN_IO;
+
+	return __ioswab8(__val);
+}
+
+static inline unsigned short inw_p(unsigned long port)
+{
+	u16 __val;
+
+	__val = *(volatile u16 *)(mips_io_port_base + port);
+	SLOW_DOWN_IO;
+
+	return __ioswab16(__val);
+}
+
+static inline unsigned int inl_p(unsigned long port)
+{
+	u32 __val;
+
+	__val = *(volatile u32 *)(mips_io_port_base + port);
+	SLOW_DOWN_IO;
+	return __ioswab32(__val);
+}
+
+static inline void outsb(unsigned long port, void *addr, unsigned int count)
+{
+	while (count--) {
+		outb(*(u8 *)addr, port);
+		addr++;
+	}
+}
+
+static inline void insb(unsigned long port, void *addr, unsigned int count)
+{
+	while (count--) {
+		*(u8 *)addr = inb(port);
+		addr++;
+	}
+}
+
+static inline void outsw(unsigned long port, void *addr, unsigned int count)
+{
+	while (count--) {
+		outw(*(u16 *)addr, port);
+		addr += 2;
+	}
+}
+
+static inline void insw(unsigned long port, void *addr, unsigned int count)
+{
+	while (count--) {
+		*(u16 *)addr = inw(port);
+		addr += 2;
+	}
+}
+
+static inline void outsl(unsigned long port, void *addr, unsigned int count)
+{
+	while (count--) {
+		outl(*(u32 *)addr, port);
+		addr += 4;
+	}
+}
+
+static inline void insl(unsigned long port, void *addr, unsigned int count)
+{
+	while (count--) {
+		*(u32 *)addr = inl(port);
+		addr += 4;
+	}
+}
 
 /*
  * The caches on some architectures aren't dma-coherent and have need to
Index: include/asm-mips64/irq.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/irq.h,v
retrieving revision 1.4
diff -u -r1.4 irq.h
--- include/asm-mips64/irq.h	2001/03/02 03:04:55	1.4
+++ include/asm-mips64/irq.h	2002/06/07 12:26:15
@@ -48,6 +48,12 @@
 extern void disable_irq(unsigned int);
 extern void enable_irq(unsigned int);
 
+#ifndef CONFIG_NEW_IRQ
+#define disable_irq_nosync      disable_irq
+#else
+extern void disable_irq_nosync(unsigned int);
+#endif
+
 /* Machine specific interrupt initialization  */
 extern void (*irq_setup)(void);
 
Index: include/asm-mips64/page.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/page.h,v
retrieving revision 1.10.2.6
diff -u -r1.10.2.6 page.h
--- include/asm-mips64/page.h	2002/01/24 23:14:28	1.10.2.6
+++ include/asm-mips64/page.h	2002/06/07 12:26:15
@@ -29,6 +29,10 @@
  */
 void sb1_clear_page(void * page);
 void sb1_copy_page(void * to, void * from);
+void mips64_clear_page_dc(unsigned long page);
+void mips64_clear_page_sc(unsigned long page);
+void mips64_copy_page_dc(unsigned long to, unsigned long from);
+void mips64_copy_page_sc(unsigned long to, unsigned long from);
 
 extern void (*_clear_page)(void * page);
 extern void (*_copy_page)(void * to, void * from);
@@ -94,8 +98,8 @@
 #define PAGE_OFFSET	0xa800000000000000UL
 #endif
 
-#define __pa(x)		((unsigned long) (x) - PAGE_OFFSET)
-#define __va(x)		((void *)((unsigned long) (x) + PAGE_OFFSET))
+#define __pa(x)		((unsigned long) (x) & ~PAGE_OFFSET)
+#define __va(x)		((void *)((unsigned long) (x) | PAGE_OFFSET))
 #ifndef CONFIG_DISCONTIGMEM
 #define virt_to_page(kaddr)	(mem_map + (__pa(kaddr) >> PAGE_SHIFT))
 #define VALID_PAGE(page)	((page - mem_map) < max_mapnr)
Index: include/asm-mips64/pci.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/pci.h,v
retrieving revision 1.16.2.2
diff -u -r1.16.2.2 pci.h
--- include/asm-mips64/pci.h	2002/02/26 06:00:25	1.16.2.2
+++ include/asm-mips64/pci.h	2002/06/07 12:26:15
@@ -173,7 +173,7 @@
 	dma_cache_wback_inv(addr, size);
 #endif
 
-	return virt_to_bus(addr);
+	return virt_to_bus((void *)addr);
 }
 
 static inline void pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address,
@@ -213,7 +213,7 @@
 #ifdef CONFIG_NONCOHERENT_IO
 		dma_cache_wback_inv((unsigned long)sg->address, sg->length);
 #endif
-		sg->dma_address = (char *)(__pa(sg->address));
+/*		sg->dma_address = (char *)(__pa(sg->address));*/
 	}
 
 	return nents;
@@ -250,7 +250,7 @@
 	if (direction == PCI_DMA_NONE)
 		BUG();
 #ifdef CONFIG_NONCOHERENT_IO
-	dma_cache_wback_inv((unsigned long)__va(dma_handle - bus_to_baddr[hwdev->bus->number]), size);
+	dma_cache_wback_inv((unsigned long)bus_to_virt(dma_handle), size);
 #endif
 }
 
@@ -287,7 +287,7 @@
 	 * so we can't guarantee allocations that must be
 	 * within a tighter range than GFP_DMA..
 	 */
-	if (mask < 0x00ffffff)
+	if (mask < 0x1fffffff)
 		return 0;
 
 	return 1;
@@ -339,7 +339,7 @@
  * returns, or alternatively stop on the first sg_dma_len(sg) which
  * is 0.
  */
-#define sg_dma_address(sg)	((unsigned long)((sg)->address))
+#define sg_dma_address(sg)	(virt_to_bus((sg)->address))
 #define sg_dma_len(sg)		((sg)->length)
 
 #endif /* __KERNEL__ */
Index: include/asm-mips64/pgtable.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/pgtable.h,v
retrieving revision 1.47.2.10
diff -u -r1.47.2.10 pgtable.h
--- include/asm-mips64/pgtable.h	2002/05/28 09:49:45	1.47.2.10
+++ include/asm-mips64/pgtable.h	2002/06/07 12:26:15
@@ -74,23 +74,13 @@
 
 #else
 
-extern void (*_flush_icache_all)(void);
-extern void (*_flush_icache_range)(unsigned long start, unsigned long end);
-extern void (*_flush_icache_page)(struct vm_area_struct *vma, struct page *page);
-
 #define flush_cache_mm(mm)		_flush_cache_mm(mm)
 #define flush_cache_range(mm,start,end)	_flush_cache_range(mm,start,end)
 #define flush_cache_page(vma,page)	_flush_cache_page(vma, page)
 #define flush_page_to_ram(page)		_flush_page_to_ram(page)
 #define flush_icache_range(start, end)	_flush_icache_range(start, end)
 #define flush_icache_page(vma, page)	_flush_icache_page(vma, page)
-#ifdef CONFIG_VTAG_ICACHE
-#define flush_icache_all()		_flush_icache_all()
-#else
-#define flush_icache_all()		do { } while(0)
-#endif
 
-
 #endif /* !CONFIG_CPU_R10000 */
 
 #define flush_cache_sigtramp(addr)	_flush_cache_sigtramp(addr)
@@ -198,11 +188,11 @@
 #ifdef CONFIG_MIPS_UNCACHED
 #define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED
 #else /* ! UNCACHED */
-#ifdef CONFIG_SGI_IP22
-#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
-#else /* ! IP22 */
+#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP32)
 #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
-#endif /* IP22 */
+#else
+#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
+#endif
 #endif /* UNCACHED */
 
 #define PAGE_NONE	__pgprot(_PAGE_PRESENT | PAGE_CACHABLE_DEFAULT)
@@ -569,6 +559,8 @@
 #ifndef CONFIG_DISCONTIGMEM
 #define kern_addr_valid(addr)	(1)
 #endif
+
+#define io_remap_page_range remap_page_range
 
 /*
  * No page table caches to initialise
Index: include/asm-mips64/serial.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/serial.h,v
retrieving revision 1.7.2.3
diff -u -r1.7.2.3 serial.h
--- include/asm-mips64/serial.h	2002/05/29 03:03:18	1.7.2.3
+++ include/asm-mips64/serial.h	2002/06/07 12:26:15
@@ -65,7 +65,6 @@
 /*
  * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
  */
-
 /* Standard COM flags (except for COM4, because of the 8514 problem) */
 #ifdef CONFIG_SERIAL_DETECT_IRQ
 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
@@ -88,13 +87,37 @@
           iomem_base: (u8*)MACE_BASE+MACEISA_SER2_BASE,	\
           iomem_reg_shift: 8,				\
           io_type: SERIAL_IO_MEM},                      
+
 #else
 #define IP32_SERIAL_PORT_DEFNS
 #endif /* CONFIG_SGI_IP31 */
 
+#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
+
+/* Standard COM flags (except for COM4, because of the 8514 problem) */
+#ifdef CONFIG_SERIAL_DETECT_IRQ
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
+#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
+#endif
+
+#define STD_SERIAL_PORT_DEFNS			\
+	/* UART CLK   PORT IRQ     FLAGS        */			\
+	{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },	/* ttyS0 */	\
+	{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },	/* ttyS1 */	\
+	{ 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },	/* ttyS2 */	\
+	{ 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },	/* ttyS3 */
+
+#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
+#define STD_SERIAL_PORT_DEFNS
+#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
+
 #define SERIAL_PORT_DFNS				\
 	IP27_SERIAL_PORT_DEFNS				\
-	IP32_SERIAL_PORT_DEFNS
+	IP32_SERIAL_PORT_DEFNS				\
+	STD_SERIAL_PORT_DEFNS
 
 #define RS_TABLE_SIZE	64
 
Index: include/asm-mips64/system.h
===================================================================
RCS file: /cvs/linux/include/asm-mips64/system.h,v
retrieving revision 1.18.2.7
diff -u -r1.18.2.7 system.h
--- include/asm-mips64/system.h	2002/05/28 05:53:06	1.18.2.7
+++ include/asm-mips64/system.h	2002/06/07 12:26:15
@@ -202,9 +202,9 @@
 
 extern asmlinkage void lazy_fpu_switch(void *, void *);
 extern asmlinkage void init_fpu(void);
-extern asmlinkage void save_fp(struct task_struct *);
-extern asmlinkage void restore_fp(struct task_struct *);
+extern asmlinkage void save_fp(void *);
+extern asmlinkage void restore_fp(void *);
 
 #ifdef CONFIG_SMP
 #define SWITCH_DO_LAZY_FPU \

--------------6A228B530B40164C0D9211A7
Content-Type: text/plain; charset=iso-8859-15;
 name="c-mips64.c"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="c-mips64.c"

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
 *
 * This program is free software; you can distribute it and/or modify it
 * under the terms of the GNU General Public License (Version 2) as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * MIPS64 CPU variant specific Cache routines.
 * These routine are not optimized in any way, they are done in a generic way
 * so they can be used on all MIPS64 compliant CPUs, and also done in an 
 * attempt not to break anything for the R4xx0 style CPUs.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>

#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/bcache.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/mmu_context.h>

/* CP0 hazard avoidance. */
#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
				     "nop; nop; nop; nop; nop; nop;\n\t" \
				     ".set reorder\n\t")

/* Primary cache parameters. */
int icache_size, dcache_size; /* Size in bytes */
int ic_lsize, dc_lsize;       /* LineSize in bytes */

/* Secondary cache (if present) parameters. */
unsigned int scache_size, sc_lsize;	/* Again, in bytes */

#include <asm/cacheops.h>
#include <asm/mips64_cache.h>

#undef DEBUG_CACHE

/*
 * Dummy cache handling routines for machines without boardcaches
 */
static void no_sc_noop(void) {}

static struct bcache_ops no_sc_ops = {
	(void *)no_sc_noop, (void *)no_sc_noop,
	(void *)no_sc_noop, (void *)no_sc_noop
};

struct bcache_ops *bcops = &no_sc_ops;


static inline void mips64_flush_cache_all_sc(void)
{
	unsigned long flags;

	__save_and_cli(flags);
	blast_dcache(); blast_icache(); blast_scache();
	__restore_flags(flags);
}

static inline void mips64_flush_cache_all_pc(void)
{
	unsigned long flags;

	__save_and_cli(flags);
	blast_dcache(); blast_icache();
	__restore_flags(flags);
}

static void
mips64_flush_cache_range_sc(struct mm_struct *mm,
			 unsigned long start,
			 unsigned long end)
{
	struct vm_area_struct *vma;
	unsigned long flags;

	if(mm->context == 0)
		return;

	start &= PAGE_MASK;
#ifdef DEBUG_CACHE
	printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
#endif
	vma = find_vma(mm, start);
	if(vma) {
		if(mm->context != current->mm->context) {
			mips64_flush_cache_all_sc();
		} else {
			pgd_t *pgd;
			pmd_t *pmd;
			pte_t *pte;

			__save_and_cli(flags);
			while(start < end) {
				pgd = pgd_offset(mm, start);
				pmd = pmd_offset(pgd, start);
				pte = pte_offset(pmd, start);

				if(pte_val(*pte) & _PAGE_VALID)
					blast_scache_page(start);
				start += PAGE_SIZE;
			}
			__restore_flags(flags);
		}
	}
}

static void mips64_flush_cache_range_pc(struct mm_struct *mm,
				     unsigned long start,
				     unsigned long end)
{
	if(mm->context != 0) {
		unsigned long flags;

#ifdef DEBUG_CACHE
		printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
#endif
		__save_and_cli(flags);
		blast_dcache(); blast_icache();
		__restore_flags(flags);
	}
}

/*
 * On architectures like the Sparc, we could get rid of lines in
 * the cache created only by a certain context, but on the MIPS
 * (and actually certain Sparc's) we cannot.
 */
static void mips64_flush_cache_mm_sc(struct mm_struct *mm)
{
	if(mm->context != 0) {
#ifdef DEBUG_CACHE
		printk("cmm[%d]", (int)mm->context);
#endif
		mips64_flush_cache_all_sc();
	}
}

static void mips64_flush_cache_mm_pc(struct mm_struct *mm)
{
	if(mm->context != 0) {
#ifdef DEBUG_CACHE
		printk("cmm[%d]", (int)mm->context);
#endif
		mips64_flush_cache_all_pc();
	}
}

static void mips64_flush_cache_page_sc(struct vm_area_struct *vma,
				    unsigned long page)
{
	struct mm_struct *mm = vma->vm_mm;
	unsigned long flags;
	pgd_t *pgdp;
	pmd_t *pmdp;
	pte_t *ptep;

	/*
	 * If ownes no valid ASID yet, cannot possibly have gotten
	 * this page into the cache.
	 */
	if (mm->context == 0)
		return;

#ifdef DEBUG_CACHE
	printk("cpage[%d,%08lx]", (int)mm->context, page);
#endif
	__save_and_cli(flags);
	page &= PAGE_MASK;
	pgdp = pgd_offset(mm, page);
	pmdp = pmd_offset(pgdp, page);
	ptep = pte_offset(pmdp, page);

	/*
	 * If the page isn't marked valid, the page cannot possibly be
	 * in the cache.
	 */
	if (!(pte_val(*ptep) & _PAGE_VALID))
		goto out;

	/*
	 * Doing flushes for another ASID than the current one is
	 * too difficult since R4k caches do a TLB translation
	 * for every cache flush operation.  So we do indexed flushes
	 * in that case, which doesn't overly flush the cache too much.
	 */
	if (mm->context != current->active_mm->context) {
		/*
		 * Do indexed flush, too much work to get the (possible)
		 * tlb refills to work correctly.
		 */
		page = (KSEG0 + (page & (scache_size - 1)));
		blast_dcache_page_indexed(page);
		blast_scache_page_indexed(page);
	} else
		blast_scache_page(page);
out:
	__restore_flags(flags);
}

static void mips64_flush_cache_page_pc(struct vm_area_struct *vma,
				    unsigned long page)
{
	struct mm_struct *mm = vma->vm_mm;
	unsigned long flags;
	pgd_t *pgdp;
	pmd_t *pmdp;
	pte_t *ptep;

	/*
	 * If ownes no valid ASID yet, cannot possibly have gotten
	 * this page into the cache.
	 */
	if (mm->context == 0)
		return;

#ifdef DEBUG_CACHE
	printk("cpage[%d,%08lx]", (int)mm->context, page);
#endif
	__save_and_cli(flags);
	page &= PAGE_MASK;
	pgdp = pgd_offset(mm, page);
	pmdp = pmd_offset(pgdp, page);
	ptep = pte_offset(pmdp, page);

	/*
	 * If the page isn't marked valid, the page cannot possibly be
	 * in the cache.
	 */
	if (!(pte_val(*ptep) & _PAGE_VALID))
		goto out;

	/*
	 * Doing flushes for another ASID than the current one is
	 * too difficult since Mips64 caches do a TLB translation
	 * for every cache flush operation.  So we do indexed flushes
	 * in that case, which doesn't overly flush the cache too much.
	 */
	if (mm == current->active_mm) {
		blast_dcache_page(page);
	} else {
		/* Do indexed flush, too much work to get the (possible)
		 * tlb refills to work correctly.
		 */
		page = (KSEG0 + (page & ((unsigned long)dcache_size - 1)));
		blast_dcache_page_indexed(page);
	}
out:
	__restore_flags(flags);
}

/* If the addresses passed to these routines are valid, they are
 * either:
 *
 * 1) In KSEG0, so we can do a direct flush of the page.
 * 2) In KSEG2, and since every process can translate those
 *    addresses all the time in kernel mode we can do a direct
 *    flush.
 * 3) In KSEG1, no flush necessary.
 */
static void mips64_flush_page_to_ram_sc(struct page *page)
{
	blast_scache_page((unsigned long)page_address(page));
}

static void mips64_flush_page_to_ram_pc(struct page *page)
{
	blast_dcache_page((unsigned long)page_address(page));
}

static void
mips64_flush_icache_page_s(struct vm_area_struct *vma, struct page *page)
{
	/*
	 * We did an scache flush therefore PI is already clean.
	 */
}

static void
mips64_flush_icache_range(unsigned long start, unsigned long end)
{
	flush_cache_all();
}

static void
mips64_flush_icache_page(struct vm_area_struct *vma, struct page *page)
{
	unsigned long address;

	if (!(vma->vm_flags & VM_EXEC))
		return;

	address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & ((unsigned long)dcache_size - 1));
	blast_icache_page_indexed(address);
}

/*
 * Writeback and invalidate the primary cache dcache before DMA.
 */
static void
mips64_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size)
{
	unsigned long end, a;
	unsigned int flags;

	if (size >= (unsigned long)dcache_size) {
		flush_cache_all();
	} else {
	        __save_and_cli(flags);
		a = addr & ~(dc_lsize - 1);
		end = (addr + size) & ~((unsigned long)dc_lsize - 1);
		while (1) {
			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
			if (a == end) break;
			a += dc_lsize;
		}
		__restore_flags(flags);
	}
	bc_wback_inv(addr, size);
}

static void
mips64_dma_cache_wback_inv_sc(unsigned long addr, unsigned long size)
{
	unsigned long end, a;

	if (size >= scache_size) {
		flush_cache_all();
		return;
	}

	a = addr & ~(sc_lsize - 1);
	end = (addr + size) & ~(sc_lsize - 1);
	while (1) {
		flush_scache_line(a);	/* Hit_Writeback_Inv_SD */
		if (a == end) break;
		a += sc_lsize;
	}
}

static void
mips64_dma_cache_inv_pc(unsigned long addr, unsigned long size)
{
	unsigned long end, a;
	unsigned int flags;

	if (size >= (unsigned long)dcache_size) {
		flush_cache_all();
	} else {
	        __save_and_cli(flags);
		a = addr & ~((unsigned long)dc_lsize - 1);
		end = (addr + size) & ~((unsigned long)dc_lsize - 1);
		while (1) {
			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
			if (a == end) break;
			a += (unsigned long)dc_lsize;
		}
		__restore_flags(flags);
	}

	bc_inv(addr, size);
}

static void
mips64_dma_cache_inv_sc(unsigned long addr, unsigned long size)
{
	unsigned long end, a;

	if (size >= scache_size) {
		flush_cache_all();
		return;
	}

	a = addr & ~(sc_lsize - 1);
	end = (addr + size) & ~(sc_lsize - 1);
	while (1) {
		flush_scache_line(a); /* Hit_Writeback_Inv_SD */
		if (a == end) break;
		a += sc_lsize;
	}
}

static void
mips64_dma_cache_wback(unsigned long addr, unsigned long size)
{
	panic("mips64_dma_cache called - should not happen.\n");
}

/*
 * While we're protected against bad userland addresses we don't care
 * very much about what happens in that case.  Usually a segmentation
 * fault will dump the process later on anyway ...
 */
static void mips64_flush_cache_sigtramp(unsigned long addr)
{
	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
	protected_flush_icache_line(addr & ~(ic_lsize - 1));
}

static void
mips64_flush_icache_all(void)
{
	if (mips_cpu.cputype == CPU_20KC) {
		blast_icache();
	}
}


/* Detect and size the various caches. */
static void __init probe_icache(unsigned long config)
{
        unsigned long config1;
	unsigned int lsize;

        if (!(config & (1 << 31))) {
	        /* 
		 * Not a MIPS64 complainant CPU. 
		 * Config 1 register not supported, we assume R4k style.
		 */
	        icache_size = 1 << (12 + ((config >> 9) & 7));
		ic_lsize = 16 << ((config >> 5) & 1);
		mips_cpu.icache.linesz = ic_lsize;
		
		/* 
		 * We cannot infer associativity - assume direct map
		 * unless probe template indicates otherwise
		 */
		if(!mips_cpu.icache.ways) mips_cpu.icache.ways = 1;
		mips_cpu.icache.sets = 
			(icache_size / ic_lsize) / mips_cpu.icache.ways;
	} else {
	       config1 = read_mips32_cp0_config1(); 

	       if ((lsize = ((config1 >> 19) & 7)))
		       mips_cpu.icache.linesz = 2 << lsize;
	       else 
		       mips_cpu.icache.linesz = lsize;
	       mips_cpu.icache.sets = 64 << ((config1 >> 22) & 7);
	       mips_cpu.icache.ways = 1 + ((config1 >> 16) & 7);

	       ic_lsize = mips_cpu.icache.linesz;
	       icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways * 
		             ic_lsize;
	}
	printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n",
	       icache_size >> 10, ic_lsize, mips_cpu.icache.ways);
}

static void __init probe_dcache(unsigned long config)
{
        unsigned long config1;
	unsigned int lsize;

        if (!(config & (1 << 31))) {
	        /* 
		 * Not a MIPS64 complainant CPU. 
		 * Config 1 register not supported, we assume R4k style.
		 */  
		dcache_size = 1 << (12 + ((config >> 6) & 7));
		dc_lsize = 16 << ((config >> 4) & 1);
		mips_cpu.dcache.linesz = dc_lsize;
		/* 
		 * We cannot infer associativity - assume direct map
		 * unless probe template indicates otherwise
		 */
		if(!mips_cpu.dcache.ways) mips_cpu.dcache.ways = 1;
		mips_cpu.dcache.sets = 
			(dcache_size / dc_lsize) / mips_cpu.dcache.ways;
	} else {
	        config1 = read_mips32_cp0_config1();

		if ((lsize = ((config1 >> 10) & 7)))
		        mips_cpu.dcache.linesz = 2 << lsize;
		else 
		        mips_cpu.dcache.linesz= lsize;
		mips_cpu.dcache.sets = 64 << ((config1 >> 13) & 7);
		mips_cpu.dcache.ways = 1 + ((config1 >> 7) & 7);

		dc_lsize = mips_cpu.dcache.linesz;
		dcache_size = 
			mips_cpu.dcache.sets * mips_cpu.dcache.ways
			* dc_lsize;
	}
	printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n",
	       dcache_size >> 10, dc_lsize, mips_cpu.dcache.ways);
}


/* If you even _breathe_ on this function, look at the gcc output
 * and make sure it does not pop things on and off the stack for
 * the cache sizing loop that executes in KSEG1 space or else
 * you will crash and burn badly.  You have been warned.
 */
static int __init probe_scache(unsigned long config)
{
	extern unsigned long stext;
	unsigned long flags, addr, begin, end, pow2;
	int tmp;

	if (mips_cpu.scache.flags == MIPS_CACHE_NOT_PRESENT)
		return 0;

	tmp = ((config >> 17) & 1);
	if(tmp)
		return 0;
	tmp = ((config >> 22) & 3);
	switch(tmp) {
	case 0:
		sc_lsize = 16;
		break;
	case 1:
		sc_lsize = 32;
		break;
	case 2:
		sc_lsize = 64;
		break;
	case 3:
		sc_lsize = 128;
		break;
	}

	begin = (unsigned long) &stext;
	begin &= ~((4 * 1024 * 1024) - 1);
	end = begin + (4 * 1024 * 1024);

	/* This is such a bitch, you'd think they would make it
	 * easy to do this.  Away you daemons of stupidity!
	 */
	__save_and_cli(flags);

	/* Fill each size-multiple cache line with a valid tag. */
	pow2 = (64 * 1024);
	for(addr = begin; addr < end; addr = (begin + pow2)) {
		unsigned long *p = (unsigned long *) addr;
		__asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
		pow2 <<= 1;
	}

	/* Load first line with zero (therefore invalid) tag. */
	set_taglo(0);
	set_taghi(0);
	__asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
	__asm__ __volatile__("\n\t.set noreorder\n\t"
			     "cache 8, (%0)\n\t"
			     ".set reorder\n\t" : : "r" (begin));
	__asm__ __volatile__("\n\t.set noreorder\n\t"
			     "cache 9, (%0)\n\t"
			     ".set reorder\n\t" : : "r" (begin));
	__asm__ __volatile__("\n\t.set noreorder\n\t"
			     "cache 11, (%0)\n\t"
			     ".set reorder\n\t" : : "r" (begin));

	/* Now search for the wrap around point. */
	pow2 = (128 * 1024);
	tmp = 0;
	for(addr = (begin + (128 * 1024)); addr < (end); addr = (begin + pow2)) {
		__asm__ __volatile__("\n\t.set noreorder\n\t"
				     "cache 7, (%0)\n\t"
				     ".set reorder\n\t" : : "r" (addr));
		__asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
		if(!get_taglo())
			break;
		pow2 <<= 1;
	}
	__restore_flags(flags);
	addr -= begin;
	printk("Secondary cache sized at %dK linesize %d bytes.\n",
	       (int) (addr >> 10), sc_lsize);
	scache_size = addr;
	return 1;
}

static void __init setup_noscache_funcs(void)
{
	_clear_page = (void *)mips64_clear_page_dc;
	_copy_page = (void *)mips64_copy_page_dc;
	_flush_cache_all = mips64_flush_cache_all_pc;
	___flush_cache_all = mips64_flush_cache_all_pc;
	_flush_cache_mm = mips64_flush_cache_mm_pc;
	_flush_cache_range = mips64_flush_cache_range_pc;
	_flush_cache_page = mips64_flush_cache_page_pc;
	_flush_page_to_ram = mips64_flush_page_to_ram_pc;

	_flush_icache_page = mips64_flush_icache_page;

	_dma_cache_wback_inv = mips64_dma_cache_wback_inv_pc;
	_dma_cache_wback = mips64_dma_cache_wback;
	_dma_cache_inv = mips64_dma_cache_inv_pc;
}

static void __init setup_scache_funcs(void)
{
        _flush_cache_all = mips64_flush_cache_all_sc;
        ___flush_cache_all = mips64_flush_cache_all_sc;
	_flush_cache_mm = mips64_flush_cache_mm_sc;
	_flush_cache_range = mips64_flush_cache_range_sc;
	_flush_cache_page = mips64_flush_cache_page_sc;
	_flush_page_to_ram = mips64_flush_page_to_ram_sc;
	_clear_page = (void *)mips64_clear_page_sc;
	_copy_page = (void *)mips64_copy_page_sc;

	_flush_icache_page = mips64_flush_icache_page_s;

	_dma_cache_wback_inv = mips64_dma_cache_wback_inv_sc;
	_dma_cache_wback = mips64_dma_cache_wback;
	_dma_cache_inv = mips64_dma_cache_inv_sc;
}

typedef int (*probe_func_t)(unsigned long);

static inline void __init setup_scache(unsigned int config)
{
	probe_func_t probe_scache_kseg1;
	int sc_present = 0;

	/* Maybe the cpu knows about a l2 cache? */
	probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
	sc_present = probe_scache_kseg1(config);

	if (sc_present) {
	  	mips_cpu.scache.linesz = sc_lsize;
		/* 
		 * We cannot infer associativity - assume direct map
		 * unless probe template indicates otherwise
		 */
		if(!mips_cpu.scache.ways) mips_cpu.scache.ways = 1;
		mips_cpu.scache.sets = 
		  (scache_size / sc_lsize) / mips_cpu.scache.ways;

		setup_scache_funcs();
		return;
	}

	setup_noscache_funcs();
}

void __init ld_mmu_mips64(void)
{
	unsigned long config = read_32bit_cp0_register(CP0_CONFIG);

#ifdef CONFIG_MIPS_UNCACHED
	change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
#else
	change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
#endif

	probe_icache(config);
	probe_dcache(config);
	setup_scache(config);

	_flush_cache_sigtramp = mips64_flush_cache_sigtramp;
	_flush_icache_range = mips64_flush_icache_range;	/* Ouch */
	_flush_icache_all = mips64_flush_icache_all;
	_flush_cache_l1 = _flush_cache_all;
	_flush_cache_l2 = _flush_cache_all;

	__flush_cache_all();
}

--------------6A228B530B40164C0D9211A7
Content-Type: text/plain; charset=iso-8859-15;
 name="pg-mips64.c"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="pg-mips64.c"

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
 *
 * This program is free software; you can distribute it and/or modify it
 * under the terms of the GNU General Public License (Version 2) as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * MIPS64 CPU variant specific Cache routines.
 * These routine are not optimized in any way, they are done in a generic way
 * so they can be used on all MIPS64 compliant CPUs, and also done in an 
 * attempt not to break anything for the R4xx0 style CPUs.
 */
#include <linux/sched.h>
#include <linux/mm.h>

#include <asm/bootinfo.h>
#include <asm/cacheops.h>
#include <asm/cpu.h>

extern int dc_lsize, ic_lsize, sc_lsize;

/*
 * Zero an entire page.
 */

void mips64_clear_page_dc(unsigned long page)
{
	unsigned long i;

        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX)
	{
	        for (i=page; i<page+PAGE_SIZE; i+=dc_lsize)
		{
		        __asm__ __volatile__(
			        ".set\tnoreorder\n\t"
				".set\tnoat\n\t"
				"cache\t%2,(%0)\n\t"
				".set\tat\n\t"
				".set\treorder"
				:"=r" (i)
				:"0" (i),
				"I" (Create_Dirty_Excl_D));
		}
	}
	for (i=page; i<page+PAGE_SIZE; i+=sizeof(long))
	        *(unsigned long *)(i) = 0;
}

void mips64_clear_page_sc(unsigned long page)
{
	unsigned long i;

        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX)
	{
	        for (i=page; i<page+PAGE_SIZE; i+=sc_lsize)
		{
		        __asm__ __volatile__(
				".set\tnoreorder\n\t"
				".set\tnoat\n\t"
				"cache\t%2,(%0)\n\t"
				".set\tat\n\t"
				".set\treorder"
				:"=r" (i)
				:"0" (i),
				"I" (Create_Dirty_Excl_SD));
		}
	}
	for (i=page; i<page+PAGE_SIZE; i+=sizeof(long))
	        *(unsigned long *)(i) = 0;
}

void mips64_copy_page_dc(unsigned long to, unsigned long from)
{
	unsigned long i;

        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX)
	{
	        for (i=to; i<to+PAGE_SIZE; i+=dc_lsize)
		{
		        __asm__ __volatile__(
			        ".set\tnoreorder\n\t"
				".set\tnoat\n\t"
				"cache\t%2,(%0)\n\t"
				".set\tat\n\t"
				".set\treorder"
				:"=r" (i)
				:"0" (i),
				"I" (Create_Dirty_Excl_D));
		}
	}
	for (i=0; i<PAGE_SIZE; i+=sizeof(long))
	        *(unsigned long *)(to+i) = *(unsigned long *)(from+i);
}

void mips64_copy_page_sc(unsigned long to, unsigned long from)
{
	unsigned long i;

        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX)
	{
	        for (i=to; i<to+PAGE_SIZE; i+=sc_lsize)
		{
		        __asm__ __volatile__(
				".set\tnoreorder\n\t"
				".set\tnoat\n\t"
				"cache\t%2,(%0)\n\t"
				".set\tat\n\t"
				".set\treorder"
				:"=r" (i)
				:"0" (i),
				"I" (Create_Dirty_Excl_SD));
		}
	}
	for (i=0; i<PAGE_SIZE; i+=sizeof(long))
	        *(unsigned long *)(to+i) = *(unsigned long *)(from+i);
}

--------------6A228B530B40164C0D9211A7
Content-Type: text/plain; charset=iso-8859-15;
 name="tlb-r4k.c"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="tlb-r4k.c"

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
 *
 * This program is free software; you can distribute it and/or modify it
 * under the terms of the GNU General Public License (Version 2) as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * MIPS64 CPU variant specific MMU routines.
 * These routine are not optimized in any way, they are done in a generic way
 * so they can be used on all MIPS64 compliant CPUs, and also done in an 
 * attempt not to break anything for the R4xx0 style CPUs.
 */
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/mm.h>

#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/system.h>

#undef DEBUG_TLB
#undef DEBUG_TLBUPDATE

/*extern char except_vec1_r4k;*/

/* CP0 hazard avoidance. */
#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
				     "nop; nop; nop; nop; nop; nop;\n\t" \
				     ".set reorder\n\t")

void local_flush_tlb_all(void)
{
	unsigned long flags;
	unsigned long old_ctx;
	int entry;

#ifdef DEBUG_TLB
	printk("[tlball]");
#endif

	__save_and_cli(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = (get_entryhi() & 0xff);
	set_entryhi(KSEG0);
	set_entrylo0(0);
	set_entrylo1(0);
	BARRIER;

	entry = get_wired();

	/* Blast 'em all away. */
	while(entry < mips_cpu.tlbsize) {
	        /* Make sure all entries differ. */  
	        set_entryhi(KSEG0+entry*0x2000);
		set_index(entry);
		BARRIER;
		tlb_write_indexed();
		BARRIER;
		entry++;
	}
	BARRIER;
	set_entryhi(old_ctx);
	__restore_flags(flags);
}

void local_flush_tlb_mm(struct mm_struct *mm)
{
	if (CPU_CONTEXT(smp_processor_id(), mm) != 0) {
		unsigned long flags;

#ifdef DEBUG_TLB
		printk("[tlbmm<%d>]", mm->context);
#endif
		__save_and_cli(flags);
		get_new_mmu_context(mm, smp_processor_id());
		if (mm == current->active_mm)
			set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & 
				    0xff);
		__restore_flags(flags);
	}
}

void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
				unsigned long end)
{
	if (CPU_CONTEXT(smp_processor_id(), mm) != 0) {
		unsigned long flags;
		int size;

#ifdef DEBUG_TLB
		printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff),
		       start, end);
#endif
		__save_and_cli(flags);
		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
		size = (size + 1) >> 1;
		if(size <= mips_cpu.tlbsize/2) {
			int oldpid = (get_entryhi() & 0xff);
			int newpid = (CPU_CONTEXT(smp_processor_id(), mm) & 
				      0xff);

			start &= (PAGE_MASK << 1);
			end += ((PAGE_SIZE << 1) - 1);
			end &= (PAGE_MASK << 1);
			while(start < end) {
				int idx;

				set_entryhi(start | newpid);
				start += (PAGE_SIZE << 1);
				BARRIER;
				tlb_probe();
				BARRIER;
				idx = get_index();
				set_entrylo0(0);
				set_entrylo1(0);
				if(idx < 0)
					continue;
				/* Make sure all entries differ. */
				set_entryhi(KSEG0+idx*0x2000);
				BARRIER;
				tlb_write_indexed();
				BARRIER;
			}
			set_entryhi(oldpid);
		} else {
			get_new_mmu_context(mm, smp_processor_id());
			if (mm == current->active_mm)
				set_entryhi(CPU_CONTEXT(smp_processor_id(), 
							mm) & 0xff);
		}
		__restore_flags(flags);
	}
}

void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
	if (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) != 0) {
		unsigned long flags;
		unsigned long oldpid, newpid, idx;

#ifdef DEBUG_TLB
		printk("[tlbpage<%d,%08lx>]", vma->vm_mm->context, page);
#endif
		newpid = (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff);
		page &= (PAGE_MASK << 1);
		__save_and_cli(flags);
		oldpid = (get_entryhi() & 0xff);
		set_entryhi(page | newpid);
		BARRIER;
		tlb_probe();
		BARRIER;
		idx = get_index();
		set_entrylo0(0);
		set_entrylo1(0);
		if(idx < 0)
			goto finish;
		/* Make sure all entries differ. */  
		set_entryhi(KSEG0+idx*0x2000);
		BARRIER;
		tlb_write_indexed();
	finish:
		BARRIER;
		set_entryhi(oldpid);
		__restore_flags(flags);
	}
}

/* 
 * Updates the TLB with the new pte(s).
 */
void mips64_update_mmu_cache(struct vm_area_struct * vma,
		      unsigned long address, pte_t pte)
{
	unsigned long flags;
	pgd_t *pgdp;
	pmd_t *pmdp;
	pte_t *ptep;
	int idx, pid;

	/*
	 * Handle debugger faulting in for debugee.
	 */
	if (current->active_mm != vma->vm_mm)
		return;

	pid = get_entryhi() & 0xff;

#ifdef DEBUG_TLB
	if((pid != (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff)) ||
	   (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) == 0)) {
		printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d
			tlbpid=%d\n", (int) (CPU_CONTEXT(smp_processor_id(),
			vma->vm_mm) & 0xff), pid);
	}
#endif

	__save_and_cli(flags);
	address &= (PAGE_MASK << 1);
	set_entryhi(address | (pid));
	pgdp = pgd_offset(vma->vm_mm, address);
	BARRIER;
	tlb_probe();
	BARRIER;
	pmdp = pmd_offset(pgdp, address);
	idx = get_index();
	ptep = pte_offset(pmdp, address);
	BARRIER;
	set_entrylo0(pte_val(*ptep++) >> 6);
	set_entrylo1(pte_val(*ptep) >> 6);
	set_entryhi(address | (pid));
	BARRIER;
	if(idx < 0) {
		tlb_write_random();
	} else {
		tlb_write_indexed();
	}
	BARRIER;
	set_entryhi(pid);
	BARRIER;
	__restore_flags(flags);
}

void dump_mm_page(unsigned long addr)
{
	pgd_t	*page_dir, *pgd;
	pmd_t	*pmd;
	pte_t	*pte, page;
	unsigned long val;

	page_dir = pgd_offset(current->mm, 0);
	pgd = pgd_offset(current->mm, addr);
	pmd = pmd_offset(pgd, addr);
	pte = pte_offset(pmd, addr);
	page = *pte;
	printk("Memory Mapping: VA = %08x, PA = %08x ", addr, (unsigned int) pte_val(page));
	val = pte_val(page);
	if (val & _PAGE_PRESENT) printk("present ");
	if (val & _PAGE_READ) printk("read ");
	if (val & _PAGE_WRITE) printk("write ");
	if (val & _PAGE_ACCESSED) printk("accessed ");
	if (val & _PAGE_MODIFIED) printk("modified ");
	if (val & _PAGE_R4KBUG) printk("r4kbug ");
	if (val & _PAGE_GLOBAL) printk("global ");
	if (val & _PAGE_VALID) printk("valid ");
	printk("\n");
}

void show_tlb(void)
{
        unsigned int flags;
        unsigned int old_ctx;
	unsigned int entry;
	unsigned int entrylo0, entrylo1, entryhi;

	__save_and_cli(flags);

	/* Save old context */
	old_ctx = (get_entryhi() & 0xff);

	printk("TLB content:\n");
	entry = 0;
	while(entry < mips_cpu.tlbsize) {
		set_index(entry);
		BARRIER;
		tlb_read();
		BARRIER;
		entryhi = get_entryhi();
		entrylo0 = get_entrylo0();
		entrylo1 = get_entrylo1();
		printk("%02d: ASID=%02d%s VA=0x%08x ", entry, entryhi & ASID_MASK, (entrylo0 & entrylo1 & 1) ? "(G)" : "   ", entryhi & ~ASID_MASK);
		printk("PA0=0x%08x C0=%x %s%s%s\n", (entrylo0>>6)<<12, (entrylo0>>3) & 7, (entrylo0 & 4) ? "Dirty " : "", (entrylo0 & 2) ? "Valid " : "Invalid ", (entrylo0 & 1) ? "Global" : ""); 
		printk("\t\t\t     PA1=0x%08x C1=%x %s%s%s\n", (entrylo1>>6)<<12, (entrylo1>>3) & 7, (entrylo1 & 4) ? "Dirty " : "", (entrylo1 & 2) ? "Valid " : "Invalid ", (entrylo1 & 1) ? "Global" : ""); 

		dump_mm_page(entryhi & ~0xff);
		dump_mm_page((entryhi & ~0xff) | 0x1000);
		entry++;
	}
	BARRIER;
	set_entryhi(old_ctx);

	__restore_flags(flags);
}

void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
				      unsigned long entryhi, unsigned long pagemask)
{
        unsigned long flags;
        unsigned long wired;
        unsigned long old_pagemask;
        unsigned long old_ctx;

        __save_and_cli(flags);
        /* Save old context and create impossible VPN2 value */
        old_ctx = (get_entryhi() & 0xff);
        old_pagemask = get_pagemask();
        wired = get_wired();
        set_wired (wired + 1);
        set_index (wired);
        BARRIER;    
        set_pagemask (pagemask);
        set_entryhi(entryhi);
        set_entrylo0(entrylo0);
        set_entrylo1(entrylo1);
        BARRIER;    
        tlb_write_indexed();
        BARRIER;    
    
        set_entryhi(old_ctx);
        BARRIER;    
        set_pagemask (old_pagemask);
        local_flush_tlb_all();    
        __restore_flags(flags);
}

/*
 * Used for loading TLB entries before trap_init() has started, when we
 * don't actually want to add a wired entry which remains throughout the
 * lifetime of the system
 */

static int temp_tlb_entry __initdata;

__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
			       unsigned long entryhi, unsigned long pagemask)
{
	int ret = 0;
	unsigned long flags;
	unsigned long wired;
	unsigned long old_pagemask;
	unsigned long old_ctx;

	__save_and_cli(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = get_entryhi() & 0xff;
	old_pagemask = get_pagemask();
	wired = get_wired();
	if (--temp_tlb_entry < wired) {
		printk(KERN_WARNING "No TLB space left for add_temporary_entry\n");
		ret = -ENOSPC;
		goto out;
	}

	set_index(temp_tlb_entry);
	BARRIER;    
	set_pagemask(pagemask);
	set_entryhi(entryhi);
	set_entrylo0(entrylo0);
	set_entrylo1(entrylo1);
	BARRIER;    
	tlb_write_indexed();
	BARRIER;    
    
	set_entryhi(old_ctx);
	BARRIER;    
	set_pagemask(old_pagemask);
out:
	__restore_flags(flags);
	return ret;
}

static void __init probe_tlb(unsigned long config)
{
        unsigned long config1;

        if (!(config & (1 << 31))) {
	        /* 
		 * Not a MIPS64 complainant CPU. 
		 * Config 1 register not supported, we assume R4k style.
		 */  
	        mips_cpu.tlbsize = 48;
	} else {
	        config1 = read_mips32_cp0_config1();
		if (!((config >> 7) & 3))
		        panic("No MMU present");
		else
		        mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1;
	}	

	printk("Number of TLB entries %d.\n", mips_cpu.tlbsize);
}

void __init r4k_tlb_init(void)
{
	unsigned long config = read_32bit_cp0_register(CP0_CONFIG);

	probe_tlb(config);
	_update_mmu_cache = mips64_update_mmu_cache;
	set_pagemask(PM_4K);
	write_32bit_cp0_register(CP0_WIRED, 0);
	temp_tlb_entry = mips_cpu.tlbsize - 1;
	local_flush_tlb_all();

/*	memcpy((void *)(KSEG0 + 0x80), &except_vec1_r4k, 0x80);*/
	flush_icache_range(KSEG0, KSEG0 + 0x80);
}

--------------6A228B530B40164C0D9211A7
Content-Type: text/plain; charset=iso-8859-15;
 name="mips64_cache.h"
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/*
 * mips64_cache.h
 *
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 *
 * Inline assembly cache operations.
 * 
 * This file is the original r4cache.c file with modification that makes the
 * cache handling more generic.
 *
 * FIXME: Handle split L2 caches.
 *
 */
#ifndef _MIPS_MIPS64_CACHE_H
#define _MIPS_MIPS64_CACHE_H

#include <asm/asm.h>
#include <asm/cacheops.h>

static inline void flush_icache_line_indexed(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"cache %1, (%0)\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Index_Invalidate_I));
}

static inline void flush_dcache_line_indexed(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"cache %1, (%0)\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Index_Writeback_Inv_D));
}

static inline void flush_scache_line_indexed(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"cache %1, (%0)\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Index_Writeback_Inv_SD));
}

static inline void flush_icache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"cache %1, (%0)\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Hit_Invalidate_I));
}

static inline void flush_dcache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"cache %1, (%0)\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Hit_Writeback_Inv_D));
}

static inline void invalidate_dcache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"cache %1, (%0)\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Hit_Invalidate_D));
}

static inline void invalidate_scache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"cache %1, (%0)\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Hit_Invalidate_SD));
}

static inline void flush_scache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"cache %1, (%0)\n\t"
		".set reorder"
		:
		: "r" (addr),
		  "i" (Hit_Writeback_Inv_SD));
}

/*
 * The next two are for badland addresses like signal trampolines.
 */
static inline void protected_flush_icache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"1:\tcache %1,(%0)\n"
		"2:\t.set reorder\n\t"
		".section\t__ex_table,\"a\"\n\t"
		".dword\t1b,2b\n\t"
		".previous"
		:
		: "r" (addr), "i" (Hit_Invalidate_I));
}

static inline void protected_writeback_dcache_line(unsigned long addr)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"1:\tcache %1,(%0)\n"
		"2:\t.set reorder\n\t"
		".section\t__ex_table,\"a\"\n\t"
		".dword\t1b,2b\n\t"
		".previous"
		:
		: "r" (addr), "i" (Hit_Writeback_D));
}

#define cache_unroll(base,op)			\
	__asm__ __volatile__("			\
		.set noreorder;			\
		cache %1, (%0);			\
		.set reorder"			\
		:				\
		: "r" (base),			\
		  "i" (op));


static inline void blast_dcache(void)
{
	unsigned long start = KSEG0;
	unsigned long end = (start + dcache_size);

	while(start < end) {
		cache_unroll(start,Index_Writeback_Inv_D);
		start += dc_lsize;
	}
}

static inline void blast_dcache_page(unsigned long page)
{
	unsigned long start = page;
	unsigned long end = (start + PAGE_SIZE);

	while(start < end) {
		cache_unroll(start,Hit_Writeback_Inv_D);
		start += dc_lsize;
	}
}

static inline void blast_dcache_page_indexed(unsigned long page)
{
	unsigned long start = page;
	unsigned long end = (start + PAGE_SIZE);

	while(start < end) {
		cache_unroll(start,Index_Writeback_Inv_D);
		start += dc_lsize;
	}
}

static inline void blast_icache(void)
{
	unsigned long start = KSEG0;
	unsigned long end = (start + icache_size);

	while(start < end) {
		cache_unroll(start,Index_Invalidate_I);
		start += ic_lsize;
	}
}

static inline void blast_icache_page(unsigned long page)
{
	unsigned long start = page;
	unsigned long end = (start + PAGE_SIZE);

	while(start < end) {
		cache_unroll(start,Hit_Invalidate_I);
		start += ic_lsize;
	}
}

static inline void blast_icache_page_indexed(unsigned long page)
{
	unsigned long start = page;
	unsigned long end = (start + PAGE_SIZE);

	while(start < end) {
		cache_unroll(start,Index_Invalidate_I);
		start += ic_lsize;
	}
}

static inline void blast_scache(void)
{
	unsigned long start = KSEG0;
	unsigned long end = KSEG0 + scache_size;

	while(start < end) {
		cache_unroll(start,Index_Writeback_Inv_SD);
		start += sc_lsize;
	}
}

static inline void blast_scache_page(unsigned long page)
{
	unsigned long start = page;
	unsigned long end = page + PAGE_SIZE;

	while(start < end) {
		cache_unroll(start,Hit_Writeback_Inv_SD);
		start += sc_lsize;
	}
}

static inline void blast_scache_page_indexed(unsigned long page)
{
	unsigned long start = page;
	unsigned long end = page + PAGE_SIZE;

	while(start < end) {
		cache_unroll(start,Index_Writeback_Inv_SD);
		start += sc_lsize;
	}
}

#endif /* !(_MIPS_MIPS64_CACHE_H) */



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From owner-linux-mips@oss.sgi.com Mon Jun 10 04:58:45 2002
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Subject: Re: R10K speculative store on non-coherent systems workaround
	proposal
From: Ralf Baechle <ralf@uni-koblenz.de>
To: Vivien Chappelier <vivien.chappelier@enst-bretagne.fr>
Cc: linux-mips@oss.sgi.com
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On Sat, 2002-06-08 at 00:15, Vivien Chappelier wrote:

> 	Here is a proposal for a software workaround to speculative
> execution on a non-coherent system such as the i2 R10k and the o2 R10k.
> 
> 1. Problem:
> ===========
> 
> 	The R10000 processor can (and will) execute intructions ahead.
> These instructions will be cancelled if they're not supposed to execute,
> e.g. if a jump happened. If a load or store instruction is executed
> speculatively, and the accessed memory is not in the cache, the cache
> line will be fetched in main memory and, on a store, be marked dirty.
> These speculative loads and stores can happen anywhere, since there might
> be old values in registers used in a speculative load/store
> instruction that would be cancelled afterwards.
> 
> The problem is:
> 	- on a speculative load, the fetched cache line will remain in the
> cache even if the speculative load is cancelled
> 	- on a speculative store, the *dirty* cache line will remain in
> the cache even if the speculative store is cancelled
> 
> 	On non-coherent systems we need to flush the cache lines to main
> memory before doing DMA to device, so that the device can see them. We
> also need to invalidate lines before reading from a DMA'd buffer to make
> sure the CPU will read main memory and not the cache.
> 	However, if a speculative load or store happens during DMA
> transfer, the cache line will be fetched from memory and, on a store, 
> be marked dirty. That means this cache line could be evicted when the
> line is needed, thus being written back in memory if it was dirty,
> thus overwritting the data a device could have put in the DMA
> buffer. Something we really don't want to happen ;)
> 
> 2. Proposed solution
> ====================
> 
> 	Speculative execution will not happen in the following conditions:
> 		- access to memory is uncached
> 		- the speculated instruction causes an exception: that
> also means a speculative load/store will not happen in a mapped memory
> region which doesn't have a TLB line for it.
> 
> 	This second point means that any mapped space can be made safe by
> removing the DMA'd buffer address translations from the TLB or by marking
> them 'uncached' during DMA transfer.
> 	The remaining unmapped adress spaces are:
> 		- kseg1, which is safe since uncached
> 		- kseg0, which can turned uncached with the K0 bits
> from the CPO Config register
> 		- xkphys which will cause adress error if the KX bit is
> not set, the aborting the speculative load/store before it can do harm ;)
> 
> 	Since we need to turn KX off, xkseg will not be accessible
> either.. and since we need to have KSEG0 uncached, we need to remap the
> kernel elsewhere if we want performance ;). We could use the xsseg
> segment, available in Supervisor mode, which is mapped (safe) and moreover
> allows to access all memory (on o2 it can be up to 2G I think, whereas in
> 32bit mode, only 512Mb would be accessible). So the proposed workaround is
> to permanently map the lower 16MB of memory in xsseg in using a wired TLB
> entry and a page size of 16MB. This memory would not be usable for
> DMA. Everything else would, so we could for example reserve the upper 16Mb
> for DMA (and give them to the DMA zoned memory allocator). On exception or
> error, the handler (in KSEG0) would set CU0 to allow access to CPO, then
> switch to Supervisor mode and jump to the equivalent xsseg location and
> continue execution in Supervisor mode. The code for returning to userland
> would need to clear the CU0 bit, to prevent user access to CP0.
> 	Before DMA transfer, the DMA'd buffer cache lines would be
> flushed, and then it would be remapped 'uncached', thus preventing that
> any speculative load or store to this memory happens during
> transfer. After the DMA transfer, the cache would be invalidated to make
> sure main memory is read, and the DMA buffer would be remapped 'cacheable
> non-coherent'.
> 	A diagram is attached to illustrate the workaround. Comments,
> suggestions (and even flames) are welcome before anyone starts coding
> the workaround ;)

Looks like a good start but unfortunately your concept is ignoring
userspace entirely.  You might have to deal with mmapped pages that are
being written to backing storage.  In such a case you'll have to
trackdown all mappings and disable access to them and that's something
that is pretty hard in the current memory managment code.  The solution
would be Rik's rmap patches which themselves are still under
development..  Intially I guess you can simply avoid this hairy job by
doing all DMA using bounce buffers only.  Expensive but doable ...

  Ralf

(Testing evolution ...)




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<PRE>On Sat, 2002-06-08 at 00:15, Vivien Chappelier wrote:

&gt; 	Here is a proposal for a software workaround to speculative
&gt; execution on a non-coherent system such as the i2 R10k and the o2 R10k.
&gt; 
&gt; 1. Problem:
&gt; ===========
&gt; 
&gt; 	The R10000 processor can (and will) execute intructions ahead.
&gt; These instructions will be cancelled if they're not supposed to execute,
&gt; e.g. if a jump happened. If a load or store instruction is executed
&gt; speculatively, and the accessed memory is not in the cache, the cache
&gt; line will be fetched in main memory and, on a store, be marked dirty.
&gt; These speculative loads and stores can happen anywhere, since there might
&gt; be old values in registers used in a speculative load/store
&gt; instruction that would be cancelled afterwards.
&gt; 
&gt; The problem is:
&gt; 	- on a speculative load, the fetched cache line will remain in the
&gt; cache even if the speculative load is cancelled
&gt; 	- on a speculative store, the *dirty* cache line will remain in
&gt; the cache even if the speculative store is cancelled
&gt; 
&gt; 	On non-coherent systems we need to flush the cache lines to main
&gt; memory before doing DMA to device, so that the device can see them. We
&gt; also need to invalidate lines before reading from a DMA'd buffer to make
&gt; sure the CPU will read main memory and not the cache.
&gt; 	However, if a speculative load or store happens during DMA
&gt; transfer, the cache line will be fetched from memory and, on a store, 
&gt; be marked dirty. That means this cache line could be evicted when the
&gt; line is needed, thus being written back in memory if it was dirty,
&gt; thus overwritting the data a device could have put in the DMA
&gt; buffer. Something we really don't want to happen ;)
&gt; 
&gt; 2. Proposed solution
&gt; ====================
&gt; 
&gt; 	Speculative execution will not happen in the following conditions:
&gt; 		- access to memory is uncached
&gt; 		- the speculated instruction causes an exception: that
&gt; also means a speculative load/store will not happen in a mapped memory
&gt; region which doesn't have a TLB line for it.
&gt; 
&gt; 	This second point means that any mapped space can be made safe by
&gt; removing the DMA'd buffer address translations from the TLB or by marking
&gt; them 'uncached' during DMA transfer.
&gt; 	The remaining unmapped adress spaces are:
&gt; 		- kseg1, which is safe since uncached
&gt; 		- kseg0, which can turned uncached with the K0 bits
&gt; from the CPO Config register
&gt; 		- xkphys which will cause adress error if the KX bit is
&gt; not set, the aborting the speculative load/store before it can do harm ;)
&gt; 
&gt; 	Since we need to turn KX off, xkseg will not be accessible
&gt; either.. and since we need to have KSEG0 uncached, we need to remap the
&gt; kernel elsewhere if we want performance ;). We could use the xsseg
&gt; segment, available in Supervisor mode, which is mapped (safe) and moreover
&gt; allows to access all memory (on o2 it can be up to 2G I think, whereas in
&gt; 32bit mode, only 512Mb would be accessible). So the proposed workaround is
&gt; to permanently map the lower 16MB of memory in xsseg in using a wired TLB
&gt; entry and a page size of 16MB. This memory would not be usable for
&gt; DMA. Everything else would, so we could for example reserve the upper 16Mb
&gt; for DMA (and give them to the DMA zoned memory allocator). On exception or
&gt; error, the handler (in KSEG0) would set CU0 to allow access to CPO, then
&gt; switch to Supervisor mode and jump to the equivalent xsseg location and
&gt; continue execution in Supervisor mode. The code for returning to userland
&gt; would need to clear the CU0 bit, to prevent user access to CP0.
&gt; 	Before DMA transfer, the DMA'd buffer cache lines would be
&gt; flushed, and then it would be remapped 'uncached', thus preventing that
&gt; any speculative load or store to this memory happens during
&gt; transfer. After the DMA transfer, the cache would be invalidated to make
&gt; sure main memory is read, and the DMA buffer would be remapped 'cacheable
&gt; non-coherent'.
&gt; 	A diagram is attached to illustrate the workaround. Comments,
&gt; suggestions (and even flames) are welcome before anyone starts coding
&gt; the workaround ;)

Looks like a good start but unfortunately your concept is ignoring
userspace entirely.  You might have to deal with mmapped pages that are
being written to backing storage.  In such a case you'll have to
trackdown all mappings and disable access to them and that's something
that is pretty hard in the current memory managment code.  The solution
would be Rik's rmap patches which themselves are still under
development..  Intially I guess you can simply avoid this hairy job by
doing all DMA using bounce buffers only.  Expensive but doable ...

  Ralf

(Testing evolution ...)


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From owner-linux-mips@oss.sgi.com Mon Jun 10 12:35:39 2002
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Date: Mon, 10 Jun 2002 21:41:42 +0200
From: Carsten Langgaard <carstenl@mips.com>
Organization: MIPS Technologies
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Subject: Re: Bug in the _save_fp_context.
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"H . J . Lu" wrote:

> On Thu, Jan 17, 2002 at 02:34:37PM +0100, Carsten Langgaard wrote:
> > I posted the following problem on the list almost a year ago, but it
> > still hasn't made into the SGI CVS.
> > I think there is a bug in the _save_fp_context function in
> > arch/mips/kernel/r4k_fpu.S
> >
> > The problem is the following piece of code:
> >
> >  jr ra
> >  .set nomacro
> >  EX(sw t0,SC_FPC_EIR(a0))
> >  .set macro
> >
> > We do not handle entries in the __ex_table which is located in a branch
> > delay.
> > So we need to handle the situation where we take a page fault on an
> > instruction which is located in a brach delay slot, or we don't put the
> > "potential" faulting instruction in a delay slot.
> >
> > This situation probably doesn't generally hit people since it hasn't
> > been fix yet, but if you try run something nasty like Crashme, you will
> > get hit by this problem.
> > I suggest the following patch.
> >
> > /Carsten
> >
> >
> > --
> > _    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
> > |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> > | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> >   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> >                    Denmark             http://www.mips.com
> >
> >
>
> > Index: arch/mips/kernel/r4k_fpu.S
> > ===================================================================
> > RCS file: /cvs/linux/arch/mips/kernel/r4k_fpu.S,v
> > retrieving revision 1.12
> > diff -u -r1.12 r4k_fpu.S
> > --- arch/mips/kernel/r4k_fpu.S        2001/04/11 05:19:46     1.12
> > +++ arch/mips/kernel/r4k_fpu.S        2002/01/17 14:21:09
> > @@ -50,11 +50,10 @@
> >       EX(sdc1 $f30,(SC_FPREGS+240)(a0))
> >       EX(sw   t1,SC_FPC_CSR(a0))
> >       cfc1    t0,$0                           # implementation/version
> > +     EX(sw   t0,SC_FPC_EIR(a0))
> >
> >       jr      ra
> > -     .set    nomacro
> > -      EX(sw  t0,SC_FPC_EIR(a0))
> > -     .set    macro
> > +      nop
> >       END(_save_fp_context)
> >
> >  /*
>
> Do we still need this patch for 2.4 on OSS?
>
> H.J.

No, this fix is not needed any more, as we now handle entries in the
__ex_table which is located in a branch delay.



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Subject: Atomicity & preemptive kernels
From: Justin Carlson <justin@cs.cmu.edu>
To: linux-mips@oss.sgi.com
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I know we're not there yet, but I'm trying to understand some issues
with rml's preemptive kernel and ASID's.

While doing a virtually-tagged hit invalidate of a cache, I was going to
write code something like this;

set_entryhi(CPU_CONTEXT(cpu, mm->vm_mm));
hit_invalidate_range(start, end);
set_entryhi(CPU_CONTEXT(cpu, current->mm));

Insofar as I understand current kernel scheduling guarantees, this is
safe because we won't reschedule while running in kernel mode.  But, if
I'm looking ahead to the preemptive kernel, then I think there is a
slight window for a race in between the reading of current->mm and 
the setting of entryhi.  Something like this:

current->mm->context is read
  * kernel reschedules.  
  * switch_mm() called
  * current->mm->context changes on return to this process
entryhi is set to the wrong context.

Is this a real race?  If so, is there any way around it other than
locally disabling interrupts around the restoration of the context?

-Justin
 

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Date: Mon, 10 Jun 2002 13:36:52 -0700
From: "H . J . Lu" <hjl@lucon.org>
To: linux-gcc@vger.kernel.org, GNU C Library <libc-alpha@sources.redhat.com>,
   gcc@gcc.gnu.org, Kenneth Albanowski <kjahds@kjahds.com>,
   Mat Hostetter <mat@lcs.mit.edu>,
   Andy Dougherty <doughera@lafcol.lafayette.edu>,
   Warner Losh <imp@village.org>, linux-mips@oss.sgi.com,
   Ron Guilmette <rfg@monkeys.com>,
   "Polstra; John" <linux-binutils-in@polstra.com>,
   Ralf Baechle <ralf@mailhost.uni-koblenz.de>,
   Linas Vepstas <linas@linas.org>, Feher Janos <aries@hal2000.terra.vein.hu>,
   Leonard Zubkoff <lnz@dandelion.com>, "Steven J. Hill" <sjhill@cotw.com>
Subject: The Linux binutils 2.12.90.0.11 is released.
Message-ID: <20020610133652.A27414@lucon.org>
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This is the beta release of binutils 2.12.90.0.11 for Linux, which is
based on binutils 2002 0608 in CVS on sourecs.redhat.com plus various
changes. It is purely for Linux.

The Linux/mips support is added. You have to use

# rpm --target=[mips|mipsel] -ta binutils-xx.xx.xx.xx.xx.tar.gz

to build it. Or you can read mips/README in the source tree to apply
the mips patches and build it by hand.

FYI, the binutils man pages now are generated from the texinfo files
during the build. As the result, those man pages may be changed for
each build even if you only have done

# ..../configure ...
# make

That means you may have many failures on the man pages when you apply
the binutils diffs next time. Those failures can be safely ignored.
You should remove all those man pages from your source tree by

# find -name *.1 | xargs rm -f
# find -name *.1.rej | xargs rm -f
# find -name *.man | xargs rm -f
# find -name *.man.rej | xargs rm -f

I am planning to make the public release soon. Please test it as much
as you can.

Please report any bugs related to binutils 2.12.90.0.11 to hjl@lucon.org.

For arm-linux targets, there are some important differences in behaviour 
between these tools and binutils 2.9.1.0.x.  The linker emulation name has 
changed from elf32arm{26} to armelf_linux{26}.  Also, the "-p" flag must be 
passed with the linker when working with object files (or static libraries) 
created using older versions of the assembler.  If this flag is omitted the 
linker will silently generate bad output when given old input files.

To get the correct behaviour from gcc, amend the *link section of your specs 
file as follows:

*link:
%{h*} %{version:-v}    %{b} %{Wl,*:%*}    %{static:-Bstatic}    %{shared:-shared}    %{symbolic:-Bsymbolic}    %{rdynamic:-export-dynamic}    %{!dynamic-linker: -dynamic-linker /lib/ld-linux.so.2}    -X    %{mbig-endian:-EB} %{mapcs-26:-m armelf_linux26} %{!mapcs-26:-m armelf_linux} -p


Changes from binutils 2.12.90.0.9:

1. Update from binutils 2002 0608.
2. Fix an ELF/mips SHF_MERGE bug.

Changes from binutils 2.12.90.0.7:

1. Update from binutils 2002 0526.
2. Support "-z muldefs".

Changes from binutils 2.12.90.0.4:

1. Update from binutils 2002 0423.
2. ELF EH frame bug fix.
3. MIPS ELF visibility bug fix.

Changes from binutils 2.12.90.0.3:

1. Update from binutils 2002 0408.
2. Bug fixes for ELF/sparc.
3. Bug fixes for ELF/CRIS.

Changes from binutils 2.12.90.0.1:

1. Update from binutils 2002 0323.
2. Fix linking a.out relocatable files with ELF.
3. Fix a PPC altivec assembler bug.

Changes from binutils 2.11.93.0.2:

1. Update from binutils 2002 0307.
2. Add the .preinit_array/.init_array/.fini_array support.
3. Fix eh_frame.
4. Turn on combreloc by default.
5. Enable gprof for Linux/mips.

Changes from binutils 2.11.92.0.12.3:

1. Update from binutils 2002 0207.
2. Fix a weak symbol alpha linker bug for glibc.
3. More support for gcc 3.1.

Changes from binutils 2.11.92.0.12:

1. Fix a regression in 2.11.92.0.12 when linking with none-ELF object
files.

Changes from binutils 2.11.92.0.10:

1. Update from binutils 2001 1121.
2. Fix a linker symbol version bug for common symbols.
3. Update handling relocations against the discarded sections. You may
need to apply the kernel patch enclosed here to your kernel source. If
you still see things like

drivers/char/char.o(.data+0x46b4): undefined reference to `local symbols in discarded section .text.exit'

in the final kernel link, that means you have compiled a driver into
the kernel which has a reference to the symbol in a discarded section.
Kernel 2.4.17 or above should work fine.

4. Support "-march=xxx -mipsN" for mips gas if they are compatible.

Changes from binutils 2.11.92.0.7:

1. Update from binutils 2001 1021.
2. Fix the ELF/PPC linker.
3. Fix the ELF/cris linker.
4. Fix ELF strip.

Changes from binutils 2.11.92.0.5:

1. Update from binutils 2001 1016.
2. Fix all breakages introduced in 2.11.92.0.12.

Changes from binutils 2.11.90.0.31:

1. Update from binutils 2001 1005.
2. Support gcc 3.1 for ia64.
3. Support prelink for ELF/PPC.
4. Fix an ELF/x86 linker bug for Oracle.
5. Fix a weak symbol bug.
6. Support locale.

Changes from binutils 2.11.90.0.29:

1. Update from binutils 2001 0830.
2. Fix a mips linker bug.

Changes from binutils 2.11.90.0.27:

1. Update from binutils 2001 0827.
2. Fix an alpha assembler bug.
3. Fix an ia64 linker bug.
4. Fix a mips linker bug.
5. Support `-z combreloc|nocombreloc' in linker.

Changes from binutils 2.11.90.0.25:

1. Update from binutils 2001 0810.
2. Fix an x86 linker bug.

Changes from binutils 2.11.90.0.24:

1. Update from binutils 2001 0726.
2. Fix an x86 assembler bug.
3. "make check" in the windres test in binutils may call uudecode. We
are working on it.
4. "make check" fails the windres test in binutils if the i386/pe
is enabled in bfd. Fixed in the next release.
5. "make check" has 2 failures in the ld-selective test in ld on
Linux/alpha. They should be marked xfail. Fixed in the next release.

Changes from binutils 2.11.90.0.23:

1. Update from binutils 2001 0714.
2. Fix Sparc/ElF for Linux/sparc.
3. Fix Alpha/ELF for gcc 3.0.

Changes from binutils 2.11.90.0.19:

1. Update from binutils 2001 0706.
2. Fix objcopy/strip broken by accident.
3. Avoid COPY relocs on ia32.
4. Fix the ia64 assembler.
5. This release may not work on Linux/sparc due to the unaligned
relocation changes, which are not handled by all versions of glibc.
The current glibc in CVS on sourceware should be ok. The last known
working binutils for Linux/sparc is 2.11.90.0.8. We are working on it.

Changes from binutils 2.11.90.0.15:

1. Update from binutils 2001 0620.
2. Fix a static linking the PIC object files on ia32.
3. Add the verion script support for --export-dynamic. It can be used
to selectively export dynamic symbols from the executables.

Changes from binutils 2.11.90.0.8:

1. Update from binutils 2001 0610.
2. Fix a gas bug for gcc 3.0.

Changes from binutils 2.11.90.0.7:

1. Update from binutils 2001 0512.
2. Fix some P/III SSE 2 assembler bugs.
3. Fix DT_NEEDED and symbol version bugs.
4. Support hidden versioned symbols in DSOs.

Changes from binutils 2.11.90.0.6:

1. Update from binutils 2001 0427.
2. Fix the -Bsymbolic bug introduced in binutils 2.11.90.0.5.

Changes from binutils 2.11.90.0.5:

1. Update from binutils 2001 0425.
2. Update "ld --multilib-dir PATH".

Changes from binutils 2.11.90.0.4:

1. Update from binutils 2001 0414.
2. Fix an ia64 assembler bug.
3. Change Linux/MIPS to use the SVR4 MIPS ABI instead of the IRIX ABI.
since there are no supports for the IRIX ABI in glibc. The current
Linux/MIPS targets are elf64-tradlittlemips for little endian MIPS
instead of elf32-littlemips and elf64-tradbigmips for big endian MIPS
instead of elf32-bigmips. Glibc, gcc and kernel may have to be modified
for this change. 

Changes from binutils 2.11.90.0.1:

1. Update from binutils 2001 0401.
2. Fix a gas bug for the gcc from the CVS main trunk. It involves some
changes in gas. I compiled kernel 2.2.18, gcc and glibc under
Linux/ia32. The resulting binaries work fine. 
3. Fix the linker core dump on unsupported ELF binaries.

Changes from binutils 2.10.91.0.4:

1. Update from binutils 2001 0309.

Changes from binutils 2.10.91.0.2:

1. Update from binutils 2001 0223.
2. More ia64 bug fixes.

Changes from binutils 2.10.1.0.7:

1. Update from binutils 2001 0215.
2. More ia64 bug fixes. Support EFI and "ld -relax" on ia64.
3. Fix a weak definition, -Bsymbolic, non-PIC bug for ia32.

Changes from binutils 2.10.1.0.4:

1. Update from binutils 2001 0206.
2. Enable the IA64 support.
3. Now you need to use

# ld --oformat TARGET

instead of

# ld -oformat TARGET

The Linux kernel build may be affected. BTW

# ld --oformat TARGET

should work with all previous releases of binutils.

Changes from binutils 2.10.1.0.2:

1. Update from binutils 2000 1221.

Changes from binutils 2.10.0.33:

1. Update from binutils 2000 1119.
2. It has some symbol versioning related updates.

Changes from binutils 2.10.0.32:

1. Update from binutils 2000 1018.
2. A proper ELF/PPC visibility fix.
3. m68k-a.out is supposed to be fixed.

Changes from binutils 2.10.0.31:

1. Update from binutils 2000 1014.
2. An ELF/PPC weak symbol bug fix.
3. A new linkonce section name approach.
4. m68k-a.out is still broken. To be fixed.

Changes from binutils 2.10.0.29:

1. Update from binutils 2000 1011.
2. Back out the linkonce section name change so that C++ will work.
A different approach is being worked on.
3. m68k-a.out is known to be broken. To be fixed.

Changes from binutils 2.10.0.26:

1. Update from binutils 2000 1008.

Changes from binutils 2.10.0.24:

1. Update from binutils 2000 0907.

Changes from binutils 2.10.0.18:

1. Update from binutils 2000 0823. Fix DT_RPATH/DT_RUNPATH handling.
Fix the ELF/ia32 DSO not compiled with PIC.
2. Try to fix the ELF visibility bug on PPC with glibc 2.2.

Changes from binutils 2.10.0.12:

1. Update from binutils 2000 0720.
2. Fix the DT_NEEDED link bug.
3. Add the new DT_XXXX dynamic tags. Glibc 2.2 will use them at least
on libpthread.so.

Changes from binutils 2.10.0.9:

1. Update from binutils 2000 0701. Fix the parallel build in ld when PE
is enabled.

Changes from binutils 2.9.5.0.46:

1. Update from binutils 2000 0617. The demangler support for the new
g++ ABI. Minor fix for the ELF visibility. Fix linking non-ELF
relocatable object files under ELF with symbol versioning.
2. Support for linking PE relocatable object files under ia32/ELF.

Changes from binutils 2.9.5.0.42:

1. Update from binutils 2000 0604. The ELF visibility attribuite should
work correctly now.
2. The ia32 assembler has changed the way it assembles the "jmp"
instructions to the global symbols. The old assembler will optimize the
jump to the global symbol defined in the same source file so that no
relocation will be used. The new assembler will use relocation for
global jumps. It will mainly affect PIC asm code. The segment like

	.globl  __setjmp
__setjmp:
	...
	jmp __sigsetjmp
	...
	.globl __sigsetjmp
__sigsetjmp:

is no longer PIC safe since "jmp __sigsetjmp" jumps to a global symbol
and relocation will be used. Instead, it can be changed to

	.globl  __setjmp
__setjmp:
	...
	jmp sigsetjmp
	...
	.globl __sigsetjmp
__sigsetjmp:
sigsetjmp:

so that "jmp sigsetjmp" jumps to a local symbol and the new assembler
will optimize out the relocation.

Changes from binutils 2.9.5.0.41:

1. Update from binutils 2000 0512.
2. Add testsuite for ELF visibility.

Changes from binutils 2.9.5.0.37:

1. Update from binutils 2000 0502.
2. Support STV_HIDDEN and STV_INTERNAL.

Changes from binutils 2.9.5.0.35:

1. Update from binutils 2000 0418.
2. Fix an ld demangle style option bug.

Changes from binutils 2.9.5.0.34:

1. Update from binutils 2000 0412. Fix a relocation bug which affects
the Linux kernel compilation.
2. An ELF/PPC linker script update.

Changes from binutils 2.9.5.0.33:

1. Update from binutils 2000 0404. Fix the bug report bug.

Changes from binutils 2.9.5.0.32:

1. Update from binutils 2000 0403. Fix the 16bit ia32 assembler bug.

Changes from binutils 2.9.5.0.31:

1. Update from binutils 2000 0331. Fix the Linux/ARM assembler bug.
2. Fix a Debian assembler security bug.

Changes from binutils 2.9.5.0.29:

1. Update from binutils 2000 0319.
2. An ELF/alpha bug is fixed.

Changes from binutils 2.9.5.0.27:

1. Update from binutils 2000 0301.
2. A demangler bug is fixed.
3. A better fix for undefined symbols with -Bsymbolic when building
shared library.

Changes from binutils 2.9.5.0.24:

1. Update from binutils 2000 0204.
2. Added -taso to linker on alpha.
3. Fixed a -shared -Bsymbolic bug when PIC is not used.

Changes from binutils 2.9.5.0.22:

1. Update from binutils 2000 0113.
2. A symbol version bug is fixed.
3. A -Bsymbolic bug is fixed.

Changes from binutils 2.9.5.0.21:

1. Update from binutils 1999 1202.
2. Remove a MIPS/ELF change.
3. Enable SOM for HPPA.

Changes from binutils 2.9.5.0.19:

1. Update from binutils 1999 1122. An ia32 gas bug is fixed.

Changes from binutils 2.9.5.0.16:

1. Update from binutils 1999 1104.
2. i370 is changed to use EM_S370 and ELFOSABI_LINUX. Update readelf.
3. Fix Compaq's demangler support.

Changes from binutils 2.9.5.0.14:

1. Update from binutils 1999 1012. A gas bug which affects Linux 2.3.21
is fixed.
2. i370 update.
3. The new demangler code. You should use "--style=xxx" to select the
demnangle style instead of "--lang=xxx".

Changes from binutils 2.9.5.0.13:

1. Update from binutils 1999 0925.
2. Fix a -s and linker script bug.

Changes from binutils 2.9.5.0.12:

1. Update from binutils 1999 0922.
2. i370 update.

Changes from binutils 2.9.5.0.11:

1. Update from binutils 1999 0910. It fixed a PIC linker bug on ix86
   and sparc introduced in the last release.
2. i370 update.

Changes from binutils 2.9.5.0.10:

1. Update from binutils 1999 0906. It fixed a PIC linker bug on ix86
   and sparc.
2. Remove elf/hppa since it is WIP.

Changes from binutils 2.9.5.0.8:

1. Update from binutils 1999 0831. It allows spaces around '(' and ')'
   in x86 FP register names.

Changes from binutils 2.9.5.0.7:

1. Update from binutils 1999 0821.
2. Some MIPS changes.

Changes from binutils 2.9.5.0.6:

1. Update from binutils 1999 0813.
2. i370 update.

Changes from binutils 2.9.5.0.5:

1. Update from binutils 1999 0809. An ELF/Sparc ld bug is fixed.

Changes from binutils 2.9.5.0.4:

1. Update from binutils 1999 0806. A Solaris/Sparc gas bug is fixed.
2. Remove mips gas patches from binutils 2.9.1.0.25.

Changes from binutils 2.9.5.0.3:

1. Update from binutils 1999 0801.
2. Support for real mode x86 gcc.

Changes from binutils 2.9.4.0.8:

1. Update from binutils 1999 0719. A libc 5 related bug fix.
2. Fix a typo in mips gas.

Changes from binutils 2.9.4.0.7:

1. Update from binutils 1999 0710. A weak symbol bug

http://egcs.cygnus.com/ml/egcs-bugs/1999-07/msg00129.html

is fixed.

Changes from binutils 2.9.4.0.6:

1. Update from binutils 1999 0626.

Changes from binutils 2.9.4.0.5:

1. Update from binutils 1999 0620.
2. Remove my fwait fix and use the one in cvs.
3. Use "--only-section=section" instead of "--extract-section=section".
   for objcopy.

Changes from binutils 2.9.4.0.4:

1. Update from binutils 1999 0612.
2. Remove various temporary fixes of mine since those bugs are fixed
   now.

Changes from binutils 2.9.4.0.3:

1. Update from binutils 1999 0611.
2. Remove my ELF/Alpha bfd changes.
3. Use the local symbol copy fix in binutils 1999 0611.

Changes from binutils 2.9.4.0.2:

1. Update from binutils 1999 0607.
2. Remove my Sparc hacks.
3. Fix local symbol copy.

Changes from binutils 2.9.4.0.1:

1. Update from binutils 1999 0606.
2. Restore relocation overflow checking in binutils 2.9.1.0.25 so that
   Linux kernel can build.
3. Fix i370 for the new gas.

Changes from binutils 1999 0605:

1. Fix a -Bsymbolic bug for Linux/alpha.
2. Add ELF/i370.
3. Fix 8/16-bit relocations for i386.
4. Add --redefine-sym=old_form=new_form to objcopy.
5. Add "-j section" for objcopy.
6. Fix i386 disassembler for fwait.
7. Fix a Sparc asm bug.
8. Add Ada demangle support.
9. Fix MIPS/ELF bugs.
10. Add some vxworks suppport.
11. Fix a.out assembler.

The file list:

1. binutils-2.12.90.0.11.tar.gz. Source code.
2. binutils-2.12.90.0.9-2.12.90.0.11.diff.gz. Patch against the
   previous beta source code.
3. binutils-2.12.90.0.11-1.i386.rpm. IA-32 binary RPM for RedHat 7.3.

There is no separate source rpm. You can do

# rpm -ta binutils-2.12.90.0.11.tar.gz

to create both binary and source rpms.

The primary sites for the beta Linux binutils are:

1. http://ftp.kernel.org/pub/linux/devel/binutils/

Thanks.


H.J. Lu
hjl@lucon.org
06/10/2002

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From: "Robert Williamson" <robbiew@us.ibm.com>
Date: Mon, 10 Jun 2002 15:52:33 -0500
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Thanks to Carsten Langgaard for volunteering to create the MIPS binary
RPMS.  Carsten doesn't have time right now to actually run and test the
testsuite, so could some MIPS users please download the appropriate binary
(big or little endian) and give us feedback.

Thanks,
- Robbie

Robert V. Williamson <robbiew@us.ibm.com>
Linux Test Project
IBM Linux Technology Center
Phone: (512) 838-9295   T/L: 638-9295
http://ltp.sourceforge.net



From owner-linux-mips@oss.sgi.com Mon Jun 10 15:15:54 2002
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To: Justin Carlson <justin@cs.cmu.edu>
CC: linux-mips@oss.sgi.com
Subject: Re: Atomicity & preemptive kernels
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Justin Carlson wrote:

> I know we're not there yet, but I'm trying to understand some issues
> with rml's preemptive kernel and ASID's.
> 
> While doing a virtually-tagged hit invalidate of a cache, I was going to
> write code something like this;
> 
> set_entryhi(CPU_CONTEXT(cpu, mm->vm_mm));
> hit_invalidate_range(start, end);
> set_entryhi(CPU_CONTEXT(cpu, current->mm));
> 
> Insofar as I understand current kernel scheduling guarantees, this is
> safe because we won't reschedule while running in kernel mode.  But, if
> I'm looking ahead to the preemptive kernel, then I think there is a
> slight window for a race in between the reading of current->mm and 
> the setting of entryhi.  Something like this:
> 
> current->mm->context is read
>   * kernel reschedules.  
>   * switch_mm() called
>   * current->mm->context changes on return to this process
> entryhi is set to the wrong context.
> 
> Is this a real race? 


I am not sure if I am following your logic, but I don't see a race condition here.

Once current->mm is read into a register, the register is saved into stack 
when an interrupt happens (which later incurs a reschedule presumbably).  When 
the current preempted process comes back later, it goes back to the "tail" of 
do_IRQ(), followed by restoring the registers.  Since the register now holds 
the right value, set_entryhi() should be correct.

BTW, I have preemptiable kernel working fine under both UP and SMP.  If there 
is much interestes, I will publish it on the list.

Jun



From owner-linux-mips@oss.sgi.com Mon Jun 10 16:58:33 2002
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Subject: Re: Atomicity & preemptive kernels
From: Justin Carlson <justin@cs.cmu.edu>
To: Jun Sun <jsun@mvista.com>
Cc: linux-mips@oss.sgi.com
In-Reply-To: <3D0524B5.403@mvista.com>
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On Mon, 2002-06-10 at 15:14, Jun Sun wrote:
> I am not sure if I am following your logic, but I don't see a race condition here.
> 
> Once current->mm is read into a register, the register is saved into stack 
> when an interrupt happens (which later incurs a reschedule presumbably).  When 
> the current preempted process comes back later, it goes back to the "tail" of 
> do_IRQ(), followed by restoring the registers.  Since the register now holds 
> the right value, set_entryhi() should be correct.
> 

You've described exactly what happens.  The only problem is, it's
possible the underlying value for current->mm has changed.  It's a
*really* narrow window, at most a cycle or two, but I think it is
there.  In addition, even if you hit the window, to trigger wrong
behavior it requires that you also saturate the local ASID space,
invoking the tlb flush and asid reset in get_mmu_context().

The change that's introduced by the preemptive kernel is that
switch_mm() can be called after an interrupt.  So, with some
hypothetical assembly, the code flow looks like this:

	lw	$1, 120($29) ; Load current->mm->context into a register
         * Interrupt happens *
	 * reschedule happens, switch_mm() is called *
	   * get_new_mmu_context() invoked, starts a new ASID cycle.
	   * current->mm->context for the original process changes
	 * (sometime later) switch back to original process
	mtc0 	$entryhi, $1 ; stale context put back into entryhi!

Does that make more sense?  It's really a tiny race, but I think it's a
real one.  

-Justin
	   


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Subject: Atomicity & preemptive kernels
From: Justin Carlson <justin@cs.cmu.edu>
To: linux-mips@oss.sgi.com
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I know we're not there yet, but I'm trying to understand some issues
with rml's preemptive kernel and ASID's.

While doing a virtually-tagged hit invalidate of a cache, I was going to
write code something like this;

set_entryhi(CPU_CONTEXT(cpu, mm->vm_mm));
hit_invalidate_range(start, end);
set_entryhi(CPU_CONTEXT(cpu, current->mm));

Insofar as I understand current kernel scheduling guarantees, this is
safe because we won't reschedule while running in kernel mode.  But, if
I'm looking ahead to the preemptive kernel, then I think there is a
slight window for a race in between the reading of current->mm and 
the setting of entryhi.  Something like this:

current->mm->context is read
  * kernel reschedules.  
  * switch_mm() called
  * current->mm->context changes on return to this process
entryhi is set to the wrong context.

Is this a real race?  If so, is there any way around it other than
locally disabling interrupts around the restoration of the context?

-Justin
 

From owner-linux-mips@oss.sgi.com Tue Jun 11 11:46:23 2002
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Subject: Re: Atomicity & preemptive kernels
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Justin Carlson wrote:

> On Mon, 2002-06-10 at 15:14, Jun Sun wrote:
> 
>>I am not sure if I am following your logic, but I don't see a race condition here.
>>
>>Once current->mm is read into a register, the register is saved into stack 
>>when an interrupt happens (which later incurs a reschedule presumbably).  When 
>>the current preempted process comes back later, it goes back to the "tail" of 
>>do_IRQ(), followed by restoring the registers.  Since the register now holds 
>>the right value, set_entryhi() should be correct.
>>
>>
> 
> You've described exactly what happens.  The only problem is, it's
> possible the underlying value for current->mm has changed.  It's a
> *really* narrow window, at most a cycle or two, but I think it is
> there.  In addition, even if you hit the window, to trigger wrong
> behavior it requires that you also saturate the local ASID space,
> invoking the tlb flush and asid reset in get_mmu_context().
> 
> The change that's introduced by the preemptive kernel is that
> switch_mm() can be called after an interrupt.  So, with some
> hypothetical assembly, the code flow looks like this:
> 
> 	lw	$1, 120($29) ; Load current->mm->context into a register
>          * Interrupt happens *
> 	 * reschedule happens, switch_mm() is called *
> 	   * get_new_mmu_context() invoked, starts a new ASID cycle.
> 	   * current->mm->context for the original process changes
> 	 * (sometime later) switch back to original process
> 	mtc0 	$entryhi, $1 ; stale context put back into entryhi!
> 
> Does that make more sense?  It's really a tiny race, but I think it's a
> real one.  
> 


I see your point now.

However, the race is not there.  switch_mm() is only called from inside 
schedule() function, which as a whole is preemption-safe.  In other words, the 
above event sequence won't cause a context switch until we exit from 
schedule() function.

Jun



From owner-linux-mips@oss.sgi.com Tue Jun 11 12:55:27 2002
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Subject: Re: Atomicity & preemptive kernels
From: Justin Carlson <justin@cs.cmu.edu>
To: Jun Sun <jsun@mvista.com>
Cc: linux-mips@oss.sgi.com
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On Tue, 2002-06-11 at 11:44, Jun Sun wrote:

> I see your point now.
> 
> However, the race is not there.  switch_mm() is only called from inside 
> schedule() function, which as a whole is preemption-safe.  In other words, the 
> above event sequence won't cause a context switch until we exit from 
> schedule() function.
> 

Yes, but the initial code I cited was explicitly not in the schedule
function.  It was an icache_flush_page() implementation.

Just something to be careful of.  I think it's going to bite more than a
few people as a bug that's about impossible to track down...

-Justin

From owner-linux-mips@oss.sgi.com Tue Jun 11 23:08:20 2002
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To: linux-mips@oss.sgi.com
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Subject: Accessing the serial port
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Hello,
   
I am using a Galileo Board with a RM 7000 MIPS processor. I have connected a Linux box to the board and set up a Cross-Compiler for Linux-MIPS (gcc). How do I access the serial port and print a string to the Hyperterminal on a Win NT machine which is also connected to the board. If someone could reply ASAP, please. If u can suggest any websites which contain such info. Thanks in advance.

Domcan
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From owner-linux-mips@oss.sgi.com Wed Jun 12 05:40:42 2002
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Date: Wed, 12 Jun 2002 20:39:09 +0800
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To: linux-mips@oss.sgi.com, saw@saw.sw.com.sg, linux-kernel@vger.kernel.org
Subject: NAPI for eepro100
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hi,all
   Recently i've converted eepro100 driver to use napi,in order to improve
network performance of my poor 150M mips machine. It does eliminate
the interrupt live lock seen before,maintaining a peak throughput under
heavy load.
  In case anybody are interested,i post the patches to the list. They are
3 incremental patchs:
   eepro100-napi.patch is against 2.5.20 eepro100.c and provide basic
napi support
   eepro100-proc.patch is proc file system support adapted from intel's
e100 driver. I am using it for debugging.
   eepro100-mips.patch is mips specific patch to make it work(well) for 
my mips
platform.
(i suppose people use: patch eepro100.c < x.patch to apply patch)

   Tests are mainly done on my mips machine for 2.4 kernel,though i think
 it should work for at least x86 on which minimal test is performed. Be 
careful.

   A little pitty is that to achieve good performance under heavy load, the
/proc/sys/net/core/netdev_max_backlog value may need to be adjusted.
   
  Feedbacks are always welcome:). But i am not on linux-kernel list,so 
people
there please CC me.

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 name="eepro100-mips.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="eepro100-mips.patch"

--- eepro100-napi-proc.c	Wed Jun 12 17:33:51 2002
+++ eepro100-mips.c	Wed Jun 12 19:22:29 2002
@@ -45,7 +45,7 @@
 
 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx method.
    Lower values use more memory, but are faster. */
-#if defined(__alpha__) || defined(__sparc__) || defined(__mips__) || \
+#if defined(__alpha__) || defined(__sparc__) || /*defined(__mips__) ||*/ \
     defined(__arm__)
 static int rx_copybreak = 1518;
 #else
@@ -66,8 +66,8 @@
 
 /* A few values that may be tweaked. */
 /* The ring sizes should be a power of two for efficiency. */
-#define TX_RING_SIZE	64
-#define RX_RING_SIZE	64
+#define TX_RING_SIZE	32
+#define RX_RING_SIZE	32
 /* How much slots multicast filter setup may take.
    Do not descrease without changing set_rx_mode() implementaion. */
 #define TX_MULTICAST_SIZE   2
@@ -1298,7 +1298,14 @@
 		if (skb == NULL)
 			break;			/* OK.  Just initially short of Rx bufs. */
 		skb->dev = dev;			/* Mark as being used by this device. */
+#ifndef __mips__
 		rxf = (struct RxFD *)skb->tail;
+#else
+		/* use uncached address,use pci_dma_sync_xx seems 
+		 * problematic in my mips platform
+		 */
+		rxf = (struct RxFD *)(KSEG1ADDR(skb->tail));
+#endif
 		sp->rx_ringp[i] = rxf;
 		sp->rx_ring_dma[i] =
 			pci_map_single(sp->pdev, rxf,
@@ -1306,8 +1313,10 @@
 		skb_reserve(skb, sizeof(struct RxFD));
 		if (last_rxf) {
 			last_rxf->link = cpu_to_le32(sp->rx_ring_dma[i]);
+#ifndef __mips__
 			pci_dma_sync_single(sp->pdev, last_rxf_dma,
 					sizeof(struct RxFD), PCI_DMA_TODEVICE);
+#endif
 		}
 		last_rxf = rxf;
 		last_rxf_dma = sp->rx_ring_dma[i];
@@ -1316,14 +1325,18 @@
 		/* This field unused by i82557. */
 		rxf->rx_buf_addr = 0xffffffff;
 		rxf->count = cpu_to_le32(PKT_BUF_SZ << 16);
+#ifndef __mips__
 		pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[i],
 				sizeof(struct RxFD), PCI_DMA_TODEVICE);
+#endif
 	}
 	sp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
 	/* Mark the last entry as end-of-list. */
 	last_rxf->status = cpu_to_le32(0xC0000002);	/* '2' is flag value only. */
+#ifndef __mips__
 	pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[RX_RING_SIZE-1],
 			sizeof(struct RxFD), PCI_DMA_TODEVICE);
+#endif
 	sp->last_rxf = last_rxf;
 	sp->last_rxf_dma = last_rxf_dma;
 }
@@ -1733,15 +1746,21 @@
 #endif
 		return NULL;
 	}
+#ifndef __mips__
 	rxf = sp->rx_ringp[entry] = (struct RxFD *)skb->tail;
+#else
+	rxf = sp->rx_ringp[entry] = (struct RxFD *)(KSEG1ADDR(skb->tail));
+#endif
 	sp->rx_ring_dma[entry] =
 		pci_map_single(sp->pdev, rxf,
 					   PKT_BUF_SZ + sizeof(struct RxFD), PCI_DMA_FROMDEVICE);
 	skb->dev = dev;
 	skb_reserve(skb, sizeof(struct RxFD));
 	rxf->rx_buf_addr = 0xffffffff;
+#ifndef __mips__
 	pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[entry],
 			sizeof(struct RxFD), PCI_DMA_TODEVICE);
+#endif
 	return rxf;
 }
 
@@ -1754,8 +1773,10 @@
 	rxf->count = cpu_to_le32(PKT_BUF_SZ << 16);
 	sp->last_rxf->link = cpu_to_le32(rxf_dma);
 	sp->last_rxf->status &= cpu_to_le32(~0xC0000000);
+#ifndef __mips__
 	pci_dma_sync_single(sp->pdev, sp->last_rxf_dma,
 			sizeof(struct RxFD), PCI_DMA_TODEVICE);
+#endif
 	sp->last_rxf = rxf;
 	sp->last_rxf_dma = rxf_dma;
 }
@@ -2274,8 +2295,10 @@
 		int status;
 		int pkt_len;
 
+#ifndef __mips__
 		pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[entry],
 			sizeof(struct RxFD), PCI_DMA_FROMDEVICE);
+#endif
 		status = le32_to_cpu(sp->rx_ringp[entry]->status);
 		pkt_len = le32_to_cpu(sp->rx_ringp[entry]->count) & 0x3fff;
 

--------------070502030508090306010005
Content-Type: text/plain;
 name="eepro100-napi.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="eepro100-napi.patch"

--- eepro100.c.ori	Wed Jun 12 17:25:28 2002
+++ eepro100-napi.c	Wed Jun 12 17:11:38 2002
@@ -25,6 +25,8 @@
 		Disabled FC and ER, to avoid lockups when when we get FCP interrupts.
 	2000 Jul 17 Goutham Rao <goutham.rao@intel.com>
 		PCI DMA API fixes, adding pci_dma_sync_single calls where neccesary
+	2002 Jun 12 Zhang Fuxin <fxzhang@ict.ac.cn>
+		add NAPI support
 */
 
 static const char *version =
@@ -115,6 +117,8 @@
 #include <linux/skbuff.h>
 #include <linux/ethtool.h>
 
+#define CONFIG_EEPRO100_NAPI
+
 MODULE_AUTHOR("Maintainer: Andrey V. Savochkin <saw@saw.sw.com.sg>");
 MODULE_DESCRIPTION("Intel i82557/i82558/i82559 PCI EtherExpressPro driver");
 MODULE_LICENSE("GPL");
@@ -494,8 +498,34 @@
 #ifdef CONFIG_PM
 	u32 pm_state[16];
 #endif
+
+	/* added by zfx for NAPI*/
+#ifdef CONFIG_EEPRO100_NAPI
+
+	/* used to pass rx_work_limit into speedo_rx,i don't want to 
+	 * change its prototype
+	 */
+	int curr_work_limit;
+	unsigned long poll_switch;
+	unsigned long failed_poll_switch;
+	unsigned long done_poll;
+	unsigned long notdone_poll;
+	unsigned long empty_poll;
+	unsigned long soft_reset_count;
+	unsigned long rx_resume_count;
+	unsigned long alloc_fail;
+	unsigned long long poll_cycles;
+
+#ifdef CONFIG_NET_FASTROUTE
+	unsigned long fastroute_hit;
+	unsigned long fastroute_success;
+	unsigned long fastroute_defer;
+#endif
+
+#endif
 };
 
+
 /* The parameters for a CmdConfigure operation.
    There are so many options that it would be difficult to document each bit.
    We mostly use the default or recommended settings. */
@@ -546,6 +576,14 @@
 static void set_rx_mode(struct net_device *dev);
 static void speedo_show_state(struct net_device *dev);
 
+#ifdef CONFIG_EEPRO100_NAPI
+
+static int speedo_poll (struct net_device *dev, int *budget);
+static void enable_rx_and_rxnobuf_ints(struct net_device *dev);
+static void disable_rx_and_rxnobuf_ints(struct net_device *dev);
+
+#endif
+
 
 
 #ifdef honor_default_port
@@ -842,6 +880,10 @@
 	dev->set_multicast_list = &set_rx_mode;
 	dev->do_ioctl = &speedo_ioctl;
 
+#ifdef CONFIG_EEPRO100_NAPI
+	dev->poll = speedo_poll;
+	dev->quota = dev->weight = RX_RING_SIZE;
+#endif
 	return 0;
 }
 
@@ -1517,6 +1559,9 @@
 	struct speedo_private *sp;
 	long ioaddr, boguscnt = max_interrupt_work;
 	unsigned short status;
+#ifdef CONFIG_EEPRO100_NAPI
+	int first = 1;
+#endif
 
 #ifndef final_version
 	if (dev == NULL) {
@@ -1543,16 +1588,21 @@
 		/* Acknowledge all of the current interrupt sources ASAP. */
 		/* Will change from 0xfc00 to 0xff00 when we start handling
 		   FCP and ER interrupts --Dragan */
+#ifndef CONFIG_EEPRO100_NAPI
 		outw(status & 0xfc00, ioaddr + SCBStatus);
+#else
+		/* Rx & RxNoBuf is acked in speedo_poll */
+		outw(status & 0xac00, ioaddr + SCBStatus);
+#endif
 
 		if (speedo_debug > 4)
 			printk(KERN_DEBUG "%s: interrupt  status=%#4.4x.\n",
 				   dev->name, status);
 
+#ifndef CONFIG_EEPRO100_NAPI
 		if ((status & 0xfc00) == 0)
 			break;
 
-
 		if ((status & 0x5000) ||	/* Packet received, or Rx error. */
 			(sp->rx_ring_state&(RrNoMem|RrPostponed)) == RrPostponed)
 									/* Need to gather the postponed packet. */
@@ -1560,8 +1610,33 @@
 
 		/* Always check if all rx buffers are allocated.  --SAW */
 		speedo_refill_rx_buffers(dev, 0);
+#else
+		/* Packet received, or Rx error. */
+		if (first && ((status & 0x5000) || (sp->rx_ring_state&(RrNoMem|RrPostponed)) == RrPostponed || (status & 0x3c) != 0x10 ))
+			/* Need to gather the postponed packet. */
+		{
+			if (speedo_debug > 4) 
+				printk("switching to poll,status=%x\n",status);
+			first = 0;
+			if (netif_rx_schedule_prep(dev)) {
+				sp->poll_switch++;
+				/* disable interrupts caused by arriving packets */
+				disable_rx_and_rxnobuf_ints(dev);
+				/* tell system we have work to be done. */
+				__netif_rx_schedule(dev);
+			}else {
+				sp->failed_poll_switch++;
+			}
+
+		}
+
+		if ((status & 0xac00) == 0)
+			break;
+#endif
 		
 		spin_lock(&sp->lock);
+
+#ifndef CONFIG_EEPRO100_NAPI
 		/*
 		 * The chip may have suspended reception for various reasons.
 		 * Check for that, and re-prime it should this be the case.
@@ -1581,7 +1656,7 @@
 			/* these are all reserved values */
 			break;
 		}
-		
+#endif
 		
 		/* User interrupt, Command/Tx unit interrupt or CU not active. */
 		if (status & 0xA400) {
@@ -1602,7 +1677,12 @@
 			/* Clear all interrupt sources. */
 			/* Will change from 0xfc00 to 0xff00 when we start handling
 			   FCP and ER interrupts --Dragan */
+#ifndef CONFIG_EEPRO100_NAPI
 			outw(0xfc00, ioaddr + SCBStatus);
+#else
+			outw(0xac00, ioaddr + SCBStatus);
+#endif
+
 			break;
 		}
 	} while (1);
@@ -1611,7 +1691,9 @@
 		printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
 			   dev->name, inw(ioaddr + SCBStatus));
 
+#ifndef final_version
 	clear_bit(0, (void*)&sp->in_interrupt);
+#endif
 	return;
 }
 
@@ -1625,6 +1707,9 @@
 	sp->rx_skbuff[entry] = skb;
 	if (skb == NULL) {
 		sp->rx_ringp[entry] = NULL;
+#ifdef CONFIG_EEPRO100_NAPI
+		sp->alloc_fail++;
+#endif
 		return NULL;
 	}
 	rxf = sp->rx_ringp[entry] = (struct RxFD *)skb->tail;
@@ -1705,12 +1790,112 @@
 			speedo_refill_rx_buf(dev, force) != -1);
 }
 
+#ifdef CONFIG_EEPRO100_NAPI
+static void enable_rx_and_rxnobuf_ints(struct net_device *dev)
+{
+	long ioaddr = dev->base_addr;
+	outw(SCBMaskEarlyRx | SCBMaskFlowCtl, ioaddr + SCBCmd);
+	inw(ioaddr + SCBStatus); /* flushes last write, read-safe */
+};
+
+static void disable_rx_and_rxnobuf_ints(struct net_device *dev)
+{
+	long ioaddr = dev->base_addr;
+	outw(SCBMaskRxDone | SCBMaskRxSuspend | SCBMaskEarlyRx | SCBMaskFlowCtl, ioaddr + SCBCmd);
+	inw(ioaddr + SCBStatus); /* flushes last write, read-safe */
+};
+
+static int speedo_poll (struct net_device *dev, int *budget)
+{
+	struct speedo_private *sp = (struct speedo_private *)dev->priv;
+	long ioaddr, received = 0;
+	unsigned short intr_status;
+
+	ioaddr = dev->base_addr;
+	intr_status = inw(ioaddr + SCBStatus);
+
+	if (speedo_debug > 4)
+		printk(KERN_DEBUG " In speedo_poll().\n");
+
+	sp->curr_work_limit = *budget;
+	if (sp->curr_work_limit > dev->quota) 
+		sp->curr_work_limit = dev->quota;
+
+	do {  
+		/* ack Rx & RxNobuf intrs*/
+		outw(intr_status & 0x5000, ioaddr + SCBStatus);
+
+		received += speedo_rx(dev);
+
+		if (sp->curr_work_limit < 0) /* out of quota */
+			goto not_done;
+
+		/* no packets on ring; but new ones can arrive since we last checked  */
+		intr_status = inw(ioaddr + SCBStatus);
+
+		if ((intr_status & 0x5000) == 0) {
+			/* If something arrives in this narrow window,an interrupt 
+			 * will be generated 
+			 */
+			goto done;
+		}
+		/* done! at least thats what it looks like ;->
+		   if new packets came in after our last check on status bits
+		   they'll be caught by the while check and we go back and clear them
+		   since we havent exceeded our quota 
+		 */
+	} while (intr_status & 0x5000);
+
+done:
+	if (!received) {
+		if (speedo_debug > 4) printk("received==0\n");
+		received = 1;
+		sp->empty_poll++;
+	}
+	dev->quota -= received;
+	*budget -= received;
+
+	/* we are happy/done, no more packets on ring; put us back
+	 * to where we can start processing interrupts again 
+	 */
+	netif_rx_complete(dev);
+	enable_rx_and_rxnobuf_ints(dev);
+
+	sp->done_poll++;
+
+	if (speedo_debug > 3)
+		printk("done,received=%lu\n",received);
+
+        return 0;   /* done */
+
+not_done:
+	if (!received) {
+		if (speedo_debug > 4) printk("received==0\n");
+		received = 1;
+		sp->empty_poll++;
+	}
+	dev->quota -= received;
+	*budget -= received;
+
+	sp->notdone_poll++;
+
+	if (speedo_debug > 3)
+		printk("not done,received=%lu\n",received);
+
+	return 1;  /* not_done */
+}
+
+#endif /* NAPI */
+
 static int
 speedo_rx(struct net_device *dev)
 {
 	struct speedo_private *sp = (struct speedo_private *)dev->priv;
 	int entry = sp->cur_rx % RX_RING_SIZE;
+#ifndef CONFIG_EEPRO100_NAPI
 	int rx_work_limit = sp->dirty_rx + RX_RING_SIZE - sp->cur_rx;
+#endif
+	int received = 0;
 	int alloc_ok = 1;
 
 	if (speedo_debug > 4)
@@ -1725,11 +1910,42 @@
 		status = le32_to_cpu(sp->rx_ringp[entry]->status);
 		pkt_len = le32_to_cpu(sp->rx_ringp[entry]->count) & 0x3fff;
 
+#ifndef CONFIG_EEPRO100_NAPI
 		if (!(status & RxComplete))
 			break;
 
 		if (--rx_work_limit < 0)
 			break;
+#else
+		if (!(status & RxComplete)) {
+			int intr_status;
+			unsigned long ioaddr = dev->base_addr;
+
+			intr_status = inw(ioaddr + SCBStatus);
+			/* We check receiver state here because if 
+			 * we have to do soft reset,sp->cur_rx should
+			 * point to an empty entry or something 
+			 * unexpected will happen
+			 */
+			if (intr_status | 0x1000) { /* suspended */
+				outw(0x5000,ioaddr + SCBStatus);
+				/* No resources */
+				if ((intr_status & 0x3c) == 0x28) {
+					outw(RxResumeNoResources,ioaddr+SCBCmd);
+					sp->rx_resume_count++;
+				}else if ((intr_status & 0x3c) == 0x8) {
+					if (speedo_debug > 4) 
+						printk("No resource,reset\n");
+					speedo_rx_soft_reset(dev);
+					sp->soft_reset_count++;
+				}
+			}
+			break;
+		}
+
+		if (--sp->curr_work_limit < 0) 
+			break;
+#endif
 
 		/* Check for a rare out-of-memory case: the current buffer is
 		   the last buffer allocated in the RX ring.  --SAW */
@@ -1793,7 +2009,12 @@
 						PKT_BUF_SZ + sizeof(struct RxFD), PCI_DMA_FROMDEVICE);
 			}
 			skb->protocol = eth_type_trans(skb, dev);
+#ifndef CONFIG_EEPRO100_NAPI
 			netif_rx(skb);
+#else
+			netif_receive_skb(skb);
+			received ++;
+#endif
 			dev->last_rx = jiffies;
 			sp->stats.rx_packets++;
 			sp->stats.rx_bytes += pkt_len;
@@ -1811,7 +2032,7 @@
 
 	sp->last_rx_time = jiffies;
 
-	return 0;
+	return received;
 }
 
 static int

--------------070502030508090306010005
Content-Type: text/plain;
 name="eepro100-proc.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="eepro100-proc.patch"

--- eepro100-napi.c	Wed Jun 12 17:11:38 2002
+++ eepro100-napi-proc.c	Wed Jun 12 17:33:51 2002
@@ -119,6 +119,10 @@
 
 #define CONFIG_EEPRO100_NAPI
 
+#ifdef CONFIG_PROC_FS
+#include <linux/proc_fs.h>
+#endif
+
 MODULE_AUTHOR("Maintainer: Andrey V. Savochkin <saw@saw.sw.com.sg>");
 MODULE_DESCRIPTION("Intel i82557/i82558/i82559 PCI EtherExpressPro driver");
 MODULE_LICENSE("GPL");
@@ -516,6 +520,10 @@
 	unsigned long alloc_fail;
 	unsigned long long poll_cycles;
 
+#ifdef CONFIG_PROC_FS
+	struct proc_dir_entry *proc_parent;
+#endif
+
 #ifdef CONFIG_NET_FASTROUTE
 	unsigned long fastroute_hit;
 	unsigned long fastroute_success;
@@ -582,6 +590,11 @@
 static void enable_rx_and_rxnobuf_ints(struct net_device *dev);
 static void disable_rx_and_rxnobuf_ints(struct net_device *dev);
 
+#ifdef CONFIG_PROC_FS
+int __devinit speedo_create_proc_subdir(struct net_device *sp);
+void speedo_remove_proc_subdir(struct net_device *sp);
+#endif
+
 #endif
 
 
@@ -883,6 +896,14 @@
 #ifdef CONFIG_EEPRO100_NAPI
 	dev->poll = speedo_poll;
 	dev->quota = dev->weight = RX_RING_SIZE;
+
+#ifdef CONFIG_PROC_FS
+	if (speedo_create_proc_subdir(dev) < 0) {
+		printk(KERN_ERR "Failed to create proc directory for %s\n",
+				dev->name);
+	}              
+#endif
+
 #endif
 	return 0;
 }
@@ -1885,6 +1906,354 @@
 	return 1;  /* not_done */
 }
 
+#ifdef CONFIG_PROC_FS
+/* adapted from intel's e100 code */
+static struct proc_dir_entry *adapters_proc_dir = 0;
+
+static void speedo_proc_cleanup(void);
+static unsigned char speedo_init_proc_dir(void);
+
+#define ADAPTERS_PROC_DIR "eepro100"
+#define WRITE_BUF_MAX_LEN 20	
+#define READ_BUF_MAX_LEN  256
+#define SPEEDO_PE_LEN       25
+
+#define sp_off(off) (unsigned long)(offsetof(struct speedo_private, off))
+
+typedef struct _speedo_proc_entry {
+	char *name;
+	read_proc_t *read_proc;
+	write_proc_t *write_proc;
+	unsigned long offset;	/* offset into sp. ~0 means no value, pass NULL. */
+} speedo_proc_entry;
+
+static int
+generic_read(char *page, char **start, off_t off, int count, int *eof, int len)
+{
+	if (len <= off + count)
+		*eof = 1;
+
+	*start = page + off;
+	len -= off;
+	if (len > count)
+		len = count;
+
+	if (len < 0)
+		len = 0;
+
+	return len;
+}
+
+static int
+read_ulong(char *page, char **start, off_t off,
+	   int count, int *eof, unsigned long l)
+{
+	int len;
+
+	len = sprintf(page, "%lu\n", l);
+
+	return generic_read(page, start, off, count, eof, len);
+}
+
+static int
+read_gen_ulong(char *page, char **start, off_t off,
+	       int count, int *eof, void *data)
+{
+	unsigned long val = 0;
+
+	if (data)
+		val = *((unsigned long *) data);
+
+	return read_ulong(page, start, off, count, eof, val);
+}
+
+static int
+read_ulonglong(char *page, char **start, off_t off,
+	   int count, int *eof, unsigned long long ll)
+{
+	int len;
+
+	len = sprintf(page, "%llu\n", ll);
+
+	return generic_read(page, start, off, count, eof, len);
+}
+
+static int
+read_gen_ulonglong(char *page, char **start, off_t off,
+	       int count, int *eof, void *data)
+{
+	unsigned long val = 0;
+
+	if (data)
+		val = *((unsigned long long *) data);
+
+	return read_ulonglong(page, start, off, count, eof, val);
+}
+
+static int
+set_debug(struct file *file, const char *buffer,
+		    unsigned long count, void *data)
+
+{
+	if (speedo_debug == 1) 
+		speedo_debug = 6;
+	else
+		speedo_debug = 1;
+	return count;
+}
+
+static int
+_speedo_show_state(struct file *file, const char *buffer,
+		    unsigned long count, void *data)
+{
+	
+	struct net_device *dev = (struct net_device *)data;
+
+	speedo_show_state(dev);
+
+	return count;
+}
+
+static speedo_proc_entry speedo_proc_list[] = {
+	{"set_debug", 0, set_debug, ~0},
+	{"show_state", 0, _speedo_show_state, ~0},
+	{"poll_switch",read_gen_ulong,0,sp_off(poll_switch)},
+	{"failed_poll_switch",read_gen_ulong,0,sp_off(failed_poll_switch)},
+	{"done_poll",read_gen_ulong,0,sp_off(done_poll)},
+	{"notdone_poll",read_gen_ulong,0,sp_off(notdone_poll)},
+	{"empty_poll",read_gen_ulong,0,sp_off(empty_poll)},
+	{"soft_reset_count",read_gen_ulong,0,sp_off(soft_reset_count)},
+	{"rx_resume_count",read_gen_ulong,0,sp_off(rx_resume_count)},
+	{"alloc_fail",read_gen_ulong,0,sp_off(alloc_fail)},
+	{"poll_cycles",read_gen_ulonglong,0,sp_off(poll_cycles)},
+	{"fastroute_hit",read_gen_ulonglong,0,sp_off(fastroute_hit)},
+	{"fastroute_success",read_gen_ulonglong,0,sp_off(fastroute_success)},
+	{"fastroute_defer",read_gen_ulonglong,0,sp_off(fastroute_defer)},
+	{"", 0, 0, 0}
+};
+
+static int
+read_info(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+	struct speedo_private *sp = data;
+	speedo_proc_entry *pe;
+	int tmp;
+	void *val;
+	int len = 0;
+
+	for (pe = speedo_proc_list; pe->name[0]; pe++) {
+		if (pe->name[0] == '\n') {
+			len += sprintf(page + len, "\n");
+			continue;
+		}
+
+		if (pe->read_proc) {
+			if ((len + READ_BUF_MAX_LEN + SPEEDO_PE_LEN + 1) >=
+			    PAGE_SIZE)
+				break;
+
+			if (pe->offset != ~0)
+				val = ((char *) sp) + pe->offset;
+			else
+				val = NULL;
+
+			len += sprintf(page + len, "%-"
+				       __MODULE_STRING(SPEEDO_PE_LEN)
+				       "s ", pe->name);
+			len += pe->read_proc(page + len, start, 0,
+					     READ_BUF_MAX_LEN + 1, &tmp, val);
+		}
+	}
+
+	return generic_read(page, start, off, count, eof, len);
+}
+
+static struct proc_dir_entry * __devinit
+create_proc_rw(char *name, void *data, struct proc_dir_entry *parent,
+	       read_proc_t * read_proc, write_proc_t * write_proc)
+{
+	struct proc_dir_entry *pdep;
+	mode_t mode = S_IFREG;
+
+	if (write_proc) {
+		mode |= S_IWUSR;
+		if (read_proc) {
+			mode |= S_IRUSR;
+		}
+
+	} else if (read_proc) {
+		mode |= S_IRUGO;
+	}
+
+	if (!(pdep = create_proc_entry(name, mode, parent)))
+		return NULL;
+
+	pdep->read_proc = read_proc;
+	pdep->write_proc = write_proc;
+	pdep->data = data;
+	return pdep;
+}
+
+void
+speedo_remove_proc_subdir(struct net_device *dev)
+{
+	struct speedo_private *sp = (struct speedo_private *)dev->priv;
+	speedo_proc_entry *pe;
+	char info[256];
+	int len;
+
+	/* If our root /proc dir was not created, there is nothing to remove */
+	if (adapters_proc_dir == NULL) {
+		return;
+	}
+
+	len = strlen(dev->name);
+	strncpy(info, dev->name, sizeof (info));
+	strncat(info + len, ".info", sizeof (info) - len);
+
+	if (sp->proc_parent) {
+		for (pe = speedo_proc_list; pe->name[0]; pe++) {
+			if (pe->name[0] == '\n')
+				continue;
+
+			remove_proc_entry(pe->name, sp->proc_parent);
+		}
+
+		remove_proc_entry(dev->name, adapters_proc_dir);
+		sp->proc_parent = NULL;
+	}
+
+	remove_proc_entry(info, adapters_proc_dir);
+
+	/* try to remove the main /proc dir, if it's empty */
+	speedo_proc_cleanup();
+}
+
+int __devinit
+speedo_create_proc_subdir(struct net_device *dev)
+{
+	struct speedo_private *sp = (struct speedo_private *)dev->priv;
+	struct proc_dir_entry *dev_dir;
+	speedo_proc_entry *pe;
+	char info[256];
+	int len;
+	void *data;
+
+	/* create the main /proc dir if needed */
+	if (!adapters_proc_dir) {
+		if (!speedo_init_proc_dir())
+			return -ENOMEM;
+	}
+
+	strncpy(info, dev->name, sizeof (info));
+	len = strlen(info);
+	strncat(info + len, ".info", sizeof (info) - len);
+
+	/* info */
+	if (!(create_proc_rw(info, sp, adapters_proc_dir, read_info, 0))) {
+		speedo_proc_cleanup();
+		return -ENOMEM;
+	}
+
+	dev_dir = create_proc_entry(dev->name, S_IFDIR,
+				    adapters_proc_dir);
+	sp->proc_parent = dev_dir;
+
+	if (!dev_dir) {
+		speedo_remove_proc_subdir(dev);
+		return -ENOMEM;
+	}
+
+	for (pe = speedo_proc_list; pe->name[0]; pe++) {
+		if (pe->name[0] == '\n')
+			continue;
+
+		if (pe->offset != ~0)
+			data = ((char *) sp) + pe->offset;
+		else
+			data = dev;
+
+		if (!(create_proc_rw(pe->name, data, dev_dir,
+				     pe->read_proc, pe->write_proc))) {
+			speedo_remove_proc_subdir(dev);
+			return -ENOMEM;
+		}
+	}
+
+	return 0;
+}
+
+/****************************************************************************
+ * Name:          speedo_init_proc_dir
+ *
+ * Description:   This routine creates the top-level /proc directory for the
+ *                driver in /proc/net
+ *
+ * Arguments:     none
+ *
+ * Returns:       true on success, false on fail
+ *
+ ***************************************************************************/
+static unsigned char
+speedo_init_proc_dir(void)
+{
+	int len;
+
+	/* first check if adapters_proc_dir already exists */
+	len = strlen(ADAPTERS_PROC_DIR);
+	for (adapters_proc_dir = proc_net->subdir;
+	     adapters_proc_dir; adapters_proc_dir = adapters_proc_dir->next) {
+
+		if ((adapters_proc_dir->namelen == len) &&
+		    (!memcmp(adapters_proc_dir->name, ADAPTERS_PROC_DIR, len)))
+			break;
+	}
+
+	if (!adapters_proc_dir)
+		adapters_proc_dir =
+			create_proc_entry(ADAPTERS_PROC_DIR, S_IFDIR, proc_net);
+
+	if (!adapters_proc_dir)
+		return 0;
+
+	return 1;
+}
+
+/****************************************************************************
+ * Name:          speedo_proc_cleanup
+ *
+ * Description:   This routine clears the top-level /proc directory, if empty.
+ *
+ * Arguments:     none
+ *
+ * Returns:       none
+ *
+ ***************************************************************************/
+static void
+speedo_proc_cleanup(void)
+{
+	struct proc_dir_entry *de;
+
+	if (adapters_proc_dir == NULL) {
+		return;
+	}
+
+	/* check if subdir list is empty before removing adapters_proc_dir */
+	for (de = adapters_proc_dir->subdir; de; de = de->next) {
+		/* ignore . and .. */
+		if (*(de->name) != '.')
+			break;
+	}
+
+	if (de)
+		return;
+
+	remove_proc_entry(ADAPTERS_PROC_DIR, proc_net);
+	adapters_proc_dir = NULL;
+}
+
+#endif /* CONFIG_PROC_FS */
+
 #endif /* NAPI */
 
 static int
@@ -2474,6 +2843,9 @@
 	
 	unregister_netdev(dev);
 
+#if defined(CONFIG_EEPRO100_NAPI) && defined(CONFIG_PROC_FS)
+	speedo_remove_proc_subdir(dev);
+#endif
 	release_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
 	release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
 

--------------070502030508090306010005--


From owner-linux-mips@oss.sgi.com Wed Jun 12 16:01:05 2002
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Message-ID: <3D07D270.5060902@mandrakesoft.com>
Date: Wed, 12 Jun 2002 19:00:00 -0400
From: Jeff Garzik <jgarzik@mandrakesoft.com>
Organization: MandrakeSoft
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To: Zhang Fuxin <fxzhang@ict.ac.cn>
CC: linux-mips@oss.sgi.com, saw@saw.sw.com.sg, linux-kernel@vger.kernel.org,
   netdev@oss.sgi.com
Subject: Re: NAPI for eepro100
References: <3D0740ED.2060907@ict.ac.cn>
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Zhang Fuxin wrote:
> hi,all
>   Recently i've converted eepro100 driver to use napi,in order to improve
> network performance of my poor 150M mips machine. It does eliminate
> the interrupt live lock seen before,maintaining a peak throughput under
> heavy load.
>  In case anybody are interested,i post the patches to the list. They are
> 3 incremental patchs:
>   eepro100-napi.patch is against 2.5.20 eepro100.c and provide basic
> napi support

Nifty, I'll take a look at this.


>   eepro100-proc.patch is proc file system support adapted from intel's
> e100 driver. I am using it for debugging.
>   eepro100-mips.patch is mips specific patch to make it work(well) for 
> my mips
> platform.


Just FWIW I'm not gonna apply these... for the 'proc' patch, that either 
needs to be moved to ethtool, or we should make a filesystem for net 
drivers that exports procfs-like inodes.  for the 'mips' patch, it looks 
like the arch maintainer(s) need to fix the PCI DMA support...

	Jeff




From owner-linux-mips@oss.sgi.com Wed Jun 12 16:07:32 2002
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Date: Wed, 12 Jun 2002 16:05:32 -0700 (PDT)
Message-Id: <20020612.160532.134201977.davem@redhat.com>
To: jgarzik@mandrakesoft.com
Cc: fxzhang@ict.ac.cn, linux-mips@oss.sgi.com, saw@saw.sw.com.sg,
   linux-kernel@vger.kernel.org, netdev@oss.sgi.com
Subject: Re: NAPI for eepro100
From: "David S. Miller" <davem@redhat.com>
In-Reply-To: <3D07D270.5060902@mandrakesoft.com>
References: <3D0740ED.2060907@ict.ac.cn>
	<3D07D270.5060902@mandrakesoft.com>
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   From: Jeff Garzik <jgarzik@mandrakesoft.com>
   Date: Wed, 12 Jun 2002 19:00:00 -0400
   
   for the 'mips' patch, it looks 
   like the arch maintainer(s) need to fix the PCI DMA support...

No, it's worse than that.

See how non-consistent memory is used by the eepro100 driver
for descriptor bits?  The skb->tail bits?

That is very problematic.

From owner-linux-mips@oss.sgi.com Wed Jun 12 16:18:54 2002
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Date: Wed, 12 Jun 2002 19:17:58 -0400
From: Jeff Garzik <jgarzik@mandrakesoft.com>
Organization: MandrakeSoft
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CC: fxzhang@ict.ac.cn, linux-mips@oss.sgi.com, saw@saw.sw.com.sg,
   linux-kernel@vger.kernel.org, netdev@oss.sgi.com
Subject: Re: NAPI for eepro100
References: <3D0740ED.2060907@ict.ac.cn>	<3D07D270.5060902@mandrakesoft.com> <20020612.160532.134201977.davem@redhat.com>
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David S. Miller wrote:
>    From: Jeff Garzik <jgarzik@mandrakesoft.com>
>    Date: Wed, 12 Jun 2002 19:00:00 -0400
>    
>    for the 'mips' patch, it looks 
>    like the arch maintainer(s) need to fix the PCI DMA support...
> 
> No, it's worse than that.
> 
> See how non-consistent memory is used by the eepro100 driver
> for descriptor bits?  The skb->tail bits?
> 
> That is very problematic.


Oh crap, you're right...   eepro100 in general does funky stuff with the 
way packets are handled, mainly due to the need to issue commands to the 
NIC engine instead of the normal per-descriptor owner bit way of doing 
things.

Well, I accept patches to that clean eepro100 up...   I'm not terribly 
motivated to clean it up myself, as we have e100 and an e100 maintainer 
we can beat on if such uglies arise :)

	Jeff




From owner-linux-mips@oss.sgi.com Wed Jun 12 16:35:43 2002
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Subject: Re: NAPI for eepro100
From: "David S. Miller" <davem@redhat.com>
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   From: Jeff Garzik <jgarzik@mandrakesoft.com>
   Date: Wed, 12 Jun 2002 19:17:58 -0400

   Oh crap, you're right...   eepro100 in general does funky stuff with the 
   way packets are handled, mainly due to the need to issue commands to the 
   NIC engine instead of the normal per-descriptor owner bit way of doing 
   things.

The question is, do the descriptor bits have to live right before
the RX packet data buffer or can other schemes be used?

From owner-linux-mips@oss.sgi.com Wed Jun 12 19:23:13 2002
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	Wed, 12 Jun 2002 22:25:22 -0400
Date: Wed, 12 Jun 2002 22:25:22 -0400 (EDT)
From: Donald Becker <becker@scyld.com>
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Subject: Re: NAPI for eepro100
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On Wed, 12 Jun 2002, David S. Miller wrote:
>    From: Jeff Garzik <jgarzik@mandrakesoft.com>
>    Oh crap, you're right...   eepro100 in general does funky stuff with the
>    way packets are handled, mainly due to the need to issue commands to the
>    NIC engine instead of the normal per-descriptor owner bit way of doing
>    things.

The eepro100 has a unique design in many different aspects.

> The question is, do the descriptor bits have to live right before
> the RX packet data buffer or can other schemes be used?

With the current driver structure, yes, the descriptor words must be
immediately before the packet data.  You can use other Rx and Tx
structures/modes to avoid this, but they use less efficient memory access.
For instance, the current Tx structure allows transmitting a packet with
a single PCI burst, rather than multiple transfers.


-- 
Donald Becker				becker@scyld.com
Scyld Computing Corporation		http://www.scyld.com
410 Severn Ave. Suite 210		Second Generation Beowulf Clusters
Annapolis MD 21403			410-990-9993


From owner-linux-mips@oss.sgi.com Thu Jun 13 00:17:32 2002
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From: xcd4u@yahoo.de
To: <linux-mips@oss.sgi.com>
Cc: 
Subject: Falls du Kinder hast - wichtig! Gegen Gewalt am Computer!
Date: Donnerstag, 13 Juni 2002 06:03:33 0100
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Hi du!

Hab noch irgendwo am Computer deine Mailadresse gefunden. Will dir auch nicht weiter deine Zeit stehlen - wollte dich nur auf eine, wie ich finde, wichtige Initiative aufmerksam machen:

http://www.netkids.info  - gegen Gewalt im Internet

Kostet nichts - außer ein bißchen Zeit -  hilft aber ungemein falls man Kinder im Haushalt hat die am Computer surfen oder spielen. Mit diesem Gratisvideo ist es mir unglaublich leicht gefallen den Computer meiner Kinder so einzurichten daß sie wirklich nur Seiten sehen die für Sie geeignet sind.

Außerdem weiß ich jetzt endlich welche Spiele sie spielen - und ob die auch schon wirklich für ihr Alter gedacht sind! Das wars auch schon - außer vielleicht - wenn du jemanden kennst der auch Kinder hat - schick ihm doch bitte das Mail weiter.

Schöne Grüße aus Salzburg

Paula


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From: "Sam" <iskoo@ms45.hinet.net>
To: <linux-mips@oss.sgi.com>
Subject: # ld.script syntax
Date: Thu, 13 Jun 2002 16:13:11 +0800
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Hi everybody,

I try to find the relation about the setup of ramdisk initrd
>From the sample of Philp Nino, I found the ld.script.in on /arch/mips/
But I do not understand the syntax of ld script,
Does anybody tell me where to find the relevent document to understand the
file,

thanks all,
--Sam


====
OUTPUT_ARCH(mips)
ENTRY(kernel_entry)
SECTIONS
{
  /* Read-only sections, merged into text segment: */
  . = @@LOADADDR@@;
  .init          : { *(.init)  } =0
  .text      :
  {
    _ftext = . ;
    *(.text)
    *(.rodata)
    *(.rodata1)
    /* .gnu.warning sections are handled specially by elf32.em.  */
    *(.gnu.warning)
  } =0
  .kstrtab : { *(.kstrtab) }

  . = ALIGN(16);  /* Exception table */
  __start___ex_table = .;
  __ex_table : { *(__ex_table) }
  __stop___ex_table = .;

  __start___dbe_table = .; /* Exception table for data bus errors */
  __dbe_table : { *(__dbe_table) }
  __stop___dbe_table = .;

  __start___ksymtab = .; /* Kernel symbol table */
  __ksymtab : { *(__ksymtab) }
  __stop___ksymtab = .;

  _etext = .;

  . = ALIGN(8192);
  .data.init_task : { *(.data.init_task) }

  /* Startup code */
  . = ALIGN(4096);
  __init_begin = .;
  .text.init : { *(.text.init) }
  .data.init : { *(.data.init) }
  . = ALIGN(16);
  __setup_start = .;
  .setup.init : { *(.setup.init) }
  __setup_end = .;
  __initcall_start = .;
  .initcall.init : { *(.initcall.init) }
  __initcall_end = .;
  . = ALIGN(4096); /* Align double page for init_task_union */
  __init_end = .;

  . = ALIGN(4096);
  .data.page_aligned : { *(.data.idt) }

  . = ALIGN(32);
  .data.cacheline_aligned : { *(.data.cacheline_aligned) }

  .fini      : { *(.fini)    } =0
  .reginfo : { *(.reginfo) }
  /* Adjust the address for the data segment.  We want to adjust up to
     the same address within the page on the next page up.  It would
     be more correct to do this:
       . = .;
     The current expression does not correctly handle the case of a
     text segment ending precisely at the end of a page; it causes the
     data segment to skip a page.  The above expression does not have
     this problem, but it will currently (2/95) cause BFD to allocate
     a single segment, combining both text and data, for this case.
     This will prevent the text segment from being shared among
     multiple executions of the program; I think that is more
     important than losing a page of the virtual address space (note
     that no actual memory is lost; the page which is skipped can not
     be referenced).  */
  . = .;
  .data    :
  {
    _fdata = . ;
    *(.data)

   /* Align the initial ramdisk image (INITRD) on page boundaries. */
   . = ALIGN(4096);
   __rd_start = .;
   *(.initrd)
   __rd_end = .;
   . = ALIGN(4096);

    CONSTRUCTORS
  }
  .data1   : { *(.data1) }
  _gp = . + 0x8000;
  .lit8 : { *(.lit8) }
  .lit4 : { *(.lit4) }
  .ctors         : { *(.ctors)   }
  .dtors         : { *(.dtors)   }
  .got           : { *(.got.plt) *(.got) }
  .dynamic       : { *(.dynamic) }
  /* We want the small data sections together, so single-instruction offsets
     can access them all, and initialized data all before uninitialized, so
     we can shorten the on-disk segment size.  */
  .sdata     : { *(.sdata) }
  . = ALIGN(4);
  _edata  =  .;
  PROVIDE (edata = .);

  __bss_start = .;
  _fbss = .;
  .sbss      : { *(.sbss) *(.scommon) }
  .bss       :
  {
   *(.dynbss)
   *(.bss)
   *(COMMON)
   .  = ALIGN(4);
  _end = . ;
  PROVIDE (end = .);
  }

  /* Sections to be discarded */
  /DISCARD/ :
  {
        *(.text.exit)
        *(.data.exit)
        *(.exitcall.exit)
  }

  /* This is the MIPS specific mdebug section.  */
  .mdebug : { *(.mdebug) }
  /* These are needed for ELF backends which have not yet been
     converted to the new style linker.  */
  .stab 0 : { *(.stab) }
  .stabstr 0 : { *(.stabstr) }
  /* DWARF debug sections.
     Symbols in the .debug DWARF section are relative to the beginning of
the
     section so we begin .debug at 0.  It's not clear yet what needs to
happen
     for the others.   */
  .debug          0 : { *(.debug) }
  .debug_srcinfo  0 : { *(.debug_srcinfo) }
  .debug_aranges  0 : { *(.debug_aranges) }
  .debug_pubnames 0 : { *(.debug_pubnames) }
  .debug_sfnames  0 : { *(.debug_sfnames) }
  .line           0 : { *(.line) }
  /* These must appear regardless of  .  */
  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
  .comment : { *(.comment) }
  .note : { *(.note) }
}
====




From owner-linux-mips@oss.sgi.com Thu Jun 13 01:26:00 2002
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From: Keith Owens <kaos@sgi.com>
To: "Sam" <iskoo@ms45.hinet.net>
Cc: linux-mips@oss.sgi.com
Subject: Re: # ld.script syntax 
In-reply-to: Your message of "Thu, 13 Jun 2002 16:13:11 +0800."
             <004801c212b2$295c7900$780411ac@sam> 
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On Thu, 13 Jun 2002 16:13:11 +0800, 
"Sam" <iskoo@ms45.hinet.net> wrote:
>I try to find the relation about the setup of ramdisk initrd
>From the sample of Philp Nino, I found the ld.script.in on /arch/mips/
>But I do not understand the syntax of ld script,
>Does anybody tell me where to find the relevent document to understand the
>file,

info ld, option 'Scripts'.


From owner-linux-mips@oss.sgi.com Thu Jun 13 01:27:21 2002
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Date: Thu, 13 Jun 2002 10:29:49 +0200
From: Guido Guenther <agx@sigxcpu.org>
To: Sam <iskoo@ms45.hinet.net>
Cc: linux-mips@oss.sgi.com
Subject: Re: # ld.script syntax
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On Thu, Jun 13, 2002 at 04:13:11PM +0800, Sam wrote:
> Hi everybody,
> 
> I try to find the relation about the setup of ramdisk initrd
> >From the sample of Philp Nino, I found the ld.script.in on /arch/mips/
> But I do not understand the syntax of ld script,
> Does anybody tell me where to find the relevent document to understand the
> file,
"info ld". See section "Scripts".
Hope this helps,
 -- Guido

From owner-linux-mips@oss.sgi.com Thu Jun 13 01:45:55 2002
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Date: Thu, 13 Jun 2002 12:57:53 +0400
From: Andrey Savochkin <saw@saw.sw.com.sg>
To: "David S. Miller" <davem@redhat.com>
Cc: fxzhang@ict.ac.cn, linux-mips@oss.sgi.com, linux-kernel@vger.kernel.org,
   netdev@oss.sgi.com, jgarzik@mandrakesoft.com
Subject: Re: NAPI for eepro100
References: <3D0740ED.2060907@ict.ac.cn> <3D07D270.5060902@mandrakesoft.com> <20020612.160532.134201977.davem@redhat.com>
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On Wed, Jun 12, 2002 at 04:05:32PM -0700, David S. Miller wrote:
>    From: Jeff Garzik <jgarzik@mandrakesoft.com>
>    Date: Wed, 12 Jun 2002 19:00:00 -0400
>    
>    for the 'mips' patch, it looks 
>    like the arch maintainer(s) need to fix the PCI DMA support...
> 
> No, it's worse than that.
> 
> See how non-consistent memory is used by the eepro100 driver
> for descriptor bits?  The skb->tail bits?
> 
> That is very problematic.

What's the problem?
If it isn't allowed to do, then what is the meaning of PCI_DMA_BIDIRECTIONAL
mappings?

	Andrey

From owner-linux-mips@oss.sgi.com Thu Jun 13 01:49:04 2002
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Cc: fxzhang@ict.ac.cn, linux-mips@oss.sgi.com, linux-kernel@vger.kernel.org,
   netdev@oss.sgi.com, jgarzik@mandrakesoft.com
Subject: Re: NAPI for eepro100
From: "David S. Miller" <davem@redhat.com>
In-Reply-To: <20020613125753.A23693@castle.nmd.msu.ru>
References: <3D07D270.5060902@mandrakesoft.com>
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   From: Andrey Savochkin <saw@saw.sw.com.sg>
   Date: Thu, 13 Jun 2002 12:57:53 +0400

   On Wed, Jun 12, 2002 at 04:05:32PM -0700, David S. Miller wrote:
   > No, it's worse than that.
   > 
   > See how non-consistent memory is used by the eepro100 driver
   > for descriptor bits?  The skb->tail bits?
   > 
   > That is very problematic.
   
   What's the problem?
   If it isn't allowed to do, then what is the meaning of PCI_DMA_BIDIRECTIONAL
   mappings?

It's slow.  Not wrong, just inefficient.

Descriptors were meant to be done using consistent mappings, not
"pci_map_*()"'d memory.  The latter is meant to be used for long
linear DMA transfers to/from the device.  It is not meant for things
the cpu pokes small bits of data in and out of, that is what
consistent DMA memory is for.

From owner-linux-mips@oss.sgi.com Thu Jun 13 05:36:34 2002
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To: linux-mips@oss.sgi.com, saw@saw.sw.com.sg, linux-kernel@vger.kernel.org
Subject: NAPI for eepro100
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--------------070502030508090306010005
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hi,all
   Recently i've converted eepro100 driver to use napi,in order to improve
network performance of my poor 150M mips machine. It does eliminate
the interrupt live lock seen before,maintaining a peak throughput under
heavy load.
  In case anybody are interested,i post the patches to the list. They are
3 incremental patchs:
   eepro100-napi.patch is against 2.5.20 eepro100.c and provide basic
napi support
   eepro100-proc.patch is proc file system support adapted from intel's
e100 driver. I am using it for debugging.
   eepro100-mips.patch is mips specific patch to make it work(well) for 
my mips
platform.
(i suppose people use: patch eepro100.c < x.patch to apply patch)

   Tests are mainly done on my mips machine for 2.4 kernel,though i think
 it should work for at least x86 on which minimal test is performed. Be 
careful.

   A little pitty is that to achieve good performance under heavy load, the
/proc/sys/net/core/netdev_max_backlog value may need to be adjusted.
   
  Feedbacks are always welcome:). But i am not on linux-kernel list,so 
people
there please CC me.

--------------070502030508090306010005
Content-Type: text/plain;
 name="eepro100-mips.patch"
Content-Transfer-Encoding: 7bit
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 filename="eepro100-mips.patch"

--- eepro100-napi-proc.c	Wed Jun 12 17:33:51 2002
+++ eepro100-mips.c	Wed Jun 12 19:22:29 2002
@@ -45,7 +45,7 @@
 
 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx method.
    Lower values use more memory, but are faster. */
-#if defined(__alpha__) || defined(__sparc__) || defined(__mips__) || \
+#if defined(__alpha__) || defined(__sparc__) || /*defined(__mips__) ||*/ \
     defined(__arm__)
 static int rx_copybreak = 1518;
 #else
@@ -66,8 +66,8 @@
 
 /* A few values that may be tweaked. */
 /* The ring sizes should be a power of two for efficiency. */
-#define TX_RING_SIZE	64
-#define RX_RING_SIZE	64
+#define TX_RING_SIZE	32
+#define RX_RING_SIZE	32
 /* How much slots multicast filter setup may take.
    Do not descrease without changing set_rx_mode() implementaion. */
 #define TX_MULTICAST_SIZE   2
@@ -1298,7 +1298,14 @@
 		if (skb == NULL)
 			break;			/* OK.  Just initially short of Rx bufs. */
 		skb->dev = dev;			/* Mark as being used by this device. */
+#ifndef __mips__
 		rxf = (struct RxFD *)skb->tail;
+#else
+		/* use uncached address,use pci_dma_sync_xx seems 
+		 * problematic in my mips platform
+		 */
+		rxf = (struct RxFD *)(KSEG1ADDR(skb->tail));
+#endif
 		sp->rx_ringp[i] = rxf;
 		sp->rx_ring_dma[i] =
 			pci_map_single(sp->pdev, rxf,
@@ -1306,8 +1313,10 @@
 		skb_reserve(skb, sizeof(struct RxFD));
 		if (last_rxf) {
 			last_rxf->link = cpu_to_le32(sp->rx_ring_dma[i]);
+#ifndef __mips__
 			pci_dma_sync_single(sp->pdev, last_rxf_dma,
 					sizeof(struct RxFD), PCI_DMA_TODEVICE);
+#endif
 		}
 		last_rxf = rxf;
 		last_rxf_dma = sp->rx_ring_dma[i];
@@ -1316,14 +1325,18 @@
 		/* This field unused by i82557. */
 		rxf->rx_buf_addr = 0xffffffff;
 		rxf->count = cpu_to_le32(PKT_BUF_SZ << 16);
+#ifndef __mips__
 		pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[i],
 				sizeof(struct RxFD), PCI_DMA_TODEVICE);
+#endif
 	}
 	sp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
 	/* Mark the last entry as end-of-list. */
 	last_rxf->status = cpu_to_le32(0xC0000002);	/* '2' is flag value only. */
+#ifndef __mips__
 	pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[RX_RING_SIZE-1],
 			sizeof(struct RxFD), PCI_DMA_TODEVICE);
+#endif
 	sp->last_rxf = last_rxf;
 	sp->last_rxf_dma = last_rxf_dma;
 }
@@ -1733,15 +1746,21 @@
 #endif
 		return NULL;
 	}
+#ifndef __mips__
 	rxf = sp->rx_ringp[entry] = (struct RxFD *)skb->tail;
+#else
+	rxf = sp->rx_ringp[entry] = (struct RxFD *)(KSEG1ADDR(skb->tail));
+#endif
 	sp->rx_ring_dma[entry] =
 		pci_map_single(sp->pdev, rxf,
 					   PKT_BUF_SZ + sizeof(struct RxFD), PCI_DMA_FROMDEVICE);
 	skb->dev = dev;
 	skb_reserve(skb, sizeof(struct RxFD));
 	rxf->rx_buf_addr = 0xffffffff;
+#ifndef __mips__
 	pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[entry],
 			sizeof(struct RxFD), PCI_DMA_TODEVICE);
+#endif
 	return rxf;
 }
 
@@ -1754,8 +1773,10 @@
 	rxf->count = cpu_to_le32(PKT_BUF_SZ << 16);
 	sp->last_rxf->link = cpu_to_le32(rxf_dma);
 	sp->last_rxf->status &= cpu_to_le32(~0xC0000000);
+#ifndef __mips__
 	pci_dma_sync_single(sp->pdev, sp->last_rxf_dma,
 			sizeof(struct RxFD), PCI_DMA_TODEVICE);
+#endif
 	sp->last_rxf = rxf;
 	sp->last_rxf_dma = rxf_dma;
 }
@@ -2274,8 +2295,10 @@
 		int status;
 		int pkt_len;
 
+#ifndef __mips__
 		pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[entry],
 			sizeof(struct RxFD), PCI_DMA_FROMDEVICE);
+#endif
 		status = le32_to_cpu(sp->rx_ringp[entry]->status);
 		pkt_len = le32_to_cpu(sp->rx_ringp[entry]->count) & 0x3fff;
 

--------------070502030508090306010005
Content-Type: text/plain;
 name="eepro100-napi.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="eepro100-napi.patch"

--- eepro100.c.ori	Wed Jun 12 17:25:28 2002
+++ eepro100-napi.c	Wed Jun 12 17:11:38 2002
@@ -25,6 +25,8 @@
 		Disabled FC and ER, to avoid lockups when when we get FCP interrupts.
 	2000 Jul 17 Goutham Rao <goutham.rao@intel.com>
 		PCI DMA API fixes, adding pci_dma_sync_single calls where neccesary
+	2002 Jun 12 Zhang Fuxin <fxzhang@ict.ac.cn>
+		add NAPI support
 */
 
 static const char *version =
@@ -115,6 +117,8 @@
 #include <linux/skbuff.h>
 #include <linux/ethtool.h>
 
+#define CONFIG_EEPRO100_NAPI
+
 MODULE_AUTHOR("Maintainer: Andrey V. Savochkin <saw@saw.sw.com.sg>");
 MODULE_DESCRIPTION("Intel i82557/i82558/i82559 PCI EtherExpressPro driver");
 MODULE_LICENSE("GPL");
@@ -494,8 +498,34 @@
 #ifdef CONFIG_PM
 	u32 pm_state[16];
 #endif
+
+	/* added by zfx for NAPI*/
+#ifdef CONFIG_EEPRO100_NAPI
+
+	/* used to pass rx_work_limit into speedo_rx,i don't want to 
+	 * change its prototype
+	 */
+	int curr_work_limit;
+	unsigned long poll_switch;
+	unsigned long failed_poll_switch;
+	unsigned long done_poll;
+	unsigned long notdone_poll;
+	unsigned long empty_poll;
+	unsigned long soft_reset_count;
+	unsigned long rx_resume_count;
+	unsigned long alloc_fail;
+	unsigned long long poll_cycles;
+
+#ifdef CONFIG_NET_FASTROUTE
+	unsigned long fastroute_hit;
+	unsigned long fastroute_success;
+	unsigned long fastroute_defer;
+#endif
+
+#endif
 };
 
+
 /* The parameters for a CmdConfigure operation.
    There are so many options that it would be difficult to document each bit.
    We mostly use the default or recommended settings. */
@@ -546,6 +576,14 @@
 static void set_rx_mode(struct net_device *dev);
 static void speedo_show_state(struct net_device *dev);
 
+#ifdef CONFIG_EEPRO100_NAPI
+
+static int speedo_poll (struct net_device *dev, int *budget);
+static void enable_rx_and_rxnobuf_ints(struct net_device *dev);
+static void disable_rx_and_rxnobuf_ints(struct net_device *dev);
+
+#endif
+
 
 
 #ifdef honor_default_port
@@ -842,6 +880,10 @@
 	dev->set_multicast_list = &set_rx_mode;
 	dev->do_ioctl = &speedo_ioctl;
 
+#ifdef CONFIG_EEPRO100_NAPI
+	dev->poll = speedo_poll;
+	dev->quota = dev->weight = RX_RING_SIZE;
+#endif
 	return 0;
 }
 
@@ -1517,6 +1559,9 @@
 	struct speedo_private *sp;
 	long ioaddr, boguscnt = max_interrupt_work;
 	unsigned short status;
+#ifdef CONFIG_EEPRO100_NAPI
+	int first = 1;
+#endif
 
 #ifndef final_version
 	if (dev == NULL) {
@@ -1543,16 +1588,21 @@
 		/* Acknowledge all of the current interrupt sources ASAP. */
 		/* Will change from 0xfc00 to 0xff00 when we start handling
 		   FCP and ER interrupts --Dragan */
+#ifndef CONFIG_EEPRO100_NAPI
 		outw(status & 0xfc00, ioaddr + SCBStatus);
+#else
+		/* Rx & RxNoBuf is acked in speedo_poll */
+		outw(status & 0xac00, ioaddr + SCBStatus);
+#endif
 
 		if (speedo_debug > 4)
 			printk(KERN_DEBUG "%s: interrupt  status=%#4.4x.\n",
 				   dev->name, status);
 
+#ifndef CONFIG_EEPRO100_NAPI
 		if ((status & 0xfc00) == 0)
 			break;
 
-
 		if ((status & 0x5000) ||	/* Packet received, or Rx error. */
 			(sp->rx_ring_state&(RrNoMem|RrPostponed)) == RrPostponed)
 									/* Need to gather the postponed packet. */
@@ -1560,8 +1610,33 @@
 
 		/* Always check if all rx buffers are allocated.  --SAW */
 		speedo_refill_rx_buffers(dev, 0);
+#else
+		/* Packet received, or Rx error. */
+		if (first && ((status & 0x5000) || (sp->rx_ring_state&(RrNoMem|RrPostponed)) == RrPostponed || (status & 0x3c) != 0x10 ))
+			/* Need to gather the postponed packet. */
+		{
+			if (speedo_debug > 4) 
+				printk("switching to poll,status=%x\n",status);
+			first = 0;
+			if (netif_rx_schedule_prep(dev)) {
+				sp->poll_switch++;
+				/* disable interrupts caused by arriving packets */
+				disable_rx_and_rxnobuf_ints(dev);
+				/* tell system we have work to be done. */
+				__netif_rx_schedule(dev);
+			}else {
+				sp->failed_poll_switch++;
+			}
+
+		}
+
+		if ((status & 0xac00) == 0)
+			break;
+#endif
 		
 		spin_lock(&sp->lock);
+
+#ifndef CONFIG_EEPRO100_NAPI
 		/*
 		 * The chip may have suspended reception for various reasons.
 		 * Check for that, and re-prime it should this be the case.
@@ -1581,7 +1656,7 @@
 			/* these are all reserved values */
 			break;
 		}
-		
+#endif
 		
 		/* User interrupt, Command/Tx unit interrupt or CU not active. */
 		if (status & 0xA400) {
@@ -1602,7 +1677,12 @@
 			/* Clear all interrupt sources. */
 			/* Will change from 0xfc00 to 0xff00 when we start handling
 			   FCP and ER interrupts --Dragan */
+#ifndef CONFIG_EEPRO100_NAPI
 			outw(0xfc00, ioaddr + SCBStatus);
+#else
+			outw(0xac00, ioaddr + SCBStatus);
+#endif
+
 			break;
 		}
 	} while (1);
@@ -1611,7 +1691,9 @@
 		printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
 			   dev->name, inw(ioaddr + SCBStatus));
 
+#ifndef final_version
 	clear_bit(0, (void*)&sp->in_interrupt);
+#endif
 	return;
 }
 
@@ -1625,6 +1707,9 @@
 	sp->rx_skbuff[entry] = skb;
 	if (skb == NULL) {
 		sp->rx_ringp[entry] = NULL;
+#ifdef CONFIG_EEPRO100_NAPI
+		sp->alloc_fail++;
+#endif
 		return NULL;
 	}
 	rxf = sp->rx_ringp[entry] = (struct RxFD *)skb->tail;
@@ -1705,12 +1790,112 @@
 			speedo_refill_rx_buf(dev, force) != -1);
 }
 
+#ifdef CONFIG_EEPRO100_NAPI
+static void enable_rx_and_rxnobuf_ints(struct net_device *dev)
+{
+	long ioaddr = dev->base_addr;
+	outw(SCBMaskEarlyRx | SCBMaskFlowCtl, ioaddr + SCBCmd);
+	inw(ioaddr + SCBStatus); /* flushes last write, read-safe */
+};
+
+static void disable_rx_and_rxnobuf_ints(struct net_device *dev)
+{
+	long ioaddr = dev->base_addr;
+	outw(SCBMaskRxDone | SCBMaskRxSuspend | SCBMaskEarlyRx | SCBMaskFlowCtl, ioaddr + SCBCmd);
+	inw(ioaddr + SCBStatus); /* flushes last write, read-safe */
+};
+
+static int speedo_poll (struct net_device *dev, int *budget)
+{
+	struct speedo_private *sp = (struct speedo_private *)dev->priv;
+	long ioaddr, received = 0;
+	unsigned short intr_status;
+
+	ioaddr = dev->base_addr;
+	intr_status = inw(ioaddr + SCBStatus);
+
+	if (speedo_debug > 4)
+		printk(KERN_DEBUG " In speedo_poll().\n");
+
+	sp->curr_work_limit = *budget;
+	if (sp->curr_work_limit > dev->quota) 
+		sp->curr_work_limit = dev->quota;
+
+	do {  
+		/* ack Rx & RxNobuf intrs*/
+		outw(intr_status & 0x5000, ioaddr + SCBStatus);
+
+		received += speedo_rx(dev);
+
+		if (sp->curr_work_limit < 0) /* out of quota */
+			goto not_done;
+
+		/* no packets on ring; but new ones can arrive since we last checked  */
+		intr_status = inw(ioaddr + SCBStatus);
+
+		if ((intr_status & 0x5000) == 0) {
+			/* If something arrives in this narrow window,an interrupt 
+			 * will be generated 
+			 */
+			goto done;
+		}
+		/* done! at least thats what it looks like ;->
+		   if new packets came in after our last check on status bits
+		   they'll be caught by the while check and we go back and clear them
+		   since we havent exceeded our quota 
+		 */
+	} while (intr_status & 0x5000);
+
+done:
+	if (!received) {
+		if (speedo_debug > 4) printk("received==0\n");
+		received = 1;
+		sp->empty_poll++;
+	}
+	dev->quota -= received;
+	*budget -= received;
+
+	/* we are happy/done, no more packets on ring; put us back
+	 * to where we can start processing interrupts again 
+	 */
+	netif_rx_complete(dev);
+	enable_rx_and_rxnobuf_ints(dev);
+
+	sp->done_poll++;
+
+	if (speedo_debug > 3)
+		printk("done,received=%lu\n",received);
+
+        return 0;   /* done */
+
+not_done:
+	if (!received) {
+		if (speedo_debug > 4) printk("received==0\n");
+		received = 1;
+		sp->empty_poll++;
+	}
+	dev->quota -= received;
+	*budget -= received;
+
+	sp->notdone_poll++;
+
+	if (speedo_debug > 3)
+		printk("not done,received=%lu\n",received);
+
+	return 1;  /* not_done */
+}
+
+#endif /* NAPI */
+
 static int
 speedo_rx(struct net_device *dev)
 {
 	struct speedo_private *sp = (struct speedo_private *)dev->priv;
 	int entry = sp->cur_rx % RX_RING_SIZE;
+#ifndef CONFIG_EEPRO100_NAPI
 	int rx_work_limit = sp->dirty_rx + RX_RING_SIZE - sp->cur_rx;
+#endif
+	int received = 0;
 	int alloc_ok = 1;
 
 	if (speedo_debug > 4)
@@ -1725,11 +1910,42 @@
 		status = le32_to_cpu(sp->rx_ringp[entry]->status);
 		pkt_len = le32_to_cpu(sp->rx_ringp[entry]->count) & 0x3fff;
 
+#ifndef CONFIG_EEPRO100_NAPI
 		if (!(status & RxComplete))
 			break;
 
 		if (--rx_work_limit < 0)
 			break;
+#else
+		if (!(status & RxComplete)) {
+			int intr_status;
+			unsigned long ioaddr = dev->base_addr;
+
+			intr_status = inw(ioaddr + SCBStatus);
+			/* We check receiver state here because if 
+			 * we have to do soft reset,sp->cur_rx should
+			 * point to an empty entry or something 
+			 * unexpected will happen
+			 */
+			if (intr_status | 0x1000) { /* suspended */
+				outw(0x5000,ioaddr + SCBStatus);
+				/* No resources */
+				if ((intr_status & 0x3c) == 0x28) {
+					outw(RxResumeNoResources,ioaddr+SCBCmd);
+					sp->rx_resume_count++;
+				}else if ((intr_status & 0x3c) == 0x8) {
+					if (speedo_debug > 4) 
+						printk("No resource,reset\n");
+					speedo_rx_soft_reset(dev);
+					sp->soft_reset_count++;
+				}
+			}
+			break;
+		}
+
+		if (--sp->curr_work_limit < 0) 
+			break;
+#endif
 
 		/* Check for a rare out-of-memory case: the current buffer is
 		   the last buffer allocated in the RX ring.  --SAW */
@@ -1793,7 +2009,12 @@
 						PKT_BUF_SZ + sizeof(struct RxFD), PCI_DMA_FROMDEVICE);
 			}
 			skb->protocol = eth_type_trans(skb, dev);
+#ifndef CONFIG_EEPRO100_NAPI
 			netif_rx(skb);
+#else
+			netif_receive_skb(skb);
+			received ++;
+#endif
 			dev->last_rx = jiffies;
 			sp->stats.rx_packets++;
 			sp->stats.rx_bytes += pkt_len;
@@ -1811,7 +2032,7 @@
 
 	sp->last_rx_time = jiffies;
 
-	return 0;
+	return received;
 }
 
 static int

--------------070502030508090306010005
Content-Type: text/plain;
 name="eepro100-proc.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="eepro100-proc.patch"

--- eepro100-napi.c	Wed Jun 12 17:11:38 2002
+++ eepro100-napi-proc.c	Wed Jun 12 17:33:51 2002
@@ -119,6 +119,10 @@
 
 #define CONFIG_EEPRO100_NAPI
 
+#ifdef CONFIG_PROC_FS
+#include <linux/proc_fs.h>
+#endif
+
 MODULE_AUTHOR("Maintainer: Andrey V. Savochkin <saw@saw.sw.com.sg>");
 MODULE_DESCRIPTION("Intel i82557/i82558/i82559 PCI EtherExpressPro driver");
 MODULE_LICENSE("GPL");
@@ -516,6 +520,10 @@
 	unsigned long alloc_fail;
 	unsigned long long poll_cycles;
 
+#ifdef CONFIG_PROC_FS
+	struct proc_dir_entry *proc_parent;
+#endif
+
 #ifdef CONFIG_NET_FASTROUTE
 	unsigned long fastroute_hit;
 	unsigned long fastroute_success;
@@ -582,6 +590,11 @@
 static void enable_rx_and_rxnobuf_ints(struct net_device *dev);
 static void disable_rx_and_rxnobuf_ints(struct net_device *dev);
 
+#ifdef CONFIG_PROC_FS
+int __devinit speedo_create_proc_subdir(struct net_device *sp);
+void speedo_remove_proc_subdir(struct net_device *sp);
+#endif
+
 #endif
 
 
@@ -883,6 +896,14 @@
 #ifdef CONFIG_EEPRO100_NAPI
 	dev->poll = speedo_poll;
 	dev->quota = dev->weight = RX_RING_SIZE;
+
+#ifdef CONFIG_PROC_FS
+	if (speedo_create_proc_subdir(dev) < 0) {
+		printk(KERN_ERR "Failed to create proc directory for %s\n",
+				dev->name);
+	}              
+#endif
+
 #endif
 	return 0;
 }
@@ -1885,6 +1906,354 @@
 	return 1;  /* not_done */
 }
 
+#ifdef CONFIG_PROC_FS
+/* adapted from intel's e100 code */
+static struct proc_dir_entry *adapters_proc_dir = 0;
+
+static void speedo_proc_cleanup(void);
+static unsigned char speedo_init_proc_dir(void);
+
+#define ADAPTERS_PROC_DIR "eepro100"
+#define WRITE_BUF_MAX_LEN 20	
+#define READ_BUF_MAX_LEN  256
+#define SPEEDO_PE_LEN       25
+
+#define sp_off(off) (unsigned long)(offsetof(struct speedo_private, off))
+
+typedef struct _speedo_proc_entry {
+	char *name;
+	read_proc_t *read_proc;
+	write_proc_t *write_proc;
+	unsigned long offset;	/* offset into sp. ~0 means no value, pass NULL. */
+} speedo_proc_entry;
+
+static int
+generic_read(char *page, char **start, off_t off, int count, int *eof, int len)
+{
+	if (len <= off + count)
+		*eof = 1;
+
+	*start = page + off;
+	len -= off;
+	if (len > count)
+		len = count;
+
+	if (len < 0)
+		len = 0;
+
+	return len;
+}
+
+static int
+read_ulong(char *page, char **start, off_t off,
+	   int count, int *eof, unsigned long l)
+{
+	int len;
+
+	len = sprintf(page, "%lu\n", l);
+
+	return generic_read(page, start, off, count, eof, len);
+}
+
+static int
+read_gen_ulong(char *page, char **start, off_t off,
+	       int count, int *eof, void *data)
+{
+	unsigned long val = 0;
+
+	if (data)
+		val = *((unsigned long *) data);
+
+	return read_ulong(page, start, off, count, eof, val);
+}
+
+static int
+read_ulonglong(char *page, char **start, off_t off,
+	   int count, int *eof, unsigned long long ll)
+{
+	int len;
+
+	len = sprintf(page, "%llu\n", ll);
+
+	return generic_read(page, start, off, count, eof, len);
+}
+
+static int
+read_gen_ulonglong(char *page, char **start, off_t off,
+	       int count, int *eof, void *data)
+{
+	unsigned long val = 0;
+
+	if (data)
+		val = *((unsigned long long *) data);
+
+	return read_ulonglong(page, start, off, count, eof, val);
+}
+
+static int
+set_debug(struct file *file, const char *buffer,
+		    unsigned long count, void *data)
+
+{
+	if (speedo_debug == 1) 
+		speedo_debug = 6;
+	else
+		speedo_debug = 1;
+	return count;
+}
+
+static int
+_speedo_show_state(struct file *file, const char *buffer,
+		    unsigned long count, void *data)
+{
+	
+	struct net_device *dev = (struct net_device *)data;
+
+	speedo_show_state(dev);
+
+	return count;
+}
+
+static speedo_proc_entry speedo_proc_list[] = {
+	{"set_debug", 0, set_debug, ~0},
+	{"show_state", 0, _speedo_show_state, ~0},
+	{"poll_switch",read_gen_ulong,0,sp_off(poll_switch)},
+	{"failed_poll_switch",read_gen_ulong,0,sp_off(failed_poll_switch)},
+	{"done_poll",read_gen_ulong,0,sp_off(done_poll)},
+	{"notdone_poll",read_gen_ulong,0,sp_off(notdone_poll)},
+	{"empty_poll",read_gen_ulong,0,sp_off(empty_poll)},
+	{"soft_reset_count",read_gen_ulong,0,sp_off(soft_reset_count)},
+	{"rx_resume_count",read_gen_ulong,0,sp_off(rx_resume_count)},
+	{"alloc_fail",read_gen_ulong,0,sp_off(alloc_fail)},
+	{"poll_cycles",read_gen_ulonglong,0,sp_off(poll_cycles)},
+	{"fastroute_hit",read_gen_ulonglong,0,sp_off(fastroute_hit)},
+	{"fastroute_success",read_gen_ulonglong,0,sp_off(fastroute_success)},
+	{"fastroute_defer",read_gen_ulonglong,0,sp_off(fastroute_defer)},
+	{"", 0, 0, 0}
+};
+
+static int
+read_info(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+	struct speedo_private *sp = data;
+	speedo_proc_entry *pe;
+	int tmp;
+	void *val;
+	int len = 0;
+
+	for (pe = speedo_proc_list; pe->name[0]; pe++) {
+		if (pe->name[0] == '\n') {
+			len += sprintf(page + len, "\n");
+			continue;
+		}
+
+		if (pe->read_proc) {
+			if ((len + READ_BUF_MAX_LEN + SPEEDO_PE_LEN + 1) >=
+			    PAGE_SIZE)
+				break;
+
+			if (pe->offset != ~0)
+				val = ((char *) sp) + pe->offset;
+			else
+				val = NULL;
+
+			len += sprintf(page + len, "%-"
+				       __MODULE_STRING(SPEEDO_PE_LEN)
+				       "s ", pe->name);
+			len += pe->read_proc(page + len, start, 0,
+					     READ_BUF_MAX_LEN + 1, &tmp, val);
+		}
+	}
+
+	return generic_read(page, start, off, count, eof, len);
+}
+
+static struct proc_dir_entry * __devinit
+create_proc_rw(char *name, void *data, struct proc_dir_entry *parent,
+	       read_proc_t * read_proc, write_proc_t * write_proc)
+{
+	struct proc_dir_entry *pdep;
+	mode_t mode = S_IFREG;
+
+	if (write_proc) {
+		mode |= S_IWUSR;
+		if (read_proc) {
+			mode |= S_IRUSR;
+		}
+
+	} else if (read_proc) {
+		mode |= S_IRUGO;
+	}
+
+	if (!(pdep = create_proc_entry(name, mode, parent)))
+		return NULL;
+
+	pdep->read_proc = read_proc;
+	pdep->write_proc = write_proc;
+	pdep->data = data;
+	return pdep;
+}
+
+void
+speedo_remove_proc_subdir(struct net_device *dev)
+{
+	struct speedo_private *sp = (struct speedo_private *)dev->priv;
+	speedo_proc_entry *pe;
+	char info[256];
+	int len;
+
+	/* If our root /proc dir was not created, there is nothing to remove */
+	if (adapters_proc_dir == NULL) {
+		return;
+	}
+
+	len = strlen(dev->name);
+	strncpy(info, dev->name, sizeof (info));
+	strncat(info + len, ".info", sizeof (info) - len);
+
+	if (sp->proc_parent) {
+		for (pe = speedo_proc_list; pe->name[0]; pe++) {
+			if (pe->name[0] == '\n')
+				continue;
+
+			remove_proc_entry(pe->name, sp->proc_parent);
+		}
+
+		remove_proc_entry(dev->name, adapters_proc_dir);
+		sp->proc_parent = NULL;
+	}
+
+	remove_proc_entry(info, adapters_proc_dir);
+
+	/* try to remove the main /proc dir, if it's empty */
+	speedo_proc_cleanup();
+}
+
+int __devinit
+speedo_create_proc_subdir(struct net_device *dev)
+{
+	struct speedo_private *sp = (struct speedo_private *)dev->priv;
+	struct proc_dir_entry *dev_dir;
+	speedo_proc_entry *pe;
+	char info[256];
+	int len;
+	void *data;
+
+	/* create the main /proc dir if needed */
+	if (!adapters_proc_dir) {
+		if (!speedo_init_proc_dir())
+			return -ENOMEM;
+	}
+
+	strncpy(info, dev->name, sizeof (info));
+	len = strlen(info);
+	strncat(info + len, ".info", sizeof (info) - len);
+
+	/* info */
+	if (!(create_proc_rw(info, sp, adapters_proc_dir, read_info, 0))) {
+		speedo_proc_cleanup();
+		return -ENOMEM;
+	}
+
+	dev_dir = create_proc_entry(dev->name, S_IFDIR,
+				    adapters_proc_dir);
+	sp->proc_parent = dev_dir;
+
+	if (!dev_dir) {
+		speedo_remove_proc_subdir(dev);
+		return -ENOMEM;
+	}
+
+	for (pe = speedo_proc_list; pe->name[0]; pe++) {
+		if (pe->name[0] == '\n')
+			continue;
+
+		if (pe->offset != ~0)
+			data = ((char *) sp) + pe->offset;
+		else
+			data = dev;
+
+		if (!(create_proc_rw(pe->name, data, dev_dir,
+				     pe->read_proc, pe->write_proc))) {
+			speedo_remove_proc_subdir(dev);
+			return -ENOMEM;
+		}
+	}
+
+	return 0;
+}
+
+/****************************************************************************
+ * Name:          speedo_init_proc_dir
+ *
+ * Description:   This routine creates the top-level /proc directory for the
+ *                driver in /proc/net
+ *
+ * Arguments:     none
+ *
+ * Returns:       true on success, false on fail
+ *
+ ***************************************************************************/
+static unsigned char
+speedo_init_proc_dir(void)
+{
+	int len;
+
+	/* first check if adapters_proc_dir already exists */
+	len = strlen(ADAPTERS_PROC_DIR);
+	for (adapters_proc_dir = proc_net->subdir;
+	     adapters_proc_dir; adapters_proc_dir = adapters_proc_dir->next) {
+
+		if ((adapters_proc_dir->namelen == len) &&
+		    (!memcmp(adapters_proc_dir->name, ADAPTERS_PROC_DIR, len)))
+			break;
+	}
+
+	if (!adapters_proc_dir)
+		adapters_proc_dir =
+			create_proc_entry(ADAPTERS_PROC_DIR, S_IFDIR, proc_net);
+
+	if (!adapters_proc_dir)
+		return 0;
+
+	return 1;
+}
+
+/****************************************************************************
+ * Name:          speedo_proc_cleanup
+ *
+ * Description:   This routine clears the top-level /proc directory, if empty.
+ *
+ * Arguments:     none
+ *
+ * Returns:       none
+ *
+ ***************************************************************************/
+static void
+speedo_proc_cleanup(void)
+{
+	struct proc_dir_entry *de;
+
+	if (adapters_proc_dir == NULL) {
+		return;
+	}
+
+	/* check if subdir list is empty before removing adapters_proc_dir */
+	for (de = adapters_proc_dir->subdir; de; de = de->next) {
+		/* ignore . and .. */
+		if (*(de->name) != '.')
+			break;
+	}
+
+	if (de)
+		return;
+
+	remove_proc_entry(ADAPTERS_PROC_DIR, proc_net);
+	adapters_proc_dir = NULL;
+}
+
+#endif /* CONFIG_PROC_FS */
+
 #endif /* NAPI */
 
 static int
@@ -2474,6 +2843,9 @@
 	
 	unregister_netdev(dev);
 
+#if defined(CONFIG_EEPRO100_NAPI) && defined(CONFIG_PROC_FS)
+	speedo_remove_proc_subdir(dev);
+#endif
 	release_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
 	release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
 

--------------070502030508090306010005--

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From owner-linux-mips@oss.sgi.com Thu Jun 13 12:06:15 2002
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Date: Thu, 13 Jun 2002 12:06:46 -0700
From: Tom Rini <trini@kernel.crashing.org>
To: Roman Zippel <zippel@linux-m68k.org>,
   Linux/MIPS Development <linux-mips@oss.sgi.com>,
   Linux/m68k <linux-m68k@lists.linux-m68k.org>,
   Linux/PPC Development <linuxppc-dev@lists.linuxppc.org>
Subject: [RFC and PATCH] Move the m68k genrtc driver into 2.5 and use on PPC
Message-ID: <20020613190646.GT13541@opus.bloom.county>
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Hello all.  A few months back yet another RTC thread was started.  I've
finally gotten around to trying to do something about the generic RTC
issue.  The following patch takes the m68k generic RTC driver
(drivers/char/genrtc.c) and drops it into 2.5.21, along with
include/asm-ppc/rtc.h with the needed inlines to get basic functionality
going.

My first question is to the MIPS people.  What did you end up doing in
the end about a 'generic' RTC driver?  Did you do something
quick-and-dirty ala drivers/macintosh/rtc.c or did you go and take the
m68k one?  If you did something other than take the m68k driver, did you
find any problems with genrtc.c that stopped you from using it?  Or was
it the generic code changes (include/linux/rtc.h)

Secondly to the m68k people, does anyone have an objection (or would
like to do it themselves?) with me trying to get Linus to take the
changes to include/linux/rtc.h?  radeonfb.c currently conflicts with the
'pll_info' struct, but Ani Joshi is renaming it.  Also, CONFIG_GEN_RTC
used to be define_bool'ed to y on CONFIG_SUN3, but I'm not sure if that
looks nice in a common file.  Any idea on how to solve this nicely?
(create arch/m68k/configs/*defconfig ala ppc or arch/m68k/defconfig-xxx
ala mips or arch/m68k/def-configs/ ala arm?)

And to everyone, while this patch is vs 2.5.21'ish, it should mostly
apply to 2.4.x, so please test this on your favorite arch (or for MIPS,
create <asm/rtc.h> and test :)) and get back to me.  What I'd like to
try and do in the end is perhaps replace drivers/char/rtc.c, but at a
miniumum, I'd like to kill off drivers/macintosh/rtc.c.

-- 
Tom Rini (TR1265)
http://gate.crashing.org/~trini/

diff -Nru a/drivers/char/Config.help b/drivers/char/Config.help
--- a/drivers/char/Config.help	Thu Jun 13 12:03:49 2002
+++ b/drivers/char/Config.help	Thu Jun 13 12:03:49 2002
@@ -1058,6 +1058,34 @@
   The module is called rtc.o. If you want to compile it as a module,
   say M here and read <file:Documentation/modules.txt>.
 
+Generic Real Time Clock Support
+CONFIG_GEN_RTC
+  If you say Y here and create a character special file /dev/rtc with
+  major number 10 and minor number 135 using mknod ("man mknod"), you
+  will get access to the real time clock (or hardware clock) built
+  into your computer.
+
+  In 2.4 and later kernels this is the only way to set and get rtc
+  time on m68k systems so it is highly recommended.
+
+  It reports status information via the file /proc/driver/rtc and its
+  behaviour is set by various ioctls on /dev/rtc. If you enable the
+  "extended RTC operation" below it will also provide an emulation
+  for RTC_UIE which is required by some programs and may improve
+  precision in some cases.
+
+  This driver is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module is called rtc.o. If you want to compile it as a module,
+  say M here and read <file:Documentation/modules.txt>. To load the
+  module automaticaly add 'alias char-major-10-135 genrtc' to your
+  /etc/modules.conf
+
+Extended RTC operation
+CONFIG_GEN_RTC_X
+  Provides an emulation for RTC_UIE which is required by some programs
+  and may improve precision of the generic RTC support in some cases.
+
 CONFIG_H8
   The Hitachi H8/337 is a microcontroller used to deal with the power
   and thermal environment. If you say Y here, you will be able to
diff -Nru a/drivers/char/Config.in b/drivers/char/Config.in
--- a/drivers/char/Config.in	Thu Jun 13 12:03:49 2002
+++ b/drivers/char/Config.in	Thu Jun 13 12:03:49 2002
@@ -188,6 +188,14 @@
 dep_tristate 'Intel i8x0 Random Number Generator support' CONFIG_INTEL_RNG $CONFIG_PCI
 tristate '/dev/nvram support' CONFIG_NVRAM
 tristate 'Enhanced Real Time Clock Support' CONFIG_RTC
+# XXX: RTC drivers conflict.  Only allow one.
+if [ "$CONFIG_RTC" = "n" ]; then
+   # XXX: CONFIG_SUN3 used to define_bool this to y
+   tristate 'Generic /dev/rtc emulation' CONFIG_GEN_RTC      
+   if [ "$CONFIG_GEN_RTC" != "n" ]; then
+      bool '   Extended RTC operation' CONFIG_GEN_RTC_X
+   fi
+fi
 if [ "$CONFIG_IA64" = "y" ]; then
    bool 'EFI Real Time Clock Services' CONFIG_EFI_RTC
 fi
diff -Nru a/drivers/char/Makefile b/drivers/char/Makefile
--- a/drivers/char/Makefile	Thu Jun 13 12:03:49 2002
+++ b/drivers/char/Makefile	Thu Jun 13 12:03:49 2002
@@ -173,6 +173,7 @@
 obj-$(CONFIG_ADBMOUSE) += adbmouse.o
 obj-$(CONFIG_PC110_PAD) += pc110pad.o
 obj-$(CONFIG_RTC) += rtc.o
+obj-$(CONFIG_GEN_RTC) += genrtc.o
 obj-$(CONFIG_EFI_RTC) += efirtc.o
 ifeq ($(CONFIG_PPC),)
   obj-$(CONFIG_NVRAM) += nvram.o
diff -Nru a/drivers/char/genrtc.c b/drivers/char/genrtc.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/char/genrtc.c	Thu Jun 13 12:03:49 2002
@@ -0,0 +1,517 @@
+/*
+ *	Real Time Clock interface for q40 and other m68k machines
+ *      emulate some RTC irq capabilities in software
+ *
+ *      Copyright (C) 1999 Richard Zidlicky
+ *
+ *	based on Paul Gortmaker's rtc.c device and
+ *           Sam Creasey Generic rtc driver
+ *
+ *	This driver allows use of the real time clock (built into
+ *	nearly all computers) from user space. It exports the /dev/rtc
+ *	interface supporting various ioctl() and also the /proc/dev/rtc
+ *	pseudo-file for status information.
+ *
+ *	The ioctls can be used to set the interrupt behaviour where
+ *  supported.
+ *
+ *	The /dev/rtc interface will block on reads until an interrupt
+ *	has been received. If a RTC interrupt has already happened,
+ *	it will output an unsigned long and then block. The output value
+ *	contains the interrupt status in the low byte and the number of
+ *	interrupts since the last read in the remaining high bytes. The
+ *	/dev/rtc interface can also be used with the select(2) call.
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ *
+
+ *      1.01 fix for 2.3.X                    rz@linux-m68k.org
+ *      1.02 merged with code from genrtc.c   rz@linux-m68k.org
+ *      1.03 make it more portable            zippel@linux-m68k.org
+ *      1.04 removed useless timer code       rz@linux-m68k.org
+ *      1.05 portable RTC_UIE emulation       rz@linux-m68k.org
+ */
+
+#define RTC_VERSION	"1.05"
+
+#include <linux/module.h>
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/miscdevice.h>
+#include <linux/fcntl.h>
+
+#include <linux/rtc.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <linux/proc_fs.h>
+
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/rtc.h>
+
+/*
+ *	We sponge a minor off of the misc major. No need slurping
+ *	up another valuable major dev number for this. If you add
+ *	an ioctl, make sure you don't conflict with SPARC's RTC
+ *	ioctls.
+ */
+
+static DECLARE_WAIT_QUEUE_HEAD(gen_rtc_wait);
+
+static int gen_rtc_ioctl(struct inode *inode, struct file *file,
+		     unsigned int cmd, unsigned long arg);
+
+/*
+ *	Bits in gen_rtc_status.
+ */
+
+#define RTC_IS_OPEN		0x01	/* means /dev/rtc is in use	*/
+
+unsigned char gen_rtc_status;		/* bitmapped status byte.	*/
+unsigned long gen_rtc_irq_data;		/* our output to the world	*/
+
+/* months start at 0 now */
+unsigned char days_in_mo[] =
+{31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
+
+static int irq_active;
+
+#ifdef CONFIG_GEN_RTC_X
+struct tq_struct genrtc_task;
+static struct timer_list timer_task;
+
+static unsigned int oldsecs;
+static int lostint;
+static int tt_exp;
+
+void gen_rtc_timer(unsigned long data);
+
+static volatile int stask_active;              /* schedule_task */
+static volatile int ttask_active;              /* timer_task */
+static int stop_rtc_timers;                    /* don't requeue tasks */
+static spinlock_t gen_rtc_lock = SPIN_LOCK_UNLOCKED;
+
+/*
+ * Routine to poll RTC seconds field for change as often as posible,
+ * after first RTC_UIE use timer to reduce polling
+ */
+void genrtc_troutine(void *data)
+{
+	unsigned int tmp = get_rtc_ss();
+	
+	if (stop_rtc_timers) {
+		stask_active = 0;
+		return;
+	}
+
+	if (oldsecs != tmp){
+		oldsecs = tmp;
+
+		timer_task.function = gen_rtc_timer;
+		timer_task.expires = jiffies + HZ - (HZ/10);
+		tt_exp=timer_task.expires;
+		ttask_active=1;
+		stask_active=0;
+		add_timer(&timer_task);
+
+		gen_rtc_interrupt(0);
+	} else if (schedule_task(&genrtc_task) == 0)
+		stask_active = 0;
+}
+
+void gen_rtc_timer(unsigned long data)
+{
+	lostint = get_rtc_ss() - oldsecs ;
+	if (lostint<0) 
+		lostint = 60 - lostint;
+	if (jiffies-tt_exp>1)
+		printk("genrtc: timer task delayed by %ld jiffies\n",
+		       jiffies-tt_exp);
+	ttask_active=0;
+	stask_active=1;
+	if ((schedule_task(&genrtc_task) == 0))
+		stask_active = 0;
+}
+
+/* 
+ * call gen_rtc_interrupt function to signal an RTC_UIE,
+ * arg is unused.
+ * Could be invoked either from a real interrupt handler or
+ * from some routine that periodically (eg 100HZ) monitors
+ * whether RTC_SECS changed
+ */
+void gen_rtc_interrupt(unsigned long arg)
+{
+	/*  We store the status in the low byte and the number of
+	 *	interrupts received since the last read in the remainder
+	 *	of rtc_irq_data.  */
+
+	gen_rtc_irq_data += 0x100;
+	gen_rtc_irq_data &= ~0xff;
+	gen_rtc_irq_data |= RTC_UIE;
+
+	if (lostint){
+		printk("genrtc: system delaying clock ticks?\n");
+		/* increment count so that userspace knows something is wrong */
+		gen_rtc_irq_data += ((lostint-1)<<8);
+		lostint = 0;
+	}
+
+	wake_up_interruptible(&gen_rtc_wait);
+}
+
+/*
+ *	Now all the various file operations that we export.
+ */
+static ssize_t gen_rtc_read(struct file *file, char *buf,
+			size_t count, loff_t *ppos)
+{
+	DECLARE_WAITQUEUE(wait, current);
+	unsigned long data;
+	ssize_t retval;
+
+	if (count < sizeof(unsigned long))
+		return -EINVAL;
+
+	if (file->f_flags & O_NONBLOCK && !gen_rtc_irq_data)
+		return -EAGAIN;
+
+	add_wait_queue(&gen_rtc_wait, &wait);
+	retval = -ERESTARTSYS;
+
+	while (1) {
+		set_current_state(TASK_INTERRUPTIBLE);
+		data = xchg(&gen_rtc_irq_data, 0);
+		if (data)
+			break;
+		if (signal_pending(current))
+			goto out;
+		schedule();
+	}
+
+	retval = put_user(data, (unsigned long *)buf);
+	if (!retval)
+		retval = sizeof(unsigned long);
+ out:
+	current->state = TASK_RUNNING;
+	remove_wait_queue(&gen_rtc_wait, &wait);
+
+	return retval;
+}
+
+static unsigned int gen_rtc_poll(struct file *file,
+				 struct poll_table_struct *wait)
+{
+	poll_wait(file, &gen_rtc_wait, wait);
+	if (gen_rtc_irq_data != 0)
+		return POLLIN | POLLRDNORM;
+	return 0;
+}
+
+#endif
+
+/*
+ * Used to disable/enable interrupts, only RTC_UIE supported
+ * We also clear out any old irq data after an ioctl() that
+ * meddles with the interrupt enable/disable bits.
+ */
+
+static inline void gen_clear_rtc_irq_bit(unsigned char bit)
+{
+#ifdef CONFIG_GEN_RTC_X
+	stop_rtc_timers = 1;
+	if (ttask_active){
+		del_timer_sync(&timer_task);
+		ttask_active = 0;
+	}
+	while (stask_active)
+		schedule();
+
+	spin_lock(&gen_rtc_lock);
+	irq_active = 0;
+	spin_unlock(&gen_rtc_lock);
+#endif
+}
+
+static inline int gen_set_rtc_irq_bit(unsigned char bit)
+{
+#ifdef CONFIG_GEN_RTC_X
+	spin_lock(&gen_rtc_lock);
+	if ( !irq_active ) {
+		irq_active = 1;
+		stop_rtc_timers = 0;
+		lostint = 0;
+		genrtc_task.routine = genrtc_troutine;
+		oldsecs = get_rtc_ss();
+		init_timer(&timer_task);
+
+		stask_active = 1;
+		if (schedule_task(&genrtc_task) == 0){
+			stask_active = 0;
+		}
+	}
+	spin_unlock(&gen_rtc_lock);
+	gen_rtc_irq_data = 0;
+	return 0;
+#else
+	return -EINVAL;
+#endif
+}
+
+static int gen_rtc_ioctl(struct inode *inode, struct file *file,
+			 unsigned int cmd, unsigned long arg)
+{
+	struct rtc_time wtime;
+	struct pll_info pll;
+
+	switch (cmd) {
+
+	case RTC_PLL_GET:
+	    if (get_rtc_pll(&pll))
+	 	    return -EINVAL;
+	    else
+		    return copy_to_user((void *)arg, &pll, sizeof pll) ? -EFAULT : 0;
+
+	case RTC_PLL_SET:
+		if (!capable(CAP_SYS_TIME))
+			return -EACCES;
+		if (copy_from_user(&pll, (struct pll_info*)arg,
+				   sizeof(pll)))
+			return -EFAULT;
+	    return set_rtc_pll(&pll);
+
+	case RTC_UIE_OFF:	/* disable ints from RTC updates.	*/
+		gen_clear_rtc_irq_bit(RTC_UIE);
+		return 0;
+
+	case RTC_UIE_ON:	/* enable ints for RTC updates.	*/
+	        return gen_set_rtc_irq_bit(RTC_UIE);
+
+	case RTC_RD_TIME:	/* Read the time/date from RTC	*/
+		/* this doesn't get week-day, who cares */
+		memset(&wtime, 0, sizeof(wtime));
+		get_rtc_time(&wtime);
+
+		return copy_to_user((void *)arg, &wtime, sizeof(wtime)) ? -EFAULT : 0;
+
+	case RTC_SET_TIME:	/* Set the RTC */
+	    {
+		int year;
+		unsigned char leap_yr;
+
+		if (!capable(CAP_SYS_TIME))
+			return -EACCES;
+
+		if (copy_from_user(&wtime, (struct rtc_time *)arg,
+				   sizeof(wtime)))
+			return -EFAULT;
+
+		year = wtime.tm_year + 1900;
+		leap_yr = ((!(year % 4) && (year % 100)) ||
+			   !(year % 400));
+
+		if ((wtime.tm_mon < 0 || wtime.tm_mon > 11) || (wtime.tm_mday < 1))
+			return -EINVAL;
+
+		if (wtime.tm_mday < 0 || wtime.tm_mday >
+		    (days_in_mo[wtime.tm_mon] + ((wtime.tm_mon == 1) && leap_yr)))
+			return -EINVAL;
+
+		if (wtime.tm_hour < 0 || wtime.tm_hour >= 24 ||
+		    wtime.tm_min < 0 || wtime.tm_min >= 60 ||
+		    wtime.tm_sec < 0 || wtime.tm_sec >= 60)
+			return -EINVAL;
+
+		set_rtc_time(&wtime);
+		return 0;
+	    }
+	}
+
+	return -EINVAL;
+}
+
+/*
+ *	We enforce only one user at a time here with the open/close.
+ *	Also clear the previous interrupt data on an open, and clean
+ *	up things on a close.
+ */
+
+static int gen_rtc_open(struct inode *inode, struct file *file)
+{
+	if (gen_rtc_status & RTC_IS_OPEN)
+		return -EBUSY;
+
+	MOD_INC_USE_COUNT;
+
+	gen_rtc_status |= RTC_IS_OPEN;
+	gen_rtc_irq_data = 0;
+	irq_active = 0;
+
+	return 0;
+}
+
+static int gen_rtc_release(struct inode *inode, struct file *file)
+{
+	/*
+	 * Turn off all interrupts once the device is no longer
+	 * in use and clear the data.
+	 */
+
+	gen_clear_rtc_irq_bit(RTC_PIE|RTC_AIE|RTC_UIE);
+
+	gen_rtc_status &= ~RTC_IS_OPEN;
+	MOD_DEC_USE_COUNT;
+
+	return 0;
+}
+
+static int gen_rtc_read_proc(char *page, char **start, off_t off,
+			     int count, int *eof, void *data);
+
+
+/*
+ *	The various file operations we support.
+ */
+
+static struct file_operations gen_rtc_fops = {
+	owner:		THIS_MODULE,
+#ifdef CONFIG_GEN_RTC_X
+	read:		gen_rtc_read,
+	poll:		gen_rtc_poll,
+#endif
+	ioctl:		gen_rtc_ioctl,
+	open:		gen_rtc_open,
+	release:	gen_rtc_release
+};
+
+static struct miscdevice rtc_gen_dev =
+{
+	RTC_MINOR,
+	"rtc",
+	&gen_rtc_fops
+};
+
+int __init rtc_generic_init(void)
+{
+
+		printk(KERN_INFO "Generic RTC Driver v%s\n", RTC_VERSION);
+
+	misc_register(&rtc_gen_dev);
+	create_proc_read_entry ("driver/rtc", 0, 0, gen_rtc_read_proc, NULL);
+
+	return 0;
+}
+
+static void __exit rtc_generic_exit(void)
+{
+	remove_proc_entry ("driver/rtc", NULL);
+	misc_deregister(&rtc_gen_dev);
+}
+
+module_init(rtc_generic_init);
+module_exit(rtc_generic_exit);
+EXPORT_NO_SYMBOLS;
+
+
+/*
+ *	Info exported via "/proc/rtc".
+ */
+
+int gen_rtc_proc_output(char *buf)
+{
+	char *p;
+	struct rtc_time tm;
+	unsigned tmp;
+	struct pll_info pll;
+
+	p = buf;
+
+	get_rtc_time(&tm);
+
+	p += sprintf(p,
+		     "rtc_time\t: %02d:%02d:%02d\n"
+		     "rtc_date\t: %04d-%02d-%02d\n"
+		     "rtc_epoch\t: %04u\n",
+		     tm.tm_hour, tm.tm_min, tm.tm_sec,
+		     tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, 1900);
+
+	tm.tm_hour=0;tm.tm_min=0;tm.tm_sec=0;
+
+	p += sprintf(p, "alarm\t\t: ");
+	if (tm.tm_hour <= 24)
+		p += sprintf(p, "%02d:", tm.tm_hour);
+	else
+		p += sprintf(p, "**:");
+
+	if (tm.tm_min <= 59)
+		p += sprintf(p, "%02d:", tm.tm_min);
+	else
+		p += sprintf(p, "**:");
+
+	if (tm.tm_sec <= 59)
+		p += sprintf(p, "%02d\n", tm.tm_sec);
+	else
+		p += sprintf(p, "**\n");
+
+	tmp= RTC_24H ;
+	p += sprintf(p,
+		     "DST_enable\t: %s\n"
+		     "BCD\t\t: %s\n"
+		     "24hr\t\t: %s\n"
+		     "square_wave\t: %s\n"
+		     "alarm_IRQ\t: %s\n"
+		     "update_IRQ\t: %s\n"
+		     "periodic_IRQ\t: %s\n"
+		     "periodic_freq\t: %ld\n"
+		     "batt_status\t: %s\n",
+		     (tmp & RTC_DST_EN) ? "yes" : "no",
+		     (tmp & RTC_DM_BINARY) ? "no" : "yes",
+		     (tmp & RTC_24H) ? "yes" : "no",
+		     (tmp & RTC_SQWE) ? "yes" : "no",
+		     (tmp & RTC_AIE) ? "yes" : "no",
+		     irq_active ? "yes" : "no",
+		     (tmp & RTC_PIE) ? "yes" : "no",
+		     0L /* freq */,
+		     "okay" );
+	if (!get_rtc_pll(&pll))
+	    p += sprintf(p,
+			 "PLL adjustment\t: %d\n"
+			 "PLL max +ve adjustment\t: %d\n"
+			 "PLL max -ve adjustment\t: %d\n"
+			 "PLL +ve adjustment factor\t: %d\n"
+			 "PLL -ve adjustment factor\t: %d\n"
+			 "PLL frequency\t: %ld\n",
+			 pll.pll_value,
+			 pll.pll_max,
+			 pll.pll_min,
+			 pll.pll_posmult,
+			 pll.pll_negmult,
+			 pll.pll_clock);
+	return  p - buf;
+}
+
+static int gen_rtc_read_proc(char *page, char **start, off_t off,
+			     int count, int *eof, void *data)
+{
+	int len = gen_rtc_proc_output (page);
+        if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+        if (len>count) len = count;
+        if (len<0) len = 0;
+	return len;
+}
+
+
+MODULE_AUTHOR("Richard Zidlicky");
+MODULE_LICENSE("GPL");
+
+/*
+ * Local variables:
+ * compile-command: "m68k-linux-gcc -D__KERNEL__ -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -ffixed-a2 -c -o genrtc.o genrtc.c"
+ * End:
+ */
+
diff -Nru a/drivers/video/radeonfb.c b/drivers/video/radeonfb.c
--- a/drivers/video/radeonfb.c	Thu Jun 13 12:03:49 2002
+++ b/drivers/video/radeonfb.c	Thu Jun 13 12:03:49 2002
@@ -190,7 +190,7 @@
 } __attribute__ ((packed)) PLL_BLOCK;
 
 
-struct pll_info {
+struct radeon_pll_info {
 	int ppll_max;
 	int ppll_min;
 	int xclk;
@@ -304,7 +304,7 @@
 
 	u32 dp_gui_master_cntl;
 
-	struct pll_info pll;
+	struct radeon_pll_info pll;
 	int pll_output_freq, post_div, fb_div;
 
 	struct ram_info ram;
diff -Nru a/include/asm-ppc/rtc.h b/include/asm-ppc/rtc.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ppc/rtc.h	Thu Jun 13 12:03:49 2002
@@ -0,0 +1,94 @@
+/* 
+ * inclue/asm-ppc/rtc.h
+ *
+ * Copyright 2002 MontaVista Software Inc.
+ * Author: Tom Rini <trini@mvista.com>
+ *
+ * Based on:
+ * include/asm-m68k/rtc.h
+ *
+ * Copyright Richard Zidlicky
+ * implementation details for genrtc/q40rtc driver
+ *
+ * And the old drivers/macintosh/rtc.c which was heavily based on:
+ * Linux/SPARC Real Time Clock Driver
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ *
+ * With additional work by Paul Mackerras and Franz Sirl.
+ */
+/* permission is hereby granted to copy, modify and redistribute this code
+ * in terms of the GNU Library General Public License, Version 2 or later,
+ * at your option.
+ */
+
+#ifndef __ASM_RTC_H__
+#define __ASM_RTC_H__
+
+#ifdef __KERNEL__
+
+#include <linux/rtc.h>
+
+#include <asm/machdep.h>
+#include <asm/time.h>
+
+#define RTC_PIE 0x40		/* periodic interrupt enable */
+#define RTC_AIE 0x20		/* alarm interrupt enable */
+#define RTC_UIE 0x10		/* update-finished interrupt enable */
+
+extern void gen_rtc_interrupt(unsigned long);
+
+/* some dummy definitions */
+#define RTC_SQWE 0x08		/* enable square-wave output */
+#define RTC_DM_BINARY 0x04	/* all time/date values are BCD if clear */
+#define RTC_24H 0x02		/* 24 hour mode - else hours bit 7 means pm */
+#define RTC_DST_EN 0x01	        /* auto switch DST - works f. USA only */
+
+static inline void get_rtc_time(struct rtc_time *time)
+{
+	if (ppc_md.get_rtc_time) {
+		unsigned long nowtime;
+
+		nowtime = (ppc_md.get_rtc_time)();
+
+		to_tm(nowtime, time);
+
+		time->tm_year -= 1900;
+		time->tm_mon -= 1; /* Make sure userland has a 0-based month */
+	} else
+		return -EINVAL;
+}
+
+/* Set the current date and time in the real time clock. */
+static inline void set_rtc_time(struct rtc_time *time)
+{
+	if (ppc_md.get_rtc_time) {
+		unsigned long nowtime;
+
+		nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
+				time->tm_mday, time->tm_hour, time->tm_min,
+				time->tm_sec);
+
+		(ppc_md.set_rtc_time)(nowtime);
+	} else
+		return -EINVAL;
+}
+
+static inline unsigned int get_rtc_ss(void)
+{
+	struct rtc_time h;
+
+	get_rtc_time(&h);
+	return h.tm_sec;
+}
+
+static inline int get_rtc_pll(struct pll_info *pll)
+{
+	return -EINVAL;
+}
+static inline int set_rtc_pll(struct pll_info *pll)
+{
+	return -EINVAL;
+}
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_RTC_H__ */
diff -Nru a/include/linux/rtc.h b/include/linux/rtc.h
--- a/include/linux/rtc.h	Thu Jun 13 12:03:49 2002
+++ b/include/linux/rtc.h	Thu Jun 13 12:03:49 2002
@@ -39,10 +39,32 @@
 	struct rtc_time time;	/* time the alarm is set to */
 };
 
+/*
+ * Data structure to control PLL correction some better RTC feature
+ * pll_value is used to get or set current value of correction,
+ * the rest of the struct is used to query HW capabilities.
+ * This is modeled after the RTC used in Q40/Q60 computers but
+ * should be sufficiently flexible for other devices
+ *
+ * +ve pll_value means clock will run faster by
+ *   pll_value*pll_posmult/pll_clock
+ * -ve pll_value means clock will run slower by
+ *   pll_value*pll_negmult/pll_clock
+ */ 
+
+struct pll_info {
+	int pll_ctrl;       /* placeholder for fancier control */
+	int pll_value;      /* get/set correction value */
+	int pll_max;        /* max +ve (faster) adjustment value */
+	int pll_min;        /* max -ve (slower) adjustment value */
+	int pll_posmult;    /* factor for +ve corection */
+	int pll_negmult;    /* factor for -ve corection */
+	long pll_clock;     /* base PLL frequency */
+};
 
 /*
  * ioctl calls that are permitted to the /dev/rtc interface, if 
- * CONFIG_RTC/CONFIG_EFI_RTC was enabled.
+ * any of the RTC drivers are enabled.
  */
 
 #define RTC_AIE_ON	_IO('p', 0x01)	/* Alarm int. enable on		*/
@@ -65,6 +87,9 @@
 
 #define RTC_WKALM_SET	_IOW('p', 0x0f, struct rtc_wkalrm)/* Set wakeup alarm*/
 #define RTC_WKALM_RD	_IOR('p', 0x10, struct rtc_wkalrm)/* Get wakeup alarm*/
+#define RTC_PLL_GET	_IOR('p', 0x11, struct pll_info)  /* Get PLL correction */
+#define RTC_PLL_SET	_IOW('p', 0x12, struct pll_info)  /* Set PLL correction */
+#
 
 #ifdef __KERNEL__
 

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Date: Mon, 10 Jun 2002 13:36:52 -0700
From: "H . J . Lu" <hjl@lucon.org>
To: linux-gcc@vger.kernel.org, GNU C Library <libc-alpha@sources.redhat.com>,
   gcc@gcc.gnu.org, Kenneth Albanowski <kjahds@kjahds.com>,
   Mat Hostetter <mat@lcs.mit.edu>,
   Andy Dougherty <doughera@lafcol.lafayette.edu>,
   Warner Losh <imp@village.org>, linux-mips@oss.sgi.com,
   Ron Guilmette <rfg@monkeys.com>,
   "Polstra; John" <linux-binutils-in@polstra.com>,
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   Linas Vepstas <linas@linas.org>, Feher Janos <aries@hal2000.terra.vein.hu>,
   Leonard Zubkoff <lnz@dandelion.com>, "Steven J. Hill" <sjhill@cotw.com>
Subject: The Linux binutils 2.12.90.0.11 is released.
Message-ID: <20020610133652.A27414@lucon.org>
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This is the beta release of binutils 2.12.90.0.11 for Linux, which is
based on binutils 2002 0608 in CVS on sourecs.redhat.com plus various
changes. It is purely for Linux.

The Linux/mips support is added. You have to use

# rpm --target=[mips|mipsel] -ta binutils-xx.xx.xx.xx.xx.tar.gz

to build it. Or you can read mips/README in the source tree to apply
the mips patches and build it by hand.

FYI, the binutils man pages now are generated from the texinfo files
during the build. As the result, those man pages may be changed for
each build even if you only have done

# ..../configure ...
# make

That means you may have many failures on the man pages when you apply
the binutils diffs next time. Those failures can be safely ignored.
You should remove all those man pages from your source tree by

# find -name *.1 | xargs rm -f
# find -name *.1.rej | xargs rm -f
# find -name *.man | xargs rm -f
# find -name *.man.rej | xargs rm -f

I am planning to make the public release soon. Please test it as much
as you can.

Please report any bugs related to binutils 2.12.90.0.11 to hjl@lucon.org.

For arm-linux targets, there are some important differences in behaviour 
between these tools and binutils 2.9.1.0.x.  The linker emulation name has 
changed from elf32arm{26} to armelf_linux{26}.  Also, the "-p" flag must be 
passed with the linker when working with object files (or static libraries) 
created using older versions of the assembler.  If this flag is omitted the 
linker will silently generate bad output when given old input files.

To get the correct behaviour from gcc, amend the *link section of your specs 
file as follows:

*link:
%{h*} %{version:-v}    %{b} %{Wl,*:%*}    %{static:-Bstatic}    %{shared:-shared}    %{symbolic:-Bsymbolic}    %{rdynamic:-export-dynamic}    %{!dynamic-linker: -dynamic-linker /lib/ld-linux.so.2}    -X    %{mbig-endian:-EB} %{mapcs-26:-m armelf_linux26} %{!mapcs-26:-m armelf_linux} -p


Changes from binutils 2.12.90.0.9:

1. Update from binutils 2002 0608.
2. Fix an ELF/mips SHF_MERGE bug.

Changes from binutils 2.12.90.0.7:

1. Update from binutils 2002 0526.
2. Support "-z muldefs".

Changes from binutils 2.12.90.0.4:

1. Update from binutils 2002 0423.
2. ELF EH frame bug fix.
3. MIPS ELF visibility bug fix.

Changes from binutils 2.12.90.0.3:

1. Update from binutils 2002 0408.
2. Bug fixes for ELF/sparc.
3. Bug fixes for ELF/CRIS.

Changes from binutils 2.12.90.0.1:

1. Update from binutils 2002 0323.
2. Fix linking a.out relocatable files with ELF.
3. Fix a PPC altivec assembler bug.

Changes from binutils 2.11.93.0.2:

1. Update from binutils 2002 0307.
2. Add the .preinit_array/.init_array/.fini_array support.
3. Fix eh_frame.
4. Turn on combreloc by default.
5. Enable gprof for Linux/mips.

Changes from binutils 2.11.92.0.12.3:

1. Update from binutils 2002 0207.
2. Fix a weak symbol alpha linker bug for glibc.
3. More support for gcc 3.1.

Changes from binutils 2.11.92.0.12:

1. Fix a regression in 2.11.92.0.12 when linking with none-ELF object
files.

Changes from binutils 2.11.92.0.10:

1. Update from binutils 2001 1121.
2. Fix a linker symbol version bug for common symbols.
3. Update handling relocations against the discarded sections. You may
need to apply the kernel patch enclosed here to your kernel source. If
you still see things like

drivers/char/char.o(.data+0x46b4): undefined reference to `local symbols in discarded section .text.exit'

in the final kernel link, that means you have compiled a driver into
the kernel which has a reference to the symbol in a discarded section.
Kernel 2.4.17 or above should work fine.

4. Support "-march=xxx -mipsN" for mips gas if they are compatible.

Changes from binutils 2.11.92.0.7:

1. Update from binutils 2001 1021.
2. Fix the ELF/PPC linker.
3. Fix the ELF/cris linker.
4. Fix ELF strip.

Changes from binutils 2.11.92.0.5:

1. Update from binutils 2001 1016.
2. Fix all breakages introduced in 2.11.92.0.12.

Changes from binutils 2.11.90.0.31:

1. Update from binutils 2001 1005.
2. Support gcc 3.1 for ia64.
3. Support prelink for ELF/PPC.
4. Fix an ELF/x86 linker bug for Oracle.
5. Fix a weak symbol bug.
6. Support locale.

Changes from binutils 2.11.90.0.29:

1. Update from binutils 2001 0830.
2. Fix a mips linker bug.

Changes from binutils 2.11.90.0.27:

1. Update from binutils 2001 0827.
2. Fix an alpha assembler bug.
3. Fix an ia64 linker bug.
4. Fix a mips linker bug.
5. Support `-z combreloc|nocombreloc' in linker.

Changes from binutils 2.11.90.0.25:

1. Update from binutils 2001 0810.
2. Fix an x86 linker bug.

Changes from binutils 2.11.90.0.24:

1. Update from binutils 2001 0726.
2. Fix an x86 assembler bug.
3. "make check" in the windres test in binutils may call uudecode. We
are working on it.
4. "make check" fails the windres test in binutils if the i386/pe
is enabled in bfd. Fixed in the next release.
5. "make check" has 2 failures in the ld-selective test in ld on
Linux/alpha. They should be marked xfail. Fixed in the next release.

Changes from binutils 2.11.90.0.23:

1. Update from binutils 2001 0714.
2. Fix Sparc/ElF for Linux/sparc.
3. Fix Alpha/ELF for gcc 3.0.

Changes from binutils 2.11.90.0.19:

1. Update from binutils 2001 0706.
2. Fix objcopy/strip broken by accident.
3. Avoid COPY relocs on ia32.
4. Fix the ia64 assembler.
5. This release may not work on Linux/sparc due to the unaligned
relocation changes, which are not handled by all versions of glibc.
The current glibc in CVS on sourceware should be ok. The last known
working binutils for Linux/sparc is 2.11.90.0.8. We are working on it.

Changes from binutils 2.11.90.0.15:

1. Update from binutils 2001 0620.
2. Fix a static linking the PIC object files on ia32.
3. Add the verion script support for --export-dynamic. It can be used
to selectively export dynamic symbols from the executables.

Changes from binutils 2.11.90.0.8:

1. Update from binutils 2001 0610.
2. Fix a gas bug for gcc 3.0.

Changes from binutils 2.11.90.0.7:

1. Update from binutils 2001 0512.
2. Fix some P/III SSE 2 assembler bugs.
3. Fix DT_NEEDED and symbol version bugs.
4. Support hidden versioned symbols in DSOs.

Changes from binutils 2.11.90.0.6:

1. Update from binutils 2001 0427.
2. Fix the -Bsymbolic bug introduced in binutils 2.11.90.0.5.

Changes from binutils 2.11.90.0.5:

1. Update from binutils 2001 0425.
2. Update "ld --multilib-dir PATH".

Changes from binutils 2.11.90.0.4:

1. Update from binutils 2001 0414.
2. Fix an ia64 assembler bug.
3. Change Linux/MIPS to use the SVR4 MIPS ABI instead of the IRIX ABI.
since there are no supports for the IRIX ABI in glibc. The current
Linux/MIPS targets are elf64-tradlittlemips for little endian MIPS
instead of elf32-littlemips and elf64-tradbigmips for big endian MIPS
instead of elf32-bigmips. Glibc, gcc and kernel may have to be modified
for this change. 

Changes from binutils 2.11.90.0.1:

1. Update from binutils 2001 0401.
2. Fix a gas bug for the gcc from the CVS main trunk. It involves some
changes in gas. I compiled kernel 2.2.18, gcc and glibc under
Linux/ia32. The resulting binaries work fine. 
3. Fix the linker core dump on unsupported ELF binaries.

Changes from binutils 2.10.91.0.4:

1. Update from binutils 2001 0309.

Changes from binutils 2.10.91.0.2:

1. Update from binutils 2001 0223.
2. More ia64 bug fixes.

Changes from binutils 2.10.1.0.7:

1. Update from binutils 2001 0215.
2. More ia64 bug fixes. Support EFI and "ld -relax" on ia64.
3. Fix a weak definition, -Bsymbolic, non-PIC bug for ia32.

Changes from binutils 2.10.1.0.4:

1. Update from binutils 2001 0206.
2. Enable the IA64 support.
3. Now you need to use

# ld --oformat TARGET

instead of

# ld -oformat TARGET

The Linux kernel build may be affected. BTW

# ld --oformat TARGET

should work with all previous releases of binutils.

Changes from binutils 2.10.1.0.2:

1. Update from binutils 2000 1221.

Changes from binutils 2.10.0.33:

1. Update from binutils 2000 1119.
2. It has some symbol versioning related updates.

Changes from binutils 2.10.0.32:

1. Update from binutils 2000 1018.
2. A proper ELF/PPC visibility fix.
3. m68k-a.out is supposed to be fixed.

Changes from binutils 2.10.0.31:

1. Update from binutils 2000 1014.
2. An ELF/PPC weak symbol bug fix.
3. A new linkonce section name approach.
4. m68k-a.out is still broken. To be fixed.

Changes from binutils 2.10.0.29:

1. Update from binutils 2000 1011.
2. Back out the linkonce section name change so that C++ will work.
A different approach is being worked on.
3. m68k-a.out is known to be broken. To be fixed.

Changes from binutils 2.10.0.26:

1. Update from binutils 2000 1008.

Changes from binutils 2.10.0.24:

1. Update from binutils 2000 0907.

Changes from binutils 2.10.0.18:

1. Update from binutils 2000 0823. Fix DT_RPATH/DT_RUNPATH handling.
Fix the ELF/ia32 DSO not compiled with PIC.
2. Try to fix the ELF visibility bug on PPC with glibc 2.2.

Changes from binutils 2.10.0.12:

1. Update from binutils 2000 0720.
2. Fix the DT_NEEDED link bug.
3. Add the new DT_XXXX dynamic tags. Glibc 2.2 will use them at least
on libpthread.so.

Changes from binutils 2.10.0.9:

1. Update from binutils 2000 0701. Fix the parallel build in ld when PE
is enabled.

Changes from binutils 2.9.5.0.46:

1. Update from binutils 2000 0617. The demangler support for the new
g++ ABI. Minor fix for the ELF visibility. Fix linking non-ELF
relocatable object files under ELF with symbol versioning.
2. Support for linking PE relocatable object files under ia32/ELF.

Changes from binutils 2.9.5.0.42:

1. Update from binutils 2000 0604. The ELF visibility attribuite should
work correctly now.
2. The ia32 assembler has changed the way it assembles the "jmp"
instructions to the global symbols. The old assembler will optimize the
jump to the global symbol defined in the same source file so that no
relocation will be used. The new assembler will use relocation for
global jumps. It will mainly affect PIC asm code. The segment like

	.globl  __setjmp
__setjmp:
	...
	jmp __sigsetjmp
	...
	.globl __sigsetjmp
__sigsetjmp:

is no longer PIC safe since "jmp __sigsetjmp" jumps to a global symbol
and relocation will be used. Instead, it can be changed to

	.globl  __setjmp
__setjmp:
	...
	jmp sigsetjmp
	...
	.globl __sigsetjmp
__sigsetjmp:
sigsetjmp:

so that "jmp sigsetjmp" jumps to a local symbol and the new assembler
will optimize out the relocation.

Changes from binutils 2.9.5.0.41:

1. Update from binutils 2000 0512.
2. Add testsuite for ELF visibility.

Changes from binutils 2.9.5.0.37:

1. Update from binutils 2000 0502.
2. Support STV_HIDDEN and STV_INTERNAL.

Changes from binutils 2.9.5.0.35:

1. Update from binutils 2000 0418.
2. Fix an ld demangle style option bug.

Changes from binutils 2.9.5.0.34:

1. Update from binutils 2000 0412. Fix a relocation bug which affects
the Linux kernel compilation.
2. An ELF/PPC linker script update.

Changes from binutils 2.9.5.0.33:

1. Update from binutils 2000 0404. Fix the bug report bug.

Changes from binutils 2.9.5.0.32:

1. Update from binutils 2000 0403. Fix the 16bit ia32 assembler bug.

Changes from binutils 2.9.5.0.31:

1. Update from binutils 2000 0331. Fix the Linux/ARM assembler bug.
2. Fix a Debian assembler security bug.

Changes from binutils 2.9.5.0.29:

1. Update from binutils 2000 0319.
2. An ELF/alpha bug is fixed.

Changes from binutils 2.9.5.0.27:

1. Update from binutils 2000 0301.
2. A demangler bug is fixed.
3. A better fix for undefined symbols with -Bsymbolic when building
shared library.

Changes from binutils 2.9.5.0.24:

1. Update from binutils 2000 0204.
2. Added -taso to linker on alpha.
3. Fixed a -shared -Bsymbolic bug when PIC is not used.

Changes from binutils 2.9.5.0.22:

1. Update from binutils 2000 0113.
2. A symbol version bug is fixed.
3. A -Bsymbolic bug is fixed.

Changes from binutils 2.9.5.0.21:

1. Update from binutils 1999 1202.
2. Remove a MIPS/ELF change.
3. Enable SOM for HPPA.

Changes from binutils 2.9.5.0.19:

1. Update from binutils 1999 1122. An ia32 gas bug is fixed.

Changes from binutils 2.9.5.0.16:

1. Update from binutils 1999 1104.
2. i370 is changed to use EM_S370 and ELFOSABI_LINUX. Update readelf.
3. Fix Compaq's demangler support.

Changes from binutils 2.9.5.0.14:

1. Update from binutils 1999 1012. A gas bug which affects Linux 2.3.21
is fixed.
2. i370 update.
3. The new demangler code. You should use "--style=xxx" to select the
demnangle style instead of "--lang=xxx".

Changes from binutils 2.9.5.0.13:

1. Update from binutils 1999 0925.
2. Fix a -s and linker script bug.

Changes from binutils 2.9.5.0.12:

1. Update from binutils 1999 0922.
2. i370 update.

Changes from binutils 2.9.5.0.11:

1. Update from binutils 1999 0910. It fixed a PIC linker bug on ix86
   and sparc introduced in the last release.
2. i370 update.

Changes from binutils 2.9.5.0.10:

1. Update from binutils 1999 0906. It fixed a PIC linker bug on ix86
   and sparc.
2. Remove elf/hppa since it is WIP.

Changes from binutils 2.9.5.0.8:

1. Update from binutils 1999 0831. It allows spaces around '(' and ')'
   in x86 FP register names.

Changes from binutils 2.9.5.0.7:

1. Update from binutils 1999 0821.
2. Some MIPS changes.

Changes from binutils 2.9.5.0.6:

1. Update from binutils 1999 0813.
2. i370 update.

Changes from binutils 2.9.5.0.5:

1. Update from binutils 1999 0809. An ELF/Sparc ld bug is fixed.

Changes from binutils 2.9.5.0.4:

1. Update from binutils 1999 0806. A Solaris/Sparc gas bug is fixed.
2. Remove mips gas patches from binutils 2.9.1.0.25.

Changes from binutils 2.9.5.0.3:

1. Update from binutils 1999 0801.
2. Support for real mode x86 gcc.

Changes from binutils 2.9.4.0.8:

1. Update from binutils 1999 0719. A libc 5 related bug fix.
2. Fix a typo in mips gas.

Changes from binutils 2.9.4.0.7:

1. Update from binutils 1999 0710. A weak symbol bug

http://egcs.cygnus.com/ml/egcs-bugs/1999-07/msg00129.html

is fixed.

Changes from binutils 2.9.4.0.6:

1. Update from binutils 1999 0626.

Changes from binutils 2.9.4.0.5:

1. Update from binutils 1999 0620.
2. Remove my fwait fix and use the one in cvs.
3. Use "--only-section=section" instead of "--extract-section=section".
   for objcopy.

Changes from binutils 2.9.4.0.4:

1. Update from binutils 1999 0612.
2. Remove various temporary fixes of mine since those bugs are fixed
   now.

Changes from binutils 2.9.4.0.3:

1. Update from binutils 1999 0611.
2. Remove my ELF/Alpha bfd changes.
3. Use the local symbol copy fix in binutils 1999 0611.

Changes from binutils 2.9.4.0.2:

1. Update from binutils 1999 0607.
2. Remove my Sparc hacks.
3. Fix local symbol copy.

Changes from binutils 2.9.4.0.1:

1. Update from binutils 1999 0606.
2. Restore relocation overflow checking in binutils 2.9.1.0.25 so that
   Linux kernel can build.
3. Fix i370 for the new gas.

Changes from binutils 1999 0605:

1. Fix a -Bsymbolic bug for Linux/alpha.
2. Add ELF/i370.
3. Fix 8/16-bit relocations for i386.
4. Add --redefine-sym=old_form=new_form to objcopy.
5. Add "-j section" for objcopy.
6. Fix i386 disassembler for fwait.
7. Fix a Sparc asm bug.
8. Add Ada demangle support.
9. Fix MIPS/ELF bugs.
10. Add some vxworks suppport.
11. Fix a.out assembler.

The file list:

1. binutils-2.12.90.0.11.tar.gz. Source code.
2. binutils-2.12.90.0.9-2.12.90.0.11.diff.gz. Patch against the
   previous beta source code.
3. binutils-2.12.90.0.11-1.i386.rpm. IA-32 binary RPM for RedHat 7.3.

There is no separate source rpm. You can do

# rpm -ta binutils-2.12.90.0.11.tar.gz

to create both binary and source rpms.

The primary sites for the beta Linux binutils are:

1. http://ftp.kernel.org/pub/linux/devel/binutils/

Thanks.


H.J. Lu
hjl@lucon.org
06/10/2002

From owner-linux-mips@oss.sgi.com Thu Jun 13 15:46:48 2002
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	Fri, 14 Jun 2002 00:31:43 +0200
Date: Fri, 14 Jun 2002 00:31:43 +0200
From: Richard Zidlicky <Richard.Zidlicky@stud.informatik.uni-erlangen.de>
To: Tom Rini <trini@kernel.crashing.org>
Cc: Roman Zippel <zippel@linux-m68k.org>,
   Linux/MIPS Development <linux-mips@oss.sgi.com>,
   Linux/m68k <linux-m68k@lists.linux-m68k.org>,
   Linux/PPC Development <linuxppc-dev@lists.linuxppc.org>
Subject: Re: [RFC and PATCH] Move the m68k genrtc driver into 2.5 and use on PPC
Message-ID: <20020614003143.C1230@linux-m68k.org>
References: <20020613190646.GT13541@opus.bloom.county>
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On Thu, Jun 13, 2002 at 12:06:46PM -0700, Tom Rini wrote:
Hi,
 
> Secondly to the m68k people, does anyone have an objection (or would
> like to do it themselves?) with me trying to get Linus to take the
> changes to include/linux/rtc.h?  radeonfb.c currently conflicts with the
> 'pll_info' struct, but Ani Joshi is renaming it.

I will be happy whoever gets it in. The pll_info stuff could be
renamed in genrtc.c as well.

> 	Also, CONFIG_GEN_RTC
> used to be define_bool'ed to y on CONFIG_SUN3, but I'm not sure if that
> looks nice in a common file.  Any idea on how to solve this nicely?

m68k doesn't source drivers/chars/Config.in so just don't do
anything about it?


> diff -Nru a/drivers/char/Config.help b/drivers/char/Config.help
> --- a/drivers/char/Config.help	Thu Jun 13 12:03:49 2002
> +++ b/drivers/char/Config.help	Thu Jun 13 12:03:49 2002
> @@ -1058,6 +1058,34 @@
>    The module is called rtc.o. If you want to compile it as a module,
>    say M here and read <file:Documentation/modules.txt>.
>  
> +Generic Real Time Clock Support
> +CONFIG_GEN_RTC
> +  If you say Y here and create a character special file /dev/rtc with
> +  major number 10 and minor number 135 using mknod ("man mknod"), you
> +  will get access to the real time clock (or hardware clock) built
> +  into your computer.
> +
> +  In 2.4 and later kernels this is the only way to set and get rtc
> +  time on m68k systems so it is highly recommended.
> +
> +  It reports status information via the file /proc/driver/rtc and its
> +  behaviour is set by various ioctls on /dev/rtc. If you enable the
> +  "extended RTC operation" below it will also provide an emulation
> +  for RTC_UIE which is required by some programs and may improve
> +  precision in some cases.
> +
> +  This driver is also available as a module ( = code which can be
> +  inserted in and removed from the running kernel whenever you want).
> +  The module is called rtc.o. If you want to compile it as a module,
			 ^^^^^^^
genrtc.o ... I could swear I fixed it in m68k CVS ;)


Richard

From owner-linux-mips@oss.sgi.com Thu Jun 13 16:15:24 2002
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Date: Fri, 14 Jun 2002 01:17:44 +0200 (CEST)
From: Vivien Chappelier <vivien.chappelier@enst-bretagne.fr>
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To: Ralf Baechle <ralf@uni-koblenz.de>
cc: linux-mips@oss.sgi.com
Subject: Re: R10K speculative store on non-coherent systems workaround proposal
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On 10 Jun 2002, Ralf Baechle wrote:

> Looks like a good start but unfortunately your concept is ignoring
> userspace entirely.

indeed ;)

> You might have to deal with mmapped pages that are being written to
> backing storage.

True.

> In such a case you'll have to trackdown all mappings and disable
> access to them

I don't think so. Before doing DMA, pages will be locked with lock_page
(mm/filemap.c) and processes accessing this page will be
forced to wait for I/O completion. Quote from include/asm/page.h:
>> * During disk I/O, PG_locked is used. This bit is set before I/O
>> * and reset when I/O completes. page->wait is a wait queue of all
>> * tasks waiting for the I/O on this page to complete.

Thus, no user process should be accessing the page during the I/O transfer
(this would cause problems anyway, even on coherent
architectures). However, now our problem is that the mappings may still be
in the TLB, and thus speculative stores could be executed to the DMA
buffer. However, this can be easily worked around by flushing the TLB
entries for these mappings (we only have 64 to check, or we can do the
bovine flush_tlb_all ;)). Thus mappings will be invalid for the CPU,
causing an exception that will abort the speculative store.
Does that sound ok?

> Intially I guess you can simply avoid this hairy job by doing all DMA using
> bounce buffers only.  Expensive but doable ...

I'd prefer to avoid those expensive memcpy if possible..

Vivien.


From owner-linux-mips@oss.sgi.com Thu Jun 13 23:18:53 2002
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Date: Thu, 13 Jun 2002 17:27:31 -0700
From: Tom Rini <trini@kernel.crashing.org>
To: Richard Zidlicky <Richard.Zidlicky@stud.informatik.uni-erlangen.de>
Cc: Roman Zippel <zippel@linux-m68k.org>,
   Linux/MIPS Development <linux-mips@oss.sgi.com>,
   Linux/m68k <linux-m68k@lists.linux-m68k.org>,
   Linux/PPC Development <linuxppc-dev@lists.linuxppc.org>
Subject: Re: [RFC and PATCH] Move the m68k genrtc driver into 2.5 and use on PPC
Message-ID: <20020614002731.GC13541@opus.bloom.county>
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On Fri, Jun 14, 2002 at 12:31:43AM +0200, Richard Zidlicky wrote:
> On Thu, Jun 13, 2002 at 12:06:46PM -0700, Tom Rini wrote:
> Hi,
>  
> > Secondly to the m68k people, does anyone have an objection (or would
> > like to do it themselves?) with me trying to get Linus to take the
> > changes to include/linux/rtc.h?  radeonfb.c currently conflicts with the
> > 'pll_info' struct, but Ani Joshi is renaming it.
> 
> I will be happy whoever gets it in. The pll_info stuff could be
> renamed in genrtc.c as well.

It could...  But I imagine it'll be fun getting that in either way. :)

> > 	Also, CONFIG_GEN_RTC
> > used to be define_bool'ed to y on CONFIG_SUN3, but I'm not sure if that
> > looks nice in a common file.  Any idea on how to solve this nicely?
> 
> m68k doesn't source drivers/chars/Config.in so just don't do
> anything about it?

Ah, it doesn't?  I suppose that will work too.. :)

> > diff -Nru a/drivers/char/Config.help b/drivers/char/Config.help
> > --- a/drivers/char/Config.help	Thu Jun 13 12:03:49 2002
> > +++ b/drivers/char/Config.help	Thu Jun 13 12:03:49 2002
> > @@ -1058,6 +1058,34 @@
> >    The module is called rtc.o. If you want to compile it as a module,
> >    say M here and read <file:Documentation/modules.txt>.
> >  
> > +Generic Real Time Clock Support
> > +CONFIG_GEN_RTC
> > +  If you say Y here and create a character special file /dev/rtc with
> > +  major number 10 and minor number 135 using mknod ("man mknod"), you
> > +  will get access to the real time clock (or hardware clock) built
> > +  into your computer.
> > +
> > +  In 2.4 and later kernels this is the only way to set and get rtc
> > +  time on m68k systems so it is highly recommended.
> > +
> > +  It reports status information via the file /proc/driver/rtc and its
> > +  behaviour is set by various ioctls on /dev/rtc. If you enable the
> > +  "extended RTC operation" below it will also provide an emulation
> > +  for RTC_UIE which is required by some programs and may improve
> > +  precision in some cases.
> > +
> > +  This driver is also available as a module ( = code which can be
> > +  inserted in and removed from the running kernel whenever you want).
> > +  The module is called rtc.o. If you want to compile it as a module,
> 			 ^^^^^^^
> genrtc.o ... I could swear I fixed it in m68k CVS ;)

I might have grabbed too old a version of that.  Fixing it now.

-- 
Tom Rini (TR1265)
http://gate.crashing.org/~trini/

From owner-linux-mips@oss.sgi.com Fri Jun 14 01:01:42 2002
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Date: Fri, 14 Jun 2002 10:03:16 +0200 (MEST)
From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Tom Rini <trini@kernel.crashing.org>
cc: Roman Zippel <zippel@linux-m68k.org>,
   Linux/MIPS Development <linux-mips@oss.sgi.com>,
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Subject: Re: [RFC and PATCH] Move the m68k genrtc driver into 2.5 and use on
 PPC
In-Reply-To: <20020613190646.GT13541@opus.bloom.county>
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On Thu, 13 Jun 2002, Tom Rini wrote:
> Secondly to the m68k people, does anyone have an objection (or would
> like to do it themselves?) with me trying to get Linus to take the
> changes to include/linux/rtc.h?  radeonfb.c currently conflicts with the

No objection at all :-) Thanks!

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


From owner-linux-mips@oss.sgi.com Fri Jun 14 04:48:21 2002
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From: "Domcan Sami" <domca_psg@email.com>
To: linux-mips@oss.sgi.com, linux-kernel@vger.kernel.org,
   redhat-list@redhat.com
Date: Fri, 14 Jun 2002 06:50:49 -0500
Subject: Kernel - arch support(mips)
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Hi all,

I am trying to compile a program using a MIPS-LINUX cross compiler(gcc). I've set up a connection between my i386 Linux machine and a MIPS(RM7000) processor. This is again connected to a WinNT Terminal where there should be an output from the MIPS processor.

I have 2 kernels in my Linux machine under the directories:
1) /usr/src/linux - kernel version 2.2.14
2) /root/kernels/linux - kernel version 2.4.14

I am using a boot image generated from the older kernel for booting. The problem is the older kernel doesn't support MIPS architecture. What should I do to upgrade my kernel so that it supports MIPS architecture & that I'll be able to cross-compile my programs properly.

Domcan
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Subject: Need kernel for Origin200
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Anybody able to assist me in building a kernel for the Orgin200
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From owner-linux-mips@oss.sgi.com Fri Jun 14 17:11:00 2002
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From: "Sam+" <iskoo@ms45.hinet.net>
To: "Sam" <iskoo@ms45.hinet.net>, <linux-mips@oss.sgi.com>
Subject: # CrossCompiler (Big Endian)
Date: Fri, 14 Jun 2002 15:28:10 +0800
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Hi,

    Could andbody give some suggestion?
    thanks

--Sam
  ----- Original Message -----=20
  From: Sam=20
  To: linux-mips@oss.sgi.com=20
  Sent: Thursday, June 13, 2002 5:50 PM
  Subject: # CrossCompiler (Big Endian)


  Hi everybody,

      I got some information to build Little Endian CrossCompiler for =
mips
      even precompiled binary files, and work well.....

      However, I have to build a Big Endian's one
      Should I get the binutil and glibc for big endian firstly?

      Is there any homepage for reference on web?
      anybody know the flow?=20
      gcc -BE is not work?

      thanks all!

  --Sam

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<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Hi,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; Could andbody give some=20
suggestion?</FONT></DIV>
<DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; thanks</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>--Sam</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt =B7s=B2=D3=A9=FA=C5=E9">----- Original =
Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt =B7s=B2=D3=A9=FA=C5=E9; =
font-color: black"><B>From:</B>=20
  <A href=3D"mailto:iskoo@ms45.hinet.net" =
title=3Diskoo@ms45.hinet.net>Sam</A>=20
</DIV>
  <DIV style=3D"FONT: 10pt =B7s=B2=D3=A9=FA=C5=E9"><B>To:</B> <A=20
  href=3D"mailto:linux-mips@oss.sgi.com"=20
  title=3Dlinux-mips@oss.sgi.com>linux-mips@oss.sgi.com</A> </DIV>
  <DIV style=3D"FONT: 10pt =B7s=B2=D3=A9=FA=C5=E9"><B>Sent:</B> =
Thursday, June 13, 2002 5:50=20
PM</DIV>
  <DIV style=3D"FONT: 10pt =B7s=B2=D3=A9=FA=C5=E9"><B>Subject:</B> # =
CrossCompiler (Big=20
Endian)</DIV>
  <DIV><BR></DIV>
  <DIV><FONT size=3D2>Hi everybody,</FONT></DIV>
  <DIV>&nbsp;</DIV>
  <DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; I got some information to build =
Little=20
  Endian CrossCompiler for mips</FONT></DIV>
  <DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; even precompiled binary files, =
and work=20
  well.....</FONT></DIV>
  <DIV>&nbsp;</DIV>
  <DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; However, I have to build a Big =
Endian's=20
  one</FONT></DIV>
  <DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; Should I get the binutil and =
glibc for=20
  big endian firstly?</FONT></DIV>
  <DIV>&nbsp;</DIV>
  <DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; Is there any homepage for =
reference on=20
  web?</FONT></DIV>
  <DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; anybody know the flow? =
</FONT></DIV>
  <DIV><FONT size=3D2>&nbsp;&nbsp; &nbsp;gcc -BE is not =
work?</FONT></DIV>
  <DIV>&nbsp;</DIV>
  <DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; thanks all!</FONT></DIV>
  <DIV>&nbsp;</DIV>
  <DIV><FONT size=3D2>--Sam</FONT></DIV></BLOCKQUOTE></BODY></HTML>

------=_NextPart_000_0045_01C213B8.170810F0--

From owner-linux-mips@oss.sgi.com Fri Jun 14 17:11:31 2002
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From: "David Christensen" <dpchrist@holgerdanske.com>
To: <linux-mips@oss.sgi.com>
Cc: "Domcan Sami" <domca_psg@email.com>
References: <20020614115049.16384.qmail@email.com>
Subject: Re: Kernel - arch support(mips)
Date: Fri, 14 Jun 2002 11:15:35 -0700
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linux-mips@oss.sgi.com:

Domcan Sami <domca_psg@email.com> wrote:
> I am trying to compile a program using a MIPS-LINUX cross compiler
> (gcc). I've set up a connection between my i386 Linux machine and a
> MIPS(RM7000) processor. This is again connected to a WinNT Terminal
> where there should be an output from the MIPS processor.
>
> I have 2 kernels in my Linux machine under the directories:
> 1) /usr/src/linux - kernel version 2.2.14
> 2) /root/kernels/linux - kernel version 2.4.14
>
> I am using a boot image generated from the older kernel for booting.
> The problem is the older kernel doesn't support MIPS architecture.
> What should I do to upgrade my kernel so that it supports MIPS
> architecture & that I'll be able to cross-compile my programs
> properly.

Please provide more information:

1.  What is your target platform -- e.g. make of model of the board or
    computer that has the RM7000 processor on/in it?

2.  Does the target support Linux, does it have a ROM monitor, or is it
    a raw embedded target (e.g. requires crt0)?


David Christensen
dpchrist@holgerdanske.com


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Subject: # CrossCompiler (Big Endian)
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Hi everybody,

    I got some information to build Little Endian CrossCompiler for mips
    even precompiled binary files, and work well.....

    However, I have to build a Big Endian's one
    Should I get the binutil and glibc for big endian firstly?

    Is there any homepage for reference on web?
    any sample?

    thanks all!

--Sam

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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Hi everybody,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; I got some information to build =
Little=20
Endian CrossCompiler for mips</FONT></DIV>
<DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; even precompiled binary files, =
and work=20
well.....</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; However, I have to build a Big =
Endian's=20
one</FONT></DIV>
<DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; Should I get the binutil and =
glibc for big=20
endian firstly?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; Is there any homepage for =
reference on=20
web?</FONT></DIV>
<DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; any sample?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>&nbsp;&nbsp;&nbsp; thanks all!</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>--Sam</FONT></DIV></BODY></HTML>

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Subject: MIPS RPM binaries now available for LTP.
To: ltp-list@lists.sourceforge.net, linux-mips@oss.sgi.com
Cc: Carsten Langgaard <carstenl@mips.com>, Eric LEBOEUF <eric.leboeuf@free.fr>
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Thanks to Carsten Langgaard for volunteering to create the MIPS binary
RPMS.  Carsten doesn't have time right now to actually run and test the
testsuite, so could some MIPS users please download the appropriate binary
(big or little endian) and give us feedback.

Thanks,
- Robbie

Robert V. Williamson <robbiew@us.ibm.com>
Linux Test Project
IBM Linux Technology Center
Phone: (512) 838-9295   T/L: 638-9295
http://ltp.sourceforge.net


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Date: Mon, 10 Jun 2002 13:36:52 -0700
From: "H . J . Lu" <hjl@lucon.org>
To: linux-gcc@vger.kernel.org, GNU C Library <libc-alpha@sources.redhat.com>,
   gcc@gcc.gnu.org, Kenneth Albanowski <kjahds@kjahds.com>,
   Mat Hostetter <mat@lcs.mit.edu>,
   Andy Dougherty <doughera@lafcol.lafayette.edu>,
   Warner Losh <imp@village.org>, linux-mips@oss.sgi.com,
   Ron Guilmette <rfg@monkeys.com>,
   "Polstra; John" <linux-binutils-in@polstra.com>,
   Ralf Baechle <ralf@mailhost.uni-koblenz.de>,
   Linas Vepstas <linas@linas.org>, Feher Janos <aries@hal2000.terra.vein.hu>,
   Leonard Zubkoff <lnz@dandelion.com>, "Steven J. Hill" <sjhill@cotw.com>
Subject: The Linux binutils 2.12.90.0.11 is released.
Message-ID: <20020610133652.A27414@lucon.org>
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This is the beta release of binutils 2.12.90.0.11 for Linux, which is
based on binutils 2002 0608 in CVS on sourecs.redhat.com plus various
changes. It is purely for Linux.

The Linux/mips support is added. You have to use

# rpm --target=[mips|mipsel] -ta binutils-xx.xx.xx.xx.xx.tar.gz

to build it. Or you can read mips/README in the source tree to apply
the mips patches and build it by hand.

FYI, the binutils man pages now are generated from the texinfo files
during the build. As the result, those man pages may be changed for
each build even if you only have done

# ..../configure ...
# make

That means you may have many failures on the man pages when you apply
the binutils diffs next time. Those failures can be safely ignored.
You should remove all those man pages from your source tree by

# find -name *.1 | xargs rm -f
# find -name *.1.rej | xargs rm -f
# find -name *.man | xargs rm -f
# find -name *.man.rej | xargs rm -f

I am planning to make the public release soon. Please test it as much
as you can.

Please report any bugs related to binutils 2.12.90.0.11 to hjl@lucon.org.

For arm-linux targets, there are some important differences in behaviour 
between these tools and binutils 2.9.1.0.x.  The linker emulation name has 
changed from elf32arm{26} to armelf_linux{26}.  Also, the "-p" flag must be 
passed with the linker when working with object files (or static libraries) 
created using older versions of the assembler.  If this flag is omitted the 
linker will silently generate bad output when given old input files.

To get the correct behaviour from gcc, amend the *link section of your specs 
file as follows:

*link:
%{h*} %{version:-v}    %{b} %{Wl,*:%*}    %{static:-Bstatic}    %{shared:-shared}    %{symbolic:-Bsymbolic}    %{rdynamic:-export-dynamic}    %{!dynamic-linker: -dynamic-linker /lib/ld-linux.so.2}    -X    %{mbig-endian:-EB} %{mapcs-26:-m armelf_linux26} %{!mapcs-26:-m armelf_linux} -p


Changes from binutils 2.12.90.0.9:

1. Update from binutils 2002 0608.
2. Fix an ELF/mips SHF_MERGE bug.

Changes from binutils 2.12.90.0.7:

1. Update from binutils 2002 0526.
2. Support "-z muldefs".

Changes from binutils 2.12.90.0.4:

1. Update from binutils 2002 0423.
2. ELF EH frame bug fix.
3. MIPS ELF visibility bug fix.

Changes from binutils 2.12.90.0.3:

1. Update from binutils 2002 0408.
2. Bug fixes for ELF/sparc.
3. Bug fixes for ELF/CRIS.

Changes from binutils 2.12.90.0.1:

1. Update from binutils 2002 0323.
2. Fix linking a.out relocatable files with ELF.
3. Fix a PPC altivec assembler bug.

Changes from binutils 2.11.93.0.2:

1. Update from binutils 2002 0307.
2. Add the .preinit_array/.init_array/.fini_array support.
3. Fix eh_frame.
4. Turn on combreloc by default.
5. Enable gprof for Linux/mips.

Changes from binutils 2.11.92.0.12.3:

1. Update from binutils 2002 0207.
2. Fix a weak symbol alpha linker bug for glibc.
3. More support for gcc 3.1.

Changes from binutils 2.11.92.0.12:

1. Fix a regression in 2.11.92.0.12 when linking with none-ELF object
files.

Changes from binutils 2.11.92.0.10:

1. Update from binutils 2001 1121.
2. Fix a linker symbol version bug for common symbols.
3. Update handling relocations against the discarded sections. You may
need to apply the kernel patch enclosed here to your kernel source. If
you still see things like

drivers/char/char.o(.data+0x46b4): undefined reference to `local symbols in discarded section .text.exit'

in the final kernel link, that means you have compiled a driver into
the kernel which has a reference to the symbol in a discarded section.
Kernel 2.4.17 or above should work fine.

4. Support "-march=xxx -mipsN" for mips gas if they are compatible.

Changes from binutils 2.11.92.0.7:

1. Update from binutils 2001 1021.
2. Fix the ELF/PPC linker.
3. Fix the ELF/cris linker.
4. Fix ELF strip.

Changes from binutils 2.11.92.0.5:

1. Update from binutils 2001 1016.
2. Fix all breakages introduced in 2.11.92.0.12.

Changes from binutils 2.11.90.0.31:

1. Update from binutils 2001 1005.
2. Support gcc 3.1 for ia64.
3. Support prelink for ELF/PPC.
4. Fix an ELF/x86 linker bug for Oracle.
5. Fix a weak symbol bug.
6. Support locale.

Changes from binutils 2.11.90.0.29:

1. Update from binutils 2001 0830.
2. Fix a mips linker bug.

Changes from binutils 2.11.90.0.27:

1. Update from binutils 2001 0827.
2. Fix an alpha assembler bug.
3. Fix an ia64 linker bug.
4. Fix a mips linker bug.
5. Support `-z combreloc|nocombreloc' in linker.

Changes from binutils 2.11.90.0.25:

1. Update from binutils 2001 0810.
2. Fix an x86 linker bug.

Changes from binutils 2.11.90.0.24:

1. Update from binutils 2001 0726.
2. Fix an x86 assembler bug.
3. "make check" in the windres test in binutils may call uudecode. We
are working on it.
4. "make check" fails the windres test in binutils if the i386/pe
is enabled in bfd. Fixed in the next release.
5. "make check" has 2 failures in the ld-selective test in ld on
Linux/alpha. They should be marked xfail. Fixed in the next release.

Changes from binutils 2.11.90.0.23:

1. Update from binutils 2001 0714.
2. Fix Sparc/ElF for Linux/sparc.
3. Fix Alpha/ELF for gcc 3.0.

Changes from binutils 2.11.90.0.19:

1. Update from binutils 2001 0706.
2. Fix objcopy/strip broken by accident.
3. Avoid COPY relocs on ia32.
4. Fix the ia64 assembler.
5. This release may not work on Linux/sparc due to the unaligned
relocation changes, which are not handled by all versions of glibc.
The current glibc in CVS on sourceware should be ok. The last known
working binutils for Linux/sparc is 2.11.90.0.8. We are working on it.

Changes from binutils 2.11.90.0.15:

1. Update from binutils 2001 0620.
2. Fix a static linking the PIC object files on ia32.
3. Add the verion script support for --export-dynamic. It can be used
to selectively export dynamic symbols from the executables.

Changes from binutils 2.11.90.0.8:

1. Update from binutils 2001 0610.
2. Fix a gas bug for gcc 3.0.

Changes from binutils 2.11.90.0.7:

1. Update from binutils 2001 0512.
2. Fix some P/III SSE 2 assembler bugs.
3. Fix DT_NEEDED and symbol version bugs.
4. Support hidden versioned symbols in DSOs.

Changes from binutils 2.11.90.0.6:

1. Update from binutils 2001 0427.
2. Fix the -Bsymbolic bug introduced in binutils 2.11.90.0.5.

Changes from binutils 2.11.90.0.5:

1. Update from binutils 2001 0425.
2. Update "ld --multilib-dir PATH".

Changes from binutils 2.11.90.0.4:

1. Update from binutils 2001 0414.
2. Fix an ia64 assembler bug.
3. Change Linux/MIPS to use the SVR4 MIPS ABI instead of the IRIX ABI.
since there are no supports for the IRIX ABI in glibc. The current
Linux/MIPS targets are elf64-tradlittlemips for little endian MIPS
instead of elf32-littlemips and elf64-tradbigmips for big endian MIPS
instead of elf32-bigmips. Glibc, gcc and kernel may have to be modified
for this change. 

Changes from binutils 2.11.90.0.1:

1. Update from binutils 2001 0401.
2. Fix a gas bug for the gcc from the CVS main trunk. It involves some
changes in gas. I compiled kernel 2.2.18, gcc and glibc under
Linux/ia32. The resulting binaries work fine. 
3. Fix the linker core dump on unsupported ELF binaries.

Changes from binutils 2.10.91.0.4:

1. Update from binutils 2001 0309.

Changes from binutils 2.10.91.0.2:

1. Update from binutils 2001 0223.
2. More ia64 bug fixes.

Changes from binutils 2.10.1.0.7:

1. Update from binutils 2001 0215.
2. More ia64 bug fixes. Support EFI and "ld -relax" on ia64.
3. Fix a weak definition, -Bsymbolic, non-PIC bug for ia32.

Changes from binutils 2.10.1.0.4:

1. Update from binutils 2001 0206.
2. Enable the IA64 support.
3. Now you need to use

# ld --oformat TARGET

instead of

# ld -oformat TARGET

The Linux kernel build may be affected. BTW

# ld --oformat TARGET

should work with all previous releases of binutils.

Changes from binutils 2.10.1.0.2:

1. Update from binutils 2000 1221.

Changes from binutils 2.10.0.33:

1. Update from binutils 2000 1119.
2. It has some symbol versioning related updates.

Changes from binutils 2.10.0.32:

1. Update from binutils 2000 1018.
2. A proper ELF/PPC visibility fix.
3. m68k-a.out is supposed to be fixed.

Changes from binutils 2.10.0.31:

1. Update from binutils 2000 1014.
2. An ELF/PPC weak symbol bug fix.
3. A new linkonce section name approach.
4. m68k-a.out is still broken. To be fixed.

Changes from binutils 2.10.0.29:

1. Update from binutils 2000 1011.
2. Back out the linkonce section name change so that C++ will work.
A different approach is being worked on.
3. m68k-a.out is known to be broken. To be fixed.

Changes from binutils 2.10.0.26:

1. Update from binutils 2000 1008.

Changes from binutils 2.10.0.24:

1. Update from binutils 2000 0907.

Changes from binutils 2.10.0.18:

1. Update from binutils 2000 0823. Fix DT_RPATH/DT_RUNPATH handling.
Fix the ELF/ia32 DSO not compiled with PIC.
2. Try to fix the ELF visibility bug on PPC with glibc 2.2.

Changes from binutils 2.10.0.12:

1. Update from binutils 2000 0720.
2. Fix the DT_NEEDED link bug.
3. Add the new DT_XXXX dynamic tags. Glibc 2.2 will use them at least
on libpthread.so.

Changes from binutils 2.10.0.9:

1. Update from binutils 2000 0701. Fix the parallel build in ld when PE
is enabled.

Changes from binutils 2.9.5.0.46:

1. Update from binutils 2000 0617. The demangler support for the new
g++ ABI. Minor fix for the ELF visibility. Fix linking non-ELF
relocatable object files under ELF with symbol versioning.
2. Support for linking PE relocatable object files under ia32/ELF.

Changes from binutils 2.9.5.0.42:

1. Update from binutils 2000 0604. The ELF visibility attribuite should
work correctly now.
2. The ia32 assembler has changed the way it assembles the "jmp"
instructions to the global symbols. The old assembler will optimize the
jump to the global symbol defined in the same source file so that no
relocation will be used. The new assembler will use relocation for
global jumps. It will mainly affect PIC asm code. The segment like

	.globl  __setjmp
__setjmp:
	...
	jmp __sigsetjmp
	...
	.globl __sigsetjmp
__sigsetjmp:

is no longer PIC safe since "jmp __sigsetjmp" jumps to a global symbol
and relocation will be used. Instead, it can be changed to

	.globl  __setjmp
__setjmp:
	...
	jmp sigsetjmp
	...
	.globl __sigsetjmp
__sigsetjmp:
sigsetjmp:

so that "jmp sigsetjmp" jumps to a local symbol and the new assembler
will optimize out the relocation.

Changes from binutils 2.9.5.0.41:

1. Update from binutils 2000 0512.
2. Add testsuite for ELF visibility.

Changes from binutils 2.9.5.0.37:

1. Update from binutils 2000 0502.
2. Support STV_HIDDEN and STV_INTERNAL.

Changes from binutils 2.9.5.0.35:

1. Update from binutils 2000 0418.
2. Fix an ld demangle style option bug.

Changes from binutils 2.9.5.0.34:

1. Update from binutils 2000 0412. Fix a relocation bug which affects
the Linux kernel compilation.
2. An ELF/PPC linker script update.

Changes from binutils 2.9.5.0.33:

1. Update from binutils 2000 0404. Fix the bug report bug.

Changes from binutils 2.9.5.0.32:

1. Update from binutils 2000 0403. Fix the 16bit ia32 assembler bug.

Changes from binutils 2.9.5.0.31:

1. Update from binutils 2000 0331. Fix the Linux/ARM assembler bug.
2. Fix a Debian assembler security bug.

Changes from binutils 2.9.5.0.29:

1. Update from binutils 2000 0319.
2. An ELF/alpha bug is fixed.

Changes from binutils 2.9.5.0.27:

1. Update from binutils 2000 0301.
2. A demangler bug is fixed.
3. A better fix for undefined symbols with -Bsymbolic when building
shared library.

Changes from binutils 2.9.5.0.24:

1. Update from binutils 2000 0204.
2. Added -taso to linker on alpha.
3. Fixed a -shared -Bsymbolic bug when PIC is not used.

Changes from binutils 2.9.5.0.22:

1. Update from binutils 2000 0113.
2. A symbol version bug is fixed.
3. A -Bsymbolic bug is fixed.

Changes from binutils 2.9.5.0.21:

1. Update from binutils 1999 1202.
2. Remove a MIPS/ELF change.
3. Enable SOM for HPPA.

Changes from binutils 2.9.5.0.19:

1. Update from binutils 1999 1122. An ia32 gas bug is fixed.

Changes from binutils 2.9.5.0.16:

1. Update from binutils 1999 1104.
2. i370 is changed to use EM_S370 and ELFOSABI_LINUX. Update readelf.
3. Fix Compaq's demangler support.

Changes from binutils 2.9.5.0.14:

1. Update from binutils 1999 1012. A gas bug which affects Linux 2.3.21
is fixed.
2. i370 update.
3. The new demangler code. You should use "--style=xxx" to select the
demnangle style instead of "--lang=xxx".

Changes from binutils 2.9.5.0.13:

1. Update from binutils 1999 0925.
2. Fix a -s and linker script bug.

Changes from binutils 2.9.5.0.12:

1. Update from binutils 1999 0922.
2. i370 update.

Changes from binutils 2.9.5.0.11:

1. Update from binutils 1999 0910. It fixed a PIC linker bug on ix86
   and sparc introduced in the last release.
2. i370 update.

Changes from binutils 2.9.5.0.10:

1. Update from binutils 1999 0906. It fixed a PIC linker bug on ix86
   and sparc.
2. Remove elf/hppa since it is WIP.

Changes from binutils 2.9.5.0.8:

1. Update from binutils 1999 0831. It allows spaces around '(' and ')'
   in x86 FP register names.

Changes from binutils 2.9.5.0.7:

1. Update from binutils 1999 0821.
2. Some MIPS changes.

Changes from binutils 2.9.5.0.6:

1. Update from binutils 1999 0813.
2. i370 update.

Changes from binutils 2.9.5.0.5:

1. Update from binutils 1999 0809. An ELF/Sparc ld bug is fixed.

Changes from binutils 2.9.5.0.4:

1. Update from binutils 1999 0806. A Solaris/Sparc gas bug is fixed.
2. Remove mips gas patches from binutils 2.9.1.0.25.

Changes from binutils 2.9.5.0.3:

1. Update from binutils 1999 0801.
2. Support for real mode x86 gcc.

Changes from binutils 2.9.4.0.8:

1. Update from binutils 1999 0719. A libc 5 related bug fix.
2. Fix a typo in mips gas.

Changes from binutils 2.9.4.0.7:

1. Update from binutils 1999 0710. A weak symbol bug

http://egcs.cygnus.com/ml/egcs-bugs/1999-07/msg00129.html

is fixed.

Changes from binutils 2.9.4.0.6:

1. Update from binutils 1999 0626.

Changes from binutils 2.9.4.0.5:

1. Update from binutils 1999 0620.
2. Remove my fwait fix and use the one in cvs.
3. Use "--only-section=section" instead of "--extract-section=section".
   for objcopy.

Changes from binutils 2.9.4.0.4:

1. Update from binutils 1999 0612.
2. Remove various temporary fixes of mine since those bugs are fixed
   now.

Changes from binutils 2.9.4.0.3:

1. Update from binutils 1999 0611.
2. Remove my ELF/Alpha bfd changes.
3. Use the local symbol copy fix in binutils 1999 0611.

Changes from binutils 2.9.4.0.2:

1. Update from binutils 1999 0607.
2. Remove my Sparc hacks.
3. Fix local symbol copy.

Changes from binutils 2.9.4.0.1:

1. Update from binutils 1999 0606.
2. Restore relocation overflow checking in binutils 2.9.1.0.25 so that
   Linux kernel can build.
3. Fix i370 for the new gas.

Changes from binutils 1999 0605:

1. Fix a -Bsymbolic bug for Linux/alpha.
2. Add ELF/i370.
3. Fix 8/16-bit relocations for i386.
4. Add --redefine-sym=old_form=new_form to objcopy.
5. Add "-j section" for objcopy.
6. Fix i386 disassembler for fwait.
7. Fix a Sparc asm bug.
8. Add Ada demangle support.
9. Fix MIPS/ELF bugs.
10. Add some vxworks suppport.
11. Fix a.out assembler.

The file list:

1. binutils-2.12.90.0.11.tar.gz. Source code.
2. binutils-2.12.90.0.9-2.12.90.0.11.diff.gz. Patch against the
   previous beta source code.
3. binutils-2.12.90.0.11-1.i386.rpm. IA-32 binary RPM for RedHat 7.3.

There is no separate source rpm. You can do

# rpm -ta binutils-2.12.90.0.11.tar.gz

to create both binary and source rpms.

The primary sites for the beta Linux binutils are:

1. http://ftp.kernel.org/pub/linux/devel/binutils/

Thanks.


H.J. Lu
hjl@lucon.org
06/10/2002

From owner-linux-mips@oss.sgi.com Sat Jun 15 12:58:53 2002
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How does GDB work under MIPS Linux? I'm trying to do a bring-up of an
embedded device, and it looks like the kernel is missing the code
needed to handle software breakpoints. Are there patches that need to
be applied to the kernel? 

-- 
-------------------------------------------------
Justin Wojdacki        
justin.wojdacki@analog.com         (408) 350-5032
Communications Processors Group -- Analog Devices

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From: Daniel Jacobowitz <dmj+@andrew.cmu.edu>
To: Justin Wojdacki <justin.wojdacki@analog.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: Debugging using GDB and gdbserver
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On Sat, Jun 15, 2002 at 01:01:24PM -0700, Justin Wojdacki wrote:
> 
> How does GDB work under MIPS Linux? I'm trying to do a bring-up of an
> embedded device, and it looks like the kernel is missing the code
> needed to handle software breakpoints. Are there patches that need to
> be applied to the kernel? 

No.  If you use a current GDB (I recommend 5.2 or CVS) it should work
just fine, if you are using a recent kernel (you didn't mention what
version you were looking at).

-- 
Daniel Jacobowitz                           Debian GNU/Linux Developer
MontaVista Software                         Carnegie Mellon University

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Date: Sat, 15 Jun 2002 13:29:56 -0700
From: Justin Wojdacki <justin.wojdacki@analog.com>
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Daniel Jacobowitz wrote:
> 
> On Sat, Jun 15, 2002 at 01:01:24PM -0700, Justin Wojdacki wrote:
> >
> > How does GDB work under MIPS Linux? I'm trying to do a bring-up of an
> > embedded device, and it looks like the kernel is missing the code
> > needed to handle software breakpoints. Are there patches that need to
> > be applied to the kernel?
> 
> No.  If you use a current GDB (I recommend 5.2 or CVS) it should work
> just fine, if you are using a recent kernel (you didn't mention what
> version you were looking at).
> 
> --
> Daniel Jacobowitz                           Debian GNU/Linux Developer
> MontaVista Software                         Carnegie Mellon University

Sorry, I'm using the 2.4.10 kernel and GDB 5.2. What I see happening
is the BREAK 5 instruction from a software breakpoint is hit, and the
kernel loops continuously on that, as it appears to have no way to
deal with that exception. I'm running gdbserver on the MIPS target and
gdb as a cross-debugger on an x86 host (RedHat 7.1). To me, it looks
like when the debugging breakpoint is hit, gdbserver should get
scheduled to run and handle the breakpoint, but instead the child
keep's getting scheduled. 

-- 
-------------------------------------------------
Justin Wojdacki        
justin.wojdacki@analog.com         (408) 350-5032
Communications Processors Group -- Analog Devices

From owner-linux-mips@oss.sgi.com Sat Jun 15 13:35:57 2002
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From: Daniel Jacobowitz <dmj+@andrew.cmu.edu>
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On Sat, Jun 15, 2002 at 01:29:56PM -0700, Justin Wojdacki wrote:
> Daniel Jacobowitz wrote:
> > 
> > On Sat, Jun 15, 2002 at 01:01:24PM -0700, Justin Wojdacki wrote:
> > >
> > > How does GDB work under MIPS Linux? I'm trying to do a bring-up of an
> > > embedded device, and it looks like the kernel is missing the code
> > > needed to handle software breakpoints. Are there patches that need to
> > > be applied to the kernel?
> > 
> > No.  If you use a current GDB (I recommend 5.2 or CVS) it should work
> > just fine, if you are using a recent kernel (you didn't mention what
> > version you were looking at).
> > 
> > --
> > Daniel Jacobowitz                           Debian GNU/Linux Developer
> > MontaVista Software                         Carnegie Mellon University
> 
> Sorry, I'm using the 2.4.10 kernel and GDB 5.2. What I see happening
> is the BREAK 5 instruction from a software breakpoint is hit, and the
> kernel loops continuously on that, as it appears to have no way to
> deal with that exception. I'm running gdbserver on the MIPS target and
> gdb as a cross-debugger on an x86 host (RedHat 7.1). To me, it looks
> like when the debugging breakpoint is hit, gdbserver should get
> scheduled to run and handle the breakpoint, but instead the child
> keep's getting scheduled. 

Software breakpoints have worked at least as far back as 2.4.2.  This
most likely means that the exception handling for your board is broken.

-- 
Daniel Jacobowitz                           Debian GNU/Linux Developer
MontaVista Software                         Carnegie Mellon University

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Date: Sat, 15 Jun 2002 13:45:07 -0700
From: Justin Wojdacki <justin.wojdacki@analog.com>
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Daniel Jacobowitz wrote:
> 
> Software breakpoints have worked at least as far back as 2.4.2.  This
> most likely means that the exception handling for your board is broken.
> 
> --
> Daniel Jacobowitz                           Debian GNU/Linux Developer
> MontaVista Software                         Carnegie Mellon University

What exception handling is the board expected to provide? 

-- 
-------------------------------------------------
Justin Wojdacki        
justin.wojdacki@analog.com         (408) 350-5032
Communications Processors Group -- Analog Devices

From owner-linux-mips@oss.sgi.com Sat Jun 15 14:14:48 2002
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Subject: Re: Kernel - arch support(mips)
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linux-mips@oss.sgi.com:

> 1)I'm using is a Galileo Board EV64120A.
> 2)It is a raw embedded target & does not support Linux. I'm trying to
> print a string by compiling code with RM7000 & directing the output
> via Serial Port to a WinNT HyperTerminal.

Searching on Google, it looks like you have a EV64120A-7000 made by
Galileo Technology, Inc..  It is a PCI card that plugs into a PC, and
includes the PMON ROM monitor in flash.  Galileo appears to have been
sold to Marvell (www.marvell.com).  I don't see support or search links
on the Marvell web site.  I don't see Galileo or EV64120A on their
product page.  I suggest you send them an e-mail asking if and what
support is available.


I was going to recommend the SDE-MIPS toolkit by Algorithmics, but I
don't see your board in their Programmer's Guide.  Try asking them if
they support it:

    http://www.algor-uk.com/


To be blunt, trying to make an older, slower, and unsupported board work
is going to be difficult.  It might not be possible.  If you can, get a
current, complete, and well-supported MIPS development system -- board,
ICE/JTAG, ROM monitor/ embedded OS, development toolchain, etc..


David Christensen
dpchrist@holgerdanske.com







From owner-linux-mips@oss.sgi.com Sat Jun 15 14:46:59 2002
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Subject: reenabling interrupts on return from function
From: Justin Carlson <justin@cs.cmu.edu>
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I'm obviously missing something basic here.

Looking at stackframe.h, I see this code as a part of RESTORE_SOME


		mfc0	t0, CP0_STATUS;                  \
		.set	pop;                             \
		ori	t0, 0x1f;                        \
		xori	t0, 0x1f;                        \
		mtc0	t0, CP0_STATUS;                  

Here, we're explicitly clearing the IE bit (among others) in the status
register, and we leave it cleared.  The status register is not touched
again until we do an eret.

First, why do we explicitly clear the IE bit, when we're running with
the EXL bit set?  And where is the black magic that is re-enabling
interrupts for the return to usermode?

I must be missing something really fundamental here.  Anyone care to
point out my obvious gaps of knowledge?  :) 

Thanks,
  Justin




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Date: Sat, 15 Jun 2002 15:16:05 -0700
From: Justin Wojdacki <justin.wojdacki@analog.com>
Reply-To: justin.wojdacki@analog.com
Organization: Analog Devices, Communications Processors Group
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To: Daniel Jacobowitz <dmj+@andrew.cmu.edu>
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Subject: Re: Debugging using GDB and gdbserver
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Daniel Jacobowitz wrote:
> 
> Software breakpoints have worked at least as far back as 2.4.2.  This
> most likely means that the exception handling for your board is broken.
> 

Sorry, originally misinterpretted your use of "board" as referring to
the board itself, and perhaps PMON (I've found a number of references
online to GDB talking to PMON, but not much else). 

So what I've found by looking at other board-specific code revolves
around GDB talking to an in-kernel stub via the serial port. As the
board I'm working with has an unreliable serial port (and some
incarnations don't even have that), what about ethernet-based
debugging? Is that do-able, say via putDebugChar() (although I suspect
this poses an initialization problem)? 

Thanks for the info so far. 

-- 
-------------------------------------------------
Justin Wojdacki        
justin.wojdacki@analog.com         (408) 350-5032
Communications Processors Group -- Analog Devices

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Subject: Re: reenabling interrupts on return from function
From: Justin Carlson <justin@cs.cmu.edu>
To: Justin Carlson <justin@cs.cmu.edu>
Cc: linux-mips@oss.sgi.com
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On Sat, 2002-06-15 at 14:49, Justin Carlson wrote:
> I'm obviously missing something basic here.
> 
> Looking at stackframe.h, I see this code as a part of RESTORE_SOME
> 
> 
> 		mfc0	t0, CP0_STATUS;                  \
> 		.set	pop;                             \
> 		ori	t0, 0x1f;                        \
> 		xori	t0, 0x1f;                        \
> 		mtc0	t0, CP0_STATUS;                  
> 

OK, this was a stupid question; the answer was staring me in the face
(the restoration of the status register from the stack), and I didn't
see it.

However, I still don't see the point of the above code.  Why do we
explicitly clear bits 4-0 of the status register just before reloading
it from the system stack?  

-Justin

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Date: Sat, 15 Jun 2002 17:26:45 -0500
From: Daniel Jacobowitz <dmj+@andrew.cmu.edu>
To: Justin Wojdacki <justin.wojdacki@analog.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: Debugging using GDB and gdbserver
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On Sat, Jun 15, 2002 at 03:16:05PM -0700, Justin Wojdacki wrote:
> Daniel Jacobowitz wrote:
> > 
> > Software breakpoints have worked at least as far back as 2.4.2.  This
> > most likely means that the exception handling for your board is broken.
> > 
> 
> Sorry, originally misinterpretted your use of "board" as referring to
> the board itself, and perhaps PMON (I've found a number of references
> online to GDB talking to PMON, but not much else). 
> 
> So what I've found by looking at other board-specific code revolves
> around GDB talking to an in-kernel stub via the serial port. As the
> board I'm working with has an unreliable serial port (and some
> incarnations don't even have that), what about ethernet-based
> debugging? Is that do-able, say via putDebugChar() (although I suspect
> this poses an initialization problem)? 
> 
> Thanks for the info so far. 

Wait, wait.  What are you trying to do?  Originally you were talking
about userspace debugging via gdbserver.  Now you're talking about
kernel debugging via kgdb.  They're separate (and coexisting can cause
problems if you are not careful with your exception handlers; I do not
remember when my patches to make that work went into the tree, or if
someone else did it).

gdbserver can just use TCP.

-- 
Daniel Jacobowitz                           Debian GNU/Linux Developer
MontaVista Software                         Carnegie Mellon University

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Message-ID: <3D0BC248.16CB7EC2@analog.com>
Date: Sat, 15 Jun 2002 15:40:08 -0700
From: Justin Wojdacki <justin.wojdacki@analog.com>
Reply-To: justin.wojdacki@analog.com
Organization: Analog Devices, Communications Processors Group
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Subject: Re: Debugging using GDB and gdbserver
References: <3D0B9D14.BFE27F7E@analog.com> <20020615151413.A19123@crack.them.org> <3D0BA3C4.79ED2B5D@analog.com> <20020615153831.B19123@crack.them.org> <3D0BBCA5.5A0D722A@analog.com> <20020615172645.A19472@crack.them.org>
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Daniel Jacobowitz wrote:
>
> Wait, wait.  What are you trying to do?  Originally you were talking
> about userspace debugging via gdbserver.  Now you're talking about
> kernel debugging via kgdb.  They're separate (and coexisting can cause
> problems if you are not careful with your exception handlers; I do not
> remember when my patches to make that work went into the tree, or if
> someone else did it).
> 
> gdbserver can just use TCP.
> 
> --
> Daniel Jacobowitz                           Debian GNU/Linux Developer
> MontaVista Software                         Carnegie Mellon University

Sorry for the confusion. I've been discussing userspace debugging via
gdbserver the entire time. However, I've noticed that gdbserver
doesn't seem to be fully functional because the kernel doesn't seem to
be handling the "BREAK 5" instruction correctly. You mentioned
problems with board exception handling and I looked at the ddb series
board support code. In there, I found handling for software
breakpoints, and got the impression from the code that it was a
general debugging interface, not just for kernel debugging. Again,
sorry for the confusion.

As it stands right now, when I get hit a "BREAK 5" instruction,
gdbserver never get's a chance to handle it, as the kernel keeps
scheduling the child process I'm trying to debug, and hitting the
"BREAK 5" instruction over and over again. What I can't seem to find
out is how gdbserver is supposed to get scheduled again. 

-- 
-------------------------------------------------
Justin Wojdacki        
justin.wojdacki@analog.com         (408) 350-5032
Communications Processors Group -- Analog Devices

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From: Daniel Jacobowitz <dmj+@andrew.cmu.edu>
To: Justin Wojdacki <justin.wojdacki@analog.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: Debugging using GDB and gdbserver
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On Sat, Jun 15, 2002 at 03:40:08PM -0700, Justin Wojdacki wrote:
> Daniel Jacobowitz wrote:
> >
> > Wait, wait.  What are you trying to do?  Originally you were talking
> > about userspace debugging via gdbserver.  Now you're talking about
> > kernel debugging via kgdb.  They're separate (and coexisting can cause
> > problems if you are not careful with your exception handlers; I do not
> > remember when my patches to make that work went into the tree, or if
> > someone else did it).
> > 
> > gdbserver can just use TCP.
> > 
> > --
> > Daniel Jacobowitz                           Debian GNU/Linux Developer
> > MontaVista Software                         Carnegie Mellon University
> 
> Sorry for the confusion. I've been discussing userspace debugging via
> gdbserver the entire time. However, I've noticed that gdbserver
> doesn't seem to be fully functional because the kernel doesn't seem to
> be handling the "BREAK 5" instruction correctly. You mentioned
> problems with board exception handling and I looked at the ddb series
> board support code. In there, I found handling for software
> breakpoints, and got the impression from the code that it was a
> general debugging interface, not just for kernel debugging. Again,
> sorry for the confusion.
> 
> As it stands right now, when I get hit a "BREAK 5" instruction,
> gdbserver never get's a chance to handle it, as the kernel keeps
> scheduling the child process I'm trying to debug, and hitting the
> "BREAK 5" instruction over and over again. What I can't seem to find
> out is how gdbserver is supposed to get scheduled again. 

What should happen is that the child receives a signal (SIGTRAP) after
the exception.  Then it is scheduled again, drops into do_signal, and
the kernel notices that the traced bit is set and wakes the tracer.  I'd
guess your board needs to do something different to deliver the SIGTRAP
properly, if that isn't happening.

-- 
Daniel Jacobowitz                           Debian GNU/Linux Developer
MontaVista Software                         Carnegie Mellon University

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Date: Sat, 15 Jun 2002 16:05:36 -0700
From: Justin Wojdacki <justin.wojdacki@analog.com>
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Daniel Jacobowitz wrote:
> 
> What should happen is that the child receives a signal (SIGTRAP) after
> the exception.  Then it is scheduled again, drops into do_signal, and
> the kernel notices that the traced bit is set and wakes the tracer.  I'd
> guess your board needs to do something different to deliver the SIGTRAP
> properly, if that isn't happening.
> 
> --
> Daniel Jacobowitz                           Debian GNU/Linux Developer
> MontaVista Software                         Carnegie Mellon University

Okay, thanks for the clarification. :)

-- 
-------------------------------------------------
Justin Wojdacki        
justin.wojdacki@analog.com         (408) 350-5032
Communications Processors Group -- Analog Devices

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Date: Sat, 15 Jun 2002 18:56:30 -0500
From: Louis Hamilton <hamilton@redhat.com>
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Subject: Bug in Linux?  fcr31 not being saved-restored
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We have a customer here testing a 2.4.16 mips kernel on an embedded
Linux RM7000/SR71000 based system who has written a test that they
believe has uncovered a bug in Linux.  The FPU control register appears
to not get saved and restored.  I've reproduced the problem described
below and find the results consistent with their description.  The
problem occurs on both the RM7000 and SR71000 cpus.

It looks like save_fp_context and restore_fp_context are not being
called since the kernel save-restore logic thinks the process is not 
using floating point math.  If you do some fp math before calling the
test routine below, it seems to works fine.

Is this a known caveat?  A true bug?  Or a contorted corner case
unlikely to be seen under typical end-user usage (see customer's
last paragraph :-) ?   If true bug, recommended remedy?

TIA,
Louis

Louis Hamilton
hamilton@redhat.com


------ customer reports the following: ---------
We found a bug in Linux.  A ^C (control-C) typed into a shell (or a
running program, it doesn't matter), causes the FCR (floating-point
control register) to be corrupted in another, unrelated process.  This
is repeatable behavior.

This can be reproduced with the following short assembly language
program that loops forever, waiting for the FCR to change.

	.align 2
	.globl mips_float_debug_loop
mips_float_debug_loop:
	li	$9, 0xF000F02F
	ctc1    $9, $31		# set FCR to some non-zero value
	nop
1:	cfc1	$8, $31		# get FCR
	beq	$8, $9, 1b	# spin, waiting for FCR to change
	nop
	or	$2, $0, $8
	jr    $31
	nop

You can call this function from a short C program and the return value
is the (corrupted) FCR, which turns out to alwyas be: 0x00000002.

Run the above loop in one window (connected to the board using telnet)
and then in another window (connected to the same board) type ^C.

I'm surprised this bug hasn't been encountered by other MIPS vendors.

<end>



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Message-ID: <3D0D7F98.566B3176@mips.com>
Date: Mon, 17 Jun 2002 08:20:09 +0200
From: Carsten Langgaard <carstenl@mips.com>
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To: Louis Hamilton <hamilton@redhat.com>
CC: linux-mips@oss.sgi.com, sandcraft-elinux-project@redhat.com
Subject: Re: Bug in Linux?  fcr31 not being saved-restored
References: <3D0BD42E.20602@redhat.com>
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This is one of the bugs, among others, we have fixed.
I'm not sure, if Ralf have integrated the patches we send him yet.

/Carsten

Louis Hamilton wrote:

> We have a customer here testing a 2.4.16 mips kernel on an embedded
> Linux RM7000/SR71000 based system who has written a test that they
> believe has uncovered a bug in Linux.  The FPU control register appears
> to not get saved and restored.  I've reproduced the problem described
> below and find the results consistent with their description.  The
> problem occurs on both the RM7000 and SR71000 cpus.
>
> It looks like save_fp_context and restore_fp_context are not being
> called since the kernel save-restore logic thinks the process is not
> using floating point math.  If you do some fp math before calling the
> test routine below, it seems to works fine.
>
> Is this a known caveat?  A true bug?  Or a contorted corner case
> unlikely to be seen under typical end-user usage (see customer's
> last paragraph :-) ?   If true bug, recommended remedy?
>
> TIA,
> Louis
>
> Louis Hamilton
> hamilton@redhat.com
>
> ------ customer reports the following: ---------
> We found a bug in Linux.  A ^C (control-C) typed into a shell (or a
> running program, it doesn't matter), causes the FCR (floating-point
> control register) to be corrupted in another, unrelated process.  This
> is repeatable behavior.
>
> This can be reproduced with the following short assembly language
> program that loops forever, waiting for the FCR to change.
>
>         .align 2
>         .globl mips_float_debug_loop
> mips_float_debug_loop:
>         li      $9, 0xF000F02F
>         ctc1    $9, $31         # set FCR to some non-zero value
>         nop
> 1:      cfc1    $8, $31         # get FCR
>         beq     $8, $9, 1b      # spin, waiting for FCR to change
>         nop
>         or      $2, $0, $8
>         jr    $31
>         nop
>
> You can call this function from a short C program and the return value
> is the (corrupted) FCR, which turns out to alwyas be: 0x00000002.
>
> Run the above loop in one window (connected to the board using telnet)
> and then in another window (connected to the same board) type ^C.
>
> I'm surprised this bug hasn't been encountered by other MIPS vendors.
>
> <end>

--
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From owner-linux-mips@oss.sgi.com Mon Jun 17 01:35:43 2002
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Date: Mon, 17 Jun 2002 14:07:46 +0530
To: linux-mips@oss.sgi.com
From: aditya <aditya.ps@ap.sony.com>
Subject: regarding jal instruction in mips
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hello,

I have a doubt w.r.t. Linux on mips.

in mips there is a instruction jal which jumps across 256 MB boundry. 
but this is a restriction as shared text (libraries) and private text (program's text) should be located within 256 MB boundry. Is it true ??

how this problem is solved in linux ???

Thanks
Aditya







From owner-linux-mips@oss.sgi.com Mon Jun 17 02:46:10 2002
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From: "Balakrishnan Ananthanarayanan" <balakris_ananth@email.com>
To: linux-mips@oss.sgi.com, linux-kernel@vger.kernel.org,
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Subject: Code error - why?
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I wrote a SAMPLE CODE - Hello.S to work for a cross-assembler mips-linux-as - but this is giving me an error message:
   ".data 
         quest: .asciiz "Hello World!"
    .text
    _start:
         la $a0, quest
         li $v0, 4
         syscall   "
       
The error messages are:
  " Hello.S line 5: illegal operands 'la' 
    Hello.S line 6: illegal operands 'li'"

Can anyone help? What is wrong?

-- 
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From owner-linux-mips@oss.sgi.com Mon Jun 17 03:54:33 2002
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Date: Mon, 17 Jun 2002 12:57:10 +0200
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I can see the 'dma_cache_inv_pc' routines (in the arch/mips/mm cache
files), in almost every incarnation, is actually doing a write-back
invalidation, why ?
My first thought was, that this will never work for the PCI devices
doing DMA, so I was wondering why it actually does work.
And the answer is, that this routine isn't used by the
PCI DMA functions, no matter what the DIRECTION of the DMA transfer is.
Has anyone got an idea why the while PCI DMA stuff is implemented this
way (only using write-back invalidations) ?
I would expect that we did a write-back invalidation of the D-cache,
when the direction was PCI_DMA_TODEVICE and only did invalidation of the
D-cache, when the direction was PCI_DMA_FROMDEVICE.

/Carsten


--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
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From owner-linux-mips@oss.sgi.com Mon Jun 17 04:14:25 2002
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aditya (aditya.ps@ap.sony.com) writes:

> I have a doubt w.r.t. Linux on mips.
> 
> in mips there is a instruction jal which jumps across 256 MB
> boundry.  but this is a restriction as shared text (libraries) and
> private text (program's text) should be located within 256 MB
> boundry. Is it true ??

In the usual Linux address map it isn't true: library code might
easily fail to be in the same 256Mbyte 'chunk' of virtual memory.

Linux/MIPS applications implement calls between modules (and for
relocatable libraries, calls inside modules too) with an indirection
through a table of pointers - the "global access table" or GOT.

We normally think of this as a way of providing suitably
position-independent code...  There's a fair description of this in my
book "See MIPS Run" under the heading "Sharing Library Code in the
MIPS ABI" - Chapter 10 or so.

-- 
Dominic Sweetman, 
Algorithmics Ltd
The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND
phone: +44 1223 706200 / fax: +44 1223 706250 / direct: +44 1223 706205
http://www.algor.co.uk

From owner-linux-mips@oss.sgi.com Mon Jun 17 04:32:56 2002
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Date: Mon, 17 Jun 2002 13:33:11 +0200
To: linux-mips@oss.sgi.com
Subject: DBE/IBE handling incompatibility
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hi,

i'd like to release GIO64 bus support. Before doing so DBE/IBE handling
should be done in the same fashion for both mips and mips64 (*). Currently
mips is using handler in handler via dbe_board_handler and ibe_board_handler 
which are not used anywhere while mips64 is using BUILD_HANDLER macro defined
in include/asm-mips64/exception.h (see arch/mips64/sgi-ip27/ip27-dbe-glue.S)
Unfortunately I have nearly zero knowledge of MIPS assembler, so I'm
unable to code mips way same as mips64 is... Help from someone more
experienced will be greatly appreciated :-)

(*) How GIO device detection works? each IP22 machine contains three GIO bus
slots. GIO device provides information about itself in first (three) word(s)
of address space it occupies. The only way how to detect GIO card is
trying to read word from it's base address. If DBE exception is generated 
then there is definitely no card present, otherwise read value encodes 
information about device.

	ladis

From owner-linux-mips@oss.sgi.com Mon Jun 17 04:51:20 2002
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Message-ID: <3D0DCDCB.252F5565@mips.com>
Date: Mon, 17 Jun 2002 13:53:47 +0200
From: Carsten Langgaard <carstenl@mips.com>
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The __access_ok macro in include/asm-mips64/uaccess.h need to be changed
in order to work correctly, it's a copy from the 32-bit kernel.
It's not good enough to simply check for the "sign bit" of the address.
The area between USEG (XUSEG) and KSEG0 will in 64-bit addressing mode
generate an address error, if
accessed. The size of the area depend on the number of virtual
addressing bits, implemented in the CPU.

I have tried to come up with a patch, please see below. Any thought ?
I also changed the macro in arch/mips64/kernel/unaligned.c

/Carsten


Index: include/asm-mips64//uaccess.h
===================================================================
RCS file:
/home/repository/sw/linux-2.4.18/include/asm-mips64/uaccess.h,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 uaccess.h
--- include/asm-mips64//uaccess.h       4 Mar 2002 11:13:26 -0000
1.1.1.1
+++ include/asm-mips64//uaccess.h       17 Jun 2002 11:35:32 -0000
@@ -12,6 +12,8 @@
 #include <linux/errno.h>
 #include <linux/sched.h>

+#include <asm/addrspace.h>
+
 #define STR(x)  __STR(x)
 #define __STR(x)  #x

@@ -40,16 +42,23 @@
  * than tests.
  *
  * Address valid if:
- *  - "addr" doesn't have any high-bits set
- *  - AND "size" doesn't have any high-bits set
- *  - AND "addr+size" doesn't have any high-bits set
- *  - OR we are in kernel mode.
+ *  - In user mode and "addr" and "addr+size" in USEG (or XUSEG).
+ *  - OR we are in kernel mode and "addr" and "addr+size" isn't in the
+ *    area between USEG (XUSEG) and KSEG0.
  */
 #define
__ua_size(size)                                                       \
        (__builtin_constant_p(size) && (signed long) (size) > 0 ? 0 :
(size))

-#define __access_ok(addr,size,mask)
\
-       (((signed long)((mask)&(addr | (addr + size) |
__ua_size(size)))) >= 0)
+static inline int
+__access_ok(unsigned long addr, unsigned long size, long mask)
+{
+       if (((mask) && ((addr | (addr+size)) >= KUSIZE)) ||
+           (((addr | (addr+size)) < K0BASE) &&
+            ((addr | (addr+size)) >= KUSIZE)))
+               return 0;
+       else
+               return 1;
+}

 #define __access_mask ((long)(get_fs().seg))


Index: arch/mips64/kernel/unaligned.c
===================================================================
RCS file:
/home/repository/sw/linux-2.4.18/arch/mips64/kernel/unaligned.c,v
retrieving revision 1.2
diff -u -r1.2 unaligned.c
--- arch/mips64/kernel/unaligned.c      23 May 2002 11:11:45 -0000
1.2
+++ arch/mips64/kernel/unaligned.c      17 Jun 2002 11:51:30 -0000
@@ -89,11 +89,14 @@
 #define __STR(x)  #x

 /*
- * User code may only access USEG; kernel code may access the
- * entire address space.
+ * User code may only access USEG;
+ * Kernel code may access the entire address space, except the area
between
+ * USEG (XUSEG) and KSEG0.
  */
-#define check_axs(pc,a,s)                              \
-       if ((long)(~(pc) & ((a) | ((a)+(s)))) < 0)      \
+#define check_axs(pc,a,s)
\
+        if (((pc < KUSIZE) && (((a) | ((a)+(s))) >= KUSIZE))
||               \
+           ((((a) | ((a)+(s))) < K0BASE) &&
\
+            (((a) | ((a)+(s))) >= KUSIZE)))
\
                goto sigbus;



--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From owner-linux-mips@oss.sgi.com Mon Jun 17 09:22:44 2002
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Subject: Re: __access_ok
From: Justin Carlson <justin@cs.cmu.edu>
To: Carsten Langgaard <carstenl@mips.com>
Cc: linux-mips@oss.sgi.com
In-Reply-To: <3D0DCDCB.252F5565@mips.com>
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On Mon, 2002-06-17 at 04:53, Carsten Langgaard wrote:

>   * Address valid if:
> - *  - "addr" doesn't have any high-bits set
> - *  - AND "size" doesn't have any high-bits set
> - *  - AND "addr+size" doesn't have any high-bits set
> - *  - OR we are in kernel mode.
> + *  - In user mode and "addr" and "addr+size" in USEG (or XUSEG).
> + *  - OR we are in kernel mode and "addr" and "addr+size" isn't in the
> + *    area between USEG (XUSEG) and KSEG0.

You also need to test for high bit set in size.  Otherwise, for example,
if a process was ok to access range 0x40000000-0x40003fff, 
access_ok(0x40001000, 0xfffff100) would return 1.  The addition will
wrap around, leading to all sorts of fun havoc.

-Justin


From owner-linux-mips@oss.sgi.com Mon Jun 17 09:26:55 2002
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Date: Mon, 17 Jun 2002 09:29:15 -0700
From: Justin Wojdacki <justin.wojdacki@analog.com>
Reply-To: justin.wojdacki@analog.com
Organization: Analog Devices, Communications Processors Group
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To: Balakrishnan Ananthanarayanan <balakris_ananth@email.com>
CC: linux-mips@oss.sgi.com
Subject: Re: Code error - why?
References: <20020617094851.30730.qmail@email.com>
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Balakrishnan Ananthanarayanan wrote:
> 
> I wrote a SAMPLE CODE - Hello.S to work for a cross-assembler mips-linux-as - but this is giving me an error message:
>    ".data
>          quest: .asciiz "Hello World!"
>     .text
>     _start:
>          la $a0, quest
>          li $v0, 4
>          syscall   "
> 
> The error messages are:
>   " Hello.S line 5: illegal operands 'la'
>     Hello.S line 6: illegal operands 'li'"
> 
> Can anyone help? What is wrong?
> 

$a0 and $v0 are what's probably giving you grief. Are you relying on
the assembler to know these symbols or are you including a file that
defines them. 

Just to be sure, try replacing $a0 with $4 and $v0 with $2 and see if
the code builds.

-- 
-------------------------------------------------
Justin Wojdacki        
justin.wojdacki@analog.com         (408) 350-5032
Communications Processors Group -- Analog Devices

From owner-linux-mips@oss.sgi.com Mon Jun 17 09:52:35 2002
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Date: Mon, 17 Jun 2002 18:55:14 +0200
To: linux-mips@oss.sgi.com
Subject: Re: Code error - why?
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Balakrishnan Ananthanarayanan wrote:
[snip]
>          la $a0, quest
>          li $v0, 4
>          syscall   "
>        
> The error messages are:
>   " Hello.S line 5: illegal operands 'la' 
>     Hello.S line 6: illegal operands 'li'"
> 
> Can anyone help? What is wrong?

The register names are wrong. The software names, if defined in some
assembler header, are 'a0' and 'v0', while the assembler recognized
hardware names are '$4' and '$2'.


Thiemo

From owner-linux-mips@oss.sgi.com Mon Jun 17 10:17:42 2002
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Date: Mon, 17 Jun 2002 10:17:08 -0700
From: William Jhun <wjhun@ayrnetworks.com>
To: Carsten Langgaard <carstenl@mips.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: PCI DMA transfer
Message-ID: <20020617101708.A28405@ayrnetworks.com>
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On Mon, Jun 17, 2002 at 12:57:10PM +0200, Carsten Langgaard wrote:
> I can see the 'dma_cache_inv_pc' routines (in the arch/mips/mm cache
> files), in almost every incarnation, is actually doing a write-back
> invalidation, why ?
> My first thought was, that this will never work for the PCI devices
> doing DMA, so I was wondering why it actually does work.

It ought to work, though it's just not as efficient. One clear problem
is that there is no wback/inv on pci_unmap_{single,sg}(). This will
cause a problem when a driver:

- calls pci_map_single()
- DMAs into the buffer
- calls pci_dma_sync_single() [eg, a buffer smaller than rx_copybreak in
  tulip]
- copies the buffer
- returns the buffer to the device
- does another DMA transfer
- this time calls pci_unmap_single() [eg, buffer > rx_copybreak]

Clearly, stale cache lines will remain after the first buffer copy. For
the time being, we can just put the flush in the pci_unmap_* calls. This
is also pretty lame as we are always needlessly flushing the cache one
extra time (in the map *and* in the unmap. Or in the map and in the
dma_sync). I've proposed some API changes to Dave Miller that should
solve this problem. Hopefully they'll be integrated in some way and we
can enjoy both correctness and optimal performance. :o) (BTW, we've
found that the performance implications of getting this stuff right *IS*
significant, and there is indeed a noticeable difference between doing
an invalidate and a writeback-invalidate, even if there is nothing to
write back.)

> And the answer is, that this routine isn't used by the
> PCI DMA functions, no matter what the DIRECTION of the DMA transfer is.
> Has anyone got an idea why the while PCI DMA stuff is implemented this
> way (only using write-back invalidations) ?

Broken cache routines? Apathy? :o) Most likely that this hasn't hit a
lot of people yet... (see below)

> I would expect that we did a write-back invalidation of the D-cache,
> when the direction was PCI_DMA_TODEVICE and only did invalidation of the
> D-cache, when the direction was PCI_DMA_FROMDEVICE.

I sent out a patch to change this a while ago, but it got dropped since
most implementations of dma_cache_wback() just call BUG(). I've been
meaning to get a patch ready for this as well, but haven't had the time.
Well, it's a slow Monday morning, so maybe I'll do it now. :o)

For architectures that can only do a wback/inv and not an inv or wback
by itself, it should be suitable to do a wback/inv in place. In effect,
an invalidate or writeback should only be requested as a performance
enhancement, and should not differ in correctness when replaced with a
writeback-invalidate. As such, code should not write something to cache,
do an invalidate some measured amount of time later and expect the write
to be completely invalidated. Is it reasonable to expect that code will
not do this? And doing a wback/inv in place of a wback does not seem
harmful to me... At least, I can't think of a case where it would be.

Agree? Disagree? I'll put together some patches shortly...

Will

From owner-linux-mips@oss.sgi.com Mon Jun 17 11:18:32 2002
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Subject: system.h asm fixes
From: Justin Carlson <justin@cs.cmu.edu>
To: linux-mips@oss.sgi.com
Cc: ralf@oss.sgi.com
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Looks to me like we're missing some proper asm clobber markers:

diff -u -r1.13 system.h
--- system.h	4 Feb 2002 17:35:51 -0000	1.13
+++ system.h	17 Jun 2002 18:18:56 -0000
@@ -41,7 +41,8 @@
 		"__sti"
 		: /* no outputs */
 		: /* no inputs */
-		: "memory");
+		: "$1","memory"
+		);
 }
 
 /*
@@ -73,7 +74,7 @@
 		"__cli"
 		: /* no outputs */
 		: /* no inputs */
-		: "memory");
+		: "$1","memory");
 }
 
 __asm__ (
@@ -110,7 +111,7 @@
 	"__save_and_cli\t%0"						\
 	: "=r" (x)							\
 	: /* no inputs */						\
-	: "memory")
+	: "$1","memory")
 
 __asm__(".macro\t__restore_flags flags\n\t"
 	".set\tpush\n\t"
@@ -136,7 +137,7 @@
 		"__restore_flags\t%0"					\
 		: "=r" (__tmp1)						\
 		: "0" (flags)						\
-		: "memory");						\
+		: "$1","memory");					\
 } while(0)
 
 #ifdef CONFIG_SMP


From owner-linux-mips@oss.sgi.com Mon Jun 17 12:33:19 2002
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Date: Mon, 17 Jun 2002 12:30:48 -0700
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To: Carsten Langgaard <carstenl@mips.com>
CC: Louis Hamilton <hamilton@redhat.com>, linux-mips@oss.sgi.com,
   sandcraft-elinux-project@redhat.com
Subject: Re: Bug in Linux?  fcr31 not being saved-restored
References: <3D0BD42E.20602@redhat.com> <3D0D7F98.566B3176@mips.com>
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Carsten Langgaard wrote:

> This is one of the bugs, among others, we have fixed.
> I'm not sure, if Ralf have integrated the patches we send him yet.
> 


Carsten,

Do you remember the cause and the fix?  It appears to me the first ctc1 
instruction should trap into kernel and mark current process as fpu owner, and 
should not cause fcr31 corruption.

Or somehow the ctc1 does not trap into kernel?

Jun


> /Carsten
> 
> Louis Hamilton wrote:
> 
> 
>>We have a customer here testing a 2.4.16 mips kernel on an embedded
>>Linux RM7000/SR71000 based system who has written a test that they
>>believe has uncovered a bug in Linux.  The FPU control register appears
>>to not get saved and restored.  I've reproduced the problem described
>>below and find the results consistent with their description.  The
>>problem occurs on both the RM7000 and SR71000 cpus.
>>
>>It looks like save_fp_context and restore_fp_context are not being
>>called since the kernel save-restore logic thinks the process is not
>>using floating point math.  If you do some fp math before calling the
>>test routine below, it seems to works fine.
>>
>>Is this a known caveat?  A true bug?  Or a contorted corner case
>>unlikely to be seen under typical end-user usage (see customer's
>>last paragraph :-) ?   If true bug, recommended remedy?
>>
>>TIA,
>>Louis
>>
>>Louis Hamilton
>>hamilton@redhat.com
>>
>>------ customer reports the following: ---------
>>We found a bug in Linux.  A ^C (control-C) typed into a shell (or a
>>running program, it doesn't matter), causes the FCR (floating-point
>>control register) to be corrupted in another, unrelated process.  This
>>is repeatable behavior.
>>
>>This can be reproduced with the following short assembly language
>>program that loops forever, waiting for the FCR to change.
>>
>>        .align 2
>>        .globl mips_float_debug_loop
>>mips_float_debug_loop:
>>        li      $9, 0xF000F02F
>>        ctc1    $9, $31         # set FCR to some non-zero value
>>        nop
>>1:      cfc1    $8, $31         # get FCR
>>        beq     $8, $9, 1b      # spin, waiting for FCR to change
>>        nop
>>        or      $2, $0, $8
>>        jr    $31
>>        nop
>>
>>You can call this function from a short C program and the return value
>>is the (corrupted) FCR, which turns out to alwyas be: 0x00000002.
>>
>>Run the above loop in one window (connected to the board using telnet)
>>and then in another window (connected to the same board) type ^C.
>>
>>I'm surprised this bug hasn't been encountered by other MIPS vendors.
>>
>><end>
>>
> 
> --
> _    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark             http://www.mips.com
> 
> 
> 
> 



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To: Justin Carlson <justin@cs.cmu.edu>
Cc: linux-mips@oss.sgi.com, ralf@oss.sgi.com
Subject: Re: system.h asm fixes
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On Mon, Jun 17, 2002 at 11:20:42AM -0700, Justin Carlson wrote:
> Looks to me like we're missing some proper asm clobber markers:

Not really, I think those actually caused a problem at some point but
that might be my imagination.  They certainly aren't necessary.  The
compiler can not use $1 for anything, because it doesn't know what the
assembler might be doing with it.

-- 
Daniel Jacobowitz                           Carnegie Mellon University
MontaVista Software                         Debian GNU/Linux Developer

From owner-linux-mips@oss.sgi.com Mon Jun 17 13:02:04 2002
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From: James Simmons <jsimmons@transvirtual.com>
To: Pavel Machek <pavel@ucw.cz>
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> Hi!
>
> >    This patch includes the latest in the fbdev BK repository. I have
> > modified several fbdev drivers (maxinefb, tx3912fb, pmag drivers) to the
> > new api. Please test these changes out before I submit them to linus.
> > Thank you. It is against the latest BK tree and 2.5.20.
>
> Does the code even boot on any machine having tx3912fb?

Yes :-) Also a few other types of MIPS devices use this framebuffer.


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Date: Mon, 17 Jun 2002 22:44:52 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: Justin Carlson <justin@cs.cmu.edu>
Cc: linux-mips@oss.sgi.com
Subject: Re: system.h asm fixes
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In-Reply-To: <1024338042.1463.21.camel@localhost.localdomain>; from justin@cs.cmu.edu on Mon, Jun 17, 2002 at 11:20:42AM -0700

You may consider configuring a hostname for your machine :)

On Mon, Jun 17, 2002 at 11:20:42AM -0700, Justin Carlson wrote:

> Looks to me like we're missing some proper asm clobber markers:

No, as per convention $1 is never used by the compiler per convention,
so clobbering not necessary.  I recently removed all "$1" clobbers to
make the code a bit easier to read.

  Ralf

From owner-linux-mips@oss.sgi.com Mon Jun 17 13:44:48 2002
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Date: Mon, 17 Jun 2002 21:58:11 +0200
To: Daniel Jacobowitz <dan@debian.org>
Cc: Justin Carlson <justin@cs.cmu.edu>, linux-mips@oss.sgi.com,
   ralf@oss.sgi.com
Subject: Re: system.h asm fixes
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Daniel Jacobowitz wrote:
> On Mon, Jun 17, 2002 at 11:20:42AM -0700, Justin Carlson wrote:
> > Looks to me like we're missing some proper asm clobber markers:
> 
> Not really, I think those actually caused a problem at some point but
> that might be my imagination.  They certainly aren't necessary.  The
> compiler can not use $1 for anything, because it doesn't know what the
> assembler might be doing with it.

But other assembler routines which run in the meantime may do.


Thiemo

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Just to be nit-picking, the end point should be (addr + size - 1).

Jun

Carsten Langgaard wrote:

> The __access_ok macro in include/asm-mips64/uaccess.h need to be changed
> in order to work correctly, it's a copy from the 32-bit kernel.
> It's not good enough to simply check for the "sign bit" of the address.
> The area between USEG (XUSEG) and KSEG0 will in 64-bit addressing mode
> generate an address error, if
> accessed. The size of the area depend on the number of virtual
> addressing bits, implemented in the CPU.
> 
> I have tried to come up with a patch, please see below. Any thought ?
> I also changed the macro in arch/mips64/kernel/unaligned.c
> 
> /Carsten
> 
> 
> Index: include/asm-mips64//uaccess.h
> ===================================================================
> RCS file:
> /home/repository/sw/linux-2.4.18/include/asm-mips64/uaccess.h,v
> retrieving revision 1.1.1.1
> diff -u -r1.1.1.1 uaccess.h
> --- include/asm-mips64//uaccess.h       4 Mar 2002 11:13:26 -0000
> 1.1.1.1
> +++ include/asm-mips64//uaccess.h       17 Jun 2002 11:35:32 -0000
> @@ -12,6 +12,8 @@
>  #include <linux/errno.h>
>  #include <linux/sched.h>
> 
> +#include <asm/addrspace.h>
> +
>  #define STR(x)  __STR(x)
>  #define __STR(x)  #x
> 
> @@ -40,16 +42,23 @@
>   * than tests.
>   *
>   * Address valid if:
> - *  - "addr" doesn't have any high-bits set
> - *  - AND "size" doesn't have any high-bits set
> - *  - AND "addr+size" doesn't have any high-bits set
> - *  - OR we are in kernel mode.
> + *  - In user mode and "addr" and "addr+size" in USEG (or XUSEG).
> + *  - OR we are in kernel mode and "addr" and "addr+size" isn't in the
> + *    area between USEG (XUSEG) and KSEG0.
>   */
>  #define
> __ua_size(size)                                                       \
>         (__builtin_constant_p(size) && (signed long) (size) > 0 ? 0 :
> (size))
> 
> -#define __access_ok(addr,size,mask)
> \
> -       (((signed long)((mask)&(addr | (addr + size) |
> __ua_size(size)))) >= 0)
> +static inline int
> +__access_ok(unsigned long addr, unsigned long size, long mask)
> +{
> +       if (((mask) && ((addr | (addr+size)) >= KUSIZE)) ||
> +           (((addr | (addr+size)) < K0BASE) &&
> +            ((addr | (addr+size)) >= KUSIZE)))
> +               return 0;
> +       else
> +               return 1;
> +}
> 
>  #define __access_mask ((long)(get_fs().seg))
> 
> 
> Index: arch/mips64/kernel/unaligned.c
> ===================================================================
> RCS file:
> /home/repository/sw/linux-2.4.18/arch/mips64/kernel/unaligned.c,v
> retrieving revision 1.2
> diff -u -r1.2 unaligned.c
> --- arch/mips64/kernel/unaligned.c      23 May 2002 11:11:45 -0000
> 1.2
> +++ arch/mips64/kernel/unaligned.c      17 Jun 2002 11:51:30 -0000
> @@ -89,11 +89,14 @@
>  #define __STR(x)  #x
> 
>  /*
> - * User code may only access USEG; kernel code may access the
> - * entire address space.
> + * User code may only access USEG;
> + * Kernel code may access the entire address space, except the area
> between
> + * USEG (XUSEG) and KSEG0.
>   */
> -#define check_axs(pc,a,s)                              \
> -       if ((long)(~(pc) & ((a) | ((a)+(s)))) < 0)      \
> +#define check_axs(pc,a,s)
> \
> +        if (((pc < KUSIZE) && (((a) | ((a)+(s))) >= KUSIZE))
> ||               \
> +           ((((a) | ((a)+(s))) < K0BASE) &&
> \
> +            (((a) | ((a)+(s))) >= KUSIZE)))
> \
>                 goto sigbus;
> 
> 
> 
> --
> _    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark             http://www.mips.com
> 
> 
> 
> 



From owner-linux-mips@oss.sgi.com Mon Jun 17 15:34:10 2002
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Date: Tue, 18 Jun 2002 00:36:50 +0200
To: Ralf Baechle <ralf@oss.sgi.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: system.h asm fixes
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Ralf Baechle wrote:
[snip]
> > Looks to me like we're missing some proper asm clobber markers:
> 
> No, as per convention $1 is never used by the compiler per convention,
> so clobbering not necessary.  I recently removed all "$1" clobbers to
> make the code a bit easier to read.

How can this work? A grep shows many instances of $1 usage,
I don't think all of this code is interrupt safe.


Thiemo

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Subject: Re: system.h asm fixes
From: Justin Carlson <justin@cs.cmu.edu>
To: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>
Cc: linux-mips@oss.sgi.com
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On Mon, 2002-06-17 at 15:36, Thiemo Seufer wrote:
> Ralf Baechle wrote:
> [snip]
> > > Looks to me like we're missing some proper asm clobber markers:
> > 
> > No, as per convention $1 is never used by the compiler per convention,
> > so clobbering not necessary.  I recently removed all "$1" clobbers to
> > make the code a bit easier to read.
> 
> How can this work? A grep shows many instances of $1 usage,
> I don't think all of this code is interrupt safe.
> 

The "$x" clobber markers exist so that the *compiler* won't expect
values in those registers to be preserved across the asm call.  It has
nothing to do with safety across interrupts.  In other words, it's there
to prevent something like this:

	foo = 2;   // Compiler sticks foo a register, say, $2	
	asm (
		"  lw $2, baz\n"
		"  sw $2, (%0)\n"
		::"r" (sna));   // Assembly code uses $2 as a temp reg
	(*bar) = foo;      // Compiler erroneously does (*bar) = baz;

In terms of interrupt safety, there is no issue with $1; any interrupt
would save the register before mucking with it, and restore it before
returning.  The only registers for which this is not true are k0 and k1.

As others have rightly pointed out, the compiler isn't allowed to muck
with $1 anyways, as it is defined to be a temporary register for the
assembler.  So the clobber notation isn't necessary.

Make sense?

-Justin


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In-Reply-To: <20020617223650.GD20335@rembrandt.csv.ica.uni-stuttgart.de>; from ica2_ts@csv.ica.uni-stuttgart.de on Tue, Jun 18, 2002 at 12:36:50AM +0200
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On Tue, Jun 18, 2002 at 12:36:50AM +0200, Thiemo Seufer wrote:

> Ralf Baechle wrote:
> [snip]
> > > Looks to me like we're missing some proper asm clobber markers:
> > 
> > No, as per convention $1 is never used by the compiler per convention,
> > so clobbering not necessary.  I recently removed all "$1" clobbers to
> > make the code a bit easier to read.
> 
> How can this work? A grep shows many instances of $1 usage,

Uses by assembler code only, not gcc.  Therefoe we don't need to protect
C code against use of $at.

> I don't think all of this code is interrupt safe.

How this should relate to interrupts is beyond me.  Exception handlers do
their own register saving thing.

  Ralf

From owner-linux-mips@oss.sgi.com Tue Jun 18 00:35:59 2002
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Message-ID: <3D0EE371.8C6D85FD@mips.com>
Date: Tue, 18 Jun 2002 09:38:25 +0200
From: Carsten Langgaard <carstenl@mips.com>
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To: Jun Sun <jsun@mvista.com>
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Subject: Re: __access_ok
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That's true, lets do it right, thanks.

/Carsten


Jun Sun wrote:

> Just to be nit-picking, the end point should be (addr + size - 1).
>
> Jun
>
> Carsten Langgaard wrote:
>
> > The __access_ok macro in include/asm-mips64/uaccess.h need to be changed
> > in order to work correctly, it's a copy from the 32-bit kernel.
> > It's not good enough to simply check for the "sign bit" of the address.
> > The area between USEG (XUSEG) and KSEG0 will in 64-bit addressing mode
> > generate an address error, if
> > accessed. The size of the area depend on the number of virtual
> > addressing bits, implemented in the CPU.
> >
> > I have tried to come up with a patch, please see below. Any thought ?
> > I also changed the macro in arch/mips64/kernel/unaligned.c
> >
> > /Carsten
> >
> >
> > Index: include/asm-mips64//uaccess.h
> > ===================================================================
> > RCS file:
> > /home/repository/sw/linux-2.4.18/include/asm-mips64/uaccess.h,v
> > retrieving revision 1.1.1.1
> > diff -u -r1.1.1.1 uaccess.h
> > --- include/asm-mips64//uaccess.h       4 Mar 2002 11:13:26 -0000
> > 1.1.1.1
> > +++ include/asm-mips64//uaccess.h       17 Jun 2002 11:35:32 -0000
> > @@ -12,6 +12,8 @@
> >  #include <linux/errno.h>
> >  #include <linux/sched.h>
> >
> > +#include <asm/addrspace.h>
> > +
> >  #define STR(x)  __STR(x)
> >  #define __STR(x)  #x
> >
> > @@ -40,16 +42,23 @@
> >   * than tests.
> >   *
> >   * Address valid if:
> > - *  - "addr" doesn't have any high-bits set
> > - *  - AND "size" doesn't have any high-bits set
> > - *  - AND "addr+size" doesn't have any high-bits set
> > - *  - OR we are in kernel mode.
> > + *  - In user mode and "addr" and "addr+size" in USEG (or XUSEG).
> > + *  - OR we are in kernel mode and "addr" and "addr+size" isn't in the
> > + *    area between USEG (XUSEG) and KSEG0.
> >   */
> >  #define
> > __ua_size(size)                                                       \
> >         (__builtin_constant_p(size) && (signed long) (size) > 0 ? 0 :
> > (size))
> >
> > -#define __access_ok(addr,size,mask)
> > \
> > -       (((signed long)((mask)&(addr | (addr + size) |
> > __ua_size(size)))) >= 0)
> > +static inline int
> > +__access_ok(unsigned long addr, unsigned long size, long mask)
> > +{
> > +       if (((mask) && ((addr | (addr+size)) >= KUSIZE)) ||
> > +           (((addr | (addr+size)) < K0BASE) &&
> > +            ((addr | (addr+size)) >= KUSIZE)))
> > +               return 0;
> > +       else
> > +               return 1;
> > +}
> >
> >  #define __access_mask ((long)(get_fs().seg))
> >
> >
> > Index: arch/mips64/kernel/unaligned.c
> > ===================================================================
> > RCS file:
> > /home/repository/sw/linux-2.4.18/arch/mips64/kernel/unaligned.c,v
> > retrieving revision 1.2
> > diff -u -r1.2 unaligned.c
> > --- arch/mips64/kernel/unaligned.c      23 May 2002 11:11:45 -0000
> > 1.2
> > +++ arch/mips64/kernel/unaligned.c      17 Jun 2002 11:51:30 -0000
> > @@ -89,11 +89,14 @@
> >  #define __STR(x)  #x
> >
> >  /*
> > - * User code may only access USEG; kernel code may access the
> > - * entire address space.
> > + * User code may only access USEG;
> > + * Kernel code may access the entire address space, except the area
> > between
> > + * USEG (XUSEG) and KSEG0.
> >   */
> > -#define check_axs(pc,a,s)                              \
> > -       if ((long)(~(pc) & ((a) | ((a)+(s)))) < 0)      \
> > +#define check_axs(pc,a,s)
> > \
> > +        if (((pc < KUSIZE) && (((a) | ((a)+(s))) >= KUSIZE))
> > ||               \
> > +           ((((a) | ((a)+(s))) < K0BASE) &&
> > \
> > +            (((a) | ((a)+(s))) >= KUSIZE)))
> > \
> >                 goto sigbus;
> >
> >
> >
> > --
> > _    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
> > |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> > | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> >   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> >                    Denmark            http://www.mips.com
> >
> >
> >
> >

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From owner-linux-mips@oss.sgi.com Tue Jun 18 00:41:27 2002
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Message-ID: <3D0EE4C5.99F67A43@mips.com>
Date: Tue, 18 Jun 2002 09:44:05 +0200
From: Carsten Langgaard <carstenl@mips.com>
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To: Justin Carlson <justin@cs.cmu.edu>
CC: linux-mips@oss.sgi.com
Subject: Re: __access_ok
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Note, that this is in the 64-bit kernel, a size there the high bit is set,
will be astronomical and not a true value.

/Carsten

Justin Carlson wrote:

> On Mon, 2002-06-17 at 04:53, Carsten Langgaard wrote:
>
> >   * Address valid if:
> > - *  - "addr" doesn't have any high-bits set
> > - *  - AND "size" doesn't have any high-bits set
> > - *  - AND "addr+size" doesn't have any high-bits set
> > - *  - OR we are in kernel mode.
> > + *  - In user mode and "addr" and "addr+size" in USEG (or XUSEG).
> > + *  - OR we are in kernel mode and "addr" and "addr+size" isn't in the
> > + *    area between USEG (XUSEG) and KSEG0.
>
> You also need to test for high bit set in size.  Otherwise, for example,
> if a process was ok to access range 0x40000000-0x40003fff,
> access_ok(0x40001000, 0xfffff100) would return 1.  The addition will
> wrap around, leading to all sorts of fun havoc.
>
> -Justin

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From owner-linux-mips@oss.sgi.com Tue Jun 18 01:05:41 2002
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Message-ID: <3D0EEA5A.1B5DAA23@mips.com>
Date: Tue, 18 Jun 2002 10:07:54 +0200
From: Carsten Langgaard <carstenl@mips.com>
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To: Jun Sun <jsun@mvista.com>
CC: Louis Hamilton <hamilton@redhat.com>, linux-mips@oss.sgi.com,
   sandcraft-elinux-project@redhat.com
Subject: Re: Bug in Linux?  fcr31 not being saved-restored
References: <3D0BD42E.20602@redhat.com> <3D0D7F98.566B3176@mips.com> <3D0E38E8.10804@mvista.com>
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I believe this is the patch that solve the problem.
The lazy fpu stuff has cause so many problems, that we have decided (together
with Ralf) to get rid of it, and do the FPU context save and restore a little bit
differently.
We now have a solution here locally and we are testing it at the moment.

/Carsten


Index: arch/mips/kernel/traps.c
===================================================================
RCS file: /cvs/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.99.2.14
diff -u -r1.99.2.14 traps.c
--- arch/mips/kernel/traps.c    2002/05/28 06:33:13     1.99.2.14
+++ arch/mips/kernel/traps.c    2002/06/18 07:53:47
+               {
+                       __enable_fpu();
                        save_fp(last_task_used_math);
+                       /* last_task_used_math loose fpu */
+                       ((struct pt_regs *)(__KSTK_TOS(last_task_used_math) -
+                                           sizeof(struct pt_regs)))->
+                               cp0_status &= ~ST0_CU1;
+               }

Index: include/asm-mips/processor.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/processor.h,v
retrieving revision 1.43.2.2
diff -u -r1.43.2.2 processor.h
--- include/asm-mips/processor.h        2002/05/28 06:11:56     1.43.2.2
+++ include/asm-mips/processor.h        2002/06/18 07:56:58
@@ -215,6 +215,7 @@
        regs->cp0_epc = new_pc;                                         \
        regs->regs[29] = new_sp;                                        \
        current->thread.current_ds = USER_DS;                           \
+       current->used_math = 0;                                         \
 } while (0)

 unsigned long get_wchan(struct task_struct *p);



Jun Sun wrote:

> Carsten Langgaard wrote:
>
> > This is one of the bugs, among others, we have fixed.
> > I'm not sure, if Ralf have integrated the patches we send him yet.
> >
>
> Carsten,
>
> Do you remember the cause and the fix?  It appears to me the first ctc1
> instruction should trap into kernel and mark current process as fpu owner, and
> should not cause fcr31 corruption.
>
> Or somehow the ctc1 does not trap into kernel?
>
> Jun
>
> > /Carsten
> >
> > Louis Hamilton wrote:
> >
> >
> >>We have a customer here testing a 2.4.16 mips kernel on an embedded
> >>Linux RM7000/SR71000 based system who has written a test that they
> >>believe has uncovered a bug in Linux.  The FPU control register appears
> >>to not get saved and restored.  I've reproduced the problem described
> >>below and find the results consistent with their description.  The
> >>problem occurs on both the RM7000 and SR71000 cpus.
> >>
> >>It looks like save_fp_context and restore_fp_context are not being
> >>called since the kernel save-restore logic thinks the process is not
> >>using floating point math.  If you do some fp math before calling the
> >>test routine below, it seems to works fine.
> >>
> >>Is this a known caveat?  A true bug?  Or a contorted corner case
> >>unlikely to be seen under typical end-user usage (see customer's
> >>last paragraph :-) ?   If true bug, recommended remedy?
> >>
> >>TIA,
> >>Louis
> >>
> >>Louis Hamilton
> >>hamilton@redhat.com
> >>
> >>------ customer reports the following: ---------
> >>We found a bug in Linux.  A ^C (control-C) typed into a shell (or a
> >>running program, it doesn't matter), causes the FCR (floating-point
> >>control register) to be corrupted in another, unrelated process.  This
> >>is repeatable behavior.
> >>
> >>This can be reproduced with the following short assembly language
> >>program that loops forever, waiting for the FCR to change.
> >>
> >>        .align 2
> >>        .globl mips_float_debug_loop
> >>mips_float_debug_loop:
> >>        li      $9, 0xF000F02F
> >>        ctc1    $9, $31         # set FCR to some non-zero value
> >>        nop
> >>1:      cfc1    $8, $31         # get FCR
> >>        beq     $8, $9, 1b      # spin, waiting for FCR to change
> >>        nop
> >>        or      $2, $0, $8
> >>        jr    $31
> >>        nop
> >>
> >>You can call this function from a short C program and the return value
> >>is the (corrupted) FCR, which turns out to alwyas be: 0x00000002.
> >>
> >>Run the above loop in one window (connected to the board using telnet)
> >>and then in another window (connected to the same board) type ^C.
> >>
> >>I'm surprised this bug hasn't been encountered by other MIPS vendors.
> >>
> >><end>
> >>
> >
> > --
> > _    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
> > |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> > | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> >   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> >                    Denmark            http://www.mips.com
> >
> >
> >
> >

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From owner-linux-mips@oss.sgi.com Tue Jun 18 04:48:03 2002
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From: "Bradley D. LaRonde" <brad@ltc.com>
To: "Balakrishnan Ananthanarayanan" <balakris_ananth@email.com>,
   <linux-mips@oss.sgi.com>
References: <20020617094851.30730.qmail@email.com>
Subject: Re: Code error - why?
Date: Mon, 17 Jun 2002 12:01:56 -0400
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Drop the $ on the registers?

Regards,
Brad

----- Original Message -----
From: "Balakrishnan Ananthanarayanan" <balakris_ananth@email.com>
To: <linux-mips@oss.sgi.com>; <linux-kernel@vger.kernel.org>;
<redhat-list@redhat.com>
Sent: Monday, June 17, 2002 5:48 AM
Subject: Code error - why?


> I wrote a SAMPLE CODE - Hello.S to work for a cross-assembler
mips-linux-as - but this is giving me an error message:
>    ".data
>          quest: .asciiz "Hello World!"
>     .text
>     _start:
>          la $a0, quest
>          li $v0, 4
>          syscall   "
>
> The error messages are:
>   " Hello.S line 5: illegal operands 'la'
>     Hello.S line 6: illegal operands 'li'"
>
> Can anyone help? What is wrong?

From owner-linux-mips@oss.sgi.com Tue Jun 18 05:31:11 2002
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Message-ID: <3D0F28AE.7B0D822B@mips.com>
Date: Tue, 18 Jun 2002 14:33:50 +0200
From: Carsten Langgaard <carstenl@mips.com>
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To: linux-mips@oss.sgi.com
Subject: 64-bit kernel
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I don't know if anymore has a interest in the 64-bit kernel, but I just
found this bug (see patch below).
It would be nice to know, how many are interested in the 64-bit kernel
and who actually got something running.
So please rise you voice.

/Carsten

Index: include/asm-mips64/exception.h
===================================================================
RCS file:
/home/repository/sw/linux-2.4.18/include/asm-mips64/exception.h,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 exception.h
--- include/asm-mips64/exception.h      4 Mar 2002 11:13:25 -0000
1.1.1.1
+++ include/asm-mips64/exception.h      18 Jun 2002 12:18:40 -0000
@@ -28,7 +28,7 @@

        .macro  __build_clear_fpe
        cfc1    a1, fcr31
-       li      a2, ~(0x3f << 13)
+       li      a2, ~(0x3f << 12)
        and     a2, a1
        ctc1    a2, fcr31
        STI



--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From owner-linux-mips@oss.sgi.com Tue Jun 18 06:50:25 2002
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	Tue, 18 Jun 2002 06:53:04 -0700 (PDT)
Message-ID: <007601c216d0$6f7f0840$10eca8c0@grendel>
From: "Kevin D. Kissell" <kevink@mips.com>
To: <linux-mips@fnet.fr>, <linux-mips@oss.sgi.com>
Subject: Linux and the Sony Playstation 2
Date: Tue, 18 Jun 2002 15:59:57 +0200
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The Sony PS2 Linux kit has been shipping for nearly
a month now, and I'm frankly astonished at how little
I've seen on this mailing list about it.  For better or
for worse, this changes everything for MIPS/Linux.
The number of MIPS/Linux users worldwide has
just gone up by at least an order of magnitude,
and they are on a platform running a 2.2.1-derived
kernel and using gcc 2.95.2.

It's a perfectly usable platform out of the box, but
Carsten has thrown "crashme" at it, and it goes down
relatively quickly.  People trying to port kaffe and
other programs that do double-precision float are
blocked because there's no double precision on the
R5900, and the Sony kernel lacks the Algorithmics
emulator.

It's not clear what Sony is going to put into further
development, and what they are going to expect the
user community to take over from here.  There is a 
group of people trying to take the kernel up to
2.2.20, but I'm not yet sure whether they know
what they are doing, and anyway, that box needs
to get to 2.4.x ASAP.

I respectfully submit that, within a year, any 
MIPS/Linux  source tree that does not support 
the PS2 will be considered obsolete.  And that
quite specifically includes the one at oss.sgi.com.
I personally would want to approach this in terms 
of merging the necessary PS2 code into something
that could be expressed as a patch over kernel.org's
2.4.19_or_better, and which would be provded 
as the default MIPS kernel technology by MIPS 
and SGI servers, and ultimately by kernel.org.

Is no one else here working on this?

            Regards,

            Kevin K.

From owner-linux-mips@oss.sgi.com Tue Jun 18 08:16:38 2002
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Date: Tue, 18 Jun 2002 08:19:18 -0700
From: "H . J . Lu" <hjl@lucon.org>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com
Subject: Re: Linux and the Sony Playstation 2
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In-Reply-To: <007601c216d0$6f7f0840$10eca8c0@grendel>; from kevink@mips.com on Tue, Jun 18, 2002 at 03:59:57PM +0200
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On Tue, Jun 18, 2002 at 03:59:57PM +0200, Kevin D. Kissell wrote:
> The Sony PS2 Linux kit has been shipping for nearly
> a month now, and I'm frankly astonished at how little
> I've seen on this mailing list about it.  For better or
> for worse, this changes everything for MIPS/Linux.
> The number of MIPS/Linux users worldwide has
> just gone up by at least an order of magnitude,
> and they are on a platform running a 2.2.1-derived
> kernel and using gcc 2.95.2.
> 
> It's a perfectly usable platform out of the box, but
> Carsten has thrown "crashme" at it, and it goes down
> relatively quickly.  People trying to port kaffe and
> other programs that do double-precision float are
> blocked because there's no double precision on the
> R5900, and the Sony kernel lacks the Algorithmics
> emulator.
> 

I looked at PS2 when I was looking for a mips platform for my
Linux/mips work. Unfortunately, PS2 doesn't have ll/sc, which
makes many things complicated.


H.J.

From owner-linux-mips@oss.sgi.com Tue Jun 18 09:00:59 2002
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Subject: Re: 64-bit kernel
From: Justin Carlson <justin@cs.cmu.edu>
To: Carsten Langgaard <carstenl@mips.com>
Cc: linux-mips@oss.sgi.com
In-Reply-To: <3D0F28AE.7B0D822B@mips.com>
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On Tue, 2002-06-18 at 05:33, Carsten Langgaard wrote:
> I don't know if anymore has a interest in the 64-bit kernel, but I just
> found this bug (see patch below).
> It would be nice to know, how many are interested in the 64-bit kernel
> and who actually got something running.
> So please rise you voice.
> 

Been running 64-bit stuff here, but nothing even remotely fpu intensive.
It's quite possible we'd never run into this case.

-Justin



From owner-linux-mips@oss.sgi.com Tue Jun 18 10:04:50 2002
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Date: Tue, 18 Jun 2002 10:03:47 -0700
From: William Jhun <wjhun@ayrnetworks.com>
To: "linux-mips@oss.sgi.com"@ayrnetworks.com
Subject: [PATCH] dma_cache_wback, pci DMA cache coherency changes
Message-ID: <20020618100347.A1361@ayrnetworks.com>
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This is a re-hash of patches I sent out a while ago which do a more
optimal cache-flushing for pci_map_*() and pci_dma_sync_*(). It
basically does an invalidate for PCI_DMA_FROMDEVICE operations and a
writeback for PCI_DMA_TODEVICE pci_map_* (or writeback/invalidate if
PCI_DMA_BIDIRECTIONAL). This is similar to the ARM implementation.

Additionally, I filled in the _dma_cache_wback calls in the
arch/mips/c-*.c to call *_dma_cache_wback_inv* instead of calling
panic(). Some architectures could probably do a real writeback instead
of just wback_inv, but this will at least allow code that can use
writeback-only if available.

Note: I'm not familiar with a lot of these CPUs, but the change should
be innocuous. Could someone validate/improve these?

Thanks,
William

Index: include/asm/pci.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/pci.h,v
retrieving revision 1.24.2.1
diff -u -r1.24.2.1 pci.h
--- include/asm/pci.h	2002/02/26 06:00:25	1.24.2.1
+++ include/asm/pci.h	2002/06/18 16:51:30
@@ -79,7 +79,40 @@
 extern void pci_free_consistent(struct pci_dev *hwdev, size_t size,
 				void *vaddr, dma_addr_t dma_handle);
 
+#ifdef CONFIG_NONCOHERENT_IO
+/*
+ * Prepare buffer for DMA transfer
+ */
+static inline void prep_buffer(void *ptr, size_t size, int direction)
+{
+        switch(direction) {
+        case PCI_DMA_TODEVICE:
+                dma_cache_wback((unsigned long)ptr, size);
+                break;
+        case PCI_DMA_FROMDEVICE:
+                dma_cache_inv((unsigned long)ptr, size);
+                break;
+        case PCI_DMA_BIDIRECTIONAL:
+                dma_cache_wback_inv((unsigned long)ptr, size);
+                break;
+        }
+}
+
 /*
+ * Prepare buffer for CPU access after DMA transfer
+ */
+static inline void sync_buffer(void *ptr, size_t size, int direction)
+{
+        switch(direction) {
+        case PCI_DMA_FROMDEVICE:
+        case PCI_DMA_BIDIRECTIONAL:
+                dma_cache_inv((unsigned long)ptr, size);
+                break;
+        }
+}
+#endif
+
+/*
  * Map a single buffer of the indicated size for DMA in streaming mode.
  * The 32-bit bus address to use is returned.
  *
@@ -93,7 +126,7 @@
 		BUG();
 
 #ifdef CONFIG_NONCOHERENT_IO
-	dma_cache_wback_inv((unsigned long)ptr, size);
+	prep_buffer(ptr, size, direction);
 #endif
 
 	return virt_to_bus(ptr);
@@ -132,7 +165,7 @@
 	addr = (unsigned long) page_address(page);
 	addr += offset;
 #ifdef CONFIG_NONCOHERENT_IO
-	dma_cache_wback_inv(addr, size);
+	prep_buffer((void*)addr, size, direction);
 #endif
 
 	return virt_to_bus((void *)addr);
@@ -183,7 +216,7 @@
 #ifdef CONFIG_NONCOHERENT_IO
 	/* Make sure that gcc doesn't leave the empty loop body.  */
 	for (i = 0; i < nents; i++, sg++)
-		dma_cache_wback_inv((unsigned long)sg->address, sg->length);
+		prep_buffer(sg->address, sg->length, direction);
 #endif
 
 	return nents;
@@ -221,7 +254,7 @@
 		BUG();
 
 #ifdef CONFIG_NONCOHERENT_IO
-	dma_cache_wback_inv((unsigned long)bus_to_virt(dma_handle), size);
+	sync_buffer(bus_to_virt(dma_handle), size, direction);
 #endif
 }
 
@@ -246,8 +279,9 @@
 	/* Make sure that gcc doesn't leave the empty loop body.  */
 #ifdef CONFIG_NONCOHERENT_IO
 	for (i = 0; i < nelems; i++, sg++)
-		dma_cache_wback_inv((unsigned long)sg->address, sg->length);
+		sync_buffer(sg->address, sg->length, direction);
 #endif
+
 }
 
 /* Return whether the given PCI device DMA address mask can

Index: arch/mips/mm/c-mips32.c
===================================================================
RCS file: /cvs/linux/arch/mips/mm/c-mips32.c,v
retrieving revision 1.3.2.4
diff -u -r1.3.2.4 c-mips32.c
--- arch/mips/mm/c-mips32.c	2002/05/29 03:03:17	1.3.2.4
+++ arch/mips/mm/c-mips32.c	2002/06/18 16:52:21
@@ -393,12 +393,6 @@
 	}
 }
 
-static void
-mips32_dma_cache_wback(unsigned long addr, unsigned long size)
-{
-	panic("mips32_dma_cache called - should not happen.");
-}
-
 /*
  * While we're protected against bad userland addresses we don't care
  * very much about what happens in that case.  Usually a segmentation
@@ -603,7 +597,7 @@
 	_flush_icache_page = mips32_flush_icache_page;
 
 	_dma_cache_wback_inv = mips32_dma_cache_wback_inv_pc;
-	_dma_cache_wback = mips32_dma_cache_wback;
+	_dma_cache_wback = mips32_dma_cache_wback_inv_pc;
 	_dma_cache_inv = mips32_dma_cache_inv_pc;
 }
 
@@ -621,7 +615,7 @@
 	_flush_icache_page = mips32_flush_icache_page_s;
 
 	_dma_cache_wback_inv = mips32_dma_cache_wback_inv_sc;
-	_dma_cache_wback = mips32_dma_cache_wback;
+	_dma_cache_wback = mips32_dma_cache_wback_inv_sc;
 	_dma_cache_inv = mips32_dma_cache_inv_sc;
 }
 
Index: arch/mips/mm/c-r3k.c
===================================================================
RCS file: /cvs/linux/arch/mips/mm/c-r3k.c,v
retrieving revision 1.4.2.1
diff -u -r1.4.2.1 c-r3k.c
--- arch/mips/mm/c-r3k.c	2002/02/18 15:22:30	1.4.2.1
+++ arch/mips/mm/c-r3k.c	2002/06/18 16:52:21
@@ -337,7 +337,9 @@
 	_flush_icache_page = r3k_flush_icache_page;
 	_flush_icache_range = r3k_flush_icache_range;
 
+	_dma_cache_inv = r3k_dma_cache_wback_inv;
 	_dma_cache_wback_inv = r3k_dma_cache_wback_inv;
+	_dma_cache_wback = r3k_dma_cache_wback_inv;
 
 	printk("Primary instruction cache %dkb, linesize %d bytes\n",
 		(int) (icache_size >> 10), (int) icache_lsize);
Index: arch/mips/mm/c-r4k.c
===================================================================
RCS file: /cvs/linux/arch/mips/mm/c-r4k.c,v
retrieving revision 1.3.2.3
diff -u -r1.3.2.3 c-r4k.c
--- arch/mips/mm/c-r4k.c	2002/05/29 03:03:17	1.3.2.3
+++ arch/mips/mm/c-r4k.c	2002/06/18 16:52:21
@@ -1150,12 +1150,6 @@
 	}
 }
 
-static void
-r4k_dma_cache_wback(unsigned long addr, unsigned long size)
-{
-	panic("r4k_dma_cache called - should not happen.");
-}
-
 /*
  * While we're protected against bad userland addresses we don't care
  * very much about what happens in that case.  Usually a segmentation
@@ -1358,7 +1352,7 @@
 	_flush_icache_page = r4k_flush_icache_page_p;
 
 	_dma_cache_wback_inv = r4k_dma_cache_wback_inv_pc;
-	_dma_cache_wback = r4k_dma_cache_wback;
+	_dma_cache_wback = r4k_dma_cache_wback_inv_pc;
 	_dma_cache_inv = r4k_dma_cache_inv_pc;
 }
 
@@ -1441,7 +1435,7 @@
 	___flush_cache_all = _flush_cache_all;
 	_flush_icache_page = r4k_flush_icache_page_s;
 	_dma_cache_wback_inv = r4k_dma_cache_wback_inv_sc;
-	_dma_cache_wback = r4k_dma_cache_wback;
+	_dma_cache_wback = r4k_dma_cache_wback_inv_sc;
 	_dma_cache_inv = r4k_dma_cache_inv_sc;
 }
 
Index: arch/mips/mm/c-r5432.c
===================================================================
RCS file: /cvs/linux/arch/mips/mm/c-r5432.c,v
retrieving revision 1.4
diff -u -r1.4 c-r5432.c
--- arch/mips/mm/c-r5432.c	2001/11/30 13:28:06	1.4
+++ arch/mips/mm/c-r5432.c	2002/06/18 16:52:21
@@ -414,12 +414,6 @@
 	bc_inv(addr, size);
 }
 
-static void
-r5432_dma_cache_wback(unsigned long addr, unsigned long size)
-{
-	panic("r5432_dma_cache called - should not happen.");
-}
-
 /*
  * While we're protected against bad userland addresses we don't care
  * very much about what happens in that case.  Usually a segmentation
@@ -470,7 +464,7 @@
 	_flush_cache_page = r5432_flush_cache_page_d32i32;
 	_flush_icache_page = r5432_flush_icache_page_i32;
 	_dma_cache_wback_inv = r5432_dma_cache_wback_inv_pc;
-	_dma_cache_wback = r5432_dma_cache_wback;
+	_dma_cache_wback = r5432_dma_cache_wback_inv_pc;
 	_dma_cache_inv = r5432_dma_cache_inv_pc;
 
 	_flush_cache_sigtramp = r5432_flush_cache_sigtramp;
Index: arch/mips/mm/c-rm7k.c
===================================================================
RCS file: /cvs/linux/arch/mips/mm/c-rm7k.c,v
retrieving revision 1.4.2.2
diff -u -r1.4.2.2 c-rm7k.c
--- arch/mips/mm/c-rm7k.c	2002/05/29 03:03:17	1.4.2.2
+++ arch/mips/mm/c-rm7k.c	2002/06/18 16:52:21
@@ -177,12 +177,6 @@
 	}
 }
 
-static void
-rm7k_dma_cache_wback(unsigned long addr, unsigned long size)
-{
-	panic("rm7k_dma_cache_wback called - should not happen.");
-}
-
 /*
  * While we're protected against bad userland addresses we don't care
  * very much about what happens in that case.  Usually a segmentation
@@ -342,7 +336,7 @@
 	_flush_icache_page = rm7k_flush_icache_page;
 
 	_dma_cache_wback_inv = rm7k_dma_cache_wback_inv;
-	_dma_cache_wback = rm7k_dma_cache_wback;
+	_dma_cache_wback = rm7k_dma_cache_wback_inv;
 	_dma_cache_inv = rm7k_dma_cache_inv;
 
 	__flush_cache_all_d32i32();
Index: arch/mips/mm/c-tx39.c
===================================================================
RCS file: /cvs/linux/arch/mips/mm/c-tx39.c,v
retrieving revision 1.4
diff -u -r1.4 c-tx39.c
--- arch/mips/mm/c-tx39.c	2001/11/30 13:28:06	1.4
+++ arch/mips/mm/c-tx39.c	2002/06/18 16:52:21
@@ -225,11 +225,6 @@
 	}
 }
 
-static void tx39_dma_cache_wback(unsigned long addr, unsigned long size)
-{
-	panic("tx39_dma_cache called - should not happen.");
-}
-
 static void tx39_flush_cache_sigtramp(unsigned long addr)
 {
 	unsigned long config;
@@ -317,7 +312,7 @@
 		_flush_icache_range = tx39_flush_icache_range;
 
 		_dma_cache_wback_inv = tx39_dma_cache_wback_inv;
-		_dma_cache_wback = tx39_dma_cache_wback;
+		_dma_cache_wback = tx39_dma_cache_wback_inv;
 		_dma_cache_inv = tx39_dma_cache_inv;
 
 		break;
Index: arch/mips/mm/c-tx49.c
===================================================================
RCS file: /cvs/linux/arch/mips/mm/c-tx49.c,v
retrieving revision 1.3.2.1
diff -u -r1.3.2.1 c-tx49.c
--- arch/mips/mm/c-tx49.c	2002/05/29 03:03:17	1.3.2.1
+++ arch/mips/mm/c-tx49.c	2002/06/18 16:52:21
@@ -343,12 +343,6 @@
 	}
 }
 
-static void
-r4k_dma_cache_wback(unsigned long addr, unsigned long size)
-{
-	panic("r4k_dma_cache called - should not happen.");
-}
-
 /*
  * While we're protected against bad userland addresses we don't care
  * very much about what happens in that case.  Usually a segmentation
@@ -429,7 +423,7 @@
 	_flush_icache_page = r4k_flush_icache_page;
 
 	_dma_cache_wback_inv = r4k_dma_cache_wback_inv;
-	_dma_cache_wback = r4k_dma_cache_wback;
+	_dma_cache_wback = r4k_dma_cache_wback_inv;
 	_dma_cache_inv = r4k_dma_cache_inv;
 
 	_flush_cache_sigtramp = r4k_flush_cache_sigtramp;

From owner-linux-mips@oss.sgi.com Tue Jun 18 10:49:44 2002
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To: Carsten Langgaard <carstenl@mips.com>
CC: Louis Hamilton <hamilton@redhat.com>, linux-mips@oss.sgi.com,
   sandcraft-elinux-project@redhat.com
Subject: Re: Bug in Linux?  fcr31 not being saved-restored
References: <3D0BD42E.20602@redhat.com> <3D0D7F98.566B3176@mips.com> <3D0E38E8.10804@mvista.com> <3D0EEA5A.1B5DAA23@mips.com>
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Your first chunk is not clear as to where it applies.  Maybe you are using a 
different code base.

The second chunck is not necessary.  Although the FPU values in thread struct 
for the new thread are stale, the new program cannot assume the fpu register 
values and cannot use them without initialization anyway.

I don't see such a code in x86's code.  Current call to start_thread() is ok 
with or without this change.  I am afraid future use of start_thread() may 
give undesired effect after we make this change.

As for the new fpu context switch code, I wrote a experiemental patch after 
much discussion with Ralf and Kevin.  It is at

http://linux.junsun.net/patches/oss.sgi.com/experimental/020304-half-fpu-context-switch

I also did some performance study of this patch.  Did not get much feedbacks 
when I asked last time. :-(

Jun

Carsten Langgaard wrote:

> I believe this is the patch that solve the problem.
> The lazy fpu stuff has cause so many problems, that we have decided (together
> with Ralf) to get rid of it, and do the FPU context save and restore a little bit
> differently.
> We now have a solution here locally and we are testing it at the moment.
> 
> /Carsten
> 
> 
> Index: arch/mips/kernel/traps.c
> ===================================================================
> RCS file: /cvs/linux/arch/mips/kernel/traps.c,v
> retrieving revision 1.99.2.14
> diff -u -r1.99.2.14 traps.c
> --- arch/mips/kernel/traps.c    2002/05/28 06:33:13     1.99.2.14
> +++ arch/mips/kernel/traps.c    2002/06/18 07:53:47
> +               {
> +                       __enable_fpu();
>                         save_fp(last_task_used_math);
> +                       /* last_task_used_math loose fpu */
> +                       ((struct pt_regs *)(__KSTK_TOS(last_task_used_math) -
> +                                           sizeof(struct pt_regs)))->
> +                               cp0_status &= ~ST0_CU1;
> +               }
> 
> Index: include/asm-mips/processor.h
> ===================================================================
> RCS file: /cvs/linux/include/asm-mips/processor.h,v
> retrieving revision 1.43.2.2
> diff -u -r1.43.2.2 processor.h
> --- include/asm-mips/processor.h        2002/05/28 06:11:56     1.43.2.2
> +++ include/asm-mips/processor.h        2002/06/18 07:56:58
> @@ -215,6 +215,7 @@
>         regs->cp0_epc = new_pc;                                         \
>         regs->regs[29] = new_sp;                                        \
>         current->thread.current_ds = USER_DS;                           \
> +       current->used_math = 0;                                         \
>  } while (0)
> 
>  unsigned long get_wchan(struct task_struct *p);
> 
> 
> 
> Jun Sun wrote:
> 
> 
>>Carsten Langgaard wrote:
>>
>>
>>>This is one of the bugs, among others, we have fixed.
>>>I'm not sure, if Ralf have integrated the patches we send him yet.
>>>
>>>
>>Carsten,
>>
>>Do you remember the cause and the fix?  It appears to me the first ctc1
>>instruction should trap into kernel and mark current process as fpu owner, and
>>should not cause fcr31 corruption.
>>
>>Or somehow the ctc1 does not trap into kernel?
>>
>>Jun
>>
>>
>>>/Carsten
>>>
>>>Louis Hamilton wrote:
>>>
>>>
>>>
>>>>We have a customer here testing a 2.4.16 mips kernel on an embedded
>>>>Linux RM7000/SR71000 based system who has written a test that they
>>>>believe has uncovered a bug in Linux.  The FPU control register appears
>>>>to not get saved and restored.  I've reproduced the problem described
>>>>below and find the results consistent with their description.  The
>>>>problem occurs on both the RM7000 and SR71000 cpus.
>>>>
>>>>It looks like save_fp_context and restore_fp_context are not being
>>>>called since the kernel save-restore logic thinks the process is not
>>>>using floating point math.  If you do some fp math before calling the
>>>>test routine below, it seems to works fine.
>>>>
>>>>Is this a known caveat?  A true bug?  Or a contorted corner case
>>>>unlikely to be seen under typical end-user usage (see customer's
>>>>last paragraph :-) ?   If true bug, recommended remedy?
>>>>
>>>>TIA,
>>>>Louis
>>>>
>>>>Louis Hamilton
>>>>hamilton@redhat.com
>>>>
>>>>------ customer reports the following: ---------
>>>>We found a bug in Linux.  A ^C (control-C) typed into a shell (or a
>>>>running program, it doesn't matter), causes the FCR (floating-point
>>>>control register) to be corrupted in another, unrelated process.  This
>>>>is repeatable behavior.
>>>>
>>>>This can be reproduced with the following short assembly language
>>>>program that loops forever, waiting for the FCR to change.
>>>>
>>>>       .align 2
>>>>       .globl mips_float_debug_loop
>>>>mips_float_debug_loop:
>>>>       li      $9, 0xF000F02F
>>>>       ctc1    $9, $31         # set FCR to some non-zero value
>>>>       nop
>>>>1:      cfc1    $8, $31         # get FCR
>>>>       beq     $8, $9, 1b      # spin, waiting for FCR to change
>>>>       nop
>>>>       or      $2, $0, $8
>>>>       jr    $31
>>>>       nop
>>>>
>>>>You can call this function from a short C program and the return value
>>>>is the (corrupted) FCR, which turns out to alwyas be: 0x00000002.
>>>>
>>>>Run the above loop in one window (connected to the board using telnet)
>>>>and then in another window (connected to the same board) type ^C.
>>>>
>>>>I'm surprised this bug hasn't been encountered by other MIPS vendors.
>>>>
>>>><end>
>>>>
>>>--
>>>_    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
>>>|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
>>>| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>>>  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>>>                   Denmark            http://www.mips.com
>>>
>>>
>>>
>>>
>>>
> 
> --
> _    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark             http://www.mips.com
> 
> 
> 
> 



From owner-linux-mips@oss.sgi.com Tue Jun 18 10:54:40 2002
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Date: Tue, 18 Jun 2002 10:52:19 -0700
From: Jun Sun <jsun@mvista.com>
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To: Carsten Langgaard <carstenl@mips.com>
CC: linux-mips@oss.sgi.com
Subject: Re: 64-bit kernel
References: <3D0F28AE.7B0D822B@mips.com>
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Carsten Langgaard wrote:

> I don't know if anymore has a interest in the 64-bit kernel, but I just
> found this bug (see patch below).
> It would be nice to know, how many are interested in the 64-bit kernel
> and who actually got something running.
> So please rise you voice.
> 


Actually I think there is an increased interestes to 64bit kernel with the 
recent introduction of RM7K and bcm1250 CPUs.

If 64bit kernel gets mature, I think two years down the road we will see 
mid-range CPUs edging into that domain as well.

(Jun is raising his voice....)

Jun


> /Carsten
> 
> Index: include/asm-mips64/exception.h
> ===================================================================
> RCS file:
> /home/repository/sw/linux-2.4.18/include/asm-mips64/exception.h,v
> retrieving revision 1.1.1.1
> diff -u -r1.1.1.1 exception.h
> --- include/asm-mips64/exception.h      4 Mar 2002 11:13:25 -0000
> 1.1.1.1
> +++ include/asm-mips64/exception.h      18 Jun 2002 12:18:40 -0000
> @@ -28,7 +28,7 @@
> 
>         .macro  __build_clear_fpe
>         cfc1    a1, fcr31
> -       li      a2, ~(0x3f << 13)
> +       li      a2, ~(0x3f << 12)
>         and     a2, a1
>         ctc1    a2, fcr31
>         STI
> 
> 
> 
> --
> _    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark             http://www.mips.com
> 
> 
> 
> 



From owner-linux-mips@oss.sgi.com Tue Jun 18 11:29:10 2002
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From: "David Christensen" <dpchrist@holgerdanske.com>
To: <linux-mips@oss.sgi.com>
Cc: <license-discuss@opensource.org>, <kevink@mips.com>
References: <007601c216d0$6f7f0840$10eca8c0@grendel>
Subject: Re: Linux and the Sony Playstation 2
Date: Tue, 18 Jun 2002 11:31:34 -0700
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Kevin:

Kevin D. Kissell <kevink@mips.com> wrote on linux-mips@oss.sgi.com:
> The Sony PS2 Linux kit has been shipping for nearly...

If the PS2 is an open source platform, I would like to know that.
However, I do not see Sony on the OSI approved license list:

    http://www.opensource.org/licenses/index.php


So, let me get out my soap box...

When people say "Open Source", the first thing that comes to mind is
software.  But, this is only one half of the equation.  The hardware
must also be "open", or the concept doesn't work.  First, because
attempting to write systems software without complete and accurate
hardware documentation is an exercise in reverse engineering.  The
community can better spend its time on documented hardware.  Second, and
more importantly, because any intellectual property (IP) encumbrance
will make the results pointless in the marketplace.


Closed hardware breaks the community development model.  Vendors who
provide a Linux distribution but keep their hardware proprietary cannot
honestly claim "Open Source".  Vendors who fully disclose and freely
license both their hardware and software have embraced "Open Source".
As consumers, we vote with our dollars. As engineers, we further one
cause or the other by our education, employment, and personal project
choices.


David Christensen
dpchrist@holgerdanske.com








From owner-linux-mips@oss.sgi.com Tue Jun 18 15:11:44 2002
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Subject: Re: Code error - why?
From: Justin Carlson <justin@cs.cmu.edu>
To: "Bradley D. LaRonde" <brad@ltc.com>
Cc: Balakrishnan Ananthanarayanan <balakris_ananth@email.com>,
   linux-mips@oss.sgi.com
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After preprocessing, the assembler needs to see $<number> as 
register specifiers, so typically your choices are to do either:

#define a0 $4  // See include/asm-mips/regdef.h for these
#define v0 $2

...

	la a0, quest
	li v0, 4



Or to just use the register numbers, e.g.

	la $4, quest
	li $2, 4


-Justin


> ----- Original Message -----
> From: "Balakrishnan Ananthanarayanan" <balakris_ananth@email.com>
> To: <linux-mips@oss.sgi.com>; <linux-kernel@vger.kernel.org>;
> <redhat-list@redhat.com>
> Sent: Monday, June 17, 2002 5:48 AM
> Subject: Code error - why?
> 
> 
> > I wrote a SAMPLE CODE - Hello.S to work for a cross-assembler
> mips-linux-as - but this is giving me an error message:
> >    ".data
> >          quest: .asciiz "Hello World!"
> >     .text
> >     _start:
> >          la $a0, quest
> >          li $v0, 4
> >          syscall   "
> >
> > The error messages are:
> >   " Hello.S line 5: illegal operands 'la'
> >     Hello.S line 6: illegal operands 'li'"
> >
> > Can anyone help? What is wrong?

From owner-linux-mips@oss.sgi.com Tue Jun 18 23:53:23 2002
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Subject: Re: Bug in Linux?  fcr31 not being saved-restored
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Jun Sun wrote:

> Your first chunk is not clear as to where it applies.  Maybe you are using a
> different code base.

Here is my do_cpu handler:

asmlinkage void do_cpu(struct pt_regs *regs)
{
        unsigned int cpid;
        extern void lazy_fpu_switch(void *);
        extern void save_fp(struct task_struct *);
        extern void init_fpu(void);
        void fpu_emulator_init_fpu(void);
        int sig;

        cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
        if (cpid != 1)
                goto bad_cid;

        if (!(mips_cpu.options & MIPS_CPU_FPU))
                goto fp_emul;

        regs->cp0_status |= ST0_CU1;
        if (last_task_used_math == current)
                return;

        if (current->used_math) {               /* Using the FPU again.  */
                lazy_fpu_switch(last_task_used_math);
        } else {                                /* First time FPU user.  */
                if (last_task_used_math != NULL)
                {
                        __enable_fpu();
                        save_fp(last_task_used_math);
                        /* last_task_used_math loose fpu */
                        ((struct pt_regs *)(__KSTK_TOS(last_task_used_math) -
                                            sizeof(struct pt_regs)))->
                                cp0_status &= ~ST0_CU1;
                }
                init_fpu();
                current->used_math = 1;
        }
        last_task_used_math = current;

        return;

fp_emul:
        if (last_task_used_math != current) {
                if (!current->used_math) {
                        fpu_emulator_init_fpu();
                        current->used_math = 1;
                }
        }
        sig = fpu_emulator_cop1Handler(0, regs, &current->thread.fpu.soft);
        last_task_used_math = current;
        if (sig)
        {
                /*
                 * Return EPC is not calculated in the FPU emulator, if
                 * a signal is being send. So we calculate it here.
                 */
                compute_return_epc(regs);
                force_sig(sig, current);
        }
        return;

bad_cid:
#ifndef CONFIG_CPU_HAS_LLSC
        switch (mips_cpu.cputype) {
        case CPU_TX3927:
        case CPU_TX39XX:
                do_ri(regs);
                return;
        }
#endif
        compute_return_epc(regs);
        force_sig(SIGILL, current);
}


>
> The second chunck is not necessary.  Although the FPU values in thread struct
> for the new thread are stale, the new program cannot assume the fpu register
> values and cannot use them without initialization anyway.

At least with the do_cpu handler above, you need this.
I'm not sure which tests failed without this, but I think it was some of the gcc selftests
and I think the problem was, that a thread inherited the previous thread's fsr (floating
point status register).

>
> I don't see such a code in x86's code.  Current call to start_thread() is ok
> with or without this change.  I am afraid future use of start_thread() may
> give undesired effect after we make this change.

Why ?

>
> As for the new fpu context switch code, I wrote a experiemental patch after
> much discussion with Ralf and Kevin.  It is at
>
> http://linux.junsun.net/patches/oss.sgi.com/experimental/020304-half-fpu-context-switch
>
> I also did some performance study of this patch.  Did not get much feedbacks
> when I asked last time. :-(
>
> Jun
>
> Carsten Langgaard wrote:
>
> > I believe this is the patch that solve the problem.
> > The lazy fpu stuff has cause so many problems, that we have decided (together
> > with Ralf) to get rid of it, and do the FPU context save and restore a little bit
> > differently.
> > We now have a solution here locally and we are testing it at the moment.
> >
> > /Carsten
> >
> >
> > Index: arch/mips/kernel/traps.c
> > ===================================================================
> > RCS file: /cvs/linux/arch/mips/kernel/traps.c,v
> > retrieving revision 1.99.2.14
> > diff -u -r1.99.2.14 traps.c
> > --- arch/mips/kernel/traps.c    2002/05/28 06:33:13     1.99.2.14
> > +++ arch/mips/kernel/traps.c    2002/06/18 07:53:47
> > +               {
> > +                       __enable_fpu();
> >                         save_fp(last_task_used_math);
> > +                       /* last_task_used_math loose fpu */
> > +                       ((struct pt_regs *)(__KSTK_TOS(last_task_used_math) -
> > +                                           sizeof(struct pt_regs)))->
> > +                               cp0_status &= ~ST0_CU1;
> > +               }
> >
> > Index: include/asm-mips/processor.h
> > ===================================================================
> > RCS file: /cvs/linux/include/asm-mips/processor.h,v
> > retrieving revision 1.43.2.2
> > diff -u -r1.43.2.2 processor.h
> > --- include/asm-mips/processor.h        2002/05/28 06:11:56     1.43.2.2
> > +++ include/asm-mips/processor.h        2002/06/18 07:56:58
> > @@ -215,6 +215,7 @@
> >         regs->cp0_epc = new_pc;                                         \
> >         regs->regs[29] = new_sp;                                        \
> >         current->thread.current_ds = USER_DS;                           \
> > +       current->used_math = 0;                                         \
> >  } while (0)
> >
> >  unsigned long get_wchan(struct task_struct *p);
> >
> >
> >
> > Jun Sun wrote:
> >
> >
> >>Carsten Langgaard wrote:
> >>
> >>
> >>>This is one of the bugs, among others, we have fixed.
> >>>I'm not sure, if Ralf have integrated the patches we send him yet.
> >>>
> >>>
> >>Carsten,
> >>
> >>Do you remember the cause and the fix?  It appears to me the first ctc1
> >>instruction should trap into kernel and mark current process as fpu owner, and
> >>should not cause fcr31 corruption.
> >>
> >>Or somehow the ctc1 does not trap into kernel?
> >>
> >>Jun
> >>
> >>
> >>>/Carsten
> >>>
> >>>Louis Hamilton wrote:
> >>>
> >>>
> >>>
> >>>>We have a customer here testing a 2.4.16 mips kernel on an embedded
> >>>>Linux RM7000/SR71000 based system who has written a test that they
> >>>>believe has uncovered a bug in Linux.  The FPU control register appears
> >>>>to not get saved and restored.  I've reproduced the problem described
> >>>>below and find the results consistent with their description.  The
> >>>>problem occurs on both the RM7000 and SR71000 cpus.
> >>>>
> >>>>It looks like save_fp_context and restore_fp_context are not being
> >>>>called since the kernel save-restore logic thinks the process is not
> >>>>using floating point math.  If you do some fp math before calling the
> >>>>test routine below, it seems to works fine.
> >>>>
> >>>>Is this a known caveat?  A true bug?  Or a contorted corner case
> >>>>unlikely to be seen under typical end-user usage (see customer's
> >>>>last paragraph :-) ?   If true bug, recommended remedy?
> >>>>
> >>>>TIA,
> >>>>Louis
> >>>>
> >>>>Louis Hamilton
> >>>>hamilton@redhat.com
> >>>>
> >>>>------ customer reports the following: ---------
> >>>>We found a bug in Linux.  A ^C (control-C) typed into a shell (or a
> >>>>running program, it doesn't matter), causes the FCR (floating-point
> >>>>control register) to be corrupted in another, unrelated process.  This
> >>>>is repeatable behavior.
> >>>>
> >>>>This can be reproduced with the following short assembly language
> >>>>program that loops forever, waiting for the FCR to change.
> >>>>
> >>>>       .align 2
> >>>>       .globl mips_float_debug_loop
> >>>>mips_float_debug_loop:
> >>>>       li      $9, 0xF000F02F
> >>>>       ctc1    $9, $31         # set FCR to some non-zero value
> >>>>       nop
> >>>>1:      cfc1    $8, $31         # get FCR
> >>>>       beq     $8, $9, 1b      # spin, waiting for FCR to change
> >>>>       nop
> >>>>       or      $2, $0, $8
> >>>>       jr    $31
> >>>>       nop
> >>>>
> >>>>You can call this function from a short C program and the return value
> >>>>is the (corrupted) FCR, which turns out to alwyas be: 0x00000002.
> >>>>
> >>>>Run the above loop in one window (connected to the board using telnet)
> >>>>and then in another window (connected to the same board) type ^C.
> >>>>
> >>>>I'm surprised this bug hasn't been encountered by other MIPS vendors.
> >>>>
> >>>><end>
> >>>>
> >>>--
> >>>_    _ ____  ___   Carsten Langgaard Mailto:carstenl@mips.com
> >>>|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> >>>| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> >>>  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> >>>                   Denmark           http://www.mips.com
> >>>
> >>>
> >>>
> >>>
> >>>
> >
> > --
> > _    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
> > |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> > | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
> >   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
> >                    Denmark            http://www.mips.com
> >
> >
> >
> >

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From owner-linux-mips@oss.sgi.com Wed Jun 19 00:15:08 2002
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From: Hartvig Ekner <hartvige@mips.com>
Message-Id: <200206190717.g5J7Hnc27328@copfs01.mips.com>
Subject: Re: Linux and the Sony Playstation
To: linux-mips@oss.sgi.com (user alias)
Date: Wed, 19 Jun 2002 09:17:49 +0200 (MEST)
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Forwarded message:
> From: "Kevin D. Kissell" <kevink@mips.com>
> To: <linux-mips@fnet.fr>, <linux-mips@oss.sgi.com>
> Subject: Linux and the Sony Playstation 2
> Date: Tue, 18 Jun 2002 15:59:57 +0200
> 
> The Sony PS2 Linux kit has been shipping for nearly
> a month now, and I'm frankly astonished at how little
> I've seen on this mailing list about it.  For better or
> for worse, this changes everything for MIPS/Linux.
> The number of MIPS/Linux users worldwide has
> just gone up by at least an order of magnitude,
> and they are on a platform running a 2.2.1-derived
> kernel and using gcc 2.95.2.
> 
> It's a perfectly usable platform out of the box, but
> Carsten has thrown "crashme" at it, and it goes down
> relatively quickly.  People trying to port kaffe and
> other programs that do double-precision float are
> blocked because there's no double precision on the
> R5900, and the Sony kernel lacks the Algorithmics
> emulator.

The few simple double-precision programs (ala hello world) I ran worked,
and the compiler substitutes integer code (softfloat) for any double
precision operation. What are the things known not to work?

> It's not clear what Sony is going to put into further
> development, and what they are going to expect the
> user community to take over from here.  There is a 
> group of people trying to take the kernel up to
> 2.2.20, but I'm not yet sure whether they know
> what they are doing, and anyway, that box needs
> to get to 2.4.x ASAP.

It would be great to get 2.4.x on PS/2, and if one doesn't run into 
glibc/kernel dependencies in the upgrade, it should be a reasonable amount
of work. The biggest benefit I see is that a 2.4.x upgrade with the emulator
would allow binary portability of userland using double prec floats.

But one thing which I really admire on the Sony release is the thoroughness
and completeness of their offering. The kernel has full support for the
additional T5900 SIMD state, all new instructions and state is supported
fully in toolchain: binutils, gdb, you name it. Everything in the kit works
(at least what I have tested).

Getting the kernel upgraded would be nice, but there is probably even
more work getting the toolchain, glibc and userland up to speed. There
are about  600 binary userland RPMs provided, which is also a ton of
work to keep updated.

One needs to be very careful that the individual "upgrade" pieces people
do doesn't break the overall nice picture of "everything works out of
the box". What is really needed is that somebody puts together a
productized PS/2 Linux kit version 2.0, which has the
kernel/glibc/toolchain/userland RPMs upgraded to recent versions. 

If somebody else volunteers for the rest, I'll do the kernel :-)
(One of us here here might do it anyway).

/Hartvig


-- 
 _    _   _____  ____     Hartvig Ekner        Mailto:hartvige@mips.com
 |\  /| | |____)(____                          Direct: +45 4486 5503
 | \/ | | |     _____)    MIPS Denmark         Switch: +45 4486 5555
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From owner-linux-mips@oss.sgi.com Wed Jun 19 02:12:53 2002
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Date: Wed, 19 Jun 2002 11:01:59 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: Carsten Langgaard <carstenl@mips.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: 64-bit kernel
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On Tue, Jun 18, 2002 at 02:33:50PM +0200, Carsten Langgaard wrote:

> I don't know if anymore has a interest in the 64-bit kernel, but I just
> found this bug (see patch below).
> It would be nice to know, how many are interested in the 64-bit kernel
> and who actually got something running.
> So please rise you voice.

More and more systems run into the limits of system memory so once it's
practically unavoidable.  Take the existence of highmem as a proof for
it.

  Ralf

From owner-linux-mips@oss.sgi.com Wed Jun 19 02:16:27 2002
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Subject: Re: Linux and the Sony Playstation 2
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The DVDs you get with the linux kit, contain all necessary hardware
documentation.

/Carsten


David Christensen wrote:

> Kevin:
>
> Kevin D. Kissell <kevink@mips.com> wrote on linux-mips@oss.sgi.com:
> > The Sony PS2 Linux kit has been shipping for nearly...
>
> If the PS2 is an open source platform, I would like to know that.
> However, I do not see Sony on the OSI approved license list:
>
>     http://www.opensource.org/licenses/index.php
>
> So, let me get out my soap box...
>
> When people say "Open Source", the first thing that comes to mind is
> software.  But, this is only one half of the equation.  The hardware
> must also be "open", or the concept doesn't work.  First, because
> attempting to write systems software without complete and accurate
> hardware documentation is an exercise in reverse engineering.  The
> community can better spend its time on documented hardware.  Second, and
> more importantly, because any intellectual property (IP) encumbrance
> will make the results pointless in the marketplace.
>
> Closed hardware breaks the community development model.  Vendors who
> provide a Linux distribution but keep their hardware proprietary cannot
> honestly claim "Open Source".  Vendors who fully disclose and freely
> license both their hardware and software have embraced "Open Source".
> As consumers, we vote with our dollars. As engineers, we further one
> cause or the other by our education, employment, and personal project
> choices.
>
> David Christensen
> dpchrist@holgerdanske.com

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




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On Mon, Jun 17, 2002 at 12:55:08PM -0700, Jun Sun wrote:

> Just to be nit-picking, the end point should be (addr + size - 1).

You better don't use the last bit of userspace and make that (addr + size).
Saves several kB on the entire kernel.

  Ralf

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Date: Wed, 19 Jun 2002 11:28:52 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: Carsten Langgaard <carstenl@mips.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: 64-bit kernel
Message-ID: <20020619112852.A22048@dea.linux-mips.net>
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On Tue, Jun 18, 2002 at 02:33:50PM +0200, Carsten Langgaard wrote:

> X-Mailer: Mozilla 4.77 [en] (X11; U; SunOS 5.8 sun4u)
> 
> I don't know if anymore has a interest in the 64-bit kernel, but I just
> found this bug (see patch below).
> It would be nice to know, how many are interested in the 64-bit kernel
> and who actually got something running.
> So please rise you voice.

The patch is ok but please do not send inline patches with Mozilla - it
does bad things like converting tabs to spaces and wordwrapping to
patches.

  Ralf

From owner-linux-mips@oss.sgi.com Wed Jun 19 02:32:16 2002
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Date: Wed, 19 Jun 2002 11:32:44 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: Justin Carlson <justin@cs.cmu.edu>
Cc: Carsten Langgaard <carstenl@mips.com>, linux-mips@oss.sgi.com
Subject: Re: 64-bit kernel
Message-ID: <20020619113244.B22048@dea.linux-mips.net>
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On Tue, Jun 18, 2002 at 09:03:18AM -0700, Justin Carlson wrote:

> On Tue, 2002-06-18 at 05:33, Carsten Langgaard wrote:
> > I don't know if anymore has a interest in the 64-bit kernel, but I just
> > found this bug (see patch below).
> > It would be nice to know, how many are interested in the 64-bit kernel
> > and who actually got something running.
> > So please rise you voice.
> 
> Been running 64-bit stuff here, but nothing even remotely fpu intensive.
> It's quite possible we'd never run into this case.

At this time probably most 64-bit kernels are running on a certain 64-bit
CPU with it's hardware fp disabled so nobody ever saw this one.

  Ralf

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Message-ID: <002901c21775$45209190$10eca8c0@grendel>
From: "Kevin D. Kissell" <kevink@mips.com>
To: "Hartvig Ekner" <hartvige@mips.com>, "user alias" <linux-mips@oss.sgi.com>
References: <200206190717.g5J7Hnc27328@copfs01.mips.com>
Subject: Re: Linux and the Sony Playstation
Date: Wed, 19 Jun 2002 11:39:41 +0200
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From: "Hartvig Ekner" <hartvige@mips.com>
To: "user alias" <linux-mips@oss.sgi.com>
> > From: "Kevin D. Kissell" <kevink@mips.com>
> > To: <linux-mips@fnet.fr>, <linux-mips@oss.sgi.com>
> > Subject: Linux and the Sony Playstation 2
> > Date: Tue, 18 Jun 2002 15:59:57 +0200
> > 
> > The Sony PS2 Linux kit has been shipping for nearly
> > a month now, and I'm frankly astonished at how little
> > I've seen on this mailing list about it.  For better or
> > for worse, this changes everything for MIPS/Linux.
> > The number of MIPS/Linux users worldwide has
> > just gone up by at least an order of magnitude,
> > and they are on a platform running a 2.2.1-derived
> > kernel and using gcc 2.95.2.
> > 
> > It's a perfectly usable platform out of the box, but
> > Carsten has thrown "crashme" at it, and it goes down
> > relatively quickly.  People trying to port kaffe and
> > other programs that do double-precision float are
> > blocked because there's no double precision on the
> > R5900, and the Sony kernel lacks the Algorithmics
> > emulator.
> 
> The few simple double-precision programs (ala hello world) I ran worked,
> and the compiler substitutes integer code (softfloat) for any double
> precision operation. What are the things known not to work?

You didn't disassemble the code.  The Sony gcc distribution
is hard-wired to generate soft-float code, even if you 
specify -mhard-float on the command line.

Since most embedded/multimedia FP is single precision,
one could imagine why Sony and Toshiba could have
decided to leave out floating doubles.  The real problem
is the accursed C stipulation that all FP arguments be
promoted to doubles.  Having every damned passed
argument converted by the kernel would be a bit of
a hit, but I would expect that, in any (single precision)
floating point computation intensive application, that
would be more than made up for by the time gained
in executing the loops native.  And, as always, we
have the correctness issue.  We need to get the PS2
to 2.4.x (and 2.5) fairly quickly, and we want to 
be able to have interoperability of MIPS32 binaries 
across PS2 and non-PS2 platforms, including those 
who habitually use their FPUs.  I've started hacking 
the current (2.4.18+) MIPS/Algorithmics emulator 
code into the Sony 2.2.1 kernel as a stopgap, but
it's a little tricky to test, given that the Sony tools
go out of their way to stop me generating any 
real FP instructions. 

            Regards,

            Kevin K.


From owner-linux-mips@oss.sgi.com Wed Jun 19 02:40:23 2002
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Date: Wed, 19 Jun 2002 11:39:33 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: William Jhun <wjhun@ayrnetworks.com>
Cc: "linux-mips@oss.sgi.com"@ayrnetworks.com
Subject: Re: [PATCH] dma_cache_wback, pci DMA cache coherency changes
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On Tue, Jun 18, 2002 at 10:03:47AM -0700, William Jhun wrote:

> To: "linux-mips@oss.sgi.com"@ayrnetworks.com
      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Your mail software is smoking funny stuff ;-)

> This is a re-hash of patches I sent out a while ago which do a more
> optimal cache-flushing for pci_map_*() and pci_dma_sync_*(). It
> basically does an invalidate for PCI_DMA_FROMDEVICE operations and a
> writeback for PCI_DMA_TODEVICE pci_map_* (or writeback/invalidate if
> PCI_DMA_BIDIRECTIONAL). This is similar to the ARM implementation.
> 
> Additionally, I filled in the _dma_cache_wback calls in the
> arch/mips/c-*.c to call *_dma_cache_wback_inv* instead of calling
> panic(). Some architectures could probably do a real writeback instead
> of just wback_inv, but this will at least allow code that can use
> writeback-only if available.
> 
> Note: I'm not familiar with a lot of these CPUs, but the change should
> be innocuous. Could someone validate/improve these?

Can you try to get rid of all these #ifdef CONFIG_NONCOHERENT_IO things?
We already had too many of them and you're adding even more ...
Basically if dma_cache_wback_inv, dma_cache_wback and dma_cache_inv are
just empty macros as they are if CONFIG_NONCOHERENT_IO is undefined
gcc should be able to optimize most of the #ifdef'd code away.

Please always cc patches you want to submit to me or I might miss them on
the list.

  Ralf

From owner-linux-mips@oss.sgi.com Wed Jun 19 02:49:17 2002
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From: Hartvig Ekner <hartvige@mips.com>
Message-Id: <200206190951.g5J9pt620966@copfs01.mips.com>
Subject: Re: Linux and the Sony Playstation
To: kevink@mips.com (Kevin D. Kissell)
Date: Wed, 19 Jun 2002 11:51:55 +0200 (MEST)
Cc: hartvige@mips.com (Hartvig Ekner), linux-mips@oss.sgi.com (user alias)
In-Reply-To: <002901c21775$45209190$10eca8c0@grendel> from "Kevin D. Kissell" at Jun 19, 2002 11:39:41 AM
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Kevin D. Kissell writes:
> 
> From: "Hartvig Ekner" <hartvige@mips.com>
> To: "user alias" <linux-mips@oss.sgi.com>
> > > From: "Kevin D. Kissell" <kevink@mips.com>
> > > To: <linux-mips@fnet.fr>, <linux-mips@oss.sgi.com>
> > > Subject: Linux and the Sony Playstation 2
> > > Date: Tue, 18 Jun 2002 15:59:57 +0200
> > > 
> > > The Sony PS2 Linux kit has been shipping for nearly
> > > a month now, and I'm frankly astonished at how little
> > > I've seen on this mailing list about it.  For better or
> > > for worse, this changes everything for MIPS/Linux.
> > > The number of MIPS/Linux users worldwide has
> > > just gone up by at least an order of magnitude,
> > > and they are on a platform running a 2.2.1-derived
> > > kernel and using gcc 2.95.2.
> > > 
> > > It's a perfectly usable platform out of the box, but
> > > Carsten has thrown "crashme" at it, and it goes down
> > > relatively quickly.  People trying to port kaffe and
> > > other programs that do double-precision float are
> > > blocked because there's no double precision on the
> > > R5900, and the Sony kernel lacks the Algorithmics
> > > emulator.
> > 
> > The few simple double-precision programs (ala hello world) I ran worked,
> > and the compiler substitutes integer code (softfloat) for any double
> > precision operation. What are the things known not to work?
> 
> You didn't disassemble the code.  The Sony gcc distribution
> is hard-wired to generate soft-float code, even if you 
> specify -mhard-float on the command line.


I did disassemble the code. It generates true FPU code for floats, and
soft-float for double. See the example below:

[hartvige@copps01 test]$ more hellof.c
int main()
{
float a,b;
a = 3.0f;
b = a + 2.0f;
printf("hello world %f\n",b);
}

gcc hellof.c, and disassembling:

0000000000400a70 <main>:
  400a70:       3c1c0fc0        lui     $gp,0xfc0
  400a74:       279c75c0        addiu   $gp,$gp,30144
  400a78:       0399e021        addu    $gp,$gp,$t9
  400a7c:       27bdffc0        addiu   $sp,$sp,-64
  400a80:       afbc0010        sw      $gp,16($sp)
  400a84:       afbf0038        sw      $ra,56($sp)
  400a88:       afbe0034        sw      $s8,52($sp)
  400a8c:       afbc0030        sw      $gp,48($sp)
  400a90:       03a0f021        move    $s8,$sp
  400a94:       3c014040        lui     $at,0x4040
  400a98:       44810000        mtc1    $at,$f0
  400a9c:       00000000        nop
  400aa0:       e7c00020        swc1    $f0,32($s8)
  400aa4:       c7c00020        lwc1    $f0,32($s8)
  400aa8:       3c014000        lui     $at,0x4000
  400aac:       44810800        mtc1    $at,$f1
  400ab0:       00000000        nop
  400ab4:       46010000        add.s   $f0,$f0,$f1
  400ab8:       e7c00024        swc1    $f0,36($s8)
  400abc:       c7cc0024        lwc1    $f12,36($s8)
  400ac0:       8f998054        lw      $t9,-32684($gp)
  400ac4:       0320f809        jalr    $t9
  400ac8:       00000000        nop
  400acc:       8fdc0010        lw      $gp,16($s8)
  400ad0:       8f848018        lw      $a0,-32744($gp)
  400ad4:       24841040        addiu   $a0,$a0,4160
  400ad8:       00403021        move    $a2,$v0
  400adc:       00603821        move    $a3,$v1
  400ae0:       8f998064        lw      $t9,-32668($gp)
  400ae4:       0320f809        jalr    $t9
  400ae8:       00000000        nop
  400aec:       8fdc0010        lw      $gp,16($s8)
  400af0:       03c0e821        move    $sp,$s8


Were you talking about double-precision only, or is there something different
in the kits?

/Hartvig

From owner-linux-mips@oss.sgi.com Wed Jun 19 03:12:59 2002
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From: "Kevin D. Kissell" <kevink@mips.com>
To: "Hartvig Ekner" <hartvige@mips.com>
Cc: "user alias" <linux-mips@oss.sgi.com>
References: <200206190951.g5J9pt620966@copfs01.mips.com>
Subject: Re: Linux and the Sony Playstation
Date: Wed, 19 Jun 2002 12:15:37 +0200
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> > You didn't disassemble the code.  The Sony gcc distribution
> > is hard-wired to generate soft-float code, even if you 
> > specify -mhard-float on the command line.
> 
> I did disassemble the code. It generates true FPU code for floats, and
> soft-float for double. See the example below:

I tested both double and single variants last night, 
and I *thought* that I had seen soft-float code
generated for both cases.  By the light of day,
I can see that that the single case disassembly
does indeed use the FPU - I must have gotten
the disassembly files confused last night.  In any
case, as I said, even if you specify "hard-float",
you'll get soft doubles from the Sony gcc.

While various users have complained about
both the speed and the accuracy of the Sony
soft float implementation, it does pass paranoia
with flying colors.

            Kevin K.

From owner-linux-mips@oss.sgi.com Wed Jun 19 04:05:06 2002
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Date: Wed, 19 Jun 2002 13:07:46 +0200
From: Carsten Langgaard <carstenl@mips.com>
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CC: Justin Carlson <justin@cs.cmu.edu>, linux-mips@oss.sgi.com
Subject: Re: 64-bit kernel
References: <3D0F28AE.7B0D822B@mips.com> <1024416198.1166.1.camel@xyzzy.rlson.org> <20020619113244.B22048@dea.linux-mips.net>
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I'm trying to compile glibc natively using my 64-bit kernel, but it fails with
the following message:

Out of Memory: Killed process 641 (qmgr).
Out of Memory: Killed process 642 (tlsmgr).
Out of Memory: Killed process 378 (portmap).
Out of Memory: Killed process 9363 (cc1).
Out of Memory: Killed process 9363 (cc1).

So there may be a memory leak problem in 64-bit kernel.
Has anyone seen this ?

/Carsten


Ralf Baechle wrote:

> On Tue, Jun 18, 2002 at 09:03:18AM -0700, Justin Carlson wrote:
>
> > On Tue, 2002-06-18 at 05:33, Carsten Langgaard wrote:
> > > I don't know if anymore has a interest in the 64-bit kernel, but I just
> > > found this bug (see patch below).
> > > It would be nice to know, how many are interested in the 64-bit kernel
> > > and who actually got something running.
> > > So please rise you voice.
> >
> > Been running 64-bit stuff here, but nothing even remotely fpu intensive.
> > It's quite possible we'd never run into this case.
>
> At this time probably most 64-bit kernels are running on a certain 64-bit
> CPU with it's hardware fp disabled so nobody ever saw this one.
>
>   Ralf

--
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|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
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	Wed, 19 Jun 2002 13:13:47 +0200
Date: Wed, 19 Jun 2002 13:13:47 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: Carsten Langgaard <carstenl@mips.com>
Cc: Justin Carlson <justin@cs.cmu.edu>, linux-mips@oss.sgi.com
Subject: Re: 64-bit kernel
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On Wed, Jun 19, 2002 at 01:07:46PM +0200, Carsten Langgaard wrote:

> I'm trying to compile glibc natively using my 64-bit kernel, but it fails with
> the following message:
> 
> Out of Memory: Killed process 641 (qmgr).
> Out of Memory: Killed process 642 (tlsmgr).
> Out of Memory: Killed process 378 (portmap).
> Out of Memory: Killed process 9363 (cc1).
> Out of Memory: Killed process 9363 (cc1).
> 
> So there may be a memory leak problem in 64-bit kernel.
> Has anyone seen this ?

No.  The entire Redhat 7.0 stuff I built was done exclusivly on a 64-bit
kernel (with 2GB RAM however ...) and no such problem ever, even after
long uptimes.

  Ralf

From owner-linux-mips@oss.sgi.com Wed Jun 19 05:01:24 2002
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From: "Balakrishnan Ananthanarayanan" <balakris_ananth@email.com>
To: linux-mips@oss.sgi.com, linux-kernel@vger.kernel.org,
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Date: Wed, 19 Jun 2002 07:04:14 -0500
Subject: MIPS - Serial port
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Hi all,

   Is there anyone who has accessed the serial port of an RM7000 MIPS processor? If u can provide me the code please - or atleast the Serial PORT number of an RM7000 proc. mounted on an EV64120A Galileo Board? 

Balakrishnan

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From owner-linux-mips@oss.sgi.com Wed Jun 19 08:13:17 2002
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Date: Wed, 19 Jun 2002 17:16:37 +0200 (MET DST)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Justin Carlson <justin@cs.cmu.edu>
cc: linux-mips@oss.sgi.com
Subject: Re: reenabling interrupts on return from function
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On 15 Jun 2002, Justin Carlson wrote:

> However, I still don't see the point of the above code.  Why do we
> explicitly clear bits 4-0 of the status register just before reloading
> it from the system stack?  

 Not to receive an interrupt in the middle of register restoration.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Wed Jun 19 09:15:12 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Justin Carlson <justin@cs.cmu.edu>
cc: "Bradley D. LaRonde" <brad@ltc.com>,
   Balakrishnan Ananthanarayanan <balakris_ananth@email.com>,
   linux-mips@oss.sgi.com
Subject: Re: Code error - why?
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On 18 Jun 2002, Justin Carlson wrote:

> After preprocessing, the assembler needs to see $<number> as 
> register specifiers, so typically your choices are to do either:
> 
> #define a0 $4  // See include/asm-mips/regdef.h for these
> #define v0 $2
> 
> ...
> 
> 	la a0, quest
> 	li v0, 4

 Well, the usual choice is to put "#include <asm/regdef.h>" instead of
copying definitions.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Wed Jun 19 09:43:56 2002
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Date: Wed, 19 Jun 2002 18:47:05 +0200 (MET DST)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Ladislav Michl <ladis@psi.cz>
cc: linux-mips@oss.sgi.com
Subject: Re: DBE/IBE handling incompatibility
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On Mon, 17 Jun 2002, Ladislav Michl wrote:

> i'd like to release GIO64 bus support. Before doing so DBE/IBE handling
> should be done in the same fashion for both mips and mips64 (*). Currently
> mips is using handler in handler via dbe_board_handler and ibe_board_handler 
> which are not used anywhere while mips64 is using BUILD_HANDLER macro defined
> in include/asm-mips64/exception.h (see arch/mips64/sgi-ip27/ip27-dbe-glue.S)
> Unfortunately I have nearly zero knowledge of MIPS assembler, so I'm
> unable to code mips way same as mips64 is... Help from someone more
> experienced will be greatly appreciated :-)

 I'm going to work on unifying and extending the code a bit once I have my
64-bit world running, so don't worry about the divergence between the
ports. 

 Don't rely in dbe_board_handler and ibe_board_handler -- they are
system-specific backends that shouldn't be touched unless you want to
handle the exceptions in a system-specific way (e.g. to report ECC errors
from a memory controller).  Also expect the handlers to get rewritten so
that search_dbe_table() gets invoked unconditionally, before a
system-specific backend.

> (*) How GIO device detection works? each IP22 machine contains three GIO bus
> slots. GIO device provides information about itself in first (three) word(s)
> of address space it occupies. The only way how to detect GIO card is
> trying to read word from it's base address. If DBE exception is generated 
> then there is definitely no card present, otherwise read value encodes 
> information about device.

 Use get_dbe() from <asm/paccess.h> for reading data with an additional
DBE status.  For a simple example see drivers/mtd/devices/ms02-nv.c.  The
macro is used in a somewhat more complex way in drivers/tc/tc.c as well --
this bit of code fits your situation quite closely (here probing
TURBOchannel bus slots).  The macro works in modules as well. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Wed Jun 19 10:13:33 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Ralf Baechle <ralf@oss.sgi.com>
cc: Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de>, linux-mips@oss.sgi.com
Subject: Re: system.h asm fixes
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On Tue, 18 Jun 2002, Ralf Baechle wrote:

> > How can this work? A grep shows many instances of $1 usage,
> 
> Uses by assembler code only, not gcc.  Therefoe we don't need to protect
> C code against use of $at.

 Moreover, gcc assumes ".set at" is always in effect and includes macros
in its output that are known to clobber $1 and don't work with ".set
noat". 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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Date: Wed, 19 Jun 2002 11:22:07 -0700
From: William Jhun <wjhun@ayrnetworks.com>
To: Ralf Baechle <ralf@oss.sgi.com>
Cc: linux-mips@oss.sgi.com
Subject: [PATCH] include/asm-mips/pci.h
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On Wed, Jun 19, 2002 at 11:39:33AM +0200, Ralf Baechle wrote:
> On Tue, Jun 18, 2002 at 10:03:47AM -0700, William Jhun wrote:
> 
> > To: "linux-mips@oss.sgi.com"@ayrnetworks.com
>       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> 
> Your mail software is smoking funny stuff ;-)

Well! I'll just have to give it a strict spanking and send it off to
rehab. No wonder the office window is always wide open when I arrive in
the morning!

> Can you try to get rid of all these #ifdef CONFIG_NONCOHERENT_IO things?
> We already had too many of them and you're adding even more ...
> Basically if dma_cache_wback_inv, dma_cache_wback and dma_cache_inv are
> just empty macros as they are if CONFIG_NONCOHERENT_IO is undefined
> gcc should be able to optimize most of the #ifdef'd code away.

Ok, so I got rid of most except the ones in the *_sg() functions; gcc
won't optimize the loop out, even with -O2. It just creates a tight loop
that increments sg..

Note that without the #ifdefs, you may get warnings like:

../../../ayr/linux/include/asm/pci.h: In function `prep_buffer':
../../../ayr/linux/include/asm/pci.h:89: warning: statement with no effect
../../../ayr/linux/include/asm/pci.h:89: warning: statement with no effect
../../../ayr/linux/include/asm/pci.h:92: warning: statement with no effect
../../../ayr/linux/include/asm/pci.h:92: warning: statement with no effect
../../../ayr/linux/include/asm/pci.h:95: warning: statement with no effect
../../../ayr/linux/include/asm/pci.h:95: warning: statement with no effect
../../../ayr/linux/include/asm/pci.h: In function `sync_buffer':
../../../ayr/linux/include/asm/pci.h:108: warning: statement with no effect
../../../ayr/linux/include/asm/pci.h:108: warning: statement with no effect

So are we still sure we want to leave them out?

Will

---
Index: include/asm-mips/pci.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/pci.h,v
retrieving revision 1.24.2.1
diff -u -r1.24.2.1 pci.h
--- include/asm-mips/pci.h	2002/02/26 06:00:25	1.24.2.1
+++ include/asm-mips/pci.h	2002/06/19 18:20:51
@@ -80,6 +80,37 @@
 				void *vaddr, dma_addr_t dma_handle);
 
 /*
+ * Prepare buffer for DMA transfer
+ */
+static inline void prep_buffer(void *ptr, size_t size, int direction)
+{
+        switch(direction) {
+        case PCI_DMA_TODEVICE:
+                dma_cache_wback((unsigned long)ptr, size);
+                break;
+        case PCI_DMA_FROMDEVICE:
+                dma_cache_inv((unsigned long)ptr, size);
+                break;
+        case PCI_DMA_BIDIRECTIONAL:
+                dma_cache_wback_inv((unsigned long)ptr, size);
+                break;
+        }
+}
+
+/*
+ * Prepare buffer for CPU access after DMA transfer
+ */
+static inline void sync_buffer(void *ptr, size_t size, int direction)
+{
+        switch(direction) {
+        case PCI_DMA_FROMDEVICE:
+        case PCI_DMA_BIDIRECTIONAL:
+                dma_cache_inv((unsigned long)ptr, size);
+                break;
+        }
+}
+
+/*
  * Map a single buffer of the indicated size for DMA in streaming mode.
  * The 32-bit bus address to use is returned.
  *
@@ -92,9 +123,7 @@
 	if (direction == PCI_DMA_NONE)
 		BUG();
 
-#ifdef CONFIG_NONCOHERENT_IO
-	dma_cache_wback_inv((unsigned long)ptr, size);
-#endif
+	prep_buffer(ptr, size, direction);
 
 	return virt_to_bus(ptr);
 }
@@ -131,9 +160,7 @@
 
 	addr = (unsigned long) page_address(page);
 	addr += offset;
-#ifdef CONFIG_NONCOHERENT_IO
-	dma_cache_wback_inv(addr, size);
-#endif
+	prep_buffer((void*)addr, size, direction);
 
 	return virt_to_bus((void *)addr);
 }
@@ -183,7 +210,7 @@
 #ifdef CONFIG_NONCOHERENT_IO
 	/* Make sure that gcc doesn't leave the empty loop body.  */
 	for (i = 0; i < nents; i++, sg++)
-		dma_cache_wback_inv((unsigned long)sg->address, sg->length);
+		prep_buffer(sg->address, sg->length, direction);
 #endif
 
 	return nents;
@@ -220,9 +247,7 @@
 	if (direction == PCI_DMA_NONE)
 		BUG();
 
-#ifdef CONFIG_NONCOHERENT_IO
-	dma_cache_wback_inv((unsigned long)bus_to_virt(dma_handle), size);
-#endif
+	sync_buffer(bus_to_virt(dma_handle), size, direction);
 }
 
 /*
@@ -246,7 +271,7 @@
 	/* Make sure that gcc doesn't leave the empty loop body.  */
 #ifdef CONFIG_NONCOHERENT_IO
 	for (i = 0; i < nelems; i++, sg++)
-		dma_cache_wback_inv((unsigned long)sg->address, sg->length);
+		sync_buffer(sg->address, sg->length, direction);
 #endif
 }
 

From owner-linux-mips@oss.sgi.com Wed Jun 19 12:03:56 2002
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References: <A9CCF75C3F008040A1B6AFC351DC9AD943EA55@pony-express.bts.co.uk>
Subject: Re: Linux and the Sony Playstation 2
Date: Wed, 19 Jun 2002 12:06:13 -0700
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linux-mips@oss.sgi.com:

"Dave J Woolley" <david.woolley@bts.co.uk> wrote to "David Christensen"
<dpchrist@holgerdanske.com>:
> You are off topic on license discuss - it has a rather narrow charter
> of discussing proposed Open Source licence documents.

OK


> There are two levels of open-ness in hardware.  I'm not sure that
> there is any electronic computing hardware that is completely open to
> the level that open source software is++, but there is basically
> hardware for which the design documentation is published and there is
> hardware for which a programming model is published.  Open source
> drivers require the latter,

Open source development may require both.  for example, let's say I want
to buy a PS2, open it up, add some goodies, and then sell, release under
GPL, gift to the public domain, etc., my derivative work.


> or reverse engineering - which may be illegal (even in Europe as I
> think publishing the driver source code exceeds the limited
> permissions given to reverse engineer without the vendors permission -
> black box reverse engineering is OK, I believe, but not anything that
> looks at mechanism rather than behaviour##).
>
> I'm not sure if you meant open programming models (which in software
> terms mean open interface specifications) or open design information.
>
> ++ I doubt that the photo-lithography masks for even simple
> transistors re published.

I want open programming models and open design information down to the
schematic, board layout, and parts list level.  The insides of
integrated circuits can remain secret so long as their operation and
interfaces are completely documented and there are no IP entanglements
when I want to design, publish, build, sell, give away, etc., circuits,
software, and products which use them.


> ## My understanding is that the EEC law requires refusal of the
> supplier to provide the information on reasonable (not necessarily
> cost free) terms; the information not to be used to create a competing
> product; the information only being sufficient to interface; the
> information not to be published to third parties.  IANAL.

Interesting.


David Christensen
dpchrist@holgerdanske.com



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Cc: <carstenl@mips.com>
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Subject: Re: Linux and the Sony Playstation 2
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Everyone:

"Carsten Langgaard" <carstenl@mips.com> wrote on linux-mips@oss.sgi.com:
> The DVDs you get with the linux kit, contain all necessary hardware
> documentation.

OK  I assume the license is also on the DVD's.

1.  Are the documents and license available online?  If so, what is/are
    the URL(s)?

2.  Has Sony submitted their license to OSI for approval?


David Christensen
dpchrist@holgerdanske.com








From owner-linux-mips@oss.sgi.com Wed Jun 19 12:05:02 2002
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From: "Matthew Dharm" <mdharm@momenco.com>
To: "Balakrishnan Ananthanarayanan" <balakris_ananth@email.com>,
   <linux-mips@oss.sgi.com>, <linux-kernel@vger.kernel.org>,
   <redhat-list@redhat.com>
Subject: RE: MIPS - Serial port
Date: Wed, 19 Jun 2002 12:07:51 -0700
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The RM7000 does not have an on-chip serial port.  The EV board has
it's own UART.

Matt

--
Matthew D. Dharm                            Senior Software Designer
Momentum Computer Inc.                      1815 Aston Ave.  Suite 107
(760) 431-8663 X-115                        Carlsbad, CA 92008-7310
Momentum Works For You                      www.momenco.com

> -----Original Message-----
> From: owner-linux-mips@oss.sgi.com
> [mailto:owner-linux-mips@oss.sgi.com]On Behalf Of Balakrishnan
> Ananthanarayanan
> Sent: Wednesday, June 19, 2002 5:04 AM
> To: linux-mips@oss.sgi.com; linux-kernel@vger.kernel.org;
> redhat-list@redhat.com
> Subject: MIPS - Serial port
>
>
> Hi all,
>
>    Is there anyone who has accessed the serial port of an
> RM7000 MIPS processor? If u can provide me the code please
> - or atleast the Serial PORT number of an RM7000 proc.
> mounted on an EV64120A Galileo Board?
>
> Balakrishnan
>
> --
> __________________________________________________________
> Sign-up for your own FREE Personalized E-mail at Mail.com
> http://www.mail.com/?sr=signup
>
> Save up to $160 by signing up for NetZero Platinum Internet service.
> http://www.netzero.net/?refcd=N2P0602NEP8
>


From owner-linux-mips@oss.sgi.com Wed Jun 19 13:09:43 2002
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From: "Smith, Todd" <Todd.Smith@camc.org>
To: "'linux-mips@oss.sgi.com'" <linux-mips@oss.sgi.com>
Subject: RE: Linux and the Sony Playstation 2
Date: Wed, 19 Jun 2002 16:10:52 -0400
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Hello Kevin,

This list is been pretty quiet lately so I don't really know what is
happening on the Linux/MIPS front.  I am hoping that work is still slowly
proceeding on the DECstation that I have, but I don't really know.  I agree
with you that PS2 offer enormous power to the developer and as a cheap
source of computing power to other countries.

I don't know a great deal about it, but I am least willing to discuss it if
it will create some additional interest.

Todd Smith <todd.smith@camc.org>



-----Original Message-----
From: Kevin D. Kissell [mailto:kevink@mips.com]
Sent: Tuesday, June 18, 2002 10:00 AM
To: linux-mips@fnet.fr; linux-mips@oss.sgi.com
Subject: Linux and the Sony Playstation 2


The Sony PS2 Linux kit has been shipping for nearly
a month now, and I'm frankly astonished at how little
I've seen on this mailing list about it.  For better or
for worse, this changes everything for MIPS/Linux.
The number of MIPS/Linux users worldwide has
just gone up by at least an order of magnitude,
and they are on a platform running a 2.2.1-derived
kernel and using gcc 2.95.2.

It's a perfectly usable platform out of the box, but
Carsten has thrown "crashme" at it, and it goes down
relatively quickly.  People trying to port kaffe and
other programs that do double-precision float are
blocked because there's no double precision on the
R5900, and the Sony kernel lacks the Algorithmics
emulator.

It's not clear what Sony is going to put into further
development, and what they are going to expect the
user community to take over from here.  There is a 
group of people trying to take the kernel up to
2.2.20, but I'm not yet sure whether they know
what they are doing, and anyway, that box needs
to get to 2.4.x ASAP.

I respectfully submit that, within a year, any 
MIPS/Linux  source tree that does not support 
the PS2 will be considered obsolete.  And that
quite specifically includes the one at oss.sgi.com.
I personally would want to approach this in terms 
of merging the necessary PS2 code into something
that could be expressed as a patch over kernel.org's
2.4.19_or_better, and which would be provded 
as the default MIPS kernel technology by MIPS 
and SGI servers, and ultimately by kernel.org.

Is no one else here working on this?

            Regards,

            Kevin K.

From owner-linux-mips@oss.sgi.com Wed Jun 19 13:37:20 2002
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Date: Wed, 19 Jun 2002 13:38:52 -0700 (PDT)
From: Paul Jackson <pj@engr.sgi.com>
To: William Jhun <wjhun@ayrnetworks.com>
Cc: Ralf Baechle <ralf@oss.sgi.com>, <linux-mips@oss.sgi.com>
Subject: Re: [PATCH] include/asm-mips/pci.h
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On Wed, 19 Jun 2002, William Jhun wrote:
> Note that without the #ifdefs, you may get warnings like:
>
> ../../../ayr/linux/include/asm/pci.h: In function `prep_buffer':
> ../../../ayr/linux/include/asm/pci.h:89: warning: statement with no effect
> ...
>
> So are we still sure we want to leave them out?


Yes - leave them out (speaking out of context here - hopefully still
useful).

Remove the warnings instead.

I've gotten in the habit of having the following form to
optional code logic:

In some header file foobar.h:

    #if CONFIG_FOOBAR
    #define init_foobar(x) do {		\
	    int f = 2 * (x);		\
	    foobar_initialize(f);	\
	| while (0)
    #else
    #define init_foobar(x) do {} while (0)
    #endif

I don't see any warnings from this, and it provides just
the right sort of syntax wrapper on the macro init_foobar(),
forcing it to be a single statement, regardless of context,
while providing a nested block context for any local variables.


-- 
                          I won't rest till it's the best ...
                          Programmer, Linux Scalability
                          Paul Jackson <pj@sgi.com> 1.650.933.1373


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From: Ralf Baechle <ralf@oss.sgi.com>
To: Paul Jackson <pj@engr.sgi.com>
Cc: William Jhun <wjhun@ayrnetworks.com>, linux-mips@oss.sgi.com
Subject: Re: [PATCH] include/asm-mips/pci.h
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On Wed, Jun 19, 2002 at 01:38:52PM -0700, Paul Jackson wrote:

> Yes - leave them out (speaking out of context here - hopefully still
> useful).
> 
> Remove the warnings instead.
> 
> I've gotten in the habit of having the following form to
> optional code logic:
> 
> In some header file foobar.h:
> 
>     #if CONFIG_FOOBAR
>     #define init_foobar(x) do {		\
> 	    int f = 2 * (x);		\
> 	    foobar_initialize(f);	\
> 	| while (0)
>     #else
>     #define init_foobar(x) do {} while (0)
>     #endif
> 
> I don't see any warnings from this, and it provides just
> the right sort of syntax wrapper on the macro init_foobar(),
> forcing it to be a single statement, regardless of context,
> while providing a nested block context for any local variables.

Note your variant doesn't deal with side effects of the argument expression
x (basically none of the equivalent constructions in the kernels do!) which
is why our code in question does something like this:

     #if CONFIG_FOOBAR
     #define init_foobar(x) do {               \
           int f = 2 * (x);            \
           foobar_initialize(f);       \
       | while (0)
     #else
     #define init_foobar(x) do { (x); } while (0)
     #endif

This can potencially expand into something like:

     do { 42; } while(0)

which will result in warnings.  The solution is:

     #define init_foobar(x) do { (void) (x); } while (0)

  Ralf

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To: "Smith, Todd" <Todd.Smith@camc.org>
cc: "'linux-mips@oss.sgi.com'" <linux-mips@oss.sgi.com>
Subject: RE: Linux and the Sony Playstation 2
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On Wed, 19 Jun 2002, Smith, Todd wrote:

> This list is been pretty quiet lately so I don't really know what is
> happening on the Linux/MIPS front.  I am hoping that work is still slowly
> proceeding on the DECstation that I have, but I don't really know.  I agree
> with you that PS2 offer enormous power to the developer and as a cheap
> source of computing power to other countries.

 I'm doing some development on the DECstation -- changes get applied to
the CVS as they are ready (e.g. I fixed a few bugs in declance yesterday). 
The last large change was the IRQ handling rewrite (small parts of which
are still pending awaiting approval of generic bits they depend on).  I'm
planning another big change soon.

 If you have any problems, just report them here. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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To: "Smith, Todd" <Todd.Smith@camc.org>
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Subject: Re: Linux and the Sony Playstation 2
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On Wed, Jun 19, 2002 at 04:10:52PM -0400, Smith, Todd wrote:

> This list is been pretty quiet lately so I don't really know what is
> happening on the Linux/MIPS front.  I am hoping that work is still slowly
> proceeding on the DECstation that I have, but I don't really know.  I agree

Which model Du you have? I am actively using Linux/MIPS on a DECstation
5000/150 (although not with a bleeding-edge kernel), and it works rather
well for me.

Regards,
Karsten
-- 
#include <standard_disclaimer>
Nach Paragraph 28 Abs. 3 Bundesdatenschutzgesetz widerspreche ich der Nutzung
oder Uebermittlung meiner Daten fuer Werbezwecke oder fuer die Markt- oder
Meinungsforschung.

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Thanks for the update.  Has there been any work on the website updating what
works and what doesn't?

Todd Smith

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Subject: Re: Bug in Linux?  fcr31 not being saved-restored
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I think this patch is OK.

Whatever your gcc test is, it seems like it should fail on all other archs 
too, because a new program would always inherit the old fpu registers.  It 
would be interesting to do a test on those platforms.

I can see that having old values for general FPU registers is not a problem, 
but having the old value in FPU status register might.  So an alternative is 
to clear fcr31 only in start_thread().

Note that without your patch, the secondary if (last_task_used_math != NULL) 
branch is never taken.  This is because init process will be the only process 
that does not have used_math flag set and in that case last_task_use_math is 
indeed NULL.  All other processes will inherit the used_math flag from its parent.

Jun

Carsten Langgaard wrote:

> Jun Sun wrote:
> 
> 
>>Your first chunk is not clear as to where it applies.  Maybe you are using a
>>different code base.
>>
> 
> Here is my do_cpu handler:
> 
> asmlinkage void do_cpu(struct pt_regs *regs)
> {
>         unsigned int cpid;
>         extern void lazy_fpu_switch(void *);
>         extern void save_fp(struct task_struct *);
>         extern void init_fpu(void);
>         void fpu_emulator_init_fpu(void);
>         int sig;
> 
>         cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
>         if (cpid != 1)
>                 goto bad_cid;
> 
>         if (!(mips_cpu.options & MIPS_CPU_FPU))
>                 goto fp_emul;
> 
>         regs->cp0_status |= ST0_CU1;
>         if (last_task_used_math == current)
>                 return;
> 
>         if (current->used_math) {               /* Using the FPU again.  */
>                 lazy_fpu_switch(last_task_used_math);
>         } else {                                /* First time FPU user.  */
>                 if (last_task_used_math != NULL)
>                 {
>                         __enable_fpu();
>                         save_fp(last_task_used_math);
>                         /* last_task_used_math loose fpu */
>                         ((struct pt_regs *)(__KSTK_TOS(last_task_used_math) -
>                                             sizeof(struct pt_regs)))->
>                                 cp0_status &= ~ST0_CU1;
>                 }
>                 init_fpu();
>                 current->used_math = 1;
>         }
>         last_task_used_math = current;
> 
>         return;
> 
> fp_emul:
>         if (last_task_used_math != current) {
>                 if (!current->used_math) {
>                         fpu_emulator_init_fpu();
>                         current->used_math = 1;
>                 }
>         }
>         sig = fpu_emulator_cop1Handler(0, regs, &current->thread.fpu.soft);
>         last_task_used_math = current;
>         if (sig)
>         {
>                 /*
>                  * Return EPC is not calculated in the FPU emulator, if
>                  * a signal is being send. So we calculate it here.
>                  */
>                 compute_return_epc(regs);
>                 force_sig(sig, current);
>         }
>         return;
> 
> bad_cid:
> #ifndef CONFIG_CPU_HAS_LLSC
>         switch (mips_cpu.cputype) {
>         case CPU_TX3927:
>         case CPU_TX39XX:
>                 do_ri(regs);
>                 return;
>         }
> #endif
>         compute_return_epc(regs);
>         force_sig(SIGILL, current);
> }
> 
> 
> 
>>The second chunck is not necessary.  Although the FPU values in thread struct
>>for the new thread are stale, the new program cannot assume the fpu register
>>values and cannot use them without initialization anyway.
>>
> 
> At least with the do_cpu handler above, you need this.
> I'm not sure which tests failed without this, but I think it was some of the gcc selftests
> and I think the problem was, that a thread inherited the previous thread's fsr (floating
> point status register).
> 
> 
>>I don't see such a code in x86's code.  Current call to start_thread() is ok
>>with or without this change.  I am afraid future use of start_thread() may
>>give undesired effect after we make this change.
>>
> 
> Why ?
> 
> 
>>As for the new fpu context switch code, I wrote a experiemental patch after
>>much discussion with Ralf and Kevin.  It is at
>>
>>http://linux.junsun.net/patches/oss.sgi.com/experimental/020304-half-fpu-context-switch
>>
>>I also did some performance study of this patch.  Did not get much feedbacks
>>when I asked last time. :-(
>>
>>Jun
>>
>>Carsten Langgaard wrote:
>>
>>
>>>I believe this is the patch that solve the problem.
>>>The lazy fpu stuff has cause so many problems, that we have decided (together
>>>with Ralf) to get rid of it, and do the FPU context save and restore a little bit
>>>differently.
>>>We now have a solution here locally and we are testing it at the moment.
>>>
>>>/Carsten
>>>
>>>
>>>Index: arch/mips/kernel/traps.c
>>>===================================================================
>>>RCS file: /cvs/linux/arch/mips/kernel/traps.c,v
>>>retrieving revision 1.99.2.14
>>>diff -u -r1.99.2.14 traps.c
>>>--- arch/mips/kernel/traps.c    2002/05/28 06:33:13     1.99.2.14
>>>+++ arch/mips/kernel/traps.c    2002/06/18 07:53:47
>>>+               {
>>>+                       __enable_fpu();
>>>                        save_fp(last_task_used_math);
>>>+                       /* last_task_used_math loose fpu */
>>>+                       ((struct pt_regs *)(__KSTK_TOS(last_task_used_math) -
>>>+                                           sizeof(struct pt_regs)))->
>>>+                               cp0_status &= ~ST0_CU1;
>>>+               }
>>>
>>>Index: include/asm-mips/processor.h
>>>===================================================================
>>>RCS file: /cvs/linux/include/asm-mips/processor.h,v
>>>retrieving revision 1.43.2.2
>>>diff -u -r1.43.2.2 processor.h
>>>--- include/asm-mips/processor.h        2002/05/28 06:11:56     1.43.2.2
>>>+++ include/asm-mips/processor.h        2002/06/18 07:56:58
>>>@@ -215,6 +215,7 @@
>>>        regs->cp0_epc = new_pc;                                         \
>>>        regs->regs[29] = new_sp;                                        \
>>>        current->thread.current_ds = USER_DS;                           \
>>>+       current->used_math = 0;                                         \
>>> } while (0)
>>>
>>> unsigned long get_wchan(struct task_struct *p);
>>>
>>>
>>>
>>>Jun Sun wrote:
>>>
>>>
>>>
>>>>Carsten Langgaard wrote:
>>>>
>>>>
>>>>
>>>>>This is one of the bugs, among others, we have fixed.
>>>>>I'm not sure, if Ralf have integrated the patches we send him yet.
>>>>>
>>>>>
>>>>>
>>>>Carsten,
>>>>
>>>>Do you remember the cause and the fix?  It appears to me the first ctc1
>>>>instruction should trap into kernel and mark current process as fpu owner, and
>>>>should not cause fcr31 corruption.
>>>>
>>>>Or somehow the ctc1 does not trap into kernel?
>>>>
>>>>Jun
>>>>
>>>>
>>>>
>>>>>/Carsten
>>>>>
>>>>>Louis Hamilton wrote:
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>>We have a customer here testing a 2.4.16 mips kernel on an embedded
>>>>>>Linux RM7000/SR71000 based system who has written a test that they
>>>>>>believe has uncovered a bug in Linux.  The FPU control register appears
>>>>>>to not get saved and restored.  I've reproduced the problem described
>>>>>>below and find the results consistent with their description.  The
>>>>>>problem occurs on both the RM7000 and SR71000 cpus.
>>>>>>
>>>>>>It looks like save_fp_context and restore_fp_context are not being
>>>>>>called since the kernel save-restore logic thinks the process is not
>>>>>>using floating point math.  If you do some fp math before calling the
>>>>>>test routine below, it seems to works fine.
>>>>>>
>>>>>>Is this a known caveat?  A true bug?  Or a contorted corner case
>>>>>>unlikely to be seen under typical end-user usage (see customer's
>>>>>>last paragraph :-) ?   If true bug, recommended remedy?
>>>>>>
>>>>>>TIA,
>>>>>>Louis
>>>>>>
>>>>>>Louis Hamilton
>>>>>>hamilton@redhat.com
>>>>>>
>>>>>>------ customer reports the following: ---------
>>>>>>We found a bug in Linux.  A ^C (control-C) typed into a shell (or a
>>>>>>running program, it doesn't matter), causes the FCR (floating-point
>>>>>>control register) to be corrupted in another, unrelated process.  This
>>>>>>is repeatable behavior.
>>>>>>
>>>>>>This can be reproduced with the following short assembly language
>>>>>>program that loops forever, waiting for the FCR to change.
>>>>>>
>>>>>>      .align 2
>>>>>>      .globl mips_float_debug_loop
>>>>>>mips_float_debug_loop:
>>>>>>      li      $9, 0xF000F02F
>>>>>>      ctc1    $9, $31         # set FCR to some non-zero value
>>>>>>      nop
>>>>>>1:      cfc1    $8, $31         # get FCR
>>>>>>      beq     $8, $9, 1b      # spin, waiting for FCR to change
>>>>>>      nop
>>>>>>      or      $2, $0, $8
>>>>>>      jr    $31
>>>>>>      nop
>>>>>>
>>>>>>You can call this function from a short C program and the return value
>>>>>>is the (corrupted) FCR, which turns out to alwyas be: 0x00000002.
>>>>>>
>>>>>>Run the above loop in one window (connected to the board using telnet)
>>>>>>and then in another window (connected to the same board) type ^C.
>>>>>>
>>>>>>I'm surprised this bug hasn't been encountered by other MIPS vendors.
>>>>>>
>>>>>><end>
>>>>>>
>>>>>--
>>>>>_    _ ____  ___   Carsten Langgaard Mailto:carstenl@mips.com
>>>>>|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
>>>>>| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>>>>> TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>>>>>                  Denmark           http://www.mips.com
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>--
>>>_    _ ____  ___   Carsten Langgaard  Mailto:carstenl@mips.com
>>>|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
>>>| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>>>  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>>>                   Denmark            http://www.mips.com
>>>
>>>
>>>
>>>
>>>
> 
> --
> _    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
> |\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
> | \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
>   TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
>                    Denmark             http://www.mips.com
> 
> 
> 
> 



From owner-linux-mips@oss.sgi.com Thu Jun 20 12:21:06 2002
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Date: Thu, 20 Jun 2002 12:22:49 -0700
From: "H . J . Lu" <hjl@lucon.org>
To: linux-gcc@vger.kernel.org, GNU C Library <libc-alpha@sources.redhat.com>,
   gcc@gcc.gnu.org, Kenneth Albanowski <kjahds@kjahds.com>,
   Mat Hostetter <mat@lcs.mit.edu>,
   Andy Dougherty <doughera@lafcol.lafayette.edu>,
   Warner Losh <imp@village.org>, linux-mips@oss.sgi.com,
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   Leonard Zubkoff <lnz@dandelion.com>, "Steven J. Hill" <sjhill@cotw.com>
Subject: The Linux binutils 2.12.90.0.12 is released
Message-ID: <20020620122249.A17654@lucon.org>
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This is the beta release of binutils 2.12.90.0.12 for Linux, which is
based on binutils 2002 0618 in CVS on sourecs.redhat.com plus various
changes. It is purely for Linux.

The Linux/mips support is added. You have to use

# rpm --target=[mips|mipsel] -ta binutils-xx.xx.xx.xx.xx.tar.gz

to build it. Or you can read mips/README in the source tree to apply
the mips patches and build it by hand.

FYI, the binutils man pages now are generated from the texinfo files
during the build. As the result, those man pages may be changed for
each build even if you only have done

# ..../configure ...
# make

That means you may have many failures on the man pages when you apply
the binutils diffs next time. Those failures can be safely ignored.
You should remove all those man pages from your source tree by

# find -name *.1 | xargs rm -f
# find -name *.1.rej | xargs rm -f
# find -name *.man | xargs rm -f
# find -name *.man.rej | xargs rm -f

Please report any bugs related to binutils 2.12.90.0.12 to hjl@lucon.org.

For arm-linux targets, there are some important differences in behaviour 
between these tools and binutils 2.9.1.0.x.  The linker emulation name has 
changed from elf32arm{26} to armelf_linux{26}.  Also, the "-p" flag must be 
passed with the linker when working with object files (or static libraries) 
created using older versions of the assembler.  If this flag is omitted the 
linker will silently generate bad output when given old input files.

To get the correct behaviour from gcc, amend the *link section of your specs 
file as follows:

*link:
%{h*} %{version:-v}    %{b} %{Wl,*:%*}    %{static:-Bstatic}    %{shared:-shared}    %{symbolic:-Bsymbolic}    %{rdynamic:-export-dynamic}    %{!dynamic-linker: -dynamic-linker /lib/ld-linux.so.2}    -X    %{mbig-endian:-EB} %{mapcs-26:-m armelf_linux26} %{!mapcs-26:-m armelf_linux} -p


Changes from binutils 2.12.90.0.11:
1. Update from binutils 2002 0618.
2. Fix an mips assembler bug.

Changes from binutils 2.12.90.0.9:

1. Update from binutils 2002 0608.
2. Fix an ELF/mips SHF_MERGE bug.

Changes from binutils 2.12.90.0.7:

1. Update from binutils 2002 0526.
2. Support "-z muldefs".

Changes from binutils 2.12.90.0.4:

1. Update from binutils 2002 0423.
2. ELF EH frame bug fix.
3. MIPS ELF visibility bug fix.

Changes from binutils 2.12.90.0.3:

1. Update from binutils 2002 0408.
2. Bug fixes for ELF/sparc.
3. Bug fixes for ELF/CRIS.

Changes from binutils 2.12.90.0.1:

1. Update from binutils 2002 0323.
2. Fix linking a.out relocatable files with ELF.
3. Fix a PPC altivec assembler bug.

Changes from binutils 2.11.93.0.2:

1. Update from binutils 2002 0307.
2. Add the .preinit_array/.init_array/.fini_array support.
3. Fix eh_frame.
4. Turn on combreloc by default.
5. Enable gprof for Linux/mips.

Changes from binutils 2.11.92.0.12.3:

1. Update from binutils 2002 0207.
2. Fix a weak symbol alpha linker bug for glibc.
3. More support for gcc 3.1.

Changes from binutils 2.11.92.0.12:

1. Fix a regression in 2.11.92.0.12 when linking with none-ELF object
files.

Changes from binutils 2.11.92.0.10:

1. Update from binutils 2001 1121.
2. Fix a linker symbol version bug for common symbols.
3. Update handling relocations against the discarded sections. You may
need to apply the kernel patch enclosed here to your kernel source. If
you still see things like

drivers/char/char.o(.data+0x46b4): undefined reference to `local symbols in discarded section .text.exit'

in the final kernel link, that means you have compiled a driver into
the kernel which has a reference to the symbol in a discarded section.
Kernel 2.4.17 or above should work fine.

4. Support "-march=xxx -mipsN" for mips gas if they are compatible.

Changes from binutils 2.11.92.0.7:

1. Update from binutils 2001 1021.
2. Fix the ELF/PPC linker.
3. Fix the ELF/cris linker.
4. Fix ELF strip.

Changes from binutils 2.11.92.0.5:

1. Update from binutils 2001 1016.
2. Fix all breakages introduced in 2.11.92.0.12.

Changes from binutils 2.11.90.0.31:

1. Update from binutils 2001 1005.
2. Support gcc 3.1 for ia64.
3. Support prelink for ELF/PPC.
4. Fix an ELF/x86 linker bug for Oracle.
5. Fix a weak symbol bug.
6. Support locale.

Changes from binutils 2.11.90.0.29:

1. Update from binutils 2001 0830.
2. Fix a mips linker bug.

Changes from binutils 2.11.90.0.27:

1. Update from binutils 2001 0827.
2. Fix an alpha assembler bug.
3. Fix an ia64 linker bug.
4. Fix a mips linker bug.
5. Support `-z combreloc|nocombreloc' in linker.

Changes from binutils 2.11.90.0.25:

1. Update from binutils 2001 0810.
2. Fix an x86 linker bug.

Changes from binutils 2.11.90.0.24:

1. Update from binutils 2001 0726.
2. Fix an x86 assembler bug.
3. "make check" in the windres test in binutils may call uudecode. We
are working on it.
4. "make check" fails the windres test in binutils if the i386/pe
is enabled in bfd. Fixed in the next release.
5. "make check" has 2 failures in the ld-selective test in ld on
Linux/alpha. They should be marked xfail. Fixed in the next release.

Changes from binutils 2.11.90.0.23:

1. Update from binutils 2001 0714.
2. Fix Sparc/ElF for Linux/sparc.
3. Fix Alpha/ELF for gcc 3.0.

Changes from binutils 2.11.90.0.19:

1. Update from binutils 2001 0706.
2. Fix objcopy/strip broken by accident.
3. Avoid COPY relocs on ia32.
4. Fix the ia64 assembler.
5. This release may not work on Linux/sparc due to the unaligned
relocation changes, which are not handled by all versions of glibc.
The current glibc in CVS on sourceware should be ok. The last known
working binutils for Linux/sparc is 2.11.90.0.8. We are working on it.

Changes from binutils 2.11.90.0.15:

1. Update from binutils 2001 0620.
2. Fix a static linking the PIC object files on ia32.
3. Add the verion script support for --export-dynamic. It can be used
to selectively export dynamic symbols from the executables.

Changes from binutils 2.11.90.0.8:

1. Update from binutils 2001 0610.
2. Fix a gas bug for gcc 3.0.

Changes from binutils 2.11.90.0.7:

1. Update from binutils 2001 0512.
2. Fix some P/III SSE 2 assembler bugs.
3. Fix DT_NEEDED and symbol version bugs.
4. Support hidden versioned symbols in DSOs.

Changes from binutils 2.11.90.0.6:

1. Update from binutils 2001 0427.
2. Fix the -Bsymbolic bug introduced in binutils 2.11.90.0.5.

Changes from binutils 2.11.90.0.5:

1. Update from binutils 2001 0425.
2. Update "ld --multilib-dir PATH".

Changes from binutils 2.11.90.0.4:

1. Update from binutils 2001 0414.
2. Fix an ia64 assembler bug.
3. Change Linux/MIPS to use the SVR4 MIPS ABI instead of the IRIX ABI.
since there are no supports for the IRIX ABI in glibc. The current
Linux/MIPS targets are elf64-tradlittlemips for little endian MIPS
instead of elf32-littlemips and elf64-tradbigmips for big endian MIPS
instead of elf32-bigmips. Glibc, gcc and kernel may have to be modified
for this change. 

Changes from binutils 2.11.90.0.1:

1. Update from binutils 2001 0401.
2. Fix a gas bug for the gcc from the CVS main trunk. It involves some
changes in gas. I compiled kernel 2.2.18, gcc and glibc under
Linux/ia32. The resulting binaries work fine. 
3. Fix the linker core dump on unsupported ELF binaries.

Changes from binutils 2.10.91.0.4:

1. Update from binutils 2001 0309.

Changes from binutils 2.10.91.0.2:

1. Update from binutils 2001 0223.
2. More ia64 bug fixes.

Changes from binutils 2.10.1.0.7:

1. Update from binutils 2001 0215.
2. More ia64 bug fixes. Support EFI and "ld -relax" on ia64.
3. Fix a weak definition, -Bsymbolic, non-PIC bug for ia32.

Changes from binutils 2.10.1.0.4:

1. Update from binutils 2001 0206.
2. Enable the IA64 support.
3. Now you need to use

# ld --oformat TARGET

instead of

# ld -oformat TARGET

The Linux kernel build may be affected. BTW

# ld --oformat TARGET

should work with all previous releases of binutils.

Changes from binutils 2.10.1.0.2:

1. Update from binutils 2000 1221.

Changes from binutils 2.10.0.33:

1. Update from binutils 2000 1119.
2. It has some symbol versioning related updates.

Changes from binutils 2.10.0.32:

1. Update from binutils 2000 1018.
2. A proper ELF/PPC visibility fix.
3. m68k-a.out is supposed to be fixed.

Changes from binutils 2.10.0.31:

1. Update from binutils 2000 1014.
2. An ELF/PPC weak symbol bug fix.
3. A new linkonce section name approach.
4. m68k-a.out is still broken. To be fixed.

Changes from binutils 2.10.0.29:

1. Update from binutils 2000 1011.
2. Back out the linkonce section name change so that C++ will work.
A different approach is being worked on.
3. m68k-a.out is known to be broken. To be fixed.

Changes from binutils 2.10.0.26:

1. Update from binutils 2000 1008.

Changes from binutils 2.10.0.24:

1. Update from binutils 2000 0907.

Changes from binutils 2.10.0.18:

1. Update from binutils 2000 0823. Fix DT_RPATH/DT_RUNPATH handling.
Fix the ELF/ia32 DSO not compiled with PIC.
2. Try to fix the ELF visibility bug on PPC with glibc 2.2.

Changes from binutils 2.10.0.12:

1. Update from binutils 2000 0720.
2. Fix the DT_NEEDED link bug.
3. Add the new DT_XXXX dynamic tags. Glibc 2.2 will use them at least
on libpthread.so.

Changes from binutils 2.10.0.9:

1. Update from binutils 2000 0701. Fix the parallel build in ld when PE
is enabled.

Changes from binutils 2.9.5.0.46:

1. Update from binutils 2000 0617. The demangler support for the new
g++ ABI. Minor fix for the ELF visibility. Fix linking non-ELF
relocatable object files under ELF with symbol versioning.
2. Support for linking PE relocatable object files under ia32/ELF.

Changes from binutils 2.9.5.0.42:

1. Update from binutils 2000 0604. The ELF visibility attribuite should
work correctly now.
2. The ia32 assembler has changed the way it assembles the "jmp"
instructions to the global symbols. The old assembler will optimize the
jump to the global symbol defined in the same source file so that no
relocation will be used. The new assembler will use relocation for
global jumps. It will mainly affect PIC asm code. The segment like

	.globl  __setjmp
__setjmp:
	...
	jmp __sigsetjmp
	...
	.globl __sigsetjmp
__sigsetjmp:

is no longer PIC safe since "jmp __sigsetjmp" jumps to a global symbol
and relocation will be used. Instead, it can be changed to

	.globl  __setjmp
__setjmp:
	...
	jmp sigsetjmp
	...
	.globl __sigsetjmp
__sigsetjmp:
sigsetjmp:

so that "jmp sigsetjmp" jumps to a local symbol and the new assembler
will optimize out the relocation.

Changes from binutils 2.9.5.0.41:

1. Update from binutils 2000 0512.
2. Add testsuite for ELF visibility.

Changes from binutils 2.9.5.0.37:

1. Update from binutils 2000 0502.
2. Support STV_HIDDEN and STV_INTERNAL.

Changes from binutils 2.9.5.0.35:

1. Update from binutils 2000 0418.
2. Fix an ld demangle style option bug.

Changes from binutils 2.9.5.0.34:

1. Update from binutils 2000 0412. Fix a relocation bug which affects
the Linux kernel compilation.
2. An ELF/PPC linker script update.

Changes from binutils 2.9.5.0.33:

1. Update from binutils 2000 0404. Fix the bug report bug.

Changes from binutils 2.9.5.0.32:

1. Update from binutils 2000 0403. Fix the 16bit ia32 assembler bug.

Changes from binutils 2.9.5.0.31:

1. Update from binutils 2000 0331. Fix the Linux/ARM assembler bug.
2. Fix a Debian assembler security bug.

Changes from binutils 2.9.5.0.29:

1. Update from binutils 2000 0319.
2. An ELF/alpha bug is fixed.

Changes from binutils 2.9.5.0.27:

1. Update from binutils 2000 0301.
2. A demangler bug is fixed.
3. A better fix for undefined symbols with -Bsymbolic when building
shared library.

Changes from binutils 2.9.5.0.24:

1. Update from binutils 2000 0204.
2. Added -taso to linker on alpha.
3. Fixed a -shared -Bsymbolic bug when PIC is not used.

Changes from binutils 2.9.5.0.22:

1. Update from binutils 2000 0113.
2. A symbol version bug is fixed.
3. A -Bsymbolic bug is fixed.

Changes from binutils 2.9.5.0.21:

1. Update from binutils 1999 1202.
2. Remove a MIPS/ELF change.
3. Enable SOM for HPPA.

Changes from binutils 2.9.5.0.19:

1. Update from binutils 1999 1122. An ia32 gas bug is fixed.

Changes from binutils 2.9.5.0.16:

1. Update from binutils 1999 1104.
2. i370 is changed to use EM_S370 and ELFOSABI_LINUX. Update readelf.
3. Fix Compaq's demangler support.

Changes from binutils 2.9.5.0.14:

1. Update from binutils 1999 1012. A gas bug which affects Linux 2.3.21
is fixed.
2. i370 update.
3. The new demangler code. You should use "--style=xxx" to select the
demnangle style instead of "--lang=xxx".

Changes from binutils 2.9.5.0.13:

1. Update from binutils 1999 0925.
2. Fix a -s and linker script bug.

Changes from binutils 2.9.5.0.12:

1. Update from binutils 1999 0922.
2. i370 update.

Changes from binutils 2.9.5.0.11:

1. Update from binutils 1999 0910. It fixed a PIC linker bug on ix86
   and sparc introduced in the last release.
2. i370 update.

Changes from binutils 2.9.5.0.10:

1. Update from binutils 1999 0906. It fixed a PIC linker bug on ix86
   and sparc.
2. Remove elf/hppa since it is WIP.

Changes from binutils 2.9.5.0.8:

1. Update from binutils 1999 0831. It allows spaces around '(' and ')'
   in x86 FP register names.

Changes from binutils 2.9.5.0.7:

1. Update from binutils 1999 0821.
2. Some MIPS changes.

Changes from binutils 2.9.5.0.6:

1. Update from binutils 1999 0813.
2. i370 update.

Changes from binutils 2.9.5.0.5:

1. Update from binutils 1999 0809. An ELF/Sparc ld bug is fixed.

Changes from binutils 2.9.5.0.4:

1. Update from binutils 1999 0806. A Solaris/Sparc gas bug is fixed.
2. Remove mips gas patches from binutils 2.9.1.0.25.

Changes from binutils 2.9.5.0.3:

1. Update from binutils 1999 0801.
2. Support for real mode x86 gcc.

Changes from binutils 2.9.4.0.8:

1. Update from binutils 1999 0719. A libc 5 related bug fix.
2. Fix a typo in mips gas.

Changes from binutils 2.9.4.0.7:

1. Update from binutils 1999 0710. A weak symbol bug

http://egcs.cygnus.com/ml/egcs-bugs/1999-07/msg00129.html

is fixed.

Changes from binutils 2.9.4.0.6:

1. Update from binutils 1999 0626.

Changes from binutils 2.9.4.0.5:

1. Update from binutils 1999 0620.
2. Remove my fwait fix and use the one in cvs.
3. Use "--only-section=section" instead of "--extract-section=section".
   for objcopy.

Changes from binutils 2.9.4.0.4:

1. Update from binutils 1999 0612.
2. Remove various temporary fixes of mine since those bugs are fixed
   now.

Changes from binutils 2.9.4.0.3:

1. Update from binutils 1999 0611.
2. Remove my ELF/Alpha bfd changes.
3. Use the local symbol copy fix in binutils 1999 0611.

Changes from binutils 2.9.4.0.2:

1. Update from binutils 1999 0607.
2. Remove my Sparc hacks.
3. Fix local symbol copy.

Changes from binutils 2.9.4.0.1:

1. Update from binutils 1999 0606.
2. Restore relocation overflow checking in binutils 2.9.1.0.25 so that
   Linux kernel can build.
3. Fix i370 for the new gas.

Changes from binutils 1999 0605:

1. Fix a -Bsymbolic bug for Linux/alpha.
2. Add ELF/i370.
3. Fix 8/16-bit relocations for i386.
4. Add --redefine-sym=old_form=new_form to objcopy.
5. Add "-j section" for objcopy.
6. Fix i386 disassembler for fwait.
7. Fix a Sparc asm bug.
8. Add Ada demangle support.
9. Fix MIPS/ELF bugs.
10. Add some vxworks suppport.
11. Fix a.out assembler.

The file list:

1. binutils-2.12.90.0.12.tar.gz. Source code.
2. binutils-2.12.90.0.11-2.12.90.0.12.diff.gz. Patch against the
   previous beta source code.
3. binutils-2.12.90.0.12-1.i386.rpm. IA-32 binary RPM for RedHat 7.3.

There is no separate source rpm. You can do

# rpm -ta binutils-2.12.90.0.12.tar.gz

to create both binary and source rpms.

The primary sites for the beta Linux binutils are:

1. http://ftp.kernel.org/pub/linux/devel/binutils/

Thanks.


H.J. Lu
hjl@lucon.org
06/19/2002

From owner-linux-mips@oss.sgi.com Thu Jun 20 16:56:24 2002
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From: "David Christensen" <dpchrist@holgerdanske.com>
To: <linux-mips@oss.sgi.com>
Cc: <laguest@nebulas.demon.co.uk>
References: <007601c216d0$6f7f0840$10eca8c0@grendel> <3D104BA4.BEEAAB6C@mips.com> <011501c217c4$8daeb0a0$0b01a8c0@w2k30g> <E17LA2R-0001PQ-0X@anchor-post-33.mail.demon.net>
Subject: Re: Linux and the Sony Playstation 2
Date: Thu, 20 Jun 2002 16:59:53 -0700
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Luke:

"OSI" is the Open Source Initiative:

    http://www.opensource.org/


David



----- Original Message -----
From: "Luke A. Guest" <laguest@nebulas.demon.co.uk>
To: "David Christensen" <dpchrist@holgerdanske.com>
Sent: Wednesday, June 19, 2002 3:08 PM
Subject: Re: Linux and the Sony Playstation 2


On Wednesday 19 Jun 2002 7:18 pm, you wrote:
> Everyone:
>
> "Carsten Langgaard" <carstenl@mips.com> wrote on
> linux-mips@oss.sgi.com:
> > The DVDs you get with the linux kit, contain all necessary hardware
> > documentation.

Not all, but most of them. Basically you get the black/blue books in PDF
form.

> OK  I assume the license is also on the DVD's.
>
> 1.  Are the documents and license available online?  If so, what
>     is/are the URL(s)?

Not unless you're a PS2 developer.

> 2.  Has Sony submitted their license to OSI for approval?

OSI?

Luke.



From owner-linux-mips@oss.sgi.com Fri Jun 21 00:43:19 2002
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Date: Fri, 21 Jun 2002 09:46:48 +0200 (MET DST)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: "Smith, Todd" <Todd.Smith@camc.org>
cc: "'linux-mips@oss.sgi.com'" <linux-mips@oss.sgi.com>
Subject: Re: DECstation
In-Reply-To: <490E0430C3C72046ACF7F18B7CD76A2A568B90@KES.camcare.com>
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On Thu, 20 Jun 2002, Smith, Todd wrote:

> Thanks for the update.  Has there been any work on the website updating what
> works and what doesn't?

 What website do you specifically refer to?  If you mean
'http://decstation.unix-ag.org/', then that's notoriously out of date. 
But Karel does a pretty good job maintaining his site -- see
'http://www.xs4all.nl/~vhouten/mipsel/'. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Fri Jun 21 06:53:26 2002
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From: "Smith, Todd" <Todd.Smith@camc.org>
To: "''linux-mips@oss.sgi.com' '" <linux-mips@oss.sgi.com>
Subject: DECstation
Date: Fri, 21 Jun 2002 09:56:11 -0400
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Hello,

I was curious about the DECstation 5000/133 and a graphical console.

Todd Smith

-----Original Message-----
From: Karsten Merker
To: Smith, Todd
Cc: 'linux-mips@oss.sgi.com'
Sent: 6/20/2002 1:27 PM
Subject: Re: Linux and the Sony Playstation 2

On Wed, Jun 19, 2002 at 04:10:52PM -0400, Smith, Todd wrote:

> This list is been pretty quiet lately so I don't really know what is
> happening on the Linux/MIPS front.  I am hoping that work is still
slowly
> proceeding on the DECstation that I have, but I don't really know.  I
agree

Which model Du you have? I am actively using Linux/MIPS on a DECstation
5000/150 (although not with a bleeding-edge kernel), and it works rather
well for me.

Regards,
Karsten
-- 
#include <standard_disclaimer>
Nach Paragraph 28 Abs. 3 Bundesdatenschutzgesetz widerspreche ich der
Nutzung
oder Uebermittlung meiner Daten fuer Werbezwecke oder fuer die Markt-
oder
Meinungsforschung.

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From: "Smith, Todd" <Todd.Smith@camc.org>
To: "''linux-mips@oss.sgi.com' '" <linux-mips@oss.sgi.com>
Subject: RE: DECstation
Date: Fri, 21 Jun 2002 09:58:25 -0400
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Hello,

The http://decstation.unix-ag.org is the site that I was refering to.  The
sother site that you mentioned, I get a 404 on it.

Thanks for your time

Todd Smith <todd.smith@camc.org>

-----Original Message-----
From: Maciej W. Rozycki
To: Smith, Todd
Cc: 'linux-mips@oss.sgi.com'
Sent: 6/21/2002 3:46 AM
Subject: Re: DECstation

On Thu, 20 Jun 2002, Smith, Todd wrote:

> Thanks for the update.  Has there been any work on the website
updating what
> works and what doesn't?

 What website do you specifically refer to?  If you mean
'http://decstation.unix-ag.org/', then that's notoriously out of date. 
But Karel does a pretty good job maintaining his site -- see
'http://www.xs4all.nl/~vhouten/mipsel/'. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

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From: "Siders, Keith" <keith_siders@toshibatv.com>
To: "Linux-Mips (E-mail)" <linux-mips@oss.sgi.com>
Subject: File permission handling
Date: Fri, 21 Jun 2002 11:22:05 -0500
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I am attempting to bunzip and untar a file in an embedded system. The
application invokes a system() call to launch bzcat piped to tar. tar is
reporting the filenames, but refuses to untar complaining about permissions
violations. How do I get the files to untar successfully? Script invocation
is "bzcat -xk %s | tar xf -" and a filename is supplied to the string
argument through sprintf(). What am I doing wrong here? 

BTW, for those who would throw up security warning flags, this is an
enclosed box where I don't have much worry about security issues revolviing
around forking a shell script.

Keith Siders
Software Engineer
 Toshiba America Consumer Products, Inc.
Advanced Television Technology Center
801 Royal Parkway, Suite 100
Nashville, Tennessee 37214
Phone: (615) 257-4050
Fax:   (615) 453-7880


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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: "Smith, Todd" <Todd.Smith@camc.org>
cc: "''linux-mips@oss.sgi.com' '" <linux-mips@oss.sgi.com>
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On Fri, 21 Jun 2002, Smith, Todd wrote:

> I was curious about the DECstation 5000/133 and a graphical console.

 The system should be fine -- basically all I/O ASIC based systems should
work, though not all devices have been supplied with drivers yet. 

 You should be able to use X11 with an XF86_FBDev Xserver on a PMAG-B (CX) 
or a PMAGB-B (HX) display adapter (I wasn't able to try myself so far
though).  For other display adapters, the answer is either "not yet" or
"no way". 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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On Fri, 2002-06-21 23:06:19 +0200, Maciej W. Rozycki <macro@ds2.pg.gda.pl>
wrote in message <Pine.GSO.3.96.1020621225833.2531B-100000@delta.ds2.pg.gda=
.pl>:
> On Fri, 21 Jun 2002, Smith, Todd wrote:
>  You should be able to use X11 with an XF86_FBDev Xserver on a PMAG-B (CX=
)=20
> or a PMAGB-B (HX) display adapter (I wasn't able to try myself so far
> though).  For other display adapters, the answer is either "not yet" or
> "no way".=20

I had X4 with framebuffer running on my DECstation with a PMAGB-B
framebuffer. However, seems there were some threading problems (which
might exist because the lack of ll/sc...).

However, graphic was functional, but I haven't switched on that box for
three months or so. I'm currently moving to an other city (well, quite a
smallish town)...

MfG, JBG

--=20
Jan-Benedict Glaw   .   jbglaw@lug-owl.de   .   +49-172-7608481
	 -- New APT-Proxy written in shell script --
	   http://lug-owl.de/~jbglaw/software/ap2/

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To: "Smith, Todd" <Todd.Smith@camc.org>
cc: "''linux-mips@oss.sgi.com' '" <linux-mips@oss.sgi.com>
Subject: RE: DECstation
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On Fri, 21 Jun 2002, Smith, Todd wrote:

> The http://decstation.unix-ag.org is the site that I was refering to.  The
> sother site that you mentioned, I get a 404 on it.

 Well, I've copied and pasted the URL as is from my web client.  You may
get to the page from 'http://decstation.unix-ag.org/people/' as well. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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Thank you for your information.  I was unsure since the website that I was
reading for information was very much out of date.

Keep up the good work!

Todd Smith

-----Original Message-----
From: Maciej W. Rozycki [mailto:macro@ds2.pg.gda.pl]

 The system should be fine -- basically all I/O ASIC based systems should
work, though not all devices have been supplied with drivers yet. 

 You should be able to use X11 with an XF86_FBDev Xserver on a PMAG-B (CX) 
or a PMAGB-B (HX) display adapter (I wasn't able to try myself so far
though).  For other display adapters, the answer is either "not yet" or
"no way". 

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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Jan-Benedict Glaw <jbglaw@lug-owl.de>
cc: "''linux-mips@oss.sgi.com' '" <linux-mips@oss.sgi.com>
Subject: Re: DECstation
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On Fri, 21 Jun 2002, Jan-Benedict Glaw wrote:

> I had X4 with framebuffer running on my DECstation with a PMAGB-B
> framebuffer. However, seems there were some threading problems (which
> might exist because the lack of ll/sc...).

 Either sysmips (ouch) or the emulation should handle them.  There may be
bugs, however...

> However, graphic was functional, but I haven't switched on that box for
> three months or so. I'm currently moving to an other city (well, quite a
> smallish town)...

 I'm on the way to getting appropriate monitor adapter cables, so I may
finally be able to access consoles.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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From: Karsten Merker <karsten@excalibur.cologne.de>
To: "Smith, Todd" <Todd.Smith@camc.org>
Cc: linux-mips@oss.sgi.com
Subject: Re: DECstation
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On Fri, Jun 21, 2002 at 11:06:19PM +0200, Maciej W. Rozycki wrote:
> On Fri, 21 Jun 2002, Smith, Todd wrote:
> 
> > I was curious about the DECstation 5000/133 and a graphical console.
> 
>  The system should be fine -- basically all I/O ASIC based systems should
> work, though not all devices have been supplied with drivers yet. 
> 
>  You should be able to use X11 with an XF86_FBDev Xserver on a PMAG-B (CX) 
> or a PMAGB-B (HX) display adapter (I wasn't able to try myself so far
> though).  For other display adapters, the answer is either "not yet" or
> "no way". 

Graphical console on PMAG-B and PMAGB-B works fine. 

X works in principle, too, i.e. you get graphical output and you can 
use the mouse (with the help of gpm's repeater mode), but the keyboard 
support within X is broken.

Regards,
Karsten
-- 
#include <standard_disclaimer>
Nach Paragraph 28 Abs. 3 Bundesdatenschutzgesetz widerspreche ich der Nutzung
oder Uebermittlung meiner Daten fuer Werbezwecke oder fuer die Markt- oder
Meinungsforschung.

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On Sat, 2002-06-22 00:46:04 +0200, Maciej W. Rozycki <macro@ds2.pg.gda.pl>
wrote in message <Pine.GSO.3.96.1020621231916.2531D-100000@delta.ds2.pg.gda=
.pl>:
> On Fri, 21 Jun 2002, Jan-Benedict Glaw wrote:

>  I'm on the way to getting appropriate monitor adapter cables, so I may
> finally be able to access consoles.

I've only got one DEC monitor cable (and I can't find it currently, I'm
moving...), but maybe I can ask around in a university nearby if there
are DECstations going their last way out, then I'll send you an original
cable...

MfG, JBG

--=20
Jan-Benedict Glaw   .   jbglaw@lug-owl.de   .   +49-172-7608481
	 -- New APT-Proxy written in shell script --
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From: Jan-Benedict Glaw <jbglaw@lug-owl.de>
To: linux-mips@oss.sgi.com
Subject: Re: DECstation
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On Sat, 2002-06-22 04:36:57 +0200, Karsten Merker <karsten@excalibur.cologn=
e.de>
wrote in message <20020622043657.B253@excalibur.cologne.de>:
> On Fri, Jun 21, 2002 at 11:06:19PM +0200, Maciej W. Rozycki wrote:
> > On Fri, 21 Jun 2002, Smith, Todd wrote:
> > > I was curious about the DECstation 5000/133 and a graphical console.

> X works in principle, too, i.e. you get graphical output and you can=20
> use the mouse (with the help of gpm's repeater mode), but the keyboard=20
> support within X is broken.

Well... Some keys are functional, some are not, and some are better to
never press... I've tried to understand how X handles the keyboard one
evening, but I badly failed to understand all those mappings and layouts
and so on:-(

MfG, JBG

--=20
Jan-Benedict Glaw   .   jbglaw@lug-owl.de   .   +49-172-7608481
	 -- New APT-Proxy written in shell script --
	   http://lug-owl.de/~jbglaw/software/ap2/

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From owner-linux-mips@oss.sgi.com Sat Jun 22 02:30:18 2002
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From: "Domcan Sami" <domca_psg@email.com>
To: <linux-mips@oss.sgi.com>, linux-kernel@vger.kernel.org
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Date: Sat, 22 Jun 2002 04:33:21 -0500
Subject: Linux Boot sequence on MIPS??
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Hello everybody
 I m trying to develop a Linux boot-loader for MIPS processor, can anybody help me sending the Linux boot sequence on MIPS. Any sites for reference? Thanks

Domcan
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From owner-linux-mips@oss.sgi.com Sun Jun 23 05:57:24 2002
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Date: Sun, 23 Jun 2002 14:58:11 +0200
From: Guido Guenther <agx@sigxcpu.org>
To: linux-mips@oss.sgi.com
Subject: 2.4.18: pgtable.h compile fix
Message-ID: <20020623125811.GA24851@bogon.ms20.nix>
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Hi,
I need the following to make head.S compile again for IP22 on the 
current linux_2_4 branch:

Index: include/asm-mips/pgtable.h
===================================================================
RCS file: /cvs/linux/include/asm-mips/pgtable.h,v
retrieving revision 1.63.2.12
diff -u -r1.63.2.12 pgtable.h
--- include/asm-mips/pgtable.h	2002/05/28 09:49:40	1.63.2.12
+++ include/asm-mips/pgtable.h	2002/06/23 12:48:50
@@ -13,6 +13,8 @@
 #include <asm/addrspace.h>
 #include <asm/page.h>
 
+#ifndef _LANGUAGE_ASSEMBLY
+
 #include <linux/linkage.h>
 #include <asm/cachectl.h>
 #include <asm/fixmap.h>
@@ -78,6 +80,7 @@
 extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
 			       unsigned long entryhi, unsigned long pagemask);
 
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 /* Basically we have the same two-level (which is the logical three level
  * Linux page table layout folded) page tables as the i386.  Some day
@@ -167,6 +170,8 @@
 #define __S110	PAGE_SHARED
 #define __S111	PAGE_SHARED
 
+#if !defined (_LANGUAGE_ASSEMBLY)
+
 #ifdef CONFIG_64BIT_PHYS_ADDR
 #define pte_ERROR(e) \
 	printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
@@ -472,6 +477,8 @@
 #define kern_addr_valid(addr)	(1)
 
 #include <asm-generic/pgtable.h>
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 /*
  * We provide our own get_unmapped area to cope with the virtual aliasing

Is there a reason why the "_LANGUAGE_ASSEMBLY" ifdefs were removed?
Mips64 still has these #ifdefs though.
Regards, 
 -- Guido

From owner-linux-mips@oss.sgi.com Mon Jun 24 00:15:36 2002
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Date: Mon, 24 Jun 2002 09:19:15 +0200 (MET DST)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Jan-Benedict Glaw <jbglaw@lug-owl.de>
cc: linux-mips@oss.sgi.com
Subject: Re: DECstation
In-Reply-To: <20020622080045.GT24903@lug-owl.de>
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On Sat, 22 Jun 2002, Jan-Benedict Glaw wrote:

> Well... Some keys are functional, some are not, and some are better to
> never press... I've tried to understand how X handles the keyboard one
> evening, but I badly failed to understand all those mappings and layouts
> and so on:-(

 A fix is on my to-do list -- hopefully to be done just after the current
task.  There is a long-standing bug in the generic keyboard handling code. 
After fixing it and then the LK driver (which cannot be fixed now because
of the bug), you'll be able to use LK mappings included in the X11
distribution.  It was discussed here earlier this year. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


From owner-linux-mips@oss.sgi.com Mon Jun 24 01:11:06 2002
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Date: Mon, 24 Jun 2002 10:11:23 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: Guido Guenther <agx@sigxcpu.org>
Cc: linux-mips@oss.sgi.com
Subject: Re: 2.4.18: pgtable.h compile fix
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On Sun, Jun 23, 2002 at 02:58:11PM +0200, Guido Guenther wrote:

> Hi,
> I need the following to make head.S compile again for IP22 on the 
> current linux_2_4 branch:

> Is there a reason why the "_LANGUAGE_ASSEMBLY" ifdefs were removed?
> Mips64 still has these #ifdefs though.

The necessity for these was believed to be removed.  What are you trying
to do when you run into this problem?

  Ralf

From owner-linux-mips@oss.sgi.com Mon Jun 24 01:26:45 2002
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Date: Mon, 24 Jun 2002 10:30:22 +0200 (MET DST)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Guido Guenther <agx@sigxcpu.org>
cc: linux-mips@oss.sgi.com
Subject: Re: 2.4.18: pgtable.h compile fix
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On Sun, 23 Jun 2002, Guido Guenther wrote:

> Is there a reason why the "_LANGUAGE_ASSEMBLY" ifdefs were removed?
> Mips64 still has these #ifdefs though.

 MIPS64 lags behind a bit due to less interest/testing.  Note that you
should use "__ASSEMBLY__" to guard assembly-unsafe parts of headers.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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Date: Mon, 24 Jun 2002 11:07:24 +0200
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@oss.sgi.com>, linux-mips@oss.sgi.com
Subject: sys_syscall patch.
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--------------58C8EEAD283815526023212C
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The 'sys_syscall' syscall isn't properly implemented in the 64-bit
kernel (for o32 as well as n64).
Below is a patch, it seems to work for in the o32 case, but I haven't
tested the n64 version (obviously).

/Carsten


--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
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--------------58C8EEAD283815526023212C
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Index: arch/mips64/kernel//linux32.c
===================================================================
RCS file: /home/repository/sw/linux-2.4.18/arch/mips64/kernel/linux32.c,v
retrieving revision 1.3
diff -u -r1.3 linux32.c
--- arch/mips64/kernel//linux32.c	13 Jun 2002 09:08:02 -0000	1.3
+++ arch/mips64/kernel//linux32.c	24 Jun 2002 08:56:02 -0000
@@ -32,6 +32,7 @@
 #include <asm/uaccess.h>
 #include <asm/mman.h>
 #include <asm/ipc.h>
+#include <asm/unistd.h>
 
 
 #define A(__x) ((unsigned long)(__x))
@@ -872,6 +873,82 @@
 		oldalarm++;
 
 	return oldalarm;
+}
+
+typedef asmlinkage long (*syscall_t)(void *a0,...);
+extern syscall_t sys32_call_table[];
+extern unsigned char sys32_narg_table[];
+
+/*
+ * Do the indirect syscall syscall.
+ * Don't care about kernel locking; the actual syscall will do it.
+ *
+ * XXX This is broken.
+ */
+asmlinkage int sys32_syscall(abi64_no_regargs, struct pt_regs regs)
+{
+	syscall_t syscall;
+	unsigned long syscallnr = regs.regs[4];
+	unsigned long a0, a1, a2, a3, a4, a5, a6;
+	int nargs, errno;
+
+	if ((syscallnr < __NR_Linux32) || 
+	    (syscallnr > __NR_Linux32 + __NR_Linux32_syscalls))
+		return -ENOSYS;
+
+	syscall = sys32_call_table[syscallnr-__NR_Linux32];
+	nargs = sys32_narg_table[syscallnr-__NR_Linux32];
+
+	/*
+	 * Prevent stack overflow by recursive
+	 * syscall(__NR_syscall, __NR_syscall,...);
+	 */
+	if (syscall == (syscall_t) sys32_syscall) {
+		return -EINVAL;
+	}
+
+	if (syscall == NULL) {
+		return -ENOSYS;
+	}
+
+	if(nargs > 3) {
+		unsigned long usp = regs.regs[29];
+		unsigned long *sp = (unsigned long *) usp;
+		if(usp & 3) {
+			printk("unaligned usp -EFAULT\n");
+			force_sig(SIGSEGV, current);
+			return -EFAULT;
+		}
+		errno = verify_area(VERIFY_READ, (void *) (usp + 16),
+		                    (nargs - 3) * sizeof(unsigned long));
+		if(errno) {
+			return -EFAULT;
+		}
+		switch(nargs) {
+		case 7:
+			a3 = sp[4]; a4 = sp[5]; a5 = sp[6]; a6 = sp[7];
+			break;
+		case 6:
+			a3 = sp[4]; a4 = sp[5]; a5 = sp[6]; a6 = 0;
+			break;
+		case 5:
+			a3 = sp[4]; a4 = sp[5]; a5 = a6 = 0;
+			break;
+		case 4:
+			a3 = sp[4]; a4 = a5 = a6 = 0;
+			break;
+
+		default:
+			a3 = a4 = a5 = a6 = 0;
+			break;
+		}
+	} else {
+		a3 = a4 = a5 = a6 = 0;
+	}
+	a0 = regs.regs[5]; a1 = regs.regs[6]; a2 = regs.regs[7];
+	if(nargs == 0)
+		a0 = (unsigned long) &regs;
+	return syscall((void *)a0, a1, a2, a3, a4, a5, a6);
 }
 
 /* Translations due to time_t size differences.  Which affects all
Index: arch/mips64/kernel//scall_64.S
===================================================================
RCS file: /home/repository/sw/linux-2.4.18/arch/mips64/kernel/scall_64.S,v
retrieving revision 1.3
diff -u -r1.3 scall_64.S
--- arch/mips64/kernel//scall_64.S	19 Jun 2002 07:04:08 -0000	1.3
+++ arch/mips64/kernel//scall_64.S	24 Jun 2002 08:10:23 -0000
@@ -132,7 +132,7 @@
 	j	ret_from_sys_call
 	END(handle_sys64)
 
-sys_call_table:
+EXPORT(sys_call_table)
 	PTR	sys_syscall				/* 5000 */
 	PTR	sys_exit
 	PTR	sys_fork
Index: arch/mips64/kernel//scall_o32.S
===================================================================
RCS file: /home/repository/sw/linux-2.4.18/arch/mips64/kernel/scall_o32.S,v
retrieving revision 1.3
diff -u -r1.3 scall_o32.S
--- arch/mips64/kernel//scall_o32.S	19 Jun 2002 07:04:08 -0000	1.3
+++ arch/mips64/kernel//scall_o32.S	24 Jun 2002 08:53:48 -0000
@@ -52,8 +52,8 @@
 
 	/* XXX Put both in one cacheline, should save a bit. */
 	dsll	t0, v0, 3		# offset into table
-	ld	t2, (sys_call_table - (__NR_Linux32 * 8))(t0) # syscall routine
-	lbu	t3, (sys_narg_table - __NR_Linux32)(v0)	# number of arguments
+	ld	t2, (sys32_call_table - (__NR_Linux32 * 8))(t0) # syscall routine
+	lbu	t3, (sys32_narg_table - __NR_Linux32)(v0)	# number of arguments
 
 	subu	t0, t3, 5		# 5 or more arguments?
 	sd	a3, PT_R26(sp)		# save a3 for syscall restarting
@@ -246,7 +246,7 @@
 	END(sys_sysmips)
 
 	.macro	syscalltable
-	sys	sys_syscall	0			/* 4000 */
+	sys	sys32_syscall	0			/* 4000 */
 	sys	sys_exit	1
 	sys	sys_fork	0
 	sys	sys_read	3
@@ -489,12 +489,12 @@
 	PTR	\function
 	.endm
 
-sys_call_table:
+EXPORT(sys32_call_table)
 	syscalltable
 
 	.macro	sys function, nargs
 	.byte	\nargs
 	.endm
-
-sys_narg_table:
+	
+EXPORT(sys32_narg_table)
 	syscalltable
Index: arch/mips64/kernel//syscall.c
===================================================================
RCS file: /home/repository/sw/linux-2.4.18/arch/mips64/kernel/syscall.c,v
retrieving revision 1.2
diff -u -r1.2 syscall.c
--- arch/mips64/kernel//syscall.c	13 Jun 2002 09:08:02 -0000	1.2
+++ arch/mips64/kernel//syscall.c	24 Jun 2002 08:38:55 -0000
@@ -123,14 +123,41 @@
 	return error;
 }
 
+typedef asmlinkage long (*syscall_t)(void *a0,...);
+extern syscall_t sys_call_table[];
+
 /*
  * Do the indirect syscall syscall.
- *
- * XXX This is borken.
+ * Don't care about kernel locking; the actual syscall will do it.
  */
 asmlinkage int sys_syscall(abi64_no_regargs, struct pt_regs regs)
 {
-	return -ENOSYS;
+	syscall_t syscall;
+	unsigned long syscallnr = regs.regs[4];
+	unsigned long a0, a1, a2, a3, a4, a5, a6;
+
+	if ((syscallnr < __NR_Linux) || 
+	    (syscallnr > __NR_Linux + __NR_Linux_syscalls))
+		return -ENOSYS;
+
+	syscall = sys_call_table[syscallnr-__NR_Linux];
+
+	/*
+	 * Prevent stack overflow by recursive
+	 * syscall(__NR_syscall, __NR_syscall,...);
+	 */
+	if (syscall == (syscall_t) sys_syscall) {
+		return -EINVAL;
+	}
+
+	if (syscall == NULL) {
+		return -ENOSYS;
+	}
+
+	a0 = regs.regs[5]; a1 = regs.regs[6]; a2 = regs.regs[7];
+	a3 = regs.regs[8]; a4 = regs.regs[9]; a5 = regs.regs[10];
+	a6 = regs.regs[11];
+	return syscall((void *)a0, a1, a2, a3, a4, a5, a6);
 }
 
 asmlinkage int

--------------58C8EEAD283815526023212C--


From owner-linux-mips@oss.sgi.com Mon Jun 24 02:54:35 2002
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Date: Mon, 24 Jun 2002 11:54:52 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: Carsten Langgaard <carstenl@mips.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: sys_syscall patch.
Message-ID: <20020624115452.A25138@dea.linux-mips.net>
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On Mon, Jun 24, 2002 at 11:07:24AM +0200, Carsten Langgaard wrote:

> The 'sys_syscall' syscall isn't properly implemented in the 64-bit
> kernel (for o32 as well as n64).
> Below is a patch, it seems to work for in the o32 case, but I haven't
> tested the n64 version (obviously).

> +/*
> + * Do the indirect syscall syscall.
> + * Don't care about kernel locking; the actual syscall will do it.
> + *
> + * XXX This is broken.
> + */

As the comment says - it's broken.  This implementation just like it's
32-bit predecessor don't handle the error return value correctly.  Worse,
there's unprotected accesses to userspace which allow any user crashing
the system ...

  Ralf

From owner-linux-mips@oss.sgi.com Mon Jun 24 03:03:49 2002
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Date: Mon, 24 Jun 2002 12:06:52 +0200
From: Carsten Langgaard <carstenl@mips.com>
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Ralf Baechle wrote:

> On Mon, Jun 24, 2002 at 11:07:24AM +0200, Carsten Langgaard wrote:
>
> > The 'sys_syscall' syscall isn't properly implemented in the 64-bit
> > kernel (for o32 as well as n64).
> > Below is a patch, it seems to work for in the o32 case, but I haven't
> > tested the n64 version (obviously).
>
> > +/*
> > + * Do the indirect syscall syscall.
> > + * Don't care about kernel locking; the actual syscall will do it.
> > + *
> > + * XXX This is broken.
> > + */
>
> As the comment says - it's broken.  This implementation just like it's
> 32-bit predecessor don't handle the error return value correctly.  Worse,
> there's unprotected accesses to userspace which allow any user crashing
> the system ...
>

At least it makes my system work as well as for the 32-bit kernel.



--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




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Date: Mon, 24 Jun 2002 12:24:50 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: Carsten Langgaard <carstenl@mips.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: sys_syscall patch.
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On Mon, Jun 24, 2002 at 12:06:52PM +0200, Carsten Langgaard wrote:

> 
> At least it makes my system work as well as for the 32-bit kernel.

What programs btw are using syscall()?  To be honest I don't recall one ...

Looking more into it I found a nice showstopper - a few functions like
_sys_sigsuspend() expect a struct pt_regs on the stack.  That's only
working if we call those functions directly from the exception handler.
It won't work if we have another function's stackframe - in this case
sys_syscall()'s there also ...

  Ralf

From owner-linux-mips@oss.sgi.com Mon Jun 24 03:43:39 2002
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Subject: Re: sys_syscall patch.
References: <3D16E14C.5C8D2FAD@mips.com> <20020624115452.A25138@dea.linux-mips.net> <3D16EF3C.BCCB020@mips.com> <20020624122450.A25659@dea.linux-mips.net>
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Ralf Baechle wrote:

> On Mon, Jun 24, 2002 at 12:06:52PM +0200, Carsten Langgaard wrote:
>
> >
> > At least it makes my system work as well as for the 32-bit kernel.
>
> What programs btw are using syscall()?  To be honest I don't recall one ...

/sbin/rpc.lockd.
It use syscall() to indirectly call the 'sys_nfsservctl' syscall, why it
doesn't do the syscall directly is beyond me.


>
> Looking more into it I found a nice showstopper - a few functions like
> _sys_sigsuspend() expect a struct pt_regs on the stack.  That's only
> working if we call those functions directly from the exception handler.
> It won't work if we have another function's stackframe - in this case
> sys_syscall()'s there also ...
>
>   Ralf

--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com




From owner-linux-mips@oss.sgi.com Mon Jun 24 04:34:48 2002
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	Mon, 24 Jun 2002 13:38:27 +0200 (MET DST)
Date: Mon, 24 Jun 2002 13:38:27 +0200 (MET DST)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Carsten Langgaard <carstenl@mips.com>
cc: Ralf Baechle <ralf@oss.sgi.com>, linux-mips@oss.sgi.com
Subject: Re: sys_syscall patch.
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On Mon, 24 Jun 2002, Carsten Langgaard wrote:

> > What programs btw are using syscall()?  To be honest I don't recall one ...
> 
> /sbin/rpc.lockd.
> It use syscall() to indirectly call the 'sys_nfsservctl' syscall, why it
> doesn't do the syscall directly is beyond me.

 Hmm, shouldn't syscall() be a library wrapper?  I think we should kill
sys_syscall(). 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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From: Ralf Baechle <ralf@oss.sgi.com>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Cc: Carsten Langgaard <carstenl@mips.com>, linux-mips@oss.sgi.com
Subject: Re: sys_syscall patch.
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On Mon, Jun 24, 2002 at 01:38:27PM +0200, Maciej W. Rozycki wrote:

> > > What programs btw are using syscall()?  To be honest I don't recall one ...
> > 
> > /sbin/rpc.lockd.
> > It use syscall() to indirectly call the 'sys_nfsservctl' syscall, why it
> > doesn't do the syscall directly is beyond me.
> 
>  Hmm, shouldn't syscall() be a library wrapper?  I think we should kill
> sys_syscall(). 

It's in the kernel for no better reason than Risc/OS and IRIX having this
syscall.  Also the glibc syscall implementation was historically broken
wrt. syscall restarting and a few other subtilities.

  Ralf

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From: "Kevin D. Kissell" <kevink@mips.com>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
   "Carsten Langgaard" <carstenl@mips.com>
Cc: "Ralf Baechle" <ralf@oss.sgi.com>, <linux-mips@oss.sgi.com>
References: <Pine.GSO.3.96.1020624133501.22509K-100000@delta.ds2.pg.gda.pl>
Subject: Re: sys_syscall patch.
Date: Mon, 24 Jun 2002 14:02:49 +0200
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
> On Mon, 24 Jun 2002, Carsten Langgaard wrote:
> 
> > > What programs btw are using syscall()?  To be honest I don't recall one ...
> > 
> > /sbin/rpc.lockd.
> > It use syscall() to indirectly call the 'sys_nfsservctl' syscall, why it
> > doesn't do the syscall directly is beyond me.

I can only speculate that at the time it was written, there was not
a universally respected library binding to get to the direct syscall.

>  Hmm, shouldn't syscall() be a library wrapper?  I think we should kill
> sys_syscall(). 

While I agree that rpc.lockd should directly invoke the desired
system call if possible, having an indirect system call mechanism
is something that has proved useful to me in the past on other
Unices, and I would rather see it fixed than discarded.

            Kevin K.

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From: Ralf Baechle <ralf@oss.sgi.com>
To: Carsten Langgaard <carstenl@mips.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: sys_syscall patch.
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On Mon, Jun 24, 2002 at 12:46:41PM +0200, Carsten Langgaard wrote:

> > > At least it makes my system work as well as for the 32-bit kernel.
> >
> > What programs btw are using syscall()?  To be honest I don't recall one ...
> 
> /sbin/rpc.lockd.
> It use syscall() to indirectly call the 'sys_nfsservctl' syscall, why it
> doesn't do the syscall directly is beyond me.

More historic garbage - the kernel NFS server for a long time didn't
have it's own, registered syscall.

  Ralf

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Date: Mon, 24 Jun 2002 14:04:03 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>,
   Carsten Langgaard <carstenl@mips.com>, linux-mips@oss.sgi.com
Subject: Re: sys_syscall patch.
Message-ID: <20020624140403.B28145@dea.linux-mips.net>
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On Mon, Jun 24, 2002 at 02:02:49PM +0200, Kevin D. Kissell wrote:

> While I agree that rpc.lockd should directly invoke the desired
> system call if possible, having an indirect system call mechanism
> is something that has proved useful to me in the past on other
> Unices, and I would rather see it fixed than discarded.

The question is not wheather to drop this mechnism - we can't anyway for
compatibility reasons - but if a kernel or userspace implementation is
preferable for the future.

  Ralf

From owner-linux-mips@oss.sgi.com Mon Jun 24 06:00:44 2002
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Message-ID: <A4E787A2467EF849B00585F14C900559068906@dprn03.deltartp.com>
From: Chien-Lung Wu <cwu@deltartp.com>
To: "'linux-mips@oss.sgi.com'" <linux-mips@oss.sgi.com>
Cc: Chien-Lung Wu <cwu@deltartp.com>
Subject: cross-compiler
Date: Mon, 24 Jun 2002 08:54:00 -0400
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Hi,
I try to buils a cross-comipler in my linux box (build=i386-mips) with
host=windowNT, and target=linux-mips. But it is not successful.

I use the following tar-ball as base: (The newest one)
	a. binutils (2.11.2)
	b. gcc 3.1
	c. glibc 2.2.5

As a newbie in linux embedded system, could anyone kindly show me "HOWTO"
build up a cross-compiler in general and specifically for MIPS (IDT
R32334/32332)?

If you know any good stuffs in building cross-compiler and porting Linux to
MIPS, please send me the web-side or pointers. Thanks in advance.

Regards,

Chien-Lung

***********************************************************************
Chien-Lung Wu                                 TEL: 919-767-3903
Sr. Software Engineer                        FAX: 919-767-2458
DataCom Lab of Delta Network Inc..    e-mail: cwu@deltartp.com
***********************************************************




From owner-linux-mips@oss.sgi.com Mon Jun 24 06:20:40 2002
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Date: Mon, 24 Jun 2002 21:22:15 +0800
From: "Zhang Fuxin" <fxzhang@ict.ac.cn>
To: Ralf Baechle <ralf@oss.sgi.com>
CC: "linux-mips@oss.sgi.com" <linux-mips@oss.sgi.com>
Subject: Re: Re: sys_syscall patch.
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hi,

======= 2002-06-24 12:24:00 you wrote£º=======

>On Mon, Jun 24, 2002 at 12:06:52PM +0200, Carsten Langgaard wrote:
>
>> 
>> At least it makes my system work as well as for the 32-bit kernel.
>
>What programs btw are using syscall()?  To be honest I don't recall one ...
I used it in a userland checkpoint program to intercept syscalls.
>
>Looking more into it I found a nice showstopper - a few functions like
>_sys_sigsuspend() expect a struct pt_regs on the stack.  That's only
>working if we call those functions directly from the exception handler.
>It won't work if we have another function's stackframe - in this case
>sys_syscall()'s there also ...
>
>  Ralf

= = = = = = = = = = = = = = = = = = = =
			

Best Regards
---------------------------------------
Zhang Fuxin
System Architecture Lab
Institute of Computing Technology
Chinese Academy of Sciences,China
http://www.ict.ac.cn
 
			¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2002-06-24





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 section
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Hi,

I get the above error from gdb 5.2 when using the <file> command.
...
(gdb) file iprbs
file iprbs
Reading symbols from iprbs...DW_FORM_strp pointing outside of .debug_str section
(gdb)                                                       
...

My mipsel-linux- toolchain consist of the following packages:
	binutils-2.12.1
	gcc-3.1
	glibc-2.2.5
	gdb-5.2

I have no idea what the problem might be.

Any hints (solutions/workaround) are welcome.

Best regards,
	Carsten
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From owner-linux-mips@oss.sgi.com Mon Jun 24 07:14:24 2002
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Message-ID: <3D1729F3.7241A74A@mips.com>
Date: Mon, 24 Jun 2002 16:17:23 +0200
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@oss.sgi.com>,
   "linux-mips@oss.sgi.com" <linux-mips@oss.sgi.com>
Subject: Bug in __copy_user
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I have started to look a little bit at the LTP tests.
And one of the testcases that fails (actually it doesn't fail as it
supposed to do) is the syscall getsockopt.
I think the failure is due to the copy_to_user(0, from, 4) call returns
0, which I wouldn't expect when the destination pointer is NULL.

I think the problem is in the __copy_user function in
arch/mips/lib/memcpy.
It tries to handle the exception, which we get because the destination
pointer is NULL, by returning the number of uncopied bytes in $a2 to the
caller.
But in this case the length is only 4 bytes, and the copying is done by
a single 'sw'. The problem is the length ($a2) is decreased by 4 before
the 'sw' is executed.
The 'sw' fails and __copy_user terminates, but returns with $a2 = 0
(instead 4).

I thing the following patch will solve the problem.

/Carsten



--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



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Index: arch/mips/lib/memcpy.S
===================================================================
RCS file: /home/repository/sw/linux-2.4.18/arch/mips/lib/memcpy.S,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 memcpy.S
--- arch/mips/lib/memcpy.S	4 Mar 2002 11:12:21 -0000	1.1.1.1
+++ arch/mips/lib/memcpy.S	24 Jun 2002 13:46:07 -0000
@@ -248,8 +248,8 @@
 1:
 EXC(	LOAD	 t0, 0(src),		l_exc)
 	ADD	src, src, NBYTES
-	SUB	len, len, NBYTES
 EXC(	STORE	t0, 0(dst),		s_exc)
+	SUB	len, len, NBYTES
 	bne	rem, len, 1b
 	 ADD	dst, dst, NBYTES
 

--------------4EBBDD03DDAA4619AEF963D7--


From owner-linux-mips@oss.sgi.com Mon Jun 24 07:25:22 2002
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Date: Mon, 24 Jun 2002 16:28:29 +0200
From: Johannes Stezenbach <js@convergence.de>
To: Chien-Lung Wu <cwu@deltartp.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: cross-compiler
Message-ID: <20020624142829.GA4015@convergence.de>
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	Chien-Lung Wu <cwu@deltartp.com>, linux-mips@oss.sgi.com
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Chien-Lung Wu wrote:
> I use the following tar-ball as base: (The newest one)
> 	a. binutils (2.11.2)
> 	b. gcc 3.1
> 	c. glibc 2.2.5
> 
> As a newbie in linux embedded system, could anyone kindly show me "HOWTO"
> build up a cross-compiler in general and specifically for MIPS (IDT
> R32334/32332)?
> 
> If you know any good stuffs in building cross-compiler and porting Linux to
> MIPS, please send me the web-side or pointers. Thanks in advance.

http://linux-mips.sourceforge.net/
http://www.junsun.net/linux/porting-howto/

HTH,
Johannes

From owner-linux-mips@oss.sgi.com Mon Jun 24 07:45:21 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Ralf Baechle <ralf@oss.sgi.com>
cc: Carsten Langgaard <carstenl@mips.com>, linux-mips@oss.sgi.com
Subject: Re: sys_syscall patch.
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On Mon, 24 Jun 2002, Ralf Baechle wrote:

> It's in the kernel for no better reason than Risc/OS and IRIX having this
> syscall.  Also the glibc syscall implementation was historically broken
> wrt. syscall restarting and a few other subtilities.

 Well, userland implementations for other archs seem quite
straightforward.  So should be ours -- we only have to shuffle arguments
appropriately.  Restarting is easy -- we just have to make sure to reload
v0 just before "syscall" reliably (we can use a static register or an
automatic variable to preserve it).  What are the few other subtleties?

 Also I can't see an implementation of syscall() for MIPS/Linux anywhere
in glibc.  What implementation do you refer to?  The Mach one?

 The win is we don't have to mess with user accesses specially -- the
final syscall will handle them. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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Date: Mon, 24 Jun 2002 11:00:01 -0400
From: Daniel Jacobowitz <dan@debian.org>
To: Carsten Lange <Carsten.Lange@detewe.de>
Cc: "'linux-mips@oss.sgi.com'" <linux-mips@oss.sgi.com>
Subject: Re: mipsel-linux-gdb(5.2): DW_FORM_strp pointing outside of .debug_str section
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On Mon, Jun 24, 2002 at 03:29:47PM +0200, Carsten Lange wrote:
> Hi,
> 
> I get the above error from gdb 5.2 when using the <file> command.
> ...
> (gdb) file iprbs
> file iprbs
> Reading symbols from iprbs...DW_FORM_strp pointing outside of .debug_str section
> (gdb)                                                       
> ...
> 
> My mipsel-linux- toolchain consist of the following packages:
> 	binutils-2.12.1
> 	gcc-3.1
> 	glibc-2.2.5
> 	gdb-5.2
> 
> I have no idea what the problem might be.
> 
> Any hints (solutions/workaround) are welcome.

Can you produce a testcase?  These versions of the tools should not
show the problem, assuming you rebuilt everything using them.

-- 
Daniel Jacobowitz                           Carnegie Mellon University
MontaVista Software                         Debian GNU/Linux Developer

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From: "H. J. Lu" <hjl@lucon.org>
To: Daniel Jacobowitz <dan@debian.org>
Cc: Carsten Lange <Carsten.Lange@detewe.de>,
   "'linux-mips@oss.sgi.com'" <linux-mips@oss.sgi.com>
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On Mon, Jun 24, 2002 at 11:00:01AM -0400, Daniel Jacobowitz wrote:
> On Mon, Jun 24, 2002 at 03:29:47PM +0200, Carsten Lange wrote:
> > Hi,
> > 
> > I get the above error from gdb 5.2 when using the <file> command.
> > ...
> > (gdb) file iprbs
> > file iprbs
> > Reading symbols from iprbs...DW_FORM_strp pointing outside of .debug_str section
> > (gdb)                                                       
> > ...
> > 
> > My mipsel-linux- toolchain consist of the following packages:
> > 	binutils-2.12.1
> > 	gcc-3.1
> > 	glibc-2.2.5
> > 	gdb-5.2
> > 
> > I have no idea what the problem might be.
> > 
> > Any hints (solutions/workaround) are welcome.
> 
> Can you produce a testcase?  These versions of the tools should not
> show the problem, assuming you rebuilt everything using them.
> 

Please get the Linux binutils 2.12.90.0.12. You need that for gcc 3.1
on Linux/mips.


H.J.

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Date: Mon, 24 Jun 2002 15:33:30 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Cc: Guido Guenther <agx@sigxcpu.org>, linux-mips@oss.sgi.com
Subject: Re: 2.4.18: pgtable.h compile fix
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On Mon, Jun 24, 2002 at 10:30:22AM +0200, Maciej W. Rozycki wrote:

>  MIPS64 lags behind a bit due to less interest/testing.  Note that you
> should use "__ASSEMBLY__" to guard assembly-unsafe parts of headers.

_LANGUAGE_ASSEMBLY is the traditional MIPS cpp symbol to indicate assembler
source code.

  Ralf

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Date: Mon, 24 Jun 2002 19:14:51 +0400
From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Organization: NIISI RAN
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Carsten Langgaard wrote:
> 
> I have started to look a little bit at the LTP tests.
> And one of the testcases that fails (actually it doesn't fail as it
> supposed to do) is the syscall getsockopt.
> I think the failure is due to the copy_to_user(0, from, 4) call returns
> 0, which I wouldn't expect when the destination pointer is NULL.
> 
> I think the problem is in the __copy_user function in
> arch/mips/lib/memcpy.
> It tries to handle the exception, which we get because the destination
> pointer is NULL, by returning the number of uncopied bytes in $a2 to the
> caller.
> But in this case the length is only 4 bytes, and the copying is done by
> a single 'sw'. The problem is the length ($a2) is decreased by 4 before
> the 'sw' is executed.
> The 'sw' fails and __copy_user terminates, but returns with $a2 = 0
> (instead 4).
> 
> I thing the following patch will solve the problem.

Been here, done that. In fact, I posted the following patch few days ago
to the list:
less_than_4units:
        /*
         * rem = len % NBYTES
         */
        beq     rem, len, copy_bytes
         nop
1:
EXC(    LOAD     t0, 0(src),            l_exc)
        ADD     src, src, NBYTES
        SUB     len, len, NBYTES
-EXC(    STORE   t0, 0(dst),             s_exc)
+EXC(    STORE   t0, 0(dst),             s_exc_p1u)
        bne     rem, len, 1b
         ADD    dst, dst, NBYTES

This patch also solves the problem for mips in 2.4/2.5 kernel. My
question was about the patch for mips64 and mips in 2.2 kernel.

Shall memcpy.S from 2.4/2.5 be backported to 2.2 and mips64?

Regards,
Gleb.

From owner-linux-mips@oss.sgi.com Mon Jun 24 08:40:52 2002
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Date: Mon, 24 Jun 2002 17:39:55 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Cc: Carsten Langgaard <carstenl@mips.com>,
   "linux-mips@oss.sgi.com" <linux-mips@oss.sgi.com>
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Gleb,

On Mon, Jun 24, 2002 at 07:14:51PM +0400, Gleb O. Raiko wrote:

> This patch also solves the problem for mips in 2.4/2.5 kernel. My
> question was about the patch for mips64 and mips in 2.2 kernel.
> 
> Shall memcpy.S from 2.4/2.5 be backported to 2.2 and mips64?

I think that would be the prefered solution as it'll be easier to maintain.

I've not received any 2.2 patches in a very long, long time - anybody
actually still using it?

  Ralf

From owner-linux-mips@oss.sgi.com Mon Jun 24 08:50:48 2002
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From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Ralf Baechle <ralf@oss.sgi.com>
cc: Guido Guenther <agx@sigxcpu.org>, linux-mips@oss.sgi.com
Subject: Re: 2.4.18: pgtable.h compile fix
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On Mon, 24 Jun 2002, Ralf Baechle wrote:

> >  MIPS64 lags behind a bit due to less interest/testing.  Note that you
> > should use "__ASSEMBLY__" to guard assembly-unsafe parts of headers.
> 
> _LANGUAGE_ASSEMBLY is the traditional MIPS cpp symbol to indicate assembler
> source code.

 Well, but the rest of the kernel uses "__ASSEMBLY__", that's defined in
the top-level Makefile.  What's the point in being different? 

 Also it doesn't seem to work for me -- the rules in specs look broken:

$ mipsel-linux-gcc -E -dM -xassembler-with-cpp /dev/null | grep LANGUAGE
#define __LANGUAGE_C 1
#define _LANGUAGE_C 1
#define LANGUAGE_C 1

thus it cannot be considered reliable.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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Subject: Re: Bug in __copy_user
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Ralf Baechle wrote:
> 
> Gleb,
> 
> On Mon, Jun 24, 2002 at 07:14:51PM +0400, Gleb O. Raiko wrote:
> 
> > This patch also solves the problem for mips in 2.4/2.5 kernel. My
> > question was about the patch for mips64 and mips in 2.2 kernel.
> >
> > Shall memcpy.S from 2.4/2.5 be backported to 2.2 and mips64?
> 
> I think that would be the prefered solution as it'll be easier to maintain.
> 
> I've not received any 2.2 patches in a very long, long time - anybody
> actually still using it?

Yes, I am still using 2.2. Considering pathes, I've got patches for r3k,
which doesn't work with a standard 2.2 kernel. But those patches are
backports from 2.4. So, I don't think they shall be applied. From other
hand, I don't plan develop 'normal' patches for 2.2.

Regards,
Gleb.

From owner-linux-mips@oss.sgi.com Mon Jun 24 09:04:00 2002
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Message-ID: <019401c21b99$387ce290$10eca8c0@grendel>
From: "Kevin D. Kissell" <kevink@mips.com>
To: "Ralf Baechle" <ralf@oss.sgi.com>, "Gleb O. Raiko" <raiko@niisi.msk.ru>
Cc: "Carsten Langgaard" <carstenl@mips.com>, <linux-mips@oss.sgi.com>
References: <3D1729F3.7241A74A@mips.com> <3D17376B.59333E27@niisi.msk.ru> <20020624173954.A1109@dea.linux-mips.net>
Subject: Re: Bug in __copy_user
Date: Mon, 24 Jun 2002 18:07:18 +0200
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From: "Ralf Baechle" <ralf@oss.sgi.com> 
> On Mon, Jun 24, 2002 at 07:14:51PM +0400, Gleb O. Raiko wrote:
> 
> > This patch also solves the problem for mips in 2.4/2.5 kernel. My
> > question was about the patch for mips64 and mips in 2.2 kernel.
> > 
> > Shall memcpy.S from 2.4/2.5 be backported to 2.2 and mips64?
> 
> I think that would be the prefered solution as it'll be easier to maintain.
> 
> I've not received any 2.2 patches in a very long, long time - anybody
> actually still using it?

Only a few thousand (or tens of thousands) of Sony Playstation 2
users.  ;-)  Most of them are running the wierd 2.2.1.?? Sony
branch, but there are a few poor deluded souls tryng to update
to 2.2.20...

            Kevin K.


From owner-linux-mips@oss.sgi.com Mon Jun 24 09:22:12 2002
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Date: Mon, 24 Jun 2002 18:22:35 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: "Gleb O. Raiko" <raiko@niisi.msk.ru>,
   Carsten Langgaard <carstenl@mips.com>, linux-mips@oss.sgi.com
Subject: Re: Bug in __copy_user
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On Mon, Jun 24, 2002 at 06:07:18PM +0200, Kevin D. Kissell wrote:

> Only a few thousand (or tens of thousands) of Sony Playstation 2
> users.  ;-)  Most of them are running the wierd 2.2.1.?? Sony
> branch, but there are a few poor deluded souls tryng to update
> to 2.2.20...

Just in time when the Linux world has already mostly abandoned 2.2 ...

  Ralf

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From: "Kevin D. Kissell" <kevink@mips.com>
To: "Ralf Baechle" <ralf@oss.sgi.com>
Cc: "Gleb O. Raiko" <raiko@niisi.msk.ru>,
   "Carsten Langgaard" <carstenl@mips.com>, <linux-mips@oss.sgi.com>
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Subject: Re: Bug in __copy_user
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From: "Ralf Baechle" <ralf@oss.sgi.com>
> On Mon, Jun 24, 2002 at 06:07:18PM +0200, Kevin D. Kissell wrote:
> 
> > Only a few thousand (or tens of thousands) of Sony Playstation 2
> > users.  ;-)  Most of them are running the wierd 2.2.1.?? Sony
> > branch, but there are a few poor deluded souls tryng to update
> > to 2.2.20...
> 
> Just in time when the Linux world has already mostly abandoned 2.2 ...

Well, like I said last week, we need to get the PS2 onto 2.4 ASAP,
for a whole bunch of reasons...

            Kevin K.

From owner-linux-mips@oss.sgi.com Mon Jun 24 10:28:13 2002
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Date: Mon, 24 Jun 2002 10:31:16 -0700
From: Justin Wojdacki <justin.wojdacki@analog.com>
Reply-To: justin.wojdacki@analog.com
Organization: Analog Devices, Communications Processors Group
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To: Domcan Sami <domca_psg@email.com>
CC: linux-mips@oss.sgi.com, linux-kernel@vger.kernel.org,
   redhat-list@redhat.com
Subject: Re: Linux Boot sequence on MIPS??
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Domcan Sami wrote:
> 
> Hello everybody
>  I m trying to develop a Linux boot-loader for MIPS processor, can
> anybody help me sending the Linux boot sequence on MIPS. Any sites for
> reference? Thanks
> 

Where do you expect to load the kernel from? And what CPU/Board? 

The basic process is to POST the board, load the kernel into SDRAM,
and run the kernel. Where you want to load the kernel from determines
the other initialization work you need to do. 

Alternately, have you looked at PMON? It may provide everything you
need for a MIPS-based system. 

-- 
-------------------------------------------------
Justin Wojdacki        
justin.wojdacki@analog.com         (408) 350-5032
Communications Processors Group -- Analog Devices

From owner-linux-mips@oss.sgi.com Mon Jun 24 12:48:07 2002
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From: "M. R. Brown" <mrbrown@0xd6.org>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: Ralf Baechle <ralf@oss.sgi.com>, "Gleb O. Raiko" <raiko@niisi.msk.ru>,
   Carsten Langgaard <carstenl@mips.com>, linux-mips@oss.sgi.com
Subject: Re: Bug in __copy_user
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* Kevin D. Kissell <kevink@mips.com> on Mon, Jun 24, 2002:

> From: "Ralf Baechle" <ralf@oss.sgi.com>
> > On Mon, Jun 24, 2002 at 06:07:18PM +0200, Kevin D. Kissell wrote:
> >=20
> > > Only a few thousand (or tens of thousands) of Sony Playstation 2
> > > users.  ;-)  Most of them are running the wierd 2.2.1.?? Sony
> > > branch, but there are a few poor deluded souls tryng to update
> > > to 2.2.20...
> >=20
> > Just in time when the Linux world has already mostly abandoned 2.2 ...
>=20
> Well, like I said last week, we need to get the PS2 onto 2.4 ASAP,
> for a whole bunch of reasons...
>=20

ps2hacking.sourceforge.net - broken port of Sony's 2.2.1 kernel to 2.4.8
(or so).

M. R.

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From owner-linux-mips@oss.sgi.com Mon Jun 24 17:38:02 2002
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Date: Tue, 25 Jun 2002 02:36:34 +0200
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Cc: linux-mips@oss.sgi.com
Subject: Re: DBE/IBE handling incompatibility
Message-ID: <20020625003634.GA1917@kopretinka>
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On Wed, Jun 19, 2002 at 06:47:05PM +0200, Maciej W. Rozycki wrote:
>  Don't rely in dbe_board_handler and ibe_board_handler -- they are
> system-specific backends that shouldn't be touched unless you want to
> handle the exceptions in a system-specific way (e.g. to report ECC errors
> from a memory controller).

MC sends an interrupt whenever bus or parity errors occur. In addition, if the
error happened during a CPU read, it also asserts the bus error pin on the R4K.
so once one access nonexistent memory on Indy first DBE is generated followed
by Bus Error interupt (IRQ 6). When GIO status register is cleared inside DBE
handler, irq is not delivered.

> Also expect the handlers to get rewritten so that search_dbe_table() gets 
> invoked unconditionally, before a system-specific backend.

i don't want to use these handlers, i'd like to write it mips64 way.

> Use get_dbe() from <asm/paccess.h> for reading data with an additional
> DBE status.  For a simple example see drivers/mtd/devices/ms02-nv.c.  The
> macro is used in a somewhat more complex way in drivers/tc/tc.c as well --
> this bit of code fits your situation quite closely (here probing
> TURBOchannel bus slots).  The macro works in modules as well.

that does't work. i used folowing pseudocode:

my_get_dbe()
  nofault = 1;
  ret = get_dbe(*val, (unsigned int *) addr);
  __asm__ __volatile__("nop;nop;nop;nop");
  nofault = 0;
	
my_do_buserr()
  save_and_clear_buserr();
  if (nofault) {
    nofault = 0;
    return;
  }
  panic();

when calling my_get_dbe for nonexistent address it enters my_do_buserr
and returns "somewhere" causing machine to freeze. calling
save_and_clear_buserr() from board specific DBE handler works as
expected. is there better solution or i missed anything important?

thanks,
	ladis

From owner-linux-mips@oss.sgi.com Tue Jun 25 00:12:33 2002
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Message-ID: <3D181898.837E864A@mips.com>
Date: Tue, 25 Jun 2002 09:15:36 +0200
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@oss.sgi.com>,
   "linux-mips@oss.sgi.com" <linux-mips@oss.sgi.com>
Subject: LTP testing
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The next LTP failure is:
mprotect01    1  FAIL  :  unexpected error - 14 : Bad address - expected
12

This has been fixed in the 2.4.19-pre4 patch.
But here is a local patch that solve the above problem, so we can have
this fixed before we have merged with kernel.org.

/Carsten


--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



--------------AFB792D746638736CFC1E76F
Content-Type: text/plain; charset=iso-8859-15;
 name="mprotect.patch"
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 filename="mprotect.patch"

Index: mm/mprotect.c
===================================================================
RCS file: /home/repository/sw/linux-2.4.18/mm/mprotect.c,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 mprotect.c
--- mm/mprotect.c	4 Mar 2002 11:13:35 -0000	1.1.1.1
+++ mm/mprotect.c	25 Jun 2002 07:00:55 -0000
@@ -284,7 +284,7 @@
 	down_write(&current->mm->mmap_sem);
 
 	vma = find_vma_prev(current->mm, start, &prev);
-	error = -EFAULT;
+	error = -ENOMEM;
 	if (!vma || vma->vm_start > start)
 		goto out;
 
@@ -317,7 +317,7 @@
 		nstart = tmp;
 		vma = next;
 		if (!vma || vma->vm_start != nstart) {
-			error = -EFAULT;
+			error = -ENOMEM;
 			goto out;
 		}
 	}

--------------AFB792D746638736CFC1E76F--


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Date: Tue, 25 Jun 2002 10:54:36 +0200
From: Ralf Baechle <ralf@oss.sgi.com>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Cc: Guido Guenther <agx@sigxcpu.org>, linux-mips@oss.sgi.com
Subject: Re: 2.4.18: pgtable.h compile fix
Message-ID: <20020625105436.A16439@dea.linux-mips.net>
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In-Reply-To: <Pine.GSO.3.96.1020624174346.22509N-100000@delta.ds2.pg.gda.pl>; from macro@ds2.pg.gda.pl on Mon, Jun 24, 2002 at 05:54:28PM +0200
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On Mon, Jun 24, 2002 at 05:54:28PM +0200, Maciej W. Rozycki wrote:

> > >  MIPS64 lags behind a bit due to less interest/testing.  Note that you
> > > should use "__ASSEMBLY__" to guard assembly-unsafe parts of headers.
> > 
> > _LANGUAGE_ASSEMBLY is the traditional MIPS cpp symbol to indicate assembler
> > source code.
> 
>  Well, but the rest of the kernel uses "__ASSEMBLY__", that's defined in
> the top-level Makefile.  What's the point in being different? 
> 
>  Also it doesn't seem to work for me -- the rules in specs look broken:
> 
> $ mipsel-linux-gcc -E -dM -xassembler-with-cpp /dev/null | grep LANGUAGE
> #define __LANGUAGE_C 1
> #define _LANGUAGE_C 1
> #define LANGUAGE_C 1
> 
> thus it cannot be considered reliable.

The machanism guesses the language based on the source file name extension:

[ralf@dea tmp]$ echo -n > c.c && mips-linux-gcc -E -dM -xassembler-with-cpp c.c | grep LANG
#define __LANGUAGE_C 1 
#define _LANGUAGE_C 1 
#define LANGUAGE_C 1 
[ralf@dea tmp]$ echo -n > c.S && mips-linux-gcc -E -dM c.S | grep LANG
#define LANGUAGE_ASSEMBLY 1 
#define _LANGUAGE_ASSEMBLY 1 
#define __LANGUAGE_ASSEMBLY 1 
[ralf@dea tmp]$

Buggy?  Yes ...

  Ralf

From owner-linux-mips@oss.sgi.com Tue Jun 25 02:56:13 2002
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Date: Tue, 25 Jun 2002 11:59:14 +0200
From: Carsten Langgaard <carstenl@mips.com>
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To: Ralf Baechle <ralf@oss.sgi.com>,
   "linux-mips@oss.sgi.com" <linux-mips@oss.sgi.com>
Subject: LTP testing
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The LTP test fails with:
msgctl01    1  FAIL  :  qs_buf.msg_qbytes did not change
msgctl02    1  FAIL  :  qs_buf.msg_qbytes value is not expected
msgsnd01    1  FAIL  :  queue bytes != MSGSIZE
msgsnd01    2  FAIL  :  queue message != 1

All the above failures is fixed by the attached patch.
The msgbuf.h file is now a copy from i386, instead of alpha.
I guess the fix goes for 64-bit kernel as well.

/Carsten



--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



--------------A57255ACE7E444374521FB17
Content-Type: text/plain; charset=iso-8859-15;
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Index: include/asm-mips/msgbuf.h
===================================================================
RCS file: /home/repository/sw/linux-2.4.18/include/asm-mips/msgbuf.h,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 msgbuf.h
--- include/asm-mips/msgbuf.h	4 Mar 2002 11:13:24 -0000	1.1.1.1
+++ include/asm-mips/msgbuf.h	25 Jun 2002 09:30:03 -0000
@@ -2,26 +2,30 @@
 #define _ASM_MSGBUF_H
 
 /* 
- * The msqid64_ds structure for alpha architecture.
+ * The msqid64_ds structure for i386 architecture.
  * Note extra padding because this structure is passed back and forth
  * between kernel and user space.
  *
  * Pad space is left for:
- * - 2 miscellaneous 64-bit values
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
  */
 
 struct msqid64_ds {
 	struct ipc64_perm msg_perm;
 	__kernel_time_t msg_stime;	/* last msgsnd time */
+	unsigned long	__unused1;
 	__kernel_time_t msg_rtime;	/* last msgrcv time */
+	unsigned long	__unused2;
 	__kernel_time_t msg_ctime;	/* last change time */
+	unsigned long	__unused3;
 	unsigned long  msg_cbytes;	/* current number of bytes on queue */
 	unsigned long  msg_qnum;	/* number of messages in queue */
 	unsigned long  msg_qbytes;	/* max number of bytes on queue */
 	__kernel_pid_t msg_lspid;	/* pid of last msgsnd */
 	__kernel_pid_t msg_lrpid;	/* last receive pid */
-	unsigned long  __unused1;
-	unsigned long  __unused2;
+	unsigned long  __unused4;
+	unsigned long  __unused5;
 };
 
 #endif /* _ASM_MSGBUF_H */

--------------A57255ACE7E444374521FB17--


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Date: Tue, 25 Jun 2002 12:47:54 +0200
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To: Ralf Baechle <ralf@oss.sgi.com>,
   "linux-mips@oss.sgi.com" <linux-mips@oss.sgi.com>
Subject: LTP testing
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The next LTP failure is:
msync05     1  FAIL  :  msync() fails, unexpected errno:14, expected:
ENOMEM

This has also been fixed in the 2.4.19-pre4 patch.
See the attached patch below.

/Carsten



--
_    _ ____  ___   Carsten Langgaard   Mailto:carstenl@mips.com
|\  /|||___)(___   MIPS Denmark        Direct: +45 4486 5527
| \/ |||    ____)  Lautrupvang 4B      Switch: +45 4486 5555
  TECHNOLOGIES     2750 Ballerup       Fax...: +45 4486 5556
                   Denmark             http://www.mips.com



--------------B685E88831FE5634C4CE0DD0
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 name="filemap.patch"
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 filename="filemap.patch"

Index: mm/filemap.c
===================================================================
RCS file: /home/repository/sw/linux-2.4.18/mm/filemap.c,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 filemap.c
--- mm/filemap.c	4 Mar 2002 11:13:34 -0000	1.1.1.1
+++ mm/filemap.c	25 Jun 2002 10:36:12 -0000
@@ -2179,18 +2179,18 @@
 		goto out;
 	/*
 	 * If the interval [start,end) covers some unmapped address ranges,
-	 * just ignore them, but return -EFAULT at the end.
+	 * just ignore them, but return -ENOMEM at the end.
 	 */
 	vma = find_vma(current->mm, start);
 	unmapped_error = 0;
 	for (;;) {
 		/* Still start < end. */
-		error = -EFAULT;
+		error = -ENOMEM;
 		if (!vma)
 			goto out;
 		/* Here start < vma->vm_end. */
 		if (start < vma->vm_start) {
-			unmapped_error = -EFAULT;
+			unmapped_error = -ENOMEM;
 			start = vma->vm_start;
 		}
 		/* Here vma->vm_start <= start < vma->vm_end. */

--------------B685E88831FE5634C4CE0DD0--


From owner-linux-mips@oss.sgi.com Tue Jun 25 04:04:54 2002
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   "'linux-mips@oss.sgi.com'" <linux-mips@oss.sgi.com>
Subject: Re: mipsel-linux-gdb(5.2): DW_FORM_strp pointing outside of .debug_str 
 section
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Hi,

when I use binutils 2.12.90.0.12 gcc 3.1 will not compile anymore.

The error is:

...
mkdir libgcc
if [ -f stmp-dirs ]; then true; else touch stmp-dirs; fi
/opt/cross/production/build/gcc/gcc/xgcc -B/opt/cross/production/build/gcc/gcc/
-B/opt/cross/mipsel-linux/mipsel-linux/bin/ -B/opt/cross/mipsel-linux/mipsel-linux/lib/ -isystem
/opt/cross/mipsel-linux/mipsel-linux/include -O2  -DIN_GCC -DCROSS_COMPILE   -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -isystem ./include  -fPIC -g  -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -Dinhibit_libc -I. -I. -I/opt/cross/production/src/gcc-3.1/gcc
-I/opt/cross/production/src/gcc-3.1/gcc/. -I/opt/cross/production/src/gcc-3.1/gcc/config
-I/opt/cross/production/src/gcc-3.1/gcc/../include  -DL_muldi3 -c
/opt/cross/production/src/gcc-3.1/gcc/libgcc2.c -o libgcc/./_muldi3.o
/tmp/ccPEIznf.s: Assembler messages:
/tmp/ccPEIznf.s:5: Error: file number 1 already allocated
make[2]: *** [libgcc/./_muldi3.o] Error 1
make[2]: Leaving directory `/opt/cross/production/build/gcc/gcc'
make[1]: *** [libgcc.a] Error 2
make[1]: Leaving directory `/opt/cross/production/build/gcc/gcc'
make: *** [all-gcc] Error 2                                  
...

Building the toolchain works fine with binutils-2.12.1.

I attach 2 files (the build_mips_toolchain and mipsel-linux.source) which I use to build the tools
from scratch on my linux i586 box.
Any program build with this toolchain cannot be opened with gdb. 

What are the recommended versions of gcc, glibc and gdb?

Many thanks 
	Carsten



"H. J. Lu" wrote:
> 
> On Mon, Jun 24, 2002 at 11:00:01AM -0400, Daniel Jacobowitz wrote:
> > On Mon, Jun 24, 2002 at 03:29:47PM +0200, Carsten Lange wrote:
> > > Hi,
> > >
> > > I get the above error from gdb 5.2 when using the <file> command.
> > > ...
> > > (gdb) file iprbs
> > > file iprbs
> > > Reading symbols from iprbs...DW_FORM_strp pointing outside of .debug_str section
> > > (gdb)
> > > ...
> > >
> > > My mipsel-linux- toolchain consist of the following packages:
> > >     binutils-2.12.1
> > >     gcc-3.1
> > >     glibc-2.2.5
> > >     gdb-5.2
> > >
> > > I have no idea what the problem might be.
> > >
> > > Any hints (solutions/workaround) are welcome.
> >
> > Can you produce a testcase?  These versions of the tools should not
> > show the problem, assuming you rebuilt everything using them.
> >
> 
> Please get the Linux binutils 2.12.90.0.12. You need that for gcc 3.1
> on Linux/mips.
> 
> H.J.
--------------4E8576234784E74CD2CBC2A8
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#!/bin/sh

if [ "x$1" == "x" ]
then
echo "usage: $0 <file_to_get_config_from>"
exit 1
fi
 
if [ -f ${1}.source ]
then
. ${1}.source
else
echo "usage: $0 <file_to_get_config_from>"
exit 1
fi           


execute()
{
        echo "+++++++++++++++++++++++++++ $@ "
        echo "+++++++++++++++++++++++++++ $@ " >> $LOGFILE 2>&1
        $@ >> $LOGFILE 2>&1
        if [ ! $? = 0 ]
        then
                echo "$@ FAILED!"
                exit 1
	fi
}

execute_patch()
{
        echo "+ patch $1 -s < $2"
        if [ -f $2 ]
        then
                pkgpatch $1 -s < $2
                if [ ! $? = 0 ]
                then
                        echo "patch $1 -s < $2 FAILED!"
                        exit 1
                fi
        else
                echo "Patchfile $2 not found!"
                exit 1
        fi
}

#cleanup
execute rm -rf $BUILD
execute mkdir -p $BUILD
execute rm -rf $SRC
execute mkdir -p $SRC


#
#
# BINUTILS

if [ ! -f ${PREFIX}/binutils-${BINUTILS_V} ] ; then
execute cd $SRC
#execute tar xzf $PKG/binutils-${BINUTILS_V}.tar.gz
execute tar xjf $PKG/binutils-${BINUTILS_V}.tar.bz2
execute cd $BUILD
execute mkdir binutils
execute cd binutils
execute $SRC/binutils-${BINUTILS_V}/configure \
			--target=${TARGET} \
			--prefix=${PREFIX}
execute make
execute make install
execute rm -rf $SRC/binutils-${BINUTILS_V}
execute rm -rf $BUILD/binutils
execute touch ${PREFIX}/binutils-${BINUTILS_V}
fi
#
#
# INCLUDE FILES
#execute rm -rf ${PREFIX}/target
#execute mkdir -p ${PREFIX}/target/include

#execute cd /opt/cross/devel/ip_rbs/linux/include
#execute tar cf /tmp/${TARGET}_include . 
#execute cd ${PREFIX}/target/usr/include
#execute tar xf /tmp/${TARGET}_include

#execute ln -sf /opt/cross/devel/ip_rbs/linux/include/asm ${PREFIX}/target/include/asm
#execute ln -sf /opt/cross/devel/ip_rbs/linux/include/linux ${PREFIX}/target/include/linux

# GCC
if [ ! -f ${PREFIX}/gcc-${GCC_V}_step1 ]  ; then
execute cd $SRC
execute tar xzf $PKG/gcc-${GCC_V}.tar.gz
execute cd $BUILD
execute mkdir gcc
execute cd gcc
execute $SRC/gcc-${GCC_V}/configure \
			--target=${TARGET} \
			--prefix=${PREFIX} \
			--enable-languages=c \
			--disable-shared \
			--with-newlib \
			--with-headers=${HEADERS}
execute make
execute make install
execute touch ${PREFIX}/gcc-${GCC_V}_step1
fi
#
#
# GLIBC
if [ ! -f ${PREFIX}/glibc-${GLIBC_V} ]  ; then
execute cd $SRC
execute tar xzf $PKG/glibc-${GLIBC_V}.tar.gz
execute cd glibc-${GLIBC_V}
execute tar xzf $PKG/glibc-linuxthreads-${GLIBC_V}.tar.gz
execute cd $BUILD
execute mkdir glibc
execute cd glibc
execute $SRC/glibc-${GLIBC_V}/configure  \
			--build=i686-linux \
			--host=${TARGET} \
			--enable-add-ons \
			--disable-sanity-checks \
			--prefix=${PREFIX}/${TARGTET}
execute make
execute make install
execute touch ${PREFIX}/glibc-${GLIBC_V}
fi

#
#
# GCC again
if [ ! -f ${PREFIX}/gcc-${GCC_V} ] ; then
execute cd $BUILD
execute cd gcc
execute $SRC/gcc-${GCC_V}/configure \
			--target=${TARGET} \
			--prefix=${PREFIX} \
			--enable-languages=c,c++ \
			--with-libs=${PREFIX}/${TARGTET}/lib \
			--with-headers=${HEADERS}
execute make
execute make install
execute touch ${PREFIX}/gcc-${GCC_V}
fi




#
#
# GDB
if [ ! -f ${PREFIX}/gdb-${GDB_V} ] ; then
execute cd $SRC
execute execute tar xzf $PKG/gdb-${GDB_V}.tar.gz 
execute cd $BUILD
execute mkdir -p gdb
execute cd gdb
execute $SRC/gdb-${GDB_V}/configure \
                        --target=${TARGET} \
                        --prefix=${PREFIX}
execute make
execute make install 
execute touch ${PREFIX}/gdb-${GDB_V}
fi



#
#
# GDB SERVER
if [ ! -f ${PREFIX}/gdbserver-${GDB_V} ] ; then
execute mkdir -p $BUILD/gdbserver
execute cd $BUILD
execute cd gdbserver
execute chmod u+x $SRC/gdb-${GDB_V}/gdb/gdbserver/configure
export CC=mipsel-linux-gcc
execute $SRC/gdb-${GDB_V}/gdb/gdbserver/configure \
                        --target=${TARGET} \
                        --prefix=${PREFIX}
execute make
execute make install 
execute touch ${PREFIX}/gdbserver-${GDB_V}
fi



execute echo "############ DONE ############"

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# TARGET
TARGET=mipsel-linux
HEADERS=/opt/cross/devel/ip_rbs/linux/include

# VERSIONS

#BINUTILS_V="2.12.90.0.12"
BINUTILS_V="2.12.1"
GCC_V="3.1"
GLIBC_V="2.2.5"

INSIGHT_V="5.1.1"
GDB_V="5.2"

DDD_V="3.3.1"

# CONFIGURATION

CROSSROOT=/opt/cross
BASEDIR=$CROSSROOT/production

PREFIX=$CROSSROOT/${TARGET}

BUILD=$BASEDIR/build
SRC=$BASEDIR/src
PKG=$BASEDIR/pkg
LOGDIR=$BASEDIR/log
LOGFILE=$LOGDIR/${0}_`date +%d%m%Y`_`date +%H%M`.log

# PATH
PATH="$PREFIX/bin:$HOSTPREFIX/bin:$PATH"
export PATH    


echo "LOGFILE is ${LOGFILE}"

--------------4E8576234784E74CD2CBC2A8
Content-Type: text/x-vcard; charset=us-ascii;
 name="Carsten.Lange.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Carsten Lange
Content-Disposition: attachment;
 filename="Carsten.Lange.vcf"

begin:vcard 
n:Lange;Carsten
tel;fax:+49 6104 4234
tel;work:+49 30 6104 4228
x-mozilla-html:FALSE
url:http://www.detewe.de
org:Cordless Technology A/S Berlin
adr:;;Koepenicker Str. 180;10997 Berlin;;;
version:2.1
email;internet:Carsten.Lange@detewe.de
x-mozilla-cpt:;0
fn:Carsten Lange
end:vcard

--------------4E8576234784E74CD2CBC2A8--


From owner-linux-mips@oss.sgi.com Tue Jun 25 04:51:55 2002
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Date: Tue, 25 Jun 2002 13:55:22 +0200 (MET DST)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Ladislav Michl <ladis@psi.cz>, Ralf Baechle <ralf@uni-koblenz.de>
cc: linux-mips@oss.sgi.com
Subject: Re: DBE/IBE handling incompatibility
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On Tue, 25 Jun 2002, Ladislav Michl wrote:

> >  Don't rely in dbe_board_handler and ibe_board_handler -- they are
> > system-specific backends that shouldn't be touched unless you want to
> > handle the exceptions in a system-specific way (e.g. to report ECC errors
> > from a memory controller).
> 
> MC sends an interrupt whenever bus or parity errors occur. In addition, if the
> error happened during a CPU read, it also asserts the bus error pin on the R4K.
> so once one access nonexistent memory on Indy first DBE is generated followed
> by Bus Error interupt (IRQ 6). When GIO status register is cleared inside DBE
> handler, irq is not delivered.

 So you want both a system-specific DBE handler and a DBE detection in a
driver, right?

> > Also expect the handlers to get rewritten so that search_dbe_table() gets 
> > invoked unconditionally, before a system-specific backend.
> 
> i don't want to use these handlers, i'd like to write it mips64 way.

 The MIPS way is the right one and I'll fix MIPS64 as soon as I get it
fixed much enough to boot into the single-user mode on my system.  They
have to be identical, because there are drivers that work both on MIPS and
MIPS64 and expect consistent semantics. 

 A cleanup hook will be provided to let system-specific code do whatever
is needed to discard saved DBE state regardless -- I didn't add it so far
as I haven't managed to get at it yet. 

> > Use get_dbe() from <asm/paccess.h> for reading data with an additional
> > DBE status.  For a simple example see drivers/mtd/devices/ms02-nv.c.  The
> > macro is used in a somewhat more complex way in drivers/tc/tc.c as well --
> > this bit of code fits your situation quite closely (here probing
> > TURBOchannel bus slots).  The macro works in modules as well.
> 
> that does't work. i used folowing pseudocode:
> 
> my_get_dbe()
>   nofault = 1;
>   ret = get_dbe(*val, (unsigned int *) addr);
>   __asm__ __volatile__("nop;nop;nop;nop");
>   nofault = 0;
> 	
> my_do_buserr()
>   save_and_clear_buserr();
>   if (nofault) {
>     nofault = 0;
>     return;
>   }
>   panic();
> 
> when calling my_get_dbe for nonexistent address it enters my_do_buserr
> and returns "somewhere" causing machine to freeze. calling
> save_and_clear_buserr() from board specific DBE handler works as
> expected. is there better solution or i missed anything important?

 Well, that's not the right approach -- you are trying to work around the
current MIPS64 brokenness.  The handler for DBE and IBE in
arch/mips*/kernel/traps.c is intended to look more or less as follows: 

asmlinkage void do_be(struct pt_regs *regs)
{
	unsigned long new_epc;
	unsigned long fixup = 0;
	int data = regs->cp0_cause & 4;

	if (data && !user_mode(regs))
		fixup = search_dbe_table(regs->cp0_epc);

	if (be_board_handler)
		fixup = be_board_handler(regs, fixup);

	if (fixup) {
		new_epc = fix