From macro@ds2.pg.gda.pl Fri Jul 5 17:21:21 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id RAA15606; Fri, 5 Jul 2002 17:21:21 +0200 (MET DST) Received-Date: Fri, 5 Jul 2002 17:21:21 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd015604; Fri Jul 5 17:21:12 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g65FKkM02518 for ; Fri, 5 Jul 2002 17:20:49 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id RAA12700; Fri, 5 Jul 2002 17:21:35 +0200 (MET DST) Date: Fri, 5 Jul 2002 17:21:34 +0200 (MET DST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: [patch] linux: Cache coherency fixes Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Ralf, Following is a fix for the currently broken TLB cache coherency attributes setup. Of R4[04]00 processors only the MC versions support cache coherency. Looking at the current setup I infer SB1 is another CPU that supports it -- for any other CPU, the patch will have to be updated. Then it's only relevant for SMP setups. My R4400SC locks up solid (and I mean it, even NMI doesn't work) when a write back of a line marked as CACHABLE_COW is to happen. Somebody's laziness costed me a week of debugging, sigh... :-( OK to apply? Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + patch-mips-2.4.19-rc1-20020705-cache-coherency-2 diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020705.macro/arch/mips/config.in linux-mips-2.4.19-rc1-20020705/arch/mips/config.in --- linux-mips-2.4.19-rc1-20020705.macro/arch/mips/config.in 2002-06-27 02:57:13.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020705/arch/mips/config.in 2002-07-05 14:58:52.000000000 +0000 @@ -393,6 +393,19 @@ else fi fi fi + +if [ "$CONFIG_CPU_R4X00" = "y" -o "$CONFIG_CPU_SB1" = "y" ]; then + define_bool CONFIG_CPU_CACHE_COHERENCY $CONFIG_SMP +else + define_bool CONFIG_CPU_CACHE_COHERENCY n +fi + +if [ "$CONFIG_VTAG_ICACHE" != "y" ]; then + define_bool CONFIG_VTAG_ICACHE n +fi +if [ "$CONFIG_CPU_HAS_PREFETCH" != "y" ]; then + define_bool CONFIG_CPU_HAS_PREFETCH n +fi endmenu mainmenu_option next_comment diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020705.macro/arch/mips64/config.in linux-mips-2.4.19-rc1-20020705/arch/mips64/config.in --- linux-mips-2.4.19-rc1-20020705.macro/arch/mips64/config.in 2002-06-27 02:57:26.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020705/arch/mips64/config.in 2002-07-05 14:59:16.000000000 +0000 @@ -126,7 +126,6 @@ choice 'CPU type' \ R8000 CONFIG_CPU_R8000 \ R10000 CONFIG_CPU_R10000 \ SB1 CONFIG_CPU_SB1" R4x00 -endmenu if [ "$CONFIG_CPU_SB1" = "y" ]; then bool ' Workarounds for pass 1 sb1 bugs' CONFIG_SB1_PASS_1_WORKAROUNDS @@ -137,6 +136,20 @@ fi define_bool CONFIG_CPU_HAS_LLSC y define_bool CONFIG_CPU_HAS_LLDSCD y +if [ "$CONFIG_CPU_R4X00" = "y" -o "$CONFIG_CPU_SB1" = "y" ]; then + define_bool CONFIG_CPU_CACHE_COHERENCY $CONFIG_SMP +else + define_bool CONFIG_CPU_CACHE_COHERENCY n +fi + +if [ "$CONFIG_VTAG_ICACHE" != "y" ]; then + define_bool CONFIG_VTAG_ICACHE n +fi +if [ "$CONFIG_CPU_HAS_PREFETCH" != "y" ]; then + define_bool CONFIG_CPU_HAS_PREFETCH n +fi +endmenu + mainmenu_option next_comment comment 'General setup' diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020705.macro/include/asm-mips/pgtable-bits.h linux-mips-2.4.19-rc1-20020705/include/asm-mips/pgtable-bits.h --- linux-mips-2.4.19-rc1-20020705.macro/include/asm-mips/pgtable-bits.h 2002-04-15 07:50:23.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020705/include/asm-mips/pgtable-bits.h 2002-07-05 14:52:59.000000000 +0000 @@ -74,9 +74,9 @@ #define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ #define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ #define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00 only */ -#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00 only */ -#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00 only */ +#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ #define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ #endif @@ -87,12 +87,20 @@ #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) -#ifdef CONFIG_MIPS_UNCACHED + +#if defined(CONFIG_MIPS_UNCACHED) + #define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED -#elif CONFIG_CPU_SB1 + +#elif defined(CONFIG_CPU_CACHE_COHERENCY) + #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW + #else + #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT + #endif + #endif /* _ASM_CACHINGMODES_H */ diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020705.macro/include/asm-mips64/pgtable.h linux-mips-2.4.19-rc1-20020705/include/asm-mips64/pgtable.h --- linux-mips-2.4.19-rc1-20020705.macro/include/asm-mips64/pgtable.h 2002-07-03 02:58:29.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020705/include/asm-mips64/pgtable.h 2002-07-05 14:52:59.000000000 +0000 @@ -191,9 +191,9 @@ extern void (*_flush_icache_page)(struct #define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ #define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ #define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00 only */ -#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00 only */ -#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00 only */ +#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ #define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ #define _CACHE_MASK (7<<9) @@ -202,15 +202,21 @@ extern void (*_flush_icache_page)(struct #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) -#ifdef CONFIG_MIPS_UNCACHED -#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED -#else /* ! UNCACHED */ -#ifdef CONFIG_SGI_IP22 -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT -#else /* ! IP22 */ -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW -#endif /* IP22 */ -#endif /* UNCACHED */ + +#if defined(CONFIG_MIPS_UNCACHED) + +#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED + +#elif defined(CONFIG_CPU_CACHE_COHERENCY) + +#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW + +#else + +#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT + +#endif + #define PAGE_NONE __pgprot(_PAGE_PRESENT | PAGE_CACHABLE_DEFAULT) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ From macro@ds2.pg.gda.pl Thu Jul 25 02:25:06 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id CAA25600; Thu, 25 Jul 2002 02:25:06 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 02:25:06 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpdb20017; Thu Jul 25 02:24:59 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6NBsjM17362 for ; Tue, 23 Jul 2002 13:54:46 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id NAA26838; Tue, 23 Jul 2002 13:55:14 +0200 (MET DST) Date: Tue, 23 Jul 2002 13:55:13 +0200 (MET DST) From: "Maciej W. Rozycki" Reply-To: "Maciej W. Rozycki" To: linux-mips@fnet.fr, linux-mips@oss.sgi.com, Ralf Baechle Subject: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Hello, There is no need to carry support for pure 32-bit CPUs around in cpu_probe() in arch/mips64/kernel/setup.c, since such CPUs are not supported by the port and likely won't ever reach that code due to a reserved instruction exception earlier. The code is misleading and a possible cause of troubles, e.g. the 2.4 branch doesn't link now because of an unresolved reference to cpu_has_fpu() which is only needed for R2000/R3000. The following patch removes the code for 2.4. For the trunk cpu_has_fpu() would be removed as well. Any objections? Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + patch-mips-2.4.19-rc1-20020719-mips64-cpu-2 diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips64/kernel/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips64/kernel/setup.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips64/kernel/setup.c 2002-07-15 02:57:48.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips64/kernel/setup.c 2002-07-22 23:44:00.000000000 +0000 @@ -123,16 +123,6 @@ static inline void check_wait(void) { printk("Checking for 'wait' instruction... "); switch(mips_cpu.cputype) { - case CPU_R3081: - case CPU_R3081E: - cpu_wait = r3081_wait; - printk(" available.\n"); - break; - case CPU_TX3927: - case CPU_TX39XX: - cpu_wait = r39xx_wait; - printk(" available.\n"); - break; case CPU_R4200: /* case CPU_R4300: */ case CPU_R4600: @@ -143,9 +133,6 @@ static inline void check_wait(void) case CPU_NEVADA: case CPU_RM7000: case CPU_TX49XX: - case CPU_4KC: - case CPU_4KEC: - case CPU_4KSC: case CPU_5KC: /* case CPU_20KC:*/ cpu_wait = r4k_wait; @@ -163,28 +150,6 @@ void __init check_bugs(void) } /* - * Probe whether cpu has config register by trying to play with - * alternate cache bit and see whether it matters. - * It's used by cpu_probe to distinguish between R3000A and R3081. - */ -static inline int cpu_has_confreg(void) -{ -#ifdef CONFIG_CPU_R3000 - extern unsigned long r3k_cache_size(unsigned long); - unsigned long size1, size2; - unsigned long cfg = read_32bit_cp0_register(CP0_CONF); - - size1 = r3k_cache_size(ST0_ISC); - write_32bit_cp0_register(CP0_CONF, cfg^CONF_AC); - size2 = r3k_cache_size(ST0_ISC); - write_32bit_cp0_register(CP0_CONF, cfg); - return size1 != size2; -#else - return 0; -#endif -} - -/* * Get the FPU Implementation/Revision. */ static inline unsigned long cpu_get_fpu_id(void) @@ -235,28 +200,6 @@ static inline void cpu_probe(void) switch (mips_cpu.processor_id & 0xff0000) { case PRID_COMP_LEGACY: switch (mips_cpu.processor_id & 0xff00) { - case PRID_IMP_R2000: - mips_cpu.cputype = CPU_R2000; - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; - if (cpu_has_fpu()) - mips_cpu.options |= MIPS_CPU_FPU; - mips_cpu.tlbsize = 64; - break; - case PRID_IMP_R3000: - if ((mips_cpu.processor_id & 0xff) == PRID_REV_R3000A) - if (cpu_has_confreg()) - mips_cpu.cputype = CPU_R3081E; - else - mips_cpu.cputype = CPU_R3000A; - else - mips_cpu.cputype = CPU_R3000; - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; - if (cpu_has_fpu()) - mips_cpu.options |= MIPS_CPU_FPU; - mips_cpu.tlbsize = 64; - break; case PRID_IMP_R4000: if ((mips_cpu.processor_id & 0xff) == PRID_REV_R4400) mips_cpu.cputype = CPU_R4400SC; @@ -329,32 +272,6 @@ static inline void cpu_probe(void) mips_cpu.tlbsize = 48; break; #endif - case PRID_IMP_TX39: - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB; - - if ((mips_cpu.processor_id & 0xf0) == - (PRID_REV_TX3927 & 0xf0)) { - mips_cpu.cputype = CPU_TX3927; - mips_cpu.tlbsize = 64; - mips_cpu.icache.ways = 2; - mips_cpu.dcache.ways = 2; - } else { - switch (mips_cpu.processor_id & 0xff) { - case PRID_REV_TX3912: - mips_cpu.cputype = CPU_TX3912; - mips_cpu.tlbsize = 32; - break; - case PRID_REV_TX3922: - mips_cpu.cputype = CPU_TX3922; - mips_cpu.tlbsize = 64; - break; - default: - mips_cpu.cputype = CPU_UNKNOWN; - break; - } - } - break; case PRID_IMP_R4700: mips_cpu.cputype = CPU_R4700; mips_cpu.isa_level = MIPS_CPU_ISA_III; @@ -401,18 +318,6 @@ static inline void cpu_probe(void) mips_cpu.icache.ways = 2; mips_cpu.dcache.ways = 2; break; - case PRID_IMP_R6000: - mips_cpu.cputype = CPU_R6000; - mips_cpu.isa_level = MIPS_CPU_ISA_II; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU; - mips_cpu.tlbsize = 32; - break; - case PRID_IMP_R6000A: - mips_cpu.cputype = CPU_R6000A; - mips_cpu.isa_level = MIPS_CPU_ISA_II; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU; - mips_cpu.tlbsize = 32; - break; case PRID_IMP_RM7000: mips_cpu.cputype = CPU_RM7000; mips_cpu.isa_level = MIPS_CPU_ISA_IV; @@ -459,15 +364,6 @@ static inline void cpu_probe(void) #ifdef CONFIG_CPU_MIPS32 case PRID_COMP_MIPS: switch (mips_cpu.processor_id & 0xff00) { - case PRID_IMP_4KC: - mips_cpu.cputype = CPU_4KC; - break; - case PRID_IMP_4KEC: - mips_cpu.cputype = CPU_4KEC; - break; - case PRID_IMP_4KSC: - mips_cpu.cputype = CPU_4KSC; - break; case PRID_IMP_5KC: mips_cpu.cputype = CPU_5KC; mips_cpu.isa_level = MIPS_CPU_ISA_M64; @@ -481,20 +377,6 @@ static inline void cpu_probe(void) break; } break; - case PRID_COMP_ALCHEMY: - switch (mips_cpu.processor_id & 0xff00) { - case PRID_IMP_AU1_REV1: - case PRID_IMP_AU1_REV2: - if (mips_cpu.processor_id & 0xff000000) - mips_cpu.cputype = CPU_AU1500; - else - mips_cpu.cputype = CPU_AU1000; - break; - default: - mips_cpu.cputype = CPU_UNKNOWN; - break; - } - break; #endif /* CONFIG_CPU_MIPS32 */ case PRID_COMP_SIBYTE: switch (mips_cpu.processor_id & 0xff00) { @@ -793,18 +675,6 @@ void __init setup_arch(char **cmdline_p) paging_init(); } -void r3081_wait(void) -{ - unsigned long cfg = read_32bit_cp0_register(CP0_CONF); - write_32bit_cp0_register(CP0_CONF, cfg|CONF_HALT); -} - -void r39xx_wait(void) -{ - unsigned long cfg = read_32bit_cp0_register(CP0_CONF); - write_32bit_cp0_register(CP0_CONF, cfg|TX39_CONF_HALT); -} - void r4k_wait(void) { __asm__(".set\tmips3\n\t" From ralf@linux-mips.net Thu Jul 25 02:18:05 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id CAA23248; Thu, 25 Jul 2002 02:18:05 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 02:18:05 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd020017; Thu Jul 25 02:17:55 2002 Received: from dea.linux-mips.net (shaft17-f249.dialo.tiscali.de [62.246.17.249]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6NCE9M17412 for ; Tue, 23 Jul 2002 14:14:10 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6NCE7b10917; Tue, 23 Jul 2002 14:14:07 +0200 Date: Tue, 23 Jul 2002 14:14:07 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 Message-ID: <20020723141407.B10566@dea.linux-mips.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: ; from macro@ds2.pg.gda.pl on Tue, Jul 23, 2002 at 01:55:13PM +0200 X-Accept-Language: de,en,fr On Tue, Jul 23, 2002 at 01:55:13PM +0200, Maciej W. Rozycki wrote: > There is no need to carry support for pure 32-bit CPUs around in > cpu_probe() in arch/mips64/kernel/setup.c, since such CPUs are not > supported by the port and likely won't ever reach that code due to a > reserved instruction exception earlier. The code is misleading and a > possible cause of troubles, e.g. the 2.4 branch doesn't link now because > of an unresolved reference to cpu_has_fpu() which is only needed for > R2000/R3000. > > The following patch removes the code for 2.4. For the trunk > cpu_has_fpu() would be removed as well. Any objections? I intentionally have that 32-bit stuff in the 64-bit kernel so we can simply have share identical CPU probing code between the 32-bit and 64-bit kernels. This in anticipation of a further unification of the two ports which still duplicate plenty of code with just minor changes. To make sharing easier I suggest to move all the CPU probing code into it's own file, probe.c or so? Ralf From macro@ds2.pg.gda.pl Thu Jul 25 02:06:37 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id CAA19015; Thu, 25 Jul 2002 02:06:37 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 02:06:37 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpde09995; Thu Jul 25 02:06:25 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6ND5DM17549 for ; Tue, 23 Jul 2002 15:05:13 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id PAA28389; Tue, 23 Jul 2002 15:05:48 +0200 (MET DST) Date: Tue, 23 Jul 2002 15:05:47 +0200 (MET DST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 In-Reply-To: <20020723141407.B10566@dea.linux-mips.net> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On Tue, 23 Jul 2002, Ralf Baechle wrote: > I intentionally have that 32-bit stuff in the 64-bit kernel so we can simply > have share identical CPU probing code between the 32-bit and 64-bit kernels. > This in anticipation of a further unification of the two ports which still > duplicate plenty of code with just minor changes. I suspected a maintability reason. Thus as a temporary fix I'm checking in a version that provides the missing cpu_has_fpu() function (a copy from the trunk). > To make sharing easier I suggest to move all the CPU probing code into it's > own file, probe.c or so? That might be a good idea in principle, but it won't solve the problem anyway. I'd like to see the code for 32-bit processors get annihilated by the compiler if built for mips64. I'll look at it soon. The MIPS32/64 crap needs to be fixed here as well. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From ralf@linux-mips.net Thu Jul 25 02:06:37 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id CAA19008; Thu, 25 Jul 2002 02:06:37 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 02:06:37 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpda09995; Thu Jul 25 02:06:30 2002 Received: from dea.linux-mips.net (shaft17-f249.dialo.tiscali.de [62.246.17.249]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6NDMvM17595 for ; Tue, 23 Jul 2002 15:22:57 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6NDN0f21170; Tue, 23 Jul 2002 15:23:00 +0200 Date: Tue, 23 Jul 2002 15:23:00 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 Message-ID: <20020723152300.A14474@dea.linux-mips.net> References: <20020723141407.B10566@dea.linux-mips.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: ; from macro@ds2.pg.gda.pl on Tue, Jul 23, 2002 at 03:05:47PM +0200 X-Accept-Language: de,en,fr On Tue, Jul 23, 2002 at 03:05:47PM +0200, Maciej W. Rozycki wrote: > > I intentionally have that 32-bit stuff in the 64-bit kernel so we can simply > > have share identical CPU probing code between the 32-bit and 64-bit kernels. > > This in anticipation of a further unification of the two ports which still > > duplicate plenty of code with just minor changes. > > I suspected a maintability reason. Right > Thus as a temporary fix I'm checking in a version that provides the > missing cpu_has_fpu() function (a copy from the trunk). You've been a little bit too fast :) I've almost implemented my suggestion of moving the probing code into cpu-probe.c. > > To make sharing easier I suggest to move all the CPU probing code into it's > > own file, probe.c or so? > > That might be a good idea in principle, but it won't solve the problem > anyway. I'd like to see the code for 32-bit processors get annihilated by > the compiler if built for mips64. I'll look at it soon. The MIPS32/64 > crap needs to be fixed here as well. If you find a nice way of implementing this I certainly won't object. Ralf From macro@ds2.pg.gda.pl Thu Jul 25 02:06:37 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id CAA19016; Thu, 25 Jul 2002 02:06:37 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 02:06:37 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpdf09995; Thu Jul 25 02:06:25 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6NDUuM17614 for ; Tue, 23 Jul 2002 15:30:56 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id PAA28869; Tue, 23 Jul 2002 15:31:30 +0200 (MET DST) Date: Tue, 23 Jul 2002 15:31:30 +0200 (MET DST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 In-Reply-To: <20020723152300.A14474@dea.linux-mips.net> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On Tue, 23 Jul 2002, Ralf Baechle wrote: > You've been a little bit too fast :) I've almost implemented my suggestion > of moving the probing code into cpu-probe.c. What's the problem? Now the branch and the trunk are in sync (I just did a `cp' from the trunk as the missing function was the only difference), so you may apply the same changes to both. :-) Otherwise you'd have to deal with the difference. > > That might be a good idea in principle, but it won't solve the problem > > anyway. I'd like to see the code for 32-bit processors get annihilated by > > the compiler if built for mips64. I'll look at it soon. The MIPS32/64 > > crap needs to be fixed here as well. > > If you find a nice way of implementing this I certainly won't object. The MIPS32/64 fix is obvious; the 32-bit CPU is not so, but I have a sort of an idea. I'd like to get rid of all ifdefs in the area. Not a high priority, though, sorry. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From ralf@linux-mips.net Thu Jul 25 02:04:58 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id CAA18895; Thu, 25 Jul 2002 02:04:58 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 02:04:58 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpda09995; Thu Jul 25 02:04:46 2002 Received: from dea.linux-mips.net (shaft17-f249.dialo.tiscali.de [62.246.17.249]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6NDxWM17693 for ; Tue, 23 Jul 2002 15:59:33 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6NDxZI24818; Tue, 23 Jul 2002 15:59:35 +0200 Date: Tue, 23 Jul 2002 15:59:35 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 Message-ID: <20020723155935.A22195@dea.linux-mips.net> References: <20020723152300.A14474@dea.linux-mips.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: ; from macro@ds2.pg.gda.pl on Tue, Jul 23, 2002 at 03:31:30PM +0200 X-Accept-Language: de,en,fr On Tue, Jul 23, 2002 at 03:31:30PM +0200, Maciej W. Rozycki wrote: > > You've been a little bit too fast :) I've almost implemented my suggestion > > of moving the probing code into cpu-probe.c. > > What's the problem? Now the branch and the trunk are in sync (I just did > a `cp' from the trunk as the missing function was the only difference), so > you may apply the same changes to both. :-) Otherwise you'd have to deal > with the difference. No real toy, just a merge conflict. Doing this cleanup I also noticed that the 2.4 and 2.5 cpu probing code is out of sync, so I took care of that as well. Any future clean and fix should new be easier as the merge between 32-bit and 64-bit, 2.4 and 2.5 can simply be done using cp. Modern technology rules :) > > > That might be a good idea in principle, but it won't solve the problem > > > anyway. I'd like to see the code for 32-bit processors get annihilated by > > > the compiler if built for mips64. I'll look at it soon. The MIPS32/64 > > > crap needs to be fixed here as well. > > > > If you find a nice way of implementing this I certainly won't object. > > The MIPS32/64 fix is obvious; the 32-bit CPU is not so, but I have a sort > of an idea. I'd like to get rid of all ifdefs in the area. Not a high > priority, though, sorry. I was refering to the less obvious part, obviously ;-) Ralf From kevink@mips.com Thu Jul 25 01:50:56 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id BAA17695; Thu, 25 Jul 2002 01:50:56 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 01:50:56 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpdf09995; Thu Jul 25 01:50:47 2002 Received: from mx2.mips.com (mx2.mips.com [206.31.31.227]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6NEbZM17828 for ; Tue, 23 Jul 2002 16:37:36 +0200 (CEST) Received: from newman.mips.com (ns-dmz [206.31.31.225]) by mx2.mips.com (8.12.5/8.12.5) with ESMTP id g6NEb0Xb024976; Tue, 23 Jul 2002 07:37:00 -0700 (PDT) Received: from Ulysses (sfr-tgn-sfb-vty22.as.wcom.net [216.192.4.22]) by newman.mips.com (8.9.3/8.9.0) with SMTP id HAA05075; Tue, 23 Jul 2002 07:36:54 -0700 (PDT) Message-ID: <003b01c23256$b262f080$1604c0d8@Ulysses> From: "Kevin D. Kissell" To: "Maciej W. Rozycki" , , , "Ralf Baechle" References: Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 Date: Tue, 23 Jul 2002 16:38:58 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 > There is no need to carry support for pure 32-bit CPUs around in > cpu_probe() in arch/mips64/kernel/setup.c, since such CPUs are not > supported by the port and likely won't ever reach that code due to a > reserved instruction exception earlier. The code is misleading and a > possible cause of troubles, e.g. the 2.4 branch doesn't link now because > of an unresolved reference to cpu_has_fpu() which is only needed for > R2000/R3000. > > The following patch removes the code for 2.4. For the trunk > cpu_has_fpu() would be removed as well. Any objections? I'm on the road and don't have ready access to the sources, but if I understand you correctly, I object. The MIPS 5Kc and the NEC Vr41xx are two examples of 64-bit CPUs which don't have FPUs, and I believe there is at least one other from Toshiba. (Tx49-something-or-other). My personal bleief is that the mips and mips64 trees should ultimately be merged, and that creating additional and gratuitous differences should be avoided. From ralf@linux-mips.net Thu Jul 25 01:50:58 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id BAA17698; Thu, 25 Jul 2002 01:50:58 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 01:50:58 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpde09995; Thu Jul 25 01:50:47 2002 Received: from dea.linux-mips.net (shaft17-f249.dialo.tiscali.de [62.246.17.249]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6NEnkM17865 for ; Tue, 23 Jul 2002 16:49:47 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6NEniB31573; Tue, 23 Jul 2002 16:49:44 +0200 Date: Tue, 23 Jul 2002 16:49:44 +0200 From: Ralf Baechle To: "Kevin D. Kissell" Cc: "Maciej W. Rozycki" , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 Message-ID: <20020723164944.A31534@dea.linux-mips.net> References: <003b01c23256$b262f080$1604c0d8@Ulysses> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: <003b01c23256$b262f080$1604c0d8@Ulysses>; from kevink@mips.com on Tue, Jul 23, 2002 at 04:38:58PM +0200 X-Accept-Language: de,en,fr On Tue, Jul 23, 2002 at 04:38:58PM +0200, Kevin D. Kissell wrote: > My personal bleief is that the mips and mips64 trees > should ultimately be merged, and that creating additional > and gratuitous differences should be avoided. A first attempt at building a unifying 32-bit and 64-bit kernel was so ugly that I dumped all that as of 2.0.14. Ralf From macro@ds2.pg.gda.pl Thu Jul 25 01:27:54 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id BAA15086; Thu, 25 Jul 2002 01:27:54 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 01:27:54 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd009995; Thu Jul 25 01:27:52 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6NG0HM18053 for ; Tue, 23 Jul 2002 18:00:17 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id SAA01637; Tue, 23 Jul 2002 18:00:53 +0200 (MET DST) Date: Tue, 23 Jul 2002 18:00:53 +0200 (MET DST) From: "Maciej W. Rozycki" To: "Kevin D. Kissell" cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com, Ralf Baechle Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 In-Reply-To: <003b01c23256$b262f080$1604c0d8@Ulysses> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On Tue, 23 Jul 2002, Kevin D. Kissell wrote: > > The following patch removes the code for 2.4. For the trunk > > cpu_has_fpu() would be removed as well. Any objections? > > I'm on the road and don't have ready access to the sources, > but if I understand you correctly, I object. The MIPS 5Kc and > the NEC Vr41xx are two examples of 64-bit CPUs which don't > have FPUs, and I believe there is at least one other from > Toshiba. (Tx49-something-or-other). The function is exclusively for R2000/R3000 (mostly based on your past suggestion there are broken processors that lock up on CP1 instructions when none is present) which may have an external FPU. Vr41xx CPUs have FPU absence hardcoded (as do others which can't have an FPU) and MIPS32/64 ones obtain the information from the CP0 Config1 register, obviously. The function is never reached on a mips64 kernel -- there is no need to bloat binaries with it. The coincidence with the i386's cpu_has_fpu definition is misleading. At this point we check MIPS_CPU_FPU in mips_cpu.options directly and there is no need to wrap it in a macro, at least not yet. > My personal bleief is that the mips and mips64 trees > should ultimately be merged, and that creating additional > and gratuitous differences should be avoided. I don't think it's possible to be fully achieved. Some differences will have to exist, at least in the headers, but likely within the arch tree as well. The reason is binary code size or perfomance -- having R3000 support code in mips64 binaries is simply ridiculous as is using 32-bit operations with 64-bit data on a 64-bit CPU. However, it is worth trying to minimize visible differences where possible, e.g. by convincing the compiler to optimize irrelevant bits away. Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From jsun@mvista.com Thu Jul 25 00:59:34 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id AAA12416; Thu, 25 Jul 2002 00:59:34 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 00:59:34 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd009995; Thu Jul 25 00:59:27 2002 Received: from av.mvista.com ([12.44.186.158]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6NIVbM18528 for ; Tue, 23 Jul 2002 20:31:37 +0200 (CEST) Received: from mvista.com (av [127.0.0.1]) by av.mvista.com (8.9.3/8.9.3) with ESMTP id LAA20170; Tue, 23 Jul 2002 11:28:38 -0700 Message-ID: <3D3D9E5D.8080309@mvista.com> Date: Tue, 23 Jul 2002 11:20:13 -0700 From: Jun Sun User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:0.9.9) Gecko/20020408 X-Accept-Language: en-us, en MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: Ralf Baechle , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 References: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Maciej W. Rozycki wrote: > On Tue, 23 Jul 2002, Ralf Baechle wrote: > > >>I intentionally have that 32-bit stuff in the 64-bit kernel so we can simply >>have share identical CPU probing code between the 32-bit and 64-bit kernels. >>This in anticipation of a further unification of the two ports which still >>duplicate plenty of code with just minor changes. > > > I suspected a maintability reason. Thus as a temporary fix I'm checking > in a version that provides the missing cpu_has_fpu() function (a copy > from the trunk). > > >>To make sharing easier I suggest to move all the CPU probing code into it's >>own file, probe.c or so? > > > That might be a good idea in principle, but it won't solve the problem > anyway. I'd like to see the code for 32-bit processors get annihilated by > the compiler if built for mips64. I'll look at it soon. The MIPS32/64 > crap needs to be fixed here as well. > FWIW, I like to see CPU probing and setup done in a distributed, configurable fashion. Here are some of my ideas which have been floating around for a while. . There is a global table, where each entry in the table have (at least) four fields: uint company_id uint processor_id uint revision_id void (*setup_cpu)(void); . cpu_probe() simply reads prid register and search through the table. If it finds matching one, then issue the (setup_cpu) call. . matching allows wildcard matching. Apparently more specific entry should be checked before more generic entries. . cpu cache routines and tlb routines are organized accordingly, so that static configurations can be done sensibly. This structure allows maximum code sharing for conforming CPUs and also give an easy for unique ones or buggy, early-production ones. It should also make it easy to add or remove support for particular CPU or CPU family. Of course, more details need to be fleshed out. Jun From kevink@mips.com Thu Jul 25 00:40:14 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id AAA11179; Thu, 25 Jul 2002 00:40:14 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 00:40:14 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpdc09995; Thu Jul 25 00:40:05 2002 Received: from mx2.mips.com (mx2.mips.com [206.31.31.227]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6NLERM18979 for ; Tue, 23 Jul 2002 23:14:27 +0200 (CEST) Received: from newman.mips.com (ns-dmz [206.31.31.225]) by mx2.mips.com (8.12.5/8.12.5) with ESMTP id g6NLDHXb026374; Tue, 23 Jul 2002 14:13:17 -0700 (PDT) Received: from menelaus.mips.com (menelaus [192.168.65.223]) by newman.mips.com (8.9.3/8.9.0) with ESMTP id OAA27298; Tue, 23 Jul 2002 14:13:10 -0700 (PDT) Received: from mips.com (localhost [127.0.0.1]) by menelaus.mips.com (8.9.3/8.9.0) with ESMTP id OAA04095; Tue, 23 Jul 2002 14:13:10 -0700 (PDT) Sender: kevink@mips.com Message-ID: <3D3DC6E6.AFF9CBFD@mips.com> Date: Tue, 23 Jul 2002 14:13:10 -0700 From: "Kevin D. Kissell" Organization: MIPS Technologies Inc. X-Mailer: Mozilla 4.61 [en] (X11; U; SunOS 5.8 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: linux-mips@fnet.fr, linux-mips@oss.sgi.com, Ralf Baechle Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit > > My personal belief is that the mips and mips64 trees > > should ultimately be merged, and that creating additional > > and gratuitous differences should be avoided. > > I don't think it's possible to be fully achieved. Some differences will > have to exist, at least in the headers, but likely within the arch tree as > well. The reason is binary code size or perfomance -- having R3000 > support code in mips64 binaries is simply ridiculous as is using 32-bit > operations with 64-bit data on a 64-bit CPU. However, it is worth trying > to minimize visible differences where possible, e.g. by convincing the > compiler to optimize irrelevant bits away. I am not interested in running R3000's with 64-bit binaries - only in having common sources for both. I fully expect that there will always be differences between the platforms, but the last time I checked, there were more identical or nearly identical source modules across the two arch trees than there were distinctly different ones. The result is that the two subtrees tend to drift out of sync. For me, it's really a "Software Engineering 101" kind of thing that there should be exactly one instance in the source tree of any source module that is common to 32-bit and 64-bit MIPS kernels, and that where the code cannot be common, sensible rules should be applied in terms of when to put both sets of code in the same module as conditionally complied blocks and when to split things out into seperately maintained modules. Etc. Etc. Kevin K. From ralf@linux-mips.net Wed Jul 24 23:52:31 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id XAA00922; Wed, 24 Jul 2002 23:52:31 +0200 (MET DST) Received-Date: Wed, 24 Jul 2002 23:52:31 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd000812; Wed Jul 24 23:52:26 2002 Received: from dea.linux-mips.net (shaft17-f182.dialo.tiscali.de [62.246.17.182]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6OEqwM21734 for ; Wed, 24 Jul 2002 16:52:58 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6OEqdm28375; Wed, 24 Jul 2002 16:52:39 +0200 Date: Wed, 24 Jul 2002 16:52:39 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" , "Kevin D. Kissell" , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 Message-ID: <20020724165239.F28010@dea.linux-mips.net> References: <3D3DC6E6.AFF9CBFD@mips.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: <3D3DC6E6.AFF9CBFD@mips.com>; from kevink@mips.com on Tue, Jul 23, 2002 at 02:13:10PM -0700 X-Accept-Language: de,en,fr Maciej, > I don't think it's possible to be fully achieved. Some differences will > have to exist, at least in the headers, but likely within the arch tree as > well. The reason is binary code size or perfomance -- having R3000 > support code in mips64 binaries is simply ridiculous as is using 32-bit > operations with 64-bit data on a 64-bit CPU. However, it is worth trying > to minimize visible differences where possible, e.g. by convincing the > compiler to optimize irrelevant bits away. In this particular case all the bloat is just in __init code, could that convince you? Ralf From macro@ds2.pg.gda.pl Wed Jul 24 22:49:22 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id WAA17674; Wed, 24 Jul 2002 22:49:22 +0200 (MET DST) Received-Date: Wed, 24 Jul 2002 22:49:22 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpdb17226; Wed Jul 24 22:49:16 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6OF5LM21812 for ; Wed, 24 Jul 2002 17:05:22 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id RAA00413; Wed, 24 Jul 2002 17:05:53 +0200 (MET DST) Date: Wed, 24 Jul 2002 17:05:52 +0200 (MET DST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: "Kevin D. Kissell" , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 In-Reply-To: <20020724165239.F28010@dea.linux-mips.net> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Ralf, > > I don't think it's possible to be fully achieved. Some differences will > > have to exist, at least in the headers, but likely within the arch tree as > > well. The reason is binary code size or perfomance -- having R3000 > > support code in mips64 binaries is simply ridiculous as is using 32-bit > > operations with 64-bit data on a 64-bit CPU. However, it is worth trying > > to minimize visible differences where possible, e.g. by convincing the > > compiler to optimize irrelevant bits away. > > In this particular case all the bloat is just in __init code, could that > convince you? Nope, sorry. I'm by all means for keeping any questionable but at least remotely useful code under the __init justification. But in this case, the code will never, ever be used. As I stated, I'm going to look deeper at the issue. Just let it exist as is for now, until me (or someone else) invents an improvement. To state it explicitly: yes, I'm going to keep a single source for both paths and convince the compiler somehow to rip unneeded bits in the 64-bit case. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From macro@ds2.pg.gda.pl Wed Jul 24 22:49:22 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id WAA17675; Wed, 24 Jul 2002 22:49:22 +0200 (MET DST) Received-Date: Wed, 24 Jul 2002 22:49:22 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpda17226; Wed Jul 24 22:49:15 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6OFB5M21850 for ; Wed, 24 Jul 2002 17:11:06 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id RAA00650; Wed, 24 Jul 2002 17:11:38 +0200 (MET DST) Date: Wed, 24 Jul 2002 17:11:37 +0200 (MET DST) From: "Maciej W. Rozycki" To: Jun Sun cc: Ralf Baechle , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: cpu_probe(): remove 32-bit CPU bits for MIPS64 In-Reply-To: <3D3D9E5D.8080309@mvista.com> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On Tue, 23 Jul 2002, Jun Sun wrote: > This structure allows maximum code sharing for conforming CPUs and also give > an easy for unique ones or buggy, early-production ones. It should also make > it easy to add or remove support for particular CPU or CPU family. Of course, > more details need to be fleshed out. Go ahead, that sounds much reasonable. Most of the hassle will be for pre-MIPS32/64 processors, obviously. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From macro@ds2.pg.gda.pl Wed Jul 24 23:52:20 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id XAA00819; Wed, 24 Jul 2002 23:52:20 +0200 (MET DST) Received-Date: Wed, 24 Jul 2002 23:52:20 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpda00812; Wed Jul 24 23:52:09 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6OFXiM21888 for ; Wed, 24 Jul 2002 17:33:44 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id RAA01570; Wed, 24 Jul 2002 17:34:21 +0200 (MET DST) Date: Wed, 24 Jul 2002 17:34:20 +0200 (MET DST) From: "Maciej W. Rozycki" To: Ralf Baechle , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: [patch] wbflush() fixes and updates Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Hello, Here is a follow-on patch to the recent synchronization rewrite. It converts a few of wbflush() references to iob() (functionally equivalent, but with a somewhat more consistent naming) and it removes a few unnecessary private __wbflush() implementations (that now are covered by the generic code). Finally, it fixes the DECstation __wbflush() implementation to match hardware reality. OK to apply? Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + patch-mips-2.4.19-rc1-20020719-wbflush-9 diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1000/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1000/setup.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1000/setup.c 2002-07-05 02:57:37.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1000/setup.c 2002-07-23 21:25:22.000000000 +0000 @@ -67,7 +67,6 @@ extern struct ide_ops std_ide_ops; extern struct ide_ops *ide_ops; #endif -void (*__wbflush) (void); extern struct rtc_ops no_rtc_ops; extern char * __init prom_getcmdline(void); extern void au1000_restart(char *); @@ -78,11 +77,6 @@ extern struct resource iomem_resource; void __init bus_error_init(void) { /* nothing */ } -void au1000_wbflush(void) -{ - __asm__ volatile ("sync"); -} - void __init au1000_setup(void) { char *argptr; @@ -103,7 +97,6 @@ void __init au1000_setup(void) #endif rtc_ops = &no_rtc_ops; - __wbflush = au1000_wbflush; _machine_restart = au1000_restart; _machine_halt = au1000_halt; _machine_power_off = au1000_power_off; diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1100/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1100/setup.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1100/setup.c 2002-07-14 21:20:57.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1100/setup.c 2002-07-23 21:25:56.000000000 +0000 @@ -71,7 +71,6 @@ extern struct ide_ops *ide_ops; extern struct rtc_ops pb1500_rtc_ops; #endif -void (*__wbflush) (void); extern char * __init prom_getcmdline(void); extern void au1000_restart(char *); extern void au1000_halt(void); @@ -80,11 +79,6 @@ extern struct resource ioport_resource; extern struct resource iomem_resource; -void au1100_wbflush(void) -{ - __asm__ volatile ("sync"); -} - void __init bus_error_init(void) { /* nothing */ } void __init au1100_setup(void) @@ -112,7 +106,6 @@ void __init au1100_setup(void) argptr = prom_getcmdline(); #endif - __wbflush = au1100_wbflush; _machine_restart = au1000_restart; _machine_halt = au1000_halt; _machine_power_off = au1000_power_off; diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1500/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1500/setup.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1500/setup.c 2002-07-15 02:57:11.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1500/setup.c 2002-07-23 21:26:24.000000000 +0000 @@ -71,7 +71,6 @@ extern struct ide_ops *ide_ops; extern struct rtc_ops pb1500_rtc_ops; #endif -void (*__wbflush) (void); extern char * __init prom_getcmdline(void); extern void au1000_restart(char *); extern void au1000_halt(void); @@ -82,11 +81,6 @@ extern struct resource iomem_resource; void __init bus_error_init(void) { /* nothing */ } -void au1500_wbflush(void) -{ - __asm__ volatile ("sync"); -} - void __init au1500_setup(void) { char *argptr; @@ -112,7 +106,6 @@ void __init au1500_setup(void) argptr = prom_getcmdline(); #endif - __wbflush = au1500_wbflush; _machine_restart = au1000_restart; _machine_halt = au1000_halt; _machine_power_off = au1000_power_off; diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/baget/Makefile linux-mips-2.4.19-rc1-20020719/arch/mips/baget/Makefile --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/baget/Makefile 2001-01-11 05:25:50.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/baget/Makefile 2002-07-23 21:27:40.000000000 +0000 @@ -14,7 +14,7 @@ O_TARGET := baget.a export-objs := vacserial.o vacrtc.o obj-y := baget.o print.o setup.o time.o irq.o bagetIRQ.o \ - reset.o wbflush.o + reset.o obj-$(CONFIG_SERIAL) += vacserial.o obj-$(CONFIG_VAC_RTC) += vacrtc.o diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/baget/wbflush.c linux-mips-2.4.19-rc1-20020719/arch/mips/baget/wbflush.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/baget/wbflush.c 2000-03-28 04:26:02.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/baget/wbflush.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,24 +0,0 @@ -/* - * Setup the right wbflush routine for Baget/MIPS. - * - * Copyright (C) 1999 Gleb Raiko & Vladimir Roganov - */ - -#include -#include - -void (*__wbflush) (void); - -static void wbflush_baget(void); - -void __init wbflush_setup(void) -{ - __wbflush = wbflush_baget; -} - -/* - * Baget/MIPS doesnt need to write back the WB. - */ -static void wbflush_baget(void) -{ -} diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/Makefile linux-mips-2.4.19-rc1-20020719/arch/mips/dec/Makefile --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/Makefile 2002-06-26 03:04:35.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/dec/Makefile 2002-07-21 18:11:04.000000000 +0000 @@ -14,9 +14,10 @@ all: dec.o export-objs := setup.o wbflush.o obj-y := int-handler.o ioasic-irq.o kn02-irq.o reset.o rtc-dec.o setup.o \ - time.o wbflush.o + time.o obj-$(CONFIG_PROM_CONSOLE) += promcon.o +obj-$(CONFIG_CPU_HAS_WB) += wbflush.o int-handler.o: int-handler.S diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/ioasic-irq.c linux-mips-2.4.19-rc1-20020719/arch/mips/dec/ioasic-irq.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/ioasic-irq.c 2002-04-09 02:27:12.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/dec/ioasic-irq.c 2002-04-16 20:53:43.000000000 +0000 @@ -84,6 +84,7 @@ static inline void ack_ioasic_irq(unsign spin_lock(&ioasic_lock); mask_ioasic_irq(irq); spin_unlock(&ioasic_lock); + fast_iob(); } static inline void end_ioasic_irq(unsigned int irq) @@ -119,6 +120,7 @@ static struct hw_interrupt_type ioasic_i static inline void end_ioasic_dma_irq(unsigned int irq) { clear_ioasic_irq(irq); + fast_iob(); end_ioasic_irq(irq); } @@ -142,6 +144,7 @@ void __init init_ioasic_irqs(int base) /* Mask interrupts. */ ioasic_write(SIMR, 0); + fast_iob(); for (i = base; i < base + IO_INR_DMA; i++) { irq_desc[i].status = IRQ_DISABLED; diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/kn02-irq.c linux-mips-2.4.19-rc1-20020719/arch/mips/dec/kn02-irq.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/kn02-irq.c 2002-04-09 02:27:12.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/dec/kn02-irq.c 2002-04-16 20:53:43.000000000 +0000 @@ -83,6 +83,7 @@ static void ack_kn02_irq(unsigned int ir spin_lock(&kn02_lock); mask_kn02_irq(irq); spin_unlock(&kn02_lock); + iob(); } static void end_kn02_irq(unsigned int irq) @@ -113,6 +114,7 @@ void __init init_kn02_irqs(int base) /* Mask interrupts and preset write-only bits. */ cached_kn02_csr = (*csr & ~0xff0000) | 0xff; *csr = cached_kn02_csr; + iob(); for (i = base; i < base + KN02_IRQ_LINES; i++) { irq_desc[i].status = IRQ_DISABLED; diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips/dec/setup.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/setup.c 2002-07-19 03:01:49.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/dec/setup.c 2002-07-21 18:11:04.000000000 +0000 @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -89,8 +90,6 @@ static struct irqaction fpuirq = {NULL, static struct irqaction haltirq = {dec_intr_halt, 0, 0, "halt", NULL, NULL}; -extern void wbflush_setup(void); - extern struct rtc_ops dec_rtc_ops; void (*board_time_init) (struct irqaction * irq); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/wbflush.c linux-mips-2.4.19-rc1-20020719/arch/mips/dec/wbflush.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/wbflush.c 2001-11-06 05:26:15.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/dec/wbflush.c 2002-02-04 01:03:17.000000000 +0000 @@ -11,15 +11,18 @@ * for more details. * * Copyright (C) 1998 Harald Koerfgen + * Copyright (C) 2002 Maciej W. Rozycki */ -#include #include +#include +#include +#include + static void wbflush_kn01(void); static void wbflush_kn210(void); -static void wbflush_kn02ba(void); -static void wbflush_kn03(void); +static void wbflush_mips(void); void (*__wbflush) (void); @@ -27,28 +30,23 @@ void __init wbflush_setup(void) { switch (mips_machtype) { case MACH_DS23100: - __wbflush = wbflush_kn01; - break; - case MACH_DS5100: /* DS5100 MIPSMATE */ - __wbflush = wbflush_kn210; - break; case MACH_DS5000_200: /* DS5000 3max */ - __wbflush = wbflush_kn01; - break; + __wbflush = wbflush_kn01; + break; + case MACH_DS5100: /* DS5100 MIPSMATE */ + __wbflush = wbflush_kn210; + break; case MACH_DS5000_1XX: /* DS5000/100 3min */ - __wbflush = wbflush_kn02ba; - break; - case MACH_DS5000_2X0: /* DS5000/240 3max+ */ - __wbflush = wbflush_kn03; - break; case MACH_DS5000_XX: /* Personal DS5000/2x */ - __wbflush = wbflush_kn02ba; - break; + case MACH_DS5000_2X0: /* DS5000/240 3max+ */ + default: + __wbflush = wbflush_mips; + break; } } /* - * For the DS3100 and DS5000/200 the writeback buffer functions + * For the DS3100 and DS5000/200 the R2020/R3220 writeback buffer functions * as part of Coprocessor 0. */ static void wbflush_kn01(void) @@ -78,29 +76,16 @@ static void wbflush_kn210(void) "mtc0\t$2,$12\n\t" "nop\n\t" ".set\tpop" - : : :"$2", "$3"); -} - -/* - * Looks like some magic with the System Interrupt Mask Register - * in the famous IOASIC for kmins and maxines. - */ -static void wbflush_kn02ba(void) -{ - asm(".set\tpush\n\t" - ".set\tnoreorder\n\t" - "lui\t$2,0xbc04\n\t" - "lw\t$3,0x120($2)\n\t" - "lw\t$3,0x120($2)\n\t" - ".set\tpop" - : : :"$2", "$3"); + : : : "$2", "$3"); } /* - * The DS500/2x0 doesnt need to write back the WB. + * I/O ASIC systems use a standard writeback buffer that gets flushed + * upon an uncached read. */ -static void wbflush_kn03(void) +static void wbflush_mips(void) { + __fast_iob(); } #include diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/galileo-boards/ev96100/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips/galileo-boards/ev96100/setup.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/galileo-boards/ev96100/setup.c 2001-11-26 05:25:59.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/galileo-boards/ev96100/setup.c 2002-07-23 21:30:52.000000000 +0000 @@ -52,8 +52,6 @@ #include -void (*__wbflush) (void); - #if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE) extern void console_setup(char *, int *); char serial_console[20]; @@ -65,11 +63,6 @@ extern void mips_reboot_setup(void); extern struct rtc_ops no_rtc_ops; extern struct resource ioport_resource; -static void rm7000_wbflush(void) -{ - __asm__ __volatile__ ("sync"); -} - unsigned char mac_0_1[12]; @@ -83,7 +76,6 @@ void __init ev96100_setup(void) char *argptr; clear_cp0_status(ST0_FR); - __wbflush = rm7000_wbflush; if (config & 0x8) { printk("Secondary cache is enabled\n"); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/c-r3k.c linux-mips-2.4.19-rc1-20020719/arch/mips/mm/c-r3k.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/c-r3k.c 2002-02-19 05:28:14.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/mm/c-r3k.c 2002-03-24 21:16:14.000000000 +0000 @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -314,7 +313,7 @@ static void r3k_flush_cache_sigtramp(uns static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size) { - wbflush(); + iob(); r3k_flush_dcache_range(start, start + size); } diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/c-tx39.c linux-mips-2.4.19-rc1-20020719/arch/mips/mm/c-tx39.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/c-tx39.c 2001-12-01 05:26:01.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/mm/c-tx39.c 2002-02-04 01:12:41.000000000 +0000 @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -63,8 +62,8 @@ static void tx39h_flush_icache_all(void) static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size) { unsigned long end, a; - wbflush(); + iob(); a = addr & ~(dcache_lsize - 1); end = (addr + size) & ~(dcache_lsize - 1); while (1) { diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/tlb-r3k.c linux-mips-2.4.19-rc1-20020719/arch/mips/mm/tlb-r3k.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/tlb-r3k.c 2002-05-30 02:57:46.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/mm/tlb-r3k.c 2002-06-15 15:38:41.000000000 +0000 @@ -20,7 +20,6 @@ #include #include #include -#include #include #include diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/drivers/char/dz.c linux-mips-2.4.19-rc1-20020719/drivers/char/dz.c --- linux-mips-2.4.19-rc1-20020719.macro/drivers/char/dz.c 2002-06-27 02:58:15.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/drivers/char/dz.c 2002-07-21 18:11:04.000000000 +0000 @@ -35,7 +35,6 @@ #include #include #include -#include #include #include @@ -53,6 +52,8 @@ #include #include +#include + #define CONSOLE_LINE (3) /* for definition of struct console */ extern int (*prom_printf) (char *,...); @@ -1415,7 +1416,7 @@ int __init dz_init(void) #ifndef CONFIG_SERIAL_CONSOLE dz_out(info, DZ_CSR, DZ_CLR); while ((tmp = dz_in(info, DZ_CSR)) & DZ_CLR); - wbflush(); + iob(); /* enable scanning */ dz_out(info, DZ_CSR, DZ_MSE); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/drivers/net/declance.c linux-mips-2.4.19-rc1-20020719/drivers/net/declance.c --- linux-mips-2.4.19-rc1-20020719.macro/drivers/net/declance.c 2002-07-08 16:46:24.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/drivers/net/declance.c 2002-07-21 18:11:05.000000000 +0000 @@ -62,7 +62,7 @@ #include #include #include -#include +#include static char version[] __devinitdata = "declance.c: v0.009 by Linux MIPS DECstation task force\n"; @@ -289,7 +289,7 @@ static struct net_device *root_lance_dev static inline void writereg(volatile unsigned short *regptr, short value) { *regptr = value; - wbflush(); + iob(); } /* Load the CSR registers */ @@ -369,7 +369,7 @@ void cp_to_buf(const int type, void *to, } } - wbflush(); + iob(); } void cp_from_buf(const int type, void *to, const void *from, int len) @@ -497,7 +497,7 @@ static void lance_init_ring(struct net_d if (i < 3 && ZERO) printk("%d: 0x%8.8x(0x%8.8x)\n", i, leptr, (int) lp->rx_buf_ptr_cpu[i]); } - wbflush(); + iob(); } static int init_restart_lance(struct lance_private *lp) @@ -794,7 +794,7 @@ static int lance_open(struct net_device return -EAGAIN; } /* Enable I/O ASIC LANCE DMA. */ - wbflush(); + fast_wmb(); ioasic_write(SSR, ioasic_read(SSR) | LANCE_DMA_EN); } @@ -823,7 +823,7 @@ static int lance_close(struct net_device if (lp->dma_irq >= 0) { /* Disable I/O ASIC LANCE DMA. */ ioasic_write(SSR, ioasic_read(SSR) & ~LANCE_DMA_EN); - wbflush(); + fast_iob(); free_irq(lp->dma_irq, dev); } free_irq(dev->irq, dev); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/drivers/scsi/NCR53C9x.h linux-mips-2.4.19-rc1-20020719/drivers/scsi/NCR53C9x.h --- linux-mips-2.4.19-rc1-20020719.macro/drivers/scsi/NCR53C9x.h 2001-10-19 04:29:11.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/drivers/scsi/NCR53C9x.h 2002-02-04 01:14:34.000000000 +0000 @@ -144,12 +144,7 @@ #ifndef MULTIPLE_PAD_SIZES -#ifdef CONFIG_CPU_HAS_WB -#include -#define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0) -#else -#define esp_write(__reg, __val) ((__reg) = (__val)) -#endif +#define esp_write(__reg, __val) do{(__reg) = (__val); iob();} while(0) #define esp_read(__reg) (__reg) struct ESP_regs { diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/drivers/scsi/dec_esp.c linux-mips-2.4.19-rc1-20020719/drivers/scsi/dec_esp.c --- linux-mips-2.4.19-rc1-20020719.macro/drivers/scsi/dec_esp.c 2002-04-10 02:58:49.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/drivers/scsi/dec_esp.c 2002-07-21 18:12:55.000000000 +0000 @@ -46,6 +46,8 @@ #include #include +#include + /* * Once upon a time the pmaz code used to be working but * it hasn't been maintained for quite some time. @@ -308,17 +310,9 @@ static void scsi_dma_err_int(int irq, vo static void scsi_dma_int(int irq, void *dev_id, struct pt_regs *regs) { - volatile unsigned int *dummy = (volatile unsigned int *)KSEG1; - /* next page */ *scsi_next_ptr = ((*scsi_dma_ptr + PAGE_SIZE) & PAGE_MASK) << 3; - - /* - * This routine will only work on IOASIC machines - * so we can avoid an indirect function call here - * and flush the writeback buffer the fast way - */ - *dummy; + fast_iob(); } static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count) @@ -370,8 +364,6 @@ static void dma_dump_state(struct NCR_ES static void dma_init_read(struct NCR_ESP *esp, __u32 vaddress, int length) { - volatile unsigned int *dummy = (volatile unsigned int *)KSEG1; - if (vaddress & 3) panic("dec_efs.c: unable to handle partial word transfers, yet..."); @@ -384,17 +376,11 @@ static void dma_init_read(struct NCR_ESP /* prepare for next page */ *scsi_next_ptr = ((vaddress + PAGE_SIZE) & PAGE_MASK) << 3; *ioasic_ssr |= (SCSI_DMA_DIR | SCSI_DMA_EN); - - /* - * see above - */ - *dummy; + fast_iob(); } static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length) { - volatile unsigned int *dummy = (volatile unsigned int *)KSEG1; - if (vaddress & 3) panic("dec_efs.c: unable to handle partial word transfers, yet..."); @@ -407,11 +393,7 @@ static void dma_init_write(struct NCR_ES /* prepare for next page */ *scsi_next_ptr = ((vaddress + PAGE_SIZE) & PAGE_MASK) << 3; *ioasic_ssr |= SCSI_DMA_EN; - - /* - * see above - */ - *dummy; + fast_iob(); } static void dma_ints_off(struct NCR_ESP *esp) @@ -492,6 +474,8 @@ static void pmaz_dma_init_read(struct NC *dmareg = TC_ESP_DMA_ADDR(esp->slot + DEC_SCSI_SRAM + ESP_TGT_DMA_SIZE); + iob(); + esp_virt_buffer = vaddress; scsi_current_length = length; } @@ -506,6 +490,7 @@ static void pmaz_dma_init_write(struct N *dmareg = TC_ESP_DMAR_WRITE | TC_ESP_DMA_ADDR(esp->slot + DEC_SCSI_SRAM + ESP_TGT_DMA_SIZE); + iob(); } static void pmaz_dma_ints_off(struct NCR_ESP *esp) diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/drivers/tc/zs.c linux-mips-2.4.19-rc1-20020719/drivers/tc/zs.c --- linux-mips-2.4.19-rc1-20020719.macro/drivers/tc/zs.c 2002-06-27 02:59:46.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/drivers/tc/zs.c 2002-07-21 18:11:05.000000000 +0000 @@ -67,7 +67,6 @@ #include #include #include -#include #include #ifdef CONFIG_DECSTATION #include @@ -276,7 +275,7 @@ static inline unsigned char read_zsreg(s if (reg != 0) { *channel->control = reg & 0xf; - wbflush(); RECOVERY_DELAY; + fast_iob(); RECOVERY_DELAY; } retval = *channel->control; RECOVERY_DELAY; @@ -288,10 +287,10 @@ static inline void write_zsreg(struct de { if (reg != 0) { *channel->control = reg & 0xf; - wbflush(); RECOVERY_DELAY; + fast_iob(); RECOVERY_DELAY; } *channel->control = value; - wbflush(); RECOVERY_DELAY; + fast_iob(); RECOVERY_DELAY; return; } @@ -308,7 +307,7 @@ static inline void write_zsdata(struct d unsigned char value) { *channel->data = value; - wbflush(); RECOVERY_DELAY; + fast_iob(); RECOVERY_DELAY; return; } From macro@ds2.pg.gda.pl Wed Jul 24 22:40:12 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id WAA14366; Wed, 24 Jul 2002 22:40:12 +0200 (MET DST) Received-Date: Wed, 24 Jul 2002 22:40:12 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpdb13984; Wed Jul 24 22:40:06 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6OGO5M22025 for ; Wed, 24 Jul 2002 18:24:06 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id SAA03644; Wed, 24 Jul 2002 18:24:39 +0200 (MET DST) Date: Wed, 24 Jul 2002 18:24:39 +0200 (MET DST) From: "Maciej W. Rozycki" To: Pete Popov cc: Ralf Baechle , linux-mips@fnet.fr, linux-mips Subject: Re: [patch] wbflush() fixes and updates In-Reply-To: <1027527551.18017.13.camel@zeus.mvista.com> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On 24 Jul 2002, Pete Popov wrote: > The Au1x00 looks fine. I suppose I'll have to update the defconfig > files to include CONFIG_CPU_HAS_SYNC. No need to, as the option is not user selectable. No hurt though, either. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From macro@ds2.pg.gda.pl Wed Jul 24 22:38:09 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id WAA13453; Wed, 24 Jul 2002 22:38:09 +0200 (MET DST) Received-Date: Wed, 24 Jul 2002 22:38:09 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd013449; Wed Jul 24 22:38:03 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6OH4xM22137 for ; Wed, 24 Jul 2002 19:05:00 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id TAA05311; Wed, 24 Jul 2002 19:05:37 +0200 (MET DST) Date: Wed, 24 Jul 2002 19:05:36 +0200 (MET DST) From: "Maciej W. Rozycki" Reply-To: "Maciej W. Rozycki" To: linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: [patch] linux: RFC: elf_check_arch() rework Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Hello, After noticing I cannot run a trivial ELF64 program because of the EF_MIPS_ARCH_3 flag (quite a reasonable setting for a 64-bit executable, isn't it?), I concluded a considerable rework of elf_check_arch() is needed as what we currently have is inadequate. Here is my proposal. I think binfmt_elf.c for mips and binfmt_elf32.c for mips64 should accept all ELF32 binaries either with no ABI mark (as produced by most versions of binutils) or with a 32 (aka o32) ABI one and binfmt_elf.c for mips64 should accept all ELF32 binaries with an n32 ABI mark and all ELF64 ones (which essentially means the 64 aka n64 ABI). Everything else (i.e. o64 and EABIs) is rejected. The patch adds necessary ELF file header flag definitions and synchronizes a few wrong ones to the binutils' definitions as well. It removes the bogus check of architecture flags as they are really irrelevant -- the code is intended to handle executable formats and not execution of code. If a user incorporates unsupported opcodes, he'll just get SIGILL at one moment. We may actually check if an architecture is supported even no other Linux port seems to care, but then the comparison should be against mips_cpu.isa_level and not against hardcoded constants. Note, this is an RFC at this stage -- I haven't tested the code adequately for an immediate inclusion, even if it looks obvious. There should be no problems with code made with old binutils as unset flags are treated as (o)32. Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + patch-mips-2.4.19-rc1-20020719-mips64-elf-2 diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips64/kernel/binfmt_elf32.c linux-mips-2.4.19-rc1-20020719/arch/mips64/kernel/binfmt_elf32.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips64/kernel/binfmt_elf32.c 2002-06-29 03:01:44.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips64/kernel/binfmt_elf32.c 2002-07-23 23:15:27.000000000 +0000 @@ -27,8 +27,26 @@ typedef elf_greg_t elf_gregset_t[ELF_NGR typedef double elf_fpreg_t; typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; -#define elf_check_arch(x) \ - ((x)->e_machine == EM_MIPS) +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(hdr) \ +({ \ + int __res = 1; \ + struct elfhdr *__h = (hdr); \ + \ + if (__h->e_machine != EM_MIPS) \ + __res = 0; \ + if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ + __res = 0; \ + if ((__h->e_flags & EF_MIPS_ABI2) != 0) \ + __res = 0; \ + if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ + ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ + __res = 0; \ + \ + __res; \ +}) #define TASK32_SIZE 0x80000000UL #undef ELF_ET_DYN_BASE diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/include/asm-mips/elf.h linux-mips-2.4.19-rc1-20020719/include/asm-mips/elf.h --- linux-mips-2.4.19-rc1-20020719.macro/include/asm-mips/elf.h 2002-04-25 02:57:43.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/include/asm-mips/elf.h 2002-07-23 22:50:48.000000000 +0000 @@ -16,10 +16,11 @@ #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -#define EF_MIPS_ARCH_32R2 0x80000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64R2 0x90000000 /* MIPS64 code. */ +#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ +#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ +/* The ABI of the file. */ +#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ +#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */ typedef unsigned long elf_greg_t; typedef elf_greg_t elf_gregset_t[ELF_NGREG]; @@ -37,10 +38,12 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_N \ if (__h->e_machine != EM_MIPS) \ __res = 0; \ - if (((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_1) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_2) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_32) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_32R2)) \ + if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ + __res = 0; \ + if ((__h->e_flags & EF_MIPS_ABI2) != 0) \ + __res = 0; \ + if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ + ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ __res = 0; \ \ __res; \ diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/include/asm-mips64/elf.h linux-mips-2.4.19-rc1-20020719/include/asm-mips64/elf.h --- linux-mips-2.4.19-rc1-20020719.macro/include/asm-mips64/elf.h 2002-07-22 08:49:30.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/include/asm-mips64/elf.h 2002-07-23 23:12:28.000000000 +0000 @@ -9,21 +9,23 @@ #include #include -#ifndef ELF_ARCH -/* ELF register definitions */ -#define ELF_NGREG 45 -#define ELF_NFPREG 33 - -/* ELF header e_flags defines. MIPS architecture level. */ +/* ELF header e_flags defines. */ +/* MIPS architecture level. */ #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -#define EF_MIPS_ARCH_32R2 0x80000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64R2 0x90000000 /* MIPS64 code. */ +#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ +#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ +/* The ABI of the file. */ +#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ +#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */ + +#ifndef ELF_ARCH +/* ELF register definitions */ +#define ELF_NGREG 45 +#define ELF_NFPREG 33 typedef unsigned long elf_greg_t; typedef elf_greg_t elf_gregset_t[ELF_NGREG]; @@ -41,14 +43,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_N \ if (__h->e_machine != EM_MIPS) \ __res = 0; \ - if (sizeof(elf_caddr_t) == 8 && \ - __h->e_ident[EI_CLASS] == ELFCLASS32) \ - __res = 0; \ - if (((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_1) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_2) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_32) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_32R2)) \ - __res = 0; \ + if ((__h->e_ident[EI_CLASS] == ELFCLASS32) && \ + ((__h->e_flags & EF_MIPS_ABI2) == 0)) \ + __res = 0; \ \ __res; \ }) diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/include/linux/elf.h linux-mips-2.4.19-rc1-20020719/include/linux/elf.h --- linux-mips-2.4.19-rc1-20020719.macro/include/linux/elf.h 2002-07-22 08:49:30.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/include/linux/elf.h 2002-07-23 22:18:54.000000000 +0000 @@ -37,6 +37,9 @@ typedef __s64 Elf64_Sxword; #define EF_MIPS_NOREORDER 0x00000001 #define EF_MIPS_PIC 0x00000002 #define EF_MIPS_CPIC 0x00000004 +#define EF_MIPS_ABI2 0x00000020 +#define EF_MIPS_32BITMODE 0x00000100 +#define EF_MIPS_ABI 0x0000f000 #define EF_MIPS_ARCH 0xf0000000 /* These constants define the different elf file types */ From macro@ds2.pg.gda.pl Thu Jul 25 13:55:49 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id NAA18037; Thu, 25 Jul 2002 13:21:56 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 13:21:56 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd018035; Thu Jul 25 13:21:49 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6PBLfM03778 for ; Thu, 25 Jul 2002 13:21:41 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id NAA29941; Thu, 25 Jul 2002 13:10:06 +0200 (MET DST) Date: Thu, 25 Jul 2002 13:10:06 +0200 (MET DST) From: "Maciej W. Rozycki" To: Carsten Langgaard cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: RFC: elf_check_arch() rework In-Reply-To: <3D3EFC14.D8D690F0@mips.com> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On Wed, 24 Jul 2002, Carsten Langgaard wrote: > We at MIPS are in the process of making an ABI spec for all this, which > is the intention that should be used by the tool-vendors. So please > don't change the ELF header defines. It'd be better the spec matched the real world... > I don't see that is wrong with checking the ISA level, I rather have an > error telling me that I can't execute a certain ISA level than > eventually getting a reserved instruction or something worse like > something unpredictable. Well, -ENOEXEC in not any more useful than SIGILL -- with the latter you have at least an idea what happened. The ISA check is not implemented for any Linux port, so there no suitable hook in binfmt_*.c files. You might propose an implementation if that's particularly important for you. > You are obviously right about the elf_check_arch in the 64-bit part of > the kernel is broken. It's probably just be copied from the 32-bit part > without changes, like a lot of the code in the 64-bit kernel is. Possibly, but it still makes me wonder why it wasn't adjusted at the time binfmt_elf32.c was created... Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From carstenl@mips.com Thu Jul 25 15:30:09 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id PAA20025; Thu, 25 Jul 2002 15:30:09 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 15:30:09 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd020019; Thu Jul 25 15:30:01 2002 Received: from mx2.mips.com (mx2.mips.com [206.31.31.227]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6PDTrM04309 for ; Thu, 25 Jul 2002 15:29:53 +0200 (CEST) Received: from newman.mips.com (ns-dmz [206.31.31.225]) by mx2.mips.com (8.12.5/8.12.5) with ESMTP id g6PDTEXb002671; Thu, 25 Jul 2002 06:29:14 -0700 (PDT) Received: from copfs01.mips.com (copfs01 [192.168.205.101]) by newman.mips.com (8.9.3/8.9.0) with ESMTP id GAA18905; Thu, 25 Jul 2002 06:29:14 -0700 (PDT) Received: from mips.com (copsun17 [192.168.205.27]) by copfs01.mips.com (8.11.4/8.9.0) with ESMTP id g6PDTDb20911; Thu, 25 Jul 2002 15:29:14 +0200 (MEST) Sender: carstenl@mips.com Message-ID: <3D3FFD21.8DA26337@mips.com> Date: Thu, 25 Jul 2002 15:29:12 +0200 From: Carsten Langgaard X-Mailer: Mozilla 4.77 [en] (X11; U; SunOS 5.8 sun4u) X-Accept-Language: en MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: RFC: elf_check_arch() rework References: Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: 7bit "Maciej W. Rozycki" wrote: > On Wed, 24 Jul 2002, Carsten Langgaard wrote: > > > We at MIPS are in the process of making an ABI spec for all this, which > > is the intention that should be used by the tool-vendors. So please > > don't change the ELF header defines. > > It'd be better the spec matched the real world... Shouldn't it be the other way around, the real world should follow the spec ;-) The whole ELF header definition is just one big mess, because we are lacking a proper ABI spec. That's what has motivated us, to begin making this ABI spec. We have defined the e_flags this way: /* ELF header e_flags defines. MIPS architecture level. */ #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ #define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ #define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ #define EF_MIPS_ARCH_32R2 0x80000000 /* MIPS32 code. */ #define EF_MIPS_ARCH_64R2 0x90000000 /* MIPS64 code. */ The missing value 0x50000000, is because IRIX has defined a EF_MIPS_ARCH_6 and Algorithmics has a E_MIPS_ARCH_ALGOR_32, which has this value. If you look at the elf.h file in glibc, the you will see, it has the same values as the kernel. So I would prefer we fix that in binutils, I guess it not a problem as long as you don't have a toolchain that can generate MIPS32 or MIPS64 code. > > > I don't see that is wrong with checking the ISA level, I rather have an > > error telling me that I can't execute a certain ISA level than > > eventually getting a reserved instruction or something worse like > > something unpredictable. > > Well, -ENOEXEC in not any more useful than SIGILL -- with the latter you > have at least an idea what happened. The ISA check is not implemented for > any Linux port, so there no suitable hook in binfmt_*.c files. You might > propose an implementation if that's particularly important for you. > I would like a message telling me that I can't run this ISA level on the system. Imagined what would happen, if you execute mips3 code and execute ld/sd instructions on a mips32 kernel (but on a 64-bit processor), the kernel only save half the register and then everything could happen. > > > You are obviously right about the elf_check_arch in the 64-bit part of > > the kernel is broken. It's probably just be copied from the 32-bit part > > without changes, like a lot of the code in the 64-bit kernel is. > > Possibly, but it still makes me wonder why it wasn't adjusted at the time > binfmt_elf32.c was created... > > Maciej > > -- > + Maciej W. Rozycki, Technical University of Gdansk, Poland + > +--------------------------------------------------------------+ > + e-mail: macro@ds2.pg.gda.pl, PGP key available + -- _ _ ____ ___ Carsten Langgaard Mailto:carstenl@mips.com |\ /|||___)(___ MIPS Denmark Direct: +45 4486 5527 | \/ ||| ____) Lautrupvang 4B Switch: +45 4486 5555 TECHNOLOGIES 2750 Ballerup Fax...: +45 4486 5556 Denmark http://www.mips.com From macro@ds2.pg.gda.pl Thu Jul 25 16:20:30 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id QAA20995; Thu, 25 Jul 2002 16:20:30 +0200 (MET DST) Received-Date: Thu, 25 Jul 2002 16:20:30 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd020993; Thu Jul 25 16:20:23 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6PEKEM04716 for ; Thu, 25 Jul 2002 16:20:14 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id QAA03325; Thu, 25 Jul 2002 16:12:49 +0200 (MET DST) Date: Thu, 25 Jul 2002 16:12:48 +0200 (MET DST) From: "Maciej W. Rozycki" To: Carsten Langgaard cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] linux: RFC: elf_check_arch() rework In-Reply-To: <3D3FFD21.8DA26337@mips.com> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On Thu, 25 Jul 2002, Carsten Langgaard wrote: > Shouldn't it be the other way around, the real world should follow the spec > ;-) Where is the spec? If one were clearly available, the world would follow. Otherwise, having no other definite reference BFD is *the* spec, as usual (see Alpha/ELF for another example). > The whole ELF header definition is just one big mess, because we are lacking > a proper ABI spec. > That's what has motivated us, to begin making this ABI spec. > > We have defined the e_flags this way: > > /* ELF header e_flags defines. MIPS architecture level. */ > #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ > #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ > #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ > #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ > #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ > #define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ > #define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ > #define EF_MIPS_ARCH_32R2 0x80000000 /* MIPS32 code. */ > #define EF_MIPS_ARCH_64R2 0x90000000 /* MIPS64 code. */ > > The missing value 0x50000000, is because IRIX has defined a EF_MIPS_ARCH_6 > and Algorithmics has a E_MIPS_ARCH_ALGOR_32, which has this value. OK, but please show me a document. I only have a vague definition of values in the 0 - 3 range in the SGI's (n)64 ABI draft. There is no definition provided at the master SysV site (i.e. currently 'http://stage.caldera.com/developer/devspecs/') and the mipsabi.org site no longer exists. BTW, what are the two last entries meant to define, specifically, how do they differ from the preceding two? > If you look at the elf.h file in glibc, the you will see, it has the same > values as the kernel. I've seen it and currently it's broken, since real binaries (as created by binutils) define the values differently. > So I would prefer we fix that in binutils, I guess it not a problem as long > as you don't have a toolchain that can generate MIPS32 or MIPS64 code. Then please send a proposal to the binutils list ASAP, as code marked as MIPS32/64 can be already generated by binutils for quite some time now. I don't care personally, at least not yet, but others may do. > > Well, -ENOEXEC in not any more useful than SIGILL -- with the latter you > > have at least an idea what happened. The ISA check is not implemented for > > any Linux port, so there no suitable hook in binfmt_*.c files. You might > > propose an implementation if that's particularly important for you. > > I would like a message telling me that I can't run this ISA level on the > system. You need to add an error code to , then, and a suitable error message to be emitted by perror() and friends. Currently I see none that fits. I'm not sure if the various *nix standards provide any support for such functionality, but it might be worthwhile to add. > Imagined what would happen, if you execute mips3 code and execute ld/sd > instructions on a mips32 kernel (but on a 64-bit processor), the kernel only > save half the register and then everything could happen. The code would be rejected by elf_check_arch() as it would have to be marked as "n32" or "64" (or "o64", or a kind of EABI, but we don't support these) to make use of 64-bit registers. Gcc and gas won't emit 64-bit operations for any ISA (but they may make use of additional instructions defined by the ISA, as long as they operate on 32-bit data) if the selected ABI doesn't permit them (modulo possible bugs, certainly, as the 64-bit support bits are not tested sufficiently, yet, but that's the intent). If you handcode 64-bit operations in assembly, then you are fully responsible for the results and that won't be reflected in the ELF header anyway, as ".set" directives do not affect it. Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From macro@ds2.pg.gda.pl Mon Jul 29 15:25:48 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id PAA06894; Mon, 29 Jul 2002 15:25:48 +0200 (MET DST) Received-Date: Mon, 29 Jul 2002 15:25:48 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd006891; Mon Jul 29 15:25:38 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6TDPYM23898 for ; Mon, 29 Jul 2002 15:25:34 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id PAA25263; Mon, 29 Jul 2002 15:25:54 +0200 (MET DST) Date: Mon, 29 Jul 2002 15:25:53 +0200 (MET DST) From: "Maciej W. Rozycki" To: Johannes Stezenbach , Ralf Baechle , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: [patch] Oops and magic SysRq stack dump clean-ups In-Reply-To: Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Hello, I've reviewed the stack dumping code more thoroughly and here is the result. Please check if it's OK for you. Tested visually with oopses and + on MIPS/Linux and MIPS64/Linux. The idea is to fit as much data as possible in as little space as possible and at the same time lay the numbers out visually nicely so that manual copying of output from a terminal for ksymoops analysis is easier for a reader. Tools ignore spacing when processing such output anyway. Based somewhat on the i386 port. Addresses cast to signed longs, since they are such on MIPS (additionally, the code doesn't care anyway but the resulting source is smaller). Any objections? Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + patch-mips-2.4.19-rc1-20020719-mips-show_trace-8 diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/kernel/traps.c linux-mips-2.4.19-rc1-20020719/arch/mips/kernel/traps.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/kernel/traps.c 2002-07-08 16:46:04.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips/kernel/traps.c 2002-07-27 11:48:19.000000000 +0000 @@ -181,61 +181,95 @@ static inline void simulate_sc(struct pt } /* + * If the address is either in the .text section of the + * kernel, or in the vmalloc'ed module regions, it *may* + * be the address of a calling routine + */ + +#ifdef CONFIG_MODULES + +extern struct module *module_list; +extern struct module kernel_module; + +static inline int kernel_text_address(long addr) +{ + extern char _stext, _etext; + int retval = 0; + struct module *mod; + + if (addr >= (long) &_stext && addr <= (long) &_etext) + return 1; + + for (mod = module_list; mod != &kernel_module; mod = mod->next) { + /* mod_bound tests for addr being inside the vmalloc'ed + * module area. Of course it'd be better to test only + * for the .text subset... */ + if (mod_bound(addr, 0, mod)) { + retval = 1; + break; + } + } + + return retval; +} + +#else + +static inline int kernel_text_address(long addr) +{ + extern char _stext, _etext; + + return (addr >= (long) &_stext && addr <= (long) &_etext); +} + +#endif + +/* * This routine abuses get_user()/put_user() to reference pointers * with at least a bit of error checking ... */ -void show_stack(unsigned int *sp) +void show_stack(long *sp) { int i; - unsigned int *stack; - - stack = sp ? sp : (unsigned int *)&sp; - i = 0; + long stackdata; - printk("Stack:"); - while ((unsigned long) stack & (PAGE_SIZE - 1)) { - unsigned long stackdata; + sp = sp ? sp : (long *)&sp; - if (__get_user(stackdata, stack++)) { - printk(" (Bad stack address)"); + printk("Stack: "); + i = 1; + while ((long) sp & (PAGE_SIZE - 1)) { + if (i && ((i % 8) == 0)) + printk("\n"); + if (i > 40) { + printk(" ..."); break; } - printk(" %08lx", stackdata); - - if (++i > 40) { - printk(" ..."); + if (__get_user(stackdata, sp++)) { + printk(" (Bad stack address)"); break; } - if (i % 8 == 0) - printk("\n "); + printk(" %08lx", stackdata); + i++; } + printk("\n"); } -void show_trace(unsigned int *sp) +void show_trace(long *sp) { int i; - int column = 0; - unsigned int *stack; - unsigned long kernel_start, kernel_end; - unsigned long module_start, module_end; - extern char _stext, _etext; - - stack = sp ? sp : (unsigned int *) &sp; - i = 0; - - kernel_start = (unsigned long) &_stext; - kernel_end = (unsigned long) &_etext; - module_start = VMALLOC_START; - module_end = module_start + MODULE_RANGE; + long addr; - printk("\nCall Trace:"); + sp = sp ? sp : (long *) &sp; - while ((unsigned long) stack & (PAGE_SIZE -1)) { - unsigned long addr; + printk("Call Trace: "); + i = 1; + while ((long) sp & (PAGE_SIZE - 1)) { - if (__get_user(addr, stack++)) { + if (__get_user(addr, sp++)) { + if (i && ((i % 6) == 0)) + printk("\n"); printk(" (Bad stack address)\n"); break; } @@ -249,27 +283,24 @@ void show_trace(unsigned int *sp) * out the call path that was taken. */ - if ((addr >= kernel_start && addr < kernel_end) || - (addr >= module_start && addr < module_end)) { - - printk(" [<%08lx>]", addr); - if (column++ == 5) { + if (kernel_text_address(addr)) { + if (i && ((i % 6) == 0)) printk("\n"); - column = 0; - } - if (++i > 40) { + if (i > 40) { printk(" ..."); break; } + + printk(" [<%08lx>]", addr); + i++; } } - if (column != 0) - printk("\n"); + printk("\n"); } void show_trace_task(struct task_struct *tsk) { - show_trace((unsigned int *)tsk->thread.reg29); + show_trace((long *)tsk->thread.reg29); } void show_code(unsigned int *pc) @@ -321,8 +352,8 @@ void show_registers(struct pt_regs *regs show_regs(regs); printk("Process %s (pid: %d, stackpage=%08lx)\n", current->comm, current->pid, (unsigned long) current); - show_stack((unsigned int *) regs->regs[29]); - show_trace((unsigned int *) regs->regs[29]); + show_stack((long *) regs->regs[29]); + show_trace((long *) regs->regs[29]); show_code((unsigned int *) regs->cp0_epc); printk("\n"); } diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips64/kernel/traps.c linux-mips-2.4.19-rc1-20020719/arch/mips64/kernel/traps.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips64/kernel/traps.c 2002-07-08 16:46:08.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips64/kernel/traps.c 2002-07-27 11:43:15.000000000 +0000 @@ -70,60 +70,91 @@ int kstack_depth_to_print = 24; #define OPCODE 0xfc000000 /* + * If the address is either in the .text section of the + * kernel, or in the vmalloc'ed module regions, it *may* + * be the address of a calling routine + */ + +#ifdef CONFIG_MODULES + +extern struct module *module_list; +extern struct module kernel_module; + +static inline int kernel_text_address(long addr) +{ + extern char _stext, _etext; + int retval = 0; + struct module *mod; + + if (addr >= (long) &_stext && addr <= (long) &_etext) + return 1; + + for (mod = module_list; mod != &kernel_module; mod = mod->next) { + /* mod_bound tests for addr being inside the vmalloc'ed + * module area. Of course it'd be better to test only + * for the .text subset... */ + if (mod_bound(addr, 0, mod)) { + retval = 1; + break; + } + } + + return retval; +} + +#else + +static inline int kernel_text_address(long addr) +{ + extern char _stext, _etext; + + return (addr >= (long) &_stext && addr <= (long) &_etext); +} + +#endif + +/* * This routine abuses get_user()/put_user() to reference pointers * with at least a bit of error checking ... */ -void show_stack(unsigned long *sp) +void show_stack(long *sp) { int i; - unsigned long *stack; - - stack = sp; - i = 0; + long stackdata; printk("Stack:"); - while ((unsigned long) stack & (PAGE_SIZE - 1)) { - unsigned long stackdata; - - if (__get_user(stackdata, stack++)) { - printk(" (Bad stack address)"); + i = 0; + while ((long) sp & (PAGE_SIZE - 1)) { + if (i && ((i % 4) == 0)) + printk("\n "); + if (i > 40) { + printk(" ..."); break; } - printk(" %016lx", stackdata); - - if (++i > 40) { - printk(" ..."); + if (__get_user(stackdata, sp++)) { + printk(" (Bad stack address)"); break; } - if (i % 4 == 0) - printk("\n "); + printk(" %016lx", stackdata); + i++; } + printk("\n"); } -void show_trace(unsigned long *sp) +void show_trace(long *sp) { int i; - unsigned long *stack; - unsigned long kernel_start, kernel_end; - unsigned long module_start, module_end; - extern char _stext, _etext; + long addr; - stack = sp; + printk("Call Trace:"); i = 0; + while ((long) sp & (PAGE_SIZE - 1)) { - kernel_start = (unsigned long) &_stext; - kernel_end = (unsigned long) &_etext; - module_start = VMALLOC_START; - module_end = module_start + MODULE_RANGE; - - printk("\nCall Trace:"); - - while ((unsigned long) stack & (PAGE_SIZE - 1)) { - unsigned long addr; - - if (__get_user(addr, stack++)) { + if (__get_user(addr, sp++)) { + if (i && ((i % 3) == 0)) + printk("\n "); printk(" (Bad stack address)\n"); break; } @@ -137,25 +168,24 @@ void show_trace(unsigned long *sp) * out the call path that was taken. */ - if ((addr >= kernel_start && addr < kernel_end) || - (addr >= module_start && addr < module_end)) { - - /* Since our kernel is still at KSEG0, - * truncate the address so that ksymoops - * understands it. - */ - printk(" [<%08x>]", (unsigned int) addr); - if (++i > 40) { + if (kernel_text_address(addr)) { + if (i && ((i % 3) == 0)) + printk("\n "); + if (i > 40) { printk(" ..."); break; } + + printk(" [<%016lx>]", addr); + i++; } } + printk("\n"); } void show_trace_task(struct task_struct *tsk) { - show_trace((unsigned long *)tsk->thread.reg29); + show_trace((long *)tsk->thread.reg29); } @@ -224,8 +254,8 @@ void show_registers(struct pt_regs *regs show_regs(regs); printk("Process %s (pid: %d, stackpage=%016lx)\n", current->comm, current->pid, (unsigned long) current); - show_stack((unsigned long *) regs->regs[29]); - show_trace((unsigned long *) regs->regs[29]); + show_stack((long *) regs->regs[29]); + show_trace((long *) regs->regs[29]); show_code((unsigned int *) regs->cp0_epc); printk("\n"); } From macro@ds2.pg.gda.pl Mon Jul 29 16:03:18 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id QAA12468; Mon, 29 Jul 2002 16:03:18 +0200 (MET DST) Received-Date: Mon, 29 Jul 2002 16:03:18 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd012466; Mon Jul 29 16:03:13 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6TE39M24356 for ; Mon, 29 Jul 2002 16:03:09 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id QAA25873; Mon, 29 Jul 2002 16:03:31 +0200 (MET DST) Date: Mon, 29 Jul 2002 16:03:31 +0200 (MET DST) From: "Maciej W. Rozycki" Reply-To: "Maciej W. Rozycki" To: Ralf Baechle , Carsten Langgaard , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: [patch] Fix elf_check_arch() for MIPS and MIPS64 Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Hello, I've found no problems with the patch. This version differs from the previous one by minor grammar updates in comments only. If any specification changes happen later, we may update the sources accordingly. For now the patch lets binaries be properly identified and either handled or rejected. The MIPS port handles (o)32 binaries only, so binfmt_elf only accepts binaries either marked as such or unmarked at all (for compatibility with old tools). The MIPS64 port handles both n32/(n)64 and (o)32 binaries. The former ones are either ELF64 (64) or are marked ABI2 (n32) and they are handled by binfmt_elf. The latter ones are handled by binfmt_elf32. Please remember, we do not *create* these numbers, we only *interpret* them in binaries created elsewhere, so we'd better agree with them. OK to apply? Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + patch-mips-2.4.19-rc1-20020719-mips64-elf-3 diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips64/kernel/binfmt_elf32.c linux-mips-2.4.19-rc1-20020719/arch/mips64/kernel/binfmt_elf32.c --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips64/kernel/binfmt_elf32.c 2002-06-29 03:01:44.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/arch/mips64/kernel/binfmt_elf32.c 2002-07-23 23:15:27.000000000 +0000 @@ -27,8 +27,26 @@ typedef elf_greg_t elf_gregset_t[ELF_NGR typedef double elf_fpreg_t; typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; -#define elf_check_arch(x) \ - ((x)->e_machine == EM_MIPS) +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(hdr) \ +({ \ + int __res = 1; \ + struct elfhdr *__h = (hdr); \ + \ + if (__h->e_machine != EM_MIPS) \ + __res = 0; \ + if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ + __res = 0; \ + if ((__h->e_flags & EF_MIPS_ABI2) != 0) \ + __res = 0; \ + if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ + ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ + __res = 0; \ + \ + __res; \ +}) #define TASK32_SIZE 0x80000000UL #undef ELF_ET_DYN_BASE diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/include/asm-mips/elf.h linux-mips-2.4.19-rc1-20020719/include/asm-mips/elf.h --- linux-mips-2.4.19-rc1-20020719.macro/include/asm-mips/elf.h 2002-04-25 02:57:43.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/include/asm-mips/elf.h 2002-07-23 22:50:48.000000000 +0000 @@ -16,10 +16,11 @@ #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -#define EF_MIPS_ARCH_32R2 0x80000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64R2 0x90000000 /* MIPS64 code. */ +#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ +#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ +/* The ABI of a file. */ +#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ +#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */ typedef unsigned long elf_greg_t; typedef elf_greg_t elf_gregset_t[ELF_NGREG]; @@ -37,10 +38,12 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_N \ if (__h->e_machine != EM_MIPS) \ __res = 0; \ - if (((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_1) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_2) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_32) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_32R2)) \ + if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ + __res = 0; \ + if ((__h->e_flags & EF_MIPS_ABI2) != 0) \ + __res = 0; \ + if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ + ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ __res = 0; \ \ __res; \ diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/include/asm-mips64/elf.h linux-mips-2.4.19-rc1-20020719/include/asm-mips64/elf.h --- linux-mips-2.4.19-rc1-20020719.macro/include/asm-mips64/elf.h 2002-07-22 08:49:30.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/include/asm-mips64/elf.h 2002-07-23 23:12:28.000000000 +0000 @@ -9,21 +9,23 @@ #include #include -#ifndef ELF_ARCH -/* ELF register definitions */ -#define ELF_NGREG 45 -#define ELF_NFPREG 33 - -/* ELF header e_flags defines. MIPS architecture level. */ +/* ELF header e_flags defines. */ +/* MIPS architecture level. */ #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -#define EF_MIPS_ARCH_32R2 0x80000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64R2 0x90000000 /* MIPS64 code. */ +#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ +#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ +/* The ABI of a file. */ +#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ +#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */ + +#ifndef ELF_ARCH +/* ELF register definitions */ +#define ELF_NGREG 45 +#define ELF_NFPREG 33 typedef unsigned long elf_greg_t; typedef elf_greg_t elf_gregset_t[ELF_NGREG]; @@ -41,14 +43,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_N \ if (__h->e_machine != EM_MIPS) \ __res = 0; \ - if (sizeof(elf_caddr_t) == 8 && \ - __h->e_ident[EI_CLASS] == ELFCLASS32) \ - __res = 0; \ - if (((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_1) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_2) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_32) && \ - ((__h->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_32R2)) \ - __res = 0; \ + if ((__h->e_ident[EI_CLASS] == ELFCLASS32) && \ + ((__h->e_flags & EF_MIPS_ABI2) == 0)) \ + __res = 0; \ \ __res; \ }) diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/include/linux/elf.h linux-mips-2.4.19-rc1-20020719/include/linux/elf.h --- linux-mips-2.4.19-rc1-20020719.macro/include/linux/elf.h 2002-07-22 08:49:30.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020719/include/linux/elf.h 2002-07-23 22:18:54.000000000 +0000 @@ -37,6 +37,9 @@ typedef __s64 Elf64_Sxword; #define EF_MIPS_NOREORDER 0x00000001 #define EF_MIPS_PIC 0x00000002 #define EF_MIPS_CPIC 0x00000004 +#define EF_MIPS_ABI2 0x00000020 +#define EF_MIPS_32BITMODE 0x00000100 +#define EF_MIPS_ABI 0x0000f000 #define EF_MIPS_ARCH 0xf0000000 /* These constants define the different elf file types */ From macro@ds2.pg.gda.pl Mon Jul 29 16:29:08 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id QAA18455; Mon, 29 Jul 2002 16:29:08 +0200 (MET DST) Received-Date: Mon, 29 Jul 2002 16:29:08 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd018453; Mon Jul 29 16:29:07 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6TET3M24813 for ; Mon, 29 Jul 2002 16:29:03 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id QAA26325; Mon, 29 Jul 2002 16:29:35 +0200 (MET DST) Date: Mon, 29 Jul 2002 16:29:35 +0200 (MET DST) From: "Maciej W. Rozycki" To: Ralf Baechle , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: [update] [patch] linux: Cache coherency fixes In-Reply-To: Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Hello, The following patch fixes all the places the default caching policy is used but various local hacks are coded. Also the sc coherency algorithm is configured for R4k processors which was previously left as set (or not) by the firmware. A side effect is is created and all conditional CPU options are set somehow. Tested on an R4400SC (for both MIPS and MIPS64) and on an R3400. Admittedly, CONF_CM_DEFAULT is defined in a bit weird way, but I couldn't figure any better one that wouldn't result in a serious but unnecessary header bloat. If anyone has a better idea, please share any suggestions here. OK to apply? Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + patch-mips-2.4.19-rc1-20020726-cache-coherency-5 diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/config-shared.in linux-mips-2.4.19-rc1-20020726/arch/mips/config-shared.in --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/config-shared.in 2002-07-25 20:11:36.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips/config-shared.in 2002-07-27 22:14:21.000000000 +0000 @@ -403,6 +403,10 @@ fi if [ "$CONFIG_MIPS_AU1000" != "y" ]; then define_bool CONFIG_MIPS_AU1000 n fi + +if [ "$CONFIG_SMP" != "y" ]; then + define_bool CONFIG_SMP n +fi endmenu mainmenu_option next_comment @@ -492,6 +496,17 @@ if [ "$CONFIG_CPU_R3000" = "y" ]; then else define_bool CONFIG_CPU_HAS_SYNC y fi +if [ "$CONFIG_CPU_R4X00" = "y" -o "$CONFIG_CPU_SB1" = "y" ]; then + define_bool CONFIG_CPU_CACHE_COHERENCY $CONFIG_SMP +else + define_bool CONFIG_CPU_CACHE_COHERENCY n +fi +if [ "$CONFIG_VTAG_ICACHE" != "y" ]; then + define_bool CONFIG_VTAG_ICACHE n +fi +if [ "$CONFIG_CPU_HAS_PREFETCH" != "y" ]; then + define_bool CONFIG_CPU_HAS_PREFETCH n +fi endmenu mainmenu_option next_comment diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-mips32.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-mips32.c --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-mips32.c 2002-05-30 02:57:43.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-mips32.c 2002-07-27 22:59:42.000000000 +0000 @@ -657,11 +657,7 @@ void __init ld_mmu_mips32(void) { unsigned long config = read_32bit_cp0_register(CP0_CONFIG); -#ifdef CONFIG_MIPS_UNCACHED - change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); -#else - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); -#endif + change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); probe_icache(config); probe_dcache(config); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-r4k.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-r4k.c --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-r4k.c 2002-07-15 02:57:47.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-r4k.c 2002-07-27 22:59:22.000000000 +0000 @@ -1480,11 +1480,7 @@ void __init ld_mmu_r4xx0(void) { unsigned long config = read_32bit_cp0_register(CP0_CONFIG); -#ifdef CONFIG_MIPS_UNCACHED - change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); -#else - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); -#endif + change_cp0_config(CONF_CM_CMASK | CONF_CU, CONF_CM_DEFAULT); probe_icache(config); probe_dcache(config); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-r5432.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-r5432.c --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-r5432.c 2001-12-01 05:26:01.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-r5432.c 2002-07-27 23:01:23.000000000 +0000 @@ -455,7 +455,7 @@ void __init ld_mmu_r5432(void) { unsigned long config = read_32bit_cp0_register(CP0_CONFIG); - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); + change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); probe_icache(config); probe_dcache(config); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-rm7k.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-rm7k.c --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-rm7k.c 2002-05-30 02:57:46.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-rm7k.c 2002-07-27 23:02:21.000000000 +0000 @@ -319,9 +319,7 @@ void __init ld_mmu_rm7k(void) : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); } -#ifndef CONFIG_MIPS_UNCACHED - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); -#endif + change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); probe_icache(config); probe_dcache(config); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-sb1.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-sb1.c --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-sb1.c 2002-05-30 02:57:46.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-sb1.c 2002-07-27 23:04:17.000000000 +0000 @@ -519,6 +519,6 @@ void ld_mmu_sb1(void) _flush_cache_sigtramp = sb1_flush_cache_sigtramp; _flush_icache_all = sb1_flush_icache_all; - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_COW); + change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); flush_cache_all(); } diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-tx49.c linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-tx49.c --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips/mm/c-tx49.c 2002-05-30 02:57:46.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips/mm/c-tx49.c 2002-07-27 23:05:01.000000000 +0000 @@ -387,11 +387,7 @@ void __init ld_mmu_tx49(void) if (mips_configk0 != -1) change_cp0_config(CONF_CM_CMASK, mips_configk0); else -#ifdef CONFIG_MIPS_UNCACHED - change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); -#else - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); -#endif + change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); probe_icache(config); probe_dcache(config); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/c-mips64.c linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/c-mips64.c --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/c-mips64.c 2002-07-24 16:12:11.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/c-mips64.c 2002-07-27 23:07:05.000000000 +0000 @@ -654,11 +654,7 @@ void __init ld_mmu_mips64(void) { unsigned long config = read_32bit_cp0_register(CP0_CONFIG); -#ifdef CONFIG_MIPS_UNCACHED - change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); -#else - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); -#endif + change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); probe_icache(config); probe_dcache(config); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/c-sb1.c linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/c-sb1.c --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/c-sb1.c 2002-05-30 02:57:51.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/c-sb1.c 2002-07-27 23:07:42.000000000 +0000 @@ -518,6 +518,6 @@ void ld_mmu_sb1(void) _flush_cache_sigtramp = sb1_flush_cache_sigtramp; _flush_icache_all = sb1_flush_icache_all; - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_COW); + change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); flush_cache_all(); } diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/r4xx0.c linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/r4xx0.c --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/r4xx0.c 2002-06-20 02:57:39.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/r4xx0.c 2002-07-27 23:09:09.000000000 +0000 @@ -2268,11 +2268,7 @@ void __init ld_mmu_r4xx0(void) { unsigned long config = read_32bit_cp0_register(CP0_CONFIG); -#ifdef CONFIG_MIPS_UNCACHED - change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); -#else - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); -#endif /* UNCACHED */ + change_cp0_config(CONF_CM_CMASK | CONF_CU, CONF_CM_DEFAULT); probe_icache(config); probe_dcache(config); diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips/mipsregs.h linux-mips-2.4.19-rc1-20020726/include/asm-mips/mipsregs.h --- linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips/mipsregs.h 2002-07-21 19:21:19.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/include/asm-mips/mipsregs.h 2002-07-27 22:57:03.000000000 +0000 @@ -374,6 +374,7 @@ #define CONF_CM_CACHABLE_CUW 6 #define CONF_CM_CACHABLE_ACCELERATED 7 #define CONF_CM_CMASK 7 +#define CONF_CU (1 << 3) #define CONF_DB (1 << 4) #define CONF_IB (1 << 5) #define CONF_SC (1 << 17) diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips/pgtable-bits.h linux-mips-2.4.19-rc1-20020726/include/asm-mips/pgtable-bits.h --- linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips/pgtable-bits.h 2002-06-30 17:18:30.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/include/asm-mips/pgtable-bits.h 2002-07-27 23:00:05.000000000 +0000 @@ -12,7 +12,8 @@ #include -/* Note that we shift the lower 32bits of each EntryLo[01] entry +/* + * Note that we shift the lower 32bits of each EntryLo[01] entry * 6 bits to the left. That way we can convert the PFN into the * physical address by a single 'and' operation and gain 6 additional * bits for storing information which isn't present in a normal @@ -74,9 +75,9 @@ #define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ #define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ #define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00 only */ -#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00 only */ -#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00 only */ +#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ #define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ #endif @@ -87,12 +88,21 @@ #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) -#ifdef CONFIG_MIPS_UNCACHED + +#if defined(CONFIG_MIPS_UNCACHED) + #define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED -#elif CONFIG_CPU_SB1 + +#elif defined(CONFIG_CPU_CACHE_COHERENCY) + #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW + #else + #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT + #endif +#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) + #endif /* _ASM_CACHINGMODES_H */ diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/mipsregs.h linux-mips-2.4.19-rc1-20020726/include/asm-mips64/mipsregs.h --- linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/mipsregs.h 2002-06-29 03:02:05.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/include/asm-mips64/mipsregs.h 2002-07-27 22:57:22.000000000 +0000 @@ -374,6 +374,7 @@ #define CONF_CM_CACHABLE_CUW 6 #define CONF_CM_CACHABLE_ACCELERATED 7 #define CONF_CM_CMASK 7 +#define CONF_CU (1 << 3) #define CONF_DB (1 << 4) #define CONF_IB (1 << 5) #define CONF_SC (1 << 17) diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/pgtable-bits.h linux-mips-2.4.19-rc1-20020726/include/asm-mips64/pgtable-bits.h --- linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/pgtable-bits.h 1970-01-01 00:00:00.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/include/asm-mips64/pgtable-bits.h 2002-07-27 23:00:24.000000000 +0000 @@ -0,0 +1,79 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 2001 by Ralf Baechle at alii + * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. + * Copyright (C) 2002 Maciej W. Rozycki + */ +#ifndef __ASM_MIPS64_PGTABLE_BITS_H +#define __ASM_MIPS64_PGTABLE_BITS_H + +#include + +/* + * Note that we shift the lower 32bits of each EntryLo[01] entry + * 6 bits to the left. That way we can convert the PFN into the + * physical address by a single 'and' operation and gain 6 additional + * bits for storing information which isn't present in a normal + * MIPS page table. + * + * Similar to the Alpha port, we need to keep track of the ref + * and mod bits in software. We have a software "yeah you can read + * from this page" bit, and a hardware one which actually lets the + * process read from the page. On the same token we have a software + * writable bit and the real hardware one which actually lets the + * process write to the page, this keeps a mod bit via the hardware + * dirty bit. + * + * Certain revisions of the R4000 and R5000 have a bug where if a + * certain sequence occurs in the last 3 instructions of an executable + * page, and the following page is not mapped, the cpu can do + * unpredictable things. The code (when it is written) to deal with + * this problem will be in the update_mmu_cache() code for the r4k. + */ +#define _PAGE_PRESENT (1<<0) /* implemented in software */ +#define _PAGE_READ (1<<1) /* implemented in software */ +#define _PAGE_WRITE (1<<2) /* implemented in software */ +#define _PAGE_ACCESSED (1<<3) /* implemented in software */ +#define _PAGE_MODIFIED (1<<4) /* implemented in software */ +#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ +#define _PAGE_GLOBAL (1<<6) +#define _PAGE_VALID (1<<7) +#define _PAGE_SILENT_READ (1<<7) /* synonym */ +#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ +#define _PAGE_SILENT_WRITE (1<<8) +#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ +#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ +#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ +#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ +#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ +#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ +#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ +#define _CACHE_MASK (7<<9) + +#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) +#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) + +#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) + + +#if defined(CONFIG_MIPS_UNCACHED) + +#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED + +#elif defined(CONFIG_CPU_CACHE_COHERENCY) + +#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW + +#else + +#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT + +#endif + +#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) + +#endif /* __ASM_MIPS64_PGTABLE_BITS_H */ diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/pgtable.h linux-mips-2.4.19-rc1-20020726/include/asm-mips64/pgtable.h --- linux-mips-2.4.19-rc1-20020726.macro/include/asm-mips64/pgtable.h 2002-07-08 16:46:37.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/include/asm-mips64/pgtable.h 2002-07-27 23:31:48.000000000 +0000 @@ -155,64 +155,9 @@ extern void (*_flush_icache_page)(struct #define VMALLOC_END \ (VMALLOC_START + ((1 << PGD_ORDER) * PTRS_PER_PTE * PAGE_SIZE)) -/* - * Note that we shift the lower 32bits of each EntryLo[01] entry - * 6 bits to the left. That way we can convert the PFN into the - * physical address by a single 'and' operation and gain 6 additional - * bits for storing information which isn't present in a normal - * MIPS page table. - * - * Similar to the Alpha port, we need to keep track of the ref - * and mod bits in software. We have a software "yeah you can read - * from this page" bit, and a hardware one which actually lets the - * process read from the page. On the same token we have a software - * writable bit and the real hardware one which actually lets the - * process write to the page, this keeps a mod bit via the hardware - * dirty bit. - * - * Certain revisions of the R4000 and R5000 have a bug where if a - * certain sequence occurs in the last 3 instructions of an executable - * page, and the following page is not mapped, the cpu can do - * unpredictable things. The code (when it is written) to deal with - * this problem will be in the update_mmu_cache() code for the r4k. - */ -#define _PAGE_PRESENT (1<<0) /* implemented in software */ -#define _PAGE_READ (1<<1) /* implemented in software */ -#define _PAGE_WRITE (1<<2) /* implemented in software */ -#define _PAGE_ACCESSED (1<<3) /* implemented in software */ -#define _PAGE_MODIFIED (1<<4) /* implemented in software */ -#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ -#define _PAGE_GLOBAL (1<<6) -#define _PAGE_VALID (1<<7) -#define _PAGE_SILENT_READ (1<<7) /* synonym */ -#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ -#define _PAGE_SILENT_WRITE (1<<8) -#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ -#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ -#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00 only */ -#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00 only */ -#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00 only */ -#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ -#define _CACHE_MASK (7<<9) - -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) - -#ifdef CONFIG_MIPS_UNCACHED -#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED -#else /* ! UNCACHED */ -#ifdef CONFIG_SGI_IP22 -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT -#else /* ! IP22 */ -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW -#endif /* IP22 */ -#endif /* UNCACHED */ +#include -#define PAGE_NONE __pgprot(_PAGE_PRESENT | PAGE_CACHABLE_DEFAULT) +#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ PAGE_CACHABLE_DEFAULT) #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ @@ -222,7 +167,7 @@ extern void (*_flush_icache_page)(struct #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT) #define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - _CACHE_UNCACHED) + PAGE_CACHABLE_DEFAULT) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) From macro@ds2.pg.gda.pl Mon Jul 29 17:23:28 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id RAA24402; Mon, 29 Jul 2002 17:23:28 +0200 (MET DST) Received-Date: Mon, 29 Jul 2002 17:23:28 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd024400; Mon Jul 29 17:23:21 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6TFNGM25552 for ; Mon, 29 Jul 2002 17:23:17 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id RAA27091; Mon, 29 Jul 2002 17:23:46 +0200 (MET DST) Date: Mon, 29 Jul 2002 17:23:43 +0200 (MET DST) From: "Maciej W. Rozycki" Reply-To: "Maciej W. Rozycki" To: Ralf Baechle , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: [patch] MIPS64 R4k TLB refill CP0 hazards Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Hello, The except_vec1_r4k() function in arch/mips64/mm/tlbex-r4k.S is quite new and seems specifically written to handle the EntryLo vs "tlbwr" R4k CP0 hazard by adding an extra "nop" before the "tlbwr" beyond what except_vec1_r10k() puts. Unfortunately, it does not work on my R4400SC anyway. OTOH, the 32-bit MIPS version does, so I tried bits from that for MIPS64 and now the function works. Here is the resulting patch. Since barring the hazard fragment the functions are identical, I removed the redundant part and made except_vec1_r4k() make use of the LOAD_PTE2 and PTE_RELOAD macros. OK to apply? Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + patch-mips-2.4.19-rc1-20020726-mips64-tlbex-r4k-1 diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/tlbex-r4k.S linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/tlbex-r4k.S --- linux-mips-2.4.19-rc1-20020726.macro/arch/mips64/mm/tlbex-r4k.S 2002-07-25 02:57:02.000000000 +0000 +++ linux-mips-2.4.19-rc1-20020726/arch/mips64/mm/tlbex-r4k.S 2002-07-28 22:27:08.000000000 +0000 @@ -5,6 +5,7 @@ * * Copyright (C) 2000 Silicon Graphics, Inc. * Written by Ulf Carlsson (ulfc@engr.sgi.com) + * Copyright (C) 2002 Maciej W. Rozycki */ #include #include @@ -23,7 +24,7 @@ * that caused the fault in in PTR. */ - .macro LOAD_PTE2, ptr, tmp + .macro LOAD_PTE2, ptr, tmp, kaddr #ifdef CONFIG_SMP dmfc0 \ptr, CP0_CONTEXT dmfc0 \tmp, CP0_BADVADDR @@ -32,8 +33,8 @@ dmfc0 \tmp, CP0_BADVADDR dla \ptr, pgd_current #endif - bltz \tmp, kaddr - ld \ptr, (\ptr) + bltz \tmp, \kaddr + ld \ptr, (\ptr) dsrl \tmp, (PGDIR_SHIFT-3) # get pgd offset in bytes andi \tmp, ((PTRS_PER_PGD - 1)<<3) daddu \ptr, \tmp # add in pgd offset @@ -75,34 +76,16 @@ FEXPORT(except_vec0) .align 5 LEAF(except_vec1_r4k) .set noat - dla k1, pgd_current - dmfc0 k0, CP0_BADVADDR - ld k1, (k1) - bltz k0, vmaddr - dsrl k0, (PGDIR_SHIFT-3) # get pgd offset in bytes - andi k0, ((PTRS_PER_PGD - 1)<<3) - daddu k1, k0 # add in pgd offset - dmfc0 k0, CP0_BADVADDR - ld k1, (k1) # get pmd pointer - dsrl k0, (PMD_SHIFT-3) # get pmd offset in bytes - andi k0, ((PTRS_PER_PMD - 1)<<3) - daddu k1, k0 # add in pmd offset - dmfc0 k0, CP0_XCONTEXT - andi k0, 0xff0 # get pte offset - ld k1, (k1) # get pte pointer - daddu k1, k0 - ld k0, 0(k1) # get even pte - ld k1, 8(k1) # get odd pte - dsrl k0, 6 # convert to entrylo0 - dmtc0 k0, CP0_ENTRYLO0 # load it - dsrl k1, 6 # convert to entrylo1 - dmtc0 k1, CP0_ENTRYLO1 # load it - nop # Need 2 cycles between mtc0 - nop # and tlbwr (CP0 hazard). + LOAD_PTE2 k1 k0 9f + ld k0, 0(k1) # get even pte + ld k1, 8(k1) # get odd pte + PTE_RELOAD k0 k1 + b 1f tlbwr +1: nop eret -vmaddr: +9: dla k0, handle_vmalloc_address jr k0 nop @@ -116,14 +99,14 @@ END(except_vec1_r4k) .align 5 LEAF(except_vec1_r10k) .set noat - LOAD_PTE2 k1 k0 + LOAD_PTE2 k1 k0 9f ld k0, 0(k1) # get even pte ld k1, 8(k1) # get odd pte PTE_RELOAD k0 k1 nop tlbwr eret -kaddr: +9: dla k0, handle_vmalloc_address # MAPPED kernel needs this jr k0 nop From js@convergence.de Mon Jul 29 18:03:19 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id SAA00260; Mon, 29 Jul 2002 18:03:19 +0200 (MET DST) Received-Date: Mon, 29 Jul 2002 18:03:19 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd000258; Mon Jul 29 18:03:10 2002 Received: from hell (buserror-extern.convergence.de [212.84.236.66]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6TG36M26164 for ; Mon, 29 Jul 2002 18:03:06 +0200 (CEST) Received: from js by hell with local (Exim 3.35 #1 (Debian)) id 17ZCyu-0000jd-00; Mon, 29 Jul 2002 18:02:48 +0200 Date: Mon, 29 Jul 2002 18:02:48 +0200 From: Johannes Stezenbach To: "Maciej W. Rozycki" Cc: Ralf Baechle , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] Oops and magic SysRq stack dump clean-ups Message-ID: <20020729160248.GA2800@convergence.de> Mail-Followup-To: Johannes Stezenbach , "Maciej W. Rozycki" , Ralf Baechle , linux-mips@fnet.fr, linux-mips@oss.sgi.com References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4i On Mon, Jul 29, 2002 at 03:25:53PM +0200, Maciej W. Rozycki wrote: > I've reviewed the stack dumping code more thoroughly and here is the > result. Please check if it's OK for you. Tested visually with oopses and > + on MIPS/Linux and MIPS64/Linux. The idea is to fit as much > data as possible in as little space as possible and at the same time lay > the numbers out visually nicely so that manual copying of output from a > terminal for ksymoops analysis is easier for a reader. Tools ignore > spacing when processing such output anyway. > > Based somewhat on the i386 port. Addresses cast to signed longs, since > they are such on MIPS (additionally, the code doesn't care anyway but the > resulting source is smaller). Any objections? Nope, patch and its output look good to me. Johannes From ralf@linux-mips.net Tue Jul 30 13:30:49 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id NAA17599; Tue, 30 Jul 2002 13:30:49 +0200 (MET DST) Received-Date: Tue, 30 Jul 2002 13:30:49 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd017597; Tue Jul 30 13:30:42 2002 Received: from dea.linux-mips.net (shaft19-f237.dialo.tiscali.de [62.246.19.237]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6UBUaM00905 for ; Tue, 30 Jul 2002 13:30:36 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6UBTtp28422; Tue, 30 Jul 2002 13:29:55 +0200 Date: Tue, 30 Jul 2002 13:29:55 +0200 From: Ralf Baechle To: Carsten Langgaard Cc: "Maciej W. Rozycki" , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards Message-ID: <20020730132955.A28302@dea.linux-mips.net> References: <3D45A13E.79C882B5@mips.com> <3D46393D.37D36612@mips.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: <3D46393D.37D36612@mips.com>; from carstenl@mips.com on Tue, Jul 30, 2002 at 08:59:17AM +0200 On Tue, Jul 30, 2002 at 08:59:17AM +0200, Carsten Langgaard wrote: > We have been discussing this before, but I really don't like the idea of > solving the hazard problem with a branch. The branch will on some CPUs > (especially if they have a long pipeline) be a much bigger penalty than > we actually wants to solve the hazard. On other CPU (with branch > prediction) we may not even solve the hazard problem. The branch - which is used by other OSes btw. - for the R4000 / R4400 where this kind of taken branch implies a total delay of three cycles. One for the branch delay slot plus two extra cycles for the killed instructions following the branch delay slot. For R4600, R4700, R5000 and a bunch of derivates I've verified that according to the documentation this extra penalty of two cycles does not exist nor we need two extra cycles to handle the hazard. In other words the branch trick - which also is used by some other commercial OS btw. - is providing best possible performance on a wide range of processors. > The 'nop' I used is not the solution either, instead we should use > 'ssnop' instructions, which will make sure we also solve the hazard > problem on superscalar CPUs. We also need to have a hazard barrier in > the code labeled "not_vmalloc". Above trick was written with single issue CPUs in mind. I'd have to verify the pipeline timing again against CPU manuals but off my memory at least SB1 and R1x000 are fully protected against the hazards in question. Ralf From kevink@mips.com Tue Jul 30 14:39:19 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id OAA22441; Tue, 30 Jul 2002 14:39:19 +0200 (MET DST) Received-Date: Tue, 30 Jul 2002 14:39:19 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd022439; Tue Jul 30 14:39:13 2002 Received: from mx2.mips.com (mx2.mips.com [206.31.31.227]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6UCd9M01356 for ; Tue, 30 Jul 2002 14:39:10 +0200 (CEST) Received: from newman.mips.com (ns-dmz [206.31.31.225]) by mx2.mips.com (8.12.5/8.12.5) with ESMTP id g6UCcUXb017031; Tue, 30 Jul 2002 05:38:30 -0700 (PDT) Received: from grendel (grendel [192.168.236.16]) by newman.mips.com (8.9.3/8.9.0) with SMTP id FAA04230; Tue, 30 Jul 2002 05:38:30 -0700 (PDT) Message-ID: <00f801c237c6$29cabd00$10eca8c0@grendel> From: "Kevin D. Kissell" To: "Ralf Baechle" , "Carsten Langgaard" Cc: "Maciej W. Rozycki" , , References: <3D45A13E.79C882B5@mips.com> <3D46393D.37D36612@mips.com> <20020730132955.A28302@dea.linux-mips.net> Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards Date: Tue, 30 Jul 2002 14:39:24 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4910.0300 From: "Ralf Baechle" > On Tue, Jul 30, 2002 at 08:59:17AM +0200, Carsten Langgaard wrote: > > > We have been discussing this before, but I really don't like the idea of > > solving the hazard problem with a branch. The branch will on some CPUs > > (especially if they have a long pipeline) be a much bigger penalty than > > we actually wants to solve the hazard. On other CPU (with branch > > prediction) we may not even solve the hazard problem. > > The branch - which is used by other OSes btw. - for the R4000 / R4400 where > this kind of taken branch implies a total delay of three cycles. One for > the branch delay slot plus two extra cycles for the killed instructions > following the branch delay slot. For R4600, R4700, R5000 and a bunch of > derivates I've verified that according to the documentation this extra > penalty of two cycles does not exist nor we need two extra cycles to handle > the hazard. In other words the branch trick - which also is used by > some other commercial OS btw. - is providing best possible performance on > a wide range of processors. Which would be a fairly compelling argument if (a) we were constrained for some reason to only have one handler and (b) the majority of MIPS Linux systems being built had R4000/4400/4600/4700/5000 CPUs in them. But neither of those assumptions is true. I don't see any cases in the kernel of assembler functions being put into the .init segment of the kernel image, but I would think that it could be (and anyway should be) done with the various exception vectors, and in any case they are dynamically installed based on the detected CPU. If people using old workstations want to use a branch-based timing hack in their TLB handlers, that's all well and good. But there is no guarantee that the trick will work on all future (or even current) MIPS CPUs, and I agree with Carsten that it is inappropriate for the generic or default MIPS32 handlers. I guess we need to propose a patch to allow the Indy/Decstation crowd to retain their branch-based scheme, but to quarantine it from the rest of the MIPS/Linux universe. Regards, Kevin K. From macro@ds2.pg.gda.pl Tue Jul 30 14:44:19 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id OAA25564; Tue, 30 Jul 2002 14:44:19 +0200 (MET DST) Received-Date: Tue, 30 Jul 2002 14:44:19 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd025408; Tue Jul 30 14:44:11 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6UCi7M01644 for ; Tue, 30 Jul 2002 14:44:07 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id OAA17643; Tue, 30 Jul 2002 14:44:32 +0200 (MET DST) Date: Tue, 30 Jul 2002 14:44:32 +0200 (MET DST) From: "Maciej W. Rozycki" To: Carsten Langgaard cc: Ralf Baechle , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards In-Reply-To: <3D4681DE.7BE793C9@mips.com> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On Tue, 30 Jul 2002, Carsten Langgaard wrote: > > The branch - which is used by other OSes btw. - for the R4000 / R4400 where > > this kind of taken branch implies a total delay of three cycles. One for > > the branch delay slot plus two extra cycles for the killed instructions > > following the branch delay slot. For R4600, R4700, R5000 and a bunch of > > derivates I've verified that according to the documentation this extra > > penalty of two cycles does not exist nor we need two extra cycles to handle > > the hazard. In other words the branch trick - which also is used by > > some other commercial OS btw. - is providing best possible performance on > > a wide range of processors. > > If we are going to make the exception generic and usable for as many CPUs as > possible, I don't thing the branch trick is save. > Why not make a hazard barrier that contains 0, 1 or 2 'ssnop's depending on > the CPU configuration ? > This way we will have the exact number of 'ssnop' to solve the hazard, without > adding extra penalty for other CPUs. Since the handler is critical for performance, it would be desireable to have separate versions tuned for particular CPUs. The branch for the R4400 seems appropriate as it works unlike the documented code: the R4000/R4400 manual as available from the MIPS site states a single intervening instruction is needed before the last move to EntryLo and a "tlbwr" or "tlbwi" (see Table F-1 and F-2). So I conclude the branch is really a workaround for a kind of erratum or a specification change. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From ralf@linux-mips.net Wed Jul 31 00:47:18 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id AAA15461; Wed, 31 Jul 2002 00:47:18 +0200 (MET DST) Received-Date: Wed, 31 Jul 2002 00:47:18 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd015459; Wed Jul 31 00:47:15 2002 Received: from dea.linux-mips.net (shaft16-f207.dialo.tiscali.de [62.246.16.207]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6UMlBM04529 for ; Wed, 31 Jul 2002 00:47:12 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6UMl2N02372; Wed, 31 Jul 2002 00:47:02 +0200 Date: Wed, 31 Jul 2002 00:47:02 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: Carsten Langgaard , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards Message-ID: <20020731004702.A2142@dea.linux-mips.net> References: <3D4681DE.7BE793C9@mips.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: ; from macro@ds2.pg.gda.pl on Tue, Jul 30, 2002 at 02:44:32PM +0200 On Tue, Jul 30, 2002 at 02:44:32PM +0200, Maciej W. Rozycki wrote: > Since the handler is critical for performance, it would be desireable to > have separate versions tuned for particular CPUs. The branch for the > R4400 seems appropriate as it works unlike the documented code: the > R4000/R4400 manual as available from the MIPS site states a single > intervening instruction is needed before the last move to EntryLo and a > "tlbwr" or "tlbwi" (see Table F-1 and F-2). So I conclude the branch is > really a workaround for a kind of erratum or a specification change. Nope, on R4000 four cycles are needed between the tlbwr and a eret instruction; on the R4600 just two. Ralf From ralf@linux-mips.net Wed Jul 31 04:05:47 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id EAA22029; Wed, 31 Jul 2002 04:05:47 +0200 (MET DST) Received-Date: Wed, 31 Jul 2002 04:05:47 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd022027; Wed Jul 31 04:05:41 2002 Received: from dea.linux-mips.net (shaft16-f207.dialo.tiscali.de [62.246.16.207]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6V25bM06134 for ; Wed, 31 Jul 2002 04:05:38 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6V25T406353; Wed, 31 Jul 2002 04:05:29 +0200 Date: Wed, 31 Jul 2002 04:05:29 +0200 From: Ralf Baechle To: "Kevin D. Kissell" Cc: Carsten Langgaard , "Maciej W. Rozycki" , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards Message-ID: <20020731040529.A5451@dea.linux-mips.net> References: <3D45A13E.79C882B5@mips.com> <3D46393D.37D36612@mips.com> <20020730132955.A28302@dea.linux-mips.net> <00f801c237c6$29cabd00$10eca8c0@grendel> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: <00f801c237c6$29cabd00$10eca8c0@grendel>; from kevink@mips.com on Tue, Jul 30, 2002 at 02:39:24PM +0200 On Tue, Jul 30, 2002 at 02:39:24PM +0200, Kevin D. Kissell wrote: > > following the branch delay slot. For R4600, R4700, R5000 and a bunch of > > derivates I've verified that according to the documentation this extra > > penalty of two cycles does not exist nor we need two extra cycles to handle > > the hazard. In other words the branch trick - which also is used by > > some other commercial OS btw. - is providing best possible performance on > > a wide range of processors. > > Which would be a fairly compelling argument if (a) we were constrained > for some reason to only have one handler and (b) the majority of MIPS > Linux systems being built had R4000/4400/4600/4700/5000 CPUs in > them. But neither of those assumptions is true. I don't see any cases > in the kernel of assembler functions being put into the .init segment of > the kernel image, but I would think that it could be (and anyway should > be) done with the various exception vectors, and in any case they are > dynamically installed based on the detected CPU. If people using > old workstations want to use a branch-based timing hack in their > TLB handlers, that's all well and good. But there is no guarantee that > the trick will work on all future (or even current) MIPS CPUs, and > I agree with Carsten that it is inappropriate for the generic or default > MIPS32 handlers. I guess we need to propose a patch to allow > the Indy/Decstation crowd to retain their branch-based scheme, > but to quarantine it from the rest of the MIPS/Linux universe. Basically we have two groups of interrupt handlers. Some contain workarounds for hardware bugs; the rest are very similar except having to handle different hazards. I was already thinking about building the actuall exception handlers from a piece of code that inserts the right number of (ss)nops etc. as required into the right place, thereby producing an optimal handler for every CPU. Ralf From kevink@mips.com Wed Jul 31 09:28:15 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id JAA01779; Wed, 31 Jul 2002 09:28:15 +0200 (MET DST) Received-Date: Wed, 31 Jul 2002 09:28:15 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd001777; Wed Jul 31 09:28:10 2002 Received: from mx2.mips.com (mx2.mips.com [206.31.31.227]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6V7S7M07355 for ; Wed, 31 Jul 2002 09:28:07 +0200 (CEST) Received: from newman.mips.com (ns-dmz [206.31.31.225]) by mx2.mips.com (8.12.5/8.12.5) with ESMTP id g6V7RPXb020859; Wed, 31 Jul 2002 00:27:25 -0700 (PDT) Received: from grendel (grendel [192.168.236.16]) by newman.mips.com (8.9.3/8.9.0) with SMTP id AAA10962; Wed, 31 Jul 2002 00:27:16 -0700 (PDT) Message-ID: <005001c23863$e077caa0$10eca8c0@grendel> From: "Kevin D. Kissell" To: "Ralf Baechle" Cc: "Carsten Langgaard" , "Maciej W. Rozycki" , , References: <3D45A13E.79C882B5@mips.com> <3D46393D.37D36612@mips.com> <20020730132955.A28302@dea.linux-mips.net> <00f801c237c6$29cabd00$10eca8c0@grendel> <20020731040529.A5451@dea.linux-mips. Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards Date: Wed, 31 Jul 2002 09:28:09 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4910.0300 From: "Ralf Baechle" : > Basically we have two groups of interrupt handlers. Some contain > workarounds for hardware bugs; the rest are very similar except having > to handle different hazards. I was already thinking about building the > actuall exception handlers from a piece of code that inserts the right > number of (ss)nops etc. as required into the right place, thereby > producing an optimal handler for every CPU. I really don't think that's a good idea. That implies that we could no longer simply inspect the exception handlers in the source code or disassembled kernel binary file to analyse them for correctness, and I think it would lead to unnecessary and hard-to-find bugs. My personal recommendation would be to keep the model we have today, wherein handlers are selected at boot time from some set of candidates built into the kernel binary, with the slight modification that the templates be loaded into the init segment, so that the memory consumed can be reclaimed at run time. That would eliminate the only argument I can see against having a larger set of statically-built optimized handlers. The current selection process is ad-hoc based on CPU ID. We could easily formalize that a bit, and even provide a boot command line option to override the automatic selection with something "safer". Regards, Kevin K. From macro@ds2.pg.gda.pl Wed Jul 31 13:33:55 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id NAA07895; Wed, 31 Jul 2002 13:33:55 +0200 (MET DST) Received-Date: Wed, 31 Jul 2002 13:33:55 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd007892; Wed Jul 31 13:33:53 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6VBXoM08243 for ; Wed, 31 Jul 2002 13:33:51 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id NAA10688; Wed, 31 Jul 2002 13:34:17 +0200 (MET DST) Date: Wed, 31 Jul 2002 13:34:17 +0200 (MET DST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: Carsten Langgaard , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards In-Reply-To: <20020731004702.A2142@dea.linux-mips.net> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On Wed, 31 Jul 2002, Ralf Baechle wrote: > Nope, on R4000 four cycles are needed between the tlbwr and a eret > instruction; on the R4600 just two. Ugh, I missed this entirely, thanks for pointing it out. The doc implies three cycles for the R4000 actually, though. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From macro@ds2.pg.gda.pl Wed Jul 31 13:49:35 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id NAA13985; Wed, 31 Jul 2002 13:49:35 +0200 (MET DST) Received-Date: Wed, 31 Jul 2002 13:49:35 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd013981; Wed Jul 31 13:49:33 2002 Received: from delta.ds2.pg.gda.pl (macro@delta.ds2.pg.gda.pl [213.192.72.1]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6VBnUM08616 for ; Wed, 31 Jul 2002 13:49:30 +0200 (CEST) Received: from localhost by delta.ds2.pg.gda.pl (8.9.3/8.9.3) with SMTP id NAA10995; Wed, 31 Jul 2002 13:49:57 +0200 (MET DST) Date: Wed, 31 Jul 2002 13:49:57 +0200 (MET DST) From: "Maciej W. Rozycki" To: "Kevin D. Kissell" cc: Ralf Baechle , Carsten Langgaard , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards In-Reply-To: <005001c23863$e077caa0$10eca8c0@grendel> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII On Wed, 31 Jul 2002, Kevin D. Kissell wrote: > I really don't think that's a good idea. That implies that we > could no longer simply inspect the exception handlers in > the source code or disassembled kernel binary file to > analyse them for correctness, and I think it would lead > to unnecessary and hard-to-find bugs. My personal > recommendation would be to keep the model we have > today, wherein handlers are selected at boot time from > some set of candidates built into the kernel binary, with Well, as long as we don't have an insane number of variations (say 32+), I tend to agree. Thanks to macros, maintaining source code is not that hard. If we ever reach the sanity limit, we may rearrange the source again. > the slight modification that the templates be loaded into > the init segment, so that the memory consumed can be > reclaimed at run time. That would eliminate the only That already happens now. Except from the vmalloc path, which could likely be handled this way as well, by copying the appropriate handler to KSEG0 somewhere above standard exception vectors. That would have the micro-optimization advantage, we could use the "b" instruction, instead of the much longer "dla/jr" pair. Still possibly we can have a single vmalloc handler only as the epilogue should be the same as for the user path -- we need have to find a way to hook a jump back somehow in this case. > argument I can see against having a larger set of > statically-built optimized handlers. The current > selection process is ad-hoc based on CPU ID. > We could easily formalize that a bit, and even Well, the current approach seems appropriate. Only a comment here and there might be useful, to explain why a particular handler is used (with an erratum text included if applicable). > provide a boot command line option to override > the automatic selection with something "safer". Hmm, I think that's an overkill, although for debugging purposes, a single extremely conservative handler (possibly with some status output to the log) might be selectable as an alternative. Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + From ralf@linux-mips.net Wed Jul 31 20:23:23 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id UAA23693; Wed, 31 Jul 2002 20:23:23 +0200 (MET DST) Received-Date: Wed, 31 Jul 2002 20:23:23 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd023691; Wed Jul 31 20:23:13 2002 Received: from dea.linux-mips.net (shaft17-f75.dialo.tiscali.de [62.246.17.75]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6VIN9M10625 for ; Wed, 31 Jul 2002 20:23:11 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6VIMxc05139; Wed, 31 Jul 2002 20:22:59 +0200 Date: Wed, 31 Jul 2002 20:22:59 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: "Kevin D. Kissell" , Carsten Langgaard , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards Message-ID: <20020731202259.D4892@dea.linux-mips.net> References: <005001c23863$e077caa0$10eca8c0@grendel> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: ; from macro@ds2.pg.gda.pl on Wed, Jul 31, 2002 at 01:49:57PM +0200 On Wed, Jul 31, 2002 at 01:49:57PM +0200, Maciej W. Rozycki wrote: > Hmm, I think that's an overkill, although for debugging purposes, a > single extremely conservative handler (possibly with some status output to > the log) might be selectable as an alternative. Look at the C variation of the exception handler in the mips64 code. It was pretty useful to add debugging checks during early mips64 development. Ralf From ralf@linux-mips.net Wed Jul 31 22:17:23 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id WAA29276; Wed, 31 Jul 2002 22:17:23 +0200 (MET DST) Received-Date: Wed, 31 Jul 2002 22:17:23 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd029274; Wed Jul 31 22:17:18 2002 Received: from dea.linux-mips.net (shaft17-f104.dialo.tiscali.de [62.246.17.104]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6VKH7M11390 for ; Wed, 31 Jul 2002 22:17:07 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6VKGVJ06292; Wed, 31 Jul 2002 22:16:31 +0200 Date: Wed, 31 Jul 2002 22:16:31 +0200 From: Ralf Baechle To: Pete Popov Cc: "Maciej W. Rozycki" , linux-mips@fnet.fr, linux-mips Subject: Re: [patch] wbflush() fixes and updates Message-ID: <20020731221631.B6048@dea.linux-mips.net> References: <1027527551.18017.13.camel@zeus.mvista.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: <1027527551.18017.13.camel@zeus.mvista.com>; from ppopov@mvista.com on Wed, Jul 24, 2002 at 10:41:14PM +0200 Pete, if you want to post to linux-mips@fnet.fr (as long as that list still exists ...) you'll have to subscribe. The list robot which I can't configure myself is configured to only permit postings by subscribers. Do you want me to subscribe you? Ralf On Wed, Jul 24, 2002 at 10:41:14PM +0200, Pete Popov wrote: > Date: Wed, 24 Jul 2002 22:41:14 +0200 (MET DST) > Subject: Re: [patch] wbflush() fixes and updates > From: Pete Popov > To: "Maciej W. Rozycki" > Cc: Ralf Baechle , linux-mips@fnet.fr, > linux-mips > > Content-Type: text/plain > > On Wed, 2002-07-24 at 08:34, Maciej W. Rozycki wrote: > > Hello, > > > > Here is a follow-on patch to the recent synchronization rewrite. It > > converts a few of wbflush() references to iob() (functionally equivalent, > > but with a somewhat more consistent naming) and it removes a few > > unnecessary private __wbflush() implementations (that now are covered by > > the generic code). Finally, it fixes the DECstation __wbflush() > > implementation to match hardware reality. > > > > OK to apply? > > The Au1x00 looks fine. I suppose I'll have to update the defconfig > files to include CONFIG_CPU_HAS_SYNC. > > Pete > > > Maciej > > > > -- > > + Maciej W. Rozycki, Technical University of Gdansk, Poland + > > +--------------------------------------------------------------+ > > + e-mail: macro@ds2.pg.gda.pl, PGP key available + > > > > patch-mips-2.4.19-rc1-20020719-wbflush-9 > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1000/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1000/setup.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1000/setup.c 2002-07-05 02:57:37.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1000/setup.c 2002-07-23 21:25:22.000000000 +0000 > > @@ -67,7 +67,6 @@ extern struct ide_ops std_ide_ops; > > extern struct ide_ops *ide_ops; > > #endif > > > > -void (*__wbflush) (void); > > extern struct rtc_ops no_rtc_ops; > > extern char * __init prom_getcmdline(void); > > extern void au1000_restart(char *); > > @@ -78,11 +77,6 @@ extern struct resource iomem_resource; > > > > void __init bus_error_init(void) { /* nothing */ } > > > > -void au1000_wbflush(void) > > -{ > > - __asm__ volatile ("sync"); > > -} > > - > > void __init au1000_setup(void) > > { > > char *argptr; > > @@ -103,7 +97,6 @@ void __init au1000_setup(void) > > #endif > > > > rtc_ops = &no_rtc_ops; > > - __wbflush = au1000_wbflush; > > _machine_restart = au1000_restart; > > _machine_halt = au1000_halt; > > _machine_power_off = au1000_power_off; > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1100/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1100/setup.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1100/setup.c 2002-07-14 21:20:57.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1100/setup.c 2002-07-23 21:25:56.000000000 +0000 > > @@ -71,7 +71,6 @@ extern struct ide_ops *ide_ops; > > extern struct rtc_ops pb1500_rtc_ops; > > #endif > > > > -void (*__wbflush) (void); > > extern char * __init prom_getcmdline(void); > > extern void au1000_restart(char *); > > extern void au1000_halt(void); > > @@ -80,11 +79,6 @@ extern struct resource ioport_resource; > > extern struct resource iomem_resource; > > > > > > -void au1100_wbflush(void) > > -{ > > - __asm__ volatile ("sync"); > > -} > > - > > void __init bus_error_init(void) { /* nothing */ } > > > > void __init au1100_setup(void) > > @@ -112,7 +106,6 @@ void __init au1100_setup(void) > > argptr = prom_getcmdline(); > > #endif > > > > - __wbflush = au1100_wbflush; > > _machine_restart = au1000_restart; > > _machine_halt = au1000_halt; > > _machine_power_off = au1000_power_off; > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1500/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1500/setup.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/au1000/pb1500/setup.c 2002-07-15 02:57:11.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/au1000/pb1500/setup.c 2002-07-23 21:26:24.000000000 +0000 > > @@ -71,7 +71,6 @@ extern struct ide_ops *ide_ops; > > extern struct rtc_ops pb1500_rtc_ops; > > #endif > > > > -void (*__wbflush) (void); > > extern char * __init prom_getcmdline(void); > > extern void au1000_restart(char *); > > extern void au1000_halt(void); > > @@ -82,11 +81,6 @@ extern struct resource iomem_resource; > > > > void __init bus_error_init(void) { /* nothing */ } > > > > -void au1500_wbflush(void) > > -{ > > - __asm__ volatile ("sync"); > > -} > > - > > void __init au1500_setup(void) > > { > > char *argptr; > > @@ -112,7 +106,6 @@ void __init au1500_setup(void) > > argptr = prom_getcmdline(); > > #endif > > > > - __wbflush = au1500_wbflush; > > _machine_restart = au1000_restart; > > _machine_halt = au1000_halt; > > _machine_power_off = au1000_power_off; > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/baget/Makefile linux-mips-2.4.19-rc1-20020719/arch/mips/baget/Makefile > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/baget/Makefile 2001-01-11 05:25:50.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/baget/Makefile 2002-07-23 21:27:40.000000000 +0000 > > @@ -14,7 +14,7 @@ O_TARGET := baget.a > > > > export-objs := vacserial.o vacrtc.o > > obj-y := baget.o print.o setup.o time.o irq.o bagetIRQ.o \ > > - reset.o wbflush.o > > + reset.o > > obj-$(CONFIG_SERIAL) += vacserial.o > > obj-$(CONFIG_VAC_RTC) += vacrtc.o > > > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/baget/wbflush.c linux-mips-2.4.19-rc1-20020719/arch/mips/baget/wbflush.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/baget/wbflush.c 2000-03-28 04:26:02.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/baget/wbflush.c 1970-01-01 00:00:00.000000000 +0000 > > @@ -1,24 +0,0 @@ > > -/* > > - * Setup the right wbflush routine for Baget/MIPS. > > - * > > - * Copyright (C) 1999 Gleb Raiko & Vladimir Roganov > > - */ > > - > > -#include > > -#include > > - > > -void (*__wbflush) (void); > > - > > -static void wbflush_baget(void); > > - > > -void __init wbflush_setup(void) > > -{ > > - __wbflush = wbflush_baget; > > -} > > - > > -/* > > - * Baget/MIPS doesnt need to write back the WB. > > - */ > > -static void wbflush_baget(void) > > -{ > > -} > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/Makefile linux-mips-2.4.19-rc1-20020719/arch/mips/dec/Makefile > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/Makefile 2002-06-26 03:04:35.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/dec/Makefile 2002-07-21 18:11:04.000000000 +0000 > > @@ -14,9 +14,10 @@ all: dec.o > > > > export-objs := setup.o wbflush.o > > obj-y := int-handler.o ioasic-irq.o kn02-irq.o reset.o rtc-dec.o setup.o \ > > - time.o wbflush.o > > + time.o > > > > obj-$(CONFIG_PROM_CONSOLE) += promcon.o > > +obj-$(CONFIG_CPU_HAS_WB) += wbflush.o > > > > int-handler.o: int-handler.S > > > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/ioasic-irq.c linux-mips-2.4.19-rc1-20020719/arch/mips/dec/ioasic-irq.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/ioasic-irq.c 2002-04-09 02:27:12.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/dec/ioasic-irq.c 2002-04-16 20:53:43.000000000 +0000 > > @@ -84,6 +84,7 @@ static inline void ack_ioasic_irq(unsign > > spin_lock(&ioasic_lock); > > mask_ioasic_irq(irq); > > spin_unlock(&ioasic_lock); > > + fast_iob(); > > } > > > > static inline void end_ioasic_irq(unsigned int irq) > > @@ -119,6 +120,7 @@ static struct hw_interrupt_type ioasic_i > > static inline void end_ioasic_dma_irq(unsigned int irq) > > { > > clear_ioasic_irq(irq); > > + fast_iob(); > > end_ioasic_irq(irq); > > } > > > > @@ -142,6 +144,7 @@ void __init init_ioasic_irqs(int base) > > > > /* Mask interrupts. */ > > ioasic_write(SIMR, 0); > > + fast_iob(); > > > > for (i = base; i < base + IO_INR_DMA; i++) { > > irq_desc[i].status = IRQ_DISABLED; > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/kn02-irq.c linux-mips-2.4.19-rc1-20020719/arch/mips/dec/kn02-irq.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/kn02-irq.c 2002-04-09 02:27:12.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/dec/kn02-irq.c 2002-04-16 20:53:43.000000000 +0000 > > @@ -83,6 +83,7 @@ static void ack_kn02_irq(unsigned int ir > > spin_lock(&kn02_lock); > > mask_kn02_irq(irq); > > spin_unlock(&kn02_lock); > > + iob(); > > } > > > > static void end_kn02_irq(unsigned int irq) > > @@ -113,6 +114,7 @@ void __init init_kn02_irqs(int base) > > /* Mask interrupts and preset write-only bits. */ > > cached_kn02_csr = (*csr & ~0xff0000) | 0xff; > > *csr = cached_kn02_csr; > > + iob(); > > > > for (i = base; i < base + KN02_IRQ_LINES; i++) { > > irq_desc[i].status = IRQ_DISABLED; > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips/dec/setup.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/setup.c 2002-07-19 03:01:49.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/dec/setup.c 2002-07-21 18:11:04.000000000 +0000 > > @@ -25,6 +25,7 @@ > > #include > > #include > > #include > > +#include > > > > #include > > #include > > @@ -89,8 +90,6 @@ static struct irqaction fpuirq = {NULL, > > static struct irqaction haltirq = {dec_intr_halt, 0, 0, "halt", NULL, NULL}; > > > > > > -extern void wbflush_setup(void); > > - > > extern struct rtc_ops dec_rtc_ops; > > > > void (*board_time_init) (struct irqaction * irq); > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/wbflush.c linux-mips-2.4.19-rc1-20020719/arch/mips/dec/wbflush.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/dec/wbflush.c 2001-11-06 05:26:15.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/dec/wbflush.c 2002-02-04 01:03:17.000000000 +0000 > > @@ -11,15 +11,18 @@ > > * for more details. > > * > > * Copyright (C) 1998 Harald Koerfgen > > + * Copyright (C) 2002 Maciej W. Rozycki > > */ > > > > -#include > > #include > > > > +#include > > +#include > > +#include > > + > > static void wbflush_kn01(void); > > static void wbflush_kn210(void); > > -static void wbflush_kn02ba(void); > > -static void wbflush_kn03(void); > > +static void wbflush_mips(void); > > > > void (*__wbflush) (void); > > > > @@ -27,28 +30,23 @@ void __init wbflush_setup(void) > > { > > switch (mips_machtype) { > > case MACH_DS23100: > > - __wbflush = wbflush_kn01; > > - break; > > - case MACH_DS5100: /* DS5100 MIPSMATE */ > > - __wbflush = wbflush_kn210; > > - break; > > case MACH_DS5000_200: /* DS5000 3max */ > > - __wbflush = wbflush_kn01; > > - break; > > + __wbflush = wbflush_kn01; > > + break; > > + case MACH_DS5100: /* DS5100 MIPSMATE */ > > + __wbflush = wbflush_kn210; > > + break; > > case MACH_DS5000_1XX: /* DS5000/100 3min */ > > - __wbflush = wbflush_kn02ba; > > - break; > > - case MACH_DS5000_2X0: /* DS5000/240 3max+ */ > > - __wbflush = wbflush_kn03; > > - break; > > case MACH_DS5000_XX: /* Personal DS5000/2x */ > > - __wbflush = wbflush_kn02ba; > > - break; > > + case MACH_DS5000_2X0: /* DS5000/240 3max+ */ > > + default: > > + __wbflush = wbflush_mips; > > + break; > > } > > } > > > > /* > > - * For the DS3100 and DS5000/200 the writeback buffer functions > > + * For the DS3100 and DS5000/200 the R2020/R3220 writeback buffer functions > > * as part of Coprocessor 0. > > */ > > static void wbflush_kn01(void) > > @@ -78,29 +76,16 @@ static void wbflush_kn210(void) > > "mtc0\t$2,$12\n\t" > > "nop\n\t" > > ".set\tpop" > > - : : :"$2", "$3"); > > -} > > - > > -/* > > - * Looks like some magic with the System Interrupt Mask Register > > - * in the famous IOASIC for kmins and maxines. > > - */ > > -static void wbflush_kn02ba(void) > > -{ > > - asm(".set\tpush\n\t" > > - ".set\tnoreorder\n\t" > > - "lui\t$2,0xbc04\n\t" > > - "lw\t$3,0x120($2)\n\t" > > - "lw\t$3,0x120($2)\n\t" > > - ".set\tpop" > > - : : :"$2", "$3"); > > + : : : "$2", "$3"); > > } > > > > /* > > - * The DS500/2x0 doesnt need to write back the WB. > > + * I/O ASIC systems use a standard writeback buffer that gets flushed > > + * upon an uncached read. > > */ > > -static void wbflush_kn03(void) > > +static void wbflush_mips(void) > > { > > + __fast_iob(); > > } > > > > #include > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/galileo-boards/ev96100/setup.c linux-mips-2.4.19-rc1-20020719/arch/mips/galileo-boards/ev96100/setup.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/galileo-boards/ev96100/setup.c 2001-11-26 05:25:59.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/galileo-boards/ev96100/setup.c 2002-07-23 21:30:52.000000000 +0000 > > @@ -52,8 +52,6 @@ > > #include > > > > > > -void (*__wbflush) (void); > > - > > #if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE) > > extern void console_setup(char *, int *); > > char serial_console[20]; > > @@ -65,11 +63,6 @@ extern void mips_reboot_setup(void); > > extern struct rtc_ops no_rtc_ops; > > extern struct resource ioport_resource; > > > > -static void rm7000_wbflush(void) > > -{ > > - __asm__ __volatile__ ("sync"); > > -} > > - > > unsigned char mac_0_1[12]; > > > > > > @@ -83,7 +76,6 @@ void __init ev96100_setup(void) > > char *argptr; > > > > clear_cp0_status(ST0_FR); > > - __wbflush = rm7000_wbflush; > > > > if (config & 0x8) { > > printk("Secondary cache is enabled\n"); > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/c-r3k.c linux-mips-2.4.19-rc1-20020719/arch/mips/mm/c-r3k.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/c-r3k.c 2002-02-19 05:28:14.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/mm/c-r3k.c 2002-03-24 21:16:14.000000000 +0000 > > @@ -19,7 +19,6 @@ > > #include > > #include > > #include > > -#include > > #include > > #include > > > > @@ -314,7 +313,7 @@ static void r3k_flush_cache_sigtramp(uns > > > > static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size) > > { > > - wbflush(); > > + iob(); > > r3k_flush_dcache_range(start, start + size); > > } > > > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/c-tx39.c linux-mips-2.4.19-rc1-20020719/arch/mips/mm/c-tx39.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/c-tx39.c 2001-12-01 05:26:01.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/mm/c-tx39.c 2002-02-04 01:12:41.000000000 +0000 > > @@ -20,7 +20,6 @@ > > #include > > #include > > #include > > -#include > > #include > > #include > > > > @@ -63,8 +62,8 @@ static void tx39h_flush_icache_all(void) > > static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size) > > { > > unsigned long end, a; > > - wbflush(); > > > > + iob(); > > a = addr & ~(dcache_lsize - 1); > > end = (addr + size) & ~(dcache_lsize - 1); > > while (1) { > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/tlb-r3k.c linux-mips-2.4.19-rc1-20020719/arch/mips/mm/tlb-r3k.c > > --- linux-mips-2.4.19-rc1-20020719.macro/arch/mips/mm/tlb-r3k.c 2002-05-30 02:57:46.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/arch/mips/mm/tlb-r3k.c 2002-06-15 15:38:41.000000000 +0000 > > @@ -20,7 +20,6 @@ > > #include > > #include > > #include > > -#include > > #include > > #include > > > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/drivers/char/dz.c linux-mips-2.4.19-rc1-20020719/drivers/char/dz.c > > --- linux-mips-2.4.19-rc1-20020719.macro/drivers/char/dz.c 2002-06-27 02:58:15.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/drivers/char/dz.c 2002-07-21 18:11:04.000000000 +0000 > > @@ -35,7 +35,6 @@ > > #include > > #include > > #include > > -#include > > #include > > > > #include > > @@ -53,6 +52,8 @@ > > #include > > #include > > > > +#include > > + > > #define CONSOLE_LINE (3) /* for definition of struct console */ > > > > extern int (*prom_printf) (char *,...); > > @@ -1415,7 +1416,7 @@ int __init dz_init(void) > > #ifndef CONFIG_SERIAL_CONSOLE > > dz_out(info, DZ_CSR, DZ_CLR); > > while ((tmp = dz_in(info, DZ_CSR)) & DZ_CLR); > > - wbflush(); > > + iob(); > > > > /* enable scanning */ > > dz_out(info, DZ_CSR, DZ_MSE); > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/drivers/net/declance.c linux-mips-2.4.19-rc1-20020719/drivers/net/declance.c > > --- linux-mips-2.4.19-rc1-20020719.macro/drivers/net/declance.c 2002-07-08 16:46:24.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/drivers/net/declance.c 2002-07-21 18:11:05.000000000 +0000 > > @@ -62,7 +62,7 @@ > > #include > > #include > > #include > > -#include > > +#include > > > > static char version[] __devinitdata = > > "declance.c: v0.009 by Linux MIPS DECstation task force\n"; > > @@ -289,7 +289,7 @@ static struct net_device *root_lance_dev > > static inline void writereg(volatile unsigned short *regptr, short value) > > { > > *regptr = value; > > - wbflush(); > > + iob(); > > } > > > > /* Load the CSR registers */ > > @@ -369,7 +369,7 @@ void cp_to_buf(const int type, void *to, > > } > > } > > > > - wbflush(); > > + iob(); > > } > > > > void cp_from_buf(const int type, void *to, const void *from, int len) > > @@ -497,7 +497,7 @@ static void lance_init_ring(struct net_d > > if (i < 3 && ZERO) > > printk("%d: 0x%8.8x(0x%8.8x)\n", i, leptr, (int) lp->rx_buf_ptr_cpu[i]); > > } > > - wbflush(); > > + iob(); > > } > > > > static int init_restart_lance(struct lance_private *lp) > > @@ -794,7 +794,7 @@ static int lance_open(struct net_device > > return -EAGAIN; > > } > > /* Enable I/O ASIC LANCE DMA. */ > > - wbflush(); > > + fast_wmb(); > > ioasic_write(SSR, ioasic_read(SSR) | LANCE_DMA_EN); > > } > > > > @@ -823,7 +823,7 @@ static int lance_close(struct net_device > > if (lp->dma_irq >= 0) { > > /* Disable I/O ASIC LANCE DMA. */ > > ioasic_write(SSR, ioasic_read(SSR) & ~LANCE_DMA_EN); > > - wbflush(); > > + fast_iob(); > > free_irq(lp->dma_irq, dev); > > } > > free_irq(dev->irq, dev); > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/drivers/scsi/NCR53C9x.h linux-mips-2.4.19-rc1-20020719/drivers/scsi/NCR53C9x.h > > --- linux-mips-2.4.19-rc1-20020719.macro/drivers/scsi/NCR53C9x.h 2001-10-19 04:29:11.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/drivers/scsi/NCR53C9x.h 2002-02-04 01:14:34.000000000 +0000 > > @@ -144,12 +144,7 @@ > > > > #ifndef MULTIPLE_PAD_SIZES > > > > -#ifdef CONFIG_CPU_HAS_WB > > -#include > > -#define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0) > > -#else > > -#define esp_write(__reg, __val) ((__reg) = (__val)) > > -#endif > > +#define esp_write(__reg, __val) do{(__reg) = (__val); iob();} while(0) > > #define esp_read(__reg) (__reg) > > > > struct ESP_regs { > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/drivers/scsi/dec_esp.c linux-mips-2.4.19-rc1-20020719/drivers/scsi/dec_esp.c > > --- linux-mips-2.4.19-rc1-20020719.macro/drivers/scsi/dec_esp.c 2002-04-10 02:58:49.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/drivers/scsi/dec_esp.c 2002-07-21 18:12:55.000000000 +0000 > > @@ -46,6 +46,8 @@ > > #include > > #include > > > > +#include > > + > > /* > > * Once upon a time the pmaz code used to be working but > > * it hasn't been maintained for quite some time. > > @@ -308,17 +310,9 @@ static void scsi_dma_err_int(int irq, vo > > > > static void scsi_dma_int(int irq, void *dev_id, struct pt_regs *regs) > > { > > - volatile unsigned int *dummy = (volatile unsigned int *)KSEG1; > > - > > /* next page */ > > *scsi_next_ptr = ((*scsi_dma_ptr + PAGE_SIZE) & PAGE_MASK) << 3; > > - > > - /* > > - * This routine will only work on IOASIC machines > > - * so we can avoid an indirect function call here > > - * and flush the writeback buffer the fast way > > - */ > > - *dummy; > > + fast_iob(); > > } > > > > static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count) > > @@ -370,8 +364,6 @@ static void dma_dump_state(struct NCR_ES > > > > static void dma_init_read(struct NCR_ESP *esp, __u32 vaddress, int length) > > { > > - volatile unsigned int *dummy = (volatile unsigned int *)KSEG1; > > - > > if (vaddress & 3) > > panic("dec_efs.c: unable to handle partial word transfers, yet..."); > > > > @@ -384,17 +376,11 @@ static void dma_init_read(struct NCR_ESP > > /* prepare for next page */ > > *scsi_next_ptr = ((vaddress + PAGE_SIZE) & PAGE_MASK) << 3; > > *ioasic_ssr |= (SCSI_DMA_DIR | SCSI_DMA_EN); > > - > > - /* > > - * see above > > - */ > > - *dummy; > > + fast_iob(); > > } > > > > static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length) > > { > > - volatile unsigned int *dummy = (volatile unsigned int *)KSEG1; > > - > > if (vaddress & 3) > > panic("dec_efs.c: unable to handle partial word transfers, yet..."); > > > > @@ -407,11 +393,7 @@ static void dma_init_write(struct NCR_ES > > /* prepare for next page */ > > *scsi_next_ptr = ((vaddress + PAGE_SIZE) & PAGE_MASK) << 3; > > *ioasic_ssr |= SCSI_DMA_EN; > > - > > - /* > > - * see above > > - */ > > - *dummy; > > + fast_iob(); > > } > > > > static void dma_ints_off(struct NCR_ESP *esp) > > @@ -492,6 +474,8 @@ static void pmaz_dma_init_read(struct NC > > > > *dmareg = TC_ESP_DMA_ADDR(esp->slot + DEC_SCSI_SRAM + ESP_TGT_DMA_SIZE); > > > > + iob(); > > + > > esp_virt_buffer = vaddress; > > scsi_current_length = length; > > } > > @@ -506,6 +490,7 @@ static void pmaz_dma_init_write(struct N > > *dmareg = TC_ESP_DMAR_WRITE | > > TC_ESP_DMA_ADDR(esp->slot + DEC_SCSI_SRAM + ESP_TGT_DMA_SIZE); > > > > + iob(); > > } > > > > static void pmaz_dma_ints_off(struct NCR_ESP *esp) > > diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020719.macro/drivers/tc/zs.c linux-mips-2.4.19-rc1-20020719/drivers/tc/zs.c > > --- linux-mips-2.4.19-rc1-20020719.macro/drivers/tc/zs.c 2002-06-27 02:59:46.000000000 +0000 > > +++ linux-mips-2.4.19-rc1-20020719/drivers/tc/zs.c 2002-07-21 18:11:05.000000000 +0000 > > @@ -67,7 +67,6 @@ > > #include > > #include > > #include > > -#include > > #include > > #ifdef CONFIG_DECSTATION > > #include > > @@ -276,7 +275,7 @@ static inline unsigned char read_zsreg(s > > > > if (reg != 0) { > > *channel->control = reg & 0xf; > > - wbflush(); RECOVERY_DELAY; > > + fast_iob(); RECOVERY_DELAY; > > } > > retval = *channel->control; > > RECOVERY_DELAY; > > @@ -288,10 +287,10 @@ static inline void write_zsreg(struct de > > { > > if (reg != 0) { > > *channel->control = reg & 0xf; > > - wbflush(); RECOVERY_DELAY; > > + fast_iob(); RECOVERY_DELAY; > > } > > *channel->control = value; > > - wbflush(); RECOVERY_DELAY; > > + fast_iob(); RECOVERY_DELAY; > > return; > > } > > > > @@ -308,7 +307,7 @@ static inline void write_zsdata(struct d > > unsigned char value) > > { > > *channel->data = value; > > - wbflush(); RECOVERY_DELAY; > > + fast_iob(); RECOVERY_DELAY; > > return; > > } > > > > > From ralf@linux-mips.net Wed Jul 31 22:32:14 2002 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id WAA04222; Wed, 31 Jul 2002 22:32:14 +0200 (MET DST) Received-Date: Wed, 31 Jul 2002 22:32:14 +0200 (MET DST) Received: from indus.fnet.fr(192.134.188.133) via SMTP by guadalquivir.fnet.fr, id smtpd004220; Wed Jul 31 22:32:08 2002 Received: from dea.linux-mips.net (shaft17-f104.dialo.tiscali.de [62.246.17.104]) by indus.fnet.fr (8.11.3nb1/8.11.3/$RCSfile$) with ESMTP id g6VKW5M11749 for ; Wed, 31 Jul 2002 22:32:05 +0200 (CEST) Received: (from ralf@localhost) by dea.linux-mips.net (8.11.6/8.11.6) id g6VKVwZ06476; Wed, 31 Jul 2002 22:31:58 +0200 Date: Wed, 31 Jul 2002 22:31:58 +0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: Carsten Langgaard , linux-mips@fnet.fr, linux-mips@oss.sgi.com Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards Message-ID: <20020731223158.A6394@dea.linux-mips.net> References: <20020731004702.A2142@dea.linux-mips.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: ; from macro@ds2.pg.gda.pl on Wed, Jul 31, 2002 at 01:34:17PM +0200 On Wed, Jul 31, 2002 at 01:34:17PM +0200, Maciej W. Rozycki wrote: > > Nope, on R4000 four cycles are needed between the tlbwr and a eret > > instruction; on the R4600 just two. > > Ugh, I missed this entirely, thanks for pointing it out. The doc implies > three cycles for the R4000 actually, though. I doublechecked the docs for the R4700 as well - just one cycle needed between a tlbw and eret. Ralf