From vhouten@kpn.com Sun Dec 2 12:10:20 2001 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id MAA17076; Sun, 2 Dec 2001 12:10:20 +0100 (MET) Received-Date: Sun, 2 Dec 2001 12:10:20 +0100 (MET) Received: from pandora.research.kpn.com(139.63.192.11) via SMTP by guadalquivir.fnet.fr, id smtpd017074; Sun Dec 2 12:10:10 2001 Received: from sparta.research.kpn.com (sparta.research.kpn.com [139.63.192.6]) by pandora.research.kpn.com (8.9.3/8.9.3) with ESMTP id MAA09715; Sun, 2 Dec 2001 12:10:03 +0100 Received: from sparta.research.kpn.com (sparta.research.kpn.com [139.63.192.6]) by sparta.research.kpn.com (8.8.8+Sun/8.8.8) with ESMTP id MAA15571; Sun, 2 Dec 2001 12:10:03 +0100 (MET) Message-Id: <200112021110.MAA15571@sparta.research.kpn.com> X-Mailer: exmh version 1.6.5 12/11/95 To: flo@rfc822.org, linux-mips@oss.sgi.com, linux-mips@fnet.fr Reply-to: vhouten@kpn.com Subject: New delo RPMs for RH7.x and recent 2.4.x kernels X-Face: ";:TzQQC{mTp~$W,'m4@Lu1Lu$rtG_~5kvYO~F:C'KExk9o1X"iRz[0%{bq?6Aj#>VhSD?v 1W9`.Qsf+P&*iQEL8&y,RDj&U.]!(R-?c-h5h%Iw%r$|%6+Jc>GTJe!_1&A0o'lC[`I#={2BzOXT1P q366I$WL=;[+SDo1RoIT+a}_y68Y:jQ^xp4=*4-ryiymi>hy Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Sun, 02 Dec 2001 12:10:03 +0100 From: "Houten K.H.C. van (Karel)" Content-Length: 480 Lines: 18 Hi, I've uploaded new delo (DECStation bootloader) RPMs that contain Florian latest patch, and can be compiled by H.J.Lu's RH7.1 toolchain (native). It is available at: ftp://oss.sgi.com/pub/linux/mips/mipsel-linux/delo Regards, -- Karel van Houten ---------------------------------------------------------- The box said "Requires Windows 95 or better." I can't understand why it won't work on my Linux computer. ---------------------------------------------------------- From ralf@linux-mips.net Mon Dec 3 07:01:08 2001 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id HAA29073; Mon, 3 Dec 2001 07:01:08 +0100 (MET) Received-Date: Mon, 3 Dec 2001 07:01:08 +0100 (MET) Received: from oss.sgi.com(216.32.174.27) via SMTP by guadalquivir.fnet.fr, id smtpd029071; Mon Dec 3 07:01:00 2001 Received: from dea.linux-mips.net (localhost [127.0.0.1]) by oss.sgi.com (8.11.2/8.11.3) with ESMTP id fB370vo25880 for ; Sun, 2 Dec 2001 23:00:57 -0800 Received: (from ralf@localhost) by dea.linux-mips.net (8.11.1/8.11.1) id fB360mb27534; Mon, 3 Dec 2001 17:00:48 +1100 Date: Mon, 3 Dec 2001 17:00:47 +1100 From: Ralf Baechle To: nick@snowman.net, linux-mips@oss.sgi.com, linux-mips@fnet.fr Subject: Re: o200 oops Message-ID: <20011203170047.B24633@dea.linux-mips.net> References: <20011128091248.A24032@dea.linux-mips.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5i In-Reply-To: ; from nick@snowman.net on Sun, Dec 02, 2001 at 09:56:07PM -0500 X-Accept-Language: de,en,fr Content-Length: 312 Lines: 9 On Sun, Dec 02, 2001 at 09:56:07PM -0500, nick@snowman.net wrote: > unknown ioctl: 00005382 Request to users of the 64-bit kernel - if you get a kernel message like this one please tell me drop me a mail. Would be great if you can actually find the symbolic name of the ioctl triggering this message. Ralf From ralf@linux-mips.net Sun Dec 9 19:53:13 2001 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id TAA20140; Sun, 9 Dec 2001 19:53:13 +0100 (MET) Received-Date: Sun, 9 Dec 2001 19:53:13 +0100 (MET) Received: from oss.sgi.com(216.32.174.27) via SMTP by guadalquivir.fnet.fr, id smtpd020138; Sun Dec 9 19:53:08 2001 Received: from dea.linux-mips.net (localhost [127.0.0.1]) by oss.sgi.com (8.11.2/8.11.3) with ESMTP id fB9Jr3o11055 for ; Sun, 9 Dec 2001 11:53:03 -0800 Received: (from ralf@localhost) by dea.linux-mips.net (8.11.1/8.11.1) id fB8JRgU08535; Sat, 8 Dec 2001 17:27:42 -0200 Date: Sat, 8 Dec 2001 17:26:27 -0200 From: Ralf Baechle To: linux-mips@oss.sgi.com, linux-mips@fnet.fr Subject: CVS branches Message-ID: <20011208172627.A3385@dea.linux-mips.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5i X-Accept-Language: de,en,fr Content-Length: 492 Lines: 9 Some of you may already have noticed, I've created a cvs branch linux_2_4 for versions from 2.4.16 on. The main branch has 2.5 and on. For those of you who are not familiar with cvs branches - when doing a checkout or update just add the option -rlinux_2_4. This is only necessary once as cvs will remember on which branch you're on. To get back to the main branch use the option -A. This is a slow operation so most people will want to use separate directories for each branch. Ralf From ralf@linux-mips.net Wed Dec 12 00:01:21 2001 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id AAA16730; Wed, 12 Dec 2001 00:01:21 +0100 (MET) Received-Date: Wed, 12 Dec 2001 00:01:21 +0100 (MET) Received: from oss.sgi.com(216.32.174.27) via SMTP by guadalquivir.fnet.fr, id smtpd016728; Wed Dec 12 00:01:17 2001 Received: from dea.linux-mips.net (localhost [127.0.0.1]) by oss.sgi.com (8.11.2/8.11.3) with ESMTP id fBC01Bo26234 for ; Tue, 11 Dec 2001 16:01:12 -0800 Received: (from ralf@localhost) by dea.linux-mips.net (8.11.1/8.11.1) id fBBN10A23115; Tue, 11 Dec 2001 21:01:00 -0200 Date: Tue, 11 Dec 2001 21:01:00 -0200 From: Ralf Baechle To: linux-mips@oss.sgi.com, linux-mips@fnet.fr Subject: cpuinfo Message-ID: <20011211210100.A21552@dea.linux-mips.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5i X-Accept-Language: de,en,fr Content-Length: 19970 Lines: 696 Ok, the damage of no longer having /proc/cpuinfo was a bit too large it seems so here is a patch to retrofit it. Patch against 2.5 but should work for 2.4 also. Ralf Index: arch/mips/arc/identify.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/arc/identify.c,v retrieving revision 1.5 diff -u -r1.5 identify.c --- arch/mips/arc/identify.c 2001/03/18 23:29:04 1.5 +++ arch/mips/arc/identify.c 2001/12/11 22:46:55 @@ -17,17 +17,35 @@ #include struct smatch { - char *name; + char *arcname; + char *liname; int group; int type; int flags; }; static struct smatch mach_table[] = { - {"SGI-IP22", MACH_GROUP_SGI, MACH_SGI_INDY, PROM_FLAG_ARCS}, - {"Microsoft-Jazz", MACH_GROUP_JAZZ, MACH_MIPS_MAGNUM_4000, 0}, - {"PICA-61", MACH_GROUP_JAZZ, MACH_ACER_PICA_61, 0}, - {"RM200PCI", MACH_GROUP_SNI_RM, MACH_SNI_RM200_PCI, 0} + { "SGI-IP22", + "SGI Indy", + MACH_GROUP_SGI, + MACH_SGI_INDY, + PROM_FLAG_ARCS + }, { "Microsoft-Jazz", + "Jazz MIPS_Magnum_4000", + MACH_GROUP_JAZZ, + MACH_MIPS_MAGNUM_4000, + 0 + }, { "PICA-61", + "Jazz Acer_PICA_61", + "MACH_GROUP_JAZZ", + MACH_ACER_PICA_61, + 0 + }, { "RM200PCI", + "SNI RM200_PCI", + MACH_GROUP_SNI_RM, + MACH_SNI_RM200_PCI, + 0 + } }; int prom_flags; @@ -37,7 +55,7 @@ int i; for (i = 0; i < (sizeof(mach_table) / sizeof (mach_table[0])); i++) { - if (!strcmp(s, mach_table[i].name)) + if (!strcmp(s, mach_table[i].arcname)) return &mach_table[i]; } prom_printf("\nYeee, could not determine architecture type <%s>\n", @@ -48,6 +66,13 @@ return NULL; } +char *system_type; + +const char *get_system_type(void) +{ + return system_type; +} + void __init prom_identify_arch(void) { pcomponent *p; @@ -60,6 +85,7 @@ p = prom_getchild(PROM_NULL_COMPONENT); printk("ARCH: %s\n", p->iname); mach = string_to_mach(p->iname); + system_type = mach->liname; mips_machgroup = mach->group; mips_machtype = mach->type; Index: arch/mips/au1000/pb1000/init.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/au1000/pb1000/init.c,v retrieving revision 1.4 diff -u -r1.4 init.c --- arch/mips/au1000/pb1000/init.c 2001/08/28 15:58:03 1.4 +++ arch/mips/au1000/pb1000/init.c 2001/12/11 22:46:55 @@ -44,6 +44,11 @@ extern void __init prom_init_cmdline(void); extern char *prom_getenv(char *envname); +const char *get_system_type(void) +{ + return "Alchemy PB1000"; +} + int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { unsigned char *memsize_str; Index: arch/mips/baget/prom/init.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/baget/prom/init.c,v retrieving revision 1.7 diff -u -r1.7 init.c --- arch/mips/baget/prom/init.c 2001/01/28 03:44:51 1.7 +++ arch/mips/baget/prom/init.c 2001/12/11 22:46:55 @@ -9,6 +9,12 @@ char arcs_cmdline[COMMAND_LINE_SIZE]; +const char *get_system_type(void) +{ + /* Should probably return one of "BT23-201", "BT23-202" */ + return "Baget"; +} + void __init prom_init(unsigned int mem_upper) { mem_upper = PHYSADDR(mem_upper); Index: arch/mips/ddb5074/prom.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/ddb5074/prom.c,v retrieving revision 1.6 diff -u -r1.6 prom.c --- arch/mips/ddb5074/prom.c 2000/12/13 19:43:03 1.6 +++ arch/mips/ddb5074/prom.c 2001/12/11 22:46:55 @@ -15,6 +15,11 @@ char arcs_cmdline[COMMAND_LINE_SIZE]; +const char *get_system_type(void) +{ + return "NEC DDB Vrc-5074"; +} + void __init prom_init(const char *s) { int i = 0; Index: arch/mips/ddb5xxx/common/prom.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/ddb5xxx/common/prom.c,v retrieving revision 1.2 diff -u -r1.2 prom.c --- arch/mips/ddb5xxx/common/prom.c 2001/09/26 01:37:34 1.2 +++ arch/mips/ddb5xxx/common/prom.c 2001/12/11 22:46:55 @@ -25,6 +25,17 @@ char arcs_cmdline[COMMAND_LINE_SIZE]; +const char *get_system_type(void) +{ +#if defined(CONFIG_DDB5074) + return "NEC DDB Vrc-5074"; +#elif defined(CONFIG_DDB5476) + return "NEC DDB Vrc-5476"; +#elif defined(CONFIG_DDB5477) + return "NEC DDB Vrc-5477"; +#endif +} + /* [jsun@junsun.net] PMON passes arguments in C main() style */ void __init prom_init(int argc, const char **arg) { Index: arch/mips/dec/prom/identify.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/dec/prom/identify.c,v retrieving revision 1.4 diff -u -r1.4 identify.c --- arch/mips/dec/prom/identify.c 2001/09/06 13:12:01 1.4 +++ arch/mips/dec/prom/identify.c 2001/12/11 22:46:55 @@ -19,6 +19,26 @@ extern unsigned long mips_machgroup; extern unsigned long mips_machtype; +extern unsigned long mips_machtype; +const char *get_system_type(void) +{ + static char system[32]; + int called = 0; + const char *dec_system_strings[] = { "unknown", "DECstation 2100/3100", + "DECstation 5100", "DECstation 5000/200", "DECstation 5000/1xx", + "Personal DECstation 5000/xx", "DECstation 5000/2x0", + "DECstation 5400", "DECstation 5500", "DECstation 5800" + }; + + if (called == 0) { + called = 1; + strcpy(system, "Digital "); + strcat(system, dec_system_strings[mips_machtype]); + } + + return system; +} + void __init prom_identify_arch (unsigned int magic) { unsigned char dec_cpunum, dec_firmrev, dec_etc; Index: arch/mips/galileo-boards/ev64120/setup.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/galileo-boards/ev64120/setup.c,v retrieving revision 1.8 diff -u -r1.8 setup.c --- arch/mips/galileo-boards/ev64120/setup.c 2001/11/25 09:25:53 1.8 +++ arch/mips/galileo-boards/ev64120/setup.c 2001/12/11 22:46:55 @@ -149,22 +149,25 @@ } -/******************************************************************** - *SetUpBootInfo - +const char *get_system_type(void) +{ + return "Galileo EV64120A"; +} + +/* + * SetUpBootInfo - * - *This function is called at very first stages of kernel startup. - *It specifies for the kernel the evaluation board that the linux - *is running on. Then it saves the eprom parameters that holds the - *command line, memory size etc... + * This function is called at very first stages of kernel startup. + * It specifies for the kernel the evaluation board that the linux + * is running on. Then it saves the eprom parameters that holds the + * command line, memory size etc... * - *Inputs : - *argc - nothing - *argv - holds a pointer to the eprom parameters - *envp - nothing - * - *Outpus : - * - *********************************************************************/ + * Inputs : + * argc - nothing + * argv - holds a pointer to the eprom parameters + * envp - nothing + */ + void SetUpBootInfo(int argc, char **argv, char **envp) { mips_machgroup = MACH_GROUP_GALILEO; Index: arch/mips/galileo-boards/ev96100/init.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/galileo-boards/ev96100/init.c,v retrieving revision 1.3 diff -u -r1.3 init.c --- arch/mips/galileo-boards/ev96100/init.c 2001/08/29 00:26:15 1.3 +++ arch/mips/galileo-boards/ev96100/init.c 2001/12/11 22:46:55 @@ -151,6 +151,10 @@ return 0; } +const char *get_system_type(void) +{ + return "Galileo EV96100"; +} void __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { Index: arch/mips/gt64120/momenco_ocelot/prom.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/gt64120/momenco_ocelot/prom.c,v retrieving revision 1.3 diff -u -r1.3 prom.c --- arch/mips/gt64120/momenco_ocelot/prom.c 2001/06/14 21:47:15 1.3 +++ arch/mips/gt64120/momenco_ocelot/prom.c 2001/12/11 22:46:55 @@ -34,6 +34,11 @@ char arcs_cmdline[COMMAND_LINE_SIZE]; +const char *get_system_type(void) +{ + return "Momentum Ocelot"; +} + /* [jsun@junsun.net] PMON passes arguments in C main() style */ void __init prom_init(int argc, const char **arg) { Index: arch/mips/hp-lj/setup.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/hp-lj/setup.c,v retrieving revision 1.2 diff -u -r1.2 setup.c --- arch/mips/hp-lj/setup.c 2001/11/27 15:29:00 1.2 +++ arch/mips/hp-lj/setup.c 2001/12/11 22:46:55 @@ -26,6 +26,10 @@ int remote_debug = 0; #endif +const char *get_system_type(void) +{ + return "HP LaserJet"; /* But which exactly? */ +} static void (*timer_interrupt_service)(int irq, void *dev_id, struct pt_regs * regs) = NULL; Index: arch/mips/ite-boards/ivr/init.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/ite-boards/ivr/init.c,v retrieving revision 1.1 diff -u -r1.1 init.c --- arch/mips/ite-boards/ivr/init.c 2001/03/16 12:34:03 1.1 +++ arch/mips/ite-boards/ivr/init.c 2001/12/11 22:46:55 @@ -52,6 +52,10 @@ #define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) #define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK) +const char *get_system_type(void) +{ + return "Globespan IVR"; +} int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { Index: arch/mips/ite-boards/qed-4n-s01b/init.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/ite-boards/qed-4n-s01b/init.c,v retrieving revision 1.2 diff -u -r1.2 init.c --- arch/mips/ite-boards/qed-4n-s01b/init.c 2001/03/16 12:44:20 1.2 +++ arch/mips/ite-boards/qed-4n-s01b/init.c 2001/12/11 22:46:55 @@ -52,6 +52,10 @@ #define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) #define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK) +const char *get_system_type(void) +{ + return "ITE QED-4N-S01B"; +} int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { Index: arch/mips/jmr3927/rbhma3100/init.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/jmr3927/rbhma3100/init.c,v retrieving revision 1.1 diff -u -r1.1 init.c --- arch/mips/jmr3927/rbhma3100/init.c 2001/11/26 12:01:09 1.1 +++ arch/mips/jmr3927/rbhma3100/init.c 2001/12/11 22:46:55 @@ -47,6 +47,15 @@ extern char *prom_getenv(char *envname); unsigned long mips_nofpu = 0; +const char *get_system_type(void) +{ + return "Toshiba" +#ifdef CONFIG_TOSHIBA_JMR3927 + "JMR_TX3927" +#endif + ; +} + extern void puts(unsigned char *cp); int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { Index: arch/mips/kernel/proc.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/kernel/proc.c,v retrieving revision 1.29 diff -u -r1.29 proc.c --- arch/mips/kernel/proc.c 2001/12/07 19:28:43 1.29 +++ arch/mips/kernel/proc.c 2001/12/11 22:46:55 @@ -35,6 +35,12 @@ return 0; #endif + /* + * For the first processor also print the system type + */ + if (n == 0) + seq_printf(m, "system type\t\t: %s\n", get_system_type()); + seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", (mips_cpu.options & MIPS_CPU_FPU) ? " FPU V%d.%d" : ""); Index: arch/mips/mips-boards/atlas/atlas_setup.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/mips-boards/atlas/atlas_setup.c,v retrieving revision 1.7 diff -u -r1.7 atlas_setup.c --- arch/mips/mips-boards/atlas/atlas_setup.c 2001/03/15 23:48:54 1.7 +++ arch/mips/mips-boards/atlas/atlas_setup.c 2001/12/11 22:46:55 @@ -47,6 +47,11 @@ extern void mips_reboot_setup(void); +const char *get_system_type(void) +{ + return "MIPS Atlas"; +} + void __init atlas_setup(void) { #ifdef CONFIG_REMOTE_DEBUG Index: arch/mips/mips-boards/malta/malta_setup.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/mips-boards/malta/malta_setup.c,v retrieving revision 1.7 diff -u -r1.7 malta_setup.c --- arch/mips/mips-boards/malta/malta_setup.c 2001/07/19 11:37:12 1.7 +++ arch/mips/mips-boards/malta/malta_setup.c 2001/12/11 22:46:55 @@ -65,6 +65,12 @@ #define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource)) +const char *get_system_type(void) +{ + return "MIPS Malta"; +} + + void __init malta_setup(void) { #ifdef CONFIG_REMOTE_DEBUG Index: arch/mips/philips/nino/prom.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/philips/nino/prom.c,v retrieving revision 1.6 diff -u -r1.6 prom.c --- arch/mips/philips/nino/prom.c 2001/11/24 14:03:19 1.6 +++ arch/mips/philips/nino/prom.c 2001/12/11 22:46:55 @@ -25,6 +25,11 @@ extern unsigned long tx3912fb_size; #endif +const char *get_system_type(void) +{ + return "Philips Nino"; +} + /* Do basic initialization */ void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec) { Index: arch/mips/sgi-ip22/ip22-hpc.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/sgi-ip22/ip22-hpc.c,v retrieving revision 1.1 diff -u -r1.1 ip22-hpc.c --- arch/mips/sgi-ip22/ip22-hpc.c 2001/11/27 15:57:11 1.1 +++ arch/mips/sgi-ip22/ip22-hpc.c 2001/12/11 22:46:55 @@ -26,6 +26,8 @@ int sgi_guiness = 0; int sgi_boardid; +extern char *system_type; + void __init sgihpc_init(void) { unsigned long sid, crev, brev; @@ -51,12 +53,14 @@ #endif sgi_guiness = 1; mips_machtype = MACH_SGI_INDY; + strcat(system_type, "Indy"); } else { #ifdef DEBUG_SGIHPC prom_printf("FULLHOUSE "); #endif mips_machtype = MACH_SGI_INDIGO2; sgi_guiness = 0; + strcat(system_type, "Indigo2"); } sgi_boardid = brev; Index: arch/mips/sibyte/swarm/setup.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/sibyte/swarm/setup.c,v retrieving revision 1.4 diff -u -r1.4 setup.c --- arch/mips/sibyte/swarm/setup.c 2001/12/02 17:44:09 1.4 +++ arch/mips/sibyte/swarm/setup.c 2001/12/11 22:46:55 @@ -64,6 +64,10 @@ #endif +const char *get_system_type(void) +{ + return "SiByte Swarm"; +} #ifdef CONFIG_BLK_DEV_IDE_SWARM static int swarm_ide_default_irq(ide_ioreg_t base) Index: arch/mips/vr4181/osprey/prom.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/vr4181/osprey/prom.c,v retrieving revision 1.1 diff -u -r1.1 prom.c --- arch/mips/vr4181/osprey/prom.c 2001/10/02 23:27:11 1.1 +++ arch/mips/vr4181/osprey/prom.c 2001/12/11 22:46:55 @@ -23,6 +23,11 @@ char arcs_cmdline[COMMAND_LINE_SIZE]; +const char *get_system_type(void) +{ + return "NEC_Vr41xx Osprey"; +} + /* * [jsun] right now we assume it is the nec debug monitor, which does * not pass any arguments. Index: include/asm-mips/bootinfo.h =================================================================== RCS file: /home/pub/cvs/linux/include/asm-mips/bootinfo.h,v retrieving revision 1.44 diff -u -r1.44 bootinfo.h --- include/asm-mips/bootinfo.h 2001/12/03 07:48:32 1.44 +++ include/asm-mips/bootinfo.h 2001/12/11 22:46:56 @@ -34,18 +34,11 @@ #define MACH_GROUP_NEC_VR41XX 19 /* NEC Vr41xx based boards/gadgets */ #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */ -#define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", "SNI", "ACN", \ - "SGI", "Cobalt", "NEC DDB", "Baget", "Cosine", "Galileo", "Momentum", \ - "ITE", "Philips", "Globepspan", "SiByte", "Toshiba", "Alchemy", \ - "NEC Vr41xx", "HP LaserJet" } - /* * Valid machtype values for group unknown (low order halfword of mips_machtype) */ #define MACH_UNKNOWN 0 /* whatever... */ -#define GROUP_UNKNOWN_NAMES { "unknown" } - /* * Valid machtype values for group JAZZ */ @@ -53,8 +46,6 @@ #define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ #define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ -#define GROUP_JAZZ_NAMES { "Acer PICA 61", "Mips Magnum 4000", "Olivetti M700" } - /* * Valid machtype for group DEC */ @@ -69,33 +60,22 @@ #define MACH_DS5500 8 /* DECstation 5500 */ #define MACH_DS5800 9 /* DECstation 5800 */ -#define GROUP_DEC_NAMES { "unknown", "DECstation 2100/3100", "DECstation 5100", \ - "DECstation 5000/200", "DECstation 5000/1xx", "Personal DECstation 5000/xx", \ - "DECstation 5000/2x0", "DECstation 5400", "DECstation 5500", \ - "DECstation 5800" } - /* * Valid machtype for group ARC */ #define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */ #define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */ -#define GROUP_ARC_NAMES { "Deskstation rPC44", "Deskstation Tyne" } - /* * Valid machtype for group SNI_RM */ #define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ -#define GROUP_SNI_RM_NAMES { "RM200 PCI" } - /* * Valid machtype for group ACN */ #define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */ -#define GROUP_ACN_NAMES { "ACN" } - /* * Valid machtype for group SGI */ @@ -103,15 +83,11 @@ #define MACH_SGI_CHALLENGE_S 1 /* The Challenge S server */ #define MACH_SGI_INDIGO2 2 /* The Indigo2 system */ -#define GROUP_SGI_NAMES { "Indy", "Challenge S", "Indigo2" } - /* * Valid machtype for group COBALT */ #define MACH_COBALT_27 0 /* Proto "27" hardware */ -#define GROUP_COBALT_NAMES { "Microserver 27" } - /* * Valid machtype for group NEC DDB */ @@ -119,68 +95,50 @@ #define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */ #define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */ -#define GROUP_NEC_DDB_NAMES { "Vrc-5074", "Vrc-5476", "Vrc-5477"} - /* * Valid machtype for group BAGET */ #define MACH_BAGET201 0 /* BT23-201 */ #define MACH_BAGET202 1 /* BT23-202 */ -#define GROUP_BAGET_NAMES { "BT23-201", "BT23-202" } - /* * Cosine boards. */ #define MACH_COSINE_ORION 0 -#define GROUP_COSINE_NAMES { "Orion" } - /* * Valid machtype for group GALILEO */ #define MACH_EV96100 0 /* EV96100 */ #define MACH_EV64120A 1 /* EV64120A */ -#define GROUP_GALILEO_NAMES { "EV96100" , "EV64120A" } - /* * Valid machtype for group MOMENCO */ #define MACH_MOMENCO_OCELOT 0 -#define GROUP_MOMENCO_NAMES { "Ocelot" } - /* * Valid machtype for group ITE */ #define MACH_QED_4N_S01B 0 /* ITE8172 based eval board */ -#define GROUP_ITE_NAMES { "QED-4N-S01B" } /* the actual board name */ - /* * Valid machtype for group Globespan */ #define MACH_IVR 0 /* IVR eval board */ -#define GROUP_GLOBESPAN_NAMES { "IVR" } /* the actual board name */ - /* * Valid machtype for group PHILIPS */ #define MACH_PHILIPS_NINO 0 /* Nino */ #define MACH_PHILIPS_VELO 1 /* Velo */ -#define GROUP_PHILIPS_NAMES { "Nino" , "Velo" } - /* * Valid machtype for group SIBYTE */ #define MACH_SWARM 0 -#define GROUP_SIBYTE_NAMES {"SWARM" } - /* * Valid machtypes for group Toshiba */ @@ -189,23 +147,16 @@ #define MACH_JMR 2 #define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ -#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927" } - /* * Valid machtype for group Alchemy */ #define MACH_PB1000 0 /* Au1000-based eval board */ -#define GROUP_ALCHEMY_NAMES { "PB1000" } /* the actual board name */ - /* * Valid machtype for group NEC_VR41XX */ #define MACH_NEC_OSPREY 0 /* Osprey eval board */ -#define GROUP_NEC_VR41XX_NAMES { "Osprey" } - - /* * Valid cputype values */ @@ -272,6 +223,8 @@ #define BOOT_MEM_RESERVED 3 #ifndef __ASSEMBLY__ + +const char *get_system_type(void); extern unsigned long mips_machtype; extern unsigned long mips_machgroup; From ralf@linux-mips.net Mon Dec 17 20:28:19 2001 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id UAA06284; Mon, 17 Dec 2001 20:28:19 +0100 (MET) Received-Date: Mon, 17 Dec 2001 20:28:19 +0100 (MET) Received: from oss.sgi.com(216.32.174.27) via SMTP by guadalquivir.fnet.fr, id smtpd006282; Mon Dec 17 20:28:14 2001 Received: from dea.linux-mips.net (localhost [127.0.0.1]) by oss.sgi.com (8.11.2/8.11.3) with ESMTP id fBHKS7o31949 for ; Mon, 17 Dec 2001 12:28:08 -0800 Received: (from ralf@localhost) by dea.linux-mips.net (8.11.1/8.11.1) id fBHJRfQ02322; Mon, 17 Dec 2001 17:27:41 -0200 Date: Mon, 17 Dec 2001 17:27:41 -0200 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: linux-mips@oss.sgi.com, linux-mips@fnet.fr Subject: New style irqs for DEC Message-ID: <20011217172741.A2316@dea.linux-mips.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5i X-Accept-Language: de,en,fr Content-Length: 29774 Lines: 1154 Maciej, below is my attempt at fixing interrupts for DECstation against the latest 2.4. Can you give it a try? Ralf Index: arch/mips/config.in =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/config.in,v retrieving revision 1.154.2.7 diff -u -r1.154.2.7 config.in --- arch/mips/config.in 2001/12/14 23:49:15 1.154.2.7 +++ arch/mips/config.in 2001/12/17 20:21:54 @@ -83,6 +83,7 @@ define_bool CONFIG_SBUS n if [ "$CONFIG_DECSTATION" = "y" ]; then + define_bool CONFIG_NEW_IRQ y define_bool CONFIG_NONCOHERENT_IO y fi Index: arch/mips/defconfig-decstation =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/defconfig-decstation,v retrieving revision 1.76.2.1 diff -u -r1.76.2.1 defconfig-decstation --- arch/mips/defconfig-decstation 2001/12/14 23:47:16 1.76.2.1 +++ arch/mips/defconfig-decstation 2001/12/17 20:21:54 @@ -39,6 +39,7 @@ # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set # CONFIG_MCA is not set # CONFIG_SBUS is not set +CONFIG_NEW_IRQ=y CONFIG_NONCOHERENT_IO=y # CONFIG_ISA is not set # CONFIG_EISA is not set Index: arch/mips/dec/irq.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/dec/irq.c,v retrieving revision 1.17 diff -u -r1.17 irq.c --- arch/mips/dec/irq.c 2001/12/02 02:02:21 1.17 +++ arch/mips/dec/irq.c 2001/12/17 20:21:54 @@ -34,242 +34,89 @@ extern asmlinkage void decstation_handle_int(void); -volatile unsigned long irq_err_count; +spinlock_t DEC_lock = SPIN_LOCK_UNLOCKED; -static inline void mask_irq(unsigned int irq_nr) +static inline void mask_dec_irq(unsigned int irq_nr) { unsigned int dummy; - if (dec_interrupt[irq_nr].iemask) { /* This is an ASIC interrupt */ + if (dec_interrupt[irq_nr].iemask) { + /* This is an ASIC interrupt */ *imr &= ~dec_interrupt[irq_nr].iemask; dummy = *imr; dummy = *imr; - } else /* This is a cpu interrupt */ + } else { + /* This is a cpu interrupt */ change_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) & ~dec_interrupt[irq_nr].cpu_mask); + } } -static inline void unmask_irq(unsigned int irq_nr) +static inline void unmask_dec_irq(unsigned int irq_nr) { unsigned int dummy; - if (dec_interrupt[irq_nr].iemask) { /* This is an ASIC interrupt */ + if (dec_interrupt[irq_nr].iemask) { + /* This is an ASIC interrupt */ *imr |= dec_interrupt[irq_nr].iemask; dummy = *imr; dummy = *imr; } - change_cp0_status(ST0_IM, - read_32bit_cp0_register(CP0_STATUS) | + change_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) | dec_interrupt[irq_nr].cpu_mask); } - -void disable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - save_and_cli(flags); - mask_irq(irq_nr); - restore_flags(flags); -} - -void enable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - save_and_cli(flags); - unmask_irq(irq_nr); - restore_flags(flags); -} - -/* - * Pointers to the low-level handlers: first the general ones, then the - * fast ones, then the bad ones. - */ -extern void interrupt(void); - -static struct irqaction *irq_action[32] = { - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL -}; - -int get_irq_list(char *buf) -{ - int i, len = 0; - struct irqaction *action; - for (i = 0; i < 32; i++) { - action = irq_action[i]; - if (!action) - continue; - len += sprintf(buf + len, "%2d: %8d %c %s", - i, kstat.irqs[0][i], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action = action->next; action; action = action->next) { - len += sprintf(buf + len, ",%s %s", - (action-> - flags & SA_INTERRUPT) ? " +" : "", - action->name); - } - len += sprintf(buf + len, "\n"); - } - return len; -} +#define shutdown_dec_irq disable_dec_irq -/* - * do_IRQ handles IRQ's that have been installed without the - * SA_INTERRUPT flag: it uses the full signal-handling return - * and runs with other interrupts enabled. All relatively slow - * IRQ's should use this format: notably the keyboard/timer - * routines. - */ -asmlinkage void do_IRQ(int irq, struct pt_regs *regs) +static unsigned int startup_dec_irq(unsigned int irq) { - struct irqaction *action; - int do_random, cpu; - - cpu = smp_processor_id(); - irq_enter(cpu, irq); - kstat.irqs[cpu][irq]++; - - mask_irq(irq); - action = *(irq + irq_action); - if (action) { - if (!(action->flags & SA_INTERRUPT)) - __sti(); - action = *(irq + irq_action); - do_random = 0; - do { - do_random |= action->flags; - action->handler(irq, action->dev_id, regs); - action = action->next; - } while (action); - if (do_random & SA_SAMPLE_RANDOM) - add_interrupt_randomness(irq); - __cli(); - unmask_irq(irq); - } - irq_exit(cpu, irq); + unmask_dec_irq(irq); - if (softirq_pending(cpu)) - do_softirq(); + return 0; /* never anything pending */ } -/* - * Idea is to put all interrupts - * in a single table and differenciate them just by number. - */ -int setup_dec_irq(int irq, struct irqaction *new) +static void disable_dec_irq(unsigned int irq_nr) { - int shared = 0; - struct irqaction *old, **p; unsigned long flags; - p = irq_action + irq; - if ((old = *p) != NULL) { - /* Can't share interrupts unless both agree to */ - if (!(old->flags & new->flags & SA_SHIRQ)) - return -EBUSY; - - /* Can't share interrupts unless both are same type */ - if ((old->flags ^ new->flags) & SA_INTERRUPT) - return -EBUSY; - - /* add new interrupt at end of irq queue */ - do { - p = &old->next; - old = *p; - } while (old); - shared = 1; - } - if (new->flags & SA_SAMPLE_RANDOM) - rand_initialize_irq(irq); - - save_and_cli(flags); - *p = new; - - if (!shared) { - unmask_irq(irq); - } - restore_flags(flags); - return 0; -} - -int request_irq(unsigned int irq, - void (*handler) (int, void *, struct pt_regs *), - unsigned long irqflags, const char *devname, void *dev_id) -{ - int retval; - struct irqaction *action; - - if (irq >= 32) - return -EINVAL; - if (!handler) - return -EINVAL; - - action = - (struct irqaction *) kmalloc(sizeof(struct irqaction), - GFP_KERNEL); - if (!action) - return -ENOMEM; - - action->handler = handler; - action->flags = irqflags; - action->mask = 0; - action->name = devname; - action->next = NULL; - action->dev_id = dev_id; - - retval = setup_dec_irq(irq, action); - - if (retval) - kfree(action); - return retval; + spin_lock_irqsave(&DEC_lock, flags); + mask_dec_irq(irq_nr); + spin_unlock_irqrestore(&DEC_lock, flags); } -void free_irq(unsigned int irq, void *dev_id) +static inline void enable_dec_irq(unsigned int irq_nr) { - struct irqaction *action, **p; unsigned long flags; - if (irq > 39) { - printk("Trying to free IRQ%d\n", irq); - return; - } - for (p = irq + irq_action; (action = *p) != NULL; - p = &action->next) { - if (action->dev_id != dev_id) - continue; - - /* Found it - now free it */ - save_and_cli(flags); - *p = action->next; - if (!irq[irq_action]) - mask_irq(irq); - restore_flags(flags); - kfree(action); - return; - } - printk("Trying to free free IRQ%d\n", irq); + spin_lock_irqsave(&DEC_lock, flags); + unmask_dec_irq(irq_nr); + spin_unlock_irqrestore(&DEC_lock, flags); } -unsigned long probe_irq_on(void) -{ - /* TODO */ - return 0; -} +#define mask_and_ack_dec_irq disable_dec_irq -int probe_irq_off(unsigned long irqs) +static void end_dec_irq (unsigned int irq) { - /* TODO */ - return 0; + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_dec_irq(irq); } +static struct hw_interrupt_type dec_irq_type = { + "DEC", + startup_dec_irq, + shutdown_dec_irq, + enable_dec_irq, + disable_dec_irq, + mask_and_ack_dec_irq, + end_dec_irq, + NULL +}; + void __init init_IRQ(void) { + int i; + switch (mips_machtype) { case MACH_DS23100: dec_init_kn01(); @@ -300,4 +147,13 @@ break; } set_except_vector(0, decstation_handle_int); + + init_generic_irq(); + + for (i = 0; i < 32; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &dec_irq_type; + } } Index: arch/mips/dec/setup.c =================================================================== RCS file: /home/pub/cvs/linux/arch/mips/dec/setup.c,v retrieving revision 1.11 diff -u -r1.11 setup.c --- arch/mips/dec/setup.c 2001/11/24 16:47:23 1.11 +++ arch/mips/dec/setup.c 2001/12/17 20:21:54 @@ -28,7 +28,6 @@ #include #include - char *dec_rtc_base = (void *) KN01_RTC_BASE; /* Assume DS2100/3100 initially */ volatile unsigned int *ioasic_base; @@ -51,28 +50,26 @@ extern struct rtc_ops dec_rtc_ops; -extern int setup_dec_irq(int, struct irqaction *); - void (*board_time_init) (struct irqaction * irq); -static struct irqaction haltirq = {dec_intr_halt, 0, 0, "halt", NULL, NULL}; +static struct irqaction haltirq = { dec_intr_halt, 0, 0, "halt", NULL, NULL }; /* * enable the periodic interrupts */ static void __init dec_time_init(struct irqaction *irq) { - /* - * Here we go, enable periodic rtc interrupts. - */ + /* + * Here we go, enable periodic rtc interrupts. + */ #ifndef LOG_2_HZ # define LOG_2_HZ 7 #endif - CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A); - CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B); - setup_dec_irq(CLOCK, irq); + CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A); + CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B); + setup_irq(CLOCK, irq); } /* @@ -80,24 +77,24 @@ */ static void __init dec_halt_init(struct irqaction *irq) { - setup_dec_irq(HALT, irq); + setup_irq(HALT, irq); } void __init decstation_setup(void) { - board_time_init = dec_time_init; + board_time_init = dec_time_init; - wbflush_setup(); + wbflush_setup(); - _machine_restart = dec_machine_restart; - _machine_halt = dec_machine_halt; - _machine_power_off = dec_machine_power_off; + _machine_restart = dec_machine_restart; + _machine_halt = dec_machine_halt; + _machine_power_off = dec_machine_power_off; #ifdef CONFIG_FB - conswitchp = &dummy_con; + conswitchp = &dummy_con; #endif - rtc_ops = &dec_rtc_ops; + rtc_ops = &dec_rtc_ops; } /* @@ -106,43 +103,43 @@ */ void __init dec_init_kn01(void) { - /* - * Setup some memory addresses. - */ - dec_rtc_base = (char *) KN01_RTC_BASE; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ3; - dec_interrupt[CLOCK].iemask = 0; - cpu_mask_tbl[0] = IE_IRQ3; - cpu_irq_nr[0] = CLOCK; - - dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0; - dec_interrupt[SCSI_INT].iemask = 0; - cpu_mask_tbl[1] = IE_IRQ0; - cpu_irq_nr[1] = SCSI_INT; - - dec_interrupt[ETHER].cpu_mask = IE_IRQ1; - dec_interrupt[ETHER].iemask = 0; - cpu_mask_tbl[2] = IE_IRQ1; - cpu_irq_nr[2] = ETHER; - - dec_interrupt[SERIAL].cpu_mask = IE_IRQ2; - dec_interrupt[SERIAL].iemask = 0; - cpu_mask_tbl[3] = IE_IRQ2; - cpu_irq_nr[3] = SERIAL; - - dec_interrupt[MEMORY].cpu_mask = IE_IRQ4; - dec_interrupt[MEMORY].iemask = 0; - cpu_mask_tbl[4] = IE_IRQ4; - cpu_irq_nr[4] = MEMORY; - - /* - * Enable board interrupts: FPU. - */ - set_cp0_status(DEC_IE_FPU); + /* + * Setup some memory addresses. + */ + dec_rtc_base = (char *) KN01_RTC_BASE; + + /* + * Setup interrupt structure + */ + dec_interrupt[CLOCK].cpu_mask = IE_IRQ3; + dec_interrupt[CLOCK].iemask = 0; + cpu_mask_tbl[0] = IE_IRQ3; + cpu_irq_nr[0] = CLOCK; + + dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0; + dec_interrupt[SCSI_INT].iemask = 0; + cpu_mask_tbl[1] = IE_IRQ0; + cpu_irq_nr[1] = SCSI_INT; + + dec_interrupt[ETHER].cpu_mask = IE_IRQ1; + dec_interrupt[ETHER].iemask = 0; + cpu_mask_tbl[2] = IE_IRQ1; + cpu_irq_nr[2] = ETHER; + + dec_interrupt[SERIAL].cpu_mask = IE_IRQ2; + dec_interrupt[SERIAL].iemask = 0; + cpu_mask_tbl[3] = IE_IRQ2; + cpu_irq_nr[3] = SERIAL; + + dec_interrupt[MEMORY].cpu_mask = IE_IRQ4; + dec_interrupt[MEMORY].iemask = 0; + cpu_mask_tbl[4] = IE_IRQ4; + cpu_irq_nr[4] = MEMORY; + + /* + * Enable board interrupts: FPU. + */ + set_cp0_status(DEC_IE_FPU); } /* dec_init_kn01 */ /* @@ -152,23 +149,23 @@ */ void __init dec_init_kn230(void) { - /* - * Setup some memory addresses. - */ - dec_rtc_base = (char *) KN01_RTC_BASE; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ2; - dec_interrupt[CLOCK].iemask = 0; - cpu_mask_tbl[0] = IE_IRQ2; - cpu_irq_nr[0] = CLOCK; - - /* - * Enable board interrupts: FPU. - */ - set_cp0_status(DEC_IE_FPU); + /* + * Setup some memory addresses. + */ + dec_rtc_base = (char *) KN01_RTC_BASE; + + /* + * Setup interrupt structure + */ + dec_interrupt[CLOCK].cpu_mask = IE_IRQ2; + dec_interrupt[CLOCK].iemask = 0; + cpu_mask_tbl[0] = IE_IRQ2; + cpu_irq_nr[0] = CLOCK; + + /* + * Enable board interrupts: FPU. + */ + set_cp0_status(DEC_IE_FPU); } /* dec_init_kn230 */ /* @@ -176,71 +173,71 @@ */ void __init dec_init_kn02(void) { - int dec_ie_io; + int dec_ie_io; - /* - * Setup some memory addresses. FIXME: probably incomplete! - */ - dec_rtc_base = (char *) KN02_RTC_BASE; - isr = (void *) KN02_CSR_ADDR; - imr = (void *) KN02_CSR_ADDR; - - /* - * Setup I/O interrupt - */ - dec_ie_io = IE_IRQ0; - cpu_ivec_tbl[1] = kn02_io_int; - cpu_mask_tbl[1] = dec_ie_io; - cpu_irq_nr[1] = -1; - *imr = *imr & 0xff00ff00; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ1; - dec_interrupt[CLOCK].iemask = 0; - cpu_mask_tbl[0] = IE_IRQ1; - cpu_irq_nr[0] = CLOCK; - - dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0; - dec_interrupt[SCSI_INT].iemask = KN02_SLOT5; - asic_mask_tbl[0] = KN02_SLOT5; - asic_irq_nr[0] = SCSI_INT; - - dec_interrupt[ETHER].cpu_mask = IE_IRQ0; - dec_interrupt[ETHER].iemask = KN02_SLOT6; - asic_mask_tbl[1] = KN02_SLOT6; - asic_irq_nr[1] = ETHER; - - dec_interrupt[SERIAL].cpu_mask = IE_IRQ0; - dec_interrupt[SERIAL].iemask = KN02_SLOT7; - asic_mask_tbl[2] = KN02_SLOT7; - asic_irq_nr[2] = SERIAL; - - dec_interrupt[TC0].cpu_mask = IE_IRQ0; - dec_interrupt[TC0].iemask = KN02_SLOT0; - asic_mask_tbl[3] = KN02_SLOT0; - asic_irq_nr[3] = TC0; - - dec_interrupt[TC1].cpu_mask = IE_IRQ0; - dec_interrupt[TC1].iemask = KN02_SLOT1; - asic_mask_tbl[4] = KN02_SLOT1; - asic_irq_nr[4] = TC1; - - dec_interrupt[TC2].cpu_mask = IE_IRQ0; - dec_interrupt[TC2].iemask = KN02_SLOT2; - asic_mask_tbl[5] = KN02_SLOT2; - asic_irq_nr[5] = TC2; - - dec_interrupt[MEMORY].cpu_mask = IE_IRQ3; - dec_interrupt[MEMORY].iemask = 0; - cpu_mask_tbl[2] = IE_IRQ3; - cpu_irq_nr[2] = MEMORY; - - /* - * Enable board interrupts: FPU, I/O. - */ - set_cp0_status(DEC_IE_FPU | dec_ie_io); + /* + * Setup some memory addresses. FIXME: probably incomplete! + */ + dec_rtc_base = (char *) KN02_RTC_BASE; + isr = (void *) KN02_CSR_ADDR; + imr = (void *) KN02_CSR_ADDR; + + /* + * Setup I/O interrupt + */ + dec_ie_io = IE_IRQ0; + cpu_ivec_tbl[1] = kn02_io_int; + cpu_mask_tbl[1] = dec_ie_io; + cpu_irq_nr[1] = -1; + *imr = *imr & 0xff00ff00; + + /* + * Setup interrupt structure + */ + dec_interrupt[CLOCK].cpu_mask = IE_IRQ1; + dec_interrupt[CLOCK].iemask = 0; + cpu_mask_tbl[0] = IE_IRQ1; + cpu_irq_nr[0] = CLOCK; + + dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0; + dec_interrupt[SCSI_INT].iemask = KN02_SLOT5; + asic_mask_tbl[0] = KN02_SLOT5; + asic_irq_nr[0] = SCSI_INT; + + dec_interrupt[ETHER].cpu_mask = IE_IRQ0; + dec_interrupt[ETHER].iemask = KN02_SLOT6; + asic_mask_tbl[1] = KN02_SLOT6; + asic_irq_nr[1] = ETHER; + + dec_interrupt[SERIAL].cpu_mask = IE_IRQ0; + dec_interrupt[SERIAL].iemask = KN02_SLOT7; + asic_mask_tbl[2] = KN02_SLOT7; + asic_irq_nr[2] = SERIAL; + + dec_interrupt[TC0].cpu_mask = IE_IRQ0; + dec_interrupt[TC0].iemask = KN02_SLOT0; + asic_mask_tbl[3] = KN02_SLOT0; + asic_irq_nr[3] = TC0; + + dec_interrupt[TC1].cpu_mask = IE_IRQ0; + dec_interrupt[TC1].iemask = KN02_SLOT1; + asic_mask_tbl[4] = KN02_SLOT1; + asic_irq_nr[4] = TC1; + + dec_interrupt[TC2].cpu_mask = IE_IRQ0; + dec_interrupt[TC2].iemask = KN02_SLOT2; + asic_mask_tbl[5] = KN02_SLOT2; + asic_irq_nr[5] = TC2; + + dec_interrupt[MEMORY].cpu_mask = IE_IRQ3; + dec_interrupt[MEMORY].iemask = 0; + cpu_mask_tbl[2] = IE_IRQ3; + cpu_irq_nr[2] = MEMORY; + + /* + * Enable board interrupts: FPU, I/O. + */ + set_cp0_status(DEC_IE_FPU | dec_ie_io); } /* dec_init_kn02 */ /* @@ -248,84 +245,84 @@ */ void __init dec_init_kn02ba(void) { - int dec_ie_ioasic; + int dec_ie_ioasic; - /* - * Setup some memory addresses. - */ - ioasic_base = (void *) KN02XA_IOASIC_BASE; - dec_rtc_base = (char *) KN02XA_RTC_BASE; - isr = (void *) KN02XA_IOASIC_REG(SIR); - imr = (void *) KN02XA_IOASIC_REG(SIMR); - - /* - * Setup IOASIC interrupt - */ - dec_ie_ioasic = IE_IRQ3; - cpu_ivec_tbl[0] = kn02xa_io_int; - cpu_mask_tbl[0] = dec_ie_ioasic; - cpu_irq_nr[0] = -1; - *imr = 0; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ3; - dec_interrupt[CLOCK].iemask = KMIN_CLOCK; - asic_mask_tbl[0] = KMIN_CLOCK; - asic_irq_nr[0] = CLOCK; - - dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3; - dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS; - asic_mask_tbl[1] = SCSI_DMA_INTS; - asic_irq_nr[1] = SCSI_DMA_INT; - - dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3; - dec_interrupt[SCSI_INT].iemask = SCSI_CHIP; - asic_mask_tbl[2] = SCSI_CHIP; - asic_irq_nr[2] = SCSI_INT; - - dec_interrupt[ETHER].cpu_mask = IE_IRQ3; - dec_interrupt[ETHER].iemask = LANCE_INTS; - asic_mask_tbl[3] = LANCE_INTS; - asic_irq_nr[3] = ETHER; - - dec_interrupt[SERIAL].cpu_mask = IE_IRQ3; - dec_interrupt[SERIAL].iemask = SERIAL_INTS; - asic_mask_tbl[4] = SERIAL_INTS; - asic_irq_nr[4] = SERIAL; - - dec_interrupt[MEMORY].cpu_mask = IE_IRQ3; - dec_interrupt[MEMORY].iemask = KMIN_TIMEOUT; - asic_mask_tbl[5] = KMIN_TIMEOUT; - asic_irq_nr[5] = MEMORY; - - dec_interrupt[TC0].cpu_mask = IE_IRQ0; - dec_interrupt[TC0].iemask = 0; - cpu_mask_tbl[1] = IE_IRQ0; - cpu_irq_nr[1] = TC0; - - dec_interrupt[TC1].cpu_mask = IE_IRQ1; - dec_interrupt[TC1].iemask = 0; - cpu_mask_tbl[2] = IE_IRQ1; - cpu_irq_nr[2] = TC1; - - dec_interrupt[TC2].cpu_mask = IE_IRQ2; - dec_interrupt[TC2].iemask = 0; - cpu_mask_tbl[3] = IE_IRQ2; - cpu_irq_nr[3] = TC2; - - dec_interrupt[HALT].cpu_mask = IE_IRQ4; - dec_interrupt[HALT].iemask = 0; - cpu_mask_tbl[4] = IE_IRQ4; - cpu_irq_nr[4] = HALT; - - /* - * Enable board interrupts: FPU, I/O ASIC. - */ - set_cp0_status(DEC_IE_FPU | dec_ie_ioasic); + /* + * Setup some memory addresses. + */ + ioasic_base = (void *) KN02XA_IOASIC_BASE; + dec_rtc_base = (char *) KN02XA_RTC_BASE; + isr = (void *) KN02XA_IOASIC_REG(SIR); + imr = (void *) KN02XA_IOASIC_REG(SIMR); + + /* + * Setup IOASIC interrupt + */ + dec_ie_ioasic = IE_IRQ3; + cpu_ivec_tbl[0] = kn02xa_io_int; + cpu_mask_tbl[0] = dec_ie_ioasic; + cpu_irq_nr[0] = -1; + *imr = 0; + + /* + * Setup interrupt structure + */ + dec_interrupt[CLOCK].cpu_mask = IE_IRQ3; + dec_interrupt[CLOCK].iemask = KMIN_CLOCK; + asic_mask_tbl[0] = KMIN_CLOCK; + asic_irq_nr[0] = CLOCK; + + dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3; + dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS; + asic_mask_tbl[1] = SCSI_DMA_INTS; + asic_irq_nr[1] = SCSI_DMA_INT; + + dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3; + dec_interrupt[SCSI_INT].iemask = SCSI_CHIP; + asic_mask_tbl[2] = SCSI_CHIP; + asic_irq_nr[2] = SCSI_INT; + + dec_interrupt[ETHER].cpu_mask = IE_IRQ3; + dec_interrupt[ETHER].iemask = LANCE_INTS; + asic_mask_tbl[3] = LANCE_INTS; + asic_irq_nr[3] = ETHER; + + dec_interrupt[SERIAL].cpu_mask = IE_IRQ3; + dec_interrupt[SERIAL].iemask = SERIAL_INTS; + asic_mask_tbl[4] = SERIAL_INTS; + asic_irq_nr[4] = SERIAL; + + dec_interrupt[MEMORY].cpu_mask = IE_IRQ3; + dec_interrupt[MEMORY].iemask = KMIN_TIMEOUT; + asic_mask_tbl[5] = KMIN_TIMEOUT; + asic_irq_nr[5] = MEMORY; + + dec_interrupt[TC0].cpu_mask = IE_IRQ0; + dec_interrupt[TC0].iemask = 0; + cpu_mask_tbl[1] = IE_IRQ0; + cpu_irq_nr[1] = TC0; + + dec_interrupt[TC1].cpu_mask = IE_IRQ1; + dec_interrupt[TC1].iemask = 0; + cpu_mask_tbl[2] = IE_IRQ1; + cpu_irq_nr[2] = TC1; + + dec_interrupt[TC2].cpu_mask = IE_IRQ2; + dec_interrupt[TC2].iemask = 0; + cpu_mask_tbl[3] = IE_IRQ2; + cpu_irq_nr[3] = TC2; + + dec_interrupt[HALT].cpu_mask = IE_IRQ4; + dec_interrupt[HALT].iemask = 0; + cpu_mask_tbl[4] = IE_IRQ4; + cpu_irq_nr[4] = HALT; + + /* + * Enable board interrupts: FPU, I/O ASIC. + */ + set_cp0_status(DEC_IE_FPU | dec_ie_ioasic); - dec_halt_init(&haltirq); + dec_halt_init(&haltirq); } /* dec_init_kn02ba */ /* @@ -333,79 +330,79 @@ */ void __init dec_init_kn02ca(void) { - int dec_ie_ioasic; + int dec_ie_ioasic; - /* - * Setup some memory addresses. FIXME: probably incomplete! - */ - ioasic_base = (void *) KN02XA_IOASIC_BASE; - dec_rtc_base = (char *) KN02XA_RTC_BASE; - isr = (void *) KN02XA_IOASIC_REG(SIR); - imr = (void *) KN02XA_IOASIC_REG(SIMR); - - /* - * Setup IOASIC interrupt - */ - dec_ie_ioasic = IE_IRQ3; - cpu_ivec_tbl[1] = kn02xa_io_int; - cpu_mask_tbl[1] = dec_ie_ioasic; - cpu_irq_nr[1] = -1; - *imr = 0; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ1; - dec_interrupt[CLOCK].iemask = 0; - cpu_mask_tbl[0] = IE_IRQ1; - cpu_irq_nr[0] = CLOCK; - - dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3; - dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS; - asic_mask_tbl[0] = SCSI_DMA_INTS; - asic_irq_nr[0] = SCSI_DMA_INT; - - dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3; - dec_interrupt[SCSI_INT].iemask = SCSI_CHIP; - asic_mask_tbl[1] = SCSI_CHIP; - asic_irq_nr[1] = SCSI_INT; - - dec_interrupt[ETHER].cpu_mask = IE_IRQ3; - dec_interrupt[ETHER].iemask = LANCE_INTS; - asic_mask_tbl[2] = LANCE_INTS; - asic_irq_nr[2] = ETHER; - - dec_interrupt[SERIAL].cpu_mask = IE_IRQ3; - dec_interrupt[SERIAL].iemask = XINE_SERIAL_INTS; - asic_mask_tbl[3] = XINE_SERIAL_INTS; - asic_irq_nr[3] = SERIAL; - - dec_interrupt[TC0].cpu_mask = IE_IRQ3; - dec_interrupt[TC0].iemask = MAXINE_TC0; - asic_mask_tbl[4] = MAXINE_TC0; - asic_irq_nr[4] = TC0; - - dec_interrupt[TC1].cpu_mask = IE_IRQ3; - dec_interrupt[TC1].iemask = MAXINE_TC1; - asic_mask_tbl[5] = MAXINE_TC1; - asic_irq_nr[5] = TC1; - - dec_interrupt[MEMORY].cpu_mask = IE_IRQ2; - dec_interrupt[MEMORY].iemask = 0; - cpu_mask_tbl[2] = IE_IRQ2; - cpu_irq_nr[2] = MEMORY; - - dec_interrupt[HALT].cpu_mask = IE_IRQ4; - dec_interrupt[HALT].iemask = 0; - cpu_mask_tbl[3] = IE_IRQ4; - cpu_irq_nr[3] = HALT; - - /* - * Enable board interrupts: FPU, I/O ASIC. - */ - set_cp0_status(DEC_IE_FPU | dec_ie_ioasic); + /* + * Setup some memory addresses. FIXME: probably incomplete! + */ + ioasic_base = (void *) KN02XA_IOASIC_BASE; + dec_rtc_base = (char *) KN02XA_RTC_BASE; + isr = (void *) KN02XA_IOASIC_REG(SIR); + imr = (void *) KN02XA_IOASIC_REG(SIMR); + + /* + * Setup IOASIC interrupt + */ + dec_ie_ioasic = IE_IRQ3; + cpu_ivec_tbl[1] = kn02xa_io_int; + cpu_mask_tbl[1] = dec_ie_ioasic; + cpu_irq_nr[1] = -1; + *imr = 0; + + /* + * Setup interrupt structure + */ + dec_interrupt[CLOCK].cpu_mask = IE_IRQ1; + dec_interrupt[CLOCK].iemask = 0; + cpu_mask_tbl[0] = IE_IRQ1; + cpu_irq_nr[0] = CLOCK; + + dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3; + dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS; + asic_mask_tbl[0] = SCSI_DMA_INTS; + asic_irq_nr[0] = SCSI_DMA_INT; + + dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3; + dec_interrupt[SCSI_INT].iemask = SCSI_CHIP; + asic_mask_tbl[1] = SCSI_CHIP; + asic_irq_nr[1] = SCSI_INT; + + dec_interrupt[ETHER].cpu_mask = IE_IRQ3; + dec_interrupt[ETHER].iemask = LANCE_INTS; + asic_mask_tbl[2] = LANCE_INTS; + asic_irq_nr[2] = ETHER; + + dec_interrupt[SERIAL].cpu_mask = IE_IRQ3; + dec_interrupt[SERIAL].iemask = XINE_SERIAL_INTS; + asic_mask_tbl[3] = XINE_SERIAL_INTS; + asic_irq_nr[3] = SERIAL; + + dec_interrupt[TC0].cpu_mask = IE_IRQ3; + dec_interrupt[TC0].iemask = MAXINE_TC0; + asic_mask_tbl[4] = MAXINE_TC0; + asic_irq_nr[4] = TC0; + + dec_interrupt[TC1].cpu_mask = IE_IRQ3; + dec_interrupt[TC1].iemask = MAXINE_TC1; + asic_mask_tbl[5] = MAXINE_TC1; + asic_irq_nr[5] = TC1; + + dec_interrupt[MEMORY].cpu_mask = IE_IRQ2; + dec_interrupt[MEMORY].iemask = 0; + cpu_mask_tbl[2] = IE_IRQ2; + cpu_irq_nr[2] = MEMORY; + + dec_interrupt[HALT].cpu_mask = IE_IRQ4; + dec_interrupt[HALT].iemask = 0; + cpu_mask_tbl[3] = IE_IRQ4; + cpu_irq_nr[3] = HALT; + + /* + * Enable board interrupts: FPU, I/O ASIC. + */ + set_cp0_status(DEC_IE_FPU | dec_ie_ioasic); - dec_halt_init(&haltirq); + dec_halt_init(&haltirq); } /* dec_init_kn02ca */ /* @@ -413,82 +410,82 @@ */ void __init dec_init_kn03(void) { - int dec_ie_ioasic; + int dec_ie_ioasic; - /* - * Setup some memory addresses. FIXME: probably incomplete! - */ - ioasic_base = (void *) KN03_IOASIC_BASE; - dec_rtc_base = (char *) KN03_RTC_BASE; - isr = (void *) KN03_IOASIC_REG(SIR); - imr = (void *) KN03_IOASIC_REG(SIMR); - - /* - * Setup IOASIC interrupt - */ - dec_ie_ioasic = IE_IRQ0; - cpu_ivec_tbl[1] = kn03_io_int; - cpu_mask_tbl[1] = dec_ie_ioasic; - cpu_irq_nr[1] = -1; - *imr = 0; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ1; - dec_interrupt[CLOCK].iemask = 0; - cpu_mask_tbl[0] = IE_IRQ1; - cpu_irq_nr[0] = CLOCK; - - dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ0; - dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS; - asic_mask_tbl[0] = SCSI_DMA_INTS; - asic_irq_nr[0] = SCSI_DMA_INT; - - dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0; - dec_interrupt[SCSI_INT].iemask = SCSI_CHIP; - asic_mask_tbl[1] = SCSI_CHIP; - asic_irq_nr[1] = SCSI_INT; - - dec_interrupt[ETHER].cpu_mask = IE_IRQ0; - dec_interrupt[ETHER].iemask = LANCE_INTS; - asic_mask_tbl[2] = LANCE_INTS; - asic_irq_nr[2] = ETHER; - - dec_interrupt[SERIAL].cpu_mask = IE_IRQ0; - dec_interrupt[SERIAL].iemask = SERIAL_INTS; - asic_mask_tbl[3] = SERIAL_INTS; - asic_irq_nr[3] = SERIAL; - - dec_interrupt[TC0].cpu_mask = IE_IRQ0; - dec_interrupt[TC0].iemask = KN03_TC0; - asic_mask_tbl[4] = KN03_TC0; - asic_irq_nr[4] = TC0; - - dec_interrupt[TC1].cpu_mask = IE_IRQ0; - dec_interrupt[TC1].iemask = KN03_TC1; - asic_mask_tbl[5] = KN03_TC1; - asic_irq_nr[5] = TC1; - - dec_interrupt[TC2].cpu_mask = IE_IRQ0; - dec_interrupt[TC2].iemask = KN03_TC2; - asic_mask_tbl[6] = KN03_TC2; - asic_irq_nr[6] = TC2; - - dec_interrupt[MEMORY].cpu_mask = IE_IRQ3; - dec_interrupt[MEMORY].iemask = 0; - cpu_mask_tbl[2] = IE_IRQ3; - cpu_irq_nr[2] = MEMORY; - - dec_interrupt[HALT].cpu_mask = IE_IRQ4; - dec_interrupt[HALT].iemask = 0; - cpu_mask_tbl[3] = IE_IRQ4; - cpu_irq_nr[3] = HALT; - - /* - * Enable board interrupts: FPU, I/O ASIC. - */ - set_cp0_status(DEC_IE_FPU | dec_ie_ioasic); + /* + * Setup some memory addresses. FIXME: probably incomplete! + */ + ioasic_base = (void *) KN03_IOASIC_BASE; + dec_rtc_base = (char *) KN03_RTC_BASE; + isr = (void *) KN03_IOASIC_REG(SIR); + imr = (void *) KN03_IOASIC_REG(SIMR); + + /* + * Setup IOASIC interrupt + */ + dec_ie_ioasic = IE_IRQ0; + cpu_ivec_tbl[1] = kn03_io_int; + cpu_mask_tbl[1] = dec_ie_ioasic; + cpu_irq_nr[1] = -1; + *imr = 0; + + /* + * Setup interrupt structure + */ + dec_interrupt[CLOCK].cpu_mask = IE_IRQ1; + dec_interrupt[CLOCK].iemask = 0; + cpu_mask_tbl[0] = IE_IRQ1; + cpu_irq_nr[0] = CLOCK; + + dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ0; + dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS; + asic_mask_tbl[0] = SCSI_DMA_INTS; + asic_irq_nr[0] = SCSI_DMA_INT; + + dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0; + dec_interrupt[SCSI_INT].iemask = SCSI_CHIP; + asic_mask_tbl[1] = SCSI_CHIP; + asic_irq_nr[1] = SCSI_INT; + + dec_interrupt[ETHER].cpu_mask = IE_IRQ0; + dec_interrupt[ETHER].iemask = LANCE_INTS; + asic_mask_tbl[2] = LANCE_INTS; + asic_irq_nr[2] = ETHER; + + dec_interrupt[SERIAL].cpu_mask = IE_IRQ0; + dec_interrupt[SERIAL].iemask = SERIAL_INTS; + asic_mask_tbl[3] = SERIAL_INTS; + asic_irq_nr[3] = SERIAL; + + dec_interrupt[TC0].cpu_mask = IE_IRQ0; + dec_interrupt[TC0].iemask = KN03_TC0; + asic_mask_tbl[4] = KN03_TC0; + asic_irq_nr[4] = TC0; + + dec_interrupt[TC1].cpu_mask = IE_IRQ0; + dec_interrupt[TC1].iemask = KN03_TC1; + asic_mask_tbl[5] = KN03_TC1; + asic_irq_nr[5] = TC1; + + dec_interrupt[TC2].cpu_mask = IE_IRQ0; + dec_interrupt[TC2].iemask = KN03_TC2; + asic_mask_tbl[6] = KN03_TC2; + asic_irq_nr[6] = TC2; + + dec_interrupt[MEMORY].cpu_mask = IE_IRQ3; + dec_interrupt[MEMORY].iemask = 0; + cpu_mask_tbl[2] = IE_IRQ3; + cpu_irq_nr[2] = MEMORY; + + dec_interrupt[HALT].cpu_mask = IE_IRQ4; + dec_interrupt[HALT].iemask = 0; + cpu_mask_tbl[3] = IE_IRQ4; + cpu_irq_nr[3] = HALT; + + /* + * Enable board interrupts: FPU, I/O ASIC. + */ + set_cp0_status(DEC_IE_FPU | dec_ie_ioasic); - dec_halt_init(&haltirq); + dec_halt_init(&haltirq); } /* dec_init_kn03 */ From karsten@excalibur.cologne.de Mon Dec 17 22:09:29 2001 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id WAA10146; Mon, 17 Dec 2001 22:09:29 +0100 (MET) Received-Date: Mon, 17 Dec 2001 22:09:29 +0100 (MET) Received: from natwar.webmailer.de(192.67.198.70), claiming to be "post.webmailer.de" via SMTP by guadalquivir.fnet.fr, id smtpd010144; Mon Dec 17 22:09:23 2001 Received: from excalibur.cologne.de (pD9511206.dip.t-dialin.net [217.81.18.6]) by post.webmailer.de (8.9.3/8.8.7) with ESMTP id WAA23874; Mon, 17 Dec 2001 22:04:51 +0100 (MET) Received: from karsten by excalibur.cologne.de with local (Exim 3.12 #1 (Debian)) id 16G580-0001lG-00; Mon, 17 Dec 2001 22:16:52 +0100 Date: Mon, 17 Dec 2001 22:16:52 +0100 From: Karsten Merker To: linux-mips@oss.sgi.com, linux-mips@fnet.fr Cc: ralf@gnu.org Subject: Re: New style irqs for DEC Message-ID: <20011217221652.A6765@excalibur.cologne.de> Mail-Followup-To: Karsten Merker , linux-mips@oss.sgi.com, linux-mips@fnet.fr, ralf@gnu.org References: <20011217172741.A2316@dea.linux-mips.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5i In-Reply-To: <20011217172741.A2316@dea.linux-mips.net>; from ralf@uni-koblenz.de on Mon, Dec 17, 2001 at 05:27:41PM -0200 X-No-Archive: yes Content-Length: 3417 Lines: 73 On Mon, Dec 17, 2001 at 05:27:41PM -0200, Ralf Baechle wrote: > below is my attempt at fixing interrupts for DECstation against the > latest 2.4. Can you give it a try? Gives the following on a DECstation 5000/20 (R3k): ------------------------------------------------------------------------------ >>boot 3/tftp root=/dev/sda5 console=ttyS0 1527808+0+79696 This DECstation is a Personal DS5000/xx CPU revision is: 00000230 FPU revision is: 00000340 Primary instruction cache 64kb, linesize 4 bytes Primary data cache 64kb, linesize 4 bytes Linux version 2.4.16 (karsten@excalibur) (gcc version egcs-2.91.66 19990314 (egcs-1.1.2 release)) #1 Mon Dez 17 21:43:00 CET 2001 Determined physical RAM map: memory: 02800000 @ 00000000 (usable) On node 0 totalpages: 10240 zone(0): 10240 pages. zone(1): 0 pages. zone(2): 0 pages. Kernel command line: root=/dev/sda5 console=ttyS0 Calibrating delay loop... 19.82 BogoMIPS Memory: 38484k/40960k available (1284k kernel code, 2476k reserved, 137k data, 64k init) Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes) Inode-cache hash table entries: 4096 (order: 3, 32768 bytes) Mount-cache hash table entries: 1024 (order: 1, 8192 bytes) Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) Page-cache hash table entries: 16384 (order: 4, 65536 bytes) Checking for 'wait' instruction... unavailable. POSIX conformance testing by UNIFIX TURBOchannel rev. 1 at 12.5 MHz (without parity) Linux NET4.0 for Linux 2.4 Based upon Swansea University Computer Society NET3.039 Starti<1>Unable to handle kernel paging request at virtual address 00000000, epc == 00000000, ra == 8005c84c Oops in fault.c:do_page_fault, line 204: $0 : 00000000 1000a801 00000000 000000cd 801928c8 00090f96 8019dcf4 00000000 $8 : 801a05b8 801a0420 00000800 00000800 00000000 00000000 801ee250 fffffffb $16: 801928c8 000400f7 7fe11ffe 1000a800 8019cf00 80192860 0000003c 00000010 $24: ffffffff 00000020 801fc000 801fdd48 0c00b620 8005c84c Hi : 0000000f Lo : 765e2000 epc : 00000000 Not tainted Status: 1000a804 Cause : 00000008 Process swapper (pid: 1, stackpage=801fc000) Stack: 801a064c 8004def8 fffffffe 1000a800 80192000 801a064c 00000000 fffffffb 801fdda0 0000003e 8004e244 8004e1f0 00000002 80068188 8019e884 8019ea7c fffffff5 000026f0 801ad6d0 0000006e 0000000a 800cabf0 00000001 8005d2b0 8019e884 8019ea7c 000001f0 801fdf40 00000000 801a0000 ffffffff 00000078 ffffffff 000d1b70 00012e00 bc100001 00012e00 00012e00 00000018 fffffff0 00000000 ... Call Trace: [<8004def8>] [<8004e244>] [<8004e1f0>] [<80068188>] [<800cabf0>] [<8005d2b0>] [<80055964>] [<80055754>] [<800f9334>] [<800f9394>] [<8005d2b0>] [<800f9690>] [<8004c980>] [<80056974>] [<800ab1a8>] [<800ab16c>] [<80056a10>] [<80056b4c>] [<80056fdc>] [<8004804c>] [<80056e68>] [<8015a070>] [<8004804c>] [<8015a060>] [<80068510>] [<8016eefc>] [<8004804c>] [<8004805c>] [<800570e8>] [<80047e14>] [<8004897c>] [<80048020>] [<80056e68>] [<8004896c>] Code: (Bad address in epc) Kernel panic: Aiee, killing interrupt handler! In interrupt handler - not syncing ------------------------------------------------------------------------------ Greetings, Karsten -- #include Nach Paragraph 28 Abs. 3 Bundesdatenschutzgesetz widerspreche ich der Nutzung oder Uebermittlung meiner Daten fuer Werbezwecke oder fuer die Markt- oder meinungsforschung. From ralf@linux-mips.net Mon Dec 17 23:00:19 2001 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id XAA13225; Mon, 17 Dec 2001 23:00:19 +0100 (MET) Received-Date: Mon, 17 Dec 2001 23:00:19 +0100 (MET) Received: from oss.sgi.com(216.32.174.27) via SMTP by guadalquivir.fnet.fr, id smtpd013223; Mon Dec 17 23:00:09 2001 Received: from dea.linux-mips.net (localhost [127.0.0.1]) by oss.sgi.com (8.11.2/8.11.3) with ESMTP id fBHN05o04594 for ; Mon, 17 Dec 2001 15:00:05 -0800 Received: (from ralf@localhost) by dea.linux-mips.net (8.11.1/8.11.1) id fBHLxrS01947; Mon, 17 Dec 2001 19:59:53 -0200 Date: Mon, 17 Dec 2001 19:59:53 -0200 From: Ralf Baechle To: Karsten Merker , linux-mips@oss.sgi.com, linux-mips@fnet.fr Subject: Re: New style irqs for DEC Message-ID: <20011217195953.B12490@dea.linux-mips.net> References: <20011217172741.A2316@dea.linux-mips.net> <20011217221652.A6765@excalibur.cologne.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5i In-Reply-To: <20011217221652.A6765@excalibur.cologne.de>; from karsten@excalibur.cologne.de on Mon, Dec 17, 2001 at 10:16:52PM +0100 X-Accept-Language: de,en,fr Content-Length: 622 Lines: 18 On Mon, Dec 17, 2001 at 10:16:52PM +0100, Karsten Merker wrote: > > below is my attempt at fixing interrupts for DECstation against the > > latest 2.4. Can you give it a try? > > Gives the following on a DECstation 5000/20 (R3k): [long oops deleted] > Kernel panic: Aiee, killing interrupt handler! > In interrupt handler - not syncing > ------------------------------------------------------------------------------ Turns out that this is a NULL function pointer getting called. That is strange because it happened in the softirq code which I haven't touched at all. Maybe some type of memory corruption. Ralf From vhouten@kpn.com Wed Dec 19 14:46:25 2001 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id OAA04976; Wed, 19 Dec 2001 14:46:25 +0100 (MET) Received-Date: Wed, 19 Dec 2001 14:46:25 +0100 (MET) Received: from pandora.research.kpn.com(139.63.192.11) via SMTP by guadalquivir.fnet.fr, id smtpd004974; Wed Dec 19 14:46:22 2001 Received: from sparta.research.kpn.com (sparta.research.kpn.com [139.63.192.6]) by pandora.research.kpn.com (8.11.6/8.9.3) with ESMTP id fBJDkJI31249; Wed, 19 Dec 2001 14:46:19 +0100 Received: from sparta.research.kpn.com (sparta.research.kpn.com [139.63.192.6]) by sparta.research.kpn.com (8.8.8+Sun/8.8.8) with ESMTP id OAA22952; Wed, 19 Dec 2001 14:46:18 +0100 (MET) Message-Id: <200112191346.OAA22952@sparta.research.kpn.com> To: linux-mips@oss.sgi.com, linux-mips@fnet.fr Reply-to: vhouten@kpn.com Subject: New root image for mipsel based on RH 7.1 port X-Face: ";:TzQQC{mTp~$W,'m4@Lu1Lu$rtG_~5kvYO~F:C'KExk9o1X"iRz[0%{bq?6Aj#>VhSD?v 1W9`.Qsf+P&*iQEL8&y,RDj&U.]!(R-?c-h5h%Iw%r$|%6+Jc>GTJe!_1&A0o'lC[`I#={2BzOXT1P q366I$WL=;[+SDo1RoIT+a}_y68Y:jQ^xp4=*4-ryiymi>hy Date: Wed, 19 Dec 2001 14:46:18 +0100 From: "Houten K.H.C. van (Karel)" Content-Length: 344 Lines: 12 Hi All, I've compiled a new root image for mipsel systems, based on the RedHat 7.1 Port of H.J. Lu. It is available on ftp://oss.sgi.com/pub/linux/mips/mipsel-linux/root/mipsel-root-20011216.tgz New kernels for DECStations will be available soon, and I hope to update my web pages about DECStation Linux in the next weeks. Regards, Karel. From ralf@linux-mips.net Fri Dec 28 16:23:36 2001 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id QAA03744; Fri, 28 Dec 2001 16:23:36 +0100 (MET) Received-Date: Fri, 28 Dec 2001 16:23:36 +0100 (MET) Received: from mailhost.uni-koblenz.de(141.26.64.1), claiming to be "uni-koblenz.de" via SMTP by guadalquivir.fnet.fr, id smtpd003742; Fri Dec 28 16:23:30 2001 Received: from eddie (root@eddie.uni-koblenz.de [141.26.4.17]) by uni-koblenz.de (8.9.3/8.9.3) with SMTP id QAA02051 for ; Fri, 28 Dec 2001 16:23:28 +0100 (MET) Received: from dea.linux-mips.net by eddie (SMI-8.6/KO-2.0) id QAA23489; Fri, 28 Dec 2001 16:23:25 +0100 Received: (from ralf@localhost) by dea.linux-mips.net (8.11.1/8.11.1) id fBSEtKX01726; Fri, 28 Dec 2001 12:55:20 -0200 Date: Fri, 28 Dec 2001 12:55:20 -0200 From: Ralf Baechle To: Vivien Chappelier Cc: linux-mips@oss.sgi.com, linux-mips@fnet.fr Subject: Re: weekly O2 patches ;) Message-ID: <20011228125520.A1323@dea.linux-mips.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5i In-Reply-To: ; from vivien.chappelier@enst-bretagne.fr on Sat, Dec 22, 2001 at 07:28:44PM +0100 X-Accept-Language: de,en,fr Content-Length: 783 Lines: 28 On Sat, Dec 22, 2001 at 07:28:44PM +0100, Vivien Chappelier wrote: > diff -Naur linux/arch/mips64/mm/r4xx0.c linux.patch/arch/mips64/mm/r4xx0.c > --- linux/arch/mips64/mm/r4xx0.c Sun Dec 9 15:47:14 2001 > +++ linux.patch/arch/mips64/mm/r4xx0.c Thu Dec 20 19:04:46 2001 > @@ -2141,9 +2141,17 @@ > unsigned long flags, addr, begin, end, pow2; > int tmp; > > - tmp = ((config >> 17) & 1); > + /* XXX: disabling secondary cache for now */ > + change_cp0_config(CONF_SE, 0); > + > + tmp = ((config >> 17) & 1); /* check if cache present */ > if(tmp) > return 0; > + > + tmp = ((config >> 12) & 1); /* check if cache enabled */ > + if(!tmp) > + return 0; > + > tmp = ((config >> 22) & 3); > switch(tmp) { > case 0: Perfect. You just broke R4000SC / R4400SC. Ralf