From ralf@linux-mips.org Wed Jun 1 12:18:35 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Wed, 01 Jun 2005 13:18:35 +0100 (BST) From: ralf@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Wed, 01 Jun 2005 13:18:35 +0100 X-archive-position: 454 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ralf@ftp.linux-mips.org 05/06/01 13:18:30 Modified files: include/asm-mips: asm.h Log message: Fix build with CONFIG_PRINTK disabled. diff -urN linux/include/asm-mips/asm.h linux/include/asm-mips/asm.h --- linux/include/asm-mips/asm.h 2004/04/08 15:40:01 1.21 +++ linux/include/asm-mips/asm.h 2005/06/01 12:18:30 1.22 @@ -107,6 +107,7 @@ /* * Print formatted string */ +#ifdef CONFIG_PRINTK #define PRINT(string) \ .set push; \ .set reorder; \ @@ -114,6 +115,9 @@ jal printk; \ .set pop; \ TEXT(string) +#else +#define PRINT(string) +#endif #define TEXT(msg) \ .pushsection .data; \ From ralf@linux-mips.org Wed Jun 1 14:15:34 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Wed, 01 Jun 2005 15:15:34 +0100 (BST) From: ralf@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Wed, 01 Jun 2005 15:15:34 +0100 X-archive-position: 455 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ralf@ftp.linux-mips.org 05/06/01 15:15:27 Modified files: . : Tag: linux_2_4 Makefile arch/i386/kernel: Tag: linux_2_4 mtrr.c net/ipv4/ipvs : Tag: linux_2_4 ip_vs_ctl.c ip_vs_sched.c ip_vs_sync.c Log message: Merge with Linux 2.4.31. diff -urN linux/Makefile linux/Makefile --- linux/Makefile 2005/05/25 17:14:22 1.119.2.38 +++ linux/Makefile 2005/06/01 14:15:27 1.119.2.39 @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 4 SUBLEVEL = 31 -EXTRAVERSION = -rc1 +EXTRAVERSION = KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) diff -urN linux/arch/i386/kernel/mtrr.c linux/arch/i386/kernel/mtrr.c --- linux/arch/i386/kernel/Attic/mtrr.c 2004/08/14 18:38:45 1.34.2.4 +++ linux/arch/i386/kernel/Attic/mtrr.c 2005/06/01 14:15:27 1.34.2.5 @@ -1674,6 +1674,7 @@ char *ptr; char line[LINE_SIZE]; + if (!len) return -EINVAL; if ( !suser () ) return -EPERM; /* Can't seek (pwrite) on this device */ if (ppos != &file->f_pos) return -ESPIPE; diff -urN linux/net/ipv4/ipvs/ip_vs_ctl.c linux/net/ipv4/ipvs/ip_vs_ctl.c --- linux/net/ipv4/ipvs/ip_vs_ctl.c 2005/01/20 02:19:25 1.6.2.4 +++ linux/net/ipv4/ipvs/ip_vs_ctl.c 2005/06/01 14:15:27 1.6.2.5 @@ -1842,7 +1842,8 @@ entry.addr = svc->addr; entry.port = svc->port; entry.fwmark = svc->fwmark; - strcpy(entry.sched_name, svc->scheduler->name); + strncpy(entry.sched_name, svc->scheduler->name, sizeof(entry.sched_name)); + entry.sched_name[sizeof(entry.sched_name) - 1] = 0; entry.flags = svc->flags; entry.timeout = svc->timeout / HZ; entry.netmask = svc->netmask; @@ -1866,7 +1867,8 @@ entry.addr = svc->addr; entry.port = svc->port; entry.fwmark = svc->fwmark; - strcpy(entry.sched_name, svc->scheduler->name); + strncpy(entry.sched_name, svc->scheduler->name, sizeof(entry.sched_name)); + entry.sched_name[sizeof(entry.sched_name) - 1] = 0; entry.flags = svc->flags; entry.timeout = svc->timeout / HZ; entry.netmask = svc->netmask; @@ -2020,7 +2022,8 @@ svc = __ip_vs_service_get(get.protocol, get.addr, get.port); if (svc) { - strcpy(get.sched_name, svc->scheduler->name); + strncpy(get.sched_name, svc->scheduler->name, sizeof(get.sched_name)); + get.sched_name[sizeof(get.sched_name) - 1] = 0; get.flags = svc->flags; get.timeout = svc->timeout / HZ; get.netmask = svc->netmask; @@ -2083,10 +2086,14 @@ goto out; } u.state = ip_vs_sync_state; - if (ip_vs_sync_state & IP_VS_STATE_MASTER) - strcpy(u.mcast_master_ifn, ip_vs_mcast_master_ifn); - if (ip_vs_sync_state & IP_VS_STATE_BACKUP) - strcpy(u.mcast_backup_ifn, ip_vs_mcast_backup_ifn); + if (ip_vs_sync_state & IP_VS_STATE_MASTER) { + strncpy(u.mcast_master_ifn, ip_vs_mcast_master_ifn, sizeof(u.mcast_master_ifn)); + u.mcast_master_ifn[sizeof(u.mcast_master_ifn) - 1] = 0; + } + if (ip_vs_sync_state & IP_VS_STATE_BACKUP) { + strncpy(u.mcast_backup_ifn, ip_vs_mcast_backup_ifn, sizeof(u.mcast_backup_ifn)); + u.mcast_backup_ifn[sizeof(u.mcast_backup_ifn) - 1] = 0; + } if (copy_to_user(user, &u, sizeof(u)) != 0) ret = -EFAULT; } diff -urN linux/net/ipv4/ipvs/ip_vs_sched.c linux/net/ipv4/ipvs/ip_vs_sched.c --- linux/net/ipv4/ipvs/ip_vs_sched.c 2004/04/16 03:14:22 1.3.2.2 +++ linux/net/ipv4/ipvs/ip_vs_sched.c 2005/06/01 14:15:27 1.3.2.3 @@ -156,7 +156,7 @@ */ if (sched == NULL) { char module_name[IP_VS_SCHEDNAME_MAXLEN+8]; - sprintf(module_name,"ip_vs_%s", sched_name); + snprintf(module_name, sizeof(module_name), "ip_vs_%s", sched_name); request_module(module_name); sched = ip_vs_sched_getbyname(sched_name); } diff -urN linux/net/ipv4/ipvs/ip_vs_sync.c linux/net/ipv4/ipvs/ip_vs_sync.c --- linux/net/ipv4/ipvs/ip_vs_sync.c 2005/01/20 02:19:25 1.4.2.4 +++ linux/net/ipv4/ipvs/ip_vs_sync.c 2005/06/01 14:15:27 1.4.2.5 @@ -808,10 +808,12 @@ ip_vs_sync_state |= state; if (state == IP_VS_STATE_MASTER) { - strcpy(ip_vs_mcast_master_ifn, mcast_ifn); + strncpy(ip_vs_mcast_master_ifn, mcast_ifn, sizeof(ip_vs_mcast_master_ifn)); + ip_vs_mcast_master_ifn[sizeof(ip_vs_mcast_master_ifn) - 1] = 0; ip_vs_master_syncid = syncid; } else { - strcpy(ip_vs_mcast_backup_ifn, mcast_ifn); + strncpy(ip_vs_mcast_backup_ifn, mcast_ifn, sizeof(ip_vs_mcast_backup_ifn)); + ip_vs_mcast_backup_ifn[sizeof(ip_vs_mcast_backup_ifn) - 1] = 0; ip_vs_backup_syncid = syncid; } From ralf@linux-mips.org Thu Jun 2 13:22:44 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Thu, 02 Jun 2005 14:22:44 +0100 (BST) From: ralf@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Thu, 02 Jun 2005 14:22:44 +0100 X-archive-position: 456 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ralf@ftp.linux-mips.org 05/06/02 14:22:38 Modified files: drivers/net : titan_ge.c Log message: Add the titan_device_remove function to make compiling the Titan driver as a module possible. Still doesn't mean it'll actually work as a module, will fix that later. diff -urN linux/drivers/net/titan_ge.c linux/drivers/net/titan_ge.c --- linux/drivers/net/titan_ge.c 2005/01/08 15:01:59 1.59 +++ linux/drivers/net/titan_ge.c 2005/06/02 13:22:38 1.60 @@ -1877,6 +1877,10 @@ return err; } +static void __devexit titan_device_remove(struct device *device) +{ +} + /* * Reset the Ethernet port */ From ralf@linux-mips.org Thu Jun 2 14:33:10 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Thu, 02 Jun 2005 15:33:10 +0100 (BST) From: ralf@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Thu, 02 Jun 2005 15:33:10 +0100 X-archive-position: 457 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ralf@ftp.linux-mips.org 05/06/02 15:33:02 Modified files: arch/mips/vr41xx/common: Makefile giu.c icu.c int-handler.S include/asm-mips/vr41xx: vr41xx.h Log message: Update IRQ handling for vr41xx: o add common IRQ dispatch o change IRQ numbering in int-handler.S o add resource management to icu.c diff -urN linux/arch/mips/vr41xx/common/Makefile linux/arch/mips/vr41xx/common/Makefile --- linux/arch/mips/vr41xx/common/Makefile 2005/05/19 16:12:44 1.19 +++ linux/arch/mips/vr41xx/common/Makefile 2005/06/02 14:33:02 1.20 @@ -2,7 +2,7 @@ # Makefile for common code of the NEC VR4100 series. # -obj-y += bcu.o cmu.o icu.o init.o int-handler.o pmu.o +obj-y += bcu.o cmu.o icu.o init.o int-handler.o irq.o pmu.o obj-$(CONFIG_GPIO_VR41XX) += giu.o obj-$(CONFIG_VRC4173) += vrc4173.o diff -urN linux/arch/mips/vr41xx/common/giu.c linux/arch/mips/vr41xx/common/giu.c --- linux/arch/mips/vr41xx/common/giu.c 2005/04/14 11:31:25 1.17 +++ linux/arch/mips/vr41xx/common/giu.c 2005/06/02 14:33:02 1.18 @@ -291,60 +291,7 @@ EXPORT_SYMBOL(vr41xx_set_irq_level); -#ifndef MODULE - -#define GIUINT_NR_IRQS 32 - -enum { - GIUINT_NO_CASCADE, - GIUINT_CASCADE -}; - -struct vr41xx_giuint_cascade { - unsigned int flag; - int (*get_irq_number)(int irq); -}; - -static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS]; - -static struct irqaction giu_cascade = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "cascade", -}; - -static int no_irq_number(int irq) -{ - return -EINVAL; -} - -int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)) -{ - unsigned int pin; - int retval; - - if (irq < GIU_IRQ(0) || irq > GIU_IRQ(31)) - return -EINVAL; - - if(!get_irq_number) - return -EINVAL; - - pin = GIU_IRQ_TO_PIN(irq); - giuint_cascade[pin].flag = GIUINT_CASCADE; - giuint_cascade[pin].get_irq_number = get_irq_number; - - retval = setup_irq(irq, &giu_cascade); - if (retval != 0) { - giuint_cascade[pin].flag = GIUINT_NO_CASCADE; - giuint_cascade[pin].get_irq_number = no_irq_number; - } - - return retval; -} - -EXPORT_SYMBOL(vr41xx_cascade_irq); - -static inline int get_irq_pin_number(void) +static int giu_get_irq(unsigned int irq, struct pt_regs *regs) { uint16_t pendl, pendh, maskl, maskh; int i; @@ -360,12 +307,12 @@ if (maskl) { for (i = 0; i < 16; i++) { if (maskl & ((uint16_t)1 << i)) - return i; + return GIU_IRQ(i); } } else if (maskh) { for (i = 0; i < 16; i++) { if (maskh & ((uint16_t)1 << i)) - return i + GIUINT_HIGH_OFFSET; + return GIU_IRQ(i + GIUINT_HIGH_OFFSET); } } @@ -377,54 +324,7 @@ return -1; } -static inline void ack_giuint_irq(int pin) -{ - if (pin < GIUINT_HIGH_OFFSET) { - clear_giuint(GIUINTENL, (uint16_t)1 << pin); - write_giuint((uint16_t)1 << pin, GIUINTSTATL); - } else { - pin -= GIUINT_HIGH_OFFSET; - clear_giuint(GIUINTENH, (uint16_t)1 << pin); - write_giuint((uint16_t)1 << pin, GIUINTSTATH); - } -} - -static inline void end_giuint_irq(int pin) -{ - if (pin < GIUINT_HIGH_OFFSET) - set_giuint(GIUINTENL, (uint16_t)1 << pin); - else - set_giuint(GIUINTENH, (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET)); -} - -void giuint_irq_dispatch(struct pt_regs *regs) -{ - struct vr41xx_giuint_cascade *cascade; - unsigned int giuint_irq; - int pin; - - pin = get_irq_pin_number(); - if (pin < 0) - return; - - disable_irq(GIUINT_CASCADE_IRQ); - - cascade = &giuint_cascade[pin]; - giuint_irq = GIU_IRQ(pin); - if (cascade->flag == GIUINT_CASCADE) { - int irq = cascade->get_irq_number(giuint_irq); - ack_giuint_irq(pin); - if (irq >= 0) - do_IRQ(irq, regs); - end_giuint_irq(pin); - } else { - do_IRQ(giuint_irq, regs); - } - - enable_irq(GIUINT_CASCADE_IRQ); -} - -void __init init_vr41xx_giuint_irq(void) +static int __init vr41xx_giu_init(void) { int i; @@ -440,16 +340,14 @@ break; default: printk(KERN_ERR "GIU: Unexpected CPU of NEC VR4100 series\n"); - return; + return -ENODEV; } - for (i = 0; i < GIUINT_NR_IRQS; i++) { + for (i = 0; i < 32; i++) { if (i < GIUINT_HIGH_OFFSET) clear_giuint(GIUINTENL, (uint16_t)1 << i); else clear_giuint(GIUINTENH, (uint16_t)1 << (i - GIUINT_HIGH_OFFSET)); - giuint_cascade[i].flag = GIUINT_NO_CASCADE; - giuint_cascade[i].get_irq_number = no_irq_number; } for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) { @@ -459,7 +357,7 @@ irq_desc[i].handler = &giuint_high_irq_type; } - setup_irq(GIUINT_CASCADE_IRQ, &giu_cascade); + return cascade_irq(GIUINT_IRQ, giu_get_irq); } -#endif +postcore_initcall(vr41xx_giu_init); diff -urN linux/arch/mips/vr41xx/common/icu.c linux/arch/mips/vr41xx/common/icu.c --- linux/arch/mips/vr41xx/common/icu.c 2005/03/07 18:58:15 1.20 +++ linux/arch/mips/vr41xx/common/icu.c 2005/06/02 14:33:02 1.21 @@ -28,10 +28,10 @@ * Yoichi Yuasa * - Coped with INTASSIGN of NEC VR4133. */ -#include #include #include #include +#include #include #include #include @@ -43,32 +43,22 @@ #include #include -extern asmlinkage void vr41xx_handle_interrupt(void); - -#ifdef CONFIG_GPIO_VR41XX -extern void init_vr41xx_giuint_irq(void); -extern void giuint_irq_dispatch(struct pt_regs *regs); -#endif - -static uint32_t icu1_base; -static uint32_t icu2_base; - -static struct irqaction icu_cascade = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "cascade", -}; +static void __iomem *icu1_base; +static void __iomem *icu2_base; static unsigned char sysint1_assign[16] = { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static unsigned char sysint2_assign[16] = { - 2, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + +#define ICU1_TYPE1_BASE 0x0b000080UL +#define ICU2_TYPE1_BASE 0x0b000200UL -#define SYSINT1REG_TYPE1 KSEG1ADDR(0x0b000080) -#define SYSINT2REG_TYPE1 KSEG1ADDR(0x0b000200) +#define ICU1_TYPE2_BASE 0x0f000080UL +#define ICU2_TYPE2_BASE 0x0f0000a0UL -#define SYSINT1REG_TYPE2 KSEG1ADDR(0x0f000080) -#define SYSINT2REG_TYPE2 KSEG1ADDR(0x0f0000a0) +#define ICU1_SIZE 0x20 +#define ICU2_SIZE 0x1c #define SYSINT1REG 0x00 #define PIUINTREG 0x02 @@ -108,61 +98,61 @@ #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */ #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */ -#define read_icu1(offset) readw(icu1_base + (offset)) -#define write_icu1(val, offset) writew((val), icu1_base + (offset)) +#define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */ -#define read_icu2(offset) readw(icu2_base + (offset)) -#define write_icu2(val, offset) writew((val), icu2_base + (offset)) +#define icu1_read(offset) readw(icu1_base + (offset)) +#define icu1_write(offset, value) writew((value), icu1_base + (offset)) + +#define icu2_read(offset) readw(icu2_base + (offset)) +#define icu2_write(offset, value) writew((value), icu2_base + (offset)) #define INTASSIGN_MAX 4 #define INTASSIGN_MASK 0x0007 -static inline uint16_t set_icu1(uint8_t offset, uint16_t set) +static inline uint16_t icu1_set(uint8_t offset, uint16_t set) { - uint16_t res; + uint16_t data; - res = read_icu1(offset); - res |= set; - write_icu1(res, offset); + data = icu1_read(offset); + data |= set; + icu1_write(offset, data); - return res; + return data; } -static inline uint16_t clear_icu1(uint8_t offset, uint16_t clear) +static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear) { - uint16_t res; + uint16_t data; - res = read_icu1(offset); - res &= ~clear; - write_icu1(res, offset); + data = icu1_read(offset); + data &= ~clear; + icu1_write(offset, data); - return res; + return data; } -static inline uint16_t set_icu2(uint8_t offset, uint16_t set) +static inline uint16_t icu2_set(uint8_t offset, uint16_t set) { - uint16_t res; + uint16_t data; - res = read_icu2(offset); - res |= set; - write_icu2(res, offset); + data = icu2_read(offset); + data |= set; + icu2_write(offset, data); - return res; + return data; } -static inline uint16_t clear_icu2(uint8_t offset, uint16_t clear) +static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear) { - uint16_t res; + uint16_t data; - res = read_icu2(offset); - res &= ~clear; - write_icu2(res, offset); + data = icu2_read(offset); + data &= ~clear; + icu2_write(offset, data); - return res; + return data; } -/*=======================================================================*/ - void vr41xx_enable_piuint(uint16_t mask) { irq_desc_t *desc = irq_desc + PIU_IRQ; @@ -171,7 +161,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MPIUINTREG, mask); + icu1_set(MPIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -186,7 +176,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MPIUINTREG, mask); + icu1_clear(MPIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -201,7 +191,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MAIUINTREG, mask); + icu1_set(MAIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -216,7 +206,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MAIUINTREG, mask); + icu1_clear(MAIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -231,7 +221,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MKIUINTREG, mask); + icu1_set(MKIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -246,7 +236,7 @@ if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MKIUINTREG, mask); + icu1_clear(MKIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -259,7 +249,7 @@ unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - set_icu1(MDSIUINTREG, mask); + icu1_set(MDSIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -271,7 +261,7 @@ unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MDSIUINTREG, mask); + icu1_clear(MDSIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -283,7 +273,7 @@ unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - set_icu2(MFIRINTREG, mask); + icu2_set(MFIRINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -295,7 +285,7 @@ unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - clear_icu2(MFIRINTREG, mask); + icu2_clear(MFIRINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -310,7 +300,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(PCIINT0, MPCIINTREG); + icu2_write(MPCIINTREG, PCIINT0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -326,7 +316,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MPCIINTREG); + icu2_write(MPCIINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -342,7 +332,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(SCUINT0, MSCUINTREG); + icu2_write(MSCUINTREG, SCUINT0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -358,7 +348,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MSCUINTREG); + icu2_write(MSCUINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -374,7 +364,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - set_icu2(MCSIINTREG, mask); + icu2_set(MCSIINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -390,7 +380,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - clear_icu2(MCSIINTREG, mask); + icu2_clear(MCSIINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -406,7 +396,7 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(BCUINTR, MBCUINTREG); + icu2_write(MBCUINTREG, BCUINTR); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -422,30 +412,28 @@ current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MBCUINTREG); + icu2_write(MBCUINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } EXPORT_SYMBOL(vr41xx_disable_bcuint); -/*=======================================================================*/ - static unsigned int startup_sysint1_irq(unsigned int irq) { - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); return 0; /* never anything pending */ } static void shutdown_sysint1_irq(unsigned int irq) { - clear_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } static void enable_sysint1_irq(unsigned int irq) { - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } #define disable_sysint1_irq shutdown_sysint1_irq @@ -454,7 +442,7 @@ static void end_sysint1_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } static struct hw_interrupt_type sysint1_irq_type = { @@ -467,23 +455,21 @@ .end = end_sysint1_irq, }; -/*=======================================================================*/ - static unsigned int startup_sysint2_irq(unsigned int irq) { - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); return 0; /* never anything pending */ } static void shutdown_sysint2_irq(unsigned int irq) { - clear_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } static void enable_sysint2_irq(unsigned int irq) { - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } #define disable_sysint2_irq shutdown_sysint2_irq @@ -492,7 +478,7 @@ static void end_sysint2_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } static struct hw_interrupt_type sysint2_irq_type = { @@ -505,8 +491,6 @@ .end = end_sysint2_irq, }; -/*=======================================================================*/ - static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) { irq_desc_t *desc = irq_desc + irq; @@ -517,8 +501,8 @@ spin_lock_irq(&desc->lock); - intassign0 = read_icu1(INTASSIGN0); - intassign1 = read_icu1(INTASSIGN1); + intassign0 = icu1_read(INTASSIGN0); + intassign1 = icu1_read(INTASSIGN1); switch (pin) { case 0: @@ -558,8 +542,8 @@ } sysint1_assign[pin] = assign; - write_icu1(intassign0, INTASSIGN0); - write_icu1(intassign1, INTASSIGN1); + icu1_write(INTASSIGN0, intassign0); + icu1_write(INTASSIGN1, intassign1); spin_unlock_irq(&desc->lock); @@ -576,8 +560,8 @@ spin_lock_irq(&desc->lock); - intassign2 = read_icu1(INTASSIGN2); - intassign3 = read_icu1(INTASSIGN3); + intassign2 = icu1_read(INTASSIGN2); + intassign3 = icu1_read(INTASSIGN3); switch (pin) { case 0: @@ -625,8 +609,8 @@ } sysint2_assign[pin] = assign; - write_icu1(intassign2, INTASSIGN2); - write_icu1(intassign3, INTASSIGN3); + icu1_write(INTASSIGN2, intassign2); + icu1_write(INTASSIGN3, intassign3); spin_unlock_irq(&desc->lock); @@ -653,81 +637,92 @@ EXPORT_SYMBOL(vr41xx_set_intassign); -/*=======================================================================*/ - -asmlinkage void irq_dispatch(unsigned char intnum, struct pt_regs *regs) +static int icu_get_irq(unsigned int irq, struct pt_regs *regs) { uint16_t pend1, pend2; uint16_t mask1, mask2; int i; - pend1 = read_icu1(SYSINT1REG); - mask1 = read_icu1(MSYSINT1REG); + pend1 = icu1_read(SYSINT1REG); + mask1 = icu1_read(MSYSINT1REG); - pend2 = read_icu2(SYSINT2REG); - mask2 = read_icu2(MSYSINT2REG); + pend2 = icu2_read(SYSINT2REG); + mask2 = icu2_read(MSYSINT2REG); mask1 &= pend1; mask2 &= pend2; if (mask1) { for (i = 0; i < 16; i++) { - if (intnum == sysint1_assign[i] && - (mask1 & ((uint16_t)1 << i))) { -#ifdef CONFIG_GPIO_VR41XX - if (i == 8) - giuint_irq_dispatch(regs); - else -#endif - do_IRQ(SYSINT1_IRQ(i), regs); - return; - } + if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i))) + return SYSINT1_IRQ(i); } } if (mask2) { for (i = 0; i < 16; i++) { - if (intnum == sysint2_assign[i] && - (mask2 & ((uint16_t)1 << i))) { - do_IRQ(SYSINT2_IRQ(i), regs); - return; - } + if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i))) + return SYSINT2_IRQ(i); } } printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2); atomic_inc(&irq_err_count); -} -/*=======================================================================*/ + return -1; +} -static inline void init_vr41xx_icu_irq(void) +static int __init vr41xx_icu_init(void) { + unsigned long icu1_start, icu2_start; int i; switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: - icu1_base = SYSINT1REG_TYPE1; - icu2_base = SYSINT2REG_TYPE1; + icu1_start = ICU1_TYPE1_BASE; + icu2_start = ICU2_TYPE1_BASE; break; case CPU_VR4122: case CPU_VR4131: case CPU_VR4133: - icu1_base = SYSINT1REG_TYPE2; - icu2_base = SYSINT2REG_TYPE2; + icu1_start = ICU1_TYPE2_BASE; + icu2_start = ICU2_TYPE2_BASE; break; default: printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n"); - return -EINVAL; + return -ENODEV; + } + + if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL) + return -EBUSY; + + if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) { + release_mem_region(icu1_start, ICU1_SIZE); + return -EBUSY; + } + + icu1_base = ioremap(icu1_start, ICU1_SIZE); + if (icu1_base == NULL) { + release_mem_region(icu1_start, ICU1_SIZE); + release_mem_region(icu2_start, ICU2_SIZE); + return -ENOMEM; + } + + icu2_base = ioremap(icu2_start, ICU2_SIZE); + if (icu2_base == NULL) { + iounmap(icu1_base); + release_mem_region(icu1_start, ICU1_SIZE); + release_mem_region(icu2_start, ICU2_SIZE); + return -ENOMEM; } - write_icu1(0, MSYSINT1REG); - write_icu1(0xffff, MGIUINTLREG); + icu1_write(MSYSINT1REG, 0); + icu1_write(MGIUINTLREG, 0xffff); - write_icu2(0, MSYSINT2REG); - write_icu2(0xffff, MGIUINTHREG); + icu2_write(MSYSINT2REG, 0); + icu2_write(MGIUINTHREG, 0xffff); for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) irq_desc[i].handler = &sysint1_irq_type; @@ -735,20 +730,13 @@ for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) irq_desc[i].handler = &sysint2_irq_type; - setup_irq(INT0_CASCADE_IRQ, &icu_cascade); - setup_irq(INT1_CASCADE_IRQ, &icu_cascade); - setup_irq(INT2_CASCADE_IRQ, &icu_cascade); - setup_irq(INT3_CASCADE_IRQ, &icu_cascade); - setup_irq(INT4_CASCADE_IRQ, &icu_cascade); -} - -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); - init_vr41xx_icu_irq(); -#ifdef CONFIG_GPIO_VR41XX - init_vr41xx_giuint_irq(); -#endif + cascade_irq(INT0_IRQ, icu_get_irq); + cascade_irq(INT1_IRQ, icu_get_irq); + cascade_irq(INT2_IRQ, icu_get_irq); + cascade_irq(INT3_IRQ, icu_get_irq); + cascade_irq(INT4_IRQ, icu_get_irq); - set_except_vector(0, vr41xx_handle_interrupt); + return 0; } + +core_initcall(vr41xx_icu_init); diff -urN linux/arch/mips/vr41xx/common/int-handler.S linux/arch/mips/vr41xx/common/int-handler.S --- linux/arch/mips/vr41xx/common/int-handler.S 2003/12/15 20:27:45 1.2 +++ linux/arch/mips/vr41xx/common/int-handler.S 2005/06/02 14:33:02 1.3 @@ -71,24 +71,24 @@ andi t1, t0, CAUSEF_IP3 # check for Int1 bnez t1, handle_int - li a0, 1 + li a0, 3 andi t1, t0, CAUSEF_IP4 # check for Int2 bnez t1, handle_int - li a0, 2 + li a0, 4 andi t1, t0, CAUSEF_IP5 # check for Int3 bnez t1, handle_int - li a0, 3 + li a0, 5 andi t1, t0, CAUSEF_IP6 # check for Int4 bnez t1, handle_int - li a0, 4 + li a0, 6 1: andi t1, t0, CAUSEF_IP2 # check for Int0 bnez t1, handle_int - li a0, 0 + li a0, 2 andi t1, t0, CAUSEF_IP0 # check for IP0 bnez t1, handle_irq diff -urN linux/include/asm-mips/vr41xx/vr41xx.h linux/include/asm-mips/vr41xx/vr41xx.h --- linux/include/asm-mips/vr41xx/vr41xx.h 2005/05/19 15:26:29 1.23 +++ linux/include/asm-mips/vr41xx/vr41xx.h 2005/06/02 14:33:02 1.24 @@ -79,11 +79,11 @@ #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) #define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) #define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1) -#define INT0_CASCADE_IRQ MIPS_CPU_IRQ(2) -#define INT1_CASCADE_IRQ MIPS_CPU_IRQ(3) -#define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4) -#define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5) -#define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6) +#define INT0_IRQ MIPS_CPU_IRQ(2) +#define INT1_IRQ MIPS_CPU_IRQ(3) +#define INT2_IRQ MIPS_CPU_IRQ(4) +#define INT3_IRQ MIPS_CPU_IRQ(5) +#define INT4_IRQ MIPS_CPU_IRQ(6) #define TIMER_IRQ MIPS_CPU_IRQ(7) /* SYINT1 Interrupt Numbers */ @@ -97,7 +97,7 @@ #define PIU_IRQ SYSINT1_IRQ(5) #define AIU_IRQ SYSINT1_IRQ(6) #define KIU_IRQ SYSINT1_IRQ(7) -#define GIUINT_CASCADE_IRQ SYSINT1_IRQ(8) +#define GIUINT_IRQ SYSINT1_IRQ(8) #define SIU_IRQ SYSINT1_IRQ(9) #define BUSERR_IRQ SYSINT1_IRQ(10) #define SOFTINT_IRQ SYSINT1_IRQ(11) @@ -129,7 +129,7 @@ #define GIU_IRQ_TO_PIN(x) ((x) - GIU_IRQ_BASE) /* Pin 0-31 */ extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); -extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)); +extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)); #define PIUINT_COMMAND 0x0040 #define PIUINT_DATA 0x0020 From ralf@linux-mips.org Thu Jun 2 14:37:18 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Thu, 02 Jun 2005 15:37:18 +0100 (BST) From: ralf@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Thu, 02 Jun 2005 15:37:18 +0100 X-archive-position: 458 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ralf@ftp.linux-mips.org 05/06/02 15:37:13 Added files: arch/mips/vr41xx/common: irq.c Log message: Update IRQ handling for vr41xx: o add common IRQ dispatch o change IRQ numbering in int-handler.S o add resource management to icu.c diff -urN linux/arch/mips/vr41xx/common/irq.c linux/arch/mips/vr41xx/common/irq.c --- linux/arch/mips/vr41xx/common/irq.c 1970/01/01 00:00:00 +++ linux/arch/mips/vr41xx/common/irq.c 2005-06-02 15:37:13.229689000 +0100 1.1 @@ -0,0 +1,86 @@ +/* + * Interrupt handing routines for NEC VR4100 series. + * + * Copyright (C) 2005 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include + +#include +#include +#include + +typedef struct irq_cascade { + int (*get_irq)(unsigned int, struct pt_regs *); +} irq_cascade_t; + +static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned; + +static struct irqaction cascade_irqaction = { + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", +}; + +int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)) +{ + int retval = 0; + + if (irq >= NR_IRQS) + return -EINVAL; + + if (irq_cascade[irq].get_irq != NULL) + free_irq(irq, NULL); + + irq_cascade[irq].get_irq = get_irq; + + if (get_irq != NULL) { + retval = setup_irq(irq, &cascade_irqaction); + if (retval < 0) + irq_cascade[irq].get_irq = NULL; + } + + return retval; +} + +asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs) +{ + irq_cascade_t *cascade; + + if (irq >= NR_IRQS) { + atomic_inc(&irq_err_count); + return; + } + + cascade = irq_cascade + irq; + if (cascade->get_irq != NULL) { + irq = cascade->get_irq(irq, regs); + if (irq < 0) + atomic_inc(&irq_err_count); + else + irq_dispatch(irq, regs); + } else + do_IRQ(irq, regs); +} + +extern asmlinkage void vr41xx_handle_interrupt(void); + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); + + set_except_vector(0, vr41xx_handle_interrupt); +} From ths@linux-mips.org Fri Jun 3 02:21:13 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Fri, 03 Jun 2005 03:21:13 +0100 (BST) From: ths@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Fri, 03 Jun 2005 03:21:13 +0100 X-archive-position: 459 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ths@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ths@ftp.linux-mips.org 05/06/03 03:21:07 Modified files: arch/mips/mm : Tag: linux_2_4 tlbex-r4k.S arch/mips64/mm : Tag: linux_2_4 tlbex-r4k.S include/asm-mips: Tag: linux_2_4 hazards.h include/asm-mips64: Tag: linux_2_4 hazards.h Log message: Fix R4[04]00 hazards breakage. diff -urN linux/arch/mips/mm/tlbex-r4k.S linux/arch/mips/mm/tlbex-r4k.S --- linux/arch/mips/mm/Attic/tlbex-r4k.S 2004/11/25 22:18:38 1.2.2.19 +++ linux/arch/mips/mm/Attic/tlbex-r4k.S 2005/06/03 02:21:06 1.2.2.20 @@ -186,6 +186,7 @@ P_MTC0 k1, CP0_ENTRYLO1 # load it mtc0_tlbw_hazard tlbwr # write random tlb entry + nop tlbw_eret_hazard eret END(except_vec0_r4000) diff -urN linux/arch/mips64/mm/tlbex-r4k.S linux/arch/mips64/mm/tlbex-r4k.S --- linux/arch/mips64/mm/Attic/tlbex-r4k.S 2004/11/25 22:18:38 1.1.2.19 +++ linux/arch/mips64/mm/Attic/tlbex-r4k.S 2005/06/03 02:21:07 1.1.2.20 @@ -163,6 +163,7 @@ PTE_RELOAD k0 k1 mtc0_tlbw_hazard tlbwr + nop 1: tlbw_eret_hazard eret END(handle_vec1_r4k) diff -urN linux/include/asm-mips/hazards.h linux/include/asm-mips/hazards.h --- linux/include/asm-mips/hazards.h 2004/11/25 22:18:38 1.1.2.2 +++ linux/include/asm-mips/hazards.h 2005/06/03 02:21:07 1.1.2.3 @@ -68,11 +68,25 @@ #define irq_disable_hazard \ ehb # irq_disable_hazard -#else +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) + +/* + * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. + */ #define irq_enable_hazard + #define irq_disable_hazard +#else + +/* + * Classic MIPS needs 1 - 3 nops or ssnops + */ +#define irq_enable_hazard +#define irq_disable_hazard \ + _ssnop; _ssnop; _ssnop + #endif #else /* __ASSEMBLY__ */ diff -urN linux/include/asm-mips64/hazards.h linux/include/asm-mips64/hazards.h --- linux/include/asm-mips64/Attic/hazards.h 2004/11/25 22:18:38 1.1.2.2 +++ linux/include/asm-mips64/Attic/hazards.h 2005/06/03 02:21:07 1.1.2.3 @@ -68,11 +68,25 @@ #define irq_disable_hazard \ ehb # irq_disable_hazard -#else +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) + +/* + * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. + */ #define irq_enable_hazard + #define irq_disable_hazard +#else + +/* + * Classic MIPS needs 1 - 3 nops or ssnops + */ +#define irq_enable_hazard +#define irq_disable_hazard \ + _ssnop; _ssnop; _ssnop + #endif #else /* __ASSEMBLY__ */ From ralf@linux-mips.org Fri Jun 3 13:08:12 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Fri, 03 Jun 2005 14:08:12 +0100 (BST) From: ralf@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Fri, 03 Jun 2005 14:08:12 +0100 X-archive-position: 460 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ralf@ftp.linux-mips.org 05/06/03 14:08:06 Modified files: arch/mips : Kconfig Makefile defconfig arch/mips/configs: atlas_defconfig capcella_defconfig cobalt_defconfig db1000_defconfig db1100_defconfig db1500_defconfig db1550_defconfig ddb5476_defconfig ddb5477_defconfig decstation_defconfig e55_defconfig ev64120_defconfig ev96100_defconfig ip22_defconfig ip27_defconfig ip32_defconfig it8172_defconfig ivr_defconfig jaguar-atx_defconfig jmr3927_defconfig lasat200_defconfig malta_defconfig mpc30x_defconfig ocelot_3_defconfig ocelot_c_defconfig ocelot_defconfig ocelot_g_defconfig pb1100_defconfig pb1500_defconfig pb1550_defconfig rm200_defconfig sb1250-swarm_defconfig sead_defconfig tb0226_defconfig tb0229_defconfig workpad_defconfig yosemite_defconfig Removed files: arch/mips/configs: osprey_defconfig arch/mips/vr4181: Kconfig arch/mips/vr4181/common: .cvsignore Makefile int_handler.S irq.c serial.c time.c arch/mips/vr4181/osprey: .cvsignore Makefile dbg_io.c prom.c reset.c setup.c include/asm-mips/vr4181: irq.h vr4181.h Log message: Farewell, Osprey ... diff -urN linux/arch/mips/Kconfig linux/arch/mips/Kconfig --- linux/arch/mips/Kconfig 2005/03/18 17:36:52 1.145 +++ linux/arch/mips/Kconfig 2005/06/03 13:08:04 1.146 @@ -431,15 +431,6 @@ Features : kernel debugging, serial terminal, NFS root fs, on-board ether port USB, AC97, PCI, etc. -config NEC_OSPREY - bool "Support for NEC Osprey board" - select DMA_NONCOHERENT - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_LITTLE_ENDIAN - select VR4181 - config MACH_VR41XX bool "Support for NEC VR41XX-based machines" diff -urN linux/arch/mips/Makefile linux/arch/mips/Makefile --- linux/arch/mips/Makefile 2005/05/19 14:45:12 1.194 +++ linux/arch/mips/Makefile 2005/06/03 13:08:04 1.195 @@ -495,13 +495,6 @@ load-$(CONFIG_LASAT) += 0xffffffff80000000 # -# NEC Osprey (vr4181) board -# -core-$(CONFIG_NEC_OSPREY) += arch/mips/vr4181/common/ \ - arch/mips/vr4181/osprey/ -load-$(CONFIG_NEC_OSPREY) += 0xffffffff80002000 - -# # Common VR41xx # core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ diff -urN linux/arch/mips/defconfig linux/arch/mips/defconfig --- linux/arch/mips/defconfig 2005/05/26 09:12:37 1.290 +++ linux/arch/mips/defconfig 2005/06/03 13:08:04 1.291 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:50:43 2005 +# Fri Jun 3 13:55:17 2005 # CONFIG_MIPS=y @@ -91,7 +91,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set CONFIG_SGI_IP22=y diff -urN linux/arch/mips/configs/atlas_defconfig linux/arch/mips/configs/atlas_defconfig --- linux/arch/mips/configs/atlas_defconfig 2005/05/26 09:12:37 1.54 +++ linux/arch/mips/configs/atlas_defconfig 2005/06/03 13:08:04 1.55 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:50:46 2005 +# Fri Jun 3 13:55:20 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/capcella_defconfig linux/arch/mips/configs/capcella_defconfig --- linux/arch/mips/configs/capcella_defconfig 2005/05/26 09:12:37 1.54 +++ linux/arch/mips/configs/capcella_defconfig 2005/06/03 13:08:04 1.55 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:50:49 2005 +# Fri Jun 3 13:55:22 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/cobalt_defconfig linux/arch/mips/configs/cobalt_defconfig --- linux/arch/mips/configs/cobalt_defconfig 2005/05/26 09:12:37 1.51 +++ linux/arch/mips/configs/cobalt_defconfig 2005/06/03 13:08:04 1.52 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:50:50 2005 +# Fri Jun 3 13:55:24 2005 # CONFIG_MIPS=y @@ -84,7 +84,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/db1000_defconfig linux/arch/mips/configs/db1000_defconfig --- linux/arch/mips/configs/db1000_defconfig 2005/05/26 09:12:37 1.57 +++ linux/arch/mips/configs/db1000_defconfig 2005/06/03 13:08:04 1.58 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:50:53 2005 +# Fri Jun 3 13:55:27 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/db1100_defconfig linux/arch/mips/configs/db1100_defconfig --- linux/arch/mips/configs/db1100_defconfig 2005/05/26 09:12:37 1.56 +++ linux/arch/mips/configs/db1100_defconfig 2005/06/03 13:08:04 1.57 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:50:55 2005 +# Fri Jun 3 13:55:29 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/db1500_defconfig linux/arch/mips/configs/db1500_defconfig --- linux/arch/mips/configs/db1500_defconfig 2005/05/26 09:12:37 1.59 +++ linux/arch/mips/configs/db1500_defconfig 2005/06/03 13:08:04 1.60 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:50:57 2005 +# Fri Jun 3 13:55:32 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/db1550_defconfig linux/arch/mips/configs/db1550_defconfig --- linux/arch/mips/configs/db1550_defconfig 2005/05/26 09:12:37 1.34 +++ linux/arch/mips/configs/db1550_defconfig 2005/06/03 13:08:04 1.35 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:00 2005 +# Fri Jun 3 13:55:34 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ddb5476_defconfig linux/arch/mips/configs/ddb5476_defconfig --- linux/arch/mips/configs/ddb5476_defconfig 2005/05/26 09:12:37 1.51 +++ linux/arch/mips/configs/ddb5476_defconfig 2005/06/03 13:08:04 1.52 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:02 2005 +# Fri Jun 3 13:55:37 2005 # CONFIG_MIPS=y @@ -84,7 +84,6 @@ # CONFIG_DDB5074 is not set CONFIG_DDB5476=y # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ddb5477_defconfig linux/arch/mips/configs/ddb5477_defconfig --- linux/arch/mips/configs/ddb5477_defconfig 2005/05/26 09:12:37 1.51 +++ linux/arch/mips/configs/ddb5477_defconfig 2005/06/03 13:08:04 1.52 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:04 2005 +# Fri Jun 3 13:55:39 2005 # CONFIG_MIPS=y @@ -84,7 +84,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set CONFIG_DDB5477=y -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/decstation_defconfig linux/arch/mips/configs/decstation_defconfig --- linux/arch/mips/configs/decstation_defconfig 2005/05/26 09:12:37 1.52 +++ linux/arch/mips/configs/decstation_defconfig 2005/06/03 13:08:04 1.53 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:06 2005 +# Fri Jun 3 13:55:42 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/e55_defconfig linux/arch/mips/configs/e55_defconfig --- linux/arch/mips/configs/e55_defconfig 2005/05/26 09:12:37 1.53 +++ linux/arch/mips/configs/e55_defconfig 2005/06/03 13:08:04 1.54 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:08 2005 +# Fri Jun 3 13:55:44 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ev64120_defconfig linux/arch/mips/configs/ev64120_defconfig --- linux/arch/mips/configs/ev64120_defconfig 2005/05/26 09:12:37 1.50 +++ linux/arch/mips/configs/ev64120_defconfig 2005/06/03 13:08:04 1.51 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:10 2005 +# Fri Jun 3 13:55:46 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ev96100_defconfig linux/arch/mips/configs/ev96100_defconfig --- linux/arch/mips/configs/ev96100_defconfig 2005/05/26 09:12:37 1.51 +++ linux/arch/mips/configs/ev96100_defconfig 2005/06/03 13:08:04 1.52 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:12 2005 +# Fri Jun 3 13:55:48 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ip22_defconfig linux/arch/mips/configs/ip22_defconfig --- linux/arch/mips/configs/ip22_defconfig 2005/05/26 09:12:37 1.60 +++ linux/arch/mips/configs/ip22_defconfig 2005/06/03 13:08:04 1.61 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:14 2005 +# Fri Jun 3 13:55:50 2005 # CONFIG_MIPS=y @@ -91,7 +91,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set CONFIG_SGI_IP22=y diff -urN linux/arch/mips/configs/ip27_defconfig linux/arch/mips/configs/ip27_defconfig --- linux/arch/mips/configs/ip27_defconfig 2005/05/26 09:12:37 1.64 +++ linux/arch/mips/configs/ip27_defconfig 2005/06/03 13:08:04 1.65 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:17 2005 +# Fri Jun 3 13:55:53 2005 # CONFIG_MIPS=y @@ -93,7 +93,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ip32_defconfig linux/arch/mips/configs/ip32_defconfig --- linux/arch/mips/configs/ip32_defconfig 2005/05/26 09:12:37 1.54 +++ linux/arch/mips/configs/ip32_defconfig 2005/06/03 13:08:04 1.55 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:19 2005 +# Fri Jun 3 13:55:55 2005 # CONFIG_MIPS=y @@ -85,7 +85,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/it8172_defconfig linux/arch/mips/configs/it8172_defconfig --- linux/arch/mips/configs/it8172_defconfig 2005/05/26 09:12:37 1.50 +++ linux/arch/mips/configs/it8172_defconfig 2005/06/03 13:08:04 1.51 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:21 2005 +# Fri Jun 3 13:55:57 2005 # CONFIG_MIPS=y @@ -91,7 +91,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ivr_defconfig linux/arch/mips/configs/ivr_defconfig --- linux/arch/mips/configs/ivr_defconfig 2005/05/26 09:12:37 1.50 +++ linux/arch/mips/configs/ivr_defconfig 2005/06/03 13:08:04 1.51 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:23 2005 +# Fri Jun 3 13:55:59 2005 # CONFIG_MIPS=y @@ -91,7 +91,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/jaguar-atx_defconfig linux/arch/mips/configs/jaguar-atx_defconfig --- linux/arch/mips/configs/jaguar-atx_defconfig 2005/05/26 09:12:37 1.55 +++ linux/arch/mips/configs/jaguar-atx_defconfig 2005/06/03 13:08:04 1.56 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:26 2005 +# Fri Jun 3 13:56:01 2005 # CONFIG_MIPS=y @@ -88,7 +88,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/jmr3927_defconfig linux/arch/mips/configs/jmr3927_defconfig --- linux/arch/mips/configs/jmr3927_defconfig 2005/05/26 09:12:37 1.51 +++ linux/arch/mips/configs/jmr3927_defconfig 2005/06/03 13:08:04 1.52 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:28 2005 +# Fri Jun 3 13:56:03 2005 # CONFIG_MIPS=y @@ -84,7 +84,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/lasat200_defconfig linux/arch/mips/configs/lasat200_defconfig --- linux/arch/mips/configs/lasat200_defconfig 2005/05/26 09:12:37 1.51 +++ linux/arch/mips/configs/lasat200_defconfig 2005/06/03 13:08:04 1.52 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:30 2005 +# Fri Jun 3 13:56:05 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/malta_defconfig linux/arch/mips/configs/malta_defconfig --- linux/arch/mips/configs/malta_defconfig 2005/05/26 09:12:37 1.53 +++ linux/arch/mips/configs/malta_defconfig 2005/06/03 13:08:04 1.54 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:33 2005 +# Fri Jun 3 13:56:08 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/mpc30x_defconfig linux/arch/mips/configs/mpc30x_defconfig --- linux/arch/mips/configs/mpc30x_defconfig 2005/05/26 09:12:37 1.55 +++ linux/arch/mips/configs/mpc30x_defconfig 2005/06/03 13:08:04 1.56 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:35 2005 +# Fri Jun 3 13:56:10 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ocelot_3_defconfig linux/arch/mips/configs/ocelot_3_defconfig --- linux/arch/mips/configs/ocelot_3_defconfig 2005/05/26 09:12:37 1.23 +++ linux/arch/mips/configs/ocelot_3_defconfig 2005/06/03 13:08:04 1.24 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:37 2005 +# Fri Jun 3 13:56:13 2005 # CONFIG_MIPS=y @@ -91,7 +91,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ocelot_c_defconfig linux/arch/mips/configs/ocelot_c_defconfig --- linux/arch/mips/configs/ocelot_c_defconfig 2005/05/26 09:12:37 1.49 +++ linux/arch/mips/configs/ocelot_c_defconfig 2005/06/03 13:08:04 1.50 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:39 2005 +# Fri Jun 3 13:56:15 2005 # CONFIG_MIPS=y @@ -84,7 +84,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ocelot_defconfig linux/arch/mips/configs/ocelot_defconfig --- linux/arch/mips/configs/ocelot_defconfig 2005/05/26 09:12:37 1.51 +++ linux/arch/mips/configs/ocelot_defconfig 2005/06/03 13:08:04 1.52 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:41 2005 +# Fri Jun 3 13:56:16 2005 # CONFIG_MIPS=y @@ -84,7 +84,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/ocelot_g_defconfig linux/arch/mips/configs/ocelot_g_defconfig --- linux/arch/mips/configs/ocelot_g_defconfig 2005/05/26 09:12:37 1.44 +++ linux/arch/mips/configs/ocelot_g_defconfig 2005/06/03 13:08:04 1.45 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:43 2005 +# Fri Jun 3 13:56:19 2005 # CONFIG_MIPS=y @@ -84,7 +84,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/pb1100_defconfig linux/arch/mips/configs/pb1100_defconfig --- linux/arch/mips/configs/pb1100_defconfig 2005/05/26 09:12:37 1.53 +++ linux/arch/mips/configs/pb1100_defconfig 2005/06/03 13:08:04 1.54 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:48 2005 +# Fri Jun 3 14:00:26 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/pb1500_defconfig linux/arch/mips/configs/pb1500_defconfig --- linux/arch/mips/configs/pb1500_defconfig 2005/05/26 09:12:37 1.59 +++ linux/arch/mips/configs/pb1500_defconfig 2005/06/03 13:08:05 1.60 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:50 2005 +# Fri Jun 3 14:00:28 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/pb1550_defconfig linux/arch/mips/configs/pb1550_defconfig --- linux/arch/mips/configs/pb1550_defconfig 2005/05/26 09:12:37 1.49 +++ linux/arch/mips/configs/pb1550_defconfig 2005/06/03 13:08:05 1.50 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:53 2005 +# Fri Jun 3 14:00:31 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/rm200_defconfig linux/arch/mips/configs/rm200_defconfig --- linux/arch/mips/configs/rm200_defconfig 2005/05/26 09:12:37 1.60 +++ linux/arch/mips/configs/rm200_defconfig 2005/06/03 13:08:05 1.61 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:58 2005 +# Fri Jun 3 14:00:34 2005 # CONFIG_MIPS=y @@ -92,7 +92,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/sb1250-swarm_defconfig linux/arch/mips/configs/sb1250-swarm_defconfig --- linux/arch/mips/configs/sb1250-swarm_defconfig 2005/05/26 09:12:37 1.57 +++ linux/arch/mips/configs/sb1250-swarm_defconfig 2005/06/03 13:08:05 1.58 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:52:00 2005 +# Fri Jun 3 14:00:36 2005 # CONFIG_MIPS=y @@ -92,7 +92,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/sead_defconfig linux/arch/mips/configs/sead_defconfig --- linux/arch/mips/configs/sead_defconfig 2005/05/26 09:12:37 1.49 +++ linux/arch/mips/configs/sead_defconfig 2005/06/03 13:08:05 1.50 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:52:02 2005 +# Fri Jun 3 14:00:38 2005 # CONFIG_MIPS=y @@ -82,7 +82,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/tb0226_defconfig linux/arch/mips/configs/tb0226_defconfig --- linux/arch/mips/configs/tb0226_defconfig 2005/05/26 09:12:37 1.53 +++ linux/arch/mips/configs/tb0226_defconfig 2005/06/03 13:08:05 1.54 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:52:04 2005 +# Fri Jun 3 14:00:40 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/tb0229_defconfig linux/arch/mips/configs/tb0229_defconfig --- linux/arch/mips/configs/tb0229_defconfig 2005/05/26 09:12:37 1.56 +++ linux/arch/mips/configs/tb0229_defconfig 2005/06/03 13:08:05 1.57 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:52:06 2005 +# Fri Jun 3 14:00:42 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/workpad_defconfig linux/arch/mips/configs/workpad_defconfig --- linux/arch/mips/configs/workpad_defconfig 2005/05/26 09:12:37 1.53 +++ linux/arch/mips/configs/workpad_defconfig 2005/06/03 13:08:05 1.54 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:52:08 2005 +# Fri Jun 3 14:00:44 2005 # CONFIG_MIPS=y @@ -90,7 +90,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/yosemite_defconfig linux/arch/mips/configs/yosemite_defconfig --- linux/arch/mips/configs/yosemite_defconfig 2005/05/26 09:12:37 1.55 +++ linux/arch/mips/configs/yosemite_defconfig 2005/06/03 13:08:05 1.56 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:52:10 2005 +# Fri Jun 3 14:00:46 2005 # CONFIG_MIPS=y @@ -91,7 +91,6 @@ # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set # CONFIG_MACH_VR41XX is not set CONFIG_PMC_YOSEMITE=y # CONFIG_SGI_IP22 is not set diff -urN linux/arch/mips/configs/osprey_defconfig linux/arch/mips/configs/osprey_defconfig --- linux/arch/mips/configs/Attic/osprey_defconfig 2005-06-03 14:08:05.934631000 +0100 1.50 +++ linux/arch/mips/configs/Attic/osprey_defconfig 1970/01/01 00:00:00+0100 @@ -1,653 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.12-rc5 -# Wed May 25 18:51:45 2005 -# -CONFIG_MIPS=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Machine selection -# -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_EV96100 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_OCELOT_C is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set -# CONFIG_DDB5477 is not set -CONFIG_NEC_OSPREY=y -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_PTSWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_VR4181=y - -# -# CPU selection -# -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -CONFIG_CPU_VR41XX=y -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_MIPS32=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -# CONFIG_CPU_ADVANCED is not set -CONFIG_CPU_HAS_SYNC=y -# CONFIG_PREEMPT is not set - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_VR41XX is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set - -# -# XFS support -# -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_EXPORTFS=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="ip=bootp ether=46,0x03fe0300,eth0" - -# -# Security options -# -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -CONFIG_LIBCRC32C=m -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y diff -urN linux/arch/mips/vr4181/Kconfig linux/arch/mips/vr4181/Kconfig --- linux/arch/mips/vr4181/Attic/Kconfig 2005-06-03 14:08:06.008538000 +0100 1.2 +++ linux/arch/mips/vr4181/Attic/Kconfig 1970/01/01 00:00:00+0100 @@ -1,61 +0,0 @@ -config NEC_CMBVR4133 - bool "Support for NEC CMB-VR4133" - depends on MACH_VR41XX - select CPU_VR41XX - select DMA_NONCOHERENT - select IRQ_CPU - select HW_HAS_PCI - select PCI_VR41XX - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - -config ROCKHOPPER - bool "Support for Rockhopper baseboard" - depends on NEC_CMBVR4133 - select I8259 - select HAVE_STD_PC_SERIAL_PORT - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - -config CASIO_E55 - bool "Support for CASIO CASSIOPEIA E-10/15/55/65" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select IRQ_CPU - select ISA - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - -config IBM_WORKPAD - bool "Support for IBM WorkPad z50" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select IRQ_CPU - select ISA - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - -config TANBAC_TB0226 - bool "Support for TANBAC TB0226 (Mbase)" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - help - The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by - TANBAC. Please refer to about Mbase. - -config TANBAC_TB0229 - bool "Support for TANBAC TB0229 (VR4131DIMM)" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - help - The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured - by TANBAC. Please refer to about - VR4131DIMM. diff -urN linux/arch/mips/vr4181/common/.cvsignore linux/arch/mips/vr4181/common/.cvsignore --- linux/arch/mips/vr4181/common/Attic/.cvsignore 2005-06-03 14:08:06.092827000 +0100 1.8 +++ linux/arch/mips/vr4181/common/Attic/.cvsignore 1970/01/01 00:00:00+0100 @@ -1,3 +0,0 @@ -.*.o -.*.o.d -.*.cmd diff -urN linux/arch/mips/vr4181/common/Makefile linux/arch/mips/vr4181/common/Makefile --- linux/arch/mips/vr4181/common/Attic/Makefile 2005-06-03 14:08:06.107318000 +0100 1.6 +++ linux/arch/mips/vr4181/common/Attic/Makefile 1970/01/01 00:00:00+0100 @@ -1,7 +0,0 @@ -# -# Makefile for common code of NEC vr4181 based boards -# - -obj-y := irq.o int_handler.o serial.o time.o - -EXTRA_AFLAGS := $(CFLAGS) diff -urN linux/arch/mips/vr4181/common/int_handler.S linux/arch/mips/vr4181/common/int_handler.S --- linux/arch/mips/vr4181/common/Attic/int_handler.S 2005-06-03 14:08:06.122298000 +0100 1.1 +++ linux/arch/mips/vr4181/common/Attic/int_handler.S 1970/01/01 00:00:00+0100 @@ -1,206 +0,0 @@ -/* - * arch/mips/vr4181/common/int_handler.S - * - * Adapted to the VR4181 and almost entirely rewritten: - * Copyright (C) 1999 Bradley D. LaRonde and Michael Klar - * - * Clean up to conform to the new IRQ - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include -#include -#include -#include - -#include - -/* - * [jsun] - * See include/asm/vr4181/irq.h for IRQ assignment and strategy. - */ - - .text - .set noreorder - - .align 5 - NESTED(vr4181_handle_irq, PT_SIZE, ra) - - .set noat - SAVE_ALL - CLI - - .set at - .set noreorder - - mfc0 t0, CP0_CAUSE - mfc0 t2, CP0_STATUS - - and t0, t2 - - /* we check IP3 first; it happens most frequently */ - andi t1, t0, STATUSF_IP3 - bnez t1, ll_cpu_ip3 - andi t1, t0, STATUSF_IP2 - bnez t1, ll_cpu_ip2 - andi t1, t0, STATUSF_IP7 /* cpu timer */ - bnez t1, ll_cputimer_irq - andi t1, t0, STATUSF_IP4 - bnez t1, ll_cpu_ip4 - andi t1, t0, STATUSF_IP5 - bnez t1, ll_cpu_ip5 - andi t1, t0, STATUSF_IP6 - bnez t1, ll_cpu_ip6 - andi t1, t0, STATUSF_IP0 /* software int 0 */ - bnez t1, ll_cpu_ip0 - andi t1, t0, STATUSF_IP1 /* software int 1 */ - bnez t1, ll_cpu_ip1 - nop - - .set reorder -do_spurious: - j spurious_interrupt - -/* - * regular CPU irqs - */ -ll_cputimer_irq: - li a0, VR4181_IRQ_TIMER - move a1, sp - jal do_IRQ - j ret_from_irq - - -ll_cpu_ip0: - li a0, VR4181_IRQ_SW1 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip1: - li a0, VR4181_IRQ_SW2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip3: - li a0, VR4181_IRQ_INT1 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip4: - li a0, VR4181_IRQ_INT2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip5: - li a0, VR4181_IRQ_INT3 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip6: - li a0, VR4181_IRQ_INT4 - move a1, sp - jal do_IRQ - j ret_from_irq - -/* - * One of the sys irq has happend. - * - * In the interest of speed, we first determine in the following order - * which 16-irq block have pending interrupts: - * sysint1 (16 sources, including cascading intrs from GPIO) - * sysint2 - * gpio (16 intr sources) - * - * Then we do binary search to find the exact interrupt source. - */ -ll_cpu_ip2: - - lui t3,%hi(VR4181_SYSINT1REG) - lhu t0,%lo(VR4181_SYSINT1REG)(t3) - lhu t2,%lo(VR4181_MSYSINT1REG)(t3) - and t0, 0xfffb /* hack - remove RTC Long 1 intr */ - and t0, t2 - beqz t0, check_sysint2 - - /* check for GPIO interrupts */ - andi t1, t0, 0x0100 - bnez t1, check_gpio_int - - /* so we have an interrupt in sysint1 which is not gpio int */ - li a0, VR4181_SYS_IRQ_BASE - 1 - j check_16 - -check_sysint2: - - lhu t0,%lo(VR4181_SYSINT2REG)(t3) - lhu t2,%lo(VR4181_MSYSINT2REG)(t3) - and t0, 0xfffe /* hack - remove RTC Long 2 intr */ - and t0, t2 - li a0, VR4181_SYS_IRQ_BASE + 16 - 1 - j check_16 - -check_gpio_int: - lui t3,%hi(VR4181_GPINTMSK) - lhu t0,%lo(VR4181_GPINTMSK)(t3) - lhu t2,%lo(VR4181_GPINTSTAT)(t3) - xori t0, 0xffff /* why? reverse logic? */ - and t0, t2 - li a0, VR4181_GPIO_IRQ_BASE - 1 - j check_16 - -/* - * When we reach check_16, we have 16-bit status in t0 and base irq number - * in a0. - */ -check_16: - andi t1, t0, 0xff - bnez t1, check_8 - - srl t0, 8 - addi a0, 8 - j check_8 - -/* - * When we reach check_8, we have 8-bit status in t0 and base irq number - * in a0. - */ -check_8: - andi t1, t0, 0xf - bnez t1, check_4 - - srl t0, 4 - addi a0, 4 - j check_4 - -/* - * When we reach check_4, we have 4-bit status in t0 and base irq number - * in a0. - */ -check_4: - andi t0, t0, 0xf - beqz t0, do_spurious - -loop: - andi t2, t0, 0x1 - srl t0, 1 - addi a0, 1 - beqz t2, loop - -found_it: - move a1, sp - jal do_IRQ - - j ret_from_irq - - END(vr4181_handle_irq) diff -urN linux/arch/mips/vr4181/common/irq.c linux/arch/mips/vr4181/common/irq.c --- linux/arch/mips/vr4181/common/Attic/irq.c 2005-06-03 14:08:06.138752000 +0100 1.13 +++ linux/arch/mips/vr4181/common/Attic/irq.c 1970/01/01 00:00:00+0100 @@ -1,237 +0,0 @@ -/* - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * linux/arch/mips/vr4181/common/irq.c - * Completely re-written to use the new irq.c - * - * Credits to Bradley D. LaRonde and Michael Klar for writing the original - * irq.c file which was derived from the common irq.c file. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -/* - * Strategy: - * - * We essentially have three irq controllers, CPU, system, and gpio. - * - * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and - * CONFIG_IRQ_CPU config option. - * - * We here provide sys_irq and gpio_irq controller code. - */ - -static int sys_irq_base; -static int gpio_irq_base; - -/* ---------------------- sys irq ------------------------ */ -static void -sys_irq_enable(unsigned int irq) -{ - irq -= sys_irq_base; - if (irq < 16) { - *VR4181_MSYSINT1REG |= (u16)(1 << irq); - } else { - irq -= 16; - *VR4181_MSYSINT2REG |= (u16)(1 << irq); - } -} - -static void -sys_irq_disable(unsigned int irq) -{ - irq -= sys_irq_base; - if (irq < 16) { - *VR4181_MSYSINT1REG &= ~((u16)(1 << irq)); - } else { - irq -= 16; - *VR4181_MSYSINT2REG &= ~((u16)(1 << irq)); - } - -} - -static unsigned int -sys_irq_startup(unsigned int irq) -{ - sys_irq_enable(irq); - return 0; -} - -#define sys_irq_shutdown sys_irq_disable -#define sys_irq_ack sys_irq_disable - -static void -sys_irq_end(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - sys_irq_enable(irq); -} - -static hw_irq_controller sys_irq_controller = { - .typename = "vr4181_sys_irq", - .startup = sys_irq_startup, - .shutdown = sys_irq_shutdown, - .enable = sys_irq_enable, - .disable = sys_irq_disable, - .ack = sys_irq_ack, - .end = sys_irq_end, -}; - -/* ---------------------- gpio irq ------------------------ */ -/* gpio irq lines use reverse logic */ -static void -gpio_irq_enable(unsigned int irq) -{ - irq -= gpio_irq_base; - *VR4181_GPINTMSK &= ~((u16)(1 << irq)); -} - -static void -gpio_irq_disable(unsigned int irq) -{ - irq -= gpio_irq_base; - *VR4181_GPINTMSK |= (u16)(1 << irq); -} - -static unsigned int -gpio_irq_startup(unsigned int irq) -{ - gpio_irq_enable(irq); - - irq -= gpio_irq_base; - *VR4181_GPINTEN |= (u16)(1 << irq ); - - return 0; -} - -static void -gpio_irq_shutdown(unsigned int irq) -{ - gpio_irq_disable(irq); - - irq -= gpio_irq_base; - *VR4181_GPINTEN &= ~((u16)(1 << irq )); -} - -static void -gpio_irq_ack(unsigned int irq) -{ - u16 irqtype; - u16 irqshift; - - gpio_irq_disable(irq); - - /* we clear interrupt if it is edge triggered */ - irq -= gpio_irq_base; - if (irq < 8) { - irqtype = *VR4181_GPINTTYPL; - irqshift = 2 << (irq*2); - } else { - irqtype = *VR4181_GPINTTYPH; - irqshift = 2 << ((irq-8)*2); - } - if ( ! (irqtype & irqshift) ) { - *VR4181_GPINTSTAT = (u16) (1 << irq); - } -} - -static void -gpio_irq_end(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - gpio_irq_enable(irq); -} - -static hw_irq_controller gpio_irq_controller = { - .typename = "vr4181_gpio_irq", - .startup = gpio_irq_startup, - .shutdown = gpio_irq_shutdown, - .enable = gpio_irq_enable, - .disable = gpio_irq_disable, - .ack = gpio_irq_ack, - .end = gpio_irq_end, -}; - -/* --------------------- IRQ init stuff ---------------------- */ - -extern asmlinkage void vr4181_handle_irq(void); -extern void breakpoint(void); -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); -extern void mips_cpu_irq_init(u32 irq_base); - -static struct irqaction cascade = - { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL }; -static struct irqaction reserved = - { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL }; - -void __init arch_init_irq(void) -{ - int i; - - set_except_vector(0, vr4181_handle_irq); - - /* init CPU irqs */ - mips_cpu_irq_init(VR4181_CPU_IRQ_BASE); - - /* init sys irqs */ - sys_irq_base = VR4181_SYS_IRQ_BASE; - for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &sys_irq_controller; - } - - /* init gpio irqs */ - gpio_irq_base = VR4181_GPIO_IRQ_BASE; - for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &gpio_irq_controller; - } - - /* Default all ICU IRQs to off ... */ - *VR4181_MSYSINT1REG = 0; - *VR4181_MSYSINT2REG = 0; - - /* We initialize the level 2 ICU registers to all bits disabled. */ - *VR4181_MPIUINTREG = 0; - *VR4181_MAIUINTREG = 0; - *VR4181_MKIUINTREG = 0; - - /* disable all GPIO intrs */ - *VR4181_GPINTMSK = 0xffff; - - /* vector handler. What these do is register the IRQ as non-sharable */ - setup_irq(VR4181_IRQ_INT0, &cascade); - setup_irq(VR4181_IRQ_GIU, &cascade); - - /* - * RTC interrupts are interesting. They have two destinations. - * One is at sys irq controller, and the other is at CPU IP3 and IP4. - * RTC timer is used as system timer. - * We enable them here, but timer routine will register later - * with CPU IP3/IP4. - */ - setup_irq(VR4181_IRQ_RTCL1, &reserved); - setup_irq(VR4181_IRQ_RTCL2, &reserved); -} diff -urN linux/arch/mips/vr4181/common/serial.c linux/arch/mips/vr4181/common/serial.c --- linux/arch/mips/vr4181/common/Attic/serial.c 2005-06-03 14:08:06.155843000 +0100 1.3 +++ linux/arch/mips/vr4181/common/Attic/serial.c 1970/01/01 00:00:00+0100 @@ -1,51 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/vr4181/common/serial.c - * initialize serial port on vr4181. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * [jsun, 010925] - * You need to make sure rs_table has at least one element in - * drivers/char/serial.c file. There is no good way to do it right - * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your - * configure file, which would gives you 64 ports and wastes 11K ram. - */ - -#include -#include -#include -#include - -#include - -void __init vr4181_init_serial(void) -{ - struct serial_struct s; - - /* turn on UART clock */ - *VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU; - - /* clear memory */ - memset(&s, 0, sizeof(s)); - - s.line = 0; /* we set the first one */ - s.baud_base = 1152000; - s.irq = VR4181_IRQ_SIU; - s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */ - s.iomem_base = (u8*)VR4181_SIURB; - s.iomem_reg_shift = 0; - s.io_type = SERIAL_IO_MEM; - if (early_serial_setup(&s) != 0) { - panic("vr4181_init_serial() failed!"); - } -} - diff -urN linux/arch/mips/vr4181/common/time.c linux/arch/mips/vr4181/common/time.c --- linux/arch/mips/vr4181/common/Attic/time.c 2005-06-03 14:08:06.170816000 +0100 1.4 +++ linux/arch/mips/vr4181/common/Attic/time.c 1970/01/01 00:00:00+0100 @@ -1,145 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * rtc and time ops for vr4181. Part of code is drived from - * linux-vr, originally written by Bradley D. LaRonde & Michael Klar. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include /* for HZ */ -#include -#include - -#include -#include - -#include - -#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ) - -/* - * RTC ops - */ - -DEFINE_SPINLOCK(rtc_lock); - -/* per VR41xx docs, bad data can be read if between 2 counts */ -static inline unsigned short -read_time_reg(volatile unsigned short *reg) -{ - unsigned short value; - do { - value = *reg; - barrier(); - } while (value != *reg); - return value; -} - -static unsigned long -vr4181_rtc_get_time(void) -{ - unsigned short regh, regm, regl; - - // why this crazy order, you ask? to guarantee that neither m - // nor l wrap before all 3 read - do { - regm = read_time_reg(VR4181_ETIMEMREG); - barrier(); - regh = read_time_reg(VR4181_ETIMEHREG); - barrier(); - regl = read_time_reg(VR4181_ETIMELREG); - } while (regm != read_time_reg(VR4181_ETIMEMREG)); - return ((regh << 17) | (regm << 1) | (regl >> 15)); -} - -static int -vr4181_rtc_set_time(unsigned long timeval) -{ - unsigned short intreg; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - intreg = *VR4181_RTCINTREG & 0x05; - barrier(); - *VR4181_ETIMELREG = timeval << 15; - *VR4181_ETIMEMREG = timeval >> 1; - *VR4181_ETIMEHREG = timeval >> 17; - barrier(); - // assume that any ints that just triggered are invalid, since the - // time value is written non-atomically in 3 separate regs - *VR4181_RTCINTREG = 0x05 ^ intreg; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - - -/* - * timer interrupt routine (wrapper) - * - * we need our own interrupt routine because we need to clear - * RTC1 interrupt. - */ -static void -vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - /* Clear the interrupt. */ - *VR4181_RTCINTREG = 0x2; - - /* call the generic one */ - timer_interrupt(irq, dev_id, regs); -} - - -/* - * vr4181_time_init: - * - * We pick the following choices: - * . we use elapsed timer as the RTC. We set some reasonable init data since - * it does not persist across reset - * . we use RTC1 as the system timer interrupt source. - * . we use CPU counter for fast_gettimeoffset and we calivrate the cpu - * frequency. In other words, we use calibrate_div64_gettimeoffset(). - * . we use our own timer interrupt routine which clears the interrupt - * and then calls the generic high-level timer interrupt routine. - * - */ - -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); - -static void -vr4181_timer_setup(struct irqaction *irq) -{ - /* over-write the handler to be our own one */ - irq->handler = vr4181_timer_interrupt; - - /* sets up the frequency */ - *VR4181_RTCL1LREG = COUNTS_PER_JIFFY; - *VR4181_RTCL1HREG = 0; - - /* and ack any pending ints */ - *VR4181_RTCINTREG = 0x2; - - /* setup irqaction */ - setup_irq(VR4181_IRQ_INT1, irq); - -} - -void -vr4181_init_time(void) -{ - /* setup hookup functions */ - rtc_get_time = vr4181_rtc_get_time; - rtc_set_time = vr4181_rtc_set_time; - - board_timer_setup = vr4181_timer_setup; -} - diff -urN linux/arch/mips/vr4181/osprey/.cvsignore linux/arch/mips/vr4181/osprey/.cvsignore --- linux/arch/mips/vr4181/osprey/Attic/.cvsignore 2005-06-03 14:08:06.253554000 +0100 1.8 +++ linux/arch/mips/vr4181/osprey/Attic/.cvsignore 1970/01/01 00:00:00+0100 @@ -1,3 +0,0 @@ -.*.o -.*.o.d -.*.cmd diff -urN linux/arch/mips/vr4181/osprey/Makefile linux/arch/mips/vr4181/osprey/Makefile --- linux/arch/mips/vr4181/osprey/Attic/Makefile 2005-06-03 14:08:06.267920000 +0100 1.8 +++ linux/arch/mips/vr4181/osprey/Attic/Makefile 1970/01/01 00:00:00+0100 @@ -1,7 +0,0 @@ -# -# Makefile for common code of NEC Osprey board -# - -obj-y := setup.o prom.o reset.o - -obj-$(CONFIG_KGDB) += dbg_io.o diff -urN linux/arch/mips/vr4181/osprey/dbg_io.c linux/arch/mips/vr4181/osprey/dbg_io.c --- linux/arch/mips/vr4181/osprey/Attic/dbg_io.c 2005-06-03 14:08:06.282429000 +0100 1.2 +++ linux/arch/mips/vr4181/osprey/Attic/dbg_io.c 1970/01/01 00:00:00+0100 @@ -1,136 +0,0 @@ -/* - * kgdb io functions for osprey. We use the serial port on debug board. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* ======================= CONFIG ======================== */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE 0xb7fffff0 -#define MAX_BAUD 115200 - -/* distance in bytes between two serial registers */ -#define REG_OFFSET 1 - -/* - * 0 - kgdb does serial init - * 1 - kgdb skip serial init - */ -static int remoteDebugInitialized = 1; - -/* - * the default baud rate *if* kgdb does serial init - */ -#define BAUD_DEFAULT UART16550_BAUD_38400 - -/* ======================= END OF CONFIG ======================== */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up buad rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} diff -urN linux/arch/mips/vr4181/osprey/prom.c linux/arch/mips/vr4181/osprey/prom.c --- linux/arch/mips/vr4181/osprey/Attic/prom.c 2005-06-03 14:08:06.299474000 +0100 1.7 +++ linux/arch/mips/vr4181/osprey/Attic/prom.c 1970/01/01 00:00:00+0100 @@ -1,49 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * arch/mips/vr4181/osprey/prom.c - * prom code for osprey. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include -#include -#include -#include -#include -#include -#include - -const char *get_system_type(void) -{ - return "NEC_Vr41xx Osprey"; -} - -/* - * [jsun] right now we assume it is the nec debug monitor, which does - * not pass any arguments. - */ -void __init prom_init(void) -{ - // cmdline is now set in default config - // strcpy(arcs_cmdline, "ip=bootp "); - // strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 "); - // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 " - // strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 "); - - mips_machgroup = MACH_GROUP_NEC_VR41XX; - mips_machtype = MACH_NEC_OSPREY; - - /* 16MB fixed */ - add_memory_region(0, 16 << 20, BOOT_MEM_RAM); -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff -urN linux/arch/mips/vr4181/osprey/reset.c linux/arch/mips/vr4181/osprey/reset.c --- linux/arch/mips/vr4181/osprey/Attic/reset.c 2005-06-03 14:08:06.314709000 +0100 1.4 +++ linux/arch/mips/vr4181/osprey/Attic/reset.c 1970/01/01 00:00:00+0100 @@ -1,40 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - */ -#include -#include -#include -#include -#include -#include -#include - -void nec_osprey_restart(char *command) -{ - set_c0_status(ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -void nec_osprey_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void nec_osprey_power_off(void) -{ - nec_osprey_halt(); -} diff -urN linux/arch/mips/vr4181/osprey/setup.c linux/arch/mips/vr4181/osprey/setup.c --- linux/arch/mips/vr4181/osprey/Attic/setup.c 2005-06-03 14:08:06.329505000 +0100 1.8 +++ linux/arch/mips/vr4181/osprey/Attic/setup.c 1970/01/01 00:00:00+0100 @@ -1,68 +0,0 @@ -/* - * linux/arch/mips/vr4181/setup.c - * - * VR41xx setup routines - * - * Copyright (C) 1999 Bradley D. LaRonde - * Copyright (C) 1999, 2000 Michael Klar - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include -#include -#include -#include -#include -#include - - -extern void nec_osprey_restart(char* c); -extern void nec_osprey_halt(void); -extern void nec_osprey_power_off(void); - -extern void vr4181_init_serial(void); -extern void vr4181_init_time(void); - -static void __init nec_osprey_setup(void) -{ - set_io_port_base(VR4181_PORT_BASE); - isa_slot_offset = VR4181_ISAMEM_BASE; - - vr4181_init_serial(); - vr4181_init_time(); - - _machine_restart = nec_osprey_restart; - _machine_halt = nec_osprey_halt; - _machine_power_off = nec_osprey_power_off; - - /* setup resource limit */ - ioport_resource.end = 0xffffffff; - iomem_resource.end = 0xffffffff; - - /* [jsun] hack */ - /* - printk("[jsun] hack to change external ISA control register, %x -> %x\n", - (*VR4181_XISACTL), - (*VR4181_XISACTL) | 0x2); - *VR4181_XISACTL |= 0x2; - */ - - // *VR4181_GPHIBSTH = 0x2000; - // *VR4181_GPMD0REG = 0x00c0; - // *VR4181_GPINTEN = 1<<6; - - /* [jsun] I believe this will get the interrupt type right - * for the ether port. - */ - *VR4181_GPINTTYPL = 0x3000; -} - -early_initcall(nec_osprey_setup); diff -urN linux/include/asm-mips/vr4181/irq.h linux/include/asm-mips/vr4181/irq.h --- linux/include/asm-mips/vr4181/Attic/irq.h 2005-06-03 14:08:06.404041000 +0100 1.2 +++ linux/include/asm-mips/vr4181/Attic/irq.h 1970/01/01 00:00:00+0100 @@ -1,122 +0,0 @@ -/* - * Macros for vr4181 IRQ numbers. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * Strategy: - * - * Vr4181 has conceptually three levels of interrupt controllers: - * 1. the CPU itself with 8 intr level. - * 2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs - * 3. GPIO interrupts : forwarding external interrupts to sys intr controller - */ - -/* decide the irq block assignment */ -#define VR4181_NUM_CPU_IRQ 8 -#define VR4181_NUM_SYS_IRQ 32 -#define VR4181_NUM_GPIO_IRQ 16 - -#define VR4181_IRQ_BASE 0 - -#define VR4181_CPU_IRQ_BASE VR4181_IRQ_BASE -#define VR4181_SYS_IRQ_BASE (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ) -#define VR4181_GPIO_IRQ_BASE (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ) - -/* CPU interrupts */ - -/* - IP0 - Software interrupt - IP1 - Software interrupt - IP2 - All but battery, high speed modem, and real time clock - IP3 - RTC Long1 (system timer) - IP4 - RTC Long2 - IP5 - High Speed Modem (unused on VR4181) - IP6 - Unused - IP7 - Timer interrupt from CPO_COMPARE -*/ - -#define VR4181_IRQ_SW1 (VR4181_CPU_IRQ_BASE + 0) -#define VR4181_IRQ_SW2 (VR4181_CPU_IRQ_BASE + 1) -#define VR4181_IRQ_INT0 (VR4181_CPU_IRQ_BASE + 2) -#define VR4181_IRQ_INT1 (VR4181_CPU_IRQ_BASE + 3) -#define VR4181_IRQ_INT2 (VR4181_CPU_IRQ_BASE + 4) -#define VR4181_IRQ_INT3 (VR4181_CPU_IRQ_BASE + 5) -#define VR4181_IRQ_INT4 (VR4181_CPU_IRQ_BASE + 6) -#define VR4181_IRQ_TIMER (VR4181_CPU_IRQ_BASE + 7) - - -/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */ - -/* - IP2 - same as VR4181_IRQ_INT1 - IP8 - This is a cascade to GPIO IRQ's. Do not use. - IP16 - same as VR4181_IRQ_INT2 - IP18 - CompactFlash -*/ - -#define VR4181_IRQ_BATTERY (VR4181_SYS_IRQ_BASE + 0) -#define VR4181_IRQ_POWER (VR4181_SYS_IRQ_BASE + 1) -#define VR4181_IRQ_RTCL1 (VR4181_SYS_IRQ_BASE + 2) -#define VR4181_IRQ_ETIMER (VR4181_SYS_IRQ_BASE + 3) -#define VR4181_IRQ_RFU12 (VR4181_SYS_IRQ_BASE + 4) -#define VR4181_IRQ_PIU (VR4181_SYS_IRQ_BASE + 5) -#define VR4181_IRQ_AIU (VR4181_SYS_IRQ_BASE + 6) -#define VR4181_IRQ_KIU (VR4181_SYS_IRQ_BASE + 7) -#define VR4181_IRQ_GIU (VR4181_SYS_IRQ_BASE + 8) -#define VR4181_IRQ_SIU (VR4181_SYS_IRQ_BASE + 9) -#define VR4181_IRQ_RFU18 (VR4181_SYS_IRQ_BASE + 10) -#define VR4181_IRQ_SOFT (VR4181_SYS_IRQ_BASE + 11) -#define VR4181_IRQ_RFU20 (VR4181_SYS_IRQ_BASE + 12) -#define VR4181_IRQ_DOZEPIU (VR4181_SYS_IRQ_BASE + 13) -#define VR4181_IRQ_RFU22 (VR4181_SYS_IRQ_BASE + 14) -#define VR4181_IRQ_RFU23 (VR4181_SYS_IRQ_BASE + 15) -#define VR4181_IRQ_RTCL2 (VR4181_SYS_IRQ_BASE + 16) -#define VR4181_IRQ_LED (VR4181_SYS_IRQ_BASE + 17) -#define VR4181_IRQ_ECU (VR4181_SYS_IRQ_BASE + 18) -#define VR4181_IRQ_CSU (VR4181_SYS_IRQ_BASE + 19) -#define VR4181_IRQ_USB (VR4181_SYS_IRQ_BASE + 20) -#define VR4181_IRQ_DMA (VR4181_SYS_IRQ_BASE + 21) -#define VR4181_IRQ_LCD (VR4181_SYS_IRQ_BASE + 22) -#define VR4181_IRQ_RFU31 (VR4181_SYS_IRQ_BASE + 23) -#define VR4181_IRQ_RFU32 (VR4181_SYS_IRQ_BASE + 24) -#define VR4181_IRQ_RFU33 (VR4181_SYS_IRQ_BASE + 25) -#define VR4181_IRQ_RFU34 (VR4181_SYS_IRQ_BASE + 26) -#define VR4181_IRQ_RFU35 (VR4181_SYS_IRQ_BASE + 27) -#define VR4181_IRQ_RFU36 (VR4181_SYS_IRQ_BASE + 28) -#define VR4181_IRQ_RFU37 (VR4181_SYS_IRQ_BASE + 29) -#define VR4181_IRQ_RFU38 (VR4181_SYS_IRQ_BASE + 30) -#define VR4181_IRQ_RFU39 (VR4181_SYS_IRQ_BASE + 31) - -/* Cascaded from VR4181_IRQ_GIU */ -#define VR4181_IRQ_GPIO0 (VR4181_GPIO_IRQ_BASE + 0) -#define VR4181_IRQ_GPIO1 (VR4181_GPIO_IRQ_BASE + 1) -#define VR4181_IRQ_GPIO2 (VR4181_GPIO_IRQ_BASE + 2) -#define VR4181_IRQ_GPIO3 (VR4181_GPIO_IRQ_BASE + 3) -#define VR4181_IRQ_GPIO4 (VR4181_GPIO_IRQ_BASE + 4) -#define VR4181_IRQ_GPIO5 (VR4181_GPIO_IRQ_BASE + 5) -#define VR4181_IRQ_GPIO6 (VR4181_GPIO_IRQ_BASE + 6) -#define VR4181_IRQ_GPIO7 (VR4181_GPIO_IRQ_BASE + 7) -#define VR4181_IRQ_GPIO8 (VR4181_GPIO_IRQ_BASE + 8) -#define VR4181_IRQ_GPIO9 (VR4181_GPIO_IRQ_BASE + 9) -#define VR4181_IRQ_GPIO10 (VR4181_GPIO_IRQ_BASE + 10) -#define VR4181_IRQ_GPIO11 (VR4181_GPIO_IRQ_BASE + 11) -#define VR4181_IRQ_GPIO12 (VR4181_GPIO_IRQ_BASE + 12) -#define VR4181_IRQ_GPIO13 (VR4181_GPIO_IRQ_BASE + 13) -#define VR4181_IRQ_GPIO14 (VR4181_GPIO_IRQ_BASE + 14) -#define VR4181_IRQ_GPIO15 (VR4181_GPIO_IRQ_BASE + 15) - - -// Alternative to above GPIO IRQ defines -#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin)) - -#define VR4181_IRQ_MAX (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \ - VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ) diff -urN linux/include/asm-mips/vr4181/vr4181.h linux/include/asm-mips/vr4181/vr4181.h --- linux/include/asm-mips/vr4181/Attic/vr4181.h 2005-06-03 14:08:06.421067000 +0100 1.3 +++ linux/include/asm-mips/vr4181/Attic/vr4181.h 1970/01/01 00:00:00+0100 @@ -1,413 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 by Michael Klar - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - */ -#ifndef __ASM_VR4181_VR4181_H -#define __ASM_VR4181_VR4181_H - -#include - -#include - -#ifndef __ASSEMBLY__ -#define __preg8 (volatile unsigned char*) -#define __preg16 (volatile unsigned short*) -#define __preg32 (volatile unsigned int*) -#else -#define __preg8 -#define __preg16 -#define __preg32 -#endif - -// Embedded CPU peripheral registers -// Note that many of the registers have different physical address for VR4181 - -// Bus Control Unit (BCU) -#define VR4181_BCUCNTREG1 __preg16(KSEG1 + 0x0A000000) /* BCU control register 1 (R/W) */ -#define VR4181_CMUCLKMSK __preg16(KSEG1 + 0x0A000004) /* Clock mask register (R/W) */ -#define VR4181_CMUCLKMSK_MSKCSUPCLK 0x0040 -#define VR4181_CMUCLKMSK_MSKAIUPCLK 0x0020 -#define VR4181_CMUCLKMSK_MSKPIUPCLK 0x0010 -#define VR4181_CMUCLKMSK_MSKADUPCLK 0x0008 -#define VR4181_CMUCLKMSK_MSKSIU18M 0x0004 -#define VR4181_CMUCLKMSK_MSKADU18M 0x0002 -#define VR4181_CMUCLKMSK_MSKUSB 0x0001 -#define VR4181_CMUCLKMSK_MSKSIU VR4181_CMUCLKMSK_MSKSIU18M -#define VR4181_BCUSPEEDREG __preg16(KSEG1 + 0x0A00000C) /* BCU access time parameter (R/W) */ -#define VR4181_BCURFCNTREG __preg16(KSEG1 + 0x0A000010) /* BCU refresh control register (R/W) */ -#define VR4181_REVIDREG __preg16(KSEG1 + 0x0A000014) /* Revision ID register (R) */ -#define VR4181_CLKSPEEDREG __preg16(KSEG1 + 0x0A000018) /* Clock speed register (R) */ -#define VR4181_EDOMCYTREG __preg16(KSEG1 + 0x0A000300) /* Memory cycle timing register (R/W) */ -#define VR4181_MEMCFG_REG __preg16(KSEG1 + 0x0A000304) /* Memory configuration register (R/W) */ -#define VR4181_MODE_REG __preg16(KSEG1 + 0x0A000308) /* SDRAM mode register (R/W) */ -#define VR4181_SDTIMINGREG __preg16(KSEG1 + 0x0A00030C) /* SDRAM timing register (R/W) */ - -// DMA Control Unit (DCU) -#define VR4181_MICDEST1REG1 __preg16(KSEG1 + 0x0A000020) /* Microphone destination 1 address register 1 (R/W) */ -#define VR4181_MICDEST1REG2 __preg16(KSEG1 + 0x0A000022) /* Microphone destination 1 address register 2 (R/W) */ -#define VR4181_MICDEST2REG1 __preg16(KSEG1 + 0x0A000024) /* Microphone destination 2 address register 1 (R/W) */ -#define VR4181_MICDEST2REG2 __preg16(KSEG1 + 0x0A000026) /* Microphone destination 2 address register 2 (R/W) */ -#define VR4181_SPKRRC1REG1 __preg16(KSEG1 + 0x0A000028) /* Speaker Source 1 address register 1 (R/W) */ -#define VR4181_SPKRRC1REG2 __preg16(KSEG1 + 0x0A00002A) /* Speaker Source 1 address register 2 (R/W) */ -#define VR4181_SPKRRC2REG1 __preg16(KSEG1 + 0x0A00002C) /* Speaker Source 2 address register 1 (R/W) */ -#define VR4181_SPKRRC2REG2 __preg16(KSEG1 + 0x0A00002E) /* Speaker Source 2 address register 2 (R/W) */ -#define VR4181_DMARSTREG __preg16(KSEG1 + 0x0A000040) /* DMA Reset register (R/W) */ -#define VR4181_AIUDMAMSKREG __preg16(KSEG1 + 0x0A000046) /* Audio DMA mask register (R/W) */ -#define VR4181_USBDMAMSKREG __preg16(KSEG1 + 0x0A000600) /* USB DMA Mask register (R/W) */ -#define VR4181_USBRXS1AREG1 __preg16(KSEG1 + 0x0A000602) /* USB Rx source 1 address register 1 (R/W) */ -#define VR4181_USBRXS1AREG2 __preg16(KSEG1 + 0x0A000604) /* USB Rx source 1 address register 2 (R/W) */ -#define VR4181_USBRXS2AREG1 __preg16(KSEG1 + 0x0A000606) /* USB Rx source 2 address register 1 (R/W) */ -#define VR4181_USBRXS2AREG2 __preg16(KSEG1 + 0x0A000608) /* USB Rx source 2 address register 2 (R/W) */ -#define VR4181_USBTXS1AREG1 __preg16(KSEG1 + 0x0A00060A) /* USB Tx source 1 address register 1 (R/W) */ -#define VR4181_USBTXS1AREG2 __preg16(KSEG1 + 0x0A00060C) /* USB Tx source 1 address register 2 (R/W) */ -#define VR4181_USBTXS2AREG1 __preg16(KSEG1 + 0x0A00060E) /* USB Tx source 2 address register 1 (R/W) */ -#define VR4181_USBTXS2AREG2 __preg16(KSEG1 + 0x0A000610) /* USB Tx source 2 address register 2 (R/W) */ -#define VR4181_USBRXD1AREG1 __preg16(KSEG1 + 0x0A00062A) /* USB Rx destination 1 address register 1 (R/W) */ -#define VR4181_USBRXD1AREG2 __preg16(KSEG1 + 0x0A00062C) /* USB Rx destination 1 address register 2 (R/W) */ -#define VR4181_USBRXD2AREG1 __preg16(KSEG1 + 0x0A00062E) /* USB Rx destination 2 address register 1 (R/W) */ -#define VR4181_USBRXD2AREG2 __preg16(KSEG1 + 0x0A000630) /* USB Rx destination 2 address register 2 (R/W) */ -#define VR4181_USBTXD1AREG1 __preg16(KSEG1 + 0x0A000632) /* USB Tx destination 1 address register 1 (R/W) */ -#define VR4181_USBTXD1AREG2 __preg16(KSEG1 + 0x0A000634) /* USB Tx destination 1 address register 2 (R/W) */ -#define VR4181_USBTXD2AREG1 __preg16(KSEG1 + 0x0A000636) /* USB Tx destination 2 address register 1 (R/W) */ -#define VR4181_USBTXD2AREG2 __preg16(KSEG1 + 0x0A000638) /* USB Tx destination 2 address register 2 (R/W) */ -#define VR4181_RxRCLENREG __preg16(KSEG1 + 0x0A000652) /* USB Rx record length register (R/W) */ -#define VR4181_TxRCLENREG __preg16(KSEG1 + 0x0A000654) /* USB Tx record length register (R/W) */ -#define VR4181_MICRCLENREG __preg16(KSEG1 + 0x0A000658) /* Microphone record length register (R/W) */ -#define VR4181_SPKRCLENREG __preg16(KSEG1 + 0x0A00065A) /* Speaker record length register (R/W) */ -#define VR4181_USBCFGREG __preg16(KSEG1 + 0x0A00065C) /* USB configuration register (R/W) */ -#define VR4181_MICDMACFGREG __preg16(KSEG1 + 0x0A00065E) /* Microphone DMA configuration register (R/W) */ -#define VR4181_SPKDMACFGREG __preg16(KSEG1 + 0x0A000660) /* Speaker DMA configuration register (R/W) */ -#define VR4181_DMAITRQREG __preg16(KSEG1 + 0x0A000662) /* DMA interrupt request register (R/W) */ -#define VR4181_DMACLTREG __preg16(KSEG1 + 0x0A000664) /* DMA control register (R/W) */ -#define VR4181_DMAITMKREG __preg16(KSEG1 + 0x0A000666) /* DMA interrupt mask register (R/W) */ - -// ISA Bridge -#define VR4181_ISABRGCTL __preg16(KSEG1 + 0x0B0002C0) /* ISA Bridge Control Register (R/W) */ -#define VR4181_ISABRGSTS __preg16(KSEG1 + 0x0B0002C2) /* ISA Bridge Status Register (R/W) */ -#define VR4181_XISACTL __preg16(KSEG1 + 0x0B0002C4) /* External ISA Control Register (R/W) */ - -// Clocked Serial Interface (CSI) -#define VR4181_CSIMODE __preg16(KSEG1 + 0x0B000900) /* CSI Mode Register (R/W) */ -#define VR4181_CSIRXDATA __preg16(KSEG1 + 0x0B000902) /* CSI Receive Data Register (R) */ -#define VR4181_CSITXDATA __preg16(KSEG1 + 0x0B000904) /* CSI Transmit Data Register (R/W) */ -#define VR4181_CSILSTAT __preg16(KSEG1 + 0x0B000906) /* CSI Line Status Register (R/W) */ -#define VR4181_CSIINTMSK __preg16(KSEG1 + 0x0B000908) /* CSI Interrupt Mask Register (R/W) */ -#define VR4181_CSIINTSTAT __preg16(KSEG1 + 0x0B00090a) /* CSI Interrupt Status Register (R/W) */ -#define VR4181_CSITXBLEN __preg16(KSEG1 + 0x0B00090c) /* CSI Transmit Burst Length Register (R/W) */ -#define VR4181_CSIRXBLEN __preg16(KSEG1 + 0x0B00090e) /* CSI Receive Burst Length Register (R/W) */ - -// Interrupt Control Unit (ICU) -#define VR4181_SYSINT1REG __preg16(KSEG1 + 0x0A000080) /* Level 1 System interrupt register 1 (R) */ -#define VR4181_MSYSINT1REG __preg16(KSEG1 + 0x0A00008C) /* Level 1 mask system interrupt register 1 (R/W) */ -#define VR4181_NMIREG __preg16(KSEG1 + 0x0A000098) /* NMI register (R/W) */ -#define VR4181_SOFTINTREG __preg16(KSEG1 + 0x0A00009A) /* Software interrupt register (R/W) */ -#define VR4181_SYSINT2REG __preg16(KSEG1 + 0x0A000200) /* Level 1 System interrupt register 2 (R) */ -#define VR4181_MSYSINT2REG __preg16(KSEG1 + 0x0A000206) /* Level 1 mask system interrupt register 2 (R/W) */ -#define VR4181_PIUINTREGro __preg16(KSEG1 + 0x0B000082) /* Level 2 PIU interrupt register (R) */ -#define VR4181_AIUINTREG __preg16(KSEG1 + 0x0B000084) /* Level 2 AIU interrupt register (R) */ -#define VR4181_MPIUINTREG __preg16(KSEG1 + 0x0B00008E) /* Level 2 mask PIU interrupt register (R/W) */ -#define VR4181_MAIUINTREG __preg16(KSEG1 + 0x0B000090) /* Level 2 mask AIU interrupt register (R/W) */ -#define VR4181_MKIUINTREG __preg16(KSEG1 + 0x0B000092) /* Level 2 mask KIU interrupt register (R/W) */ -#define VR4181_KIUINTREG __preg16(KSEG1 + 0x0B000198) /* Level 2 KIU interrupt register (R) */ - -// Power Management Unit (PMU) -#define VR4181_PMUINTREG __preg16(KSEG1 + 0x0B0000A0) /* PMU Status Register (R/W) */ -#define VR4181_PMUINT_POWERSW 0x1 /* Power switch */ -#define VR4181_PMUINT_BATT 0x2 /* Low batt during normal operation */ -#define VR4181_PMUINT_DEADMAN 0x4 /* Deadman's switch */ -#define VR4181_PMUINT_RESET 0x8 /* Reset switch */ -#define VR4181_PMUINT_RTCRESET 0x10 /* RTC Reset */ -#define VR4181_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */ -#define VR4181_PMUINT_BATTLOW 0x100 /* Battery low */ -#define VR4181_PMUINT_RTC 0x200 /* RTC Alarm */ -#define VR4181_PMUINT_DCD 0x400 /* DCD# */ -#define VR4181_PMUINT_GPIO0 0x1000 /* GPIO0 */ -#define VR4181_PMUINT_GPIO1 0x2000 /* GPIO1 */ -#define VR4181_PMUINT_GPIO2 0x4000 /* GPIO2 */ -#define VR4181_PMUINT_GPIO3 0x8000 /* GPIO3 */ - -#define VR4181_PMUCNTREG __preg16(KSEG1 + 0x0B0000A2) /* PMU Control Register (R/W) */ -#define VR4181_PMUWAITREG __preg16(KSEG1 + 0x0B0000A8) /* PMU Wait Counter Register (R/W) */ -#define VR4181_PMUDIVREG __preg16(KSEG1 + 0x0B0000AC) /* PMU Divide Mode Register (R/W) */ -#define VR4181_DRAMHIBCTL __preg16(KSEG1 + 0x0B0000B2) /* DRAM Hibernate Control Register (R/W) */ - -// Real Time Clock Unit (RTC) -#define VR4181_ETIMELREG __preg16(KSEG1 + 0x0B0000C0) /* Elapsed Time L Register (R/W) */ -#define VR4181_ETIMEMREG __preg16(KSEG1 + 0x0B0000C2) /* Elapsed Time M Register (R/W) */ -#define VR4181_ETIMEHREG __preg16(KSEG1 + 0x0B0000C4) /* Elapsed Time H Register (R/W) */ -#define VR4181_ECMPLREG __preg16(KSEG1 + 0x0B0000C8) /* Elapsed Compare L Register (R/W) */ -#define VR4181_ECMPMREG __preg16(KSEG1 + 0x0B0000CA) /* Elapsed Compare M Register (R/W) */ -#define VR4181_ECMPHREG __preg16(KSEG1 + 0x0B0000CC) /* Elapsed Compare H Register (R/W) */ -#define VR4181_RTCL1LREG __preg16(KSEG1 + 0x0B0000D0) /* RTC Long 1 L Register (R/W) */ -#define VR4181_RTCL1HREG __preg16(KSEG1 + 0x0B0000D2) /* RTC Long 1 H Register (R/W) */ -#define VR4181_RTCL1CNTLREG __preg16(KSEG1 + 0x0B0000D4) /* RTC Long 1 Count L Register (R) */ -#define VR4181_RTCL1CNTHREG __preg16(KSEG1 + 0x0B0000D6) /* RTC Long 1 Count H Register (R) */ -#define VR4181_RTCL2LREG __preg16(KSEG1 + 0x0B0000D8) /* RTC Long 2 L Register (R/W) */ -#define VR4181_RTCL2HREG __preg16(KSEG1 + 0x0B0000DA) /* RTC Long 2 H Register (R/W) */ -#define VR4181_RTCL2CNTLREG __preg16(KSEG1 + 0x0B0000DC) /* RTC Long 2 Count L Register (R) */ -#define VR4181_RTCL2CNTHREG __preg16(KSEG1 + 0x0B0000DE) /* RTC Long 2 Count H Register (R) */ -#define VR4181_RTCINTREG __preg16(KSEG1 + 0x0B0001DE) /* RTC Interrupt Register (R/W) */ - -// Deadman's Switch Unit (DSU) -#define VR4181_DSUCNTREG __preg16(KSEG1 + 0x0B0000E0) /* DSU Control Register (R/W) */ -#define VR4181_DSUSETREG __preg16(KSEG1 + 0x0B0000E2) /* DSU Dead Time Set Register (R/W) */ -#define VR4181_DSUCLRREG __preg16(KSEG1 + 0x0B0000E4) /* DSU Clear Register (W) */ -#define VR4181_DSUTIMREG __preg16(KSEG1 + 0x0B0000E6) /* DSU Elapsed Time Register (R/W) */ - -// General Purpose I/O Unit (GIU) -#define VR4181_GPMD0REG __preg16(KSEG1 + 0x0B000300) /* GPIO Mode 0 Register (R/W) */ -#define VR4181_GPMD1REG __preg16(KSEG1 + 0x0B000302) /* GPIO Mode 1 Register (R/W) */ -#define VR4181_GPMD2REG __preg16(KSEG1 + 0x0B000304) /* GPIO Mode 2 Register (R/W) */ -#define VR4181_GPMD3REG __preg16(KSEG1 + 0x0B000306) /* GPIO Mode 3 Register (R/W) */ -#define VR4181_GPDATHREG __preg16(KSEG1 + 0x0B000308) /* GPIO Data High Register (R/W) */ -#define VR4181_GPDATHREG_GPIO16 0x0001 -#define VR4181_GPDATHREG_GPIO17 0x0002 -#define VR4181_GPDATHREG_GPIO18 0x0004 -#define VR4181_GPDATHREG_GPIO19 0x0008 -#define VR4181_GPDATHREG_GPIO20 0x0010 -#define VR4181_GPDATHREG_GPIO21 0x0020 -#define VR4181_GPDATHREG_GPIO22 0x0040 -#define VR4181_GPDATHREG_GPIO23 0x0080 -#define VR4181_GPDATHREG_GPIO24 0x0100 -#define VR4181_GPDATHREG_GPIO25 0x0200 -#define VR4181_GPDATHREG_GPIO26 0x0400 -#define VR4181_GPDATHREG_GPIO27 0x0800 -#define VR4181_GPDATHREG_GPIO28 0x1000 -#define VR4181_GPDATHREG_GPIO29 0x2000 -#define VR4181_GPDATHREG_GPIO30 0x4000 -#define VR4181_GPDATHREG_GPIO31 0x8000 -#define VR4181_GPDATLREG __preg16(KSEG1 + 0x0B00030A) /* GPIO Data Low Register (R/W) */ -#define VR4181_GPDATLREG_GPIO0 0x0001 -#define VR4181_GPDATLREG_GPIO1 0x0002 -#define VR4181_GPDATLREG_GPIO2 0x0004 -#define VR4181_GPDATLREG_GPIO3 0x0008 -#define VR4181_GPDATLREG_GPIO4 0x0010 -#define VR4181_GPDATLREG_GPIO5 0x0020 -#define VR4181_GPDATLREG_GPIO6 0x0040 -#define VR4181_GPDATLREG_GPIO7 0x0080 -#define VR4181_GPDATLREG_GPIO8 0x0100 -#define VR4181_GPDATLREG_GPIO9 0x0200 -#define VR4181_GPDATLREG_GPIO10 0x0400 -#define VR4181_GPDATLREG_GPIO11 0x0800 -#define VR4181_GPDATLREG_GPIO12 0x1000 -#define VR4181_GPDATLREG_GPIO13 0x2000 -#define VR4181_GPDATLREG_GPIO14 0x4000 -#define VR4181_GPDATLREG_GPIO15 0x8000 -#define VR4181_GPINTEN __preg16(KSEG1 + 0x0B00030C) /* GPIO Interrupt Enable Register (R/W) */ -#define VR4181_GPINTMSK __preg16(KSEG1 + 0x0B00030E) /* GPIO Interrupt Mask Register (R/W) */ -#define VR4181_GPINTTYPH __preg16(KSEG1 + 0x0B000310) /* GPIO Interrupt Type High Register (R/W) */ -#define VR4181_GPINTTYPL __preg16(KSEG1 + 0x0B000312) /* GPIO Interrupt Type Low Register (R/W) */ -#define VR4181_GPINTSTAT __preg16(KSEG1 + 0x0B000314) /* GPIO Interrupt Status Register (R/W) */ -#define VR4181_GPHIBSTH __preg16(KSEG1 + 0x0B000316) /* GPIO Hibernate Pin State High Register (R/W) */ -#define VR4181_GPHIBSTL __preg16(KSEG1 + 0x0B000318) /* GPIO Hibernate Pin State Low Register (R/W) */ -#define VR4181_GPSICTL __preg16(KSEG1 + 0x0B00031A) /* GPIO Serial Interface Control Register (R/W) */ -#define VR4181_KEYEN __preg16(KSEG1 + 0x0B00031C) /* Keyboard Scan Pin Enable Register (R/W) */ -#define VR4181_PCS0STRA __preg16(KSEG1 + 0x0B000320) /* Programmable Chip Select [0] Start Address Register (R/W) */ -#define VR4181_PCS0STPA __preg16(KSEG1 + 0x0B000322) /* Programmable Chip Select [0] Stop Address Register (R/W) */ -#define VR4181_PCS0HIA __preg16(KSEG1 + 0x0B000324) /* Programmable Chip Select [0] High Address Register (R/W) */ -#define VR4181_PCS1STRA __preg16(KSEG1 + 0x0B000326) /* Programmable Chip Select [1] Start Address Register (R/W) */ -#define VR4181_PCS1STPA __preg16(KSEG1 + 0x0B000328) /* Programmable Chip Select [1] Stop Address Register (R/W) */ -#define VR4181_PCS1HIA __preg16(KSEG1 + 0x0B00032A) /* Programmable Chip Select [1] High Address Register (R/W) */ -#define VR4181_PCSMODE __preg16(KSEG1 + 0x0B00032C) /* Programmable Chip Select Mode Register (R/W) */ -#define VR4181_LCDGPMODE __preg16(KSEG1 + 0x0B00032E) /* LCD General Purpose Mode Register (R/W) */ -#define VR4181_MISCREG0 __preg16(KSEG1 + 0x0B000330) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG1 __preg16(KSEG1 + 0x0B000332) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG2 __preg16(KSEG1 + 0x0B000334) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG3 __preg16(KSEG1 + 0x0B000336) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG4 __preg16(KSEG1 + 0x0B000338) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG5 __preg16(KSEG1 + 0x0B00033A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG6 __preg16(KSEG1 + 0x0B00033C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG7 __preg16(KSEG1 + 0x0B00033D) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG8 __preg16(KSEG1 + 0x0B000340) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG9 __preg16(KSEG1 + 0x0B000342) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG10 __preg16(KSEG1 + 0x0B000344) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG11 __preg16(KSEG1 + 0x0B000346) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG12 __preg16(KSEG1 + 0x0B000348) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG13 __preg16(KSEG1 + 0x0B00034A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG14 __preg16(KSEG1 + 0x0B00034C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG15 __preg16(KSEG1 + 0x0B00034E) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_SECIRQMASKL VR4181_GPINTEN -// No SECIRQMASKH for VR4181 - -// Touch Panel Interface Unit (PIU) -#define VR4181_PIUCNTREG __preg16(KSEG1 + 0x0B000122) /* PIU Control register (R/W) */ -#define VR4181_PIUCNTREG_PIUSEQEN 0x0004 -#define VR4181_PIUCNTREG_PIUPWR 0x0002 -#define VR4181_PIUCNTREG_PADRST 0x0001 - -#define VR4181_PIUINTREG __preg16(KSEG1 + 0x0B000124) /* PIU Interrupt cause register (R/W) */ -#define VR4181_PIUINTREG_OVP 0x8000 -#define VR4181_PIUINTREG_PADCMD 0x0040 -#define VR4181_PIUINTREG_PADADP 0x0020 -#define VR4181_PIUINTREG_PADPAGE1 0x0010 -#define VR4181_PIUINTREG_PADPAGE0 0x0008 -#define VR4181_PIUINTREG_PADDLOST 0x0004 -#define VR4181_PIUINTREG_PENCHG 0x0001 - -#define VR4181_PIUSIVLREG __preg16(KSEG1 + 0x0B000126) /* PIU Data sampling interval register (R/W) */ -#define VR4181_PIUSTBLREG __preg16(KSEG1 + 0x0B000128) /* PIU A/D converter start delay register (R/W) */ -#define VR4181_PIUCMDREG __preg16(KSEG1 + 0x0B00012A) /* PIU A/D command register (R/W) */ -#define VR4181_PIUASCNREG __preg16(KSEG1 + 0x0B000130) /* PIU A/D port scan register (R/W) */ -#define VR4181_PIUAMSKREG __preg16(KSEG1 + 0x0B000132) /* PIU A/D scan mask register (R/W) */ -#define VR4181_PIUCIVLREG __preg16(KSEG1 + 0x0B00013E) /* PIU Check interval register (R) */ -#define VR4181_PIUPB00REG __preg16(KSEG1 + 0x0B0002A0) /* PIU Page 0 Buffer 0 register (R/W) */ -#define VR4181_PIUPB01REG __preg16(KSEG1 + 0x0B0002A2) /* PIU Page 0 Buffer 1 register (R/W) */ -#define VR4181_PIUPB02REG __preg16(KSEG1 + 0x0B0002A4) /* PIU Page 0 Buffer 2 register (R/W) */ -#define VR4181_PIUPB03REG __preg16(KSEG1 + 0x0B0002A6) /* PIU Page 0 Buffer 3 register (R/W) */ -#define VR4181_PIUPB10REG __preg16(KSEG1 + 0x0B0002A8) /* PIU Page 1 Buffer 0 register (R/W) */ -#define VR4181_PIUPB11REG __preg16(KSEG1 + 0x0B0002AA) /* PIU Page 1 Buffer 1 register (R/W) */ -#define VR4181_PIUPB12REG __preg16(KSEG1 + 0x0B0002AC) /* PIU Page 1 Buffer 2 register (R/W) */ -#define VR4181_PIUPB13REG __preg16(KSEG1 + 0x0B0002AE) /* PIU Page 1 Buffer 3 register (R/W) */ -#define VR4181_PIUAB0REG __preg16(KSEG1 + 0x0B0002B0) /* PIU A/D scan Buffer 0 register (R/W) */ -#define VR4181_PIUAB1REG __preg16(KSEG1 + 0x0B0002B2) /* PIU A/D scan Buffer 1 register (R/W) */ -#define VR4181_PIUAB2REG __preg16(KSEG1 + 0x0B0002B4) /* PIU A/D scan Buffer 2 register (R/W) */ -#define VR4181_PIUAB3REG __preg16(KSEG1 + 0x0B0002B6) /* PIU A/D scan Buffer 3 register (R/W) */ -#define VR4181_PIUPB04REG __preg16(KSEG1 + 0x0B0002BC) /* PIU Page 0 Buffer 4 register (R/W) */ -#define VR4181_PIUPB14REG __preg16(KSEG1 + 0x0B0002BE) /* PIU Page 1 Buffer 4 register (R/W) */ - -// Audio Interface Unit (AIU) -#define VR4181_SODATREG __preg16(KSEG1 + 0x0B000166) /* Speaker Output Data Register (R/W) */ -#define VR4181_SCNTREG __preg16(KSEG1 + 0x0B000168) /* Speaker Output Control Register (R/W) */ -#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Mike Input Data Register (R/W) */ -#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Mike Input Control Register (R/W) */ -#define VR4181_DVALIDREG __preg16(KSEG1 + 0x0B000178) /* Data Valid Register (R/W) */ -#define VR4181_SEQREG __preg16(KSEG1 + 0x0B00017A) /* Sequential Register (R/W) */ -#define VR4181_INTREG __preg16(KSEG1 + 0x0B00017C) /* Interrupt Register (R/W) */ -#define VR4181_SDMADATREG __preg16(KSEG1 + 0x0B000160) /* Speaker DMA Data Register (R/W) */ -#define VR4181_MDMADATREG __preg16(KSEG1 + 0x0B000162) /* Microphone DMA Data Register (R/W) */ -#define VR4181_DAVREF_SETUP __preg16(KSEG1 + 0x0B000164) /* DAC Vref setup register (R/W) */ -#define VR4181_SCNVC_END __preg16(KSEG1 + 0x0B00016E) /* Speaker sample rate control (R/W) */ -#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Microphone Input Data Register (R/W) */ -#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Microphone Input Control Register (R/W) */ -#define VR4181_MCNVC_END __preg16(KSEG1 + 0x0B00017E) /* Microphone sample rate control (R/W) */ - -// Keyboard Interface Unit (KIU) -#define VR4181_KIUDAT0 __preg16(KSEG1 + 0x0B000180) /* KIU Data0 Register (R/W) */ -#define VR4181_KIUDAT1 __preg16(KSEG1 + 0x0B000182) /* KIU Data1 Register (R/W) */ -#define VR4181_KIUDAT2 __preg16(KSEG1 + 0x0B000184) /* KIU Data2 Register (R/W) */ -#define VR4181_KIUDAT3 __preg16(KSEG1 + 0x0B000186) /* KIU Data3 Register (R/W) */ -#define VR4181_KIUDAT4 __preg16(KSEG1 + 0x0B000188) /* KIU Data4 Register (R/W) */ -#define VR4181_KIUDAT5 __preg16(KSEG1 + 0x0B00018A) /* KIU Data5 Register (R/W) */ -#define VR4181_KIUSCANREP __preg16(KSEG1 + 0x0B000190) /* KIU Scan/Repeat Register (R/W) */ -#define VR4181_KIUSCANREP_KEYEN 0x8000 -#define VR4181_KIUSCANREP_SCANSTP 0x0008 -#define VR4181_KIUSCANREP_SCANSTART 0x0004 -#define VR4181_KIUSCANREP_ATSTP 0x0002 -#define VR4181_KIUSCANREP_ATSCAN 0x0001 -#define VR4181_KIUSCANS __preg16(KSEG1 + 0x0B000192) /* KIU Scan Status Register (R) */ -#define VR4181_KIUWKS __preg16(KSEG1 + 0x0B000194) /* KIU Wait Keyscan Stable Register (R/W) */ -#define VR4181_KIUWKI __preg16(KSEG1 + 0x0B000196) /* KIU Wait Keyscan Interval Register (R/W) */ -#define VR4181_KIUINT __preg16(KSEG1 + 0x0B000198) /* KIU Interrupt Register (R/W) */ -#define VR4181_KIUINT_KDATLOST 0x0004 -#define VR4181_KIUINT_KDATRDY 0x0002 -#define VR4181_KIUINT_SCANINT 0x0001 -#define VR4181_KIUDAT6 __preg16(KSEG1 + 0x0B00018C) /* Scan Line 6 Key Data Register (R) */ -#define VR4181_KIUDAT7 __preg16(KSEG1 + 0x0B00018E) /* Scan Line 7 Key Data Register (R) */ - -// CompactFlash Controller -#define VR4181_PCCARDINDEX __preg8(KSEG1 + 0x0B0008E0) /* PC Card Controller Index Register */ -#define VR4181_PCCARDDATA __preg8(KSEG1 + 0x0B0008E1) /* PC Card Controller Data Register */ -#define VR4181_INTSTATREG __preg16(KSEG1 + 0x0B0008F8) /* Interrupt Status Register (R/W) */ -#define VR4181_INTMSKREG __preg16(KSEG1 + 0x0B0008FA) /* Interrupt Mask Register (R/W) */ -#define VR4181_CFG_REG_1 __preg16(KSEG1 + 0x0B0008FE) /* Configuration Register 1 */ - -// LED Control Unit (LED) -#define VR4181_LEDHTSREG __preg16(KSEG1 + 0x0B000240) /* LED H Time Set register (R/W) */ -#define VR4181_LEDLTSREG __preg16(KSEG1 + 0x0B000242) /* LED L Time Set register (R/W) */ -#define VR4181_LEDCNTREG __preg16(KSEG1 + 0x0B000248) /* LED Control register (R/W) */ -#define VR4181_LEDASTCREG __preg16(KSEG1 + 0x0B00024A) /* LED Auto Stop Time Count register (R/W) */ -#define VR4181_LEDINTREG __preg16(KSEG1 + 0x0B00024C) /* LED Interrupt register (R/W) */ - -// Serial Interface Unit (SIU / SIU1 and SIU2) -#define VR4181_SIURB __preg8(KSEG1 + 0x0C000010) /* Receiver Buffer Register (Read) DLAB = 0 (R) */ -#define VR4181_SIUTH __preg8(KSEG1 + 0x0C000010) /* Transmitter Holding Register (Write) DLAB = 0 (W) */ -#define VR4181_SIUDLL __preg8(KSEG1 + 0x0C000010) /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */ -#define VR4181_SIUIE __preg8(KSEG1 + 0x0C000011) /* Interrupt Enable DLAB = 0 (R/W) */ -#define VR4181_SIUDLM __preg8(KSEG1 + 0x0C000011) /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */ -#define VR4181_SIUIID __preg8(KSEG1 + 0x0C000012) /* Interrupt Identification Register (Read) (R) */ -#define VR4181_SIUFC __preg8(KSEG1 + 0x0C000012) /* FIFO Control Register (Write) (W) */ -#define VR4181_SIULC __preg8(KSEG1 + 0x0C000013) /* Line Control Register (R/W) */ -#define VR4181_SIUMC __preg8(KSEG1 + 0x0C000014) /* MODEM Control Register (R/W) */ -#define VR4181_SIULS __preg8(KSEG1 + 0x0C000015) /* Line Status Register (R/W) */ -#define VR4181_SIUMS __preg8(KSEG1 + 0x0C000016) /* MODEM Status Register (R/W) */ -#define VR4181_SIUSC __preg8(KSEG1 + 0x0C000017) /* Scratch Register (R/W) */ -#define VR4181_SIURESET __preg8(KSEG1 + 0x0C000019) /* SIU Reset Register (R/W) */ -#define VR4181_SIUACTMSK __preg8(KSEG1 + 0x0C00001C) /* SIU Activity Mask (R/W) */ -#define VR4181_SIUACTTMR __preg8(KSEG1 + 0x0C00001E) /* SIU Activity Timer (R/W) */ -#define VR4181_SIURB_2 __preg8(KSEG1 + 0x0C000000) /* Receive Buffer Register (Read) (R) */ -#define VR4181_SIUTH_2 __preg8(KSEG1 + 0x0C000000) /* Transmitter Holding Register (Write) (W) */ -#define VR4181_SIUDLL_2 __preg8(KSEG1 + 0x0C000000) /* Divisor Latch (Least Significant Byte) (R/W) */ -#define VR4181_SIUIE_2 __preg8(KSEG1 + 0x0C000001) /* Interrupt Enable (DLAB = 0) (R/W) */ -#define VR4181_SIUDLM_2 __preg8(KSEG1 + 0x0C000001) /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */ -#define VR4181_SIUIID_2 __preg8(KSEG1 + 0x0C000002) /* Interrupt Identification Register (Read) (R) */ -#define VR4181_SIUFC_2 __preg8(KSEG1 + 0x0C000002) /* FIFO Control Register (Write) (W) */ -#define VR4181_SIULC_2 __preg8(KSEG1 + 0x0C000003) /* Line Control Register (R/W) */ -#define VR4181_SIUMC_2 __preg8(KSEG1 + 0x0C000004) /* Modem Control Register (R/W) */ -#define VR4181_SIULS_2 __preg8(KSEG1 + 0x0C000005) /* Line Status Register (R/W) */ -#define VR4181_SIUMS_2 __preg8(KSEG1 + 0x0C000006) /* Modem Status Register (R/W) */ -#define VR4181_SIUSC_2 __preg8(KSEG1 + 0x0C000007) /* Scratch Register (R/W) */ -#define VR4181_SIUIRSEL_2 __preg8(KSEG1 + 0x0C000008) /* SIU IrDA Selectot (R/W) */ -#define VR4181_SIURESET_2 __preg8(KSEG1 + 0x0C000009) /* SIU Reset Register (R/W) */ -#define VR4181_SIUCSEL_2 __preg8(KSEG1 + 0x0C00000A) /* IrDA Echo-back Control (R/W) */ -#define VR4181_SIUACTMSK_2 __preg8(KSEG1 + 0x0C00000C) /* SIU Activity Mask Register (R/W) */ -#define VR4181_SIUACTTMR_2 __preg8(KSEG1 + 0x0C00000E) /* SIU Activity Timer Register (R/W) */ - - -// USB Module -#define VR4181_USBINFIFO __preg16(KSEG1 + 0x0B000780) /* USB Bulk Input FIFO (Bulk In End Point) (W) */ -#define VR4181_USBOUTFIFO __preg16(KSEG1 + 0x0B000782) /* USB Bulk Output FIFO (Bulk Out End Point) (R) */ -#define VR4181_USBCTLFIFO __preg16(KSEG1 + 0x0B000784) /* USB Control FIFO (Control End Point) (W) */ -#define VR4181_USBSTAT __preg16(KSEG1 + 0x0B000786) /* Interrupt Status Register (R/W) */ -#define VR4181_USBINTMSK __preg16(KSEG1 + 0x0B000788) /* Interrupt Mask Register (R/W) */ -#define VR4181_USBCTLREG __preg16(KSEG1 + 0x0B00078A) /* Control Register (R/W) */ -#define VR4181_USBSTPREG __preg16(KSEG1 + 0x0B00078C) /* USB Transfer Stop Register (R/W) */ - -// LCD Controller -#define VR4181_HRTOTALREG __preg16(KSEG1 + 0x0A000400) /* Horizontal total Register (R/W) */ -#define VR4181_HRVISIBREG __preg16(KSEG1 + 0x0A000402) /* Horizontal Visible Register (R/W) */ -#define VR4181_LDCLKSTREG __preg16(KSEG1 + 0x0A000404) /* Load clock start Register (R/W) */ -#define VR4181_LDCLKNDREG __preg16(KSEG1 + 0x0A000406) /* Load clock end Register (R/W) */ -#define VR4181_VRTOTALREG __preg16(KSEG1 + 0x0A000408) /* Vertical Total Register (R/W) */ -#define VR4181_VRVISIBREG __preg16(KSEG1 + 0x0A00040A) /* Vertical Visible Register (R/W) */ -#define VR4181_FVSTARTREG __preg16(KSEG1 + 0x0A00040C) /* FLM vertical start Register (R/W) */ -#define VR4181_FVENDREG __preg16(KSEG1 + 0x0A00040E) /* FLM vertical end Register (R/W) */ -#define VR4181_LCDCTRLREG __preg16(KSEG1 + 0x0A000410) /* LCD control Register (R/W) */ -#define VR4181_LCDINRQREG __preg16(KSEG1 + 0x0A000412) /* LCD Interrupt request Register (R/W) */ -#define VR4181_LCDCFGREG0 __preg16(KSEG1 + 0x0A000414) /* LCD Configuration Register 0 (R/W) */ -#define VR4181_LCDCFGREG1 __preg16(KSEG1 + 0x0A000416) /* LCD Configuration Register 1 (R/W) */ -#define VR4181_FBSTAD1REG __preg16(KSEG1 + 0x0A000418) /* Frame Buffer Start Address 1 Register (R/W) */ -#define VR4181_FBSTAD2REG __preg16(KSEG1 + 0x0A00041A) /* Frame Buffer Start Address 2 Register (R/W) */ -#define VR4181_FBNDAD1REG __preg16(KSEG1 + 0x0A000420) /* Frame Buffer End Address 1 Register (R/W) */ -#define VR4181_FBNDAD2REG __preg16(KSEG1 + 0x0A000422) /* Frame Buffer End Address 2 register (R/W) */ -#define VR4181_FHSTARTREG __preg16(KSEG1 + 0x0A000424) /* FLM horizontal Start Register (R/W) */ -#define VR4181_FHENDREG __preg16(KSEG1 + 0x0A000426) /* FLM horizontal End Register (R/W) */ -#define VR4181_PWRCONREG1 __preg16(KSEG1 + 0x0A000430) /* Power Control register 1 (R/W) */ -#define VR4181_PWRCONREG2 __preg16(KSEG1 + 0x0A000432) /* Power Control register 2 (R/W) */ -#define VR4181_LCDIMSKREG __preg16(KSEG1 + 0x0A000434) /* LCD Interrupt Mask register (R/W) */ -#define VR4181_CPINDCTREG __preg16(KSEG1 + 0x0A00047E) /* Color palette Index and control Register (R/W) */ -#define VR4181_CPALDATREG __preg32(KSEG1 + 0x0A000480) /* Color palette data register (32bits Register) (R/W) */ - -// physical address spaces -#define VR4181_LCD 0x0a000000 -#define VR4181_INTERNAL_IO_2 0x0b000000 -#define VR4181_INTERNAL_IO_1 0x0c000000 -#define VR4181_ISA_MEM 0x10000000 -#define VR4181_ISA_IO 0x14000000 -#define VR4181_ROM 0x18000000 - -// This is the base address for IO port decoding to which the 16 bit IO port address -// is added. Defining it to 0 will usually cause a kernel oops any time port IO is -// attempted, which can be handy for turning up parts of the kernel that make -// incorrect architecture assumptions (by assuming that everything acts like a PC), -// but we need it correctly defined to use the PCMCIA/CF controller: -#define VR4181_PORT_BASE (KSEG1 + VR4181_ISA_IO) -#define VR4181_ISAMEM_BASE (KSEG1 + VR4181_ISA_MEM) - -#endif /* __ASM_VR4181_VR4181_H */ From ralf@linux-mips.org Fri Jun 3 15:32:12 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Fri, 03 Jun 2005 16:32:12 +0100 (BST) From: ralf@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Fri, 03 Jun 2005 16:32:12 +0100 X-archive-position: 461 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ralf@ftp.linux-mips.org 05/06/03 16:32:06 Modified files: include/asm-mips: elf.h Log message: Fix 64-bit breakage after DSP ASE support. diff -urN linux/include/asm-mips/elf.h linux/include/asm-mips/elf.h --- linux/include/asm-mips/elf.h 2005/05/31 11:49:19 1.27 +++ linux/include/asm-mips/elf.h 2005/06/03 15:32:05 1.28 @@ -216,7 +216,10 @@ #ifdef CONFIG_MIPS32_N32 #define __SET_PERSONALITY32_N32() \ - do { current->thread.abi = &mips_abi_n32; } while (0) + do { \ + current->thread.mflags |= MF_N32; \ + current->thread.abi = &mips_abi_n32; \ + } while (0) #else #define __SET_PERSONALITY32_N32() \ do { } while (0) @@ -224,7 +227,10 @@ #ifdef CONFIG_MIPS32_O32 #define __SET_PERSONALITY32_O32() \ - do { current->thread.abi = &mips_abi_32; } while (0) + do { \ + current->thread.mflags |= MF_O32; \ + current->thread.abi = &mips_abi_32; \ + } while (0) #else #define __SET_PERSONALITY32_O32() \ do { } while (0) @@ -244,11 +250,14 @@ #endif #define SET_PERSONALITY(ex, ibcs2) \ -do { current->thread.mflags &= ~MF_ABI_MASK; \ +do { \ + current->thread.mflags &= ~MF_ABI_MASK; \ if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ __SET_PERSONALITY32(ex); \ - else \ + else { \ + current->thread.mflags |= MF_N64; \ current->thread.abi = &mips_abi; \ + } \ \ if (ibcs2) \ set_personality(PER_SVR4); \ From sjhill@linux-mips.org Sun Jun 5 03:56:13 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Sun, 05 Jun 2005 04:56:13 +0100 (BST) From: sjhill@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Sun, 05 Jun 2005 04:56:13 +0100 X-archive-position: 462 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: sjhill@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: sjhill@ftp.linux-mips.org 05/06/05 04:56:02 Modified files: drivers/serial : au1x00_uart.c Log message: Fix forward declaration for consistency. This was an error when using GCC-4.1.0. diff -urN linux/drivers/serial/au1x00_uart.c linux/drivers/serial/au1x00_uart.c --- linux/drivers/serial/au1x00_uart.c 2005/04/21 05:08:25 1.14 +++ linux/drivers/serial/au1x00_uart.c 2005/06/05 03:56:02 1.15 @@ -1186,7 +1186,7 @@ return uart_set_options(port, co, baud, parity, bits, flow); } -extern struct uart_driver serial8250_reg; +static struct uart_driver serial8250_reg; static struct console serial8250_console = { .name = "ttyS", .write = serial8250_console_write, From sjhill@linux-mips.org Sun Jun 5 03:57:27 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Sun, 05 Jun 2005 04:57:27 +0100 (BST) From: sjhill@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Sun, 05 Jun 2005 04:57:27 +0100 X-archive-position: 463 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: sjhill@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: sjhill@ftp.linux-mips.org 05/06/05 04:57:20 Modified files: arch/mips : Kconfig Log message: The DbAu1500 board also support big endian. Gee, imagine that. diff -urN linux/arch/mips/Kconfig linux/arch/mips/Kconfig --- linux/arch/mips/Kconfig 2005/06/03 13:08:04 1.146 +++ linux/arch/mips/Kconfig 2005/06/05 03:57:20 1.147 @@ -84,6 +84,7 @@ select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_DB1550 From ths@linux-mips.org Mon Jun 6 14:46:28 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Mon, 06 Jun 2005 15:46:28 +0100 (BST) From: ths@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Mon, 06 Jun 2005 15:46:28 +0100 X-archive-position: 464 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ths@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ths@ftp.linux-mips.org 05/06/06 15:46:22 Modified files: include/asm-mips: Tag: linux_2_4 hazards.h include/asm-mips64: Tag: linux_2_4 hazards.h arch/mips/mm : Tag: linux_2_4 tlbex-r4k.S arch/mips64/mm : Tag: linux_2_4 tlbex-r4k.S Log message: TLB micro-optimization. diff -urN linux/include/asm-mips/hazards.h linux/include/asm-mips/hazards.h --- linux/include/asm-mips/hazards.h 2005/06/03 02:21:07 1.1.2.3 +++ linux/include/asm-mips/hazards.h 2005/06/06 14:46:22 1.1.2.4 @@ -45,7 +45,8 @@ */ #define mtc0_tlbw_hazard \ b . + 8 -#define tlbw_eret_hazard +#define tlbw_eret_hazard \ + nop #endif /* diff -urN linux/include/asm-mips64/hazards.h linux/include/asm-mips64/hazards.h --- linux/include/asm-mips64/Attic/hazards.h 2005/06/03 02:21:07 1.1.2.3 +++ linux/include/asm-mips64/Attic/hazards.h 2005/06/06 14:46:22 1.1.2.4 @@ -45,7 +45,8 @@ */ #define mtc0_tlbw_hazard \ b . + 8 -#define tlbw_eret_hazard +#define tlbw_eret_hazard \ + nop #endif /* diff -urN linux/arch/mips/mm/tlbex-r4k.S linux/arch/mips/mm/tlbex-r4k.S --- linux/arch/mips/mm/Attic/tlbex-r4k.S 2005/06/03 02:21:06 1.2.2.20 +++ linux/arch/mips/mm/Attic/tlbex-r4k.S 2005/06/06 14:46:22 1.2.2.21 @@ -186,7 +186,6 @@ P_MTC0 k1, CP0_ENTRYLO1 # load it mtc0_tlbw_hazard tlbwr # write random tlb entry - nop tlbw_eret_hazard eret END(except_vec0_r4000) @@ -468,7 +467,6 @@ PTE_RELOAD(k1, k0) mtc0_tlbw_hazard tlbwi - nop tlbw_eret_hazard .set mips3 eret @@ -493,7 +491,6 @@ PTE_RELOAD(k1, k0) mtc0_tlbw_hazard tlbwi - nop tlbw_eret_hazard .set mips3 eret @@ -523,7 +520,6 @@ PTE_RELOAD(k1, k0) mtc0_tlbw_hazard tlbwi - nop tlbw_eret_hazard .set mips3 eret diff -urN linux/arch/mips64/mm/tlbex-r4k.S linux/arch/mips64/mm/tlbex-r4k.S --- linux/arch/mips64/mm/Attic/tlbex-r4k.S 2005/06/03 02:21:07 1.1.2.20 +++ linux/arch/mips64/mm/Attic/tlbex-r4k.S 2005/06/06 14:46:22 1.1.2.21 @@ -125,6 +125,33 @@ nop END(except_vec1_r4k) + __FINIT + + .align 5 +LEAF(handle_vec1_r4k) + .set noat + LOAD_PTE2 k1 k0 9f + ld k0, 0(k1) # get even pte + ld k1, 8(k1) # get odd pte + PTE_RELOAD k0 k1 + mtc0_tlbw_hazard + tlbwr + tlbw_eret_hazard + eret + +9: # handle the vmalloc range + LOAD_KPTE2 k1 k0 invalid_vmalloc_address + ld k0, 0(k1) # get even pte + ld k1, 8(k1) # get odd pte + PTE_RELOAD k0 k1 + mtc0_tlbw_hazard + tlbwr + tlbw_eret_hazard + eret +END(handle_vec1_r4k) + + __INIT + LEAF(except_vec1_sb1) #if BCM1250_M3_WAR dmfc0 k0, CP0_BADVADDR @@ -134,18 +161,17 @@ bnez k0, 1f #endif .set noat - dla k0, handle_vec1_r4k + dla k0, handle_vec1_sb1 jr k0 nop 1: eret - nop END(except_vec1_sb1) __FINIT .align 5 -LEAF(handle_vec1_r4k) +LEAF(handle_vec1_sb1) .set noat LOAD_PTE2 k1 k0 9f ld k0, 0(k1) # get even pte @@ -153,7 +179,6 @@ PTE_RELOAD k0 k1 mtc0_tlbw_hazard tlbwr -1: tlbw_eret_hazard eret 9: # handle the vmalloc range @@ -163,10 +188,8 @@ PTE_RELOAD k0 k1 mtc0_tlbw_hazard tlbwr - nop -1: tlbw_eret_hazard eret -END(handle_vec1_r4k) +END(handle_vec1_sb1) __INIT @@ -194,7 +217,6 @@ PTE_RELOAD k0 k1 mtc0_tlbw_hazard tlbwr - tlbw_eret_hazard eret 9: # handle the vmalloc range @@ -204,7 +226,6 @@ PTE_RELOAD k0 k1 mtc0_tlbw_hazard tlbwr - tlbw_eret_hazard eret END(handle_vec1_r10k) From macro@linux-mips.org Mon Jun 6 16:41:04 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Mon, 06 Jun 2005 17:41:04 +0100 (BST) From: macro@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Mon, 06 Jun 2005 17:41:04 +0100 X-archive-position: 465 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: macro@ftp.linux-mips.org 05/06/06 17:40:58 Modified files: arch/mips/kernel: cpu-probe.c Log message: For MIPS32/MIPS64 cp0.config.mt == 1 implies a standard (R4k-style) TLB, so no need to set it separately for each implementation. diff -urN linux/arch/mips/kernel/cpu-probe.c linux/arch/mips/kernel/cpu-probe.c --- linux/arch/mips/kernel/cpu-probe.c 2005/05/31 11:49:19 1.48 +++ linux/arch/mips/kernel/cpu-probe.c 2005/06/06 16:40:58 1.49 @@ -428,7 +428,7 @@ config0 = read_c0_config(); if (((config0 & MIPS_CONF_MT) >> 7) == 1) - c->options |= MIPS_CPU_TLB; + c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB; isa = (config0 & MIPS_CONF_AT) >> 13; switch (isa) { case 0: @@ -516,7 +516,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c) { decode_configs(c); - c->options |= MIPS_CPU_4KTLB; switch (c->processor_id & 0xff00) { case PRID_IMP_4KC: c->cputype = CPU_4KC; @@ -551,7 +550,6 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) { decode_configs(c); - c->options |= MIPS_CPU_4KTLB; switch (c->processor_id & 0xff00) { case PRID_IMP_AU1_REV1: case PRID_IMP_AU1_REV2: @@ -582,7 +580,6 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) { decode_configs(c); - c->options |= MIPS_CPU_4KTLB; switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; @@ -597,7 +594,6 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) { decode_configs(c); - c->options |= MIPS_CPU_4KTLB; switch (c->processor_id & 0xff00) { case PRID_IMP_SR71000: c->cputype = CPU_SR71000; From ralf@linux-mips.org Tue Jun 7 11:40:03 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Tue, 07 Jun 2005 12:40:03 +0100 (BST) From: ralf@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Tue, 07 Jun 2005 12:40:03 +0100 X-archive-position: 466 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ralf@ftp.linux-mips.org 05/06/07 12:39:57 Modified files: include/asm-mips: mipsregs.h Log message: Remove dead code which was causing warnings. diff -urN linux/include/asm-mips/mipsregs.h linux/include/asm-mips/mipsregs.h --- linux/include/asm-mips/mipsregs.h 2005/05/31 11:49:19 1.73 +++ linux/include/asm-mips/mipsregs.h 2005/06/07 11:39:57 1.74 @@ -1010,8 +1010,6 @@ #define wrdsp(val, mask) \ do { \ - unsigned int __res; \ - \ __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ @@ -1021,7 +1019,6 @@ " .set pop \n" \ : \ : "r" (val), "i" (mask)); \ - __res; \ } while (0) #if 0 /* Need DSP ASE capable assembler ... */ From ralf@linux-mips.org Tue Jun 7 13:45:50 2005 Received: with ECARTIS (v1.0.0; list linux-cvs-patches); Tue, 07 Jun 2005 14:45:51 +0100 (BST) From: ralf@linux-mips.org To: linux-cvs-patches@linux-mips.org Subject: CVS Update@linux-mips.org: linux Date: Tue, 07 Jun 2005 14:45:50 +0100 X-archive-position: 467 X-ecartis-version: Ecartis v1.0.0 Sender: linux-cvs-patches-bounce@linux-mips.org Errors-to: linux-cvs-patches-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk Reply-to: linux-mips@linux-mips.org X-list: linux-cvs-patches CVSROOT: /home/cvs Module name: linux Changes by: ralf@ftp.linux-mips.org 05/06/07 14:45:43 Modified files: . : MAINTAINERS Makefile Documentation/DocBook: libata.tmpl arch/h8300/kernel: process.c arch/i386 : Kconfig arch/i386/kernel: setup.c smpboot.c arch/i386/kernel/cpu: intel_cacheinfo.c arch/i386/kernel/cpu/cpufreq: Kconfig Makefile longhaul.c powernow-k7.c powernow-k8.c powernow-k8.h speedstep-centrino.c speedstep-lib.c speedstep-smi.c arch/i386/kernel/timers: common.c timer_tsc.c arch/i386/pci : irq.c arch/ia64/ia32 : sys_ia32.c arch/ia64/kernel: entry.S mca.c minstate.h perfmon.c ptrace.c smpboot.c sys_ia64.c arch/ia64/sn/kernel: setup.c arch/m68knommu/kernel: process.c arch/mips : defconfig arch/mips/configs: atlas_defconfig capcella_defconfig cobalt_defconfig db1000_defconfig db1100_defconfig db1500_defconfig db1550_defconfig ddb5476_defconfig ddb5477_defconfig decstation_defconfig e55_defconfig ev64120_defconfig ev96100_defconfig ip22_defconfig ip27_defconfig ip32_defconfig it8172_defconfig ivr_defconfig jaguar-atx_defconfig jmr3927_defconfig lasat200_defconfig malta_defconfig mpc30x_defconfig ocelot_3_defconfig ocelot_c_defconfig ocelot_defconfig ocelot_g_defconfig pb1100_defconfig pb1500_defconfig pb1550_defconfig rm200_defconfig sb1250-swarm_defconfig sead_defconfig tb0226_defconfig tb0229_defconfig workpad_defconfig yosemite_defconfig arch/ppc : Kconfig arch/ppc/boot/images: Makefile arch/ppc/configs: mpc8555_cds_defconfig arch/ppc/kernel: head_fsl_booke.S traps.c arch/ppc/platforms: pmac_cpufreq.c pq2ads.h arch/ppc/platforms/83xx: mpc834x_sys.c mpc834x_sys.h arch/ppc/platforms/85xx: mpc8540_ads.c mpc85xx_cds_common.c mpc85xx_cds_common.h sbc8560.c arch/ppc/syslib: Makefile m8260_pci_erratum9.c m8260_setup.c open_pic.c ppc83xx_setup.c ppc85xx_setup.c prom_init.c arch/ppc64/kernel: entry.S head.S iSeries_setup.c idle.c mf.c pSeries_reconfig.c process.c prom_init.c rtc.c setup.c smp.c sysfs.c time.c arch/s390/appldata: appldata_base.c appldata_mem.c appldata_net_sum.c appldata_os.c arch/s390/kernel: ptrace.c arch/s390/mm : fault.c arch/sparc64/kernel: pci_iommu.c pci_psycho.c pci_sabre.c pci_schizo.c sbus.c setup.c smp.c traps.c arch/um : Kconfig.debug arch/um/drivers: random.c ssl.c stdio_console.c ubd_kern.c arch/um/include: sysrq.h arch/um/kernel : exec_kern.c main.c process_kern.c ptrace.c sysrq.c trap_kern.c um_arch.c arch/um/kernel/tt: process_kern.c arch/um/sys-i386: sysrq.c arch/um/sys-ppc: sysrq.c arch/um/sys-x86_64: syscalls.c sysrq.c arch/x86_64 : Kconfig arch/x86_64/kernel: io_apic.c mpparse.c signal.c time.c traps.c x8664_ksyms.c drivers/acpi : Kconfig pci_irq.c drivers/atm : Makefile fore200e.c he.c nicstar.c zatm.c drivers/block : ub.c drivers/cdrom : viocd.c drivers/char/ipmi: ipmi_devintf.c drivers/cpufreq: Kconfig Makefile cpufreq.c cpufreq_ondemand.c cpufreq_stats.c drivers/firmware: pcdp.c drivers/i2c/busses: i2c-ali1563.c drivers/ide : ide-cd.c ide-disk.c ide-floppy.c ide-probe.c ide-proc.c ide-tape.c ide.c drivers/ide/pci: amd74xx.c drivers/infiniband/core: sa_query.c user_mad.c drivers/infiniband/include: ib_sa.h drivers/input : joydev.c mousedev.c drivers/input/gameport: Kconfig drivers/input/keyboard: atkbd.c drivers/input/mouse: psmouse-base.c synaptics.c drivers/input/serio: i8042-x86ia64io.h i8042.c drivers/input/touchscreen: gunze.c drivers/macintosh: therm_adt746x.c via-pmu.c drivers/media/dvb/bt8xx: dst.c drivers/media/video: bttv-i2c.c drivers/net : Kconfig Makefile amd8111e.c e100.c forcedeth.c iseries_veth.c natsemi.c ns83820.c pcnet32.c r8169.c shaper.c sis900.c tg3.c tlan.c drivers/net/bonding: bond_main.c drivers/net/e1000: e1000.h e1000_ethtool.c e1000_hw.c e1000_hw.h e1000_main.c e1000_osdep.h e1000_param.c drivers/net/hamradio: baycom_epp.c drivers/net/ixgb: ixgb.h ixgb_ee.c ixgb_ethtool.c ixgb_main.c ixgb_osdep.h drivers/net/pcmcia: 3c574_cs.c drivers/net/tulip: media.c drivers/net/wireless: airo.c atmel_cs.c drivers/pci : quirks.c drivers/pci/hotplug: cpci_hotplug_core.c cpci_hotplug_pci.c shpchprm_acpi.c drivers/s390/net: Makefile ctcdbug.h ctcmain.c ctctty.c cu3088.c cu3088.h iucv.c lcs.c qeth.h qeth_eddp.c qeth_main.c qeth_tso.h drivers/scsi : ahci.c ata_piix.c ide-scsi.c libata-core.c libata-scsi.c libata.h sata_nv.c sata_promise.c sata_qstor.c sata_sil.c sata_sis.c sata_svw.c sata_sx4.c sata_uli.c sata_via.c sata_vsc.c scsi_scan.c drivers/scsi/aic7xxx: aic79xx_osm.c drivers/scsi/qla2xxx: qla_os.c drivers/usb/atm: speedtch.c drivers/usb/core: sysfs.c drivers/usb/host: Kconfig Makefile sl811-hcd.c drivers/usb/input: hid-core.c drivers/usb/media/pwc: Makefile pwc-ctrl.c pwc-if.c pwc-kiara.c pwc-timon.c pwc-uncompress.c drivers/usb/net: usbnet.c drivers/usb/serial: Kconfig Makefile cp2101.c ftdi_sio.c ftdi_sio.h usb-serial.c drivers/usb/storage: unusual_devs.h drivers/video/intelfb: intelfbdrv.c fs : mpage.c fs/cifs : README cifsproto.h cifssmb.c dir.c inode.c misc.c fs/hostfs : hostfs_kern.c fs/jbd : checkpoint.c fs/proc : proc_devtree.c fs/udf : udftime.c fs/xfs : xfs_iomap.c fs/xfs/linux-2.6: xfs_aops.c xfs_file.c xfs_ioctl32.c xfs_ioctl32.h xfs_super.c include/asm-i386: linkage.h timer.h include/asm-ia64: perfmon.h include/asm-ia64/sn: sn_sal.h include/asm-ppc: cpm2.h m8260_pci.h mpc8260.h include/asm-ppc64: processor.h prom.h thread_info.h include/asm-ppc64/iSeries: mf.h include/asm-s390: user.h include/asm-sh : thread_info.h include/asm-sh64: thread_info.h include/asm-sparc64: iommu.h pbm.h spitfire.h include/asm-um : page.h pgtable.h thread_info.h include/asm-x86_64: bug.h include/linux : acpi.h cpufreq.h etherdevice.h ethtool.h gameport.h hardirq.h ide.h if_shaper.h if_tr.h inetdevice.h libata.h mii.h netdevice.h notifier.h pci_ids.h pkt_sched.h sysctl.h usb.h include/net : route.h xfrm.h init : Kconfig kernel : cpuset.c module.c kernel/irq : handle.c lib : Kconfig.debug net/802 : tr.c net/bridge : br_device.c br_if.c br_input.c br_notify.c br_private.h br_stp_bpdu.c net/core : dev.c ethtool.c net-sysfs.c net/ipv4 : devinet.c esp4.c multipath_drr.c multipath_rr.c udp.c net/ipv4/ipvs : Makefile ip_vs_proto.c net/ipv4/netfilter: ip_queue.c net/ipv6 : ip6_flowlabel.c ipv6_syms.c xfrm6_policy.c net/sched : sch_dsmark.c sch_netem.c net/xfrm : xfrm_policy.c sound/oss : Kconfig sound/ppc : pmac.c Added files: Documentation/cpu-freq: cpufreq-stats.txt arch/i386/kernel/cpu/cpufreq: sc520_freq.c arch/ppc/syslib: m82xx_pci.c m82xx_pci.h drivers/cpufreq: cpufreq_conservative.c drivers/net : bnx2.c bnx2.h bnx2_fw.h drivers/s390/net: ctcmain.h drivers/usb/host: sl811_cs.c drivers/usb/serial: option.c Removed files: arch/ppc/syslib: m8260_pci.c m8260_pci.h arch/um/include: 2_5compat.h arch/um/kernel : initrd_kern.c initrd_user.c drivers/s390/net: qeth_tso.c drivers/usb/media/pwc: ChangeLog pwc-dec1.c pwc-dec1.h pwc-dec23.c pwc-dec23.h net/ipv4/ipvs : ip_vs_proto_icmp.c Log message: Merge with Linux 2.6.12-rc6. diff -urN linux/MAINTAINERS linux/MAINTAINERS --- linux/MAINTAINERS 2005/05/19 12:08:04 1.180 +++ linux/MAINTAINERS 2005/06/07 13:45:25 1.181 @@ -239,6 +239,12 @@ W: http://www.linux-usb.org/SpeedTouch/ S: Maintained +ALI1563 I2C DRIVER +P: Rudolf Marek +M: r.marek@sh.cvut.cz +L: sensors@stimpy.netroedge.com +S: Maintained + ALPHA PORT P: Richard Henderson M: rth@twiddle.net @@ -1023,8 +1029,8 @@ S: Maintained SN-IA64 (Itanium) SUB-PLATFORM -P: Jesse Barnes -M: jbarnes@sgi.com +P: Greg Edwards +M: edwardsg@sgi.com L: linux-altix@sgi.com L: linux-ia64@vger.kernel.org W: http://www.sgi.com/altix diff -urN linux/Makefile linux/Makefile --- linux/Makefile 2005/05/26 09:12:35 1.252 +++ linux/Makefile 2005/06/07 13:45:25 1.253 @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 6 SUBLEVEL = 12 -EXTRAVERSION =-rc5 +EXTRAVERSION =-rc6 NAME=Woozy Numbat # *DOCUMENTATION* diff -urN linux/Documentation/DocBook/libata.tmpl linux/Documentation/DocBook/libata.tmpl --- linux/Documentation/DocBook/libata.tmpl 2005/03/18 17:36:43 1.4 +++ linux/Documentation/DocBook/libata.tmpl 2005/06/07 13:45:25 1.5 @@ -14,7 +14,7 @@ - 2003 + 2003-2005 Jeff Garzik @@ -44,30 +44,38 @@ - - Thanks + + Introduction - The bulk of the ATA knowledge comes thanks to long conversations with - Andre Hedrick (www.linux-ide.org). + libATA is a library used inside the Linux kernel to support ATA host + controllers and devices. libATA provides an ATA driver API, class + transports for ATA and ATAPI devices, and SCSI<->ATA translation + for ATA devices according to the T10 SAT specification. - Thanks to Alan Cox for pointing out similarities - between SATA and SCSI, and in general for motivation to hack on - libata. - - - libata's device detection - method, ata_pio_devchk, and in general all the early probing was - based on extensive study of Hale Landis's probe/reset code in his - ATADRVR driver (www.ata-atapi.com). + This Guide documents the libATA driver API, library functions, library + internals, and a couple sample ATA low-level drivers. libata Driver API + + struct ata_port_operations is defined for every low-level libata + hardware driver, and it controls how the low-level driver + interfaces with the ATA and SCSI layers. + + + FIS-based drivers will hook into the system with ->qc_prep() and + ->qc_issue() high-level hooks. Hardware which behaves in a manner + similar to PCI IDE hardware may utilize several generic helpers, + defining at a bare minimum the bus I/O addresses of the ATA shadow + register blocks. + struct ata_port_operations + Disable ATA port void (*port_disable) (struct ata_port *); @@ -78,6 +86,9 @@ unplug). + + + Post-IDENTIFY device configuration void (*dev_config) (struct ata_port *, struct ata_device *); @@ -88,6 +99,9 @@ issue of SET FEATURES - XFER MODE, and prior to operation. + + + Set PIO/DMA mode void (*set_piomode) (struct ata_port *, struct ata_device *); void (*set_dmamode) (struct ata_port *, struct ata_device *); @@ -108,6 +122,9 @@ ->set_dma_mode() is only called if DMA is possible. + + + Taskfile read/write void (*tf_load) (struct ata_port *ap, struct ata_taskfile *tf); void (*tf_read) (struct ata_port *ap, struct ata_taskfile *tf); @@ -120,6 +137,9 @@ taskfile register values. + + + ATA command execute void (*exec_command)(struct ata_port *ap, struct ata_taskfile *tf); @@ -129,17 +149,37 @@ ->tf_load(), to be initiated in hardware. + + + Per-cmd ATAPI DMA capabilities filter + +int (*check_atapi_dma) (struct ata_queued_cmd *qc); + + + +Allow low-level driver to filter ATA PACKET commands, returning a status +indicating whether or not it is OK to use DMA for the supplied PACKET +command. + + + + + Read specific ATA shadow registers u8 (*check_status)(struct ata_port *ap); -void (*dev_select)(struct ata_port *ap, unsigned int device); +u8 (*check_altstatus)(struct ata_port *ap); +u8 (*check_err)(struct ata_port *ap); - Reads the Status ATA shadow register from hardware. On some - hardware, this has the side effect of clearing the interrupt - condition. + Reads the Status/AltStatus/Error ATA shadow register from + hardware. On some hardware, reading the Status register has + the side effect of clearing the interrupt condition. + + + Select ATA device on bus void (*dev_select)(struct ata_port *ap, unsigned int device); @@ -147,9 +187,13 @@ Issues the low-level hardware command(s) that causes one of N hardware devices to be considered 'selected' (active and - available for use) on the ATA bus. + available for use) on the ATA bus. This generally has no +meaning on FIS-based devices. + + + Reset ATA bus void (*phy_reset) (struct ata_port *ap); @@ -162,17 +206,31 @@ functions ata_bus_reset() or sata_phy_reset() for this hook. + + + Control PCI IDE BMDMA engine void (*bmdma_setup) (struct ata_queued_cmd *qc); void (*bmdma_start) (struct ata_queued_cmd *qc); +void (*bmdma_stop) (struct ata_port *ap); +u8 (*bmdma_status) (struct ata_port *ap); - When setting up an IDE BMDMA transaction, these hooks arm - (->bmdma_setup) and fire (->bmdma_start) the hardware's DMA - engine. +When setting up an IDE BMDMA transaction, these hooks arm +(->bmdma_setup), fire (->bmdma_start), and halt (->bmdma_stop) +the hardware's DMA engine. ->bmdma_status is used to read the standard +PCI IDE DMA Status register. + +These hooks are typically either no-ops, or simply not implemented, in +FIS-based drivers. + + + + + High-level taskfile hooks void (*qc_prep) (struct ata_queued_cmd *qc); int (*qc_issue) (struct ata_queued_cmd *qc); @@ -190,20 +248,26 @@ ->qc_issue is used to make a command active, once the hardware and S/G tables have been prepared. IDE BMDMA drivers use the helper function ata_qc_issue_prot() for taskfile protocol-based - dispatch. More advanced drivers roll their own ->qc_issue - implementation, using this as the "issue new ATA command to - hardware" hook. + dispatch. More advanced drivers implement their own ->qc_issue. + + + Timeout (error) handling void (*eng_timeout) (struct ata_port *ap); - This is a high level error handling function, called from the - error handling thread, when a command times out. +This is a high level error handling function, called from the +error handling thread, when a command times out. Most newer +hardware will implement its own error handling code here. IDE BMDMA +drivers may use the helper function ata_eng_timeout(). + + + Hardware interrupt handling irqreturn_t (*irq_handler)(int, void *, struct pt_regs *); void (*irq_clear) (struct ata_port *); @@ -216,6 +280,9 @@ is quiet. + + + SATA phy read/write u32 (*scr_read) (struct ata_port *ap, unsigned int sc_reg); void (*scr_write) (struct ata_port *ap, unsigned int sc_reg, @@ -227,6 +294,9 @@ if ->phy_reset hook called the sata_phy_reset() helper function. + + + Init and shutdown int (*port_start) (struct ata_port *ap); void (*port_stop) (struct ata_port *ap); @@ -240,15 +310,17 @@ tasks. - ->host_stop() is called when the rmmod or hot unplug process - begins. The hook must stop all hardware interrupts, DMA - engines, etc. - - ->port_stop() is called after ->host_stop(). It's sole function is to release DMA/memory resources, now that they are no longer actively being used. + + ->host_stop() is called after all ->port_stop() calls +have completed. The hook must finalize hardware shutdown, release DMA +and other resources, etc. + + + @@ -279,4 +351,24 @@ !Idrivers/scsi/sata_sil.c + + Thanks + + The bulk of the ATA knowledge comes thanks to long conversations with + Andre Hedrick (www.linux-ide.org), and long hours pondering the ATA + and SCSI specifications. + + + Thanks to Alan Cox for pointing out similarities + between SATA and SCSI, and in general for motivation to hack on + libata. + + + libata's device detection + method, ata_pio_devchk, and in general all the early probing was + based on extensive study of Hale Landis's probe/reset code in his + ATADRVR driver (www.ata-atapi.com). + + + diff -urN linux/Documentation/cpu-freq/cpufreq-stats.txt linux/Documentation/cpu-freq/cpufreq-stats.txt --- linux/Documentation/cpu-freq/cpufreq-stats.txt 1970/01/01 00:00:00 +++ linux/Documentation/cpu-freq/cpufreq-stats.txt 2005-06-07 14:45:26.089252000 +0100 1.1 @@ -0,0 +1,128 @@ + + CPU frequency and voltage scaling statictics in the Linux(TM) kernel + + + L i n u x c p u f r e q - s t a t s d r i v e r + + - information for users - + + + Venkatesh Pallipadi + +Contents +1. Introduction +2. Statistics Provided (with example) +3. Configuring cpufreq-stats + + +1. Introduction + +cpufreq-stats is a driver that provices CPU frequency statistics for each CPU. +This statistics is provided in /sysfs as a bunch of read_only interfaces. This +interface (when configured) will appear in a seperate directory under cpufreq +in /sysfs (/devices/system/cpu/cpuX/cpufreq/stats/) for each CPU. +Various statistics will form read_only files under this directory. + +This driver is designed to be independent of any particular cpufreq_driver +that may be running on your CPU. So, it will work with any cpufreq_driver. + + +2. Statistics Provided (with example) + +cpufreq stats provides following statistics (explained in detail below). +- time_in_state +- total_trans +- trans_table + +All the statistics will be from the time the stats driver has been inserted +to the time when a read of a particular statistic is done. Obviously, stats +driver will not have any information about the the frequcny transitions before +the stats driver insertion. + +-------------------------------------------------------------------------------- +:/sys/devices/system/cpu/cpu0/cpufreq/stats # ls -l +total 0 +drwxr-xr-x 2 root root 0 May 14 16:06 . +drwxr-xr-x 3 root root 0 May 14 15:58 .. +-r--r--r-- 1 root root 4096 May 14 16:06 time_in_state +-r--r--r-- 1 root root 4096 May 14 16:06 total_trans +-r--r--r-- 1 root root 4096 May 14 16:06 trans_table +-------------------------------------------------------------------------------- + +- time_in_state +This gives the amount of time spent in each of the frequencies supported by +this CPU. The cat output will have "