CVSROOT: /home/cvs
Module name: malta
Changes by: chris@ftp.linux-mips.org 04/07/08 18:57:45
Modified files:
linux/arch/mips: Tag: MaltaRef_2_6 Kconfig Makefile
linux/arch/mips/kernel: Tag: MaltaRef_2_6 cpu-probe.c gdb-stub.c
genex.S time.c traps.c
linux/arch/mips/mips-boards/generic: Tag: MaltaRef_2_6 init.c
mipsIRQ.S time.c
linux/arch/mips/mips-boards/malta: Tag: MaltaRef_2_6 malta_int.c
linux/arch/mips/mm: Tag: MaltaRef_2_6 c-r4k.c c-sb1.c
tlb-andes.c tlb-r3k.c tlb-r4k.c tlb-sb1.c
linux/include/asm-mips: Tag: MaltaRef_2_6 asmmacro.h
cpu-features.h cpu.h hazards.h
mipsregs.h stackframe.h system.h traps.h
linux/include/asm-mips/mips-boards: Tag: MaltaRef_2_6 maltaint.h
Log message:
* include/asm-mips/mips-boards/maltaint.h: Reorganised interrupt
numbering for EI/VI mode.
* include/asm-mips/traps.h: Prototypes for new board functions.
* include/asm-mips/system.h: Added MIPSR2 interrupt disable/enable.
* include/asm-mips/mipsregs.h: Added various MIPSR2 specific
registers.
* include/asm-mips/cpu.h: Added MIPS_CPU_VI, MIPS_CPU_EI
* include/asm-mips/cpu-features.h: Added cpu_has_ei/cpu_has_vi.
* include/asm-mips/stackframe.h:
* include/asm-mips/hazards.h:
* include/asm-mips/asmmacro.h: Imported
irq_enable_hazard/irq_disable_hazard from mainline.
* arch/mips/mm/tlb-r3k.c (tlb_init):
* arch/mips/mm/tlb-r4k.c (tlb_init):
* arch/mips/mm/tlb-sb1.c (tlb_init):
* arch/mips/mm/tlb-andes.c (tlb_init):
* arch/mips/mm/c-sb1.c (ld_mmu_sb1):
* arch/mips/mm/c-r4k.c (ld_mmu_r4xx0): Use
set_uncached_handler/set_handler to install exception vectors.
* arch/mips/mips-boards/malta/malta_int.c: EI/VI support.
* arch/mips/mips-boards/generic/time.c (mips_timer_setup): Support
for EI/VI modes. Don't initialise interrupt masks in status
register (rely on generic code to enable configured interrupts).
* arch/mips/mips-boards/generic/mipsIRQ.S: Rewrite (inspired by
macro@linux-mips.org)
* arch/mips/mips-boards/generic/init.c (prom_init): Initialise
board_nmi_handler_setup and board_ejtag_handler_setup to install
YAMON compatible handlers for NMI/EJTAG exceptions.
* arch/mips/kernel/traps.c: Use board_nmi_handler_setup
& board_ejtag_handler_setup to setup board dependent NMI/EJTAG
exception handling.
(simulate_rdhwr): Simulate rdhwr on none MIPSR2 processors.
(parity_protection_init): Setup parity handling for 24K. Use EBase
register on MIPSR2 processors. Added MIPSR2 shadow set allocation.
(set_vi_srs_handler): New routines to install vectored interrupt
handlers.
(per_cpu_trap_init): Enable rdhwr access to registers. Set Ebase.
(set_handler, set_uncached_handler): New functions to install
exception vectors.
* arch/mips/kernel/time.c: Removed accum constraint from asm's.
* arch/mips/kernel/genex.S (except_vec_vi,except_vec_vi_handler):
Exception templates for vectored interrupts.
* arch/mips/kernel/gdb-stub.c: Suppress compiler warnings for
malloc/free.
* arch/mips/kernel/cpu-probe.c (decode_config3): Decode config3 to
get interrupt support options for MIPSR2.
* arch/mips/Makefile: Select mips32r2/mips64r2 when building
MIPSR2 kernels.
* arch/mips/Kconfig: Aded IRQ_CPU for Atlas/Malta/SEAD.
Reorganised MIPS32R2/MIPS64R2 support. Select CPU_MIPS32_24K if
building MIPS32 kernel for a Atlas/Malta/SEAD. Make CPU_ADVANCED
options default to the correct values. Added MIPSR2 options
CPU_MIPSR2_IRQ_VI, CPU_MIPSR2_IRQ_EI, CPU_MIPSR2_SRS.
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