CVS Update@linux-mips.org: malta

[chris@linux-mips.org]

CVSROOT:        /home/cvs
Module name:    malta
Changes by:     chris@ftp.linux-mips.org        05/07/28 18:19:38

Modified files:
        linux/arch/mips/mips-boards/generic: Tag: MaltaRef_2_6 init.c 
                                             pci.c 
        linux/arch/mips/mips-boards/malta: Tag: MaltaRef_2_6 malta_int.c 
        linux/include/asm-mips/mips-boards: Tag: MaltaRef_2_6 generic.h 

Log message:
        * include/asm-mips/mips-boards/generic.h
        (MIPS_REVISION_CORID_CORE_FPGA3): CoreFPGA3 support.
        
        * arch/mips/mips-boards/malta/malta_int.c (mips_pcibios_iack):
        CoreFPGA3 support.
        (get_int): Spurious interrupt detection doesn't work on SMP
        because it requires atomic access to the interrupt
        controller. Rely on the generic code to detect spurious interrupts.
        (corehi_irqdispatch): CoreFPGA3 support.
        (arch_init_irq): CoreFPGA3 support
        
        * arch/mips/mips-boards/generic/pci.c (pcibios_init): CoreFPGA3 support.
        
        * arch/mips/mips-boards/generic/init.c (prom_init): CoreFPGA3 support.

diff -urN malta/linux/arch/mips/mips-boards/generic/init.c 
malta/linux/arch/mips/mips-boards/generic/init.c
--- malta/linux/arch/mips/mips-boards/generic/init.c    2005/07/27 14:25:20     
1.17.1000.4
+++ malta/linux/arch/mips/mips-boards/generic/init.c    2005/07/28 17:19:38     
1.17.1000.5
@@ -336,6 +336,7 @@
 
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
+       case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 
0x2000); 
 
diff -urN malta/linux/arch/mips/mips-boards/generic/pci.c 
malta/linux/arch/mips/mips-boards/generic/pci.c
--- malta/linux/arch/mips/mips-boards/generic/pci.c     2005/06/21 13:24:12     
1.26.1000.3
+++ malta/linux/arch/mips/mips-boards/generic/pci.c     2005/07/28 17:19:38     
1.26.1000.4
@@ -197,6 +197,7 @@
 
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
+       case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                /* Set up resource ranges from the controller's registers.  */
                MSC_READ(MSC01_PCI_SC2PMBASL, start);
diff -urN malta/linux/arch/mips/mips-boards/malta/malta_int.c 
malta/linux/arch/mips/mips-boards/malta/malta_int.c
--- malta/linux/arch/mips/mips-boards/malta/malta_int.c 2005/06/21 13:24:13     
1.20.1000.3
+++ malta/linux/arch/mips/mips-boards/malta/malta_int.c 2005/07/28 17:19:38     
1.20.1000.4
@@ -57,6 +57,7 @@
        switch(mips_revision_corid) {
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
+       case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                MSC_READ(MSC01_PCI_IACK, irq);
                irq &= 0xff;
@@ -103,22 +104,10 @@
        irq = mips_pcibios_iack();
 
        /*
-        * IRQ7 is used to detect spurious interrupts.
-        * The interrupt acknowledge cycle returns IRQ7, if no
-        * interrupts is requested.
-        * We can differentiate between this situation and a
-        * "Normal" IRQ7 by reading the ISR.
+        * The only way we can decide if an interrupt is spurious
+        * is by checking the 8259 registers.  This needs a spinlock
+        * on an SMP system,  so leave it up to the generic code...
         */
-       if (irq == 7)
-       {
-               outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR,
-                    PIIX4_ICTLR1_OCW3);
-               if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
-                       irq = -1; /* Spurious interrupt */
-                       printk("We got a spurious interrupt from PIIX4.\n");
-                       atomic_inc(&irq_err_count);
-               }
-       }
 
        spin_unlock_irqrestore(&mips_irq_lock, flags);
 
@@ -153,6 +142,7 @@
         switch(mips_revision_corid) {
         case MIPS_REVISION_CORID_CORE_MSC:
         case MIPS_REVISION_CORID_CORE_FPGA2:
+        case MIPS_REVISION_CORID_CORE_FPGA3:
         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                 ll_msc_irq(regs);
                 break;
@@ -233,6 +223,7 @@
         switch(mips_revision_corid) {
         case MIPS_REVISION_CORID_CORE_MSC:
         case MIPS_REVISION_CORID_CORE_FPGA2:
+        case MIPS_REVISION_CORID_CORE_FPGA3:
         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                if (cpu_has_veic)
                        init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, 
msc_nr_eicirqs);
diff -urN malta/linux/include/asm-mips/mips-boards/generic.h 
malta/linux/include/asm-mips/mips-boards/generic.h
--- malta/linux/include/asm-mips/mips-boards/generic.h  2004/01/20 13:04:44     
1.6
+++ malta/linux/include/asm-mips/mips-boards/generic.h  2005/07/28 17:19:38     
1.6.1000.1
@@ -66,6 +66,7 @@
 #define MIPS_REVISION_CORID_CORE_EMUL      6
 #define MIPS_REVISION_CORID_CORE_FPGA2     7
 #define MIPS_REVISION_CORID_CORE_FPGAR2    8
+#define MIPS_REVISION_CORID_CORE_FPGA3     9
 
 /**** Artificial corid defines ****/
 /*