CVSROOT: /home/cvs
Module name: malta
Changes by: beth@ftp.linux-mips.org 05/07/22 14:21:43
Modified files:
linux/arch/mips/kernel: Tag: MaltaRef_2_6 irq_cpu.c
linux/include/asm-mips: Tag: MaltaRef_2_6 interrupt.h
Log message:
Fix missing CONFIG_CPU_MIPSR2 and MT stuff following the
merge-that-shall-remain-nameless.
diff -urN malta/linux/arch/mips/kernel/irq_cpu.c
malta/linux/arch/mips/kernel/irq_cpu.c
--- malta/linux/arch/mips/kernel/irq_cpu.c 2005/06/21 13:24:03
1.8.1000.2
+++ malta/linux/arch/mips/kernel/irq_cpu.c 2005/07/22 13:21:43
1.8.1000.3
@@ -37,8 +37,22 @@
static int mips_cpu_irq_base;
+
static inline void unmask_mips_irq(unsigned int irq)
{
+#ifdef CONFIG_MIPS_MT
+ /*
+ * So long as cross-VPE interrupts are done via
+ * MFTR/MTTR read-modify-writes of Cause, we need
+ * to stop other VPEs whenever the local VPE does
+ * anything similar.
+ */
+ unsigned int vpflags = dvpe();
+#endif /* CONFIG_MIPS_MT */
+ clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
+#ifdef CONFIG_MIPS_MT
+ evpe(vpflags);
+#endif /* CONFIG_MIPS_MT */
set_c0_status(0x100 << (irq - mips_cpu_irq_base));
irq_enable_hazard();
}
@@ -82,9 +96,16 @@
*/
static void mips_cpu_irq_ack(unsigned int irq)
{
+#ifdef CONFIG_MIPS_MT
+ unsigned int vpflags = dvpe();
+#endif /* CONFIG_MIPS_MT */
+
/* Only necessary for soft interrupts */
clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
+#ifdef CONFIG_MIPS_MT
+ evpe(vpflags);
+#endif /* CONFIG_MIPS_MT */
mask_mips_irq(irq);
}
@@ -95,13 +116,14 @@
}
static hw_irq_controller mips_cpu_irq_controller = {
- .typename = "MIPS",
- .startup = mips_cpu_irq_startup,
- .shutdown = mips_cpu_irq_shutdown,
- .enable = mips_cpu_irq_enable,
- .disable = mips_cpu_irq_disable,
- .ack = mips_cpu_irq_ack,
- .end = mips_cpu_irq_end,
+ "MIPS",
+ mips_cpu_irq_startup,
+ mips_cpu_irq_shutdown,
+ mips_cpu_irq_enable,
+ mips_cpu_irq_disable,
+ mips_cpu_irq_ack,
+ mips_cpu_irq_end,
+ NULL /* no affinity stuff for UP */
};
diff -urN malta/linux/include/asm-mips/interrupt.h
malta/linux/include/asm-mips/interrupt.h
--- malta/linux/include/asm-mips/interrupt.h 2005/06/21 13:36:23
1.1.1000.1
+++ malta/linux/include/asm-mips/interrupt.h 2005/07/22 13:21:43
1.1.1000.2
@@ -13,28 +13,52 @@
#include <asm/hazards.h>
+
+#ifdef CONFIG_CPU_MIPSR2
+#if !defined(CONFIG_MIPS_MT_SMTC)
__asm__ (
- ".macro\tlocal_irq_enable\n\t"
- ".set\tpush\n\t"
- ".set\treorder\n\t"
- ".set\tnoat\n\t"
- "mfc0\t$1,$12\n\t"
- "ori\t$1,0x1f\n\t"
- "xori\t$1,0x1e\n\t"
- "mtc0\t$1,$12\n\t"
- "irq_enable_hazard\n\t"
- ".set\tpop\n\t"
- ".endm");
+ ".macro\tlocal_irq_enable\n\t"
+ "ei\n\t"
+ ".endm");
+#else /* SMTC - clear TCStatus.IXMT */
+__asm__ (
+ ".macro\tlocal_irq_enable\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1,$2,1\n\t"
+ "ori\t$1,0x400\n\t"
+ "xori\t$1,0x400\n\t"
+ "mtc0\t$1,$2,1\n\t"
+ "ehb\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+#endif /* CONFIG_MIPS_MT_SMTC */
+#else /* not MIPS32R2 */
+__asm__ (
+ ".macro\tlocal_irq_enable\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1,$12\n\t"
+ "ori\t$1,0x1f\n\t"
+ "xori\t$1,0x1e\n\t"
+ "mtc0\t$1,$12\n\t"
+ "irq_enable_hazard\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+#endif
static inline void local_irq_enable(void)
{
- __asm__ __volatile__(
- "local_irq_enable"
- : /* no outputs */
- : /* no inputs */
- : "memory");
+ __asm__ __volatile__(
+ "local_irq_enable"
+ : /* no outputs */
+ : /* no inputs */
+ : "memory");
}
+
/*
* For cli() we have to insert nops to make sure that the new value
* has actually arrived in the status register before the end of this
@@ -42,6 +66,28 @@
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
* no nops at all.
*/
+
+#ifdef CONFIG_CPU_MIPSR2
+#if !defined(CONFIG_MIPS_MT_SMTC)
+__asm__ (
+ ".macro\tlocal_irq_disable\n\t"
+ "di\n\t"
+ "ehb\n\t"
+ ".endm");
+#else /* SMTC - set TCStatus.IXMT */
+__asm__ (
+ ".macro\tlocal_irq_disable\n\t"
+ ".set\tpush\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1,$2,1\n\t"
+ "ori\t$1,0x400\n\t"
+ ".set\tnoreorder\n\t"
+ "mtc0\t$1,$2,1\n\t"
+ "ehb\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+#endif /* CONFIG_MIPS_MT_SMTC */
+#else /* not MIPS32R2 */
__asm__ (
".macro\tlocal_irq_disable\n\t"
".set\tpush\n\t"
@@ -54,6 +100,7 @@
"irq_disable_hazard\n\t"
".set\tpop\n\t"
".endm");
+#endif
static inline void local_irq_disable(void)
{
@@ -64,6 +111,15 @@
: "memory");
}
+#if defined(CONFIG_MIPS_MT_SMTC)
+__asm__ (
+ ".macro\tlocal_save_flags flags\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ "mfc0\t\\flags, $2,1\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+#else /* Not SMTC */
__asm__ (
".macro\tlocal_save_flags flags\n\t"
".set\tpush\n\t"
@@ -71,12 +127,35 @@
"mfc0\t\\flags, $12\n\t"
".set\tpop\n\t"
".endm");
+#endif /* CONFIG_MIPS_MT_SMTC */
#define local_save_flags(x) \
__asm__ __volatile__( \
"local_save_flags %0" \
: "=r" (x))
+#ifdef CONFIG_CPU_MIPSR2
+#if !defined(CONFIG_MIPS_MT_SMTC)
+__asm__ (
+ ".macro\tlocal_irq_save result\n\t"
+ "di\t\\result\n\t"
+ "ehb\n\t"
+ ".endm");
+#else /* SMTC - get/set TCStatus.IXMT */
+__asm__ (
+ ".macro\tlocal_irq_save result\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t\\result, $2,1\n\t"
+ "ori\t$1, \\result, 0x400\n\t"
+ ".set\tnoreorder\n\t"
+ "mtc0\t$1, $2,1\n\t"
+ "ehb\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+#endif /* CONFIG_MIPS_MT_SMTC */
+#else /* not MIPS32R2 */
__asm__ (
".macro\tlocal_irq_save result\n\t"
".set\tpush\n\t"
@@ -90,6 +169,7 @@
"irq_disable_hazard\n\t"
".set\tpop\n\t"
".endm");
+#endif
#define local_irq_save(x) \
__asm__ __volatile__( \
@@ -98,6 +178,36 @@
: /* no inputs */ \
: "memory")
+#ifdef CONFIG_CPU_MIPSR2
+#if !defined(CONFIG_MIPS_MT_SMTC)
+__asm__ (
+ ".macro\tlocal_irq_restore flags\n\t"
+ ".set\tpush\n\t"
+ ".set\tnoreorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1, $12\n\t"
+ "ins\t$1, \\flags, 0, 1\n\t"
+ "mtc0\t$1, $12\n\t"
+ "ehb\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+#else /* SMTC - restore TCStatus IXMT */
+__asm__ (
+ ".macro\tlocal_irq_restore flags\n\t"
+ ".set\tpush\n\t"
+ ".set\tnoreorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1, $2, 1\n\t"
+ "andi\t\\flags, 0x400\n\t"
+ "ori\t$1, 0x400\n\t"
+ "xori\t$1, 0x400\n\t"
+ "or\t\\flags, $1\n\t"
+ "mtc0\t\\flags, $2, 1\n\t"
+ "ehb\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+#endif /* CONFIG_MIPS_MT_SMTC */
+#else /* not MIPS32R2 */
__asm__ (
".macro\tlocal_irq_restore flags\n\t"
".set\tnoreorder\n\t"
@@ -112,6 +222,7 @@
".set\tat\n\t"
".set\treorder\n\t"
".endm");
+#endif
#define local_irq_restore(flags) \
do { \
@@ -124,11 +235,34 @@
: "memory"); \
} while(0)
+#if !defined(CONFIG_MIPS_MT_SMTC)
#define irqs_disabled()
\
({ \
unsigned long flags; \
local_save_flags(flags); \
!(flags & 1); \
})
+#else /* SMTC */
+/*
+ * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
+ */
+
+static inline unsigned long irqs_disabled(void)
+{
+ unsigned long __result;
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ ".set mips32\n\t"
+ "mfc0\t%0,$2,1\n\t"
+ "andi\t%0,0x400\n\t"
+ "slt\t%0,$0,%0\n\t"
+ ".set mips0\n\t"
+ ".set reorder\n\t"
+ : "=r" (__result));
+ return (__result);
+}
+
+#endif /* CONFIG_MIPS_MT_SMTC */
+
#endif /* _ASM_INTERRUPT_H */
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