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CVS Update@linux-mips.org: malta

To: maltalinux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: malta
From: beth@linux-mips.org
Date: Tue, 12 Jul 2005 17:23:41 +0100
Reply-to: linux-mips@linux-mips.org
Sender: maltalinux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    malta
Changes by:     beth@ftp.linux-mips.org 05/07/12 17:23:41

Modified files:
        linux/arch/mips/kernel: Tag: MaltaRef_2_6 traps.c 

Log message:
        Some uses of set_handler, and simulate_rdhwr got mangled in the last
        merge.

diff -urN malta/linux/arch/mips/kernel/traps.c 
malta/linux/arch/mips/kernel/traps.c
--- malta/linux/arch/mips/kernel/traps.c        2005/06/21 13:24:03     
1.193.1000.5
+++ malta/linux/arch/mips/kernel/traps.c        2005/07/12 16:23:40     
1.193.1000.6
@@ -525,6 +525,26 @@
                int rd = (opcode & RD) >> 11;
                int rt = (opcode & RT) >> 16;
                switch (rd) {
+                       case 0:         /* CPU number */
+                               regs->regs[rt] = smp_processor_id();
+                               break;
+                       case 1:         /* SYNCI length */
+                               regs->regs[rt] = 
min(current_cpu_data.dcache.linesz,
+                                                    
current_cpu_data.icache.linesz);
+                               break;
+                       case 2:         /* Read count register */
+                               regs->regs[rt] = read_c0_count();
+                               break;
+                       case 3:         /* Count register resolution */
+                               switch (current_cpu_data.cputype) {
+                               case CPU_20KC:
+                               case CPU_25KF:
+                                       regs->regs[rt] = 1;
+                                       break;
+                               default:
+                                       regs->regs[rt] = 2;
+                               }
+                               break;
                        case 29:
                                regs->regs[rt] = ti->tp_value;
                                break;
@@ -1303,10 +1323,6 @@
                //set_except_vector(15, handle_ndc);
        }
 
-
-       if (board_nmi_handler_setup)
-               board_nmi_handler_setup();
-
        if (cpu_has_fpu && !cpu_has_nofpuex)
                set_except_vector(15, handle_fpe);
 
@@ -1320,11 +1336,14 @@
 
        if (cpu_has_vce)
                /* Special exception: R4[04]00 uses also the divec space. */
-               memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
+               set_handler(0x180, &except_vec3_r4000, 0x100);
        else if (cpu_has_4kex)
-               memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
+               set_handler(0x180, &except_vec3_generic, 0x80);
        else
-               memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
+               set_handler(0x080, &except_vec3_generic, 0x80);
+
+       if (board_nmi_handler_setup)
+               board_nmi_handler_setup();
 
        signal_init();
 #ifdef CONFIG_MIPS32_COMPAT

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