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Re: MIPS: Hibernate: Flush TLB entries in swsusp_arch_resume()

To: 陈华才 <chenhc@lemote.com>
Subject: Re: MIPS: Hibernate: Flush TLB entries in swsusp_arch_resume()
From: Alexandre Oliva <oliva@gnu.org>
Date: Sun, 01 Jun 2014 03:55:55 -0300
Cc: "wuzhangjin" <wuzhangjin@gmail.com>, "linux-mips" <linux-mips@linux-mips.org>, "stable" <stable@vger.kernel.org>
In-reply-to: <tencent_03F1BF0862C094496B5D0360@qq.com> ("陈华才"'s message of "Sun, 1 Jun 2014 11:06:54 +0800")
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Hi,

Thanks for your response,

On Jun  1, 2014, "陈华才" <chenhc@lemote.com> wrote:

> The original code flush both TLB and cache, and I think the original author 
> (Wu Zhangjin) has tested his code. In my patch I only restore the TLB flush, 
> but not the cache flush. Since Loongson-3A maintain cache coherency by 
> hardware, with or without cache flush will both OK. But for Loongson-2F, I 
> guess cache flush is also needed, but I have no Yeelong-2F to test now.

I'm afraid reintroducing the cache flush is not enough to bring the
kernel back to a working state, hibernation wise.  The last oops message
I saw, after the ones that flew by, had __arch_local_irq_restore at the
top of the backtrace, called by some function with resume in its name.

Any other suggestions?


Here's the patch I tried on top of yours, as an alternative to reverting
it, unfortunately without success:

--- arch/mips/power/hibernate.S
+++ arch/mips/power/hibernate.S
@@ -43,6 +43,9 @@
        bne t1, t3, 1b
        PTR_L t0, PBE_NEXT(t0)
        bnez t0, 0b
+       /* flush caches to make sure context is in memory */
+       PTR_L t0, __flush_cache_all
+       jalr t0
        jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */
        PTR_LA t0, saved_regs
        PTR_L ra, PT_R31(t0)


-- 
Alexandre Oliva, freedom fighter    http://FSFLA.org/~lxoliva/
You must be the change you wish to see in the world. -- Gandhi
Be Free! -- http://FSFLA.org/   FSF Latin America board member
Free Software Evangelist|Red Hat Brasil GNU Toolchain Engineer

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