linux-mips
[Top] [All Lists]

[PATCH v2 0/3] MIPS: Alchemy: single kernel for all devboards

To: Linux-MIPS <linux-mips@linux-mips.org>
Subject: [PATCH v2 0/3] MIPS: Alchemy: single kernel for all devboards
From: Manuel Lauss <manuel.lauss@gmail.com>
Date: Thu, 20 Feb 2014 14:59:21 +0100
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=Izu+iptr4n/3U5eiaT1WJz+gdrw/AiJo/VFUpkfenjM=; b=WXX3W+NlvohyJpd8vCChjJQwqQkn7MdFPjcyjFo+U71XauZiopvuk8T159dpLmNQ4H 9mSsVIhWGsT8KqXjb5a6USfWKGrxe3DwpmBGVm2pMnVdGfBzP+Jexdonc83DLdrJyVzk NaVQaSrjD0mVqjmXApM0wM/woEXk9i8+oR0CEl88P7GTBo43lgDTbLhIrQSCOqIi8E4N mrwjl2lQTX9lZRclASh559VMv1ZjAhnTm2lDPTgwuoNC4ehFHU4i2b1RGDn1n9YxVz5O U0uFlGedN9EjwDhxtxWLXC15/53ITOH6YcEeUHIBjqj4nxQ62dojQEbARy9GSsP2kKmt d0ag==
List-archive: <http://www.linux-mips.org/archives/linux-mips/>
List-help: <mailto:ecartis@linux-mips.org?Subject=help>
List-id: linux-mips <linux-mips.eddie.linux-mips.org>
List-owner: <mailto:ralf@linux-mips.org>
List-post: <mailto:linux-mips@linux-mips.org>
List-software: Ecartis version 1.0.0
List-subscribe: <mailto:ecartis@linux-mips.org?subject=subscribe%20linux-mips>
List-unsubscribe: <mailto:ecartis@linux-mips.org?subject=unsubscribe%20linux-mips>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
This patchset removes the last hurdles to supporting all DB/PB Develoboards
in a single kernel image.   The main issue is that on earlier chips
(Au1000, Au1500, Au1100) some peripherals, notably the USB blocks, aren't
fully dma coherent and need manual cache massaging to work properly.
For these parts DMA_NONCOHERENT is used.
Newer variants starting with the Au1550 work fine without any additional
software intervention and use DMA_COHERENT by default.

The first patch extends the already existing DMA_MAYBE_COHERENT logic to
also cover the parts which are already compiled when DMA_NONCOHERENT is
enabled.  The second patch then uses the "coherentio" variable which
DMA_MAYBE_COHERENT exports and sets it based on CPU subtype.
The third patch finally unifies support for all Alchemy devboards.

I'm not really sure if patch #1 is even the correct way to do it; however
based on my understanding of what DMA_MAYBE_COHERENT is supposed to do I
actually thought that it's a logical extension.  But I'm not sure and
don't have a MALTA board to test it on.  Hence the RFC.

v2: new defconfig replacing two oobsolete ones, some function renaming

Thanks,
        Manuel Lauss


Manuel Lauss (3):
  MIPS: extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT use
  MIPS: Alchemy: determine cohereny at runtime based on cpu type
  MIPS: Alchemy: unify Devboard support.

 arch/mips/Kconfig                    |   1 +
 arch/mips/alchemy/Kconfig            |  22 +-
 arch/mips/alchemy/Platform           |  16 +-
 arch/mips/alchemy/common/setup.c     |  10 +
 arch/mips/alchemy/devboards/Makefile |   4 +-
 arch/mips/alchemy/devboards/db1000.c |  47 +---
 arch/mips/alchemy/devboards/db1200.c |   9 +
 arch/mips/alchemy/devboards/db1235.c |  94 --------
 arch/mips/alchemy/devboards/db1300.c |   6 +-
 arch/mips/alchemy/devboards/db1550.c |  10 +-
 arch/mips/alchemy/devboards/db1xxx.c | 121 ++++++++++
 arch/mips/configs/db1000_defconfig   | 359 -----------------------------
 arch/mips/configs/db1235_defconfig   | 434 -----------------------------------
 arch/mips/configs/db1xxx_defconfig   | 248 ++++++++++++++++++++
 arch/mips/include/asm/io.h           |   4 +-
 arch/mips/mm/c-r4k.c                 |   6 +-
 arch/mips/mm/cache.c                 |   4 +-
 arch/mips/pci/pci-alchemy.c          |   5 +-
 drivers/spi/spi-au1550.c             |   9 +
 19 files changed, 445 insertions(+), 964 deletions(-)
 delete mode 100644 arch/mips/alchemy/devboards/db1235.c
 create mode 100644 arch/mips/alchemy/devboards/db1xxx.c
 delete mode 100644 arch/mips/configs/db1000_defconfig
 delete mode 100644 arch/mips/configs/db1235_defconfig
 create mode 100644 arch/mips/configs/db1xxx_defconfig

-- 
1.8.5.5


<Prev in Thread] Current Thread [Next in Thread>