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Re: [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases

To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>, <linux-mips@linux-mips.org>
Subject: Re: [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases
From: Markos Chandras <Markos.Chandras@imgtec.com>
Date: Thu, 30 Jan 2014 17:35:51 +0000
In-reply-to: <52EA9AEB.5090606@cogentembedded.com>
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On 01/30/2014 06:33 PM, Sergei Shtylyov wrote:
Hello.

On 01/30/2014 08:21 PM, Markos Chandras wrote:

The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.

This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
[...]

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 13b549a..8017f6e 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
      case CPU_PROAPTIV:
          if (current_cpu_type() == CPU_74K)
              alias_74k_erratum(c);
-        if ((read_c0_config7() & (1 << 16))) {
+        if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
+            (c->icache.waysize > PAGE_SIZE))
+                c->icache.flags |= MIPS_CACHE_ALIASES;

     Sigh, you forgot to "outdent" this statement by a tab... :-(

WBR, Sergei

Indeed I did :) I will make sure the one committed will be fixed properly.

--
markos


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