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[PATCH 39/58] MIPS: asm: r4kcache: Build flushing code for instruction c

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Subject: [PATCH 39/58] MIPS: asm: r4kcache: Build flushing code for instruction cache
From: Markos Chandras <markos.chandras@imgtec.com>
Date: Mon, 27 Jan 2014 20:19:26 +0000
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>, Markos Chandras <markos.chandras@imgtec.com>
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From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

Build code to invalidate an address range in the  instruction cache
using the Hit Invalidate cache operation.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/r4kcache.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 34d1a19..a89e86d 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -455,6 +455,7 @@ __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, 
protected_, )
 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \
        protected_, loongson23_)
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
 /* blast_inv_dcache_range */
 __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
-- 
1.8.5.3



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