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[PATCH 2/2] MIPS: fix DECStation build for L1_CACHE_SHIFT value

To: <linux-mips@linux-mips.org>
Subject: [PATCH 2/2] MIPS: fix DECStation build for L1_CACHE_SHIFT value
From: Florian Fainelli <florian@openwrt.org>
Date: Tue, 21 Jan 2014 10:01:34 -0800
Cc: <ralf@linux-mips.org>, <blogic@openwrt.org>, <macro@linux-mips.org>, Florian Fainelli <florian@openwrt.org>
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When support for the DECStation is enabled, it will default to use a
MIPS R3000 class processor. This will cause an intentional build failure
to popup because MIPS_L1_CACHE_SHIFT and cpu_dcache_line_size()
disagree. Fix this by selecting MIPS_L1_CACHE_SHIFT_2 when we build
targetting a MIPS R3000 CPU to fix that build failure and satisfy all
requirements.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
 arch/mips/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9ab4239..33738f8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -184,7 +184,8 @@ config MACH_DECSTATION
        select SYS_SUPPORTS_128HZ
        select SYS_SUPPORTS_256HZ
        select SYS_SUPPORTS_1024HZ
-       select MIPS_L1_CACHE_SHIFT_4
+       select MIPS_L1_CACHE_SHIFT_2 if CPU_R3000
+       select MIPS_L1_CACHE_SHIFT_4 if CPU_R4X00
        help
          This enables support for DEC's MIPS based workstations.  For details
          see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
-- 
1.8.3.2


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