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[PATCH 02/15] MIPS: add CP0 CMGCRBase definitions & accessor

To: <linux-mips@linux-mips.org>
Subject: [PATCH 02/15] MIPS: add CP0 CMGCRBase definitions & accessor
From: Paul Burton <paul.burton@imgtec.com>
Date: Wed, 15 Jan 2014 10:31:47 +0000
Cc: Paul Burton <paul.burton@imgtec.com>
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The CMGCRBase register is defined by the PRA specification as an optional
register which indicates the physical base of the MIPS Coherence Manager
Global Control Register block. This patch simply adds a definition for
the base address field within the register, along with an accessor
function for reading the register.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---
 arch/mips/include/asm/mipsregs.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 5302696..3401128 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -668,6 +668,10 @@
 /*  EntryHI bit definition */
 #define MIPS_ENTRYHI_EHINV     (_ULCAST_(1) << 10)
 
+/* CMGCRBase bit definitions */
+#define MIPS_CMGCRB_BASE       11
+#define MIPS_CMGCRF_BASE       (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
+
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
  */
@@ -1022,6 +1026,8 @@ do {                                                      
                \
 
 #define read_c0_prid()         __read_32bit_c0_register($15, 0)
 
+#define read_c0_cmgcrbase()    __read_ulong_c0_register($15, 3)
+
 #define read_c0_config()       __read_32bit_c0_register($16, 0)
 #define read_c0_config1()      __read_32bit_c0_register($16, 1)
 #define read_c0_config2()      __read_32bit_c0_register($16, 2)
-- 
1.8.4.2



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