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[PATCH v3 3/3] MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

To: linux-mips@linux-mips.org
Subject: [PATCH v3 3/3] MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
From: Florian Fainelli <f.fainelli@gmail.com>
Date: Mon, 13 Jan 2014 22:07:32 -0800
Cc: ralf@linux-mips.org, blogic@openwrt.org, jogo@openwrt.org, mbizon@freebox.fr, cernekee@gmail.com, dgcbueu@gmail.com, Florian Fainelli <florian@openwrt.org>
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From: Florian Fainelli <florian@openwrt.org>

Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.

Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
Changes in v2:
- rebased on top of john's mips-next-3.14

Changes since v1:
- rebased

 arch/mips/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 68969d9..beb3766 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -139,6 +139,7 @@ config BCM63XX
        select SWAP_IO_SPACE
        select ARCH_REQUIRE_GPIOLIB
        select HAVE_CLK
+       select MIPS_L1_CACHE_SHIFT_4
        help
         Support for BCM63XX based boards
 
-- 
1.8.3.2


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