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[PATCH 1/2] Fix cache flushing on Loongson 2

To: <linux-mips@linux-mips.org>
Subject: [PATCH 1/2] Fix cache flushing on Loongson 2
From: Petr Písař <petr.pisar@atlas.cz>
Date: Wed, 25 Dec 2013 15:04:21 +0100
Cc: Petr Písař <petr.pisar@atlas.cz>
In-reply-to: <1387980262-2250-1-git-send-email-petr.pisar@atlas.cz>
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This bug was introduced by an unintended branch swap in commit
14bd8c082016cd1f67fdfd702e4cf6367869a712 (MIPS: Loongson:
Get rid of Loongson 2 #ifdefery all over arch/mips).

Signed-off-by: Petr Písař <petr.pisar@atlas.cz>
---
 arch/mips/mm/c-r4k.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 62ffd20..1c2029d 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -580,11 +580,11 @@ static inline void local_r4k_flush_icache_range(unsigned 
long start, unsigned lo
        else {
                switch (boot_cpu_type()) {
                case CPU_LOONGSON2:
-                       protected_blast_icache_range(start, end);
+                       protected_loongson23_blast_icache_range(start, end);
                        break;
 
                default:
-                       protected_loongson23_blast_icache_range(start, end);
+                       protected_blast_icache_range(start, end);
                        break;
                }
        }
-- 
1.8.5.1


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