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[PATCH v2 03/12] MIPS: features: Add initial support for TLBINVF capable

To: <linux-mips@linux-mips.org>
Subject: [PATCH v2 03/12] MIPS: features: Add initial support for TLBINVF capable cores
From: Markos Chandras <markos.chandras@imgtec.com>
Date: Thu, 14 Nov 2013 16:12:23 +0000
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>, Markos Chandras <markos.chandras@imgtec.com>
In-reply-to: <1384445552-30573-1-git-send-email-markos.chandras@imgtec.com>
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From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

New Aptiv cores support the TLBINVF instruction for flushing
the VTLB.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/include/asm/cpu-features.h | 3 +++
 arch/mips/include/asm/cpu.h          | 1 +
 arch/mips/kernel/cpu-probe.c         | 5 +++++
 3 files changed, 9 insertions(+)

diff --git a/arch/mips/include/asm/cpu-features.h 
b/arch/mips/include/asm/cpu-features.h
index d445d06..296606b 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -20,6 +20,9 @@
 #ifndef cpu_has_tlb
 #define cpu_has_tlb            (cpu_data[0].options & MIPS_CPU_TLB)
 #endif
+#ifndef cpu_has_tlbinv
+#define cpu_has_tlbinv         (cpu_data[0].options & MIPS_CPU_TLBINV)
+#endif
 
 /*
  * For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index d2035e1..fd3bc43 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -348,6 +348,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_PCI           0x00400000 /* CPU has Perf Ctr Int indicator */
 #define MIPS_CPU_RIXI          0x00800000 /* CPU has TLB Read/eXec Inhibit */
 #define MIPS_CPU_MICROMIPS     0x01000000 /* CPU has microMIPS capability */
+#define MIPS_CPU_TLBINV                0x02000000 /* CPU supports TLBINV/F */
 
 /*
  * CPU ASE encodings
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c814287..5dac95a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -286,6 +286,11 @@ static inline unsigned int decode_config4(struct 
cpuinfo_mips *c)
            && cpu_has_tlb)
                c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 
+       if (cpu_has_tlb) {
+               if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
+                       c->options |= MIPS_CPU_TLBINV;
+       }
+
        c->kscratch_mask = (config4 >> 16) & 0xff;
 
        return config4 & MIPS_CONF_M;
-- 
1.8.4.3



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