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[RFC PATCH] MIPS: Fix case mismatch in local_r4k_flush_icache_range()

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [RFC PATCH] MIPS: Fix case mismatch in local_r4k_flush_icache_range()
From: Huacai Chen <chenhc@lemote.com>
Date: Fri, 8 Nov 2013 15:21:53 +0800
Cc: John Crispin <john@phrozen.org>, "Steven J. Hill" <Steven.Hill@imgtec.com>, linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>, Zhangjin Wu <wuzhangjin@gmail.com>, Huacai Chen <chenhc@lemote.com>
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Currently, Loongson-2 call protected_blast_icache_range() and others
call protected_loongson23_blast_icache_range(), but I think the correct
behavior should be the opposite. BTW, Loongson-3's cache-ops is
compatible with MIPS64, but not compatible with Loongson-2. So, rename
xxx_loongson23_yyy things to xxx_loongson2_yyy.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/include/asm/cacheops.h |    2 +-
 arch/mips/include/asm/r4kcache.h |    8 ++++----
 arch/mips/mm/c-r4k.c             |    4 ++--
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index c75025f..06b9bc7 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -83,6 +83,6 @@
 /*
  * Loongson2-specific cacheops
  */
-#define Hit_Invalidate_I_Loongson23    0x00
+#define Hit_Invalidate_I_Loongson2     0x00
 
 #endif /* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 34d1a19..91d20b0 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -165,7 +165,7 @@ static inline void flush_icache_line(unsigned long addr)
        __iflush_prologue
        switch (boot_cpu_type()) {
        case CPU_LOONGSON2:
-               cache_op(Hit_Invalidate_I_Loongson23, addr);
+               cache_op(Hit_Invalidate_I_Loongson2, addr);
                break;
 
        default:
@@ -219,7 +219,7 @@ static inline void protected_flush_icache_line(unsigned 
long addr)
 {
        switch (boot_cpu_type()) {
        case CPU_LOONGSON2:
-               protected_cache_op(Hit_Invalidate_I_Loongson23, addr);
+               protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
                break;
 
        default:
@@ -452,8 +452,8 @@ static inline void 
prot##extra##blast_##pfx##cache##_range(unsigned long start,
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \
-       protected_, loongson23_)
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
+       protected_, loongson2_)
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
 /* blast_inv_dcache_range */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 62ffd20..73f02da 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -580,11 +580,11 @@ static inline void local_r4k_flush_icache_range(unsigned 
long start, unsigned lo
        else {
                switch (boot_cpu_type()) {
                case CPU_LOONGSON2:
-                       protected_blast_icache_range(start, end);
+                       protected_loongson2_blast_icache_range(start, end);
                        break;
 
                default:
-                       protected_loongson23_blast_icache_range(start, end);
+                       protected_blast_icache_range(start, end);
                        break;
                }
        }
-- 
1.7.7.3


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