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Re: Suspected cache coherency problem on V4L2 and AR7100 CPU

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: Suspected cache coherency problem on V4L2 and AR7100 CPU
From: khalasa@piap.pl (Krzysztof Hałasa)
Date: Wed, 09 Oct 2013 15:05:28 +0200
Cc: linux-mips@linux-mips.org, linux-media@vger.kernel.org
In-reply-to: <20131009081707.GL1615@linux-mips.org> (Ralf Baechle's message of "Wed, 9 Oct 2013 10:17:07 +0200")
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Ralf Baechle <ralf@linux-mips.org> writes:

> The kernel is supposed to perform the necessary cache flushing, so any
> remaining aliasing issue would be considered a bug.  But the code is
> performance sensitive, some of the problem cases are twisted and complex
> so bugs and unsolved corner cases show up every now and then.

Ok. This means I should also investigate the V4L2 and the hw driver
code, because the cache aliasing shouldn't be there in the first place.

> Does it work for you, even solve your problem?

Sure, with 16 KB page size everything works fine.

-- 
Krzysztof Halasa

Research Institute for Automation and Measurements PIAP
Al. Jerozolimskie 202, 02-486 Warsaw, Poland

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