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Re: Suspected cache coherency problem on V4L2 and AR7100 CPU

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: Suspected cache coherency problem on V4L2 and AR7100 CPU
From: khalasa@piap.pl (Krzysztof Hałasa)
Date: Wed, 09 Oct 2013 08:53:20 +0200
Cc: linux-mips@linux-mips.org, linux-media@vger.kernel.org
In-reply-to: <20131008120727.GH1615@linux-mips.org> (Ralf Baechle's message of "Tue, 8 Oct 2013 14:07:27 +0200")
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Ralf Baechle <ralf@linux-mips.org> writes:

> 16K is a silver bullet solution to all cache aliasing problems.  So if
> your issue persists with 16K page size, it's not a cache aliasing issue.
> Aside there are generally performance gains from the bigger page size.

I wonder why isn't the issue present in other cases. Perhaps remapping
of a userspace address and accessing it with kseg0 isn't a frequent
operation.

Shouldn't we change the default page size (on affected CPUs) to 16 KB
then? Alternatively, we could flush/invalidate the cache when needed -
is it a viable option?

Thanks.
-- 
Krzysztof Halasa

Research Institute for Automation and Measurements PIAP
Al. Jerozolimskie 202, 02-486 Warsaw, Poland

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