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Re: Suspected cache coherency problem on V4L2 and AR7100 CPU

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: Suspected cache coherency problem on V4L2 and AR7100 CPU
From: khalasa@piap.pl (Krzysztof Hałasa)
Date: Tue, 08 Oct 2013 12:46:55 +0200
Cc: linux-mips@linux-mips.org, linux-media@vger.kernel.org
In-reply-to: <20131007142429.GG3098@linux-mips.org> (Ralf Baechle's message of "Mon, 7 Oct 2013 16:24:29 +0200")
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Ralf Baechle <ralf@linux-mips.org> writes:

> That's fine.  You just need to ensure that there are no virtual aliases.
> One way to do so is to increase the page size to 16kB.

Checked, this thing works fine with 16 KB pages.
-- 
Krzysztof Halasa

Research Institute for Automation and Measurements PIAP
Al. Jerozolimskie 202, 02-486 Warsaw, Poland

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