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Re: [PATCH] MIPS: Add printing of ES bit when cache error occurs.

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH] MIPS: Add printing of ES bit when cache error occurs.
From: Markos Chandras <Markos.Chandras@imgtec.com>
Date: Tue, 8 Oct 2013 09:16:27 +0100
Cc: <linux-mips@linux-mips.org>, Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
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On 10/08/13 06:06, Ralf Baechle wrote:
On Mon, Oct 07, 2013 at 10:25:52AM +0100, Markos Chandras wrote:

From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>

Print out the source of request that caused the error (ES bit) when
a cache error exception occurs.

The reason ES isn't being printed is that not all processors that support
a cache error exception have an ES bit.  The R4000 has it, R5000 doesn't,
R10000 CacheErr looks rather different - and in fact MIPS32/64 make the
entire register optional and its details implementation specific.

Don't even ask me anymore which processor the implementation in the
kernel is trying to support - probably something R7000ish, at least
that's what guess from the 1385617929e09545f9858785ea3dc1068fedfde1
commit log.

Short of some fancy engineering, I'd suggest throwing in a switch
statement and per processor type printks just as in parity_protection_init.

   Ralf

Hi Ralf,

hmm i see. ok i will do that instead.


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