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Re: Suspected cache coherency problem on V4L2 and AR7100 CPU

To: linux-mips@linux-mips.org
Subject: Re: Suspected cache coherency problem on V4L2 and AR7100 CPU
From: khalasa@piap.pl (Krzysztof Hałasa)
Date: Mon, 07 Oct 2013 10:38:49 +0200
Cc: linux-media@vger.kernel.org
In-reply-to: <m3eh82a1yo.fsf@t19.piap.pl> ("Krzysztof Hałasa"'s message of "Thu, 03 Oct 2013 16:00:47 +0200")
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Please forgive me my MIPS TLB ignorance.

It seems there is a TLB entry pointing to the userspace buffer at the
time the kernel pointer (kseg0) is used. Is is an allowed situation on
MIPS 24K?

buffer: len 0x1000 (first page),
        userspace pointer 0x77327000,
        kernel pointer 0x867ac000 (physical address = 0x067ac000)

TLB Index: 15 pgmask=4kb va=77326000 asid=be
       [pa=01149000 c=3 d=1 v=1 g=0] [pa=067ac000 c=3 d=1 v=1 g=0]

Should the TLB entry be deleted before using the kernel pointer (which
points at the same page)?
-- 
Krzysztof Halasa

Research Institute for Automation and Measurements PIAP
Al. Jerozolimskie 202, 02-486 Warsaw, Poland

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