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Re: Suspected cache coherency problem on V4L2 and AR7100 CPU

To: linux-mips@linux-mips.org
Subject: Re: Suspected cache coherency problem on V4L2 and AR7100 CPU
From: khalasa@piap.pl (Krzysztof Hałasa)
Date: Fri, 04 Oct 2013 10:06:45 +0200
Cc: linux-media@vger.kernel.org
In-reply-to: <m3eh82a1yo.fsf@t19.piap.pl> ("Krzysztof Hałasa"'s message of "Thu, 03 Oct 2013 16:00:47 +0200")
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> I'm debugging a problem with a SOLO6110-based H.264 PCI video encoder on
> Atheros AR7100-based (MIPS, big-endian) platform.

BTW this CPU obviously has VIPT data cache, this means a physical page
with multiple virtual addresses (e.g. mapped multiple times) may and
will be cached multiple times.

AR7100 = arch/mips/ath79.
-- 
Krzysztof Halasa

Research Institute for Automation and Measurements PIAP
Al. Jerozolimskie 202, 02-486 Warsaw, Poland

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