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Re: Linux 3.12-rc2 - MIPS regression

To: Yoichi Yuasa <yuasa@linux-mips.org>
Subject: Re: Linux 3.12-rc2 - MIPS regression
From: Aaro Koskinen <aaro.koskinen@iki.fi>
Date: Tue, 1 Oct 2013 19:27:43 +0300
Cc: Linus Torvalds <torvalds@linux-foundation.org>, Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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References: <CA+55aFxoF75RJfkp0vnm-b9B0h7PGMitrQiLyTt315tKvG-wTQ@mail.gmail.com> <20130927231012.GB4572@blackmetal.musicnaut.iki.fi> <20131001142421.6cd0870138caf2fe5600a1ea@linux-mips.org>
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On Tue, Oct 01, 2013 at 02:24:21PM +0900, Yoichi Yuasa wrote:
> On Sat, 28 Sep 2013 02:10:12 +0300
> Aaro Koskinen <aaro.koskinen@iki.fi> wrote:
> > 3.12-rc2 breaks the boot (BUG: scheduling while atomic, see logs below)
> > on Lemote Mini-PC (MIPS). According to git bisect, this is caused by:
> > 
> > ff522058bd717506b2fa066fa564657f2b86477e is the first bad commit
> > commit ff522058bd717506b2fa066fa564657f2b86477e
> > Author: Ralf Baechle <ralf@linux-mips.org>
> > Date:   Tue Sep 17 12:44:31 2013 +0200
> > 
> >     MIPS: Fix accessing to per-cpu data when flushing the cache
> > 
> > Reverting the commit from v3.12-rc2 makes the board boot fine.
> 
> Please try this patch on top of rc2.
> 
> MIPS: Fix forgotten preempt_enable() when CPU has inclusive pcaches

Didn't work but making similar change to also r4k_dma_cache_inv() helps.
So both r4k_dma_cache_wback_inv() and r4k_dma_cache_inv() need to
be fixed.

A.

> Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
> 
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 627883b..2492e60 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -609,6 +609,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, 
> unsigned long size)
>                       r4k_blast_scache();
>               else
>                       blast_scache_range(addr, addr + size);
> +             preempt_enable();
>               __sync();
>               return;
>       }

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