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Re: [PATCH v3] MIPS: Tell R4k SC and MC variations apart

To: "Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: [PATCH v3] MIPS: Tell R4k SC and MC variations apart
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 24 Sep 2013 11:11:02 +0200
Cc: Jonas Gorski <jogo@openwrt.org>, MIPS Mailing List <linux-mips@linux-mips.org>
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On Mon, Sep 23, 2013 at 02:01:53PM +0100, Maciej W. Rozycki wrote:

> There is no reliable way to tell R4000/R4400 SC and MC variations apart,
> however simple heuristic should give good results.  Only the MC version
> supports coherent caching so we can rely on such a mode having been set
> for KSEG0 by the power-on firmware to reliably indicate an MC processor.
> SC processors reportedly hang on coherent cached memory accesses and Linux
> is linked to a cached load address so the firmware has to use the correct
> caching mode to download the kernel image in a cached mode successfully.
> 
> OTOH if the firmware chooses to use either the non-coherent cached or the
> uncached mode for KSEG0 on an MC processor, then the SC variant will be
> reported, just as we currently do, so no regression here.

Queued for 3.13.  Thanks,

  Ralf

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