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Re: [PATCH] MIPS: Tell R4k SC and MC variations apart

To: "Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: [PATCH] MIPS: Tell R4k SC and MC variations apart
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 24 Sep 2013 10:48:45 +0200
Cc: linux-mips@linux-mips.org
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On Sun, Sep 22, 2013 at 11:30:59PM +0100, Maciej W. Rozycki wrote:

> There is no reliable way to tell R4000/R4400 SC and MC variations apart, 
> however simple heuristic should give good results.  Only the MC version 
> supports coherent caching so we can rely on such a mode having been set 
> for KSEG0 by the power-on firmware to reliably indicate an MC processor. 
> SC processors reportedly hang on coherent cached memory accesses and Linux 
> is linked to a cached load address so the firmware has to use the correct 
> caching mode to download the kernel image in a cached mode successfully.
> 
> OTOH if the firmware chooses to use either the non-coherent cached or the 
> uncached mode for KSEG0 on an MC processor, then the SC variant will be 
> reported, just as we currently do, so no regression here.
> 
> Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
> ---
> Ralf,
> 
>  I believe we discussed this once long ago and you had some concerns about 
> such an approach although I don't recall exactly what they were.  I 
> maintain that this heuristic is reasonable, has no drawbacks and has a 
> potential to make some optimisations or errata workarounds easier.  Also 
> we can collect data about systems affected to see what their firmware does 
> -- R4000SC/R4400SC DECstations definitely get CP0.Config.K0 right.

I'm fairly sure it gets k0 right - otherwise it'd likely not work at all!

My reservations may have been about userland reading /proc/cpuinfo and
looking at the CPU type.  Some software may know how to handle the
PC/SC variants but not the MC versions.  But this seems to be a fairly
weak concern - and I trust you checked gcc's parsing of /proc/cpuinfo.

  Ralf

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