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[MIPS] Correct 74K/1074K erratum workaround

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [MIPS] Correct 74K/1074K erratum workaround
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Wed, 18 Sep 2013 19:08:15 +0100 (BST)
Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>, Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>, linux-mips@linux-mips.org
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Make sure 74K revision numbers are not applied to the 1074K.  Also catch 
invalid usage.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
---
Ralf,

 Please apply.  I saw a similar change fly by, but it lacked the necessary 
readability and the safety guard, to say nothing of the change explanation 
chosen.

  Maciej

linux-mips-74k-erratum.patch
Index: linux-mips-3.12.0-rc1-20130917-4maxp/arch/mips/mm/c-r4k.c
===================================================================
--- linux-mips-3.12.0-rc1-20130917-4maxp.orig/arch/mips/mm/c-r4k.c
+++ linux-mips-3.12.0-rc1-20130917-4maxp/arch/mips/mm/c-r4k.c
@@ -780,20 +780,30 @@ static inline void rm7k_erratum31(void)
 
 static inline void alias_74k_erratum(struct cpuinfo_mips *c)
 {
+       unsigned int imp = c->processor_id & PRID_IMP_MASK;
+       unsigned int rev = c->processor_id & PRID_REV_MASK;
+
        /*
         * Early versions of the 74K do not update the cache tags on a
         * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
         * aliases. In this case it is better to treat the cache as always
         * having aliases.
         */
-       if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_ENCODE_332(2, 4, 0))
-               c->dcache.flags |= MIPS_CACHE_VTAG;
-       if ((c->processor_id & PRID_REV_MASK) == PRID_REV_ENCODE_332(2, 4, 0))
-               write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
-       if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_1074K &&
-           (c->processor_id & PRID_REV_MASK) <= PRID_REV_ENCODE_332(1, 1, 0)) {
-               c->dcache.flags |= MIPS_CACHE_VTAG;
-               write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+       switch (imp) {
+       case PRID_IMP_74K:
+               if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
+                       c->dcache.flags |= MIPS_CACHE_VTAG;
+               if (rev == PRID_REV_ENCODE_332(2, 4, 0))
+                       write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+               break;
+       case PRID_IMP_1074K:
+               if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
+                       c->dcache.flags |= MIPS_CACHE_VTAG;
+                       write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+               }
+               break;
+       default:
+               BUG();
        }
 }
 

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