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Re: [MIPS] CP0 PRId and CP1 FPIR register access masks

To: "Maciej W. Rozycki" <>
Subject: Re: [MIPS] CP0 PRId and CP1 FPIR register access masks
From: Ralf Baechle <>
Date: Tue, 17 Sep 2013 18:19:57 +0200
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On Tue, Sep 17, 2013 at 04:58:10PM +0100, Maciej W. Rozycki wrote:

> Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout.  
> The change does not touch places that use shifted or partial masks.
> Signed-off-by: Maciej W. Rozycki <>
> ---
> Ralf,
>  Please apply.  I think the places ignored by this change should be 
> further reviewed, especially the shifted masks that can likely remove the 
> shifts and rely on compiler optimisation instead.  I decided to make this 
> change as straightforward as possible to avoid accidental breakage in code 
> I have no way to test.  Also partial masks are probably better handled 
> with macros rather than hardcoded constants scattered throughout.  I can 
> see steps have been taken towards this already (PRID_REV_ENCODE_*).

Looks ok, queud for 3.13.

But while it's cleaner, I think the idiom read_c0_prid() & some_MASK is
so common that maybe something like

  #define read_c0_prid_imp()    (read_c0_prid() & PRID_IMP_MASK)
  #define read_c0_prid_rev()    (read_c0_prid() & PRID_REV_MASK)
  #define read_c0_prid_comp()   (read_c0_prid() & PRID_COMP_MASK)

should be introduced as a next step.


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