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Re: [PATCH] MIPS: Fix errata for some 1074K cores.

To: Florian Fainelli <>
Subject: Re: [PATCH] MIPS: Fix errata for some 1074K cores.
From: Leonid Yegoshin <>
Date: Thu, 12 Sep 2013 15:12:31 +0000
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Cc: Paul Burton <>, "Steven J. Hill" <>, "" <>, "" <>
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Thread-topic: [PATCH] MIPS: Fix errata for some 1074K cores.
Well, if you read an errata text, you probably have a big chance to stare at it 
trying to understand it. At least I don't and I just put that was said to me by 
HW team. There is no sense in discussion here because it is a part of specific 
core tuneup.

Florian Fainelli <> wrote:

2013/9/12 Leonid Yegoshin <>:
> Treat it as is.
> It is a dirty laundry of HW engineers and you may need to communicate with 
> them or read Errata docs on CPU.
> If it is about a way how it is written - ask Steven, initially it was in 
> mainland probe code but he think it should be a separate function. I just 
> corrected him, pointing that erratas on 74K and 1074K are different. But 
> because he insist on having the same CPU_74K for both, so...

If you take a look at another CPU company such as ARM, they provide
lengthy explanations for their various Erratas:

config PJ4B_ERRATA_4742
        bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the
CPU Core to Cease Operation"
        depends on CPU_PJ4B && MACH_ARMADA_370
        default y
          When coming out of either a Wait for Interrupt (WFI) or a Wait for
          Event (WFE) IDLE states, a specific timing sensitivity exists between
          the retiring WFI/WFE instructions and the newly issued subsequent
          instructions.  This sensitivity can result in a CPU hang scenario.
          The software must insert either a Data Synchronization Barrier (DSB)
          or Data Memory Barrier (DMB) command immediately after the WFI/WFE

I really think that you should aim for the same level of information
so that people know whether this is relevant for their platform,
whether they have the ECO applied etc...

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