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Re: [PATCH] MIPS: Fix errata for some 1074K cores.

To: Paul Burton <Paul.Burton@imgtec.com>
Subject: Re: [PATCH] MIPS: Fix errata for some 1074K cores.
From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Date: Thu, 12 Sep 2013 14:57:37 +0000
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Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>, "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>, "ralf@linux-mips.org" <ralf@linux-mips.org>
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Thread-topic: [PATCH] MIPS: Fix errata for some 1074K cores.
Treat it as is.

It is a dirty laundry of HW engineers and you may need to communicate with them 
or read Errata docs on CPU.

If it is about a way how it is written - ask Steven, initially it was in 
mainland probe code but he think it should be a separate function. I just 
corrected him, pointing that erratas on 74K and 1074K are different. But 
because he insist on having the same CPU_74K for both, so...

- Leonid.

PS. If you think the code is bad, please be specific beyond broad blame.


Paul Burton <Paul.Burton@imgtec.com> wrote:


Could you expand on that please? What is errata E16, what are "some
problems" and how does this fix those problems? The commit message is
somewhat lacking...

Paul

On 11/09/13 21:01, Steven J. Hill wrote:
> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>
> Fixes errata E16 for some problems on 1074K cores.
>
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
> ---
>   arch/mips/mm/c-r4k.c |   12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index f749f68..8d3ed32 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -786,12 +786,12 @@ static inline void alias_74k_erratum(struct 
> cpuinfo_mips *c)
>        * aliases. In this case it is better to treat the cache as always
>        * having aliases.
>        */
> -     if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> -             c->dcache.flags |= MIPS_CACHE_VTAG;
> -     if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> -             write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> -     if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
> -         ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
> +     if ((c->processor_id & 0xff00) != PRID_IMP_1074K) {
> +             if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
> +                     c->dcache.flags |= MIPS_CACHE_VTAG;
> +             if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
> +                     write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
> +     } else if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0)) {
>               c->dcache.flags |= MIPS_CACHE_VTAG;
>               write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
>       }



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