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[PATCH] MIPS: DECstation HRT calibration bug fixes

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH] MIPS: DECstation HRT calibration bug fixes
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Wed, 4 Sep 2013 23:47:45 +0100 (BST)
Cc: linux-mips@linux-mips.org
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This change corrects DECstation HRT calibration, by removing the following 
bugs:

1. Calibration period selection -- HZ / 10 has been chosen, however on 
   DECstation computers, HZ never divides by 10, as the choice for HZ is 
   among 128, 256 and 1024.  The choice therefore results in a systematic
   calibration error, e.g. 6.25% for the usual choice of 128 for HZ:

   128 / 10 * 10 = 120

   (128 - 120) / 128 -> 6.25%

   The change therefore makes calibration use HZ / 8 that is always 
   accurate for the HZ values available, getting rid of the systematic
   error.

2. Calibration starting point synchronisation -- the duration of a number 
   of intervals between DS1287A periodic interrupt assertions is measured,
   however code does not ensure at the beginning that the interrupt has 
   not been previously asserted.  This results in a variable error of e.g. 
   up to another 6.25% for the period of HZ / 8 (8.(3)% with the original 
   HZ / 10 period) and the usual choice of 128 for HZ:

   1 / 16 -> 6.25%

   1 / 12 -> 8.(3)%

   The change therefore adds an initial call to ds1287_timer_state that 
   clears any previous periodic interrupt pending.

The same issue applies to both I/O ASIC counter and R4k CP0 timer 
calibration on DECstation systems as similar code is used in both cases 
and both pieces of code are covered by this fix.

On an R3400 test system used this fix results in a change of the I/O ASIC 
clock frequency reported from values like:

I/O ASIC clock frequency 23185830Hz

to:

I/O ASIC clock frequency 24999288Hz

removing the miscalculation by 6.25% from the systematic error and (for 
the individual sample provided) a further 1.00% from the variable error, 
accordingly.  The nominal I/O ASIC clock frequency is 25MHz on this 
system.

Here's another result, with the fix applied, from a system that has both 
HRTs available (using an R4400 at 60MHz nominal):

MIPS counter frequency 59999328Hz
I/O ASIC clock frequency 24999432Hz

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
---
Ralf,

 Please apply.

  Maciej

linux-csrc-dec-fix.patch
Index: linux/arch/mips/dec/time.c
===================================================================
--- linux.orig/arch/mips/dec/time.c
+++ linux/arch/mips/dec/time.c
@@ -126,12 +126,13 @@ int rtc_mips_set_mmss(unsigned long nowt
 void __init plat_time_init(void)
 {
        u32 start, end;
-       int i = HZ / 10;
+       int i = HZ / 8;
 
        /* Set up the rate of periodic DS1287 interrupts. */
        ds1287_set_base_clock(HZ);
 
        if (cpu_has_counter) {
+               ds1287_timer_state();
                while (!ds1287_timer_state())
                        ;
 
@@ -143,7 +144,7 @@ void __init plat_time_init(void)
 
                end = read_c0_count();
 
-               mips_hpt_frequency = (end - start) * 10;
+               mips_hpt_frequency = (end - start) * 8;
                printk(KERN_INFO "MIPS counter frequency %dHz\n",
                        mips_hpt_frequency);
        } else if (IOASIC)
Index: linux/arch/mips/kernel/csrc-ioasic.c
===================================================================
--- linux.orig/arch/mips/kernel/csrc-ioasic.c
+++ linux/arch/mips/kernel/csrc-ioasic.c
@@ -41,9 +41,9 @@ void __init dec_ioasic_clocksource_init(
 {
        unsigned int freq;
        u32 start, end;
-       int i = HZ / 10;
-
+       int i = HZ / 8;
 
+       ds1287_timer_state();
        while (!ds1287_timer_state())
                ;
 
@@ -55,7 +55,7 @@ void __init dec_ioasic_clocksource_init(
 
        end = dec_ioasic_hpt_read(&clocksource_dec);
 
-       freq = (end - start) * 10;
+       freq = (end - start) * 8;
        printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
 
        clocksource_dec.rating = 200 + freq / 10000000;

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