On Tue, Aug 27, 2013 at 04:57:51PM -0400, Jim Quinlan wrote:
> Date: Tue, 27 Aug 2013 16:57:51 -0400
> From: Jim Quinlan <firstname.lastname@example.org>
> To: email@example.com, firstname.lastname@example.org
> cc: email@example.com, Jim Quinlan <firstname.lastname@example.org>
> Subject: [PATCH] MIPS: dma: if BMIPS5000, flush region just like r10000
> Content-Type: text/plain
> The BMIPS5000 (Zephyr) processor utilizes instruction speculation. A
> stale misprediction address in either the JTB or the CRS may trigger
> a prefetch inside a region that is currently being used by a DMA
> engine, which is not IO-coherent. This prefetch will fetch a line
> into the scache, and that line will soon become stale (ie wrong)
> during/after the DMA. Mayhem ensues.
> In dma-default.c, the r10000 is handled as a special case in the
> same way that we want to handle Zephyr. So we generalize the
> exception cases into a function, and include Zephyr as one
> of the processors that needs this special care.
Is this a processor erratum or just documented, undesireable behaviour?
In case of the R10000 family it's the later and it also only affects
systems without cache coherency. In such systems it is also possible
that cachelines in speculative-dirty state will be created by a
speculativly executed store instruction. This is normal - but on a
cache coherent system the coherency logic would prevent such speculativly
dirty lines from being written back to memory.
To avoid this from happening non-coherent R10000 systems also require their
kernel to be built with a special compiler option that inserts cache barrier
operations wherever a speculativly dirty line otherwise might be created.
Patch is looking good.