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[PATCH 3/3] MIPS: ralink: mt7620: add spi clock definition

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH 3/3] MIPS: ralink: mt7620: add spi clock definition
From: Gabor Juhos <juhosg@openwrt.org>
Date: Thu, 22 Aug 2013 19:46:41 +0200
Cc: linux-mips@linux-mips.org, John Crispin <blogic@openwrt.org>, Gabor Juhos <juhosg@openwrt.org>
In-reply-to: <1377193601-18677-1-git-send-email-juhosg@openwrt.org>
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From: John Crispin <blogic@openwrt.org>

Register a clock device for the SPI block of the
MT7620 SoC. The clock device will be used by the
SPI host controller driver to determine the base
clock of the controller.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
---
This makes the following patch obsolete:
  https://patchwork.linux-mips.org/patch/5672/
---
 arch/mips/ralink/mt7620.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 1be3b0a..e7b8e81 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -323,6 +323,7 @@ void __init ralink_clk_init(void)
        ralink_clk_add("10000100.timer", periph_rate);
        ralink_clk_add("10000120.watchdog", periph_rate);
        ralink_clk_add("10000500.uart", periph_rate);
+       ralink_clk_add("10000b00.spi", sys_rate);
        ralink_clk_add("10000c00.uartlite", periph_rate);
 }
 
-- 
1.7.10

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