linux-mips
[Top] [All Lists]

[PATCH 1/2] MIPS: Handle OCTEON BBIT instructions in FPU emulator.

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH 1/2] MIPS: Handle OCTEON BBIT instructions in FPU emulator.
From: David Daney <ddaney.cavm@gmail.com>
Date: Mon, 19 Aug 2013 12:10:34 -0700
Cc: David Daney <david.daney@cavium.com>
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pfUDpZyqqywdUq/3pUyw171CjNzzektEqpCqOkxE/Dg=; b=ueVI78EyxPCEOJpIM2dgrTVNHW3UfJI+X2atSon6ZnhBdSNbw7TDD3d/PuD4NgXhlV NC/zOop7GK3WT1ISgsbkI/Z19s5RdgzyCgP27ngP1XxmDDM9up6TtdajtTQPcf79VQX6 3V5lOsLSWg9iV5bu6PxrxzNMxKYkYzfkwuFSLPqbgoLCmgynXyGz0vUqV7J6FDPStcNO XFwsCNXzNCT0Evhl1n4e1kwxggE0pTvmjJT9vfu81fWVjyRpluY4N14wHAQNRKOnLGua jbzGUPyAj177QiVscVkgTxHZjUjKSVlpqraRCuvaV7+F/mkyQ2etv76jVtORuT0x6iVT bXTA==
In-reply-to: <1376939435-19761-1-git-send-email-ddaney.cavm@gmail.com>
List-archive: <http://www.linux-mips.org/archives/linux-mips/>
List-help: <mailto:ecartis@linux-mips.org?Subject=help>
List-id: linux-mips <linux-mips.eddie.linux-mips.org>
List-owner: <mailto:ralf@linux-mips.org>
List-post: <mailto:linux-mips@linux-mips.org>
List-software: Ecartis version 1.0.0
List-subscribe: <mailto:ecartis@linux-mips.org?subject=subscribe%20linux-mips>
List-unsubscribe: <mailto:ecartis@linux-mips.org?subject=unsubscribe%20linux-mips>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <1376939435-19761-1-git-send-email-ddaney.cavm@gmail.com>
Sender: linux-mips-bounce@linux-mips.org
From: David Daney <david.daney@cavium.com>

The branch emulation needs to handle the OCTEON BBIT instructions,
otherwise we get SIGILL instead of emulation.

Signed-off-by: David Daney <david.daney@cavium.com>
---
 arch/mips/math-emu/cp1emu.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index e773659..46048d2 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -803,6 +803,32 @@ static int isBranchInstr(struct pt_regs *regs, struct 
mm_decoded_insn dec_insn,
                                dec_insn.next_pc_inc;
                return 1;
                break;
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+       case lwc2_op: /* This is bbit0 on Octeon */
+               if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 
== 0)
+                       *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate 
<< 2);
+               else
+                       *contpc = regs->cp0_epc + 8;
+               return 1;
+       case ldc2_op: /* This is bbit032 on Octeon */
+               if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 
32))) == 0)
+                       *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate 
<< 2);
+               else
+                       *contpc = regs->cp0_epc + 8;
+               return 1;
+       case swc2_op: /* This is bbit1 on Octeon */
+               if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
+                       *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate 
<< 2);
+               else
+                       *contpc = regs->cp0_epc + 8;
+               return 1;
+       case sdc2_op: /* This is bbit132 on Octeon */
+               if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 
32)))
+                       *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate 
<< 2);
+               else
+                       *contpc = regs->cp0_epc + 8;
+               return 1;
+#endif
        case cop0_op:
        case cop1_op:
        case cop2_op:
-- 
1.7.11.7


<Prev in Thread] Current Thread [Next in Thread>