[Top] [All Lists]

Re: [PATCH 2/2] SPI: ralink: add Ralink SoC spi driver

To: John Crispin <>
Subject: Re: [PATCH 2/2] SPI: ralink: add Ralink SoC spi driver
From: Mark Brown <>
Date: Tue, 13 Aug 2013 19:58:02 +0100
Cc: Gabor Juhos <>,,
In-reply-to: <>
List-archive: <>
List-help: <>
List-id: linux-mips <>
List-owner: <>
List-post: <>
List-software: Ecartis version 1.0.0
List-subscribe: <>
List-unsubscribe: <>
Original-recipient: rfc822;
References: <> <> <> <>
User-agent: Mutt/1.5.21 (2010-09-15)
On Tue, Aug 13, 2013 at 08:43:51PM +0200, John Crispin wrote:

> >There is presumably a maximum transfer size here from the FIFO that is
> >holding the data?

> The hardware is not running in DMA/IRQ mode and hence it can only
> read/write 1 byte at a time.

OK, then the code looks buggy since it does all the Tx then all the Rx
so a bidirectional transfer should fail.  I'd expect Tx and Rx to be
part of the same loop in this case.

> >Set min_speed_hz in the spi_master and the core will check this for you.

> it seems that min_speed is not handled by the core yet. I saw
> several drivers do minimum speed testing. I am leaving this code in
> the driver until there is a generic minimum speed check

Or add the check to the core...

> >clk_prepare_enable(), and it'd be nice to use runtime PM and enable the
> >clock only when doing transfers though that's not essential.

> The clock is free running and always running.

It's still nice to turn it off for power, and very cheap to implement.

Attachment: signature.asc
Description: Digital signature

<Prev in Thread] Current Thread [Next in Thread>