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[PATCH 4/5] MIPS: Generate OCTEON3 TLB handlers with the same features a

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH 4/5] MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2.
From: David Daney <ddaney.cavm@gmail.com>
Date: Mon, 29 Jul 2013 15:07:03 -0700
Cc: David Daney <david.daney@cavium.com>
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From: David Daney <david.daney@cavium.com>

From the point of view of the TLB Exception handlers, OCTEON3 and
OCTEON2 need the same code.

Signed-off-by: David Daney <david.daney@cavium.com>
---
 arch/mips/mm/tlbex.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 556cb48..821b451 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -85,6 +85,7 @@ static int use_bbit_insns(void)
        case CPU_CAVIUM_OCTEON:
        case CPU_CAVIUM_OCTEON_PLUS:
        case CPU_CAVIUM_OCTEON2:
+       case CPU_CAVIUM_OCTEON3:
                return 1;
        default:
                return 0;
@@ -95,6 +96,7 @@ static int use_lwx_insns(void)
 {
        switch (current_cpu_type()) {
        case CPU_CAVIUM_OCTEON2:
+       case CPU_CAVIUM_OCTEON3:
                return 1;
        default:
                return 0;
-- 
1.7.11.7


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