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Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k

To: Florian Fainelli <>
Subject: Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k
From: "Maciej W. Rozycki" <>
Date: Mon, 29 Jul 2013 15:53:13 +0100 (BST)
Cc: John Crispin <>, Ralf Baechle <>, Linux-MIPS <>
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On Mon, 29 Jul 2013, Florian Fainelli wrote:

> It is not clear to me whether this secondary cevt is also a r4k-cevt
> device, or if it is something else? If the IRQ is shared, is there any
> way to differentiate the ralink cevt from the r4k cevt, such that both
> could request the same irq with the IRQF_SHARED flag?

 As from rev. 2 of the MIPS architecture processors are required to 
implement a CP0.Cause.TI bit to indicate a CP0.Count/CP0.Compare timer 
interrupt pending -- so it may all bail down to figuring out what MIPS
architecture level this SoC implements.  FWIW.  HTH.


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